Home

UM10495 - NXP Semiconductors

1. Demo board connections slave configuration Protocol requirements Bit frame protocol considerations zero crossing synchronization Bit frame protocol considerations start bit UART style synchronization Protocol specification Protocol specification zero crossing synchronization Bit level protocol zero crossing synchronization Message level protocol Protocol specification start bit UART style synchronization Bit level protocol start bit UART style synchronization Master firmware overview Master firmware implementation zero crossing synchronization Main loop c 1 2 eee eee eee 16b timmert Gsi cerre ninan ar All information provided in this document is subject to legal disclaimers 8 1 4 8 1 5 8 1 6 8 1 7 8 1 8 8 1 9 8 1 10 8 1 11 8 1 12 8 2 8 2 1 8 2 2 8 2 3 8 2 4 8 2 5 8 2 6 8 2 7 8 2 8 8 2 9 8 2 10 8 2 11 8 2 12 9 9 1 9 1 1 9 1 2 9 1 3 9 1 4 9 1 5 9 1 6 9 1 7 9 1 8 9 1 9 9 1 10 9 1 11 9 1 12 9 1 13 9 1 14 9 2 9 2 1 9 2 2 9 2 3 9 2 4 9 2 5 9 2 6 lOG ERE 17 Command C nananana aaae 17 NVIG G 222 ioe amona aie eni RIRs 18 SYS TICKC 5 o RR ex Du dun Chae ae ERR 18 32b Timer0 c 200000 0 eee 18 PLM Masterc 000005 18 32b_Timerl c 22 00202 18 Timer16b_0 C
2. 20000 eee eee 18 PLM_UART c 0000 eee aee 18 Master firmware implementation start bit UART style synchronization 19 Main loOp C eee m reb RR 19 16b timeri c 00000 2c 19 WAR RG 12 2h LLERSS EPI NP PERPE 19 of DTP 19 Commandes uz ve bec ERE ERES 19 INVIG GS eos he Rae epi eye beet en eat 19 SyS TICK siesd Eae see he oa dei bas 19 32b_Timer0 c 22 0000 0 eee 19 PLM Masterc 2 2000000 20 32b Timertuo i soozalii ier indie 20 Timer16b_0 c 20002 cee eee 20 PEM UART G iier see vi eee tas 20 Slave firmware description 20 Slave firmware description zero crossing synchronization 21 Main Joop C isole pr ERR Rh 21 16b timeri c 2 00002 02 ee 21 VARTE s si 634 est LIA E EPEXREN 21 lorc PPP 21 Command c 000e cece eee eee 21 NVIG G c emer DE ates eg eee 21 SySTICK C i epa texta der oos 21 32b Timer0 c 2 0020 aani 21 plos rn 21 I2C Messag S C 00 eee eee 22 PLM_Slave c 0000 eee eaee 22 32b NME 0s coe ienis aeoeaii Lees 22 Timer16b_0 c 20002 eee eee 23 PLM _WART 6 eese Reemi ene s 23 Slave firmware description start bit UART style synchronization 23 Main loop ies kms 23 16b_timer C 2 uen 23 UART C ck sided 8 eae ME A Et E 23 ler Pp 23 Commande coil s e a Eve 23 NVC Chet eese te bt eas 23 continued gt gt NXP B V 2013 All rights rese
3. All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 3 18 December 2013 26 of 43 NXP Semiconductors U M1 0495 UM10495 TDA5051A lighting master slave demo board OM13314 10 1 3 2 Slave Assemble the hardware pieces described in Section 10 1 2 If the firmware has not been loaded into the LPC1114 on the PLM demo board slave program the devices with Zero Crossing Slave code V2_09 using one of the programming methods discussed in Section 11 Appendix A Programming instructions Slave Switch setting The firmware is set up to transmit to Slave address 1 Make sure the hex switch on the slave is set to 1 Hook up the power AC line and LEDs to the TDA5051A demo board as shown in Figure 14 A sve wr 5 NS Se CT y3tesr IT Fig 14 Hookup of DC power AC line and LEDs to TDA5051A High Bay demo board slave 002aag481 10 1 4 Demo operation zero crossing synchronization With both master and slave powered and connected to the line the HB LED should blink on both units The slave should initialize with the LEDs illuminated at about 1 4 of the maximum When the Dim Up switch is pressed the LEDs connected to the PCA9632 outputs will get brighter When the data is being received by the slave the COM_LED will blink When the Dim Down switch is pressed the LEDs connected to the P
4. Half duplex Communications 002aag486 Fig 19 Communications configuration Advanced Options Communications Hardware Config Security Just In Time Code Timeouts Misc v Use DTR and ATS to control RST and P0 14 C Keep ATS asserted while COM Port open 71 50 ms 12 100 ms Assert DTR and RTS while COM Port open 002aag487 Fig 20 Hardware configuration To verify Flash Magic is connected pull down the ISP tab and select Read Device Signature If Flash Magic returns a signature similar to that shown in Figure 21 then communications is established NXP B V 2013 All rights reserved 35 of 43 All information provided in this document is subject to legal disclaimers Rev 3 18 December 2013 UM10495 User manual NXP Semiconductors U M1 0495 TDA5051A lighting master slave demo board OM13314 Flash Magic NON PRODUCTION USE ONLY 002aag488 Fig 21 Read Device Signature result To complete programming verify the correct hex file is loaded and press Start Step 5 in the Flash Magic Window shown in Figure 18 UM10495 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 3 18 December 2013 36 of 43 NXP Semiconductors U M1 0495 TDA5051A lighting master slave demo board OM13314 11 2 SW programming interface The board may als
5. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors accepts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether th
6. the COM LED will blink The On Off switch sends the On Off command to the slave The Select switch will select different dim modes The default setting for the Select Switch is group In this mode a Dim Up or Dim Down command will affect all LED PWM outputs There are 16 steps from full ON to full OFF in this mode Pressing this switch once will select PWM output 0 The COM LED on the master will blink once when PWMO is selected Only PWMO will be affected by a Dim Up or Dim Down in this mode There are 64 steps from ON to OFF in this mode Pressing the switch again will select PWM1 with 64 steps The COM LED on the master will blink twice when PWM1 is selected Pressing the switch again will select PWM2 with 64 steps The COM LED on the master will blink three times when PWMe is selected Pressing the switch again will select PWMS with 64 steps The COM LED on the master will blink four times when PWMS is selected Pressing the switch again will bring you back to the Group mode The COM LED on the master will blink one long blink when GROUP is selected The relative levels of PWMO PWMS are preserved when dimming up or down when returning to Group mode Additional details on the group dimming mode can be found in the PCA9632 data sheet Remark when using this to communicate over DC lines it is likely that a simple inductive resistive network is needed in series at the source and the load to give a low DC resistance to minimize any I2
7. 18 December 2013 29 of 43 NXP Semiconductors U M1 0495 TDA5051A lighting master slave demo board OM13314 10 2 3 Demo configuration start bit UART style synchronization 10 2 3 1 UM10495 Master Assemble the hardware pieces described in Section 10 2 1 If the firmware has not been loaded into the LPC 1114 on the PLM demo board master program the devices with UART Style Master code V1_1 using one of the programming methods discussed in Section 11 Appendix A Programming instructions Master Switch setting The master does not use the hex switch however it is connected to the same pins on the microcontroller as the control switches Make sure the hex switch on the slave is set to 0 the open state to prevent any conflict with the external switches Hook up the Power AC line and switches to the TDA5051A demo board as shown in Figure 15 switches E power AC or DC line P dM Fig 15 Hook up of power AC line and switches to the TDA5051A demo board master 002aag482 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 3 18 December 2013 30 of 43 NXP Semiconductors U M1 0495 UM10495 TDA5051A lighting master slave demo board OM13314 10 2 3 2 Slave Assemble the hardware pieces described in Section 10 2 2 If the firmware has not been loaded into the LPC1114 on the
8. 19 of 43 NXP Semiconductors U M1 0495 8 2 9 8 2 10 8 2 11 8 2 12 TDA5051A lighting master slave demo board OM13314 PLM Master c This handles the message level communications for the PLM master providing synchronization transmitting commands receiving acknowledgements and handling error conditions This module also contains the External interrupt handler that detects the start bit for bit level synchronization 32b Timer1 c This is used to time the start of frame offset from the zero crossing Part of this involves timing the pulse width of the zero crossing pulse from the opto coupler Since the opto coupler output is symmetrical around the actual zero crossing the time from the second edge of opto coupler pulse to the actual zero crossing can be estimated by dividing the pulse width by two This is subtracted from the number of counts required for the 5 16 ms offset and loaded into timer 32b1 to set the offset time from the second edge The timer 32b1 interrupt then sets the start time of the offset bit frame Timer16b O c The master uses this as the debounce timer for the control switch inputs PLM UART c This contains the routines that handle the bit level synchronization data transmission and reception This uses the timing references from the 16b1 and 32b2 timers to implement a soft UART specifically for the interfacing to the TDA5051A 9 Slave firmware description UM10495 To implement the Slave
9. Master US v PLM Master US v LJ include include include include include include include include include Hawn luda compiling PLM UART c linking Program Size FromELF Main loop c f AA kkkks sk skkkkksXXXkk kk kx x xx xx LPC1114 PLM Master Start bit UART style sync LPCllxx h 16b Timerl 32b Timer IO h SysTick h cormand h Uart h S Uart h NVIC h MOOR Tied Code 6972 RO data 224 RW data 112 ZI data 608 creating hex file MFlashVPLM Test axf 0 Error s O Warning s E Build Output CA Find In Files Fig 23 Load button Demo Program f E Eks kExskkEkckEkkkk5Exskkkrkkuskxx kEkEsk ekrk L 002aag490 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 3 18 December 2013 38 of 43 jenuew sn 10z Jequie2eg 8L Ady sJeuire osip eB9 0 1oe qns s jueuinoop siy ui pepi oud uoreuuojul Jy v JO GE S670 LNN paniasa Syu Iv L02 N8 dXN WARNING HIGH VOLTAGE F1 T IS E Fett 20005900410 P et 2 zero cross detector m 220kn PLM ZC P593 1MQ 2 Q1 C22 U PMBT3904 2200 pF N o1 1 1L250 NE amp Is C19 b 47 nF v MPXQS47K GND GND GND iy R tea Lea Los Lu IC4 100 pF 0 1 p
10. User manual Rev 3 18 December 2013 22 of 43 NXP Semiconductors U M1 0495 UM10495 9 1 13 9 1 14 9 2 9 2 1 9 2 2 9 2 3 9 2 4 9 2 5 9 2 6 TDA5051A lighting master slave demo board OM13314 counts required for the 5 16 ms offset and loaded into timer 32b1 to set the offset time from the second edge The timer 32b1 interrupt then sets the start time of the offset bit frame Timer16b_0 c The master uses this as the debounce timer for the switch inputs PLM_UART c This contains the routines that handle the bit level synchronization data transmission and reception This uses the timing references from the 16b1 and 32b2 timers to implement a soft UART specifically for the interfacing to the TDA5051A Slave firmware description start bit UART style synchronization The slave firmware for the TDA5051A SSL demo application contains a number of C application modules combined with system and core code The modules implemented for start bit synchronization are described in Section 9 2 1 through Section 9 2 12 Main loop c This module calls all the initialization code for all the other modules and provides the While 1 loop to test for application flags The flags tested by the master include byte level and message level receive flags transmit status flag to see if all bytes in message have been transmitted and transmit response flag If the flag gets set the test function will call an applic
11. application an on board hex switch is used to set the slave address This is connected to port pins P1_8 P1_9 P1_10 and P1_11 The address assigned to the hex switch is specified as follows P1 8 2 8 P1 9 2 4 P1 10 2 2 P1 11 2 1 The sum of the addresses for the logic HIGH inputs results in the slave address recognized for commands For example when the hex switch is set to 1 P1 11 will be HIGH and P1 8 P1 10 will be LOW Remark Since the master hard codes a slave address of 0x01 make sure the Hex Switch on the slave is set to this address to be able to respond to master commands There are two LED indicators on the Slave The HB LED is for the Heartbeat function to indicate that the microcontroller is functioning The COM LED blinks when a valid frame byte has been received to indicate communications activity The Slave configuration for implementing the start bit synchronization method is the same as the zero crossing method at the high level The command responses and indicator actions are the same for the firmware implementations of both synchronization methods The differences are detailed in the individual module sections when discussing how the different synchronization methods are handled All information provided in this document is subject to legal disclaimers NXP B V 2013 AII rights reserved User manual Rev 3 18 December 2013 20 of 43 NXP Semiconductors U M1 0495 UM
12. implemented with a 4 x PCF8883 capacitive proximity sensor switch circuit shown in Figure 4 The connector pin assignments are shown in Table 2 UM10495 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 3 18 December 2013 6 of 43 NXP Semiconductors U M1 0495 TDA5051A lighting master slave demo board OM13314 GND is kQ l kQ IIE kQ D D D D n n n n PS1 PS1 PS1 PS1 ON OFF DIM UP DIM DOWN OUTPUT SELECT 019aac664 1 JPO connects to pin 1 of SV2 header 2 JP1 connects to pin 2 of SV2 header 3 JP2 connects to pin 3 of SV2 header 4 JP3 connects to pin 4 of SV2 header 5 GND ground connects to pin 5 of SV2 header 6 Vec connects to 3 3 V supply Fig 4 Schematic for 4 x PCF8883 capacitive proximity sensor switch UM10495 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 3 18 December 2013 7 of 43 NXP Semiconductors U M1 0495 TDA5051A lighting master slave demo board OM13314 Table 2 SV2 header pin assignments Header pin Switch function Signal destination Notes 1 Off On LPC1343 PIO1 8 s
13. logic state of the received bit by state of a majority of the samples The start of the sample time is determined by an offset from the zero crossing UART c This was used as a debug channel during development 10 c This configures the I O of the LPC 1114 including setting the functions and direction of the I O pins The I O interfacing with the zero crossing opto couple generates an interrupt on both edges of the signal The pulse width of the optocoupler output is measured to estimate the zero crossing as described later This module also contains the functions to detect the closure of a command switch and take the appropriate action or sent the corresponding command to the slave Command c This was used for initial debug All information provided in this document is subject to legal disclaimers NXP B V 2013 AII rights reserved User manual Rev 3 18 December 2013 17 of 43 NXP Semiconductors U M1 0495 TDA5051A lighting master slave demo board OM13314 8 1 6 NVIC c This sets the priority and enables required interrupts in the Nested Vectored Interrupt Controller NVIC The enable interrupts include timers 32b0 32b1 16b0 16b1 and external interrupt EINTO 8 1 7 SysTick c The SysTick timer provides the heartbeat and delay function timing The transmit time out counter is also implemented using the systick interrupt 8 1 8 32b TimerO0 c The 32b0 timer provides the transmit timing for the master tr
14. 013 5 of 43 NXP Semiconductors U M1 0495 TDA5051A lighting master slave demo board OM13314 4 2 TDA5051A demo board I O master configuration The TDA5051A demo board provides a number of switches and visual indicators to control and monitor the Power Line communications The details on how these are used in the master configuration are discussed in the following sections 4 x PCF8883 capacitive proximity switches or e 3 3V push button switches LDO ON OFF 1 43 8 V Cts a 1 1 1 i macc DIM DOWN 1 1 SELECT OUTPUTS Pal dc 12V to 220 V CLK OUT AC DC normal operation blinking HB_LED at 1 second intervals stops blinking with COM_LED blinks slave fault to indicate which LED is selected 002aag470 Fig 3 Block diagram of master lighting controller 4 2 1 Onboard visual indicators Table 1 shows the onboard LEDs and their function in the master configuration Table 1 Onboard LEDs and function LED label LED function Control drive source Notes HB_LED processor heartbeat LPC1114 PIO3_2 blinks when operational COM LED Com status LPC1114 PIO3 4 blinks when select is pressedll 1 When pressing the external select switch the Com LED will blink to indicate which item is being selected as detailed in Section 4 2 2 4 2 2 External switch interface The master configuration requires four external switches to be connected to header SV2 This may be
15. 10495 9 1 TDA5051A lighting master slave demo board OM13314 Slave firmware description zero crossing synchronization The slave firmware for the TDA5051A SSL demo application contains a number of C application modules combined with system and core code The modules are described in Section 9 1 1 through Section 9 1 14 Main_loop c This module calls all the initialization code for all the other modules and provides the While 1 loop to test for application flags The flags tested by the master include byte level and message level receive flags transmit status flag to see if all bytes in message have been transmitted and transmit response flag If the flag gets set the test function will call an application function in the related module to act 16b timer1 c Timer 16b1 on the LPC1114 provides the receive sample timing and is set to interrupt at a rate 16x transmit data rate The middle five samples of each bit time are used to determine the logic state of the received bit by state of a majority of the samples UART c This was used for initial debug 10 c This configures the I O of the LPC1114 including setting the functions and direction of the I O pins The I O interfacing with the zero crossing opto coupler also generates an interrupt on both edges of the signal This pulse width of the opto coupler output is measured to estimate the zero crossing as described later Command c This is only used for debug NVIC c
16. 13 V DC supply voltage The master employs 4 x PCF8883 capacitive proximity switches to provide On Off Dim Up Dim Down and Select outputs of the remote lighting slave controller The slave controller consists of the High Bay board an AC DC converter to provide 13 V supply voltage and an LED array Both the master and the slave are housed in a plastic box with 110 V AC power cords 002aag521 Fig 1 TDA5051A master lighting controller 002aag522 Fig 2 TDA5051Aslave lighting controller All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 3 18 December 2013 3 of 43 NXP Semiconductors U M1 0495 TDA5051A lighting master slave demo board OM13314 2 PLM demo board The TDA50514 lighting demo board is designed to let customers evaluate the TDA5051A in a realistic application The TDA5051A lighting demo board schematic is found in Section 12 Appendix B TDA5051A lighting demo board schematic The demo board includes a the TDA5051A an LPC1114 microcontroller a PCA9632 I C bus to PWM converter and software containing some pre defined functions to brighten and dim the four available LED outputs from the PCA9632 The parameters used by these functions can be easily changed by changing a configuration header file with parameter values used by the pre defined functions To further customize the application the drive
17. 3 10 of 43 NXP Semiconductors U M1 0495 TDA5051A lighting master slave demo board OM13314 5 1 3 Demo board connections slave configuration RS 232 interface address switch ISP set to 1 external LEDs debug interface HB LED TH t og x pes 2 iov COM LED es i DC power P n M i 002aag475 AC line Fig 8 TDA5051A demo board connections for slave configuration UM10495 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 3 18 December 2013 11 of 43 NXP Semiconductors U M1 0495 TDA5051A lighting master slave demo board OM13314 6 Protocol requirements UM10495 6 1 6 2 The objective of this demo software is to provide a protocol structure that defines the bit level frames and message frames to provide a number of capabilities including the following Source and destination addresses allowing multiple masters and multiple slaves Parity and checksum error detection and message re transmission to increase reliability of communications e Sub address to communicate with multiple channels within a fixture Bidirectional communications to allow getting status or configuration information from slaves The message level protocol for implementations using zero crossing or start bit synchronization is the same however the bit level frames are different as discussed in the next section Bit
18. CA9632 outputs will get dimmer When this data is being received by the slave the COM LED will blink The On Off switch sends the On Off command to the slave All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 3 18 December 2013 27 of 43 NXP Semiconductors U M1 0495 TDA5051A lighting master slave demo board OM13314 The Select switch will select different dim modes The default setting for the Select Switch is group In this mode a Dim Up or Dim Down command will affect all LED PWM outputs There are 16 steps from full ON to full OFF in this mode Pressing this switch once will select PWM output 0 The COM LED on the master will blink once when PWMO is selected Only PWMO will be affected by a Dim Up or Dim Down in this mode There are 64 steps from ON to OFF in this mode Pressing the switch again will select PWM1 with 64 steps The COM LED on the master will blink twice when PWM1 is selected Pressing the switch again will select PWM2 with 64 steps The COM LED on the master will blink three times when PWN2 is selected Pressing the switch again will select PWMS with 64 steps The COM LED on the master will blink four times when PWMS is selected Pressing the switch again will bring you back to the group mode The COM LED on the master will blink 1 long blink when GROUP is selected The relative levels of PWMO PWWMS are preserved when d
19. Device LPC1114 301 E 5 jack 0 QvOn0000 OXODOFFF 000 0001 FFF COM Port COM 11 ET 2 Di DO2ODO DOCZFFF Baud Rate 38400 i Interface None ISP Oscillator MHz L Erase blocks used by Hex File Hex File 3L_2011 UART_SYNC PLM_US_Mas_V1_O Flash PLM_Test hex Modified Thursday July 7 2011 7 12 56 PM more info Gen black checksume Execute Visit the Flash Magic home page for info on the latest revision www esacademy com software flashmagic 002aag485 Fig 18 Configure Flash Magic utility For Step 1 The COM port is the RS 232 port assignment for your PC usually COM1 Fill in the other entries as shown in Figure 18 For Step 2 check the box as shown in Figure 18 For Step 3 browse to the hex file provided for programming In addition to the above set up values pull down the options menu and select Advanced Options The communications and hardware configurations should be set as shown in Figure 19 and Figure 20 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 3 18 December 2013 34 of 43 UM10495 TDA5051A lighting master slave demo board OM13314 NXP Semiconductors Advanced Options Communications Hardware Config Security Just In Time Code Timeouts Misc High Speed Communications MasimumBaudRate 230400 w
20. F T o0tuF 47 uH RFB0807 470L ua TEST 8 8 DATAN GND e Ny gt Q gt T 78250_SIPM CLKOUT I4 pp 18 eg 28 axi ISP MODE oo GI Y 74AHC1GO6DCK GND L2 22 uH RFBO807 220L v GND GND PTVS7V0S1UR v GND JTAG RESET 2 JTAG TCLK SWCLK 5V IC3 MIC5205 3 3YM5 3 3 V Fig 24 TDA5051A lighting demo board schematic c2 LPC1114FHN33 RESET PIOO 0 PIOO_1 CLKOUT CT32B0_MAT2 PIO0_2 SSELO CT16B0_CAPO PIO0_3 PIOO 4 SCL PIOO 5 SDA PIO0_6 SCKO PIO0_7 CTS PIO0_8 MISOO CT16B0_MATO PIO0_9 MOSIO CT16B0_MAT1 R PIOO 11 ADO CT32B0 MAT3 RX TX R PIO1 0 AD1 CT32B1 CAPO R PIO1 1 AD2 CT32B1 MATO R PIO1 2 AD3 CT32B1 MAT1 SWDIO PIO1 3 AD4 CT32B1 MAT2 PIO1 4 ADS CT32B1 MAT3 WAKEUP PIO1 5 RTS CT32B0 CAPO PIO1 6 RXD CT32B0 MATO PIO1 7 TXD CT32BO0 MAT1 PIO1 8 CT16B1 CAPO PIO1 9 CT16B1 MATO SWCLK PIO0 10 SCKO CT16BO MAT2 PIO1 10 ADG CT16B1 MAT1 GND MAX3232CUE u a a j iS R2OUT Ramn d ISP LVF o RIOUT RINE o oS W I2IN T20UTE TP lon TIIN T10UT a IP Ot ye wlZ O c2 GND 0 1 pF c1 s uF IC6 gt GND 2 e P JTAG_TMS_SWDIO E x e e SLAVEADDRESS je e CR cma ge C2 IN IN a amp PIO1 T1 AD7 L ewe SW GND S a Az PIO2 0 DTR CRD16RMOSBOSB I 8 PIO3 2 PIO3 4 PIO3 5 i 2 3 4 e
21. Notes HB_LED processor heartbeat LPC1114 PIO3 2 blinks when operational COM LED Com status LPC1114 PIO3 4 blinks when communicating External LED interface The LED outputs from the PCA9629 can drive LEDs directly up to a specified limit or it can provide PWM controlled dimming for external high current LED power supplies In the demo application an external array of four white low power LEDs is driven from the PCA9632 The LEDS are biased with current limiting resistors and an external connection to a power supply on the demo board see the schematic in Figure 7 The connection to the external LEDs is via header J501 on the TDA5051A demo board with the pin assignments is given in Table 4 Table 4 Pin assignments for external LED connection via header J501 Header pin Function Signal destination Notes 1 PWM3 LED3 via external CL resistor to 3 3 V 2 GND supply GND 3 PWM2 LED2 via external CL resistor to 3 3 V 4 PWM1 LED1 via external CL resistor to 3 3 V 5 PWMO LEDO via external CL resistor to 43 3 V SS 7 R1 R2 R3 iod po VW nV o2 W ws Ve LEDO LED1 LED2 LED3 002aag474 X connections to 3 3 V supply and header J501 on TDA5051A demo board Fig 7 Schematic for external array of four white LEDs All information provided in this document is subject to legal disclaimers NXP B V 2013 AII rights reserved User manual Rev 3 18 December 201
22. PLM demo board slave program the devices with UART Style Slave code V1 1 using one of the programming methods discussed in Section 11 Appendix A Programming instructions Slave Switch setting The firmware is set up to transmit to Slave address 1 so make sure the hex switch on the slave is set to 1 Hook up the power AC line and LEDs to the TDA5051A demo board as shown in the following 973 FJ imo pI Dei a TAO CTI O Sleta Tey eR a JOE ERUCFER C21710 AC or DC line Je Fig 16 Hookup of power AC line and LEDs to TDA5051A demo board slave All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 3 18 December 2013 31 of 43 NXP Semiconductors U M1 0495 UM10495 10 2 4 10 2 5 TDA5051A lighting master slave demo board OM13314 Demo operation start bit UART style synchronization With both master and slave powered and connected to the line the HB_LED should blink on both units The slave should initialize with the LEDs illuminated at about 1 4 of the maximum When the Dim up switch is pressed the LEDs connected to the PCA9632 outputs will get brighter When the data is being received by the slave the COM_LED will blink When the Dim down switch is pressed the LEDs connected to the PCA9632 outputs will get dimmer When this data is being received by the slave
23. R losses but provide a known impedance at 125 kHz for the TDA5051A to communicate Troubleshooting start bit UART style synchronization In case of problems the first thing to verify is that the HB LEDs on both master and slave are blinking This means the unit is powered up and the microcontroller is functioning Verify the connections to the power are complete On the Master verify the COM LED blinks when pressing Select If not verify the switch connections If everything looks good on the master observe the slave to see if the COM LED blinks when a Dim UP or Dim Down command is received This will verify the master is communicating with the slave If everything looks good up to this point but the dim up and dim down are still not functional verify the LED connections to the TDA5051A demo board If the LEDs need external power verify the LED power is operational If still not functional verify the LEDO LED3 outputs with an oscilloscope to determine if a PWM signal is present If the PWM signal is present the problem is probably bad LEDs or other problems with the LED assembly All information provided in this document is subject to legal disclaimers NXP B V 2013 AII rights reserved User manual Rev 3 18 December 2013 32 of 43 NXP Semiconductors U M1 0495 TDA5051A lighting master slave demo board OM13314 11 Appendix A Programming instructions UM10495 The TDA5051A dem
24. This sets the priority and enables required interrupts in the Nested Vectored Interrupt Controller NVIC The enable interrupts include timers 32b0 32b1 16b0 16b1 and external interrupt EINTO SysTick c The SysTick timer provides the heartbeat and delay function timing 32b TimerO c The 32b0 timer provides transmit timing allowing the slave to respond back to a master 12C c This contains the driver code for the I2C bus peripheral on the LPC 1114 The I C interface is used by the slave to communicate with the PCA9632 I C bus to PWM LED driver The application specific code is contained in the 12C Messages c module described in Section 9 1 10 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 3 18 December 2013 21 of 43 NXP Semiconductors U M1 0495 UM10495 9 1 10 9 1 11 9 1 12 TDA5051A lighting master slave demo board OM13314 I2C Messages c This module contains the functions that interpret the incoming commands and channel assignments and sends corresponding 12C messages to the PCA9632 The PCA9632 is initialized in the Group Dim Mode where a 190 Hz fixed frequency Group signal is superimposed with the 6 25 kHz Individual brightness control signals PWMO PWM 1 PWM2 and PWM3 The Select function on the master sets the outgoing channel number in the PLM Master transmit frame This channel number is r
25. UM10495 TDA5051A lighting master slave demo board OM13314 Rev 3 18 December 2013 User manual Document information Info Content Keywords TDA5051A LPC1114 PCF8883 zero crossing and UART style synchronization lighting demo Abstract This document is a user manual for the TDA5051A Power Line Modem PLM master slave lighting controller demo OM13314 NXP Semiconductors U M1 0495 TDA5051A lighting master slave demo board OM13314 Revision history Rev Date Description v 3 20131218 User manual third release Figure 24 TDA5051A lighting demo board schematic revised T1 rotated 180 v 2 20120511 User manual second release v 1 20110816 User manual initial release Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com UM10495 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 3 18 December 2013 2 of 43 NXP Semiconductors U M1 0495 Ti TDA5051A lighting master slave demo board OM13314 Introduction UM10495 The TDA5051A lighting control demo consists of a master controller and a slave lighting controller The master controller uses the High Bay board which consists of the LPC1114 microcontroller the TDA5051A PLM IC and power management circuitry An AC DC converter is used to provide
26. al Rev 3 18 December 2013 13 of 43 NXP Semiconductors UM10495 UM10495 TDA5051A lighting master slave demo board OM13314 7 1 2 Message level protocol The message level protocol was designed to provide a number of features The message structure has the ability work with multiple masters and multiple slave by having a master and slave address included in the frame Error handling is also included by providing a message checksum along with the frame by frame parity to detect errors The message level protocol is detailed in Figure 10 starting with the master transmit message frame Fig 10 Start Slave Master Sub Byte Address Address Address Command Data Data Checksum Byte Byte 1 Byte 2 Byte 002aag477 The Start Byte is a specific value for a master transmission and indicates the beginning of a message The slave address is the destination and for lighting applications is typically a lighting fixture It could also potentially address a bridge device such as a PLM DALI bridge or PLM RS 232 bridge to allow communications between protocols The master address is present to support multi masters For example for home lighting there may be masters in every room So a slave could be programmed to only respond to the master in the room it is located in It could also respond to broadcast command to turn off or dim lights at certain hours or when a residence is vacated for energy management The sub a
27. ansmitter This is a 1x clock synchronized by an offset from the zero crossing This provides a timing reference for the output data 8 1 9 PLM_Master c This handles the message level communications for the PLM master providing synchronization transmitting commands receiving acknowledgements and handling error conditions This module also contains the External interrupt handler that is active on both edges of the zero crossing opto coupler This is used to determine the estimated zero crossing using timer 32b1 as described in Section 8 1 10 8 1 10 32b Timer1t c This is used to time the start of frame offset from the zero crossing Part of this involves timing the pulse width of the zero crossing pulse from the opto coupler Since the opto coupler output is symmetrical around the actual zero crossing the time from the second edge of opto coupler pulse to the actual zero crossing can be estimated by dividing the pulse width by two This is subtracted from the number of counts required for the 5 16 ms offset and loaded into timer 32b1 to set the offset time from the second edge The timer 32b1 interrupt then sets the start time of the offset bit frame 8 1 11 Timer16b_0 c The master uses this as the debounce timer for the switch inputs 8 1 12 PLM UART c This contains the routines that handle the bit level synchronization and data transmission and reception This uses the timing references from the 16b1 and 32b2 timers to implement a s
28. ation function in the related module to act 16b timer1 c Timer 16b1 on the LPC1114 provides the receive sample timing and is set to interrupt at a rate 16x transmit data rate The middle five samples of each bit time are used to determine the logic state of the received bit by state of a majority of the samples UART c This is only used for debug 10 c This configures the I O of the LPC 1114 including setting the functions and direction of the I O pins This also configures the RX pin used by the PLM UART as an external interrupt that detects the HIGH to LOW transition at the beginning of the start bit This module also contains the functions to detect the closure of a command switch and take the appropriate action or sent the corresponding command to the slave Command c This is only used for debug NVIC c This sets the priority and enables required interrupts in the Nested Vectored Interrupt Controller NVIC The enable interrupts include timers 32b0 32b1 16b0 16b1 and external interrupt EINTO All information provided in this document is subject to legal disclaimers NXP B V 2013 AII rights reserved User manual Rev 3 18 December 2013 23 of 43 NXP Semiconductors U M1 0495 UM10495 9 2 7 9 2 8 9 2 9 9 2 10 9 2 11 TDA5051A lighting master slave demo board OM13314 SysTick c The SysTick timer provides the heartbeat and delay function timing 32b TimerO c The 32b0 timer provides
29. ation of a logarithmic dimming curve As the eye sensitivity is logarithmic providing some approximation of this gives the Dim Up and Dim Down commands a more natural response The dimming curve functions are located in the PLM Slave module discussed in Section 9 1 11 PLM Slave c This handles the message level communications for the PLM slave providing synchronization receiving commands transmitting acknowledgements and handling error conditions The received Dim Up and Dim Down commands result in PWM values that are incremented or decremented through simple dimming curve functions contained in this module as discussed in the previous section This module also contains the External interrupt handler that is active on both edges of the zero crossing opto coupler This is used to determine the estimated zero crossing using timer 32b1 as described in Section 9 1 12 32b Timer1 c This is used to time the start of frame offset from the zero crossing in the same manner as the master Part of this involves timing the pulse width of the zero crossing pulse from the opto coupler Since the opto coupler output is symmetrical around the actual zero crossing the time from the second edge of opto coupler pulse to the actual zero crossing can be estimated by dividing the pulse width by two This is subtracted from the number of All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved
30. d 13 V DC power supply 4 LEDs with current limit resistors Power supply for LED assembly AC line connection Cabling to mate with headers on demo board for ACline DC power LED assembly with current limit resistors LED power as required All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 3 18 December 2013 25 of 43 NXP Semiconductors U M1 0495 UM10495 TDA5051A lighting master slave demo board OM13314 10 1 3 Demo configuration zero crossing synchronization 10 1 3 1 Master Assemble the hardware pieces described in Section 10 1 1 If the firmware has not been loaded into the LPC1114 on the PLM demo board master program the devices with Zero Crossing Master code V2 09 using one of the programming methods discussed in Section 11 Appendix A Programming instructions Master Switch setting The master does not use the hex switch however it is connected to the same pins on the microcontroller as the control switches Make sure the hex switch on the slave is set to 0 the open state to prevent any conflict with the external switches Hook up the power AC line and switches to the TDA5051A demo board as shown in Figure 13 y3 Fre ZIEL a rA CEP a DC power AC line EF 002aag480 Fig 13 Hook up of power AC line and switches to TDA5051A demo board master
31. d has been received over the power lines and execute the command In the demo firmware provided the commands received over the power lines result in sending an 12C message to the PCA9632 LED PWM controller to control the output brightness of four externally connected LEDs I2C BUS TEMP AND AMBIENT LIGHT SENSORS PWMO to PWM3 4x HB LEDs MODULE 7 12V to 220 V AC DC normal operation blinking HB_LED at 1 second intervals stops blinking with COM_LED blinks slave fault to indicate successful ADDRESS SET communications SWITCH 002aag473 Fig 6 Block diagram of slave lighting controller UM10495 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 3 18 December 2013 9 of 43 NXP Semiconductors U M1 0495 UM10495 5 1 TDA5051A lighting master slave demo board OM13314 TDA5051A demo board I O slave configuration The TDA5051A demo board provides a number of switches and visual indicators to control and monitor the Power Line communications The details on how these are used in the slave configuration are discussed in the following sections Onboard visual indicators slave configuration Table 3 shows the onboard LEDs and their function in the slave configuration Table 3 Onboard LEDs function in slave configuration LED label LED function Control drive source
32. ddress could be a specific light or color in the lighting fixture Or in the case of a Dali Bridge device this could be the Dali address byte The command byte tells the slave how to respond The proposed protocol uses similar command assignments as Dali In a Dali bridge device this would be the Dali command If similar command assignments are used in the PLM protocol no command translation would be required in a Dali bridge device Data Byte1 Data Byte 2 are available if the command indicates the slave should use the data that follows Depending on the specified command the data bytes can be interpreted as two 8 bit values or one 16 bit value In a PLM RS 232 bridge device this number of bytes could be expanded to allow for more data bytes if needed Larger frames are not intended to be supported in the initial implementation for the lighting application The checksum byte contains the two s complement checksum of the previous seven bytes The slave should sum the start byte and all remaining bytes including the checksum If the result is 0 the frame has been received without a checksum error Master transmit message frame All information provided in this document is subject to legal disclaimers NXP B V 2013 AII rights reserved User manual Rev 3 18 December 2013 14 of 43 NXP Semiconductors U M1 0495 UM10495 7 2 7 2 1 TDA5051A lighting master slave demo board OM13314 The slave will respo
33. e NXP UM10495 All information provided in this document is subject to legal disclaimers Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities Evaluation products This product is provided on an as is and with all faults basis for evaluation purposes only NXP Semiconductors its affiliates and their suppliers expressly disclaim all warranties whether express implied or statutory including but not limited to the implied warra
34. e is useful to be able to set the brightness mix of the different outputs then increasing or decreasing all outputs at the same time while still maintaining the same mix Refer to the PCA9632 data sheet Ref 1 for more information The brightness levels of both the GRPPWM and PWMXx registers are initialized at a mid level of brightness To get maximum duty cycle from the outputs increase both group and individual levels via the master Dim Up and Dim Down and Select The Off On command from the master results in the slave sending an I2C message to the PCA9632 to enable or disable all or none of the LEDx output drives via the LEDOUT register on the PCA9632 The actual levels sent to the GRPPWM and PWMx registers are incremented via functions that provide a simple piece wise linear approximation of a logarithmic dimming curve As the eye sensitivity is logarithmic providing some approximation of this gives the Dim Up and Dim Down commands a more natural response The dimming curve functions are located in the PLM Slave module discussed in Section 9 2 11 PLM Slave c This handles the message level communications for the PLM slave providing synchronization receiving commands transmitting acknowledgements and handling error conditions The received Dim Up and Dim Down commands result in PWM values All information provided in this document is subject to legal disclaimers NXP B V 2013 AII rights reserved User
35. e programming firmware updating SWD RS 232 UM10495 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 3 18 December 2013 4 of 43 NXP Semiconductors U M1 0495 TDA5051A lighting master slave demo board OM13314 This document will also discuss the firmware required to implement the demos One set of firmware was written utilizing the zero crossing of the AC line as a method to synchronize transmission The other set of firmware was written to use a start bit stop bit synchronization similar to a UART to allow transmission over DC lines that have no zero crossing information 3 Hardware requirements 3 1 3 2 The hardware requirements for both firmware implementations are similar when using the AC line as transmission medium Due to the synchronization differences of the two different firmware implementations the UART style would not need the opto coupler that is on the TDA5051A demo board Considerations for other implementations will be discussed in a later section Even though the same demo board is used for both the master and the slave not all components are used in both configurations as discussed later in Section 4 and Section 5 Master hardware configuration To implement the master the hex address switch SW1 is not needed If SW1 is populated set the switch to the 0 position all open This allows four exter
36. ead by the slave to determine which register on the PCA9632 is addressed when it sends out 12C commands The corresponding registers on the PCA9632 and a short description are shown in Table 5 Table 5 PCA9632 corresponding registers Register Range of values Description GRPPWM 0 to 15 this is used as a global brightness control allowing the LED outputs to be dimmed with the same value PWMO 0 to 63 Individual Brightness control for PWMO output PWM1 0 to 63 Individual Brightness control for PWM1 output PWM2 0 to 63 Individual Brightness control for PWM2 output PWM3 0 to 63 Individual Brightness control for PWMS output This mode is useful to be able to set the brightness mix of the different outputs then increasing or decreasing all outputs at the same time while still maintaining the same mix Refer to the PCA9632 data sheet Ref 1 for more information The brightness levels of both the GRPPWM and PWMXx registers are initialized at a mid level of brightness To get maximum duty cycle from the outputs increase both group and individual levels via the master Dim Up and Dim Down and Select The Off On command from the master results in the slave sending an I2C message to the PCA9632 to enable or disable all or none of the LEDx output drives via the LEDOUT register on the PCA9632 The actual levels sent to the GRPPWM and PWMx registers are incremented via functions that provide a simple piece wise linear approxim
37. eartbeat function to indicate that the microcontroller is functioning when blinking The COM LED indicates which of the functions is selected when the select switch is activated by the following indications One short blink PWMO is selected Two short blinks PWM1 is selected Three short blinks PWM2 is selected Four short blinks PWMS is selected One long blink GROUP is selected The Master transmission contains a slave address to select which device will recognize its commands Since there are no additional inputs on the TDA5051A demo board to set this address it is hard coded to be 0x01 Master firmware implementation zero crossing synchronization The master firmware for the TDA5051A SSL demo application contains a number of C application modules combined with system and core code The modules are described in Section 8 1 1 through Section 8 1 12 Main loop c This module calls all the initialization code for all the other modules and provides the While 1 loop to test for application flags The flags tested by the master include byte level and message level receive flags transmit status and transmit error flags If the flag gets set the test function will call application function in the related module 16b timer1 c Timer 16b1 on the LPC1114 provides the receive sample timing and is set to interrupt at a rate 16x transmit data rate The middle five samples of each bit time are used to determine the
38. ends an On Off command 2 Dim Up LPC1343 PIO1 9 sends a Dim Up command 3 Dim Down LPC1343 PIO1 10 sends a Dim Down command 4 Select LPC1343 PIO1 11 rotates the selected channel 5 ground 1 Rotates the selected channel from the following and blinks the COM LED when changed as noted below GROUP 1 Com LED long blink PWMO 1 Com LED short blink PWM1 2 Com LED short blinks PWM2 3 Com LED short blinks PWMS3 4 Com LED short blinks 4 2 3 Demo board connections master configuration A TDA5051A demo board four switches an AC line connection and a DC power input are required to implement a master for the SSL demo The functions assigned to the switch inputs are discussed in a later section The interface connections to the TDA5051A demo board are shown in Figure 5 RS 232 ISP external interface jumper switches address switch ISP master set to 0 debug HB LED interface COM LED DC power Led Pm E OO 002aag472 AC line Fig5 TDA5051A demo board interface connections UM10495 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 3 18 December 2013 8 of 43 NXP Semiconductors U M1 0495 TDA5051A lighting master slave demo board OM13314 5 TDA5051A demo board slave configuration In the slave configuration one of the tasks of the LPC1114 microcontroller is to detect when a comman
39. ero crossing time of the master is not coincident with the zero crossing of the slave For these applications firmware was developed that uses a start bit to synchronize the reception of the data so a zero crossing is not required After the start bit a frame bit is needed to provide message level synchronization The frame bit is then followed by eight data bits a parity bit and a stop bit In the same way as was done with the zero crossing firmware a 16x receive clock is generated and five samples taken in the middle of the bit time The received state of the sampled bit is determined by the majority of the five samples taken to increase noise immunity as noted in the previous section All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 3 18 December 2013 12 of 43 NXP Semiconductors U M1 0495 TDA5051A lighting master slave demo board OM13314 7 Protocol specification UM10495 7 1 7 1 1 Two sets of firmware were generated for the TDA5051A demo board for the two different synchronization methods discussed in the previous section Each set includes master and slave firmware The following protocol specifications were generated based on the requirements listed in Section 6 Protocol specification zero crossing synchronization Bit level protocol zero crossing synchronization In transmitting over the AC lines there is a region a
40. est function will call an application function in the related module to act 16b timer1 c Timer 16b1 on the LPC1114 provides the receive sample timing and is set to interrupt at a rate 16x transmit data rate The middle five samples of each bit time are used to determine the logic state of the received bit by state of a majority of the samples The start of the sample time is determined by an offset from the zero crossing UART c This is only used for debug 10 c This configures the I O of the LPC 1114 including setting the functions and direction of the I O pins This also configures the RX pin used by the PLM UART as an external interrupt that detects the HIGH to LOW transition at the beginning of the start bit This module also contains the functions to detect the closure of a command switch and take the appropriate action or sent the corresponding command to the slave Command c This is only used for debug NVIC c This sets the priority and enables required interrupts in the Nested Vectored Interrupt Controller NVIC The enabled interrupts include Timer 32b0 Timer 16b1 and the external interrupt SysTick c The SysTick timer provides the heartbeat and delay function timing 32b TimerO c The 32b0 timer provides the transmit timing for the master transmitter All information provided in this document is subject to legal disclaimers NXP B V 2013 AII rights reserved User manual Rev 3 18 December 2013
41. frame protocol considerations zero crossing synchronization By using the zero crossing of the AC signal to synchronize the bit frame we can structure the protocol to avoid the peaks of the AC line where the noise is greatest and the line impedance is the lowest Most low power factor equipment draws the most current at the peaks As a result the line impedance may drop significantly when the rectifier diodes in the equipment are conducting at the peaks of the AC line This can affect the amount of signal coupled onto the AC line potentially causing errors By having the bit frame start 1 ms after the peak of the AC sine wave and ending the bit frame 1 ms before the AC peak the noisy low impedance portion of the AC line can be avoided increasing the reliability of the communications link For received data 16x sample clock is generated and five samples are taken in the middle of the bit time The received state of the sampled bit is determined by the majority of the five samples taken This helps reduce reception errors due to short noise spikes that may occur at a sample time but is averaged out over several samples The bit frame for the zero crossing implementation will be detailed in Section 7 Bit frame protocol considerations start bit UART style synchronization For some applications such as DC links solar panels DC power distribution a zero crossing signal is not available Also when coupling between different phases the z
42. imming up or down when returning to Group mode Additional details on the group dimming mode can be found in the PCA9632 data sheet 10 1 5 Troubleshooting zero crossing synchronization In case of problems the first thing to verify is that the HB LEDs on both master and slave are blinking This means the unit is powered up and the microcontroller is functioning Verify the AC line is connected to both master and slave Without an AC line the TDA5051A demo board will not try to communicate since it needs to detect a zero crossing to synchronize transmission and reception On the Master verify the COM LED blinks when pressing Select If not verify the switch connections If everything looks good on the master observe the slave to see if the COM LED blinks when a Dim Up or Dim Down command is received This will verify the master is communicating with the slave If everything looks good up to this point but the dim up and dim down are still not functional verify the LED connections to the TDA5051A demo board If the LEDs need external power verify the LED power is operational If still not functional verify the LEDO LED3 outputs with an oscilloscope to determine if a PWM signal is present If the PWM signal is present the problem is probably bad LEDs or other problems with the LED assembly UM10495 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manua
43. information 15 1 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information 15 2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors
44. is for reference only The English version shall prevail in case of any discrepancy between the translated and English versions 15 3 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners NXP B V 2013 AII rights reserved User manual Rev 3 18 December 2013 41 of 43 NXP Semiconductors UM10495 16 Contents TDA5051A lighting master slave demo board OM13314 2 1 2 2 3 1 3 2 4 1 4 2 4 2 1 4 2 2 4 2 3 5 1 5 1 1 7 1 1 7 1 2 7 2 7 2 1 UM10495 Introduction 000 20 cece eee eee PLM demo board Ls Power line communications Demo application overview Hardware requirements Master hardware configuration Slave configuration 00 Master hardware description TDA5051A demo board leesslees TDA5051A demo board general TDA5051A demo board I O master configuration llle Onboard visual indicators External switch interface Demo board connections master configuration TDA5051A demo board slave configuration lses TDA5051A demo board I O slave configuration Onboard visual indicators slave configuration External LED interface
45. l Rev 3 18 December 2013 28 of 43 NXP Semiconductors U M1 0495 TDA5051A lighting master slave demo board OM13314 10 2 Setup requirements start bit UART style synchronization 10 2 1 Setup requirements master start bit UART style synchronization Hardware needed master TDA5051A demo board 13 V DC power supply Internally 5 V and 3 3 V are generated from this using linear regulators 4 mechanical or cap sense switches power supply for cap sense switch assembly If cap sense switches are used Not required when using mechanical switches AC or DC line connection DC lines may need a small network at each end to provide a controlled impedance to the PLM demo board Cabling to mate with headers on demo board for ACor DC line and networks DC power Switch interface Cap sense supply as required 10 2 2 Setup requirements slave start bit UART style synchronization Hardware needed slave UM10495 TDA5051A demo board 13 V DC power supply 4 LEDs with current limit resistors Power supply for LED assembly AC or DC line connection Cabling to mate with headers on demo board for ACor DC line and networks DC power LED Assembly with current limit resistors LED power as required All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 3
46. manual Rev 3 18 December 2013 24 of 43 NXP Semiconductors U M1 0495 TDA5051A lighting master slave demo board OM13314 that are incremented or decremented through simple dimming curve functions contained in this module as discussed in the previous section This module also contains the External interrupt handler used to detect the HIGH to LOW transition of the start bit at the beginning of a bit frame 9 2 12 PLM_UART c This contains the routines that handle the bit level synchronization data transmission and reception This uses the timing references from the 16b1 and 32b2 timers to implement a soft UART specifically for the interfacing to the TDA5051A 10 Demo setup and operation UM10495 10 1 Demo setup and operation zero crossing synchronization 10 1 1 Setup requirements master zero crossing synchronization Hardware needed master TDA5051A demo board 13 V DC power supply Internally 5 V and 3 3 V are generated from this using linear regulators 4 mechanical or cap sense switches power supply for cap sense switch assembly If cap sense switches are used Not required when using mechanical switches AC line connection Cabling to mate with headers on demo board for AC line DC power Switch interface Cap sense supply as required 10 1 2 Setup requirements slave zero crossing synchronization Hardware needed slave TDA5051A demo boar
47. nal switches to be connected to the same pins on the microcontroller as SW1 without generating a conflict The external switches mate with the SV2 connector on the demo board A DC power supply and connection to the AC line are also needed for the master Additional details can be found in Section 4 Slave configuration To implement the slave for the SSL demo the TDA5051A demo board four LEDs with current limiting resistors an AC line connection and a DC power input are required to implement a PLM slave for the SSL demo The slave actions in response to received commands are discussed in Section 5 4 Master hardware description TDA5051A demo board 4 1 UM10495 In the master configuration the TDA5051A demo board reads switch closures and generates commands that are transmitted by the TDA5051A over the AC lines The details of how the LPC1114 handles these tasks will be discussed in the firmware portion of the Users Manual TDA5051A demo board general The NXP TDA5051A and the LPC1114 are the heart of the board with the TDA5051A providing the modem interface to the power lines and the LPC1114 providing a high performance programmable processor at low power and low cost It handles all of the intelligent functions of the board and manages the peripheral interfaces All information provided in this document is subject to legal disclaimers NXP B V 2013 AII rights reserved User manual Rev 3 18 December 2
48. nd to the master if the command is received with a valid start byte Start Master Slave Command Byte Address Address Byte Completion Data Data Checksum Code Byte 1 Byte 2 Byte 002aag478 Fig 11 Slave receive message frame A completion code of 0 indicates the master s command was received with parity bits correct the checksum correct a valid start byte and the correct number of bytes received Completion codes could be assigned to parity or checksum errors so statistics can be obtained for these if desired Other completion codes for special error conditions could also be defined if needed If the master receives no response the master will transmit the message up to three times configurable before aborting the attempt The data bytes in the response frame could provide the ability to query the slave about its status configuration etc Even though the frame structure could support slave queries the application code described here only implements basic communications and command functions to demonstrate capabilities while leaving enough flexibility to allow the user to enhance the code as needed for their own applications Protocol specification start bit UART style synchronization Bit level protocol start bit UART style synchronization There are applications where zero crossing synchronization is not feasible This specification was developed and firmware was written to address those situatio
49. ns A start bit transition and additional data samples are used to synchronize the reception of the data so a zero crossing is not required After the start bit a frame bit is used to provide message level synchronization The frame bit is then followed by eight data bits a parity bit and a stop bit In the same way as was done with the zero crossing firmware a 16x receive clock is generated and five samples are taken of all bit in the middle of the bit period The received state of the sampled bit is determined by the majority of the five samples taken to increase noise immunity as noted in the previous section Synchronization at the bit level is performed in the same manner as a UART The idle state of the soft PLM UART RX and TX pins on the microcontroller is HIGH Since this matches the TDA5051A idle state we can directly connect the TX pin on the microcontroller to the DATA IN pin on the TDA5051A And likewise we can connect the soft PLM UART RX pin on the micro to the DATA OUT pin on the TDA5051A So the HIGH and LOW states referred to in the specification pertain to the logic levels of the interface between the microcontroller and the TDA5051A The bit level frame is shown in Figure 12 All information provided in this document is subject to legal disclaimers NXP B V 2013 AII rights reserved User manual Rev 3 18 December 2013 15 of 43 NXP Semiconductors U M1 0495 TDA5051A lighting master sla
50. nties of non infringement merchantability and fitness for a particular purpose The entire risk as to the quality or arising out of the use or performance of this product remains with customer In no event shall NXP Semiconductors its affiliates or their suppliers be liable to customer for any special indirect consequential punitive or incidental damages including without limitation damages for loss of business business interruption loss of use loss of data or information and the like arising out the use of or inability to use the product whether or not based on tort including negligence strict liability breach of contract breach of warranty or any other theory even if advised of the possibility of such damages Notwithstanding any damages that customer might incur for any reason whatsoever including without limitation all damages referenced above and all direct or general damages the entire liability of NXP Semiconductors its affiliates and their suppliers and customer s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars US 5 00 The foregoing limitations exclusions and disclaimers shall apply to the maximum extent permitted by applicable law even if any remedy fails of its essential purpose Translations A non English translated version of a document
51. o be programmed via SW Serial Wire Many of the IDE vendors support SWD programming The SWD cable should be removed after programming to ensure proper operation The debug connection for SWD programming is shown in Figure 22 SWDebug connector Was CD ws E 19 S329 3 pIa 002aag489 Fig 22 Debug connection for SWD programming To program via SWD open up Keil uVision4 MDK ARM version 4 21 or higher Make sure the correct project is loaded and compiled The press the Load button as shown in Figure 23 UM10495 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 3 18 December 2013 37 of 43 NXP Semiconductors UM10495 UM10495 TDA5051A lighting master slave demo board OM13314 z C WKeil_projects SSL_2011WART_SYNC PLM_US_Mas_V1_0WDemo_Test uvproj pV Load olx 1 3 LPC1114 PLM Master US 73 Startup Code El System Code Core Code y Source Code Main_loop c il 16b Timerl c command c NVIC c SysTick c 32b TimerD c E PLM_Master c 32b_Timer1 c 2 timer1 amp b 0 c S2 d o eoe I o on m os on o o os on PLM UART c Documentation me 49580 O Fu T Build Output LPC1114 PLM
52. o board can be programmed via an RS 232 interface onboard or via the Serial Wire debug interface available on the LPC1114 11 1 RS 232 interface A MAX3232 RS 232 interface is provided on the TDA5051A to provide a programming interface to program the device via the ISP In System Programming capability The RS 232 signals are brought out on connector SV4 with the pin assignments as follows Pin 1 Ground Pin 2 Receive Pin 3 Transmit Pin 4 LPC1114 Reset To put the device into ISP mode insert a jumper into JP1 ISP MODE and reset the device by grounding the reset pin and releasing or cycling the power to provide a power on reset The ISP configuration is shown in Figure 17 RS 232 interface ES ISP jumper 002aag484 Fig 17 ISP configuration All information provided in this document is subject to legal disclaimers NXP B V 2013 AII rights reserved User manual Rev 3 18 December 2013 33 of 43 NXP Semiconductors U M1 0495 UM10495 TDA5051A lighting master slave demo board OM13314 A PC utility is then needed to send the program code to the microcontroller The utility used is Flash Magic www nxp com redirect flashmagictool com This is a free download Install the utility and open it up Configure the utility as follows Flash Magic NON PRODUCTION USE ONLY File ISP Options Tools Help H lJA gt 9 ROB Step 1 Communications Step 2 Erase Select
53. o facilitate detection of the next Start bit Fig 12 Bit level frame 8 Master firmware overview UM10495 To implement the Master application three commands were defined and enumerated Dim Up Dim Down and On Off These commands are initiated by pressing one of three external switches or touch sensors active LOW that are connected to Port pins P1 8 P1 9 P1 10 of the LPC1114 microcontroller The fourth switch connected to P1 11 and will rotate through the different control channels available and set the selected channel number in the outgoing PLM transmit frame The details of the protocol and the command and response frame structure are discussed later P1 8 Off On Sends an On Off command to the slave via the PLM P1 9 Dim Up Sends a Dim Up command to the slave via the PLM P1 10 Dim Down Sends a Dim Down command to the slave via the PLM P1 11 Select Rotates the selected channel from the following e GROUP e PWMO PWM1 e PWM2 e PWMS More details of how these commands are interpreted will follow in the Slave section Section 9 All information provided in this document is subject to legal disclaimers NXP B V 2013 AII rights reserved User manual Rev 3 18 December 2013 16 of 43 NXP Semiconductors U M1 0495 UM10495 8 1 TDA5051A lighting master slave demo board OM13314 There are two LED indicators on the TDA5051A used by the master The HB LED is for the H
54. oft UART specifically for the interfacing to the TDA5051A UM10495 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 3 18 December 2013 18 of 43 NXP Semiconductors U M1 0495 UM10495 8 2 8 2 1 8 2 2 8 2 3 8 2 4 8 2 5 8 2 6 8 2 7 8 2 8 TDA5051A lighting master slave demo board OM13314 Master firmware implementation start bit UART style synchronization The Master configuration for implementing the start bit synchronization method is the same as the zero crossing method at the high level The switch commands and indicator actions are the same for the firmware implementations of both synchronization methods The differences discussed in the protocol section are detailed when discussing how the synchronization methods are handled in the individual firmware modules The master firmware for the TDA5051A SSL demo application contains a number of C application modules combined with system and core code The modules are described in Section 8 2 1 through Section 8 2 12 Main_loop c This module calls all the initialization code for all the other modules and provides the While 1 loop to test for application flags The flags tested by the master include byte level and message level receive flags transmit status flag to see if all bytes in message have been transmitted and transmit error flag If the flag gets set the t
55. pproximately 2 ms wide centered on the peaks of the AC sine wave where line disturbances have the greatest chance of corrupting the data transmission and reception One of the line disturbances is due to added noise from any number of sources that are active during this time With low power factor power supplies the rectifiers only conduct at the peaks of the AC signal This can result in lowering of the line impedance during this period This can lower the amount of signal coupled on to the line by the master as well as reducing the amount of signal received by the slave When synchronizing to the zero crossing the bit level transmission frame can be offset from the detected zero crossing The protocol then specifies 2 ms of dead time centered over the peaks of the AC line to avoid the disturbance region of the AC line At 60 Hz a half cycle of the AC line is 8 33 ms in duration Avoiding the 2 ms disturbance region leaves 6 33 ms to transmit the bit frame This does not leave enough time to transmit a byte of data with framing and parity bits As a result the half byte is transmitted every half cycle The start of the frame is offset from the zero crossing by about 5 16 ms about 1 ms after the AC peak The format of the bit level frame is detailed in Figure 9 CYCLE FRAME BIT BIT BIT BIT PARITY TET mM 002aag476 If the frame bit is 0 it indicates the following bits should contain a valid frame byte flagging the beginning of a mes
56. r functions used in the demo firmware can be easily modified 2 1 Power line communications The TDA5051A is an ASK modem chip designed for power line communications In this application the carrier frequency is 125 kHz However the frequency can be changed with the specified range by changing the frequency of the crystal or clock input The TDA5051A consists of an AGC amplifier and ADC on the front with digital band pass filtering and demodulation of the received signal It also contains a lookup ROM and DAC to provide the proper wave shape and envelope for transmitted data The internal amplifier then drives an external network to couple the transmit data onto the AC lines 2 2 Demo application overview The TDA5051A demo board is designed for easy setup and ease of operation The demo functions are executed by pressing one of four control buttons located externally to the demo board TDA5051A demo functions supported by the demo board and firmware include the following Off On Sends an On Off command to the slave via the PLM Dim Up Sends a Dim Up command to the slave via the PLM Dim Down Sends a Dim Down command to the slave via the PLM Select Rotates the selected channel from the following e GROUP e PWMO e PWM1 e PWM2 e PWMS Some of the other features of the TDA5051A demo board are Programmable device address slave configuration e Requires 12 V input has onboard 5 V and 3 3 V regulators Flexible r
57. rved User manual Rev 3 18 December 2013 42 of 43 NXP Semiconductors UM10495 9 2 7 9 2 8 9 2 9 9 2 10 9 2 11 9 2 12 10 10 1 10 1 1 10 1 2 10 1 3 10 1 3 1 10 1 3 2 10 1 4 10 1 5 10 2 10 2 1 10 2 2 10 2 3 10 2 3 1 10 2 3 2 10 2 4 10 2 5 11 11 1 11 2 12 13 14 15 15 1 15 2 15 3 16 SYSTICKIC 3 Exec eem E d 32b Timer0 6 eos oe be been l2 iesu od poppe page Sus Sora a Suis I2C Messages C ssseees esses PLM Slave iion e Ren PLM_UART C 0 cere cit 9E da Demo setup and operation Demo setup and operation zero crossing synchronization Setup requirements master zero crossing synchronization Setup requirements slave zero crossing synchronization Demo configuration zero crossing synchronization M ster cocum tus ere ce eh as atlas Slaves cuve es wy be bee Pees ee ee Demo operation zero crossing synchronization Troubleshooting zero crossing synchronization Setup requirements start bit UART style synchronization Setup requirements master start bit UART style synchronization Setup requirements slave start bit UART style synchronization Demo configuration start bit UART style synchronization Master 2 22 66 9 eee eae dene SAVE 2 ais Ae hao scare eee eee aes Demo opera
58. sage frame When the Frame Bit is 1 the bits 0 3 during the first half cycle and bits 4 7 in the second half cycle should contain a valid frame byte The value of the parity bit is then calculated including the frame bit and bits 0 3 or 4 7 depending on the half cycle indicated by the cycle frame bit If the frame bit is 1 and a frame byte has already been received this indicates the following bits should contain a data byte or checksum byte depending on the position after the frame bit The value of the parity bit is then calculated including the frame bit and bits 0 3 or 4 7 depending on the half cycle indicated by the cycle frame bit If the cycle frame bit is 0 this indicates this frame corresponds to the first half cycle of the transmitted data and contains data frame bits 0 3 If the cycle frame bit is 1 this indicates this frame corresponds to the second half cycle of the transmitted data and contains data frame bits 4 7 The dead time allows time for the slave to process the current data transmitted as well as allowing the master and the slave to avoid transmitting during the peaks of the AC line At 60 Hz the time of a half cycle is 8 33 ms Providing 2 ms of dead time leaves 6 33 ms to transmit 7 bits resulting in a data rate of 1105 bit s Fig 9 Bit level frame format All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manu
59. the transmit timing for the master transmitter 12C c This contains the driver code for the I2C peripheral on the LPC 1114 The I C interface is used by the slave to communicate with the PCA9632 I C bus to PWM LED driver The application specific code is contained in the I2C Messages c module described in Section 9 2 10 12C Messages c This module contains the functions that interpret the incoming commands and channel assignments and sends corresponding 12C messages to the PCA9632 The PCA9632 is initialized in the Group Dim Mode where a 190 Hz fixed frequency Group signal is superimposed with the 6 25 kHz Individual brightness control signals PWMO PWM1 PWM2 and PWM3 The Select function on the master sets the outgoing channel number in the PLM Master transmit frame This channel number is read by the slave to determine which register on the PCA9632 is addressed when it sends out IC commands The corresponding registers on the PCA9632 and a short description are shown in Table 6 Table 6 PCA9632 corresponding registers Register Range of values Description GRPPWM 0 to 15 this is used as a global brightness control allowing the LED outputs to be dimmed with the same value PWMO 0 to 63 Individual Brightness control for PWMO output PWM1 0 to 63 Individual Brightness control for PWM1 output PWM2 0 to 63 Individual Brightness control for PWM2 output PWM3 0 to 63 Individual Brightness control for PWMS output This mod
60. tion start bit UART style synchronization Troubleshooting start bit UART style synchronization Appendix A Programming instructions RS 232 interface 00055 SW programming interface Appendix B TDA5051A lighting demo board schematic Abbreviations lll References lu ie sar nn Legal information LL Definitions 0 cece eee Disclalmers iss em eee Trademarks llle GornterilsS 5s donas Rak e eae ca odes TDA5051A lighting master slave demo board OM13314 24 24 24 24 24 25 25 25 25 25 26 26 27 27 28 29 29 29 30 30 31 32 32 33 33 37 39 40 40 41 41 41 41 42 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP B V 2013 All rights reserved For more information please visit http Avww nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 18 December 2013 Document identifier UM10495
61. ve demo board OM13314 START FRAME BIT BIT BIT BIT BIT BIT BIT BIT PARITY STOP BIT BIT 0 1 2 3 4 5 6 f BIT BIT 002aag479 The Start bit is always LOW This is used as synchronization as the stop bit and any idle time after the stop bit are defined to be HIGH As a result there is always a HIGH to LOW transition at the beginning of a bit frame to synchronize the reception of the rest of the bits in the bit frame This means the master transmit and slave receive baud rates must be set equal to be able to sample the received signal at the correct times In addition to using the HIGH to LOW transition to synchronize the receive sampling the start bit is also sampled half a bit period after the HIGH to LOW transition This is to verify a valid start condition exists If the frame bit is O it indicates the following bits should contain a valid frame byte flagging the beginning of a message frame When the Frame Bit is 1 the bits 0 7 in the field should contain a valid frame byte The value of the parity bit is then calculated including the frame bit and bits 0 7 If the frame bit is 1 it indicates the following bits should contain a data byte or checksum byte depending on its position after the frame bit The value of the parity bit is then calculated including bits 0 7 The Stop bit is always HIGH providing time for the slave to process the current data transmitted and to provide at least 1 bit period of idle state t
62. xternal switches 5 v Sv2 GND gt S 2 Ed mini JTAG SWD connector 9 R JTAG TMS SWDIO 1 2 100kQ 3 4 JTAG TCLK SWCLK RT 5 E 10 kQ T H 9 O JTAG RESET Y JTAG GND top side 019aac665 9neuieuos pjeoq ouiep Dunubi vrcosval a xipueddy zi VLEELINO pJeoq ouiop eAe s 1ejseui Huny l VLSOSVGL S670 LINN SJOJONPUODIWIIS dXN NXP Semiconductors UM10495 13 Abbreviations TDA5051A lighting master slave demo board OM13314 14 References Table 7 Abbreviations Acronym Description ADC Analog to Digital Converter AGC Automatic Gain Control ASK Amplitude Shift Keying CL Current Limiting resistor DAC Digital to Analog Converter I2C bus Inter Integrated Circuit bus VO Input Output IDE Integrated Development Environment LED Light Emitting Diode NVIC Nested Vectored Interrupt Controller PLM Power Line Modem PWM Pulse Width Modulation ROM Read Only Memory SSL Solid State Lighting SWD Serial Wire Debug UART Universal Asynchronous Receiver Transmitter UM10495 1 PCA9632 4 bit Fm I2C bus low power LED driver NXP Semiconductors Product data sheet www nxp com documents data_sheet PCA9632 pdf All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved User manual Rev 3 18 December 2013 40 of 43 NXP Semiconductors UM10495 TDA5051A lighting master slave demo board OM13314 15 Legal

UM10495 - NXP Semiconductors

Contents

Download Pdf Manuals

Related Search

Related Contents