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RealView Compilation Tools Compiler Reference Guide

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2. Constant Meaning Value FLT RADIX Base radix of the ARM floating point number representation 2 FLT ROUNDS Rounding mode for floating point numbers nearest 1 FLT DIG Decimal digits of precision for float 6 DBL DIG Decimal digits of precision for double 15 LDBL DIG Decimal digits of precision for long double 15 FLT MANT DIG Binary digits of precision for type float 24 DBL MANT DIG Binary digits of precision for type double 53 LDBL MANT DIG Binary digits of precision for type long double 53 FLT EPSILON Smallest positive value of x that 1 0 x 1 0 for type float 1 19209290e 7F DBL_EPSILON Smallest positive value of x that 1 0 x 1 0 for type double 2 2204460492503131e 16 LDBL EPSILON Smallest positive value of x that 1 0 x 1 0 for type long 2 2204460492503131e 16L double Note e When a floating point number is converted to a shorter floating point number it is rounded to the nearest representable number Floating point arithmetic conforms to IEEE 754 D 6 Copyright O 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Appendix E Using NEON Support This appendix describes NEON intrinsics support in this release of the RealView Compilation Tools RVCT This appendix contains the following sections Introduction on page E 2 Vector data types on page E 3 Intrinsics on page E 4 ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved Non Conf
3. __breakpoint __enable_irq __return_address _ builtin_c1z __fabs __ror __builtin_constant_p __fabsf __schedule_barrier __builtin_expect __force_stores __semihost _ builtin_frame_address __Idrex Sev builtin return address ldrt sqrt builtin popcount memory changed sqrtf __cdp __nop __ssat __clrex __pld __strex __c1z pli __strt __current_pc __qadd __swp __current_sp __qdb1 __usat disable fiq __qsub __wfe __disable_irq __rbit __wfi __enable_fiq __rev __yield 4 7 1 __breakpoint ARM DUI 0348A This intrinsic inserts a BKPT instruction into the instruction stream generated by the compiler It enables you to include a breakpoint instruction in your C or C code Syntax void breakpoint int val Copyright O 2007 2010 ARM Limited All rights reserved Non Confidential 4 63 Compiler specific Features Where val is a compile time constant integer whose range is 0 65535 if you are compiling source as ARM code 0 255 if you are compiling source as Thumb code Errors The compiler does not recognize the __breakpoint intrinsic when compiling for a target that does not support the BKPT instruction The compiler generates either a warning or an error in this case The undefined instruction trap is taken if a BKPT instruction is executed on an architecture that does not support it Example void func void __breakpoint xFQ 2C See also e BKPT on page 4 1
4. 4 1 10 irq The __irq keyword enables a C or C function to be used as an interrupt routine __irq is a function qualifier It affects the type of the function Restrictions All corrupted registers except floating point registers are preserved not only those that are normally preserved under the AAPCS The default AAPCS mode must be used The function exits by setting the program counter to 1r 4 and the CPSR to the value in SPSR No arguments or return values can be used with __irq functions Note When compiling for Thumb using the thumb option or pragma thumb any functions specified as __irq are compiled for ARM See also thumb on page 2 86 pragma thumb on page 4 62 Chapter 6 Handling Processor Exceptions in the Developer Guide 4 10 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 4 1 11 __packed ARM DUI 0348A Compiler specific Features The __packed qualifier sets the alignment of any valid type to 1 This means that there is no padding inserted to align the packed object objects of packed type are read or written using unaligned accesses The __packed qualifier applies to all members of a structure or union when it is declared using __packed There is no padding between members or at the end of the structure All substructures of a packed structure must be declared using packed Integral subfields of an unpacked structure can be packed individually
5. NPADDL U8 00 00 vpaddl ul6 uintl6x4 t a VPADDL U16 00 00 vpaddl u32 uint32x2 t a VPADDL U32 d0 d0 vpaddlq s8 int8x16 t a NPADDL S8 q0 q0 vpaddlq si6 intl16x8 t a VPADDL S16 q0 q0 vpaddlq s32 int32x4 t a VPADDL S32 q0 q0 vpaddlq u8 uint8x16 t a VPADDL U8 q0 q0 vpaddlq ul6 uintl6x8 t a VPADDL U16 q0 q0 vpaddlq u32 uint32x4 t a VPADDL U32 q0 q0 Long pairwise add and accumulate intl6x4 t int32x2 t int64x1_t uint16x4_t uint32x2 t uint64x1_t int16x8_t int32x4 t int64x2 t uint16x8 t uint32x4 t uint64x2 t E 3 8 Folding maximum vpadal s8 intl6x4 t a int8x8 t b vpadal s16 int32x2 t a intl6x4 t b vpadal s32 int64x1 t a int32x2 t b vpadal u8 uintl6x4 t a uint8x8 t b vpadal ul6 uint32x2 t a uintl6x4 t b vpadal u32 uint64x1 t a uint32x2_t b vpadalq_s8 int16x8_t a int8x16 t b vpadalq s16 int32x4 t a intl16x8 t b vpadalq s32 int64x2 t a int32x4 t b vpadalq_u8 uint16x8_t a uint8x16 t b NPADAL NPADAL NPADAL NPADAL NPADAL NPADAL NPADAL NPADAL NPADAL NPADAL vpadalq ul6 uint32x4 t a uintl16x8 t b VPADAL vpadalq u32 uint64x2 t a uint32x4 t b VPADAL vpmax takes maximum of adjacent pairs int8x8 t intl6x4 t int32x2 t uint8x8 t uintl6x4 t uint32x2 t float32x2 t vpmax f32 float32x2 t a float32x2 t b E 3 9 Folding minimum ARM DUI 0348A vpmax_s8 int8x8_t a int8x8_t b vpm
6. c90 on page 2 13 c99 on page 2 13 cpp on page 2 14 no_ strict on page 2 84 GNU language extensions on page 3 25 Compiler predefines on page 4 103 no guiding decls This option enables or disables the recognition of guiding declarations for template functions in C A guiding declaration is a function declaration that matches an instance of a function template but has no explicit definition because its definition derives from the function template Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 2 1 59 help ARM DUI 0348A Compiler Command line Options If no guiding decls is combined with old specializations a specialization of a non member template function is not recognized It is treated as a definition of an independent function Note The option guiding decls is provided only as a migration aid for legacy source code that does not conform to the C standard Its use is not recommended Mode This option is effective only if the source language is C Default The default 15 no guiding decls Example template class T void f T void f int When regarded as a guiding declaration f int is an instance of the template Otherwise it is an independent function so you must supply a definition See also apcs qualifer qualifier on page 2 4 no_ old_specializations on page 2 68 This o
7. Syntax __svc int svc num return type function name argument list Where Svc num Is the immediate value used in the SVC instruction It is an expression evaluating to an integer in the range 0 to 224 a 24 bit value in an ARM instruction 0 255 an 8 bit value in a 16 bit Thumb instruction Usage This causes function invocations to be compiled inline as an AAPCS compliant operation that behaves similarly to a normal call to a function The value in regs qualifier can be used to specify that a small structure of up to 16 bytes is returned in registers rather than by the usual structure passing mechanism defined in the AAPCS Example __svc 42 void terminate l int procnum terminate 1 returns no results __svc 42 int terminate 2 int procnum terminate 2 returns one result 4 16 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler specific Features typedef struct res type int res 1 int res 2 int res 3 int res 4 res type __svc 42 value in regs res type terminate 3 int procnum terminate 3 returns more than one result Errors When an ARM architecture variant or ARM architecture based processor that does not support an SVC instruction is specified on the command line using the cpu option the compiler generates an error See also cpu name on page 2 15 value in regs on page 4 19 SVC on page 4 130 in the
8. VMLS 132 q0 00 000 float32x4 t vmlsq lane f32 float32x4 t a float32x4 t b float32x2 t v constrange 0 1 int 1 NMLS F32 q0 00 000 Vector widening multiply subtract with scalar int32xX4 t vmlsl lane s16 int32x4 t a intl6x4 t b intl6x4 t v __constrange 0 3 int 1 NMLSL S16 q0 d 000 vml1sl lane s32 int64x2 t a int32x2 t b int32x2 t v __constrange 1 int 1 NMLSL S32 q0 d 000 vml1s1 lane ul6 uint32x4 t a uintl6x4 t b uintl6x4 t v __constrange 0 3 int 1 NMLSL U16 q0 d 000 vml1sl lane u32 uint64x2 t a uint32x2 t b uint32x2 t v constrange 0 1 int 1 NMLSL U32 q0 d 000 int64x2_t uint32x4_t uint64x2_t Vector widening saturating doubling multiply subtract with scalar int32x4_t vqdmlsl lane s16 int32x4 t a intl6x4 t b intl6x4 t v __constrange 3 int 1 VQDMLSL S16 q0 d 00 0 vqdmlsl lane s32 int64x2 t a int32x2 t b int32x2 t v constrange 0 1 int 1 VQDMLSL S32 q0 00 00 0 int64x2 t Vector multiply by scalar int16x4_t int32x2 t float32x2 t uintl6x4 t uint32x2 t vmul n sl16 intl6x4 t a intl6 t b vmul n s32 int32x2 t a int32 t b vmul n 32 float32x2 t a float32 t b vmul n ul6 uintl6x4 t a uintl16 t b vmul n u32 uint32x2 t a uint32 t b NMUL 116 00 00 00 0 NMUL 132 00 00 00 0 NMUL F32 00 00 00 0 NMUL 116 00 00 00 0 NMUL 132 00 00 00 0 E 48 Copyright 2007 2010
9. assume f is not present in final link typedef void FP void FP g return f g returns non NULL if See also compiled and linked ropi Chapter 7 Using the ARM Librarian in the Linker Guide for more information on library searching Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 4 1 20 writeonly ARM DUI 0348A Compiler specific Features The __writeonly type qualifier indicates that a data object cannot be read from In the C and C type system it behaves as a cv qualifier like const or volatile Its specific effect is that an lvalue with __writeonly type cannot be converted to an rvalue Assignment to a __writeonly bitfield is not allowed if the assignment is implemented as read modify write This is implementation dependent Example void foo writeonly int ptr ptr 0 allowed printf ptr value d n ptr error Copyright 2007 2010 ARM Limited All rights reserved 4 23 Non Confidential Compiler specific Features 4 2 declspec attributes The __declspec keyword enables you to specify special attributes of objects and functions For example you can use the __declspec keyword to declare imported or exported functions and variables or to declare Thread Local Storage TLS objects The __declspec keyword must prefix the declaration specification For example __declspec noreturn void overflow void __declspec thread
10. unsigned char cannot be assigned to an entity of type Assignment of a string constant to a pointer to any kind of character is permitted without a warning Assignment of pointer types is permitted in cases where the destination type has added type qualifiers that are not at the top level for example assigning int to const int Comparisons and pointer difference of such pairs of pointer types are also permitted A warning is issued for example Copyright O 2007 2010 ARM Limited All rights reserved 3 11 Non Confidential Language Extensions 42 D operand types are incompatible const int and int In operations on pointers a pointer to void is always implicitly converted to another type if necessary Also a null pointer constant is always implicitly converted to a null pointer of the right type if necessary In ISO C some operators permit these and others do not Pointers to different function types can be assigned or compared for equality or inequality without an explicit type cast A warning or error is issued for example 42 D operand types are incompatible int char and unsigned int char This extension is prohibited in C mode A pointer to void can be implicitly converted to or from a pointer to a function type In an initializer a pointer constant value can be cast to an integral type if the integral type is big enough to contain it A n
11. C and C implementation details on page 5 2 C implementation details on page 5 13 ARM DUI 0348A Copyright 2007 2010 ARM Limited All rights reserved Non Confidential 5 1 C and C Implementation Details 5 1 5 1 1 5 2 C and C implementation details This section describes language implementation details common to both C and C Character sets and identifiers The following points apply to the character sets and identifiers expected by the compiler Uppercase and lowercase characters are distinct in all internal and external identifiers An identifier can also contain a dollar character unless the strict compiler option is specified To permit dollar signs in identifiers with the strict option also use the dollar command line option Calling setlocale LC CTYPE IS08859 1 makes the isupper and islower functions behave as expected over the full 8 bit Latin 1 alphabet rather than over the 7 bit ASCII subset The locale must be selected at link time See Tailoring locale and CTYPE using C macros on page 2 60 in the Libraries Guide Source files are compiled according to the currently selected locale You might have to select a different locale with the locale command line option if the source file contains non ASCII characters See Invoking the ARM compiler on page 2 2 in the Compiler User Guide for more information The ARM compiler supports multibyte character sets such as Unicode
12. Non Confidential NOT NOT VOT NOT NOT VOT VOT NOT NOT VOT NOT VOT NOT NOT NOT NOT 532 U32 532 U32 532 U32 532 U32 F32 F32 F32 F32 F32 F32 F32 F32 116 d0 q0 132 d0 q0 164 d0 q0 116 d0 q0 132 d0 q0 164 d0 q0 S8 q0 d0 S16 q0 d0 32 q0 d0 Copyright O 2007 2010 ARM Limited All rights reserved F32 F32 F32 F32 F32 F32 F32 F32 32 U32 32 U32 32 U32 32 U32 Using NEON Support 00 00 q 00 00 00 q q 00 00 q q 00 00 q q 00 00 q 00 00 00 q q 00 00 q q 00 00 q q 32 32 32 32 32 32 32 32 E 45 Using NEON Support uint16x8 t vmovl u8 uint8x8 t a NMOVL U8 00 00 uint32x4 t vmovl ul6 uintl6x4 t a VMOVL U16 q0 d0 uint64x2 t vmovl u32 uint32x2 t a VMOVL U32 q0 d0 Vector saturating narrow integer int8x8 t vamovn_s16 int16x8_t a VQMOVN S16 d0 q0 intl6x4 t vqmovn s32 int32x4 t a VQMOVN S32 d0 q0 int32x2 t vqmovn s64 int64x2 t a VQMOVN S64 d0 q0 uint8x8 t vqmovn ul6 uintl6x8 t a VQMOVN U16 d0 q0 uintl6x4 t vqmovn u32 uint32x4 t a VQMOVN U32 d0 q0 uint32x2 t vqmovn u64 uint64x2 t a VQMOVN U64 d0 q0 Vector saturating narrow integer signed gt unsigned uint8x8_t vamovun_s16 int16x8_t a VQMOVUN S16 d0 q0 uintl6x4 t vqmovun s32 int32x4 t a
13. PROC MOV r0 0xff LDRBT r1 r0 20 Copyright O 2007 2010 ARM Limited All rights reserved 4 77 Non Confidential Compiler specific Features 4 7 22 4 7 23 4 78 MOV r2 0x100 LDRBT r0 r2 20 ORR r0 r1 rQ LSL 8 BX Ir ENDP See also e thumb on page 2 86 LDR and STR User mode on page 4 18 in the Assembler Guide memory changed nop This intrinsic causes all variables that are visible outside the current function such as variables that have pointers to them passed into or out of the function to be written back to memory if they have been changed and then to be read back from memory This intrinsic also acts as a scheduling barrier Syntax void __memory_changed void See also __force_stores on page 4 74 __schedule_barrier on page 4 85 This intrinsic inserts a NOP instruction or an equivalent code sequence into the instruction stream generated by the compiler One NOP instruction is generated for each __nop intrinsic in the source The compiler does not optimize away the NOP instructions except for normal unreachable code elimination The __nop intrinsic also acts as a barrier for instruction scheduling in the compiler That is instructions are not moved from one side of the NOP to the other as a result of optimization Note You can use the __schedule_barrier intrinsic to insert a scheduling barrier without generating a NOP instruction Copyright 2007 2010 ARM Limited
14. The default is pch messages See also create_pch filename on page 2 18 pch on page 2 70 pch_dir dir on page 2 71 no pch verbose e use_pch filename on page 2 89 pragma hdrstop on page 4 55 pragma no_pch on page 4 57 Precompiled header files on page 2 16 in the Compiler User Guide no_ pch_verbose This option enables or disables the display of messages giving reasons why a file cannot be precompiled In automatic PCH mode this option ensures that for each PCH file that cannot be used for the current compilation a message is displayed giving the reason why the file cannot be used Default The default is no_pch_verbose See also create_pch filename on page 2 18 pch on page 2 70 pch_dir dir on page 2 71 no_ pch_messages use_pch filename on page 2 89 pragma hdrstop on page 4 55 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options pragma no_pch on page 4 57 Precompiled header files on page 2 16 in the Compiler User Guide 2 1 96 pending_instantiations n This option specifies the maximum number of concurrent instantiations of a template in C Syntax pending_instantiations n Where n is the maximum number of concurrent instantiations permitted If nis zero there is no limit Mode This option is effective only if the source language is C Defa
15. Using NEON Support constrange 0 0 int constrange 0 7 int constrange 0 3 int Using NEON Support void void void void void void void void void void void void void void void void void void void void void void void void E 28 NLD1 8 100 1 r0 poly16x4_t vidil dup p16 transfersize 1 polyl6 t const ptr VLD1 16 d0 rd vstlq u8 transfersize 16 uint8 t ptr uint8x16 t val VST1 8 100 d1 r0 vstlq ul6 transfersize 8 uint16 t ptr uintl6x8 t val NST1 16 100 d1 r0 vstlq u32 transfersize 4 uint32 t ptr uint32x4 t val NST1 32 100 d1 r0 vstlq u64 transfersize 2 uint64 t ptr uint64x2 t val NST1 64 100 d1 r0 vstlq s8 transfersize 16 int8 t ptr int8x16 t val VST1 8 100 d1 r0 vstlq s16 transfersize 8 int16 t ptr int16x8_t val NST1 16 100 01 vstlq s32 transfersize 4 int32 t ptr int32x4 t val NST1 32 100 d1 vstlq s64 transfersize 2 int64 t ptr int64x2 t val NST1 64 100 01 vstiq f32 transfersize 4 float32 t ptr float32x4 t val NST1 32 d0 01 vstlq p8 transfersize 16 poly8_t ptr poly8x16 t val r0 r0 r0 r0 VST1 8 100 d1 r0 vstlq_p16 __transfersize 8 poly16_t ptr poly16x8 t val VST1 16 100 d1 r0 vstl u8 transfersize 8 uint8 t ptr uint8x8
16. VORR d0 d0 d0 int32x2 t vorr s32 int32x2 t a int32x2 t b VORR d0 d0 d0 int64xl t vorr s64 int64x1l t a int64x1l t b VORR d0 d0 d0 uint8x8 t vorr u8 uint8x8 t a uint8x8 t b NORR d0 d0 d0 uintl6x4 t vorr ul6 uintl6x4 t a uintl6x4 t b VORR 00 00 0 uint32x2 t vorr u32 uint32x2 t a uint32x2 t b VORR dQ dQ d0 uint64x1l t vorr u64 uint64x1l t a uint64x1_t b VORR dQ dQ d0 int8x16 t vorrq s8 int8x16 t a int8x16 t b NOR q0 q0 q0 intl6x8 t vorrq sl6 intl6x8 t a intl6x8 t b VORR q0 q0 q0 int32x4 t vorrq s32 int32x4 t a int32x4 t b VORR q0 q0 q0 int64x2 t vorrq s64 int64x2 t a int64x2 t b VORR q0 q0 q0 uint8x16 t vorrq u8 uint8x16 t a uint8x16 t b VORR q0 q0 q0 uintl6x8 t vorrq ul6 uintl6x8 t a uintl6x8 t b VORR q0 q0 q0 uint32x4 t vorrq u32 uint32x4 t a uint32x4 t b VORR q0 q0 q0 uint64x2 t vorrq u64 uint64x2 t a uint64x2 t b VORR q0 q0 q0 ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved E 55 Non Confidential Using NEON Support E 56 Bitwise exclusive or EOR or XOR int8x8 t intl6x4_t int32x2 t int64x1l t uint8x8 t uintl6x4 t uint32x2 t uint64x1_t int8x16_t int16x8_t int32x4 t int64x2 t uint8x16 t uintl6x8 t uint32x4 t uint64x2_t Bit Clear int8x8 t int16x4_t int32x2_t int64x1_t uint8x8_t uint16x4_t uint32x2_t uint64x1_t int8x16_t int16x8_t int32x4 t int64x2 t uint8x16 t uintl6x8 t uint32x4 t uint64x2 t
17. alias on page 4 40 4 3 2 attribute always inline 4 30 This function attribute indicates that a function must be inlined Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler specific Features The compiler attempts to inline the function regardless of the characteristics of the function However the compiler does not inline a function if doing so causes problems For example a recursive function is inlined into itself only once Note This function attribute is a GNU compiler extension that is supported by the ARM compiler It has the keyword equivalent __forceinline Example static int max int x in y attribute always inline 1 return x y x y always inline if possible See also forceinline on page 2 39 __forceinline on page 4 6 4 3 3 attribute const ARM DUI 0348A Many functions examine only the arguments passed to them and have no effects except for the return value This is a much stricter class than attribute pure because a function is not permitted to read global memory If a function is known to operate only on its arguments then it can be subject to common sub expression elimination and loop optimizations Note This function attribute is a GNU compiler extension that is supported by the ARM compiler It has the keyword equivalent pure Example int Function Attributes const O int b
18. constrange 0 0 int lane OV d0 r0 rO vec constrange 0 1 int lane OV d0 r0 r0 t vec constrange 0 1 int lane MOV 00 0 poly8x16 t vsetq lane p8 poly8 t value E y poly16x8 t vsetq lane pl6 polyl16 t value float32x4 t vsetq lane f32 float32 t value 2 int64xl t Xvset lane s64 int64 t value nerd uint64xl t vset lane u64 uint64 t value int64x2 t vsetq lane s64 int64 t value na uint64x2 t vsetq lane u64 uint64 t value NAE N E 3 18 Initialize a vector from bit pattern These intrinsics create a vector from a literal bit pattern int8x8 t vcreate s8 uint64 t a VMOV 00 0 intl6x4_t vcreate s16 uint64 t a VMOV d0 r0 r0 int32x2 t vcreate s32 uint64 t a VMOV d0 r0 r0 float32x2 t vcreate f32 uint64 t a VMOV d0 r0 r0 uint8x8 t vcreate_u8 uint64_t a VMOV d0 r0 r0 uint16x4_t vcreate ul6 uint64 t a VMOV d0 r0 r0 uint32x2 t vcreate u32 uint64 t a VMOV d0 r0 r0 uint64xl t vcreate u64 uint64 t a VMOV d0 r0 r0 poly8x8 t vcreate p8 uint64 t a VMOV d0 r0 r0 00 16 4 t vcreate_pl6 uint64_t a VMOV d0 r0 r0 int64xl t vcreate s64 uint64 t a VMOV d0 r0 r0 E 3 19 Setall lanes to same value E 42 These intrinsics set all lanes to the same value Set all lanes to the same value uint8x8_t vdup n u8 uint8 t value NDUP 8 d0 r0 uintl6x4 t vdup_n_u16 uint16_t value NDUP 16 d0 r0 uint32x2 t vdup n u32 uint32
19. in foo code part of region return x 1 pragma arm section code See also attribute section on page 4 34 Chapter 5 Using Scatter loading Description Files in the Linker Guide 4 6 4 pragma diag default tag tag This pragma returns the severity of the diagnostic messages that have the specified tags to the severities that were in effect before any pragmas were issued ARM DUI 0348A Copyright 2007 2010 ARM Limited All rights reserved 4 51 Non Confidential Compiler specific Features Syntax pragma diag default tag tag Where tag tag is a comma separated list of diagnostic message numbers specifying the messages whose severities are to be changed At least one diagnostic message number must be specified Example stdio h not included deliberately pragma diag error 223 void hello void printf Hello pragma diag_default 223 void world void printf world n Compiling this code with the option diag_warning 223 generates diagnostic messages to report that the function printf is declared implicitly The effect of pragma diag_default 223 is to return the severity of diagnostic message 223 to Warning severity as specified by the diag_warning command line option See also diag warning tag tag on page 2 30 pragma diag error tag tag pragma diag remark tag tag on page 4 53 pragma diag suppress
20. no pid is an alias for no rwpi no fpic Enables or disables the generation of read only position independent code where relative address references are independent of the location where your program is loaded Note You can alternatively specify multiple qualifiers For example apcs nointerwork noropi norwpi is equivalent to apcs nointerwork apcs noropi norwpi Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options Default If you do not specify an apcs option the compiler assumes apcs nointerwork noropi norwpi Usage no interwork By default code is generated without interworking support that is nointerwork unless you specify a cpu option that corresponds to architecture ARMv5T or later with interworking support that is interwork for ARMv5T or later This is because ARMVST or later provides direct interworking support no ropi If you select the ropi qualifier to generate ROPI code the compiler addresses read only code and data PC relative sets the Position Independent PI attribute on read only output sections Note apcs ropi is not supported when compiling C no rwpi If you select the rwpi qualifier to generate RWPI code the compiler addresses writable data using offsets from the static base register sb This means that the base address of the RW data region
21. return address on page 4 83 Legacy inline assembler that accesses sp lr or pc on page 6 27 in the Compiler User Guide 4 7 13 disable fiq ARM DUI 0348A This intrinsic disables FIQ interrupts Syntax int disable fiq void Note On ARMv7 and ARMv7 M the disable fig intrinsic has prototype void disable fiq void Return value fiq returns the value the FIQ interrupt mask has in the PSR prior to the disabling of FIQ interrupts Restrictions The disable 110 intrinsic can only be executed in privileged modes that is in non user modes In User mode this intrinsic does not change the interrupt flags in the CPSR Example void foo void int was masked __disable_fiq Je 8 Copyright 2007 2010 ARM Limited All rights reserved 4 71 Non Confidential Compiler specific Features if Iwas masked __enable_fiq See also e enable fiq on page 4 73 4 7 14 disable irq This intrinsic disables IRQ interrupts Syntax int disable irq void Note On ARMv7 and ARMv7 M the disable irq intrinsic has prototype void disable irq void Return value irq returns the value the IRQ interrupt mask has in the PSR prior to the disabling of IRQ interrupts Example void foo void int was masked disable irq x if Iwas masked enable irq Restrictions The disable irq intrinsic can only be executed in privileged mod
22. return f See also attribute const on page 4 31 pure on page 4 15 in the Compiler User Guide Placing ARM function qualifiers on page 4 17 in the Compiler User Guide 41 13 __smc The __smc keyword declares an SMC Secure Monitor Call function A call to the SMC function inserts an SMC instruction into the instruction stream generated by the compiler at the point of function invocation Note The SMC instruction replaces the SMI instruction used in previous versions of the ARM assembly language __smc is a function qualifier It affects the type of a function Syntax __smc int smc num return type function name argument list 4 14 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 4 1 14 __softfp ARM DUI 0348A Compiler specific Features Where smc_num Is a 16 bit immediate value used in the SMC instruction The value of smc_numis ignored by the ARM processor but can be used by the SMC exception handler to determine what service is being requested Restrictions The SMC instruction is available for selected ARM architecture based processors if they have the Security Extensions See SMC on page 4 137 in the Assembler Guide for more information The compiler generates an error if you compile source code containing the __smc keyword for an architecture that does not support the SMC instruction Example __smc 5 void mycall void d
23. 2 1 65 2 48 Jdir dir on page 2 51 Implicit inclusion on page 5 15 The search path on page 2 14 in the Compiler User Guide no_ implicit typename This option controls the implicit determination from context whether a template parameter dependent name is a type or nontype in C Note The option implicit_typename is provided only as a migration aid for legacy source code that does not conform to the C standard Its use is not recommended Mode This option is effective only if the source language is C Default The default is no_implicit_typename Note The implicit_typename option has no effect unless you also specify no_parse_templates See also no_ dep_name on page 2 22 no parse templates on page 2 70 Template instantiation on page 5 15 info totals This option instructs the compiler to give totals of the object code and data size for each object file The compiler returns the same totals as fromelf returns when fromelf z is used in a similar format The totals include embedded assembler sizes when embedded assembly exists in the source code Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options Example Code inc data RO Data RW Data ZI Data Debug File Name 3308 1556 0 44 10200 8402 dhry 1 0 Code inc data RO Data RW Data ZI Data Debug File Name 416 28 0 0 0 7722 dhry_2
24. Bitfield containers in packed structures have an alignment of 1 Therefore the maximum bit padding for a bitfield in a packed structure is 7 bits For an unpacked structure the maximum padding is 8 sizeof container type 1 bits Copyright O 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential C and C Implementation Details 5 2 C implementation details This section describes language implementation details specific to C 5 2 1 Using the operator new function In accordance with the ISO C Standard the operator new std size t throws an exception when memory allocation fails rather than raising a signal If the exception is not caught std terminate is called The compiler option force new nothrow turns all new calls in a compilation into calls to operator new std size t std nothrow_t amp or operator new std size t std nothrow t amp However this does not affect operator new calls in libraries nor calls to any class specific operator new See no force new nothrow on page 2 38 for more information Legacy support In RVCT v2 0 when the operator new function ran out of memory it raised the signal SIGOUTOFHEAP instead of throwing a C exception See SO C library implementation definition on page 2 109 in the Libraries Guide In the current release it is possible to install a new handler to raise a signal and so restore the RVCT v2 0 behavior Note Do
25. Compiler specific Features Assembler labels The __asm keyword can be used to specify an assembler label for a C symbol For example int count asm count v1 export count vl not count See Assembler labels on page 3 21 for more information Named register variables The asm keyword can be used to declare a named register variable For example register int foo __asm rQ See Named register variables on page 4 101 for more information See also asm keyword on page 3 25 4 1 5 __forceinline 4 6 The __forceinline keyword forces the compiler to compile a C or C function inline The semantics of __forceinline are exactly the same as those of the C inline keyword The compiler attempts to inline a function qualified as __forceinline regardless of its characteristics However the compiler does not inline a function if doing so causes problems For example a recursive function is inlined into itself only once __forceinline is a storage class qualifier It does not affect the type of a function Note This keyword has the function attribute equivalent __attribute__ always_inline Example __forceinline static int max int x in y return x gt y x y always inline if possible See also forceinline on page 2 39 attribute always inline on page 4 30 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 4 1 6 glob
26. Compiler specific Features unsigned int __uhasx unsigned int unsigned int unsigned int __uhsax unsigned int unsigned int unsigned int __uhsubl6 unsigned int unsigned int unsigned int __uhsub8 unsigned int unsigned int unsigned int ugadd16 unsigned int unsigned int unsigned int __ugadd8 unsigned int unsigned int unsigned int __ugasx unsigned int unsigned int unsigned int __uqsax unsigned int unsigned int unsigned int __uqsubl6 unsigned int unsigned int unsigned int __uqsub8 unsigned int unsigned int unsigned int __usad8 unsigned int unsigned int unsigned int __usada8 unsigned int unsigned int unsigned int unsigned int __usax unsigned int unsigned int unsigned int __usatl6 unsigned int unsigned int unsigned int __usub16 unsigned int unsigned int unsigned int __usub8 unsigned int unsigned int unsigned int __uxtabl6 unsigned int unsigned int unsigned int __uxtb16 unsigned int unsigned int See also Named register variables on page 4 101 Registers on page 2 6 in the Assembler Guide SEL on page 4 62 in the Assembler Guide Chapter 5 NEON and VFP Programming in the Assembler Guide 4 7 47 ETSI basic operations RVCT supports for the original ETSI family of basic operations described in the ETSI G 729 recommendation Coding of speech at 8 kbit s using conjugate structure algebraic code excited linear prediction CS ACELP To make use of the ETSI basic operations in your own code include the stan
27. Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options Include files on page 2 13 in the Compiler User Guide 2 1 62 no implicit include This option controls the implicit inclusion of source files as a method of finding definitions of template entities to be instantiated in C Mode This option is effective only if the source language is C Default The default is implicit include See also no implicit include searches Implicit inclusion on page 5 15 2 1 63 no implicit include searches ARM DUI 0348A This option controls how the compiler searches for implicit include files for templates in C When the option implicit include searches is selected the compiler uses the search path to look for implicit include files based on partial names of the form fi Tename The search path is determined by I J and the RVCT31INC environment variable When the option no implicit include searches is selected the compiler looks for implicit include files based on the full names of files including path names Mode This option is effective only if the source language is C Default The default is no implicit include searches See also Idir dir on page 2 46 no implicit include Copyright O 2007 2010 ARM Limited All rights reserved 2 47 Non Confidential Compiler Command line Options 2 1 64
28. If name is the name of a processor enter it as shown on ARM data sheets for example ARM7TDMI ARM1176JZ S MPCore If name is the name of an architecture it must belong to the list of architectures shown in Table 2 2 Processor and architecture names are not case sensitive Wildcard characters are not accepted Table 2 2 Supported ARM architectures Architecture Description 4 ARMv4 without Thumb 4T ARMv4 with Thumb 5T ARMvS with Thumb and interworking 5TE ARMvS with Thumb interworking DSP multiply and double word instructions 5TEJ ARMvS with Thumb interworking DSP multiply double word instructions and Jazelle extensions ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved 2 15 Non Confidential Compiler Command line Options 2 16 Table 2 2 Supported ARM architectures continued Architecture Description 6 ARMv6 with Thumb interworking DSP multiply double word instructions unaligned and mixed endian support Jazelle and media extensions 6 M ARMv6 micro controller profile with Thumb only plus processor state instructions 6K ARMv6 with SMP extensions 6S M ARMv6 micro controller profile with Thumb only plus processor state instructions and OS extensions 6T2 ARMv6 with Thumb 2 6Z ARMvV6 with Security Extensions 7 ARMv7 with Thumb 2 only and without hardware divide 7 A ARMv7 application profile supporting virtual MMU bas
29. You might have to change this if you have installed your ARM software in a different location Typographical conventions ARM DUI 0348A The following typographical conventions are used in this book monospace Denotes text that can be entered at the keyboard such as commands file and program names and source code monospace Denotes a permitted abbreviation for a command or option The underlined text can be entered instead of the full command or option name monospace italic Denotes arguments to commands and functions where the argument is to be replaced by a specific value monospace bold Denotes language keywords when used outside example code Copyright O 2007 2010 ARM Limited All rights reserved vii Non Confidential Preface Further reading viii italic Highlights important notes introduces special terminology denotes internal cross references and citations bold Highlights interface elements such as menu names Also used for emphasis in descriptive lists where appropriate and for ARM processor signal names This section lists publications from both ARM Limited and third parties that provide additional information on developing code for the ARM family of processors ARM Limited periodically provides updates and corrections to its documentation See http www arm com for current errata sheets and addenda and the ARM Frequently Asked Questions FAQs ARM publications This book contains refer
30. constrange 0 3 int lane constrange 0 1 int lane constrange 0 7 int lane constrange 0 3 int lane constrange 0 1 int lane constrange 0 0 int lane constrange 0 0 int lane constrange 0 0 int lane constrange 0 0 int lane NDUP 32 00 00 0 NDUP 8 00 00 0 NDUP 16 00 00 0 NDUP 32 q0 d0 0 NDUP 8 00 00 0 NDUP 16 q0 d0 0 NMOV 00 00 NMOV 00 00 NMOV q0 q0 NMOV q0 q0 These intrinsics join two 64 bit vectors into a single 128bit vector int8x16 t intl16x8 t int32x4 t int64x2 t float32x4 t uint8x16 t uintl6x8 t uint32x4 t uint64x2 t poly8x16 t poly16x8 t Splitting vectors vcombine s8 int8x8 t low int8x8 t high vcombine s16 intl6x4 t low intl6x4 t high vcombine_s32 int32x2_t low int32x2 t high vcombine s64 int64x1 t low int64x1l t high vcombine f32 float32x2 t low float32x2 t high vcombine u8 uint8x8 t low uint8x8 t high vcombine ul6 uintl6x4 t low uintl6x4 t high vcombine u32 uint32x2 t low uint32x2 t high vcombine u64 uint64x1l t low uint64x1_t high vcombine p8 poly8x8 t low poly8x8 t high vcombine pl6 polyl16x4 t low polyl6x4 t high These intrinsics split a 128 bit vector into 2 component 64 bit vectors int8x8 t intlox4 t int32x2 t int64x1l t float32x2 t uint8x8 t uintl6x4 t uint32x2 t uint64x1_t poly8x8_t po
31. d2 0 d3 0 rd vst4_lane_p16 __transfersize 4 poly16_t ptr polyl6x4x4 t val constrange 0 3 int lane VST4 16 100 0 d1 0 d2 0 d3 0 rd E 3 16 Extract lanes from a vector uint8_ uint16 uint32 int8 t int16_ int32_ poly8_ poly16 E 40 These intrinsics extract a single lane element from a vector t vget lane u8 uint8x8 t vec __ _t vget lane ul6 uintl6x4 t vec _t vget lane u32 uint32x2 t vec vget lane s8 int8x8 t vec __ t vget lane sl6 intl6x4 t vec t vget lane s32 int32x2 t vec t vget lane p8 poly8x8 t vec __ _t vget lane pl6 polyl6x4 t vec constrange 0 7 int lane VMOV U8 r0 00 0 constrange 0 3 int lane VMOV U16 r0 d0 0 constrange 1 int lane VMOV 32 r0 00 0 constrange 0 7 int lane NMOV S8 r0 00 0 constrange 0 3 int lane NMOV S16 r0 00 0 _constrange 1 int lane NMOV 32 r0 00 0 constrange 0 7 int lane NMOV U8 r0 00 0 constrange 0 3 int lane VMOV U16 r0 d0 0 Copyright O 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Using NEON Support float32 t vget lane f32 float32x2 t vec constrange 0 1 int lane VMOV 32 r0 00 0 uint8 t vgetq lane u8 uint8x16 t vec __constrange 15 int lane VMOV U8 r0 dQ Q uintl6 t vgetq lane ul6 uintl16x8 t vec __constrange Q 7 int lane VMOV U16 r0 d0 0 uint32_t vgetq lane u32 uint32x4 t vec __constrange Q 3 int lane VMO
32. enum a w 2147483648 No error enum b x 0x80000000 1 No error enum c y 0x80000001 1 No error enum d z 2147483649 s Error Bit fields can have base types that are enum types or integral types besides int and unsigned int Copyright O 2007 2010 ARM Limited All rights reserved 3 23 Non Confidential Language Extensions See also Pragmas on page 4 49 Structure union enum and bitfield extensions on page 3 23 New features of C99 on page 1 5 in the Compiler User Guide 3 24 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Language Extensions 3 7 GNU language extensions This section describes GNU compiler extensions that are supported by the ARM compiler These extensions are supported only in GNU mode that is when you compile your source code with the gnu option See Language compliance on page 1 6 and gnu on page 2 44 for more information Note Not all GNU compiler extensions are supported for all languages For example extended pointer arithmetic is not supported for C For more information on the use of the GNU extensions see the GNU compiler documentation online at http gcc gnu org For additional reference material on the ARM compiler see also Appendix B Standard C Implementation Definition Appendix C Standard C Implementation Definition Appendix D C and C Compiler Implementati
33. pch_dir dir on page 2 71 no_ pch_messages on page 2 72 no_ pch_verbose on page 2 72 use_pch filename on page 2 89 pragma hdrstop on page 4 55 pragma no pch on page 4 57 Precompiled header files on page 2 16 in the Compiler User Guide 2 1 21 Dname parm 1ist def This option defines the macro name Syntax Dname parm 11st 2def Where name parm list def Is the name of the macro to be defined Is an optional list of comma separated macro parameters By appending a macro parameter list to the macro name you can define function style macros The parameter list must be enclosed in parentheses When specifying multiple parameters do not include spaces between commas and parameter names in the list Note Parentheses might need escaping on UNIX systems Is an optional macro definition If def is omitted the compiler defines name as the value 1 To include characters recognized as tokens on the command line enclose the macro definition in double quotes ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved 2 19 Non Confidential Compiler Command line Options 2 1 22 2 20 Usage Specifying Dname has the same effect as placing the text define name at the head of each source file Restrictions The compiler defines and undefines macros in the following order 1 compiler predefined macros 2 macros defined explicitly using Dnam
34. veor s8 int8x8 t a int8x8 t b veor s16 intl6x4 t a intl16x4 t b veor s32 int32x2 t a int32x2 t b veor s64 int64x1l t a int64x1l t b veor u8 uint8x8 t a uint8x8 t b veor ul6 uintl6x4 t a uintl6x4 t b veor u32 uint32x2 t a uint32x2 t b veor u64 uint64x1l t a uint64x1l t b veorq s8 int8x16 t a int8x16 t b veorq sl6 intl6x8 t a intl16x8 t b veorq s32 int32x4 t a int32x4 t b veorq s64 int64x2 t a int64x2 t b veorq u8 uint8x16 t a uint8x16 t b veorq ul6 uintl6x8 t a uintl6x8 t b veorq u32 uint32x4 t a uint32x4 t b veorg_u64 uint64x2_t a uint64x2 t b vbic s8 int8x8 t a int8x8 t b vbic_s16 int16x4_t a intl16x4 t b vbic s32 int32x2 t a int32x2 t b vbic_s64 int64x1_t a int64x1_t b vbic u8 uint8x8 t a uint8x8 t b vbic ul6 uintl6x4 t a uintl6x4 t b vbic_u32 uint32x2_t a uint32x2 t b vbic_u64 uint64x1_t a uint64x1l t b vbicq s8 int8x16 t a int8x16 t b vbicq_s16 int16x8_t a intl16x8 t b vbicq s32 int32x4 t a int32x4 t b vbicq s64 int64x2 t a int64x2 t b vbicq u8 uint8x16 t a uint8x16 t b vbicq ul6 uintl6x8 t a uintl6x8 t b vbicq u32 uint32x4 t a uint32x4 t b vbicq_u64 uint64x2_t a uint64x2 t b Bitwise OR complement int8x8 t int16x4_t int32x2_t int64x1_t uint8x8_t uint16x4_t uint32x2_t uint64x1_t int8x16_t vorn_s8 int8x8_t a int8x8 t b vorn si6 intl6x4 t a intl16x4 t b vorn s32 int32x2 t a int32x2 t b vorn s64 int6
35. 1 return static_cast lt tricolor gt i void foo void tricolor c red c okay c anachronism Compiling this code with the option anachronisms generates a warning message Compiling this code without the option anachronisms generates an error message Copyright 2007 2010 ARM Limited All rights reserved 2 3 Non Confidential Compiler Command line Options 2 1 4 2 4 See also cpp on page 2 14 no_ strict on page 2 84 strict_warnings on page 2 85 Anachronisms on page 5 14 apcs qualifer qualifier This option controls interworking and position independence when generating code By specifying qualifiers to the apcs command line option you can define the variant of the Procedure Call Standard for the ARM architecture AAPCS used by the compiler Syntax apcs qualifer qualifier Where qualifier qualifier denotes a list of qualifiers There must be at least one qualifier present no spaces separating individual qualifiers in the list Each instance of qualifier must be one of no interwork Generates code with or without ARM Thumb interworking support The default is nointerwork no ropi Enables or disables the generation of Read Only Position Independent ROPI code The default is noropi no pic is an alias for no ropi no rwpi Enables or disables the generation of Read Write Position Independent RWPI code The default is norwpi
36. 3 2 3 2 C99 language features available in C90 3 5 3 3 C99 language features available in C and C90 3 7 3 4 Standard C language extensions 3 10 3 5 Standard C language extensions 3 15 3 6 Standard C and standard C language extensions 3 19 ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved iii Non Confidential Contents Chapter 4 Chapter 5 Appendix A Appendix B Appendix C Appendix D Appendix E 3 7 GNU language extensions 3 25 Compiler specific Features 4 1 Keywords and operators ssssssseeem eene 4 2 4 2 declspec attributes sement eee io aa E te gr dint ch 4 24 4 3 Function attributes dis ror erre rx N P a aE doveva rca 4 29 4 4 Type attributes nn cc Ec t ee 4 37 4 5 Variable attrib tes 1 dei nter rhe rt Dee eerie toti 4 40 4 6 Pragmas 2 nte ba n debct v nea 4 49 4 7 Instruction Intrinsics 4 63 4 8 Compiler predefines e a ia 4 103 C and C Implementation Details 5 1 C and C implementation details seen 5 2 5 2 C implementati
37. All rights reserved ARM DUI 0348A Non Confidential 4 7 24 pld ARM DUI 0348A Compiler specific Features Syntax void __nop void See also __sev on page 4 87 _schedule_barrier on page 4 85 __wfe on page 4 94 __wfi on page 4 94 __ yield on page 4 95 NOP SEV WFE WFI and YIELD on page 4 139 in the Assembler Guide Generic intrinsics on page 3 3 in the Compiler User Guide This intrinsic inserts a data prefetch for example PLD into the instruction stream generated by the compiler It enables you to signal to the memory system from your C or C program that a data load from an address is likely in the near future Syntax void __pld Where denotes any number of pointer or integer arguments specifying addresses of memory to prefetch Restrictions If the target architecture does not support data prefetching this intrinsic has no effect Example extern int datal extern int data2 volatile ints interrupt volatile int 0x8000 volatile ints uart volatile int 0x9000 void get void __pld datal data2 Copyright O 2007 2010 ARM Limited All rights reserved 4 79 Non Confidential Compiler specific Features while interrupt xuart datal trigger uart as soon as interrupt occurs uart 1 data2 See also pli PLD and PLI on page 4 24 in the Assembler Guide 4 7 25 pli This intrinsic inserts an instruction prefetch for example PLI into the
38. Calling __builtin_expect expr c informs the compiler that it is expected that expr c Note This builtin function is a GNU compiler extension that is supported by the ARM compiler Copyright 2007 2010 ARM Limited All rights reserved 4 65 Non Confidential Compiler specific Features Syntax long builtin expect long int expr long int c Where expr is an integral expression c is a compile time constant Return value builtin expect returns the value of expr Example if __builtin_expect i 0 i 100 we do not expect foo to be called because we expect i to be zero 4 7 5 builtin frame address 4 66 This builtin function returns the frame address of the current function The frame address is usually the address of the first word the function pushes on to the stack Note This builtin function is a GNU compiler extension that is supported by the ARM compiler Mode Supported in GNU mode only Syntax void builtin frame address unsigned int val Where val is an unsigned integer evaluating to zero Return value builtin frame address returns the address of the frame of the current function Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler specific Features Example void frame address void static void frm_addr frm addr builtin frame address 0 return the sp return frm addr See al
39. It enables you to store data to memory in your C or C code using an STRT instruction 4 90 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential ARM DUI 0348A Compiler specific Features Syntax void __strt unsigned int val volatile void ptr Where val Is the value to be written to memory ptr Points to the address of the data to be written to in memory To specify the size of the data to be written cast the parameter to an appropriate integral type Table 4 11 Access widths supported by the strt intrinsic Instruction Size of data loaded C cast STRBT unsigned byte char STRHT unsigned halfword short int STRT word int Errors The compiler does not recognize the __strt intrinsic when compiling for a target that does not support the STRT instruction The compiler generates either a warning or an error in this case The __strt intrinsic does not support access either to signed data or to doubleword data The compiler generates an error if you specify an access width that is not supported Example void foo void int loc Oxff __strt x20 volatile char loc Compiling this code produces 100 PROC MOV r0 0xfF MOV r1 0x20 STRBT 1 0 0 BX Ir ENDP Copyright 2007 2010 ARM Limited All rights reserved 4 91 Non Confidential Compiler specific Features See also thumb on page 2 86 LDR and STR User mode on page 4 18
40. The compiler generates either a warning or an error in this case 4 94 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 4 7 45 yield Compiler specific Features See also yield nop on page 4 78 __sev on page 4 87 __wfe on page 4 94 NOP SEV WFE WFYI and YIELD on page 4 139 in the Assembler Guide This intrinsic inserts a YIELD instruction into the instruction stream generated by the compiler Syntax void __yield void Errors The compiler does not recognize the yield intrinsic when compiling for a target that does not support the YIELD instruction The compiler generates either a warning or an error in this case See also nop on page 4 78 sev on page 4 87 _ wfe on page 4 94 Wfi on page 4 94 NOP SEV WFE WFYI and YIELD on page 4 139 in the Assembler Guide 4 7 46 ARMv 6 SIMD intrinsics ARM DUI 0348A The ARM Architecture v6 Instruction Set Architecture adds over sixty SIMD instructions to ARMv6 for the efficient software implementation of high performance media applications The ARM compiler supports intrinsics that map to the ARMv6 SIMD instructions These intrinsics are available when compiling your code for an ARMV6 architecture or processor The following list gives the function prototypes for these intrinsics The function prototypes given in the list describe the primitive or basic forms of the ARMv6 instructions realize
41. The use of apcs ropi is not supported when compiling C Some constructs that are legal C do not work when compiled for apcs ropi For example extern const int ci ro const int sp2 amp ci this static initialization does not work with apcs ropi To enable such static initializations to work compile your code using the lower ropi option For example armcc apcs ropi lower ropi rupi The main restrictions when compiling with rwpi are Some constructs that are legal C do not work when compiled for apcs rwpi For example int i rw int pl amp i this static initialization does not work with apcs rwpi no lower rwpi To enable such static initializations to work compile your code using the lower rwpi option For example armcc apcs rwpi 2 6 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 2 1 5 arm ARM DUI 0348A Compiler Command line Options Note You do not have to specify lower rwpi because this is the default fpic The main restrictions when compiling with fpic are If you use apcs fpic the compiler exports only functions and data marked __declspec dllexport If you use apcs fpic and no hide on the same command line the compiler ignores declspec d11 and exports all extern variables and functions The compiler disables auto inlining for exported functions If you use
42. VCLZ VCLZ VCLZ VCLZ VCLZ I8 d0 d0 I16 d0 d0 132 d0 d0 I8 d0 d0 I16 d0 d0 132 d0 d0 I8 q0 q0 I16 q0 q0 132 q0 q0 I8 q0 q0 I16 q0 q0 132 q0 q0 VCNT 8 d0 d0 VCNT 8 d0 d0 VCNT 8 d0 d0 VCNT 8 q0 q0 8 q0 q0 VCNT 8 q0 q0 float32x2 t vrecpe_f32 float32x2_t a uint32x2 t vrecpe_u32 uint32x2_t a float32x4 t vrecpeq f32 float32x4 t a uint32x4 t vrecpeq u32 uint32x4 t a Reciprocal square root estimate float32x2 t vrsqrte_f32 float32x2_t a uint32x2 t vrsqrte u32 uint32Xx2 t a float32x4 t vrsqrteq f32 float32x4 t a uint32x4 t vrsqrteq u32 uint32x4 t a E 3 29 Logical operations E 54 NRECPE F32 d0 d0 NRECPE U32 00 00 NRECPE F32 q0 q0 NRECPE U32 q0 q0 NRSQRTE F32 d0 d0 NRSQRTE U32 d0 dO NRSQRTE F32 q0 q0 NRSQRTE U32 q0 q0 These intrinsics provide bitwise logical operations Bitwise not int8x8 t int16x4_t int32x2 t vmvn_s8 int8x8_t a vmvn s16 intl6x4 t a vmvn s32 int32x2 t a NM d0 d0 MVN d0 d0 MVN d0 d0 Copyright 2007 2010 ARM Limited All rights reserved Non Confidential ARM DUI 0348A Using NEON Support uint8x8 t wvmvn u8 uint8x8 t a WWN 00 0 uintl6x4 t vmvn ul6 uintl6x4 t a d0 d0 uint32x2 t vmvn u32 uint32x2 t a VMVN d0 d0 poly8x8 t vmvn p8 poly8x8 t a WWN 00 0 int8x16 t s8 int8x16 t a WWN q0 q0 intl6x8 t
43. dependent on the implementation Default The default is unsigned_bitfields Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options Note The AAPCS requirement for bitfields to default to unsigned on ARM is relaxed in version 2 03 of the standard Example typedef int integer struct integer x 1 bf Compiling this code with signed_bitfields causes to be treated as a signed bitfield 2 1 108 un signed_chars This option makes the char type signed or unsigned When char is signed the macro __FEATURE_SIGNED_CHAR is defined by the compiler Note Care must be taken when mixing translation units that have been compiled with and without this option and that share interfaces or data structures The ARM ABI defines char as an unsigned byte and this is the interpretation used by the C libraries supplied with RVCT Default The default is unsigned_chars See also Predefined macros on page 4 103 2 1 109 show_cmdline ARM DUI 0348A This option shows how the command line options are processed The commands are shown in their preferred form and the contents of any via files are expanded Copyright 2007 2010 ARM Limited All rights reserved 2 81 Non Confidential Compiler Command line Options 2 1 110 split ldm 2 82 See also Aopt on page 2 2 Lopt on page 2 52 e via filename on page
44. diag style ide implicitly selects the option brief diagnostics Explicitly selecting no brief diagnostics on the command line overrides the selection of brief diagnostics implied by diag style ide Selecting either the option diag_style arm or the option diag style gnu does not imply any selection of brief diagnostics See also diag_error tag tag on page 2 26 diag remark tag tag on page 2 27 diag suppress tag tag diag warning tag tag on page 2 30 Changing the severity of diagnostic messages on page 5 5 in the Compiler User Guide diag suppress tag tag This option disables diagnostic messages that have the specified tags The diag suppress option behaves analogously to diag errors except that the compiler suppresses the diagnostic messages having the specified tags rather than setting them to have Error severity Note This option has the pragma equivalent fpragma diag suppress Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options Syntax diag suppress tag tag Where tag tag is a comma separated list of diagnostic message numbers specifying the messages to be suppressed See also diag_error tag tag on page 2 26 diag remark tag tag on page 2 27 diag warning tag tag on page 2 30 pragma diag suppress
45. extended initializers when compiling in non strict mode See also no_ strict on page 2 84 strict_warnings on page 2 85 Constant expressions on page 3 10 2 1 50 feedback fi lename ARM DUI 0348A This option enables the efficient elimination of unused functions Syntax feedback fi Jename Where filename is the feedback file created by a previous execution of the ARM linker Usage You can perform multiple compilations using the same feedback file or specify multiple source files in a single compilation The feedback file identifies the source file that contains the unused functions in a comment and is not used by the compiler The compiler places each unused function identified in the feedback file into its own ELF section in the corresponding object file The feedback file contains information about a previous build Because of this The feedback file might be out of date That is a function previously identified as being unused might be used in the current source The linker removes the code for an unused function only if it is not used in the current source Copyright 2007 2010 ARM Limited All rights reserved 2 37 Non Confidential Compiler Command line Options 2 1 51 2 38 Note For this reason linker feedback is a safe optimization but there might be a small impact on code size You have to do a full compile and link at least twice to get the maximum benefit from linker f
46. int b VQSHRUN S32 dQ qQ 16 constrange 1 32 int b VQSHRUN S64 00 00 32 E 22 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential uint8x8 t uintl6x4 t uint32x2 t int8x8 t intl6x4 t int32x2 t uint8x8 t uintl6x4 t uint32x2 t int8x8 t intl6x4 t int32x2 t uint8x8 t uintl6x4 t uint32x2 t int8x8 t intl6x4 t int32x2 t uint8x8 t uintl6x4 t uint32x2 t intl6x8 t int32x4 t int64x2 t uintl6x8 t uint32x4 t uint64x2 t Using NEON Support Vector signed gt unsigned rounding narrowing saturating shift right by constant vqrshrun n s16 int16x8 t a __constrange 1 8 int b vqrshrun n s32 int32x4 t a __constrange 1 16 int b VQRSHRUN S32 00 00 16 vqrshrun n s64 int64x2 t a __constrange 1 32 int b VQRSHRUN S64 00 00 32 VORSHRUN S16 d0 q0 28 Vector narrowing saturating shift right by constant vqshrn n s16 int16x8 t a vqshrn n s32 int32x4 t a vqshrn n s64 int64x2 t a __ vashrn_n_u16 uint16x8_t a vqshrn n u32 uint32x4 t a vqshrn n u64 uint64x2 t a constrange 1 8 int b constrange 1 16 int b constrange 1 32 int b constrange 1 8 int b constrange 1 16 int b constrange 1 32 int b y y y lt y mmm yr c VQSHRN S16 d0 q0 8 VQSHRN S32 d0 q0 16 VQSHRN S64 00 00 32 VQSHRN U16 00 90 8 VQSHRN U32 00 90 16 VQSHRN U64 00 00 32 Vector rounding narrowing
47. int i Table 4 2 summarizes the available __declspec attributes declspec attributes are storage class modifiers They do not affect the type of a function or variable Table 4 2 declspec attributes supported by the compiler and their equivalents declspec attribute non declspec equivalent __declspec d1lexport declspec dllimport s declspec noinline attribute noinline __declspec noreturn __attribute__ noreturn __declspec nothrow z __declspec notshared B __declspec thread 4 2 1 declspec dllexport 4 24 The __declspec d1lexport attribute exports the definition of a symbol through the dynamic symbol table when building DLL libraries Usage When an inline function is marked __declspec d1lexport the function definition might be inlined but an out of line instance of the function is always generated and exported in the same way as for a non inline function See also __declspec dllimport on page 4 25 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler specific Features 4 2 2 declspec dllimport The __declspec d1limport attribute imports a symbol through the dynamic symbol table when building DLL libraries Usage When an inline function is marked declspec dllimport the function definition in this compilation unit might be inlined but is never generated out of line An out of line call
48. int32x4x4 t val constrange 0 3 int lane NST4 32 100 0 d2 0 d4 0 de 0 re vst4q lane f32 transfersize 4 float32 t ptr float32x4x4 t val __constrange 0 3 int lane VST4 32 d0 0 d2 0 d4 0 d6 0 rd vst4q_lane_p16 __transfersize 4 poly16_t ptr polyl6x8x4 t val constrange 0 7 int lane VST4 16 d0 0 d2 0 d4 0 d6 0 rd vst4_lane_u8 __transfersize 4 uint8 t ptr uint8x8x4_t val constrange 0 7 int lane NST4 8 d 0 d1 0 d2 0 d3 0 rd vst4 lane ul6 transfersize 4 uintl6 t ptr uintl6x4x4 t val __constrange 0 3 int lane VST4 16 d0 0 d1 0 d2 0 d3 0 rd vst4_lane_u32 __transfersize 4 uint32 t ptr uint32x2x4 t val __constrange 1 int lane NST4 32 d0 0 d1 0 d2 0 d3 0 rd vst4 lane s8 transfersize 4 int8 t ptr int8x8x4 t val constrange 0 7 int lane VST4 8 d 0 d1 0 d2 0 d3 0 rd vst4 lane s16 transfersize 4 intl6 t ptr intl6x4x4 t val constrange 0 3 int lane NST4 16 100 0 d1 d2 0 d3 r9 vst4 lane s32 transfersize 4 int32 t ptr int32x2x4 t val constrange 0 1 int lane NST4 32 100 0 d1 d2 0 d3 r0 vst4 lane f32 transfersize 4 float32 t ptr float32x2x4 t val __constrange 1 int lane NST4 32 d0 0 d1 0 d2 0 d3 0 rd vst4 lane p8 transfersize 4 poly8 t ptr poly8x8x4 t val constrange 0 7 int lane VST4 8 100 0 d1 0
49. interleave This option interleaves C or C source code line by line as comments within an assembly listing generated using the asm option or S option Usage The action of interleave depends on the combination of options used Table 2 3 Compiling with the interleave option Compiler option Action asm interleave Writes a listing to a file of the disassembly of the compiled source interleaving the source code with the disassembly The link step is also performed unless the c option is used The disassembly is written to a text file whose name defaults to the name of the input file with the filename extension txt S interleave Writes a listing to a file of the disassembly of the compiled source interleaving the source code with the disassembly The disassembly is written to a text file whose name defaults to the name of the input file with the filename extension txt Restrictions You cannot reassemble an assembly listing generated with asm interleave or S interleave Preprocessed source files contain line directives When compiling preprocessed files using asm interleave or S interleave the compiler searches for the original files indicated by any fine directives and uses the correct lines from those files This ensures that compiling a preprocessed file gives exactly the same output and behavior as if the original files were compiled If the compiler cannot find the original f
50. ptr NLD2 16 100 d1 rd uint32x2x2 t 1102 dup u32 transfersize 2 uint32 t const ptr NLD2 32 100 d1 re uint64x1x2_t vld2_dup_u64 __transfersize 2 uint64 t const ptr NLD1 64 100 d1 r0 int8x8x2 t vld2_dup_s8 __transfersize 2 int8 t const ptr NLD2 8 d d1 r0 intl6x4x2 t 102 dup s16 transfersize 2 intl6 t const ptr NLD2 16 100 d1 r0 int32x2x2_t vld2_dup_s32 __transfersize 2 int32 t const ptr NLD2 32 100 d1 re int64x1x2_t vld2_dup_s64 __transfersize 2 int64 t const ptr NLD1 64 100 01 r0 float32x2x2 t vld2_dup_f32 __transfersize 2 float32 t const ptr NED2 32 d d1 re poly8x8x2 t vld2_dup_p8 __transfersize 2 poly8_t const ptr NLD2 8 100 d1 r0 poly16x4x2_t vld2_dup_p16 __transfersize 2 polyl6 t const ptr NLD2 16 100 d1 r0 uint8x8x3 t vld3_dup_u8 __transfersize 3 uint8 t const ptr VLD3 8 100 d1 d2 rd uint16x4x3_t vld3_dup_u16 __transfersize 3 uint16_t const ptr E 32 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Using NEON Support NED3 16 d di d2 re uint32x2x3_t 1103 dup u32 transfersize 3 uint32 t const ptr NED3 32 d di d2 re uint64x1x3 t vl1d3 dup u64 transfersize 3 uint64 t const ptr NLD1 64 100 01 02 rd int8x8x3 t vld3_dup_s8 __transfe
51. target and instruction set SVC 0x123456 In ARM state for all architectures SVC 0xAB In Thumb state excluding ARMv7 M This behavior is not guaranteed on all debug targets from ARM or from third parties BKPT xAB For ARMv7 M Thumb 2 only Restrictions ARM processors prior to ARMv7 use SVC instructions to make semihosting calls However if you are compiling for the Cortex M3 processor semihosting is implemented using the BKPT instruction Example char buffer 100 void foo void __semihost x 1 const void buf equivalent in thumb state to int __svc xAB my svc int int result my svc O0x1 amp buffer Compiling this code with the option thumb generates foo PROC LDR r1 L1 12 MOVS r0 1 SVC 0xab L1 12 buffer 400 See also cpu list on page 2 15 thumb on page 2 86 svc on page 4 16 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 4 7 35 sev 4 7 36 __sqrt ARM DUI 0348A Compiler specific Features e BKPT on page 4 129 in the Assembler Guide SVC on page 4 130 in the Assembler Guide Appendix A Semihosting in the Developer Guide This intrinsic inserts a SEV instruction into the instruction stream generated by the compiler Syntax void __sev void Errors The compiler does not recognize the __sev intrinsic when compiling for a target that does not support the SEV instruction The compiler generates ei
52. the code letter is the lowercase version of the code letter in the initial line The source position in these lines is the same as that in the corresponding initial line Example main c include stdbool h int main void Compiling this code with the option list produces the raw listing file return true L 1 main c N include stdbool h L 1 include stdbool h 1 N stdbool h N Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 2 1 74 2 1 75 littleend ifndef __cplusplus In C bool true and false and keywords N N define bool _Bool N define true 1 N define false 0 N endif L 2 main c 2 N Nint main void N N return true X return 1 N See also asm on page 2 8 c on page 2 12 depend filename on page 2 23 depend_format string on page 2 24 info totals on page 2 48 interleave on page 2 50 md on page 2 60 S on page 2 80 Severity of diagnostic messages on page 5 3 in the Compiler User Guide This option instructs to the compiler to generate code for an ARM processor using little endian memory Compiler Command line Options With little endian memory the least significant byte of a word has the lowest address Default The compiler assumes littleend unless bigend is explicitly specified See also bigend on page 2 10 locale
53. transfersize 3 uint32 t ptr uint32x2x3 t val constrange 0 1 int lane NST3 32 d0 0 d1 d2 r0 constrange 0 7 int lane NST3 8 100 0 d1 0 d2 re constrange 0 3 int lane NST3 16 d0 d1 0 d2 r0 constrange 0 1 int lane NST3 32 d0 0 d1 d2 r0 Copyright 2007 2010 ARM Limited All rights reserved E 39 Non Confidential Using NEON Support void void void void void void void void void void void void void void void void void void vst3 lane f32 transfersize 3 float32 t ptr float32x2x3 t val constrange 0 1 int lane VST3 32 d d1 d2 0 r0 vst3_lane_p8 __transfersize 3 poly8 t ptr poly8x8x3 t val constrange 0 7 int lane VST3 8 d d1 d2 0 r0 vst3_lane_p16 __transfersize 3 poly16_t ptr polyl6x4x3 t val constrange 0 3 int lane NST3 16 100 0 d1 d2 0 r0 vst4q_lane_u16 __transfersize 4 uintl6 t ptr uintl6x8x4 t val constrange 0 7 int lane VST4 16 d0 0 d2 0 d4 0 d6 0 rd vst4q_lane_u32 __transfersize 4 uint32 t ptr uint32x4x4 t val constrange 0 3 int lane NST4 32 d0 0 d2 0 d4 0 d6 0 rd vst4q lane s16 transfersize 4 intl6 t ptr intl16x8x4 t val constrange 0 7 int lane NST4 16 100 0 d2 0 d4 0 de 0 re vst4q lane s32 transfersize 4 int32 t ptr
54. uintl6x4 t vsli n ul6 uintl6x4 t a uintl6x4 t b constrange 0 15 int c VSLI 16 d0 d0 0 uint32x2 t vsli n u32 uint32x2 t a uint32x2 t b constrange 0 31 int c VSLI 32 d0 d0 0 uint64x1l t vsli n u64 uint64x1 t a uint64x1l t b __constrange 63 int c VSLI 64 d0 d0 40 poly8x8 t vsli n p8 poly8x8 t a poly8x8_t b __constrange 0 7 int c NSLI 8 d0 d0 20 polyl6x4 t vsli n pl6 polyl6x4 t a polyl6x4 t b __constrange 15 int c VSLI 16 d0 d0 40 int8x16 t vslig n s8 int8x16 t a int8x16 t b __constrange 7 int c NSLI 8 q0 q0 0 intl6x8 t vslig_n_s16 int16x8_t a int16x8 t b constrange 0 15 int c VSLI 16 q0 q0 0 int32xX4 t vslig n s32 int32x4 t a int32x4 t b constrange 0 31 int c VSLI 32 q0 q0 0 int64x2 t vslig n s64 int64x2 t a int64x2 t b constrange 0 63 int c VSLI 64 qQ q0 0 uint8x16 t vsliq n u8 uint8x16 t a uint8x16 t b constrange 0 7 int c VSLI 8 q0 q0 0 uint16x8 t vsliq n ul6 uintl6x8 t a uintl6x8 t b constrange 0 15 int c VSLI 16 q0 q0 20 uint32x4 t vsliq n u32 uint32x4 t a uint32x4 t b constrange 0 31 int c VSLI 32 q0 q0 0 uint64x2 t vsliq n u64 uint64x2 t a uint64x2_t b __constrange 63 int c VSLI 64 q0 q0 20 poly8x16 t vsliq n p8 poly8x16 t a poly8x16 t b __constrange 7 int c VSLI 8 q0 q0 0 polyl16x8 t vsliq n p16 poly16x8 t a poly16x8 t b constrange 0 15 int c VSLI 16 qQ q0 0 DNE y y y E 3
55. vtrn_p8 poly8x8_t a poly8x8 t b vtrn pl6 poly16x4 t a polyl6x4 t b vtrnq s8 int8x16 t a int8x16 t b vtrnq sl6 intl6x8 t a intl16x8 t b vtrng_s32 int32x4_t a int32x4 t b vtrnq u8 uint8x16 t a uint8x16 t b vtrnq ul6 uintl6x8 t a uintl6x8 t b vtrng_u32 uint32x4_t a uint32x4 t b vtrnq f32 float32x4 t a float32x4 t b vtrnq p8 poly8x16 t a poly8x16_t b vtrnq pl6 poly16x8 t a poly16x8 t b Interleave elements int8x8x2 t intl6x4x2 t uint8x8x2 t uintl6x4x2 t float32x2x2 t poly8x8x2 t polyl6x4x2 t int8x16x2 t intl6x8x2 t int32x4x2 t uint8x16x2 t uintl6x8x2 t uint32x4x2 t float32x4x2 t poly8x16x2 t polyl6x8x2 t vzip s8 int8x8 t a int8x8 t b vzip sl6 intl6x4 t a intl6x4 t b vzip u8 uint8x8 t a uint8x8 t b vzip ul6 uintl6x4 t a uintl6x4 t b vzip f32 float32x2 t a float32x2 t b 210 p8 poly8x8 t a poly8x8 t b vzip pl6 poly16x4 t a polyl6x4 t b vzipq s8 int8x16 t a int8x16 t b 2100 sl6 intl16x8 t a intl16x8 t b vzipq_s32 int32x4_t a int32x4 t b 2100 u8 uint8x16 t a uint8x16 t b vzipq ul6 uintl16x8 t a uintl16x8 t b 2100 u32 uint32x4 t a uint32x4 t b vzipq f32 float32x4 t a float32x4 t b vzipq p8 poly8x16 t a poly8x16 t b vzipq pl6 poly16x8 t a poly16x8 t b De Interleave elements int8x8x2 t intl6x4x2 t int32x2x2 t uint8x8x2 t uintl6x4x2 t uint32x2x2 t float32x2x2 t poly8x8x2 t polyl6x4x2 t int8x16x2 t intl6x8x2 t int32x4x2 t uint8
56. 0 02 0 r0 constrange 3 int lane NST2 32 100 0 02 0 r0 constrange 0 7 int lane NST2 16 100 0 d2 r0 constrange 0 7 int lane NST2 8 d0 0 d1 0 r0 constrange 0 3 int lane NST2 16 100 0 d1 r0 _constrange 0 1 int lane NST2 32 100 0 d1 0 r0 vst2 lane s8 transfersize 2 int8 t ptr int8x8x2 t val __constrange 7 int lane NST2 8 100 0 d1 r0 constrange 0 3 int lane NST2 16 100 0 d1 r0 _constrange 0 1 int lane NST2 32 d0 0 d1 0 rd constrange 0 1 int lane NST2 32 100 0 d1 r0 constrange 0 7 int lane NST2 8 dO 0 d1 0 r0 _t val constrange 0 3 int lane NST2 16 d0 0 d1 r0 constrange 0 7 int lane NST3 16 dO0 0 d2 0 d4 r0 constrange 0 3 int lane NST3 32 100 0 d2 0 d4 r0 constrange 0 7 int lane NST3 16 d0 0 d2 0 d4 r0 constrange 0 3 int lane NST3 32 100 0 d2 0 d4 r0 constrange 0 3 int lane NST3 32 100 0 d2 0 d4 r0 constrange 0 7 int lane NST3 16 dO0 0 d2 0 d4 r0 constrange 0 7 int lane NST3 8 100 0 d1 0 d2 re vst3 lane ul6 transfersize 3 uint16 t ptr uintl6x4x3 t val constrange 0 3 int lane NST3 16 d0 d1 0 d2 r0 vst3 lane u32
57. 1 int16_t const ptr NED1 16 dO r0 int32x4 t vldiq dup s32 transfersize 1 int32 t const ptr VLD1 32 dO re int64x2_t vldiq dup s64 transfersize 1 int64 t const ptr VLD1 64 100 r0 float32x4 t vldiq dup f32 transfersize 1 float32 t const ptr NED1 32 d0 r0 poly8x16 t vldiq dup p8 transfersize 1 poly8_t const ptr VLD1 8 d0 3 r0 poly16x8_t vldlq dup p16 transfersize 1 polyl6 t const ptr VLD1 16 100 1 r0 uint8x8 t vldl dup u8 transfersize 1 uint8 t const ptr VLD1 8 d r0 uint16x4_t vldl dup ul6 transfersize 1 uint16_t const ptr NED1 16 dO r0 uint32x2 t vldl dup u32 transfersize 1 uint32 t const ptr NED1 32 dO rd uint64xl t vldl dup u64 transfersize 1 uint64_t const ptr VLD1 64 d0 r0 int8x8 t vldi dup s8 transfersize 1 int8 t const ptr VLD1 8 d r0 intl6x4_t vldl dup s16 transfersize 1 int16 t const ptr VLD1 16 dO rd int32x2 t vldl dup s32 transfersize 1 int32 t const ptr VLD1 32 dO r0 int64xl t vldl dup s64 transfersize 1 int64 t const ptr VLD1 64 100 r0 float32x2 t vldl dup f32 transfersize 1 float32 t const ptr NED1 32 d0 re poly8x8 t vldl dup p8 transfersize 1 poly8_t const ptr ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved Non Confidential
58. 2 69 Non Confidential Compiler Command line Options 2 1 91 2 1 92 2 70 pragma Otime on page 4 58 no_ parse_templates pch This option enables or disables the parsing of non class templates in their generic form in C that is when the template is defined and before it is instantiated Note The option no_parse_templates is provided only as a migration aid for legacy source code that does not conform to the C standard Its use is not recommended Mode This option is effective only if the source language is C Default The default is parse_templates Note no_parse_templates cannot be used with dep_name because parsing is done by default if dependent name processing is enabled Combining these options generates an error See also no_ dep_name on page 2 22 Template instantiation on page 5 15 This option instructs the compiler to use a PCH file if it exists and to create a PCH file otherwise When the option pch is specified the compiler searches for a PCH file with the name filename pch where filename is the name of the primary source file The compiler uses the PCH file fi lename pch if it exists and creates a PCH file named fiTename pch in the same directory as the primary source file otherwise Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options Restrictions This option has no e
59. 2003 International Standard for C The ARM compiler also supports several extensions to ISO C See Language extensions and language compliance on page 1 5 for more information Throughout this document the term strict C Means ISO C excepting wide streams and export templates Standard C Means strict C C Means ISO C excepting wide streams and export templates either with or without the ARM extensions Use the compiler option cpp to compile C code See also cpp on page 2 14 Language extensions and language compliance on page 1 5 Appendix C Standard C Implementation Definition Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Introduction 1 3 Language extensions and language compliance 1 3 1 Language extensions ARM DUI 0348A The compiler supports numerous extensions to its various source languages It also provides several command line options for controlling compliance with the available source languages The language extensions supported by the compiler are categorized as follows The compiler makes some language features of C99 available as extensions to strict C90 for example style comments as extensions to both Standard C and strict C90 for example restrict pointers For more information see C99 language features available in C90 on page 3 5 C99 language features available in C and C90 on page 3 7 Standar
60. 2147483648 1 This expression evaluates to 0 in strict C and C and to 1 in ARM C and C The long long types are accommodated in the usual arithmetic conversions See also int64 on page 4 9 The restrict keyword is a C99 feature that enables you to ensure that different object pointer types and function parameter arrays do not point to overlapping regions of memory Therefore the compiler performs optimizations that can be otherwise prevented because of possible aliasing Restrictions To enable the restrict keyword in C90 or C you must specify the restrict option The keywords restrict and __restrict__ are supported as synonyms for restrict and are always available regardless of whether restrict is specified Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 3 3 4 Hex floats ARM DUI 0348A Language Extensions Example void copy array int n int srestrict a int restrict b while n gt 0 a 0 See also no_ restrict on page 2 79 New features of C99 on page 1 5 in the Compiler User Guide C90 and C support floating point numbers that can be written in hexadecimal format Example float hex_floats void return 0x1 fp3 1 55e1 See also New features of C99 on page 1 5 in the Compiler User Guide Copyright 2007 2010 ARM Limited All rights reserved 3 9 Non Confidential Language Extensions 3 4 Stand
61. 4 uint32 t ptr uint32x2x2 t val NST2 32 d0 01 r0 E 36 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential void void void void void void void void void void void void void void void void void void void void void void void void void ARM DUI 0348A vst2 u64 transfersize 2 uint64 t vst2 s8 transfersize 16 int8 t vst2_s16 __transfersize 8 intl16 t vst2 s32 transfersize 4 int32 t vst2_s64 __transfersize 2 int64 t vst2 f32 transfersize 4 float32 t vst2 p8 transfersize 16 poly8 t vst2 pl6 transfersize 8 polyl6 t vst3q u8 transfersize 48 uint8 t vst3q ul6 transfersize 24 uint16_ vst3q u32 transfersize 12 uint32_ vst3q s8 transfersize 48 int8 t vst3q s16 transfersize 24 intl16 t vst3q_s32 __transfersize 12 int32 t vst3q f32 transfersize 12 float32 vst3q_p8 __transfersize 48 poly8 t vst3q_p16 __transfersize 24 poly16_ vst3_u8 __transfersize 24 uint8_t vst3_u16 __transfersize 12 uint16_t vst3_u32 __transfersize 6 uint32_t vst3 u64 transfersize 3 uint64 t vst3 s8 transfersize 24 int8 t vst3 516 transfersize 12 intl6 t vst3_s32 __transfersize 6 int32 t vst3 s64 transfersize 3 int64 t ptr uint64x1x2 t val NST1 64 100 d1 r0 ptr int8x8x2 t val NST2 8 100 d1 r0 ptr intl6x4x2 t val VST2 16 d0 d1 r0 ptr int3
62. 64 int c constrange 1 8 int c Copyright O 2007 2010 ARM Limited All rights reserved Non Confidential NSRA NSRA NSRA NSRA constrange 1 16 int c VSRA constrange 1 32 int c VSRA constrange 1 64 int c VSRA Using NEON Support NRSHR U16 dO dQ 16 NRSHR U32 00 00 32 NRSHR U64 00 00 64 NRSHR S16 00 90 16 NRSHR S32 00 90 32 NRSHR S64 00 90 64 VRSHR U16 q0 q0 16 constrange 1 32 int b VRSHR U32 00 00 32 MRSHR U64 00 00 64 S8 00 00 68 S16 00 00 16 S32 00 00 32 S64 00 00 64 U8 00 00 68 U16 00 00 16 U32 00 00 32 064 00 00 64 S8 q0 q0 8 S16 00 00 16 32 30 080 232 364 q0 q0 64 U8 q0 q0 8 U16 q0 q0 16 U32 q0 q0 32 U64 q0 q0 64 MRSRA S8 00 d0 8 VRSRA S16 d0 d0 416 MRSRA S32 d0 d0 432 MRSRA S64 d0 d0 464 MRSRA U8 d0 d0 8 MRSRA U16 d0 d0 416 MRSRA U32 d0 d0 432 MRSRA U64 d0 d0 464 MRSRA S8 q0 q0 28 VRSRA S16 q0 q0 16 MRSRA S32 00 00 32 NRSRA S64 00 00 64 MRSRA U8 q0 q0 28 constrange 1 16 int c VRSRA U16 q0 q0 16 E 21 Using NEON Support uint32x4 t vrsrag n u32 uint32x4 t a uint32x4 t b uint64x2 t vrsrag n u64 uint64x2 t a uint64x2 t b constrange 1 32 int c VRSRA U32 q0 q0 32 constrange 1 64 int c VRSRA U64 q0 q0 464 y y Vector saturating shift left by constant int8
63. ARM Limited All rights reserved Non Confidential ARM DUI 0348A Using NEON Support intl6x8 t n sl6 intl6x8 t a intl16 t b MUL 116 q0 q0 d0 0 int32xX4 t vmulq n s32 int32x4 t a int32 t b MUL 132 q0 q0 d0 0 float32x4 t vmulq n f32 float32x4 t a float32 t b VMUL F32 q0 q0 d0 0 uintl6x8 t vmulq n ul6 uint16x8 t a uint16 t b VMUL I16 q0 q0 d0 0 uint32x4 t vmulq n u32 uint32x4 t a uint32 t b VMUL I32 q0 q0 d0 0 Vector long multiply with scalar int32x4 t vmull n si6 intl6x4 t vecl intl16 t val2 NMULL S16 q0 d0 d0 0 int64x2 t vmull n s32 int32x2 t vecl int32 t val2 NMULL S32 q0 d0 d0 0 uint32x4 t vmull n ul6 uintl6x4 t vecl uintl16 t val2 VMULL U16 q0 d0 d0 0 uint64x2 t vmull n u32 uint32x2 t vecl uint32 t val2 VMULL U32 q0 d0 d0 0 Vector long multiply by scalar int32x4 t vmull lane sl16 intl6x4 t vecl intl6x4 t val2 __constrange 3 int val3 VMULL S16 q0 d0 d0 0 constrange 0 1 int val3 WMULL S32 q0 d0 d0 0 constrange 0 3 int val3 NMULL U16 q0 d0 d0 0 _ constrange 1 int val3 NMULL U32 q0 d0 d0 0 int64x2 t vmull lane s32 int32x2 t vecl int32x2 t val2 uint32x4 t vmull lane ul6 uintl6x4 t vecl uintl6x4 t val2 uint64x2 t vmull lane u32 uint32x2 t vecl uint32x2 t val2 Vector saturating doubling long multiply with scalar int32x4 t vqdmull n s16 intl16x4 t vecl int16 t val2 NQDMULL S16 q0 d0 d0 0
64. Assembler Guide 4 1 16 svc indirect ARM DUI 0348A The __svc_indirect keyword passes an operation code to the SVC handler in r12 __svc_indirect is a function qualifier It affects the type of a function Syntax __svc_indirect int svc nur return type function name int rea num argument list Where svc num Is the immediate value used in the SVC instruction It is an expression evaluating to an integer in the range 0 to 224 1 a 24 bit value in an ARM instruction 0 255 an 8 bit value in a 16 bit Thumb instruction real num Is the value passed in r12 to the handler to determine the function to perform Copyright O 2007 2010 ARM Limited All rights reserved 4 17 Non Confidential Compiler specific Features To use the indirect mechanism your system handlers must make use of the r12 value to select the required operation Usage You can use this feature to implement indirect SVCs Example int svc indirect 0 ioctl int svcino int fn void argp Calling ioctl IOCTLe4 RESET NULL compiles to SVC 40 with IOCTL 4 in r12 Errors When an ARM architecture variant or ARM architecture based processor that does not support an SVC instruction is specified on the command line using the cpu option the compiler generates an error See also cpu name on page 2 15 value in regs on page 4 19 SVC on page 4 130 in the Assembler Guide 4 1 17 svc indirect r7 4 18 The __svc_indire
65. Command line Options 2 1 72 2 54 Use an option of the form library_interface aeabi_ when linking with an ABlI compliant C library Options of the form library interface aeabi ensure that the compiler does not generate calls to any optimized functions provided by the RVCT C library Example When your code calls functions provided by an embedded operating system that replace functions provided by the RVCT C library compile your code with library interface aeabi clib to disable calls to any special RVCT variants of the library functions replaced by the operating system See also ABI for the ARM Architecture compliance on page 1 3 in the Libraries Guide library type lib This option enables the selected library to be used at link time Note Use this option with the linker to override all other library type options Syntax library type lib Where 7ib is one of standardlib Specifies that the full RVCT runtime libraries are selected at link time Use this option to exploit the full range of compiler optimizations when linking microlib Specifies that the C micro library microlib is selected at link time Default If you do not specify library type the compiler assumes library type standardlib See also Building an application with microlib on page 3 4 in the Libraries Guide Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Com
66. Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Standard C Implementation Definition B 1 11 Expression evaluation ARM DUI 0348A The compiler can re order expressions involving only associative and commutative operators of equal precedence even in the presence of parentheses For example a b C might be evaluated as a b c if a b and c are integer expressions Between sequence points t he compiler can evaluate expressions in any order regardless of parentheses Therefore side effects of expressions between sequence points can occur in any order The compiler can evaluate function arguments in any order Any aspect of evaluation order not prescribed by the relevant standard can be varied by e the optimization level you are compiling at the release of the compiler you are using Copyright O 2007 2010 ARM Limited All rights reserved B 7 Non Confidential Standard C Implementation Definition B 1 12 Preprocessing directives The ISO standard C header files can be referred to as described in the standard for example include lt stdio h gt Quoted names for includable source files are supported The compiler accepts host filenames or UNIX filenames For UNIX filenames on non UNIX hosts the compiler tries to translate the filename to a local equivalent The recognized pragma directives are shown in Pragmas on page 4 49 B 1 13 Library functions The ISO C lib
67. Guide 4 6 8 pragma diag warning tag tag This pragma sets the diagnostic messages that have the specified tag s to Warning severity 4 54 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 4 6 9 Compiler specific Features pragma diag remark behaves analogously to pragma diag errors except that the compiler sets the diagnostic messages having the specified tags to Remark severity rather than Error severity Syntax pragma diag warning tag tag Where tag tag is a comma separated list of diagnostic message numbers specifying the messages whose severities are to be changed See also diag warning tag tag on page 2 30 pragma diag default tag tag on page 4 51 pragma diag error tag tag on page 4 52 pragma diag remark tag tag on page 4 53 pragma diag suppress tag tag on page 4 54 Changing the severity of diagnostic messages on page 5 5 in the Compiler User Guide pragma no Jexceptions unwind This pragma enables or disables function unwinding at runtime Default The default is pragma exceptions unwind See also no exceptions on page 2 35 no exceptions unwind on page 2 35 Function unwinding at runtime on page 5 18 4 6 10 pragma hdrstop ARM DUI 0348A This pragma enables you to specify where the set of precompilation header files end This pragma must appear before the fi
68. Ir ENDP See also no_ data_reorder on page 2 20 feedback filename on page 2 37 no multifile on page 2 63 attribute section on page 4 34 pragma arm section section_sort_list on page 4 50 Using linker feedback on page 2 25 in the Compiler User Guide 2 1 112 no_ strict 2 84 This option enforces or relaxes strict C or strict C depending on the choice of source language used When strict is selected features that conflict with ISO C or ISO C are disabled error messages are returned when nonstandard features are used Default The default is no_strict Usage strict enforces compliance with ISO C90 ISO IEC 9899 1990 the 1990 International Standard for C ISO IEC 9899 AMI the 1995 Normative Addendum 1 ISO C99 ISO IEC 9899 1999 the 1999 International Standard for C ISO C ISO IEC 14822 2003 the 2003 International Standard for C Errors When strict is in force and a violation of the relevant ISO standard occurs the compiler issues an error message The severity of diagnostic messages can be controlled in the usual way Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options Example void foo void long long i okay in non strict C90 Compiling this code with strict generates an error See also c90 on page 2 13 c99 on page 2 13 cpp on page
69. Other properties of the source character set are host specific The properties of the execution character set are target specific The ARM C and C libraries support the ISO 8859 1 Latin 1 Alphabet character set with the following consequences The execution character set is identical to the source character set There are eight bits in a character in the execution character set There are four characters bytes in an int If the memory system is Little endian The bytes are ordered from least significant at the lowest address to most significant at the highest address Big endian The bytes are ordered from least significant at the highest address to most significant at the lowest address In C all character constants have type int In C a character constant containing one character has the type char and a character constant containing more than one character has the type int Up to four characters of the constant are represented in Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential ARM DUI 0348A C and C Implementation Details the integer value The last character in the constant occupies the lowest order byte of the integer value Up to three preceding characters are placed at higher order bytes Unused bytes are filled with the NULL character Table 5 1 lists all integer character constants that contain a single character or character escape sequence are represented in both the
70. VQMOVUN S32 d0 q0 uint32x2 t vqmovun s64 int64x2 t a VQMOVUN S64 d0 q0 E 3 23 Table look up uint8x8 t vtbll u8 uint8x8 t a uint8x8 t b VTBL 8 00 dQ dQ int8x8 t vtbll1 s8 int8x8 t a int8x8 t b NTBL 8 00 d0 00 poly8x8 t vtbll p8 poly8x8 t a uint8x8 t b VIBL 8 d 100 dO uint8x8 t vtbl2 u8 uint8x8x2 t a uint8x8 t b VTBL int8x8 t vtbl2 s8 int8x8x2 t a int8x8 t b X VIBL poly8x8 t vtbl2 p8 poly8x8x2 t a uint8x8_t b VIBL uint8x8 t vtb13 u8 uint8x8x3 t a uint8x8 t b VTBL int8x8 t vtbl3 s8 int8x8x3 t a int8x8 t b VIBL poly8x8_t vtb13 p8 poly8x8x3 t a uint8x8_t b VIBL uint8x8 t vtbl4 u8 uint8x8x4 t a uint8x8 t b VTBL int8x8 t vtbl4 s8 int8x8x4 t a int8x8 t b X VIBL poly8x8 t vtb14 p8 poly8x8x4 t a uint8x8_t b VIBL d 100 d1 dO d 100 d1 dO d 100 d1 dO d 100 01 d2 d d 100 01 d2 d d 100 01 d2 d d 100 01 02 d3 dO d 100 01 02 d3 dO d 100 01 02 d3 do OO OO OO OO OO OO CO CO CO CO CO E 3 24 Extended table look up intrinsics uint8x8 t vtbxl u8 uint8x8 t a uint8x8 t b uint8x8 t c VTBX 8 d d0 00 int8x8 t vtbxl s8 int8x8 t a int8x8 t b int8x8 t c NTBX 8 00 d0 00 poly8x8 t vtbx1_p8 poly8x8_t a poly8x8_t b uint8x8 t c VIBX 8 00 dO do uint8x8 t vtbx2 u8 uint8x8 t a uint8x8x2 t b uint8x8 t c VTBX int8x8 t vtbx2 s8 int8x8 t a int8x
71. __transfersize 24 int8 t const ptr VLD3 8 d 01 d2 r0 intl6x4x3 t vld3_s16 __transfersize 12 int16 t const ptr VLD3 16 100 d1 d2 r0 int32x2x3 v1d3 s32 transfersize 6 int32 t const ptr NED3 32 100 d1 d2 r0 int64x1x3 t vld3_s64 __transfersize 3 int64 t const ptr NED1 64 100 d1 d2 r0 float32x2x3 t v1d3 f32 transfersize 6 float32 t const ptr NED3 32 100 d1 d2 r0 poly8x8x3 t v1d3 98 transfersize 24 poly8 t const ptr poly16x4x3_t uint8x16x4_t uint16x8x4_t uint32x4x4 t NLD3 8 100 01 02 r0 103 p16 transfersize 12 poly16 t const ptr NLD3 16 100 01 02 r0 vld4q u8 transfersize 64 uint8 t const ptr NLD4 8 d0 02 d4 06 r0 vld4q ul6 transfersize 32 uintl16 t const ptr NLD4 16 d0 02 04 06 r0 vld4q u32 transfersize 16 uint32 t const ptr NLD4 32 d0 d2 d4 06 r0 int8x16x4_t vld4q s8 transfersize 64 int8 t const ptr VLD4 8 100 02 04 d6 r0 intl6x8x4 t vld4q s16 transfersize 32 intl16 t const ptr VLD4 16 100 02 d4 06 r0 int32x4x4 v1d4q s32 transfersize 16 int32 t const ptr VLD4 32 100 d2 d4 06 r0 float32x4x4 t vld4q f32 transfersize 16 float32 t const ptr poly8x16x4 t ARM DUI 0348A VLD4 32 d0 02 04 d6 r0 1049 p8 transfersize 64 poly8 t const ptr Copyright 2
72. a intl6x4 t b MMAX S16 d0 d0 d0 int32x2 t vmax s32 int32x2 t a int32x2 t b MMAX S32 d0 d0 d0 uint8x8 t vmax_u8 uint8x8_t a uint8x8 t b MMAX U8 d0 d0 d0 uint16x4_t vmax ul6 uintl6x4 t a uintl6x4 t b MMAX U16 d0 d0 d0 uint32x2 t vmax u32 uint32x2 t a uint32x2 t b MMAX U32 d0 d0 d0 float32x2 t vmax f32 float32x2 t a float32x2 t b VMAX F32 d0 d0 d0 int8x16 t vmaxq s8 int8x16 t a int8x16 t b NMAX S8 q0 q0 q0 intl6x8 t vmaxq sl6 intl6x8 t a intl6x8 t b NMAX S16 q0 q0 q0 int32x4 t Jvmaxq s32 int32x4 t a int32x4 t b NMAX S32 q0 q0 q0 uint8x16 t vmaxq u8 uint8x16 t a uint8x16 t b NMAX U8 q0 q0 q0 uintl6x8 t vmaxq ul6 uintl6x8 t a uintl16x8 t b VMAX U16 q0 q0 q0 uint32x4 t vmaxq u32 uint32x4 t a uint32x4 t b VMAX U32 q0 q0 q0 float32x4 t vmaxq f32 float32x4 t a float32x4 t b VMAX F32 q0 q0 q0 vmin gt Vr i Va i gt Vb i Vb i Va i int8x8 t vmin s8 int8x8 t a int8x8 t b MMIN S8 d0 d0 d0 intlox4 t vmin sl6 intl6x4 t a intl6x4 t b MMIN S16 d0 d0 d0 int32x2 t vmin s32 int32x2 t a int32x2 t b MMIN S32 d0 d0 d0 uint8x8 t vmin u8 uint8x8 t a uint8x8 t b MMIN U8 d0 d0 d0 uintlox4 t wvmin ul6 uintl6x4 t a uintl6x4 t b MMIN U16 d0 d0 d0 uint32x2 t wvmin u32 uint32x2 t a uint32x2 t b MMIN U32 d0 d0 d0 float32x2 t vmin f32 float32x2 t a float32x2 t b VMIN F32 d0 d0 d0 int8x16 t vming s8 int8x16 t a int8
73. a GNU compiler extension that is supported by the ARM compiler 4 4 0 __attribute packed The packed type attribute specifies that a type must have the smallest possible alignment Note This type attribute is a GNU compiler extension that is supported by the ARM compiler Errors The compiler generates a warning message if you use this attribute in a typedef ARM DUI 0348A Copyright 2007 2010 ARM Limited All rights reserved 4 37 Non Confidential Compiler specific Features See also _ packed on page 4 11 Packed structures on page 5 10 The __packed qualifier and unaligned accesses to data on page 4 24 in the Compiler User Guide _ packed structures versus individually __ packed fields on page 4 26 in the Compiler User Guide 4 4 3 attribute transparent union The transparent union type attribute enables you to specify a transparent union type that is a union data type qualified with attribute transparent union When a function is defined with a parameter having transparent union type a call to the function with an argument of any type in the union results in the initialization of a union object whose member has the type of the passed argument and whose value is set to the value of the passed argument When a union data type is qualified with __attribute__ transparent_union the transparent union applies to all function parameters with that type Note This type attribu
74. an argument of type float instead of an argument of type double it returns a float value instead of a double value See also sqrt on page 4 87 VABS VNEG and VSQRT on page 5 89 in the Assembler Guide 4 7 38 __ssat This intrinsic inserts an SSAT instruction into the instruction stream generated by the compiler It enables you to saturate a signed value from within your C or C code Syntax int ssat int val unsigned int sat Where val Is the value to be saturated sat Is the bit position to saturate to 4 88 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 4 7 39 __strex ARM DUI 0348A Compiler specific Features sat must be in the range 1 to 32 Return value The __ssat intrinsic returns va saturated to the signed range 2 4t l lt x lt 25at 1 Errors The compiler does not recognize the __ssat intrinsic when compiling for a target that does not support the SSAT instruction The compiler generates either a warning or an error in this case See also usat on page 4 93 SSAT and USAT on page 4 96 in the Assembler Guide This intrinsic inserts an instruction of the form STREX size into the instruction stream generated by the compiler It enables you to use a STREX instruction in your C or C code to store data to memory Syntax int strex unsigned int val volatile void ptr Where val Is the value to be written to me
75. and alignment of basic data types Table 5 2 gives the size and natural alignment of the basic data types Table 5 2 Size and alignment of data types Type Size in bits Natural alignment in bytes char 8 1 byte aligned short 16 2 halfword aligned int 32 4 word aligned long 32 4 word aligned long long 64 8 doubleword aligned float 32 4 word aligned double 64 8 doubleword aligned long double 64 8 doubleword aligned All pointers 32 4 word aligned bool C only 8 1 byte aligned _Bool C only 8 1 byte aligned wchar_t C only 16 2 halfword aligned a stdbool h can be used to define the bool macro in C Type alignment varies according to the context Local variables are usually kept in registers but when local variables spill onto the stack they are always word aligned For example a spilled local char variable has an alignment of 4 The natural alignment of a packed type is 1 5 4 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential C and C Implementation Details See Structures unions enumerations and bitfields on page 5 7 for more information Integer Integers are represented in two s complement form The low word of a long long is at the low address in little endian mode and at the high address in big endian mode Float Floating point quantities are stored in IEEE format float values are repres
76. apcs fpic in GNU mode you must also use no hide all See also no hide all on page 2 46 no_ Jlower_ropi on page 2 59 no lower rwpi on page 2 59 __declspec dllexport on page 4 24 Writing reentrant and thread safe code on page 2 4 in the Libraries Guide Veneer generation on page 3 20 in the Linker Guide Chapter 6 BPABI and System V Shared Libraries and Executables in the Linker Guide Procedure Call Standard for the ARM architecture in install_directory Documentation Specifications This option configures the compiler to target the ARM instruction set Note This option is not relevant for Thumb only processors such as Cortex M3 Default This is the default option for targets supporting the ARM instruction set Copyright O 2007 2010 ARM Limited All rights reserved 2 7 Non Confidential Compiler Command line Options 2 1 6 2 8 asm See also cpu list on page 2 15 cpu name on page 2 15 thumb on page 2 86 pragma arm on page 4 50 Specifying the target processor or architecture on page 2 22 in the Compiler User Guide This option instructs the compiler to write a listing to a file of the disassembly of the machine code generated by the compiler Object code is generated when this option is selected The link step is also performed unless the c option is chosen Note To produce a disassembly of the machine code generated by the compiler wit
77. can be fixed at runtime data can have multiple instances data can be but does not have to be position independent sets the PI attribute on read write output sections Note Because the lower rwpi option is the default code that is not RWPI is automatically transformed into equivalent code that is RWPI This static initialization is done at runtime by the C constructor mechanism even for C ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved 2 5 Non Confidential Compiler Command line Options no fpic Restrictions If you select this option the compiler accesses all static data using PC relative addressing accesses all imported or exported read write data using a Global Offset Table GOT entry created by the linker accesses all read only data relative to the PC You must compile your code with fpic if it uses shared objects This is because relative addressing is only implemented when your code makes use of System V shared libraries You do not need to compile with fpic if you are building either a static image or static library The use of fpic is supported when compiling C In this case virtual table functions and typeinfo are placed in read write areas so that they can be accessed relative to the location of the PC There are restrictions when you compile code with ropi or rwpi or fpic ropi The main restrictions when compiling with ropi are
78. compile time constant __constrange min max the argument must be a compile time constant in the range min to max __transfersize n the intrinsic loads n bytes from this pointer These intrinsics add vectors Each lane in the result is the consequence of performing the addition on the corresponding lanes in each operand vector The operations performed are as follows Vector add vadd gt Vr i Va i Vb i on page E 5 Vector long add vadd gt Vr i Va i Vb i on page E 5 Vector wide add vadd gt Vr i Va i Vb i on page E 5 Vector halving add vhadd gt Vr i Va i Vb i gt gt 1 on page E 6 Vector rounding halving add vrhadd gt Vr i Va i Vb i 1 gt gt J on page E 6 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Using NEON Support Vector saturating add vqadd gt Vr i sat lt size gt Va i Vb i on page E 6 Vector add high half gt Vr i Va i Vb i on page E 7 Vector rounding add high half on page E 7 Vector add vadd gt Vr i Va i Vb i Vr Va Vb have equal lane sizes int8x8 t vadd s8 int8x8 t a int8x8 t b VADD I8 d0 d0 d0 intlox4 t vadd si16 intl6x4 t a intl16x4 t b VADD I16 d0 d0 d0 int32x2 t X vadd s32 int32x2 t a int32x2 t b VADD I32 d0 d0 d0 int64xl t vadd_s64 int64x1_t a int64x1l t b VADD I64 d0 d0 d0 float32x2 t vadd f32 float32x2 t a float32x2 t b VADD F32 d0 d0 d0 uint8x8 t vadd_u
79. conformance and implementation details Chapter 4 Compiler specific Features Read this chapter for a detailed list of ARM specific keywords operators pragmas intrinsic functions macros and semihosting Supervisor Calls SVCs Chapter 5 C and C Implementation Details Read this chapter for a description of the language implementation details for the ARM compiler Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Preface Appendix A Via File Syntax Read this appendix for a description of the syntax for via files You can use via files to specify command line arguments to many ARM tools Appendix B Standard C Implementation Definition Read this appendix for information on the ARM C implementation that relates directly to the ISO C requirements Appendix C Standard C Implementation Definition Read this appendix for information on the ARM C implementation Appendix D C and C Compiler Implementation Limits Read this appendix for implementation limits of C and C in the ARM compiler Appendix E Using NEON Support Read this appendix for information on the NEON intrinsics supported in this release of RVCT This book assumes that the ARM software is installed in the default location For example on Windows this might be volume Program Files ARM This is assumed to be the location of install_directory when referring to path names for example install directoryNDocumentationN
80. entities can help to reduce the amount of debug information generated per file it has the disadvantage of reducing the number of debug sections that are common to many files This reduces the number of common debug sections that the linker is able to remove at final link time and can result in a final debug image that is larger than necessary For this reason use remove unneeded entities only when necessary 2 78 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options Restrictions The effects of these options are restricted to debug information Default Removal of unneeded entities is disabled by default See also The DWARF Debugging Standard at http dwarfstd org 2 1 104 no restrict 2 1 105 no rtti ARM DUI 0348A This option enables or disables the use of the C99 keyword restrict Note The alternative keywords restrict and __restrict__ are supported as synonyms for restrict These alternative keywords are always available regardless of the use of the restrict option Default When compiling ISO C99 source code use of the C99 keyword restrict is enabled by default When compiling ISO C90 or ISO C source code use of the C99 keyword restrict is disabled by default See also restrict on page 3 8 This option controls support for the RTTI features dynamic_cast and typeid in C Mode This option is effe
81. first specified via via file argument with the sequence of argument words extracted from the via file including recursively processing any nested via commands in the via file 2 Processes any subsequent via via filearguments in the same way in the order they are presented That is via files are processed in the order you specify them and each via file is processed completely including processing nested via files before processing the next via file A 2 Copyright O 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential A 2 Syntax Via File Syntax Via files must conform to the following syntax rules ARM DUI 0348A A via file is a text file containing a sequence of words Each word in the text file is converted into an argument string and passed to the tool Words are separated by whitespace or the end of a line except in delimited strings For example c90 strict two words c90 strict one word The end of a line is treated as whitespace For example c90 strict is equivalent to c90 strict Strings enclosed in quotation marks or apostrophes are treated as a single word Within a quoted word an apostrophe is treated as an ordinary character Within an apostrophe delimited word a quotation mark is treated as an ordinary character Quotation marks are used to delimit filenames or path names that contain spaces For example I C My Project Vincludes thr
82. in the Assembler Guide 4 7 41 __Swp This intrinsic inserts a SWP size instruction into the instruction stream generated by the compiler It enables you to swap data between memory locations from your C or C code Note The use of SWP and SWPB is deprecated in ARMv6 and above Syntax unsigned int __swp unsigned int val volatile void ptr where val Is the data value to be written to memory ptr Points to the address of the data to be written to in memory To specify the size of the data to be written cast the parameter to an appropriate integral type Table 4 12 Access widths supported by the swp intrinsic Instruction Size of data loaded C cast SWPB unsigned byte char SWP word int Return value The __swp intrinsic returns the data value that previously is in the memory address pointed to by ptr before this value is overwitten by val 4 92 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 4 7 42 __usat ARM DUI 0348A Compiler specific Features Example int foo void int loc Oxff return swp 0x20 volatile int loc Compiling this code produces foo PROC MOV rl 0xff MOV rO 0x20 SWP ro r0 r1 BX Ir ENDP See also SWP and SWPB on page 4 39 in the Assembler Guide This intrinsic inserts a USAT instruction into the instruction stream generated by the compiler It enables you to saturate an unsigned value from within your C or C c
83. instruction stream generated by the compiler It enables you to signal to the memory system from your C or C program that an instruction load from an address is likely in the near future Syntax void __pli Where denotes any number of pointer or integer arguments specifying addresses of instructions to prefetch Restrictions If the target architecture does not support instruction prefetching this intrinsic has no effect See also __pld on page 4 79 PLD and PLI on page 4 24 in the Assembler Guide 4 7 26 qadd This intrinsic inserts a QADD instruction or an equivalent code sequence into the instruction stream generated by the compiler It enables you to obtain the saturating add of two integers from within your C or C code Syntax int __qadd int vali int val2 4 80 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 4 7 27 __qdbl 4 7 28 qsub ARM DUI 0348A Compiler specific Features Where vali is the first summand of the saturating add operation val2 is the second summand of the saturating add operation Return value The __qadd intrinsic returns the saturating add of va71 and 2 See also qdbl e qsub QADD QSUB QDADD and QDSUB on page 4 94 in the Assembler Guide This intrinsic inserts instructions equivalent to the saturating add of an integer with itself into the instruction stream generated by the compiler It enables you to obtain the satu
84. intl6x4 t b VRSHL S16 d0 d0 d0 int32x2 t vrshl s32 int32x2 t a int32x2 t b VRSHL S32 d0 d0 d0 int64xl t vrshl_s64 int64x1_t a int64x1_t b VRSHL S64 d0 d0 d0 uint8x8 t vrshl u8 uint8x8 t a int8x8 t b NRSHL U8 d0 d0 d0 uintl6x4 t vrshl ul6 uintl6x4 t a intl6x4 t b VRSHL U16 dQ dQ d0 uint32x2 t vrshl u32 uint32x2 t a int32x2 t b VRSHL U32 dQ dQ d0 uint64x1l t vrshl u64 uint64x1l t a int64x1_t b VRSHL U64 dQ dQ d0 int8x16 t vrshlq s8 int8x16 t a int8x16 t b VRSHL S8 q0 q90 q0 intl6x8 t vrshlq_s16 int16x8_t a intl16x8 t b VRSHL S16 q0 q0 q0 int32x4 t vrshlq s32 int32x4 t a int32x4 t b VRSHL S32 q0 q0 q0 int64x2 t vrshlq s64 int64x2 t a int64x2 t b VRSHL S64 q0 q0 q0 uint8x16 t vrshlq u8 uint8x16 t a int8x16 t b VRSHL U8 q0 q0 q0 uintl6x8 t vrshlq ul6 uintl6x8 t a int16x8_t b VRSHL U16 q0 q0 q0 uint32x4 t vrshlq u32 uint32x4 t a int32x4 t b VRSHL U32 q0 q0 q0 uint64x2 t vrshlq u64 uint64x2 t a int64x2 t b VRSHL U64 q0 q0 q0 Vector saturating rounding shift left negative values shift right int8x8 t vqrshl s8 int8x8 t a int8x8 t b NORSHL S8 d0 d0 d0 intl6x4 t varshl_s16 int16x4_t a intl6x4 t b VQRSHL S16 d0 d0 d0 int32x2 t vqrshl s32 int32x2 t a int32x2 t b VQRSHL S32 d0 d0 d0 int64x1l t vqrshl s64 int64x1 t a int64x1 t b VQRSHL S64 d0 d0 d0 uint8x8 t vqrshl u8 uint8x8 t a int8x8 t b NORSHL U8 d0 d0 d0 uintl6x4 t vqrshl ul6 uin
85. lvalue when looking at comma expressions and constructs is relaxed in GNU mode You can use compound expressions conditional expressions and casts as follows You can assign a compound expression a b x This is equivalent to temp a b b temp x You can get the address of a compound expression amp a b This is equivalent to a amp b You can use conditional expressions for example a b c a This picks b or c as the destination dependent on a ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved 3 29 Non Confidential Language Extensions Mode Supported in GNU mode only for C90 and C99 only 3 7 12 Pointer arithmetic You can perform arithmetic on void pointers and function pointers The size of a void type or a function type is defined to be 1 Mode Supported in GNU mode for C90 and C99 only Errors The compiler generates a warning if it detects arithmetic on void pointers or function pointers Example int ptr_arith_O void void pointer return sizeof pointer int ptr arith 1 void i static int diff diff ptr arith 0 ptr_arith_1 return sizeof ptr arith 0 3 7 13 Statement expressions Statement expressions enable you to place whole sections of code including declarations within braces The result of a statement expression is the final item in the statement list 3 30 Copyright 2007 2010 ARM Limited All rights r
86. memory transfers including hardware floating point loads and stores directly on unaligned memory objects Note Code size might increase significantly when compiling for CPUs without hardware support for unaligned access for example pre v6 architectures This option does not affect the placement of objects in memory nor the layout and padding of structures See also __ packed on page 4 11 Aligning data on page 4 24 in the Compiler User Guide no project fiTename The option project fi lename instructs the compiler to load the project template file specified by filename Note To use filename as a default project file set the RVDS PROJECT environment variable to filename The option no project prevents the default project template file specified by the environment variable RVDS PROJECT from being used Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options Syntax projectefilename no project Where filename is the name of a project template file Restrictions Options from a project template file are only set when they do not conflict with options already set on the command line If an option from a project template file conflicts with an existing command line option the command line option takes precedence Example Consider the following project template file lt suiteconf cfg gt lt suiteconf na
87. more information The compiler has several modes in which compliance to a source language is either enforced or relaxed Strict mode In strict mode the compiler enforces compliance with the language GNU mode Example standard relevant to the source language For example the use of style comments results in an error when compiling strict C90 To compile in strict mode use the command line option strict In GNU mode all the GNU compiler extensions to the relevant source language are available For example in GNU mode case ranges in switch statements are available when the source language is any of C90 C99 or non strict C C99 style designated initializers are available when the source language is either C90 or non strict C To compile in GNU mode use the compiler option gnu Note Some GNU extensions are also available when you are in a non strict mode The following examples illustrate combining source language modes with language compliance modes Compiling a cpp file with the command line option strict compiles Standard C Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential ARM DUI 0348A Introduction Compiling a C source file with the command line option gnu compiles GNU mode C90 Compiling a c file with the command line options strict and gnu is an error See also gnu on page 2 44 no strict on page 2 84 GNU languag
88. not rely on the implementation details of this behavior because it might change in future releases 5 2 2 Tentative arrays The ADS v1 2 and RVCT v1 2 C compilers enabled you to use tentative that is incomplete array declarations for example int a You cannot use tentative arrays when compiling C with the RVCT v2 x compilers or above 5 2 3 Old style C parameters in C functions The ADS v1 2 and RVCT v1 2 C compilers enabled you to use old style C parameters in C functions That is void f x int x ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved 5 13 Non Confidential C and C Implementation Details 5 2 4 In the RVCT v2 x compilers or above you must use the anachronisms compiler option if your code contains any old style parameters in functions The compiler warns you if it finds any instances Anachronisms The following anachronisms are accepted when you enable anachronisms using the anachronisms option overload is permitted in function declarations It is accepted and ignored Definitions are not required for static data members that can be initialized using default initialization The anachronism does not apply to static data members of template classes because these must always be defined The number of elements in an array can be specified in an array delete operation The value is ignored A single operator and operator function can be used to overload
89. or address reference uses the imported symbol The dllimport attribute can be used on extern functions and variables See also __declspec dllexport on page 4 24 4 2 3 declspec noinline The __declspec noinline attribute suppresses the inlining of a function at the call points of the function Note This declspec attribute has the function attribute equivalent __attribute__ noinline See also pragma no_ inline on page 4 56 attribute noinline on page 4 32 4 2 4 declspec noreturn ARM DUI 0348A The __declspec noreturn attribute asserts that a function never returns Note This declspec attribute has the function attribute equivalent __attribute__ noreturn Usage Use this attribute to reduce the cost of calling a function that never returns such as exit If a noreturn function returns to its caller the behavior is undefined Copyright O 2007 2010 ARM Limited All rights reserved 4 25 Non Confidential Compiler specific Features Restrictions The return address is not preserved when calling the noreturn function This limits the ability of a debugger to display the call stack Example __declspec noreturn void overflow void never return on overflow int negate int x if x 0x80000000 overflow return x See also attribute noreturn on page 4 33 4 2 5 declspec nothrow 4 26 The __declspec nothrow attribute assert
90. or less in size Syntax bss_threshold num Where num is either 0 place small global ZI data items in ZI data sections 8 place small global ZI data items in RW data sections Default If you do not specify a bss threshold option the compiler assumes bss_threshold 8 Copyright 2007 2010 ARM Limited All rights reserved 2 11 Non Confidential Compiler Command line Options 2 1 11 C Usage In the current version of RVCT the compiler might place small global ZI data items in RW data sections as an optimization In RVCT 2 0 1 and earlier small global ZI data items were placed in ZI data sections by default Use this option to emulate the behavior of RVCT 2 0 1 and earlier with respect to the placement of small global ZI data items in ZI data sections Note Selecting the option bss_threshold instructs the compiler to place all small global ZI data items in the current compilation module in a ZI data section To place specific variables in a ZI data section use attribute zero init a specific ZI data section use a combination of __attribute section __ and attribute zero init Example int globl glob2 ZI bss in RVCT 2 0 1 and earlier RW data in RVCT 2 1 and later Compiling this code with bss_threshold 0 places glob1 and glob2 in a ZI data section See also pragma arm section section_sort_list on page 4 50 attribute section on pag
91. page 4 64 in the Assembler Guide 4 7 30 rev This intrinsic inserts a REV instruction or an equivalent code sequence into the instruction stream generated by the compiler It enables you to convert a 32 bit big endian data value into a little endian data value or a 32 bit little endian data value into big endian data value from within your C or C code 4 82 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler specific Features Note The compiler introduces REV automatically when it recognizes certain expressions Syntax unsigned int __rev unsigned int val Where val is an unsigned int Return value The __rev intrinsic returns the value obtained from val by reversing its byte order See also REV REV16 REVSH and RBIT on page 4 64 in the Assembler Guide 4 7 31 return address This intrinsic returns the return address of the current function Syntax unsigned int return address void Return value The return address intrinsic returns the value of the link register that is used in returning from the current function Restrictions The return address intrinsic does not affect the ability of the compiler to perform optimizations such as inlining tail calling and code sharing Where optimizations are made the value returned by return address reflects the optimizations performed No optimization When no optimizations are performed th
92. permitted redirections are 0 filename Reads stdin from filename lt filename Reads stdin from filename 1 filename Writes stdout to filename Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential B 1 3 Identifiers B 1 4 Characters B 1 5 Integers Standard C Implementation Definition gt filename Writes stdout to filename 2 gt filename Writes stderr to filename 2 gt amp 1 Writes stderr to the same place as stdout gt amp file Writes both stdout and stderr to filename gt gt filename Appends stdout to filename gt gt amp filename Appends both stdout and stderr to filename To redirect stdin stdout and stderr on the target you must define pragma import _main_redirection File redirection is done only if either the invoking operating system supports it the program reads and writes characters and has not replaced the C library functions fputc and fgetc See Character sets and identifiers on page 5 2 for more information See Character sets and identifiers on page 5 2 for more information See Integer on page 5 5 for more information B 1 6 Floating point See Float on page 5 5 for more information B 1 7 Arrays and pointers B 1 8 Registers ARM DUI 0348A See Arrays and pointers on page 5 5 for more information Using the ARM compiler you can declare any number of local objects to have the storage class register Copyright O 2007 20
93. q0 16 q0 q0 ARM DUI 0348A Using NEON Support uint32x4x2 t vuzpq u32 uint32x4 t a uint32x4 t b VUZP 32 q0 q0 float32x4x2 t vuzpq f32 float32x4 t a float32x4 t b VUZP 32 q0 q0 poly8x16x2 t vuzpq p8 poly8x16 t a poly8x16 t b NUZP 8 q0 q0 poly16x8x2_t vuzpq_p16 poly16x8_t a poly16x8_t b VUZP 16 q0 q0 E 3 31 Vector reinterpret cast operations In some situations you might want to treat a vector as having a different type without changing its value A set of intrinsics is provided to perform this type of conversion Syntax vreinterpret q _dsttype_srctype Where q Specifies that the conversion operates on 128 bit vectors If it is not present the conversion operates on 64 bit vectors dsttype Represents the type to convert to srctype Represents the type being converted Example The following intrinsic reinterprets a vector of four signed 16 bit integers as a vector of four unsigned integers uintl6x4 t vreinterpret_u16_s16 int16x4_t a The following intrinsic reinterprets a vector of four 32 bit floating point values integers as a vector of four signed integers int8x16 t vreinterpretq s8 f32 float32x4 t a These conversions do not change the bit pattern represented by the vector ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved E 59 Non Confidential Using NEON Support E 60 Copyright O 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential
94. reserved ARM DUI 0348A Non Confidential Compiler specific Features int32 t foo int32 t a int32 t b jint32_t c d e f Overflow 0 set global overflow flag c CL add a b C saturating add d asm L add a b assembly language saturating add e __qadd a b ARM intrinsic saturating add f L_add a b ETSI saturating add return Overflow 1 c d e f returns 1 unless overflow See also 4 7 48 C55xintrinsics the header file dspfns h for definitions of the ETSI basic operations as a combination of C code and intrinsics ETSI basic operations on page 3 6 in the Compiler User Guide ETSI Recommendation G 191 Software tools for speech and audio coding standardization ITU T Software Tool Library 2005 User s manual included as part of ETSI Recommendation G 191 ETSI Recommendation G723 1 Dual rate speech coder for multimedia communications transmitting at 5 3 and 6 3 kbit s ETSI Recommendation G 729 Coding of speech at 8 kbit s using conjugate structure algebraic code excited linear prediction CS ACELP The ARM compiler supports the emulation of selected TI C55x compiler intrinsics ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved 4 99 Non Confidential Compiler specific Features To make use of the TI C55x intrinsics in your own code include the standard header file c55x h The intrinsics supplied in c55x h are listed in Table 4 15 Table
95. rights reserved vClt s8 int8x8 t a int8x8 t b vclt s16 intl6x4 t a intl16x4 t b vClt s32 int32x2 t a int32x2 t b vclt f32 float32x2 t a float32x2 t b vclt u8 uint8x8 t a uint8x8 t b vclt ul6 uintl6x4 t a uintl6x4 t b vclt u32 uint32x2 t a uint32x2 t b vcltq s8 int8x16 t a int8x16 t b vcltq sl6 intl6x8 t a intl16x8 t b vcltq s32 int32x4 t a int32x4 t b vcltq f32 float32x4 t a float32x4 t b vcltq u8 uint8x16 t a uint8x16 t b vcltq ul6 uintl6x8 t a uintl6x8 t b vcltq u32 uint32x4 t a uint32x4 t b Non Confidential NCGE NCGE NCGT NCGT NCGT NCGT NCGT NCGT NCGT NCGT NCGT NCGT NCGT NCGT NCGT NCGT NCGT NCGT NCGT NCGT NCGT NCGT NCGT NCGT NCGT NCGT NCGT NCGT NCGT NCGT Using NEON Support F32 d 00 00 U8 00 00 d U16 00 d d U32 00 00 d S8 q0 q0 q0 S16 q0 q0 q0 332 00 q0 q0 F32 q0 q0 q0 U8 q0 q0 q0 U16 00 q0 q0 U32 00 q0 q0 S8 00 00 d S16 d d d S32 00 00 d F32 d dQ 00 U8 00 00 d U16 00 00 d U32 00 00 d S8 q0 00 q0 S16 00 q0 q0 S32 00 q0 q0 F32 q0 q0 q0 U8 q0 q0 q0 U16 q0 q0 q0 U32 00 q0 q0 S8 d d d S16 d d d S32 0
96. section section sort list pragma import symbol name pragma push pragma diag_default tag tag pragma noinline pragma no_ softfp_linkage pragma diag_error tag tag pragma no pch pragma unroll n pragma diag_remark tag tag pragma Onum pragma unroll_completely pragma diag_suppress tag tag pragma once pragma thumb pragma diag_warning tag tag pragma Ospace pragma no anon unions This pragma enables or disables support for anonymous structures and unions Default The default is pragma no anon unions Copyright O 2007 2010 ARM Limited All rights reserved Non Confidential 4 49 Compiler specific Features 4 6 2 4 6 3 4 50 pragma arm pragma arm See also Anonymous classes structures and unions on page 3 20 attribute transparent union on page 4 38 This pragma switches code generation to the ARM instruction set It overrides the thumb compiler option See also arm on page 2 7 thumb on page 2 86 pragma thumb on page 4 62 section section_sort_list This pragma specifies a section name to be used for subsequent functions or objects This includes definitions of anonymous objects the compiler creates for initializations Note You can use __attribute__ section for functions or variables as an alternative to pragma arm section Synta
97. shift right by constant vrshrn n si6 intl16x8 t a vrshrn n s32 int32x4 t a vrshrn n s64 int64x2 t a __ vrshrn n ul6 uint16x8 t a vrshrn n u32 uint32x4 t a vrshrn n u64 uint64x2 t a constrange 1 8 int b constrange 1 16 int b constrange 1 32 int b constrange 1 8 int b constrange 1 16 int b constrange 1 32 int b y y y y NRSHRN I16 d0 q0 8 NRSHRN I32 d0 q0 16 NRSHRN I64 d0 q0 432 NRSHRN I16 d0 q0 8 NRSHRN I32 d0 q0 16 NRSHRN I64 d0 q0 432 Vector rounding narrowing saturating shift right by constant vqrshrn n s16 intl16x8 t a vqrshrn n s32 int32x4 t a vqrshrn n s64 int64x2 t a __ vqrshrn n ul6 uint16x8 t a vqrshrn n u32 uint32x4 t a vqrshrn n u64 uint64x2 t a constrange 1 8 int b constrange 1 16 int b constrange 1 32 int b constrange 1 8 int b y y y y Vector widening shift left by constant vshll n s8 int8x8 t a __ vshll n si6 intl6x4 t a vshll n s32 int32x2 t a vshll n u8 uint8x8 t a __ vshll n ul6 uintl6x4 t a vshll n u32 uint32x2 t a constrange 0 7 int b constrange 0 15 int b constrange 0 31 int b constrange 0 7 int b y c y 3 lt E 3 13 Shifts with insert ARM DUI 0348A constrange 1 16 int b constrange 1 32 int b VQRSHRN S16 00 00 8 VQRSHRN S32 00 00 16 VQRSHRN S64 00 90 32 VQ
98. source and execution character sets Table 5 1 Character escape codes Escape sequence Char value Description a 7 Attention bell b 8 Backspace t 9 Horizontal tab n 10 New line line feed v 11 Vertical tab f 12 Form feed r 13 Carriage return xnn xnn ASCII code in hexadecimal nnn Onnn ASCII code in octal Characters of the source character set in string literals and character constants map identically into the execution character set Data items of type char are unsigned by default They can be explicitly declared as signed char or unsigned char the signed chars option can be used to make the char signed the unsigned chars option can be used to make the char unsigned Note Care must be taken when mixing translation units that have been compiled with and without the un signed chars option and that share interfaces or data structures The ARM ABI defines char as an unsigned byte and this is the interpretation used by the C libraries supplied with RVCT Copyright O 2007 2010 ARM Limited All rights reserved 5 8 Non Confidential C and C Implementation Details No locale is used to convert multibyte characters into the corresponding wide characters for a wide character constant This is not relevant to the generic implementation 5 1 2 Basic data types This section describes how the basic data types are implemented in ARM C and C Size
99. specific Features attribute noinline on page 4 32 4 6 13 pragma no pch This pragma suppresses PCH processing for a given source file See also pch on page 2 70 Precompiled header files on page 2 16 in the Compiler User Guide 4 6 14 pragma Onum 4 6 15 pragma once ARM DUI 0348A This pragma changes the optimization level Syntax pragma Onum Where num is the new optimization level The value of num is 0 1 2 or 3 See also Onum on page 2 66 This pragma enables the compiler to skips subsequent includes of that header file pragma once is accepted for compatibility with other compilers and enables you to use other forms of header guard coding However it is preferable to use i fndef and define coding because this is more portable Example The following example shows the placement of a ifndef guard around the body of the file with a define of the guard variable after the ifndef ifndef FILE_H define FILE_H pragma once optional Copyright 2007 2010 ARM Limited All rights reserved 4 57 Non Confidential Compiler specific Features body of the header file endif The pragma once is marked as optional in this example This is because the compiler recognizes the ifndef header guard coding and skips subsequent includes even if pragma once is absent 4 6 16 pragma Ospace This pragma instructs the compiler to perform optimizations to reduce image si
100. specified file The options read from the file are added to the current command line Via commands can be nested within via files Syntax via filename Where filename is the name of a via file containing options to be included on the command line Example Given a source file main c a via file apcs txt containing the line Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 2 1 123 no vla ARM DUI 0348A Compiler Command line Options apcs rwpi no lower rwpi via L apcs txt and a second via file L apcs txt containing the line L rwpi L callgraph compiling main c with the command line armcc main c L o main axf via apcs txt compiles main c using the command line armcc no lower rwpi apcs rwpi L rwpi L callgraph L o main axf main c See also Appendix A Via File Syntax Reading compiler options from a file on page 2 10 in the Compiler User Guide This option enables or disables support for variable length arrays Default C90 and Standard C do not support variable length arrays by default Select the option vla to enable support for variable length arrays in C90 or Standard C Variable length arrays are supported both in Standard C and the GNU compiler extensions The option vla is implicitly selected either when the source language is C99 or the option gnu is specified Example size t arr size int n char array n v
101. t b float32 t c NMLA F32 00 dO dO 0 vmlag n si6 intl6x8 t a intl6x8 t b intl16 t c WLA I16 q0 q0 d0 0 vmlaq n s32 int32x4 t a int32x4 t b int32 t C WLA I32 q0 q0 d0 0 vmlaq n ul6 uintl16x8 t a uintl6x8 t b 16 t c WLA I16 q0 q0 00 0 vmlag n u32 uint32x4 t a uint32x4_t b uint32 t c NMLA I32 q0 q0 dO 0 t vmlaq n f32 float32x4 t a float32x4 t b float32 t c WLA F32 q0 q0 dO 0 Vector widening multiply accumulate with scalar vmlal n s16 int32x4 t a intl6x4 t b int16 t c NMLAL S16 q0 d 000 vmlal n s32 int64x2 t a int32x2 t b int32 t C NMLAL S32 q0 d 0010 vmlal n ul6 uint32x4 t a uintl6x4 t b uintl16 t c NMLAL U16 q0 d 000 vmlal n u32 uint64x2 t a uint32x2 t b uint32 t c NMLAL U32 q0 d dO 0 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Using NEON Support Vector widening saturating doubling multiply accumulate with scalar int32x4 t vqdmlal n sl6 int32x4 t a intl16x4 t b intl16 t c VQDMLAL S16 00 d 00 0 int64x2 t vqdmlal n s32 int64x2 t a int32x2 t b int32 t C VQDMLAL S32 q0 d 00 0 Vector multiply subtract with scalar intl6x4_t vmls n sl6 intl6x4 t a intl6x4 t b intl16 t c MLS I16 00 00 dO 0 int32x2 t vmls n s32 int32x2 t a int32x2 t b int32 t c MLS 132 00 00 000 uintl6x4 t wvmls n ul6 uintl6x4 t a uintl16x4 t b uin
102. t b uint32x2 t C vabaq s8 int8x16 t a int8x16 t b int8x16 t c vabaq sl6 intl6x8 t a int16x8 t b int16x8 t c vabaq s32 int32x4 t a int32x4 t b int32x4 t C uint8x16 t vabaq u8 uint8x16 t a uint8x16 t b uint8x16 t c uintl16x8 t vabaq ul6 uintl6x8 t a uintl6x8 t b uint16x8_t c VABA uint32x4 t vabaq u32 uint32x4 t a uint32x4 t b uint32x4 t c VABA VABA NABA VABA VABA VABA VABA VABA VABA NABA VABA Absolute difference and accumulate long vabal s8 intl16x8 t a int8x8 t b int8x8 t c vabal_s16 int32x4_t a intl6x4 t b intl6x4 t C vabal s32 int64x2 t a int32x2_t b int32x2 t C uintl6x8 t vabal u8 uintl6x8 t a uint8x8 t b uint8x8 t c S8 d0 d0 d0 S16 d0 d0 d0 S532 d0 d0 d0 U8 d0 d0 d0 U16 d0 d0 d0 U32 00 00 00 S8 q0 q0 q0 316 q0 q0 q0 32 q0 q0 q0 U8 q0 q0 q0 U16 q0 q0 q0 U32 q0 q0 q0 VABAL S8 q0 d0 d0 VABAL S16 q0 d0 d0 VABAL S32 q0 d0 d0 VABAL U8 q0 d0 d0 uint32x4 t vabal ul6 uint32x4 t a uintl6x4 t b uintl6x4 t c VABAL U16 q0 d0 d0 uint64x2_t vabal u32 uint64x2 t a uint32x2 t b uint32x2 t c VABAL U32 q0 d0 d0 These intrinsics provide maximum and minimum operations Copyright O 2007 2010 ARM Limited All rights reserved Non Confidential Using NEON Support vmax gt Vr i Va i gt Vb i Vali Vb i int8x8 t vmax s8 int8x8 t a int8x8 t b MMAX S8 d0 d0 d0 intl6x4_t vmax_sl6 int16x4_t
103. t const ptr uint8x8x2_t src lane constrange 0 7 int VLD2 8 100 0 d1 0 rd uintl6x4x2 t vild2 lane u16 transfersize 2 uint16_t const ptr uintl6x4x2 t src int lane constrange 0 3 NLD2 16 100 0 d1 r0 uint32x2x2_t vld2_lane_u32 __transfersize 2 uint32 t const ptr uint32x2x2 t src int lane constrange 0 1 NLD2 32 100 0 d1 0 rd int8x8x2 t 1102 lane s8 transfersize 2 int8 t const ptr int8x8x2 t src lane constrange 0 7 int NLD2 8 100 0 d1 0 rd intl6x4x2 t vld2_lane_s16 __transfersize 2 int16_t const ptr intl6x4x2 t src lane constrange 0 3 int NLD2 16 100 0 d1 0 rd int32x2x2_t vld2_lane_s32 __transfersize 2 int32 t const ptr int32x2x2 t src lane constrange 0 1 int NLD2 32 100 0 d1 r0 float32x2x2 t 102 lane f32 transfersize 2 float32 t const ptr float32x2x2 t src __constrange 1 int lane NLD2 32 100 0 d1 r0 poly8x8x2 t vld2_lane_p8 __transfersize 2 poly8 t const ptr poly8x8x2 t src lane constrange 0 7 int NLD2 8 100 0 d1 r poly16x4x2_t vild2 lane pl16 transfersize 2 polyl6 t const ptr polyl6x4x2 t src int lane constrange 0 3 NLD2 16 100 0 d1 0 rd uint16x8x3 t vld3q_lane_u16 __transfersize 3 uint16_t const ptr uint16x8x3_t src __constrange 0 7 int lane VLD3 16 100 0 d2 0 d4 0 r0 uint32x4x3 t vl
104. t val VST1 8 d0 r0 vstl ul6 transfersize 4 uint16 t ptr uintl6x4 t val NST1 16 d0 r0 vstl u32 transfersize 2 uint32 t ptr uint32x2 t val NST1 32 d0 r0 vstl u64 transfersize 1 uint64 t ptr uint64x1_t val NST1 64 d0 r0 vstl s8 transfersize 8 int8 t ptr int8x8 t val NST1 8 d0 r0 vsti_s16 __transfersize 4 int16 t ptr intl6x4 t val vstlq lane u8 transfersize 1 uint8 t ptr uint8x16 t val NST1 16 d0 r0 vstl s32 transfersize 2 int32 t ptr int32x2 t val NST1 32 d0 r0 vstl s64 transfersize 1 int64 t ptr int64x1_t val NST1 64 d0 r0 vstl f32 transfersize 2 float32 t ptr float32x2 t val NST1 32 d0 r0 vstl p8 transfersize 8 poly8 t ptr poly8x8 t val NST1 8 d0 r0 vstl p16 transfersize 4 polyl6 t ptr poly16x4_t val NST1 16 d0 r0 yv NST1 8 d 0 r0 vstlq lane ul6 transfersize 1 uintl6 t ptr uintl6x8 t val Copyright O 2007 2010 ARM Limited All rights reserved Non Confidential hi constrange 15 int lane constrange 0 7 int lane ARM DUI 0348A void void void void void void void void void void void void void void void void void void void void Using NEON Support NST1 16 d 0 r0 vstlq lane u32 transfersize 1 uint32 t ptr uint32x4 t
105. tag on page 2 26 diag remark tag tag on page 2 27 diag_style armlidelgnu on page 2 27 diag_suppress tag tag on page 2 28 diag warning tag tag on page 2 30 errors filename on page 2 34 remarks on page 2 78 W on page 2 94 Chapter 5 Diagnostic Messages in the Compiler User Guide Copyright O 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Chapter 3 Language Extensions This chapter describes the language extensions supported by the ARM compiler and includes Preprocessor extensions on page 3 2 C99 language features available in C90 on page 3 5 C99 language features available in C and C90 on page 3 7 Standard C language extensions on page 3 10 Standard C language extensions on page 3 15 Standard C and standard C language extensions on page 3 19 GNU language extensions on page 3 25 For additional reference material on the ARM compiler see also Appendix B Standard C Implementation Definition Appendix C Standard C Implementation Definition Appendix D C and C Compiler Implementation Limits ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved 3 1 Non Confidential Language Extensions 3 1 3 1 1 3 2 Preprocessor extensions assert The compiler supports several extensions to the preprocessor including the assert preprocessing extensions of System V release 4 The assert preprocessing exte
106. tag tag on page 4 54 pragma diag_warning tag tag on page 4 54 Controlling the output of diagnostic messages on page 5 4 in the Compiler User Guide 4 6 5 pragma diag error tag tag This pragma sets the diagnostic messages that have the specified tags to Error severity 4 52 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler specific Features Syntax pragma diag error tag tag Where tag tag is a comma separated list of diagnostic message numbers specifying the messages whose severities are to be changed At least one diagnostic message number must be specified See also diag error tag tag on page 2 26 pragma diag default tag tag on page 4 51 pragma diag remark tag tag pragma diag suppress tag tag on page 4 54 pragma diag warning tag tag on page 4 54 Changing the severity of diagnostic messages on page 5 5 in the Compiler User Guide 4 6 6 pragma diag remark tag tag ARM DUI 0348A This pragma sets the diagnostic messages that have the specified tags to Remark severity pragma diag remark behaves analogously to pragma diag errors except that the compiler sets the diagnostic messages having the specified tags to Remark severity rather than Error severity Note Remarks are not displayed by default Use the remarks compiler option to see remark messages
107. tag tag on page 4 54 Suppressing diagnostic messages on page 5 6 in the Compiler User Guide 2 1 34 diag suppress optimizations This option suppresses diagnostic messages for high level optimizations Default By default optimization messages have Remark severity Specifying diag_suppress optimizations suppresses optimization messages Note Use the remarks option to see optimization messages having Remark severity Usage The compiler performs certain high level vector and scalar optimizations when compiling at the optimization level 03 for example loop unrolling Use this option to suppress diagnostic messages relating to these high level optimizations Example xints factorial int n int result 1 while n gt 0 result n ARM DUI 0348A Copyright 2007 2010 ARM Limited All rights reserved 2 29 Non Confidential Compiler Command line Options 2 1 35 2 30 return result Compiling this code with the options 03 Otime remarks diag_suppress optimizations suppresses optimization messages See also diag suppress tag tag on page 2 28 diag_warning optimizations on page 2 31 Onum on page 2 66 Otime on page 2 69 remarks on page 2 78 diag_warning tag tag This option sets the diagnostic messages that have the specified tags to Warning severity The diag_warning option behaves analogously to diag_errors except that the
108. the time the template is instantiated if the name is dependent When the option no dep name is selected the lookup of dependent names in templates can occur only at the time the template is instantiated That is the lookup of dependent names at the time the template is parsed is disabled Note The option no dep name is provided only as a migration aid for legacy source code that does not conform to the C standard Its use is not recommended Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options Mode This option is effective only if the source language is C Default The default 15 dep name Restrictions The option dep name cannot be combined with the option no parse templates because parsing is done by default when dependent name processing is enabled Errors When the options dep name and no parse templates are combined the compiler generates an error See also no parse templates on page 2 70 Template instantiation on page 5 15 2 1 27 depend filename ARM DUI 0348A This option instructs the compiler to write make file dependency lines to a file during compilation Syntax depend fi lename Where filename is the name of the dependency file to be output Restrictions If you specify multiple source files on the command line then any depend option is ignored No dependency file is generated in
109. this case Usage The output file is suitable for use by a make utility To change the output format to be compatible with UNIX make utilities use the depend format option Copyright O 2007 2010 ARM Limited All rights reserved 2 23 Non Confidential Compiler Command line Options See also s depend_format string list on page 2 55 md on page 2 60 2 1 28 depend_format string This option changes the format of output dependency files for compatibility with some UNIX make programs Syntax depend_format string Where string is one of unix unix escaped unix quoted Usage unix unix escaped unix quoted generate dependency file entries using UNIX style path separators is the same as unix but escapes spaces with is the same as unix but surrounds path names with double quotes On Windows systems depend format unix forces the use of UNIX style path names That is the UNIX style path separator symbol is used in place of On UNIX systems depend_format unix has no effect On Windows systems depend_format unix_escaped forces unix style path names and escapes spaces with On UNIX systems depend_format unix_escaped with escapes spaces with On Windows systems depend_format unix_quoted forces unix style path names and surrounds them with On UNIX systems depend_format unix_quoted surrounds path names with 2 24 Copyright 2007 2010 ARM Li
110. uint64x2 t a constrange 0 7 int b VSHL 18 d0 d0 0 constrange 0 15 int b VSHL I16 d0 d0 20 constrange 0 31 int b VSHL I32 d0 d0 20 constrange 0 63 int b VSHL I64 00 00 0 constrange 0 7 int b VSHL 18 d0 d0 0 constrange 0 15 int b VSHL I16 d0 d0 0 constrange 0 31 int b VSHL I32 00 00 0 constrange 0 63 int b VSHL I64 00 00 0 constrange 0 7 int b VSHL 18 q0 q0 0 constrange 0 15 int b VSHL I16 q0 q0 40 constrange 0 31 int b VSHL I32 q0 q0 40 constrange 0 63 int b VSHL I64 q0 q0 40 constrange 0 7 int b VSHL I8 q0 q0 40 constrange 0 15 int b VSHL I16 q0 q0 40 constrange 0 31 int b VSHL I32 q0 q0 40 constrange 0 63 int b VSHL I64 q0 q0 40 Vector rounding shift right by constant int8x8 t vrshr n s8 int8x8 t a __ intlox4 t vrshr_n_s16 int16x4_t a int32x2 t vrshr n s32 int32x2 t a int64x1 t vrshr_n_s64 int64x1_t a constrange 1 8 int b NRSHR S8 00 00 8 constrange 1 16 int b VRSHR S16 d 00 16 constrange 1 32 int b VRSHR S32 00 00 32 constrange 1 64 int b VRSHR S64 00 00 64 E 20 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential uint8x8 t int8x16 t intl6x8 t int32x4 t int64x2 t int8x8 t vsra n s8 int8x8 t a int8x8 t b __constrange 1 8 int c NSRA intl6x4 t vsra n sl6 intl6x4 t a intl6x4 t b __constrange 1 16 int c NSRA in
111. uintl6x8 t c VBSL uint32x4 t vbslq u32 uint32x4 t a uint32x4 t b uint32x4 t c VBSL uint64x2 t vbslq_u64 uint64x2_t a uint64x2 t b uint64x2 t c VBSL float32x4 t vbslq f32 uint32x4 t a float32x4 t b float32x4 t c VBSL poly8x16 t vbslq p8 uint8x16 t a poly8x16 t b poly8x16 t c NBSL polyl6x8 t vbslq_p16 uint16x8_t a poly16x8 t b poly16x8_t c VBSL E 3 30 Transposition operations ARM DUI 0348A This intrinsics provide transposition operations Transpose elments int8x8x2 t vtrn s8 int8x8 t a int8x8 t b intlo6x4x2 t vtrn sl6 intl6x4 t a intl6x4 t b int32x2x2 t vtrn s32 int32x2 t a int32x2 t b uint8x8x2 t vtrn u8 uint8x8 t a uint8x8 t b uint16x4x2_t vtrn ul6 uintl6x4 t a uintl6x4 t b d d0 da d dO dO d d0 dO d dO dO d d0 dO 00 dO dO 00 dO dO d d0 dO d dO dO d d0 dO d dO dO q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 VTRN 8 d0 d0 NTRN 16 d0 dO NTRN 32 d0 d0 NTRN 8 00 00 NTRN 16 d0 dO Copyright O 2007 2010 ARM Limited All rights reserved Non Confidential E 57 Using NEON Support E 58 uint32x2x2 t float32x2x2 t poly8x8x2 t polyl6x4x2 t int8x16x2 t intl6x8x2 t int32x4x2 t uint8x16x2 t uintl6x8x2 t uint32x4x2 t float32x4x2 t poly8x16x2 t polyl6x8x2 t vtrn u32 uint32x2 t a uint32x2 t b vtrn f32 float32x2 t a float32x2 t b
112. ul6 uintl6x4 t a uintl6x4 t b uintl16x4 t v __constrange 3 int 1 NMLA I16 dQ 00 000 vmla_lane_u32 uint32x2_t a uint32x2_t b uint32x2_t v __constrange 1 int 1 NMLA I32 d 00 dO 0 vmla lane f32 float32x2 t a float32x2 t b float32x2_t v __ NMLA F32 d 00 dO 0 vmlaq lane sl16 int16x8 t a intl16x8 t b intl6x4 t v __constrange 3 int 1 WLA I16 q0 q0 dolo vmlaq lane s32 int32x4 t a int32x4 t b int32x2 t v __constrange 1 int 1 NMLA I32 q0 q0 00 0 vmlaq lane ul6 uint16x8 t a uint16x8 t b uint16x4 t v __constrange Q 3 int 1 WLA I16 q0 q0 00 0 vmlaq lane u32 uint32x4 t a uint32x4 t b uint32x2 t v __constrange 1 int 1 NMLA I32 q0 q0 00 0 vmlaq lane f32 float32x4 t a float32x4 t b float32x2_t v __ NMLA F32 q0 q0 00 0 constrange 0 1 int 1 constrange 0 1 int 1 Vector widening multiply accumulate with scalar int32xX4 t vmlal lane s16 int32x4 t a intl6x4 t b intl16x4 t v __constrange Q 3 int 1 NMLAL S16 q0 d 00 0 int64x2 t vmlal lane s32 int64x2 t a int32x2 t b int32x2 t v constrange 0 1 int 1 VMLAL S32 q0 d 00 0 uint32x4 t vmlal lane ul6 uint32x4 t a uintl6x4 t b uintl6x4 t v __constrange 3 int 1 NMLAL U16 q0 d 00 0 uint64x2 t vmlal lane u32 uint64x2 t a uint32x2 t b uint32x2 t v __constrange 1 int 1 NMLAL U32 q0 d dO 0 Vector widening saturating doubling multiply accumulate with
113. unassert name unassert name token sequence Where name is a predicate name token sequence is an optional sequence of tokens If the token sequence is omitted all definitions of name are removed If the token sequence is included only the indicated definition is removed All other definitions are left intact See also assert on page 3 2 The preprocessing directive warning is supported Like the error directive this produces a user defined warning at compilation time However it does not halt compilation Restrictions The warning directive is not available if the strict option is specified If used it produces an error Copyright O 2007 2010 ARM Limited All rights reserved 3 3 Non Confidential Language Extensions 8 4 See also no_ strict on page 2 84 Copyright 2007 2010 ARM Limited All rights reserved Non Confidential ARM DUI 0348A Language Extensions 3 2 C99 language features available in C90 3 2 1 Il comments The compiler supports numerous extensions to the ISO C90 standard for example C99 style comments These extensions are available if the source language is C90 and you are compiling in non strict mode These extensions are not available if the source language is C90 and the compiler is restricted to compiling strict C90 using the strict compiler option Note Language features of Standard C and Standard C for example C style comments might
114. use the section attribute read only variables are placed in RO data sections read write variables are placed in RW data sections unless you use the zero init attribute In this case the variable is placed in a ZI section Note This variable attribute is a GNU compiler extension that is supported by the ARM compiler 4 44 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler specific Features Example in RO section const int descriptor 3 attribute section descr 1 2 3 in RW section long long rw 10 attribute section RW in ZI section long long altstack 10 attribute section STACK zero init 4 5 7 attribute transparent union The transparent union variable attribute attached to a function parameter which is a union means that the corresponding argument can have the type of any union member but the argument is passed as if its type were that of the first union member Note The C specification states that the value returned when a union is written as one type and read back with another is undefined Therefore a method of distinguishing which type a transparent union is written in must also be passed as an argument Note This variable attribute is a GNU compiler extension that is supported by the ARM compiler Note You can also use this attribute on a typedef for a union dat
115. value ALIGNOF type returns the alignment requirement for the type type or 1 if there is no alignment requirement ALIGNOF expr returns the alignment requirement for the type of the lvalue expr or if there is no alignment requirement The lvalue itself is not evaluated Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler specific Features Example typedef struct s foo int i short j foo typedef packed struct s bar 1 int i short j bar return __ALIGNOF struct s foo returns 4 return __ALIGNOF foo returns 4 return __ALIGNOF bar returns 1 See also alignof on page 4 3 4 1 4 asm This keyword is used to pass information from the compiler to the ARM assembler armasm The precise action of this keyword depends on its usage Usage Embedded assembler The asm keyword can be used to declare or define an embedded assembly function For example __asm void my strcpy const char src char dst See Embedded assembler on page 6 17 in the Compiler User Guide for more information Inline assembler The asm keyword can be used to incorporate inline assembly into a function For example int gadd int i int j int res asm QADD res i j return res Seelnline assembler on page 6 2 in the Compiler User Guide for more information ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved 4 5 Non Confidential
116. vec __constrange 3 int lane NMOV 16 d0 0 r0 int32x2 t vset lane s32 int32 t value int32x2 t vec __constrange 1 int lane NMOV 32 d0 0 r0 poly8x8 t vset lane p8 poly8 t value poly8x8 t vec constrange 0 7 int lane NMOV 8 d0 0 r0 polyl6x4 t vset lane pl6 polyl6 t value poly16x4_t vec constrange 0 3 int lane NMOV 16 d0 0 r0 float32x2_t vset lane f32 float32 t value float32x2 _t vec constrange 0 1 int lane NMOV 32 00 0 0 uint8x16 t vsetq lane u8 uint8 t value uint8x16 t vec __constrange 15 int lane NMOV 8 d0 0 r0 uintl6x8 t vsetq lane ul6 uintl6 t value uintl16x8 t vec constrange 0 7 int lane NMOV 16 d0 0 r0 uint32x4 t vsetq lane u32 uint32 t value uint32x4 t vec __constrange 0 3 int lane NMOV 32 d0 0 r0 int8x16 t vsetq lane s8 int8 t value int8x16 t vec __constrange 15 int lane NMOV 8 d0 0 r0 intl6x8 t vsetq lane sl6 intl6 t value intl6x8 t vec constrange 0 7 int lane NMOV 16 d0 0 r0 int32xX4 t vsetq lane s32 int32 t value int32x4 t vec constrange 0 3 int lane ARM DUI 0348A Copyright 2007 2010 ARM Limited All rights reserved E 41 Non Confidential Using NEON Support 0V 32 d0 0 r0 vec __constrange 0 15 int lane MOV 8 d0 rQ t vec constrange 0 7 int lane OV 16 d0 0 r0 4 t vec __constrange 0 3 int lane 0V 32 d0 0 r0 ec constrange 0 0 int lane OV d0 r0 r0 vec
117. vmvng sl6 intl6x8 t a VMVN q0 q0 int32x4 t vmvng s32 int32x4 t a q0 q0 uint8x16 t vmvng u8 uint8x16 t a VMVN q0 q0 uintl6x8 t vmvng ul6 uintl6x8 t a VMVN q0 q0 uint32x4 t vmvng u32 uint32x4 t a VMVN q0 q0 poly8x16 t vmvnq p8 poly8x16 t a VMVN q0 q0 Bitwise and int8x8 t s8 int8x8 t a int8x8 t b VAND d0 d0 d0 int16x4_t vand_s16 int16x4_t a intl6x4 t b VAND d0 d0 d0 int32x2 t vand s32 int32x2 t a int32x2 t b VAND d0 d0 d0 int64xl t vand s64 int64x1l t a int64x1l t b VAND d0 d0 d0 uint8x8 t vand u8 uint8x8 t a uint8x8 t b VAND d0 d0 d0 uintl6x4 t vand ul6 uintl6x4 t a uintl6x4 t b VAND dQ dQ d0 uint32x2 t vand u32 uint32x2 t a uint32x2 t b VAND dQ dQ d0 uint64x1l t vand u64 uint64x1l t a uint64x1_t b VAND dQ dQ d0 int8x16 t vandq s8 int8x16 t a int8x16 t b VAND q0 q0 q0 intl6x8 t vandqg_s16 int16x8_t a intl6x8 t b VAND q0 q0 q0 int32x4 t vandg_s32 int32x4_t a int32x4 t b VAND q0 q0 q0 int64x2 t vandq s64 int64x2 t a int64x2 t b VAND q0 q0 q0 uint8x16 t vandq u8 uint8x16 t a uint8x16 t b VAND q0 q0 q0 uintl6x8 t vandq ul6 uintl6x8 t a uintl6x8 t b VAND q0 q0 q0 uint32x4 t vandq u32 uint32x4 t a uint32x4 t b VAND q0 q0 q0 uint64x2 t vandq u64 uint64x2 t a uint64x2 t b VAND q0 q0 q0 Bitwise or int8x8 t vorr s8 int8x8 t a int8x8 t b NOR d0 d0 d0 int16x4_t vorr sl6 intl6x4 t a intl6x4 t b
118. you do not specify a min array alignment option the compiler assumes min array alignment 1 Example Compiling the following code with min array alignment 8 gives the alignment described in the comments char arr c1 1 alignment char 61 alignment See also align on page 4 2 __ALIGNOF__ on page 4 4 no multibyte chars This option enables or disables processing for multibyte character sequences in comments string literals and character constants Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options Default The default is no multibyte chars Usage Multibyte encodings are used for character sets such as the Japanese Shift Japanese Industrial Standard Shift JIS See also locale lang_country on page 2 57 message_locale lang_country codepage on page 2 61 2 1 84 no_ multifile ARM DUI 0348A This option enables or disables multifile compilation When multifile is selected the compiler performs optimizations across all files specified on the command line instead of on each individual file The specified files are compiled into one single object file The combined object file is named after the first source file you specify on the command line To specify a different name for the combined object file use the o filename option An empty object file is created for each subsequent source fil
119. 0 The inc data column gives the size of constants string literals and other data items used as part of the code The Code column shown in the example includes this value See also list on page 2 55 Code metrics on page 4 11 in the Compiler User Guide fromelf command syntax on page 8 3 in the Linker Guide 2 1 66 no inline ARM DUI 0348A This option enables or disables the inlining of functions Disabling the inlining of functions can help to improve the debug illusion When the option inline is selected the compiler considers inlining each function Compiling your code with inline does not guarantee that all functions are inlined See When is it practical for the compiler to inline on page 4 19 in the Compiler User Guide for more information about how the compiler decides to inline functions When the option no inline is selected the compiler does not attempt to inline functions other than functions qualified with __forceinline Default The default is inline See also no_ autoinline on page 2 9 forceinline on page 2 39 Onum on page 2 66 Ospace on page 2 68 Otime on page 2 69 __forceinline on page 4 6 inline on page 4 9 Copyright O 2007 2010 ARM Limited All rights reserved 2 49 Non Confidential Compiler Command line Options Using linker feedback on page 2 25 in the Compiler User Guide Inlining on page 4 19 in the Compiler User Guide 2 1 67
120. 0 Vector saturating doubling long multiply int32x4 t vqdmull s16 intl6x4 t a intl6x4 t b VQDMULL S16 q0 d0 d0 int64x2 t vqdmull s32 int32x2 t a int32x2 t b VQDMULL S32 q0 d0 d0 E 3 3 Subtraction ARM DUI 0348A These intrinsics provide operations including subtraction Copyright O 2007 2010 ARM Limited All rights reserved Non Confidential E 9 Using NEON Support Vector subtract int8x8 t vsub s8 int8x8 t a int8x8 t b NSUB I8 d0 d0 d0 intl6x4_t vsub_s16 int16x4_t a intl6x4 t b NSUB I16 d0 d0 d0 int32xX2 t vsub s32 int32x2 t a int32x2 t b NSUB I32 d0 d0 d0 int64xl t vsub s64 int64x1l t a int64x1l t b NSUB I64 d0 d0 d0 float32x2 t vsub f32 float32x2 t a float32x2 t b VSUB F32 d0 d0 d0 uint8x8 t vsub_u8 uint8x8_t a uint8x8 t b NSUB I8 d0 d0 d0 uint16x4_t vsub ul6 uintl6x4 t a uintl6x4 t b NSUB I16 d0 d0 d0 uint32x2 t vsub u32 uint32x2 t a uint32x2 t b NSUB I32 d0 d0 d0 uint64xl t vsub u64 uint64x1l t a uint64x1l t b NSUB I64 d0 d0 d0 int8x16 t vsubq s8 int8x16 t a int8x16 t b NSUB I8 qQ q0 q0 intl6x8 t vsubq_s16 int16x8_t a int16x8_t b VSUB 116 q0 q0 q0 int32x4 t vsubq s32 int32x4 t a int32x4 t b VSUB 132 q0 q0 q0 int64x2 t vsubq s64 int64x2 t a int64x2 t b VSUB 164 q0 q0 q0 float32x4 t vsubq f32 float32x4 t a float32x4 t b VSUB F32 q0 q0 q0 uint8x16_t vsubq u8 uint8x16 t a uint8x16 t b NSUB I8 qQ q0 q0 uintl6x8
121. 0 00 d F32 d dQ 00 U8 00 00 d U16 00 00 d U32 00 00 d S8 q0 qd q0 S16 00 q0 q0 S32 00 q0 q0 F32 q0 q0 q0 U8 q0 q0 q0 U16 q0 q0 q0 U32 00 q0 q0 Using NEON Support E 3 5 Vector compare absolute greater than or equal uint32x2 t vcage f32 float32x2 t a float32x2 t b uint32x4 t vcageq f32 float32x4 t a float32x4 t b VACGE Vector compare absolute less than or equal uint32x2 t vcale f32 float32x2 t a float32x2 t b uint32x4 t vcaleq f32 float32x4 t a float32x4 t b VACGE Vector compare absolute greater than uint32x2 t vcagt f32 float32x2 t a float32x2 t b uint32x4 t vcagtq f32 float32x4 t a float32x4 t b VACGT Vector compare absolute less than uint32x2 t vcalt f32 float32x2 t a float32x2 t b uint32x4 t vcaltq f32 float32x4 t a float32x4 t b VACGT VACGE VACGT VACGT F32 F32 F32 F32 F32 F32 F32 F32 do 00 do q0 q0 00 do d do q0 q0 00 do dO do q0 q0 00 do dO do q0 q0 00 Vector test bits uint8x8 t uintl6x4 t uint32x2 t uint8x8 t uintl6x4 t uint32x2 t uint8x8 t uint8x16 t uint16x8_t uint32x4_t uint8x16 t uint16x8_t uint32x4_t uint8x16 t Absolute difference vtst s8 int8x8 t a int8x8 t b vtst sl6 intl6x4 t a intl16x4 t b vtst s32 int32x2 t a int32x2 t b vtst u8 uint8x8 t a uint8x8 t b vtst ul6 uintl6x4 t a uintl6x4 t b vtst u32 uint32x2 t a uint32x2
122. 00 0 d1 0 d2 0 r0 intl6x4x3 vld3 lane s16 transfersize 3 intl6 t const ptr intl6x4x3 t src constrange 0 3 int lane y NED3 16 100 0 d1 0 d2 r0 int32x2x3 t vld3 lane s32 transfersize 3 int32 t const ptr int32x2x3 t src constrange 0 1 int lane y VLD3 32 100 0 d1 0 d2 0 3 rd float32x2x3 t v1d3 lane f32 transfersize 3 float32 t const ptr float32x2x3 t src __constrange 1 int lane VLD3 32 100 0 d1 0 d2 rd poly8x8x3 t v1d3 lane 08 transfersize 3 poly8_t const ptr poly8x8x3 t src constrange 0 7 int lane VLD3 8 100 0 d1 0 d2 rd polyl6x4x3 t vld3_lane_p16 __transfersize 3 poly16_t const ptr poly16x4x3_t src int lane constrange 0 3 NLD3 16 d0 0 d1 d2 r0 uintl6x8x4 t vld4q lane ul6 transfersize 4 uint16_t const ptr uintl6x8x4 t src constrange 0 7 int lane VLD4 16 100 0 d2 0 d4 0 d6 r0 uint32x4x4 t vld4q lane u32 transfersize 4 uint32 t const ptr uint32x4x4 t src __constrange 0 3 int lane VLD4 32 d0 0 d2 0 d4 0 d6 r0 intl6x8x4 t vld4q lane s16 transfersize 4 int16 t const ptr intl6x8x4 t src constrange 0 7 int lane VLD4 16 d0 0 d2 0 d4 0 d6 0 r0 int32x4x4 vld4q lane s32 transfersize 4 int32 t const ptr int32x4x4 t src constrange 0 3 int lane NLD4 32 100 0 d2 0 d4 0 d6 rd float
123. 007 2010 ARM Limited All rights reserved Non Confidential Using NEON Support E 31 Using NEON Support NLD4 8 100 02 04 06 r0 poly16x8x4_t vld4q_p16 __transfersize 32 polyl6 t const ptr VLD4 16 100 02 04 d6 r0 uint8x8x4 t vld4_u8 __transfersize 32 uint8 t const ptr NLD4 8 100 01 d2 d3 r0 uintl6x4x4 t vld4_u16 __transfersize 16 uint16 t const ptr NLD4 16 100 01 d2 d3 r9 uint32x2x4 t vld4_u32 __transfersize 8 uint32 t const ptr NLD4 32 d0 01 02 d3 r0 uint64x1x4 t vld4_u64 __transfersize 4 uint64 t const ptr NLD1 64 100 d1 d2 d3 r9 int8x8x4 t vld4_s8 __transfersize 32 int8 t const ptr NLD4 8 100 01 d2 d3 r0 intl6x4x4 t vld4 s16 transfersize 16 intl16 t const ptr VLD4 16 100 01 d2 d3 r9 int32x2x4 t vld4 s32 transfersize 8 int32 t const ptr NLD4 32 100 01 02 d3 r0 int64x1x4_t vld4 s64 transfersize 4 int64 t const ptr VLD1 64 100 01 d2 d3 r0 float32x2x4 t vld4 f32 transfersize 8 float32 t const ptr NLD4 32 100 01 d2 d3 r0 poly8x8x4 t vld4_p8 __transfersize 32 poly8 t const ptr NLD4 8 100 d1 02 d3 r0 poly16x4x4_t vld4_p16 __transfersize 16 polyl6 t const ptr NLD4 16 100 01 02 d3 r0 uint8x8x2 t vld2 dup u8 transfersize 2 uint8 t const ptr NLD2 8 100 d1 r0 uintl6x4x2 t vld2_dup_u16 __transfersize 2 uint16 t const
124. 0348A The __value_in_regs qualifier instructs the compiler to return a structure of up to four integer words in integer registers or up to four floats or doubles in floating point registers rather than using memory __value_in_regs is a function qualifier It affects the type of a function Syntax __value_in_regs return type function name argument list Copyright 2007 2010 ARM Limited All rights reserved 4 19 Non Confidential Compiler specific Features Where return type is the type of a structure of up to four words in size Usage Declaring a function value in regs can be useful when calling functions that return more than one result Restrictions A C function cannot return a value in regs structure if the structure requires copy constructing If a virtual function declared as value in regs is to be overridden the overriding function must also be declared as value in regs If the functions do not match the compiler generates an error Errors Where the structure returned in a function qualified by value in regs is too big a warning is produced and the value in regs structure is then ignored Example typedef struct int64 struct unsigned int lo unsigned int hi int64 struct value in regs extern int64 struct mul64 unsigned a unsigned b See also value in regs on page 4 14 in the Compiler User Guide 4 1 19 __weak This keyword instructs the compiler
125. 0x14000 0 RW not ZI int x4 attribute at 0x16000 ZI See also Using at sections to place sections at a specific address on page 5 37 in the Linker Guide 4 5 3 attribute aligned 4 42 The aligned variable attribute specifies a minimum alignment for the variable or structure field measured in bytes Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler specific Features Note This variable attribute is a GNU compiler extension that is supported by the ARM compiler Example int Variable Attributes aligned 0 attribute aligned 16 aligned on 16 byte boundary short Variable Attributes aligned 1 3 attribute aligned aligns on 4 byte boundary for ARM See also e align on page 4 2 4 5 4 attribute deprecated The deprecated variable attribute enables the declaration of a deprecated variable without any warnings or errors being issued by the compiler However any access to a deprecated variable creates a warning but still compiles The warning gives the location where the variable is used and the location where it is defined This helps you to determine why a particular definition is deprecated Note This variable attribute is a GNU compiler extension that is supported by the ARM compiler Example extern int Variable Attributes deprecated 0 __attribute__ deprecated extern
126. 10 ARM Limited All rights reserved B 5 Non Confidential Standard C Implementation Definition B 1 9 Structures unions enumerations and bitfields B 1 10 Qualifiers The ISO IEC C standard requires the following implementation details to be documented for structured data types the outcome when a member of a union is accessed using a member of different type the padding and alignment of members of structures whether a plain int bitfield is treated as a signed int bitfield or as an unsigned int bitfield e the order of allocation of bitfields within a unit whether a bitfield can straddle a storage unit boundary the integer type chosen to represent the values of an enumeration type See Chapter 5 C and C Implementation Details for more information Unions See Unions on page 5 7 for information Enumerations See Enumerations on page 5 7 for information Padding and alignment of structures See Structures on page 5 8 for information Bitfields See Bitfields on page 5 10 for information An object that has a volatile qualified type is accessed if any word or byte or halfword on ARM architectures that have halfword support or it is read or written For volatile qualified objects reads and writes occur as directly implied by the source code in the order implied by the source code The effect of accessing a volatile qualified short is undefined on ARM architectures that do not have halfword support
127. 14 Loads and stores of a single vector Perform loads and stores of a single vector of some type E 24 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential uint8x16 t vldiq u8 transfersize 16 uintl6x8 t vldiq ul6 transfersize 8 uint32x4 vldiq u32 transfersize 4 uint64x2 t vldiq u64 transfersize 2 int8x16 t vldiq s8 transfersize 16 intl6x8 t vldiq s16 transfersize 8 int32x4 t vldiq s32 transfersize 4 int64x2_t vldiq s64 transfersize 2 float32x4 t vldiq f32 transfersize 4 poly8x16 t vldiq p8 transfersize 16 uint8 t const ptr VLD1 8 100 d1 r0 uintl6 t const ptr VLD1 16 d0 d1 r0 uint32 t const ptr VLD1 32 d0 d1 r0 uint64 t const ptr VLD1 64 100 d1 r0 int8 t const ptr VLD1 8 d d1 r0 intl6 t const MLD1 int32 t const MLD1 int64 t const MLD1 float32 t const MLD1 poly8 t const ptr 16 100 d1 r0 ptr 32 100 d1 r0 ptr 64 100 di r0 ptr 32 100 d1 r0 ptr Using NEON Support poly16x8 t uint8x8 t uintl6x4 t uint32x2 t uint64xl t int8x8 t intl6x4 t int32x2 t int64xl t float32x2_t poly8x8_t poly16x4_t uint8x16_t lane uintl6x8 t int lane ARM DUI 0348A VLD1 8 100 d1 r0 vldiq pl6 transfersize 8 poly16_t const ptr VLD1 16 d0 d1 r0 vidi u8 transfersize
128. 2 ad f N A double f also returns 0 N x The lookup of names in template instantiations does not conform to the rules in the standard in the following respects Although only names from the template definition context are considered for names that are not functions the lookup is not limited to those names visible at the point where the template is defined Functions from the context where the template is referenced are considered for all function calls in the template Functions from the referencing context are only visible for dependent function calls Argument dependent lookup When argument dependent lookup is enabled functions that are made visible using argument dependent lookup can overload with those made visible by normal lookup The standard requires that this overloading occur even when the name found by normal lookup is a block extern declaration The compiler does this overloading but in default mode argument dependent lookup is suppressed when the normal lookup finds a block extern This means a program can have different behavior depending on whether it is compiled with or without argument dependent lookup even if the program makes no use of namespaces For example struct A A operator A double void f A al A operator A int al 1 0 calls operator A double with arg dependent lookup enabled but otherwise calls operator A int Copyright 2007 2010 ARM Limi
129. 2 14 gnu on page 2 44 strict warnings Source language modes on page 1 3 in the Compiler User Guide 2 1 113 strict warnings ARM DUI 0348A This option enforces strict C or strict C depending on the choice of source language used The strict warnings option behaves similarly to strict except that the compiler issues warning messages in place of error messages when nonstandard features are used Errors When strict warnings is in force and a violation of the relevant ISO standard occurs the compiler normally issues a warning message The severity of diagnostic messages can be controlled in the usual way Note In some cases the compiler issues an error message instead of a warning when it detects something that is strictly illegal and terminates the compilation For example ifdef Super extern void Super __aeabi_idiv void intercept __aeabi_idiv endif Compiling this code with strict_warnings generates an error Copyright 2007 2010 ARM Limited All rights reserved 2 85 Non Confidential Compiler Command line Options Example void foo void long long i okay in non strict C90 Compiling this code with strict warnings generates a warning message Compilation continues even though the expression long long is strictly illegal See also Source language modes on page 1 3 c90 on page 2 13 c99 on page 2 13 cpp on page 2 1
130. 2 92 This option instructs the compiler to split LDM and STM instructions into two or more LDM or STM instructions When split 1dm is selected the maximum number of register transfers for an LDM or STM instruction is limited to five for all STMs five for LDMs that do not load the PC four for LDMs that load the PC Where register transfers beyond these limits are required multiple LDM or STM instructions are used Note This option is deprecated and will be removed in the next release Usage The split_1dm option can be used to reduce interrupt latency on ARM systems that do not have a cache or a write buffer for example a cacheless ARM7TDMI use zero wait state 32 bit memory Note Using split_1dm increases code size and decreases performance slightly Restrictions Inline assembler LDM and STM instructions are split by default when split_1dm is used However the compiler might subsequently recombine the separate instructions into an LDM or STM VEP FLDM or FSTM instructions are not split when split_1dm is used Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options Some target hardware does not benefit from code built with split_1dm For example Ithas no significant benefit for cached systems or for processors with a write buffer thas no benefit for systems with non zero wait state m
131. 2 u8 uint8x8 t vec uint16x4_t vrev32 ul6 uintl6x4 t vec poly8x8 t vrev32 p8 poly8x8 t vec int8x16 t vrev32q s8 int8x16 t vec intl6x8 t vrev32q_s16 int16x8_t vec uint8x16_t vrev32q u8 uint8x16 t vec uintl6x8 t vrev32q ul6 uintl16x8 t vec poly8x16 t vrev32q p8 poly8x16 t vec int8x8 t vrev16 s8 int8x8 t vec uint8x8 t vrev16 u8 uint8x8 t vec poly8x8 t vrevi6 p8 poly8x8 t vec int8x16 t vrev16q s8 int8x16 t vec uint8x16_t vrevl6q u8 uint8x16 t vec poly8x16 t vrevl6q_p8 poly8x16_t vec E 3 28 Other single operand arithmetic These intrinsics provide other single operand arithmetic NREV64 VREV64 VREV64 NREV64 NREV64 NREV64 NREV64 NREV64 NREV64 NREV64 NREV64 NREV64 NREV64 VREV64 NREV64 NREV64 NREV64 NREV64 NREV32 NREV32 NREV32 NREV32 NREV32 NREV32 VREV32 NREV32 NREV32 NREV32 NREV16 NREV16 NREV16 NREV16 REV16 NREV16 E 52 Copyright 2007 2010 ARM Limited All rights reserved Non Confidential 8 00 00 16 d0 d0 32 00 00 8 00 00 16 00 00 32 00 00 8 00 00 16 00 00 32 00 00 8 q0 q0 16 q0 q0 32 q0 q0 8 q0 q0 16 q0 q0 32 q0 q0 8 q0 q0 16 q0 q0 32 q0 q0 8 00 00 16 d0 d0 8 d0 d0 16 d0 d0 8 d0 d0 8 q0 q0 16 q0 q0 8 q0 q0 16 q0 q0 ARM DUI 0348A ARM DUI 0348A Absolute Vd i Va i int8x8 t vabs s8 int8x
132. 29 in the Assembler Guide 4 7 2 __builtin_clz 4 64 This builtin function inserts a CLZ instruction or an equivalent code sequence into the instruction stream generated by the compiler It is functionally equivalent to the intrinsic __c1z except that the return type is int instead of unsigned char Note This builtin function is a GNU compiler extension that is supported by the ARM compiler See also __clz on page 4 69 CLZ on page 4 53 in the Assembler Guide Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler specific Features 4 7 3 builtin constant p This builtin function determines if a value is known to be constant at compile time Note This builtin function is a GNU compiler extension that is supported by the ARM compiler Mode Supported in GNU mode only Syntax int builtin constant p Where is the argument whose value is to be tested Return value builtin constant p returns the integer 1 if the argument is known to be a compile time constant and O if it is not known to be a compile time constant Restrictions A return value of 0 does not indicate that the value is not a constant but that the compiler cannot prove it is a constant with the specified value of the 0 option See also Onum on page 2 66 4 7 4 __builtin_expect ARM DUI 0348A This intrinsic provides the compiler with branch prediction information
133. 2x2x2 t val VST2 32 d0 d1 r0 ptr int64x1x2_t val VST1 64 100 d1 r0 x ptr float32x2x2 t val NST2 32 d0 d1 r0 ptr poly8x8x2 t val NST2 8 100 d1 r0 ptr polyl6x4x2 t val VST2 16 d0 d1 r0 ptr uint8x16x3_t val NST3 8 d0 02 d4 r9 t ptr uint16x8x3 t val NST3 16 d0 02 d4 r9 t ptr uint32x4x3_t val NST3 32 d0 02 d4 r9 ptr int8x16x3 t val NST3 8 d0 d2 d4 r9 ptr int16x8x3 t val NST3 16 100 02 d4 r9 ptr int32x4x3 t val NST3 32 d0 02 d4 r9 t ptr float32x4x3 t val NST3 32 d0 02 d4 r9 ptr poly8x16x3 t val NST3 8 d0 d2 d4 r9 t ptr polyl16x8x3 t val NST3 16 100 02 d4 r9 ptr uint8x8x3_t val NST3 8 100 01 d2 r9 ptr uintl6x4x3_t val NST3 16 100 01 d2 r9 ptr uint32x2x3 t val NST3 32 100 01 d2 r9 ptr uint64x1x3 t val NST1 64 100 01 d2 r9 ptr int8x8x3 t val NST3 8 100 01 d2 r9 ptr intl6x4x3 t val NST3 16 100 01 d2 r9 ptr int32x2x3 t val NST3 32 d0 01 d2 r9 ptr int64x1x3_t val NST1 64 100 01 d2 r9 Copyright O 2007 2010 ARM Limited All rights reserved Non Confidential Using NEON Support E 37 Using NEON Support void void void void void void void void void void void void void void void void voi
134. 31571e 308 DBL_MIN Minimum normalized positive floating point number value of 2 22507385850720138e 308 double LDBL_MAX Maximum value of long double 1 797693 13486231571e 308 LDBL_MIN Minimum normalized positive floating point number value of 2 22507385850720138e 308 long double FLT MAX EXP Maximum value of base 2 exponent for type float 128 FLT MIN EXP Minimum value of base 2 exponent for type float 125 DBL_MAX_EXP Maximum value of base 2 exponent for type double 1024 DBL_MIN_EXP Minimum value of base 2 exponent for type double 1021 LDBL MAX EXP Maximum value of base 2 exponent for type long double 1024 LDBL MIN EXP Minimum value of base 2 exponent for type long double 1021 FLT MAX 10 EXP Maximum value of base 10 exponent for type float 38 FLT MIN 10 EXP Minimum value of base 10 exponent for type float 37 DBL MAX 10 EXP Maximum value of base 10 exponent for type double 308 DBL MIN 10 EXP Minimum value of base 10 exponent for type double 307 LDBL MAX 10 EXP Maximum value of base 10 exponent for type long double 308 LDBL MIN 10 EXP Minimum value of base 10 exponent for type long double 307 ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved D 5 Non Confidential C and C Compiler Implementation Limits Table D 4 describes other characteristics of floating point numbers These constants are also defined in the float h include file Table D 4 Other floating point characteristics
135. 32x4x4 vld4q lane f32 transfersize 4 float32 t const ptr float32x4x4_t src __constrange 0 3 int lane NLD4 32 100 0 d2 0 d4 0 06 0 1 r0 polyl6x8x4 t vld4q lane p16 transfersize 4 polyl6 t const ptr polyl6x8x4 t src __constrange 0 7 int lane VLD4 16 d0 0 d2 0 d4 0 d6 re uint8x8x4 t vld4 lane u8 transfersize 4 uint8 t const ptr uint8x8x4 t src constrange 0 7 int ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved E 35 Non Confidential Using NEON Support lane NLD4 8 100 0 d1 d2 0 d3 0 r0 uintl6x4x4 t vild4 lane u16 transfersize 4 uintl6 t const ptr uintl6x4x4 t src constrange 0 3 int lane NLD4 16 100 0 01 0 d2 0 d3 0 re uint32x2x4 t vld4 lane u32 transfersize 4 uint32 t const ptr uint32x2x4 t src constrange 0 1 int lane NLD4 32 100 0 01 0 d2 0 d3 0 re int8x8x4 t vld4 lane s8 transfersize 4 int8 t const ptr int8x8x4 t src constrange 0 7 int lane NLD4 8 100 0 d1 0 d2 0 d3 0 re intl6x4x4 t vld4 lane s16 transfersize 4 int16_t const ptr intl6x4x4 t src constrange 0 3 int lane VLD4 16 100 0 d1 d2 0 d3 0 rd int32x2x4 vld4 lane s32 transfersize 4 int32 t const ptr int32x2x4 t src constrange 0 1 int lane NLD4 32 d0 0 d1 0 d2 0 d3 0 rd float32x2x4 t vld4_lane_f32 __transfersize 4 float32 t const ptr floa
136. 348A Non Confidential Compiler Command line Options Selecting this option modifies both the type of the defined type wchar t in C and the type of the native type wchar t in C It also affects the values of WCHAR MIN and WCHAR MAX Default The compiler assumes wchar16 unless wchar32 is explicitly specified See also wchar16 on page 2 94 Predefined macros on page 4 103 2 1 128 workdir directory ARM DUI 0348A This option enables you to provide a working directory for a project template Note Project templates only require working directories if they include files for example RVD configuration files Syntax workdir directory Where directory is the name of the project directory Restrictions If you specify a project working directory using workdir then you must specify a project file using project Errors An error message is produced if you try to use project without workdir and workdir is required See also no_ project filename on page 2 74 reinitialize_workdir on page 2 77 Copyright O 2007 2010 ARM Limited All rights reserved 2 95 Non Confidential Compiler Command line Options 2 1 129 no wrap diagnostics 2 96 This option enables or disables the wrapping of error message text when it is too long to fit on a single line Default The default is no wrap diagnostics See also no brief diagnostics on page 2 10 diag error tag
137. 4 gnu on page 2 44 no_ strict on page 2 84 2 1 114 sys_include 2 1 115 thumb 2 86 This option removes the current place from the include search path Quoted include files are treated in a similar way to angle bracketed include files except that quoted include files are always searched for first in the directories specified by I and angle bracketed include files are searched for first in the J directories See also Idir dir on page 2 46 Jdir dir on page 2 51 kandr_include on page 2 52 preinclude filename on page 2 75 The current place on page 2 13 in the Compiler User Guide The search path on page 2 14 in the Compiler User Guide This option configures the compiler to target the Thumb instruction set Default This is the default option for targets that do not support the ARM instruction set Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 2 1 116 Uname ARM DUI 0348A Compiler Command line Options See also arm on page 2 7 pragma arm on page 4 50 e pragma thumb on page 4 62 Specifying the target processor or architecture on page 2 22 in the Compiler User Guide Selecting the target CPU on page 4 3 in the Compiler User Guide This option removes any initial definition of the macro name The macro name can be either a predefined macro a macro specified using the D option Note
138. 4 102 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 4 8 Compiler predefines Compiler specific Features This section documents the predefined macros of the ARM compiler 4 8 1 Predefined macros Table 4 18 lists the macro names predefined by the ARM compiler for C and C Where the value field is empty the symbol is only defined Table 4 18 Predefined macros Name Value When defined __arm__ Always defined for the ARM compiler even when you specify the thumb option See also __ARMCC_VERSION ARMCC VERSION ver Always defined It is a decimal number and is guaranteed to increase between releases The format is PVtbbb where P is the major version V is the minor version t is the patch release bbb is the build number Note Use this to distinguish between RVCT and other tools that define __arm__ APCS INTERWORK When you specify the apcs interwork option or set the CPU architecture to ARMVST or later __APCS_ROPI When you specify the apcs ropi option __APCS_RWPI When you specify the apcs rwpi option __APCS_FPIC When you specify the apcs fpic option ARRAY OPERATORS In C compiler mode to specify that array new and delete are enabled BASE FILE name Always defined Similar to __FILE__ but indicates the primary source file rather than the current one that is when the current file is an included
139. 4 15 TI C55x intrinsics supported in RVCT Intrinsics _abss _Ishrs _rnd _smas count _1sadd _norm _smpy _divs _1smpy _round _sneg _labss _1sneg _roundn _sround max _1ssh1 _sadd _sroundn _Imin _1ssub shl sshl lnorm _max _shrs _ssub _1sh1 min _smac Example include limits h include lt stdint h gt include lt c55x h gt include TI C55x intrinsics __asm int32 t asm lsadd int32 t a int32 t b qadd rQ r0 r1 bx Ir int32_t foo int32_t a int32_t b int32_t c d e c asm_Isadd a b assembly language saturating add d __qadd a b ARM intrinsic saturating add e _Isadd a b TI C55x saturating add return c d e returns 1 4 100 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler specific Features See also the header file c55x h for further information on the ARM implementation of the C55x intrinsics Publications providing information about TI compiler intrinsics are available from Texas Instruments at http www ti com 4 7 49 Named register variables ARM DUI 0348A The compiler enables you to access registers of an ARM architecture based processor using named register variables Named register variables are supported at file scope at local scope but not on a function parameter Syntax register type var name asm reg Where type is the type of the named register
140. 48A Non Confidential Compiler specific Features Note This function attribute is a GNU compiler extension that is supported by the ARM compiler It has the declspec equivalent __declspec noinline Example static int b attribute noinline See also pragma no_ inline on page 4 56 __declspec noinline on page 4 25 4 3 7 attribute noreturn This function attribute informs the compiler that the function does not return The compiler can then perform optimizations by removing the code that is never reached Note This function attribute is a GNU compiler extension that is supported by the ARM compiler It has the declspec equivalent __declspec noreturn Example int Function Attributes NoReturn O0 void attribute noreturn See also __declspec noreturn on page 4 25 4 3 8 attribute pure Many functions have no effects except to return a value and that the return value depends only on the parameters and global variables Functions of this kind can be subject to data flow analysis and might be eliminated Note This function attribute is a GNU compiler extension that is supported by the ARM compiler ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved 4 33 Non Confidential Compiler specific Features Although related this function attribute is not equivalent to the __pure keyword The function attribute equivalent to __pure is __
141. 4x1l t a int64x1_t b vorn u8 uint8x8 t a uint8x8 t b vorn ul6 uintl6x4 t a uintl6x4 t b vorn u32 uint32x2 t a uint32x2 t b vorn u64 uint64x1l t a uint64x1l t b vorng s8 int8x16 t a int8x16 t b NEOR VEOR NEOR NEOR VEOR VEOR VEOR NEOR NEOR VEOR VEOR VEOR NEOR NEOR VEOR NEOR NBIC NBIC NBIC NBIC NBIC NBIC NBIC NBIC NBIC NBIC NBIC NBIC NBIC NBIC NBIC NBIC VORN NORN VORN VORN VORN VORN VORN VORN VORN Copyright 2007 2010 ARM Limited All rights reserved Non Confidential dd do dO dd do dO dd do dO dd do dO dd do dO dd do dO dd do dO dd do dO q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 dO do dO dd do dO dd do dO dd do dO dd do dO dd do dO dd do dO dd do dO q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 dd do dO dd do dO dd do dO dd do dO dd do dO dd do dO dd do dO dd do dO q0 q0 q0 ARM DUI 0348A intl6x8 t vorng_s16 int16x8_t a intl6x8 t b int32x4 t vorng_s32 int32x4_t a int32x4 t b int64x2 t vorng_s64 int64x2_t a int64x2 t b uint8x16 t vornq u8 uint8x16 t a uint8x16 t b uintl6x8 t vornqg ul6 uintl6x8 t a uintl6x8 t b uint32x4 t vorng u32 uint32x4 t a uint32x4 t b uint64x2 t vorng_u64 uint64x2_t a uint6
142. 4x2 t b Bitwise Select Note VORN VORN VORN VORN VORN VORN VORN Using NEON Support q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 q0 This intrinsic can compile to any of VBSL VBIF VBIT depending on register allocation int8x8 t vbsl s8 uint8x8 t a int8x8 t b int8x8 t c NBSL intl6x4_t vbsl_sl6 uint16x4_t a intl6x4 t b intl6x4 t c NBSL int32x2 t vbsl s32 uint32x2 t a int32x2 t b int32x2 t C NBSL int64xl t vbsl s64 uint64x1l t a int64x1l t b int64x1l t c NBSL uint8x8 t X vbsl u8 uint8x8 t a uint8x8 t b uint8x8 t c NBSL uintl6x4 t vbsl_ul6 uint16x4_t a uintl6x4 t b uintl16x4 t C NBSL uint32x2 t vbsl_u32 uint32x2_t a uint32x2 t b uint32x2_t C NBSL uint64x1_t vbsl u64 uint64x1l t a uint64x1l t b uint64x1_t c NBSL float32x2_t vbs l f32 uint32x2 t a float32x2 t b float32x2 t c VBSL poly8x8 t vbsl p8 uint8x8 t a poly8x8 t b poly8x8 t c NBSL polyl6x4 t vbs l pl6 uintl6x4 t a poly16x4_t b poly16x4_t c NBSL int8x16 t vbslq s8 uint8x16 t a int8x16 t b int8x16 t c NBSL intl6x8 t vbslq_sl6 uintl6x8_t a intl6x8 t b intl6x8 t c NBSL int32xX4 t vbslq s32 uint32x4 t a int32x4 t b int32x4 t c NBSL int64x2 t vbslq s64 uint64x2 t a int64x2 t b int64x2 t c NBSL uint8x16 t vbslq u8 uint8x16 t a uint8x16 t b uint8x16 t c NBSL uint16x8_t vbslq ul6 uintl16x8 t a uintl6x8 t b
143. 6 t b VCEQ 18 q0 q0 q0 Vector compare greater than or equal uint8x8 t vcge_s8 int8x8_t a int8x8 t b VCGE S8 00 00 00 uintl6x4 t vcge sl6 intl6x4 t a intl6x4 t b VCGE S16 00 d 00 uint32x2 t vcge s32 int32x2 t a int32x2 t b NCGE S32 00 00 00 uint32x2 t vcge f32 float32x2 t a float32x2 t b VCGE F32 00 d dQ uint8x8 t vcge u8 uint8x8 t a uint8x8 t b NCGE U8 00 00 00 uintl6x4 t vcge ul6 uintl6x4 t a uintl6x4 t b VCGE U16 00 d 00 uint32x2 t vcge u32 uint32x2 t a uint32x2 t b NCGE U32 00 00 00 uint8x16 t vcgeq s8 int8x16 t a int8x16 t b NCGE S8 q0 q0 q0 uintl6x8 t vcgeq sl6 intl6x8 t a intl16x8 t b NCGE S16 q0 00 q0 uint32x4 t vcgeq s32 int32x4 t a int32x4 t b NCGE S32 q0 00 q0 uint32x4 t vcgeq f32 float32x4 t a float32x4 t b VCGE F32 q0 q0 q0 uint8x16 t vcgeq u8 uint8x16 t a uint8x16 t b NCGE U8 q0 q0 q0 uintl6x8 t vcgeq ul6 uintl6x8 t a uintl6x8 t b VCGE U16 q0 q0 qd uint32x4 t vcgeq u32 uint32x4 t a uint32x4 t b VCGE U32 q0 q0 q0 Vector compare less than or equal uint8x8 t vcle s8 int8x8 t a int8x8 t b VCGE S8 00 00 d uintl6x4 t vcle sl16 intl6x4 t a intl6x4 t b NCGE S16 00 00 dd uint32x2 t vcle s32 int32x2 t a int32x2 t b NCGE S32 00 00 00 E 12 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential ARM DUI 0348A uint32x2 t uint8x8 t uintl6x4 t uint32x2 t uin
144. 6 t c MMA vmlag_s16 int16x8_t a intl6x8 t b int16x8 t c MLA vmlag_s32 int32x4_t a int32x4 t b int32x4 t C MMA vmlaq_f32 float32x4_t a float32x4 t b float32x4 t c VMLA vmlaq u8 uint8x16 t a uint8x16 t b uint8x16 t c MMA vmlaq ul6 uintl6x8 t a uintl6x8 t b uintl16x8 t c MMA vmlaq u32 uint32x4 t a uint32x4 t b uint32x4 t c MLA 116 d0 d0 d0 132 d0 d0 d0 I8 q0 q0 q0 116 q0 q0 q0 132 q0 q0 q0 F32 q0 q0 q0 I8 q0 q0 q0 116 q0 q0 q0 132 q0 q0 q0 Vector multiply accumulate long vmla gt Vr i Va i Vb i Vc i vmlal s8 intl16x8 t a int8x8 t b int8x8 t c vmlal sl6 int32x4 t a intl6x4 t b intl6x4 t c vmlal s32 int64x2 t a int32x2 t b int32x2 t C vmlal u8 uint16x8 t a uint8x8 t b uint8x8 t c NMLAL S8 q0 d0 d0 NMLAL S16 q0 d0 d0 NMLAL S32 q0 d0 d0 NMLAL U8 q0 d0 dO vmlal ul6 uint32x4 t a uintl6x4 t b uintl6x4 t c VMLAL U16 q0 d0 d0 vmlal u32 uint64x2 t a uint32x2 t b uint32x2 t c VMLAL U32 q0 d0 d0 Vector multiply subtract vmls gt Vr i Va i Vb i Vc i vmls s8 int8x8 t a int8x8 t b int8x8 t c MMES Vmis_s16 int16x4_t a intl6x4 t b intl6x4 t c MMES vmls s32 int32x2 t a int32x2 t b int32x2_t C MMES vmls f32 float32x2 t a float32x2 t b float32x2 t c VMLS vmls u8 uint8x8 t a uint8x8 t b uint8x8 t c MMES vmls ul6 uintl6x4 t a uintl6x4 t b uintl6x4 t c WLS vml
145. 6x4 t vqshlu n s16 intl6x4 t a uint32x2 t vqshlu n s32 int32x2 t a uint64x1l t vqshlu n s64 int64x1 t a uint8x16 t vqshlug n s8 int8x16 t a __ uint16x8 t vqshluq n s16 intl6x8 t a uint32x4 t vqshluqg n s32 int32x4 t a uint64x2 t vqshluq n s64 int64x2 t a constrange 0 7 int b VQSHLU S8 d0 d0 0 constrange 0 15 int b VQSHLU S16 d0 d0 0 constrange 0 31 int b VQSHLU S32 00 00 0 constrange 0 63 int b VQSHLU S64 00 00 0 constrange 0 7 int b VQSHLU S8 qQ q0 0 constrange 0 15 int b VQSHLU S16 qQ q0 0 constrange 0 31 int b VQSHLU S32 qQ q0 0 constrange 0 63 int b VQSHLU S64 qQ q0 0 Vector narrowing saturating shift right by constant int8x8 t vshrn_n_s16 int16x8_t a intlox4 t vshrn n s32 int32x4 t a int32x2 t vshrn n s64 into64x2 t a __ uint8x8 t vshrn n ul6 uintl16x8 t a uintl6x4 t vshrn n u32 uint32x4 t a uint32x2 t vshrn n u64 uint64x2 t a constrange 1 8 int b VSHRN I16 dQ qQ 8 constrange 1 16 int b VSHRN I32 d0 qQ 16 constrange 1 32 int b VSHRN I64 d0 q0 432 constrange 1 8 int b VSHRN I16 dQ qQ 8 constrange 1 16 int b VSHRN I32 d0 q0 16 constrange 1 32 int b VSHRN I64 d0 q0 432 Vector signed gt unsigned narrowing saturating shift right by constant uint8x8 t vqshrun n s16 int16x8 t a uintl6x4 t vqshrun n s32 int32x4 t a uint32x2 t vqshrun n s64 int64x2 t a constrange 1 8 int b VQSHRUN S16 dQ qQ 8 constrange 1 16
146. 7483648 to 42147483647 inclusive In previous releases of RVCT out of range values were cast to int without a warning unless you specified the strict option In RVCT v2 2 and above a Warning is issued for out of range enumerator values 66 enumeration value is out of int range Such values are treated the same way as in C that is they are treated as unsigned int long long or unsigned long long To ensure that out of range Warnings are reported use the following command to change them into Errors armcc diag error 66 Structures The following points apply to all C structures all C structures and classes not using virtual functions or base classes Structure alignment The alignment of a non packed structure is the maximum alignment required by any of its fields Field alignment Structures are arranged with the first named component at the lowest address Fields are aligned as follows A field with a char type is aligned to the next available byte A field with a short type is aligned to the next even addressed byte 5 8 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential ARM DUI 0348A C and C Implementation Details In RVCT v2 0 and above double and long long data types are eight byte aligned This enables efficient use of the LDRD and STRD instructions in ARMvSTE and above Bitfield alignment depends on how the bitfield is declared See Bit
147. 7ang country ARM DUI 0348A This option switches the default locale for source files to the one you specify in lang country Copyright O 2007 2010 ARM Limited All rights reserved Non Confidential 2 57 Compiler Command line Options 2 1 76 2 58 Syntax locale 7ang country Where lang country is the new default locale Use this option in combination with multibyte chars Restrictions The locale name might be case sensitive depending on the host platform The permitted settings of locale are determined by the host platform Ensure that you have installed the appropriate locale support for the host platform Example To compile Japanese source files on an English based Windows workstation use multibyte chars locale japanese and on a UNIX workstation use multibyte chars locale ja JP See also message_locale lang_country codepage on page 2 61 no_ multibyte_chars on page 2 62 loose_implicit_cast This option makes illegal implicit casts legal such as implicit casts of a non zero integer to a pointer Example int p 0x8000 Compiling this example without the option loose implicit cast generates an error Compiling this example with the option 10056 implicit cast generates a warning message that you can suppress Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options 2 1 77 no lower
148. 8 uint8 t const ptr VLD1 8 100 r0 vldi ul6 transfersize 4 uintl16 t const ptr VLD1 16 100 r0 vldi u32 transfersize 2 uint32 t const ptr NED1 32 d0 r0 vldi u64 transfersize 1 uint64 t const ptr VLD1 64 d0 r0 vldi s8 transfersize 8 int8 t const ptr VLD1 8 100 r0 vldi s16 transfersize 4 int16 t const ptr VLD1 16 100 r0 101 s32 transfersize 2 int32 t const ptr VLD1 32 d0 r0 vldi s64 transfersize 1 int64 t const ptr VLD1 64 d0 r0 vidi f32 transfersize 2 float32 t const ptr VLD1 32 d0 r0 vidi p8 transfersize 8 poly8 t const ptr VLD1 8 100 r0 vldi_p16 __transfersize 4 poly16 t const ptr VLD1 16 100 r0 vldiq lane u8 transfersize 1 uint8 t const ptr uint8x16 t vec constrange 0 15 int VLD1 8 100 0 1 r vldiq lane u16 transfersize 1 uintl6 t const ptr uintl6x8 t vec constrange 0 7 VLD1 16 d0 r0 Copyright O 2007 2010 ARM Limited All rights reserved E 25 Non Confidential Using NEON Support uint32x4 t vldiq lane u32 transfersize 1 uint32 t const ptr uint32x4 t vec int lane constrange 0 3 NLD1 32 d0 0 re uint64x2 t vldiq_lane_u64 __transfersize 1 uint64 t const ptr uint64x2 t vec int lane constrange 0 1 NLD1 64 100 r0 int8x16 t vldiq lane s8 transfersize 1 int8 t const ptr int8x16 t
149. 8 t a intlox4 t vabs sl16 intl6x4 t a int32x2 t vabs s32 int32x2 t a float32x2 t 1805 f32 float32x2 t a int8x16 t X vabsq s8 int8x16 t a intl6x8 t vabsq_s16 int16x8_t a int32xX4 t vabsq s32 int32x4 t a NABS NABS VABS VABS NABS NABS VABS float32x4 t vabsq f32 float32x4 t a VABS Saturating absolute Vd i sat Va i int8x8 t vqabs s8 int8x8 t a intl6x4 t vqabs s16 intl6x4 t a int32x2 t vqabs s32 int32x2 t a int8x16 t vqabsq s8 int8x16 t a intl16x8 t vqabsq_s16 int16x8_t a int32x4 t vqabsq s32 int32x4 t a Negate Vd i Va i int8x8 t vneg s8 int8x8 t a intl6x4 t vneg s16 intl6x4 t a int32x2 t vneg s32 int32x2 t a float32x2 t vneg_f32 float32x2_t a int8x16 t vnegq s8 int8x16 t a intl6x8 t vnegq_s16 int16x8_t a int32xX4 t vnegq s32 int32x4 t a S8 d0 d0 S16 d0 d0 S32 d0 d0 F32 d0 d0 S8 q0 q0 S16 q0 q0 332 q0 q0 F32 q0 q0 VQABS S8 d0 d0 VQABS S16 00 00 VQABS S32 00 00 VQABS S8 q0 q0 VQABS S16 q0 q0 VQABS S32 q0 q0 NEG S8 d0 d0 NNEG NNEG NNEC NNEG NNEG NNEG float32x4 vnegq f32 float32x4 t a VNEG S16 d0 d0 S32 d0 d0 F32 d0 d0 S8 q0 q0 S16 q0 q0 332 q0 q0 F32 q0 q0 Saturating Negate sat Vd i Va i int8x8 t vqneg_s8 int8x8_t a intl6x4 t vqneg s16 intl6x4 t a int32x2 t vqneg s32 int32x2 t a int
150. 8 uint8x8_t a uint8x8 t b VADD I8 d0 d0 d0 uint16x4_t vadd ul6 uintl6x4 t a uintl6x4 t b VADD I16 dQ dQ d0 uint32x2 t vadd u32 uint32x2 t a uint32x2 t b VADD I32 d0 d0 d0 uint64xl t vadd u64 uint64x1l t a uint64x1l t b VADD I64 d0 d0 d0 int8x16 t vaddq s8 int8x16 t a int8x16 t b VADD I8 q0 q0 q0 intl6x8 t vaddq_s16 int16x8_t a intl6x8 t b VADD 116 q0 q0 q0 int32xX4 t vaddq s32 int32x4 t a int32x4 t b VADD 132 q0 q0 q0 int64x2 t vaddq s64 int64x2 t a int64x2 t b VADD 164 q0 q0 q0 float32x4 t vaddq f32 float32x4 t a float32x4 t b VADD F32 q0 q0 q0 uint8x16 t vaddq u8 uint8x16 t a uint8x16 t b VADD 18 q0 q0 q0 uintl6x8 t vaddq ul6 uintl6x8 t a uintl16x8 t b VADD I16 q0 q0 q0 uint32x4 t vaddq u32 uint32x4 t a uint32x4 t b VADD 132 q0 q0 q0 uint64x2 t vaddq u64 uint64x2 t a uint64x2 t b VADD I64 q0 q0 q0 Vector long add vadd gt Vr i 2 Va i Vb i Va Vb have equal lane sizes result is a 128 bit vector of lanes that are twice the width intl16x8 t vaddl s8 int8x8 t a int8x8 t b VADDL S8 q0 d0 d0 int32x4 t vaddl_s16 int16x4_t a intl6x4 t b VADDL S16 q0 d0 d0 int64x2 t vaddl s32 int32x2 t a int32x2 t b VADDL S32 q0 d0 d0 uintl6x8 t vaddl u8 uint8x8 t a uint8x8 t b VADDL U8 q0 d0 d0 uint32x4 t vaddl ul6 uintl6x4 t a uintl6x4 t b VADDL U16 q0 d0 d0 uint64x2 t vaddl u32 uint32x2 t a uint32x2 t b VADDL U32 q0 d0 d0 Vect
151. 8x16 t vqnegq s8 int8x16 t a intl16x8 t vqnegq s16 intl6x8 t a int32x4 t vqnegq s32 int32x4 t a Count leading sign bits int8x8 t vcls_s8 int8x8_t a intl6x4 t vcls s16 int16x4 t a int32x2 t vcls s32 int32x2 t a int8x16 t vclsq s8 int8x16 t a intl16x8 t vclsq s16 intl6x8 t a int32x4 t vclsq s32 int32x4 t a VQNEG S8 d0 d0 VQNEG S16 00 00 VQNEG S32 00 00 VQNEG S8 q0 q0 VQNEG S16 q0 q0 NXQNEG S32 q0 q0 NCLS S8 d0 d0 VCLS S16 d0 d0 NCLS S32 d0 d0 NCLS S8 q0 q0 VCLS S16 q0 q0 NCLS S32 q0 q0 Copyright O 2007 2010 ARM Limited All rights reserved Non Confidential Using NEON Support E 53 Using NEON Support Count leading zeros int8x8 t int16x4_t vclz_s8 int8x8_t a vclz_s16 int16x4_t a int32xX2 t vclz s32 int32x2 t a uint8x8 t vclz u8 uint8x8 t a uintl6x4 t vclz ul6 uintl6x4 t a uint32x2 t vclz u32 uint32x2 t a int8x16 t vclzq s8 int8x16 t a intl6x8 t vclzq sl6 intl6x8 t a int32x4 t vclzq s32 int32x4 t a uint8x16 t vclzq u8 uint8x16 t a uintl6x8 t vclzq ul6 uintl6x8 t a uint32x4 t vclzq u32 uint32x4 t a Count number of set bits uint8x8 t vcnt u8 uint8x8 t a int8x8 t X vcnt s8 int8x8 t a poly8x8 t vcnt p8 poly8x8 t a uint8x16 t vcntq u8 uint8x16 t a int8x16 t vcntq s8 int8x16 t a poly8x16 t vcntq p8 poly8x16 t a Reciprocal estimate VCLZ NCLZ VCLZ VCLZ VCLZ VCLZ VCLZ
152. 8x2 t b int8x8 t c NTBX poly8x8 t vtbx2 p8 poly8x8 t a poly8x8x2 t b uint8x8 t c VIBX uint8x8 t vtbx3 u8 uint8x8 t a uint8x8x3 t b uint8x8 t c VTBX int8x8 t vtbx3 s8 int8x8 t a int8x8x3 t b int8x8 t c NTBX poly8x8_t vtbx3_p8 poly8x8_t a poly8x8x3 t b uint8x8_t c VIBX uint8x8 t vtbx4 u8 uint8x8 t a uint8x8x4 t b uint8x8 t c VTBX int8x8 t vtbx4 s8 int8x8 t a int8x8x4 t b int8x8 t c NTBX poly8x8 t vtbx4 p8 poly8x8 t a poly8x8x4 t b uint8x8_t c VIBX d 100 d1 dO d 100 d1 dO d 100 d1 d d 100 01 d2 d d 100 d1 d2 d d 100 d1 d2 d d d d1 d2 d3 dO d d d1 d2 d3 dO d d d1 d2 d3 dO 00 OO OO OO OO OO CO CO CO CO CO OO E 46 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Using NEON Support E 3 25 Operations with a scalar value intl6x4 t int32x2 t uintl6x4 t uint32x2 t float32x2 t intl6x8 t int32x4 t uintl6x8 t uint32x4 t float32x4 t Efficient code generation for these intrinsics is only guaranteed when the scalar argument is either a constant or a use of one of the vget lane intrinsics Vector multiply accumulate with scalar vmla lane s16 intl6x4 t a intl6x4 t b intl6x4 t v __constrange 3 int 1 NMLA I16 dQ 00 000 vmla lane s32 int32x2 t a int32x2 t b int32x2 t v __constrange 1 int 1 NMLA I32 d 00 000 vmla lane
153. 8x8 t vqsub u8 uint8x8 t a uint8x8 t b NQSUB U8 d0 d0 d0 uintl6x4 t vqsub ul6 uintl6x4 t a uintl6x4 t b VQSUB U16 d0 d0 d0 uint32x2 t vqsub u32 uint32x2 t a uint32x2 t b VQSUB U32 00 00 00 E 10 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Using NEON Support uint64x1 t vqsub u64 uint64x1 t a uint64x1l t b VQSUB U64 d0 d0 d0 int8x16 t vqsubq s8 int8x16 t a int8x16 t b VQSUB S8 q0 q0 q0 intl6x8 t vasubq_s16 int16x8_t a intl16x8 t b VQSUB S16 q0 q0 q0 int32x4 t vqsubq s32 int32x4 t a int32x4 t b VQSUB S32 q0 q0 q0 int64x2 t vqsubq s64 int64x2 t a int64x2 t b VQSUB S64 q0 q0 q0 uint8x16 t vqsubq u8 uint8x16 t a uint8x16 t b VQSUB U8 q0 q0 q0 uintl6x8 t vqsubq ul6 uintl6x8 t a uintl6x8 t b VQSUB U16 q0 q0 q0 uint32x4 t vqsubq u32 uint32x4 t a uint32x4 t b VQSUB U32 q0 q0 q0 uint64x2 t vqsubq u64 uint64x2 t a uint64x2 t b VQSUB U64 q0 q0 q0 Vector halving subtract int8x8 t vhsub s8 int8x8 t a int8x8 t b MHSUB S8 d0 d0 dO intl6x4 t vhsub_s16 int16x4_t a intl16x4 t b MHSUB S16 d0 d0 d0 int32x2 t vhsub_s32 int32x2_t a int32x2 t b MHSUB S32 d0 d0 d0 uint8x8 t vhsub u8 uint8x8 t a uint8x8 t b MHSUB U8 d0 d0 dO uintl6x4 t vhsub ul6 uintl6x4 t a uintl6x4 t b VHSUB U16 d0 d0 d0 uint32x2 t vhsub u32 uint32x2 t a uint32x2 t b VHSUB U32 d0 d0 d0 int8x16 t vhsubq s8 int8x16 t a int8x16 t b MHSUB
154. A Copyright 2007 2010 ARM Limited All rights reserved E 51 Non Confidential Using NEON Support int32x4 t vextq s32 int32x4 t a int32X4 t b __ uint32x4_t vextq u32 uint32x4 t a uint32x4 t b int64x2 t vextq s64 int64x2 t a int64x2_t b __ uint64x2 t vextq u64 uint64x2 t a uint64x2 t b y y E 3 27 Reverse vector elements swap endianness constrange 0 3 int c constrange 0 1 int c NEXT 32 q0 q0 q0 0 constrange 0 3 int c VEXT 32 q0 q0 q0 0 NEXT 64 q0 q0 q0 0 constrange 0 1 int c VEXT 64 qQ q0 q0 0 VREVn m reverses the order of the m bit lanes within a set that is n bits wide int8x8 t vrev64 s8 int8x8 t vec int16x4_t vrev64_s16 int16x4_t vec int32x2 t vrev64 s32 int32x2 t vec uint8x8 t vrev64 u8 uint8x8 t vec uint16x4_t X vrev64 ul6 uintl6x4 t vec uint32x2 t vrev64 u32 uint32x2 t vec poly8x8 t vrev64 p8 poly8x8 t vec 00 1674 t vrev64_p16 poly16x4_t vec float32x2 t vrev64 f32 float32x2 t vec int8x16 t vrev64q s8 int8x16 t vec intl6x8 t vrev64q s16 int16x8 t vec int32x4 t vrev64q s32 int32x4 t vec uint8x16_t X vrev64q u8 uint8x16 t vec uintl6x8 t vrev64q ul6 uintl16x8 t vec uint32x4 t vrev64q u32 uint32x4 t vec poly8x16 t vrev64q p8 poly8x16 t vec poly16x8 t vrev64q pl6 polyl16x8 t vec float32x4 t vrev64q_f32 float32x4_t vec int8x8 t vrev32 s8 int8x8 t vec intl6x4_t vrev32_s16 int16x4_t vec uint8x8 t vrev3
155. ADD U32 q0 q0 q0 Vector rounding halving add vrhadd gt Vr i Va i Vb i 1 gt gt 1 int8x8 t vrhadd s8 int8x8 t a int8x8 t b NRHADD S8 dQ dQ d0 intl6x4 t vrhadd_s16 int16x4_t a intl16x4 t b NRHADD S16 d0 d0 d0 int32x2 t vrhadd s32 int32x2 t a int32x2 t b NRHADD S32 d0 d0 d0 uint8x8 t vrhadd u8 uint8x8 t a uint8x8 t b NRHADD U8 00 00 0 uintl6x4 t vrhadd ul6 uintl6x4 t a uintl6x4 t b VRHADD U16 d0 d0 d0 uint32x2 t vrhadd u32 uint32x2 t a uint32x2 t b VRHADD U32 d0 d0 d0 int8x16 t vrhaddq s8 int8x16 t a int8x16 t b NRHADD S8 q0 q0 q0 intl6x8 t vrhaddg_s16 int16x8_t a intl16x8 t b VRHADD S16 q0 q0 q0 int32x4 t vrhaddq s32 int32x4 t a int32x4 t b VRHADD S32 q0 q0 q0 uint8x16_t vrhaddq u8 uint8x16 t a uint8x16 t b VRHADD U8 q0 q0 q0 uintl16x8 t vrhaddq ul6 uintl16x8 t a uintl6x8 t b VRHADD U16 q0 q0 q0 uint32x4 t vrhaddq u32 uint32x4 t a uint32x4 t b VRHADD U32 q0 q0 q0 Vector saturating add vqadd gt Vr i sat lt size gt Va i Vb i int8x8 t vqadd s8 int8x8 t a int8x8 t b NQADD S8 d0 d0 d0 intl6x4 t vqadd sl6 intl6x4 t a intl6x4 t b NQADD S16 d0 d0 d0 int32x2 t vqadd s32 int32x2 t a int32x2 t b NQADD S32 00 00 0 int64xl t vqadd s64 int64x1l t a int64x1_t b NQADD S64 00 00 0 uint8x8 t vqadd u8 uint8x8 t a uint8x8 t b NQADD U8 d0 d0 d0 uintl6x4 t vqadd ul6 uintl6x4 t a uintl6x4 t b VQADD U16 d0 d0 d0 uint32
156. All rights reserved 5 9 Non Confidential C and C Implementation Details 5 10 Packed structures A packed structure is one where the alignment of the structure and of the fields within it is always 1 Packed structures are defined with the __packed qualifier There is no command line option to change the default packing of structures Bitfields In non packed structures the ARM compiler allocates bitfields in containers A container is a correctly aligned object of a declared type Bitfields are allocated so that the first field specified occupies the lowest addressed bits of the word depending on configuration Little endian Lowest addressed means least significant Big endian Lowest addressed means most significant A bitfield container can be any of the integral types Note In strict 1990 ISO Standard C the only types permitted for a bit field are int signed int and unsigned int For non int bitfields the compiler displays an error A plain bitfield declared without either signed or unsigned qualifiers is treated as unsigned For example int x 10 allocates an unsigned integer of 10 bits A bitfield is allocated to the first container of the correct type that has a sufficient number of unallocated bits for example struct X i int x 10 int y 20 The first declaration creates an integer container and allocates 10 bits to x At the second declaration the compiler finds the existing integer conta
157. C Implementation Definition B 4 Note A whitespace character is any character where the result of isspace is true e A double quote or backslash character inside double quotes must be preceded by a backslash character An input output redirection is not recognized inside double quotes Interactive device In a non hosted implementation of the ARM C library the term interactive device might be meaningless The generic ARM C library supports a pair of devices both called tt intended to handle keyboard input and VDU screen output In the generic implementation no buffering is done on any stream connected to tt unless input output redirection has occurred if input output redirection other than to tt has occurred full file buffering is used except that line buffering is used if both stdout and stderr were redirected to the same file Redirecting standard input output and error streams Using the generic ARM C library the standard input output and error streams can be redirected at runtime For example if mycopy is a program running on a host debugger that copies the standard input to the standard output the following line runs the program mycopy lt infile gt outfile 2 gt errfile and redirects the files as follows stdin The standard input stream is redirected to infile stdout The standard output stream is redirected to outfile stderr The standard error stream is redirected to errfile The
158. Confidential C and C Implementation Details Bitwise operations on signed integral types follow the rules that arise naturally from two s complement representation No sign extension takes place Right shifts on signed quantities are arithmetic For values of type int Shifts outside the range 0 to 127 are undefined Left shifts of more than 31 give a result of zero Right shifts of more than 31 give a result of zero from a shift of an unsigned value or positive signed value They yield 1 from a shift of a negative signed value For values of type long long shifts outside the range 0 to 63 are undefined The remainder on integer division has the same sign as the divisor as mandated by the ISO C99 standard If a value of integral type is truncated to a shorter signed integral type the result is obtained by discarding an appropriate number of most significant bits If the original number is too large positive or negative for the new type there is no guarantee that the sign of the result is going to be the same as the original A conversion between integral types does not raise an exception e Integer overflow does not raise an exception Integer division by zero returns zero by default Operations on floating point types The following statements apply to operations on floating point types Normal IEEE 754 rules apply Rounding is to the nearest representable value by default F
159. DUI 0348A Non Confidential Compiler specific Features 4 5 9 attribute used This variable attribute informs the compiler that a variable is to be retained in the object even if it is unreferenced Variables marked as used are emitted to a single section in the order they are declared You can specify the section into which variables are placed using attribute section Note This variable attribute is a GNU compiler extension that is supported by the ARM compiler Note Functions might also be marked as used using the corresponding function attribute __attribute__ used Usage You can use __attributte__ used to build tables in the object Example static int lose_this 1 static int keep this 2 __attribute__ used retained in object file static int keep this too 3 attribute used retained in object file ll See also attribute section on page 4 44 attribute used on page 4 35 4 5 10 attribute weak ARM DUI 0348A The declaration of a weak variable is permitted and acts in a similar way to weak in GNU mode extern int Variable Attributes weak 1 attribute weak the equivalent in non GNU mode is __weak int Variable Attributes weak compare Copyright O 2007 2010 ARM Limited All rights reserved 4 47 Non Confidential Compiler specific Features Note The extern qualifier is required in GNU mode In non
160. GNU mode the compiler assumes that if the variable is not extern then it is treated like any other non weak variable Note This variable attribute is a GNU compiler extension that is supported by the ARM compiler See also _ weak on page 4 20 4 5 11 __attribute__ zero_init The section attribute specifies that a variable must be placed in a particular data section The zero_init attribute specifies that a variable with no initializer is placed in a ZI data section If an initializer is specified an error is reported Note This variable attribute is a GNU compiler extension that is supported by the ARM compiler Example __attribute__ zero_init int x in section bss attribute section mybss zero init int y in section mybss See also attribute section on page 4 44 4 48 Copyright O 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 4 6 Pragmas 4 6 1 ARM DUI 0348A Compiler specific Features The ARM compiler recognizes a number of ARM specific pragmas Table 4 6 summarizes the available pragmas Note Pragmas override related command line options For example pragma arm overrides the command line option thumb Table 4 6 Pragmas supported by the compiler Pragmas pragma no anon unions pragma no exceptions unwind pragma Otime pragma arm pragma hdrstop pragma pop pragma arm
161. LD2 32 100 d2 r0 int8x16x2 t vld2q_s8 __transfersize 32 int8 t const ptr NLD2 8 100 02 r0 intl6x8x2 t vld2q_s16 __transfersize 16 int16_t const ptr VLD2 16 100 d2 r0 int32x4x2_t vld2q_s32 __transfersize 8 int32 t const ptr VLD2 32 100 d2 r0 float32x4x2 t vld2q_f32 __transfersize 8 float32 t const ptr VLD2 32 100 d2 r0 poly8x16x2 vld2q_p8 __transfersize 32 poly8 t const ptr NLD2 8 100 02 r0 polyl6x8x2 t vld2q_p16 __transfersize 16 poly16_t const ptr VLD2 16 100 d2 r0 uint8x8x2 t vld2_u8 __transfersize 16 uint8 t const ptr VLD2 8 100 d1 r0 uint16x4x2_t vld2_u16 __transfersize 8 uintl6 t const ptr NLD2 16 100 d1 r0 uint32x2x2 t vild2 u32 transfersize 4 uint32 t const ptr NLD2 32 100 d1 r0 uint64x1x2_t vld2_u64 __transfersize 2 uint64 t const ptr VLD1 64 100 d1 r0 int8x8x2 t vld2_s8 __transfersize 16 int8 t const ptr VLD2 8 100 d1 r0 intl6x4x2 t vld2_s16 __transfersize 8 int16 t const ptr VLD2 16 100 d1 r0 int32x2x2 t v1d2 s32 transfersize 4 int32 t const ptr VLD2 32 100 011 r0 int64x1x2_t v1d2 s64 transfersize 2 int64 t const ptr VLD1 64 100 d1 r0 float32x2x2 t vld2_f32 __transfersize 4 float32 t const ptr VLD2 32 100 011 r0 poly8x8x2 t vld2_p8 __transfersize 16 poly8 t const ptr NLD2 8 100 01 r0 poly16x4
162. Not all compiler predefined macros can be undefined Syntax Uname Where name is the name of the macro to be undefined Usage Specifying Uname has the same effect as placing the text undef name at the head of each source file Restrictions The compiler defines and undefines macros in the following order l compiler predefined macros 2 macros defined explicitly using Dname 3 macros explicitly undefined using Uname Copyright O 2007 2010 ARM Limited All rights reserved 2 87 Non Confidential Compiler Command line Options See also C on page 2 13 Dname parm list def on page 2 19 E on page 2 33 M on page 2 60 Compiler predefines on page 4 103 2 1 117 no_ unaligned_access This option enables or disables unaligned accesses to data on ARM architecture based processors Default The default is unaligned access on ARM architecture based processors that support unaligned accesses to data This includes all ARMv6 architecture based processors ARMv7 A and ARMv7 R architecture based processors The default is no unaligned access on ARM architecture based processors that do not support unaligned accesses to data This includes all pre ARMv6 architecture based processors ARMv7 M architecture based processors Usage unaligned access Use unaligned access on processors that support unaligned accesses to data for example cpu ARM1136J S to speed
163. RM DUI 0348A Non Confidential Preface This preface introduces the RealView Compilation Tools Compiler Reference Guide It contains the following sections About this book on page vi Feedback on page x ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved V Non Confidential Preface About this book Intended audience Using this book vi This book provides reference information for Real View Compilation Tools RV CT and describes the command line options to the ARM compiler The book also gives reference material on the ARM implementation of C and C in the compiler For general information on using and controlling the ARM compiler see the RVCT Compiler User Guide This book is written for all developers who are producing applications using RVCT It assumes that you are an experienced software developer See the RealView Compilation Tools Essentials Guide for an overview of the ARM development tools provided with RVCT This book is organized into the following chapters and appendixes Chapter 1 Introduction Read this chapter for an overview of the ARM compiler the conformance standards and the C and C Libraries Chapter 2 Compiler Command line Options Read this chapter for a list of all command line options accepted by the ARM compiler Chapter 3 Language Extensions Read this chapter for a description of the language extensions provided by the ARM compiler and for information on standards
164. RM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler specific Features 4 7 33 schedule barrier 4 7 84 __semihost ARM DUI 0348A This intrinsic creates a sequence point where operations before and operations after the sequence point are not merged by the compiler A scheduling barrier does not cause memory to be updated If variables are held in registers they are updated in place and not written out This intrinsic is similar to the __nop intrinsic except that no NOP instruction is generated Syntax void schedule barrier void See also nop on page 4 78 This intrinsic inserts an SVC or BKPT instruction into the instruction stream generated by the compiler It enables you to make semihosting calls from C or C that are independent of the target architecture Syntax int semihost int val const void sptr Where val Is the request code for the semihosting request See Appendix A Semihosting in the Developer Guide for more information ptr Is a pointer to an argument result block See Appendix A Semihosting in the Developer Guide for more information Return value See Appendix A Semihosting in the Developer Guide for more information on the results of semihosting calls Copyright O 2007 2010 ARM Limited All rights reserved 4 85 Non Confidential Compiler specific Features 4 86 Usage Use this intrinsic from C or C to generate the appropriate semihosting call for your
165. RSHRN U16 00 90 8 VQRSHRN U32 00 90 16 VQRSHRN U64 00 90 32 NSHLL S8 00 00 0 NSHLL S16 00 00 NSHLL S32 q0 d0 0 NSHLL U8 q0 d0 0 constrange 0 15 int b VSHLL U16 qQ d0 0 constrange 0 31 int b VSHLL U32 qQ d0 0 These intrinsics provide operations including shifts with insert Non Confidential Copyright O 2007 2010 ARM Limited All rights reserved E 23 Using NEON Support Vector shift right and insert int8x8 t vsri n s8 int8x8 t a int8x8 t b __constrange 1 8 int c NSRI 8 00 00 68 intl6x4 t vsri_n_s16 int16x4_t a intl6x4 t b __constrange 1 16 int c NSRI 16 d0 d0 216 int32x2 t vsri n s32 int32x2 t a int32x2 t b __constrange 1 32 int c NSRI 32 00 00 32 int64x1l t vsri n s64 int64x1l t a int64x1l t b __constrange 1 64 int c NSRI 64 00 00 64 uint8x8 t vsri n u8 uint8x8 t a uint8x8 t b constrange 1 8 int c NSRI 8 00 00 68 uintl6x4 t vsri n ul6 uintl6x4 t a uintl6x4 t b constrange 1 16 int c VSRI 16 00 00 16 uint32x2 t vsri n u32 uint32x2 t a uint32x2 t b constrange 1 32 int c VSRI 32 d0 d0 32 uint64x1l t vsri n u64 uint64x1 t a uint64x1l t b __constrange 1 64 int c VSRI 64 d0 d0 464 poly8x8 t vsri n p8 poly8x8 t a poly8x8 t b __constrange 1 8 int c NSRI 8 00 00 68 polyl6x4 t vsri n pl6 polyl6x4 t a polyl6x4 t b constrange 1 16 int c VSRI 16 d0 d0 416 int8x16 t vsrig n s8 int8x16
166. RealView Compilation Tools Version 3 1 Compiler Reference Guide ARM Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A RealView Compilation Tools Compiler Reference Guide Copyright 2007 2010 ARM Limited All rights reserved Release Information The following changes have been made to this book Change History Date Issue Confidentiality Change March2007 A Non confidential Release 3 1 for RVDS v3 1 April 2010 A Non confidential Documentation update for Release 3 1 for RVDS v3 1 Proprietary Notice Words and logos marked with or are registered trademarks or trademarks owned by ARM Limited Other brands and names mentioned herein may be the trademarks of their respective owners Neither the whole nor any part of the information contained in or the product described in this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder The product described in this document is subject to continuous developments and improvements All particulars of the product and its use contained in this document are given by ARM in good faith However all warranties implied or expressed including but not limited to implied warranties of merchantability or fitness for purpose are excluded This document is intended only to assist the reader in the use of the product ARM Limited shall not be liable for any loss or damage arising from the
167. S8 q0 q0 q0 intl6x8 t vhsubq_s16 int16x8_t a intl16x8 t b VHSUB S16 q0 q0 q0 int32x4 t wvhsubq s32 int32x4 t a int32x4 t b VHSUB S32 q0 q0 q0 uint8x16 t vhsubq u8 uint8x16 t a uint8x16 t b VHSUB U8 q0 q0 q0 uintl6x8 t vhsubq ul6 uintl6x8 t a uintl6x8 t b VHSUB U16 q0 q0 q0 uint32x4 t vhsubq u32 uint32x4 t a uint32x4 t b VHSUB U32 q0 q0 q0 Vector subtract high half int8x8 t X vsubhn s16 intl16x8 t a intl6x8 t b VSUBHN I16 d0 q0 q0 intl6x4 t vsubhn s32 int32x4 t a int32x4 t b VSUBHN I32 d0 q0 q0 int32x2 t vsubhn s64 int64x2 t a int64x2 t b VSUBHN I64 d0 q0 q0 uint8x8 t vsubhn ul6 uintl6x8 t a uintl6x8 t b VSUBHN I16 d0 q0 q0 uintl6x4 t vsubhn u32 uint32x4 t a uint32x4 t b VSUBHN I32 d0 q0 q0 uint32x2 t vsubhn u64 uint64x2 t a uint64x2 t b VSUBHN I64 d0 q0 q0 Vector rounding subtract high half int8x8 t vrsubhn_s16 int16x8_t a int16x8 t b VRSUBHN I16 d0 q0 q0 intl6x4 t vrsubhn s32 int32x4 t a int32x4 t b VRSUBHN I32 d0 q0 q0 int32x2 t vrsubhn s64 int64x2 t a int64x2 t b VRSUBHN I64 d0 q0 q0 uint8x8 t vrsubhn ul6 uintl16x8 t a uintl16x8 t b VRSUBHN I16 d0 q0 q0 uintl6x4 t vrsubhn u32 uint32x4 t a uint32x4 t b VRSUBHN I32 d0 q0 q0 uint32x2 t vrsubhn u64 uint64x2 t a uint64x2_t b VRSUBHN I64 d0 q0 q0 ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved E 11 Non Confidential Using NEON Support E 3 4 Comparison A r
168. SQRTS F32 00 00 dQ float32x4 t vrsqrtsq f32 float32x4 t a float32x4 t b VRSQRTS F32 q0 q0 q E 3 11 Shifts by signed variable These intrinsics provide operations including shift by signed variable Vector shift left Vr i Va i lt lt Vb i negative values shift right int8x8 t vshl s8 int8x8 t a int8x8 t b NSHL intl6ox4 t vshl si6 intl6x4 t a intl6x4 t b NSHL int32x2 t vshl s32 int32x2 t a int32x2 t b NSHL int64xl t vshl s64 int64x1l t a int64x1l t b NSHL uint8x8 t vshl u8 uint8x8 t a int8x8 t b NSHL uintl6x4 t vshl ul6 uintl6x4 t a intlox4 t b VSHL uint32x2 t vshl u32 uint32x2 t a int32x2 t b VSHL uint64x1_t vshl u64 uint64x1l t a int64x1_t b VSHL int8x16 t vshlq s8 int8x16 t a int8x16 t b NSHL intl6x8 t vshlq sl6 intl6x8 t a intl16x8 t b VSHL int32x4 t vshlq s32 int32x4 t a int32x4 t b X VSHL int64x2_t vshlq s64 int64x2 t a int64x2 t b X VSHL uint8x16_t vshlq u8 uint8x16 t a int8x16 t b VSHL uint16x8 t vshlq ul6 uintl6x8 t a intl6x8 t b VSHL uint32x4 t vshlq u32 uint32x4 t a int32x4 t b VSHL uint64x2 t vshlq u64 uint64x2 t a int64x2 t b VSHL S8 d0 d0 d0 S16 d0 d0 d0 S32 d0 d0 d0 S64 d0 d0 d0 U8 d0 d0 dO U16 d0 d0 d0 U32 00 00 00 064 00 00 00 S8 q0 q0 q0 S16 q0 q0 q0 32 q0 q0 q0 364 q0 q0 q0 U8 00 0 00 U16 q0 q80 q0 U32 qQ q0 q0 U64 q0 q80 q0 Vector saturating shift left nega
169. Syntax pragma diag remark tag tag Where tag tag is a comma separated list of diagnostic message numbers specifying the messages whose severities are to be changed Copyright O 2007 2010 ARM Limited All rights reserved 4 53 Non Confidential Compiler specific Features See also diag remark tag tag on page 2 27 remarks on page 2 78 pragma diag_default tag tag on page 4 51 pragma diag error tag tag on page 4 52 pragma diag suppress tag tag pragma diag warning tag tag Changing the severity of diagnostic messages on page 5 5 in the Compiler User Guide 4 6 7 pragma diag suppress tag tag This pragma disables all diagnostic messages that have the specified tags pragma diag suppress behaves analogously to pragma diag errors except that the compiler suppresses the diagnostic messages having the specified tags rather than setting them to have Error severity Syntax pragma diag suppress tag tag Where tag tag is a comma separated list of diagnostic message numbers specifying the messages to be suppressed See also diag suppress tag tag on page 2 28 pragma diag_default tag tag on page 4 51 pragma diag error tag tag on page 4 52 pragma diag remark tag tag on page 4 53 pragma diag warning tag tag Suppressing diagnostic messages on page 5 6 in the Compiler User
170. TION ieee_fixed IEEE standard with round to nearest and no inexact exceptions This defines the symbols __FP_IEEE __FP_FENV_EXCEPTIONS jeee_no_fenv IEEE standard with round to nearest and no exceptions This mode is stateless and is compatible with the Java floating point arithmetic model This defines the symbol __FP_IEEE std IEEE finite values with denormals flushed to zero round to nearest and no exceptions This is compatible with standard C and C and is the default option Normal finite values are as predicted by the IEEE standard However NaNs and infinities might not be produced in all circumstances defined by the IEEE model When they are produced they might not have the same sign The sign of zero might not be that predicted by the IEEE model fast Perform more aggressive floating point optimizations that might cause a small loss of accuracy to provide a significant performance increase This option defines the symbol FP FAST This option results in behavior that is not fully compliant with the ISO C or C standard However numerically robust floating point programs are expected to behave correctly 2 40 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 2 1 54 fpu list ARM DUI 0348A See also Compiler Command line Options A number of transformations might be performed including Double precision math functions might be converted to single prec
171. Unions When a member of a union is accessed using a member of a different type the resulting value can be predicted from the representation of the original type No error is given Enumerations An object of type enum is implemented in the smallest integral type that contains the range of the enum The storage type of an enum is the first of the following according to the range of the enumerators in the enum unsigned char if not using enum_is_int signed char if not using enum_is_int unsigned short if not using enum_is_int signed short if not using enum_is_int signed int unsigned int except C with strict signed long long except C with strict unsigned long long except C with strict Implementing enum in this way can reduce data size The command line option enum is int forces the underlying type of enum to at least as wide as int Copyright O 2007 2010 ARM Limited All rights reserved 5 7 Non Confidential C and C Implementation Details See the description of C language mappings in the Procedure Call Standard for the ARM Architecture specification for more information Note Care must be taken when mixing translation units that have been compiled with and without the enum is int option and that share interfaces or data structures Handling values that are out of range In strict C enumerator values must be representable as ints for example they must be in the range 214
172. Usage The packed qualifier is useful to map a structure to an external data structure or for accessing unaligned data but it is generally not useful to save data size because of the relatively high cost of access Only packing fields in a structure that requires packing can reduce the number of unaligned accesses Note On ARM processors that do not support unaligned access in hardware for example pre ARMv6 access to unaligned data can be costly in terms of code size and execution speed Data accesses through packed structures must be minimized to avoid increase in code size and performance loss Restrictions The following restrictions apply to the use of __packed The __packed qualifier cannot be used on structures that were previously declared without __packed Unlike other type qualifiers you cannot have both a __packed and non __packed version of the same structure type e The __packed qualifier does not affect local variables of integral type A packed structure or union is not assignment compatible with the corresponding unpacked structure Because the structures have a different memory layout the only way to assign a packed structure to an unpacked structure is by a field by field copy Copyright 2007 2010 ARM Limited All rights reserved 4 11 Non Confidential Compiler specific Features The effect of casting away __packed is undefined The effect of casting a non packed structure to a packe
173. V 32 r0 00 0 int8 t vgetqg lane s8 int8x16 t vec constrange 0 15 int lane VMOV S8 r0 00 0 intl6 t vgetq lane sl6 intl16x8 t vec __constrange Q 7 int lane VMOV S16 r0 d0 0 int32 t vgetq lane s32 int32x4 t vec __constrange Q 3 int lane VMOV 32 r0 d0 0 poly8 t vgetq lane p8 poly8x16 t vec __constrange 15 int lane VMOV U8 r0 dQ Q polyl6 t vgetq lane pl6 poly16x8 t vec __constrange Q 7 int lane VMOV U16 r0 d0 0 float32 vgetq lane f32 float32x4 t vec constrange 0 3 int lane VMOV 32 r0 00 0 int64 t vget lane s64 int64x1l t vec constrange 0 0 int lane VMOV r0 r0 d uint64 t vget_lane_u64 uint64x1_t vec __constrange Q 0 int lane VMOV r0 r0 d0 int64_t vgetq_lane_s64 int64x2_t vec __constrange Q 1 int lane VMOV r0 r0 d0 uint64 t vgetq_lane_u64 uint64x2_t vec __constrange Q 1 int lane VMOV r0 r0 d0 E 3 17 Set lanes within a vector These intrinsics set a single lane element within a vector uint8x8 t vset_lane_u8 uint8_t value uint8x8 t vec __constrange 7 int lane NMOV 8 d0 0 r0 uintl6x4 t vset lane ul6 uintl6 t value uintl6x4 t vec constrange 0 3 int lane NMOV 16 d0 0 r0 uint32x2_t vset lane u32 uint32 t value uint32x2 t vec constrange 0 1 int lane NMOV 32 d0 0 r0 int8x8 t vset lane s8 int8 t value int8x8 t vec __constrange 7 int lane NMOV 8 d0 0 rO intl6x4 t vset lane sl16 intl6 t value intl6x4 t
174. _gen This option enables or disables the generation of object code When generation of object code is disabled the compiler performs syntax checking only without creating an object file Default The default is code_gen 2 1 16 no compile all input This option enables or disables the suppression of filename extension processing When enabled the compiler suppresses filename extension processing entirely treating all input files as if they have the suffix c Default The default is no compile all input See also File naming conventions on page 2 11 in the Compiler User Guide 2 1 17 cpp This option enables the compilation of C source code Default This option is implicitly selected for files having a suffix of cpp cxx C cc CC acpp or tcpp See also no_ anachronisms on page 2 3 c90 on page 2 13 c99 on page 2 13 gnu on page 2 44 2 14 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options e no_ strict on page 2 84 Source language modes on page 1 3 2 1 18 cpu list This option lists the supported architecture and processor names that can be used with the cpu name option See also cpu name 2 1 19 cpu name This option enables code generation for the selected ARM processor or architecture Syntax cpu name Where name is the name of a processor or architecture
175. _s16 int16x8_t vecl intl6x4 t val2 __constrange 3 int val3 VQDMULH S16 q0 q0 d0 0 vqdmulhq lane s32 int32x4 t vecl int32x2_t val2 constrange 0 1 int val3 VQDMULH S32 q0 q0 d0 0 Vector saturating rounding doubling multiply high with scalar vqrdmulh n s16 intl6x4 t vecl intl16 t val2 VQRDMULH S16 d0 d0 d0 0 vqrdmulh n s32 int32x2 t vecl int32 t val2 VQRDMULH S32 d0 d0 d0 0 vardmulhq_n_s16 int16x8_t vecl intl16 t val2 VQRDMULH S16 q0 q0 d0 0 vardmulhq_n_s32 int32x4_t vecl int32 t val2 VQRDMULH S32 q0 q0 d0 0 Vector rounding saturating doubling multiply high by scalar vqrdmulh lane s16 int16x4 t vecl intl6x4 t val2 constrange 0 3 int val3 VQRDMULH S16 d0 d0 d0 0 vqrdmulh lane s32 int32x2 t vecl int32x2_t val2 constrange 0 1 int val3 VQRDMULH S32 d0 d0 d0 0 vardmulhq_lane_s16 int16x8_t vecl intl6x4 t val2 constrange 0 3 int val3 VQRDMULH S16 q0 q0 d0 0 vqrdmulhg lane s32 int32x4 t vecl int32x2_t val2 constrange 0 1 int val3 VQRDMULH S32 q0 q0 d0 0 Vector multiply accumulate with scalar vmla n sl6 intl6x4 t a intl6x4 t b intl16 t c NMLA I16 00 d0 dO 0 vmla n s32 int32x2 t a int32x2 t b int32 t c NMLA I32 d0 d dO 0 vmla n ul6 uintl6x4 t a uintl6x4 t b uint16 t c NMLA I16 00 d dO 0 vmla_n_u32 uint32x2_t a uint32x2_t b uint32_t c NMLA I32 d 00 dO 0 t vmla n f32 float32x2 t a float32x2
176. _sort_list on page 4 50 4 3 10 __attribute__ unused The unused function attribute prevents the compiler from generating warnings if the function is not referenced This does not change the behavior of the unused function removal process Note This function attribute is a GNU compiler extension that is supported by the ARM compiler Example static int Function Attributes unused O int b attribute unused 4 3 11 attribute used This function attribute informs the compiler that a function is to be retained in the object even if it is unreferenced ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved 4 35 Non Confidential Compiler specific Features Function marked as used are emitted to a single section in the order they are declared You can specify the section functions are placed in using __attribute__ section Note This function attribute is a GNU compiler extension that is supported by the ARM compiler Note Variables might also be marked as used using the corresponding variable attribute attribute used Example int lose this int int keep this int attribute used retained in object file int keep this too int attribute used retained in object file See also attribute section on page 4 34 attribute used on page 4 47 4 3 12 attribute weak Functions defined with attribute weak
177. a type In this case it applies to all function parameters with that type Mode Supported in GNU mode only Example typedef union int myint float myfloat transparent_union_t ARM DUI 0348A Copyright 2007 2010 ARM Limited All rights reserved 4 45 Non Confidential Compiler specific Features void Variable Attributes transparent union 0 transparent union t aUnion __attribute__ transparent union i static int aStatic aStatic aUnion myint void Variable_Attributes_transparent_union_1 int aLocal 0 float bLocal 0 Variable_Attributes_transparent_union_ aLocal Variable_Attributes_transparent_union_ bLocal See also attribute transparent union on page 4 38 4 5 8 attribute unused 4 46 Normally the compiler warns if a variable is declared but is never referenced This attribute informs the compiler that you expect a variable to be unused and tells it not issue a warning if it is not used Note This variable attribute is a GNU compiler extension that is supported by the ARM compiler Example void Variable Attributes unused 0 i static int aStatic 0 int aUnused attribute unused int bUnused aStatic In this example the compiler warns that bUnused is declared but never referenced but does not warn about aUnused Note The GNU compiler does not give any warning Copyright 2007 2010 ARM Limited All rights reserved ARM
178. al reg ARM DUI 0348A Compiler specific Features The global reg storage class specifier allocates the declared variable to a global variable register Syntax __global_reg n type varName Where n Is an integer between one and eight type Is one of the following types any integer type except long long any char type any pointer type varName Is the name of a variable Restrictions If you use this storage class you cannot use any additional storage class such as extern static or typedef In C global register variables cannot be qualified or initialized at declaration In C any initialization is treated as a dynamic initialization The number of available registers varies depending on the variant of the AAPCS being used there are between five and seven registers available for use as global variable registers In practice it is recommended that you do not use more than three global register variables in ARM or Thumb 2 one global register variable in Thumb 1 half the number of available floating point registers as global floating point register variables If you declare too many global variables code size increases significantly In some cases your program might not compile Copyright O 2007 2010 ARM Limited All rights reserved 4 7 Non Confidential Compiler specific Features 4 8 Caution You must take care when using global register variables because e There is no check at link
179. and build numbers If you notice any errors or omissions in this book send email to errata arm com giving the document title the document number the page number s to which your comments apply a concise explanation of the problem General suggestions for additions and improvements are also welcome Copyright O 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Chapter 1 Introduction This chapter introduces the ARM compiler provided with RealView Compilation Tools RVCT It describes the standards of conformance and gives an overview of the runtime libraries provided with RVCT It contains the following sections ARM DUI 0348A About the ARM compiler on page 1 2 Source language modes on page 1 3 Language extensions and language compliance on page 1 5 The C and C libraries on page 1 8 Copyright O 2007 2010 ARM Limited All rights reserved 1 1 Non Confidential Introduction 1 1 About the ARM compiler The ARM compiler armcc enables you to compile your C and C code The compiler Is an optimizing compiler Command line options enable you to control the level of optimization Compiles ISO Standard C 1990 source SO Standard C 1999 source except for complex numbers and wide I O ISO Standard C 2003 source into 32 bit ARM code 16 32 bit Thumb 2 code 16 bit Thumb code Complies with the Base Standard Application Binary Interface for the ARM Ar
180. ange 3 int lane NST1 16 d 0 r0 vstl lane s32 transfersize 1 int32 t ptr int32x2 t val __constrange 1 int lane NST1 32 d 0 r0 vstl lane s64 transfersize 1 int64 t ptr int64x1_t val constrange 0 0 int lane NST1 64 d0 r0 vstl lane f32 transfersize 1 float32 t ptr float32x2 t val __ NST1 32 d 0 r0 vstl lane p8 transfersize 1 poly8 t ptr poly8x8 t val __constrange 7 int lane NST1 8 d0 0 r0 vstl lane pl6 transfersize 1 poly16 t ptr poly16x4_t val __ NST1 16 d 0 r0 constrange 0 3 int lane constrange 0 1 int lane constrange 0 3 int lane constrange 0 7 int lane constrange 0 3 int lane constrange 0 1 int lane constrange 0 0 int lane constrange 0 1 int lane constrange 0 3 int lane E 3 15 Loads and stores of an N element structure These intrinsics load or store an n element structure The array structures are defined similarly for example the int16x4x2 t structure is defined as ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved E 29 Non Confidential Using NEON Support struct intl6x4x2 t i intl6x4 t val 2 uint8x16x2 t vld2q_u8 __transfersize 32 uint8 t const ptr VLD2 8 100 d2 r0 uintl6x8x2 t vld2q_u16 __transfersize 16 uintl6 t const ptr VLD2 16 100 d2 r0 uint32x4x2 t vld2q u32 transfersize 8 uint32 t const ptr N
181. ange of comparison intrinsics are provided If the comparison is true for a lane the result in that lane is all bits set to one If the comparison is false for a lane all bits are set to zero The return type is an unsigned integer type This means that you can use the result of a comparison as the first argument for the vbsl intrinsics Vector compare equal uint8x8 t vceq s8 int8x8 t a int8x8 t b NCEQ I8 00 00 00 uintl6x4 t vceq sl6 intl6x4 t a intl6x4 t b VCEQ 116 00 d 00 uint32x2 t vceq s32 int32x2 t a int32x2 t b NCEQ I32 00 00 00 uint32x2 t vceq f32 float32x2 t a float32x2 t b VCEQ F32 00 d dQ uint8x8 t vceq u8 uint8x8 t a uint8x8 t b NCEQ I8 00 00 00 uintl6x4 t vceq ul6 uintl6x4 t a uintl6x4 t b VCEQ 116 00 d 00 uint32x2 t vceq u32 uint32x2 t a uint32x2 t b VCEQ 132 00 00 00 uint8x8 t vceq p8 poly8x8 t a poly8x8_t b NCEQ I8 d d0 00 uint8x16 t vceqq s8 int8x16 t a int8x16 t b NCEQ I8 q0 q0 q0 uintl6x8 t vceqq sl6 intl6x8 t a intl16x8 t b VCEQ 116 q0 00 q0 uint32x4 t vceqq s32 int32x4 t a int32x4 t b VCEQ 132 q0 00 q0 uint32x4 t vceqq f32 float32x4 t a float32x4 t b VCEQ F32 q0 q0 q0 uint8x16 t vceqq u8 uint8x16 t a uint8x16 t b NCEQ I8 q0 q0 q0 uintl6x8 t vceqq ul6 uintl6x8 t a uintl6x8 t b VCEQ I16 q0 q q0 uint32x4 t vceqq u32 uint32x4 t a uint32x4 t b VCEQ 132 q0 q0 q0 uint8x16 t vceqq p8 poly8x16 t a poly8x1
182. ar 127 0x7F SCHAR MIN Minimum value of signed char 128 0x80 UCHAR MAX Maximum value of unsigned char 255 OxFF SHRT_MAX Maximum value of short 32767 Ox7FFF SHRT_MIN Minimum value of short 32 768 0x8000 USHRT MAX Maximum value of unsigned short 65535 OxFFFF INT MAX Maximum value of int 2147483647 Ox7FFFFFFF INT MIN Minimum value of int 2 147483648 0x80000000 LONG MAX Maximum value of long 2147483647 Ox7FFFFFFF LONG MIN Minimum value of long 2 147483648 0x80000000 ULONG_MAX Maximum value of unsigned long 4294967295 OxFFFFFFFF LLONG MAX Maximum value of long long 9 2E 18 Ox7FFFFFFF FFFFFFFF LLONG MIN Minimum value of long long 9 2E 18 0x80000000 00000000 ULLONG MAX Maximum value of unsigned long long 1 8E 19 OxFFFFFFFF FFFFFFFF Non Confidential Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A C and C Compiler Implementation Limits D 3 Limits for floating point numbers This section describes the characteristics of floating point numbers Table D 3 gives the characteristics ranges and limits for floating point numbers These constants are defined in the float h include file Table D 3 Floating point limits Constant Meaning Value FLT MAX Maximum value of float 3 40282347e 38F FLT_MIN Minimum normalized positive floating point number value of 1 17549435e 38F float DBL_MAX Maximum value of double 1 797693134862
183. aration of f is followed by its definition 5 2 5 Template instantiation ARM DUI 0348A The ARM compiler does all template instantiations automatically and makes sure there is only one definition of each template entity left after linking The compiler does this by emitting template entities in named common sections Therefore all duplicate common sections that is common sections with the same name are eliminated by the linker Note You can limit the number of concurrent instantiations of a given template with the pending instantiations compiler option See also pending instantiations n on page 2 73 for more information Implicit inclusion When implicit inclusion is enabled the compiler assumes that if it requires a definition to instantiate a template entity declared in a h file it can implicitly include the corresponding cc file to get the source code for the definition For example if a template entity ABC f is declared in file xyz h and an instantiation of ABC f is required in a compilation but no definition of ABC f appears in the source code processed by the compilation then the compiler checks to see if a file xyz cc exists If this file exists the compiler processes the file as if it were included at the end of the main source file To find the template definition file for a given template entity the compiler has to know the full path name of the file where the template is declared and whether the
184. ard C language extensions The compiler supports numerous extensions to the ISO C99 standard for example function prototypes that override old style non prototype definitions These extensions are available if the source language is C99 and you are compiling in non strict mode the source language is C90 and you are compiling in non strict mode None of these extensions is available if the source language is C90 and the compiler is restricted to compiling strict C90 using the strict compiler option the source language is C99 and the compiler is restricted to compiling strict Standard C using the strict compiler option the source language is C 3 4 1 Constant expressions Extended constant expressions are supported in initializers The following examples show the compiler behavior for the default strict_warnings and strict compiler modes Example 1 assigning the address of variable Your code might contain constant expressions that assign the address of a variable at file scope for example int i int j int amp i but not allowed by ISO When compiling for C this produces the following behavior In default mode a warning is produced In strict_warnings mode a warning is produced In strict mode an error is produced Example 2 constant value initializers The compiler behavior when you have expressions that include constant values in C code is summarized in the followi
185. ariable length array dynamically allocated return sizeof array evaluated at runtime See also c90 on page 2 13 c99 on page 2 13 cpp on page 2 14 gnu on page 2 44 Copyright 2007 2010 ARM Limited All rights reserved 2 93 Non Confidential Compiler Command line Options 2 1 124 vsn 2 1 125 W 2 1 126 wchar16 2 1 127 wchar32 2 94 This option displays the version information and the license details See also help on page 2 45 This option instructs the compiler to suppress all warning messages See also no_ brief_diagnostics on page 2 10 diag error tag tag on page 2 26 diag remark tag tag on page 2 27 e diag_style armlidelgnu on page 2 27 diag suppress tag tag on page 2 28 diag warning tag tag on page 2 30 errors filename on page 2 34 remarks on page 2 78 no_ wrap_diagnostics on page 2 96 This option changes the type of wchar_t to unsigned short Selecting this option modifies both the type of the defined type wchar t in C and the type of the native type wchar t in C It also affects the values of WCHAR MIN and WCHAR MAX Default The compiler assumes wchar16 unless wchar32 is explicitly specified See also wchar32 Predefined macros on page 4 103 This option changes the type of wchar t to unsigned int Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0
186. assembler automatically whenever it is invoked by the compiler For example if the option cpu is specified on the compiler command line then this option is passed to the assembler whenever it is invoked to assemble s files or embedded assembler To see the compiler command line options passed by the compiler to the assembler use the compiler command line option A show_cmdline Example armcc A predefine NEWVERSION SETL TRUE main c Restrictions If an unsupported option is passed through using A an error is generated See also cpu name on page 2 15 Lopt on page 2 52 show_cmdline on page 2 81 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options 2 1 2 no alternative tokens This option enables or disables the recognition of alternative tokens in C and C Default The default 15 alternative tokens Usage In C and C use this option to control recognition of the digraphs In C use this option to control recognition of operator keywords for example and and bitand 2 1 3 no_ anachronisms ARM DUI 0348A This option enables or disables anachronisms in C Mode This option is effective only if the source language is C Default The default is no_anachronisms Example typedef enum red white blue tricolor inline tricolor operator tricolor c int int i static_cast lt int gt c
187. at shows the current version of the GNU mode being used WCHAR T In C mode to specify that wchar t is a keyword WCHAR TYPE In GNU mode It defines the correct underlying type for the wchar t typedef WCHAR UNSIGNED In GNU mode when you specify the cpp option It is defined if and only if wchar_t is an unsigned type MWINT TYPE In GNU mode It defines the correct underlying type for the wint_t typedef 4 8 2 Function names Table 4 19 lists builtin variables supported by the ARM compiler for C and C Table 4 19 Builtin variables Name Value FUNCTION Holds the name of the function as it appears in the source FUNCTION is a constant string literal You cannot use the preprocessor to join the contents to other text to form new tokens PRETTY FUNCTION Holds the name of the function as it appears pretty printed in a language specific fashion PRETTY FUNCTION is a constant string literal You cannot use the preprocessor to join the contents to other text to form new tokens ARM DUI 0348A Copyright 2007 2010 ARM Limited All rights reserved 4 107 Non Confidential Compiler specific Features 4 108 Copyright O 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Chapter 5 C and C Implementation Details This chapter describes the language implementation details for the ARM compiler It includes
188. attribute const int Function Attributes const 2 int b int aLocal 0 aLocal Function Attributes const 0 b aLocal Function Attributes const 0 b return aLocal Copyright 2007 2010 ARM Limited All rights reserved 4 31 Non Confidential Compiler specific Features In this code Function Attributes const 0 might be called once only with the result being doubled to obtain the correct return value See also attribute pure on page 4 33 pure on page 4 15 in the Compiler User Guide 4 3 4 attribute deprecated This function attribute indicates that a function exists but the compiler must generate a warning if the deprecated function is used Note This function attribute is a GNU compiler extension that is supported by the ARM compiler Example int Function Attributes deprecated O int b attribute deprecated 4 3 5 attribute malloc This function attribute indicates that the function can be treated like malloc and the associated optimizations can be performed Note This function attribute is a GNU compiler extension that is supported by the ARM compiler Example void Function Attributes malloc O0 int b attribute malloc 4 3 6 attribute noinline This function attribute suppresses the inlining of a function at the call points of the function 4 32 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 03
189. attribute__ const Example int Function Attributes pure O int b attribute pure int Function Attributes pure O int b i static int aStatic aStatic return b int Function Attributes pure 2 int b i int aLocal 0 aLocal Function Attributes pure 0 b return 0 The call to Function Attributes pure 0 in this example might be eliminated because its result is not used 4 3 9 attribute section The section function attribute enables you to place code in different sections of the image Note This function attribute is a GNU compiler extension that is supported by the ARM compiler Example In the following example Function Attributes section 0 is placed into the RO section new section rather than text void Function Attributes section 0 void attribute section new section void Function Attributes section 0 void static int aStatic 0 aStatic 4 34 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler specific Features In the following example section function attribute overrides the pragma arm section setting pragma arm section code foo int f2 return 1 into the foo area __attribute__ section bar int f3 return 1 into the bar area int f4 return 1 into the foo area pragma arm section See also e pragma arm section section
190. atures of C99 on page 1 5 in the Compiler User Guide 3 6 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Language Extensions 3 3 C99 language features available in C and C90 The compiler supports numerous extensions to the ISO C standard and to the C90 language for example function prototypes that override old style non prototype definitions These extensions are available if the source language is C and you are compiling in non strict mode the source language is C90 and you are compiling in non strict mode These extensions are not available if the source language is C and the compiler is restricted to compiling strict C90 using the strict compiler option the source language is C90 and the compiler is restricted to compiling strict Standard C using the strict compiler option Note Language features of Standard C for example long long integers might be similar to the language extensions described in this section Such features continue to remain available if you are compiling strict standard C or strict C90 using the strict compiler option 3 3 1 Variadic macros ARM DUI 0348A In C90 and C you can declare a macro to accept a variable number of arguments The syntax for declaring a variadic macro in C90 and C follows the C99 syntax for declaring a variadic macro unless the option gnu is selected If the option gnu is specified the s
191. ax sl6 intl6x4 t a intl6x4 t b vpmax s32 int32x2 t a int32x2 t b vpmax u8 uint8x8 t a uint8x8 t b vpmax ul6 uintl6x4 t a uintl6x4 t b vpmax u32 uint32x2 t a uint32x2 t b vpmin takes minimum of adjacent pairs int8x8 t intl6x4 t int32x2 t Copyright O 2007 2010 ARM Limited All rights reserved vpmin_s8 int8x8_t a int8x8 t b vpmin sl6 intl6x4 t a intl6x4 t b vpmin_s32 int32x2_t a int32x2 t b Non Confidential NPMAX NPMAX NPMAX NPMAX NPMAX NPMAX NPMAX NPMIN NPMIN NPMIN Using NEON Support S8 d0 d0 S16 d0 d0 S32 d0 d0 U8 00 00 U16 d0 d0 U32 d0 d0 S8 q0 q0 S16 q0 q0 332 q0 q0 U8 q0 q0 U16 q0 q0 U32 q0 q0 S8 d0 d0 d0 S16 d0 d0 d0 S32 00 00 00 U8 d0 d0 d0 U16 d0 d0 d0 U32 d0 d0 d0 F32 d0 d0 d0 S8 00 00 00 S16 d0 d0 d0 S32 00 00 00 Using NEON Support uint8x8_t vpmin u8 uint8x8 t a uint8x8 t b NPMIN U8 d0 d0 d0 uintl6x4 t vpmin ul6 uintl6x4 t a uintl6x4 t b VPMIN U16 d0 d0 d0 uint32x2 t vpmin u32 uint32x2 t a uint32x2 t b VPMIN U32 d0 d0 d0 float32x2 t vpmin f32 float32x2 t a float32x2 t b VPMIN F32 d0 d0 d0 E 3 10 Reciprocal Sqrt Reciprocal estimate step and 1 sqrt estimate step float32x2_t vrecps f32 float32x2 t a float32x2 t b VRECPS F32 00 00 dQ float32x4 t vrecpsq f32 float32x4 t a float32x4 t b VRECPS F32 q0 q0 q0 float32x2 t vrsqrts f32 float32x2 t a float32x2 t b VR
192. be similar to the C90 language extensions described in this section Such features continue to remain available if you are compiling strict Standard C or strict Standard C using the strict compiler option The character sequence starts a one line comment just as in C99 or C comments in C90 have the same semantics as comments in C99 Example this is a comment See also New features of C99 on page 1 5 in the Compiler User Guide 3 2 2 Subscripting struct ARM DUI 0348A In C90 arrays that are not lvalues still decay to pointers and can be subscripted However you must not modify or use them after the next sequence point and you must not apply the unary amp operator to them Arrays of this kind can be subscripted in C90 but they do not decay to pointers outside C99 mode Example struct Subscripting Struct int a 4 Copyright 2007 2010 ARM Limited All rights reserved 3 5 Non Confidential Language Extensions extern struct Subscripting_Struct Subscripting 0 void int Subscripting_1 int index i return Subscripting 0 a index 3 2 3 Flexible array members The last member of a struct can have an incomplete array type The last member must not be the only member of the struct otherwise the struct is zero in size Example typedef struct int len char p incomplete array type for use in a malloced data structure str See also New fe
193. be used to describe the function which assists smart linkers with table optimization Function inlining is restricted because the caller and callee must interact correctly Therefore pragma no_exceptions_unwind can be used to forcibly prevent unwinding in a way that requires no additional source decoration By contrast in C an empty function exception specification permits unwinding as far as the protected function then calls std unexpected in accordance with the ISO C Standard Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential C and C Implementation Details 5 2 8 Extern inline functions ARM DUI 0348A The ISO C Standard requires inline functions to be defined wherever you use them To prevent the clashing of multiple out of line copies of inline functions the C compiler emits out of line extern functions in common sections Out of line inline functions The compiler emits inline functions out of line in the following cases The address of the function is taken for example inline int g int fp amp g return 1 The function cannot be inlined for example a recursive function inline int g return g The heuristic used by the compiler decides that it is better not to inline the function This heuristic is influenced by Ospace and Otime If you use Otime the compiler inlines more functions You can override this heurist
194. bject file This might lead to unpredictable results See also c on page 2 12 interleave on page 2 50 no_ multifile on page 2 63 o filename on page 2 65 S on page 2 80 File naming conventions on page 2 11 in the Compiler User Guide 2 1 7 no autoinline ARM DUI 0348A This option enables or disables automatic inlining of functions The compiler automatically inlines functions where it is sensible to do so The Ospace and Otime options together with some other factors such as function size influence how the compiler automatically inlines functions Selecting Otime in combination with various other factors increases the likelihood that functions are inlined Default For optimization levels 00 and 01 the default is no_autoinline For optimization levels 02 and 03 the default is autoinline Copyright O 2007 2010 ARM Limited All rights reserved 2 9 Non Confidential Compiler Command line Options 2 1 8 2 1 9 2 10 bigend See also forceinline on page 2 39 no_Jinline on page 2 49 Onum on page 2 66 Ospace on page 2 68 Otime on page 2 69 This option instructs the compiler to generate code for an ARM processor using big endian memory ARMvV6 supports two different big endian modes BE8 ARMv6 Byte Invariant Addressing mode BE32 Legacy big endian mode The selection of BE8 versus BE32 is specified at link time Default The compiler a
195. ble if the source language is C and you are compiling in non strict mode These extensions are not available if the source language is C and the compiler is restricted to compiling strict Standard C using the strict compiler option A operator whose second and third operands are string literals or wide string literals can be implicitly converted to char or wchar t In C string literals are const There is an implicit conversion that enables conversion of a string literal to char or wchar t dropping the const That conversion however applies only to simple string literals Permitting it for the result of a operation is an extension Example char sp x abc def 3 5 2 Declaration of a class member 3 5 3 friend ARM DUI 0348A A qualified name can be used in the declaration of a class member Errors A warning is issued if a qualified name is used in the declaration of a class member Example struct A int A f is the same as int f A friend declaration for a class can omit the class keyword Access checks are not carried out on friend declarations by default Use the strict command line option to force access checking Copyright O 2007 2010 ARM Limited All rights reserved 3 15 Non Confidential Language Extensions Example class B class A friend B is the same as friend class B See also no_ strict on page 2 84 3 5 4 Read write c
196. both prefix and postfix operations The base class name can be omitted in a base class initializer if there is only one immediate base class Assignment to the this pointer in constructors and destructors is permitted A bound function pointer that is a pointer to a member function for a given Object can be cast to a pointer to a function A nested class name can be used as a non nested class name provided no other class of that name has been declared The anachronism is not applied to template classes A reference to a non const type can be initialized from a value of a different type A temporary is created it is initialized from the converted initial value and the reference is set to the temporary A reference to a non const class type can be initialized from an rvalue of the class type or a class derived from that class type No additional temporary is used A function with old style parameter declarations is permitted and can participate in function overloading as if it were prototyped Default argument promotion is not applied to parameter types of such functions when the check for compatibility is done so that the following declares the overloading of two functions named f int f int int f x char x return x Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential C and C Implementation Details Note In C this code is legal but has a different meaning A tentative decl
197. change in source position That is the line has a format similar to the line identifying directive output by the preprocessor L line number filename key where key can be 1 For entry into an include file 2 For exit from an include file ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved 2 55 Non Confidential Compiler Command line Options 2 56 Otherwise key is omitted The first line in the raw listing file is always an L line identifying the primary input file L lines are also output for line directives where key is omitted L lines indicate the source position of the following source line in the raw listing file R W E Indicates a diagnostic where R Indicates a remark W Indicates a warning E Indicates an error The line has the form type filename line number column number message text where type can be R W or E Errors at the end of file indicate the last line of the primary source file and a column number of zero Command line errors are errors with a filename of command line No line or column number is displayed as part of the error message Internal errors are errors with position information as usual and message text beginning with Internal fault When a diagnostic message displays a list for example all the contending routines when there is ambiguity on an overloaded call the initial diagnostic line is followed by one or more lines with the same overall format However
198. chitecture BSABI In particular the compiler Generates output objects in ELF format Generates DWARF Debugging Standard Version 3 DWARF 3 debug information RVCT also contains support for DWARF 2 debug tables See ABI for the ARM Architecture compliance on page 1 3 in the Libraries Guide for more information Can generate an assembly language listing of the output code and can interleave an assembly language listing with source code If you are upgrading to RVCT from a previous release or are new to RVCT ensure that you read RealView Compilation Tools Essentials Guide for the latest information Copyright O 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Introduction 1 2 Source language modes 1 21 ISO C90 1 2 2 ISO C99 ARM DUI 0348A The ARM compiler has three distinct source language modes that you can use to compile different varieties of C and C source code These are ISO C90 ISO C99 ISO C The ARM compiler compiles C as defined by the 1990 C standard and addenda excepting wide I O ISO IEC 9899 1990 The 1990 International Standard for C e ISO IEC 9899 AM1 The 1995 Normative Addendum 1 adding international character support through wchar h and wtype h The ARM compiler also supports several extensions to ISO C90 See Language extensions and language compliance on page 1 5 for more information Throughout this document the term C90 Means ISO C90
199. compiler sets the diagnostic messages having the specified tags to Warning severity rather than Error severity Note This option has the pragma equivalent pragma diag_warning Syntax diag warning tag tag Where tag tag is a comma separated list of diagnostic message numbers specifying the messages whose severities are to be changed See also diag_error tag tag on page 2 26 diag remark tag tag on page 2 27 diag suppress tag tag on page 2 28 pragma diag warning tag tag on page 4 54 Changing the severity of diagnostic messages on page 5 5 in the Compiler User Guide Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options 2 1 36 diag_warning optimizations This option sets high level optimization diagnostic messages to have Warning severity Default By default optimization messages have Remark severity Usage The compiler performs certain high level vector and scalar optimizations when compiling at the optimization level 03 Otime for example loop unrolling Use this option to display diagnostic messages relating to these high level optimizations Example int factorial int n int result 1 while n gt 0 result n return result Compiling this code with the options vectorize cpu Cortex A8 03 Otime diag_warning optimizations generates optimization wa
200. crease in execution time Use this option if code size is more critical than performance For example when the Ospace option is selected large structure copies are done by out of line function calls instead of inline code If required you can compile the time critical parts of your code with Otime and the rest with Ospace Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 2 1 90 Otime ARM DUI 0348A Compiler Command line Options Default If you do not specify either Ospace or Otime the compiler assumes Ospace See also Otime Onum on page 2 66 pragma Onum on page 4 57 pragma Ospace on page 4 58 pragma Otime on page 4 58 This option instructs the compiler to perform optimizations to reduce execution time at the expense of a possible increase in image size Use this option if execution time is more critical than code size If required you can compile the time critical parts of your code with Otime and the rest with Ospace Default If you do not specify Otime the compiler assumes Ospace Example When the Otime option is selected the compiler compiles while expression body as if expression do body while expression See also no_ multifile on page 2 63 Onum on page 2 66 Ospace on page 2 68 pragma Onum on page 4 57 pragma Ospace on page 4 58 Copyright O 2007 2010 ARM Limited All rights reserved
201. ct keyword behaves like svc indirect but uses r7 instead of r12 __svcindirect_r7 is a function qualifier It affects the type of a function Syntax svc indirect r7 int svc num return type function name int rea num argument list Where Svc num Is the immediate value used in the SVC instruction It is an expression evaluating to an integer in the range 0 to 274 1 a 24 bit value in an ARM instruction Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler specific Features 0 255 an 8 bit value in a 16 bit Thumb instruction real num Is the value passed in r7 to the handler to determine the function to perform Usage Thumb applications on ARM Linux use svc indirect r7 to make kernel syscalls You can also use this feature to implement indirect SVCs Example long svc indirect r7 0 SVC write unsigned int fd const char buf size t count define write fd buf count SVC write 4 fd buf count Calling write fd buf count compiles to SVC 0 with r0 fd r1 buf r2 count and r7 4 Errors When an ARM architecture variant or ARM architecture based processor that does not support an SVC instruction is specified on the command line using the cpu option the compiler generates an error See also E value in regs cpu name on page 2 15 SVC on page 4 130 in the Assembler Guide 4 1 18 __value_in_regs ARM DUI
202. ctive only if the source language is C Copyright 2007 2010 ARM Limited All rights reserved 2 79 Non Confidential Compiler Command line Options 2 1 106 S Default The default is rtti See also no_ dllimport_runtime on page 2 32 This option instructs the compiler to output the disassembly of the machine code generated by the compiler to a file Unlike the asm option object modules are not generated The name of the assembly output file defaults to fi Tename s in the current directory where filename is the name of the source file stripped of any leading directory names The default filename can be overridden with the o option You can use armasm to assemble the output file and produce object code The compiler adds ASSERT directives for command line options such as AAPCS variants and byte order to ensure that compatible compiler and assembler options are used when reassembling the output You must specify the same AAPCS settings to both the assembler and the compiler See also asm on page 2 8 c on page 2 12 info totals on page 2 48 e interleave on page 2 50 list on page 2 55 o filename on page 2 65 2 1 107 un signed_bitfields 2 80 This option makes bitfields of type int signed or unsigned The C Standard specifies that if the type specifier used in declaring a bitfield is either int or a typedef name defined as int then whether the bitfield is signed or unsigned is
203. d extern Ce read write const int i 5 placed in read only segment not extern because implicitly static extern const T x 6 placed in read write segment struct S static const T T x placed in read write segment Constant objects must not be redeclared with another linkage The code in Example 3 3 produces a compile error Example 3 3 Compiler error extern C const T x extern C read write const T x error Note Because C does not have the linkage specifications you cannot use a const object declared in C as extern C read write from C See also apcs qualifer qualifier on page 2 4 3 5 5 Scalar type constants Constants of scalar type can be defined within classes This is an old form The modern form uses an initialized static data member ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved 3 17 Non Confidential Language Extensions Errors A warning is issued if you define a member of constant integral type within a class Example class A i const int size 10 must be static const int size 10 int a size ie 3 5 6 Type conversions Type conversion between a pointer to an extern C function and a pointer to an extern C function is permitted Example extern C void f f s type has extern C linkage void pf amp f pf points to an extern C function error unless implicit conversi
204. d void void void void void void void void E 38 vst3_f32 __transfersize 6 float32 t ptr float32x2x3 t val NST3 32 100 01 02 r0 vst3 p8 transfersize 24 poly8 t ptr poly8x8x3 t val NST3 8 100 d1 02 r0 vst3 016 transfersize 12 polyl6 t ptr poly16x4x3_t val NST3 16 100 01 02 r0 vst4q u8 transfersize 64 uint8 t ptr uint8x16x4 t val NST4 8 100 02 04 06 r0 vst4q ul6 transfersize 32 uint16 t ptr uintl6x8x4 t val NST4 16 100 02 d4 d6 r0 vst4q u32 transfersize 16 uint32 t ptr uint32x4x4 t val NST4 32 d0 02 d4 06 r0 vst4q s8 transfersize 64 int8 t ptr int8x16x4 t val VST4 8 d0 d2 d4 d6 r0 vst4q s16 transfersize 32 int16 t ptr intl6x8x4 t val NST4 16 100 02 d4 d6 r0 vst4q s32 transfersize 16 int32 t ptr int32x4x4 t val NST4 32 100 02 d4 d6 r0 vst4q f32 transfersize 16 float32 t ptr float32x4x4 t val NST4 32 100 02 04 d6 r0 vst4q p8 transfersize 64 poly8 t ptr poly8x16x4 t val NST4 8 100 02 04 06 r0 vst4q 016 transfersize 32 polyl6 t ptr poly16x8x4_t val NST4 16 100 02 d4 d6 r0 vst4 u8 transfersize 32 uint8 t ptr uint8x8x4 t val NST4 8 100 d1 02 d3 r0 vst4 ul6 transfersize 16 uint16 t ptr uintl6x4x4 t val NST4 16 d0 d1 d2 d3 r9 vst4 u32 transfersize 8 uint32 t ptr uin
205. d C extensions The compiler supports numerous extensions to strict C99 for example function prototypes that override old style non prototype definitions See Standard C language extensions on page 3 10 for more information These extensions to Standard C are also available in C90 Standard C extensions The compiler supports numerous extensions to strict C for example qualified names in the declaration of class members See Standard C language extensions on page 3 15 for more information These extensions are not available in either Standard C or C90 Standard C and Standard C extensions The compiler supports some extensions specific to strict C and strict C90 for example anonymous classes structures and unions See Standard C and standard C language extensions on page 3 19 for more information Copyright 2007 2010 ARM Limited All rights reserved 1 5 Non Confidential Introduction 1 3 2 1 6 GNU extensions The compiler supports some extensions offered by the GNU compiler for example GNU style extended lvalues and GNU builtin functions For more information see Language compliance s GNU language extensions on page 3 25 Chapter 4 Compiler specific Features ARM specific extensions Language compliance The compiler supports a range of extensions specific to the ARM compiler for example instruction intrinsics and other builtin functions See Chapter 4 Compiler specific Features for
206. d RunTime Type Information RTTI for classes with a key function A key function is the first virtual function of a class in declaration order that is not inline and is not pure virtual Note You can disable export for specific classes by using declspec notshared See also __declspec notshared on page 4 27 2 1 48 no export defs implicitly This option controls how dynamic symbols are exported Default The default is no export defs implicitly Usage Use the option export defs implicitly to export definitions where the prototype is marked declspec dllimport See also __declspec dllimport on page 4 25 2 1 49 no_ extended_initializers This option enables the use of extended constant initializers even when compiling with strict or strict_warnings 2 36 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options When certain non portable but widely supported constant initializers such as the cast of an address to an integral type are used extended_initializers causes the compiler to produce the same general warning concerning constant initializers that it normally produces in non strict mode rather than specific errors stating that the expression must have a constant value or have arithmetic type Default The default is no extended initializers when compiling with strict or strict warnings The default is
207. d by the intrinsics To obtain the name of the basic instruction realized by an intrinsic drop the leading underscores __ from the intrinsic name For example the __qadd16 intrinsic corresponds to an ARMv6 QADD16 instruction Copyright 2007 2010 ARM Limited All rights reserved 4 95 Non Confidential Compiler specific Features 4 96 Note Each ARMv6 SIMD intrinsic is guaranteed to be compiled into a single inline machine instruction for an ARM v6 architecture or processor However the compiler might use optimized forms of underlying instructions when it detects opportunities to do so The ARMv6 SIMD instructions can set the GE 3 0 bits in the Application Program Status Register APSR The SIMD instructions might update these flags to indicate the greater than or equal to status of each 8 16 bit slice of a SIMD operation The ARM compiler treats the GE 3 0 bits as a global variable To access these bits from within your C or C program either access bits 16 19 of the APSR through a named register variable use the __sel intrinsic to control a SEL instruction unsigned int qaddl6 unsigned int unsigned int unsigned int qadd8 unsigned int unsigned int unsigned int __qasx unsigned int unsigned int unsigned int __qsax unsigned int unsigned int unsigned int qsubl6 unsigned int unsigned int unsigned int __qsub8 unsigned int unsigned int unsigned int __sadd1l6 unsigned int unsigned int unsig
208. d for mixed ARM Thumb systems for processors that support ARMv4T or ARMVST then you must specify the interworking option apcs interwork By default this is enabled for processors that support ARMvST or above If you compile for Thumb that is with the thumb option on the command line the compiler compiles as much of the code as possible using the Thumb instruction set However the compiler might generate ARM code for some parts of the compilation For example if you are compiling code for a Thumb 1 processor and using VFP any function containing floating point operations is compiled for ARM If you are compiling code for ARMv7 M for example cpu Cortex M3 you do not need to specify thumb on the command line because ARMv7 M supports Thumb 2 only Restrictions You cannot specify both a processor and an architecture on the same command line See also apcs qualifer qualifier on page 2 4 cpu list on page 2 15 fpu name on page 2 42 thumb on page 2 86 create pch filename This option instructs the compiler to create a PreCompiled Header PCH file with the specified filename This option takes precedence over all other PCH options Syntax create_pch f1lename Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Where filename See also Compiler Command line Options is the name of the PCH file to be created pch on page 2 70
209. d off by default and the smallest data type is used that can hold the values of all enumerators Note The enum_is_int option is not recommended for general use errors filename This option redirects the output of diagnostic messages from stderr to the specified errors file Syntax errors filename Where filename is the name of the file to which errors are to be redirected Diagnostics that relate to problems with the command options are not redirected for example if you type an option name incorrectly However if you specify an invalid argument to an option for example cpu 999 the related diagnostic is redirected to the specified filename See also no_ brief_diagnostics on page 2 10 diag_error tag tag on page 2 26 diag remark tag tag on page 2 27 e diag_style armlidelgnu on page 2 27 diag suppress tag tag on page 2 28 diag warning tag tag on page 2 30 remarks on page 2 78 W on page 2 94 no_ wrap_diagnostics on page 2 96 Chapter 5 Diagnostic Messages in the Compiler User Guide Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options 2 1 45 no exceptions This option enables or disables exception handling In C the exceptions option enables the use of throw and try catch causes function exception specifications to be respected and causes the compiler to
210. d structure is undefined A pointer to an integral type can be legally cast explicitly or implicitly to a pointer to a packed integral type You can also cast away the packed on char types There are no packed array types A packed array is an array of objects of packed type There is no padding in the array Example Example 4 4 shows that a pointer can point to a packed type Example 4 4 Pointer to packed typedef __packed int Ppl pointer to a __packed int __packed int p pointer to a packed int Ppl p2 p2 has the same type as p packed is a qualifier just like const or volatile typedef int PI pointer to int __packed PI p3 a packed pointer to a normal int not the same type as p and p2 int packed p4 p4 has the same type as p3 Example 4 5 shows that when a packed object is accessed using a pointer the compiler generates code that works and that is independent of the pointer alignment Example 4 5 Packed structure typedef packed struct char x all fields inherit the packed qualifier int y PX 5 byte structure natural alignment 1 int f X xp return p gt y does an unaligned read typedef struct Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 4 1 12 pure ARM DUI 0348A Compiler specific Features short x char y __packed int z only pack th
211. d3q_lane_u32 __transfersize 3 uint32 t const ptr uint32x4x3 t src __constrange 0 3 int lane VLD3 32 100 0 d2 0 d4 0 rd intl6x8x3 t vld3q_lane_s16 __transfersize 3 intl6 t const ptr intl6x8x3 t src constrange 0 7 int lane VLD3 16 100 0 d2 0 d4 0 r0 int32x4x3 vld3q lane s32 transfersize 3 int32 t const ptr int32x4x3 t src constrange 0 3 int lane VLD3 32 100 0 d2 0 d4 0 rd float32x4x3 vld3q_lane_f32 __transfersize 3 float32 t const ptr float32x4x3_t src __constrange 3 int lane E 34 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Using NEON Support NLD3 32 100 0 d2 0 d4 r0 poly16x8x3_t vld3q_lane_p16 __transfersize 3 polyl6 t const ptr polyl6x8x3 t src __constrange 0 7 int lane NLD3 16 100 0 d2 0 d4 r0 uint8x8x3 t v1d3 lane u8 transfersize 3 uint8 t const ptr uint8x8x3 t src constrange 0 7 int lane VLD3 8 100 0 di 0 d2 0 uint16x4x3_t vld3 lane u16 transfersize 3 uintl6 t const ptr uintl6x4x3 t src int lane constrange 0 3 VLD3 16 100 0 d1 0 d2 r0 uint32x2x3 t vld3 lane u32 transfersize 3 uint32 t const ptr uint32x2x3 t src int lane constrange 0 1 VLD3 32 d0 0 d1 0 d2 rd int8x8x3 t 1103 lane s8 transfersize 3 int8 t const ptr int8x8x3 t src constrange 0 7 int lane VLD3 8 1
212. dard header file dspfns h The intrinsics supplied in dspfns h are listed in Table 4 13 Table 4 13 ETSI basic operations supported in RVCT Intrinsics abs s L add c L mult L sub c norm 1 add L deposit h L negate mac r round div 5 L deposit 1 L sat msu saturate extract h L_mac L_shl mult sh ARM DUI 0348A Copyright 2007 2010 ARM Limited All rights reserved 4 97 Non Confidential Compiler specific Features Table 4 13 ETSI basic operations supported in RVCT continued Intrinsics extract L_macNs L_shr mult r shr L abs L msu L shr r negate shr_r L_add L_msuNs L_sub norm_s sub The header file dspfns h also exposes certain status flags as global variables for use in your C or C programs The status flags exposed by dspfns h are listed in Table 4 14 Table 4 14 ETSI status flags exposed in RVCT Status flag Description Overflow Overflow status flag Generally saturating functions have a sticky effect on overflow Carry Carry status flag Example include lt limits h gt include lt stdint h gt include lt dspfns h gt include ETSI basic operations int32_t C L add int32 t a int32_t b int32_t c a b if a b amp INT MIN 0 if c A a amp INT MIN C a 0 INT MIN INT MAX return C __asm int32 t asm L add int32 t a int32 t b qadd r0 r r1 bx Ir 4 98 Copyright 2007 2010 ARM Limited All rights
213. dix B Standard C Implementation Definition This appendix gives information required by the ISO C standard for conforming C implementations It contains the following section Implementation definition on page B 2 Behaviors considered undefined by the ISO C Standard on page B 9 ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved Non Confidential B 1 Standard C Implementation Definition B 1 B 2 Implementation definition Appendix G of the ISO C standard ISO IEC 9899 1990 E collates information about portability issues Sub clause G3 lists the behavior that each implementation must document Note This appendix does not duplicate information that is part of Chapter 4 Compiler specific Features This appendix provides references where applicable The following subsections correspond to the relevant sections of sub clause G3 They describe aspects of the ARM C compiler and C library not defined by the ISO C standard that are implementation defined Note The support for the wctype h and wchar h headers excludes wide file operations Copyright O 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential B 1 1 Translation Standard C Implementation Definition Diagnostic messages produced by the compiler are of the form source file line number severity error code explanation where severity is one of blank If the severity is blank this is a remark and i
214. e 3 macros explicitly undefined using Uname Example Specifying the option DMAX X Y X gt Y X Y on the command line is equivalent to defining the macro define MAX X Y X gt Y X Y at the head of each source file See also C on page 2 13 E on page 2 33 Uname on page 2 87 Compiler predefines on page 4 103 no_ data_reorder This option enables or disables automatic reordering of top level data items for example global variables The compiler can save memory by eliminating wasted space between data items However data_reorder can break legacy code if the code makes invalid assumptions about ordering of data by the compiler The ISO C Standard does not guarantee data order so you must avoid writing code that depends on any assumed ordering If you require data ordering place the data items into a structure Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options Default The default is data_reorder 2 1 23 no_ debug This option enables or disables the generation of debug tables for the current compilation The compiler produces the same code regardless of whether debug is used The only difference is the existence of debug tables Default The default is no debug Using debug does not affect optimization settings By default using the debug option alone is equivalent to deb
215. e is compiled to run on any processor supporting that architecture For example cpu 5TE produces code that can be used by the ARM926EJ S FPU Some specifications of cpu imply an fpu selection For example when compiling with the arm option cpu ARM1136JF S implies fpu vfpv2 Note Any explicit FPU set with fpu on the command line overrides an implicit FPU If no fpu option is specified and no cpu option is specified fpu softvfp is used If an architecture v7 processor with an FPU is selected the default FPU type is fpu vfpv3 ARM Thumb Specifying a processor or architecture that supports Thumb instructions such as cpu ARM7TDMI does not make the compiler generate Thumb code It only enables features of the processor to be used such as long multiply Use the thumb option to generate Thumb code Note Specifying the target processor or architecture might make the object code generated by the compiler incompatible with other ARM processors For example code compiled for architecture ARMvV6 might not run on an ARM920T processor if the compiled ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved 2 17 Non Confidential Compiler Command line Options 2 1 20 2 18 code includes instructions specific to ARMv6 Therefore you must choose the lowest common denominator processor suited to your purpose If you are compiling code that is intende
216. e 4 44 attribute zero init on page 4 48 This option instructs the compiler to perform the compilation step but not the link step Note This option is different from the uppercase C option Usage The use of the c option is recommended in projects with more than one source file Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 2 1 12 C 2 1 13 c90 2 1 14 c99 ARM DUI 0348A Compiler Command line Options See also asm on page 2 8 list on page 2 55 o filename on page 2 65 S on page 2 80 This option instructs the compiler to retain comments in preprocessor output Choosing this option implicitly selects the option E Note This option is different from the lowercase c option See also E on page 2 33 This option enables the compilation of C90 source code Default This option is implicitly selected for files having a suffix of c ac or tc See also c99 gnu on page 2 44 no strict on page 2 84 Source language modes on page 1 3 File naming conventions on page 2 11 in the Compiler User Guide This option enables the compilation of C99 source code See also c90 gnu on page 2 44 Copyright 2007 2010 ARM Limited All rights reserved 2 13 Non Confidential Compiler Command line Options no_ strict on page 2 84 Source language modes on page 1 3 2 1 45 no_ code
217. e directory set using workdir refers to an existing working directory containing modified project template files specifying this option causes the working directory to be deleted and recreated with new copies of the original project template files Restrictions This option must be used in combination with the workdir option See also no_ project filename on page 2 74 workdir directory on page 2 95 Copyright O 2007 2010 ARM Limited All rights reserved 2 77 Non Confidential Compiler Command line Options 2 1 102 remarks This option instructs the compiler to issue remark messages such as warning of padding in structures Note The compiler does not issue remarks by default See also no_ brief_diagnostics on page 2 10 diag_error tag tag on page 2 26 diag remark tag tag on page 2 27 e diag_style armlidelgnu on page 2 27 diag suppress tag tag on page 2 28 diag warning tag tag on page 2 30 errors filename on page 2 34 W on page 2 94 no_ wrap_diagnostics on page 2 96 2 1 103 remove_unneeded_entities no_remove_unneeded_entities These options control whether debug information is generated for all source symbols or only for those symbols actually used Usage Use remove_unneeded_entities to reduce debug object and image file sizes Faster linkage times can also be achieved Caution Although remove unneeded
218. e extensions on page 3 25 File naming conventions on page 2 11 in the Compiler User Guide Copyright O 2007 2010 ARM Limited All rights reserved 1 7 Non Confidential Introduction 14 The C and C libraries RVCT provides the following runtime C and C libraries The ARM C libraries The ARM C libraries provide standard C functions and helper functions used by the C and C libraries The C libraries also provide target dependent functions that are used to implement the standard C library functions such as printf in a semihosted environment The C libraries are structured so that you can redefine target dependent functions in your own code to remove semihosting dependencies The ARM libraries comply with the C Library ABI for the ARM Architecture CLIBABI the C ABI for the ARM Architecture CPPABI See ABI for the ARM Architecture compliance on page 1 3 in the Libraries Guide for more information Rogue Wave Standard C Library version 2 02 03 The Rogue Wave Standard C Library as supplied by Rogue Wave Software Inc provides standard C functions and objects such as cout It includes data structures and algorithms known as the Standard Template Library STL The C libraries use the C libraries to provide target specific support The Rogue Wave Standard C Library is provided with C exceptions enabled For more information on the Rogue Wave libraries see the Rogue Wave HTML documentation and the Rogue Wa
219. e is needed for example if the array is subscripted If the array is not extern the element type must be completed by the end of the compilation The final semicolon preceding the closing brace of a struct or union specifier can be omitted A warning is issued An initializer expression that is a single value and is used to initialize an entire static array struct or union does not have to be enclosed in braces ISO C requires the braces An extension is supported to enable constructs similar to C anonymous unions including the following not only anonymous unions but also anonymous structs are permitted The members of anonymous structs are promoted to the scope of the containing struct and looked up like ordinary members they can be introduced into the containing struct by a typedef name That is they do not have to be declared directly as is the case with true anonymous unions atag can be declared but only in C mode To enable support for anonymous structures and unions you must use the anon unions pragma An extra comma is permitted at the end of an enum list but a remark is issued enum tags can be incomplete You can define the tag name and resolve it later by specifying the brace enclosed list The values of enumeration constants can be given by expressions that evaluate to unsigned quantities that fit in the unsigned int range but not in the int range For example When ints are 32 bits
220. e option strict is specified then the default is no dollar Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 2 1 40 dwarf2 2 4 44 dwarf3 2 1 42 E ARM DUI 0348A Compiler Command line Options See also no_ strict on page 2 84 This option instructs the compiler to use DWARF 2 debug table format Default The compiler assumes dwarf3 unless dwarf2 is explicitly specified See also dwarf3 This option instructs the compiler to use DWARF 3 debug table format Default The compiler assumes dwarf3 unless dwarf2 is explicitly specified See also dwarf2 This option instructs the compiler to execute only the preprocessor step By default output from the preprocessor is sent to the standard output stream and can be redirected to a file using standard UNIX and MS DOS notation You can also use the o option to specify a file for the preprocessed output By default comments are stripped from the output The preprocessor accepts source files with any extension for example 0 s and txt Example armcc E source c raw c See also C on page 2 13 Copyright 2007 2010 ARM Limited All rights reserved 2 33 Non Confidential Compiler Command line Options 2 1 43 2 1 44 2 34 o filename on page 2 65 enum_is_int This option forces the size of all enumeration types to be at least four bytes This option is switche
221. e specified on the command line to meet the requirements of standard make systems Note Compiling with multifile has no effect if only a single source file is specified on the command line Default The default is no_multifile unless the option 03 is specified If the option 03 is specified then the default is multifile Usage When multifile is selected the compiler might be able to perform additional optimizations by compiling across several source files Copyright O 2007 2010 ARM Limited All rights reserved 2 63 Non Confidential Compiler Command line Options 2 1 85 2 64 There is no limit to the number of source files that can be specified on the command line but ten files is a practical limit because multifile requires large amounts of memory while compiling For the best optimization results choose small groups of functionally related source files Example armcc c multifile testl c testn c o test o The resulting object file is named test o instead of test1 c and empty object files test2 0 to testn o are created for each source file test1 c testn c specified on the command line See also c on page 2 12 default_extension ext on page 2 22 e o filename on page 2 65 Onum on page 2 66 no_ nonstd_qualifier_deduction This option controls whether or not nonstandard template argument deduction is to be performed in the qualifier portion of a qualified name
222. e value returned by return address from within a function foo is the return address of foo ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved 4 83 Non Confidential Compiler specific Features Inline optimization If a function foo is inlined into a function bar then the value returned by return address from within foo is the return address of bar Tail call optimization If a function foo is tail called from a function bar then the value returned by return address from within foo is the return address of bar See also _ builtin return address on page 4 67 current pc on page 4 70 current sp on page 4 70 Legacy inline assembler that accesses sp lr or pc on page 6 27 in the Compiler User Guide 4 7 32 ror This intrinsic inserts a ROR instruction or operand rotation into the instruction stream generated by the compiler It enables you to rotate a value right by a specified number of places from within your C or C code Note The compiler introduces ROR automatically when it recognizes certain expressions Syntax unsigned int __ror unsigned int val unsigned int shift Where val is the value to be shifted right shift is a constant shift in the range 1 31 Return value The __ror intrinsic returns the value of val rotated right by shift number of places See also ASR LSL LSR ROR and RRX on page 4 66 in the Assembler Guide 4 84 Copyright 2007 2010 A
223. eature support for language Major feature ISO IEC sta dard Support section Core language 1 to 13 Yes Templates 14 Yes with the exception of export templates Exceptions 15 Yes Libraries 17 to 27 See the Standard C library implementation definition on page C 5 and the Libraries and Floating Point Support Guide C 4 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Standard C Implementation Definition C 4 Standard C library implementation definition ARM DUI 0348A Version 2 02 03 of the Rogue Wave library provides a subset of the library defined in the standard There are small differences from the 1999 ISO C standard For information on the implementation definition see Standard C library implementation definition on page 2 115 in the Libraries and Floating Point Support Guide The library can be used with user defined functions to produce target dependent applications See About the runtime libraries on page 1 2 in the Libraries and Floating Point Support Guide Copyright 2007 2010 ARM Limited All rights reserved C 5 Non Confidential Standard C Implementation Definition C 6 Copyright O 2007 2010 ARM Limited All rights reserved Non Confidential ARM DUI 0348A Appendix D C and C Compiler Implementation Limits This appendix lists the implementation limits when using the ARM compiler to compile C and C It contains the following sections e C ISO IEC standa
224. ecified for function parameters other than those of a top level function declaration For example they are accepted on typedef declarations and on pointer to function and pointer to member function declarations Copyright O 2007 2010 ARM Limited All rights reserved 3 19 Non Confidential Language Extensions 3 6 5 Anonymous classes structures and unions 3 20 Anonymous classes structures and unions are supported as an extension Anonymous structures and unions are supported in C and C Anonymous unions are available by default in C However you must specify the anon unions pragma if you want to use anonymous unions and structures in C anonymous classes and structures in C An anonymous union can be introduced into a containing class by a typedef name Unlike a true anonymous union it does not have to be declared directly For example typedef union int i j U U identifies a reusable anonymous union pragma anon_unions class A U Okay references to A i and A j are allowed F The extension also enables anonymous classes and anonymous structures as long as they have no C features For example no static data members or member functions no non public members and no nested types except anonymous classes structures or unions are allowed in anonymous classes and anonymous structures For example pragma anon_unions struct A struct int i j Okay refer
225. eclare a name by which SMC 5 can be called mycall invoke the function See also SMC on page 4 137 in the Assembler Guide The __softfp keyword asserts that a function uses software floating point linkage __softfp is a function qualifier It affects the type of the function Note This keyword has the pragma equivalent pragma softfp linkage Usage Calls to the function pass floating point arguments in integer registers If the result is a floating point value the value is returned in integer registers This duplicates the behavior of compilation targeting software floating point This keyword enables the same library to be used by sources compiled to use hardware and software floating point Copyright O 2007 2010 ARM Limited All rights reserved 4 15 Non Confidential Compiler specific Features Note In C if a virtual function qualified with the __softfp keyword is to be overridden the overriding function must also be declared as __softfp If the functions do not match the compiler generates an error See also fpu name on page 2 42 e pragma no_ softfp_linkage on page 4 59 Floating point linkage on page 4 33 in the Compiler User Guide 4 1 15 _SVC The __svc keyword declares a SuperVisor Call SVC function taking up to four integer like arguments and returning up to four results in a value_in_regs structure __svc is a function qualifier It affects the type of a function
226. ed fpu softvfp and a CPU with implicit VFP hardware the linker chose a library that implemented the software floating point calls using VFP instructions This is no longer the case If you require this legacy behavior use fpu softvfp vfp 2 42 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options softvfp vfpv2 Selects a floating point library with software floating point linkage that uses VFP instructions Select this option if you are interworking Thumb code with ARM code on a system that implements a VFP unit If you select this option Compiling with thumb behaves in a similar way to fpu softvfp except that it links with floating point libraries that use VFP instructions Compiling with arm behaves in a similar way to fpu vfpv2 except that all functions are given software floating point linkage This means that functions pass and return floating point arguments and results in the same way as fpu softvfp but use VFP instructions internally Note If you specify softvfp vfpv2 with the arm or thumb option for C code it ensures that your interworking floating point code is compiled to use software floating point linkage softvfp vfpv3 Selects a floating point library with software floating point linkage that uses VFPv3 instructions Select this option if you are interworking Thumb code with ARM code on a system that implements a VFPv3
227. ed memory systems with ARM Thumb Thumb 2 and Thumb 2EE instruction sets DSP support and 32 bit SIMD support 7 R ARMv7 real time profile with ARM Thumb Thumb 2 DSP support and 32 bit SIMD support 7 M ARMv7 micro controller profile with Thumb 2 only and hardware divide a The ARM compiler cannot generate Java bytecodes b ARM v7 15 not a recognized ARM architecture Rather it is the common subset of architectures ARMv7 A ARMv7 R and ARMv7 M Default If you do not specify a cpu option the compiler assumes cpu ARM7TDMI To get a full list of CPU architectures and processors use the cpu list option Usage The following general points apply to processor and architecture options Processors Copyright 2007 2010 ARM Limited All rights reserved Selecting the processor selects the appropriate architecture Floating Point Unit FPU and memory organization ARM DUI 0348A Non Confidential Compiler Command line Options The supported cpu values include all current ARM product names or architecture versions Other ARM architecture based processors such as the Marvell Feroceon and the Intel XScale are also supported If you specify a processor for the cpu option the compiled code is optimized for that processor This enables the compiler to use specific coprocessors or instruction scheduling for optimum performance Architectures If you specify an architecture name for the cpu option the cod
228. ed only once If the original value of i is nonzero the result is the original value of i Regardless of this i is incremented once As in standard C and ISO C99 the elements of an aggregate initializer for an automatic variable are not required to be constant expressions Mode Supported in GNU mode only for C90 Example float Initializers 0 float f float g i float beat freqs 2 f g f g float aLocal int i20 for i2 i aLocal beat freqs i return aLocal Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Language Extensions 3 7 10 Inline The inline function qualifier specifies that the function is to be inlined static inline foo foo is used internally to the file and the symbol is not exported inline foo foo is used internally to the file and an out of line version is made available and the name foo exported extern inline foo In GNU mode foo is used internally if it is inlined If it is not inlined then an external version is referenced rather than using a call to the internal version Also the foo symbol is not emitted In non GNU mode extern is ignored and the functionality is the same as inline foo for C In C you must use __inline See Extern inline functions on page 5 19 for more information Mode Supported in GNU mode only for C90 3 7 11 Extended lvalues The definition of what constitutes an
229. ee words I C My Project Vincludes two words Apostrophes can be used to delimit words that contain quotes For example DNAME RealView Compilation Tools one word Characters enclosed in parentheses are treated as a single word For example option x y z one word option x y z two words Within quoted or apostrophe delimited strings you can use a backslash V character to escape the quote apostrophe and backslash characters A word that occurs immediately next to a delimited word is treated as a single word For example I C Project includes is treated as the single word IC Project includes Copyright 2007 2010 ARM Limited All rights reserved A 3 Non Confidential Via File Syntax A 4 Lines beginning with a semicolon or a hash character as the first non whitespace character are comment lines If a semicolon or hash character appears anywhere else in a line it is not treated as the start of a comment For example o objectname axf this is not a comment A comment ends at the end of a line or at the end of the file There are no multi line comments and there are no part line comments Lines that include the preprocessor option Dsymbol value must be delimited with a single quote either as Dsymbol value or as Dsymbolz value For example c DFOO_VALUE FOO_VALUE Copyright O 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Appen
230. eedback However a single compile and link using feedback from a previous build is usually sufficient See also split sections on page 2 83 Using linker feedback on page 2 25 in the Compiler User Guide no_ force_new_nothrow This option controls the behavior of new expressions in C The C standard states that only a no throw operator new one that is declared with throw is permitted to return NULL on failure Any other operator new is never permitted to return NULL and the default operator new throws an exception on failure If you use force_new_nothrow the compiler treats expressions such as new T args that use the global operator new 01 operator new as if they are new std nothrow T args force_new_nothrow also causes any class specific operator new or any overloaded global operator new to be treated as no throw Note The option force_new_nothrow is provided only as a migration aid for legacy source code that does not conform to the C standard Its use is not recommended Mode This option is effective only if the source language is C Default The default is no_force_new_nothrow Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options Example struct S voids operator new std size_t voids operator new std size_t void soperator new std size t int With the force new nothr
231. emit unwinding tables to support exception propagation at runtime In C when the no exceptions option is specified throw and try catch are not permitted in source code However function exception specifications are still parsed but most of their meaning is ignored In C the behavior of code compiled with no exceptions is undefined if an exception is thrown through the compiled functions You must use exceptions if you want exceptions to propagate correctly though C functions Default The default is no exceptions See also no_ exceptions_unwind 2 1 46 no_ exceptions_unwind This option enables or disables function unwinding for exception aware code This option is only effective if exceptions is enabled When you use no_exceptions_unwind and exceptions then no exception can propagate through the compiled functions std terminate is called instead Default The default is exceptions_unwind See also no_ exceptions Function unwinding at runtime on page 5 18 2 1 47 no_ export_all_vtb l This option controls how dynamic symbols are exported in C ARM DUI 0348A Copyright 2007 2010 ARM Limited All rights reserved 2 35 Non Confidential Compiler Command line Options Mode This option is effective only if the source language is C Default The default is no export all Usage Use the option export all vtb1 to export all virtual table functions an
232. emory or for systems with slow peripheral devices Interrupt latency in such systems is determined by the number of cycles required for the slowest memory or peripheral access Typically this is much greater than the latency introduced by multiple register transfers See also Instruction expansion on page 6 9 in the Compiler User Guide 2 1 111 split_sections ARM DUI 0348A This option instructs the compiler to generate one ELF section for each function in the source file Output sections are named with the same name as the function that generates the section but with an i prefix Note If you want to place specific data items or structures in separate sections mark them individually with attribute section If you want to remove unused functions it is recommended that you use the linker feedback optimization in preference to this option This is because linker feedback produces smaller code by avoiding the overhead of splitting all sections Restrictions This option reduces the potential for sharing addresses data and string literals between functions Consequently it might increase code size slightly for some functions Example int f int x Compiling this code with split_sections produces return x 1 Copyright 2007 2010 ARM Limited All rights reserved 2 83 Non Confidential Compiler Command line Options AREA i f CODE READONLY ALIGN 2 f PROC ADD r0 r0 1 BX
233. en you specify the Otime option OPTIMIZE When 01 or 02 is specified in GNU mode OPTIMIZE SIZE When Ospace is specified in GNU mode PLACEMENT DELETE In C mode to specify that placement delete that is an operator delete corresponding to a placement operator new to be called if the constructor throws an exception is enabled This is only relevant when using exceptions __PTRDIFF_TYPE__ In GNU mode It defines the correct underlying type for the ptrdiff t typedef _ RTTI In C mode when RTTI is enabled sizeof int 4 For sizeof int but available in preprocessor expressions __sizeof_long 4 For sizeof long but available in preprocessor expressions sizeof ptr 4 For sizeof void but available in preprocessor expressions SIZE TYPE In GNU mode It defines the correct underlying type for the size_t typedef __SOFTFP__ If compiling to use the software floating point calling standard and library Set when you specify the fpu softvfp option for ARM or Thumb or when you specify fpu softvfp vfpv2 for Thumb __STDC__ In all compiler modes STDC VERSION Standard version information STRICT ANSI When you specify the strict option TARGET ARCH ARM num The number of the ARM base architecture of the target CPU irrespective of whether the compiler is compiling for ARM or Thumb TARGET ARCH THUMB num The number of the Thumb base architecture of the target CPU i
234. ence information that is specific to development tools supplied with RVCT Other publications included in the suite are RVCT Essentials Guide ARM DUI 0202 RVCT Compiler User Guide ARM DUI 0205 RVCT Libraries and Floating Point Support Guide ARM DUI 0349 RVCT Linker and Utilities Guide ARM DUI 0206 RVCT Assembler Guide ARM DUI 0204 RVCT Developer Guide ARM DUI 0203 RealView Development Suite Glossary ARM DUI 0324 NEON Vectorizing Compiler Guide ARM DUI 0350 For full information about the base standard software interfaces and standards supported by ARM see install_directory Documentation Specifications In addition see the following documentation for specific information relating to ARM products ARM6 M Architecture Reference Manual ARM DDI 0419 ARM7 M Architecture Reference Manual ARM DDI 0403 ARM Architecture Reference Manual ARMv7 A and ARMV7 R edition ARM DDI 0406 ARM Architecture Reference Manual Advanced SIMD Extension and VFPv3 Supplement ARM DDI 0268 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential ARM DUI 0348A Preface e ARM datasheet or technical reference manual for your hardware device Other publications The following publications provide information about the ETSI basic operations They are all available from the telecommunications bureau of the International Telecommunications Union ITU at http ww
235. ences to A i and A j are allowed See also Unnamed fields on page 3 31 pragma no anon unions on page 4 49 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Language Extensions 3 6 4 Assembler labels Assembler labels specify the assembler name to use for a C symbol For example you might have assembler code and C code that uses the same symbol name such as counter Therefore you can export a different name to be used by the assembler int counter asm counter v1 0 This exports the symbol counter v1 and not the symbol counter See also asm on page 4 5 3 6 5 Empty declaration An empty declaration that is a semicolon with nothing before it is permitted Example do nothing 3 6 6 Hexadecimal floating point constants The ARM compiler implements an extension to the syntax of numeric constants in C to enable explicit specification of floating point constants as IEEE bit patterns Syntax The syntax for specifying floating point constants as IEEE bit patterns is 0f n Interpret an 8 digit hex number n as a float constant There must be exactly eight digits 0d nn Interpret a 16 digit hex number nn as a double constant There must be exactly 16 digits 3 6 7 Incomplete enums ARM DUI 0348A Forward declarations of enums are supported Example enum Incomplete Enums 0 int Incomplete Enums 2 enum Incomplete Enums 0 passon Co
236. ented by IEEE single precision values double and long double values are represented by IEEE double precision values For double and long double quantities the word containing the sign the exponent and the most significant part of the mantissa is stored with the lower machine address in big endian mode and at the higher address in little endian mode See Operations on floating point types on page 5 6 for more information Arrays and pointers The following statements apply to all pointers to objects in C and C except pointers to members Adjacent bytes have addresses that differ by one The macro NULL expands to the value 0 Casting between integers and pointers results in no change of representation The compiler warns of casts between pointers to functions and pointers to data The type size t is defined as unsigned int The type ptrdiff_t is defined as signed int 5 1 3 Operations on basic data types ARM DUI 0348A The ARM compiler performs the usual arithmetic conversions set out in relevant sections of the ISO C99 and ISO C standards The following subsections describe additional points that relate to arithmetic operations See also Expression evaluation on page B 7 Operations on integral types The following statements apply to operations on the integral types All signed integer arithmetic uses a two s complement representation Copyright O 2007 2010 ARM Limited All rights reserved 5 5 Non
237. ept that the compiler sets the diagnostic messages having the specified tags to Remark severity rather than Error severity Note Remarks are not displayed by default To see remark messages use the compiler option remarks Note This option has the pragma equivalent pragma diag_remark Syntax diag_remark tag tag Where tag tag is a comma separated list of diagnostic message numbers specifying the messages whose severities are to be changed See also diag_error tag tag on page 2 26 diag suppress tag tag on page 2 28 diag warning tag tag on page 2 30 remarks on page 2 78 pragma diag remark tag tag on page 4 53 Changing the severity of diagnostic messages on page 5 5 in the Compiler User Guide 2 1 32 diag_style arm ide gnu This option specifies the style used to display diagnostic messages ARM DUI 0348A Copyright 2007 2010 ARM Limited All rights reserved 2 27 Non Confidential Compiler Command line Options 2 1 33 2 28 Syntax diag style string Where string is one of arm Display messages using the ARM compiler style ide Include the line number and character count for any line that is in error These values are displayed in parentheses gnu Display messages in the format used by gcc Default If you do not specify a diag style option the compiler assumes diag_style arm Usage Choosing the option
238. es that is in non user modes In User mode this intrinsic does not change the interrupt flags in the CPSR 4 72 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 4 7 15 enable fiq 4 7 16 enable irq 4 7 47 fabs ARM DUI 0348A Compiler specific Features See also enable irq This intrinsic enables FIQ interrupts Syntax void enable fiq void Restrictions The enable fig intrinsic can only be executed in privileged modes that is in non user modes In User mode this intrinsic does not change the interrupt flags in the CPSR See also disable fig on page 4 71 This intrinsic enables IRQ interrupts Syntax void enable irq void Restrictions The enable irqintrinsic can only be executed in privileged modes that is in non user modes In User mode this intrinsic does not change the interrupt flags in the CPSR See also disable irq on page 4 72 This intrinsic inserts a VABS instruction or an equivalent code sequence into the instruction stream generated by the compiler It enables you to obtain the absolute value of a double precision floating point value from within your C or C code Copyright O 2007 2010 ARM Limited All rights reserved 4 73 Non Confidential Compiler specific Features Note The __fabs intrinsic is an analogue of the standard C library function fabs It differs from the standard library function in that a call
239. es for the storage to be allocated automatically when a thread is created Copyright 2007 2010 ARM Limited All rights reserved 4 27 Non Confidential Compiler specific Features Note The keyword thread is supported as a synonym for declspec thread Restrictions File scope thread local variables cannot be dynamically initialized Example __declspec thread int i __thread int j same as __decspec thread int j 4 28 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler specific Features 4 3 Function attributes The attribute keyword enables you to specify special attributes of variables or structure fields functions and types The keyword format is either attribute attributel attribute2 attribute __attributel__ __attribute2__ For example void Function Attributes malloc O0 int b attribute malloc static int b attribute __unused__ Table 4 3 summarizes the available function attributes Table 4 3 Function attributes supported by the compiler and their equivalents Function attribute non attribute equivalent __attribute__ alias z attribute always inline __forceinline __attribute__ const __pure __attribute__ deprecated __attribute__ malloc attribute noinline __declspec noinline __attribute__ noreturn __declspec noret
240. eserved ARM DUI 0348A Non Confidential Language Extensions Example int bar int b int foo if int y foo int z if y gt 0 z y else z y z b 0 return b 3 7 14 Unnamed fields When embedding a structure or union within another structure or union you do not have to name the internal structure You can access the contents of the unnamed structure without using name to reference it Unnamed fields are the same as anonymous unions and structures Mode Supported in GNU mode for C90 and C99 only Example struct int a union int b float c int d Unnamed Fields 0 int Unnamed Fields 1 return Unnamed_Fields_0 b ARM DUI 0348A Copyright 2007 2010 ARM Limited All rights reserved 3 31 Non Confidential Language Extensions See also Anonymous classes structures and unions on page 3 20 3 32 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Chapter 4 Compiler specific Features This chapter describes the ARM compiler specific features and includes Keywords and operators on page 4 2 __declspec attributes on page 4 24 Function attributes on page 4 29 Type attributes on page 4 37 Variable attributes on page 4 40 Pragmas on page 4 49 Instruction intrinsics on page 4 63 Compiler predefines on page 4 103 ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved 4 1 Non Conf
241. excepting wide I O together with the ARM extensions Use the compiler option c90 to compile C90 code This is the default Strict C90 Means C as defined by the 1990 C standard and addenda excepting wide I O See also c90 on page 2 13 Language extensions and language compliance on page 1 5 Appendix B Standard C Implementation Definition The ARM compiler compiles C as defined by the 1999 C standard and addenda excepting complex numbers and wide I O ISO IEC 9899 1999 The 1999 International Standard for C The ARM compiler also supports several extensions to ISO C99 See Language extensions and language compliance on page 1 5 for more information Copyright O 2007 2010 ARM Limited All rights reserved 1 3 Non Confidential Introduction 1 2 3 ISO C Throughout this document the term C99 Means ISO C99 excepting complex numbers and wide I O together with the ARM and GNU extensions Use the compiler option c99 to compile C99 code Strict C99 Means C as defined by the 1999 C standard and addenda excepting complex numbers and wide I O Standard C Means strict C99 C Means any of C90 strict C90 C99 and Standard C See also c99 on page 2 13 Language extensions and language compliance on page 1 5 Appendix B Standard C Implementation Definition The ARM compiler compiles C as defined by the 2003 standard excepting wide streams and export templates ISO IEC 14822 2003 The
242. export their symbols weakly Functions declared with attribute weak and then defined without attribute weak behave as weak functions This is not the same behavior as the weak keyword Note This function attribute is a GNU compiler extension that is supported by the ARM compiler Example extern int Function Attributes weak 0 int b attribute weak See also _ weak on page 4 20 4 36 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler specific Features 4 4 Type attributes The attribute keyword enables you to specify special attributes of variables or structure fields functions and types The keyword format is either attribute attributel attribute2 attribute __attributel__ __attribute2__ For example void Function Attributes malloc O0 int b attribute malloc static int b attribute __unused__ Table 4 4 summarizes the available type attributes Table 4 4 Type attributes supported by the compiler and their equivalents Type attribute non attribute equivalent __attribute__ aligned __align attribute packed packed attribute transparent union a The packed qualifier does not affect type in GNU mode 4 4 1 attribute aligned The aligned type attribute specifies a minimum alignment for the type Note This type attribute is
243. f you specify multiple source files a single dependency file is created If you specify the o filename option the dependency lines generated on standard output make reference to filename o and not to source o However no object file is produced with the combination of M o filename Use the md option to generate dependency lines and object files for each source file Example You can redirect output to a file by using standard UNIX and MS DOS notation for example armcc M source c Makefile See also C on page 2 13 no_ depend_system_headers on page 2 25 E on page 2 33 md o filename on page 2 65 This option instructs the compiler to compile the source and write make file dependency lines to a file The output file is suitable for use by a make utility The compiler names the file fi7ename d where filename is the name of the source file If you specify multiple source files a dependency file is created for each source file See also depend filename on page 2 23 depend_format string on page 2 24 no_ depend_system_headers on page 2 25 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options M on page 2 60 o filename on page 2 65 2 1 81 message locale 7ang country codepage ARM DUI 0348A This option switches the default language for the display of error and warning messages to the one
244. fersize 2 int32 t ptr int32x4x2 t val vst2q lane f32 transfersize 2 float32 t ptr float32x4x2 t val vst2q lane p16 transfersize 2 polyl t ptr polyl6x8x2 t val vst2 lane u8 transfersize 2 uint8 t ptr uint8x8x2 t val vst2 lane ul6 transfersize 2 uintl6 t ptr uintl6x4x2 t val vst2 lane u32 transfersize 2 uint32 t ptr uint32x2x2 t val vst2 lane s16 transfersize 2 int16 t ptr intl6x4x2 t val vst2 lane s32 transfersize 2 int32 t ptr int32x2x2 t val vst2 lane f32 transfersize 2 float32 t ptr floati2x2x2 t val vst2 lane p8 transfersize 2 poly8 t ptr poly8x8x2 t val vst2_lane_p16 __transfersize 2 polyl16 t ptr poly16x4x2 vst3q lane ul6 transfersize 3 uintl6 t ptr uintl6x8x3 t val vst3q lane u32 transfersize 3 uint32 t ptr uint32x4x3 t val vst3q lane s16 transfersize 3 intl6 t ptr intl6x8x3 t val vst3q lane s32 transfersize 3 int32 t ptr int32x4x3 t val vst3q lane f32 transfersize 3 float32 t ptr float32x4x3 t val vst3q lane p16 transfersize 3 polyl t ptr poly16x8x3_t val vst3 lane u8 transfersize 3 uint8 t ptr uint8x8x3 t val vst3 lane s8 transfersize 3 int8 t ptr int8x8x3 t val vst3 lane s16 transfersize 3 int16 t ptr intl6x4x3 t val vst3 lane s32 transfersize 3 int32 t ptr int32x2x3 t val Using NEON Support constrange 0 7 int lane NST2 16 d0 0 d2 re constrange 3 int lane NST2 32 100
245. ffect if you include either the option use pch fiTename 01 the option create pch fiTename on the same command line See also create_pch filename on page 2 18 pch_dir dir no_ pch_messages on page 2 72 no_ pch_verbose on page 2 72 use_pch filename on page 2 89 pragma hdrstop on page 4 55 pragma no pch on page 4 57 Precompiled header files on page 2 16 in the Compiler User Guide 2 1 93 pch_dir dir ARM DUI 0348A This option enables you to specify the directory where PCH files are stored The directory is accessed whenever PCH files are created or used You can use this option with automatic or manual PCH mode Syntax pch_dir dir Where dir is the name of the directory where PCH files are stored Errors If the specified directory dir does not exist the compiler generates an error See also create_pch filename on page 2 18 pch on page 2 70 no_ pch_messages on page 2 72 no_ pch_verbose on page 2 72 use_pch filename on page 2 89 pragma hdrstop on page 4 55 pragma no pch on page 4 57 Copyright O 2007 2010 ARM Limited All rights reserved 2 71 Non Confidential Compiler Command line Options 2 1 94 2 1 95 2 72 Precompiled header files on page 2 16 in the Compiler User Guide no pch messages This option enables or disables the display of messages indicating that a PCH file is used in the current compilation Default
246. fields in packed structures on page 5 12 for more information All other types are aligned on word boundaries Structures can contain padding to ensure that fields are correctly aligned and that the structure itself is correctly aligned Figure 5 1 shows an example of a conventional non packed structure Bytes 1 2 and 3 are padded to ensure correct field alignment Bytes 11 and 12 are padded to ensure correct structure alignment The sizeof function returns the size of the structure including padding struct char c int x short s exl 0 1 2 3 C padding 4 5 7 8 X 9 10 11 12 S padding Figure 5 1 Conventional non packed structure example The compiler pads structures in one of the following ways according to how the structure is defined Structures that are defined as static or extern are padded with zeros Structures on the stack or heap such as those defined with malloc or auto are padded with whatever is previously stored in those memory locations You cannot use memcmp to compare padded structures defined in this way see Figure 5 1 Use the remarks option to view the messages that are generated when the compiler inserts padding in a struct Structures with empty initializers are permitted in C struct tx ih in X However if you are compiling C or compiling C with the cpp and c90 options an error is generated Copyright 2007 2010 ARM Limited
247. file BIG ENDIAN If compiling for a big endian target BOOL In C compiler mode to specify that bool is a keyword __cplusplus In C compiler mode ARM DUI 0348A Copyright 2007 2010 ARM Limited All rights reserved 4 103 Non Confidential Compiler specific Features Table 4 18 Predefined macros continued Name Value When defined CC ARM 1 Always set to 1 for the ARM compiler even when you specify the thumb option CHAR UNSIGNED gt In GNU mode It is defined if and only if char is an unsigned type DATE date Always defined __EDG__ Always defined EDG IMPLICIT USING STD gt In C mode when you specify the implicit_using_std option EDG VERSION Always set to an integer value that represents the version number of the Edison Design Group EDG front end For example version 3 8 is represented as 308 The version number of the EDG front end does not necessarily match the RVCT or RVDS version number EXCEPTIONS 1 In C mode when you specify the exceptions option FEATURE SIGNED CHAR When you specify the signed chars option used by CHAR MIN and CHAR MAX FILE name Always defined as a string literal FP FAST When you specify the fpmode fast option 8 FENV EXCEPTIONS When you specify the fpmode ieee full or fpmodezieee fixed options __FP_FENV_ROUNDING When you specif
248. file is included using the system include syntax for example include file h This information is not available for preprocessed source containing line directives Consequently the compiler does not attempt implicit inclusion for source code containing line directives The compiler looks for the definition file suffixes cc and CC You can turn implicit inclusion mode on or off with the command line options implicit include and no implicit include Implicit inclusions are only performed during the normal compilation of a file that is when not using the E command line option Copyright O 2007 2010 ARM Limited All rights reserved 5 15 Non Confidential C and C Implementation Details 5 2 6 5 16 Namespaces See Command line options on page 2 2 for more information When doing name lookup in a template instantiation some names must be found in the context of the template definition Other names can be found in the context of the template instantiation The compiler implements two different instantiation lookup algorithms the algorithm mandated by the standard and referred to as dependent name lookup the algorithm that exists before dependent name lookup is implemented Dependent name lookup is done in strict mode unless explicitly disabled by another command line option or when dependent name processing is enabled by either a configuration flag or a command line option Dependent name lookup proce
249. ge 3 15 C99 language features available in C and C90 on page 3 7 Standard C and standard C language extensions on page 3 19 Copyright 2007 2010 ARM Limited All rights reserved C 1 Non Confidential Standard C Implementation Definition C 1 Integral conversion During integral conversion if the destination type is signed the value is unchanged if it can be represented in the destination type and bitfield width Otherwise the value is truncated to fit the size of the destination type Note This section is related to Section 4 7 of the ISO IEC standard C 2 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Standard C Implementation Definition C 2 Calling a pure virtual function Calling a pure virtual function is illegal If your code calls a pure virtual function then the compiler includes a call to the library function cxa pure virtual cxa pure virtual raises the signal SIGPVEN The default signal handler prints an error message and exits See default signal handler on page 2 79 in the Libraries and Floating Point Support Guide for more information ARM DUI 0348A Copyright 2007 2010 ARM Limited All rights reserved C 3 Non Confidential Standard C Implementation Definition C 3 Major features of language support Table C 1 shows the major features of the language supported by this release of ARM C Table C 1 Major f
250. h of array t An example structure definition is struct intl6x4x2 t intl6x4 t val 2 Copyright O 2007 2010 ARM Limited All rights reserved Non Confidential These types are treated as ordinary C structures containing a single element named val There are array types defined for array lengths between 2 and 4 with any of the vector types listed above E 3 Using NEON Support E 3 E 3 1 E 4 Intrinsics Addition The intrinsics described in this section map closely to NEON instructions Each section begins with a list of function prototypes with a comment specifying an equivalent assembler instruction The compiler selects an instruction that has the required semantics but there is no guarantee that the compiler produces the listed instruction The intrinsics use a naming scheme that is similar to the NEON unified assembler syntax That is each intrinsic has the form opname flags type An additional q flag is provided to specify that the intrinsic operates on 128 bit vectors For example vmul_s16 multiplies two vectors of signed 16 bit values This compiles to VMUL I16 d2 d d1 vadd1_u8 is a long add of two 64 bit vectors containing unsigned 8 bit values resulting in a 128 bit vector of unsigned 16 bit values This compiles to VADDL U8 q1 dQ di Note The intrinsic function prototypes in this section use the following type annotations __const n the argument n must be a
251. haracter itself For example a warning is generated if you use s because it is the same as s A struct that has no named fields but at least one unnamed field is accepted by default but generates an error in strict 1990 ISO Standard C ARM DUI 0348A Copyright 2007 2010 ARM Limited All rights reserved B 9 Non Confidential Standard C Implementation Definition B 10 Copyright O 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Appendix C Standard C Implementation Definition ARM DUI 0348A The ARM compiler supports the majority of the language features described in the ISO IEC standard for C when compiling C This appendix lists the C language features defined in the standard and states whether or not that language feature is supported by ARM C It contains the following sections Integral conversion on page C 2 Calling a pure virtual function on page C 3 Major features of language support on page C 4 Standard C library implementation definition on page C 5 Note This appendix does not duplicate information that is part of the standard C implementation See Appendix B Standard C Implementation Definition When compiling C in ISO C mode the ARM compiler is identical to the ARM C compiler Where there is an implementation feature specific to either C or C this is noted in the text For extensions to standard C see Standard C language extensions on pa
252. hout generating object code select S instead of asm Usage The action of asm and the full name of the disassembly file produced depends on the combination of options used Table 2 1 Compiling with the asm option Compiler option Action asm Writes a listing to a file of the disassembly of the compiled source The link step is also performed unless the c option is used The disassembly is written to a text file whose name defaults to the name of the input file with the filename extension s asm c As for asm except that the link step is not performed Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options Table 2 1 Compiling with the asm option continued Compiler option Action asm interleave As for asm except that the source code is interleaved with the disassembly The disassembly is written to a text file whose name defaults to the name of the input file with the filename extension txt asm multifile As for asm except that the compiler produces empty object files for the files merged into the main file asm o filename As for asm except that the object file is named filename The disassembly is written to the file filename s The name of the object file must not have the filename extension s If the filename extension of the object file is s the disassembly is written over the top of the o
253. ic by declaring a function with __forceinline For example __forceinline int g See also forceinline on page 2 39 for more information return 1 Copyright 2007 2010 ARM Limited All rights reserved 5 19 Non Confidential C and C Implementation Details 5 20 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Appendix A Via File Syntax This appendix describes the syntax of via files accepted by all the ARM development tools It contains the following sections Overview of via files on page A 2 Syntax on page A 3 ARM DUI 0348A Copyright 2007 2010 ARM Limited All rights reserved A 1 Non Confidential Via File Syntax A 1 Overview of via files Via files are plain text files that contain command line arguments and options to ARM development tools You can use via files with all the ARM command line tools that is you can specify a via file from the command line using the via command line option with armcc armasm armlink fromelf armar See the documentation for the individual tool for more information Note In general you can use a via file to specify any command line option to a tool including via This means that you can call multiple nested via files from within a via file This section includes Via file evaluation A 1 4 Via file evaluation When a tool that supports via files is invoked it 1 Replaces the
254. idential Compiler specific Features 4 1 4 1 1 Keywords and operators __align This section describes the function keywords and operators supported by the ARM compiler armcc Table 4 1 lists keywords that are ARM extensions to the C and C Standards Standard C and Standard C keywords that do not have behavior or restrictions specific to the ARM compiler are not documented in the table Table 4 1 Keyword extensions supported by the ARM compiler Keywords __align __int64 __SVC _ ALIGNOF__ INTADDR __svc_indirect __asm __irq __svc_indirect_r7 __declspec __packed __value_in_regs __forceinline __pure __weak __global_reg __softfp __writeonly __inline __smc The __align keyword instructs the compiler to align a variable on an n byte boundary __align is a storage class modifier It does not affect the type of the function Syntax __align n Where n is the alignment boundary ncan take the values 1 2 4 or 8 The keyword __align comes immediately before the variable name Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 41 2 __alignof__ ARM DUI 0348A Compiler specific Features Usage __align n is useful when the normal alignment of the variable being declared is less than n Eight byte alignment can give a significant performance advantage with VFP instructions __align can be used in conjunction with extern and static Restrictio
255. idential E 1 Using NEON Support E 1 E 2 Introduction RVCT provides intrinsics to generate NEON code for the Cortex A8 processor in both ARM and Thumb state The NEON intrinsics are defined in the header file arm neon h The header file defines both the intrinsics and a set of vector types There is no support for NEON intrinsics for architectures before ARMv7 When building for earlier architectures or for ARMv7 architecture profiles that do not include NEON the compiler treats NEON intrinsics as ordinary function calls This results in an error at link time Copyright O 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential E 2 Vector data types ARM DUI 0348A type size x number of lanes t Using NEON Support The following types are defined to represent vectors NEON vector data types are named according to the following pattern For example int16x4 t is a vector containing four lanes each containing a signed 16 bit integer Table E 1 lists the vector data types Table E 1 Vector data types int8x8 t int8x16 t intl6x4 t intl6x8 t int32x2_t int32x4 t int64xl t int64x2 t uint8x8 t uint8x16_t uint16x4_t uint16x8_t uint32x2_t uint32x4_t uint64x1_t uint64x2_t float32x2 t float32x4 t poly8x8 t poly8x16 t poly16x4_t poly16x8_t Some intrinsics use an array of vector types of the form type size x number of lanes x lengt
256. iles it is unable to interleave the source Therefore if you have preprocessed source files with line directives but the original unpreprocessed files are not present you must remove all the line directives before you compile with interleave 2 50 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 2 1 68 Jdir dir ARM DUI 0348A Compiler Command line Options See also asm on page 2 8 S on page 2 80 This option adds the specified directory or comma separated list of directories to the list of system includes The RVCT31INC environment variable is set to the default system include path unless you use J to override it Angle bracketed include files are searched for first in the list of system includes followed by any include list specified with the option I Note On Windows systems you must enclose RVCT31INC in double quotes if you specify this environment variable on the command line because the default path defined by the variable contains spaces For example armcc J RVCT31INC c main c Syntax Jdir dir Where dir dir is a comma separated list of directories to be added to the list of system includes At least one directory must be specified When specifying multiple directories do not include spaces between commas and directory names in the list See also Idir dir on page 2 46 kandr include on page 2 52
257. ime This can give significant performance benefits at a small code size cost but at the risk of a longer build time More aggressive inlining and automatic inlining for 03 Otime Multifile compilation by default Note Do not rely on the implementation details of these optimizations because they might change in future releases If you do not specify Onum the compiler assumes 02 Copyright O 2007 2010 ARM Limited All rights reserved 2 67 Non Confidential Compiler Command line Options 2 1 88 2 1 89 2 68 See also no_ autoinline on page 2 9 no_ debug on page 2 21 forceinline on page 2 39 fpmode model on page 2 39 no_ inline on page 2 49 no_ multifile on page 2 63 e Ospace Otime on page 2 69 Optimizing code on page 4 2 in the Compiler User Guide no_ old_specializations Ospace This option controls the acceptance of old style template specializations in C Old style template specializations do not use the template lt gt syntax Note The option old_specializations is provided only as a migration aid for legacy source code that does not conform to the C standard Its use is not recommended Mode This option is effective only if the source language is C Default The default is no_old_specializations This option instructs the compiler to perform optimizations to reduce image size at the expense of a possible in
258. in C With this feature enabled a template argument for the template parameter T can be deduced in contexts like A lt T gt B or T B The standard deduction mechanism treats these as non deduced contexts that use the values of template parameters that were either explicitly specified or deduced elsewhere Note The option nonstd qualifier deduction is provided only as a migration aid for legacy source code that does not conform to the C standard Its use is not recommended Mode This option is effective only if the source language is C Default The default is no nonstd qualifier deduction Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 2 1 86 o filename ARM DUI 0348A Compiler Command line Options This option specifies the name of the output file The full name of the output file produced depends on the combination of options used as described in Table 2 4 and Table 2 5 Syntax If you specify a o option the compiler names the output file according to the conventions of Table 2 4 Table 2 4 Compiling with the o option Compiler option Action Usage notes 0 writes output to the standard output stream filename 15 S is assumed unless E is specified o filename produces an executable image with name filename c 0 filename produces an object file with name filename S o filename produces an assembly lang
259. iner with a sufficient number of unallocated bits and allocates y in the same container as x A bitfield is wholly contained within its container A bitfield that does not fit in a container is placed in the next container of the same type For example the declaration of z overflows the container if an additional bitfield is declared for the structure Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential ARM DUI 0348A C and C Implementation Details struct X int x 10 int y 20 int z 5 The compiler pads the remaining two bits for the first container and assigns a new integer container for z Bitfield containers can overlap each other for example struct X int x 10 char y 2 The first declaration creates an integer container and allocates 10 bits to x These 10 bits occupy the first byte and two bits of the second byte of the integer container At the second declaration the compiler checks for a container of type char There is no suitable container so the compiler allocates a new correctly aligned char container Because the natural alignment of char is 1 the compiler searches for the first byte that contains a sufficient number of unallocated bits to completely contain the bitfield In the example structure the second byte of the int container has two bits allocated to x and six bits unallocated The compiler allocates a char container starting at the second byte of
260. inserts a CDP or CDP2 instruction into the instruction stream generated by the compiler It enables you to include coprocessor data operations in your C or C code Syntax __cdp unsigned int coproc unsigned int opcodel unsigned int opcode2 4 68 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 4 7 9 __clrex 4 7 10 __clz ARM DUI 0348A Compiler specific Features Where coproc Identifies the coprocessor the instruction is for coproc must be an integer in the range 0 to 15 opcodel Is a coprocessor specific opcode Add 0x100 to the opcode to generate a CDP2 instruction opcode2 Is a coprocessor specific opcode Usage The use of these instructions depends on the coprocessor See your coprocessor documentation for more information See also CDP and CDP2 on page 4 121 in the Assembler Guide This intrinsic inserts a CLREX instruction into the instruction stream generated by the compiler It enables you to include a CLREX instruction in your C or C code Syntax void __clrex void Errors The compiler does not recognize the __clrex intrinsic when compiling for a target that does not support the CLREX instruction The compiler generates either a warning or an error in this case See also CLREX on page 4 38 in the Assembler Guide This intrinsic inserts a CLZ instruction or an equivalent code sequence into the instruction stream generated by the compiler It enables you to c
261. int Variable Attributes deprecated 1 attribute deprecated void Variable Attributes deprecated 2 Variable_Attributes_deprecated_Q 1 Variable Attributes deprecated 1 2 Compiling this example generates two warning messages ARM DUI 0348A Copyright 2007 2010 ARM Limited All rights reserved 4 43 Non Confidential Compiler specific Features 4 5 5 __attribute__ packed The packed variable attribute specifies that a variable or structure field has the smallest possible alignment That is one byte for a variable and one bit for a field unless you specify a larger value with the aligned attribute Note This variable attribute is a GNU compiler extension that is supported by the ARM compiler Example struct i char a int b __attribute__ packed j Variable Attributes packed 0 See also Packed structures on page 5 10 The __packed qualifier and unaligned accesses to data on page 4 24 in the Compiler User Guide _ packed structures versus individually __packed fields on page 4 26 in the Compiler User Guide 4 5 6 attribute section Normally the ARM compiler places the objects it generates in sections like data and bss However you might require additional data sections or you might want a variable to appear in a special section for example to map to special hardware The section attribute specifies that a variable must be placed in a particular data section If you
262. int64x2 t vqdmull n s32 int32x2 t vecl int32 t val2 NQDMULL S32 q0 d0 d0 0 Vector saturating doubling long multiply by scalar int32x4 t vqdmull lane sl6 intl6x4 t vecl intl6x4 t val2 constrange 0 3 int val3 VQDMULL S16 q0 d0 d0 0 int64x2 t vqdmull lane s32 int32x2 t vecl int32x2 t val2 constrange 0 1 int val3 VQDMULL S32 q0 d0 d0 0 Vector saturating doubling multiply high with scalar intl6x4 t vqdmulh n s16 intl6x4 t vecl int16 t val2 VQDMULH S16 d0 d0 d0 0 int32x2 t vqdmulh n s32 int32x2 t vecl int32 t val2 VQDMULH S32 d0 d0 d0 0 intl16x8 t vqdmulhq n sl16 int16x8 t vecl intl16 t val2 NQDMULH S16 q0 q0 d0 0 int32x4 t vqdmulhq n s32 int32x4 t vecl int32 t val2 NQDMULH S32 q0 q0 d0 0 Vector saturating doubling multiply high by scalar intl6x4 t vqdmulh lane sl6 intl6x4 t vecl intl6x4 t val2 constrange 0 3 int val3 VQDMULH S16 d0 d0 d0 0 ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved E 49 Non Confidential Using NEON Support int32x2 t intl6x8 t int32x4 t intl6x4 t int32x2 t intl6x8 t int32x4 t intl6x4 t int32x2 t intl6x8 t int32x4 t intl6x4 t int32x2 t uintl6x4 t uint32x2 t float32x2_ int16x8_t int32x4 t uint16x8 t uint32x4 t float32x4 int32x4 t int64x2_t uint32x4_t uint64x2_t E 50 vqdmulh_lane_s32 int32x2_t vecl int32x2_t val2 __constrange 1 int val3 VQDMULH S32 d0 d0 d0 0 vadmulhq_lane
263. is field char a LY 8 byte structure natural alignment 2 int g Y p return p z p x only unaligned read for z See also attribute packed on page 4 44 Packed structures on page 5 10 The __packed qualifier and unaligned accesses to data on page 4 24 in the Compiler User Guide _ packed structures versus individually __packed fields on page 4 26 in the Compiler User Guide The __pure keyword asserts that a function declaration is pure A function is pure only if the result depends exclusively on the values of its arguments the function has no side effects __pure is a function qualifier It affects the type of a function Note This keyword has the function attribute equivalent __attribute__ const Default By default functions are assumed to be impure Usage Pure functions are candidates for common subexpression elimination Copyright O 2007 2010 ARM Limited All rights reserved 4 13 Non Confidential Compiler specific Features Restrictions A function that is declared as pure can have no side effects For example pure functions cannot call impure functions cannot use global variables or dereference pointers because the compiler assumes that the function does not access memory except stack memory must return the same value each time when called twice with the same parameters Example int factr int n pure i int f 1 while n gt 0 f x n
264. ision equivalents if all floating point arguments can be exactly represented as single precision values and the result is immediately converted to a single precision value This transformation is only performed when the selected library contains the single precision equivalent functions for example when the selected library is rvct or aeabi_glibc For example float f float a i is transformed to float f float a Double precision floating point expressions that are narrowed to single precision are evaluated in single precision when it is beneficial to do so For example float y float x 1 0 is evaluated as float y float x 1 0f return sqrt a return sqrtf a Division by a floating point constant is replaced by multiplication with the inverse For example x 3 0 is evaluated as x 1 0 3 0 Itis not guaranteed that the value of errno is compliant with the ISO C or C standard after math functions have been called This enables the compiler to inline the VFP square root instructions in place of calls to sqrt or sqrtf The fpmode option on page 4 34 in the Compiler User Guide ARM Application Note 133 Using VFP with RVDS in install_directory RVDS Examples vfpsupport This option lists the supported FPU architecture names that you can use with the fpu name option Deprecated options are not listed Copyright 2007 2010 ARM Limited All rights reserved 2 41 Non Co
265. itecture supports the hardware divide instruction that is ARMv7 M or ARMv7 R TARGET FEATURE THUMB If the target architecture supports Thumb ARMv4T or later TARGET FPU xx One of the following is set to indicate the FPU usage Q __TARGET_FPU_NONE TARGET FPU VFP TARGET FPU SOFTVFP In addition if compiling fpu softvfp vfpv2 or fpu softvfp vfpv3 __TARGET_FPU_SOFTVFP_VFPV2 or __TARGET_FPU_SOFTVFP_VFPV3 is also set See fpu name on page 2 42 for more information __thumb__ 4 106 When the compiler is in Thumb mode That is you have either specified the thumb option on the command line or pragma thumb in your source code Note The compiler might generate some ARM code even if it is compiling for Thumb __thumb and __thumb__ become defined or undefined when using pragma thumb or pragma arm but do not change in cases where Thumb functions are generated as ARM code for other reasons for example a function specified as __irq Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler specific Features Table 4 18 Predefined macros continued Name Value When defined __TIME__ time Always defined UINTMAX TYPE m In GNU mode It defines the correct underlying type for the uintmax_t typedef VERSION ver When you specify the gnu option It is a string th
266. itu int ETSI Recommendation G 191 Software tools for speech and audio coding standardization ITU T Software Tool Library 2005 User s manual included as part of ETSI Recommendation G 191 ETSI Recommendation G723 1 Dual rate speech coder for multimedia communications transmitting at 5 3 and 6 3 kbit s ETSI Recommendation G 729 Coding of speech at 8 kbit s using conjugate structure algebraic code excited linear prediction CS ACELP Publications providing information about TI compiler intrinsics are available from Texas Instruments at http www ti com Copyright O 2007 2010 ARM Limited All rights reserved ix Non Confidential Preface Feedback ARM Limited welcomes feedback on both RealView Compilation Tools and the documentation Feedback on RealView Compilation Tools If you have any problems with RVCT contact your supplier To help them provide a rapid and useful response give Feedback on this book your name and company the serial number of the product details of the release you are using details of the platform you are running on such as the hardware platform operating system type and version a small standalone sample of code that reproduces the problem a clear explanation of what you expected to happen and what actually happened the commands you used including any command line options sample output illustrating the problem the version string of the tools including the version number
267. l16x8 t vadmulhq_s16 int16x8_t a intl16x8 t b VQDMULH S16 q0 q0 q0 int32x4 t vqdmulhq s32 int32x4 t a int32x4 t b VQDMULH S32 q0 q0 q0 Vector saturating rounding doubling multiply high intl6x4 t vqrdmulh sl16 intl6x4 t a intl6x4 t b VQRDMULH S16 d0 d0 d0 int32x2 t vqrdmulh s32 int32x2 t a int32x2 t b VQRDMULH S32 d0 d0 d0 intl16x8 t vardmulhq_s16 int16x8_t a int16x8 t b VQRDMULH S16 q0 q0 q0 int32x4 t vqrdmulhg s32 int32x4 t a int32x4 t b VQRDMULH S32 q0 q0 q0 Vector saturating doubling multiply accumulate long int32x4 t vqdmlal s16 int32x4 t a intl6x4 t b intl6x4 t c VQDMLAL S16 q0 d0 d0 int64x2 t vqdmlal s32 int64x2 t a int32x2 t b int32x2 t c VQDMLAL S32 q0 d0 d0 Vector saturating doubling multiply subtract long int32x4 t vqdmlsl s16 int32x4 t a intl6x4 t b intl6x4 t c VQDMLSL S16 q0 d0 d0 int64x2 t vqdmls l s32 int64x2 t a int32x2 t b int32x2 t c VQDMLSL S32 q0 d0 d0 Vector long multiply intl6x8 t vmull s8 int8x8 t a int8x8 t b NMULL S8 q0 d0 d0 int32x4_ t vmull si6 intl6x4 t a intl6x4 t b VMULL S16 q0 d0 d0 int64x2 t vmull s32 int32x2 t a int32x2 t b VMULL S32 q0 d0 d0 uintl6x8 t vmull u8 uint8x8 t a uint8x8 t b NMULL U8 q0 d0 d0 uint32x4 t vmull ul6 uintl6x4 t a uintl6x4 t b VMULL U16 q0 d0 d0 uint64x2 t vmull u32 uint32x2 t a uint32x2 t b VMULL U32 q0 d0 d0 polyl6x8 t p8 poly8x8 t a poly8x8 t b NMULL P8 q0 d0 d
268. laration void foo void printf newname d n newname prints 1 See also attribute alias on page 4 29 4 5 2 attribute at address This variable attribute enables you to specify the absolute address of a variable The variable is placed in its own section and the section containing the variable is given an appropriate type by the compiler Read only variables are placed in a section with type RO Initialized read write variables are placed in a section with type RW ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved 4 41 Non Confidential Compiler specific Features In particular variables explicitly initialized to zero are placed in RW not ZI Such variables are not candidates for the ZI to RW optimization of the compiler Uninitialized variables are placed in a section with type ZI Note This variable attribute is not supported by GNU compilers Syntax __attribute__ at address Where address is the desired address of the variable The keyword __at comes immediately after the variable name Restrictions The linker is not always able to place sections produced by the at variable attribute Errors The linker gives an error message if it is not possible to place a section at a specified address Example const int x1 attribute at 0x10000 10 RO int x2 attribute at 0x12000 10 RW int x3 attribute at
269. ler option remarks See also remarks on page 2 78 3 4 6 Benign redeclarations ARM DUI 0348A Benign redeclarations of typedef names are permitted That is a typedef name can be redeclared in the same scope as the same type Example typedef int INT typedef int INT redeclaration Copyright 2007 2010 ARM Limited All rights reserved 3 13 Non Confidential Language Extensions 3 4 7 External entities External entities declared in other scopes are visible Errors The compiler generates a warning if an external entity declared in another scope is visible Example void fl void i extern void f void f2 void i fO s Out of scope declaration 3 4 8 Function prototypes The compiler recognizes function prototypes that override old style non prototype definitions that appear at a later position in your code for example Errors The compiler generates a warning message if you use old style function prototypes Example int function_prototypes char Old style function definition int function_prototypes x char x return x 0 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Language Extensions 3 5 Standard C language extensions 3 5 1 operator The compiler supports numerous extensions to the ISO C standard for example qualified names in the declaration of class members These extensions are availa
270. ling loops optimally by itself Restrictions pragma unro1l completely can only be used immediately before a for loop a while loop or a do while loop Using pragma unroll completely on an outer loop can prevent vectorization On the other hand using pragma unro11 completely on an inner loop might help in some cases Copyright O 2007 2010 ARM Limited All rights reserved 4 61 Non Confidential Compiler specific Features See also 4 6 23 pragma thumb 4 62 diag_warning optimizations on page 2 31 Onum on page 2 66 Otime on page 2 69 no_ vectorize on page 2 91 pragma unroll n on page 4 59 Optimizing loops on page 4 4 in the Compiler User Guide This pragma switches code generation to the Thumb instruction set It overrides the arm compiler option If you are compiling code for a pre Thumb 2 processor and using VFP any function containing floating point operations is compiled for ARM See also arm on page 2 7 thumb on page 2 86 pragma arm on page 4 50 Copyright O 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 4 7 Instruction intrinsics Compiler specific Features This section describes instruction intrinsics for realizing ARM machine language instructions from C or C code Table 4 7 summarizes the available intrinsics Table 4 7 Instruction intrinsics supported by the ARM compiler Instruction intrinsics
271. loating point exceptions are disabled by default Also see fpmode model on page 2 39 Note The IEEE 754 standard for floating point processing states that the default action to an exception is to proceed without a trap You can modify floating point error handling by tailoring the functions and definitions in fenv h See Tailoring error signaling error handling and program exit on page 2 76 for more information 5 6 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential C and C Implementation Details Pointer subtraction The following statements apply to all pointers in C They also apply to pointers in C other than pointers to members When one pointer is subtracted from another the difference is the result of the expression int a int b int sizeof type pointed to e If the pointers point to objects whose alignment is the same as their size this alignment ensures that division is exact If the pointers point to objects whose alignment is less than their size such as packed types and most structs both pointers must point to elements of the same array 5 1 4 Structures unions enumerations and bitfields ARM DUI 0348A This section describes the implementation of the structured data types union enum and struct It also discusses structure padding and bitfield implementation See Anonymous classes structures and unions on page 3 20 for more information
272. ly16x4_t int8x8_t int16x4_t int32x2_t int64x1_t float32x2_t uint8x8_t vget high s8 int8x16 t a vget high s16 int16x8 t a vget high s32 int32x4 t a vget high s64 int64x2 t a vget high f32 float32x4 t a vget high u8 uint8x16 t a vget high ul6 uintl16x8 t a vget high u32 uint32x4 t a vget high u64 uint64x2 t a vget high p8 poly8x16 t a vget high p16 poly16x8 t a vget low s8 int8x16 t a vget low s16 int16x8 t a vget low s32 int32x4 t a vget low s64 int64x2 t a vget low f32 float32x4 t a vget low u8 uint8x16 t a V V V OV 00 00 OV d0 d0 OV d0 d0 OV d0 d0 OV d0 d0 OV d0 d0 OV d0 d0 OV d0 d0 OV d0 d0 OV d0 d0 OV d0 d0 OV d0 d0 OV d0 d0 OV d0 d0 OV d0 d0 OV d0 d0 OV d0 d0 Copyright 2007 2010 ARM Limited All rights reserved Non Confidential NDUP 32 00 00 0 OV d0 d0 MOV 00 00 MOV 00 00 MOV 00 00 OV 00 00 OV 00 00 OV 00 00 OV 00 00 MOV 00 00 MOV 00 00 OV 00 00 ARM DUI 0348A uintl6x4 t vget low ul6 uintl6x8 t a VMOV d0 dO uint32x2 t vget low u32 uint32x4 t a VMOV d0 dO uint64x1_t vget low u64 uint64x2 t a VMOV d0 dO poly8x8 t vget low p8 poly8x16 t a NMOV 00 00 polyl x4 t vget low pl6 poly16x8 t a NMOV d0 d0 E 3 22 Converting vectors int32x2 t uint32x2
273. me Platform Baseboard for ARM926EJ S gt tool name armcc gt cmdline cpu ARM926EJ S fpu vfpv2 cmdline tool lt suiteconf gt When the RVDS_PROJECT environment variable is set to point to this file the command armcc c foo c results in an actual command line of armcc cpu ARM926EJ S fpu VFPv2 c foo c See also reinitialize workdir on page 2 77 workdir directory on page 2 95 2 1 99 preinclude fi lename This option instructs the compiler to include the source code of the specified file at the beginning of the compilation ARM DUI 0348A Copyright 2007 2010 ARM Limited All rights reserved 2 75 Non Confidential Compiler Command line Options Syntax preinclude f1 lename Where filename is the name of the file whose source code is to be included Usage This option can be used to establish standard macro definitions The filename is searched for in the directories on the include search list See also Idir dir on page 2 46 Jdir dir on page 2 51 kandr_include on page 2 52 e sys_include on page 2 86 Include files on page 2 13 in the Compiler User Guide 2 1 100 no_ reduce_paths 2 76 This option enables or disables the elimination of redundant path name information in file paths When elimination of redundant path name information is enabled the compiler removes sequences of the form xyz from directory paths passed to the opera
274. mited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options Default If you do not specify a depend format option then the format of output dependency files depends on your choice of operating system Windows On Windows systems the default is to use either Windows style paths or UNIX style paths whichever is given UNIX On UNIX systems the default is depend format unix Example On a Windows system compiling a file main c containing the line include include header files common h using the options depend depend txt depend_format unix_escaped produces a dependency file depend txt containing the entries main axf main c main axf include header files common h See also depend filename on page 2 23 md on page 2 60 2 1 29 no_ depend_system_headers ARM DUI 0348A This option enables or disables the output of system include dependency lines when generating make file dependency information using either the M option or the md option Default The default is depend_system_headers Example hello c include lt stdio h gt int main void printf Hello world n return Q Copyright 2007 2010 ARM Limited All rights reserved 2 25 Non Confidential Compiler Command line Options 2 1 30 2 26 Compiling this code with the option M produces __image axf hello c __image axf include stdio h Compiling thi
275. mory ptr Points to the address of the data to be written to in memory To specify the size of the data to be written cast the parameter to an appropriate integral type Table 4 10 Access widths supported by the __strex intrinsic Instruction Size of data loaded C cast STREXB unsigned byte char STREXH unsigned halfword short int STREX word int Copyright 2007 2010 ARM Limited All rights reserved 4 89 Non Confidential Compiler specific Features Return value The __strex intrinsic returns 0 if the STREX instruction succeeds 1 if the STREX instruction is locked out Errors The compiler does not recognize the __strex intrinsic when compiling for a target that does not support the STREX instruction The compiler generates either a warning or an error in this case The __strex intrinsic does not support access to doubleword data The compiler generates an error if you specify an access width that is not supported Example int foo void int loc Oxff return __strex x20 volatile char loc Compiling this code with the command line option cpu 6k produces foo PROC MOV r0 0xff MOV r2 0x20 STREXB r1 r2 r0 RSBS r0 r1 1 MOVCC r0 0 BX Ir ENDP See also __Idrex on page 4 75 LDREX and STREX on page 4 35 in the Assembler Guide 4 7 40 5 This intrinsic inserts an assembly language instruction of the form STR size T into the instruction stream generated by the compiler
276. n u32 uint32x4 t a uint32x4 t b VRADDHN I32 d0 q0 q0 vraddhn_u64 uint64x2_t a uint64x2_t b VRADDHN I64 d0 q0 q0 I8 d0 d0 d0 116 d0 d0 d0 132 d0 d0 d0 F32 d0 d0 d0 I8 d0 d0 d0 116 d0 d0 d0 132 d0 d0 d0 P8 d0 d0 d0 I8 q0 q0 q0 116 q0 q0 q0 132 q0 q0 q0 F32 q0 q0 q0 I8 q0 q0 q0 116 q0 q0 q0 132 q0 q0 q0 P8 q0 q0 q0 Vector multiply accumulate vmla Vr i Va i Vb i Vc i vmla s8 int8x8 t a int8x8 t b int8x8 t c vmla sl6 intl6x4 t a intl6x4 t b intl6x4 t c vmla s32 int32x2 t a int32x2 t b int32x2 t c float32x2 t vmla f32 float32x2 t a float32x2 t b float32x2 t c vmla u8 uint8x8 t a uint8x8 t b uint8x8_t c Copyright O 2007 2010 ARM Limited All rights reserved Non Confidential NMLA I8 d0 d0 d0 MLA 116 00 00 00 MLA 132 00 00 00 NMLA F32 00 00 00 NMLA I8 00 00 00 E 7 Using NEON uintl6x4 t uint32x2 t int8x16 t intl6x8 t int32x4 t float32x4 t uint8x16 t uint16x8_t uint32x4_t int16x8_t int32x4 t int64x2_t uint16x8_t uint32x4_t uint64x2_t int8x8 t intl6x4 t int32x2 t float32x2 t uint8x8 t uintl6x4 t uint32x2 t int8x16 t intl6x8 t int32x4 t float32x4 t uint8x16 t uint16x8 t uint32x4 t intl6x8 t int32x4 t int64x2_t uint16x8_t uint32x4_t uint64x2_t E 8 Support vmla ul6 uintl6x4 t a uintl6x4 t b uint16x4_t c MMA vmla u32 uint32x2 t a uint32x2 t b uint32x2 t c MLA vmlaq s8 int8x16 t a int8x16 t b int8x1
277. n C Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 4 1 7 inline 4 1 8 __int64 4 1 9 INTADDR ARM DUI 0348A Compiler specific Features Example 4 3 Global register initialization error __global_reg 1 int x 1 error in C OK in C The __inline keyword suggests to the compiler that it compiles a C or C function inline if it is sensible to do so The semantics of inline are exactly the same as those of the C inline keyword inline is a storage class qualifier It does not affect the type of a function Example inline int f int x return xx5 1 int g int x int y return f x f y See also Inlining on page 4 19 in the Compiler User Guide The __int64 keyword is a synonym for the keyword sequence long long __int64 is accepted even when using strict See also no strict on page 2 84 long long on page 3 8 The __INTADDR__ operation treats the enclosed expression as a constant expression and converts it to an integer constant Copyright O 2007 2010 ARM Limited All rights reserved 4 9 Non Confidential Compiler specific Features Note This is used in the offsetof macro Syntax __INTADDR expr Where expr is an integral constant expression Return value __INTADDR__ expr returns an integer constant equivalent to expr See also Restrictions on embedded assembly on page 6 19 in the Compiler User Guide
278. n U 0 A 1in CP15 register 1 is not supported by the compiler or more generally by the RVCT toolset The RVCT libraries include special versions of certain library functions designed to exploit unaligned accesses To prevent these enhanced library functions being used when unaligned access support is disabled you need to specify no unaligned access on both the compiler command line and the assembler command line when compiling a mixture of C and C source files and asssembly language source files Restrictions Code compiled for processors supporting unaligned accesses to data can run correctly only if the choice of alignment support in software matches the choice of alignment support on the processor core See also cpu name on page 2 15 Command syntax on page 3 2 in the Assembler Guide Alignment support on page 4 43 in the Compiler User Guide 2 1 118 use_pch fi Jename This option instructs the compiler to use a PCH file with the specified filename as part of the current compilation ARM DUI 0348A Copyright 2007 2010 ARM Limited All rights reserved 2 89 Non Confidential Compiler Command line Options This option takes precedence if you include pch on the same command line Syntax use pchefilename Where filename is the PCH file to be used as part of the current compilation Restrictions The effect of this option is negated if you include create_pch fi Jename on the same command li
279. n one translation unit 65536 memory Parameters in one function declaration 256 memory Arguments in one function call 256 memory Parameters in one macro definition 256 memory Arguments in one macro invocation 256 memory Characters in one logical source line 65536 memory Characters in a character string literal or wide string literal after 65536 memory concatenation Size of a C or C object including arrays 262144 4294967296 Nesting levels of include file 256 memory Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential C and C Compiler Implementation Limits Table D 1 Implementation limits continued Non Confidential Description Recommended ARM Case labels for a switch statement excluding those for any nested 16384 memory switch statements Data members in a single class structure or union 16384 memory Enumeration constants in a single enumeration 4096 memory Levels of nested class structure or union definitions in a single 256 memory struct declaration list Functions registered by atexit 32 33 Direct and indirect base classes 16384 memory Direct base classes for a single class 1024 memory Members declared in a single class 4096 memory Final overriding virtual functions in a class accessible or not 16384 memory Direct and indirect virtual bases of a class 1024 memory Static members of a class 1024 memory F
280. ndicates common but sometimes unconventional use of C or C Remarks are not displayed by default Use the remarks option to display remark messages See Controlling the output of diagnostic messages on page 5 4 for more information Compilation continues Warning Flags unusual conditions in your code that might indicate a problem Compilation continues Error Indicates a problem that causes the compilation to stop For example violations in the syntactic or semantic rules of the C or C language Internal fault Indicates an internal problem with the compiler Contact your supplier with the information listed in Feedback on page x Here error code Is a number identifying the error type explanation Is a text description of the error See Chapter 5 Diagnostic Messages in the Compiler User Guide for more information B 1 2 Environment ARM DUI 0348A The mapping of a command line from the ARM architecture based environment into arguments to main is implementation specific The generic ARM C library supports the following main Interactive device on page B 4 Redirecting standard input output and error streams on page B 4 main The arguments given to main are the words of the command line not including input output redirections delimited by whitespace except where the whitespace is contained in double quotes Copyright 2007 2010 ARM Limited All rights reserved B 3 Non Confidential Standard
281. ne Errors If the specified file does not exist or is not a valid PCH file then the compiler generates an error See also create_pch filename on page 2 18 pch on page 2 70 pch_dir dir on page 2 71 no_ pch_messages on page 2 72 no_ pch_verbose on page 2 72 Precompiled header files on page 2 16 in the Compiler User Guide 2 1 119 no_ using_std 2 90 This option enables or disables implicit use of the std namespace when standard header files are included in C Note This option is provided only as a migration aid for legacy source code that does not conform to the C standard Its use is not recommended Mode This option is effective only if the source language is C Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options Default The default 15 no using std See also Namespaces on page 5 16 2 1 120 no_ vectorize ARM DUI 0348A This option enables or disables the generation of NEON vector instructions directly from C or C code Default The default is no_vectorize Restrictions The following options must be specified for loops to vectorize cpu name Target processor must have NEON capability Otime Type of optimization to reduce execution time Onum Level of optimization One of the following must be used 02 High optimization This is the default 03 Maximum
282. ned int __sadd8 unsigned int unsigned int unsigned int __sasx unsigned int unsigned int unsigned int __sel unsigned int unsigned int unsigned int __shaddl6 unsigned int unsigned int unsigned int __shadd8 unsigned int unsigned int unsigned int __shasx unsigned int unsigned int unsigned int __shsax unsigned int unsigned int unsigned int __shsubl6 unsigned int unsigned int unsigned int __shsub8 unsigned int unsigned int unsigned int __smlad unsigned int unsigned int unsigned int unsigned long long __smlald unsigned int unsigned int unsigned long long unsigned int __smlsd unsigned int unsigned int unsigned int unsigned long long smlsld unsigned int unsigned int unsigned long long unsigned int __smuad unsigned int unsigned int unsigned int __smusd unsigned int unsigned int unsigned int __ssatl6 unsigned int unsigned int unsigned int __ssax unsigned int unsigned int unsigned int __ssub16 unsigned int unsigned int unsigned int __ssub8 unsigned int unsigned int unsigned int __sxtabl6 unsigned int unsigned int unsigned int __sxtb16 unsigned int unsigned int unsigned int __uadd16 unsigned int unsigned int unsigned int __uadd8 unsigned int unsigned int unsigned int __uasx unsigned int unsigned int unsigned int __uhadd16 unsigned int unsigned int unsigned int __uhadd8 unsigned int unsigned int Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential
283. nfidential Compiler Command line Options See also fpu name 2 1 55 fpu name This option enables you to determine the target FPU architecture If you specify this option it overrides any implicit FPU option that appears on the command line for example where you use the cpu option To obtain a full list of FPU architectures use the fpu list option Syntax fpu name Where name is one of none Selects no floating point option No floating point code is to be used This produces an error if your code contains float types vfpv3 Selects hardware vector floating point unit conforming to architecture VFPv3 vfpv2 Selects hardware vector floating point unit conforming to architecture VFPv2 This is the default if you specify fpu vfp Note If you enter armcc thumb fpu vfpv2 on the command line the compiler compiles as much of the code using the Thumb instruction set as possible but hard floating point sensitive functions are compiled to ARM code In this case the value of the predefine __thumb is not correct If you specify either vfp or vfpv2 with the arm option for ARM C code you must use the __softfp keyword to ensure that your interworking ARM code is compiled to use software floating point linkage softvfp Selects software floating point linkage This is the default if you do not specify a fpu option or if you select a CPU that does not have an FPU In previous releases of RVCT if you specifi
284. ng example Std RVCT v3 1 extern int const c 10 ok ok x extern int const x c 10 error ext x Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential static int y c 10 error ext x static int const z c 10 error ext x extern int const cp int 0x100 ok ok x extern int const xp cp 0x100 error ext x static int yp cp 0x100 error ext x static int const zp cp 0x100 error ext x Language Extensions This indicates the behavior defined by the ISO C Standard Std and the behavior in RVCT ok indicates that the statement is accepted in all C modes ext is an extension to the ISO C Standard The behavior depends on the strict mode used when compiling C Non strict Accepted without a warning strict warnings Accepted but gives a warning strict Conforms to the ISO C Standard but gives an error See also no_ extended_initializers on page 2 36 no_ strict on page 2 84 strict_warnings on page 2 85 3 4 2 Array and pointer extensions ARM DUI 0348A The following array and pointer extensions are supported Assignment and pointer differences are permitted between pointers to types that are interchangeable but not identical for example unsigned char and char This includes pointers to same sized integral types typically int and long A warning is issued for example 513 D a value of type char
285. ns Because align is a storage class modifier it cannot be used on types including typedefs and structure definitions function parameters You can only overalign That is you can make a two byte object four byte aligned but you cannot align a four byte object at 2 bytes Example __align 8 char buffer 128 buffer starts on eight byte boundary See also min_array_alignment opt on page 2 62 in the Compiler Reference Guide The __alignof__ keyword enables you to enquire about the alignment of a type or variable Note This keyword is a GNU compiler extension that is supported by the ARM compiler Syntax alignof type __alignof__ expr Where type is a type expr is an lvalue Copyright 2007 2010 ARM Limited All rights reserved 4 3 Non Confidential Compiler specific Features 4 1 3 4 4 ALIGNOF Return value __alignof__ type returns the alignment requirement for the type type or 1 if there is no alignment requirement __alignof__ expr returns the alignment requirement for the type of the lvalue expr or 1 if there is no alignment requirement Example int Alignment O void i return __alignof__ int See also ALIGNOF The __ALIGNOF__ keyword returns the alignment requirement for a specified type or for the type of a specified object Syntax ALIGNOF type ALIGNOF expr Where type is a type expr is an lvalue Return
286. nsions of System V release 4 are permitted These enable definition and testing of predicate names Such names are in a namespace distinct from all other names including macro names Syntax assert name assert name token sequence Where name is a predicate name token sequence is an optional sequence of tokens If the token sequence is omitted name is not given a value If the token sequence is included name is given the value token sequence Example A predicate name defined using assert can be tested in a if expression for example if name token sequence This has the value 1 if a assert of the name name with the token sequence token sequence has appeared and 0 otherwise A given predicate can be given more than one value at a given time See also unassert on page 3 3 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Language Extensions 3 1 2 Zinclude next 3 1 3 unassert 3 1 4 warning ARM DUI 0348A This preprocessor directive is a variant of the include directive It searches for the named file only in the directories on the search path that follow the directory where the current source file is found that is the one containing the include_next directive Note This preprocessor directive is a GNU compiler extension that is supported by the ARM compiler A predicate name can be deleted using a unassert preprocessing directive Syntax
287. nt32 t value vmov n s8 int8 t value vmov n s16 int16 t value vmov n s32 int32 t value vmov n p8 poly8 t value vmov n pl6 poly16 t value vmov n 32 float32 t value vmovq n u8 uint8 t value vmovq n ul6 uintl6 t value vmovq n u32 uint32 t value vmovq n s8 int8 t value vmovq n s16 intl6 t value vmovq n s32 int32 t value vmovq n p8 poly8 t value vmovq n pl6 poly16 t value vmovq n f32 float32 t value vmov n s64 int64 t value vmov n u64 uint64 t value vmovq n s64 int64 t value vmovq n u64 uint64 t value NDUP 8 q0 r0 NDUP 16 q0 r0 NDUP 32 q0 r0 NDUP 8 q0 r0 NDUP 16 q0 r0 NDUP 32 q0 r0 NDUP 8 q0 r0 NDUP 16 q0 r0 NDUP 32 q0 r0 NMOV d0 r0 r0 NMOV d0 r0 r0 NMOV d0 r0 r0 NMOV d0 r0 r0 NDUP 8 d0 rO NDUP 16 d0 r0 NDUP 32 d0 r0 NDUP 8 d0 r0 NDUP 16 d0 r0 NDUP 32 d0 r0 NDUP 8 d0 rO NDUP 16 d0 r0 NDUP 32 d0 r0 NDUP 8 q0 r0 NDUP 16 q0 r0 NDUP 32 q0 r0 NDUP 8 q0 r0 NDUP 16 q0 r0 NDUP 32 q0 r0 NDUP 8 q0 r0 NDUP 16 q0 r0 NDUP 32 q0 r0 MOV d0 r0 r0 NMOV d0 r0 r0 NMOV d0 r0 r0 NMOV d0 r0 r0 Set all lanes to the value of one lane of a vector vdup lane u8 uint8x8 t vec vdup lane ul6 uintl16x4 t vec vdup lane u32 uint32x2 t vec vdup lane s8 int8x8 t vec vdup lane s16 intl16x4 t vec vdup lane s32 int32x2 t vec vdup lane p8 poly8x8 t vec
288. nt8x8 t b vrsra n sl6 intl6x4 t a intl6x4 t b vrsra n s32 int32x2 t a int32x2 t b vrsra n s64 int64x1l t a int64x1l t b vrsra n u8 uint8x8 t a uint8x8 t b uintl6x4 t vrsra n ul6 uintl6x4 t a uint16x4_t b uint32x2 t vrsra n u32 uint32x2 t a uint32x2 t b uint64x1l t vrsra n u64 uint64x1l t a uint64x1l t b vrsrag n s8 int8x16 t a int8x16 t b vrsrag n sl6 intl6x8 t a intl16x8 t b vrsraq n s32 int32x4 t a int32x4 t b vrsraq n s64 int64x2 t a int64x2 t b uint8x16 t vrsraq n u8 uint8x16 t a uint8x16 t b uintl16x8 t vrsraq n ul6 uintl16x8 t a uintl16x8 t b constrange 1 8 int b NRSHR U8 00 00 8 constrange 1 16 int b constrange 1 32 int b _constrange 1 64 int b constrange 1 8 int b constrange 1 16 int b constrange 1 32 int b constrange 1 64 int b constrange 1 8 int b constrange 1 16 int b ME VRSHR S8 q0 q0 8 AE VRSHR U8 90 q0 8 constrange 1 64 int b yo uds Vector shift right by constant and accumulate constrange 1 16 int c constrange 1 32 int c constrange 1 64 int c uint8x16 t b constrange 1 8 int c Vector rounding shift right by constant and accumulate constrange 1 8 int c constrange 1 16 int c constrange 1 32 int c constrange 1 64 int c constrange 1 8 int c constrange 1 16 int c constrange 1 32 int c constrange 1 64 int c constrange 1 8 int c constrange 1 16 int c constrange 1 32 int c constrange 1
289. ntl6x4 t b vabd u32 uint32x2 t a uint32x2 t b vabd f32 float32x2 t a float32x2 t b vabdq s8 int8x16 t a int8x16 t b vabdq s16 intl6x8 t a vabdq s32 int32x4 t a vabdq u8 uint8x16 t a int16x8 t b int32x4 t b uint8x16 t b vabdq ul6 uintl6x8 t a uintl6x8 t b vabdq u32 uint32x4 t a uint32x4 t b NABD NABD NABD NABD NABD NABD NABD NABD NABD vabdq f32 float32x4 t a float32x4 t b VABD Absolute difference long intl6x8 t int32x4 t int64x2_t uint16x8_t uint32x4_t uint64x2_t vabdl s8 int8x8 t a int8x8 t b vabdl si6 intl6x4 t a intl6x4 t b vabdl s32 int32x2 t a int32x2 t b vabdl u8 uint8x8 t a uint8x8 t b vabdl ul6 uintl6x4 t a uintl6x4 t b VABDL U16 q0 d0 d0 vabdl u32 uint32x2 t a uint32x2 t b VABDL U32 q0 d0 d0 Using NEON Support U16 d0 d0 d0 U32 d0 d0 d0 F32 d0 d0 d0 S8 q0 q0 q0 S16 q0 q0 q0 32 q0 q0 q0 U8 q0 q00 q0 U16 q0 q90 q0 U32 qQ q0 q0 F32 q0 q0 q0 VABDL S8 q0 d0 d0 VABDL S16 q0 d0 d0 VABDL S32 q0 d0 d0 VABDL U8 q0 d0 d0 Absolute difference and accumulate Vr i Va i Vb i Vc i vaba s8 int8x8 t a int8x8 t b int8x8 t c vaba sl16 intl6x4 t a intl6x4 t b intl6x4 t c vaba s32 int32x2 t a int32x2 t b int32x2 t c vaba u8 uint8x8 t a uint8x8 t b uint8x8_t c uintl6x4 t vaba ul6 uintl6x4 t a uintl6x4 t b uintl16x4 t C uint32x2 t vaba u32 uint32x2 t a uint32x2
290. ode Syntax int __usat unsigned int val unsigned int sat Where val Is the value to be saturated sat Is the bit position to saturate to usat must be in the range 0 to 31 Return value The __usat intrinsic returns val saturated to the unsigned range 0 lt x 2sat 1 Errors The compiler does not recognize the __usat intrinsic when compiling for a target that does not support the USAT instruction The compiler generates either a warning or an error in this case Copyright O 2007 2010 ARM Limited All rights reserved 4 93 Non Confidential Compiler specific Features See also __ssat on page 4 88 SSAT and USAT on page 4 96 in the Assembler Guide 4 7 43 __wfe This intrinsic inserts a WFE instruction into the instruction stream generated by the compiler Syntax void __wfe void Errors The compiler does not recognize the __wfe intrinsic when compiling for a target that does not support the WFE instruction The compiler generates either a warning or an error in this case See also wfi nop on page 4 78 __sev on page 4 87 yield on page 4 95 NOP SEV WFE WFT and YIELD on page 4 139 in the Assembler Guide 4 7 44 wfi This intrinsic inserts a WFI instruction into the instruction stream generated by the compiler Syntax void __wfi void Errors The compiler does not recognize the __wfi intrinsic when compiling for a target that does not support the WFI instruction
291. on Limits 3 7 1 Alternate keywords The compiler recognizes alternate keywords of the form __keyword__ These alternate keywords have the same behavior as the original keywords Example __const__ int pi 3 14 same as const int pi 3 14 3 7 2 asm keyword This keyword is a synonym for the __asm keyword Mode Supported in GNU mode for C90 and C99 only See also asm on page 4 5 3 7 3 Case ranges You can specify ranges of values in switch statements ARM DUI 0348A Copyright 2007 2010 ARM Limited All rights reserved 3 25 Non Confidential Language Extensions Example int Case Ranges O int arg i int aLocal int bLocal arg switch bLocal case 0 10 aLocal 1 break case 11 100 aLocal 22 break default aLocal 1 return aLocal 3 7 4 Cast of a union 3 26 A cast to a union type is similar to other casts except that the type specified is a union type You can specify the type either with a union tag or with a typedef name Mode Supported in GNU mode for C90 and C99 only Example typedef union double d int i foo t int Cast to Union O int a double b i foo t u if a gt 100 u 100 t a automatically equivalent to u i a else u foo t b automatically equivalent to u d b return u i Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Language Extensions 3 7 5 Character escape se
292. on details 5 13 Via File Syntax A 1 Overview of via files A 2 A 2 rd A 3 Standard C Implementation Definition B 1 Implementation definition B 2 B 2 Behaviors considered undefined by the ISO C Standard B 9 Standard C Implementation Definition C 1 Integral conversion lt C 2 C 2 Calling a pure virtual function C 3 C 3 Major features of language support C 4 C 4 Standard C library implementation definition C 5 C and C Compiler Implementation Limits D 1 C ISO IEC standard limits D 2 D 2 Limits for integral numbers D 4 D 3 Limits for floating point numbers seem D 5 Using NEON Support E 1 IMEFOCU tii Ass Dh dod o tus ose e mede me deco ituri tiet fume E 2 E 2 Vector data types sa eR E dee es E 3 E 3 5 4 Copyright 2007 2010 ARM Limited All rights reserved A
293. on is allowed 3 18 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Language Extensions 3 6 Standard C and standard C language extensions The compiler supports numerous extensions to both the ISO C99 and the ISO C Standards such as various integral type extensions various floating point extensions hexadecimal floating point constants and anonymous classes structures and unions These extensions are available if the source language is C and you are compiling in non strict mode the source language is C99 and you are compiling in non strict mode the source language is C90 and you are compiling in non strict mode These extensions are not available if the source language is C and the compiler is restricted to compiling strict C using the strict compiler option the source language is C99 and the compiler is restricted to compiling strict Standard C using the strict compiler option the source language is C90 and the compiler is restricted to compiling strict C90 using the strict compiler option 3 6 1 Address of a register variable The address of a variable with register storage class can be taken Errors The compiler generates a warning if you take the address of a variable with register storage class Example void foo void register int i int xj amp i 3 6 2 Arguments to functions ARM DUI 0348A Default arguments can be sp
294. on lvalue array expression is converted to a pointer to the first element of the array when it is subscripted or similarly used 3 4 3 Block scope function declarations Two extensions to block scope function declarations are supported a block scope function declaration also declares the function name at file scope a block scope function declaration can have static storage class thereby causing the resulting declaration to have internal linkage by default Example void f1 void i static void g void static function declared in local scope i use of static keyword is illegal in strict ISO C void f2 void 90 uses previous local declaration static void g int i error conflicts with previous declaration of g 3 12 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Language Extensions 3 4 4 Dollar signs in identifiers Dollar signs are permitted in identifiers Note When compiling with the strict option you can use the dollar command line option to permit dollar signs in identifiers Example define DOLLAR See also no_ dollar on page 2 32 no_ strict on page 2 84 3 4 5 Top level declarations A C input file can contain no top level declarations Errors A remark is issued if a C input file contains no top level declarations Note Remarks are not displayed by default To see remark messages use the compi
295. onstants 3 16 A linkage specification for external constants indicates that a constant can be dynamically initialized or have mutable members Note The use of C read write linkage is only necessary for code compiled with apcs rwpi If you recompile existing code with this option you must change the linkage specification for external constants that are dynamically initialized or have mutable members Compiling C with the apcs rwpi option deviates from the ISO C Standard The declarations in Example 3 1 assume that x is in a read only segment Example 3 1 External access extern const T x extern C const T x extern C const T x Dynamic initialization of x including user defined constructors is not possible for constants and T cannot contain mutable members The new linkage specification in Example 3 2 on page 3 17 declares that x is in a read write segment even if it is initialized with a constant Dynamic initialization of x is permitted and T can contain mutable members The definitions of x y and z in another file must have the same linkage specifications Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Language Extensions Example 3 2 Linkage specification extern const int z in read only segment cannot be dynamically initialized Pd L3 extern C read write const int y in read write segment can be dynamically initialize
296. optimization Note NEON is an implementation of the ARM Advanced Single Instruction Multiple Data SIMD extension A separate FLEXnet license is needed to enable the use of vectorization Example armcc vectorize cpu Cortex A8 03 Otime c file c See also cpu name on page 2 15 Onum on page 2 66 Otime on page 2 69 Copyright 2007 2010 ARM Limited All rights reserved 2 91 Non Confidential Compiler Command line Options 2 1 121 no_ vfe The NEON Vectorizing Compiler Guide This option enables or disables Virtual Function Elimination VFE in C VFE enables unused virtual functions to be removed from code When VFE is enabled the compiler places the information in special sections with the prefix arm_vfe_ These sections are ignored by linkers that are not VFE aware because they are not referenced by the rest of the code Therefore they do not increase the size of the executable However they increase the size of the object files Mode This option is effective only if the source language is C Default The default is vfe except for the case where legacy object files compiled with a pre RVCT v2 1 compiler do not contain VFE information See also Calling a pure virtual function on page C 3 Unused function elimination on page 3 12 in the Linker Guide 2 1 122 via filename 2 92 This option instructs the compiler to read additional command line options from a
297. or wide add vadd gt Vr i Va i Vb i intl16x8 t vaddw s8 int16x8 t a int8x8 t b VADDW S8 q0 q0 d0 int32x4 t vaddw_sl6 int32x4_t a intl6x4 t b VADDW S16 q0 q0 d0 int64x2 t vaddw s32 int64x2 t a int32x2 t b VADDW S32 q0 q0 d0 uintl6x8 t vaddw u8 uintl6x8 t a uint8x8 t b VADDW U8 q0 q0 d0 uint32x4 t vaddw ul6 uint32x4 t a uintl6x4 t b VADDW U16 q0 q0 d0 uint64x2 t vaddw u32 uint64x2 t a uint32x2 t b VADDW U32 q0 q0 d0 ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved E 5 Non Confidential Using NEON Support Vector halving add vhadd gt Vr i Va i Vb i gt gt 1 int8x8 t vhadd_s8 int8x8_t a int8x8 t b MHADD S8 d0 d0 d0 intl6x4 t vhadd_s16 int16x4_t a intl6x4 t b MHADD S16 d0 d0 d0 int32x2 t vhadd s32 int32x2 t a int32x2 t b MHADD S32 00 00 0 uint8x8 t vhadd u8 uint8x8 t a uint8x8 t b MHADD U8 d0 d0 d0 uintl6x4 t vhadd ul6 uintl6x4 t a uintl6x4 t b VHADD U16 d0 d0 d0 uint32x2 t vhadd u32 uint32x2 t a uint32x2 t b VHADD U32 d0 d0 d0 int8x16 t vhaddq s8 int8x16 t a int8x16 t b MHADD S8 q0 q0 q0 intl6x8 t vhaddq sl6 intl6x8 t a intl6x8 t b VHADD S16 qQ q0 q0 int32x4 t vhaddq s32 int32x4 t a int32x4 t b X VHADD S32 q0 q0 q0 uint8x16_t vhaddq u8 uint8x16 t a uint8x16 t b VHADD U8 q0 q0 q0 uintl6x8 t vhaddq ul6 uintl6x8 t a uintl6x8 t b VHADD U16 q0 q0 q0 uint32x4 t vhaddq u32 uint32x4 t a uint32x4 t b VH
298. ount the number of leading zeros of a data value in your C or C code Copyright 2007 2010 ARM Limited All rights reserved 4 69 Non Confidential Compiler specific Features 4 7 11 current pc 4 7 12 current 50 4 70 Syntax unsigned char __clz unsigned int val Where val is an unsigned int Return value The __c1z intrinsic returns the number of leading zeros in val See also __builtin_clz on page 4 64 CLZ on page 4 53 in the Assembler Guide This intrinsic enables you to determine the current value of the program counter at the point in your program where the intrinsic is used Syntax unsigned int __current_pc void Return value The current pc intrinsic returns the current value of the program counter at the point in the program where the intrinsic is used See also current sp return address on page 4 83 Legacy inline assembler that accesses sp lr or pc on page 6 27 in the Compiler User Guide This intrinsic returns the value of the stack pointer at the current point in your program Syntax unsigned int __current_sp void Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler specific Features Return value The current sp intrinsic returns the current value of the stack pointer at the point in the program where the intrinsic is used See also builtin frame address on page 4 66 d current pc on page 4 70
299. ow option in effect this is treated as struct S voids operator new std size_t throw voids operator new std size_t throw void soperator new std size t int throw See also Using the operator new function on page 5 13 2 1 52 forceinline This option forces functions marked __inline to be inlined If used the compiler always attempts to inline those functions marked as inline if possible The compiler attempts to inline the function regardless of its characteristics However it does not inline a function if doing so causes problems For example a recursive function is inlined into itself only once See also no_ autoinline on page 2 9 no inline on page 2 49 __forceinline on page 4 6 inline on page 4 9 Managing inlining on page 4 20 in the Compiler User Guide 2 1 53 fpmode model ARM DUI 0348A This option specifies the floating point conformance and sets library attributes and floating point optimizations Syntax fpmode mode Copyright 2007 2010 ARM Limited All rights reserved 2 39 Non Confidential Compiler Command line Options Where model is one of ieee full All facilities operations and representations guaranteed by the IEEE standard are available in single and double precision Modes of operation can be selected dynamically at runtime This defines the symbols __FP_IEEE __FP_FENV_EXCEPTIONS __FP_FENV_ROUNDING __FP_INEXACT_EXCEP
300. piler Command line Options library_type 17b in Specifying an input file list on page 2 6 in the Linker Guide 2 1 73 list This option instructs the compiler to generate raw listing information for a source file The name of the raw listing file defaults to the name of the input file with the filename extension 1st If you specify multiple source files on the command line then raw listing information is generated for only the first of the specified files Usage Typically raw listing information is used to generate a formatted listing The raw listing file contains raw source lines information on transitions into and out of include files and diagnostics generated by the compiler Each line of the listing file begins with any of the following key characters that identifies the type of line N A normal line of source The rest of the line is the text of the line of source x The expanded form of a normal line of source The rest of the line is the text of the line This line appears following the N line and only if the line contains nontrivial modifications Comments are considered trivial modifications and macro expansions line splices and trigraphs are considered nontrivial modifications Comments are replaced by a single space in the expanded form line S A line of source skipped by an if or similar The rest of the line is text Note The else elseif or endif that ends a skip is marked with an N L Indicates a
301. preinclude filename on page 2 75 sys_include on page 2 86 Include files on page 2 13 in the Compiler User Guide Copyright O 2007 2010 ARM Limited All rights reserved 2 51 Non Confidential Compiler Command line Options 2 1 69 2 1 70 2 52 kandr include Lopt This option ensures that Kernighan and Ritchie search rules are used for locating included files The current place is defined by the original source file and is not stacked If you do not use this option Berkeley style searching is used See also Idir dir on page 2 46 Jdir dir on page 2 51 preinclude filename on page 2 75 sys include on page 2 86 Include files on page 2 13 in the Compiler User Guide The current place on page 2 13 in the Compiler User Guide This option specifies command line options to pass to the linker when a link step is being performed after compilation Options can be passed when creating a partially linked object or an executable image Syntax Lopt Where opt is a command line option to pass to the linker Restrictions If an unsupported Linker option is passed to it using L an error is generated Example armcc main c L map See also Aopt on page 2 2 show_cmdline on page 2 81 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 2 1 71 library interface lib ARM DUI 0348A Compiler Command line Options Thi
302. ption displays a summary of the main command line options This is the default if you do not specify any options or source files See also show_cmdline on page 2 81 vsn on page 2 94 Copyright 2007 2010 ARM Limited All rights reserved 2 45 Non Confidential Compiler Command line Options 2 1 60 2 1 61 2 46 no_ hide_ Idir dir all This option enables you to control symbol visibility when building SVr4 shared objects Usage Use no hide a11 to mark all extern definitions as __declspec dllexport and to import all undefined references Default The default is hide all See also __declspec dllexport on page 4 24 symver_script in Controlling image contents on page 2 16 in the Linker Guide This option adds the specified directory or comma separated list of directories to the list of places that are searched to find included files If you specify more than one directory the directories are searched in the same order as the I options specifying them Syntax Idir dir Where dir dir is a comma separated list of directories to be searched for included files At least one directory must be specified When specifying multiple directories do not include spaces between commas and directory names in the list See also Jdir dir on page 2 51 kandr_include on page 2 52 preinclude filename on page 2 75 e sys_include on page 2 86
303. pyright O 2007 2010 ARM Limited All rights reserved 3 21 Non Confidential Language Extensions return 0 int Incomplete_Enums_1 enum Incomplete Enums 0 passon return Incomplete Enums 2 passon enum Incomplete Enums 0 ALPHA BETA GAMMA 3 6 8 Integral type extensions In an integral constant expression an integral constant can be cast to a pointer type and then back to an integral type 3 6 9 Label definitions In Standard C and Standard C a statement must follow a label definition In C and C a label definition can be followed immediately by a right brace Errors The compiler generates a warning if a label definition is followed immediately by a right brace Example void foo char xp if p label 3 6 10 Long float long float is accepted as a synonym for double 3 6 11 Non static local variables Non static local variables of an enclosing function can be referenced in a non evaluated expression for example a sizeof expression inside a local class A warning is issued 3 22 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Language Extensions 3 6 12 Structure union enum and bitfield extensions The following structure union enum and bitfield extensions are supported ARM DUI 0348A In C the element type of a file scope array can be an incomplete struct or union type The element type must be completed before its siz
304. quences In strings the escape sequence e is accepted for the escape character lt ESC gt ASCII 27 Example void foo void printf Escape sequence is e n 3 7 6 Compound literals As in C99 compound literals are supported All compound literals are lvalues Example int y int 1 2 3 error in strict C99 okay in C99 gnu int z int 3 1 Mode Supported in GNU mode for C90 and C99 only Note Compound literals can also be used as initializers in C99 However the compiler is more relaxed about which compound literals it accepts as initializers in GNU mode than it is when compiling C99 source code 3 7 7 Designated inits ARM DUI 0348A As in C99 designated initializers are supported Example int a 6 1 4 29 2 15 int b 6 0 0 15 E 29 0 3 af is equivalent to b Mode Supported in GNU mode for C90 and C only Copyright O 2007 2010 ARM Limited All rights reserved 3 27 Non Confidential Language Extensions 3 7 8 3 7 9 3 28 Conditionals Initializers See also New features of C99 on page 1 5 in the Compiler User Guide The middle operand in a conditional statement can be omitted if the result is to be the same as the test for example i i j This is most useful if the test modifies the value in some way for example i where i comes from a macro If you write code in this way then i is evaluat
305. rary variants are listed in About the runtime libraries on page 1 2 in the Libraries Guide The precise nature of each C library is unique to the particular implementation The generic ARM C library has or supports the following features The macro NULL expands to the integer constant 0 If a program redefines a reserved external identifier such as printf an error might occur when the program is linked with the standard libraries If it is not linked with standard libraries no error is detected The __aeabi_assert function prints details of the failing diagnostic on stderr and then calls the abort function xxx assertion failed expression file name line number Note The behavior of the assert macro depends on the conditions in operation at the most recent occurrence of include assert h See Exiting from the program on page 2 37 in the Libraries Guide for more information For implementation details of mathematical functions macros locale signals and input output see Chapter 2 The C and C Libraries in the Libraries Guide B 8 Copyright O 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Standard C Implementation Definition B 2 Behaviors considered undefined by the ISO C Standard The following are considered undefined behavior by the ISO C Standard In character and string escapes if the character following the has no special meaning the value of the escape is the c
306. rating double of an integer from within your C or C code Syntax int __qdbl int val Where val is the data value to be doubled Return value The __qdb intrinsic returns the saturating add of val with itself or equivalently __qadd val val See also qadd on page 4 80 This intrinsic inserts a QSUB instruction or an equivalent code sequence into the instruction stream generated by the compiler It enables you to obtain the saturating subtraction of two integers from within your C or C code Copyright 2007 2010 ARM Limited All rights reserved 4 81 Non Confidential Compiler specific Features Syntax int __qsub int vall int val2 Where vall is the minuend of the saturating subtraction operation val2 is the subtrahend of the saturating subtraction operation Return value The __qsub intrinsic returns the saturating subtraction of va11 and va12 See also qadd on page 4 80 QADD QSUB QDADD and QDSUB on page 4 94 in the Assembler Guide 4 7 29 __rbit This intrinsic inserts an RBIT instruction into the instruction stream generated by the compiler It enables you to reverse the bit order in a 32 bit word from within your C or C code Syntax unsigned int __rbit unsigned int val where val is the data value whose bit order is to be reversed Return value The __rbit intrinsic returns the value obtained from val by reversing its bit order See also REV REVI6 REVSH and RBIT on
307. rd limits on page D 2 Limits for integral numbers on page D 4 Limits for floating point numbers on page D 5 ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved D 1 Non Confidential C and C Compiler Implementation Limits D 1 D 2 C ISO IEC standard limits The ISO IEC C standard recommends minimum limits that a conforming compiler must accept You must be aware of these when porting applications between compilers Table D 1 gives a summary of these limits In this table a limit of memory indicates that the ARM compiler imposes no limit other than that imposed by the available memory Table D 1 Implementation limits Description Recommended ARM Nesting levels of compound statements iteration control structures 256 memory and selection control structures Nesting levels of conditional inclusion 256 memory Pointer array and function declarators in any combination 256 memory modifying an arithmetic structure union or incomplete type in a declaration Nesting levels of parenthesized expressions within a full expression 256 memory Number of initial characters in an internal identifier or macro name 1024 memory Number of initial characters in an external identifier 1024 memory External identifiers in one translation unit 65536 memory Identifiers with block scope declared in one block 1024 memory Macro identifiers simultaneously defined i
308. re num is one of the following 0 Minimum optimization Turns off most optimizations It gives the best possible debug view and the lowest level of optimization Copyright 2007 2010 ARM Limited All rights reserved Non Confidential ARM DUI 0348A ARM DUI 0348A Note The performance of floating point code can be influenced by selecting an appropriate numerical model using the fpmode option Compiler Command line Options Restricted optimization Removes unused inline functions and unused static functions Turns off optimizations that seriously degrade the debug view If used with debug this option gives a satisfactory debug view with good code density High optimization If used with debug the debug view might be less satisfactory because the mapping of object code to source code is not always clear This is the default optimization level Maximum optimization 03 performs the same optimizations as 02 however the balance between space and time optimizations in the generated code is more heavily weighted towards space or time compared with 02 That is 03 Otime aims to produce faster code than 02 Otime at the risk of increasing your image size 03 Ospace aims to produce smaller code than 02 Ospace but performance might be degraded In addition 03 performs extra optimizations that are more aggressive such as High level scalar optimizations including loop unrolling for 03 Ot
309. riable declarations and function definitions with __weak Functions and variable declarations A function or variable cannot be used both weakly and non weakly in the same compilation For example the following code uses f weakly from g and h void f void void g fO ARM DUI 0348A Copyright 2007 2010 ARM Limited All rights reserved 4 21 Non Confidential Compiler specific Features 4 22 weak void f void void h It is not possible to use a function or variable weakly from the same compilation that defines the function or variable The following code uses f non weakly from h F0 __weak void f void void h void f The linker does not load the function or variable from a library unless another compilation uses the function or variable non weakly If the reference remains unresolved its value is assumed to be NULL Unresolved references however are not NULL if the reference is from code to a position independent section or to a missing __weak function f0 Function definitions Example Weakly defined functions cannot be inlined weak const int c assume c is not present in final link const int f1 return amp c amp c returns non NULL if compiled and linked ropi weak int i assume i is not present in final link int f2 return amp i amp i returns non NULL if compiled and linked rwpi weak void f void
310. riend declarations in a class 4096 memory Access control declarations in a class 4096 memory Member initializers in a constructor definition 6144 memory Scope qualifications of one identifier 256 memory Nested external specifications 1024 memory Template arguments in a template declaration 1024 memory Recursively nested template instantiations 17 memory Handlers per try block 256 memory Throw specifications on a single function declaration 256 memory ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved D 3 C and C Compiler Implementation Limits D 2 D 4 Limits for integral numbers Table D 2 gives the ranges for integral numbers in ARM C and C The Endpoint column of the table gives the numerical value of the range endpoint The Hex value column gives the bit pattern in hexadecimal that is interpreted as this value by the ARM compiler These constants are defined in the limits h include file When entering a constant choose the size and sign with care Constants are interpreted differently in decimal and hexadecimal octal See the appropriate C or C standard or any of the recommended C and C textbooks for more information as described in Further reading on page viii Table D 2 Integer ranges Constant Meaning Value Hex value CHAR MAX Maximum value of char 255 OxFF CHAR MIN Minimum value of char 0 0x00 SCHAR MAX Maximum value of signed ch
311. rning messages See also diag_suppress optimizations on page 2 29 diag warning tag tag on page 2 30 Onum on page 2 66 Otime on page 2 69 2 1 37 no_ dllexport_all ARM DUI 0348A This option enables you to control symbol visibility when building DLLs Default The default is no dllexport all Copyright 2007 2010 ARM Limited All rights reserved 2 31 Non Confidential Compiler Command line Options 2 1 38 2 1 39 2 32 Usage Use the option d11 export to mark all extern definitions as declspec dllexport See also apcs qualifer qualifier on page 2 4 __declspec dllexport on page 4 24 no dllimport runtime This option enables you to control symbol visibility when using the runtime library as a shared library Default The default 15 no dllimport runtime Usage Use the option d11 import runtime to mark all builtin symbols as declspec dllimport RTTI generated in the cpprt runtime libraries for import any optimized printf and __hardfp_ functions for import provided that the original function is marked as __declspec d1limport See also no_ guiding_decls on page 2 44 no_ rtti on page 2 79 __declspec dllimport on page 4 25 no dollar This option instructs the compiler to accept or reject dollar signs in identifiers Default The default is dollar unless the option strict is specified If th
312. rolled using pragma unroll n That is pragma unroll n applies to both vectorize and no vectorize Syntax pragma unroll pragma unroll n Where n is an optional value indicating the number of iterations to unroll Copyright O 2007 2010 ARM Limited All rights reserved 4 59 Non Confidential Compiler specific Features 4 60 Default If you do not specify a value for n the compiler assumes pragma unroll 4 Usage When compiling at 03 Otime the compiler automatically unrolls loops where it is beneficial to do so You can use this pragma to request that the compiler to unroll a loop that has not been unrolled automatically Note Use this pragma only when you have evidence for example from diag_warning optimizations that the compiler is not unrolling loops optimally by itself Restrictions pragma unroll n can be used only immediately before a for loop a while loop or a do while loop Example void matrix multiply float restrict dest float restrict srcl float restrict src2 unsigned int n i unsigned int i j k for i 0 i lt n i for 0 k lt n k float sum 0 0f pragma unroll for j 0 j n j sum srcl i j src2 j k dest i k sum In this example the compiler does not normally complete its loop analysis because src2 is indexed as src2 j k but the loops are nested in the opposite order
313. ropi This option enables or disables less restrictive C when compiling with apcs ropi Default The default is no lower ropi Note If you compile with lower ropi then the static initialization is done at runtime by the C constructor mechanism for both C and C code This enables these static initializations to work with ROPI code See also apcs qualifer qualifier on page 2 4 no_ lower_rwpi Position independence qualifiers on page 2 23 in the Compiler User Guide 2 1 78 no lower rwpi ARM DUI 0348A This option enables or disables less restrictive C and C when compiling with apcs rwpi Default The default 15 lower_rwpi Note If you compile with lower rwpi then the static initialization is done at runtime by the C constructor mechanism even for C This enables these static initializations to work with RWPI code See also apcs qualifer qualifier on page 2 4 no_ lower_ropi Position independence qualifiers on page 2 23 in the Compiler User Guide Copyright 2007 2010 ARM Limited All rights reserved 2 59 Non Confidential Compiler Command line Options 2 1 79 2 1 80 2 60 M md This option instructs the compiler to produce a list of make file dependency lines suitable for use by a make utility The compiler executes only the preprocessor step of the compilation By default output is on the standard output stream I
314. rrespective of whether the compiler is compiling for ARM or Thumb The value is defined as zero if the target does not support Thumb ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved 4 105 Non Confidential Compiler specific Features Table 4 18 Predefined macros continued Name Value When defined TARGET ARCH xx xx represents the target architecture and its value depends on the target architecture For example if you specify the compiler options cpu 4T or cpu ARM7TDMI then TARGET ARCH 4T is defined TARGET CPU xx xx represents the target cpu The value of xx is derived from the cpu compiler option or the default if none is specified For example if you specify the compiler option cpu ARM7TM then TARGET CPU ARM7TM is defined and no other symbol starting with TARGET CPU is defined If you specify the target architecture then TARGET CPU generic is defined If the processor name contains hyphen characters these are mapped to an underscore _ For example cpu ARM1136JF S is mapped to TARGET CPU ARM1136JF S TARGET FEATURE DOUBLEWORD ARMVvST and above TARGET FEATURE DSPMUL If the DSP enhanced multiplier is available for example ARMvSTE TARGET FEATURE MULTIPLY Ifthe target architecture supports the long multiply instructions MULL and MULAL TARGET FEATURE DIVIDE If the target arch
315. rsize 3 int8 t const ptr VLD3 8 d 1 d2 re intl6x4x3 t vld3_dup_s16 __transfersize 3 int16_t const ptr NED3 16 d di d2 re int32x2x3_t v1d3 dup 532 transfersize 3 int32 t const ptr NED3 32 d d1 d2 re int64x1x3 t v1d3 dup s64 transfersize 3 int64_t const ptr NLD1 64 100 01 02 r0 float32x2x3 vld3_dup_f32 __transfersize 3 float32 t const ptr NED3 32 d di d2 re poly8x8x3 t v1d3 dup p8 transfersize 3 poly8_t const ptr VLD3 8 d 1 d2 poly16x4x3_t vld3_dup_p16 __transfersize 3 poly16_t const ptr NED3 16 d di d2 re uint8x8x4 t vld4 dup u8 transfersize 4 uint8 t const ptr VLD4 8 100 d1 d2 d3 r0 uint16x4x4_t vld4_dup_u16 __transfersize 4 uint16_t const ptr NED4 16 d di d2 d3 r0 uint32x2x4 t 1104 dup u32 transfersize 4 uint32 t const ptr VLD4 32 d di d2 d3 rd uint64xlx4 t vld4 dup u64 transfersize 4 uint64 t const ptr VLD1 64 100 d1 02 d3 r0 int8x8x4 t vld4 dup s8 transfersize 4 int8 t const ptr VLD4 8 100 d1 d2 d3 re intl6x4x4 t vld4 dup s16 transfersize 4 int16_t const ptr VLD4 16 d di d2 d3 rd int32x2x4 t vld4 dup s32 transfersize 4 int32 t const ptr VLD4 32 d d1 d2 d3 re int64x1x4_t vld4 dup s64
316. rst token that does not belong to a preprocessing directive Copyright 2007 2010 ARM Limited All rights reserved 4 55 Non Confidential Compiler specific Features See also Precompiled header files on page 2 16 in the Compiler User Guide 4 6 11 pragma import symbol name This pragma generates an importing reference to symbol_name This is the same as the assembler directive IMPORT symbol name Syntax pragma import symbol name Where symbol name is a symbol to be imported Usage You can use this pragma to select certain features of the C library such as the heap implementation or real time division If a feature described in this book requires a symbol reference to be imported the required symbol is specified See also Building an application with the C library on page 2 18 in the Libraries Guide 4 6 12 pragma no inline This pragma controls inlining similar to the no inline command line option A function defined under pragma no_inline is not inlined into other functions and does not have its own calls inlined The effect of suppressing inlining into other functions can also be achieved by marking the function as __declspec noinline or __attribute__ noinline Default The default is pragma inline See also no_ inline on page 2 49 __declspec noinline on page 4 25 4 56 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler
317. s z attribute at address __attribute__ aligned __attribute__ deprecated __attribute__ packed attribute section attribute transparent union __attribute__ unused z __attribute__ used attribute weak weak attribute zeroinit 4 5 1 attribute alias 4 40 This variable attribute enables you to specify multiple aliases for variables Where a variable is defined in the current translation unit the alias reference is replaced by a reference to the variable and the alias is emitted alongside the original name Where a variable is not defined in the current translation unit the alias reference is Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler specific Features replaced by a reference to the real variable Where a variable is defined as static the variable name is replaced by the alias name and the variable is declared external if the alias is declared external Note Function names might also be aliased using the corresponding function attribute attribute alias Syntax type newname attribute alias oTdname Where oldname is the name of the variable to be aliased newname is the new name of the aliased variable Example include lt stdio h gt int oldname 1 extern int newname __attribute__ alias oldname dec
318. s code with the options M depend_system_headers produces __image axf hello c See also M on page 2 60 md on page 2 60 diag_error tag tag This option sets the diagnostic messages that have the specified tags to Error severity Note This option has the pragma equivalent pragma diag_error Syntax diag_error tag tag Where tag tag is a comma separated list of diagnostic message numbers specifying the messages whose severities are to be changed At least one diagnostic message number must be specified When specifying multiple diagnostic message numbers do not include spaces between commas and numbers in the list Usage The severity of the following types of diagnostic messages can be changed Messages with the number format nnnn D Warning messages with the number format CnnnnW See also diag remark tag tag on page 2 27 diag suppress tag tag on page 2 28 diag warning tag tag on page 2 30 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options pragma diag error tag tag on page 4 52 Changing the severity of diagnostic messages on page 5 5 in the Compiler User Guide 2 1 31 diag_remark tag tag This option sets the diagnostic messages that have the specified tags to Remark severity The diag_remark option behaves analogously to diag_errors exc
319. s option enables the generation of code that is compatible with the selected library type Syntax library interface lib Where 7ib is one of rvct aeabi clib90 aeabi clib99 aeabi_clib aeabi_glibc Default Specifies that the compiler output works with the RVCT runtime libraries Specifies that the compiler output works with any ISO C90 library compliant with the ARM Embedded Application Binary Interface AEABI Specifies that the compiler output works with any ISO C99 library compliant with the ARM Embedded Application Binary Interface AEABI Specifies that the compiler output works with any ISO C library compliant with the ARM Embedded Application Binary Interface AEABI Selecting the option library_interface aeabi_clib is equivalent to specifying either library interface aeabi clib90 or library interface aeabi c1ib99 depending on the choice of source language used The choice of source language is dependent both on the command line options selected and on the filename suffixes used Specifies that the compiler output works with an AEABI compliant version of the GNU C library If you do not specify library interface the compiler assumes library interface rvct Usage Use the option library_interface rvct to exploit the full range of compiler and library optimizations when linking Copyright 2007 2010 ARM Limited All rights reserved 2 53 Non Confidential Compiler
320. s that a call to a function never results in a C exception being propagated from the call into the caller The ARM library headers automatically add this qualifier to declarations of C functions that according to the ISO C Standard can never throw Usage If the compiler knows that a function can never throw out it might be able to generate smaller exception handling tables for callers of that function Restrictions If a call to a function results in a C exception being propagated from the call into the caller the behavior is undefined This modifier is ignored when not compiling with exceptions enabled Example struct S i S Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler specific Features __declspec nothrow extern void f void void g void 5 FO See also no force new nothrow on page 2 38 Using the operator new function on page 5 13 4 2 __declspec notshared The __declspec notshared attribute asserts that specific classes of dynamic symbols are not exported Example struct __declspec notshared X virtual int f do not export this int X f return 1 struct Y X virtual int g do export this int Y g return 1 4 2 7 __declspec thread ARM DUI 0348A The __declspec thread attribute asserts that variables are thread local and have thread storage duration so that the linker arrang
321. s u32 uint32x2 t a uint32x2 t b uint32x2 t c MMES vmlsq s8 int8x16 t a int8x16 t b int8x16 t c MMES vmlsq sl6 intl6x8 t a int16x8 t b int16x8 t c MMES vmlsq s32 int32x4 t a int32x4 t b int32x4 t C MMES vmlsq f32 float32x4 t a float32x4 t b float32x4 t c WLS vmlsq u8 uint8x16 t a uint8x16 t b uint8x16 t c MMES vmlsq ul6 uintl6x8 t a uintl6x8 t b uintl16x8 t c MMES vmlsq u32 uint32x4 t a uint32x4 t b uint32x4 t c WLS Vector multiply subtract long vmlsl s8 intl6x8 t a int8x8 t b int8x8 t c vmlsl sl6 int32x4 t a intl6x4 t b intl6x4 t c vmlsl s32 int64x2 t a int32x2 t b int32x2 t c vmlsl u8 uint16x8 t a uint8x8 t b uint8x8 t c I8 d0 d0 d0 I16 d0 d0 d0 132 d0 d0 d0 F32 d0 d0 d0 I8 d0 d0 d0 I16 d0 d0 d0 132 d0 d0 d0 I8 q0 q0 q0 116 q0 q0 q0 132 q0 q0 q0 F32 q0 q0 q0 I8 q0 q0 q0 116 q0 q0 q0 132 q0 q0 q0 MMLSL S8 q0 d0 d NMLSL S16 q0 d0 d0 MMLSL S32 q0 d0 d0 NMLSL U8 q0 d0 dO vmlsl ul6 uint32x4 t a uintl6x4 t b uintl6x4 t c VMLSL U16 q0 d0 d0 vmlsl u32 uint64x2 t a uint32x2 t b uint32x2 t c VMLSL U32 q0 d0 d0 Copyright 2007 2010 ARM Limited All rights reserved Non Confidential ARM DUI 0348A Using NEON Support Vector saturating doubling multiply high intl6x4 t vqdmulh s16 intl6x4 t a intl6x4 t b VQDMULH S16 d0 d0 d0 int32x2 t vqdmulh_s32 int32x2_t a int32x2 t b VQDMULH S32 d0 d0 d0 int
322. scalar int32xX4 t vqdmlal lane s16 int32x4 t a intl6x4 t b intl6x4 t v constrange 0 3 int 1 NQDMLAL S16 q0 d 00 0 int64x2 t vqdmlal lane s32 int64x2 t a int32x2 t b int32x2 t v __constrange 1 int 1 NQDMLAL S32 q0 d 00 0 ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved E 47 Non Confidential Using NEON Support Vector multiply subtract with scalar intl6x4 t vmls lane sl6 intl6x4 t a intl6x4 t b intl6x4 t v __constrange Q 3 int 1 MMLS I16 d 00 000 int32x2 t vmls lane s32 int32x2 t a int32x2 t b int32x2 t v constrange 0 1 int 1 MMLS I32 d 00 dO 0 uintl6x4 t vmls lane ul6 uintl6x4 t a uintl6x4 t b uintl6x4 t v __constrange Q 3 int 1 MMLS I16 00 00 dO 0 uint32x2 t vmls lane u32 uint32x2 t a uint32x2 t b uint32x2 t v constrange 0 1 int 1 NMLS I32 d0 d 00 0 float32x2_t vmls lane f32 float32x2 t a float32x2 t b float32x2 t v constrange 0 1 int 1 NMLS F32 00 00 00 0 intl6x8 t vmlsq lane s16 intl6x8 t a intl6x8 t b intl6x4 t v __constrange 0 3 int 1 5 116 q0 00 000 int32xX4 t vmlsq lane s32 int32x4 t a int32x4 t b int32x2 t v constrange 0 1 int 1 VMLS 132 q0 00 000 uint16x8 t wvmlsq lane ul6 uintl6x8 t a uintl6x8 t b uintl6x4 t v __constrange 3 int 1 VMLS 116 q0 00 000 uint32x4 t vmlsq lane u32 uint32x4 t a uint32x4 t b uint32x2 t v constrange 0 1 int 1
323. so builtin return address current sp on page 4 70 4 7 6 builtin return address ARM DUI 0348A This builtin function returns the return address of the current function Note This builtin function is a GNU compiler extension that is supported by the ARM compiler Mode Supported in GNU mode only Syntax void builtin return address unsigned int val Where val is an unsigned integer evaluating to zero Return value builtin return address returns the value of the link register that is used in returning from the current function Example void return address void static void rtn_addr Copyright 2007 2010 ARM Limited All rights reserved 4 67 Non Confidential Compiler specific Features rtn addr builtin return address 0 return the Ir return rtn_addr See also _builtin_frame_address on page 4 66 return address on page 4 83 4 7 7 builtin popcount This builtin function returns the population count of a specified value that is the number of 1 bits in the value Syntax int __builtin_popcount unsigned int val Where val is an unsigned integer whose population is to be counted Return value __builtin_popcount returns the number of bits set to 1 in val Example void foo void int i __builtin_popcount 3 returns 2 int j __builtin_popcount 5 returns 2 int k __builtin_popcount 8 returns 1 4 7 8 __cdp This intrinsic
324. ssing When doing dependent name lookup the compiler implements the instantiation name lookup rules specified in the standard This processing requires that non class prototype instantiations be done This in turn requires that the code be written using the typename and template keywords as required by the standard Lookup using the referencing context When not using dependent name lookup the compiler uses a name lookup algorithm that approximates the two phase lookup rule of the standard but in a way that is more compatible with existing code and existing compilers When a name is looked up as part of a template instantiation but is not found in the local context of the instantiation it is looked up in a synthesized instantiation context This synthesized instantiation context includes both names from the context of the template definition and names from the context of the instantiation For example namespace N int g int int x 0 template class T struct A T f T t return g t T f return x js Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential ARM DUI 0348A C and C Implementation Details namespace M int x 99 double g double N A lt int gt ai int i ai f 0 N A int f int calls N g int int i2 ai f N A int f returns 0 N x N A double ad double d ad f 0 N A double f double calls M g double double d
325. ssumes littleend unless bigend is explicitly specified See also littleend on page 2 57 Endian support on page 4 45 in the Compiler User Guide Specifying Byte Addressing mode on page 2 27 in the Linker Guide no_ brief_diagnostics This option enables or disables the output of brief diagnostic messages by the compiler When enabled the original source line is not displayed and error message text is not wrapped if it is too long to fit on a single line Default The default is no_brief_diagnostics Example main c include lt stdio h gt Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options int main void printf Hello world n return Q Compiling this code with brief_diagnostics produces a warning message See also diag_error tag tag on page 2 26 diag remark tag tag on page 2 27 diag_style armlidelgnu on page 2 27 diag suppress tag tag on page 2 28 diag warning tag tag on page 2 30 errors filename on page 2 34 remarks on page 2 78 W on page 2 94 no_ wrap_diagnostics on page 2 96 Chapter 5 Diagnostic Messages in the Compiler User Guide 2 1 10 bss_threshold num ARM DUI 0348A This option controls the placement of small global ZI data items in sections A small global ZI data item is an uninitialized data item that is eight bytes
326. struction of the form LDR size T into the instruction stream generated by the compiler It enables you to load data from memory in your C or C code using an LDRT instruction Syntax unsigned int __ldrt const volatile void ptr 4 76 Copyright O 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential ARM DUI 0348A Compiler specific Features Where ptr Points to the address of the data to be loaded from memory To specify the size of the data to be loaded cast the parameter to an appropriate integral type Table 4 9 Access widths supported by the Idrt intrinsic Instruction Size of data loaded C cast LDRSBT signed byte signed char LDRBT unsigned byte char LDRSHT signed half word signed short int LDRHT unsigned halfword short int LDRT word int a Or equivalent Return value The __ldrt intrinsic returns the data loaded from the memory address pointed to by ptr Errors The compiler does not recognize the __ldrt intrinsic when compiling for a target that does not support the LDRT instruction The compiler generates either a warning or an error in this case The __ldrt intrinsic does not support access to doubleword data The compiler generates an error if you specify an access width that is not supported Example int foo void int loc Oxff return __ldrt const volatile int loc Compiling this code with the default options produces 100
327. t int32x4 t uint32x4 t int32x2 t uint32x2 t int32x4 t uint32x4 t float32x2 t float32x2 t float32x4 t float32x4 t float32x2 t float32x2 t float32x4 t float32x4 t ARM DUI 0348A These intrinsics are used to convert vectors Convert from float vcvt s32 f32 float32x2 t a vcvt u32 f32 float32x2 t a vcvtq 532 f32 float32x4 t a vevtq_u32_f32 float32x4_t a vcvt n s32 f32 float32x2 t a vcvt n u32 f32 float32x2 t a __ vcvtq n 532 f32 float32x4 t a vcvtq n u32 f32 float32x4 t a constrange 1 32 int b constrange 1 32 int b constrange 1 32 int b constrange 1 32 int b y Convert to float vcvt f32 s32 int32x2 t a vcvt 132 u32 uint32x2 t a vcvtq 32 s32 int32x4 t a vcvtq 32 u32 uint32x4 t a vcvt n f32 s32 int32x2 t a __ vcvt n f32 u32 uint32x2 t a vcvtq n 32 s32 int32x4 t a __ vcvtq n 32 u32 uint32x4 t a constrange 1 32 int b constrange 1 32 int b constrange 1 32 int b constrange 1 32 int b y Vector narrow integer int8x8 t vmovn sl6 intl6x8 t a VMOVN intl6x4 t vmovn s32 int32x4 t a VMOVN int32x2 t vmovn_s64 int64x2_t a VMOVN uint8x8 t vmovn ul6 uintl6x8 t a VMOVN uintl6x4 t vmovn u32 uint32x4 t a VMOVN uint32x2 t vmovn u64 uint64x2 t a VMOVN Vector long move intl6x8 t vmovl s8 int8x8 t a NMOVL int32x4 t vmovl_s16 int16x4_t a VMOVL int64x2 t vmovl_s32 int32x2_t a VMOVL
328. t a int8x16 t b __constrange 1 8 int c NSRI 8 q0 q0 8 intl6x8 t vsrig_n_s16 int16x8_t a int16x8 t b constrange 1 16 int c VSRI 16 q0 q0 416 int32x4 t vsrig n s32 int32x4 t a int32x4 t b constrange 1 32 int c VSRI 32 q0 q0 32 int64x2 t vsrig n s64 int64x2 t a int64x2 t b constrange 1 64 int c VSRI 64 qQ q0 64 uint8x16 t vsriq n u8 uint8x16 t a uint8x16 t b __constrange 1 8 int c VSRI 8 q0 q0 48 uint16x8 t vsriq n ul6 uintl6x8 t a uint16x8_t b constrange 1 16 int c VSRI 16 00 00 16 uint32x4 t vsrig_n_u32 uint32x4_t a uint32x4 t b constrange 1 32 int c VSRI 32 q0 q0 32 uint64x2 t vsrig_n_u64 uint64x2_t a uint64x2 t b constrange 1 64 int c VSRI 64 q0 q0 464 poly8x16 t vsriq n p8 poly8x16 t a poly8x16 t b __constrange 1 8 int c VSRI 8 q0 q0 48 polyl6x8 t vsriq n p16 poly16x8 t a poly16x8 t b constrange 1 16 int c VSRI 16 q0 q0 416 y y y y uu Vector shift left and insert int8x8 t vsli n s8 int8x8 t a int8x8 t b constrange 0 7 int c NSLI 8 d0 d0 20 intl6x4 t vsli_n_s16 int16x4_t a intl6x4 t b __constrange 15 int c NSLI 16 00 00 0 int32x2 t vsli_n_s32 int32x2_t a int32x2 t b __constrange 31 int c NSLI 32 d0 d0 0 int64x1 t vsli n s64 int64x1 t a int64x1l t b __constrange 63 int c NSLI 64 00 00 0 uint8x8 t vsli n u8 uint8x8 t a uint8x8 t b constrange 0 7 int c NSLI 8 d0 d0 20
329. t b vtst p8 poly8x8 t a poly8x8 t b vtstq s8 int8x16 t a int8x16 t b vtstq sl6 intl6x8 t a intl16x8 t b vtstq s32 int32x4 t a int32x4 t b vtstq u8 uint8x16 t a uint8x16 t b vtstq ul6 uintl6x8 t a uintl6x8 t b vtstq u32 uint32x4 t a uint32x4 t b vtstq p8 poly8x16 t a poly8x16 t b NTST VIST NTST NTST NTST VIST NTST NTST NTST NTST VIST VIST NTST NTST 8 00 00 dO 16 00 00 dO 32 00 00 dO 8 00 00 dO 16 00 00 dO 32 00 00 dd 8 00 dd dO 8 00 00 00 16 00 q0 q0 32 00 00 q0 8 00 00 00 16 q0 q0 q0 32 00 00 q0 8 00 00 q0 These intrinsics provide operations including absolute difference Absolute difference between the arguments Vr i Va i Vb i int8x8 t intlox4 t int32x2 t uint8x8 t vabd s8 int8x8 t a int8x8 t b 800 si16 intl6x4 t a intl16x4 t b 800 s32 int32x2 t a int32x2 t b vabd u8 uint8x8 t a uint8x8 t b 080 58 00 00 00 VABD S16 d0 d0 d0 VABD S32 d0 d0 d0 VABD U8 00 00 00 Copyright 2007 2010 ARM Limited All rights reserved Non Confidential ARM DUI 0348A int8x8 t intl6x4 t int32x2 t uint8x8 t int8x16 t intl6x8 t int32x4 t intl6x8 t int32x4 t int64x2 t E 3 6 Max Min ARM DUI 0348A uintl6x4 t uint32x2 t float32x2 t int8x16 t intl6x8 t int32x4 t uint8x16 t uint16x8 t uint32x4 t float32x4 t 800 ul6 uintl6x4 t a ui
330. t value NDUP 32 00 0 int8x8 t vdup n s8 int8 t value NDUP 8 d0 r0 intl6x4 t vdup n s16 intl6 t value NDUP 16 d0 r0 int32x2 t J vdup n s32 int32 t value NDUP 32 00 0 poly8x8 t vdup n p8 poly8 t value NDUP 8 d0 r0 polyl x4 t vdup_n_p1l6 poly16_t value NDUP 16 d0 r0 float32x2 t vdup n f32 float32 t value VDUP 32 d0 r0 Copyright 2007 2010 ARM Limited All rights reserved Non Confidential ARM DUI 0348A uint8x8 t uintl6x4 t uint32x2 t int8x8 t intl6x4 t int32x2 t poly8x8 t polyl6x4 t uint8x16 t uintl6x8 t ARM DUI 0348A uint8x16 t uint16x8 t uint32x4 t int8x16 t intl6x8 t int32x4 t poly8x16 t poly16x8 t float32x4 t int64x1_t uint64x1_t int64x2_t uint64x2_t uint8x8 t uintl6x4 t uint32x2 t int8x8 t int16x4_t int32x2 t poly8x8 t 00 1674 t float32x2 t uint8x16 t uint16x8_t uint32x4_t int8x16 t intl6x8 t int32x4 t poly8x16 t poly16x8 t float32x4 t int64x1_t uint64x1_t int64x2_t uint64x2_t vdupq_n_u8 uint8_t value vdupq n ul6 uintl6 t value vdupq n u32 uint32 t value vdupg_n_s8 int8_t value vdupq n s16 intl6 t value vdupq n s32 int32 t value vdupq n p8 poly8 t value vdupq n pl6 poly16 t value vdupq n f32 float32 t value vdup n s64 int64 t value vdup n u64 uint64 t value vdupq n s64 int64 t value vdupq n u64 uint64 t value vmov n u8 uint8 t value vmov n ul6 uintl6 t value vmov n u32 ui
331. t vsubq ul6 uintl6x8 t a uint16x8_t b VSUB I16 q0 q0 q0 uint32x4 t vsubq u32 uint32x4 t a uint32x4 t b VSUB I32 q0 q0 q0 uint64x2 t vsubq u64 uint64x2 t a uint64x2 t b VSUB I64 q0 q0 q0 Vector long subtract vsub gt Vr i 2 Va i Vb i intl6x8 t vsubl s8 int8x8 t a int8x8 t b NSUBL S8 q0 d0 d0 int32x4 t vsubl si6 intl6x4 t a intl6x4_t b VSUBL S16 q0 d0 d0 int64x2 t vsubl s32 int32x2 t a int32x2 t b VSUBL S32 q0 d0 d0 uintl16x8 t vsubl u8 uint8x8 t a uint8x8 t b NSUBL U8 q0 d0 d0 uint32x4 t vsubl ul6 uintl6x4 t a uintl6x4 t b VSUBL U16 q0 d0 d0 uint64x2 t vsubl u32 uint32x2 t a uint32x2 t b VSUBL U32 q0 d0 d0 Vector wide subtract vsub gt Vr i 2 Va i Vb i intl6x8 t vsubw s8 int16x8 t a int8x8 t b NSUBW S8 q0 q0 d0 int32x4 t vsubw sl6 int32x4 t a intl6x4_t b VSUBW S16 q0 q0 d0 int64x2 t vsubw s32 int64x2 t a int32x2 t b VSUBW S32 q0 q0 d0 uintl6x8 t vsubw u8 uintl6x8 t a uint8x8 t b VSUBW U8 q0 q0 d0 uint32x4 t vsubw ul6 uint32x4 t a uintl6x4 t b VSUBW U16 q0 q0 d0 uint64x2 t vsubw u32 uint64x2 t a uint32x2 t b VSUBW U32 q0 q0 d0 Vector saturating subtract int8x8 t vqsub s8 int8x8 t a int8x8 t b NQSUB S8 d0 d0 d0 intl6x4 t vasub_s16 int16x4_t a intl6x4 t b NQSUB S16 00 00 0 int32x2 t vqsub s32 int32x2 t a int32x2 t b 05 8 532 d0 d0 dO int64xl t vasub_s64 int64x1_t a int64x1_t b NQSUB S64 00 00 0 uint
332. t32x2 t vsra n s32 int32x2 t a int32x2 t b __constrange 1 32 int c NSRA int64x1l t vsra n s64 int64x1l t a int64x1l t b __constrange 1 64 int c NSRA uint8x8 t vsra n u8 uint8x8 t a uint8x8 t b __constrange 1 8 int c NSRA uintl6x4 t vsra n ul6 uintl6x4 t a uintl6x4 t b uint32x2_t vsra n u32 uint32x2 t a uint32x2 t b uint64x1 t vsra n u64 uint64x1l t a uint64x1l t b int8x16 t vsrag n s8 int8x16 t a int8x16 t b __constrange 1 8 int c NSRA intl6x8 t vsrag n sl16 intl16x8 t a intl16x8 t b constrange 1 16 int c VSRA int32x4 t vsrag n s32 int32x4 t a int32x4 t b __constrange 1 32 int c VSRA int64x2 t vsrag n s64 int64x2 t a int64x2 t b __constrange 1 64 int c VSRA uint8x16 t vsraq_n_u8 uint8x16_t a uintl16x8 t vsrag n ul6 uintl16x8 t a uint16x8 t b Uint32x4 t vsrag n u32 uint32x4 t a uint32x4 t b uint64x2 t vsrag_n_u64 uint64x2_t a uint64x2 t b int8x8 t intl6x4 t int32x2 t int64x1_t uint8x8_t int8x16 t int16x8_t int32x4 t int64x2 t ARM DUI 0348A vrshr n u8 uint8x8 t a uintl6x4 t vrshr n ul6 uintl6x4 t a uint32x2 t vrshr n u32 uint32x2 t a uint64x1 t vrshr n u64 uint64x1 t a vrshrq n s8 int8x16 t a vrshrq n s16 int16x8 t a vrshrq n s32 int32x4 t a vrshrq n s64 int64x2 t a uint8x16 t vrshrq n u8 uint8x16 t a uintl16x8 t vrshrq n ul6 uintl16x8 t a uint32x4_t vrshrq n u32 uint32x4 t a uint64x2 t vrshrq n u64 uint64x2 t a vrsra n s8 int8x8 t a i
333. t32x2x4 t src __constrange 1 int lane NLD4 32 d0 0 d1 0 d2 0 d3 0 rd poly8x8x4 t vld4 lane p8 transfersize 4 poly8 t const ptr poly8x8x4 t src constrange 0 7 int lane VLD4 8 100 0 d1 d2 0 d3 0 r0 poly16x4x4_t vild4 lane p16 transfersize 4 polyl6 t const ptr polyl6x4x4 t src constrange 0 3 int lane NLD4 16 100 0 di 0 d2 0 d3 0 re void vst2q u8 transfersize 32 uint8 t ptr uint8x16x2 t val VST2 8 100 02 r0 void vst2q ul6 transfersize 16 uintl6 t ptr uint16x8x2_t val NST2 16 100 d2 r0 void vst2q u32 transfersize 8 uint32 t ptr uint32x4x2 t val NST2 32 100 02 r0 void vst2q s8 transfersize 32 int8 t ptr int8x16x2 t val NST2 8 100 d2 rd void vst2q s16 transfersize 16 intl6 t ptr int16x8x2_t val NST2 16 100 02 r0 void vst2q s32 transfersize 8 int32 t ptr int32x4x2 t val NST2 32 100 02 r0 void vst2q f32 transfersize 8 float32 t ptr float32x4x2 t val NST2 32 100 02 r0 void vst2q_p8 __transfersize 32 poly8 t ptr poly8x16x2 t val NST2 8 100 d2 rd void vst2q_p16 __transfersize 16 poly16 t ptr polyl6x8x2 t val NST2 16 d0 d2 r0 void vst2 u8 transfersize 16 uint8 t ptr uint8x8x2 t val VST2 8 100 d1 r0 void vst2 ul6 transfersize 8 uintl6 t ptr uintl6x4x2 t val NST2 16 100 d1 r0 void vst2 u32 transfersize
334. t32x2x4 t val VST4 32 d0 d1 d2 d3 r9 vst4 u64 transfersize 4 uint64 t ptr uint64x1x4_t val NST1 64 d0 d1 d2 d3 r9 vst4 s8 transfersize 32 int8 t ptr int8x8x4 t val NST4 8 100 d1 02 d3 r0 vst4_s16 __transfersize 16 int16 t ptr intl6x4x4 t val NST4 16 100 01 d2 d3 r0 vst4 s32 transfersize 8 int32 t ptr int32x2x4 t val NST4 32 100 01 02 d3 r0 vst4 s64 transfersize 4 int64 t ptr int64x1x4_t val NST1 64 100 01 d2 d3 r0 vst4_f32 __transfersize 8 float32 t ptr float32x2x4 t val NST4 32 100 01 02 d3 r0 vst4 p8 transfersize 32 poly8 t ptr poly8x8x4 t val NST4 8 100 d1 02 d3 r0 vst4 pl6 transfersize 16 polyl6 t ptr poly16x4x4_t val NST4 16 d0 d1 d2 d3 r9 vst2q lane ul6 transfersize 2 uintl6 t ptr uintl6x8x2 t val constrange 0 7 int lane NST2 16 100 0 d2 0 rd vst2q_lane_u32 __transfersize 2 uint32 t ptr uint32x4x2 t val __constrange 0 3 int lane NST2 32 100 0 d2 0 rd Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential void void void void void void void void void void void void void void void void void void void void void void void void void ARM DUI 0348A vst2q lane s16 transfersize 2 intl6 t ptr intl6x8x2 t val vst2q lane s32 trans
335. t8x16 t uint16x8_t uint32x4_t uint32x4_t uint8x16 t uint16x8 t uint32x4 t vcle f32 float32x2 t a float32x2 t b vcle_u8 uint8x8_t a uint8x8 t b vcle_ul6 uint16x4_t a uintl6x4 t b vcle_u32 uint32x2_t a uint32x2 t b vcleq s8 int8x16 t a int8x16 t b vcleq s16 intl6x8 t a intl16x8 t b vcleq s32 int32x4 t a int32x4 t b vcleq f32 float32x4 t a float32x4 t b vcleq u8 uint8x16 t a uint8x16 t b vcleq ul6 uintl6x8 t a uintl6x8 t b vcleq u32 uint32x4 t a uint32x4 t b Vector compare greater than uint8x8 t uintl6x4 t uint32x2 t uint32x2 t uint8x8 t uintl6x4 t uint32x2 t uint8x16 t uint16x8 t uint32x4 t uint32x4 t uint8x16 t uint16x8 t uint32x4 t vcgt s8 int8x8 t a int8x8 t b vcgt sl6 intl6x4 t a intl6x4 t b vcgt s32 int32x2 t a int32x2 t b vcgt f32 float32x2 t a float32x2 t b vcgt u8 uint8x8 t a uint8x8 t b vcgt ul6 uintl6x4 t a uintl6x4 t b vcgt u32 uint32x2 t a uint32x2 t b vcgtq s8 int8x16 t a int8x16 t b vcgtq sl6 intl6x8 t a intl16x8 t b vcgtq s32 int32x4 t a int32x4 t b vcgtq f32 float32x4 t a float32x4 t b vcgtq u8 uint8x16 t a uint8x16 t b vcgtq ul6 uintl6x8 t a uintl6x8 t b vcgtq u32 uint32x4 t a uint32x4 t b Vector compare less than uint8x8 t uintl6x4 t uint32x2 t uint32x2 t uint8x8 t uintl6x4 t uint32x2 t uint8x16 t uint16x8_t uint32x4_t uint32x4_t uint8x16 t uint16x8 t uint32x4 t Copyright O 2007 2010 ARM Limited All
336. t8x8 t vldl lane s8 transfersize 1 int8 t const ptr int8x8 t vec VLD1 8 d 0 rd intl6x4_t vldl lane s16 transfersize 1 int16_t const ptr intl6x4 t vec lane constrange 0 7 int lane constrange 0 3 int VLD1 16 d 0 r0 int32x2 t vldl lane s32 transfersize 1 int32 t const ptr int32x2 t vec lane constrange 0 1 int VLD1 32 d0 0 rd float32x2 t vldl lane f32 transfersize 1 float32 t const ptr float32x2 t vec int lane constrange 0 1 VLD1 32 d0 0 10 E 26 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential int64xl t vldl lane s64 transfersize 1 int64 t const ptr int64x1l t vec lane NLD1 64 100 r0 poly8x8 t vidl lane p8 transfersize 1 poly8 t const ptr poly8x8 t vec lane NLD1 8 d0 0 r0 polyl6x4 t 1101 lane pl6 transfersize 1 poly16_t const ptr polyl6x4 t vec lane NLD1 16 d0 0 r0 uint8x16 t vldiq dup u8 transfersize 1 uint8 t const ptr VLD1 8 d r0 uintl6x8 t vldiq dup ul6 transfersize 1 uintl16 t const ptr NED1 16 dO r0 uint32x4 t vldiq dup u32 transfersize 1 uint32 t const ptr VLD1 32 d0 r0 uint64x2 t vldiq dup u64 transfersize 1 uint64 t const ptr VLD1 64 d0 r0 int8x16 t vldiq dup s8 transfersize 1 int8 t const ptr VLD1 8 d r0 intl6x8 t vldiq dup s16 transfersize
337. te is a GNU compiler extension that is supported by the ARM compiler Note Individual function parameters might also be qualified with the corresponding __attribute__ transparent_union variable attribute Example typedef union int i float f U __attribute__ transparent_union void foo U u static int s S u i Use the int field 4 38 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler specific Features void caller void foo 1 u i is set to 1 foo 1 0f u f is set to 1 0f Mode Supported in GNU mode only See also attribute transparent union on page 4 45 ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved 4 39 Non Confidential Compiler specific Features 4 5 Variable attributes The attribute keyword enables you to specify special attributes of variables or structure fields functions and types The keyword format is either attribute attributel attribute2 attribute __attributel__ __attribute2__ For example void Function Attributes malloc O0 int b attribute malloc static int b attribute __unused__ Table 4 3 on page 4 29 summarizes the available variable attributes Table 4 5 Variable attributes supported by the compiler and their equivalents Variable attribute non attribute equivalent __attribute__ alia
338. ted All rights reserved 5 17 Non Confidential C and C Implementation Details 5 2 7 5 18 C exception handling C exception handling is fully supported in RVCT However the compiler does not support this by default You must enable C exception handling with the exceptions option See no exceptions on page 2 35 for more information Note The Rogue Wave Standard C Library is provided with C exceptions enabled You can exercise limited control over exception table generation Function unwinding at runtime By default functions compiled with exceptions can be unwound at runtime See no exceptions on page 2 35 for more information Function unwinding includes destroying C automatic variables and restoring register values saved in the stack frame Function unwinding is implemented by emitting an exception table describing the operations to be performed You can enable or disable unwinding for specific functions with the pragmas pragma exceptions unwind and pragma no exceptions unwind see Pragmas on page 4 49 for more information The exceptions_unwind option sets the initial value of this pragma Disabling function unwinding for a function has the following effects Exceptions cannot be thrown through that function at runtime and no stack unwinding occurs for that throw If the throwing language is C then std terminate is called A very compact exception table representation can
339. that is with j inside k When pragma unroll is uncommented in the example the compiler proceeds to unroll the loop four times Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler specific Features If the intention is to multiply a matrix that is not a multiple of four in size for example an n n matrix pragma unroll m might be used instead where m 15 some value such that nis an integral multiple of m See also diag_warning optimizations on page 2 31 Onum on page 2 66 Otime on page 2 69 no_ vectorize on page 2 91 pragma unroll completely Optimizing loops on page 4 4 in the Compiler User Guide 4 6 22 pragma unroll completely ARM DUI 0348A This pragma instructs the compiler to completely unroll a loop It has an effect only if the compiler can determine the number of iterations the loop has Note Both vectorized and non vectorized loops can be unrolled using pragma unro1l completely That 13 pragma unroll completely applies to both no vectorize and vectorize Usage When compiling at 03 Otime the compiler automatically unrolls loops where it is beneficial to do so You can use this pragma to request that the compiler completely unroll a loop that has not automatically been unrolled completely Note Use this pragma only when you have evidence for example from diag_warning optimizations that the compiler is not unrol
340. the previous int container skips the first two bits that are allocated to x and allocates two bits to y If y is declared char y 8 the compiler pads the second byte and allocates a new char container to the third byte because the bitfield cannot overflow its container Figure 5 2 shows the bitfield allocation for the following example structure struct X int x 10 char y 8 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1615 14 13121110987654 3210 Figure 5 2 Bitfield allocation 1 Copyright 2007 2010 ARM Limited All rights reserved 5 11 Non Confidential C and C Implementation Details Note The same basic rules apply to bitfield declarations with different container types For example adding an int bitfield to the example structure gives struct X int x 10 char y 8 int z 5 The compiler allocates an int container starting at the same location as the int x 10 container and allocates a byte aligned char and 5 bit bitfield see Figure 5 3 Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 free 2 y padding X Figure 5 3 Bitfield allocation 2 You can explicitly pad a bitfield container by declaring an unnamed bitfield of size zero A bitfield of zero size fills the container up to the end if the container is not empty A subsequent bitfield declaration starts a new empty container Bitfields in packed structures
341. ther a warning or an error in this case See also nop on page 4 78 __wfe on page 4 94 __wfi on page 4 94 _ yield on page 4 95 NOP SEV WFE WFI and YIELD on page 4 139 in the Assembler Guide This intrinsic inserts a VFP VSQRT instruction into the instruction stream generated by the compiler It enables you to obtain the square root of a double precision floating point value from within your C or C code Note The __sqrt intrinsic is an analogue of the standard C library function sqrt It differs from the standard library function in that a call to __sqrt is guaranteed to be compiled into a single inline machine instruction on an ARM architecture based processor equipped with a VFP coprocessor Syntax double __sqrt double val Copyright O 2007 2010 ARM Limited All rights reserved 4 87 Non Confidential Compiler specific Features Where val is a double precision floating point value Return value The __sqrt intrinsic returns the square root of val as a double Errors The compiler does not recognize the __sqrt intrinsic when compiling for a target that is not equipped with a VFP coprocessor The compiler generates either a warning or an error in this case See also __sqrtf VABS VNEG and VSQRT on page 5 89 in the Assembler Guide 47 37 __sqrtf This intrinsic is a single precision version of the __sqrtf intrinsic It is functionally equivalent to __sqrt except that it takes
342. time to ensure that direct calls between different compilation units are sensible If possible define global register variables used in a program in each compilation unit of the program In general it is best to place the definition in a global header file You must set up the value in the global register early in your code before the register is used A global register variable maps to a callee saved register so its value is saved and restored across a call to a function in a compilation unit that does not use it as a global register variable such as a library function Calls back into a compilation unit that uses a global register variable are dangerous For example if a function using a global register is called from a compilation unit that does not declare the global register variable the function reads the wrong values from its supposed global register variables This storage class can only be used at file scope Example Example 4 1 declares a global variable register allocated to r5 Example 4 1 Declaring a global integer register variable _ global_reg 2 int x v2 is the synonym for r5 Example 4 2 produces an error because global register must be specified in all declarations of the same variable Example 4 2 Global register declaration error int x _ global_reg 1 int x error In C global reg variables cannot be initialized at definition Example 4 3 on page 4 9 produces an error in C but not i
343. ting system This includes system paths constructed by the compiler itself for example for include searching Note The removal of sequences of the form xyz might not be valid if xyz is a link Mode This option is effective on Windows systems only Usage Windows systems impose a 260 character limit on file paths Where path names exist whose absolute names expand to longer than 260 characters you can use the reduce paths option to reduce absolute path name length by matching up directories with corresponding instances of and eliminating the directory sequences in pairs Copyright O 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options Note It is recommended that you avoid using long and deeply nested file paths in preference to minimizing path lengths using the reduce paths option Default The default 15 no reduce paths Example Compiling the file xyzzy xyzzy objects file c from the directory foo bar baz gazonk quux bop results in an actual path of foo bar baz gazonk quux bop xyzzy xyzzy objects file o Compiling the same file from the same directory using the option reduce_paths results in an actual path of foo bar baz xyzzy xyzzy objects file c 2 1 101 reinitialize_workdir ARM DUI 0348A This option enables you to reinitialize the project template working directory set using workdir When th
344. tions including multiplication Vector multiply vmul gt Vr i Va i Vb i int8x8 t intl6x4 t int32x2 t float32x2 t uint8x8 t uintl6x4 t uint32x2 t poly8x8 t int8x16 t intl6x8 t int32x4 t float32x4 t uint8x16 t uint16x8 t uint32x4 t poly8x16 t vmul s8 int8x8 t a int8x8 t b vmul si6 intl6x4 t a intl16x4 t b vmul s32 int32x2 t a int32x2 t b f32 float32x2 t a float32x2 t b vmul u8 uint8x8 t a uint8x8 t b ul6 uintl6x4 t a uintl6x4 t b vmul_u32 uint32x2_t a uint32x2 t b vmul p8 poly8x8 t a poly8x8 t b vmulq s8 int8x16 t a int8x16 t b vmulq sl6 intl6x8 t a intl16x8 t b vmulq s32 int32x4 t a int32x4 t b vmulq f32 float32x4 t a float32x4 t b vmulq u8 uint8x16 t a uint8x16 t b vmulq ul6 uintl6x8 t a uintl6x8 t b vmulq u32 uint32x4 t a uint32x4 t b vmulq p8 poly8x16 t a poly8x16 t b V MUL MUL MUL UL UL UL UL MUL MUL MUL MUL MUL MUL MUL MUL MUL Using NEON Support VADDHN I16 d0 q0 q0 VADDHN I32 d0 q0 q0 VADDHN I64 d0 q0 q0 uintl16x8 t b VADDHN I16 d0 q0 q0 uint32x4 t b VADDHN I32 d0 q0 q0 uint64x2 t b VADDHN I64 d0 q0 q0 VRADDHN I16 d0 q0 q0 NRADDHN I32 d0 q0 q0 NRADDHN I64 d0 q0 q0 vraddhn ul6 uintl16x8 t a uintl16x8 t b VRADDHN I16 d0 q0 q0 vraddh
345. tive values shift right int8x8 t vqshl s8 int8x8 t a int8x8 t b VQSHL intl6x4 t vashl_s16 int16x4_t a intl6x4 t b VQSHL int32x2 t vqshl s32 int32x2 t a int32x2 t b VQSHL int64xl t vashl_s64 int64x1_t a int64x1_t b VQSHL uint8x8 t vqshl u8 uint8x8 t a int8x8 t b NQSHL uintl6x4 t vqshl ul6 uintl6x4 t a intl6x4 t b VQSHL uint32x2 t vqshl u32 uint32x2 t a int32x2 t b VQSHL uint64x1 t vqshl u64 uint64x1 t a int64x1l t b VQSHL int8x16 t vqshlq s8 int8x16 t a int8x16 t b VQSHL E 18 Copyright 2007 2010 ARM Limited All rights reserved Non Confidential S8 d0 d0 d0 S16 d0 d0 d0 S32 d0 d0 d0 S64 d0 d0 d0 U8 d0 d0 dO U16 d0 d0 dO U32 00 00 00 064 00 00 00 S8 q0 q0 q0 ARM DUI 0348A ARM DUI 0348A Using NEON Support intl6x8 t vashlq_s16 int16x8_t a intl16x8 t b VQSHL S16 q0 q0 q0 int32x4 t vqshlq s32 int32x4 t a int32x4 t b VQSHL S32 q0 q0 q0 int64x2 t vashlq_s64 int64x2_t a int64x2 t b VQSHL S64 q0 q0 q0 uint8x16 t vqshlq u8 uint8x16 t a int8x16 t b VQSHL U8 q0 q0 q0 uintl6x8 t vqshlq ul6 uintl6x8 t a int16x8_t b VQSHL U16 q0 q0 q0 uint32x4 t vqshlq u32 uint32x4 t a int32x4 t b VQSHL U32 q0 q0 q0 uint64x2 t vqshlq u64 uint64x2 t a int64x2 t b VQSHL U64 q0 q0 q0 Vector rounding shift left negative values shift right int8x8 t vrshl_s8 int8x8_t a int8x8 t b NRSHL S8 d0 d0 d0 intlox4 t vrshl si16 intl6x4 t a
346. tl6 t c MLS 116 00 00 000 uint32x2 t wvmls n u32 uint32x2 t a uint32x2 t b uint32_t c MMLS I32 00 00 dO 0 float32x2 t vmls n f32 float32x2 t a float32x2 t b float32 t c VMLS F32 d 00 d0 0 intl6x8 t vmlsq n sl16 int16x8 t a intl6x8 t b intl16 t c MMLS I16 q0 q0 000 int32xX4 t vmlsq n s32 int32x4 t a int32x4 t b int32 t c 5 132 q0 q0 000 uint16x8 t vmlsq n ul6 uint16x8 t a uintl16x8 t b uint16 t c MMLS I16 q0 q0 d0 0 uint32x4 t vmlsq n u32 uint32x4 t a uint32x4 t b uint32_t c 5 132 q0 q0 000 float32x4 t vmlsq n f32 float32x4 t a float32x4 t b float32 t c VMLS F32 00 q0 00 0 Vector widening multiply subtract with scalar int32x4 t vmlsl n sl6 int32x4 t a intl6x4 t b intl16 t c MMLSL S16 q0 d dO 0 int64x2 t vmlsl n s32 int64x2 t a int32x2 t b int32 t c MMLSL S32 q0 d dO 0 uint32x4 t wvmlsl n ul6 uint32x4 t a uintl6x4 t b uint16_t c MMLSL U16 q0 d dO 0 uinto4x2 t wvmlsl n u32 uint64x2 t a uint32x2_t b uint32 t c MMLSL U32 q0 d 000 Vector widening saturating doubling multiply subtract with scalar int32x4 t vqdmlsl n sl6 int32x4 t a intl6x4 t b intl16 t c VQDMLSL S16 00 dQ 00 0 int64x2 t vqdmlsl n s32 int64x2 t a int32x2 t b int32 t c VQDMLSL S32 00 d 00 0 E 3 26 Vector extract int8x8 t vext s8 int8x8 t a int8x8 t b __constrange Q 7 int c NEXT 8 d d0 d0 0
347. tl6x4 t a intl6x4 t b VQRSHL U16 d0 d0 d0 uint32x2 t vqrshl u32 uint32x2 t a int32x2 t b VQRSHL U32 d0 d0 d0 uint64x1 t vqrshl u64 uint64x1 t a int64x1l t b VQRSHL U64 d0 d0 d0 int8x16 t vqrshlq s8 int8x16 t a int8x16 t b VQRSHL S8 q0 q0 q0 intl6x8 t varshlq_s16 int16x8_t a intl16x8 t b VQRSHL S16 q0 q0 q0 int32x4 t vqrshlq s32 int32x4 t a int32x4 t b VQRSHL S32 q0 q0 q0 int64x2 t vqrshlq s64 int64x2 t a int64x2 t b VQRSHL S64 q0 q0 q0 uint8x16 t vqrshlq u8 uint8x16 t a int8x16 t b VQRSHL U8 q0 q0 q0 uintl6x8 t vqrshlq ul6 uintl6x8 t a intl16x8 t b VQRSHL U16 q0 q0 q0 uint32x4 t vqrshlq u32 uint32x4 t a int32x4 t b VQRSHL U32 q0 q0 q0 uint64x2 t vqrshlq u64 uint64x2 t a int64x2 t b VQRSHL U64 q0 q0 q0 Copyright O 2007 2010 ARM Limited All rights reserved Non Confidential Using NEON Support E 3 12 Shifts by a constant These intrinsics provide operations for shifting by a constant Vector shift right by constant int8x8 t vshr n s8 int8x8 t a __ intlox4 t vshr_n_s16 int16x4_t a int32x2 t vshr n s32 int32x2 t a int64xl t vshr n se4 int64xl t a uint8x8 t vshr n u8 uint8x8 t a __ uintl6x4 t vshr n ul6 uintl6x4 t a uint32x2 t vshr n u32 uint32x2 t a uint64x1l t vshr n u64 uint64x1l t a int8x16 t vshrg n s8 int8x16 t a __ intl6x8 t vshrq_n_s16 int16x8_t a int32x4 t vshrg n s32 int32x4 t a int64x2 t vshrq_n_s64 int64x2_t a uint8x16 t vshrq n u8 uint8x16 t a __ uintl6
348. to __fabs is guaranteed to be compiled into a single inline machine instruction on an ARM architecture based processor equipped with a VFP coprocessor Syntax double __fabs double val Where val is a double precision floating point value Return value The __fabs intrinsic returns the absolute value of val as a double See also fabsf VABS VNEG and VSQRT on page 5 89 in the Assembler Guide 4 7 18 fabsf This intrinsic is a single precision version of the fabs intrinsic It is functionally equivalent to __fabs except that it takes an argument of type float instead of an argument of type double it returns a float value instead of a double value See also _ fabs on page 4 73 V QJABS and V Q NEG on page 5 52 in the Assembler Guide 4 7 19 force stores This intrinsic causes all variables that are visible outside the current function such as variables that have pointers to them passed into or out of the function to be written back to memory if they have been changed This intrinsic also acts as a scheduling barrier 4 74 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential 4 7 20 ldrex ARM DUI 0348A Compiler specific Features Syntax void force stores void See also memory changed on page 4 78 schedule barrier on page 4 85 This intrinsic inserts an instruction of the form LDREX size into the instruction stream generated b
349. to export symbols weakly The __weak keyword can be applied to function and variable declarations and to function definitions 4 20 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler specific Features Usage Functions and variable declarations For declarations this storage class specifies an extern object declaration that even if not present does not cause the linker to fault an unresolved reference For example weak void f void fO call f weakly If the reference to a missing weak function is made from code that compiles to a branch or branch link instruction then either The reference is resolved as branching to the next instruction This effectively makes the branch a NOP The branch is replaced by a NOP instruction Function definitions Functions defined with __weak export their symbols weakly A weakly defined function behaves like a normally defined function unless a non weakly defined function of the same name is linked into the same image If both a non weakly defined function and a weakly defined function exist in the same image then all calls to the function resolve to call the non weak function If multiple weak definitions are available the linker chooses one for use by all calls Functions declared with __weak and then defined without __weak behave as non weak functions Restrictions There are restrictions when you qualify function and va
350. transfersize 4 int64_t const ptr VLD1 64 100 d1 02 d3 float32x2x4 t vld4 dup f32 transfersize 4 float32 t const ptr VLD4 32 d di d2 d3 poly8x8x4 t vld4_dup_p8 __transfersize 4 poly8_t const ptr VLD4 8 100 d1 d2 d3 re polyl6x4x4 t vld4_dup_p16 __transfersize 4 poly16_t const ptr NED4 16 d di d2 d3 r0 uintl6x8x2 t vld2q_lane_u16 __transfersize 2 uint16 t const ptr uint16x8x2_t src __constrange 0 7 int lane NED2 16 d0 0 d2 r0 uint32x4x2 t vld2q lane u32 transfersize 2 uint32 t const ptr uint32x4x2 t src __constrange 0 3 int lane VLD2 32 d0 0 d2 r0 intl6x8x2 t vld2q lane s16 transfersize 2 int16 t const ptr intl6x8x2 t src int lane constrange 0 7 VLD2 16 do 0 d2 0 3 r0 ARM DUI 0348A Copyright 2007 2010 ARM Limited All rights reserved E 33 Non Confidential Using NEON Support int32x4x2 t v1d2q lane s32 transfersize 2 int32 t const ptr int32x4x2 t src int lane constrange 0 3 NLD2 32 100 0 d2 0 r float32x4x2 t vld2q_lane_f32 __transfersize 2 float32 t const ptr float32x4x2_t src __constrange 0 3 int lane NLD2 32 100 0 d2 0 rd poly16x8x2 t vld2q lane pl6 transfersize 2 poly16 t const ptr polyl6x8x2 t src __constrange 7 int lane VLD2 16 100 0 d2 0 rd uint8x8x2 t vld2_lane_u8 __transfersize 2 uint8
351. uage file with name filename E o filename produces a file containing preprocessor output with name filename If you do not specify a o option the compiler names the output file according to the conventions of Table 2 5 Table 2 5 Compiling without the o option Compiler option C Action Usage notes produces an object file whose name defaults to the name of the input file with the filename extension o Copyright O 2007 2010 ARM Limited All rights reserved 2 65 Non Confidential Compiler Command line Options 2 1 87 2 66 Onum Table 2 5 Compiling without the o option continued Compiler option Action Usage notes S produces an output file whose name defaults to the name of the input file with the filename extension s E writes output from the preprocessor to the standard output stream No option produces an executable image with the none of o c E or S default name of __image axf is specified on the command line Note This option overrides the default extension option See also asm on page 2 8 c on page 2 12 default_extension ext on page 2 22 depend filename on page 2 23 depend_format string on page 2 24 E on page 2 33 interleave on page 2 50 list on page 2 55 md on page 2 60 S on page 2 80 This option specifies the level of optimization to be used when compiling source files Syntax Onum Whe
352. ug dwarf3 debug macros See also no debug macros dwarf2 on page 2 33 dwarf3 on page 2 33 Onum on page 2 66 2 1 24 no_ debug_macros ARM DUI 0348A This option enables or disables the generation of debug table entries for preprocessor macro definitions Usage Using no_debug_macros might reduce the size of the debug image This option must be used with the debug option Default The default is debug_macros See also no_ debug Copyright 2007 2010 ARM Limited All rights reserved 2 21 Non Confidential Compiler Command line Options 2 1 25 2 1 26 2 22 default_extension ext This option enables you to change the filename extension for object files from the default extension 0 to an extension of your choice Syntax default_extension ext Where ext is the filename extension of your choice Example The following example creates an object file called test obj instead of test o armcc default_extension obj c test c Note The o filename option overrides this For example the following command results in an object file named test o armcc default_extension obj o test o c test c no dep name This option enables or disables dependent name processing in C The C standard states that lookup of names in templates occurs at the time the template is parsed if the name is non dependent at the time the template is parsed or at
353. uint8x8 t vext u8 uint8x8 t a uint8x8 t b __constrange Q 7 int c NEXT 8 d d0 d0 0 poly8x8 t vext p8 poly8x8 t a poly8x8_t b __constrange Q 7 int c NEXT 8 d0 d0 d0 20 intl6x4 t vext sl6 intl6x4 t a intl6x4_t b __ uintl6x4 t vext ul6 uintl6x4 t a uintl6x4 t b poly16x4_t vext pl6 polyl6x4 t a polyl6x4 t b int32x2 t vext s32 int32x2 t a int32x2_t b __ uint32x2 t vext u32 uint32x2 t a uint32x2 t b int64xl t vext_s64 int64x1_t a int64x1_t b __ uint64x1l t vext u64 uint64x1l t a uint64x1_t b int8x16 t vextq s8 int8x16 t a int8x16 t b __ uint8x16 t vextq u8 uint8x16 t a uint8x16 t b poly8x16 t vextq p8 poly8x16 t a poly8x16 t b intl6x8 t vextq sl6 intl6x8 t a intl16x8 t b __ uintl16x8 t vextq ul6 uintl6x8 t a uintl6x8 t b polyl6x8 t vextq pl6 poly16x8 t a poly16x8 t b constrange 0 3 int c NEXT 16 d d0 d0 0 constrange 0 3 int c VEXT 16 dQ d0 d0 0 constrange 0 3 int c VEXT 16 d0 d0 d0 0 constrange 0 1 int c NEXT 32 00 00 00 0 constrange 0 1 int c VEXT 32 d0 d0 d0 0 constrange 0 0 int c NEXT 64 00 00 00 0 constrange 0 0 int c VEXT 64 d0 d0 d0 0 constrange 0 15 int c VEXT 8 q0 q0 90 20 constrange 0 15 int c VEXT 8 q0 q0 q0 0 constrange 0 15 int c VEXT 8 q0 q0 q0 0 constrange 0 7 int c VEXT 16 q0 q0 q0 20 constrange 0 7 int c VEXT 16 q0 q0 q0 40 constrange 0 7 int c VEXT 16 q0 q0 q0 0 ARM DUI 0348
354. ult If you do not specify a pending_instantations option then the compiler assumes pending instantiations 64 Usage Use this option to detect runaway recursive instantiations 2 1 97 pointer alignmentenum ARM DUI 0348A This option specifies the unaligned pointer support required for an application Syntax pointer_alignment num Where num is one of 1 Treats accesses through pointers as having an alignment of one that is byte aligned or unaligned 2 Treats accesses through pointers as having an alignment of at most two that is at most halfword aligned Copyright 2007 2010 ARM Limited All rights reserved 2 73 Non Confidential Compiler Command line Options 2 1 98 2 74 4 Treats accesses through pointers as having an alignment of at most four that is at most word aligned 8 Accesses through pointers have normal alignment that is at most doubleword aligned Usage This option can help you port source code that has been written for architectures without alignment requirements You can achieve finer control of access to unaligned data with less impact on the quality of generated code using the packed qualifier Restrictions De aligning pointers might increase the code size even on CPUs with unaligned access support This is because only a subset of the load and store instructions benefit from unaligned access support The compiler is unable to use multiple word transfers or coprocessor
355. unit See also arm on page 2 7 cpu name on page 2 15 thumb on page 2 86 __softfp on page 4 15 The fpu option on page 4 32 in the Compiler User Guide Using the fpu option on page 4 34 in the Compiler User Guide 2 1 56 no friend injection This option controls the visibility of friend declarations in C In C it controls whether or not the name of a class or function that is declared only in friend declarations is visible when using the normal lookup mechanisms ARM DUI 0348A Copyright O 2007 2010 ARM Limited All rights reserved 2 43 Non Confidential Compiler Command line Options 2 1 57 2 1 58 2 44 gnu When friend names are declared they are visible to these lookups When friend names are not declared as required by the standard function names are visible only when using argument dependent lookup and class names are never visible Note The option friend injection is provided only as a migration aid for legacy source code that does not conform to the C standard Its use is not recommended Mode This option is effective only if the source language is C Default The default is no friend injection See also friend on page 3 15 This option enables the GNU compiler extensions supported by the ARM compiler The version of GCC the extensions are compatible with can be determined by inspecting the predefined macros __GNUC__ and __GNUC_MINOR__ See also
356. up accesses to packed structures To enable unaligned support you must Clear the A bit bit 1 of CP15 register 1 in your initialization code Set the U bit bit 22 of CP15 register 1 in your initialization code The initial value of the U bit is determined by the UBITINIT input to the core The RVCT libraries include special versions of certain library functions designed to exploit unaligned accesses When unaligned access support is enabled the RVCT tools use these library functions to take advantage of unaligned accesses 2 88 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler Command line Options no unaligned access Use no unaligned access to disable the generation of unaligned word and halfword accesses on ARMV6 processors To enable modulo four byte alignment checking on an ARMv6 target without unaligned accesses you must Set the A bit bit 1 of CP15 register 1 in your initialization code Set the U bit bit 22 of CP15 register 1 in your initialization code The initial value of the U bit is determined by the UBITINIT input to the core Note Unaligned doubleword accesses for example unaligned accesses to long long integers are not supported by ARM processor cores Doubleword accesses must be either eight byte or four byte aligned The compiler does not provide support for modulo eight byte alignment checking That is the configuratio
357. urn __attribute__ pure 7 __attribute__ unused __attribute__ used attribute weak weak 4 3 1 attribute alias ARM DUI 0348A This function attribute enables you to specify multiple aliases for functions Where a function is defined in the current translation unit the alias call is replaced by a call to the function and the alias is emitted alongside the original name Where a function is not defined in the current translation unit the alias call is replaced by a call Copyright O 2007 2010 ARM Limited All rights reserved 4 29 Non Confidential Compiler specific Features to the real function Where a function is defined as static the function name is replaced by the alias name and the function is declared external if the alias name is declared external Note This function attribute is a GNU compiler extension that is supported by the ARM compiler Note Variables names might also be aliased using the corresponding variable attribute attribute alias Syntax return type newname argument list attribute alias oTdname Where oldname is the name of the function to be aliased newname is the new name of the aliased function Example include lt stdio h gt void foo void printf s n FUNCTION__ void bar void __attribute__ alias foo void gazonk void bar calls foo See also attribute
358. use of any information in this document or any error or omission in such information or any incorrect use of the product Where the term ARM is used it means ARM or any of its subsidiaries as appropriate Confidentiality Status This document is Non Confidential The right to use copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to Product Status The information in this document is final that is for a developed product Web Address http www arm com Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Contents RealView Compilation Tools Compiler Reference Guide Preface About this DOOK cet dtt toic te gift ftus vi Feedback teint e tede ea A ee eee x Chapter 1 Introduction 1 1 About the ARM compiler lt 1 2 1 2 Source language modes sss eene nni 1 3 1 8 Language extensions and language compliance 1 5 1 4 The C and C libraries ss 1 8 Chapter 2 Compiler Command line Options 2 1 Command line options 2 2 Chapter 3 Language Extensions 3 1 Preprocessor extensions lt lt
359. val __ NST1 32 d0 0 r0 vstlq lane u64 transfersize 1 uint64 t ptr uint64x2 t val VST1 64 d0 r0 vstlq lane s8 transfersize 1 int8 t ptr int8x16 t val __constrange 15 int lane NST1 8 d0 0 r0 vstlq lane s16 transfersize 1 intl6 t ptr intl6x8 t val constrange 0 7 int lane NST1 16 d 0 r0 vstlq lane s32 transfersize 1 int32 t ptr int32x4 t val constrange 0 3 int lane NST1 32 d0 0 r0 vstlq lane s64 transfersize 1 int64 t ptr int64x2 t val constrange 0 1 int lane NST1 64 d0 r0 vstlq lane f32 transfersize 1 float32 t ptr float32x4 t val __ NST1 32 d 0 r0 vstlq lane p8 transfersize 1 poly8 t ptr poly8x16 t val constrange 0 15 int lane NST1 8 d0 0 r0 vstlq_lane_p16 __transfersize 1 polyl6 t ptr poly16x8_t val __ NST1 16 d 0 r0 vstl lane u8 transfersize 1 uint8 t ptr uint8x8 t val __constrange 7 int lane NST1 8 d0 0 r0 vstl lane ul6 transfersize 1 uintl6 t ptr uintl6x4 t val __ NST1 16 d 0 r0 vstl lane u32 transfersize 1 uint32 t ptr uint32x2 t val __ NST1 32 d0 0 r0 vstl lane u64 transfersize 1 uint64 t ptr uint64x1l t val __ NST1 64 d0 r0 vstl lane s8 transfersize 1 int8 t ptr int8x8 t val __constrange 7 int lane NST1 8 d0 0 r0 vstl lane s16 transfersize 1 int16 t ptr intl6x4 t val __constr
360. variable Any type of the same size as the register being named can be used in the declaration of a named register variable The type can be a structure but note that bitfield layout is sensitive to endianness var name is the name of the named register variable reg is a character string denoting the name of a register on an ARM architecture based processor Registers available for use with named register variables on ARM architecture based processors are shown in Table 4 16 Table 4 16 Named registers available on ARM architecture based processors Register Character string for asm CPSR cpsr or apsr SPSR spsr r0 to r12 ro to r12 Copyright 2007 2010 ARM Limited All rights reserved 4 101 Non Confidential Compiler specific Features Table 4 16 Named registers available on ARM architecture based processors Register Character string for __asm r13 or sp r13 or sp r14 or Ir r14 or Ir r15 or pc r15 or pc On targets with a VFP the registers of Table 4 17 are also available for use with named register variables Table 4 17 Named registers available on targets with a VFP Register Character string for asm FPSID fpsid FPSCR fpscr FPEXC fpexc Example void foo void register int foo __asm rQ In this example foo is declared as a named register variable for the register r0 See also Named register variables on page 3 9 in the Compiler User Guide
361. vdup lane pl6 poly16x4 t vec float32x2_t vdup lane f32 float32x2 t vec vdupq lane u8 uint8x8 t vec vdupq lane ul6 uintl6x4 t vec y y gy lt gt y constrange 0 7 int lane constrange 0 3 int lane constrange 0 1 int lane constrange 0 7 int lane constrange 0 3 int lane constrange 0 1 int lane constrange 0 7 int lane constrange 0 3 int lane constrange 0 1 int lane constrange 0 7 int lane constrange 0 3 int lane Copyright O 2007 2010 ARM Limited All rights reserved Non Confidential Using NEON Support NDUP 8 00 00 0 NDUP 16 00 00 0 NDUP 32 00 00 0 NDUP 8 00 00 0 NDUP 16 00 00 0 NDUP 32 00 00 0 NDUP 8 00 00 0 NDUP 16 00 00 0 NDUP 32 00 00 0 NDUP 8 00 00 0 NDUP 16 q0 d0 0 E 43 Using NEON Support uint32x4 t int8x16 t intl6x8 t int32x4 t poly8x16 t polyl6x8 t SE float32x4 int64x1_t uint64x1_t int64x2_t uint64x2_t E 3 20 E 3 21 E 44 Combining vectors vdupq lane u32 uint32x2 t vec vdupq lane s8 int8x8 t vec vdupq lane s16 intl16x4 t vec vdupq lane s32 int32x2 t vec vdupq lane p8 poly8x8 t vec vdupq lane pl6 polyl16x4 t vec vdupq lane f32 float32x2 t vec vdup lane s64 int64x1l t vec vdup lane u64 uint64x1l t vec vdupq lane s64 int64x1l t vec vdupq lane u64 uint64x1l t vec constrange 0 1 int lane constrange 0 7 int lane
362. ve web site at http www roguewave com Support libraries The ARM C libraries provide additional components to enable support for C and to compile code for different architectures and processors The C and C libraries are provided as binaries only There is a variant of the 1990 ISO Standard C library for each combination of major build options such as the byte order of the target system whether interworking is selected and whether floating point support is selected See Chapter 2 The C and C Libraries in the Libraries Guide for more information 1 8 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Chapter 2 Compiler Command line Options This chapter lists the command line options accepted by the ARM compiler armcc It includes the following section Command line options on page 2 2 ARM DUI 0348A Copyright 2007 2010 ARM Limited All rights reserved 2 1 Non Confidential Compiler Command line Options 2 1 2 1 1 2 2 Command line options Aopt This section lists the command line options supported by the compiler in alphabetical order This option specifies command line options to pass to the assembler when it is invoked by the compiler to assemble either s input files or embedded assembly language functions Syntax Aopt Where opt is a command line option to pass to the assembler Note Some compiler command line options are passed to the
363. vec lane constrange 0 15 int VLD1 8 d0 0 rd intl6x8_t vldiq lane s16 transfersize 1 int16_t const ptr int16x8_t vec lane constrange 0 7 int NED1 16 d 0 r0 int32x4 t vldiq lane s32 transfersize 1 int32 t const ptr int32x4 t vec lane constrange 0 3 int NLD1 32 d0 0 3 r0 float32x4 t vldiq lane f32 transfersize 1 float32 t const ptr float32x4 t vec int lane constrange 0 3 NLD1 32 d0 0 re int64x2_t vldiq lane s64 transfersize 1 int64 t const ptr int64x2 t vec lane constrange 0 1 int VLD1 64 d0 r0 poly8x16 t vildiq lane p8 transfersize 1 poly8 t const ptr poly8x16 t vec lane constrange 0 15 int y VLD1 8 d0 0 3 r0 poly16x8 t vldiq lane pl6 transfersize 1 poly16 t const ptr polyl6x8 t vec int lane constrange 0 7 NED1 16 d 0 r0 uint8x8 t vldl lane u8 transfersize 1 uint8 t const ptr uint8x8 t vec lane constrange 0 7 int VLD1 8 100 0 r0 uint16x4_t vld1 lane u16 transfersize 1 uintl6 t const ptr uintl6x4 t vec lane constrange 0 3 int NLD1 16 d0 0 r0 uint32x2 t vldl lane u32 transfersize 1 uint32 t const ptr uint32x2 t vec lane constrange 0 1 int nos NLD1 32 d0 0 r0 uint64x1 t 1101 lane u64 transfersize 1 uint64 t const ptr uint64x1l t vec lane constrange 0 0 int NLD1 64 100 r0 in
364. x pragma arm section section_sort_list Where section_sort_list specifies an optional list of section names to be used for subsequent functions or objects Usage Use a scatter loading description file with the ARM linker to control how to place a named section at a particular address in memory Restrictions This option has no effect on Inline functions and their local static variables Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler specific Features e Template instantiations and their local static variables Elimination of unused variables and functions However using pragma arm section enables the linker to eliminate a function or variable that might otherwise be kept because it is in the same section as a used function or variable The order that definitions are written to the object file Example int x1 5 in data default int y1 100 in bss default int const z1 3 1 2 3 in constdata default pragma arm section rwdata foo rodata bar int x2 5 in foo data part of region int y2 100 in bss int const z2 3 1 2 3 in bar char 52 abc s2 in foo abc in conststring pragma arm section rodata int x3 5 in foo int y3 100 in bss int const z3 3 1 2 3 in constdata char 53 abc s3 in foo abc in conststring pragma arm section code foo int addl int x
365. x16 t b MMIN S8 q0 q0 q0 intl6x8 t vming_sl6 int16x8_t a intl6x8 t b MMIN S16 q0 q0 q0 int32x4 t vming_s32 int32x4_t a int32x4 t b MMIN S32 q0 q0 q0 uint8x16_t vminq u8 uint8x16 t a uint8x16 t b MMIN U8 q0 q0 q0 uintl6x8 t vming ul6 uintl6x8 t a uintl16x8 t b VMIN U16 q0 q0 q0 uint32x4 t vming_u32 uint32x4_t a uint32x4 t b VMIN U32 q0 q0 q0 float32x4 t vminq f32 float32x4 t a float32x4 t b VMIN F32 q0 q0 q0 E 3 7 Pairwise addition These intrinsics provide pairwise addition operations Pairwise add int8x8 t vpadd s8 int8x8 t a int8x8 t b NPADD I8 d0 d0 d0 intl6x4 t vpadd_s16 int16x4_t a intl6x4 t b NPADD I16 d0 d0 d0 int32x2 t vpadd s32 int32x2 t a int32x2 t b NPADD I32 00 00 0 uint8x8 t vpadd_u8 uint8x8_t a uint8x8 t b NPADD I8 d0 d0 d0 uintl6x4 t vpadd_u16 uint16x4_t a uintl6x4 t b VPADD I16 d0 d0 d0 uint32x2 t vpadd u32 uint32x2 t a uint32x2 t b VPADD I32 d0 d0 d0 float32x2 t vpadd f32 float32x2 t a float32x2 t b VPADD F32 d0 d0 d0 E 16 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Long pairwise add intl6x4 t int32x2 t int64x1_t uint16x4_t uint32x2_t uint64x1_t int16x8_t int32x4 t int64x2_t uint16x8_t uint32x4_t uint64x2_t 0200 s8 int8x8 t a NPADDL S8 d0 dO vpaddl s16 intl6x4 t a VPADDL S16 d0 d0 vpaddl s32 int32x2 t a NPADDL S32 d0 d0 vpaddl u8 uint8x8 t a
366. x16x2 t uintl6x8x2 t 20 s8 int8x8 t a int8x8 t b vuzp sl6 intl6x4 t a intl6x4 t b vuzp s32 int32x2 t a int32x2 t b vuzp_u8 uint8x8_t a uint8x8 t b 1 20 ul6 uintl6x4 t a uintl6x4 t b vuzp u32 uint32x2 t a uint32x2 t b vuzp f32 float32x2 t a float32x2 t b vuzp p8 poly8x8 t a poly8x8 t b vuzp pl6 poly16x4 t a polyl6x4 t b vuzpq s8 int8x16 t a int8x16 t b vuzpq_s16 int16x8_t a intl16x8 t b vuzpq s32 int32x4 t a int32x4 t b vuzpq u8 uint8x16 t a uint8x16 t b vuzpq ul6 uintl6x8 t a uintl6x8 t b Copyright 2007 2010 ARM Limited All rights reserved Non Confidential NTRN NTRN NTRN NTRN NTRN NTRN NTRN NTRN NTRN NTRN NTRN NTRN NTRN NZIP NZIP NZIP NZIP NZIP NZIP NZIP NZIP NZIP NZIP NZIP NZIP NZIP NZIP NZIP NZIP NUZP NUZP NUZP NUZP NUZP NUZP NUZP NUZP NUZP NUZP NUZP NUZP NUZP NUZP 32 00 00 32 00 00 8 00 00 16 00 00 8 q0 q0 16 q0 q0 32 q0 q0 8 q0 q0 16 q0 q0 32 q0 q0 32 q0 q0 8 q0 q0 16 q0 q0 8 d0 d0 16 d0 d0 8 d0 d0 16 d0 d0 32 d0 d0 8 d0 d0 16 d0 d0 8 q0 q0 16 q0 q0 32 q0 q0 8 q0 q0 16 q0 q0 32 q0 q0 32 q0 q0 8 q0 q0 16 q0 q0 8 00 00 16 d0 d0 32 00 00 8 00 00 16 00 00 32 00 00 32 00 00 8 00 00 16 00 00 8 q0 q0 16 q0 q0 32 q0 q0 8 q0
367. x2 t vqadd u32 uint32x2 t a uint32x2 t b VQADD U32 d0 d0 d0 uint64x1 t vqadd u64 uint64x1l t a uint64x1l t b VQADD U64 d0 d0 d0 int8x16 t vqaddq s8 int8x16 t a int8x16 t b VQADD S8 q0 q0 q0 intl6x8 t vqaddq sl6 intl6x8 t a intl6x8 t b VQADD S16 q0 q0 q0 int32x4 t vqaddq s32 int32x4 t a int32x4 t b VQADD S32 q0 q0 q0 int64x2 t vqaddq s64 int64x2 t a int64x2_t b X VQADD S64 q0 q0 q0 uint8x16 t vqaddq u8 uint8x16 t a uint8x16 t b VQADD U8 q0 q0 q0 uintl6x8 t vqaddq ul6 uintl6x8 t a uintl6x8 t b VQADD U16 q0 q0 q0 uint32x4 t vqaddq u32 uint32x4 t a uint32x4 t b VQADD U32 q0 q0 q0 uint64x2 t vqaddq u64 uint64x2 t a uint64x2 t b VQADD U64 q0 q0 q0 E 6 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential E 3 2 int8x8 t intl6x4 t int32x2 t uint8x8 t ARM DUI 0348A Vector add high half gt Vr i Va i Vb i int8x8 t intl6x4 t int32x2 t uint8x8 t uintl6x4 t uint32x2 t vaddhn_s16 int16x8_t a intl16x8 t b vaddhn s32 int32x4 t a int32x4 t b vaddhn s64 int64x2 t a int64x2 t b vaddhn ul6 uintl6x8 t a vaddhn u32 uint32x4 t a vaddhn u64 uint64x2 t a Vector rounding add high half int8x8 t intl6x4 t int32x2 t uint8x8 t uintl6x4 t uint32x2 t Multiplication vraddhn s16 int16x8 t a vraddhn s32 int32x4 t a vraddhn s64 int64x2 t a int16x8 t b int32x4 t b int64x2 t b These intrinsics provide opera
368. x2_t vld2_p16 __transfersize 8 poly16 t const ptr NLD2 16 100 d1 r0 uint8x16x3 t vld3q_u8 __transfersize 48 uint8 t const ptr VLD3 8 100 02 d4 r0 uintl6x8x3 t vld3q_u16 __transfersize 24 uintl6 t const ptr VLD3 16 100 02 d4 r0 uint32x4x3_t vld3q_u32 __transfersize 12 uint32 t const ptr E 30 Copyright O 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential NED3 32 100 02 d4 r0 int8x16x3 t vld3q_s8 __transfersize 48 int8 t const ptr VLD3 8 100 02 d4 r0 intl6x8x3 vld3q_s16 __transfersize 24 intl16 t const ptr VLD3 16 100 02 d4 r0 int32x4x3 v1d3q s32 transfersize 12 int32 t const ptr VLD3 32 100 02 d4 r0 float32x4x3_t vld3q f32 transfersize 12 float32 t const ptr poly8x16x3 t poly16x8x3_t VLD3 32 100 02 d4 r0 v1d3q p8 transfersize 48 poly8_t const ptr VLD3 8 100 02 d4 r0 vld3q_p16 __transfersize 24 polyl6 t const ptr VLD3 16 d d2 d4 r0 uint8x8x3 t v1d3 u8 transfersize 24 uint8 t const ptr uintl6x4x3 t uint32x2x3 t uint64x1x3 t VLD3 8 100 01 02 r0 103 u16 transfersize 12 uint16 t const ptr NED3 16 100 01 d2 r0 v1d3 u32 transfersize 6 uint32 t const ptr NED3 32 100 01 d2 r0 v1d3 u64 transfersize 3 uint64 t const ptr VLD1 64 100 01 d2 r0 int8x8x3 t vld3_s8
369. x8 t vqshl n s8 int8x8 t a __ intl6x4 t vgshl n sl16 intl6x4 t a int32x2 t vgshl n s32 int32xX2 t a int64x1l t vgshl n se4 int64xl t a uint8x8 t vqshl n u8 uint8x8 t a __ uintl6x4 t vqshl ul6 uintl6x4 t a uint32x2 t vqshl n u32 uint32x2 t a uint64x1l t vqshl n u64 uint64x1 t a int8x16 t vgshlg n s8 int8x16 t a __ intl6x8 t vashlq_n_s16 int16x8_t a int32x4 t vgshlq n s32 int32x4 t a int64x2 t vgshlq n s64 int64x2 t a uint8x16 t vqshlq n u8 uint8x16 t a __ uint16x8 t vqshlq n ul6 uintl6x8 t a uint32x4 t vqshlq n u32 uint32x4 t a uint64x2 t vqshlq n u64 uint64x2 t a constrange 0 7 int b VQSHL S8 00 00 0 constrange 0 15 int b VQSHL S16 00 00 0 constrange 0 31 int b VQSHL S32 00 00 0 constrange 0 63 int b VQSHL S64 dQ d0 0 constrange 0 7 int b VQSHL U8 00 00 0 constrange 0 15 int b VQSHL U16 00 00 0 constrange 0 31 int b VQSHL U32 00 00 0 constrange 0 63 int b VQSHL U64 00 00 0 constrange 0 7 int b VQSHL S8 qQ q0 0 constrange 0 15 int b VQSHL S16 qQ q0 0 constrange 0 31 int b VQSHL S32 qQ q0 0 constrange 0 63 int b VQSHL S64 qQ q0 0 constrange 0 7 int b VQSHL U8 q0 q0 40 constrange 0 15 int b VQSHL U16 q0 q0 40 constrange 0 31 int b VQSHL U32 q0 q0 40 constrange 0 63 int b VQSHL U64 q0 q0 40 Vector signed gt unsigned saturating shift left by constant uint8x8 t vashlu_n_s8 int8x8_t a __ uintl
370. x8 t vshrq n ul6 uintl6x8 t a uint32x4 t vshrq n u32 uint32x4 t a uint64x2 t vshrq n u64 uint64x2 t a constrange 1 8 int b NSHR S8 d0 d0 8 constrange 1 16 int b VSHR S16 00 00 16 constrange 1 32 int b VSHR S32 d0 d0 232 constrange 1 64 int b VSHR S64 dQ d0 64 constrange 1 8 int b NSHR U8 00 00 8 constrange 1 16 int b VSHR U16 00 00 16 constrange 1 32 int b VSHR U32 00 00 32 constrange 1 64 int b VSHR U64 dQ d0 64 constrange 1 8 int b VSHR S8 amp qQ q0 8 constrange 1 16 int b VSHR S16 q0 q0 16 constrange 1 32 int b VSHR S32 q0 q0 432 constrange 1 64 int b VSHR S64 q0 q0 464 constrange 1 8 int b VSHR U8 q0 q0 48 constrange 1 16 int b VSHR U16 q0 q0 16 constrange 1 32 int b VSHR U32 00 90 32 constrange 1 64 int b VSHR U64 00 0 64 Vector shift left by constant int8x8 t vshl n s8 int8x8 t a __ intlox4 t vshl_n_s16 int16x4_t a int32x2 t vshl n s32 int32x2t a int64xl t vshl n se4 int64xl t a uint8x8 t vshl n u8 uint8x8 t a __ uintl6x4 t vshl n ul6 uintl6x4 t a uint32x2 t vshl n u32 uint32x2 t a uint64x1l t vshl n u64 uint64x1l t a int8x16 t vshlg n s8 int8x16 t a __ intl6x8 t vshlg n sl6 intl16x8 t a int32xX4 t vshlg n s32 int32x4 t a int64x2 t vshlg n se4 int64x2 t a uint8x16 t vshlq n u8 uint8x16 t a __ uintl6x8 t vshlq n ul6 uintl6x8 t a uint32x4 t vshlq n u32 uint32x4 t a uint64x2 t vshlq n u64
371. y the fpmode ieee full option FP IEEE When you specify the fpmode ieee full fpmode ieee_fixed or fpmode ieee_no_fenv options FP INEXACT EXCEPTION When you specify the fpmode ieee_full option __GNUC__ ver When you specify the gnu option It is an integer that shows the current major version of the GNU mode being used __GNUC_MINOR__ ver When you specify the gnu option It is an integer that shows the current minor version of the GNU mode being used GNUG ver In GNU mode when you specify the cpp option It has the same value as __GNUC__ IMPLICIT INCLUDE When you specify the implicit include option INTMAX TYPE In GNU mode It defines the correct underlying type for the intmax_t typedef LINE num Always set It is the source line number of the line of code containing this macro 4 104 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler specific Features Table 4 18 Predefined macros continued Name Value When defined MODULE mod Contains the filename part of the value of __FILE__ NO INLINE When you specify the no inline option in GNU mode OPTIMISE LEVEL num Always set to 2 by default unless you change the optimization level using the Onum option OPTIMISE SPACE gt When you specify the Ospace option OPTIMISE TIME Wh
372. y the compiler It enables you to load data from memory in your C or C code using an LDREX instruction Syntax unsigned int __Idrex volatile void ptr Where ptr Points to the address of the data to be loaded from memory To specify the size of the data to be loaded cast the parameter to an appropriate integral type Table 4 8 Access widths supported by the __Idrex intrinsic Instruction Size of data loaded C cast LDREXB unsigned byte char LDREXH unsigned halfword short int LDREX word int Return value The __1drex intrinsic returns the data loaded from the memory address pointed to by ptr Errors The compiler does not recognize the __1drex intrinsic when compiling for a target that does not support the LDREX instruction The compiler generates either a warning or an error in this case Copyright O 2007 2010 ARM Limited All rights reserved 4 75 Non Confidential Compiler specific Features The __1drex intrinsic does not support access to doubleword data The compiler generates an error if you specify an access width that is not supported Example int foo void int loc Oxff return __ldrex volatile char loc Compiling this code with the command line option cpu 6k produces foo PROC MOV r0 0xff LDREXB r0 r0 BX Ir ENDP See also __strex on page 4 89 LDREX and STREX on page 4 35 in the Assembler Guide 4 7 21 __1drt This intrinsic inserts an assembly language in
373. yntax follows GNU syntax for variadic macros Example define debug format fprintf stderr format VA ARGS void variadic macros void debug a test string is printed out along with x x x n 12 14 20 See also gnu on page 2 44 Copyright 2007 2010 ARM Limited All rights reserved 3 7 Non Confidential Language Extensions 3 3 2 3 3 3 3 8 long long restrict New features of C99 on page 1 5 in the Compiler User Guide The ARM compiler supports 64 bit integer types through the type specifiers long long and unsigned long long They behave analogously to long and unsigned long with respect to the usual arithmetic conversions __int64 is a synonym for long long Integer constants can have an 11 suffix to force the type of the constant to long long if it fits or to unsigned long long if it does not fit a ull or 11u suffix to force the type of the constant to unsigned long long Format specifiers for printf and scanf can include 11 to specify that the following conversion applies to a long long argument as7 in 11d or 11u Also a plain integer constant is of type long long or unsigned long long if its value is large enough There is a warning message from the compiler indicating the change For example in strict 1990 ISO Standard C 2147483648 has type unsigned long In ARM C and C it has the type long long One consequence of this is the value of an expression such as
374. you specify in Jang country or Tang country codepage Syntax message locale 7ang country codepage Where lang country codepage is the new default language for the display of error and warning messages The permitted languages are independent of the host platform The following settings are supported en US zh CN ko KR ja_JP Default If you do not specify message_locale the compiler assumes message_locale en_US Restrictions Ensure that you have installed the appropriate locale support for the host platform The locale name might be case sensitive depending on the host platform The ability to specify a codepage and its meaning depends on the host platform Errors If you specify a setting that is not supported the compiler generates an error message Example To display messages in Japanese use Copyright 2007 2010 ARM Limited All rights reserved 2 61 Non Confidential Compiler Command line Options 2 1 82 2 1 83 2 62 message locale ja JP See also locale lang_country on page 2 57 no multibyte chars min array alignmentzopt This option enables you to specify the minimum alignment of arrays Syntax min array alignment opt Where opt specifies the minimum alignment of arrays The value of opt is 1 byte alignment or unaligned 2 two byte halfword alignment 4 four byte word alignment 8 eight byte doubleword alignment Default If
375. ze at the expense of a possible increase in execution time See also pragma Otime Ospace on page 2 68 4 6 17 pragma Otime This pragma instructs the compiler to perform optimizations to reduce execution time at the expense of a possible increase in image size See also pragma Ospace Otime on page 2 69 4 6 18 pragma pop This pragma restores the previously saved pragma state See also pragma push 4 6 19 pragma push This pragma saves the current pragma state See also pragma pop 4 58 Copyright 2007 2010 ARM Limited All rights reserved ARM DUI 0348A Non Confidential Compiler specific Features 4 6 20 pragma no softfp linkage This pragma controls software floating point linkage pragma softfp linkage asserts that all function declarations up to the next pragma no softfp linkage describe functions that use software floating point linkage Note This pragma has the keyword equivalent __softfp Usage This pragma can be useful when applied to an entire interface specification located in the header file without altering that file Default The default is pragma no_softfp_linkage See also __softfp on page 4 15 Floating point linkage on page 4 33 in the Compiler User Guide 4 6 21 pragma unroll n ARM DUI 0348A This pragma instructs the compiler to unroll a loop by n interations Note Both vectorized and non vectorized loops can be un

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