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R&S RTO-K26 D-PHY Compliance Test

1. 9f e Test 1 2 5 Clock Lane LP TX Slew Rate vs C oap OV Otsg 39 3 4 3 1 Test 1 2 1 Clock Lane LP TX Thevenin Output High Level Voltage Voi The purpose of this test case is to verify that the Thevenin Output High Level Voltage Vou of the DUT s clock lane LP transmitter is within the conformance limits The con formance range for V au is between 1 1 and 1 3 Volts Von is measured as the mode of all waveform samples that are greater than 50 of the absolute peak to peak Vpp and Vpn signal amplitudes and across all LP 1 states in a single LP Escape Mode sequence A ULPS Entry sequence is specified for this test The measurement is performed sepa rately on both Vpp and Von clock lane waveforms An example is shown in figure 3 12 2014 09 09 18 35 36 Horizontal settings Res 100 ps 10 GSa s Rec len 50 008 kSa Scl 500 08 ns div Position 0 s Trigger Morma A imeout Gn Fig 3 12 Typical result of a clock lane LP TX Thevenin output High Level and Low Level voltage measurement 3 4 3 2 3 4 3 3 Clock Lane LP TX Signaling Requirements Group 2 Test 1 2 2 Clock Lane LP TX Thevenin Output Low Level Voltage VoL The purpose of this test case is to verify that the Thevenin Output Low Level Voltage VoL of the DUT s clock lane LP transmitter is within the conformance limits The con formance range for Vo is between 50 and 50 mV Vo is mea
2. Any D PHY configuration consists of at least one clock lane module and one or sev eral data lane modules Each module provides a synchronized connection between master and slave During normal operation a lane switches between the modes low power LP and high speed HS High speed functions are used for HS data trans mission in bursts with an arbitrary number of payload data bytes Low power functions are mainly used for control but have other optional use cases like LP escape mode The presence of HS and LP functions is correlated e Starting D PHY Compliance Tests eee eee 17 e Test Configuration for DTTV sep ee eee 18 e Data Lane LP TX Signaling Requirements Group Tle eee eee ee eee 21 e Clock Lane LP TX Signaling Requirements Group 21 eee eee eee e eee 31 e Data Lane HS TX Signaling Requirements Group 3 arrrranrnnnnnnnnnnrvnnnennnnrnnnnenn 40 e Clock Lane HS TX Signaling Requirements Group 4 e 62 e HS TX Clock to Data Lane Timing Requirements Group 5 88 Starting D PHY Compliance Tests 3 1 Starting D PHY Compliance Tests Before you run the test complete the following actions Initial setup of the equipment see chapter 1 2 Installing Software and License on page 5 LAN connection of the oscilloscope and the computer running the R amp S Scope Suite see chapter 1 5 Connecting the R amp S RTO on page 7 Select D PHY in
3. T CLK TRAIL Fig 3 53 Typical result of an CLK TRAIL state duration measurement Clkp Waveform of Clock Vpp Clkn Waveform of Clock Vpn Clkd Differential waveform Vpp Von T CLK TRAIL Duration of the CLK TRAIL state immediately after a clock lane HS transmission This test case is tested for Zip 100 ohms only and for all clock lanes Test 1 4 14 Clock Lane HS Exit 30 85 Post EoT Rise Time Tagor The purpose of this test case is to verify that the 3096 8596 post EoT rise time T sor is not more than 35 ns To compute the 3096 8596 Post EoT Rise Time Tgagor the software measures the rise time starting at the end of the CLK TRAIL state and ending at the time when the Vpp rising edge crosses above the minimum logic 1 input voltage Vi mn 880 mV 3 6 3 15 Clock Lane HS TX Signaling Requirements Group 4 Amplitude V Time ns Che LEM CE 05 T REOT Fig 3 54 Typical result of a 3026 8576 post EoT rise time measurement Clkp Waveform of Clock Vpp Clkn Waveform of Clock Vpn Clkd Differential waveform Vpp Vpn T REOT Duration of the 30 85 post EoT rise time This test case is tested for Zip 100 ohms only and for all clock lanes Test 1 4 15 Clock Lane HS Exit Ttor Value The purpose of this test case is to verify that the combined value of Tey k TraL and Treot Is not more than 105 ns 12 UI The software computes the combined value of To tray
4. In the measurement of the duration Tys gt s tray of this state the software distinguishes two cases e lf the last bit in the HS PAYLOAD is a 0 then the HS TRAIL state is a differen tial 1 state The start of the state is defined at the time when the differential waveform crosses above the maximum differential input high threshold Vipt 70 mV The end of the state is defined at the time when the differential waveform crosses below the maximum differential input high threshold Vipru 70 mV e If the last bit in the HS PAYLOAD is a 1 then the HS TRAIL state is a differen tial O state The start of the state is defined at the time when the differential waveform crosses below the minimum differential input low threshold Vin 70 mV The end of the state is defined at the time when the differential waveform crosses above the minimum differential input low threshold Vipt 70 mV Amplitude V Time ns Datp Datn Datd T HS TRAIL Fig 3 33 Typical result of an HS TRAIL state duration measurement This figure shows a failure case T HS TRAIL lt 60 ns 4 Ul 3 5 3 14 Data Lane HS TX Signaling Requirements Group 3 Datp Waveform of Data Vpp Datn Waveform of Data Vpn Datd Differential waveform Vpp Von T_HS TRAIL Duration of the HS TRAIL state immediately after an HS transmission This test case is tested for Zip 100 ohms only and
5. lt V Size 480 pixels gt co Q N RO h Cn e ol e Cn e e e e e e e S 50 100 150 200 250 300 Line Width 320 pixels gt Fig 3 19 Example reference HS test pattern RGB888 format courtesy MIPI Alliance D PHY specs Settings in the HS Configuration dialog box See also chapter 3 2 Test Configuration for D PHY on page 18 e Data Lane Under Test If the DUT implements multiple data lanes select which pair of data lanes is to be tested e Zp If Zp is 100 ohms the pair of data lanes under test dat and dat and the pair of clock lanes clk and cika have to be terminated with the 100 ohms loads on the RTB The data signal two probes single ended or differential in single ended mode and the clock signal either two single ended or one differential probe are captured by the RTO and processed by the software If Zp is 80 or 125 ohms the pair of data lanes under test have to be terminated with the 80 or 125 ohms loads on the RTB whereas the pair of clock lanes have to be terminated with the 100 ohms loads on the RTB Only the data sig nal two probes single ended or differential in single ended mode is captured by the RTO The clock signal is recovered from the data signal by the software e Clock Format Data Lane HS TX Signaling Requirements Group 3 This setting depends on the probes that are used to capture the clock signals see also the explanations above at Zip
6. Select the clock format Single Ended when using two single ended probes or two differential probes in single ended mode Select the clock format Differential when using one differential probe 3 5 2 Performing Group 3 Test Cases 1 Start running the tests as described in chapter 3 1 Starting D PHY Compliance Tests on page 17 2 Select Data Lane HS TX Signaling Requirements Group 3 d RSScopeSuite Select Test Case mm D PHY Test lul an Data Lane LP TX Signaling Requirements Group 1 Clock Lane LP TX Signaling Requirements Group 2 4 Data Lane HS TX Signaling Requirements Group 3 Data Lane HS Entry T LPX Value 1 3 1 Data Lane HS Entry T HS PREPARE Value 1 3 2 Data Lane HS Entry T HS PREPARE T HS ZERO Value 1 3 3 Start Return To Main Menu 3 Click Start 4 The Test Cycle dialog box shows the status of the test cases included in the test cycle and marks the next case to be done see chapter 2 2 Controlling Test Cycles on page 12 Click Run This group of tests uses the MIPI D PHY Reference Termination Board RTB test fixture from the UNH IOL 5 Follow the instructions of the step by step guide Group 3 of test cases requires 2 setup steps The data and clock signals can be tapped either on the DUT or RTB or even on the SMA cables between the DUT and the RTB 3 5 3 3 5 3 1 Data Lane HS TX Signaling Requirements Group 3 The connections may diffe
7. Taxsermg Ff Toux TERM EN VIH min os ML mar pp NET XIOODOQDUGLEHLEP NN LBEBHOQOOOdIOOOQDQ Data Lane Disconnect T T Dp Dn Terminator pia mS VIH min H K 3 poaa ED oe p l THS SKIF Tp renmen THs sETTLE Fig 3 38 A typical MIPI D PHY HS clock burst waveform courtesy of MIPI Alliance Specification for D PHY version 1 1 The software requires at least one set of complete clock burst waveforms for correct processing to perform the test successfully HS Clock Transmission Requirements More than half of the Group 4 test cases are analyzing the clock signal in HS clock transmission Therefore it is important for the CLK Toggling HS 0 HS 1 to contain at least e a 128 occurrences of 01 e b 128 occurrences of 10 If the CLK Toggling HS 0 HS 1 does not meet these minimum requirements the soft ware does still process the waveforms but the measurements may not be accurate and test results may be invalid Clock Lane HS TX Signaling Requirements Group 4 It is recommended to use reference HS test patterns or images UNH IOL has created a PATGUI utility which can be used to generate test patterns and images for various resolutions and formats For members of the MIPI Alliance this utility can be obtained free of charge from the MIPI Testing Resources page on the MIPI Alliance website https members mipi org mipi testing workspace Test Vehicle Board Resources Unpacked Pay
8. figuration settings described below e LP Configuration for DUT lanes in low power LP mode e HS Configuration for DUT lanes in high speed HS mode Configuration LP Configuration HS Configuration Report Configuration Test Mode Test Setup amp Allow Skip Repeat Data Lane Under Test Do Not Allow Skip Repeat C LOAD 50 pF Use Previous Settings Debugging Option Low Pass Filter Export Waveform Cancel Fig 3 1 LP Configuration for D PHY compliance test cases Groups 1 and 2 Select the LP Configuration tab for Group 1 and 2 test cases configuration of e Test Mode e Data Lane Under Test eo CL op e Use Previous Settings e Low Pass Filter e Export Waveform Test Configuration for D PHY Configuration LP Configuration HS Configuration Report Configuration Test Mode Test Setup amp Allow Skip Repeat Data Lane Under Test Do Not Allow Skip Repeat 7 ID 100 ohms DUT Clock Format Single Ended lt Camera Display Use Previous Settings Bitrate Mbps EGGE Debugging Option aloes TEs Export Waveform Cancel Fig 3 2 HS Configuration for D PHY compliance test cases Groups 3 4 and 5 Select the HS Configuration tab for Group 3 4 and 5 test cases configuration of e Test Mode e Data Lane Under Test e Ap e Clock Format e Use Previous Settings DUT e Bitrate e Clock Type e Export Waveform Some fields are shared
9. on page 18 e Data Lane Under Test If the DUT implements multiple data lanes select which pair of data lanes is to be tested C oap Requirements Select C gAp to be 50 pF which is also the default selection Most of the Group 1 tests require a 50 pF C oap test fixture which is practically used as maximum capacitive load Some other tests are independent of termina Test Procedures 1326 1010 02 02 22 Data Lane LP TX Signaling Requirements Group 1 tion capacitance For procedural consistency all tests are performed using a 50 pF Ci oap test fixture e Low Pass Filter Enable the Low Pass Filter For details regarding this filter see chapter 3 2 Test Configuration for D PHY on page 18 3 3 2 Performing Group 1 Test Cases 1 Start the test as described in chapter 3 1 Starting D PHY Compliance Tests on page 17 2 Select the test case group Data Lane LP TX Signaling Requirements Group 1 D PHY Test 19 n 4 Data Lane LP TX Signaling Requirements Group 1 Data Lane LP TX Thevenin Output High Level Voltage V OH 1 1 Data Lane LP TX Thevenin Output Low Level Voltage V OL 1 1 2 Data Lane LP TX 1526 8596 Rise Time T RLP 1 1 3 Data Lane LP TX 8576 1556 Fall Time T FLP 1 1 4 Data Lane LP TX Slew Rate vs C LOAD d V d T SR 1 1 5 Return To Main Menu 3 Click Start 4 The Test Cycle dialog box shows the status of the test cases included in the test cycle and marks the nex
10. Datp Waveform of Data Vpp Datn Waveform of Data Vpn Datd Differential waveform Vpp Vpn T EOT T HS TRAIL T REOT This test case is tested for Zip 100 ohms only and for all data lanes Test 1 3 16 Data Lane HS Exit Tus gi Value The purpose of this test case is to verify that the duration of the LP 11 state that occurs immediately after an HS transmission is at least 100 ns The software measures Tys x 7 the duration of the last LP 11 state that occurs imme diately after an HS transmission as follows 3 6 Clock Lane HS TX Signaling Requirements Group 4 The state is measured starting at the end of the HS TRAIL state and ending at the time when the Vpp falling edge crosses below the maximum logic 0 input voltage VIL Max 950 mV For the end of the HS TRAIL state two cases have to be distin guished e f HS TRAIL is a differential 1 state the end of the state will be defined at the time when the differential waveform crosses below the minimum differential input low threshold Vip 70 mV e f HS TRAIL is a differential O state the end of the state will be defined at the time when the differential waveform crosses above the maximum differential input high threshold Vipty 70 mV Amplitude V Time ns Datp Datn T HS EXIT Fig 3 36 Typical result of a measurement of the duration of the LP 11 state immediately after an HS transmission Datp Waveform o
11. Group 2 Clock Lane LP TX Thevenin Output High Level Voltage V OH 1 Clock Lane LP TX Thevenin Output Low Level Voltage V OL 1 2 Clock Lane LP TX 15 85 Rise Time T RLP 1 2 3 Clock Lane LP TX 85 15 Fall Time T FLP 1 2 4 V T Return To Main Menu 3 Click Start 4 The Test Cycle dialog box shows the status of the test cases included in the test cycle and marks the next case to be done see chapter 2 2 Controlling Test Cycles on page 12 Click Run This group of tests uses the MIPI D PHY Capacitive Load C oap test fixture from the UNH IOL The C oap fixture provides 50 pF capacitive load Follow the instructions of the step by step guide Group 2 of test cases requires 5 setup steps The clock signals can be tapped on the DUT or the C oap or even the SMA cables between the DUT and the C oap The Group 2 test cases do not require data sig nals When you have finished all steps the compliance test runs automatically Further steps chapter 2 3 Getting Test Results on page 13 Clock Lane LP TX Signaling Requirements Group 2 3 4 3 Measurements e Test 1 2 1 Clock Lane LP TX Thevenin Output High Level Voltage Vou 34 e Test 1 2 2 Clock Lane LP TX Thevenin Output Low Level Voltage Vo 9D e Test 1 2 3 Clock Lane LP TX 1596 8596 Rise Time Tgip 35 e Test 1 2 4 Clock Lane LP TX 85 15 Fall Time Tg p
12. ence waveforms to a common anchor point which is the zero crossing time of the first transition The value of Vouus pp is then determined from that average waveform it is the mean of all voltage amplitude samples that fall between the centers of the fourth and fifth 1 bit in the 011111 data pattern Amplitude V Time ns OE m V OHHS DP Fig 3 25 Typical result of a D HS single ended output high voltage measurement V_OHHS High speed output high voltage DP Data positive D 3 5 3 7 Data Lane HS TX Signaling Requirements Group 3 Vonnsion The software measures the Dy HS output high voltage in a similar way as VoHHs pp One exception is e It searches for reference waveforms with the data pattern 100000 instead of 011111 because 100000 on the differential signal corresponds with 011111 on the Dy single ended signal Amplitude V Time ns OMG ee V OHHS DN Fig 3 26 Typical result of a D HS single ended output high voltage measurement V OHHS High speed output high voltage DN Data negative D This test case is executed for all three cases of Zn 100 ohms 80 ohms and 125 ohms as well as for all data lanes Test 1 3 7 Data Lane HS TX Static Common Mode Voltages Vcyrx and Vomrxo The purpose of this test case is to verify that the HS transmit static common mode vol tages Vemrxa and Voyrx o are between 150 mV and 250 mV The HS
13. 400 Time ns Clkp Cln Clkd T CLK PREPARE Fig 3 41 Typical result of a clock lane T LPX measurement CIkp Waveform of Clock Vpp Clkn Waveform of Clock Vpn Clkd Differential waveform Vpp Von T CLK PREPARE Duration of last LP 00 state immediately before HS transmission This test case is tested for Zip 100 ohms only and for all clock lanes Test 1 4 3 Clock Lane HS Entry Tc x prepare T Tcuk zero Value The purpose of this test case is to verify that the combined value of Te k prepare and the duration prior to the clock transmission To k zero IS at least 300 ns The duration is measured e starting at the time when the differential waveform crosses below the minimum dif ferential input low threshold Vipt 70 mV and e ending at the Tc k zero HS differential state The software then computes the combined value of Tc k prepare See chapter 3 6 3 2 Test 1 4 2 Clock Lane HS Entry Te k prepare Value on page 69 and Tei kzeno 3 6 3 4 Clock Lane HS TX Signaling Requirements Group 4 2 i T_CLK PREPARE 52 6 ns T CLK ZERD 313 03 ns Amplitude V x 100 200 300 400 Time ns Che LEM CE 0n T CLK PREPARE T CLK ZERO Fig 3 42 Typical result of a clock lane T CLK PREPARE T CLK ZERO measurement Clikp Waveform of Clock Vpp Clkn Waveform of Clock Vpn Clkd Differential waveform Vpp Vpn T CLK PREPARE Duration
14. 8 order Butterworth bandpass fil ter with cutoff frequencies of 50 MHz and 450 MHz respectively The value of AVcwrx Lr Is measured as the absolute peak voltage at the output of the bandpass fil ter Amplitude V Time us V CMTX LF V CMTX LF PEAK Fig 3 49 Typical result of a clock lane HS transmit dynamic common level variations measurement at low frequencies V CMTX LF This test case is tested for Zip 100 ohms only and for all clock lanes 3 6 3 10 Test 1 4 10 Clock Lane HS TX Dynamic Common Level Variations Above 450 MHz AV cwrx ur The purpose of this test case is to verify that the common level variation above 450 MHz is not more than 15 mV pus The common level variation above 450 MHz AV wrie is measured as follows The software uses the same list of HS transmit static common voltage voltages from chapter 3 6 3 9 Test 1 4 9 gap Lane HS TX Dynamic Common Level Variations Between 50 450 MHz AVcwurxury on page 78 as the input to an 8 order Butterworth Test Procedures 1326 1010 02 02 79 3 6 3 11 Clock Lane HS TX Signaling Requirements Group 4 highpass filter with a cutoff frequency of 450 MHz The value of AVowtxHF is measured as the RMS voltage at the output of the highpass filter V_CMTX HF 8 64 mV_RMS Amplitude V 5 10 15 20 Time us V CMTX HF V CMTX HF RMS Fig 3 50 Typical result of a clock lane HS transmit dynamic common le
15. Data Lane HS Exit Tus gx Value Test Groups and Tests Group 4 18 tests Clock Lane HS TX Signaling Requirements 1 4 1 Clock Lane HS Entry T px Value 1 4 2 Clock Lane HS Entry Teyk prepare Value 1 4 3 Clock Lane HS Entry Tork prepare Touk zero Value 1 4 4 Clock Lane HS TX Differential Voltages Vop and Vop 1 1 4 5 Clock Lane HS TX Differential Voltage Mismatch AVop 1 4 6 Clock Lane HS TX Single Ended Output Voltages VoyHsyop and VonHsyon 1 4 7 Clock Lane HS TX Static Common Mode Voltages Vcyrx and Voyrxqo 1 4 8 Clock Lane HS TX Static Common Mode Voltage Mismatch AVcyrx o 1 4 9 Clock Lane HS TX Dynamic Common Level Variations Between 50 450 MHz AVemtx LF 1 4 10 Clock Lane HS TX Dynamic Common Level Variations Above 450 MHz AV wrur 1 4 11 Clock Lane HS TX 2096 8096 Rise Time tg 1 4 12 Clock Lane HS TX 8096 2096 Fall Time tr 1 4 13 Clock Lane HS Exit Tc 1g Value 1 4 14 Clock Lane HS Exit 3096 8596 Post EoT Rise Time Treor 1 4 15 Clock Lane HS Exit Tror Value 1 4 16 Clock Lane HS Exit Tis exir Value 1 4 17 Clock Lane HS Clock Instantaneous Ulingr Value 1 4 18 Clock Lane HS Clock Delta Ul AUI Value Group 5 4 tests HS TX Clock to Data Lane Timing Requirements 1 5 1 HS Entry Tei ege Value 1 5 2 HS Exit Tc pog1 Value 1 5 3 HS Clock Rising Edge Alignment to First Payload Bit 1 5 4 Data to Clock Skew Tskewprx
16. LP 11 LP 11 LP 01 LP 00 T T 1 EOT D 1 HS SETTLE Tus TRAIL Tus Exr Fig 3 18 A typical MIPI D PHY HS data burst waveform courtesy of MIPI Alliance Specification for D PHY version 1 1 The software requires at least one set of complete data burst waveforms for correct processing to perform the test successfully Payload Requirements More than half of the Group 3 test cases are analyzing the data in the HS transmission Therefore it is important for the HS PAYLOAD to contain at least e a 5000 occurrences of 1 e b 5000 occurrences of 0 e c 128 occurrences of 100000 e d 128 occurrences of 0111111 e 6 128 occurrences of 111000 e f 128 occurrences of 000111 If the HS PAYLOAD does not meet these minimum requirements the software does still process the waveforms but the measurements may not be accurate and the test results may be invalid Data Lane HS TX Signaling Requirements Group 3 It is recommended to use reference HS test patterns or images UNH IOL has created a PATGUI utility which can be used to generate test patterns and images for various resolutions and formats For members of the MIPI Alliance this utility can be obtained free of charge from the MIPI Testing Resources page on the MIPI Alliance website https members mipi org mipi testing workspace Test_Vehicle_Board_Resources Unpacked Payload Image 24 bpp 8 8 8 RGB
17. LP TX 8546 1595 fall time and slew rate measurement for V DP Clock Lane LP TX Signaling Requirements Group 2 VDN LP 85 15 Fall Time and Slew Rate First Fall Edge 1 2 6 Amplitude V 4 e 0 2 0 2 Time ns VDN Signal VDN VOL Slew Rate High Limit High Threshold Time Start Time End panis VDN VOH SlewRate Slew Rate Low Limit Low Threshold Fig 3 16 Typical result of a clock lane LP TX 85 15 fall time and slew rate measurement for V_DN 3 4 3 5 Test 1 2 5 Clock Lane LP TX Slew Rate vs C gAp OV tsp The purpose of this test case is to verify the slew rate OV tsg of the DUT s clock lane LP transmitter is within the conformance limits for specific capacitive loading condi tions Various conformance ranges apply as detailed below The slew rate is computed and measured independently for each edge of the Vpp and Vpn Signals using a 50 mV vertical window The slew rate curve is computed for a sin gle edge using the sliding window technique For falling edges 1 The final averaged maximum V dtgr result is computed over the entire vertical edge region The conformance range is less than 150 V us 2 The final averaged minimum V tag result is computed over the 400 930 mV region The conformance range is greater than 30 V us For rising edges 1 The final averaged maximum V dtgr result is computed over the entire vertical ed
18. LP TX Signaling Requirements Group 2 LP 15 85 Rise Time and Slew Rate First Rise Edge Amplitude V Time ns Signal VOL Slew Rate High Limit High Threshold Time Start Time End sasas VOH SlewRate Slew Rate Low Limit Low Threshold Fig 3 14 Typical result of a clock lane LP TX 15 85 rise time and slew rate measurement for V_DN Test 1 2 4 Clock Lane LP TX 85 15 Fall Time To p The purpose of this test case is to verify the 8596 1596 Fall Time Tg p of the DUT s clock lane LP transmitter is within the conformance limits The conformance range for Tryp IS less than 25 ns Using the measured Vau and Vo LP TX Thevenin Output Voltage Levels as referen ces the 85 15 fall time Tg p is measured independently for the falling edges of the Vpp and Vpn waveforms A ULPS Entry sequence is specified for this test The measurement is performed sepa rately on both VDP and VDN Clock Lane waveforms Examples are shown in figure 3 15 and figure 3 16 Clock Lane LP TX Signaling Requirements Group 2 VDP LP 85 15 Fall Time and Slew Rate First Fall Edge 0 8 BEEN D 0 6 PN Amplitude V Time ns VDP Signal VDP VOL Slew Rate High Limit High Threshold Time Start Time End satin VDP VOH Slew Rate Slew Rate Low Limit Low Threshold Fig 3 15 Typical result of a clock lane
19. Time ns VDN Signal VDN VOL Slew Rate High Limit High Threshold Time Stat Time End VDN VOH Slew Rate Slew Rate Low Limit Low Threshold Fig 3 6 Typical result of a data lane LP TX 15926 85976 rise time measurement for V DN Test 1 1 4 Data Lane LP TX 85 15 Fall Time Tr p The purpose of this test case is to verify that the 8596 1596 Fall Time Tg p of the DUT s data lane LP transmitter is within the conformance limits The conformance range for Tz p is less than 25 ns Using the measured Vau and Vo LP TX Thevenin Output Voltage Levels as referen ces the 8596 1596 Fall Time Tr p is measured for each falling edge of the Vpp and Vpn waveforms The mean value across all observed falling edges are computed to produce the final Tg p result A ULPS Entry sequence is specified for this test The measurement is performed sepa rately on both Vpp and Vpy waveforms for each data lane An example is shown in figure 3 7 Data Lane LP TX Signaling Requirements Group 1 VDP LP 85 15 Fall Time and Slew Rate First Fall Edge E o z 2 Time ns VDP Signal VDP VOL Slew Rate High Limit High Threshold Time Stat Time End i VDP VOH Slew Rate Slew Rate Low Limit Low Threshold Fig 3 7 Typical result of a data lane LP TX 85 15 Fall time and slew rate measurement for V
20. a clock lane HS single ended output high voltage measurement V_OHHS High speed output high voltage DP Data positive D Vonns pn The software measures the Dy HS output high voltage in a similar way as Vonuus pey because the data pattern 01 is also required 3 6 3 7 Clock Lane HS TX Signaling Requirements Group 4 Amplitude V Time ns P OM lt V OHHS DN Fig 3 46 Typical result of a clock lane HS single ended output high voltage measurement V_OHHS High speed output high voltage DN Data negative D This test case is executed for all three cases of Zn 100 ohms 80 ohms and 125 ohms as well as for all clock lanes Test 1 4 7 Clock Lane HS TX Static Common Mode Voltages Vcyry4 and Vemrtx o The purpose of this test case is to verify that the clock lane HS transmit static common mode voltages Vcyrxq and Vemrxp are between 150 mV and 250 mV The HS transmit static common mode voltage is defined in the specification as the arithmetic mean of the value of the voltages at Dp and Dy Vemtx Wop Vpn 2 Vemrx1 The software measures the HS transmit differential 1 static common mode voltage by searching for all occurrences of bit 1 in the HS transmission differential data signal Three cases are to be distinguished e lf there are less than 5000 occurrences of 1 the software does still process the bits However the test results may be invalid it is recommended to u
21. between HS Configuration and LP Configuration as well as other compliance tests in R amp S ScopeSuite Test Mode This is only applicable if multiple groups of test cases shall be executed e Select Allow Skip Repeat to receive at the end of each test execution the choice to repeat or skip a test case e Otherwise select Do Not Allow Skip Repeat For more details on the effects of this selection see chapter 2 2 Controlling Test Cycles on page 12 R amp S9RTO K26 D PHY Compliance Tests Data Lane Under Test Select the data lane number to be tested This selection is only applicable for Group 1 test cases Default selection is data lane O C oap e Ifa Copp test fixture with 50 pF termination capacitance is used as required in the MIPI Alliance Specification for D PHY version 1 1 select 50 pF e If the 50 pF C oap fixture is removed select Open Note Test results are then reported as Informative cio Open 7 Informative Be aware that the test results may not be valid if no C opp test fixture with 50 pF termi nation capacitance is used The optional Open configuration setting is used to pro vide a qualitative estimate of the amount of C aan contributed by the DUT s PCB Zip The software supports all three cases of terminations Zp e a 100 ohms nominal load e b 80 ohms minimum load e c 125 ohms maximum load Specify the termination which is applied to the DUT This selection i
22. can be installed on a computer or directly on the R amp S RTO if the instru ment has Windows 7 Installing Software and License The preparation steps have to be performed only once for each computer and instru ment that are used for testing Uninstall older versions of the R amp S ScopeSuite If an older version of the R amp S ScopeSuite is installed make sure to uninstall the old version before you install the new one You can find the version number of the current installation in Help menu gt About To unistall the R amp S ScopeSuite use the Win dows Control Panel gt Programs R amp S RTO K26 Preparing the Measurements To install the R amp S ScopeSuite 1 Download the R amp S ScopeSuite software from the Downloads gt Software section on the Rohde amp Schwarz Scope of the Art web page www scope of the art com product rto html 2 Install the R amp S ScopeSuite software e Either on the computer that is used for testing e oronthe R amp S RTO if the instrument has a Windows 7 operating system To install the license key on the R amp S RTO When you got the license key of the compliance test option enable it on the R amp S RTO using SETUP SW Options For a detailed description refer to the R amp S RTO User Manual chapter Installing Options or to the online help on the instrument 1 3 Setting Up the Network If the R amp S ScopeSuite software runs on a test computer the computer and the
23. each data lane An example is shown in figure 3 10 Computed LP XOR Clock 930mV trip level and 500mV Trip Levels Amplitude V Positive Signal XOR Clock 930mV Trip Level 930mV Trip Level 500mV Trip Level Negative Signal XOR Clock 500mV Trip Level Fig 3 10 Typical result of a data lane LP TX pulse width of XOR clock measurement R amp SRTO K26 D PHY Compliance Tests 3 3 3 7 3 4 3 4 1 Test 1 1 7 Data Lane LP TX Period of Exclusive OR Clock T p pen rx The purpose of this test case is to verify that the pulse width T p pga rx of the DUT s data lane LP transmitter XOR clock is within the conformance limits The T p per Tx conformance range is composed of two parts e Minimum T p pgg 1x rising edge to rising edge period is greater than 90 ns e Minimum T p pen 1x falling edge to falling edge period is greater than 90 ns For a graphical example of XOR clock generation see figure 3 9 The LP XOR clock is computed separately using the maximum trip level threshold volt age of 930 mV and the minimum trip level threshold voltage of 500 mV A ULPS Entry sequence is specified for this test The measurement is performed sepa rately on both Vpp and Vpn waveforms for each data lane An example is shown in figure 3 10 Clock Lane LP TX Signaling Requirements Group 2 The purpose of Group 2 test cases is to verify various requirements specific to clock lane lo
24. for all data lanes Test 1 3 14 Data Lane HS Exit 30 85 Post EoT Rise Time Tagor The purpose of this test case is to verify that the 30 85 post EoT rise time Trror IS not more than 35 ns To compute the 30 85 Post EoT Rise Time Treo the software measures the rise time starting at the end of the HS TRAIL state and ending at the time when the Vpp rising edge crosses above the minimum logic 1 input voltage Viu y 880 mV Amplitude V Time ns Dap Dam Dad T REOT Fig 3 34 Typical result of a 30 85 post EoT rise time measurement Datp Waveform of Data Vpp Datn Waveform of Data Vpn Datd Differential waveform Vpp Vpn T REOT Duration of the 30 85 post EoT rise time This test case is tested for Zn 100 ohms only and for all data lanes 3 5 3 15 3 5 3 16 Data Lane HS TX Signaling Requirements Group 3 Test 1 3 15 Data Lane HS Exit Tror Value The purpose of this test case is to verify that the combined value of Tys Tra and Treor is not more than 105 ns 12 UI The software computes the combined value of Tus tray and Treor as Obtained accord ing to chapter 3 5 3 13 Test 1 3 13 Data Lane HS Exit Tis t7ra Value on page 59 and chapter 3 5 3 14 Test 1 3 14 Data Lane HS Exit 30 85 Post EoT Rise Time Treot on page 60 Amplitude V Dam Da Dag T EOT Fig 3 35 Typical result of a measurement of the combined value of T
25. the R amp S ScopeSuite start window Check the test configuration settings and adjust if necessary See e chapter 2 1 1 1 User Input on page 11 e chapter 2 1 1 3 Limit Editor on page 12 e chapter 3 2 Test Configuration for D PHY on page 18 Specific information on the required settings is given in the Test Require ments chapters for each test group Click Start Test In the Test Management dialog box select the session and click Next e To start a new test session select New and enter the session name e To resume an existing test session select Resume Existing and select the session name Umm ET Test Management Test Session New Resume Existing Name DPHY 20141001 164438 In the D PHY Test dialog box select one or more groups of test cases as descri bed in the relevant test case chapter Note By selecting a group all test cases of that group are selected It is not possi ble to select individual test cases To view all test cases of a group click on the little triangle on the left of the group name Test Configuration for D PHY 4 Iv Data Lane HS TX Signaling Requirements Group 3 Data Lane HS Entry T LPX Value 1 3 1 Data Lane HS Entry T HS PREPARE Value 1 3 2 3 2 Test Configuration for D PHY The test configuration consists of the general configuration settings as described in chapter 2 1 Configuring the Test on page 10 and some additional test specific con
26. the report has not yet been generated a message box asks if you want to create the report Click Yes The report opens in a separate application window depending on the file format You can check the test results and print the report To delete the report diagrams and waveform files of a session 1 In the Report Management dialog box select the session name to be deleted 2 Click Remove To change the session name 1 In the Report Management dialog box select the session name 2 Click Rename 3 D PHY Compliance Tests D PHY Ethernet compliance tests require option R amp S RTO K26 The software closely follows the MIPI Alliance s Conformance Test Suite for D PHY Physical Layer Version 1 1 Revision 03 dated June 5 2013 Should anything remain unclear in this manual please refer to that CTS document which is available for members of the MIPI Alliance at https members mipi org wg All Members home approved specs Table 3 1 Overview of D PHY compliance tests Test Groups and Tests Group 1 7 tests Data Lane LP TX Signaling Requirements 1 1 1 Data Lane LP TX Thevenin Output High Level Voltage Voy 1 1 2 Data Lane LP TX Thevenin Output Low Level Voltage VoL 1 1 3 Data Lane LP TX 1596 8596 Rise Time Tg p 1 1 4 Data Lane LP TX 8596 1596 Fall Time Tg p 1 1 5 Data Lane LP TX Slew Rate vs C oap OV dtsr 1 1 6 Data Lane LP TX Pulse Width of Exclusive OR Clock T p pui se r
27. voltage amplitude samples that fall between the centers of the fourth and fifth O bit in the 100000 data pattern 0 05 Amplitude V 0 1 2 6 8 Time ns V OD V OD 0 Fig 3 23 Typical result of an HS transmit differential 0 voltage measurement Vopi1 The software measures the HS transmit differential 1 voltage in a similar way as Vop oy Two exceptions are e t searches for reference waveforms with the data pattern 0111111 instead of 100000 e The value of Vann is then determined from that average waveform it is the mean of all voltage amplitude samples that fall between the centers of the fourth and fifth 1 bit in the 0111111 data pattern instead of 4 5 0 bit in the 100000 data pat tern Data Lane HS TX Signaling Requirements Group 3 Amplitude V Time ns V OD V OD 1 Fig 3 24 Typical result of an HS transmit differential 1 voltage measurement This test case is executed for all three cases of Zip 100 ohms 80 ohms and 125 ohms as well as for all data lanes 3 5 3 5 Test 1 3 5 Data Lane HS TX Differential Voltage Mismatch AVop The purpose of this test case is to verify that the HS transmit differential voltage mis match AVop is between 14 mV and 14 mV Using the values obtained in chapter 3 5 3 4 Test 1 3 4 Data Lane HS TX Differen tial Voltages Vopio and Vopn on page 48 the software computes the HS tr
28. 150 V us e The final averaged minimum V dtgr result is computed over 400 700 mV region The conformance range is greater than 30 V us e The final averaged minimum V dtsr margin result is computed over 700 930 mV region The minimum limit is defined by the equation 30 0 075 Vo nst 700 The conformance range is greater than 0 V us A ULPS Entry sequence is specified for this test The measurement is performed sepa rately on both Vpp and Vpn waveforms for each data lane Examples are shown in figure 3 7 figure 3 6 figure 3 5 and figure 3 8 Test 1 1 6 Data Lane LP TX Pulse Width of Exclusive OR Clock T p pui se Tx The purpose of this test case is to verify that the pulse width T p py se rx of the DUT s data lane LP transmitter Exclusive OR XOR clock is within the conformance limits The Ti p puise rx conformance range is composed of two parts e The first LP XOR clock pulse after a Stop state is wider than 40 ns e The minimum of all other LP XOR clock pulses is wider than 20 ns Data Lane LP TX Signaling Requirements Group 1 LP CLK EXOR Dp Dn Fig 3 9 Graphical example of XOR clock generation according to the specification The LP XOR clock is computed separately using the maximum trip level threshold voltage of 930 mV and the minimum trip level threshold voltage of 500 mV A ULPS Entry sequence is specified for this test The measurement is performed sepa rately on both Vpp and Vpn waveforms for
29. 88 Test Procedures 1326 1010 02 02 3 TTE 3 7 2 Performing Group 5 Test Cases sees eee eee 3 3 ee re T 75 e ocsetccerse pseraficrseitesiiacss ttsneardesasnede ni a a es iiaiai erie iieiea 1 1 1 2 Test Equipment Preparing the Measurements Test Equipment For D PHY compliance tests the following test equipment is needed R amp S RTO oscilloscope with 4 channels and at least 4 GHz bandwidth R amp S RTO1044 or equivalent alternatively R amp S RTO1004 1014 1024 with band width extension 4 GHz R amp S RTO B202 B204 205 For measuring the clock signal and either 1 differential probe or 2 single ended probes with at least 4 GHz bandwidth R amp S RT ZD40 or R amp S RT ZS60 However note that D PHY Group 2 and Group 4 tests require 2 probes for the clock signal For measuring the data signal and 2 probes with at least 4 GHz bandwidth either 2 R amp S RT ZD40 or 2 R amp S RT ZS60 R amp S RTO K26 D PHY compliance test option required option installed on the R amp S RTO Recommended test fixture for LP TX tests MIP D PHY Capacitive Load C oAp Fixture from The University of New Hampshire InterOperability Laboratory UNH IOL Recommended termination board for HS TX tests MIPI D PHY Reference Termi nation Board RTB from The University of New Hampshire InterOperability Labora tory UNH IOL The free of charge R amp S ScopeSuite software requires the Windows 7 operating system It
30. DP VDN LP 85 1596 Fall Time and Slew Rate First Fall Edge e Q DU amp E Time ns VDN Signal VDN VOL Slew Rate High Limit High Threshold Time Start Time End VDN VOH Slew Rate Slew Rate Low Limit Low Threshold Fig 3 8 Typical result of a data lane LP TX 85 15 Fall time and slew rate measurement for V DN 3 3 3 5 3 3 3 6 Data Lane LP TX Signaling Requirements Group 1 Test 1 1 5 Data Lane LP TX Slew Rate vs C oAp 6V Stsp The purpose of this test case is to verify that the Slew Rate SV dtsr of the DUT s data lane LP transmitter is within the conformance limits for specific capacitive loading con ditions The conformance ranges are specified below in the lists for falling and rising edges The Slew Rate is computed and measured independently for each edge of the Vpp and Vpn Signals using a 50 mV vertical window The Slew Rate curve is computed for a sin gle edge using the sliding window technique For falling edges e The final averaged maximum V dtgr result is computed over the entire vertical edge region The conformance range is less than 150 V us e The final averaged minimum OV dtsp result is computed over 400 930 mV region The conformance range is greater than 30 V us For rising edges e The final averaged maximum OV dtsp result is computed over the entire vertical edge region The conformance range is less than
31. NH IOL Refer to https www iol unh edu services test ing mipi fixtures php or https www iol unh edu services testing mipi UNH IOL MIPI D PHY RTB Data sheet 20090421 pdf for details T Lr 4 Ja kun qr 7 Jar aS e oe eae L MIF vi Inf a ir Inr Phi E Wi c JA hireh m lr uf Fale r a zii a urs ghi sili TIT Tq T KS dr AEFT 8 CMI ee ITE gn kd ie i wi j 3 m E ME el ein Ui DI ed ET Zr Ww In a C 4 S EU G 3 di a fiji ii wir mi IE Ee i I 3 i L Ew LE per i me D amp ui g SL la J iow m B i PH s cs ce eru ca biot E Le IL cis pig T ig dis 7 GL S icm Fa Fy EP F 2 rA T Zip rp El FAT Zip S Exil MIPT D PpHY REFERENCE TERMINATION BOARD IRE ud ey 2 0 E j HT MINIHI Fig 3 17 MIPI D PHY Reference Termination Board test fixture from UNH IOL Waveform Requirements Group 3 test cases require the DUT to transmit HS data burst waveforms as shown in figure 3 18 consisting of e a LP 11 HS Entry s b LP 01 e c LP 00 e d HS ZERO e e HS SYNC e f HS PAYLOAD Fe mail EEE SE det Test Procedures 1326 1010 02 02 41 Data Lane HS TX Signaling Requirements Group 3 e g HS TRAIL e h LP 11 HS Exit X G0Q000p00000600000000000000000000000060 x Dp Dn TLP Tus PREPARE T Hs ZERO Disconnect Terminator VrermEN MAX P Je E IMipr max EE emt D TERM EN 15T Data Bit Ths skip
32. R amp SSRTO K26 D PHY Compliance Test Test Procedures 19206 1010 02 02 Test amp Measurement Test Procedures This manual describes the D PHY compliance test procedures with the following option e R amp S RTO K26 1317 5668 02 D PHY The tests require the R amp S ScopeSuite software O 2014 Rohde amp Schwarz GmbH amp Co KG Muhldorfstr 15 81671 Munchen Germany Phone 49 89 41 29 0 Fax 49 89 41 29 12 164 E mail info rohde schwarz com Internet www rohde schwarz com Subject to change Data without tolerance limits is not binding R amp S is a registered trademark of Rohde amp Schwarz GmbH amp Co KG Trade names are trademarks of the owners The following abbreviations are used throughout this manual R amp S9RTO is abbreviated as R amp S RTO and R amp S ScopeSuite is abbreviated as R amp S ScopeSuite R amp S RTO K26 Contents Contents 1 Preparing the Measurements anrannnnnennnnnnunnnnnnnnnnunnnnnnnnnnnnnnnnnnennuennunnn 5 14 PESCIE CUI NE ec sictesacusanvienautamanenisiinsaseustworcionsewiavsinaahitneucbaverenwisstinmunaeriutiemaateciansaciis 5 1 2 Installing Software and LiCcenSe anxrrvnnuvnnnnnnnnnnnnnnnnnnvnnnnnernnnnnnnnnnennnnnnennnnnnnnnnnnnnnnnnr 5 1 3 Setting Up the NetWwork Lissasvamsiesgmskivmanemngsmemnmeimiemavvdnusd nane 6 1 4 Starting the R amp S ScopeSuite rrr nnrrrnnnnerrnnnvnnnnnnnnnnnnennnnnvnnnnnvnnnnnnennnnnennnnnvennnnnennnnnunr 7 1 5 Con
33. S TX Signaling Requirements Group 4 Amplitude V Time ns V OD V_OD 1 Fig 3 44 Typical result of a clock lane HS transmit differential 1 voltage measurement This figure shows a failure case V_OD lt 140 mV This test case is executed for all three cases of Zn 100 ohms 80 ohms and 125 ohms as well as for all clock lanes Test 1 4 5 Clock Lane HS TX Differential Voltage Mismatch AV an The purpose of this test case is to verify that the clock lane HS transmit differential volt age mismatch AV op is between 14 mV and 14 mV Using the values obtained in chapter 3 6 3 4 Test 1 4 4 Clock Lane HS TX Differen tial Voltages Vop o and Vopi1 on page 71 the software computes the clock transmit differential voltage mismatch according to this formula AV op Vann IVop ojl This test case is executed for all three cases of Zip 100 ohms 80 ohms and 125 ohms as well as for all clock lanes Test 1 4 6 Clock Lane HS TX Single Ended Output Voltages Vonns pp and VoHHs DN The purpose of this test case is to verify that the single ended HS output high voltage is not more than 360 mV Clock Lane HS TX Signaling Requirements Group 4 Vonnsipp TO measure the Dp HS output high voltage the software searches for refer ence waveforms with the data pattern 01 in the HS transmission differential data sig nal Although in this context it is referring to the single ended sign
34. S TX Signaling Requirements Group 4 Clock Lane HS Entry T LPX Value 1 4 1 Clock Lane HS Entry T CLK PREPARE Value 1 4 2 Return To Main Menu 3 Click Start 4 The Test Cycle dialog box shows the status of the test cases included in the test cycle and marks the next case to be done see chapter 2 2 Controlling Test Cycles on page 12 Click Run This group of tests uses the MIPI D PHY Reference Termination Board RTB test fixture from the UNH IOL Follow the instructions of the step by step guide Group 4 of test cases requires 2 setup steps Only two clock signals are required for the test The clock signals can be tapped either from the DUT or RTB or even on the SMA cables between the DUT and the RIB When you have finished all steps the compliance test runs automatically Further steps chapter 2 3 Getting Test Results on page 13 3 6 3 3 6 3 1 Clock Lane HS TX Signaling Requirements Group 4 Measurements e Test 1 4 1 Clock Lane HS Entry T px Value eese 68 e Test 1 4 2 Clock Lane HS Entry Te k PrRepare Value eere 69 e Test 1 4 3 Clock Lane HS Entry Te k Prepare Touk zero Value 70 e Test 1 4 4 Clock Lane HS TX Differential Voltages Vana and Vopq 71 e Test 1 4 5 Clock Lane HS TX Differential Voltage Mismatch AVop is e Test 1 4 6 Clock Lane HS TX S
35. S transmission is between 40 ns 4 UI and 85 ns 6 UI with Ul Unit Interval which is the symbol duration time The software measures the duration of the last LP 00 state that occurs immediately before an HS transmission This duration is labeled Tus pnepAnr The duration is measured e starting at the time when the Vp falling edge crosses below the maximum logic 0 input voltage Vi max 550 mV and e ending at the time when the differential waveform crosses below the minimum dif ferential input low threshold Vipz 70 mV 3 5 3 3 Data Lane HS TX Signaling Requirements Group 3 Amplitude V Time ns Datp Datn Datd T HS PREPARE Fig 3 21 Typical result of a data lane T HS PREPARE measurement Datp Waveform of Data Vpp Datn Waveform of Data Vpn Datd Differential waveform Vpp Vpn T HS PREPARE Duration of last LP 00 state immediately before HS transmission This test case is tested for Zip 100 ohms only and for all data lanes Test 1 3 3 Data Lane HS Entry Data Lane Tys _prepare Tus zego Value The purpose of this test case is to verify that the combined value of Tys prepare and the duration of the HS ZERO state that occurs immediately before an HS transmission is at least 145 ns 10 UI The software measures the duration of the HS ZERO state that occurs immediately before an HS transmission This duration is labeled Tys zero The duration
36. able and pro ceeds with the next test case If there are less than 128 occurrences of 10 the software does still process the reference waveforms However the test results may be invalid in this case it is recommended to use a different test pattern and then redo the test For the clock type of partial clock burst and continuous clock if there are less than 128 occurrences of 10 the software does still process the reference waveforms However the test results may be invalid in this case it is recommended to modify the time base of the oscilloscope to acquire more waveforms and then redo the test If there are 128 or more occurrences of 10 the software processes the last 128 reference waveforms An average waveform is then constructed by horizontally aligning 128 or less refer ence waveforms to a common anchor point which is the zero crossing time of the first transition Once the average waveform is obtained the value of tc is measured as the time taken for the waveform to fall from Vop o 0 8 Vopv1 Vopoyl to Vop o 0 2 Vap Vop oyl Amplitude V 0 131 95 mV Fig 3 52 Typical result of a clock lane HS transmit 80 20 fall time measurement 3 6 3 13 Clock Lane HS TX Signaling Requirements Group 4 Vop Clock lane high speed transmission differential data signal Vopi1 Clock lane HS transmit differential 1 voltage Vop o Clock lane HS transmit differential 0 volta
37. al 01 on the differen tial signal means the same pattern on the Dp single ended signal Four cases are to be distinguished e If there is no occurrence of 01 the software marks Vouus pp as indeterminable and proceeds with the next measurement Vouus pyy e fthere are less than 128 occurrences of 01 the software does still process the reference waveforms However the test results may be invalid in this case it is recommended to use a different test pattern and then redo the test e For the clock type of partial clock burst and continuous clock if there are less than 128 occurrences of 01 the software does still process the reference waveforms However the test results may be invalid in this case it is recommended to modify the time base of the oscilloscope to acquire more waveforms and then redo the test e lf there are 128 or more occurrences of 01 the software processes the last 128 reference waveforms An average waveform is then constructed by horizontally aligning 128 or less refer ence waveforms to a common anchor point which is the zero crossing time of the first transition The value of Vouus pp is then determined from that average waveform it is the mean of all samples that are closest to the center of the second bit which is the 1 bit Clock Lane HS TX Signaling Requirements Group 4 Amplitude V Time ns V OHH V_OHHS DP Fig 3 45 Typical result of
38. amp S RT ZD40 or Single ended probes R amp S RT ZS60 Test fixture UNH IOL MIPI D PHY Capacitive Load C gap LR n this group of tests sampling the signals requires 2 probes either single ended or differential used in single ended mode We recommend to use a MIPI D PHY Capacitive Load C oap test fixture from the University of New Hampshire InterOperability Laboratory UNH IOL Refer to https www iol unh edu services testing mipi fixtures php for details Test Procedures 1326 1010 02 02 21 R amp S RTO K26 D PHY Compliance Tests Fig 3 3 MIPI D PHY Capacitive Load test fixture from UNH IOL Waveform requirements Group 1 test cases require the DUT to source a MIPI D PHY LP data lane ULPS Entry sequence The figure below shows a typical ULPS Entry sequence waveform It con sists of e a Escape Mode Entry LP 11 gt 10 gt 00 gt 01 gt 00 e b Ultra Low Power State Entry Command Pattern 00011110 I I I I I 51 TU VU UT og I I l l Id l l tl 2 1534 ee ee eae ee eS Ec GE ee NE ET TR SET FER ER EN Escape Mode Entry l l l Entry Command The software requires a pair of waveforms containing a and b as stated above to measure correctly and perform the test successfully Settings in the LP Configuration dialog box See also chapter 3 2 Test Configuration for D PHY
39. ance limits of 15 of the unit interval Ul duration HS TX Clock to Data Lane Timing Requirements Group 5 Tskewrrx IS the permissible deviation of the data launch time to the ideal 7 Ulingr dis placed quadrature clock edge The software measures the timing error Tskewrx between each data lane edge and its corresponding clock lane edge in a minimum sample of 10 000 events to produce an array of timing error values The maximum minimum and mean timing error values across all observed edges are recorded The example in figure 3 62 shows how the software presents Tskewrx in a report Skew Ul Time ns Skew Skew Range Fig 3 62 Evaluation of the relative skew between clock and data signaling
40. and Treor as obtained according to chapter 3 6 3 13 Test 1 4 13 Clock Lane HS Exit Tc k Tra Value on page 83 and chapter 3 6 3 14 Test 1 4 14 Clock Lane HS Exit 3096 8596 Post EoT Rise Time Treo07 on page 84 3 6 3 16 Clock Lane HS TX Signaling Requirements Group 4 Amplitude V Time ns Op LEM Chl 1 T EOT Fig 3 55 Typical result of a measurement of the combined value of T Clkp Waveform of Clock Vpp Clkn Waveform of Clock Vpn Clkd Differential waveform Vpp Von T_EOT T_CLK TRAIL T REOT This test case is tested for Zip 100 ohms only and for all clock lanes Test 1 4 16 Clock Lane HS Exit Tis gx Value The purpose of this test case is to verify that the duration of the LP 11 state that occurs immediately after an HS transmission is at least 100 ns The software measures Tus gxi7 the duration of the last LP 11 state that occurs imme diately after an HS transmission as follows The state is measured starting at the end of the CLK TRAIL state and ending at the time when the Vpp falling edge crosses below the maximum logic 0 input voltage Vi Max 950 mV For the end of the CLK TRAIL state two cases have to be distin guished e f CLK TRAIL is a differential 1 state the end of the state will be defined at the time when the differential waveform crosses below the minimum differential input low threshold Vip 70 mV e f CLK TRAIL is a dif
41. ansmit dif ferential voltage mismatch according to this formula AVop Vann G IVop ojl This test case is executed for all three cases of Zp 100 ohms 80 ohms and 125 ohms as well as for all data lanes 3 5 3 6 Test 1 3 6 Data Lane HS TX Single Ended Output Voltages Vonns pp and VoHHs DN The purpose of this test case is to verify that the single ended HS output high voltage is not more than 360 mV Data Lane HS TX Signaling Requirements Group 3 Vonnsipp TO measure the Dp HS output high voltage the software searches for refer ence waveforms with the data pattern 011111 in the HS transmission differential data signal Although in this context it is referring to the single ended signal 011111 on the differential signal means the same pattern on the Dp single ended signal Three cases are to be distinguished e If there is no occurrence of 011111 the software marks Vokksprp as indetermina ble and proceeds with the next measurement Vouus pyy e lf there are less than 128 occurrences of 011111 the software does still process the reference waveforms However the test results may be invalid in this case it is recommended to use a different test pattern and then redo the test e lf there are 128 or more occurrences of 011111 the software processes the last 128 reference waveforms An average waveform is then constructed by horizontally aligning 128 or less refer
42. cases require the DUT to source a MIPI D PHY LP data lane ULPS Entry sequence and an Exit sequence on the clock lane e Atypical ULPS Entry sequence waveform consists of LP 11 gt 10 gt 00 e Atypical ULPS Exit sequence waveform consists of LP 00 gt 10 gt 11 The software requires 2 pairs of waveforms containing ULPS Entry and Exit sequences as stated above to measure correctly and perform the test successfully Settings in the LP Configuration dialog box See also chapter 3 2 Test Configuration for D PHY on page 18 C oap Requirements Select C oap to be 50 pF which is also the default selection Most of the Group 2 tests require a 50 pF Coan test fixture which is practically used aS maximum capacitive load Some other tests are independent of termina tion capacitance For procedural consistency all tests are performed using a 50 pF Ci oap test fixture e Low PassFilter Enable the Low Pass Filter For details regarding this filter see chapter 3 2 Test Configuration for D PHY on page 18 3 4 2 Performing Group 2 Test Cases 1 Start running the tests as described in chapter 3 1 Starting D PHY Compliance Tests on page 17 2 Select Clock Lane LP TX Signaling Requirements Group 2 Hue EE XS a ER Test Procedures 1326 1010 02 02 32 Clock Lane LP TX Signaling Requirements Group 2 D PHY Test 4 ai Data Lane LP TX Signaling Requirements Group 1 Clock Lane LP TX Signaling Requirements
43. d RTB test fixture from the UNH IOL Follow the instructions of the step by step guide Group 5 of test cases requires 2 setup steps The clock signals can be tapped either from the DUT or RTB or even on the SMA cables between the DUT and the RTB The connections may differ slightly depending on the clock format and the termina tions which are applied to the DUT When you have finished all steps the compliance test runs automatically Further steps chapter 2 3 Getting Test Results on page 13 HS TX Clock to Data Lane Timing Requirements Group 5 3 3 Measurements e Test 1 5 1 HS Entry Tepicpre Value ee eee eee 93 e Test 1 5 2 HS Exit Topk post Value eee 94 e Test 1 5 3 HS Clock Rising Edge Alignment to First Payload Bit 95 JEGER GR Ge TET ET EE 95 3 7 3 1 Test 1 5 1 HS Entry Tc pac Value The purpose of this test case is to verify that the time Tc pag during which the high speed clock is driven prior to an associated data lane that begins the transition from low power to high speed mode is greater than the minimum required value 8 Ul The state is measured e beginning at the end of the clock lane To k zero interval at the point where the clock lane differential waveform crosses below the minimum valid HS RX differen tial threshold level of 70 mV and e ending at the point where the data lane s Vpp LP 01 falling edge crosses Vi max 550 mV An exam
44. determinable and proceeds with the next test case e fthere are less than 128 occurrences of 111000 the software does still process the reference waveforms However the test results may be invalid in this case it is recommended to use a different test pattern and then redo the test e lf there are 128 or more occurrences of 111000 the software processes the last 128 reference waveforms An average waveform is then constructed by horizontally aligning 128 or less refer ence waveforms to a common anchor point which is the zero crossing time of the first transition Once the average waveform is obtained the value of tc is measured as the time taken for the waveform to fall from Vop o 0 8 Vona Vop yl to Vop o 0 2 Von Vop oyl 0 2 0 15 0 1 0 05 Amplitude V 0 05 Fig 3 32 Typical result of a data lane HS transmit 80 20 fall time measurement Vop High speed transmission differential data signal Von HS transmit differential 1 voltage Von HS transmit differential 0 voltage tr Fall time Data Lane HS TX Signaling Requirements Group 3 This test case is executed for all three cases of Zn 100 ohms 80 ohms and 125 ohms as well as for all data lanes 3 5 3 13 Test 1 3 13 Data Lane HS Exit Tys tray Value The purpose of this test case is to verify that the duration of the HS TRAIL state that occurs immediately after an HS transmission is at least 60 ns 4 Ul
45. dge crosses below the maximum logic 0 input voltage Vi max 550 mV and ending at the time when the Vp falling edge crosses below the same logic 0 input voltage Vit max 3 6 3 2 Clock Lane HS TX Signaling Requirements Group 4 Amplitude V x i me Lo Lo 2 100 200 300 400 Time ns Op LEM CE T LPX Fig 3 40 Typical result of a clock lane T LPX measurement Clkp Waveform of Clock Vpp Clkn Waveform of Clock Vpn Clkd Differential waveform Vpp Vpn T LPX Duration of last LP 01 state immediately before HS transmission This test case is tested for Zip 100 ohms only and for all clock lanes Test 1 4 2 Clock Lane HS Entry Tc prepare Value The purpose of this test case is to verify that the duration of the last LP 00 state Terk prepare prior to driving Te zego When entering HS mode is between 38 ns and 95 ns The software measures the duration of the last LP 00 state that occurs immediately before an HS transmission This duration is labeled Tc k PREPARE The duration is measured e starting at the time when the Vp falling edge crosses below the maximum logic 0 input voltage Vi max 550 mV and e ending at the time when the differential waveform crosses below the minimum dif ferential input low threshold Vipr 70 mV 3 6 3 3 Clock Lane HS TX Signaling Requirements Group 4 2 15 T_CLK PREPARE 52 6 ns NENNEN Amplitude V x i me Lo Lo 2 100 200 300
46. e It searches for all occurrences of bit 0 instead of bit 1 Test Procedures 1326 1010 02 02 53 3 5 3 8 3 5 3 9 Data Lane HS TX Signaling Requirements Group 3 0 25 Amplitude V Time ns V CMTX 0 Mean Fig 3 28 Typical result of a data lane HS transmit differential 0 static common mode voltage mea surement V CMTX 0 This test case is executed for all three cases of Zip 100 ohms 80 ohms and 125 ohms as well as for all data lanes Test 1 3 8 Data Lane HS TX Static Common Mode Voltage Mismatch AVcyrx o The purpose of this test is to verify that the HS transmit static common mode voltage mismatch is between 5 mV and 5 mV Using the values obtained in chapter 3 5 3 7 Test 1 3 7 Data Lane HS TX Static Common Mode Voltages Vowrtx1 and V Gwreg on page 52 the software computes the HS transmit static common mode voltage mismatch AVcmrx1 0 according to this for mula AVemtx 1 0 AVemrxa 7 AVomrxo 2 This test case is executed for all three cases of Zip 100 ohms 80 ohms and 125 ohms as well as for all data lanes Test 1 3 9 Data Lane HS TX Dynamic Common Level Variations Between 50 450 MHz AVcwrx LF The purpose of this test case is to verify that the common level variation between 50 450 MHz is not more than 25 MVpegax R amp S9RTO K26 D PHY Compliance Tests The common level variation between 50 450 MHz AVoyrxqr is measured as follows The
47. ed for this test The measurement is performed sepa rately on both Vpp and Vpn waveforms for each data lane An example is shown in figure 3 4 Test 1 1 3 Data Lane LP TX 15 85 Rise Time Tg p The purpose of this test case is to verify that the 1596 8596 Rise Time Tg p of the DUT s data lane LP transmitter is within the conformance limits The conformance range for TRLP is less than 25 ns Using the measured Vau and Vo LP TX Thevenin Output Voltage Levels as referen ces the 1596 8596 Rise Time Tg p is measured for each rising edge of the Vpp and Data Lane LP TX Signaling Requirements Group 1 Vpn waveforms The mean value across all observed rising edges are computed to produce the final Tg p result A ULPS Entry sequence is specified for this test The measurement is performed sepa rately on both Vpp and Vpn waveforms for each data lane An example is shown in figure 3 5 VDP LP 15 8596 Rise Time and Slew Rate First Rise Edge Amplitude V Time ns VDP Signal VDP VOL Slew Rate High Limit High Threshold Time Stat Time End VDP VOH SlewRate Slew Rate Low Limit Low Threshold Fig 3 5 Typical result of a data lane LP TX 15 85 rise time measurement for V_DP 3 3 3 4 Data Lane LP TX Signaling Requirements Group 1 VDN LP 15 85 Rise Time and Slew Rate First Rise Edge BEL OL L LEAL IL Ul pL Amplitude V
48. eference Termination Board RTB E i 1 In this group of tests sampling the signals requires 2 probes either single ended or differential used in single ended mode 1 We recommend to use a MIPI D PHY Reference Termination Board RTB test fixture from the University of New Hampshire InterOperability Laboratory UNH IOL Refer to https www iol unh edu services test ing mipi fixtures php or https www iol unh edu services testing mipi UNH IOL MIPI D PHY RTB Data sheet 20090421 pdf for details R amp S RTO K26 D PHY Compliance Tests HOPE ETP E Ly F I hr f aill 0P G ni n MP Al uf zie dre E E 3 wi sir wa ATT EET lil B S alu liii S Zr n Ul illia M REI iil a di aj IH E T IS P m tr e 5 ja m ACIE SL L m B L G B E m ia T KU 5 eB Biot a Cin oe cis fjer T cis itis amp LE i cH e cid C17 CIG se J d a R pa pa P N iD FAT Zip FOU Zip EO SE MIPT D PHY REFERENCE TERMI NAT LON BOARD omg TP amp bil E pau Fig 3 37 MIPI D PHY Reference Termination Board test fixture from UNH IOL Waveform Requirements Group 4 test cases require the DUT to transmit HS clock burst waveforms as shown in figure 3 38 consisting of e a CLK ZERO e b CLK PRE e c Toggling HS 0 HS 1 e d CLK TRAIL T Test Procedures 1326 1010 02 02 64 Clock Lane HS TX Signaling Requirements Group 4 Clock Lane Disconnect Dp Dn Terminator Teixrost KE
49. eport in section General Information Configuration User Input HS Configuration Report Configuration Device Under Test DUT Device A version 003 User Max Mayer Site Temperature Comments Complete device test 2 1 1 2 Report Configuration On the Report Configuration tab you select the format of the report and the details to be included in the report Here you can also select an icon that will be displayed in the upper left corner of the report Controlling Test Cycles d RSScopeSuite Configuration Configuration LP Configuration HS Configuration Report Configuration Content Report Format Display Summary amp PDF Display Detail MSWord Display Screen Shots HTML Left Icon QD Come Cancel 2 1 1 3 Limit Editor The Limit Editor shows the measurement limits that are used for compliance testing Each limit comprises the comparison criterion the unit the limit value A and a second limit value B if the criterion requires two limits You can set the values to defaults change the values in the table export the table in xml format or import xml files with limit settings 1 Select the Test Type in the lower left corner of the dialog box 2 Check and adjust the measurement limits 2 2 Controlling Test Cycles If you have selected several test cases or test case groups and the test mode Allow Skip Repeat is set in the Configuration dialog box you can control the
50. esses the last 128 reference waveforms 3 5 3 12 Data Lane HS TX Signaling Requirements Group 3 An average waveform is then constructed by horizontally aligning 128 or less refer ence waveforms to a common anchor point which is the zero crossing time of the first transition Once the average waveform is obtained the value of tz is measured as the time taken for the waveform to rise from Vop o 0 2 V apn Vono to Vono 0 8 Von Vopioytl Amplitude V Fig 3 31 Typical result of a data lane HS transmit 20 80 rise time measurement Vop High speed transmission differential data signal Vopio HS transmit differential 0 voltage Vana HS transmit differential 1 voltage tr Rise time This test case is executed for all three cases of Zn 100 ohms 80 ohms and 125 ohms as well as for all data lanes Test 1 3 12 Data Lane HS TX 80 20 Fall Time te The purpose of this test case is to verify that the 80 20 fall time is e between 150 ps and 0 3 UI when operating at HS bit rates up to 1 Gbps e between 100 ps and 0 35 UI when operating at HS bit rates greater than 1 Gbps Data Lane HS TX Signaling Requirements Group 3 To measure the 80 20 fall time te the software searches for reference waveforms with the data pattern 111000 in the HS transmission differential data signal Three cases are to be distinguished e If there is no occurrence of 111000 the software marks tc as in
51. f Data Vpp Datn Waveform of Data Vpn T HS EXIT duration of last LP 11 state after HS transmission This test case is tested for Zip 100 ohms only and for all data lanes Clock Lane HS TX Signaling Requirements Group 4 The purpose of Group 4 test cases is to verify the various transmission requirements specific to clock lane high speed HS signaling 3 6 1 Clock Lane HS TX Signaling Requirements Group 4 Group 4 consists of 18 test cases described in chapter 3 6 3 Measurements on page 68 A single captured HS TX clock lane signaling sequence is measured including LP exit and LP entry sequences that occur before and after the HS burst sequence There are also test cases to measure the Unit Interval Ul symbol duration time Particularly within the Group 4 test cases the software can process three different clock types e clock burst non continuous clock e partial clock burst where HS entry and HS exit are captured separately and e continuous clock Therefore various DUT configurations are required to generate signals with these three clock types This group of test cases is only applicable to master devices Test Setup Table 3 5 Equipment for Group 4 Clock Lane HS TX Signaling Requirements test Rohde amp Schwarz oscilloscope R amp S RTO1044 or equivalent 4 GHz Probes Differential probes R amp S RT ZD40 or Single ended probes R amp S RT ZS60 Test fixture UNH IOL MIPI D PHY R
52. ferential O state the end of the state will be defined at the time when the differential waveform crosses above the maximum differential input high threshold Vipty 70 mV Clock Lane HS TX Signaling Requirements Group 4 N Amplitude V o i i uo L S Time ns Che c E nm T HS EXIT Fig 3 56 Typical result of a measurement of the duration of the LP 11 state immediately after an HS transmission Clikp Waveform of Clock Vpp Clkn Waveform of Clock Vpn T HS EXIT duration of last LP 11 state after HS transmission This test case is tested for Zi 100 ohms only and for all clock lanes 3 6 3 17 Test 1 4 17 Clock Lane HS Clock Instantaneous Ulysr Value The purpose of this test is to verify that the instantaneous unit interval values Ulinst of the DUT s high speed clock meet the following requirements e the calculated maximum Ulis value is less than 12 5 ns e the calculated minimum Ulsr value is greater than or equal to the specified Ulinst min Value as obtained from the vendor or from the datasheet The software measures the instantaneous unit interval values Ulus as follows A sample with at least 5000 Uls of the DUT s HS clock signaling is captured The difference of the positive and negative single ended clock lane waveforms Vpp Vpy is computed to acquire the differential clock lane waveform Based on the difference between successive 0 V crossing time
53. from UNH IOL Waveform Requirements Group 5 test cases require the DUT to transmit HS clock burst waveforms as shown in figure 3 58 consisting of e a LP 11 HS Entry e b LP 01 e c LP 00 d HS ZERO e e HS SYNC f HS PAYLOAD g HS TRAIL h LP 11 HS Exit T Test Procedures 1326 1010 02 02 90 HS TX Clock to Data Lane Timing Requirements Group 5 Clock Lane Disconnect Dp Dn Terminator e 1 2 ViL max EE r 7 EL lupx Teuceneeane T CLK ZERO Teuceng Data Lane Disconnect Dp Dn Terminator o min boum ED T m NE THS SKIP Tp renmen T Hs sETTLE Fig 3 58 A typical MIPI D PHY HS clock burst waveform courtesy of MIPI Alliance Specification for D PHY version 1 1 The software requires at least one set of complete data burst waveforms for correct processing to perform the test successfully If the clock is set to normal burst mode the software also requires at least one set of complete clock burst waveforms Settings in the HS Configuration dialog box See also chapter 3 2 Test Configuration for D PHY on page 18 Zp Group 5 is performed using the Zn 100 ohms termination case only and is mea sured for all data lanes So the pair of data lanes under test dat and dat and the pair of clock lanes clk and cik have to be terminated with the 100 ohms loads on the RTB e Clock Format Data signals two single ended p
54. ge tr Fall time This test case is executed for all three cases of Zn 100 ohms 80 ohms and 125 ohms as well as for all clock lanes Test 1 4 13 Clock Lane HS Exit Tc k Tra Value The purpose of this test case is to verify that the duration of the CLK TRAIL state that occurs immediately after a clock lane HS transmission is at least 60 ns In the measurement of the duration Tc x tRai Of this state the software distinguishes two cases e If the last bit in the clock lane HS PAYLOAD is a 0 then the CLK TRAIL state is a differential 1 state The start of the state is defined at the time when the differential waveform crosses above the maximum differential input high threshold Vipty 70 mV The end of the state is defined at the time when the differential waveform crosses below the maximum differential input high threshold Vipru 70 mV e If the last bit in the clock lane HS PAYLOAD is a 1 then the CLK TRAIL state is a differential O state The start of the state is defined at the time when the differential waveform crosses below the minimum differential input low threshold Vipz 70 mV The end of the state is defined at the time when the differential waveform crosses above the minimum differential input low threshold Vipt 70 mV 3 6 3 14 Clock Lane HS TX Signaling Requirements Group 4 i N AM TI Amplitude V Time ns Clkp Clkn Clkd
55. ge region The conformance range is less than 150 V us R amp S9RTO K26 D PHY Compliance Tests 2 The final averaged minimum OV dtsr result is computed over the 400 700 mV region The conformance range is greater than 30 V us 3 The final averaged minimum SV dtsr margin result is computed over the 700 930 mV region The minimum limit is defined by the equation 30 0 075 Vo nst 700 The conformance range is greater than 0 V us Both a ULPS Entry sequence and an Exit sequence are specified for this test The measurement is performed separately on both Vpp and Vpn clock lane waveforms Examples are shown in figure 3 13 figure 3 14 figure 3 15 and figure 3 16 3 5 Data Lane HS TX Signaling Requirements Group 3 The purpose of Group 3 test cases is to verify the various transmission requirements specific to data lane high speed HS burst signaling Group 3 consists of 16 test cases described in chapter 3 5 3 Measurements on page 45 They include LP Exit and Entry sequences occurring before and after the HS burst sequence The software is intended to facilitate the execution of a set of several HS TX measure ments on a set of captured HS burst waveforms This version of the ScopeSuite MIPI D PHY compliance test software only processes data burst waveforms also known as non continuous data waveforms It does not support partial data burst where HS Entry and HS Exit are captured separately or continuous data However the softwa
56. illoscope to acquire more waveforms and then redo the test e lf there are 128 or more occurrences of 10 the software processes the last 128 reference waveforms The reason for this procedure is this In some cases transient effects introduced by some high impedance probes can introduce a small error in the HS common mode level at the beginning of the transmission This error can be significant enough to affect the test result Therefore an average waveform is constructed by horizontally aligning 128 or less reference waveforms to a common anchor point which is the zero cross ing time of the first transition The value of Vono is then determined from that average waveform it is the mean of all samples that are closest to the center of the second bit which is the O bit 0 05 0 05 Amplitude V 0 1 0 2 Time ns v_OD V_OD 0 Fig 3 43 Typical result of a clock lane HS transmit differential 0 voltage measurement This figure shows a failure case V_OD gt 140 mV Vopi1 The software measures the clock transmit differential 1 voltage in a similar way as Vop oy Two exceptions are e It searches for reference waveforms with the data pattern 01 instead of 10 e From the obtained average waveform the value of Vopi1 is measured as the mean of all samples that are closest to the center of the second bit which is the 1 bit instead of O bit 3 6 3 5 3 6 3 6 Clock Lane H
57. ingle Ended Output Voltages Vokkspr and LISTS ELT 73 e Test 1 4 7 Clock Lane HS TX Static Common Mode Voltages Vemtx 1 and LT EEE EE EE EE 76 e Test 1 4 8 Clock Lane HS TX Static Common Mode Voltage Mismatch T TRT ZE EE H ee oe tne E 78 e Test 1 4 9 Clock Lane HS TX Dynamic Common Level Variations Between SONO TUER ERE 78 e Test 1 4 10 Clock Lane HS TX Dynamic Common Level Variations Above AE EE EE E 79 e Test 1 4 11 Clock Lane HS TX 20 80 Rise Time tg 80 e Test 1 4 12 Clock Lane HS TX 80 20 Fall Time e s see eee eee 81 e Test 1 4 13 Clock Lane HS Exit Te tray Value eee eee 83 e Test 1 4 14 Clock Lane HS Exit 30 85 Post EoT Rise Time Tgzgorz 84 e Test 1 4 15 Clock Lane HS Exit Tror Value sees 85 e Test 1 4 16 Clock Lane HS Exit Tis gwr Value eee eee 86 e Test 1 4 17 Clock Lane HS Clock Instantaneous Ulis Value 87 e Test 1 4 18 Clock Lane HS Clock Delta Ul AUI Value 88 Test 1 4 1 Clock Lane HS Entry T px Value The purpose of this test case is to verify the duration of the last LP 01 state immedi ately before HS transmission is at least 50 ns The software measures the duration of the last LP 01 state that occurs immediately before an HS transmission This duration is labeled T px The duration is measured starting at the time when the Vpp falling e
58. is measured e starting at the time when the differential waveform crosses below the minimum dif ferential input low threshold Vip7 70 mV and e ending at the start of HS SYNC state However the HS SYNC sequence begins with a 0001 and so there will be no visi ble delineation between the end of the HS ZERO state and the start of the HS SYNC state Therefore the start of the HS SYNC state is defined at 3 bit times before the differential waveform crosses the maximum differential input high threshold Vipty 70 mV 3 5 3 4 Data Lane HS TX Signaling Requirements Group 3 The software then computes the combined value of Tys prepare See chapter 3 5 3 2 Test 1 3 2 Data Lane HS Entry Data Lane Tys prepare Value on page 46 and Tus ZERO Amplitude V 2 PP 0 50 100 150 200 250 Time ns Datp Datn Datd T HS PREPARE T HS ZERO Fig 3 22 Typical result of a data lane T HS PREPARE T HS ZERO measurement Datp Waveform of Data Vpp Datn Waveform of Data Vpn Datd Differential waveform Vpp Von T HS PREPARE Duration of last LP 00 state immediately before HS transmission T HS ZERO Duration of HS ZERO state immediately before HS transmission This test case is tested for Zip 100 ohms only and for all data lanes Test 1 3 4 Data Lane HS TX Differential Voltages Von and Vop The purpose of this test case is to verify that e the HS transmit differen
59. it Tus tray Value see eee 59 e Test 1 3 14 Data Lane HS Exit 30 85 Post EoT Rise Time Tarare 60 e Test 1 3 15 Data Lane HS Exit Teor Value eee eee 61 e Test 1 3 16 Data Lane HS Exit Tis gir Value eee 61 Test 1 3 1 Data Lane HS Entry Data Lane T px Value The purpose of this test case is to verify that the duration of the last LP 01 state imme diately before HS transmission is at least 50 ns The software measures the duration of the last LP 01 state that occurs immediately before an HS transmission This duration is labeled T px The duration is measured starting at the time when the Vpp falling edge crosses below the maximum logic 0 input voltage Vi max 550 mV and ending at the time when the Vp falling edge crosses below the same logic 0 input voltage Vii max 3 5 3 2 Data Lane HS TX Signaling Requirements Group 3 Amplitude V Da p Dad TEFA Fig 3 20 Typical result of a data lane T_LPX measurement This figure shows a failure case T_LPX lt 50 ns Datp Waveform of Data Vpp Datn Waveform of Data Vpn Datd Differential waveform Vpp Vpn T_LPX Duration of last LP 01 state immediately before HS transmission This test case is tested for Zip 100 ohms only and for all data lanes Test 1 3 2 Data Lane HS Entry Data Lane Tys_prepare Value The purpose of this test case is to verify that the duration of the last LP 00 state imme diately before H
60. ith a cut off frequency of 2 0 MHz is required to remove high frequency noise from the inverse Ul values By using the inverse UI values as the input to the filter the resulting output is conver ted to units of percent to generate AUI values To explain this A set of AUI values is acquired from the formula AUlsampie Ulsampie Ulaveragel Ulaverage 100 hence rendering relative values Finally the peak maximum and peak minimum values are identified and compared with each other to find the greater absolute value This is reported as the final result of AUI This test case is tested for Zi 100 ohms only and for all clock lanes 3 HS TX Clock to Data Lane Timing Requirements Group 5 The purpose of Group 5 test cases is to verify the various requirements regarding clock lane to data lane timing Test Procedures 1326 1010 02 02 88 3 7 1 HS TX Clock to Data Lane Timing Requirements Group 5 Group 5 consists of four test cases described in chapter 3 7 3 Measurements on page 93 This group of test cases is only applicable to master devices The software is intended to facilitate the execution of a set of several HS TX measure ments on a set of captured HS burst waveforms This version of the ScopeSuite MIPI D PHY compliance test software only processes data burst waveforms also known as non continuous data waveforms It does not support partial data burst where HS Entry and HS Exit are captured
61. l m m m m e e d w m mees Amplitude V n E I li TAI Time ns CLK D DATAP DATAN DATAD TCLK POST Fig 3 60 Typical result of a measurement of the duration T CLK POST 3 7 3 3 3 7 3 4 HS TX Clock to Data Lane Timing Requirements Group 5 CLK D Waveform of Clock Vpp DATA P Waveform of Data Vpp DATA N Waveform of Data Vpn DATA D Differential waveform Vpp Von T CLK POST Duration of HS clock signaling after the last data lane switches from LP to HS mode Test 1 5 3 HS Clock Rising Edge Alignment to First Payload Bit The purpose of this test case is to verify that the DUT s high speed clock is properly aligned to the payload data signaling The first payload bit of the burst data should align with a rising edge of the DDR clock The software checks if the first payload bit of burst data i e the first bit after the Sync byte aligns with a rising edge of the DDR clock A PASS result is shown in fig ure 3 61 Amplitude V Time ns LIED DATAD First Payload Bit Fig 3 61 Testing the alignment of the first data bit with a rising edge of the clock CLK D Waveform of Clock Vpp DATA D Differential waveform Vpp Vpn Test 1 5 4 Data to Clock Skew Tsxewrrx The purpose of this test case is to verify that the skew between the clock and data sig naling as measured at the transmitter Ts gwrrxj is within the conform
62. load Image 24 bpp 8 8 8 RGB V Size 480 pixels 50 100 150 200 250 300 Line Width 320 pixels gt Fig 3 39 Example reference HS test pattern RGB888 format courtesy MIPI Alliance D PHY specs Settings in the HS Configuration dialog box See also chapter 3 2 Test Configuration for D PHY on page 18 Zp If Zip is 100 ohms the pair of clock lanes clk and clk has to be terminated with the 100 ohms loads on the RTB If Zip is 80 or 125 ohms the pair of clock lanes under test has to be terminated with the 80 or 125 ohms loads on the RTB e Clock Format Group 4 test cases do no support Differential clock format Therefore the clock format setting has to be Single Ended If this is not the case the Differential clock format setting will be changed by the software to Single Ended clock for mat Use either two single ended probes or two differential probes in the Single Ended clock format Clock Lane HS TX Signaling Requirements Group 4 3 6 2 Performing Group 4 Test Cases Start running the tests as described in chapter 3 1 Starting D PHY Compliance Tests on page 17 Select Clock Lane HS TX Signaling Requirements Group 4 E RSScopeSuite Select Test Case gt D PHY Test 9 an Data Lane LP TX Signaling Requirements Group 1 Clock Lane LP TX Signaling Requirements Group 2 Data Lane HS TX Signaling Requirements Group 3 Clock Lane H
63. mp S RTO on page 7 Starting the R amp S ScopeSuite To start the R amp S ScopeSuite on the test computer or on the oscilloscope gt Double click the R amp S ScopeSuite program icon To start the R amp S ScopeSuite on the instrument in the R amp S RTO firmware On the Analysis menu tap Start Compliance Test Connecting the R amp S RTO If the R amp S ScopeSuite is installed directly on the instrument the software detects the R amp S RTO firmware automatically and the Oscilloscope tab is not available in the R amp S ScopeSuite If the R amp S ScopeSuite software runs on a test computer the computer and the testing R amp S RTO require a LAN connection see chapter 1 3 Setting Up the Network on page 6 The R amp S ScopeSuite software needs the IP address of the R amp S RTO to establish connection 1 Start the R amp S RTO 2 Start the R amp S ScopeSuite software 3 Click Instrument Settings Connecting the R amp S RTO Rohde amp Schwarz Scope Suite G Instrument Settings Compliance Test Settings 4 Click the Oscilloscope tab 5 Enter the IP address of the R amp S RTO To obtain the IP address Press the SETUP key on the instrument and tap the System tab 6 Click Get Instrument Information The computer connects with the instrument and gets the instrument data Connecting the R amp S RTO Instrument Settings Vector Network Analyzer Spectrum Analyzer Oscilloscope Arbit
64. nd repeats the test case Use this function if operat ing errors occured Next Finishes the test case writes the results to the measurement report and goes to the next test case of the test cycle Abort Cancels the test cycle and returns to the start window of the test Getting Test Results For each test the test data report diagrams and waveform files is saved in the fol lowing folder Getting Test Results ProgramData Rohde Schwarz RSScopeSuite Sessions lt Protocolgroup gt lt Protocol gt lt Session Name gt If you resume an existing session new measurements are appended to the report new diagrams and waveform files are added to the session folder Existing files are not deleted or replaced Sessions data remain until you delete them in the Report Man agement dialog box The report format and content is configured in Test Configuration gt Report Configu ration All reports are listed in the Report Management dialog box Reports can be provided in PDF RTF or HTML format To view and print PDF reports you need a PDF viewer for example the Acrobat Reader The configured report file can be created directly at the end of the test cycle or later in the Report Management dialog box To show a test report In the R amp S ScopeSuite window select the compliance test to be performed 2 Click Report Management 3 Select the session name in the Reports list and click Show 4 If
65. ne HS TX Signaling Requirements Group 3 highpass filter with a cutoff frequency of 450 MHz The value of AVowtxHF is measured as the RMS voltage at the output of the highpass filter FI nm p T T T T AI 0 02 V CMTX HF 6 28 mV_RMS Amplitude V T TT lila bcd iyi aii Time us V CMTX HF V CMTX HF RMS Fig 3 30 Typical result of a data lane HS transmit dynamic common level variations measurement at high frequencies V CMTX HF This test case is tested for Zip 100 ohms only and for all data lanes Test 1 3 11 Data Lane HS TX 20 80 Rise Time tg The purpose of this test case is to verify that the 20 80 rise time is e between 150 ps and 0 3 UI when operating at HS bit rates up to 1 Gbps e between 100 ps and 0 35 UI when operating at HS bit rates greater than 1 Gbps To measure the 20 80 rise time tr the software searches for reference waveforms with the data pattern 000111 in the HS transmission differential data signal Three cases are to be distinguished e fthere is no occurrence of 000111 the software marks tr as indeterminable and proceeds with the next test case e fthere are less than 128 occurrences of 000111 the software does still process the reference waveforms However the test results may be invalid in this case it is recommended to use a different test pattern and then redo the test e lf there are 128 or more occurrences of 000111 the software proc
66. necting the R amp S RIO weiner ennenen eee eee ee 7 ME ney 165 Buan de 10 2 1 Configuring the Test sss sss s esse sees enesenn eenn eee 10 2 1 1 General Test Settings eee eee 11 22 Controlling Test Cycles sssss sees sees 12 23 Getting Test RESUMES a u iieri artnet c eap edant vie we 13 3 D PHY Compliance T6Ss s iciessivexi ins auc ka EA RIEN ERR NERA SS REB ee 15 3 1 Starting D PHY Compliance TestS rrrrnnnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnevnnnnnnnnnnnnnnnnnnrnnnnnennn 17 3 2 Test Configuration for D PPH Y ss ssssssssss sees sees v tou edP vu eenn enen 18 3 3 Data Lane LP TX Signaling Requirements Group 1 21 oe TEN 21 3 3 2 Performing Group 1 Test Cases eee eee 23 ENN 24 3 4 Clock Lane LP TX Signaling Requirements Group 2 31 K a WSN o NM TR n 31 3 4 2 Performing Group 2 Test Cases eee eee 32 343 ISAS URSIN EE EE 34 3 5 Data Lane HS TX Signaling Requirements Group 3 40 ST TS 1 00 40 3 5 2 Performing Group 3 Test Cases e eee eee eee eee 44 T NENNE 45 3 6 Clock Lane HS TX Signaling Requirements Group 4 62 01 VTS lt 63 3 6 2 Performing Group 4 Test CASS si ces diem eee 67 3603 NENNE 68 3 7 HS TX Clock to Data Lane Timing Requirements Group 5
67. of last LP 00 state immediately before HS transmission T CLK ZERO Duration of the CLK ZERO state immediately before clock transmission This test case is tested for Zip 100 ohms only and for all clock lanes Test 1 4 4 Clock Lane HS TX Differential Voltages Vop o and Vopu The purpose of this test case is to verify that e the clock lane HS transmit differential 0 voltage Vona is between 140 mV and 270 mV and e the clock lane HS transmit differential 1 voltage V onu is between 140 mV and 2 0 mV Vopio TO measure the clock transmit differential O voltage the software searches for reference waveforms with the data pattern 10 in the clock transmission differential data signal Four cases are to be distinguished e If there is no occurrence of 10 the software marks Vop o as indeterminable and proceeds with the next measurement Vop 1 e fthere are less than 128 occurrences of 10 the software does still process the reference waveforms However the test results may be invalid in this case it is recommended to use a different test pattern and then redo the test Clock Lane HS TX Signaling Requirements Group 4 e For the clock type of partial clock burst and continuous clock if there are less than 128 occurrences of 10 the software does still process the reference waveforms However the test results may be invalid in this case it is recommended to modify the time base of the osc
68. ple is shown in figure 3 59 that represents a PASS result To pae 242 9 ns which is much greater than the minimum required value of 8 Ul 11 2 ns with Ul 1 4 ns AO RA v TM S me ra wi k yi ith M d M Amplitude V 1 5 Time ns CLK D DATAP DATAN DATAD TCLK PRE Fig 3 59 Typical result of a measurement of the duration T_CLK PRE 3 7 3 2 HS TX Clock to Data Lane Timing Requirements Group 5 CLK D Waveform of Clock Vpp DATA P Waveform of Data Vpp DATA N Waveform of Data Vpn DATA D Differential waveform Vpp Von T CLK PRE Duration of HS clock signaling prior to a data lane transition from LP to HS mode Test 1 5 2 HS Exit Te k rpost Value The purpose of this test case is to verify that the DUT s clock lane high speed transmit ter continues to transmit clock signaling for the minimum required duration Tc k post after the last data lane switches from high speed to low power mode Tc pos1 IS required to last no shorter than 60 ns 52 UI The state is measured e beginning at the end of the data lane Tus trai period and e ending at the he start of the clock lane To k tra period An example is shown in figure 3 60 that represents a PASS result To post 180 5 ns which is greater than the minimum required value of 60 ns 52 UI 132 8 ns with Ul 1 4 ns e m m m m m m la m m m m m m m m m m m m m m m m m
69. processes the last 128 reference waveforms An average waveform is then constructed by horizontally aligning 128 or less refer ence waveforms to a common anchor point which is the zero crossing time of the first transition Once the average waveform is obtained the value of tz is measured as the time taken for the waveform to rise from Vopo 0 2 V anr Vono to Vono 0 8 Von ty Vop oyl 123 01 mV Amplitude V Fig 3 51 Typical result of a clock lane HS transmit 20 80 rise time measurement Vop Clock lane high speed transmission differential data signal Von Clock lane HS transmit differential 0 voltage Vann Clock lane HS transmit differential 1 voltage tr Rise time This test case is executed for all three cases of Zn 100 ohms 80 ohms and 125 ohms as well as for all clock lanes Test 1 4 12 Clock Lane HS TX 80 20 Fall Time tp The purpose of this test case is to verify that the 80 20 fall time is e between 150 ps and 0 3 UI when operating at HS bit rates up to 1 Gbps e between 100 ps and 0 35 UI when operating at HS bit rates greater than 1 Gbps Clock Lane HS TX Signaling Requirements Group 4 To measure the 80 20 fall time te the software searches for reference waveforms with the data pattern 10 in the clock lane HS transmission differential data signal Four cases are to be distinguished If there is no occurrence of 10 the software marks tp as indetermin
70. r slightly depending on the clock format and the termina tions which are applied to the DUT When you have finished all steps the compliance test runs automatically Further steps chapter 2 3 Getting Test Results on page 13 Measurements e Test 1 3 1 Data Lane HS Entry Data Lane T py Value 45 e Test 1 3 2 Data Lane HS Entry Data Lane Tys prepare Value 46 e Test 1 3 3 Data Lane HS Entry Data Lane Tys prepare Tus zero Value 47 e Test 1 3 4 Data Lane HS TX Differential Voltages Vop o and Vopq 48 e Test 1 3 5 Data Lane HS TX Differential Voltage Mismatch AVop 50 e Test 1 3 6 Data Lane HS TX Single Ended Output Voltages Vokkspr and ETE ENE EEE EE 50 e Test 1 3 7 Data Lane HS TX Static Common Mode Voltages Vomrx 1 and Vemrxo aoe 52 e Test 1 3 8 Data Lane HS TX Static Common Mode Voltage Mismatch AVoyrx o 54 e Test 1 3 9 Data Lane HS TX Dynamic Common Level Variations Between EE TE RE EE HEE 54 e Test 1 3 10 Data Lane HS TX Dynamic Common Level Variations Above E TDI REE TE nq E SSIDM EH E HUN Md 55 e Test 1 3 11 Data Lane HS TX 20 80 Rise Time a e eee eee 56 e Test 1 3 12 Data Lane HS TX 80 20 Fall Time e s sees eee 57 e Test 1 3 13 Data Lane HS Ex
71. rary Waveform Generator Oscilloscope IP address 10 113 10 30 Get Instrument Information Device RTO Serial Number 100007 Firmware Version 2 15 7 0 Cancel If the connection fails an error message is shown T Click Save Configuring the Test 2 Performing Tests 2 1 Configuring the Test 1 Inthe R amp S ScopeSuite window select the compliance test to be performed e D PHY 2 Click Configuration Compliance Test Configuration Limit Editor Report Management 3 Click the User Input tab and enter common information on the test See e chapter 2 1 1 1 User Input on page 11 4 Click the LP Configuration and HS Configuration tabs Then for each of them 5 Check and adjust the configuration settings See e chapter 3 2 Test Configuration for D PHY on page 18 6 Select the Report Configuration tab to define the format and contents of the report See e chapter 2 1 1 2 Report Configuration on page 11 7 Click OK 8 Click Limit Editor Configuring the Test 9 Select the Test Type in the lower left corner of the dialog box and check the mea surement limits See e chapter 2 1 1 3 Limit Editor on page 12 10 Click Start Test and proceed as descibed in the relevant test case chapter 2 1 1 General Test Settings 2 1 1 1 User Input On the User Input tab you enter common information on the test This information is written to the test r
72. re supports clock burst partial clock burst and continuous clock These test cases are applicable to master devices only 3 5 1 Test Setup Table 3 4 Equipment for Group 3 Data Lane HS TX Signaling Requirements test Rohde amp Schwarz oscilloscope R amp S RTO1044 or equivalent 4 GHz Probes Differential probes R amp S RT ZD40 or 2 3 4 Single ended probes R amp S RT ZS60 Test fixture UNH IOL MIPI D PHY Reference Termination Board RTB DUT Any MIPI D PHY CSI 2 or DSI device Test Procedures 1326 1010 02 02 40 R amp S RTO K26 D PHY Compliance Tests Regarding the selection of probes there are three different configuration scenarios e No clock If in the HS configuration dialog Zip has been selected to be 80 ohms or 125 ohms 2 probes are required either single ended or differential in single ended mode Differential clock If in the HS configuration dialog the Clock Format has been selected to be Differ ential 3 probes are required 1 differential probe and 2 additional probes the latter 2 either single ended or differential in single ended mode Single ended clock If in the HS configuration dialog the Clock Format has been selected to be Sin gle Ended 4 probes are required either single ended or differential in single ended mode 1 We recommend to use a MIPI D PHY Reference Termination Board RTB test fixture from the University of New Hampshire InterOperability Laboratory U
73. robes or two differential probes and clock signals either two single ended probes or one differential probe are captured by the RTO and processed by the software This setting depends on the probes that are used to capture the clock signals Select the clock format Single Ended when using two single ended probes or two differential probes in single ended mode Select the clock format Differential when using one differential probe 3 2 Performing Group 5 Test Cases 1 Start running the tests as described in chapter 3 1 Starting D PHY Compliance Tests on page 17 HS TX Clock to Data Lane Timing Requirements Group 5 2 Select HS Clock To Data Lane Timing Requirements Group 5 d RSScopeSuite Select Test Case D PHY Test Data Lane LP TX Signaling Requirements Group 1 Clock Lane LP TX Signaling Requirements Group 2 Data Lane HS TX Signaling Requirements Group 3 Clock Lane HS TX Signaling Requirements Group 4 HS Clock To Data Lane Timing Requirements Group 5 HS Entry T CLK PRE Value 1 5 1 HS Exit T CLK POST Value 1 5 2 HS Clock Rising Edge Alignment to First Payload Bit 1 5 3 Return To Main Menu 3 Click Start 4 The Test Cycle dialog box shows the status of the test cases included in the test cycle and marks the next case to be done see chapter 2 2 Controlling Test Cycles on page 12 Click Run This group of tests uses the MIPI D PHY Reference Termination Boar
74. s of the differential clock lane waveform the Uliygr are computed R amp S9RTO K26 D PHY Compliance Tests All acquired HS Uls are processed to determine their maximum minimum and average values Ulinst max Ulinst min and Uliysr AvERAGE The computed Ulinst max must be less than 12 5 ns The computed Ulinst averaGE Must not be less than the specified Ulinst min value as obtained from the vendor or from the datasheet This test case is tested for Zi 100 ohms only and for all clock lanes 3 6 3 18 Test 1 4 18 Clock Lane HS Clock Delta Ul AUI Value The purpose of this test is to verify that the Delta Ul AUI values of the DUT high speed clock meet the following requirement e The peak AUI is between 5 and 5 of the unit interval Ul duration at HS bit rates up to 1 Gbps e The peak AUI is between 10 and 10 of the unit interval Ul duration at HS bit rates above 1 Gbps The software measures the AUI values as follows A sample of the DUT s HS clock signaling is captured The difference of the positive and negative single ended clock lane waveforms Vpp Vpn is computed to acquire the differential clock lane waveform The differences between successive 0 V crossing times of the differential clock lane waveform are measured as Ul values The instantaneous bitrate of the clock transmitter is determined as the inverse value of the computed Ul values Additionally a 279 order Butterworth low pass filter w
75. s only applicable for Group 3 and 4 test cases Clock Format e Select Single Ended if using two single ended probes or two differential probes in single ended mode for the clock lane e Select Differential if using one differential probe for the clock lane This selection is only applicable for Group 3 and 5 test cases Use Previous Settings Check this if you want to use the previous settings which include trigger conditions vertical scale and horizontal time scale for a new execution of the same group of test cases with the same configurations If this is not checked the software will e incase of LP configuration use the pre defined trigger conditions vertical scale and horizontal time scale e incase of HS configuration go through a set of pre defined routines to determine the best trigger conditions and horizontal time scale DUT Defines if the DUT is a camera CSI 2 or display DSI Bitrate DUT If the bitrate of the DUT is known enable Bitrate and enter the bitrate value in Mbps This is useful if the signal is noisy This selection is only applicable for Group 3 test cases Test Procedures 1326 1010 02 02 20 R amp S9RTO K26 D PHY Compliance Tests Clock Type Bitrate DUT If the DUT has a burst or non continuous clock select Normal Burst If the DUT has a partial burst clock select HS Entry and Exit If the DUT has a continuous clock select All Continuous Low Pass Fil
76. se a different test pattern and then redo the test e For the clock type of partial clock burst and continuous clock if there are less than 5000 occurrences of 1 the software does still process the reference waveforms However the test results may be invalid in this case it is recommended to modify Clock Lane HS TX Signaling Requirements Group 4 the time base of the oscilloscope to acquire more waveforms and then redo the test e lf there are 5000 or more occurrences of 1 the software processes all of them For every occurrence of 1 that the software can find in the differential signal it com putes the HS transmitter static common mode voltage according to the formula men tioned above The value of Vowrx 1 is measured as the average of these common mode voltages 25 LL E Q D 2 a E EE qt 01 0 Time ns V CMTX 1 Mean Fig 3 47 Typical result of a clock lane HS transmit differential 1 static common mode voltage mea surement V_CMTX 1 Vcurx oy The software measures the HS transmit differential 0 static common mode voltage in a similar way as Veytx 1 One exception is e It searches for all occurrences of bit O instead of bit 1 3 6 3 8 3 6 3 9 Clock Lane HS TX Signaling Requirements Group 4 0 15 DEINER 0 05 o Time ns Amplitude V V_CMTX 0 Mean Fig 3 48 Typical result of a clock lane HS transmit differential 0
77. separately or continuous data However the software supports clock burst partial clock burst and continuous clock Test Setup Table 3 6 Equipment for Group 5 HS TX Clock to Data Lane Timing Requirements test tem Reanna ay Probes Differential probes R amp S RT ZD40 or 3 4 ee Single ended probes R amp S RT ZS60 Any MIPI D PHY CSI 2 or DSI device In this group of tests sampling the clock signal requires either 2 single ended probes or 1 differential probe Sampling the data signal requires 2 probes either single ended or differential used in single ended mode Hence in total either 4 single ended probes or 3 differential probes or combinations thereof are required We recommend to use a MIPI D PHY Reference Termination Board RTB test fixture from the University of New Hampshire InterOperability Laboratory UNH IOL Refer to https www iol unh edu services test ing mipi fixtures php or https www iol unh edu services testing mipi UNH IOL MIPI D PHY RTB Data sheet 20090421 pdf for details R amp S RTO K26 D PHY Compliance Tests Pr HS get iy r Kal pa T ne kun qo of Jer z LEUR a0 ik nc aill ES G lar fu Er sif z nms UI zr il zit liti i d ali ghi si g N E E Box Wi Wie i m a Uil 6 di g 2i Zr E 3 ii iil amp 9i3 i w Mg S i me t t kel XE nr LE TERMI NAT N BOARD mm ev e 0 pau Fig 3 57 MIPI D PHY Reference Termination Board test fixture
78. software compiles a list of HS transmit static common voltage voltages for every zero crossing of the clock signal using the formula stated in chapter 3 5 3 7 Test 1 3 7 Data Lane HS TX Static Common Mode Voltages Veur and Voyrx o on page 52 This list will be used as the input to an 8 order Butterworth bandpass fil ter with cutoff frequencies of 50 MHz and 450 MHz respectively The value of AVcwrx Lr Is measured as the absolute peak voltage at the output of the bandpass fil ter 0 015 NNNM 0 005 I BON il Vi yt gt Qo OD 0 a E m m IMPR WC 0 015 Time us V CMTX LF V CMTX LF PEAK Fig 3 29 Typical result of a data lane HS transmit dynamic common level variations measurement at low frequencies V CMTX LF This test case is tested for Zip 100 ohms only and for all data lanes 3 5 3 10 Test 1 3 10 Data Lane HS TX Dynamic Common Level Variations Above 450 MHz AV cutx HF The purpose of this test case is to verify that the common level variation above 450 MHz is not more than 15 mV pus The common level variation above 450 MHz AVcoyrx ue is measured as follows The software uses the same list of HS transmit static common voltage voltages from chapter 3 5 3 9 Test 1 3 9 urs Lane HS TX Dynamic Common Level Variations Between 50 450 MHz AVcourtxur on page 54 as the input to an 8 order Butterworth Test Procedures 1326 1010 02 02 55 3 5 3 11 Data La
79. static common mode voltage mea surement V_CMTX 0 This test case is executed for all three cases of Zn 100 ohms 80 ohms and 125 ohms as well as for all clock lanes Test 1 4 8 Clock Lane HS TX Static Common Mode Voltage Mismatch AVcmrtx 1 0 The purpose of this test is to verify that the clock lane HS transmit static common mode voltage mismatch is between 5 mV and 5 mV Using the values obtained in chapter 3 6 3 7 Test 1 4 7 Clock Lane HS TX Static Common Mode Voltages Veurs and Voyrx o on page 76 the software computes the clock lane HS transmit static common mode voltage mismatch AVeytx 1 0 according to this formula AVcomrx1 0 AVemrxa 7 AVemtx oy 2 This test case is executed for all three cases of Zn 100 ohms 80 ohms and 125 ohms as well as for all clock lanes Test 1 4 9 Clock Lane HS TX Dynamic Common Level Variations Between 50 450 MHz AVcwrx LF The purpose of this test case is to verify that the common level variation between 50 450 MHz is not more than 25 MVpegax R amp S9RTO K26 D PHY Compliance Tests The common level variation between 50 450 MHz AVoyrxqr is measured as follows The software compiles a list of clock lane HS transmit static common voltage voltages for every zero crossing of the clock signal using the formula stated in chapter 3 6 3 7 Test 1 4 7 Clock Lane HS TX Static Common Mode Voltages Vuran and Vomrx o on page 76 This list will be used as the input to an
80. sured as the mode of all waveform samples that are less than 50 of the absolute peak to peak Vpp and Vpy signal amplitudes and across all LP 0 states in a single LP Escape Mode sequence A ULPS Entry sequence is specified for this test The measurement is performed sepa rately on both Vpp and Vpy clock waveforms An example is shown in figure 3 12 Test 1 2 3 Clock Lane LP TX 15 85 Rise Time Tg p The purpose of this test case is to verify the 1596 8596 Rise Time Tg p of the DUT s clock lane LP transmitter is within the conformance limits The conformance range for Tryp IS less than 25 ns Using the measured Voy and Vo LP TX Thevenin Output Voltage Levels as referen ces the 15 85 rise time Tp p is measured independently for the rising edges of the Vpp and Vpn waveforms A ULPS Exit sequence is specified for this test The mea surement is performed separately on both Vpp and Vpn clock lane waveforms Examples are shown in figure 3 13 and figure 3 14 Clock Lane LP TX Signaling Requirements Group 2 VDP LP 15 85 Rise Time and Slew Rate First Rise Edge S Q KZ a E lt Time ns VDP Signal VDP VOL Slew Rate High Limit High Threshold Time Start Time End in VDP VOH Slew Rate Slew Rate Low Limit Low Threshold Fig 3 13 Typical result of a clock lane LP TX 15 85 rise time and slew rate measurement for V DP 3 4 3 4 Clock Lane
81. t case to be done see chapter 2 2 Controlling Test Cycles on page 12 Click Run This group of tests uses the MIPI D PHY Capacitive Load C oap test fixture from the UNH IOL The C oan fixture provides 50 pF capacitive load 5 Follow the instructions of the step by step guide Group 1 of test cases requires 2 setup steps The data signals can be tapped on the DUT or the C opp or even the SMA cables between the DUT and the C opp 3 3 3 3 3 3 1 Data Lane LP TX Signaling Requirements Group 1 Switch the probes to tap a specific pair of data lanes under test if the DUT imple ments multiple data lanes When you have finished all steps the compliance test runs automatically Further steps e chapter 2 3 Getting Test Results on page 13 Measurements e Test 1 1 1 Data Lane LP TX Thevenin Output High Level Voltage Vo 24 e Test 1 1 2 Data Lane LP TX Thevenin Output Low Level Voltage Vo 25 e Test 1 1 3 Data Lane LP TX 15 85 Rise Time Tg p 25 e Test 1 1 4 Data Lane LP TX 85 15 Fall Time Tg p 27 e Test 1 1 5 Data Lane LP TX Slew Rate vs C oAp OV Otag 29 e Test 1 1 6 Data Lane LP TX Pulse Width of Exclusive OR Clock T p pui se tx ENN EE 29 e Test 1 1 7 Data Lane LP TX Period of Exclusive OR Clock T p pgp r
82. ter If Low Pass Filter is enabled the software applies a 4 order Butterworth low pass filter with a cutoff frequency of 400 MHz to the input signal as required in the MIPI Alli ance Specification for D PHY version 1 1 Keep this option enabled as some meas urements are very sensitive to high frequency noise Export Waveform Enable Export Waveform to export the captured waveforms The exported waveform files are stored in the current session folder in ProgramData Rohde Schwarz RSScopeSuite Sessions DPHY D PHY lt Session Name gt 3 3 Data Lane LP TX Signaling Requirements Group 1 The purpose of Group 1 test cases is to verify various requirements specific to data lane low power LP signaling Group 1 consists of seven test cases described in chapter 3 3 3 Measurements on page 24 They perform related LP TX measurements on a single data lane LP transmit waveform sequence The software is intended to facilitate the execution of a set of LP TX measurements on a pair of captured LP data lane waveforms with ULPS Entry sequence These test cases are typically performed on CSI 2 and DSI Master devices only 3 3 1 Test Setup Table 3 2 Equipment for Group 1 Data Lane LP TX Signaling Requirements test Rohde Rohde amp Schwarz oscilloscope Schwarz Rohde amp Schwarz oscilloscope R amp S RTO1044 or equivalent 4GH2 RTO1044 or equivalent R amp S RTO1044 or equivalent 4GH2 GHz Probes Differential probes R
83. test cycle After each completed test its results are displayed in the Test Case Result dialog box 2 3 Getting Test Results B R Scopesuite Test Case Result m D PHY Data Lane HS TX Signaling Requirements Test Result Test Description 1 3 0 Clock Information 1 3 1 Data Lane HS Entry T LPX Value 1 3 2 Data Lane HS Entry T HS PREPARE Value 13 3 Data Lane HS Entry T HS PREPARE T HS ZERO Value 1 3 4 Data Lane HS TX Differential Voltages 1 3 5 Data Lane HS TX Differential Voltage Mismatch 1 33 6 Data Lane HS TX Single Ended Output High Voltages 1 3 7 Data Lane HS TX Static Common Mode Voltages 13 8 Data Lane HS TX Static Common Mode Voltages Mismatch 1 338 Data Lane HS TX Dynamic Common Level Variations Between 50 450 MHz 13 10 Data Lane HS TX Dynamic Common Level Variations Above 450 MHz 1 3 11 Data Lane HS TX 20926 8095 Rise Time 1 312 Data Lane HS TX 80926 2096 Fall Time 1 3 13 Data Lane HS Exit T HS TRAIL Value 13 14 Data Lane HS Exit 3075 8576 Post EoT Rise Time 1 3 15 Data Lane HS Exit T EOT Value 1 3 16 Data Lane HS Exit T HS EXIT Value 00000000000000000 Repeat Repeat Here you decide how to continue the test cycle Repeat Keep Previous Repeats the test case and writes the results to the measurement report as often as required Use this function for debugging during develeopment and for stability tests after interface integration Repeat Discard Previous Deletes the measurement results a
84. testing R amp S RTO require a LAN connection For some test cases you need an additional instrument arbitrary waveform generator ARB vector network analyzer VNA or spectrum analyzer These instruments can be used in automatic or manual mode For automatic testing a LAN connection to the additional instrument is required There are two ways of connection e LAN local area network It is recommended that you connect to a LAN with DHCP server This server uses the Dynamic Host Configuration Protocol DHCP to assign all address information automatically If no DHCP server is available or if the Tabor WX2182B is used for automatic test ing assign fixed IP adresses to all devices e Direct connection of the instruments and the computer or connection to a switch using LAN cables Assign fixed IP addresses to the computer and the instruments and reboot all devices To set up and test the LAN connection 1 Connect the computer and the instruments to the same LAN Start all devices If no DHCP server is available assign fixed IP addresses to all devices Ping the instruments to make sure that the connection has been established gb GR If VISA is installed check if VISA can access the instruments a Start VISA on the test computer b Validate the VISA address string of each device Test Procedures 1326 1010 02 02 6 1 4 1 5 Starting the R amp S ScopeSuite See also e chapter 1 5 Connecting the R a
85. tial 0 voltage Vana is between 140 mV and 270 mV and e the HS transmit differential 1 voltage Vop 1 is between 140 mV and 270 mV Vopio TO measure the HS transmit differential O voltage the software searches for ref erence waveforms with the data pattern 100000 in the HS transmission differential data signal Three cases are to be distinguished e If there is no occurrence of 100000 the software marks Vop as indeterminable and proceeds with the next measurement V anan Data Lane HS TX Signaling Requirements Group 3 e If there are less than 128 occurrences of 100000 the software does still process the reference waveforms However the test results may be invalid in this case it is recommended to use a different test pattern and then redo the test e lf there are 128 or more occurrences of 100000 the software processes the last 128 reference waveforms The reason for this procedure is this In some cases transient effects introduced by some high impedance probes can introduce a small error in the HS common mode level at the beginning of the transmission This error can be significant enough to affect the test result Therefore an average waveform is constructed by horizontally aligning 128 or less reference waveforms to a common anchor point which is the zero cross ing time of the first transition The value of Vop is then determined from that average waveform it is the mean of all
86. transmit static common mode voltage is defined in the specification as the arithmetic mean of the value of the voltages at Dp and Dy Vemrx Vpp Vpn 2 R amp S9RTO K26 D PHY Compliance Tests Vemrxa The software measures the HS transmit differential 1 static common mode voltage by searching for all occurrences of bit 1 in the HS transmission differential data signal Two cases are to be distinguished e fthere are less than 5000 occurrences of 1 the software does still process the bits However the test results may be invalid it is recommended to use a different test pattern and then redo the test e lf there are 5000 or more occurrences of 1 the software processes all of them For every occurrence of 1 that the software can find in the differential signal it com putes the HS transmitter static common mode voltage according to the formula men tioned above The voltages Vpp and Vpn of all the 1 bits are taken at the correspond ing clock zero crossings The value of Vowrx1 is measured as the average of these common mode voltages 0 15 Amplitude V 0 05 m a a TE PT AAI PETAI IL i Ju 1 Time ns V CMTX 1 Mean Fig 3 27 Typical result of a data lane HS transmit differential 1 static common mode voltage mea surement V CMTX 1 Vcurx o The software measures the HS transmit differential 0 static common mode voltage in a similar way as Vowrtx1 One exception is
87. vel variations measurement at high frequencies V CMTX HF This test case is tested for Zi 100 ohms only and for all clock lanes Test 1 4 11 Clock Lane HS TX 2095 8094 Rise Time tp The purpose of this test case is to verify that the 20 80 rise time is e between 150 ps and 0 3 UI when operating at HS bit rates up to 1 Gbps e between 100 ps and 0 35 UI when operating at HS bit rates greater than 1 Gbps To measure the 20 80 rise time tr the software searches for reference waveforms with the data pattern 01 in the clock lane HS transmission differential data signal Four cases are to be distinguished e lf there is no occurrence of 01 the software marks tr as indeterminable and pro ceeds with the next test case e fthere are less than 128 occurrences of 01 the software does still process the reference waveforms However the test results may be invalid in this case it is recommended to use a different test pattern and then redo the test e For the clock type of partial clock burst and continuous clock if there are less than 128 occurrences of 01 the software does still process the reference waveforms However the test results may be invalid in this case it is recommended to modify 3 6 3 12 Clock Lane HS TX Signaling Requirements Group 4 the time base of the oscilloscope to acquire more waveforms and then redo the test e lf there are 128 or more occurrences of 01 the software
88. w power LP signaling Group 2 consists of five test cases described in chapter 3 4 3 Measurements on page 34 They perform related LP TX measurements on a single clock lane LP transmit waveform sequence The software is intended to facilitate the execution of a set of LP TX measurements on a pair of captured LP clock lane waveforms with ULPS Entry and Exit sequence These test cases are typically performed on CSI 2 and DSI Master devices only Test Setup Table 3 3 Equipment for Group 2 Clock Lane LP TX Signaling Requirements test Rohde Rohde amp Schwarz oscilloscope Schwarz Rohde amp Schwarz oscilloscope R amp S RTO1044 or equivalent 4GH2 RTO1044 or equivalent R amp S RTO1044 or equivalent 4GH2 GHz Probes Differential probes R amp S RT ZD40 or Single ended probes R amp S RT ZS60 Test fixture UNH IOL MIPI D PHY Capacitive Load C oan o3 n this group of tests sampling the signals requires 2 probes either single ended or differential used in single ended mode We recommend to use a MIPI D PHY Capacitive Load C oap test fixture from the University of New Hampshire InterOperability Laboratory UNH IOL Refer to https www iol unh edu services testing mipi fixtures php for details Test Procedures 1326 1010 02 02 31 R amp S RTO K26 D PHY Compliance Tests Fig 3 11 MIPI D PHY Capacitive Load test fixture from UNH IOL Waveform Requirements Group 2 test
89. x 31 Test 1 1 1 Data Lane LP TX Thevenin Output High Level Voltage Voi The purpose of this test case is to verify that the Thevenin Output High Level Voltage Vou of the DUT s data lane LP transmitter is within the conformance limits The con formance range for Vo is between 1 1 and 1 3 Volts Vou is measured as the mode of all waveform samples which are greater than 50 of the absolute peak to peak Vpp and Vpn signal amplitudes and across all LP 1 states in a single LP Escape Mode sequence A ULPS Entry sequence is specified for this test The measurement is performed sepa rately on both Vpp and Vpn waveforms for each data lane An example is shown in figure 3 4 3 3 3 2 3 3 3 3 Data Lane LP TX Signaling Requirements Group 1 2014 10 07 11 24 19 a s Fig 3 4 Typical result of a data lane LP TX Thevenin output High Level and Low Level voltage mea surement Test 1 1 2 Data Lane LP TX Thevenin Output Low Level Voltage VoL The purpose of this test case is to verify that the Thevenin Output Low Level Voltage VoL of the DUT s data lane LP transmitter is within the conformance limits The con formance range for Vo is between 50 and 50 mV Vo is measured as the mode of all waveform samples which are less than 50 of the absolute peak to peak Vpp and Vpy signal amplitudes and across all LP O states in a single LP Escape Mode sequence A ULPS Entry sequence is specifi
90. x 1 1 7 Data Lane LP TX Period of Exclusive OR Clock T p_per tx Group 2 5 tests Clock Lane LP TX Signaling Requirements 1 2 1 Clock Lane LP TX Thevenin Output High Level Voltage Voy 1 2 2 Clock Lane LP TX Thevenin Output Low Level Voltage Vo 1 2 3 Clock Lane LP TX 1596 8596 Rise Time Tg p 1 2 4 Clock Lane LP TX 8596 1596 Fall Time Tg p 1 2 5 Clock Lane LP TX Slew Rate vs C gap OV OtsR Group 3 16 tests Data Lane HS TX Signaling Requirements 1 3 1 Data Lane HS Entry Data Lane T px Value 1 3 2 Data Lane HS Entry Data Lane Tyus prepare Value 1 3 3 Data Lane HS Entry Data Lane Tyas prepare T us zeno Value 1 3 4 Data Lane HS TX Differential Voltages Vop o and Vann 1 3 5 Data Lane HS TX Differential Voltage Mismatch AVop 1 3 6 Data Lane HS TX Single Ended Output Voltages Vouuspe and Vouus py 1 3 7 Data Lane HS TX Static Common Mode Voltages Vomrtx 1 and VemTx 0 1 3 8 Data Lane HS TX Static Common Mode Voltage Mismatch AVoyrxq o 1 3 9 Data Lane HS TX Dynamic Common Level Variations Between 50 450 MHz AV wrie 1 3 10 Data Lane HS TX Dynamic Common Level Variations Above 450 MHz AVoyrx ur 1 3 11 Data Lane HS TX 2096 8096 Rise Time tg 1 3 12 Data Lane HS TX 8096 2096 Fall Time tp 1 3 13 Data Lane HS Exit Tus trai Value 1 3 14 Data Lane HS Exit 3096 8596 Post EoT Rise Time Treor 1 3 15 Data Lane HS Exit Tror Value 1 3 16

R&S RTO-K26 D-PHY Compliance Test

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R&amp;S RTO-K26 D-PHY Compliance Test

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R&S RTO-K26 D-PHY Compliance Test