AnaGate UP 2.0
Contents
1. nennen nnn nnn nnn 5 Using AnaGate hardware with firewall sese 17 Bpod EP 20 SPI device list A ove ne neni ea na A RACER 21 Feature list of universal programming devices 22 Feature list of standalone and universal programming devices 22 Programming speed for I2C 24 Programming speed for SPI 24 V 2007 2013 Analytica GmbH Introduction This document describes the features and objectives of the programming unit AnaGate UP 2 0 The AnaGate UP 2 0 is designed to program I2C EEPROMs SPI EEPROMs and SPI flash devices In addition it is also possible to access JTAG able flash devices NOR NAND CPUs via the existing JTAG interface even the debugging of CPU s is supported via OpenOCD This unit is an improvement of the established AnaGate Universal Programmer UPP which provides the core functionality of the ethernet gateways AnaGate I2C and AnaGate SPI The concept of transparent access to I2C and SPI bus via ethernet interface was taken and both hardware interfaces are combined in a single programing unit Via the software interface of the AnaGate UP 2 0 any I2C and SPI commands can be issued An JTAG interface and a galvanically isolated power interface for supplying the connected devices or printed circuit boards completes the unit2. The rear panel of the AnaGate UP 2 0 features the following connectors and LEDs from left to right Power LED Power supply LAN USB Hosts Digital IO Reset Activity LED This green LED lights up when voltage is being supplied The AnaGate UP 2 0 can be power supplied in two different ways For the use as desktop device the barrel connector socket is intended in order to supply the device via a plug power supply For the use in a switchboard the two pole Wago clamping socket can be used to connect an external power supply 9 Warning Be sure to use only one power supply Via the RJ45 socket the AnaGate UP 2 0 is connected with the Ethernet The device can be connected to a network component like a hub or a switch For a direct connection to a PC a crossover network cable has to be used The AnaGate UP 2 0 has two USB 1 1 interfaces for further extensions or customer specific solutions The AnaGate UP 2 0 has 4 digital inputs and 4 digital outputs which can be used freely The digital io are galvanically decoupled from the device and must be externally power supplied from 3 3V to 24V see Section 2 3 Digital IO The AnaGate UP 2 0 can be reset to the factory settings using this button see Section 2 4 Factory reset for further details This yellow LED lights up when the AnaGate UP 2 0 is processing incoming CAN messages 6 O 2007 2013 Analytica GmbH Chapter 2 Configuration 2 1 Initial i
3. immediately The IP address and subnet mask are pulsed out one after the other Following pulse codes are used e Digits 1 2 3 9 1x 2x 9x Flashing 200ms delay between each flash e Digit 0 10x flashing 200ms delay between each flash e Dot 1x very fast flash Between two single digits a delay of 1 seconds is made and between the IP address and subnet mask two fast flashes are pulsed out Figure 2 4 AnaGate UP 2 0 Example blinking output 192 168 1 1 NEHEHHEEHHENH EE COCE OM OO 2 5 Firmware update The device firmware of the AnaGate UP 2 0 is updated via the integrated web server of the device 10 2007 2013 Analytica GmbH Configuration On the home page of the web server the current firmware information is displayed Figure 2 5 HTTP interface AnaGate UP 2 0 Firefox S A ES As Index 192 168 1 254 23 D fru AnaGate Universal Programmer Welcome to the Web Interface of the AnaGate Universal Programmer device AnaGate Universal Programmer Device information E DHCP OFF Copyright IP address 192 168 1 254 Subnet mask 255 255 255 0 Gateway MAC 00 50 C2 3C B6 68 Serial 01080668 Versions Software version 2 0 4 Feb 6 2013 Hardware version 2 0 0 Model GT UP2 HW CoreRev 0 21 ModuleRev 2 2 SubModuleRev 1 0 Webinterface version 1 3 0 Copyright 2008 2010 Analytica GmbH vrw w anagate de Stand
4. o o d D io e TDI Input Test Data Input 1 I TMS Input Test Mode Select 82 2924 3 22 8 GR Input a TCK Output Test Clock TDO Output Test Data Output SRST Output Slave Reset GND Ground for JTAG NC not connected I2C port 6 pole connector plug to connect the I2C bus galvanically isolated The pin allocation of the plug can be inferred from the following table 4 2007 2013 Analytica GmbH Description Table 1 4 Pin layout 12C socket Pin Type Description VCCIN External voltage for I2C 999 1 8 up to 5V DC O SCL Input Clock line for I2C Output SDA Input Data line for 12C Output GND Ground for 12C VAUX port 10 pole connector plug to power supply the connected PCB s The pin allocation of the plug can be inferred from the following table Table 1 5 Pin layout VAUX socket Pin Type Description 5Vour Output 5V output for current supply of devices up to 200mA 3 3Vour Output 3 3V output for current supply of devices up to 200mA 2 7Vout Output 2 7V output for current supply of devices up to 200mA 1 8Vout Output 1 8V output for current supply of devices up to 200mA GND Ground for SPI NC not connected 5 O 2007 2013 Analytica GmbH Description 1 4 2 AnaGate UP 2 0 rear view Figure 1 3 AnaGate UP 2 0 back panel Digital 10 OUT IN tT 1 4 1 4 Reset Act
5. see previous FAQ but you still can t connect to the AnaGate then please try the following 1 Check if the AnaGate can be reached via ping To do so in Windows open a command prompt and enter the command ping a b c d where a b c d is the device IP address In case the AnaGate is unreachable via ping reset the device to factory settings Set the IP address of your PC to 192 168 1 253 and the subnet mask to 255 255 255 0 Check if the AnaGate can be reached via ping 192 168 1 254 If the device can be reached via ping then the next step is to try if you can open a TCP connection to port 5001 Open a Windows command prompt and enter telnet a b c d 5001 where a b c d is the device IP address If this command fails check if a firewall runs on your PC or if there is a packet filter in the network between your PC and the AnaGate 16 O 2007 2013 Analytica GmbH FAQ Frequently asked questions No network connection after changing the network address After changing the network address of the AnaGate device via web interface the device is not longer reachable The used internet browser displays only an empty web page additional error messages are not available Please check if your anti virus software has blocked the new network address After changing the network address you are redirected to the new network address in the browser Such activity is suspicious for some anti virus software so they block the new web page sometimes
6. 5 0V DC The signal level of the interface is always identical to the supply voltage So it is advisable to supply the interface and the device to program with the same power supply Since the interface is galvanically isolated the supply voltage of the programming board can be used for example On the AnaGate UP 2 0 and on the AnaGate UPP the installed power module can be used to supply the JTAG device up to 200mA directly When using higher baud rates ensure that a GND is present between two signal lines The cables should be kept as short as possible In the following picture the use of the JTAG interface is schematically shown 14 O 2007 2013 Analytica GmbH Fields of application Figure 3 3 Universal Programmer connected a JTAG device The lines have to be interconnected as follows TMS TCK TRST SRST TDI TDO O 3 4 Power interface These lines have to be interconnected to each JTAG device to the same designation These lines have to be interconnected to each JTAG device to the same designation The connection is optional test and system reset lines This line have to be interconnected to the TDI data input of the JTAG device This line have to be interconnected to the TDO of the JTAG device in single device mode If there is more than a single JTAG device is attached the TDO of the first device is interconnected to the TDO of the second and so one The TDO of the last JTAG device
7. Single Multi Master modes SPI Bus Baud rates 10 to 8600 kpbs 200 to 10000 kpbs JTAG Baud rates 10 to 8000 kpbs Power Output voltage 1 8V 2 7V 3 3V 5 0V LAN Speed 10 100 Mbps 10 100 Mbps Digital IO Inputs 4 4 4 Outputs 4 4 4 23 O 2007 2013 Analytica GmbH Appendix E Programming speed The specific behavior of the Universal Programmer compared to the predecessor models for SPI and I2C is shown in the following tables on the basis of two different reference devices Table E 1 Programming speed for 12C Programmer Device Size Baud Program Verify Total rate AnaGate I2C AT24C1024 128KB 400 6 4s 5 1s 11 5s kbps AnaGate UP AT24C1024 128KB 400 5 0s 3 85 8 85 kbps AnaGate UP 2 0 AT24C1024 128KB 400 4 65 3 85 8 45 kbps AnaGate UP 2 0 AT24C1024 128KB 1 Mbps 2 65 2 15 4 75 AnaGate UP 2 0 24LC512 64KB 400 3 85 2 05 5 85 kbps Imax 400 kBit s Table E 2 Programming speed for SPI Programmer Device Size Baud Delete Program Verify Total rate AnaGate SPI AT45DB642D 4MB 6 25 18 2s 123 05 61 95 202 95 MHz AnaGate UP AT45DB642D 4MB 6 25 18 15 56 1s 31 95 106 25 MHz AnaGate UP AT45DB642D 4MB 8 33 18 15 56 05 31 85 105 95 MHz AnaGate UP 2 0 AT45DB642D 4MB 8 33 18 15 20 6s 21 05 59 7 5 MHz AnaGate UP 2 0 AT45DB642D 4MB 10 0 18 15 19 45 19 65 57 15 MHz AnaGate SPI M25P16 2MB 6 25 14 8s 141 65 28 7s 185 15 MHz AnaGate UP M25P16 2MB 8
8. changed Using a firewall When working with a firewall a TCP port has to be opened for communication with the AnaGate device Table A 1 Using AnaGate hardware with firewall Device Port number AnaGate I2C 5000 17 2007 2013 Analytica GmbH FAQ Frequently asked questions Device Port number AnaGate 12C X7 5100 5200 5300 5400 5500 5600 5700 AnaGate CAN 5001 AnaGate CAN USB 5001 AnaGate CAN uno 5001 AnaGate CAN duo 5001 5101 AnaGate CAN quattro 5001 5101 5201 5301 AnaGate CAN X1 5001 AnaGate CAN X2 AnaGate CAN FD X2 5001 5101 AnaGate CAN X4 AnaGate CAN FD X4 5001 5101 5201 5301 AnaGate CAN X8 5001 5101 5201 5301 5401 5501 5601 5701 AnaGate SPI 5002 AnaGate Renesas 5008 AnaGate Universal Programmer UP UPP 5000 5002 3333 4444 20 21 AnaGate Universal Programmer UPR 5000 5002 5008 3333 4444 20 21 AnaGate Universal Programmer UP 2 0 5000 5002 3333 4444 20 21 A 2 Questions concerning the SPI interface Q No SPI communication A If SPI communication with your SPI device fails please proceed as follows 1 Check that the SPI device and the SPI interface of the AnaGate UP 2 0 are connected to a power supply Check that no other devices uC are active on the SPI bus Ensure that no other electrical components can interfere with communication on the SPI bus between the AnaGate Universal Programmer and the SPI devi
9. 08 2010 Analytica GmbH www anagate de Stand Apr 13 2011 The inputs will be taken over immediately after clicking the button Save settings and saved permanently on the AnaGate UP 2 0 A restart of the device is not necessary for activation of the settings Note Maybe the ARP cache of the PC has to be deleted to find the device with the changed IP address 8 2007 2013 Analytica GmbH Configuration 2 3 Digital lO 2 3 1 Pin layout of plug Over the 10 pole pin row on the back of the AnaGate UP 2 0four digital inputs and four digital outputs are led out which can be used freely Since the IO s are electrically isolated from the device they must be separately supplied via the pins 1 us 2 with a voltage by 3 3V 24V DC Figure 2 3 Pin layout digital IO plug 4 LNO 2 3 1 1 Connecting the digital inputs At the inputs IN1 to IN4 any external voltage between VCC and GND can be applied As soon as the voltage difference between INx and GND is more than 1 0 V the AnaGate UP 2 0 interprets the input as logically HI otherwise LOW 2 3 1 2 Connecting the digital outputs The outputs are implemented as open collector drivers If a output is active it is pulled down to GND In the inactive condition the output is floating In principle the maximum current of each individual output is 400mA For thermal reasons is the sum of all output currents is limited to 500mA The outputs not short circuit pro
10. 27 Bibliography EE E so na p x Nae ER UE AAG ER erue RE TRE CRT IEEE 28 iii O 2007 2013 Analytica GmbH List of Figures A DN 2 015 AS 1 Front view AnaGate UP 2 0 cda bd AS 3 AnaGate UP 2 0 back panel 6 HTTP interface AnaGate UP 2 0 7 HTTP interface network settings eee ee eee mee 8 Pin layout digital IO plug cvs Rx TREE estes veces 9 AnaGate UP 2 0 Example blinking output 10 HTTP interface AnaGate UP 2 0 11 HTTP interface firmware update mme mmn 11 Universal Programmer connected a single SIP device 13 Universal Programmer connected to two I2C 14 Universal Programmer connected a JTAG device 15 iv 2007 2013 Analytica GmbH List of Tables MMODUOWDPRRRRR NPMOPEPRPEPUARWNEB Technical data AnaGate UP2 2 Pin layout SPI Socket 5 i EO Ema er RUPEE 4 Pin layout JTAG socket renina a E EE nennen nnne nene sare nin 4 iPinlayout I2G socket a tit 5 Pin layout VAUX socket
11. 33 14 7s 37 85 8 0s 60 55 MHz AnaGate UP 2 0 M25P16 2MB 10 0 14 7s 9 9s 5 0s 29 65 MHz Note A conventional PC Intel Core2 Duo E8400 3 0 GHz 4 GB RAM running Windows 7 64bit SP1 was used for taking the readings everal measurements are taken and averaged the memory was always written 24 2007 2013 Analytica GmbH Programming speed and read completely from and to the personal computer by use of the LAN interconnection 25 2007 2013 Analytica GmbH Appendix F Technical support The AnaGate hardware series software tools and all existing programming interfaces are developed and supported by Analytica GmbH Technical support can be requested as follows Internet E Mail The AnaGate web site http www anagate de en index html of Analytica GmbH contains information and software downloads for AnaGate Library users e Product updates featuring bug fixes or new features are available here free of charge If you require technical assistance over the Internet please send an e mail to lt support anagate de gt To help us provide you with the best possible support please keep the following information and details at hand when you contact our support team e Version number of the used programming tool or AnaGate library e AnaGate hardware series model and firmware version e Name and version of the operating system you are using 26 2007 2013 Analytica GmbH Abbrevia
12. AnaGate UP 2 0 aS User Manual Analytica GmbH A Schmidt Analytica GmbH AnaGate UP 2 0 User Manual Analytica GmbH by A Schmidt This document was generated with DocBook at 2014 06 17 14 30 01 PDF Datei dtsch AnaGateUP2 2 0 pdf PDF Datei engl AnaGateUP2 2 0 EN pdf Publication date 26 Juli 2013 Copyright 2007 2013 Analytica GmbH Abstract This manual describes the interfaces and modes of operation of a AnaGate UP 2 0 All rights reserved All the information in this manual was compiled with the greatest of care However no warranty can be given for it No parts of this manual or the program are to be reproduced in any way printing photocopying microfilm or any other process without written authorisation Any processing duplication or distribution by means of any electronic system is also strictly prohibited You are also advised that all the names and brand names of the respective companies mentioned in this documentation are generally protected by brand trademark or patent laws Analytica GmbH VorholzstraBe 36 76137 Karlsruhe Germany Fon 49 0 721 43035 0 Fax 49 0 721 43035 20 lt support analytica gmbh de gt www analytica gmbh de http www analytica gmbh de www anagate de http www anagate de Revision History Revision 10 12 2008 Uwe Initial version 0 9 Revision 30 09 2009 Uwe JTAG Renesas Power 1 0 Revision 22 07 2010 THa Change of PIN assig
13. Apr 13 2011 Proceed please as follows in order to install the firmware on the AnaGate UP 2 0 e Click Firmware on the left navigation bar to navigate to the Firmware Upload page Figure 2 6 HTTP interface firmware update Firefox h olx s Firmware lt 192 168 1 254 index cgi site Fwupload C 7 Google ya 4 e M T AnaGate Universal Programmer Firmware update To update the AnaGate Universal Programmer please select the firmwarefile and press the update AnaGate Universal button The update can take several minutes If the update is done the browser returns on the main Programmer page Please check there basised on the version numbers whether the update was successful em Remarks Use only software which is specified for this equipment irmware Copyright Firmware Current Version 2 0 4 Feb 6 2013 Durchsuchen Keine Datei ausgew hlt Upload Clear Copyright 2008 2010 Analytica GmbH www anagate de Stand Apr 13 2011 e Select the update package file extension upd via the Browse button e Clicking on the button Upload loads the update file to the device and starts the update process 11 O 2007 2013 Analytica GmbH Configuration e During the update process several installation messaged are displayed on the website If the update is successfully finished Update done is displayed When the update is finished the browser navigates back to the home page Check if the
14. GmbH Appendix D Feature list programming devices Table D 1 Feature list of universal programming devices Feature Universal Programmer Universal Programmer 2 0 System Hardware AnaGate AnaGate AnaGate AnaGate UP 2 0 UP UPP UPR Processor ARMO 32bit 200MHz ARM9 32bit 200MHz I2C Bus Baud rates 50 100 200 400 kpbs 50 100 200 400 1000 kpbs Operatinf modes Single Master Single Multi Master SPI Bus Baud rates 200 to 8333 kpbs 200 to 10000 kpbs JTAG Baud rates 10 to 8000 kpbs 10 to 8000 kpbs Renesas Baud rates 9600 19200 38400 57600 kpbs Power Output voltage 1 8V 1 8V 2 7V 3 3V 2 7V 5 0V 3 3V 5 0V Digital IO Inputs 4 4 Outputs 4 4 Table D 2 Feature list of standalone and universal programming devices Feature I2C SPI Universal Programmer Programmer Programmer 2 0 System Hardware AnaGate I2C AnaGate SPI AnaGate UP 2 0 Processor eZ80 Acclaim 8bit ARMO 32bit Operating Zilog ZTP RTOS Linux Kernel 2 6 20 System USB 2 x USB 1 1 Indiv upload of executables extensions GCC Temp range 0 60 C 0 60 C 0 60 C Input voltage 8 28V DC 8 28V DC 8 28V DC I2C Bus Baud rates 50 100 200 50 100 200 400 400 kpbs 1000 kpbs 22 2007 2013 Analytica GmbH Feature list programming devices Feature 12C SPI Universal Programmer Programmer Programmer 2 0 Operatinf Single Master
15. ce Questions concerning the 12C interface Q No I2C communication A IfI2C communication with your I2C device fails please proceed as follows 1 Check that the I2C device and the I2C interface of the AnaGate UP 2 0 are connected to a power supply Check that no other devices uC are active on the I2C bus Ensure that the SDA and SCL circuits are provided with an adequate pull up resistance e g 4 7 kOhm to the voltage supply 3 3 V resp 5 V 18 2007 2013 Analytica GmbH FAQ Frequently asked questions Ensure that no other electrical components can interfere with communication on the I2C bus between the AnaGate I2C and the I2C device Ensure that the chip enable address of the 12C device and the software are identical What is the correct order to connect the GND SCL and SDA when using an external power supply To avoid potential damage to the AnaGate UP 2 0 the GND pin MUST be connected to the application board first Only then can the SCL and SDA pins be allowed to make contact with the application board A 4 Questions concerning the JTAG interface Q A No JTAG communication If JTAG communication with your JTAG device fails please proceed as follows 1 Check that the JTAG device and the JTAG interface of the AnaGate UP 2 0 are connected to a power supply Ensure that the TDO pin of the last JTAG device is connected to the TDO pin of the AnaGate UP 2 0 19 O 2007 2013 Ana
16. even without notification of the user Connection problems using multiple devices If multiple devices with identical IP addresses are used in a local area network at the same time the connections to the devices are not stable Because of this behaviour it is necessary to use different IP addresses This problem can also occur if devices with identical IP addresses are used not concurrently but within short intervals For example this can arise if some new devices which have the default IP address 192 168 1 254 are configured from a single PC The Address Resolution Protocol ARP is used in IPv4 networks to determine the MAC address of a given IP address The necessary information is cached in the ARP table If there is a wrong entry in the ARP table or even an entry which is not up to date it is not possible to communicate with the corresponding host An entry in the ARP table is deleted if it is not used any more after a short period time The time interval used depends on the operating system On a current Linux distribution an unused entry is discarded after about 5 minutes The ARP cache can be displayed and manipulated with the arp on Windows and Linux Gg Weg a tec Mer 10 1 2550 062 Internetadresse Physikal Adresse Typ 192 168d 29 Quo Fez 3 eb dit dynamisch The command arp d can be used to empty the ARP Cache Note Possibly the ARP cache of the PC has to be deleted if the IP address of a device is
17. face This means that any communication partner with a LAN interface is able to communicate to the device Accessing the device with the supplied application libraries for Windows and Linux is much comfortable The libraries includes the entire range of device functions and can be used with conventional programming languages Features The AnaGate UP 2 0 offers basically interfaces for 12C SPI and JTAG I2C interface e Supports I2C Read and Write commands for all 12C devices 7 and 10 Bit format e Variable 12C bus speed 50 100 200 400 1000 kbps e Galvanically isolated SCL SDA lines SPI interface e Supports all SPI Salve devices sending and receiving data e Variable SPI bus speed 200 10000 kbps e Galvanically isolated CLK MISO MOSI CS lines JTAG interface e Supports JTAG interface to programm flash memories and debug CPUs 1 2007 2013 Analytica GmbH Description 1 2 e Variable JTAG bus speed 10 8333 kbps e galvanically isolated TRST SRST TDI TMD TCK TDO lines Other features e Two different plugs for voltage supply e Power inteface with output voltage of 1 8V 2 7V 3 3V or 5 0V DC e System is addressed using a proprietary network protocol e Static or dynamic assignment DHCP of IP address e 4 digital inputs and outputs which can be accessed via LAN Ethernet Specification Table 1 1 Technical data AnaGate UP2 Technical aspect Spec
18. fication Measurements Desktop casing 155mm x 105mm x 40mm fixable on DIN rail with optional adapter kit Weight approx 315g I2C bus Baud rate Standard Mode 100kbps Fast Mode 400kbps Fast Mode Plus 1000kbps software configuration Operating mode Single Master Multi Master High level SCL SCA 3 0V Max 5 0V isolated Interface 6 pole plug with SCL SCA Vcc GND SPI bus Baud rate 200 10000kbps software configuration Operating mode SPI Master High level Min 1 8V Max 5 5V isolated Interface 10 pole plug with MISO MOSI CLK SS GND Vcc GND JTAG Baud rate 10 8333kbps software configuration Operating mode JTAG Master Mode High level Min 1 8V Max 5 5V isolated Interface 20 pole plug with TRST SRST TDI TMD TCK TDO Vcc GND Digital IO Inputs 4 galvanically isolated 3 3 24V Outputs 4 galvanically isolated 3 3 24V Itotal max 0 5A LAN interface rate 10 100 Mbps TCP IP Static or dynamic DHCP IP address Interface RJ45 socket 2 2007 2013 Analytica GmbH Description 1 3 1 4 1 4 1 Technical aspect Specfication Voltage supply Voltage 9V 28V direct current Power consumption max 350 mA 9V without plugged USB consumers Ambient Storage 0 85 C temperature In operation 0 60 C Scope of delivery The AnaGate UP 2 0 is supplied with the following components e 1x AnaGate UP 2 0 e 1x CD with manual programming API for Windows Linux P
19. have to be interconnected to the TDO of the AnaGate Universal Programmer Note RCLK is not supported by the AnaGate Universal Programmer The power interface VAUX make the following voltages available during a maximum total current load of 200mA e 1 8V DC e 2 7V DC e 3 3V DC e 5 0V DC These tensions can be used to supply a PCB during programming 15 O 2007 2013 Analytica GmbH Appendix A FAQ Frequently asked questions Here is a list of frequently asked questions A 1 Common questions Q A No network connection 1 Please check the physical connection to the device first In general the AnaGate has to be connected directly to a personal computer or to an active network component hub switch If the AnaGate device is connected to a personal computer a cross wired network cable must be used to connect the device otherwise the included network cable is to be used USB Digital 10 Power LAN F D J t The physical interconnection is OK if the yellow link LED turns on when LAN cable is plugged in The yellow light stays on until the connection breaks down On some hardware models the link LED flickers synchronously to the green activity LED if there is traffic on the network line If the link LED is always off then please check the wiring between the AnaGate and the hub switch or the personal computer No network connection 2 If the link LED indicates a proper Ethernet connection
20. interconnected to the clock input of the SPI Slave often referred as CLK or SCK SS This line have to be interconnected to the chip select input of the SPI Slave often referred as SS or CS 3 2 Using the 12C interface Before using the I2C interface the Vcc and GND pins have to be supplied with an external voltage of 3 3V up to 5 0V DC The signal level of the interface is always 13 O 2007 2013 Analytica GmbH Fields of application 3 3 identical to the supply voltage Since the interface is galvanically isolated the supply voltage of the programming board can be used On the AnaGate UP 2 0 and on the AnaGate UPP the installed power module can be used to supply the 12C device up to 200mA directly Two 4 7 kOhm pull up resistors have to be switched between the voltage supply and the SDA or SCL circuit These are not integrated in the Anagate UP 2 0 and must be attached externally In most cases these resistors are already present on the boards to program In the following picture the use of the 12C interface is schematically shown Figure 3 2 Universal Programmer connected to two 12C devices 12C Device 12C Device If the I2C device is fitted with chip enable address inputs usually designated A0 EO A1 E1 and A2 E2 these also have to be provided with GND or power Using the JTAG interface Before using the SPI interface the Vcc and GND pins have to be supplied with an external voltage of 1 8V up to
21. lytica GmbH Appendix B 12C device list The AnaGate UP 2 0 provides with its 12C inferface a fully working 12C Ethernet gateway which can perform Read Write requests from the PC via ethnernet to a connected I2C bus Accesing serial I2C EEPROMs is included in particular The free programming software I2C EEPROM Programmer uses this feature and extends the AnaGate UP 2 0 to a remarkably efficient programming tool for 12C EEPROM devices As an example the supported different EEPROM devices of a single manufacturer are listed in the following table Of course all identical hardware devices of other manufacturers are supported too Table B 1 I2C device list Part No Mamufacturer Memory M24C01 M24LCO1 STMicroelectronics 1 Kbit M24C02 M24LCO1 STMicroelectronics 2 Kbit M24C04 M24LC04 STMicroelectronics 4 Kbit M24C08 M24LC08 STMicroelectronics 8 Kbit M24C16 M24LC16 STMicroelectronics 16 Kbit M24C32 M24LC32 STMicroelectronics 32 Kbit M24C64 M24LC64 STMicroelectronics 64 Kbit M24C128 M24LC128 STMicroelectronics 128 Kbit M24C256 M24LC256 STMicroelectronics 256 Kbit M24C512 M24LC512 STMicroelectronics 512 Kbit M24M01 STMicroelectronics 1024 Kbit M24M02 STMicroelectronics 2048 Kbit i Important If a I2C device does not still exist in the device databare of the software I2C EEPROM Programmer it can be added permanently The required settings can be found in the device data shee
22. mation CiA e V CAN in Automation CiA e V 13 02 2002 Cia 301 CANopen Application Layer and Communication Profile 28 2007 2013 Analytica GmbH
23. new firmware version is display here Warning If the firmware could not be flashed correctly on the device the AnaGate may not longer ready for operation Please visit our web site http www anagate de for further information 12 O 2007 2013 Analytica GmbH Chapter 3 Fields of application 3 1 Using the SPI interface Before using the SPI interface the Vcc and GND pins have to be supplied with an external voltage of 1 8V up to 5 0V DC The signal level of the interface is always identical to the supply voltage So it is advisable to supply the interface and the device to program with the same power supply Since the interface is galvanically isolated the supply voltage of the programming board can be used for example On the AnaGate UP 2 0 and on the AnaGate UPP the installed power module can be used to supply the SPI device up to 200mA directly When using higher baud rates ensure that a GND is present between two signal lines The cables should be kept as short as possible In the following picture the use of the 12C interface is schematically shown Figure 3 1 Universal Programmer connected a single SIP device SPI Slave The lines have to be interconnected as follows MOSI This line have to be interconnected to the data input of the SPI Slave often referred as DI or SI MISO This line have to be interconnected to the data output of the SPI Slave often referred as DO or SO CLK This line have to be
24. nment of Renesas module 1 1 Revision 22 07 2013 ASc Manual changed to DocBook format and extended to new AnaGate UP 2 0 2 0 device Table of Contents INEFOGUCHON A Saa vi 1 Description A O te E ere aes 1 Tais A O 1 1 2 SPECICATION oorr A ee em vr Rd Vw oe o e e EE 2 1 3 Scope of delivery 3 1 47 Interfaces and plugs peret DERE De rea eH Y xen ce Ro Tales 3 2 Configuration vine ECL A didas 7 2 T Initial SA eee te De e E p EN Re 7 2 27 Network settihgs teen ear ad re ea nee 8 2 9 Digital 1091 5 5 2 oo iM mi rei T 9 24 Factory assi TS 9 2 5 Firmware update sec x ere exer o ee ee de een ev Ed weis 10 3 Fields of application 13 3 1 Using the SPI interface x ac eee o Re let ek pe Rea Ta 13 3 2 Using the I2C interface sete ts acne ud RR eR esa ree RE a 13 3 3 Using the JTAG interface erre erre al 14 3 4 POWer Interface isses erede adas 15 A FAQ Frequently asked questions 16 12 list tee exe iii dealer Rie A dale EI VES dx eie 20 C SPI device liSt CRDI mto e e RM E d a 21 D Feature list programming devices ooocooccccncconcnnnnnennncnnnnrnnennnnnannrnannannrnnnes 22 Es Programming Speed ou e ER e ae TE eem te Ct 24 E Technical Support eere ehh eere ER TER 26 Abbreviatiofis A er te A
25. nstallation First the AnaGate UP 2 0 must be supplied via the power plug with a tension from 9 to 24 V Insert the included LAN cable into the plug labelled LAN and connect it either to a hub or switch If connecting directly to a PC use a crossover LAN cable not in scope of delivery instead of the included LAN cable 2 1 1 Factory settings The AnaGate UP 2 0 is delivered with the following initial network settings IP address Address type Network mask Gateway 192 168 1 254 static 255 255 255 0 192 168 1 1 The device can now be configured using a standard browser Internet Explorer Firefox etc by using nttp 192 168 1 254 Figure 2 1 Firefox HTTP interface AnaGate UP 2 0 Ps Index ES 192 168 1 254 c El y AnaGate Universal Programmer Welcome to the Web Interface of the AnaGate Universal Programmer device AnaGate Universal Programmer Device information IP Settings Firmware DHCP OFF Copyright IP address 192 168 1 254 Subnet mask 255 255 255 0 Gateway MAC 00 50 C2 3C B6 68 Serial 01080668 Versions Software version 2 0 4 Feb 6 2013 Hardware version 2 0 0 Model GT UP2 HW CoreRev 0 21 ModuleRev 2 2 SubModuleRev 1 0 Webinterface version 1 3 0 Copyright 2008 2010 Analytica GmbH www anagate de Stand Apr 13 2011 Note The PC used for the configuration must be in the 192 168 1 x network The static IP address 192 168 1 2 with the subne
26. ofed and must be protected with a pre resistor Warning The outputs are not short circuit safe 2 4 Factory reset In order to restore the default factory settings hold the RESET for approx 10 seconds If the device is reset successfully the yellow LED blinks until the RESET is released The default factory settings are activated immediately without a restart of the device IP address 192 168 1 254 Address type static 9 2007 2013 Analytica GmbH Configuration Network mask 255 255 255 0 Gateway 192 168 1 1 i Important If the RESET push button is pressed too briefly the actual IP address and network mask is pulsed via the yellow LED Morse code A second push of the RESET terminates the pulsing the device is not reset Note Q The factory reset is not possible directly after power on until complete loading of the operating system and the firmware of the device This initialization period is signalled via the yellow activity LED On power on the LED is switched on and after initialization the LED is switched off Note Maybe the ARP cache of the PC has to be deleted to find the device with the changed IP address 2 4 1 Examining the network settings It is possible to check the current network settings directly on the device After pressing shortly the RESET button the device starts to pulse out the current n settings via the yellow activity LED Pressing again the buttons stops the pulsing
27. rogramming software for 12C SPI and JTAG Windows Linux e 1x 1 8 m Cat 5 LAN cable standard not crossed e 1x 10 pole plug connector for digital e 1x 2 pole plug connector for external power supply e 1 x plug in power supply unit compatible with country of delivery EU US or UK Interfaces and plugs AnaGate UP 2 0 front view Figure 1 2 Front view AnaGate UP 2 0 AnaGate UP 2 0 The front panel of the AnaGate UP 2 0 features the following connectors from left to right SPI port 10 pole connector plug to connect the SPI bus galvanically isolated The pin allocation of the plug can be inferred from the following table 3 O 2007 2013 Analytica GmbH Description Table 1 2 Pin layout SPI socket Pin Type Description VCCIN External voltage for SPI 1 8 up to 5V DC CLK Output Clock line SS Output Slave Select line low active MOSI Input Master In Slave Out MISO Output Master Out Save JTAG port In 19 SS ISOIN OSIN 20 pole connector plug to connect the SPI bus galvanically isolated The pin allocation of the plug can be inferred from the following table Table 1 3 Pin layout JTAG socket Pin Type Description VCCIN External voltage for rof 2 222 JTAG 1 8 up te 511 909090005 DC 2e o 5 Oa o 205 TRST Output Test Reset 1
28. t O 2007 2013 Analytica GmbH Appendix C SPI device list The AnaGate UP 2 0 provides with its SPI inferface a fully working SPI Ethernet gateway which can perform data requests from the PC via ethnernet to a connected SPI bus Accesing serial SPI EEPROM and other memory devices is included in particular The free programming software SPI EEPROM Programmer uses this feature and extends the AnaGate UP 2 0 to a remarkably efficient programming tool for SPI EEPROM and other memeory devices As an example some supported devices of a different manufacturer are listed in the following table Of course all identical hardware devices of other manufacturers are supported too Table C 1 SPI device list Part No Manufacturer Algorithm M95128 M95256 M95640 ST M25P05 M25P10 M25P20 M25P30 M25P40 ST M25P80 M25P128 M25PX30 FM25CL64S Ramtron ST AT25010A AT25020A AT25040A AT25128 AT250x0A AT25160A AT25256 AT2532A AT25640A AT25F512 AT25F2048 AT25F4096 AT25Fxxx AT24BD041D AT24BD081D AT24BD161D AT45xxx AT24BD321D AT24BD641D AT24BD642D i Important If a I2C device does not still exist in the device databare of the software SPI EEPROM Programmer Analytica can check if the missing device is currently supported The required informations are mostly found in the device data sheet Adding new programming algorithm in the SPI EEPROM Programmer is possible on demand 21 2007 2013 Analytica
29. t mask 255 255 255 0 7 2007 2013 Analytica GmbH Configuration can be e g used If neccessary the settings of the network interface on the configuration pc has to be changed temporarily 2 2 Network settings On the page IP Settings the following settings can be changed DHCP Here you can switch between static IP and dynamic via DHCP addresses If DHCP is being used the remaining fields are ignored because this information is retrieved from the DHCP server In this case a DHCP server must be available and accessible in the network IP address The IP address of the AnaGate UP 2 0 is entered in dot format e g 192 168 1 200 Subnet mask The subnet mask is entered in dot format e g 255 255 255 0 Gateway The default gateway is entered in dot format e g 192 168 1 1 Leave blank or enter 0 0 0 0 if a default gateway is not required Figure 2 2 HTTP interface network settings Firefox Y h A x As IP Settings 192 168 1 254 index cai site settings c E 23 D T AnaGate Universal Programmer Settings Please enter the new TCP IP settings of the AnaGate Universal Programmer AnaGate Universal Programmer Remarks If DHCP is used the IP address the subnet mask and the gateway are set by the DHCP server of the local network IP Settings Firmware Duce Copyright IP address 132 168 1 254 Subnet mask 255 255 255 0 Gateway Save settings Resetform Copyright 20
30. tions I2C SCL SDA SPI CLK MISO SS MOSI TRST SRST JTAG TDI TDO TMS TCK DHCP Inter Integrated Circuit Serial Clock Line Serial DAta Line Serial Peripheral Interface Clock Master In Slave Out Slave Select Master Out Slave In Test Reset Slave Reset Joint Test Action Group Test Data Input Test Data Output Test Mode Select Input Test Clock Dynamic Host Configuration Protocol 27 2007 2013 Analytica GmbH Bibliography Books LuaRef2006 EN Roberto lerusalimschy Luiz Henrique Figueiredo and Waldemar Celes Copyright O 2006 R lerusalimschy L H de Figueiredo W Celes ISBN 85 903798 3 3 Lua org Lua 5 1 Reference Manual LuaProg2006 EN Roberto Ierusalimschy Copyright 2006 Roberto Ierusalimschy Rio de Janeiro ISBN 85 903798 2 5 Lua org Programming in Lua second edition LuaProg2013 EN Roberto Ierusalimschy Copyright 2013 Roberto Ierusalimschy Rio de Janeiro ISBN 85 903798 5 X Lua org Programming in Lua Third Edition Other publications NXP I2C NXP Semiconductors Copyright O 2007 NXP Semiconductors UM10204 I2C bus specification and user manual Rev 03 19 06 2007 TCP 2010 Analytica GmbH Copyright 2010 Analytica GmbH Manual TCP IP communication Version 1 2 6 15 05 2008 Prog 2013 Analytica GmbH Copyright 2013 Analytica GmbH AnaGate API 2 Programmer s Manual Version 2 0 15 05 2013 CiA DS301 Copyright 2002 CAN in Auto
31. to a highly flexible programming solution A programming software which can be run in batch mode for programming of memory devices is included Not already supported devices can be added into the programming software on demand Alternatively is is also possible to access the AnaGate UP 2 0 via a free application library API and to integrate the unit into individual software applications The AnaGate UP 2 0 is particularly suitable for in series line production and in system programming of pcb s due its reliability and high programming speed Of course it is pretty often used in laboratory during development too The connection to the programming unit is always done via a standard network line TCP IP LAN WLAN Installation of additional unit drivers is not neccessary if the network is already running vi 2007 2013 Analytica GmbH Chapter 1 Description 1 1 The AnaGate UP 2 0 connects a PC an embedded PC or an other general device to a SPI bus I2C bus or JTAG capable device via the TCP IP network protocol For this reason the AnaGate UP 2 0 provides a SPI interface an I2C interface a JTAG interface and an ethernet interface Figure 1 1 AnaGate UP 2 0 JTAG aUer UP 2 0 Controlling and configuration of an AnaGate UP 2 0 is made through TCP IP The application protocol itself is described in detail see TCP 2010 Thus the access to the device can be programmed via native calls to the TCP IP socket inter
Download Pdf Manuals
Related Search