ADS1224 - Texas Instruments
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1. ey gt 0 15 NOM y LA 4 Gage Plane NM 4040064 5 G 02 11 NOTES All linear dimensions are in millimeters Dimensioning and tolerancing per ASME 14 5 1994 B This drawing is subject to change without notice Body length does not include mold flash protrusions or gate burrs Mold flash protrusions or gate burrs shall not exceed 0 15 each side Body width does not include interlead flash Interlead flash shall not exceed 0 25 each side E Falls within MO 153 TEXAS INSTRUMENTS www ti com LAND PATTERN DATA PW R PDSO G20 PLASTIC SMALL OUTLINE Example Board Layout T Based on a stencil thickness of 127mm 005inch 180 65 20x0 25 00000000017 1 95 18 0 5 Example Non Soldermask Defined Pad 1 Example Solder Mask Opening See Note E Pad Geometry All Around Wa 7 4211284 5 G 08 15 NOTES All linear dimensions are in millimeters B This drawing is subject to change without notice C Publication IPC 7351 is recommended for alternate design D Laser cutting apertures with trapezoidal walls and also rounding corners will offer better paste rele2. 5 120 a 110 06 6 9 0 a Ie 90 80 70 25 3 0 3 5 4 0 4 5 5 0 55 55 25 5 35 65 95 125 Supply Voltage V Temperature C Figure 5 Figure 6 ADS1224 4i TEXAS INSTRUMENTS www ti com SBAS286C JUNE 2003 REVISED JANUARY 2009 TYPICAL CHARACTERISTICS CONTINUED At TA 40 C to 85 C AVDD 45V DVDD 5V fci 2MHz and VREF 2 5V unless otherwise noted INTEGRAL NONLINEARITY vs INPUT VOLTAGE INTEGRAL NONLINEARITY vs INPUT VOLTAGE 0 0010 folk 2MHz 2MHz 0 0008 Buffer Off Buffer On 0 0006 0 0004 2 0 0002 5 E 0 z 2 I 0 0002 2 Z 0 0004 0 0006 0 0008 0 0010 b 4 3 2 0 1 2 3 4 5 95 2 5 f 5 05 0 5 1 5 2 5 3 5 Input Voltage Vin V Input Voltage Vi V Figure 7 Figure 8 INTEGRAL NONLINEARITY vs INPUT VOLTAGE INTEGRAL NONLINEARITY vs INPUT VOLTAGE 0 0015 4MHz fork 4MHz Buff ff Buff uffer 0 0010 uffer On 5 e 5 0 a 0 0005 0 0010 0 0015 3 5 2 5 15 05 05 15 25 35 Input Voltage Vn V Input Voltage Vin V Figure 9 Figure 10 NOISE vs INPUT VOLTAGE 15 NOISE vs INPUT VOLTAGE fou 2MHz Buffer On 2MHz T Buffer Off E
3. Each load cell input uses an external amplifier The outputs of the amplifiers connect to the analog inputs of the ADS1224 through a low pass filter The cut off frequency is set to 360Hz allowing full settling in a single measurement cycle A lower cut off frequency can be used to reduce noise from mechanical vibrations but at the expense of filter settling time The internal buffer of the ADS1224 is disabled allowing the VREFN pin to be grounded Note that the loading from the reference inputs will change the effective reference voltage The effective input impedance into the VREFP and VREFN pins will lower the reference voltage seen at these pins At 2MHz input impedance is approximately 500kQ For the reference circuit shown in Figure 32 this lowers the effective reference voltage by approximately 0 1 Q ies j Shielded Mad Cable 1 2 OPA2335 1kQ Filter AM VREFN TEMPEN ADS1224 MSP430F41x 1 NOTE 1 Low drift resistors 1 2 OPA2335 A in Replicate for Channels 2 3 and 4 Figure 32 Vessel Weighing System with Four Load Cells CLK SCLK DRDY DOUT MUXO MUX1 P1 1 TAO MCLK P1 2 TA1 P1 0 TAO P1 6 0A0 XOUT TCLK P1 7 CA1 GND ADS1224 TEXAS INSTRUMENTS www ti com SBAS286C JUNE 2003 REVISED JANUARY 2009 SUMMARY OF SERIAL INTERFACE WAVEFORMS b
4. 5V DVDD 5V fci 2MHz and VREF 2 5V unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Digital Input Output VIH 0 8 DVDD DVDD 0 1 V Logic VIL GND 0 1 0 2 DVDD V levels VOH 1 0 8 DVDD V VOL lo 1mA 0 2 DVDD V Input leakage 10 uA CLK frequency fci 8 MHz CLK duty cycle 30 70 Power Supply AVDD DVDD Standby mode AVDD 5V normal mode buffer off AVDD current AVDD 5V normal mode buffer on AVDD 3V normal mode buffer off AVDD 3V normal mode buffer on Standby mode DVDD current DVDD 5V normal mode DVDD 3V normal mode AVDD DVDD 5V buffer off AVDD DVDD 3V buffer off Total power dissipation Temperature Range Specified Operating Storage 1 SPS samples per second 2 FSR full scale range 4VREF 3 It will not be possible to reach the digital output full scale code when VREr gt AVDD 2 ADS1224 4i TEXAS INSTRUMENTS www ti com SBAS286C JUNE 2003 REVISED JANUARY 2009 PIN ASSIGNMENTS PW PACKAGE TSSOP TOP VIEW DVDD SCLK CLK DRDY DOUT MER ADS1224 MUX1 TEMPEN BUFEN AINP4 AINN4 Terminal Functions TERMINAL NAME NO VO DESCRIPTION DVDD 1 Digital Digital power supply SCLK 2 Digital input Serial clock input CLK 3 Digital input System clock input DRDY DOUT Digital Ouput Dual purpose output Data Ready indicates valid
5. Data Retrieval with DRDY DOUT Forced High Afterwards Data Ready After Calibration PEO Begin Calibration SCLK a es 5 c Self Calibration Data Ready Standby Mode A E Start Conversion SCLK PLY LE Ly 2 d Standby Mode Single Conversions Data Ready After Calibration Standby Mode DRDY DOUT Begin Calibration e Standby Mode Single Conversions with Self Calibration Figure 33 Summary of Serial Interface Waveforms 20 ADS1224 ki TEXAS INSTRUMENTS www ti com SBAS286C JUNE 2003 REVISED JANUARY 2009 Revision History DATE REV PAGE SECTION DESCRIPTION Analog Input Measurement with the Added last sentence to first paragraph describing standby mode 12 2 08 Input Buffer Standby Mode Added last sentence to first paragraph describing standby mode NOTE Page numbers for previous revisions may differ from page numbers in the current version 21 Texas PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 25 Nov 2008 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Type Drawing Qty ADS1224IPWR ACTIVE TSSOP PW 20 2000 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br ADS1224IPWRG4 ACTIVE TSSOP PW 20 2000 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br ADS1224IPWT ACTIVE TSSOP PW 20 250 Green RoHS amp CU NIPDAU Level 2 260C 1 Y
6. When only single conversions are needed the ADS1224 can be quickly shut down Standby mode APPLICATIONS while idle between measurements to dramatically reduce the overall power consumption Multiple Hand Held Instrumentation ADS1224s can be connected together to create a Portable Medical Equipment synchronously sampling multichannel measurement Industrial Process Control system The ADS1224 is designed to easily connect to microcontrollers such as the MSP430 Weigh Scales The ADS1224 supports 2 7V to 5 5V analog supplies and 2 7V to 5 5V digital supplies Power is typically less than 1mW in 3V operation and less than 1uW during Standby mode TEMPEN AVDD VREFP VREFN DVDD Serial Interface NN2 AZ Digital Filter SCLK and NP3 gt K Modulator DRDY DOUT gt gt gt gt gt gt gt gt O O MUXO MUX1 BUFEN GND Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments A semiconductor products and disclaimers thereto appears at the end of this data sheet All trademarks are the property of their respective owners PRODUCTION DATA information is current as of publication date Products i conform to specifications per the terms of Texas Instruments standard warranty TEXAS Production processing does not necessarily include testing of all parameters IN STRUMENTS www ti com Copyright 2003 2008
7. X TEXAS ADS1224 INSTRUMENTS gt gt www ti com SBAS286C JUNE 2003 REVISED JANUARY 2009 24 Bit Analog to Digital Converter with 4 Channel Differential Input Multiplexer FEATURES DESCRIPTION 240SPS Data Rate with 4MHz Clock The ADS1224 is a 4 channel 24 bit delta sigma ana 20 Bit Effective Resolution log to digital A D converter It offers excellent perfor mance and low power in a TSSOP 20 package The ADS1224 is well suited for demanding high resolution measurements especially in portable systems and oth Input Multiplexer with Four Differential Channels Pin Selectable High Impedance Input Buffer er space saving and power constrained applications 5V Differential Input Range A delta sigma AX modulator and digital filter form the 0 0003 INL typ 0 0015 INL max basis of the A D converter The analog modulator has Self Calibrating a 5V differential input range An input multiplexer e Wi MUX is used to select between four separate Sipe Serial Interiaca differential input channels A buffer can be selected to On Chip Temperature Sensor increase the input impedance of the measurement Single Conversions m Standby Mode A simple 2 wire serial interface provides all the Low Current Consumption 3004A necessary control Data retrieval self calibration and Analog Supply 2 7V to 5 5V Standby mode are handled with a few simple e Digital Supply 2 7V to 5 5V waveforms
8. military aerospace applications or environments Buyer acknowledges and agrees that any military or aerospace use of Tl components which have not been so designated is solely at the Buyer s risk and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use TI has specifically designated certain components as meeting ISO TS16949 requirements mainly for automotive use In any case of use of non designated products TI will not be responsible for any failure to meet ISO TS16949 Products Applications Audio www ti com audio Automotive and Transportation www ti com automotive Amplifiers amplifier ti com Communications and Telecom www ti com communications Data Converters DLP Products DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID OMAP Applications Processors Wireless Connectivity dataconverter ti com www dlp com www ti com clocks interface ti com logic ti com microcontroller ti com www ti rfid com www ti com omap Computers and Peripherals Consumer Electronics Energy and Lighting Industrial Medical Security Space Avionics and Defense Video and Imaging TI E2E Community www ti com wirelessconnectivity www ti com computers www ti com consumer apps www ti com energy www ti com industrial www ti com medical www ti com security www ti com space avionics defense www ti com video Mailing
9. Calibration Y Calibration Begins 25 26 lg SYMBOL DESCRIPTION MN UNITS tg 1 First data ready after calibration 1 Values given for fci 2MHz For different fci frequencies scale proportional to CLK period Figure 27 Self Calibration Timing 15 ADS1224 SBAS286C JUNE 2003 REVISED JANUARY 2009 DRDY DOUT TEXAS INSTRUMENTS www ti com Data Ready Standby Mode 23 X 22 X 21 00 aa Conversion a EN 1 1 SCLK high after DRDY DOUT goes low to activate Standby mode 0 8 272 ms 8 272 8 304 ms 27 7 28 1 ms 2 Values given for fci 2MHz For different frequencies scale proportional to CLK period Standby mode activation time Data ready after exiting Standby mode Figure 28 Standby Mode Timing can be used for single conversions DRDY DOUT Data Ready After Calibration Standby Mode X 2 X21 X Begin Calibration 5 a SYMBOL DESCRIPTION UNITS 1121 Data ready after exiting Standby mode and calibration 1 Values given for fc 2MHz For different fci frequencies scale proportional to CLK period Figure 29 Standby Mode with Self Calibration Timing can be used for single conversions SINGLE CONVERSIONS When only single conversions are needed Standby mode can be used to start and stop the ADS1224 To make a single conversion first
10. Texas Instruments Incorporated ADS1224 SBAS286C JUNE 2003 REVISED JANUARY 2009 ORDERING INFORMATION 1 PACKAGE PRODUCT PACKAGE LEAD DESIGNATOR Ww TEXAS INSTRUMENTS www ti com SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA QUANTITY ADS1224IPWT Tape and Reel 250 ADS1224 TSSOP 20 40 C to 85 C ADS1224 ADS1224IPWR Tape and Reel 2500 For the most current specification and package information refer to our web site at www ti com ABSOLUTE MAXIMUM RATINGS over operating free air temperature range unless otherwise noted 1 AVDD to GND 0 3 to 6 V DVDD to GND 0 3 to 6 V 100 momentary mA Input current 10 continuous mA Analog input voltage to GND 0 3 to AVDD 0 3 V Digital input voltage to GND 0 3 to DVDD 0 3 V Maximum Junction Temperature 150 C Operating Temperature Range 55 to 125 C Storage Temperature Range 60 to 150 C Lead Temperature soldering 10s 300 1 Stresses above these ratings may cause permanent damage Exposure to absolute maximum conditions for extended periods may degrade device reliability These are stress ratings only and functional operation of the device at these or any other conditions beyond those specified is not implied This integrated circuit can be damaged by ESD Texas 6 A Instruments recommends that all integrated circuits be handled with appropriate p
11. as close as possible to the pins CLOCK INPUT CLK This digital input supplies the system clock to the ADS1224 The CLK frequency can be increased to speed up the data rate CLK must be left running during normal operation It may be turned off during Standby mode to save power but this is not required The CLK input may be driven with 5V logic regardless of the DVDD or AVDD voltage Minimize the overshoot and undershoot on CLK for the best analog performance A small resistor in series with CLK 100 to 10090 can often help CLK can be generated from a number of sources including standalone crystal oscillators and microcontrollers DATA READY DATA OUTPUT DRDY DOUT This digital output pin serves two purposes First it indicates when new data is ready by going LOW Afterwards on the first rising edge of SCLK the DRDY DOUT pin changes function and begins outputting the conversion data most significant bit MSB first Data is shifted out on each subsequent SCLK rising edge After all 24 bits have been retrieved ADS1224 SBAS286C JUNE 2003 REVISED JANUARY 2009 the pin can be forced high with an additional SCLK It will then stay high until new data is ready This is useful when polling on the status of DRDY DOUT to determine when to begin data retrieval SERIAL CLOCK INPUT SCLK This digital input shifts serial data out with each rising edge As with CLK this input may be driven with 5V logic regardless
12. of the DVDD or AVDD voltage There is hysteresis built into this input but care should still be taken to ensure a clean signal Glitches or slow rising signals can cause unwanted additional shifting For this reason it is best to make sure the rise and fall times of SCLK are less than 50ns FREQUENCY RESPONSE The ADS1224 frequency response for 2MHz is shown in Figure 20 The frequency response repeats at multiples of the modulator sampling frequency of 62 5kHz The overall response is that of a low pass filter with a 3db cutoff frequency of 31 5Hz As shown the ADS1224 does a good job attenuating out to GOKHz For the best resolution limit the input bandwidth to less than this value to keep higher frequency noise from affecting performance Often a simple RC filter on the ADS1224 analog inputs is all that is needed 31250 Input Frequency Hz Figure 20 Frequency Response 11 ADS1224 SBAS286C JUNE 2003 REVISED JANUARY 2009 To help see the response at lower frequencies Figure 21 illustrates the response out to 1kHz Notice that signals at multiples of 120Hz are rejected The ADS1224 data rate and frequency response scale directly with CLK frequency For example if fci increases from 2MHz to 4MHz the data rate increases from 120SPS to 240SPS while the notches increase from 120Hz to 240Hz 100 200 300 400 500 600 700 800 900 1k Input Frequency H
13. power consumption typically lt 1uW with CLK stopped by shutting down all of the active circuitry To enter Standby mode simply hold SCLK high after DRDY DOUT goes low as shown in Figure 28 Standby mode can be initiated at any time during readback it is not necessary to retrieve all 24 bits of data beforehand Note that during standby mode the buffer must be disabled to prevent loading of the inputs When t44 has passed with SCLK held high Standby mode will activate DRDY DOUT stays high when Standby mode begins SCLK must remain high to stay in Standby mode To exit Standby mode wakeup set SCLK low The first data after exiting Standby mode is valid It is not necessary to stop CLK during Standby mode but doing so will further reduce the digital supply current Standby Mode With Self Calibration Self calibration can be set to run immediately after exiting Standby mode This is useful when the ADS1224 is put in Standby mode for long periods of time and self calibration is desired afterwards to compensate for temperature or supply voltage changes To force a self calibration with Standby mode shift 25 bits out before taking SCLK high to enter Standby mode Self calibration then begins after wakeup Figure 29 shows the appropriate timing Note the extra time needed after wakeup for calibration before data is ready The first data after Standby mode with self calibration is fully settled and can be used Data Ready After
14. the original channel By toggling the mux the ADS1224 resets the digital filter and initiates a new conversion During this time the DRDY DOUT line is held high until fully settled data is available DATA FORMAT The ADS1224 outputs 24 bits of data in binary two s complement format The least significant bit LSB has a weight of 2VREF 223 1 The positive full scale input produces an output code of 7FFFFFh and the negative full scale input produces an output code of 800000h The output clips at these codes for signals exceeding full scale Table 2 summarizes the ideal output codes for different input signals Abrupt change in external Vi ADS1224 SBAS286C JUNE 2003 REVISED JANUARY 2009 Table 2 Ideal Output Code vs Input Signal INPUT SIGNAL Vin AINP AINN IDEAL OUTPUT CODE 1 gt 2V REF 7FFFFFh 2V REF 000001h 223 1 0 000000h Vner FFFFFFh 223 1 223 800000h 1522 1 Excludes effects of noise INL offset and gain errors DATA RETRIEVAL The ADS1224 continuously converts the analog input signal To retrieve data wait until DRDY DOUT goes low as shown in Figure 25 After this occurs begin shifting out the data by applying SCLKs Data is shifted out MSB first It is not required to shift out all 24 bits of data but the data must be retrieved before the new data is updated see to or else it will be overwritten Avoid data retrieval during the update period DRD
15. used in the MSC1210 for temperature measurement For more information see Tl application report SBAA100 Using the MSC121x as a High Precision Intelligent Temperature Sensor available for download at www ti com TEMPEN 53020532052 O 0 7 Figure 18 Measurement of the Temperature Sensor in the Input Multiplexer 10 TEXAS INSTRUMENTS www ti com VOLTAGE REFERENCE INPUTS VREFP VREFN The voltage reference used by the modulator is generated from the voltage difference between VREFP and VREFN Vngre VREFP VREFN The reference inputs use a structure similar to that of the analog inputs A simplified diagram of the circuitry on the reference inputs is shown in Figure 19 The switches and capacitors can be modeled with an effective impedance of t E 16pF 500kQ where fo_K 2MHz VREFP VREFN Figure 19 Simplified Reference input Circuitry ESD diodes protect the reference inputs To prevent these diodes from turning on make sure the voltages on the reference pins do not go below GND by more than 100mV and likewise do not exceed AVDD by 100mV GND 100mV VREFP VREFN AVDD 100mV During self gain calibration all the switches in the input multiplexer are opened VREFN is internally connected to AINN and VREFP is connected to AINP The input buffer may be disabled or enabled during calibration When the b
16. 5 NOM Seating Plane 20 MAX 0 15 0 10 0 05 PINS DIM A MAX A MIN 4040064 F 01 97 NOTES A All linear dimensions in millimeters This drawing is subject to change without notice Body dimensions do not include mold flash or protrusion not to exceed 0 15 Falls within JEDEC MO 153 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 H PACKAGE OPTION ADDENDUM TEXAS INSTRUMENTS www ti com PACKAGING INFORMATION 11 Apr 2013 Orderable Device Status Package Type Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Op Temp C Top Side Markings Samples 1 Drawing Qty 2 3 4 ADS1224IPWR ACTIVE TSSOP PW 20 2000 pe CU NIPDAU Level 2 260C 1 YEAR 40 to 85 ADS1224 ADS1224IPWRG4 ACTIVE TSSOP PW 20 2000 CU NIPDAU Level 2 260C 1 YEAR 40 to 85 ADS1224 ADS1224IPWT ACTIVE TSSOP PW 20 250 posi CU NIPDAU Level 2 260C 1 YEAR 40 to 85 ADS1224 ADS1224IPWTG4 ACTIVE TSSOP PW 20 250 poscis CU NIPDAU Level 2 260C 1 YEAR 40 to 85 ADS1224 0 The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in produc
17. Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2015 Texas Instruments Incorporated
18. EAR no Sb Br ADS1224IPWTG4 ACTIVE TSSOP PW 20 250 Green RoHS amp CU NIPDAU Level 2 260C 1 YEAR no Sb Br The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free RoHS Pb Free RoHS Exempt or Green RoHS amp no Sb Br please check http Awww ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 196 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2
19. LS INFORMATION INSTRUMENTS www ti com 26 Jan 2013 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS Diameter Dimension designed to accommodate the component width BO Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness y Overall width of the carrier tape Y Pitch between successive cavity centers Reel Width W1 QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O O COO 0 O Sprocket Holes Q1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 User Direction of Feed Pocket Quadrants All dimensions are nominal Device Package Package SPQ Reel Reel AO BO KO P1 1 Type Drawing Diameter Width mm mm mm mm mm Quadrant mm W1 mm ADS1224IPWR TSSOP PW 20 2000 330 0 16 4 6 95 7 1 1 6 8 0 16 0 01 ADS1224IPWT TSSOP PW 20 250 180 0 16 4 6 95 7 1 1 6 8 0 16 0 01 Pack Materials Page 1 ip TEXAS PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 26 Jan 2013 TAPE AND REEL BOX DIMENSIONS All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length mm Width mm Height mm ADS1224IPWR TSSOP PW 20 2000 367 0 367 0 38 0 ADS1224IPWT TSSOP PW 20 250 210 0 185 0 35 0 Pack Materials Page 2 MECHANICAL DATA PW R PDSO G20 PLASTIC SMALL OUTLINE
20. NFORMATION INSTRUMENTS www ti com 30 Jan 2009 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS Reel Diameter Dimension designed to accommodate the component width BO Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness y Overall width of the carrier tape Y Pitch between successive cavity centers t Reel Width W1 QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes User Direction of Feed All dimensions are nominal Device Package Package Pins SPQ Reel Reel A0 mm BO mm KO mm P1 Pini Type Drawing Diameter Width mm mm Quadrant mm W1 mm ADS1224IPWR TSSOP PW 20 2000 330 0 16 4 6 95 7 1 1 6 8 0 16 0 Q1 ADS1224IPWT TSSOP PW 20 250 180 0 16 4 6 95 7 1 1 6 8 0 16 0 01 Pack Materials Page 1 X3 Texas PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 30 Jan 2009 TAPE AND REEL BOX DIMENSIONS All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length mm Width mm Height mm ADS1224IPWR TSSOP PW 20 2000 346 0 346 0 33 0 ADS1224IPWT TSSOP PW 20 250 190 5 212 7 31 8 Pack Materials Page 2 MECHANICAL DATA MTSS001C JANUARY 1995 REVISED FEBRUARY 1999 PW R PDSO G PLASTIC SMALL OUTLINE PACKAGE 14 PINS SHOWN 0 1
21. TS www ti com SELF CALIBRATION Self calibration can be initiated at any time although in many applications the ADS1224 drift performance is so good that the self calibration performed automatically at power up is all that is needed To initiate self calibration apply at least two additional SCLKs after retrieving 24 bits of data Figure 27 shows the timing pattern The 25th SCLK will send DRDY DOUT high The falling edge of the 26th SCLK will begin the calibration cycle Additional SCLK pulses may be sent after the 26th SCLK however activity on SCLK should be minimized during calibration for best results When the calibration is complete DRDY DOUT goes low indicating that new data is ready There is no need to alter the analog input signal applied to the ADS1224 during calibration the input pins are disconnected within the A D converter and the appropriate signals are applied internally and automatically The first conversion after a calibration is fully settled and valid for use The time required for a calibration depends on two independent signals the falling edge of SCLK and an internal clock derived from CLK Variations in the internal calibration values will change the time required for calibration tg within the range given by the min max specs 111 and t42 described in the next section are affected likewise ADS1224 SBAS286C JUNE 2003 REVISED JANUARY 2009 STANDBY MODE Standby mode dramatically reduces
22. Y DOUT remain at the state of the last bit shifted out until it is taken high see tg indicating that new data is being updated To avoid having DRDY DOUT remain in the state of the last bit shift a 25th SCLK to force DRDY DOUT high see Figure 26 This technique is useful when a host controlling the ADS1224 is polling DRDY DOUT to determine when data is ready Vin Start of 4 conversion 74 includes DRDY DOUT unsettled Vi Conversion time First Conversion Second Conversion Third Conversion Vin settled but Vin settled but digital filter MK digital filter unsettled unsettled Fourth Conversion 74 Vin and digital filter both settled Figure 24 Settling Time in Continuous Conversion Mode 13 ADS1224 TEXAS INSTRUMENTS www ti com SBAS286C JUNE 2003 REVISED JANUARY 2009 Data Ready New Data Ready y DRDY DOUT DRDY DOUT low to first SCLK rising edge SCLK positive or negative pulse width SCLK rising edge to new data bit valid propogation delay SCLK rising edge to old data bit valid hold time Data updating no readback allowed Conversion time 1 data rate 1 Values given for fci 2MHz For different fcLK frequencies scale proportional to CLK period Figure 25 Data Retrieval Timing Data Ready New Data Ready 25th SCLK to Force DRDY DOUT High Figure 26 Data Retrieval with DRDY DOUT Forced High Afterwards 14 TEXAS INSTRUMEN
23. all devices To synchronize the ADS1224s connect the same SCLK signal to all devices Then place all the devices in Standby mode Afterwards starting a conversion will synchronize all the ADS1224s that is they will sample the input signals simultaneously The DRDY DOUT outputs will go low at approximately the same time after synchronization When reading data from the devices the data appears in parallel on DRDY DOUT as a result of the common SCLK connection ADs1224 AINP1 AINN1 Inputs i AINP4 MUX Select lt ADS1224 Inputs MUX Select lt CLK and SCLK Sources 35 TEXAS INSTRUMENTS www ti com The falling edges of DRDY DOUT indicating that new data is ready will vary with respect to each other no more than time t43 This variation is due to possible differences in the ADS1224 internal calibration settings To account for this when using multiple devices either wait for t43 to pass after seeing one DRDY DOUT go low or wait until all DRDY DOUTs have gone low before retrieving data Note that changing channels using the MUXO and pins or using the input buffer BUFEN or the temperature sensor TEMPEN may require more care to settle the digital filter For example if the MUXO pin is toggled on one device and not the other the DRDY DOUT line will be held high until the conversion settles on the first device The latter device will continue conversions
24. ase Customers should contact their board assembly site for stencil design recommendations Refer to IPC 7525 for other stencil recommendations E Customers should contact their board fabrication site for solder mask tolerances between and around signal pads X69 TEXAS INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries reserve the right to make corrections enhancements improvements and other changes to its semiconductor products and services per JESD46 latest issue and to discontinue any product or service per JESD48 latest issue Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All semiconductor products also referred to herein as components are sold subject to 115 terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its components to the specifications applicable at the time of sale in accordance with the warranty Tl s terms and conditions of sale of semiconductor products Testing and other quality control techniques are used to the extent deems necessary to support this warranty Except where mandated by applicable law testing of all parameters of each component is not necessarily performed TI assumes no liability for applications assistance or the design of Buyers products Buyers are responsible for their products and ap
25. c 10 E i 5 5 8 amp 9 05 eo z o z 0 o 4 m 0 5 ur c WD O 10 KE de C 10 yop oo AS ey ie Input Voltage Vi V Input Voltage Vi V Figure 11 Figure 12 ADS1224 SBAS286C JUNE 2003 REVISED JANUARY 2009 OVERVIEW The ADS1224 is an A D converter comprised of a delta sigma modulator followed by a digital filter A mux allows for one of four input channels to be selected A buffer can also be selected to increase the input impedance The modulator measures the differential input signal ViN AINP AINN against the differential reference VREFP VREFN Figure 13 shows a conceptual diagram of the device The differential reference is scaled internally so that the full scale input range is 2Vpe_r The digital filter receives the modulator signal and provides a low noise digital output A 2 wire serial interface indicates conversion completion and provides the user with the output data ANALOG INPUTS AINPx AINNx The input signal to be measured is applied to the input pins AINPx and AINNx The positive internal input is generalized as AINP and the negative internal input is generalized as AINN The signal is selected though the input mux which is controlled by pins MUXO and MUX1 TEMPEN A A A A A A A A TEXAS INSTRUMENTS www ti com as shown in Table 1 The ADS1224 accepts differential inpu
26. dance The buffer charges the input sampling capacitors thus removing the load from the measurement Because the input buffer is chopper stabilized the charging of parasitic capacitances causes the charge to be carried away as if by resistance The input impedance can be modeled by a single resistor as shown in Figure 17 The impedance scales inversely with fc frequency as in the nonbuffered case Note that during standby mode the buffer must be disabled to prevent loading of the inputs NOTE 1 2MHz Figure 17 Effective Analog Input Impedances with the Buffer On Note also that the analog inputs listed in the Electrical Characteristics table as Absolute Input Range must remain between GND 0 05V to AVDD 1 5V Exceeding this range degrades linearity and results in performance outside the specified limits ADS1224 SBAS286C JUNE 2003 REVISED JANUARY 2009 TEMPERATURE SENSOR On chip diodes provide temperature sensing capabili ty By setting the TEMPEN pin high the selected analog inputs are disconnected and the inputs to the A D converter are connected to the anodes of two diodes scaled to 1x and 64x in current and size inside the mux as shown in Figure 18 By measuring the difference in voltage of these diodes temperature changes can be inferred from a baseline temperature Typically the difference in diode voltages is 106mV at 25 C with a temperature coefficient of 3604 V C A similar structure is
27. data by going low Data Output outputs data MSB first on the rising edge of SCLK AINP4 9 Analog input Analog channel 4 positive input AINN4 10 Analog input Analog channel 4 negative input AINP3 11 Analog input Analog channel 3 positive input ADS1224 TEXAS INSTRUMENTS www ti com SBAS286C JUNE 2003 REVISED JANUARY 2009 TYPICAL CHARACTERISTICS At TA 40 C to 85 C AVDD 5V DVDD 5V K 2MHz and VREF 2 5V unless otherwise noted ANALOG CURRENT vs TEMPERATURE ANALOG CURRENT vs TEMPERATURE 500 Buffer Off Buffer On fci 4MHz AVDD fork 4MHz AVDD 5V 1 2 450 fork 2MHz AVDD 5V fork 2MHz AVDD 5V E 3 fork 4MHz AVDD 3V 400 E MHz AVD E fork 2MHz AVDD 3V 350 300 55 25 5 35 65 95 125 55 25 5 35 65 95 125 Temperature C Temperature Figure 1 Figure 2 DIGITAL CURRENT vs TEMPERATURE ANALOG CURRENT vs SUPPLY VOLTAGE 450 400 fork 4MHz AVDD 5V 5 350 2MHz AVDD 5V o 8 m 5 ins fork 4MHz AVDD 3V 250 fc 2MHz AVDD 3V 200 55 25 5 35 65 95 125 2 5 3 0 3 5 4 0 45 5 0 5 5 Temperature Supply Voltage V Figure 3 Figure 4 DIGITAL CURRENT vs SUPPLY VOLTAGE TEMPERATURE SENSOR VOLTAGE vs TEMPERATURE 150 140 0
28. enter the Standby mode holding SCLK high Now when ready to start the conversion take SCLK low The ADS1224 wakes up and begins the conversion Wait for DRDY DOUT to go low and then retrieve the data Afterwards take SCLK 16 high to stop the ADS1224 from converting and re enter Standby mode Continue to hold SCLK high until ready to start the next conversion Operating in this fashion greatly reduces power consumption since the ADS1224 is shut down while idle between conversions Self calibrations can be performed prior to the start of the single conversions by using the waveform shown in Figure 29 TEXAS INSTRUMENTS www ti com APPLICATIONS INFORMATION GENERAL RECOMMENDATIONS The ADS1224 is a high resolution A D converter Achieving optimal device performance requires careful attention to the support circuitry and printed circuit board PCB design Figure 30 shows the basic connections for the ADS1224 As with any precision circuit be sure to use good supply bypassing capacitor techniques A smaller value ceramic capacitor in parallel with a larger value tantulum capacitor works well Place the capacitors in particular the ceramic ones close to the supply pins Use a ground plane and tie the ADS1224 GND pin and bypass capacitors directly to it Avoid ringing on the digital inputs Small resistors 100Q in series with the digital pins can help by controlling the trace impedance Place these resistors at the so
29. harges to OV This two phase sample discharge cycle repeats with a frequency of fcLK 32 62 5kHz for fci 2 2 ESD Protection AVDD 2 AVDD 2 Figure 14 Simplified Input Structure with the Buffer Turned Off I tsampe 32 fo Figure 15 S4 and S Switch Timing for Figure 14 The constant charging of the input capacitors presents a load on the inputs that can be represented by effective impedances Figure 16 shows the input circuitry with the capacitors and switches of Figure 14 replaced by their effective impedances These impedances scale inversely with fci frequency For example if fci frequency is reduced by a factor of 2 the impedances will double ADS1224 SBAS286C JUNE 2003 REVISED JANUARY 2009 AVDD 2 8 Zeff tsampLe Ca 6 52 C Zef 0 6M 0 Zeff O AVDD 2 NOTE 1 2MHz Figure 16 Effective Analog Input Impedances with the Buffer Off ESD diodes protect the inputs To keep these diodes from turning on make sure the voltages on the input pins do not go below GND by more than 100mV and likewise do not exceed AVDD by 100mV GND 100mV lt AINP AINN lt AVDD 100mV Analog Input Measurement with the Input Buffer When the buffer is enabled by setting the BUFEN pin high a low drift chopper stabilized input buffer is used to achieve very high input impe
30. ift Buffer on 02 Offset error match Between channels 20 100 uV 1 Buffer off 0 004 0 025 fai enar Buffer on 0 008 96 c Buffer off 0 00003 of FSR C Gamerordriit Buffer on 0 00006 of FSR C Gain error match Between channels 0 0005 E Buffer off at DC 90 110 dB Common mode rejection Buffer on at DC 90 110 dB E Buffer off at DC 10 Ain AVDD 95 dB Analog power supply rejection Buffer on at DC 10 A in AVDD 95 dB 1 Buffer off at DC DVDD 2 7V to 5 5V 85 dB Digital power supply rejection Buffer on at DC DVDD 2 7V to 5 5V 85 dB Noise 0 8 ppm of FSR rms Temperature Sensor Temperature sensor voltage Ta 25 C 106 mV Temperature sensor coefficient 360 uV C Voltage Reference Input Reference input voltage VREF VREFP VREFN 05 2 5 AVDD S V Negative reference input Buffer off GND 0 1 VREFP 0 5 V Positive reference input Buffer off VREFN 0 5 AVDD 0 1 V Negative reference input Buffer on GND 0 05 VREFP 0 5 V Positive reference input Buffer on VREFN 0 5 AVDD 1 5 V Voltage reference impedance fcLK 2MHz 500 kQ 1 SPS samples per second 2 FSR full scale range 4VREF 3 It will not be possible to reach the digital output full scale code when VREr gt AVDD 2 ADS1224 TEXAS INSTRUMENTS www ti com SBAS286C JUNE 2003 REVISED JANUARY 2009 ELECTRICAL CHARACTERISTICS continued All specifications at TA 40 C to 85 C AVDD
31. itivity Level rating according to the JEDEC industry standard classifications and peak solder temperature e Multiple Top Side Markings will be inside parentheses Only one Top Side Marking contained in parentheses and separated by a will appear on a device If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top Side Marking for that device Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis Addendum Page 1 H PACKAGE OPTION ADDENDUM TEXAS INSTRUMENTS www ti com 11 Apr 2013 Addendum Page 2 ip TEXAS PACKAGE MATERIA
32. lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 196 by weight in homogeneous material 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis Addendum Page 1 X3 Texas PACKAGE MATERIALS I
33. or example switch channels temp sensor buffer enable ADS1224 holds DRDY DOUT until digital filter settles DRDY DOUT Fully settled 74 data ready DRDY DOUT suppressed after status change mm wmm T ues Settling time DRDY DOUT held high after a change in any of the MUXO pd BUFEN or TEMPEN pins Values given for fc 2MHz For different fc frequencies scale proportional to CLK period Figure 23 Example of Settling Time After Changing the Input Multiplexer 12 Texas INSTRUMENTS www ti com The ADS1224 uses a Sinc digital filter to improve noise performance Therefore in certain instances large changes in input will require settling time For example an external multiplexer in front of the ADS1224 can put large changes in input voltage by simply switching input channels Abrupt changes in the input will require three data cycles to settle When continuously converting four readings may be necessary to settle the data If the change in input occurs in the middle of the first conver sion three more full conversions of the fully settled input will be required to get fully settled data Discard the first three readings because they will contain only partially settled data Figure 24 illustrates the settling time for the ADS1224 in Continuous Conversion mode If the input is known to change abruptly the mux can be quickly switched to an alternate channel and quickly switched back to
34. plications using Tl components To minimize the risks associated with Buyers products and applications Buyers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right relating to any combination machine or process in which TI components or services are used Information published by TI regarding third party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice Tl is not res
35. ponsible or liable for any such statements Buyer acknowledges and agrees that it is solely responsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any applications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures monitor failures and their consequences lessen the likelihood of failures that might cause harm and take appropriate remedial actions Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety critical applications In some cases components may be promoted specifically to facilitate safety related applications With such components goal is to help enable customers to design and create their own end product solutions that meet applicable functional safety standards and requirements Nonetheless such components are subject to these terms No TI components are authorized for use in FDA Class III or similar life critical medical equipment unless authorized officers of the parties have executed a special agreement specifically governing such use Only those TI components which TI has specifically designated as military grade or enhanced plastic are designed and intended for use in
36. recautions Failure to observe proper handling and installation procedures can cause damage ESD damage can range from subtle performance degradation to complete device failure Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications 1 ADS1224 35 TEXAS INSTRUMENTS www ti com SBAS286C JUNE 2003 REVISED JANUARY 2009 ELECTRICAL CHARACTERISTICS All specifications at TA 40 C to 85 C AVDD 5V DVDD 5V fci 2MHz and VREF 2 5V unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Analog Input Full scale input voltage AINP AINN 2VREF V Buffer AINP AINN with respect to GND GND 0 1 AVDD 0 1 V Iie ig Buffer on AINP AINN with respect GND GND 0 05 AVDD 15 V Differential input impedance Auter o 2818 eif Buffer on 2MHz 1 2 GQ Common mode input impedance Buffer off fc 2MHz 5 4 MQ System Performance Resolution No missing codes 24 Bits Data rate 120 fci k 2MHz sPs 1 liters manna NDS Buffer off Differential input signal end point fit 0 0003 0 0015 of FSR 2 Buffer on Differential input signal end point fit 0 0006 96 of FSR Buffer off 20 100 uV Offset error Buffer on 20 uv Buffer off 0 2 uV C Offset error dr
37. t signals but can also measure unipolar signals When measuring unipolar or single ended signals with respect to ground connect the negative input AINNx to ground and connect the input signal to the positive input AINPx Note that when the ADS1224 is configured this way only half of the converter full scale range is used since only positive digital output codes are produced An input buffer can be selected to increase the input impedance of the A D converter with the BUFEN pin Table 1 Input Channel selection with MUXO and 67 DIGITAL PINS SELECTED ANALOG INPUTS MUX1 MUXO POSITIVE INPUT NEGATIVE INPUT 0 0 AINP1 AINN1 0 AINP2 AINN2 1 1 0 AINN3 1 1 AINP4 AINN4 Digital Filter and Serial DRDY DOUT Interface Figure 13 Conceptual Diagram of the ADS1224 TEXAS INSTRUMENTS www ti com Analog Input Measurement without the Input Buffer With the buffer disabled by setting the BUFEN pin low the ADS1224 measures the input signal using internal capacitors that are continuously charged and discharged Figure 14 shows a simplified schematic of the ADS1224 input circuitry with Figure 15 showing the on off timings of the switches The S4 switches close during the input sampling phase With S1 closed Ca charges to AINP Cao charges to AINN and Cp charges to AINP AINN For the discharge phase S4 opens first and then So closes CA4 and Cao discharge to approximately AVDD 2 and disc
38. through this time See the Settling Time section of this data sheet for further details SYMBOL DESCRIPTION UNITS t130 Difference between DRDY DOUTs going low in multichannel 0 8 systems Values given for fc 2MHz For different frequencies scale proportional to CLK period Figure 31 Example of Using Multiple ADS1224s in Parallel 18 35 TEXAS INSTRUMENTS www ti com VESSEL WEIGHING WITH FOUR LOAD CELLS In vessel weighing systems four load cells are frequently employed to measure the weight of the vessel and its contents The output of the load cells are usually combined in an external summing junction box that balances the load cells sensitivities for accuracy The four differential inputs of the ADS1224 allow for direct measurement of the four load cells individually In this way the mechanical adjustments performed inside the summing junction box are eliminated and are replaced by digital summing of the load cells in software Figure 32 shows an example of such a system The reference voltage of the ADS1224 is derived by dividing down the AVDD supply voltage to 2 5V while the load cell has a positive full scale output of 10mV In the figure a low drift dual op amp OPA2335 provides ADS1224 SBAS286C JUNE 2003 REVISED JANUARY 2009 a differential in differential out amplifier with a gain of 499V V G 1 2Rp Rg Gain on the load cell gives the amplifier a full scale output of 5V
39. tion to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free ROHS Pb Free ROHS Exempt or Green RoHS amp no Sb Br please check http www ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 1 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 196 by weight in homogeneous material 9 MSL Peak Temp The Moisture Sens
40. uffer is disabled the reference pins will be driving the circuitry shown in Figure 9 during self gain calibration resulting in increased loading To prevent this additional loading from introducing gain errors make sure the circuitry driving the reference pins has adequate drive capability When the buffer is enabled the loading on the reference pins will be much less but the buffer will limit the TEXAS INSTRUMENTS www ti com allowable voltage range on VREFP and VREFN during self or self gain calibration as the reference pins must remain within the specified input range of the buffer in order to establish proper gain calibration For best performance Vngr should be AVDD 2 but it can be raised as high as AVDD When Vpef exceeds AVDD 2 it is not possible to reach the full scale digital output value corresponding to 2Vp_r since this requires the analog inputs to exceed the power supplies For example if AVDD 5V the positive full scale signal is 10V The maximum positive input signal that can be supplied before the ESD diodes turn on is when AINP 5 1 and AINN 0 1V resulting in 5 2V Therefore it is not possible to reach the positive or negative full scale readings in this configuration The digital output codes are limited to approximately one half of the entire range For best performance bypass the voltage reference inputs with a 0 11 capacitor between VREFP and VREFN Place the capacitor
41. urce end 0 1 DVDD SCLK CLK DRDY DOUT MUXO MUX1 TEMPEN BUFEN AINP4 AINN4 0 ADS1224 ADS1224 SBAS286C JUNE 2003 REVISED JANUARY 2009 Pay special attention to the reference and analog inputs These are the most critical circuits Bypass the voltage reference using similar techniques to the supply voltages The quality of the reference directly affects the overall accuracy of the device Make sure to use a low noise and low drift reference such as the REF1004 Often only a simple RC filter is needed on the inputs This circuits limits the higher frequency noise Avoid low grade dielectrics for the capacitors and place them as close as possible to the input pins Keep the traces to the input pins short and carefully watch how they are routed on the PCB After the power supplies and reference voltage have stabilized issue a self calibration command to minimize offset and gain errors O 42 5V Reference 10uF Same as shown for AINP4 and AINN4 Figure 30 Basic Connections 17 ADS1224 SBAS286C JUNE 2003 REVISED JANUARY 2009 MULTICHANNEL SYSTEMS Multiple ADS1224s can be operated in parallel to measure multiple input signals Figure 31 shows an example of an eight channel system For simplicity the supplies and reference circuitry are not shown The same CLK signal should be applied to
42. z Figure 21 Frequency Response to 1kHz Rejecting 50Hz or 60Hz noise is as simple as choosing the clock frequency If simultaneous rejection of 50Hz and 60Hz noise is desired 910kHz can be chosen The data rate becomes 54 7sps and the frequency response of the ADS1224 rejects the 50Hz and 60Hz noise to below 60dB The frequency response of the ADS1224 near 50Hz and 60Hz with 910kHz is shown in Figure 22 35 TEXAS INSTRUMENTS www ti com 50 60 Input Frequency Hz Figure 22 Frequency Response Near 50Hz and 60Hz with fci 910kHz SETTLING TIME After changing the input multiplexer selecting the input buffer or using temperature sensor the first data is fully settled In the ADS1224 the digital filter is allowed to settle after toggling any of the MUX0 MUX1 BUFEN or TEMPEN pins Toggling of any of these digital pins will cause the input to switch to the proper channel start conversions and hold the DRDY DOUT line high until the digital filter is fully settled For example if 0 changes from low to high selecting a different input channel DRDY DOUT immediately goes high and the conversion process restarts DRDY DOUT goes low when fully settled data is ready for retrieval There is no need to discard any data Figure 23 shows the timing of the DRDY DOUT line as the input multiplexer changes MUXO Abrupt change in internal V due to status change f
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