AudioBridge HW User Manual
Contents
1. 2Ch PR N A 8Ch PR SDO3 sp04 8Ch DSI Out 2ChPR N A EM OPT ANA ANA SD06 Attenuation dB Attenuation dB When the 8 channel DSI output is activated the stereo DSI is disabled It is still possible to route any of the DSO1 to SDO4 streams to the SPDIF output In order to operate properly the 8 channel DSI output requires all the sink ports to use the same presence rate If itis not the case the display will show 8Ch PR Mismatch The analogue output level is controllable Press anywhere around the text Attenuation on the right bottom corner to call the numerical keyboard Type any value for the attenuation The value ranges from OdB to 100 dB by step of 1 dB 2Ch PR N A OPT VIA ANA si atts Fiona dB SLIMbus Audio Bridge User Manual V3 02 31 July 2015 10 2 1 4 Loopback Mode The bridge can be placed in loopback mode to re inject on SLIMbus the data it receives from SLIMbus The loopback mode is controlled by a Value Element of the Generic device see section 6 5 of this manual or directly by the PC application When the bridge is used in a stand alone mode it can only be activated through SLIMbus messages Bus Status HW Setup Sr ce ee me PR 7 PO SD02 A T 2Ch PR N A gt EN SPDIF Loopback enabled DA SDO4 mE PS SDO3 sinl DSI spos DO 5004 8Ch DSI Out APE ttt pz L PR P8 2Ch PR N A SD06 A PO SDOS2. PO P1 P1 is configured as a Sink Port PO is configured as a Sink Port P2 is configured as a Source Port P2 P3 is configured as a Source Port rs P4 P4 is configured as a Sink Port PS P5 is configured as a Sink Port P6 P7 P8 P9 is configured as a Source Port P9 ht P10 is configured as a Sink Port P11 P11 is configured as a Sink Port P8 is configured as a Source Port The presence rate is indicated once the ports are configured Note The source ports of each group must use the same Presence Rate because they all use the same audio master clock The sink port pairs can have different Presence Rate as long as the stereo interfaces are used The master clock is changed each time a new port pair is selected When using the 8 channel DSI output mode all the sink ports of the first group must use the same Presence Rate It is possible to configure only one port of a pair or to have the two ports of a pair configured differently In this case the digital stereo stream connecting the SLIMbus port to the legacy interface will only carry one audio channel the other one will carry Os SLIMbus Audio Bridge User Manual V3 02 31 July 2015 14 In this example P6 will transport the channel B of the input stream SDI4 P7 will feed the channel A of the stream SDO4 P8 will feed the channel B of the stream SDO5 and P9 will transport the channel A of the input stream SDI5 2 2 Bus Status This page displays the recorded bus configurat
3. The 4 input data streams are fed through the DSI connector The corresponding word and bit clocks are outputs on the DSI connector the DSI 8 Ch is always clock master Press again the button 8Ch DSI In to go back to nominal stereo operations SLIMbus Audio Bridge User Manual V3 02 31 July 2015 7 E on DSI Tone Tone Setup PR SDI1 LE D SDIS LE Audio pus Framer Internal Audio SLIMbus Framer Internal 8Ch D Ah 8Ch DSI In SDI4 2 1 2 Tone Generator Setup To configure the Tone Generator press the Tone Setup button A new page will appear with the tone generator parameters Tone Generator Setup Exit Channel A Channel B DC Value Ox 76543210 DC Value Ox FEDCBAQ98 PRBS e Waveform PRBS Waveform LV a LE Frequency Hz 1000 00 Frequency Hz 1750 0 Amplitude dBFs 6 50 Amplitude dBFs 8 1 7 Sum Ch Aand ChB Delay samples 7 The Tone Generator has two independent channels The possible signal types are a constant DC value set by the PC application a Pseudo Random Bit Sequence PRBS based on a 16 bit linear feedback shift register a selectable waveform sine square triangle with selectable frequency and amplitude It is also possible to control the delay between the two channels and to sum the two channels on channel A The desired output is selected by pressing the corresponding radio button The frequency amplitude and delay are chang
4. MCLK2 OUTPUT CLOCK DOMAIN Both outputs are slaved to the bridge clock domain 3 4 3 Common Frequencies The following table lists the cardinal frequencies that are likely going to be used with the bridge Note that the bridge makes a best estimate of the measured frequencies by comparing the measured value to the commonly used frequencies and use that estimated value to program the PLLs Do not feed the bridge with an arbitrary frequency that does not relate in anyway to the frequencies listed in the table The PLL generated frequencies might not be as accurate as necessary RF 0 Not Indicated Any frequency RF 1 24 576 MHZ 24 576 MHz RF 2 22 5792 MHZ 22 578998 MHz Error of 202 Hz 22 5792 MHz RF 3 15 36 MHZ 15 36 MHz RFA 16 8 MHZ 16 8 MHz BFS 19 2 MHZ 19 2 ME RF 6 24 MHz 24 MHz AFT 25 MHZ 25 MHz AF B 26 MHZ 25 MHz RF 27 MHZ 27 Mie SLIMbus Audio Bridge User Manual V3 02 31 July 2015 29 5 SLIMbus Operations The bridge will operate accordingly to the SLIMbus specification 5 1 Device Enumeration After the boot sequence the bridge will send 3 REPORT_PRESENT messages The Instance Value IV of the Enumeration Address depends on the value given to the Component address Component address 0 Device wip po or wv Enumeration Address Ox01C1 Ox0002 0x00 0x00 0x01C100020000 0x01C1 0x0002 0x01C100020100 0x01C1 0x0002 0x01C100020200 Component address 1 Interface 0x
5. audio tests it is definitively not an issue When it is about verifying that every sample sent is well received special care must be taken Deactivating a channel does not reset the PLL settings Therefore the channel can be reactivated at any time and be immediately operational Only a port reset through a DISCONNECT_PORT or REMOVE_CHANNEL messages will affect the PLL configuration Note that these recommendations will not apply when an external clock source is used as the audio clocks are required to be present and stable before the audio channel is activated 5 3 ASRC Configuration The bridge uses the DL field Data Length to adequately set the output word length of the asynchronous sample rate converter Dithering is applied on the LSB of the sample for optimal THD N performances The data lengths of interest are 16 bits 4 slots 20 bits 5 slots and 24 bits 6 slots 32 bits data length is not an option when using the ASRCs lf the DL field is smaller than 4 slots the ASRC output word length will be set by default to 16 bits If the DL field is greater than 6 slots or set to Not Indicated the output word length will be set by default to 24 bits The data length is specified by the Data Length field value in the NEXT_DEFINE_ CONTENT message Make sure that the data Segment is large enough to fit the sample as defined by the DL field Otherwise the dithered bit will be lost and the sample truncation will lead to undesir
6. bar 2 3 1 SLIMbus Core Configuration This panel allows the configuration of the various SLIMbus related parameters Data Paths Bus Status SLIMbus Configuration Boot Framing Information PHY Signaling Level 1 80 V Subframe Mode 19 Bus Hold Off Clock Gear 9 Component Address 1 Root Frequency 1 Framer Boot Mode Primary Reset SLIMbus Core SLiMbus Audio Ext Clock Ref Clock Info The PHY signaling voltage can take any value from 0 9V to 3 2V 3 3V compatible by step of 50 mV Press the text field to call the display and type the desired value The 50mV rounding is handled automatically The Bus Hold can be enabled or disabled If there is a Bus Hold active sowere on the SLIMbus the bridge Bus Hold can be disabled If not there must be at least one active bus hold to guarantee error free operation and the bridge Bus Hold must be set The Component Address Instance Value can take the value O or 1 This allows the operation of two bridges on the same SLIMbus The bridge Framer can be set as the Primary bus framer or not By default it should be disabled The Boot Framing Information are fully programmable The framer will use these values when it boot the bus SLIMbus Audio Bridge User Manual V3 02 31 July 2015 16 Finaly the SLIMbus core can be reset This function shall be used when the boot mode or the boot framing information are changed and needed to be used immediately Note that this is a full reset and
7. be used when stereo connections are required from and to the APx analyser The adapters have markings to help identifying the DSIO connector it shall connect to To DSIO Transmitter To DSIO Receiver Refer to the Audio Precision DSIO module documentation for detailed information on the DSIO connector pinning SLIMbus Audio Bridge User Manual V3 02 31 July 2015 24 4 Clock Management The bridge has a powerful and flexible clock management scheme 4 1 Framer Clock Generation The Framer reference clock corresponds to the Root Frequency to be used on SLIMbus lf RF1 24 576MHz has to be used the framer clock generator will feed the SLIMbus Core with a frequency equal to 24 576 MHz 12 MHz SPDIF MCLK OPTICAL MCLK DSI MCLK SMA MCLK FRAMER CLOCK The framer clock can be generated by using five input clocks The default one is the internal 12 MHz clock source If the bridge framer must be frequency locked to another clock domain any of the four other inputs can be used The most accurate results will be obtained from the DSI master clock input on pin 15 of from the external clock SMA connector In some cases the PLL can be automatically bypassed the PLL reference clock frequency is equal to the desired clock frequency the desired clock frequency can be derived from the PLL reference clock by an integer divider This feature can be useful to avoid the jitter generated by the PLL or to be able to inject an on
8. time can be extended to 5 years of continuous operation 2 4 Standby Switch The standby switch is located besides the DC barrel jack on the right side of the hardware Toggle the switch up or down to activate the standby mode The display backlight will be switched off the interfaces will be disconnected and the auxiliary power supplies will be switched off Sleep modes are activated wherever possible stanpey When in standby mode the yellow led located on top of the standby He PWR switch is ON to indicate that the bridge is powered but sleeping lt lt _ The bridge will also wake up if it receives a command from its PC ON application 3 12 VDC Using the standby mode allows the bridge to wake up almost SOD instantaneously much faster than with a power on SLIMbus Audio Bridge User Manual V3 02 31 July 2015 20 3 Bridge Connectivity The bridge interfaces are located on the left and right side of the box LEDs are often associated to the connectors to indicate a status Type Standard 6 pin boxed header with pitch of 0 1 The yellow led on the left side of the connector is ON when the connector pins are connected to the internal circuitry It is possible to disable the SLIMbus connector while the bridge is powered by typing O in the PHY signalling level text field When the bridge is in stand by mode the SLIMbus connector is also disabled The SLIMbus IOs operates on a programmable level that ranges from 0 9
9. 0 30 50 100 200 300 500 1k 2k 3k 5k 10k 20k Frequency Hz 20 bits THD N 120 2 dB 46 20 40 60 80 100 120 140 160 180 poe 200 2205 30 50 100 200 300 500 1k 2k 3k 5k 10k 20k Frequency Hz 32 bits THD N 152 9 dB SLIMbus Audio Bridge User Manual V3 02 31 July 2015 35 7 Electrical Specifications Power Supply Power supply voltage Er Standby power DSI Interface DSI OUT signaling voltage output DSI OUT signaling voltage input Input pin capacitive load 1 384 kHz when the 8 channel DSI mode is used 192 kHz in stereo mode SPDIF IN OUT Interface SPDIF OUT impedance Sample Rate input and output OPTICAL IN OUT Interface Sample Rate input and output z External Clock SMA Signaling voltage input Vclk 1 8V 2 5V or 3 3V VDD 0 3 Input impedance Fewer EE SLIMbus Audio Bridge User Manual V3 02 31 July 2015 36 25 Signaling voltage output aws Analogue Output Parameter Typical Frequency Response Flatness THD N OdBFS 20kHz BW Bandwidth 3dB TE Dynamic Range Analogue Input Input level 0 5 dBFs Input impedance Bandwidth 3dB Frequency Response Flatness a THD N full scale 20kHz BW Dynamic Range i ASRC performances THD N OdBFs 24 bits resolution i Input Output Sampling Ratio ae SLIMbus Audio Bridge User Manual V3 02 31 July 2015 37 SLIMbus Electrical Perform
10. 01C1 0x0002 0x01C100020001 Framer 0x01C1 0x0002 0x01C100020101 Generic 0x01C1 0x0002 0x01C100020201 5 2 Channel Setup When using the PLLs to generate the audio clocks some care must be taken to ensure optimal data transmission and or reception The PLLs are configured once the associated Presence Rate is known The SLIMbus Core communicates that information to the controller when a port is configured and when the associated channel structure and content have been defined by a valid reconfiguration sequence Note that the channel does not need to be active yet to get the bridge to configure itself for the audio operation Once the PLLs are configured and stable it takes less than 3 ms the channel can be activated and the data streaming will start without any latency or loss of data The sequence of message will be as follow CONNECT_SOURCE or CONNECT_SINK messages BEGIN RECONFIGURATION NEXT _DEFINE_CHANNEL NEXT _DEFINE_CONTENT RECONFIGURE_NOW a lt At that moment the PLLs get configured Delay for 3 ms SLIMbus Audio Bridge User Manual V3 02 31 July 2015 30 BEGIN RECONFIGURATION NEXT _ACTIVATE_CHANNEL RECONFIGURE_NOW si lt The data streaming is effectively starting If the channel activation message is in the channel setup sequence there will be a delay of about 3 ms during which the data will either not be transmitted on the bus or not be read When dealing with
11. 11 13 15 16 16 17 18 19 20 20 21 21 21 22 22 23 23 23 23 23 24 25 25 25 26 27 27 28 29 30 30 30 31 31 5 5 Using the Value Elements to configure the Bridge 6 Tone Generator Characteristics 6 1 Pseudo Random Bit Sequence 6 2 Sine Wave 7 Electrical Specifications SLIMbus Audio Bridge User Manual V3 02 31 July 2015 32 34 34 35 36 1 Presentation of the tool The SLIMbus Multilane Audio Bridge makes the link between SLIMbus Multilane and the analogue and digital legacy audio interfaces The main purpose of the bridge is to allow easy tests of audio capabilities of a SLIMbus component with traditional audio analysers Audio Precision Rhode amp Swartiz The bridge is also a fully featured and compliant SLIMbus component with one Interface device a Framer device and a Generic device It can be used to test other SLIMbus components especially SLIMbus Manager or other audio components Main features 12 bidirectional data ports 2 SLIMbus data lines 3 different and concurrent audio clock domains SPDIF input and output Optical input and output DSI 12S stereo input and output DSI 12S 8 channel input or output with 4 data lines no TDM Analogue stereo input and output Tone generator Sine PRBS amp DC value Data loop back function Very flexible clock management I2S_MCLKI 12S 2CH IN DIR SPDIF IN SDOUT1 2 12S 8CH OUT SDI
12. 15 18 2 3 4 PLL Reference Clock Selection Both framer and audio PLLs can be fed by various clocks This panel is used to select which clock will feed which PLL Data Paths Bus Status Internal Clock Configuration Framer PLL clock ref Audio PLL clock ref INTERNAL SLIMbus SPDIF IN 0 000 MHz SPDIF IN OPTICAL IN 0 000 MHz OPTICAL IN DS MCLK 0 000 MHz DS MCLK SMA 0 000 MHz SMA SLIMbus Audio Ext Clock Ref Clock Info Framer Reference Clocks The framer PLL can be fed by several clock sources Internal oscillator a low jitter 12 MHz clock SPDIF input recovered master clock Usually at 256 x Fs Optical input recovered master clock Usually at 256 x Fs DSI master clock input External clock input on SMA Note that the reference clock does not need to match the desired framer clock The bridge measures all the clocks and configures the PLL accordingly If the selected clock appears to have the same frequency as the targeted clock the PLL is bypassed The four frequencies are measured and displayed to help the user to select the proper clock source Framer Reference Clocks The Audio PLL can be fed by several clock sources SLIMbus clock SPDIF input recovered master clock Usually at 256 x Fs Optical input recovered master clock Usually at 256 x Fs DSI master clock input External clock input on SMA When using the SLIMbus clock the clock gear shall stay above 5 CG6 to CG10 Belo
13. INPUT2_ASRC_ENA Activate the Asynchronous Sample Rate Converter of the input 2 group VEO VALIDATE Activate the functions of bit 0 to 6 when set to 1 VEO of the Generic Device at address 0x800 Nene iets OUTPUT1_SELO Select the port pair to be output on SPDIF and DSI outputs OUTPUT1_SEL1 DSI_8CH_ENA Enable 8 CH mode on the DSI interface DSI_8CH_MODE Set the DSI interface as input 0 or output 1 DSI_OUT_ASRC_ENA Activate the Asynchronous Sample Rate Converter of the DSI output DSI_OUT_ASRC_CLK Select the DSI output ASRC master clock O DSI 1 MCLKO1 7 VE1_VALIDATE Activate the functions of bit 0 to 6 when set to 1 VE1 of the Generic Device at address 0x801 OUTPUT2_SEL Select the port pair to be output on Optical and analogue outputs SLIMbus Audio Bridge User Manual V3 02 31 July 2015 32 Nene Toen OOOO DAC output attenuation level in dB ii It ranges from 0 dB to 62 dB by step of 2 dB DAC_ATTNS DAC_ATTN4 EXT CLK_ZIN_SEL Set the input clock impedance 0 1M 1 50R VE2 of the Generic Device at address 0x802 CC OO DSI_LEVELO Select the DSI signaling level DSI_LEVEL1 0 1V8 1 2V5 2 3V3 DSI_IN_FORMAT Set the Stereo DSI input format 0 L J 1 12S Set the DSI IN Master Slave clock mode 0 Slave 1 Master Set the Stereo DSI output format 0 L J 1 12S Set the DSI OUT Master Slave clock mode 0 Slave 1 Master Set the external clock direction 0 input 1 output VE3 o
14. Lak SLIMbus Multilane Audio Bridge User Manual LnK 44 rue des Combattants B 4624 Roms e Belgium www ink tools com info Ink tools com SLIMbus Audio Bridge User Manual V3 02 31 July 2015 1 Presentation of the tool 2 Using the tool 2 1 Data Path 2 1 1 2 1 2 2 1 3 2 1 4 2 1 5 2 1 6 Input Section Tone Generator Setup Output Section Loopback Mode Manual Port Configuration Port Status 2 2 Bus Status 2 3 Hardware Setup 2 3 1 2 3 2 2 3 3 2 3 4 2 3 5 SLIMbus Core Configuration Audio Setup External Clock Configuration PLL Reference Clock Selection Product Information and Diagnostic Values 2 4 Standby Switch 3 Bridge Connectivity 3 1 SLIMbus Connector 3 2 DSI Connector 3 3 Optical and Analogue Input Connector 3 4 Optical and Analogue Output Connector 3 5 SPDIF Input Connector 3 6 SPDIF Output Connector 3 7 External Clock Connector 3 8 USB 2 0 Connector 3 9 DC Supply Barrel Jack 3 10 DSI cable adapters 4 Clock Management 4 1 Framer Clock Generation 4 2 Audio Master Clock Generation 4 2 1 4 2 2 4 2 3 4 2 4 Input Clock Domain 1 MCLKI1 Input Clock Domain 3 MCLK2 Output Clock Domain 2 MCLKO1 Output Clock Domain 3 MCLK2 4 3 Common Frequencies 5 SLIMbus Operations 5 1 Device Enumeration 5 2 Channel Setup 5 3 ASRC Configuration 5 4 Audio Data Format SLIMbus Audio Bridge User Manual V3 02 31 July 2015 Oo Oo OO A
15. N1_1 ORT 0 SDOUT1_1 SDOUTIS SDOUT1_4 gt PORT 1 aie GEN 128 MCLKO PORT 2 SDOUT1_2 DORT S wr v PO bid p 12S OUT 1 12S 8CH IN L O a BCLKI1 LRCLKI1 MCLKO1 BCLKO1 LRCLKO1 DIR TOSLINK IN pen j ANALOG IN STEREO ADC MCLK2 BCLKI2 LRCLKI2 SDOUT2_1 DIT TOSLINK OUT SDOUT2_2 K STEREO DAC ANALOG OUT MCLK2 BCLKO2 LRCLKO2 PORT 11 MCLKI1 EXT_MCLK SrA SLIMbus DIR1_RMCKO DIR2_RMCKO ET I2S_MCLKO CLOCK SHIFTER DATA SLiIMbus Ref Clock SLIMbus Audio Bridge User Manual V3 02 31 July 2015 4 SLIMbus Enumeration Address Component address 0 Interface 0x01C1 0x0002 Ox00 0x01C100020000 Framer 0x01C1 0x0002 Ox00 0x01C100020100 Generic 0x01C1 0x0002 0x01C100020200 Component address 1 Enumeration Address Comes wo re Jo Interface 0x01C1 0x0002 0x01C100020001 Framer 0x01C1 0x0002 0x01 0x01C100020101 Generic 0x01C1 0x0002 0x01C100020201 Data Port Capabilities The 12 data ports support the Isochronous Pushed and Pulled protocols The Data Length is up to 32 bits Port O 1 8 and 9 are manually configurable to listen to already defined channels SLIMbus Audio Bridge User Manual V3 02 31 July 2015 2 Using the tool The bridge can operate as a stand alone device It has its own graphical user interface 4 3 colour display with touch screen for the required parameter changes The GUI is organised
16. OPT Loopback enabled P10 SDOS A SD06 ANA P11 Attenuation dB PO amp P1 P2 amp P3 P4 amp P5 P6 amp P7 P8 amp P9 P10 amp P11 2 1 5 Manual Port Configuration The Data Ports PO P1 P8 and P9 can be manually configured to transmit or receive audio streams The main purpose of that function is to listen to data channel content without having been involved in the channel configuration through SLIMBus messages The background behind these port boxes is purple not grey Push anywhere in the purple rectangle to call the port configuration panel aiian 7 SLIMbus Audio Bridge User Manual V3 02 31 July 2015 11 Manual Port Configuration Port Number PO Pl P8 Pg Exit Port Config Source Sink Disconnect Validate Track Channel Manual Setup By default the ports are in the Disconnected state There are two ways to manually configure a data port a Semi automatic mode In this mode the port will track all the messages related to the specified channels It corresponds to the effect of a CONNECT_ message The remaining of the port configuration is left to the SLIMbus protocol To activate that mode select a port configuration that is either Source or Sink then press the radio button Track Channel Push on the text field to call the keyboard and enter a channel number Manual Port Configuration Port Number PO P1 P8 P9 Exit Port Config Source Sink Disconnect
17. SMA connector indicates the direction of the signal Green it is set as an input Red it is set as an output When the yellow LED at the top right of the SMA connector is ON the 50Q input impedance is active 3 8 USB 2 0 Connector The USB 2 connector is used to remote control the bridge from a PC The bridge is self powered and does not consume any power from the USB Refer to the Audio Bridge software user manual for more detailed information 3 9 DC Supply Barrel Jack This is the power supply connector of the bridge The positive voltage is applied to the centre pin enter GC SLIMbus Audio Bridge User Manual V3 02 31 July 2015 23 3 10 DSI cable adapters Easy connection to Audio Precision APx analyser family with DSIO option is provided through a pair of custom cables The cables are made of standard flat cables 16 ways and standard plugs The user can easily build its on length of cable but be aware of the propagation delays about 1ns per15cm of cable DSI 8 Channel Output Cable The cable has a pin header socket on one side to connect to the bridge DSI and a APx DSIO Receiver adapter on the other side This cable shall only be used to transport the 8 channels from the bridge to the APx To DSIO Receiver or Transmitter DSI Stereo Input and Output Cable The cable has a pin header socket on one side to connect to the bridge DSI and a pair of APx DSIO Receiver AND Transmitter adapters This cable shall only
18. V to 3 2V 3 2 DSI Connector STEREO 12S IN amp OUT DR 8CH 12S OUT E Our 8CH 12S IN MCLKI BCLKI IN OUT LRCLKI IN OUT OUT O O O O LKI O BCLKO IN OUT BCLKO LRCLKO IN OUT LRCLKO uoko NJ MCLKO Type Standard 16 pin boxed header with pitch of 0 1 UT UT UT UT OUT OUT rr RCLKI CLKO SLIMbus Audio Bridge User Manual V3 02 31 July 2015 21 There are four LEDs around the DSI connector The bottom right green LED indicates that the DSI stereo input is used as input The bottom left red LED indicates that the 8 channel DSI output is active The top right bicolour LED indicates wether the DSI stereo output is clock master red or clock slave green The top left bicolour LED indicates wether the DSI stereo input is clock master red or clock slave green All the DSI IOs operate on a programmable level that can be 1 8V 2 5V or 3 3V The source impedance of the DSI outputs is equal to 50Q The input impedance of the DSI inputs is greater than 1MQ When feeding a clock signal to the MCLKO pin pay attention to the cable length for reliable operation 3 3 Optical and Analogue Input Connector The Optical TOSLINK and analogue inputs are sharing the same 3 5mm jack connector They cannot be used both at the same time O RNG RIGHT channel ON Tx SLEEVE en The bicolour LED on the left side of the input connector indicates that the Optical input is selected
19. Validate Track Channel 2 Manual Setup To finish the port configuration press the Validate button Once the desired ports are configured press the Exit button to go back to the Data Paths page b Manual Setup In this mode all the data channel parameters must be manually programmed The full manual configuration corresponds to the complete channel configuration sequence SLIMbus Audio Bridge User Manual V3 02 31 July 2015 12 CONNECT_SINK or CONNECT_SOURCE BEGIN_RECONFIGURATION NEXT_DEFINE_CHANNEL NEXT_DEFINE_CONTENT NEXT_ACTIVATE_CHANNEL RECONFIGURE_NOW Enter all the parameters by pushing on the text field or pressing the buttons The parameters take the values as shown in the SLIMbus specification The keyboard tip guides the user when giving a value to a parameter SD is the Segment Distribution PR is the Presence Rate SL is the Segment Length DT is the Data Type TP is the Transport Protocol Line is the data line on which the channel appears SD1_ASSIGN is the mapping of the bridge data pin 1 to a given data line Note When used as a sink the port protocol PUSHED correspond to both PUSHED and PULLED the Presence bit being the same for both protocol It is important to understand that the manual configuration mode is essentially designed to sniff the content of a data port without disturbing it Therefore the manually configured port will not act as an active port with the PULLED protoco
20. ances Parameter With Internal Framer Tov gt 2 ns Tov lt 7 2 ns DATA With External Framer Tov lt 12 ns CLOCK SLIMbus Audio Bridge User Manual V3 02 31 July 2015 38
21. and if the receiver detects a valid IEC60958 audio digital stream Optical input not selected all LEDs OFF Optical input selected but no valid stream yellow LED ON Optical input selected with a valid stream green LED ON The green LED on the right side of the input connector indicates that the analogue input is selected 3 4 Optical and Analogue Output Connector The Optical TOSLINK and analogue outputs are sharing the same 3 5mm jack connector They cannot be used both at the same time RING RIGHT channel ty sieeve fono SLIMbus Audio Bridge User Manual V3 02 31 July 2015 22 STANDBY OUT PWR son sel ooo VC USB ll SPDIF Oe CLOCK 3 5 SPDIF Input Connector The SPDIF connector is a standard RCA cinch connector The input impedance is 750 The bicolour LED on the right side of the input connector indicates that the SPDIF input is selected and if the receiver detects a valid IEC60958 audio digital stream SPDIF input not selected all LEDs OFF SPDIF input selected but no valid stream yellow LED ON SPDIF input selected with a valid stream green LED ON 3 6 SPDIF Output Connector The SPDIF connector is a standard RCA cinch connector The output impedance is 750 3 7 External Clock Connector The external clock connector is a female SMA RF connector Its characteristics impedance is 50Q The input impedance is switchable between 500 and 1MQ The bicolour LED at the bottom right side of the
22. ed by pressing on the text field A keyboard will appear with a guidance tip Type the desired value and finish the parameter edition by pressing the validate button SLIMbus Audio Bridge User Manual V3 02 31 July 2015 8 Ch A Tone Frequency lt Fs 2 2960 Hz 7 8 9 CANCEL 4 5 6 VALIDATE 1 2 3 o DEL CLEAR When the Tone Generator parameter edition is finished press the Exit button to go back to the Data Paths page 2 1 3 Output Section The output interfaces are essentially stereo two channels The Data Ports are grouped by pair to output their signals to the selected output interface As there are more port pairs than available output interfaces it is necessary to select which port pairs will reach the outputs Stereo SPDIF amp DSI Stereo SPDIF amp DSI DSI 8 Channels Stereo SPDIF amp DSI Stereo SPDIF amp DSI P8 amp P9 Stereo Optical amp Analogue P10 amp P11 Stereo Optical amp Analogue The connected stream is selected by pressing the button corresponding to that stream SLIMbus Audio Bridge User Manual V3 02 31 July 2015 9 2Ch PR N A 2Ch PR N A SDO1 spoz SPDIF SPDIF SDOS __ DSI 8Ch DSI Out 5D04 8Ch DSI Out 2Ch PR N A 2Ch PR N A SD05 SD05 OPT p er OPT SD06 ANA SD06 ANA Attenuation dB Attenuation dB SDO1 on SPDIF amp DSI SDO3 on SPDIF and DSI To activate the 8 channel DSI output press the 8Ch DSI Out button
23. ed distortions lf the ASRC is not activated the DL field value will not have any effect on the bridge behaviour 5 4 Audio Data Format The bridge supports 2 audio data formats DT 0 Not Indicated forces the bridge to use the 2 s complement data format DT 1 LPCM forces the bridge to use the sign amp offset magnitude format defined by the SLIMbus specification It will convert 2 s complement samples to LPCM and vice amp versa The data format is specified by the Data Type field value in the NEXT _DEFINE_CONTENT message SLIMbus Audio Bridge User Manual V3 02 31 July 2015 31 5 5 Using the Value Elements to configure the Bridge Most of the bridge parameters can be modified by using the Value Elements of the Generic device To validate the bits set in the Value Element the most significant bit b7 of the Value Element must be set Otherwise the Value Element content will not have any other effect than being displayed in the Bus Status page The bit assignment is shown in the following tables maae meme INPUT1_SELO Select the signal source of the ports 0 to 7 INPUT SEL1 0 SPDIF 1 Optical 2 DSI 3 Tone Generator INPUT1_SEL3 Select signal source of the ports 3 to 7 0 copy P1 P4 1 tone gen METRE Select the signal source of the ports 8 to 11 INPUT2 SEL1 0 SPDIF 1 Optical 2 Analogue INPUT1_ASRC_ENA Activate the Asynchronous Sample Rate Converter of the input 1 group
24. ed the port O to 3 inputs Ports 4 to 7 can be directly fed by the tone generator or by the ports 0 to 3 input signals On the clock domain 3 the SPDIF Optical and analogue inputs are available SLIMbus Audio Bridge User Manual V3 02 31 July 2015 6 Stereo SPDIF Optical DSI or Tone Generator DSI 8 Channels PO P3 inputs or Tone Generator P8 amp P9 Stereo SPDIF Optical amp Analogue P10 amp P11 An asynchronous sample rate converter ASRC is available on each clock domain 1 2 and 3 in case the signal sampling rate would not match exactly the SLIMbus channel Presence Rate The ASRC is controlled via the HW Setup pages When the ASRC is not in use DIRECT is shown in the ASRC box When it is activated ASRCxx is shown where xx is the sample size used by the ASRC it can be 16 20 or 24 bits To Select an input signal just press the corresponding button SPDIF OPT DS Tone The input feed of the Ports 4 to 7 is controlled by the round router Press on it to toggle the data path en o PR DSI Tone DSI Tone Vly D Tone Setup Tone Setup Audios SLIMbus Framer g Audios SLIMbus Framer Internal 8Ch DSI In 8Ch DSI In P4 7 inputs PO 3 inputs P4 7 inputs Tone Generator To activate the 8 channel DSI input press the button 8Ch DSI In In this mode all the other clock domain 1 inputs are deactivated The clock domain 2 outputs are also disabled
25. f the Generic Device at address 0x803 Name Description O SS O EXT_CLK_LEVELO Select the external clock signaling level EXT_CLK_LEVEL1 Om UO EN ES CLK_OUT_SRCO Select the clock to be output on the external clock connector CLK OUT SRC1 O Framer 1 MCLKI1 2 MCLKO1 3 MCLK2 AUDIO_PLL_REF1 0 SLIMbus 1 SPDIF IN 2 OPRICAL IN 3 DSI MCLK 4 SMA AUDIO_PLL_REF2 7 VE4 VALIDATE Activate the functions of bit 0 to 6 when set to 1 VE4 of the Generic Device at address 0x804 AUDIO_PLL_REFO Select the audio PLL clock reference SLIMbus Audio Bridge User Manual V3 02 31 July 2015 6 Tone Generator Characteristics The internal tone generator offers basic signals for quick and simple tests It has 2 independent channels Not that the generator has not been designed to fulfil all the duties of a fully featured audio analyzer The generator offers signals for all the sampling rates from 8 KHz up to 384 kHz There are 3 signals available 32 bits constant DC value per channel APseudo Random Bit Sequence common to both channels Asine wave with selectable frequencies and amplitude per channel 6 1 Pseudo Random Bit Sequence The PRBS generator is based on a 16 bits linear feedback shift register LFSR The polynomial is equal to X16 X14 X13 X11 1 Fibonacci implementation b15 b14 b13 b12 b11 b10 bg b8 b7 b6 b5 b4 b3 b2 b1 b0 o gt Bit shift direction The 32 bit sample is built with 2 co
26. hall not be used when the aim of the test is to characterise the Device Under Test audio performances 4 2 1 Input Clock Domain 1 MCLKI1 The following figure shows the block diagram of the clock domain 1 inputs EXTERNAL CLOCK DOMAIN MCLKI1 INPUT CLOCK DOMAIN SPDIF IN LRCLKI1 BCLKI1 OPTICAL IN ce ASRC ee SLIMbus Data Port Pair DSI IN nal MCLKIt TONE GEN The SPDIF and Optical inputs have their own clock domain The use of an ASRC appears to be necessary if the audio master clock MCLKI1 is not generated from the SPDIF or Optical clocks The DSI input may also have its own clock domain when the interface is set as a clock slave However when the DSI input is set as clock master the DSI input use the audio master clock MCLKI1 clock domain 1 as reference Note that the bridge tone generator is always using the audio master clock MCLKI1 as a reference When using the DSI 8 Channel input mode the interface is clock master and depends entirely on the MCLKI1 clock domain SLIMbus Audio Bridge User Manual V3 02 31 July 2015 26 SLIMbus DSI 8CH IN DATA1 Data Port Pair SLIMbus Data Port Pair DSI 8CH IN DATA2 SLIMbus DSI 8CH IN DATA3 Date Fost Pair DSI 8CH IN DATA4 DSI 8CH IN LRCLK DSI 8CH IN BCLK SLIMbus Data Port Pair MCLKI1 OUTPUT CLOCK DOMAIN MCLKI1 4 2 2 Input Clock Domain 3 MCLK2 The following figure shows the block diagram of the clock domain 3 inputs It is very similar to the clock doma
27. in 1 inputs with the exception that there is no DSI interface available in this group MCLK2 INPUT CLOCK DOMAIN LRCLK2 SLIMbus Data Port Pair Note that the analogue to digital converter ADC is always using the audio master clock MCLK2 as a reference 4 2 3 Output Clock Domain 2 MCLKO1 The following figure shows the block diagram of the clock domain 2 outputs SLIMbus Audio Bridge User Manual V3 02 31 July 2015 27 LRCLKO1 SLIMbus BCLKO1 SPDIF Data Port Pair S gt ENCODER ROMA SD MCLKO1 MCLKO1 OUTPUT CLOCK DOMAIN The SPDIF output is always belonging to the internal clock domain 2 The DSI output can operate in different configuration The following table lists the configurations that will not generate any audio stream disturbances Clock Mode ASRC Clock domain When using the DSI 8 Channel output mode the interface is clock master and depends entirely on the MCLKO1 clock domain SLIMbus Data Port Pair DS 8CH OUT DATA SLIMbus Data Port Pair DSI 8CH OUT DATA2 SLIMbus Data Port Pair DSI 8CH OUT DATA3 DSI 8CH OUT DATA4 DSI 8CH OUT LRCLK DSI 8CH OUT BCLK SLIMbus LRCLKO1 Data Port Pair MCLKO1 MCLKO1 OUTPUT CLOCK DOMAIN 4 2 4 Output Clock Domain 3 MCLK2 The following figure shows the block diagram of the clock domain 3 outputs SLIMbus Audio Bridge User Manual V3 02 31 July 2015 28 SLIMbus OPTICAL Data Port Pair ENCODER OPTICAL OUT ANALOGUE OUT
28. in three main pages Data Paths Bus Status Hardware Setup 2 1 Data Path This page shows the port status and associated presence rate the signal routing and various information like the Sample Rate converter status the digital receiver status the loop back configuration Bus Status HW Setup PR PO F on f i DIRECT 2Ch PR N A DSI Tone Lu SPDIF P 3 P4 Tone ps SDO3 aac Baba CES From Dani PE DSI _8ChDSiin DSI In P7 SDO4 8Ch DSI Out PR Pg 2Ch PR N A ni Pg OPT DIRECT ANA SD06 ANA P11 Attenuation dB The Data Ports are numbered from O to 11 There are two groups of ports The first one has the first 8 ports 0 to 7 The second one has the last 4 ports 8 to 11 The first group uses the clock domain 1 also referred as MCLKI1 for the Source ports and the clock domain 2 also referred as MCLKO1 for the Sink ports The second group has the same clock domain 3 also referred as MCLK2 for both Source and Sink ports The clock domains are identified by the background colour Clock domain 1 MCLKI1 light green Clock domain 2 MCLKO1 light orange Clock domain 3 MCLK2 light blue 2 1 1 Input Section The input signals are shown on the left side of the display On the clock domain 1 the SPDIF Optical DSI stereo and DSI 8 channels inputs are available as well as the internal tone generator These input signals directly fe
29. ion and the SLIMBus related registers of the bridge Data Paths HW Setup Framing Information Physical Layer Subframe Mode 19 4 32 Level 1 80 Clock Gear 9 6 4 gt 14 4 MHz Bus Hold ON Root Frequency 1 24 576 MHz SD1_ASSIGN 0 Bus Clock Bridge VE Programmed Bus Clock 12 2880 MHz GenDev VEO 0 Measured Bus Clock 0 0000 MHz GenDev VE1 0 Internal Framer Status Inactive smilies GenDev VE3 O GenDev VE4 0 The Framing Information is decoded and displayed The Subframe Mode Clock Gear and Root Frequency are explicitly shown The programmed bus clock and the measured bus clock are shown for comparison They must match The framer status indicates if the bridge is the active framer or not The physical layer information shows the programmed signaling level the bus hold status and the data line mapping of the data pin 1 SD1 This value reflects the content of the Value Element 0x400 of the Interface device The five Geberic device Value Elements are also shown These value elements are used to remote control the bridge see section 6 5 of this document SLIMbus Audio Bridge User Manual V3 02 31 July 2015 15 2 3 Hardware Setup This page has five sub pages each dedicated to a specific function of the bridge SLIMBus configuration Audio setup External clock configuration Reference clock selection Hardware information and diagnostic The sub page navigation relies on the bottom button
30. l Manual Port Configuration Port Number PO P1 P8 P9 Exit Port Config Source Sink Disconnect Validate Track Channel e Manual Setup sp 3140 st 6 TP i ISOC SD1_ASSIGN PR 3 DT 1 Line Primary Secondary 1 Once a manually configured channel is active the port text is yellow not white to show the user that the port has a special behaviour 2 1 6 Port Status When a port is not configured it appears grey in the middle of the central bar When a port is fully configured its position and colour change depending on the function and clock domain to which it belongs SLIMbus Audio Bridge User Manual V3 02 31 July 2015 13 ee Bus Status HW Setup PR Mismatch PO 2ChPR 96 kHz FM on gt DS Tone a P3 spo SPDIF Tone Setup _ sos PS Audio SLIMbus Framer Internal P6 DSI 8Ch DSI In P7 sb04 8Ch DSI Out PR 192 kHz P8 2Ch PR 192 kHz SBF orr ro mi OPT ANA an P11 5006 Attenuation dB The source ports 0 to 7 will appear on the left side coloured in green The sink ports 0 to 7 will appear in the right side coloured in orange The source ports 8 to 11 will appear on the left side coloured in blue The sink ports 8 to 11 will appear on the right side coloured in blue The source and sink ports are both blue because they belong to the same clock domain 3 MCLK2
31. o achieve long connection of high frequency signals without suffering reflections lf the clock source has a 500 output impedance the signaling level at the connector input will be half of the output level of the source Select the signaling voltage accordingly For instance a source generating a 3 3V clock signal will end up being 1 65V at the bridge SMA connector Therefore select 1 8V for optimal operation If the clock source is only capable of sourcing 1 8V it might be wise to shorten the link to set the input impedance to 1M and to set the signaling voltage to 1 8V The bridge constantly measures the frequency of the signal present on the SMA connector and displays it Output Clock When configured as an output the SMA provides a variety of clock signals The output impedance is fixed at 500 The output clock source is selectable It can be a user defined frequency derived from framer PLL ref clock the framer reference clock CG10 the audio MCLKI1 MCLKO1 or MCLK2 The selected frequency can be divided by an integer number to accommodate various use cases The displayed frequency is measured and is provided to monitor the output Not all integer factors are available to divide the clock It all depends on the PLL settings If the desired clock is obtain all is fine If the measured clock is either O or some other unexpected values then the desired frequency is not reachable SLIMbus Audio Bridge User Manual V3 02 31 July 20
32. ould be left OFF Stereo DSI Interface configuration The signaling level of the DSI interface is programmable and can be 1 8V 2 5V or 3 3V Both stereo DSI input and output have programmable format and sample size The format can be Left Justified Philips 12S or Right Justified When selecting Right Justified the sample size must be programmed for proper operation The sample size can be 16 20 or 24 bits The interfaces can be clock master active drive of the BCLK and LRCLKk or slave to the BCLK and LRCLK SLIMbus Audio Bridge User Manual V3 02 31 July 2015 17 2 3 3 External Clock Configuration This panel groups all the controls related to the external clock management The bridge has a single SMA connector to either input or output a clock signal These controls program the behaviour of that connector Data Paths Bus Status External Clock Configuration Direction Input Output Signaling Level 1V8 2V5 3V3 Framerpuu Output Clock Source Audio PLL User Framer MCKI1 MCKO1 MCK2 MHz Output Clock Divider None 2 4 Frequency n a SLIMbus Audio Ext Clock Ref Clock Info The main controls are the clock direction input or output and the clock signaling level 1 8V 2 5V and 3 3V Input Clock When configured as an input the input impedance can be set to 50Q or to high impedance typically gt 1 MQ The SMA connector has a characteristic impedance of 50Q and can be used t
33. pies of the LFSR Sample 31 16 214 LSRF Sample 15 0 214 LSFR The constant value 214 has been added to flatten the noise spectrum density There is a small 1 5 dB rise from Fs 48 till Fs 2 A0 cn 34 Li D gt D 30 50 100 200 300 500 1k 2k 3k 5k 10k 20k Frequency Hz Noise spectrum at a sampling rate of 48 kHz The LFSR cycle length is equal to 216 1 65535 The LFSR is initialised with the value 0x0001 SLIMbus Audio Bridge User Manual V3 02 31 July 2015 34 6 2 Sine Wave The waveforms are built on a look up table The possible tone frequencies are given by the formula Ft Fs x N 3072 At Fs 48 kHz the frequency step is equal to 15 625 Hz Dithering is applied to the samples at the appropriate location depending on the Data Length information provided in the NEXT_DEFINE_CONTENT message that defined the data channel in use The following plots show a 1 kHz sine wave 0 dBFs and Fs 48kHz Even if not absolutely perfect the signal purity is excellent see the THD N figures Ap Level dBFS 20 30 50 100 200 300 500 1k 2k 3k 5k 10k 20k Frequency Hz 16 bits THD N 95 5 dB Level dBFS 20 30 50 100 200 300 500 1k 2k 3k 5k 10k 20k Frequency Hz 24 bits THD N 143 8 dB Level dBFS 0 10 Ap 20 30 40 50 60 70 80 90 100 110 120 130 140 En ne Aah ele N 160 170 180 190 Level dBFS 2
34. purpose jittered clock signal 4 2 Audio Master Clock Generation The audio master clock corresponds to 256 x Fs when Fs lt 128 kHz and 128 x Fs when Fs gt 128 kHz smn MCLKI1 PLL p SLIMbus CG6 ne ne SPDIF MCLK OPTICAL MCLK ra MCLKO1 PLL DSI MCLK PLL SMA MCLK ees MCLK2 rasp SLIMbus Audio Bridge User Manual V3 02 31 July 2015 25 The audio laster clocks can be generated by using five input clocks Note that the three audio clock domains are all derived from a common clock reference through a PLL or direct division The default clock reference is the SLIMbus bus clock as if it was running at Clock Gear 6 This option is therefore only usable as long as the bus Clock Gear is greater or equal to 6 If the bus runs in Clock Gear 5 or less the PLL cannot be used anymore with the SLIMBus as a reference lf the audio sample rates are not related to the SLIMbus clock use of the Pushed or Pulled protocol for instance an external master clock shall be used It can be any of the four other ones e SPDIF input recovered master clock e Optical input recovered master clock e DSI master clock input on pin 15 of the DSI connector External clock on the SMA connector It is also possible to use the sample rate converters but they will add their own contribution to the signal delay frequency response ripple and time domain ringing The sample rate converters are provided for convenience but they s
35. that the bus will be completely reset also 2 3 2 Audio Setup This panel groups all the audio interface parameters that can be programmed Data Paths Bus Status Sample Rate Converter Stereo DSI Input Setup INPUT 1 On OFF Format L J 12S R J INPUT 2 On OF Clock Master Slave DSI OUT On Stereo DSI Output Setup Ref Clk DSI MCLKO1 Format L J 12S R J DSI Level 1V8 2V5 3V3 Clock Master Slave SLIMbus Audio Ext Clock Ref Clock Info Asynchronous Sample Rate Converters There are three sample rate converters in the bridge Two are located at the inputs and one at the DSI output They can be turned ON or OFF The sample rate converter ASRC shall be used turned ON when the input sampling rate does not match exactly the SLIMBus channel presence rate If the ASRC is OFF samples will be missed or repeated inducing THD In the other hand the use of an ASRC is not benign It introduces a delay pre and post ringing in the time domain and measurable ripple in the frequency domain When a bit perfect transmission is required the best practice is to clock the audio section of the bridge and the audio source with the same master clock The DSI output ASRC can get two reference clocks the internal MCLKO1 clock domain 2 or the DSI MCLK input This is to be used if the receiver connected to the bridge output cannot cope with the sample rate provided by the bridge By default this ASRC sh
36. w that frequency lt 1 5 MHz the Audio PLL will not lock properly anymore and the results will not be guaranteed As for the framer PLL if the selected clock appears to have the same frequency as the targeted clock the PLL is bypassed This property is useful to feed a master clock below 1 5 MHz into the bridge SLIMbus Audio Bridge User Manual V3 02 31 July 2015 19 2 3 5 Product Information and Diagnostic Values The panel shows the product information hardware revision firmware revision IP revision and the serial number Data Paths Bus Status Product Information Diagnostic Values HW Rev 1 00 VDD 3 297 V FW Rev 3 00 PHY 1 805 V 3 mA IP Rev 3 00 PLL1 24 5760 MHz Serial SBB1214A000 PLL2 12 2880 MHz Temp 37C amp 41C www lnk tools com Calibrate Touch Screen LCD Brightness Ea SLIMbus Audio Ext Clock Ref Clock Info The diagnostic values show the measured main 3 3V supply voltage the measured SLIMbus PHY voltage and consumed current the Framer PLL PLL2 monitoring output the audio PLL PLL1 monitoring output and the temperature measured by two internal sensor On this panel it is also possible to dim the LCD backlight If the unit has to be tuned ON permanently we strongly recommend to dim the backlight to the minimum The typical life time of the backlight is 20000 hours which corresponds to 2 3 years of continuous operation By dimming the backlight to the minimum the display life
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