Microcomputer Components SAB 80C515A/83C515A-5
Contents
1. P1 0 INT3 CCO T2CON 6 Compare 1 v P1 1 INT4 CC1 Comp P1 2 INT5 CC2 Comp v P1 3 INT6 CC3 MCB00081 Figure 5 Interrupt Request Sources Semiconductor Group 31 SIEMENS SAB 80C515A 83C515A 5 Level 3 Level 2 Level 1 Level 0 m z m m 2 Interrupt Request Vector Priority Control Locations m No m 2 m z A m m n SE Ip m T e 27 e 27 ca t t 2 500082 Figure 6 Interrupt Priority Level Structure Semiconductor Group 32 SIEMENS SAB 80 515 83 515 5 Ports The SAB 80C515A has six 8 bit I O ports and one input port Port 0 is an open drain bidirectional I O port while ports 1 to 5 are quasi bidirectional I O ports with internal pull up resistors That means when configured as inputs ports 1 to 5 will be pulled high and will source current when externally pulled low Port O will float when configured as input Port 0 and port 2 can be used to expand the program and data memory externally During an access to external memory port 0 emits the low order address byte and reads writes the data byte while port 2 emits the high order address byte In this function port 0 is not an open drain port but uses a strong internal pull up FET Ports 1 3 and 4 are provide2. WR N C P1 7 T2 P1 6 CLKOUT N C pins must not be connected Pin Configuration P MQFP 80 Semiconductor Group 1 4 INT2 1 3 1 6 P1 2 INT5 CC2 P1 1 INT4 CC1 VSS VSS XTAL2 XTAL1 VCC P2 0 A8 P1 5 2 VCC P1 0 INT3 P2 1 A9 P2 2 A10 P5 7 7 AD7 6 AD6 5 ADS P0 4 AD4 P0 3 ADS P0 2 AD2 PO 1 AD1 P0 0 ADO N C N C EA ALE PSEN N C P2 7 A15 P2 6 14 P2 5 A13 P2 4 A12 P2 3 A11 SIEMENS SAB 80 515 83 515 5 Pin Definitions and Functions Symbol Pin Pin Input 1 Function P LCC 68 P MQFP 80 Output P4 0 P4 7 1 3 5 9 72 74 4 76 80 is 8 bit bidirectional I O port with internal pull up resistors Port 4 pins that have 1 s writ ten to them are pulled high by the internal pull up resistors and in that state can be used as inputs As inputs port 4 pins being externally pulled low will source current Z in the DC characteristics because of the internal pull up resistors P4 also contains the external A D converter control pin The output latch corresponding to a secondary function must be programmed to a one 1 for that function to operate The sec ondary function assigned to port 6 ADST P4 0 external A D converter start pin PE SWD 4 75 Power saving mode enable Start Watch dog Timer A low level on this pin allows the software
3. 20 ns Fall time ICHCL 20 ns Oscillator frequency l teic 3 5 18 MHz 00793 External Clock Cycle Semiconductor Group 51 SIEMENS SAB 80C515A 83C515A 5 AC Characteristics cont d Parameter Symbol Limit values Unit 18 MHz clock Variable clock 1 t 3 5 MHz 18 MHz min max min max System Clock Timing ALE to CLKOUT tLLSH 349 40 l ns CLKOUT high time tSHSL 71 2 40 l 5 CLKOUT low time 516 101 40 ns low to ALE tSLLH 16 96 40 40 ns Ig CLKOUT PSEN Programm Memory Access Data Memory Access RD WR 00794 System Clock Timing Semiconductor Group 52 SIEMENS SAB 80C515A 83C515A 5 ROM Verification Characteristics 25 5 5 10 15 Veg OV Parameter Symbol Limit values Unit min max ROM Verification Mode 1 Standard Verify Mode for not Read Protected ROM Address to valid data fAVQV 48 tci cL ns ENABLE to valid data fELQV 48 tci cL ns Data float after ENABLE teyoz 0 48 tci cL ns Oscillator frequency 1 4 6 2 Data Out MCD01498 Address 1 0 1 7 0 2 0 2 6 8 14 Data 0 0 0 7 00 07 ROM Verification Mode 1 Semiconductor Group 53 SIEME
4. 515 83 515 5 The Serial Interface can operate in 4 modes Mode 0 Mode 1 Mode 2 Mode 3 Shift register mode Serial data enters and exits through R x D T x D outputs the shift clock 8 data bits are transmitted received LSB first The baud rate is fixed at 1 12 of the oscillator fre quency 8 bit UART variable baud rate 10 bit are transmitted through T x D or received through R x D a start bit 0 8 data bits LSB first and a stop bit 1 On reception the stop bit goes into RB80 in special function register SCON The baud rate is variable 9 bit UART fixed baud rate 11 bit are transmitted through T x D or received through R x D a start bit 0 8 data bits LSB first a programmable 9th and a stop bit 1 On transmission the 9th data bit TB80 in SCON can be assigned to the value of 0 or 1 For example the par ity bit P in the PSW could be moved into TB80 or a second stop bit by setting TB80 to 1 On reception the 9th data bit goes into RB80 in special function register SCON while the stop bit is ignored The baud rate is programmable to either 1 32 or 1 64 of the oscillator frequency 9 bit UART variable baud rate 11 bit are transmitted through T x D or received through R x D a start bit 0 8 data bits LSB first a programmable 9th and a stop bit 1 In fact mode 3 is the same as mode 2 in all respects except the baud rate The baud rate in mode 3 is vari able Varia
5. 10 X1 DPTR XRAM a PO P2 Bus a PO P2 Bus a PO P2 Bus a PO P2 Bus a PO P2 Bus a PO P2 Bus b RD WR active b RD WR active b RD WR active b RD WR active b RD WR active b RD WR active 9 C ext memory c ext memory is C ext memory is C ext memory is C ext memory is C ext memory is used used used used used used DPTR gt XRAM a PO P2 BUS PO P2 BUS a 2 a 2 1 0 a PO P2 BUS a 2 address WR Data only WR Data only b RD WR active b RD WR inactive WR Data only b RD WR active range b RD WR inactive b RD WR active ext memoryis c XRAM is used b RD WR active c ext memory is c XRAM is used c XRAM is used used c XRAM is used used XPAGE lt XRAM a PO Bus a PO Bus a PO Bus a P0 Bus a PO Bus a PO Bus addr P2 1 0 P2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 page ange b RD WR active b RD WRactive b RD WRactive b RD WRactive b RD WRactive b RD WR active C ext memory is C ext memory is C ext memory is C ext memory is C ext memory is C ext memory is used used used used used used XPAGE 2 XRAM a PO P2 BUS PO P2 BUS a a 2 1 0 a Po BUS a WR Data only WR Data only 2 910 b RD WR inactive WR Data only 2 910 ee eec v ids 12222 20 b RD WR active c XRAMisused 2 V 0 b R
6. 1V 00606 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V level occurs gt 20 mA AC Testing Float Waveforms XTAL1 XTAL1 MQFP 80 Pin 37 MQFP 80 Pin 37 P LCC 68 Pin 40 P LCC 68 Pin 40 XTAL2 XTAL2 MQFP 80 Pin 36 External Oscillator MQFP 80 Pin 36 P LCC 68 Pin 39 Signal P LCC 68 Pin 39 C 30 10 MCS02495 incl stray capacitance Crystal Oscillator Mode Driving from External Source Recommended Oscillator Circuits Semiconductor Group 56
7. HWPD 0 1 Input low voltage EA Vins 0 5 0 2Vcc V 0 3 Input low voltage Vito 0 5 0 2 Vcc HWPD RESET 0 1 Input high voltage exept 0 2 Vcc 0 5 V RESET XTAL2 and 0 9 Input high voltage to XTAL2 0 7 0 5 V Input high voltage to RESET Vino 0 6 0 5 V HWPD Semiconductor Group 43 SIEMENS SAB 80C515A 83C515A 5 DC Characteristics cont d Parameter Symbol Limit Values Unit Test condition min max Output low voltage VoL 0 45 V Io 1 6 mA ports 1 2 3 4 5 Output low voltage Vout E 0 45 V IoL 3 2 mA ports 0 ALE RESET Output high voltage 2 4 E V 80 uA ports1 2 3 4 5 0 9 Vec 7 V 10 uA Output high voltage 2 4 V Tou 800 uA port 0 in external bus mode 0 9 Vec V 80 uA ALE PSEN Logic 0 input current 10 70 ViN 2V ports 1 2 3 4 5 Logical 1 to 0 transition IH 65 650 Vin 2V current ports 1 2 3 4 5 Input leakage current 100 nA 0 45 lt VIN lt port 0 EA P6 HWPD 150 nA 0 45 lt ViN lt Vee TA gt 100 C Input low current to RESET 12 10 100 Vin 0 45 V for reset Input low current XTAL2 13 15 uA Vin 0 45 V Input low current PE SWD 20 uA Vin 0 45 V Pin capacita
8. MOVX accesses are performed by the external bus reset state XMAP1 Control bit for RD WRsignals during accesses to XRAM this bit has no effect if XRAM is disabled XMAPO 1 or if addresses exceeding the XRAM address range are used for MOVX accesses 0 The signals RD and WR are not activated during accesses to XRAM XMAP 1 1 The signals RD and WR are activated during accesses to XRAM Reset value of SYSCON is XXXX XX01B The control bit XMAPO is a global enable disable bit for the additional On Chip RAM XRAM If this bitis set the XRAM is disabled all MOVX accesses use external memory via the external bus In this case the SAB 80C515A does not use the additional On Chip RAM and is compatible with the types without XRAM Semiconductor Group 17 SIEMENS SAB 80C515A 83C515A 5 is hardware protected by an unsymmetric latch An unintentional disabling of XRAM could be dangerous since indeterminate values would be read from external bus To avoid this the XMAP bit is forced to 1 only by reset Additionally during reset an internal capacitor is loaded So after reset state XRAM is disabled Because of the load time of the capacitor XMAPO bit once written to 0 that is discharging capacitor cannot be set 1 again by software On the other hand any distortion software hang up noise is not able to load this capacitor too That is the stable status is XRAM enabled The only way to disa
9. are pulled high by the internal pullup resistors and in that state can be used as inputs As inputs port 1 pins being externally pulled low will source current 1 in the DC characteristics because of the internal pullup resistors The port is used for the low order address byte during program verification Port 1 also contains the interrupt timer clock capture and compare pins that are used by various options The output latch corresponding to a secondary function must be programmed to a one 1 for that function to operate except when used for the compare functions The secondary functions are assigned to the port 1 pins as follows INT3 CCO P1 0 interrupt 3 input compare 0 output capture 0 input INT4 CC1 P1 1 interrupt 4 input compare 1 output capture 1 input INT5 CC2 P1 2 interrupt 5 input compare 2 output capture 2 input INT6 CC3 P1 3 interrupt 6 input compare 3 output capture 3 input INT2 P1 4 T2EX P1 5 interrupt 2 input timer 2 external reloadtrigger input CLKOUT P1 6 T2 P1 7 XTAL2 Input to the inverting oscillator amplifier and input to the internal clock generator circuits system clock output counter 2 input Semiconductor Group SIEMENS SAB 80 515 83 515 5 Pin Definitions and Functions cont d Pin P LCC 68 Pin P MQFP 80 Symbol Input 1 Output O Function XTAL1 40 37 XTA
10. internal RAM of the base type SAB 80C515 This RAM is called XRAM extended in this document External Data Memory Up to 64 Kbyte external data memory can be addressed by instructions that use 8 bit or 16 bit indirect addressing For 8 bit addressing MOVX instructions in combination with registers RO and R1 can be used A 16 bit external memory addressing is supported by a 16 bit datapointer Registers and SYSCON are controlling whether data fetches at addresses F800 to FBFFy are done from internal XRAM or from external data memory Internal Data Memory The internal data memory is divided into four physically distinct blocks the lower 128 bytes of RAM including four register banks containing eight registers each the upper 128 byte of RAM the 128 byte special function register area a1Kx8 area which is accessed like external RAM MOVX instructions implemented on chip at the address range from F800 to FBFF Special Function Register SYSCON controls whether data is read from or written to XRAM or external RAM A map of the internal data memory is shown in figure 2 The overlapping address spaces of the standard internal data memory 256 byte are accessed by different addressing modes see User s Manual SAB 80C515 The stack can be located anywhere in the internal data memory Architecture of the XRAM The contents of the XRAM is not affected by a reset or HW Power Down After power up th
11. is independent of the state of pin PE SWD HWPD is sampled once per machine cycle If it is found active the device starts a complete internal reset sequence The watchdog timer is stopped and its status flag WDTS is cleared exactly the same effects as a hardware reset In this phase the power consumption is not yet reduced After completion of the internal reset both oscillators of the chip are disabled At the same time the port pins and several control lines enter a floating state as shown in table 5 In this state the power consumption is reduced to the power down current IPD Also the supply voltage can be reduced Table 5 also lists the voltages which may be applied at the pins during Hardware Power Down Mode without affecting the low power consumption Termination of HWPD Mode This power down state is maintained while pin HWPD is held active If HWPD goes to high level inactive state an automatic start up procedure is performed First the pins leave their floating condition and enter their default reset state as they had immediately before going to float state Both oscillators are enabled The oscillator watchdog s RC oscillator starts up very fast typ less than 2 ms Because the oscillator watchdog is active it detects a failure condition if the on chip oscillator hasn t yet started Hence the watchdog keeps the part in reset and supplies the internal clock from the RC oscillator Finally when the on c
12. 1 Bit addressable special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X means that the value is indeterminate and the location is reserved Semiconductor Group 23 SIEMENS SAB 80C515A 83C515A 5 Table 3 Special Function Registers Functional Blocks Block Symbol Name Address Contents after Reset Ports PO Port 0 801 OFF P1 Port 1 901 1 OFF P2 Port 2 0 0 1 OFFy P3 Port 3 OBO OFF P4 Port 4 0 8 OFF P5 Port 5 0F8H OFF P6 Port 6 Analog Digital Input ODBy Pow Sav M PCON Power Control Register 874 004 ode Serial ADCONO 2 A D Converter Control Reg 008 004 Channels PCON 2 Power Control Register 874 00H SBUF Serial Channel Buffer Reg 99H OXX49 SCON Serial Channel Control Reg 98H 1 00H SRELL Serial Channel Reload Reg AAW D94 low byte SRELH Serial Channel Reload Reg XX115g high byte Timer 0 TCON Timer Control Register 88H 1 00H Timer 1 THO Timer 0 High Byte 8CH 00H TH1 Timer 1 High Byte 8DH 00H TLO Timer 0 Low Byte 8 00 TL1 Timer 1 Low Byte 8BH 00H TMOD Timer Mode Register 89H 00H Watchdog IENO 2 Interrupt Enable Register 0 0A8H 00H IEN1 2 Interrupt Enable Register 1 0B8H 1 00H IPO 2 Interrupt Priority Register O 0A9H 00H IP1 2 Interrupt Priority Register 1 0B9H XX00 0000B WDTREL Watchdog Timer Reload Reg 86H 00H 1 Bit addressable
13. 15A 5 has 32 Kbyte of on chip ROM while the SAB 80C515A has no internal ROM The program memory can externally be expanded up to 64 Kbyte Pin EA determines whether program fetches below address 8000 are done from internal or external memory As a new feature the SAB 83C5154A 5 offers the possibility of protecting the internal ROM against unauthorized access This protection is implemented in the ROM Mask Therefore the decision ROM Protection yes or no has to be made when delivering the ROM Code Once enabled there is no way of disabling the ROM Protection Effect access to internal ROM done by an externally fetched MOVC instruction is disabled Nevertheless an access from internal ROM to external ROM is possible To verify the read protected ROM Code a special ROM Verify Mode is implemented This mode also can be used to verify unprotected internal ROM ROM Protection ROM Verification Mode Restrictions see AC Characteristics no ROM Verification Mode 1 standard 8051 Verification Mode ROM Verification Mode 2 yes ROM Verification Mode 2 standard 8051 Verification Mode is disabled externally applied MOVC accessing internal ROM is disabled Semiconductor Group 13 SIEMENS SAB 80C515A 83C515A 5 Data Memory Data Space The data memory space consists of an internal and an external memory space The SAB 80C515A contains another 1 Kbyte on On Chip RAM additional to the 256 bytes
14. 4 reserved 2 C3y CCH1 00 E3 reserved XXH 3 C4H CCL2 00H E44 reserved XX4 C5 CCH2 E5 reserved XX4 2 00 reserved XX4 7 004 7 reserved XX4 T2CON 1 004 E8H P4 1 OFFy reserved E94 reserved XXH 3 CA CRCL 004 EA reserved XX4 CBy CRCH 004 reserved XXH 3 CCH TL2 00H ECH reserved CDy TH2 004 EDH reserved XXH 3 CEH reserved XXH EEy reserved XX4 CFy reserved EFy reserved XXH 3 1 Bit addressable special function registers 2 X means that the value is indeterminate and the location is reserved Semiconductor Group 21 SIEMENS SAB 80C515A 83C515A 5 Table 2 Special Function Register cont d Address Register Contents Address Register Contents after Reset after Reset B 00 F84 51 00F F1 reserved F9 reserved XXH F24 reserved reserved F34 reserved FBy F4 reserved XXH 3 FCH F5 reserved Xx FDy F6 reserved XX FE F7 reserved XXy 1 Bit addressable special function registers 2 X means that the value is indeterminate and the location is reserved Semiconductor Group 22 SIEMENS SAB 80 515 83 515 5 Table 3 Special Function Registers Functional Blocks Block Symbol Address _ after Reset CPU ACC Accumulator OEO 00 B Register 1 00 DPH Data Pointer
15. 40 to 85 C SAB 80C515A M18 T3 067120 0851 80 for external memory 18 MHz ext temperature 40 to 85 C SAB 83C515A 5M18 T3 Q67120 DXXXX P MQFP 80 with mask programmable ROM 18 MHz ext temperature 40 to 85 C Notes Versions for extended temperature range 40 to 110 C on request The ordering number of ROM types DXXXX extension is defined after program release verification of the customer Semiconductor Group 2 SIEMENS SAB 80C515A 83C515A 5 Logic Symbol Semiconductor Group SAB 80C515A 83C515A 5 MCLO1562 SIEMENS SAB 80 515 83 515 5 The pin functions of the SAB 80C515A are identical with those of the SAB 80C515 with following exception Pin SAB 80C515A SAB 800515 68 HWPD Vee 1 PO 4 ADST P4 0 4 PE SWD PE 0 ADST WPD SAB 80C515A 83C515A 5 RxD P3 0 TxD P3 1 INTO P3 2 INT1 P3 3 T0 P3 4 T1 P3 5 01561 Pin Configuration P LCC 68 Semiconductor Group 4 SIEMENS SAB 80 515 83 515 5 RESET N C VAREF VAGND P6 7 7 5 P6 6 AIN6 P6 5 AIN5 P6 4 AIN4 P6 3 P6 2 AIN2 P6 1 AIN1 P6 0 AINO N C N C P3 0 RXDO P3 1 TXDO 2 INTO P3 3 INTT P3 4 TO P3 5 T1 A 6 SAB 80 515 80C515A 5 CD 55 50 45 A On P3 7 RD P3 6
16. 5A 5 Functional Description The SAB 80C515A is based on 8051 architecture It is a fully compatible member of the Siemens SAB 8051 80C51 microcontroller family being an significantly enhanced SAB 806515 The SAB 80C515A is therefore code compatible with the SAB 80C515 Having an 8 bit CPU with extensive facilities for bit handling and binary BCD arithmetics the SAB 80C515A is optimized for control applications With a 18 MHz crystal 58 of the instructions are executed in 666 67 ns While maintaining all architectural and operational characteristics of the SAB 80C515 the SAB 80C515A incorporates more on chip RAM A new 10 bit A D Converter is implemented as well as an oscillator watchdog unit Also the maximum operating frequency of 18 MHz is higher than at the SAB 80C515 With exception of the ROM sizes both parts are identical Therefore the therm SAB 80C515A refers to both versions within this specification unless otherwise noted Memory Organisation According to the SAB 8051 architecture the SAB 80C515A has separate address spaces for program and data memory Figure 2 illustrates the mapping of address spaces 7 FFFFH 27 indirectly addressable not used ty ty 0 indirect d F800y 2 F7FFH int RAM 21 99 Code rom external Data ENTE ARN internal Data emo co 001564 Figure 2 Memory Map Semiconductor Group 12 SIEMENS SAB 80 515 83 515 5 Program Memory Code Space The SAB 83C5
17. B 80C515A 83C515A 5 internal Bus P6 DBy a ae me ADCON1 DCH ADCONO 08 y A ADEX BSY ADM MX 2 MX AAA 5 4 3 2 1 A ADDATH ADDATL Continous Mode A D Converter P4 0 ADST Write to ADDATL 22 Shaded areas are not used in ADC functions infernal Bus Bit MX3 in SFR ADCON1 must not be set 01565 Figure 3 Block Diagram A D Converter Semiconductor Group 26 SIEMENS SAB 80 515 83 515 5 Timers Counters The SAB 80C515A contains three 16 bit timers counters wich are useful in many applications for timing and counting the input clock for wach timer counter is 1 12 of the oscillator frequency in the timer operation or can be taken from an external clock source for the counter operation maximum count rate is 1 24 of the oscillator frequency Timer Counter 0 and 1 These timers counters can operate in four modes Mode 0 8 bit timer counter with 32 1 prescaler Mode 1 16 bit timer counter Mode 2 8 timer counter with 8 bit auto reload Mode 3 Timer counter 0 is configured as 8 bit timer counter and one 8 bit timer Timer counter 1 in this mode holds its count External inputs INTO and INT1 can be programmed to function as a gate for timer counters 0 and 1 to facilitate pulse width measurements Timer Counter 2 Timer counter 2 of the SAB 80C515A is a 16 bit timer counter with s
18. D WR active b RD WR inactive c XRAM is used b RD WR active c XRAM is used c ext memory is used b RD WR active c XRAM is used c ext memory is used modes compatible to 8051 family SNAWGIS S VSLSOE8 VSILSD08 JVS SIEMENS SAB 80C515A 83C515A 5 Special Function Registers All registers except the program counter and the four general purpose register banks reside in the special function register area The special function registers include arithmetic registers pointers and registers that provide an interface between the CPU and the on chip peripherals There are also 128 directly addressable bits within the SFR area All special function registers are listed in table 2 and table 3 In table 2 they are organized in numeric order of their addresses In table 3 they are organized in groups which refer to the functional blocks of the SAB 80C515A Table 2 Special Function Register Address Register Contents Address Register Contents after Reset after Reset 804 PO 1 OFF 98 SOCON 00 81 SP 07 99 SBUF 82H DPL 00H 9A reserved XX4 834 DPH 00H 9By reserved 844 WDTL 9 reserved XxX4 85 WDTH 9DH reserved 2 86 WDTREL 004 9EH reserved XX4 2 874 PCON 00H 9FH reserved XXH 884 TCON 00 AOp P2 OFF 89 TMOD 00 Aly reserved XX4 8 TLO 00H A2y reserved XXy 8By TET 004 reserved XX4 8 THO 00H A4y reserved 8DH TH1 00
19. H A5H reserved XX4 8EH reserved A64 reserved XX4 8Fy reserved A7 reserved XX4 90 1 1 OFF 1 00H 91 XPAGE Xx 2 A9 IPO 00 92 reserved XXH SRELL 009 93 reserved XX AB reserved 944 reserved XXH 23 ACH reserved XX4 95 reserved XXH 23 ADH reserved XX4 2 96 reserved XXH AEH reserved XX4 97 reserved XXH 23 AFH reserved 1 Bit addressable special function registers 2 X means that the value is indeterminate and the location is reserved Semiconductor Group 20 SIEMENS SAB 80 515 83 515 5 Table 2 Special Function Register cont d Address Register Contents Address Register Contents after Reset after Reset P3 1 PSW 1 00 SYSCON XX01g D1H reserved XX4 B24 reserved D24 reserved XXH 3 B3H reserved D3y reserved XX4 reserved XXH 2 D4H reserved B5 reserved Xx D5H reserved XX4 reserved XXH 3 D6H reserved XXH 3 B7H reserved D7H reserved XX4 B84 1 1 00 D84 ADCONO 00 0000 2 9 ADDATH 00 SRELH XX11p2 ADDATL 004 BBy reserved DBy P6 XX BCy reserved XX4 DVH ADCVON1 0000p BDy reserved XX4 DDy reserved XX BE reserved DE reserved XX BFy reserved DFy reserved IRCON 00 EO ACC 00 CCEN 004 Ely reserved XX4 C24 CCL1 00 E2
20. High Byte 83H 00 DPL Data Pointer Low Byte 824 00 PSW Program Status Word Register 1 004 SP Stack Pointer 81H 074 A D ADCONO A D Converter Control Register 0 0D8 00 Converter ADCON Converter Control Register 1 ODCy 000083 ADDATH A D Converter Data Reg High Byte 0D9 00 ADDATL Converter Data Reg Low Byte ODA 00 Interrupt ENO Interrupt Enable Register 0 0A8H 1 00 System IEN1 Interrupt Enable Register 1 0B8H 1 004 IPO Interrupt Priority Register O 0A9H 00H 1 Interrupt Priority Register 1 0B9H XX00 0000B IRCONO Interrupt Request Control Register OCO 00 TCON 2 Control Register 88H 1 00H T2CON 2 Timer 2 Control Register 0 8 00 Comp Capture Enable Reg 0 1 00 Capture Comp Capture Reg 1 High Byte 0C3 00 Unit CCH2 Comp Capture Reg 2 High Byte 0C5 00 CCU CCH3 Comp Capture Reg 3 High Byte 0 7 00 CCL1 Reg 1 Low Byte 0C2 00 CCL2 Comp Capture Reg 2 Low Byte 0C4 00 Reg 3 Low Byte 0 6 00 CRCH Com Rel Capt Reg High Byte OCBy 00 CRCL Com Rel Capt Reg Low Byte OCA 00 2 2 00H TL2 Timer 2 Low Byte 0CCH 00H T2CON Timer 2 Control Register 0C8H 00H XRAM XPAGE Address Register for Exten 914 00 ded Chip RAM SYSCON XRAM Control Register 0B1H XX01p
21. L1 Output of the inverting oscillator amplifier To drive the device from an external clock source XTAL2 should be driven while XTAL1 is left unconnected There are no require ments on the duty cycle of the external clock signal since the input to the internal clok king circuitry is divided down by a divide by two flip flop Minimum and maximum high and low times and rise fall times specified in the AC characteristics must be taken into account P2 0 P2 7 41 48 38 45 I O Port 2 is an 8 bit bidirectional I O port with internal pullup resistors Port 2 pins that have 1 s written to them are pulled high by the internal pullup resistors and in that state can be used as inputs As inputs port 2 pins being externally pulled low will source current CIL in the DC characteristics because of the internal pullup resistors Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that use 16 bit addresses MOVX DPTR In this application it uses strong internal pullup resistors when issuing 1 s During accesses to external data memory that use 8 bit addresses MOVX Ri port 2 issues the contents of the P2 special function register The Program Store Enable output is a control signal that enables the external program memory to the bus during external fetch operations It is activated every six oscillator periods except during external data memory acces
22. NS SAB 80C515A 83C515A 5 ROM Verification Mode 2 New Verify Mode for Protected and not Protected ROM 55 S4 55 S S4 3535 St 5 S4 3 3 S2 4 S P2 P2 PP P2 p P2 P2 8 2 1 sample RESET ege EM int CORN E E LL dew rk ROM Code ROM Code ROM Code adr 0000H adr 0001H adr 00024 001499 Y Y RESET State Increment Address counter for external ROM Inputs Vy ALE forced to low level by a weak pull down resistor 4000 during RESET activ Port 0 00 07 Outputs Port 3 5 shows all 1024 cycles low level for one cycle when compared ROM Code was not alright ROM Verification Mode 2 Semiconductor Group 54 SIEMENS SAB 80 515 83 515 5 Compare Result Logic SAB 83C515A 5 ALE Reset Adr Counter Reset Compare ROM Compare Code 01570 Application Example for Verifying the Internal ROM with ROM Verify Mode 2 Semiconductor Group 55 SIEMENS SAB 80C515A 83C515A 5 0 2 Voc 0 9V Test Points 0 2 Vog 0 1V 0 45V MCA00697 AC Inputs during testing are driven at 0 5 V for a logic 1 and 0 45 V for a logic 0 Timing measure ments are made at Vinmin for a logic 1 and Vi max for a logic 0 AC Testing Input Output Waveforms Timing Reference Points Vo 0
23. SIEMENS M icrocomputer Components 8 Bit CM OS Single Chip M icrocontroller SAB 80C515A 83 515 5 Data Sheet 08 95 SIEMENS High Performance SAB 80C515A 83C515A 5 8 Bit CMOS Single Chip Microcontroller Preliminary SAB 83C515A 5 Microcontroller with factory mask programmable ROM SAB 80C515A Microcontroller for external ROM SAB 80 515 83C515A 5 up to 18 MHz operation frequency 32 Kx 8 ROM SAB 83C515A 5 only ROM Protection available 256 x 8 on chip RAM Additional 1 K x 8 on chip RAM XRAM Superset of SAB 80C51 architecture 1 us instruction cycle time at 12 MHz 666 ns instruction cycle time at 18 MHz 256 directly addressable bits Boolean processor 64 Kbyte external data and program memory addressing Three 16 bit timer counters Versatile fail safe provisions Twelve interrupt vectors four priority levels selectable Genuine 10 bit A D converter with 8 multiplexed inputs Full duplex serial interface with programmable Baudrate Generator Functionally compatible with SAB 80C515 Extended power saving mode Fast Power On Reset Seven ports 48 I O lines 8 input lines Two temperature ranges available 0 to 70 C T1 40 to 85 C T3 Plastic packages P LCC 68 and P MQFP 80 The SAB 80C515A 83C515A 5 is a high end member of the Siemens SAB 8051 microcontroller family It is designed in Siemens ACMOS technology and based on the SAB 8051 architecture ACMOS is a technology which co
24. X 0 0 5 ns Data float after RD tRHDZ 51 2 1 1 060 5 ALE to valid data in tLLDV 294 150 ns Address to valid tAVDV 335 9 165 ins data ALE to WR or RD fU WL 117 217 90 50 ns WR or RD high to 16 96 40 40 ns ALE high Address valid to WR AVWL 92 4 130 ns Data valid to WR t QVWX 11 45 ns transition Data setup before WR tovw H 239 150 ns Data hold after WR tWHOX 16 40 ns Address float after RD tp az 0 0 ns Semiconductor Group 48 SIEMENS SAB 80C515A 83C515A 5 01497 mn j AVWL tayoy 2 0 2 7 or 8 15 from DPH A8 A15 from PCH 00791 Data Memory Read Cycle Semiconductor Group 49 SIEMENS SAB 80C515A 83C515A 5 2 0 2 7 or 8 15 from DPH 8 15 from PCH 00792 Data Memory Write Cycle Semiconductor Group 50 SIEMENS SAB 80C515A 83C515A 5 AC Characteristics cont d Parameter Symbol Limit values Unit Variable clock Frequ 3 5 MHz to 18 MHz min max External Clock Drive Oscillator period 55 6 285 ns High time ICHCX 20 tcLCL CLCX ns Low time 20 ns Rise time ICLCH
25. are Power Down Mode The control pin PE SWD has no control function in this mode It enables and disables only the use of software controlled power saving modes Software Controlled Power Saving Modes All of these modes are entered by software Special function register PCON power control register address is 874 is used to select one of these modes Slow Down Mode During slow down operation all signal frequencies that are derived from the oscillator clock are divided by eight also the clockout signal and and the watchdog timer count The slow down mode is enabled by setting bit SD The controller actually enters the slow down mode after a short synchronisation period max 2 machine cycles The slow down mode is disabled by clearing bit SD Idle Mode During idle mode all peripherals of the SAB 80C515A except for the watchdog timer are still supplied by the oscillator clock Thus the user has to take care which peripheral should continue to run and which has to be stopped during Idle The procedure to enter the Idle mode is similar to the one entering the power down mode The two bits IDLE and IDLS must be set by two consecutive instructions to minimize the chance of unintentional activating of the idle mode There are two ways to terminate the idle mode The idle mode can be terminated by activating any enabled interrupt This interrupt will be serviced and the instruction to be executed following the RETI instruction wil
26. ble Baud Rates for Serial Interface Variable baud rates for modes 1 and 3 of serial interface can be derived from either timer 1 or a new dedicated Baudrate Generator The baud rate is generated by a free running 10 bit timer with programmable reload register 2 SMOD fosc 64 20 SREL Mode 1 3 baud rate The default value after reset in the reload registers SRELL and SRELH provides a baud rate of 4 8 kBaud SMOD 0 or 9 6 kBaud SMOD 1 at 12 MHz oscillator frequency This guaran tees full compatibility to the SAB 80C515 Semiconductor Group 39 SIEMENS SAB 80C515A 83C515A 5 Fail Safe Units The SAB 80C515A offers enhanced fail safe mechanisms which allow an automatic recovery from software upset or hardware failure a programmable watchdog timer WDT with variable time out period from 512 us up to appr 1 1 s 412 MHz Upward compatible to SAB 80C515 watchdog timer anoscillator watchdog OWD which monitors the on chip oscillator and forces the microcontroller into reset state in case the on chip oscillator fails it also controls the restart from the Hardware Power Down Mode and provides the clock for a fast internal reset after power on Programmable Watchdog Timer The WDT can be activated by hardware or software Hardware initialization is done when pin PE SWD Pin 4 is held high during RESET The SAB 80C515A then starts program execution with the WDT running Since pin PE SWD is only sampl
27. ble XRAM after it was enabled is a reset The clear instruction for XMAPO should be integrated in the program initialization routine before XRAM is used In extremely noisy systems the user may have redundant clear instructions The control bit XMAP1 is relevant only if the XRAM is accessed In this case the external RD and WR signals at P3 6 and P3 7 are not activated during the access if XMAP1 is cleared For debug purposes it might be useful to have these signals and the addresses at Ports 0 2 available This is performed if XMAP1 is set The behaviour of Port 0 and P2 during a MOVX access depends on the control bits in register SYSCON and on the state of pin EA The table 1 lists the various operating conditions It shows the following characteristics a Use of PO and P2 pins during the MOVX access Bus The pins work as external address data bus If internal XRAM is accessed the data written to the XRAM can be seen on the bus in debug mode 0 The pins work as Input Output lines under control of their latch b Activation of the RD and WR pin during the access C Use of internal or external XDATA memory The shaded areas describe the standard operation as each 80C51 device without on chip XRAM behaves Semiconductor Group 18 dno19 1ojonpuooruies 61 Table 1 Behaviour of 2 and RD WR during MOVX accesses MOVX DPTR MOVX 0 1 XMAP1 XMAPO XMAP1 XMAPO 00 10 X1 00
28. d for several alternate functions as listed below Port Symbol Function P1 0 INT3 CCO External interrupt 3 input compare 0 output capture 0 input P1 1 INT4 CC1 External interrupt 4 input compare 1 output capture 1 input P1 2 INT5 CC2 External interrupt 5 input compare 2 output capture 2 input P1 3 INT6 CC3 External interrupt 6 input compare 3 output capture 3 input P1 4 INT2 External interrupt 2 input P1 5 T2EX Timer 2 external reload trigger input P1 6 CLKOUT System clock output P1 7 T2 Timer 2 external count or gate input P3 0 RxD Serial port s receiver data input asynchronous or data input output synchronous P3 1 TxD Serial port s transmitter data output asynchronous or clock output synchronous P3 2 INTO External interrupt 0 input timer 0 gate control P3 3 INT 1 External interrupt 1 input timer 1 gate control P3 4 TO Timer 0 external counter input 5 T1 Timer 1 external counter input P3 6 WR External data memory write strobe 7 RD External data memory read strobe P4 0 ADST A D Converter external start of conversion The SAB 80C515A has one dual purpose input port The ANx lines of port 6 in the SAB 806515 can individually be used as analog or digital inputs Reading the special function register P6 allows the user to input the digital values currently applied to the port pins It is not necessary to select these modes by software the voltages applied at port 6 pins can be converted to digital val
29. disconnected Ipp Hardware Power Down Mode independent of any particular pin connection Icc active mode is measured with XTAL2 driven with 1 5 ns Ves 4 0 5 V 0 5 V XTAL1 N C EA PE SWD Voc PortO Port6 Voc HWPD Voc RESET Vss all other pins are disconnected cc would be slightly higher if a crystal oscillator is used ap pr 1 mA Idle mode is measured with all output pins disconnected and with all peripherals dis abled XTAL2 driven with tc 1 5 ns Vj 0 5 V Vj Vog 0 5 V XTAL1 N C RESET Voc HWPD Port0 Port6 Voc EA PE SWD Vas all other pins are disconnected slow down mode is measured with all output pins disconnected and with all peripherals disabled XTAL2 driven with cLCH CHCL 5 ns ViL V ss 0 5 V 0 5 V XTAL1 N C RESET HWPD Vcc Port6 Voc EA PE SWD Vas all other pins are disconnected Max at other frequencies is given by active mode cc max 1 5 fosc 8 idle mode cc 0 4 fosc 7 where fosc is the oscillator frequency in MHz cc values are given in mA and measured at Voc 5 V Semiconductor Group 45 SIEMENS SAB 80C515A 83C515A 5 A D Converter Characteristics 5 10 15 Vgg 20 V VAREF Voc t 596 VAGND 0 2 T a 0 to 70 C for th
30. e 1 s written to them are pulled high by the internal pullup resistors and in that state can be used as inputs As inputs port 5 pins being externally pulled low will source current Ij in the DC characteristics because of the internal pullup resistors 69 Hardware Power Down A low level on this pin for the duration of one machine cycle while the oscillator is running resets the SAB 80C515A A low level for a longer period will force the part to Power Down Mode with the pins float ing see table 5 32 33 Supply voltage during normal idle and power down operation 34 35 Ground 0 V 2 13 14 23 46 50 51 68 70 71 Not connected These pins of the P MQFP 80 package must not be connected Semiconductor Group 10 SIEMENS SAB 80 515 83 515 5 77 Oscillat ROM SAB 05 amp 83C515A 5 Timing only Ge Port 0 Watchdog 22 EA RE A Bi 8 Bit 8 81 Capture Unit m or 8 Bit Serial Port Port 5 oe E 8 81 2 Interrupt 7 Port 6 8 Bit VAREF VAGND 7 777 Enhancements to the Ext Start 80C515 80C535 MCB01563 Figure 1 Block Diagram Semiconductor Group 11 SIEMENS SAB 80C515A 83C51
31. e contents is undefined while it remains unchanged during and after a reset or HW Power Down if the power supply is not turned off The additional On Chip RAM is logically located in the external data memory range at the upper end of the 64 Kbyte address range F800 FBFF Nevertheless when XRAM is enabled the address range F800 to FFFFy is occupied This is done to assure software compatibility to SAB 80C517A It is possible to enable and disable only by reset the XRAM If itis disabled the device shows the same behaviour as the parts without XRAM i e all MOVX accesses use the external bus to physically external data memory Semiconductor Group 14 SIEMENS SAB 80 515 83 515 5 Accesses to XRAM Because the XRAM is used in the same way as external data memory the same instruction types must be used for accessing the XRAM Note fa reset occurs during a write operation to XRAM the effect on XRAM depends on the cycle which the reset is detected at MOVX is a 2 cycle instruction Reset detection at cycle 1 The new value will not be written to XRAM The old value is not affected Reset detection at cycle 2 old value in XRAM is overwritten by the new value Accesses to XRAM using the DPTR There are a Read and a Write instruction from and to XRAM which use one of the 16 bit DPTR for indirect addressing The instructions are MOVXA QDPTR Read MOVX DPTR A Write Normally the use of these instruction
32. e SAB 80C515A 83C515A 5 T a 40 to 85 for the SAB 80C515A T3 83C515A 5 T3 Parameter Symbol Limit values Unit Test condition min typ max Analog input capacitance C 25 70 pF Sample time Ts 4tcy Jus 2 inc load time Conversion time Tc 14tgy us 3 inc sample time Total unadjusted error TUE 2 LSB Vangr Vcc YAGND Vss Varer Supply current InErF t 20 1 _ aso E ADCL t cy 872 fosc tcv lfApc fapc 7 fosc 8 2 2 This parameter specifies the time during the input capacitance be charged discharged by the external source It must be guaranteed that the input capacitance is fully loaded within this time ATCY is 2 us at the fosc 16 MHz After the end of the sample time T s changes of the analog input voltage have no effect on the conversion result 9 This parameter includes the sample time 14TCY is 7 us at fosc 16 MHz Semiconductor Group 46 SIEMENS SAB 80C515A 83C515A 5 AC Characteristics 5 10 15 Vss 0V Ta Oto 70 C for the SAB 80C515A 83C515A 5 T 40 to 85 C for the SAB 80C515A T3 83C515A 5 T3 C for port 0 ALE and PSEN outputs 100 pF C for all other outputs 80 pF Parameter Symbol Limit values Unit 18 MHz clock Variable clock 1 3 5 MHz to 18 MHz min max min max Program Me
33. e XRAM address range then an external access is performed For the SAB 80C515A the contents of XPAGE must be greater or equal than F8H in order to use the XRAM Of course the XRAM must be enabled if it shall be used with MOVX Ri instructions Thus the register XPAGE is used for addressing of the XRAM additionally its contents are used for generating the internal XRAM select If the contents of XPAGE is less than the XRAM address range then an external bus access is performed where the upper address byte is provided by P2 and not by XPAGE Therefore the software has to distinguish two cases if the MOVX Ri instructions with paging shall be used a Access to XRAM The upper address byte must be written to XPAGE or P2 both writes selects the XRAM address range b Access to external memory The upper address byte must be written to P2 XPAGE will be loaded with the same address in order to deselect the XRAM Semiconductor Group 16 SIEMENS SAB 80 515 83 515 5 Control of XRAM in the SAB 80C515A There are two control bits in register SYSCON which control the use and the bus operation during accesses to the additional On Chip RAM XRAM Special Function Register SYSCON Addr 1 XMAP1 XMAPO SYSCON Bit Function XMAPO Global enable disable bit for XRAM memory 0 The access to XRAM On Chip XDATA memory is en abled XMAPO 1 The access to XRAM is disabled All
34. ed during Reset the WDT cannot be started externally during normal operation Software initialization is done by setting bit SWDT in SFR IEN1 A refresh of the watchdog timer is done by setting bits WDT SFR IENO and SWDT consecutively This double instruction sequence has been implemented to increase system security When a watchdog timer reset occurs the watchdog timer keeps on running but a status flag WDTS SFR is set This flag can also be cleared by software Figure 7 shows the block diagram of the programmable Watchdog Timer Oscillator Watchdog The unit serves three functions Monitoring of the on chip oscillator s function The watchdog monitors the on chip oscillator s frequency if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit the internal clock is supplied by the RC oscillator and the device is forced into reset if the failure condition disappears i e the on chip oscillator has again a higher frequency than the RC oscillator the part executes a final reset phase of appr 0 25 ms in order to allow the oscillator to stabilize then the oscillator watchdog reset is released and the part starts program execution again Restart from the Hardware Power Down Mode If the Hardware Power Down Mode is terminated the oscillator watchdog has to control the correct start up of the on chip oscillator and to restart the program The oscillator watchdog function is only part of the c
35. ernal pullup resistors and in that state can be used as inputs As inputs port 3 pins being externally pulled low will source current in the DC characteristics because of the internal pullup resistors Port 3 also contains the interrupt timer serial port and external memory strobe pins that are used by various options The output latch corresponding to a secondary function must be programmed to a one 1 for that function to operate The secondary functions are assigned to the pins of port 3 as follows RxD P3 0 serial port s receiver data input asynchronous or data input output synchronous TxD P3 1 serial port s transmitter data output asynchronous or clock output synchronous INTO P3 2 interrupt 0 input timer 0 gate control input NT1 P3 3 interrupt 1 input timer 1 gate control input TO P3 4 counter 0 input T1 P3 5 WR P3 6 counter 1 input the write control signal latches the data byte from port 0 into the external data memory RD P3 7 the read control signal enables the external data memory to port 0 Semiconductor Group SIEMENS SAB 80 515 83 515 5 Pin Definitions and Functions cont d Symbol Pin Pin Input 1 Function P LCC 68 P MQFP 80 Output 7 29 36 24 31 Port 1 XTAL2 39 36 is an 8 bit bidirectional I O port with internal pullup resistors Port 1 pins that have 1 s written to them
36. errupt IEX2 004By External interrupt 2 IEX3 00534 External interrupt 3 IEX4 005BH External interrupt 4 IEX5 0063 External interrupt 5 IEX6 OO6By External interrupt 6 Each interrupt vector can be individually enabled disabled The minimum response time to an interrupt request is more than 3 machine cycles and less than 9 machine cycles if no other interrrupt of the same or a higher priority level is in process Figure 5 shows the interrupt request sources External interrupts 0 and 1 can be activated by a low level or a negative transition selectable at their corresponding input pin external interrupts 2 and 3 can be programmed for triggering on a negative or a positive transition The external interrupts 3 or 6 are combined with the corresponding alternate functions compare output and capture input on port 1 For programming of the priority levels the interrupt vectors are combined to pairs Each pair can be programmed individually to one of four priority levels by setting or clearing one bit in special function register IPO and one in IP1 Figure 6 shows the priority level structure Semiconductor Group 30 SIEMENS SAB 80 515 83 515 5 P3 2 INTO TIMER 0 Overflow P3 3 INT1 TIMER 1 Overflow Receiver SERIAL PORT Transmitter TIMER 2 Overflow gt TF2 P1 5 T2EX e o2 EXEN2 Interrupt Control A D Converter gt P1 4 INT2 P T2CON 5 Compare 0
37. everal additional features It offers a 2 1 prescaler a selectable gate function and compare capture and reload functions Corresponding to the 16 bit timer register there are four 16 bit capture compare registers one of them can be used to perform a 16 bit reload on a timer overflow or external event Each of these registers corresponds to a pin of port 1 for capture input compare output Figure 4 shows a block diagram of timer counter 2 Reload A 16 bit reload can be performed with the 16 bit CRC register consisting of CRCL and CRCH There are two modes from which to select Mode 0 Reload is caused by a timer 2 overflow auto reload Mode 1 Reload is caused in response to a negative transition at pin T2EX P1 5 which can also request an interrupt Semiconductor Group 27 SIEMENS SAB 80C515A 83C515A 5 Capture This feature permits saving of the actual timer counter contents into a selected register upon an external event or a software write operation Two modes are provided to latch the current 16 bit value of timer 2 registers TL2 and TH2 into a dedicated capture register Mode 0 Capture is performed in response to a transition at the corresponding port 1 pins CCO to CC3 Mode 1 Write operation into the low order byte of the dedicated capture register causes the timer 2 contents to be latched into this register Compare In compare mode the 16 bit values stored in the dedicated compare registers are compared to
38. hip oscillator has started the oscillator watchdog releases the part from reset with oscillator watchdog status flag set When automatic start of the watchdog was enabled PE SWD connected to Voc the Watchdog Timer will start too with its default reload value for time out period The Reset pin overrides the Hardware Power Down function i e if reset gets active during Hardware Power Down it is terminated and the device performs the normal resetfunction Thus pin Reset has to be inactive during Hardware Power Down Mode function Thus pin Reset has to be inactive during Hardware Power Down Mode Semiconductor Group 36 SIEMENS SAB 80C515A 83C515A 5 Table 5 Status of all pins during Idle Mode Power Down Mode and Hardware Power Down Mode Pins Idle Mode Power Down Mode Hardware Power Last instruction Last instruction Down executed from executed from internal external internal external Status ROM ROM ROM ROM PO Data float Data float P1 Data Dat Data Data floating 7 alt outputs alt outputsa last outputs last outputs P2 Data Address Data Data P3 Data Data Data Data outputs alt outputs alt outputs output last output P4 Data Data Data Data disabled alt outputs alt outputs last outputs last output P5 Data Data Data Data input alt output alt output last output last output P6 y function EA active input 2 PE SWD acti
39. l be the one following the instruction that set the bit IDLS The other way to terminate the idle mode is a hardware reset Since the oscillator is still running the hardware reset must be held active only for two machine cycles for a complete reset Normally the port pins hold the logical state they had at the time idle mode was activated If some pins are programmed to serve their alternate functions they still continue to output during idle mode if the assigned function is on The control signals ALE and PSEN hold at logic high levels see table 5 Semiconductor Group 35 SIEMENS SAB 80C515A 83C515A 5 Software Power Down Mode The power down mode is entered by two consecutive instructions directly following each other The first instruction has to set the flag PDE power down enable and must not set PDS power down set The following instruction has to set the start bit PDS Bits PDE and PDS will automatically be cleared after having been set The instruction that sets bit PDS is the last instruction executed before going into power down mode The only exit from power down mode is a hardware reset The status of all output lines of the controller can be looked up in table 5 Hardware Controlled Power Down Mode The pin HWPD controls this mode If it is on logic high level inactive the part is running in the normal operating modes If pin HWPD gets active low level the part enters the Hardware Power Down Mode this
40. l reset signal must be internally synchronized and processed in order to bring the device into the correct reset state Especially if a crystal is used the start up time of the oscillator is relatively long typ 1 ms During this time period the pins have an undefined state which could have severe effects e g to actuators connected to port pins In the SAB 80C515A the oscillator watchdog unit avoids this situation After power on the oscillator watchdog s RC oscillator starts working within a very short start up time typ less than 2 ms In the following the watchdog circuitry detects a failure condition for the on chip oscillator because this has not yet started a failure is always recognized if the watchdog s RC oscillator runs faster than the on chip oscillator As long as this condition is valid the watchdog uses the RC oscillator output as clock source for the chip rather than the on chip oscillator s output This allows correct resetting of the part and brings also all ports to the defined state Delay time between power on and correct reset state Typ 18 us Max 34 us Instruction Set The SAB 80C515A 83C515A 5 has the same instruction set as the industry standard 8051 microcontroller A pocket guide is available which contains the complete instruction set in functional and hexadecimal order Furtheron it provides helpful information about Special Function Registers Interrupt Vectors and Assembler Directives Literatu
41. mbines high speed and density characteristics with low power consumption or dissipation While maintaining all the SAB 80C515 features and operating characteristics the SAB 80 515 83 515 5 contains more on chip RAM ROM Furthermore a new 10 bit A D Converter is implemented as well as extended security mechanisms The SAB 80C515A is identical with the SAB 83C515A 5 except that it lacks the on chip program memory The SAB 80C515A 83C515A 5 is supplied in 68 pin plastic leaded chip carrier package P LCC 68 and in a 80 pin plastic metric quad flat package P MQFP 80 Versions for extended temperature range 40 to 110 C are available on request Semiconductor Group 1 08 95 SIEMENS SAB 80C515A 83C515A 5 SAB 80 515 80 535 Oscillator Watchdog A x 8 HW Power CPU Down 2 80C51 Core Mode Slow Down Mode Analog 1 0 ROM Digital 24k x 8 Input ROM Protection available Shaded areas meaning improved functionality 01560 Ordering Information Type Ordering Package Description Code 8 Bit CMOS microcontroller SAB 80C515A N18 Q67120 C0581 P LCC 68 for external memory 18 MHz SAB 83 515 5 18 Q67120 DXXXX P LCC 68 mask programmable ROM 18 MHz SAB 80C515A N18 T3 Q67120 C0784 P LCC 68 external memory 18 MHz ext temperature 40 to 85 C SAB 83C515A 5N18 T3 Q67120 DXXXX P LCC 68 with mask programmable ROM 18 MHz ext temperature
42. mory Characteristics ALE pulse width fL HLL 71 s 2 tc LCL 40 ns Address setup to ALE tAVLL 26 30 ns Address hold after ALE ti Ax 26 30 ns ALE to valid m 122 4tcicL 100 ns instruction in ALE to PSEN 31 tc LCL 25 ns PSEN pulse width p pH 132 3 tc LCL 35 ns PSEN to valid fp IV 92 3 tc LCL 75 ns instruction in Input instruction hold 0 0 ns after PSEN Input instruction float tpxjz 46 x 10 ns after PSEN Address valid after tpxav 48 8 ns PSEN Address to valid taviv 218 60 ins instruction in Address float to PSEN 0 0 ns Interfacing the SAB 80C515A to devices with float times up to 45 ns is permissible This limited bus contention will not cause any damage to port 0 drivers Semiconductor Group 47 SIEMENS SAB 80C515A 83C515A 5 AC Characteristics cont d Parameter Symbol Limit values Unit 18 MHz clock Variable clock 1 3 5 MHz to 18 MHz min max min max External Data Memory Characteristics RD pulse width 233 100 ns WR pulse width 233 100 l ns Address hold after tLLAX2 81 2 30 ns ALE RD to valid data in 128 150 ns DATA hold after RD tRHD
43. n chip oscillator and the RC oscillator are turned off The pin HWPD controls this mode Port pins and several control lines enter a floating state The Hardware Power Down Mode is new in the SAB 80C515A and is independent of the state of pin PE SWD which enables only the software initiated power reduction modes Hardware Enable for Software controlled Power Saving Modes A dedicated pin PE SWD of the SAB 80C5154 allows to block the Software controlled power saving modes Since this pin is mostly used in noise critical application it is combined with an automatic start of the Watchdog Timer PE SWD V logic high level Using of the power saving modes is not possible The watchdog timer starts immediately after reset The instruction sequences used for entering of power saving modes will not affect the normal operation of the device PE SWD V logic low level All power saving moes can be activated by software The watchdog timer can be started by software at any time When left unconnected pin PE SWD is pulled high by a weak internall pull up This is done to provide system protection on default The logic level applied to pin PE SWD can be changed during program execution to allow or to block the use of the power saving modes without any effect on the on chip watchdog circuitry Semiconductor Group 34 SIEMENS SAB 80 515 83 515 5 Requirements for Hardware Power Down Mode There is no dedicated pin to enable the Hardw
44. nce Cio 10 pF 1 MHz TA 25 C Power supply current Active mode 12 MHz 26 mA Voc 5V 4 Active mode 18 MHz 35 mA 5 Idle mode 12 MHz Icc 11 8 mA 5 Idle mode 18 MHz 14 2 mA 5 Slow down mode 12 MHz 9 mA 5 Slow down mode 18 MHz 10 mA 5 6 Power Down Mode Ipp 50 2 5 5 V9 Notes see page 43 Semiconductor Group 44 SIEMENS SAB 80 515 83 515 5 Notes for page 44 1 X 2 2 Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed the Vo of ALE and ports 1 3 4 and 5 The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus operation In the worst case capacitive loading gt 100 pF the noise pulse on ALE line may exceed 0 8 V In such cases it may be desirable to qualify ALE with a schmitt trigger or use an address latch with a schmitt trigger strobe input Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the 0 9 Voc specification when the address lines are stabilizing Ipp Software Power Down Mode is measured under following conditions EA RESET Voc Port0 Port6 Voc XTAL1 N C XTAL2 Vas PE SWD HWPD Voc VAGND VaRef Voc all other pins are
45. omplete Hardware Power Down sequence however the watchdog works identically to the monitoring function Fast internal reset after power on In this function the oscillator watchdog unit provides a clock supply for the reset before the on chip oscillator has started In this case the oscillator watchdog unit also works identically to the monitoring function Semiconductor Group 40 SIEMENS SAB 80 515 83 515 5 Figure 8 shows the block diagram of the oscillator watchdog unit It consists of an internal RC oscillator which provides the reference frequency for the frequency comparator ME LR WDT Reset Request 0 9 10511111 Hardware Power Down HWPD ternal HW Reset 1 495 Figure 7 Block Diagram of the Programmable Watchdog Timer RC fre fi Oscillator 3MHz 5 Frequency fa lt fi Comparator Delay 049 On Chi Oscillator 111111 ONL int Clock 2 or MCB01569 Figure 8 Functional Block Diagram of the Oscillator Watchdog Semiconductor Group 41 SIEMENS SAB 80C515A 83C515A 5 Fast internal reset after power on The SAB 80C515A can use the oscillator watchdog unit for a fast internal reset procedure after power on Normally members of the 8051 family like the SAB 80C515 enter their default reset state not before the on chip oscillator starts The reason is that the externa
46. re Information Title Ordering No Microcontroller Family SAB 8051 Pocket Guide B158 H6497 X X 7600 Semiconductor Group 42 SIEMENS SAB 80 515 83 515 5 Absolute Maximum Ratings Ambient temperature under bias 40 to 85 C Storage temperature 65 to 150 C Voltage on pins with respect to ground Vss 0 5 Vto6 5V Voltage on pin with respect to ground Vss 0 5 to Veg 0 5 V Input current on any pin during overload condition 10mA to 10 mA Absolute sum of all input currents during overload condition 1100 mA Power dissipation 1W Note Stresses above those listed under Absolute Maximum Ratings may cause permanent damage of the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for longer periods may affect device reliability During overload conditions gt Vec or Vin lt Vss theVoltage on Vcc pins with respect to ground Vss must not exeed the values defind ed by the absolute maximum ratings DC Characteristics 25V 1026 15 96 Vag 20 V T a 0 to 70 C for the SAB 80C515A T a 40 to 85 C for the SAB 80C515A T3 Parameter Symbol Limit Values Unit Test condition min max Input low voltage VL 0 5 0 2 Vcc exept EA RESET
47. s would use a physically external memory However in the SAB 80C515A the XRAM is accessed if it is enabled and if the DPTR points to the XRAM address space DPTR gt F800 Accesses to XRAM using the Registers RO R1 The 8051 architecture provides also instructions for accesses to external data memory range which use only an 8 bit address indirect addressing with registers RO or R1 The instructions are MOVX A Qhi Read MOVX Ri A Write In application systems either a real 8 bit bus with 8 bit address is used or Port 2 serves as page register which selects pages of 256 byte However the distinction whether Port 2 is used as general purpose or as page address is made by the external system design From the device s point of view it cannot be decided whether the Port 2 data is used externally as address or as 1 data Hence a special page register is implemented into the SAB 80C515A to provide the possibility of accessing the XRAM also with the MOVX Ri instructions i e XPAGE serves the same function for the XRAM as Port 2 for external data memory Semiconductor Group 15 SIEMENS SAB 80C515A 83C515A 5 Special Function Register XPAGE Addr 914 XPAGE The reset value of XPAGE is 00 XPAGE can be set and read by software The register XPAGE provides the upper address byte for accesses to XRAM with MOVX Ri instructions If the address formed from XPAGE and Ri is less than th
48. ses The signal remains high during internal program execution ALE 50 48 The Address Latch enable output is used for latching the address into external memory during normal operation It is activated every six oscillator periods except during an external data memory access Semiconductor Group SIEMENS SAB 80C515A 83C515A 5 Pin Definitions and Functions cont d Symbol Pin P LCC 68 Pin P MQFP 80 Input 1 Output O Function EA 51 49 External Access Enable When held high the SAB 80C515A executes instructions from the internal ROM as long as the PC is less than 32768 When held low the SAB 80C515A fetches all instructions from external program memory For the SAB 80C515A this pin must be tied low 7 52 59 52 59 I O Port 0 is an 8 bit open drain bidirectional MO port Port 0 pins that have 1 s written to them float and in that state can be used as high impedance inputs Port 0 is also the multiplexed low order address and data bus during accesses to external program and data memory In this application it uses strong internal pullup resistors when issuing 1 s Port 0 also outputs the code bytes during program verification in the SAB 80C515A External pullup resistors are required during program verification P5 7 P5 0 60 67 60 67 I O Port 5 is an 8 bit bidirectional I O port with internal pullup resistors Port 5 pins that hav
49. special function registers 2 This special function register is listed repeatedly since some bits of it also belong to other functional blocks 3 X means that the value is indeterminate and the location is reserved Semiconductor Group 24 SIEMENS SAB 80 515 83 515 5 A D Converter In the SAB 80C515A a new high performance high speed 8 channel 10 bit A D Converter ADC is implemented Its successive approximation technique provides 7 us conversion time fosc 16 MHz The conversion principle is upward compatible to the one used in the SAB 80C515 The main functional blocks are shown in figure 3 The comparator is a fully differential comparator for a high power supply rejection ratio and very low offset voltages The capacitor network is binary weighted providing genuine10 bit resolution The table below shows the sample time T s and the conversion time T c which are dependend f osc and a new prescaler f osc MHz Prescaler f MHz Sample Time Conversion Time incl sample time Ts us Tc us 12 8 1 5 2 67 9 3 16 0 75 5 33 18 66 16 8 2 0 2 0 7 0 16 1 0 1 0 14 0 18 8 16 1 125 3 55 12 4 The ADC is clocked f Apc with f osc 8 Because of the ADC s maximum clock frequency of 2 MHz the prescaler divide by 2 has to be enabled set Bit ADCL in SFR ADCON 1 when the oscillator frequency f osc is higher than 16 MHz Semiconductor Group 25 SIEMENS SA
50. the contents of the timer 2 registers If the count value in the timer 2 registers matches one of the stored values an appropriate output signal is generated and an interrupt is requested Two compare modes are provided Mode 0 Upon a match the output signal changes from low to high It goes back to low level when timer 2 overflows Mode 1 The transition of the output signal can be determined by software A timer 2 overflow causes no output change Semiconductor Group 28 SIEMENS SAB 80 515 83 515 5 P15 T2EX emm 21 Interrupt Request TL2 TH2 Compare P1 0 INT3 P1 1 INT4 CC1 Le P1 2 INT5 CC1 4 gt P1 3 INT6 CC3 6 Bit 16 Bit Comparator Comparator Input Output Control v Capture CCL3 CCH3 CCL2 CCH2 CCL1 CCH1 CRCL CRCH 00079 Figure 4 Block Diagram of Timer Counter 2 Semiconductor Group 29 SIEMENS SAB 80C515A 83C515A 5 Interrupt Structure The SAB 80C515A has 12 interrupt vectors with the following vector addresses and request flags Table 4 Interrupt Sources and Vectors Source Request Flags Vector Address Vector IEO 0003 External interrupt 0 TFO 000BH Timer 0 interrupt IE1 0013 External interrupt 1 TF1 001By Timer 1 interrupt RI TI 00234 Serial port interrupt TF2 EXF2 002By Timer 2 interrupt IADC 0043 A D converter int
51. to enter the power down idle and slow down mode In case the low level is also seen during reset the watchdog timer function is off on de fault Use of the software controlled power saving modes is blocked when this pin is held on high level A high level during reset performs an automatic start of the watchdog timer im mediately after reset When left unconnected this pin is pulled high by a weak internal pull up resistor HESET 10 1 Reset pin A low level on this pin for the duration of two machine cycles while the oscillator is running resets the SAB 80C515A A small internal pullup resistor permits power on reset using only a capacitor connected to Vss V AREF 11 3 Reference voltage for the A D converter VAGND 12 4 Reference ground for the A D converter Semiconductor Group 6 SIEMENS SAB 80 515 83 515 5 Pin Definitions and Functions cont d Pin P LCC 68 Symbol Pin P MQFP 80 Input 1 Output O Function P6 7 P6 0 13 20 5 12 Port 6 is an 8 bit unidirectional input port to the A D converter Port pins can be used for digital input if voltage levels simultaneously meet the specifications high low input voltages and for the eight multiplexed analog inputs 0 7 21 28 15 22 I O Port 3 is an 8 bit bidirectional I O port with internal pullup resistors Port pins that have1 s written to them are pulled high by the int
52. ues using the A D converter and at the same time the pins can be read via SFR P6 It must be noted however that the results in port P6 bits will be indeterminate if the levels at the corresponding pins are not within their Vj specifications Furthermore it is not possible to use port P6 as an output port Special function register P6 is located at address In Hardware Power Down Mode the port pins and several control lines enter a floating state For more details see the section about Hardware Power Down Mode Semiconductor Group 33 SIEMENS SAB 80C515A 83C515A 5 Power Saving Modes The SAB 80C515A provides due to Siemens ACMOS technology four modes in which power consumption can be significantly reduced The Slow Down Mode The controller keeps up the full operating functionality but is driven with one eight of its normal operating frequency Slowing down the frequency remarkable reduces power consumption The Idle Mode The CPU is gated off from the oscillator but all peripherals are still supplied with the clock and continue working The Software Power Down Mode Operation of the SAB 80C515A is stopped the on chip oscillator and the RC oscillator are turned off This mode is used to save the contents of the internal RAM with a very low standby current and is fully compatible to the Power Down Mode of the SAB 80C515 The Hardware Power Down Mode Operation of the SAB 80C515A is stopped the o
53. ve input pull up disabled XTAL1 active output XTAL2 disabled input function 1 PSEN high high low low floating output ALE high high low low VAREF active supply pins VAGND HESET active input must be high 1 Applied voltage range at pin Vas lt Vec 2 Vin Vss or Vin Voc Vas lt Vin lt Voc V AREF 2 VAGND Semiconductor Group 37 SIEMENS SAB 80C515A 83C515A 5 Serial Interface The SAB 80C515A has a full duplex and receive buffered serial interface It is functionally identical with the serial interface of the SAB 8051 Table 6 shows possible configurations and the according baud rates Table 6 Baud Rate Generation Mode 8 Bit fosc 12 MHz 1 MHz syn E chron Josce 16 MHz 1 33 MHz ous fosc 18 MHz 11 5 MHz channel derived from fosc Mode Mode 1 8 Bit fosc 12 MHz 1 Baud 62 5 kBaud 183 Baud 375 kBaud eee fosc 16 MHz 1 Baud 83 kBaud 244 Baud 500 kBaud fosc 18 MHz 1 Baud 93 7 kBaud 2375 Baud 562 5 kBaud derived from Timer 1 10 Bit Baudrate Generator Mode Mode 2 Mode 3 9 Bit fosc 12 MHz 187 5 kBaud 1 Baud 183 Baud 75 kBaud UART 375 kBaud 62 5 kBaud fosc 16 MHz 250 Baud 1 Baud 244 Baud 500 kBaud 500 kBaud 83 3 kBaud fosc 18 MHz 281 2 kBaud 11 Baud 275 Baud 562 5 kBaud 562 5 kBaud 93 7 kBaud derived from Timer 1 10 Bit Baudrate Generator Semiconductor Group 38 SIEMENS SAB 80
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