MEG Array Daughter Card Interface Description
Contents
1. A27 DCC1P23 A26 B28 DCC1N23 B26 C27 DCC1P24 A24 D28 DCC1N24 A25 H27 DCC1P25 G23 G28 DCC1N25 H24 K27 DCC1P0 F24 J28 DCC1NO E24 2 3 6 Bank B2 10 Pins shaded yellow are CC pins E27 DCC2P28 N32 F27 DCC2N28 P32 A29 DCC2P30 P30 B30 DCC2N30 P31 C29 DCC2P2 T24 D30 DCC2N2 T25 E29 DCC2P29 AB31 F29 DCC2N29 AA31 H29 DCC2P3 Y29 G30 DCC2N3 W29 K29 DCC2P4 W27 J30 DCC2N4 V27 A31 DCC2P5 R27 B32 DCC2N5_VR R28 C31 DCC2P6 T23 D32 DCC2N6 U23 E31 DCC2P25 P29 Daughter Card Specification www dinigroup com DAUGHTERCARD SPECIFICATION F31 DCC2N25 R29 H31 DCC2P7 U30 G32 DCC2N7 U31 31 DCC2P8 Y31 J32 DCC2N8_VR W31 A33 DCC2P9 V28 B34 DCC2N9_VR V29 C33 DCC2P10 W32 D34 DCC2N10 V32 E33 DCC2P26 AB32 F33 DCC2N26 AB33 H33 DCC2P11 U26 G34 DCC2N11 U27 K33 DCC2P12 T28 J34 DCC2N12_VR U28 A35 pcc2P13 C N33 B36 DCC2N13_C N34 C35 DCC2P14 V23 D36 DCC2N14 V24 E35 DCC2P27 AA33 F35 DCC2N27 AA34 H35 DCC2P15 T33 G36 DCC2N15 T34 35 DCC2P16_C Y32 36 DCC2N16_C Y33 A37 DCC2P17_C W30 B38 DCC2N17_C V30 C37 DCC2P18 V33 D38 DCC2N18 V34 E37 DCC2P1 R26 F37 DCC2N1 T26 H37 DCC2P19 R31 G38 DCC2N19 T31 K37 DCC2P20_C P34 38 DCC2N20_C R34 A39 DCC2P21 U32 B40 DCC2N21 U33 C39 DCC2P22 V25 D40 DCC2N22 U25 E39 DCC2P0 Y27 F39 DCC2N0 Y28 H39 DCC2P23 T29 G40 DCC2N23 T30 K39 DCC2P24 R32 J40 DCC2N24 R33 Daughter Card Specification www dinigroup com DAUGHTERCARD SPECIFICATION 2 3 7 VCCIO Signals VCCO corresponds to bank BO V2. L28 DCCON18 L29 DCCOP28 L33 DCCON28 L34 DCCOP19 J29 DCCON19 J30 DCCOP20_C G30 DCCON20_C G31 DCCOP21 P24 DCCON21 R24 DCCOP22 M27 DCCON22 M28 DCCOP29 M32 DCCON29 M33 DCCOP23 P22 DCCON23 R21 DCCOP24 E32 DCCON24 E33 DCCOP25 H33 Daughter Card Specification www dinigroup com DAUGHTERCARD SPECIFICATION B16 DCCON25 H34 C15 DCCOPO P20 D16 DCCONO R19 F15 DCCON30 C34 E15 DCCOP30 C33 2 3 5 Bank B1 10 Pins shaded yellow are CC pins H15 DCC1P1 B21 G16 DCC1N1 A21 K15 DCC1P2 E28 J16 DCC1N2 F28 A17 DCC1P3 A30 B18 DCC1N3 B30 C17 DCC1P4 K24 D18 DCC1N4 J24 E17 DCC1P26 D24 F17 DCC1N26 D25 H17 DCC1P5 G27 G18 DCC1N5 G28 K17 DCC1P6 D30 J18 DCC1N6 D31 A19 DCC1P7 C29 B20 DCC1N7_VR C30 C19 DCC1P8 C22 D20 DCC1N8 B22 E19 DCC1P27 D29 F19 DCC1N27 E29 H19 DCC1P9 J25 G20 DCC1N9 K26 K19 DCC1P10 F29 J20 DCC1N10 VR F30 A21 DCC1P11 G25 B22 DCC1N11_VR H25 C21 DCC1P12 F25 D22 DCC1N12 F26 E21 DCC1P28 L25 F21 DCC1N28 L26 H21 DCC1P13 B25 G22 DCC1N13 C25 21 DCC1P14 D27 J22 DCC1N14_VR E27 A23 DCC1P15_C A31 B24 DCC1N15_C B31 C23 DCC1P16 C23 Daughter Card Specification www dinigroup com DAUGHTERCARD SPECIFICATION D24 DCC1N16 C24 E23 DCC1P29 B32 F23 DCC1N29 B33 H23 DCC1P17 A28 G24 DCC1N17 A29 K23 DCC1P18_C B28 24 DCC1N18_C C28 5 DCC1P19_C B27 B26 DCC1N19_C C27 C25 DCC1P20 B23 D26 DCC1N20 A23 E25 DCC1P30 E31 F25 DCC1N30 F31 H25 DCC1P21 D26 G26 DCC1N21 E26 K25 DCC1P22_C F23 26 DCC1N22_C E23
3. are not length matched except for each signal in a differential pair which are Differential pairs are routed in parallel but not closely coupled to make single ended signaling possible Using the IDELAY and ODELAY Stratix devices adaptive delay elements on the FPGA the skew between mismatched signals can be corrected Most pins are assigned in a GSG pattern to minimize crosstalk Some signals are arranged in a GSSG pattern Pins in column E and F 2 1 1 DCI Host boards whose FPGAs that have DCI digitally controlled impedance capabilities have DCI enabled with a 50 ohm reference resistor This allows LVCMOS_DCI and SSTL_DCI IO standards to be used 2 2 Daughter card Signals Bank 0 VCCOOQ0 includes the signals BL 0 31 Bank 1 VCCO1 includes B1L 0 31 Bank 2 VCCO2 includes signals B2L 0 31 Special purpose pins are described below 2 2 1 Clock Outputs These signals are used for sending a clock signal differential from the daughter card to the host The pair GCAP GCAN Pairs E1 F1 can be used as a SSTL18 SSTL25 LVDS differential pair or GCAP can be used single endedly as LVCMOS25 These signals only connect to the FPGA associated with the connector The pait GCBP GCBN B3 F3 can be used as a SSTL18 SSTL25 LVDS differential pair or GCAP can be used single endedly as LVCMOS25 These signals only connect to the FPGA associated with the connector The pair GCCP GCCN Pair E5 F5 must be used as an LVDS pair T
4. deskewed on the host FPGAs on the host will receive this signal synchronized with respect to each other but with no phase relationship with the daughter card 4 2 2 DN8000K10 Daughter cards DO D1 D2 D3 D4 D9 use 300 pin Meg Array connectors instead of 400 pin The signal definitions remain the same except that pin rows 29 40 are not present and the connector supports two banks BO B1 instead of three DCO and DC3 do not comply with these specifications See the DN8000K10 user guide and schematic These headers are used for RocketIO signaling These signals are routed as 110 ohm differential pairs instead of 100 Ohm DC10 is reserved for Dini Group use and should not be used for a custom daughter card without the cooperation of Dini Group 4 2 3 DN7000K10PCI Banks BO and B1 must be set to the same VCCIO voltage These two nets are connected on the host 4 2 4 DNMEG S2GX Note that only DC_TOP P4 is a daughter card header that complies with this specification P5 is the receptacle for a host board 4 2 5 DN9000K10 On headers DC4 and DC9 VCCO is shared between some banks See the User Manual for a complete description of this deviation 4 3 Standard Daughter cards The Dini Group has some general purpose daughter cards available See the Dini Group website for more information Daughter Card Specification www dinigroup com 17 DAUGHTERCARD SPECIFICATION 4 3 1 DNMEG_OBS400 The breakout daughter card provides 48 sign
5. CC1 corresponds to bank B1 VCC2 corresponds to bank B2 Daughter Card Specification www dinigroup com 11 DAUGHTERCARD SPECIFICATION ABCODEFGH J K Bo L6N B0 B0 60 L10P L27P L27N BO L10N 9 Bo Bo B0 B0 B0 L13P L14P L28P L28N L15P 1 0 BO 80 60 LISN L14N L15N L16N 1 1 60 Bo Bo B0 BO L18P L29P L29N L19P 1 2 Bo B0 B0 Bo LI7N L18N L19N L20N B0 B0 BO Bo L22P L30P L30N L23P 1 4 60 60 80 Bo L21N L22N L23N L24N Bo Bo BO B1 L26P L31P L31N LIP 4 6 Bo 60 B1 B1 L25N L26N LIN 1 7 B1 B1 B1 L4P L27P L27N L3N LAN LSN 1 9 B1 B1 B1 B1 L8P L28P L28N L9P 20 B1 81 L8N LON 21 B1 B1 B1 B1 L12P L29P L29N L13P 22 B1 B1 L12N L13N 23 B1 B1 B1 B1 B1 L15P L16P L30P L30N Li7P 24 B1 B1 B1 LISN LI6N LI7N 25 B1 B1 B1 B1 L19P L20P L31P L31N 26 B1 B1 B1 L19N L20N L21N B1 B2 B2 B1 L24P L25P L25N L25P 28 B1 B1 B1 L23N L24N AN OAR WN BO LIN lt Oo w w a B1 L25N L26N B2 B2 B2 B2 L2P L26P L26N L3P 2 2 B B2 L3N L4N 30 E 31 32 A A 33 B2 B2 B2 B2 L10P L28P L28N LI1P 2 B L10N L11N 35 B2 B2 B2 B2 B2 L14P L29P L29N L15P 36 62 B2 B2 LISN L14N L15N L16N 37 B2 B2 B2 B2 L30P L30N L19P 2 B L18N L19N B2 B2 B2 L31P L31N L23P B2 B2 Ww CD Oo Daughter Card Specification Clock outputs J 10 clock P Ground www dinigroup com DAUGHTERCARD SPECIFICATION 2 4 VCCO bias generation Since a daughter ca
6. GA side down or on its side to allow physical access to the daughter card and the controls of the DN8000K10 With this host plate daughter card arrangement there is a limited Z dimension clearance for backside components on the daughter card This dimension is determined by the daughter card designer s part selection for the MegArray receptacle 3 1 2 Insertion and removal Due to the small dimensions of the very high speed MegArray connector system the pins on the plug and receptacle of the Meg Array connectors are very delicate When plugging in a daughter card make sure to align the daughter card first before pressing on the connector Be absolutely certain that both the small and the large keys at the narrow ends of the Meg Array line up BEFORE applying pressure to mate the connectors Daughter Card Specification www dinigroup com 15 DAUGHTERCARD SPECIFICATION Place it down flat then press down gently z rr Sie The following two excerpts are taken from the FCI application guide for the Meg Array series of connectors A part can be started from either end Locate and match the connector s A1 position marking for both the Plug and Receptacle Markings are located on the long side of the housing Rough alignment is required prior to connector mating as misalignment of gt 0 8mm could damage connector contacts Rough alignment of the connector is achieved through matching the Small alignment slot of the pl
7. O_GCAP 104 P12V 2 DCO_GCAN 104 DCO_GCBP 104 DCO_GCBN 104 P5V_1 P5V_2 1A PER PIN P3 3V_1 DCO_GCCP 85 P3 3V_2 DCO_GCCN 85 P3 3V_3 000 6867 60 RSTn RSTn Section 1 of 5 Clock Power Reset 74LVC 1G 07 SOT95P280 5N MEG Array 300 Pin The RSTn signal to the daughter card is an open drain buffered copy of the SYS_RSTn signal This signal causes the entire DN8000K10 to reset losing all FPGA configuration data and resetting the configuration circuitry 2 3 Pin out The following lists are the pin assignments to the MEG Array connector The pins are labeled as in the FCI connector part drawing 2 3 1 Clock and Reset Signals Daughter Card Specification www dinigroup com 5 DAUGHTERCARD SPECIFICATION 2 3 2 Power Signals 2 3 4 Bank BO IO Pins shaded yellow are CC pins A3 DCCOP1 N22 B4 DCCON1 N23 C3 DCCOP2 H29 D4 DCCON2 H30 H3 DCCOP3 N27 G4 DCCON3 P27 K3 DCCOP4 K32 J4 DCCON4 K33 A5 DCCOP5 M25 Daughter Card Specification www dinigroup com DAUGHTERCARD SPECIFICATION DCCON5_VR M26 DCCOP6 J27 DCCON6 K27 DCCOP7 G32 DCCON7 G33 DCCOP8 M30 DCCON8_VR M31 DCCOP9 H32 DCCONS_VR J32 DCCOP10 C32 DCCON10 D32 DCCOP26 J34 DCCON26 K34 DCCOP11 K28 DCCON11 K29 DCCOP12 N25 DCCON12_VR P26 DCCOP13_C D34 DCCON13_C E34 DCCOP14 H27 DCCON14 H28 DCCOP27 N29 DCCON27 N30 DCCOP15 F33 DCCON15 F34 DCCOP16_C R22 DCCON16_C R23 DCCOP17_C L30 DCCON17_C L31 DCCOP18
8. Some of the signals connected to the daughter card expansion headers are clock capable the inputs on the host FPGA can be used for source synchronous clocking On Virtex 4 devices these pins have CC in the name The CC pins on each bank are suitable for IO source synchronous clocking for all signals on that bank A CC clock can only be used to clock signals on the bank associated with it If source synchronous clocking is not required these signals can be used as User IO On Virtex 4 DN8000K10 series the host cannot drive LVDS signals on these pins due to a hardware constraint 2 2 4 VREF Pins declared as VREF pins by Xilinx have a defined placement on the daughter card pin out to allow the daughter card to define a logic threshold as required by some standards If you want to use a standard with a VREF SSTL15 SSTL15 SSTL18 HSTL15 HSTL18 HSLVCMOS833 the daughter card should supply this reference voltage on these pins For optimal performance capacitors should be installed on the host board on these signals near the host s FPGAs Space provisions for these capacitors have been provided If VREF is not required by the intended signaling standard then these signals can be used as User IO without restriction 2 2 5 Power The 3 3V 5 0V and 12V power rails are supplied to the Daughter card headers Each pin on the MegArray connector is rated to tolerate 1A of current without thermal overload Most
9. The Dini Group LOGIC Emulation Source Dauehtercard Interface Description DAUGHTERCARD SPECIFICATION 1 Dini Group Meg Array Daughter card Interface This file describes the Dini Group s standard daughter card interface The interface provides 186 signals from a host board to a daughter card These signals are high speed flexible and differentially capable The daughter card interface is built around a 400 pin FCI MegArray connector This BGA array of pins is designed for high speed high density board to board connections The Plug of the system is located on the host and the receptacle is located on the expansion board This selection was made to give a greater height selection to the daughter card designer The user typically designs his own daughter card with interfaces required for the emulation project The Dini Group is happy to review daughter card designs intended for interface to a Dini Group host for possible compatibility problems A daughter card designer should use the schematic of the host board provided with the board to verify his design 1 1 Banking System To allow flexibility to the daughter card designer the daughter card interface is divided into three Banks Each bank can have it s own VCCO power VREF threshold voltage and source synchronous IO clocking Each bank contains 62 user IO signals can be used as 31 differential pairs Eight of these signals can be used as a so
10. als on Mictor connector 124 signals on 1 pitch headers arranged for differential signaling 14 differential coax cable connection intended for use with the DN8000K10 tocketIO headers and global clock inputs Oscillator Buffer LVPECL input LVDS Connector utput RocketlO QSE Ribbon cables 606 LVDS able 22 Selection y via Jumpers Mictor Mictor GCA GCB MGTCLK sa sma aua Bank 0 FPGA generated Output Banks 1 2 MEG Array 300 or 400 pin 4 3 2 DNMEG_OBS300 The DNMEG_OBS300 is identical to the DNMEG_OBS400 except that the receptacle is a 300 pin instead of a 400 pin connector This can only be used with DCO DC1 DC2 DC3 DC4 DC9 on the DN8000K10 4 3 3 DNMEG S2GX This board provides a Stratix 2 GX FPGA capable of 6 5Gbs serial data transmission And some memory options The DNMEG_S2GX also has a daughter card header configured as a pass through from it s own daughter card receptacle 4 3 4 DNMEG_ADC coming soon This board provides a high speed ADC and DAC 1Gb Ethernet Virtex 4 SX55 FGPA and Memoty options 4 3 5 DNMEG_ DVI coming soon This board provides dual DVI D input and output and memory options 4 3 6 DNMEG_ARM coming soon Arm processor Daughter Card Specification www dinigroup com 18 DAUGHTERCARD SPECIFICATION 4 3 7 DNMEG_PROTO coming soon Prototype area Daughter Card Specification www dinigroup com 19
11. his differential clock is buffered and distributed to every FPGA on the host This clock may be de skewed on the host through a zeto delay buffer If this is the case DN7000K10PCI DN8000K10 DN9000K10PCI there may be special frequency requirements or settings for the buffers to work See the user manual for the specific board for these requirements This clock network may also be multi purpose so a setting may have to be used to enable this clock distribution 2 2 2 UserlO User IO signals connect directly to a general purpose IO site on the host FPGA These signals can be used as any drive standard supported by the host FPGA Each bank must share VCCIO and VREF requirements For example if bank BO is supplied 1 8V by the daughter card on Daughter Card Specification www dinigroup com 3 DAUGHTERCARD SPECIFICATION ALL of the VCCIO_BO pins and supplies 0 9V to ALL of the VREF_BO pins then the daughter card may use each of the user IO pins as 1 8V SSTL inputs or outputs LVDS outputs 1 8V LVCMOS inputs or outputs since all of these signal standards requirements are met User IO signals can be used single endedly or differentially Differential pairs are pre selected Each set of signals whose signal names differ only by a p or n in the signal name can be used as differential pairs For example the signals 12 1 46 and B2_L4n can be used as a differential pair These two signals are matched in length 2 2 3 10 Clock
12. of the power available to daughter cards through the connector comes from the two 12V pins for a total of 24W The host provides a fuse on each of these rails 2 2 6 10 Power The signaling standard of the daughter card is left undefined by the host For a standard to be used the daughter card should supply power to the VCCIO pins of the daughter card connector The pins are connected directly to the VCCIO power pin on the host FPGA Each of the three banks on the daughter card has two VCCIO pins Each of the three banks can have its VCCIO set independently but both pins on a bank must be the same voltage The daughter card should be able to supply enough current to the host FPGA to power the entire bus The daughter card designer will need to calculate the host FPGA s current requirements Daughter Card Specification www dinigroup com 4 DAUGHTERCARD SPECIFICATION When the daughter card does not supply a voltage the host the host will power these pins at 1 2V with a minimal current capacity The daughter card can overdrive this voltage safely 2 2 7 Reset The reset signal Active low is an open drain buffered copy of the reset signal on the host This signal is asserted when the host power is not within tolerance The signal must be pulled up on the daughter card with a resistor When the reset signal is active the FPGAs on the host will not be configured 33V 30V 12 0V 2 2 g 7 6 F5 7A 5A 5A P100 1 Pivi DC
13. rd will not always be present on a daughter card connector a VCCO bias generator is used on the motherboard for each daughter card bank to keep the VCCO pin on the FPGA within its recommended operating range The VCCO bias generators supply 1 2V to the VCCO pins on the FPGAs and are back biased by the daughter card when it drives the VCCO rails The VCCO voltage impressed by the daughter card should be less than 3 75 to prevent destruction of the Virtex 4 IOs connected to that daughter card IN OUT lt 000 60 1000 SHDN 380mA MAX AT 1 22V R452 0 Vadj 1 22V LT1763CS8 SOIC 127P600 8N 380mA MAX AT 1 22V 3 Daughter card Mechanical Daughter card expansion headers are located on the bottom side of the PWB This is done to eliminate the need for resolving board to board clearance issues assuming the daughter card uses no large components on the backside Comonent top Side Solder bottom Side MegArray Receptacle MegArray Plug 7 65mm Solder bottom Side ee Comonent top GN SIG Sn Daughter Card Specification www dinigroup com 13 DAUGHTERCARD SPECIFICATION Each host with a daughter card interface makes certain minimal provisions for daughter cards Enough space is reserved for each daughter card plug to accommodate the following hypothetical daughter card The DNMEG_OBS400 conforms to these dimensions Note that the component
14. s on the topside of the daughter card and DN8000K10 face in opposite directions View Top Side 400 Pin Receptacle on Back P N 74390 101 5 000 ine gt 1 950 1 0 500 7 At least four mounting positions are provided for each header in a standard location as shown above Boards that have multiple daughter card connectors next to each other horizontally use a standard spacing of 78 25mm 3 08in from pin A1 to pin A1 and aligned vertically The connectors used in the expansion system on the host are FCI MEG Array 400 pin plug 6mm part 84520 102 A suitable mating connector for use on a daughter card would be FCI Daughter Card Specification www dinigroup com 14 DAUGHTERCARD SPECIFICATION part 74390 101 lead free 74390 101LF This provides the minimum board to board spacing Other spacings are possible with different connectors on the daughter card 3 1 1 Daughter card mounting DN8000K10 The DN8000K10 features a standard metal base plate that gives the board mechanical stability and provides plenty of mounting points for daughter cards The daughter card receptacle on the daughter card itself will also be mounted on the backside of the board Daughter Card AN rere Aay Mated Height Shield i 14mm ep eR Motherboard The daughter card should use standoffs to secure itself to the backside of the base plate The standard chassis that comes with the DN8000K10 will allow it to operate FP
15. ug housing with the Small alignment key of the receptacle housing and the Large alignment slot with the Large alignment key Both connector housings have generous lead in around the perimeter and will allow the user to blind mate assemble the connectors Align the two connectors by feel and when the receptacle keys start into the plug slots push down on one end and then move force forward until the receptacle cover flange bottoms on the front face of the plug Dec 09 2004 Like mating a connector pair can be unmated by pulling them straight apart However it requires less effort to un mate if the force is originated from one of the slot key ends of the assembly Reverse procedure from mating Mating or un mating of the connector by rolling in a direction perpendicular to alignment slots keys may cause damage to the terminal contacts and is not recommended 4 Dini Group products 4 1 Board List The following boards comply with this document s header specifications Daughter Card Specification www dinigroup com 16 DAUGHTERCARD SPECIFICATION DN7000K10PCI 3 Headers DN8000K10 11 Headers 7 are non standard DN8000K10PSX 1 Header DNMEG_S82GX 1 Header Coming Soon DN9000K10PCI 3 Headers DNMEG_ADC 1 Header 4 2 Exceptions The following products have headers that do not fully comply with these specification A list of exceptions to this specification follows with a description of the deviation 4 2 1 DN8000K10PSX GCCP GCCN is not
16. urce synchronous clock into the host FPGA Four of these signals can be used as a reference voltage to the host fpga for standards requiring a reference voltage The banks are named BO B1 and B2 and every user IO on the header interface corresponds to one of these banks The signals name given to each user IO pin contains either BO B1 or B2 in the name Other connections on the daughter card connector system not correlated to a bank include three dedicated differential clock connections for inputting global clocks from an external source power connections bank VCCO power a buffered power on reset signal 1 2 Non Compliant Boards See section 4 2 of this guide for deviations from this specification 2 Daughter Card Electrical The daughter card pin out and routing were designed to allow use of the Virtex 4 s 1 Gbps general purpose IO The connector itself is capable of as high as 10Gbs transmission rates using differential signaling All signals on the host are all routed as differential 50 Ohm transmission lines with means to properly terminate All signals are routed against a ground plane so for the best signal integrity should be routed against a ground plane on the daughter card with excellent Daughter Card Specification www dinigroup com 2 DAUGHTERCARD SPECIFICATION IO voltage bypassing close to the terminus When signals are used differentially the trace impedance is 100 ohms Signals on the host
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