PCIe to UART Bridge
Contents
1. 1 3 Features PCIe Interface O O O O O OO O The Xilinx endpoint cores for PCIe follows PCI express base specification v1 1 layering model 32 bit internal data path The endpoint core implements the physical layer datalink layer transaction layer amp configuration management layer Six individually programmable BAR s amp expansion ROM BAR Supports MSI amp INTX emulation Supports removal of corrupt packets for error detection and recovery Compatible with PCI PCI Express power management functions Used in conjunction with NXP PX1011A PCI Express standalone PHY to achieve high transceiver capability 2 5 GBPS line speed automatic clock and data recovery 8b 10b encode and decode Supports a maximum transaction payload of up to 512 bytes UART Controller Interface O O OO The UART bridge uses IO mapped interface Full duplex asynchronous communication Baud rate of 115200 with a single odd parity stop amp start bit Supports transmit amp receive FIFO of size 16 byte depth iWave Systems Technologies Pvt Ltd Page 4 of 15 3 IWave User Manual for PCIe to UART Controller Embedding Intelligence R 2 0 1 4 Evaluation Board and Core requirements O O O Spartan 3 PCI Express Kit Mother Board with PCle slot with PCle tree software installed PC laptop with an available COM port 9 pin RS 232 Serial cable Endpoint core for PCI express from xilinx PCIe to UART controller core iWave Systems Technolo2. 3 0 0 Locate the Spartan 3 PCI Express board in the PCI bus list once you locate the device PCItree software will displays bus number device number function number Vendor ID PCI ISA Bridge Device WID x1lOEE Xilimx Corp DID xOOO7 no device name found no SubVID x1lOEE Xilinx SubID xOOO7 no name rew x00 edit ConfReg hex xFF lt INTA 16 64 Nr of ComfRegs use BIOS int refresh dump Write ConfReg TI refr after wr Config Space Dump DID VID Stat Cmd BaseClass SubClass type 1 xz BAR BAR BAR BAR io mem 3zbit PO n nr i n n E BIST Header LatTimer Select the BAR register now UART bridge is mapped to BAR 0 IO bar at address location 00000010h locate the BAR 0 register to test the UART bridge functionality Double click on the BAR 0 register position to access the IO register mapped to BAR 0 EDI PCI ISAR Bridge Device VID xl1O0EE Xilinx Corp DID xOOO7 no device name found no SubVID xlO0EE Xilinx SubID xOOO7 no name rew x00 redit ConftReg xO0003001 hex xFF lt INTA 16 64 Nr of ComftRegs use BIOS int Write ConfRec Eol I refr after wr refresh dump Config Space Dump itype l xz i amp e so o o 5 52 Subtractive gt PCI PCI Bridge Device 8086 244e int 5 04 0 5 05 0 0 31 0 0 31 1 O 31 3 VGA PC Compati
3. 9 IWave User Manual for PCIe to UART Controller Embedding Intelligence R 2 0 User Manual for PCIe to UART Controller iWave Systems Technologies Pvt Ltd Page 1 of 15 3 IWave User Manual for PCIe to UART Controller Embedding Intelligence R 2 0 Table of Contents 1 INTRODUCTION 4 1 1 PURPOSE 4 1 2 SCOPE 4 1 3 FEATURES 4 1 4 EVALUATION BOARD AND CORE REQUIREMENTS 5 2 PCIE TO UART CONTROLLER CORE 6 2 1 BLOCK DIAGRAM 6 2 2 DESCRIPTION 6 2 3 PIN OUTS OF PCIE TO UART CONTROLLER CORE 7 3 QUICK START 9 3 1 CONNECTING TO A HOST COMPUTER 9 3 1 1 Installation Requirements 9 3 1 2 Board Installation amp Testing 9 3 2 PROCEDURE FOR DEMO 10 APPENDIX A 15 iWave Systems Technologies Pvt Ltd Page 2 of 15 3 IWave User Manual for PCIe to UART Controller Embedding Intelligence R 2 0 List of Figures Figure 1 Detailed view of 1W PCle to UART Controller core 6 List of Tables Table 1 Pin outs of 1W PCle UART Bridge eere n nsnsi 7 iWave Systems Technologies Pvt Ltd Page 3 of 15 3 IWave User Manual for PCIe to UART Controller Embedding Intelligence R 2 0 1 Introduction 1 1 Purpose The purpose of this document is to explain the procedure to power on and setting up working environment of the PCIe to UART controller for demo purpose 1 2 Scope This document describes the Hardware connection procedure to power on and establishes Serial communication with PC
4. Ethernet Netwe PCI ISAR Bridge De Mass Storage Cc SMBus o Serial Bus iWave Systems Technologies Pvt Ltd 0000 lt 08 BaseClass SubClass EF BIsT Header LatTimer 3001 mem 3Zbit Page 12 of 15 9 Wave Embedding Intelligence User Manual for PCIe to UART Controller R 2 0 Open the hyper terminal on the PC laptop locate the IO address location 00000010h to write amp read the buffer registers of UART in the PCItree window in the edit memory tab enter some ascii value of data then press enter the data as to come in the hyper terminal We can observe digit 2 on the hyper terminal 32000000 32000000 32000000 32000000 32000000 32000000 32000000 32000000 32000000 32000000 32000000 32000000 32000000 32000000 32000000 32000000 32000000 32000000 32000000 32000000 32000000 32000000 32000000 32000000 32000000 32000000 32000000 32000000 32000000 32000000 32000000 lt x00000000 x00000004 x00000008 lt x0000000C lt x00000010 x00000014 x00000018 x0000001C x00000020 x00000024 x00000028 x0000002C x00000030 x00000034 x00000038 x0000003C x00000040 x00000044 x00000048 lt x0000004C x00000050 x00000054 x00000058 x0000005C x00000060 x00000064 x00000068 x0000006C x00000070 x00000074 x00000078 x0000007C v iWave Systems Technologies Pvt Ltd Page 13 of 15 9 Wave Embedding Intelligence
5. User Manual for PCIe to UART Controller R 2 0 To check the receiver path enter some data on the hyper terminal window amp try to read it back from the host cpu by selecting auto read memory also locate the IO address location 00000010h amp then press refr view tab to read the received data We can observe the data entered in the hyper terminal to reflect on the 00000010h register contents 35000000 35000000 35000000 36000000 36000000 36000000 36000000 36000000 36000000 36000000 36000000 36000000 36000000 36000000 36000000 36000000 36000000 36000000 36000000 36000000 36000000 36000000 36000000 36000000 36000000 36000000 36000000 36000000 36000000 36000000 lt x00000000 lt x00000004 lt x00000008 lt x0000000C lt x00000010 lt x00000014 lt x00000018 lt x0000001C lt x00000020 lt x00000024 lt x00000028 lt x0000002C lt x00000030 lt x00000034 lt x00000038 lt x0000003C lt x00000040 lt x00000044 lt x00000048 lt x0000004C lt x00000050 lt x00000054 x 0000058 lt x0000005C lt x00000060 lt x00000064 lt x00000068 lt x0000006C lt x00000070 lt x00000074 lt x00000078 lt x0000007C v x36000000 iWave Systems Technologies Pvt Ltd Page 14 of 15 3 IWave User Manual for PCIe to UART Controller Embedding Intelligence R 2 0 APPENDIX A Reference Documents PClItree software usage from http www pcitree de userguide html Spartan 3 for PCI Expres
6. e R 2 0 e Start the PCItree software installed in the host computer to which Spartan 3 PCI Express board is connected then Press OK please register this program is distributed as shareware please register mailto info pcitree de http www pcitree de http www shareit com programs 103142 htm e The software will scan all the PCI bus attached to the host computer amp displays all the PCI bus as the tree structure Each PCI component has an integer number for bus device and function bdf pdirect select 7 show INT routing highest bus dev Ed busnr zd o show Mem Map 5 i Lr 0 0 0 El host CPU Host PCI Bridge Device i 9 00 0 Host PCI Bridge I VID x8086 Intel Corporation E o 28 0 O gt 1 2 PCI PCI Br DID x2778 no device name found no 1 00 l gt 2 2 PCI PCI SubVID x8086 Intel 0 28 4 O gt 3 3 PCI PCI Br SubID x348D no name 3 PCI ISA Bridge rev x00 no INT 0 28 0 4 4 PCI PCI Br _eqit ConfReg Nr of ConfRegs Ethernet Netuc hex 16 C 64 16550 Compatibl o serial bus L use BIOS int Universal Host Cor Write ConfReg rufrash Universal Host Cor dump Universal Host Cor D refr after wr Universal Host Coy Config Space Dump type 1 xs DID VID o serial bus Dev O gt 5 5 Subt ti re ag d Stat Cmd KOGAZ RD Posest BaseClass SubClass I Ethernet Netwc BIST Header LatTimer PCI ISA Br
7. gies Pvt Ltd Page 5 of 15 3 IWave User Manual for PCIe to UART Controller Embedding Intelligence R 2 0 2 PCIe to UART Controller Core 2 4 Block Diagram User PCI Express PCI Express UART Transaction Transaction PHY Interface c Interface PIO Interface En dp oint Interface Module Interface Xilinx Core Figure 1 Detailed view of iW PCIe to UART Controller core 2 2 Description The PCle Bridge has an endpoint PIPE v1 7 PHY Interface for PCIe 1 lane core from Xilinx Programmed I O module amp UART controller The endpoint core from xilinx implements the physical layer PHY interface data link layer transaction layer amp configuration management layer of PCIe base specification v1 1 layering model The PIO design interfaces with the endpoint for PCI Express core s transaction interface amp responds with read write transaction for memory or IO transaction from the endpoint core The UART controller is implemented in user interface side of the PIO design The serial controller Unit supports for asynchronous communication only The processor can access the unit through I O read and write commands The SCU converts parallel data from the host processor to serial data and transmits it and converts the serial received data into parallel data for the host processor to read The start bit parity bit and the stop bits are automatically added in the transmit direction and is stripped in the receive directi
8. idge De BAR O o Mass Storage Cc BAR 1 SMBus Serial Bus BAR 2 3 4 5 BAR BAR Fan iWave Systems Technologies Pvt Ltd Page 11 of 15 Wave Embedding Intelligence User Manual for PCIe to UART Controller device ID amp configuration space contents in the right side of the pcitree window p direct select bus dex ades EE host CPU o o00 0 Host PCI o 28 0 O gt 1 tZ 1 00 0 1 2 tz Oo 229 4 O 3 35 O gt lt 4 4 o Universal Universal Universal Universal o serial o gt S 52 VGA PCI ISA Da SMBus PciTree direct select bus dev Lc jo Bridge I PCI PCI Br PCIZ PCILI PCIZPCI Bri PCTZPCI Ethernet Netuc 16550 Compatibl serial bus L Host Host Host Host Cor Cor Cor Cor bus Dev Subtractive PC Compati Ethernet Netwe Bridge De Mass Storage Cc Serial Bus GE host CPU o 00 0 Q s 1 00 0 0 28 4 3 00 0 0 28 5 4 00 0 4 00 3 4 00 4 0 29 0 0 29 1 o 29 2 Oo 29 3 0 29 7 o gt 1 o gt s o gt 4 Host PCI Bridge I tZ PCI PCI Bri A m 2 PCI PCI 32 PCI PCI Bri PCI ISA Bridge tea PCI PCI Bri Ethernet Netuc 16550 Compatibl serial bus L Host Host Host Host o Universal Cor Universal Cor Universal Cor Universal Cor o serial bus Devi show INT routing highest busnr show Mem Map i 3 0 0 show INT routing highest busnr show Mem Map 5 r
9. mputer to test the functionality of iW PCle Bridge core 3 1 1 Installation Requirements The items listed below are necessary to install Spartan 3 PCI Express to the host computer o PC laptop with an available COM port o Host computer of windows NT 2000 or windows XP OS having an available PCIe slot with installed PCIe Tree software o RS232 serial cable Board Installation amp Testing Before connecting Spartan 3 PCI Express Kit in the PCIe slot check all these settings are properly done for starter kit o Select the master parallel mode for FPGA configuration by installing M2 in JP3 Header o Other Jumpers position on Board JP8 2 3 JP1 2 3 JP2 2 3 JP5 1 2 JP6 2 3 JP9 J4 o Select the power source from the PCIe edge connector for this install the fuse in socket F2 position dont place separate fuse in F1 position o Install the clock source of 24 576 Mhz in the user clock socket U10 for baud clock generation After this settings place the board in PCIe slot of a host computer Connect the RS232 serial cable one end to the DB9 connector P1 on Spartan 3 PCI Express board and the other end to the DB9 connector of a PC laptop which hyper terminal installed set the hyper terminal properties as in the hyper terminal screen shot Program the MCS file pcie uart bridge mcs provided with user manual to the Spartan 3 PCI Express board by connecting Xilinx platform USB cable from PC USB port to for this first prog
10. on iWave Systems Technologies Pvt Ltd Page 6 of 15 3 IWave User Manual for PCIe to UART Controller Embedding Intelligence R 2 0 2 3 Pin outs of PCIe to UART Controller core The pin outs of iW PCIe UART Bridge is as shown in the table below Table 1 Pin outs of iW PCIe UART Bridge iW PCle UART Bridge FPGA PINS PINS powerdown 0 AF22 powerdown 1 AD23 resetn AF24 rxpolarity AE24 txclk AE21 txcompliance AE23 txdata 0 ADIS5 txdata 1 AE15 txdata 2 AF15 txdata 3 AE19 txdata 4 AF19 txdata 5 AE20 txdata 6 AF20 txdata 7 AD21 txdatak 0 AE22 txdetectrx loopback AF21 txelecidle AF23 phystatus AF12 rxdata 0 AE8 amp rxdata 1 AC7 rxdata 2 AF6 iWave Systems Technologies Pvt Ltd Page 7 of 15 3 IWave User Manual for PCIe to UART Controller Embedding Intelligence R 2 0 iW PCle UART Bridge FPGA PINS PINS rxdata 3 AE6 rxdata 4 AD6 rxdata 5 AC6 rxdata 6 AES rxdata 7 ADS5 rxdatak 0 AF8 rxelecidle AF4 rxstatus 1 AD10 rxstatus 2 ACII rxvalid AD12 rxclk AE13 Sys reset n AEA txd o ABII rxd i AAI1 baud_clk_i B14 iWave Systems Technologies Pvt Ltd Page 8 of 15 3 IWave User Manual for PCIe to UART Controller Embedding Intelligence R 2 0 3 Quick Start 3 1 Connecting to a Host computer Follow the steps below to connect the Spartan 3 PCI Express to the host co
11. ram the on board 8 Mb xilinx XCFO8P parallel Platform Flash PROM then configure the FPGA from the image stored in the Platform flash PROM by power cycling switch off amp on the board Run the PCItree software on the host computer where the Spartan 3 PCI Express board is installed Check the software overview part to get more information regarding Pcitree software for read amp write of memory amp io space of host computer iWave Systems Technologies Pvt Ltd Page 9 of 15 e IWave User Manual for PCIe to UART Controller Embedding Intelligence R 2 0 3 20 Procedure for demo e Connect Spartan 3 PCI Express board to the PCIe slot of host computer also connect the RS232 serial cable to the board amp the serial port of a computer laptop e Open the HyperTerminal on PC Laptop with following settings o Baud rate 115200 bps o Data bits 8 o Parity odd o Stop bits 1 o Flow control none then press OK COM1 Properties ff ascd7 Properties Port Settings Connect tTo l Settings B ascd Change Icon Bite per second Country region z Data bits Enter the area code without the long distance prefix Parity Area code Phone number Stop bits Connect using COM1 Flow control None z Configure Restore Defaults rR OK Cancel iWave Systems Technologies Pvt Ltd Page 10 of 15 9 IWave User Manual for PCIe to UART Controller Embedding Intelligenc
12. s starter kit board user guide UG256 http www xilinx com support documentation boards and kits ug256 pdf iWave Systems Technologies Pvt Ltd Page 15 of 15
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