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221012310 Series User`s Manual

1. 1 12 CHAPTER 2 BOARD INSTALLATION NR 2 1 Board OSA 2 3 External I O Connections 02222 1 440 100 aaa 2 3 Connecting the Analog Input Pins escssssssssssssessssecseseevesssssssssssssssvsvsssssssgeasecseaeseeuesaransssecesscessssaesevasesacs 2 4 Connecting the Trigger In and Trigger Out Pins Cascading 0 010000000 2 5 Connecting the Analog Outputs ADA Boards Onlly cscssssssssssssssesessessssssescsssvssanssvsvessersesesssseasassaescansesens 2 6 Connecting the Timer Counters and Digital VO eerte rettet ertet 2 6 Running the 2210DIAG Diagnostics Program scsssssssessesssesssssssscsscsccesesssssssecsescarsssecesecscesacesasasasssecseecenscsess 2 6 CHAPTER 3 HARDWARE DESCRIPTION T 3 1 A D Conversi n Circ ltry A caida 3 3 Analog OPUS ada 3 3 AID OA A ici 3 3 Data TOA ad ren 3 4 D A Converters ADA Boards 2 4 2 2 1 01 010025 8 12000 3 4 Timet COUnIGts nenne 3 4 Digital I O Programmable Peripheral Interface eerte treten 3 5 CHAPTER 4 BOARD OPERATION AND PROGRAMMING
2. eee netten 1 3 8254 Timer Counter Sources Jumpers 3 1 4 8254 Timer Counter Circuit Diagram 0 4 4 4 1 5 Interrupt Channel Jumper P4 ica engine anne 1 6 Pulling Down the Interrupt Request Line 1 6 DMA Request amp DMA Acknowledge Channel Jumpers 5 000 1 6 DAC 1 Output Voltage Range Jumper P6 1 7 DAC 2 Output Voltage Range Jumper 7 1 8 Analog Input Voltage Range and Polarity Jumper P8 eese eene 1 8 A D Word Bit State Set Jumper PQ es seessessssstccssesserseersecsstsecsesesceneseceucesssesereseasseseaticsesseenceseessaes 1 8 Single Ended Differential Analog Input Signal Type Jumpers P10 essere 1 9 Base Address Switch ST Einnehmen seite 1 9 Pull up Pull down Resistor Circuitry eese esses eeseee seen 1 11 Adding Pull ups and Pull downs to Digital VO 2 4020020000 0100 ennemi 1 12 Gain Circuitry and Formulas for Calculating Gm and f 0 ccsssssssessssssssesescorsssecscsescousesccessessessansnssees 1 13 Diagram for Removal of Solder Short sse 1 14 P2 VO Connector Pin Assignments 444 0 tt tente tta se then 2 3 Single Ended Input Connection
3. 4 Defining the VO 4 3 0 Read Status Start Convert Read Write 4 4 4 4 BA 1 Read A D Data Update DAC Outputs Read Write 4 4 BA 2 Reset Write Only 2 2 4 5 3 Scan Burst Read Write cccsicsecscsscseecscsccsesscscsenerssssoncsosesosveservesesccesosensnsesoueansssuecocoseussesneneesracsonesesae 4 5 BA 4 PPI Port A Digital YO Read Write 4 4 5 5 PPI Port B Channel Gain Board Functions Select Read Write 244 2 2 4 5 BA 6 PPI Port C Digital VO Read Write 4 6 7 8255 PPI Control Word Write 8 4 6 BA 8 8254 Timer Counter 0 Read Write ccsccccssccsssessscccesecesseccesnceesccccsaesesssteceseseeeseeesseceeesersceseeses 4 8 BA 9 8254 Timer Counter 1 Read Write cccccccccscscsscssccessecsscsscencsecssessscessessneesesecsecesstessetesesscnsceesenenses 4 8 BA 10 8254 Timer Counter 2 Read Write ccccccsscsssesssessccssccsssesssensecssecsneeseeseseeascessnecsesecececssseeseeeenee 4 8 BA 11 8254 Control Word Write Only cccsssccesesesesesscerceccnsessecssccseensensesescescenccesseessaseeesneatencenseeneets 4 8 BA 12
4. B 3 4 APPENDIX A q _ COMPONENT DATA SHEETS C 1 Intel 82C54 Programmable Interval Timer Data Sheet Reprint intel 82 54 CHMOS PROGRAMMABLE INTERVAL m Compatible with all intel and most m Three independent 16 bit counters other microprocessors 8 Low Power CHMOS m High Speed Zero Wait State 10 mA 8 MHz Count Operation with 8 MHz 8086 88 and frequency 80186 188 Completely TTL Compatible Six Programmable Counter Modes m Avallable in EXPRESS Binary or BCD counting Standard Temperature Range Status Read Back Command Extended Temperature Range Available 24 DIP and 28 Pin PLCC The Intel 82C54 is a high performance CHMOS version of the industry standard 8254 counter timer which is designed to solve the timing control problems common in microcomputer system design It provides three independent 16 bit counters each capable of handling clock inputs up to 10 MHz All modes are software programmable The 82C54 is pin compatible with the HMOS 8254 and is a superset of the 8253 m Handles Inputs from DC to 8 MHz 10 MHz for 82C54 2 Six programmable timer modes allow the 82C54 to be used as an event counter elapsed time indicator programmable one shot and in many other applications The 82054 is fabricated on Intel s advanced CHMOS III technology which provides low power consumption with performance equal to or gre
5. 2210 2310 Characteristics Typical 25 Interface Switch selectable base address mapped software selectable interrupts Jumper selectable DMA channel Analog Input 8 differential or 16 single ended inputs Input impedance each channel sess gt 10 megohms Gains software selectable 1 2 4 amp 8 plus Gm gain multiplier E ges esee Ue vagi Nude 05 typ 0 25 max Inp t ranges AAA 5 10 or 0 to 10 volts Guaranteed linearity across input ranges 5 9 5 and O to 9 5 volts Overvoltage protection oo eesessssssssssssscscsessssesseresescsscssssesssseeensesescesencassneas 35 Common mode input voltage 10 volts max Settling time gain 1 0 80 5 usec max A D Converter S AD678 TP ata Successive approximation Resolution oononconoconoronncconeneenicacononoonoconononos 12 bits 2 44 10V 4 88 20V A 1 bit typ Conversion Speed sasari eaen ekle raras 5 usec typ Thro ghpUt 5 eerte deceat oni Peel ee 125 kHz Pacer Clock Range using on board 8 MHz 9 minutes to 5 usec Digital VO DE S TT pK CMOS 82C55 SAA ree eerte rea la a PN 16 Logic c
6. PAP 77 CONTROL 231256 5 Figure 5 Basic Mode Definitions and Bus Interface CONTROL WORD GROUP PORT C LOWER 1 INPUT 0 OUTPUT PORT 1 INPUT 0 OUTPUT MODE SELECTION MODE 0 PORT C UPPER Ye INPUT 0 OUTPUT MODE SELECTION 00 MODE 0 01 MODE 1 1X MODE 2 MODE SET FLAG 1 ACTIVE 231256 6 Figure 6 Mode Definition Format The mode definitions and possible mode combina tions may seem confusing at first but after a cursory review of the complete device operation a simple logical I O approach will surface The design of the 82C55A has taken into account things such as effi cient PC board layout control signal definition vs PC layout and complete functional flexibility to support almost any peripheral device with no external logic Such design represents the maximum use of the available pins Single Bit Set Reset Feature Any of the eight bits of Port C can be Set or Reset using a single OUTput instruction This feature re duces software requirements in Control based appli cations When Port C is being used as status control for Port Aor these bits can be set or reset by using the Bit Set Reset operation just as if they were data output ports 3 128 intel 82C55A Interrupt Control Functions When the 82C55A is programmed to operate mode 1 or mode 2 control signals are provided that can be used as interrupt request inputs to t
7. 2210 2310 Series User s Manual Ung Real Time Devices Inc Accessing the Analog World 2210 2310 Series mem User s Manual 17227 REAL TIME DEVICES INC Post Office Box 906 State College Pennsylvania 16804 USA Phone 814 234 8087 FAX 814 234 5218 Published by Real Time Devices Inc P O Box 906 State College PA 16804 USA Copyright 1993 by Real Time Devices Inc All rights reserved Printed in U S A Rev B 9342 Table of Contents INTRODUCTION o Analog to Digital Conversion i 3 Digital to Analog Conversion ADA Boards Only esie i 3 8254 a et i 3 Digital Exc 1 4 What Comes With Your Board 4 Board Accessories Mm i 4 Application Software and Drivers scsscsssssssssssssssssseseseseseseseeessenesesescseseasseeessecerscaessessacasscstnsacsceaeaensacsasaes i 4 R A 1 4 Using This Mantilla 1 4 When You Need
8. CHAPTER 5 CALIBRATION This chapter tells you how to calibrate the 2210 2310 using the 2210DIAG calibration program included in the example software package and six trimpots on the board These trimpots calibrate the A D converter gain and offset and the D A X2 multiplier output 5 2 This chapter tells you how to calibrate the converter gain and offset and the D A converter X2 multiplier ADA2210 and ADA2310 only All A D and D A ranges are factory calibrated before shipping Any time you suspect inaccurate readings you can check the accuracy of your conversions using the procedure below and make adjustments as necessary Using the 2210DIAG diagnostics program is convenient way to monitor conversions while you calibrate the board Calibration is done with the board installed in your system You can access the trimpots at the edge of the board Power up the system and let the board circuitry stabilize for 15 minutes before you start calibrating Required Equipment The following equipment is required for calibration Precision Voltage Source 10 to 10 volts Digital Voltmeter 5 1 2 digits Small Screwdriver for trimpot adjustment While not required the 2210DIAG diagnostics program included with example software is helpful when performing calibrations Figure 5 1 shows the board layout with the trimpots located along the top edge of the board BASE ADDRESS OO TRI TR2
9. CMOS 82C54 Three 16 bit down counters 2 cascaded 1 independent 6 programmable operating modes Counter input External clock 8 MHz max or on board 8 MHz clock Counter outputs 22 Available externally used as PC interrupts Counter gate source esee External gate or always enabled A 3 Miscellaneous Inputs Outputs bus sourced 5 volts 12 volts ground Current Requirements 2210 140 mA 5 volts 32 mA 12 volts 30 mA 12 volts 2310 225 mA 5 volts Connector 50 pin right angle shrouded box header Size Short slot 3 875 H x 5 25 W 99mm x 134mm A 4 APPENDIX P2 CONNECTOR PIN ASSIGNMENTS P2 Connector DIFF SE AIN1 AIN1 1 2 AN1 AINS AIN2 AiN2 3 2 AIN2 Ato AIN3 AIN3 5 6 AINS Aint AIN4 AINS 7 8 AlNa AIN12 AINS AINS 9 49 AINS AING AING 1202 AING 4 AIN7 302 AIN7 AINTS AIN8 ains 19 19 AiNe AtNt6 AOUT 1 1709 ANALOG GND AOUT 2 ANALOG GND ANALOG GND 22 ANALOG GND PA7 PAG 09 PC6 Pas 7 8 Pcs 4 4 61 G2 PA2 63 2 Par 68 Pct PAO 6268 Pco TRIGGER IN DIGITAL GND EXT GATE 1 8 82 OUT 1 TRIGGER OUT T C OUT 2 EXT GX G EXT GATE 2 12 VOLTS 6268 5 VOLTS 12 VOLTS DIGITAL GND
10. 0 Fig 2 2 Single Ended Input Connections Differential When operating in the differential mode twisted pair cable is recommended to reduce the effects of magnetic coupling at the inputs Your signal source may or may not have a separate ground reference When using the differential mode you should install a 10 kilohm resistor pack at location RN6 on the board to provide a reference to ground for signal sources without a separate ground reference First connect the high side of the analog input to the selected analog input channel AIN1 through AINS and connect the low side of the input to the corresponding AIN pin Then for signal sources with a separate ground reference connect the ground from the signal source to an ANALOG GND pins 18 and 20 22 on P2 Figure 2 3 shows how these connections are made VO CONNECTOR 2 Fig 2 3 Differential Input Connections Connecting the Trigger In and Trigger Out Pins Cascading Boards The board has an external trigger input P2 39 and output P2 43 so that conversions can be started based on external events or so that two or more boards can be cascaded and run synchronously in a master slave configura tion By cascading two or more boards as shown in Figure 2 4 they can be triggered to start an A D conversion at the same time sampling uncertainty is less than 50 nanoseconds When you cascade boards be sure to set each board for a different base address s
11. Fig 4 3 Timing Diagram Multiple Conversions Automatic Channel Scan In this mode the channel sampled is automatically incremented after each conver sion is complete The channel at which the scan starts is specified in the channel select bits of BA 5 The number of channels to be scanned is specified at BA 3 bits DO through D3 Scanning continues until stopped For ex ample by programming channel 3 at BA 5 and four channels at BA 3 the scan will be 3 4 5 6 3 4 5 6 3 until stopped Figure 4 4 shows a diagram of this mode When using channel scan you must set bits D6 and D7 at BA 3 for the scan mode Conversions can be performed through software or using the pacer clock Use automatic channel scan when you want to continuously sample a sequence of channels Since the channel counter is automatically incremented after each conversion this mode is faster and easier than using the single conversion mode and setting the channel for each conversion from software See the SCAN program in BASIC on the example programs disk included with your board 4 14 START CONVERT PACER CLOCK IL TL TL TL TL TL TL SAMPLE TAKEN nono no ECL SAMPLED CHANNEL 2 3 4 5 2 3 4 5 2x Fig 4 4 Timing Diagram Channel Scanning Programmable Burst In this mode a sequence of channels from 2 to 16 is scanned a single time at the burst clock rate each time a burst trigger is applied The starting channel is
12. PORTB LOWEN lo o o o ourur ourur o OUTPUT Lo o o 1 ourur ourur 1 PUT po o o ourur ourur 2 eur o o ourrur ourur s eur eur o o o Lo 1 o 1 wur s ourur input jo o ovur eur 6 meut OUTPUT Lo 1 17 ourur meur pt o o o meur oureur OUTPUT 1 o o 1 mer ourur eur Lt o 1 o ourur 10 meur OUTPUT topo 1 meur i 1 o weu weur 12 pa o 1 weur eur 3 i n f o wer meu 14 Lo o weu j weur 5 MODE 0 Configurations CONTROL WORD 60 CONTROL WORD 2 D 0 0 D O 0 D D D b 0 CONTROL WORD 1 CONTROL WORD 3 D Dy Dy D 0 0 D Dg 0 D 09 0 8 28 231256 10 3 131 82 55 MODE 0 Configurations Continued CONTROL WORD 04 D 0 05 D 0 0 0 0 CONTROL WORD 95 D De D 0 D D D D CONTROL WORD 06 Dj D D D D D D Dy CONTROL WORD 67 D D D 0 D O 0 D 3 132 CONTROL WORD 48 0 0 D 0 CONTROL WORD 9 D 0 0 0 0 0 D CONTROL WORD 10 0 0 0 D 0 D D D CONTROL WORD D D 0 D D D P8 P8 231256 11 intel 82 55 MODE 0 Configurations Continued CONTROL WORD 61
13. The 82C55A is fabricated on Intel s advanced CHMOS Ill technology which provides low power consumption with performance equal to or greater than the equivalent NMOS product The 82C55A is available 40 pin DIP and 44 pin plastic leaded chip carrier PLCC packages 231256 1 Figure 1 82C55A Block Diagram 231256 2 Figure 2 82C55A Pinout Diagrams are for pin reference only Package sizes are not to scale September 1987 3 124 Order Number 231256 004 intel 82 55 Table 1 Pin Description Pin Number Symbol Dip PLCC Function O PORT A PINS 0 3 Lower nibble of an 8 bit data output latch buffer and an 8 bit data input latch mo a 6 READ CONTROL This input is low during CPU read operations wala CHIP SELECT A low on this input enables the 82 55 to respond to RD and WR signals RD and WR are ignored otherwise ADDRESS These input signals in conjunction RD and WA control the selection of one of the three ports or the control word registers Data Bus Port A po fifo DataBus Pons 1 of 1 o Databus Potc pt c 1 fo o Data us Contror Disable Function x x x 1x 1 DaaBus 3 State LX Lx 11 1 o Dwame s Sue PORT C PINS 4 7 Upper nibble of an 8 bit data output latch buffer and an 8 bit data input buffer no latch for input This port can be divided into two 4 bit ports under the mode contr
14. calculate a linear address determine page corresponding to this linear address PageOffset LinearAddress MOD 65536 determine offset into the page In segment FP_SEG amp Buffer get segment of buffer offset FP_OFS amp Buffer get offset of buffer linear_address segment 16 offset calculate a linear address page linear_address 65536 determine page corresponding to this linear address page_offset linear_address 65536 determine offset into the page In BASIC S VARSEG BUFFER VARPTR BUFFER LA 5 16 0 PAGE INT LA 65536 POFF LA PAGE 65536 Beware There is one big catch when using page based addresses The DMA controller cannot write properly to a buffer that straddles a page boundary A buffer straddles a page boundary if one part of the buffer resides in one page of memory while another part resides in the following page The DMA controller cannot properly write to such a buffer because the DMA controller can only write to one page without reprogramming When it reaches the end of the current page it does not start writing to the next page Instead it starts writing back at the first byte of the current page This can be disastrous if the beginning of the page does not correspond to your buffer More often than not this location is being used by the code portion of your program or the operating system and writing data to it will almost always
15. 0 it will still be loaded on the next CLK pulse When GATE goes high OUT will go high N CLK pulses later no CLK pulse is needed to load the Counter as this has already been done CW 10 8 4 un pepe re p e 10 58 2 CW t0 1880 148 2 JURA our 231244 8 The Following Conventions Apply All Mode Timing Diagrams 1 Counters are programmed for binary not BCD counting and for Reading Writing least significant byte LSB only 2 The counter is always selected 55 always low 3 CW stands for Control Word CW 10 means a control word of 10 hex is written to the counter 4 LSB stands for Least Significant Byte of count 5 Numbers below diagrams are count values The lower number is the least significant byte The upper number is the most significant byte Since the counter is programmed to Read Write LSB only the most significant byte cannot be read N stands for an undefined count Vertical lines show transitions between count values Figure 15 Mode 0 intel 82 54 MODE 1 HARDWARE RETRIGGERABLE ONE SHOT OUT will be initially high OUT will low on the CLK pulse following a trigger to begin the one shot pulse and will remain low until tne Counter reaches zero OUT will then go high and remain high until the CLK pulse after the nex
16. INTE A Controlled by bit set reset of INTE B Controlled by bit set reset of 231256 16 Figure 11 MODE 1 Strobed Output 3 135 82C55A Combinations of MODE 1 Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I O applications CONTROL WORD Dy D Dy D D D O D leii fef ie D e 1 INPUT PORT A STROBED INPUT PORT STROBED OUTPUT CONTROL WORD D Dg D D D D D Dy Lr je 9 fp C PORT A STROBED OUTPUT PORT 8 STROBED INPUT 231256 17 Figure 12 Combinations of MODE 1 Operating Modes MODE 2 Strobed Bidirectional Bus 1 0 This functional configuration provides a means for com municating with a peripheral device or structure on a single 8 bit bus for both transmitting and receiving data bidirectional bus 1 0 Handshaking signals are provided to maintain proper bus flow discipline in a similar manner to MODE 1 Interrupt generation and enable disable functions are also available MODE 2 Basic Functional Definitions Used in Group A only One 8 bit bi directional bus port Port A and a 5 bit control port Port C e Both inputs and outputs latched e The 5 bit control port Port C is used for control and status for the 8 bit bi directional bus port Port A Bidirectional Bus I O Control Signal Definition INTR Interrupt Re
17. INTR is set by the STB is a IBF is a and is a It is reset by the falling edge of RD This procedure allows input device to quest service from the CPU by simply strobing its data into the port CONTROL WORD INTE A Controlled by bit set reset of PCa INTE B 231256 13 Controlled by bit set reset of Figure 8 MODE 1 Input FROM aa PERIPHERAL 231256 14 Figure 9 MODE 1 Strobed Input 3 134 intel 82C55A Output Control Signal Definition OBF Output Buffer Full F F The OBF output will MODE 1 PORT go low to indicate that the CPU has written data CONTROL WORD out to the specified port The OBF F F will be set b D Dg Dz D 0 D D D the rising edge of the WR input and reset by ACK Input being low Mas 1s INPUT OuTPuT ACK Acknowledge Input A low on this input informs the 82C55A that the data from Port A or Port B has been accepted In essence a response from the peripheral device indicating that it has received the data output by the CPU MODE 1 PORT Bi INTR Interrupt Request A high on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU sake INTR is set when is is and INTE is It is reset by the falling edge of LU DDD WR
18. Port 820 20 Send EOI command to 8259 end Saving the Startup Interrupt Mask Register IMR and Interrupt Vector The next step after writing the ISR is to save the startup state of the interrupt mask register and the interrupt vector that you will be using The IMR is located at VO port 21H The interrupt vector you will be using is located in the interrupt vector table which is simply an array of 256 bit 4 byte pointers and is located in the first 1024 bytes of memory Segment 0 Offset 0 You can read this value directly but it is a better practice to use DOS function 35H get interrupt vector Most C and Pascal compilers provide a library routine for reading the value of a vector The vectors for the hardware interrupts are vectors 8 through 15 where IRQO uses vector 8 IRQ1 uses vector 9 and so on Thus if the 2200 will be using IRQ3 you should save the value of interrupt vector 11 Before you install your ISR temporarily mask out the IRQ you will be using This prevents the IRQ from requesting an interrupt while you are installing and initializing your ISR To mask the IRQ read in the current IMR at I O port 21H and set the bit that corresponds to your IRQ remember setting a bit disables interrupts on that IRQ while clearing a bit enables them The IMR is arranged so that bit 0 is for IRQO bit 1 is for IRQ1 and so on See the paragraph entitled Interrupt Mask Register IMR earlier in this chapter for help in determ
19. Two 12 bit digital to analog output channels with dedicated grounds ADA boards only 35 10 0 to 5 or 0 to 10 volt analog output range ADA boards only 5 volts only operation 2310 boards only Turbo Pascal Turbo and BASIC source code diagnostics program e The following paragraphs briefly describe the major functions of the board A more detailed discussion of board functions is included in Chapter 3 Hardware Operation and Chapter 4 Board Operation and Programming The board setup is described in Chapter 1 Board Settings Analog to Digital Conversion The analog to digital A D circuitry receives up to 8 differential or 16 single ended analog inputs and converts these inputs into 12 bit digital data words which can then be read and or transferred to PC memory The board is factory set for single ended input channels The analog input voltage range is jumper selectable for bipolar ranges of 5 to 5 volts or 10 to 10 volts or a unipolar range of 0 to 10 volts The board is factory set for 5 to 5 volts Overvoltage protection to 35 volts is provided at the inputs The high performance A D converter supports fast settling software programmable gains of 1 2 4 and 8 with on board gain multiplier circuitry so that you can customize the input gain A D conversions are performed in 5 microseconds and the maximum throughput rate is 125 kHz Conversions are controlled through software b
20. 00000 nu S Coi 3 OOPS Pag 553 05055580 90 0000000000000n Be onl 0c2 06 000 Ba 005000000000000 RR um V80S IH 9 ED go A ETT C15 0000000 959956966090 x P7454 looooooooon 0010 000 000000 0000000 0000 00000000 2229925 0000000 ous 0000000 OO gcss 00 rasa 00000000 0000000 9 06606006000 Accessing the Analog World ur 00000 220 0000000000 p D Fig 5 1 Board Layout 5 3 Du 929 0000000000 22 2 gt ae Calibration Two procedures are used to calibrate the A D converter for all input voltage ranges The first procedure cali brates the converter for the unipolar range 0 to 10 volts and the second procedure calibrates the bipolar ranges 5 10 volts Table 5 1 shows the ideal input voltage for each bit weight for the unipolar straight binary range and Table 5 2 shows the ideal voltage for each bit weight for the bipolar twos complement ranges Unipolar Calibration Two adjustments are made to calibrate the A D converter for the unipolar range of 0 to 10 volts One is the offset adjustment and the other is the full scale or gain adjustment Trimpot TR4 is used to make the offset adjustment
21. 5 D ATAA A AAN OA GROUP A GROUP B Defined By Mode 0 or Mode 1 Selection Figure 17b MODE 2 Status Word Format Alternate Port C Pin Signal Mode interrupt Enable Flag INTE ACKg Output Mode 1 or STBg Input Mode 1 INTE A2 STBA Input Mode 1 or Mode 2 Output Mode 1 or Mode 2 Figure 18 Interrupt Enable Flags in Modes 1 and 2 INTE A1 3 140 inte 82C55A ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Bias 0 C to 70 C Storage Temperature 65 C to 150 C Supply Voltage 0 5 to 8 0V Operating Voltage 4V to 7V Voltage on any Input GND 2V to 6 5V Voltage on any Output GND 0 5V to Vcc 0 5V Power Dissipation 1 Watt CHARACTERISTICS 0 C to 70 C Voc 5V 310 GND m Vor Output Low Output Low Voltage IDAR Darlington Drive Current Port Hold Low Leakage Current aee Voc Supply Current Vcc Supply Current Standby NOTES 155 1 Pins Ay Ao CS WR RD Reset nn 2 Reta Bus Ports B Co 3 Outputs open 4 Limit output current to 4 0 mA a uu laa vu os os v e eem Pe Output High Voltage 0 Voc 0 4 E Input Leakage Current Ep Output Float Leakage Current Note 4 Ports A B C Vext 1 7V Port Hol
22. If GATE goes low during an output pulse OUT is set high immediately A trigger reloads the Counter with the initial count on the next CLK pulse OUT goes low N CLK pulses after the trigger Thus the GATE input can be used to synchronize the Counter After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse OUT goes low N CLK Pulses after the initial count is writ ten This allows the Counter to be synchronized by software also Cwets 158 3 E Ur EE Cw 14 158 5 14 158 4 LSB 5 231244 10 transition should not occur one clock prior to terminal count Figure 17 Mode 2 intel 82 54 Writing a new count while counting does not affect the current counting sequence If a trigger is re ceived after writing a new count but before the end of the current period the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count Otherwise the new count will be loaded at the end of the current counting cycle In mode 2 a COUNT of 1 is illegal MODE 3 SQUARE WAVE MODE Mode 3 is typically used for Baud rate generation Mode 3 is similar to Mode 2 except for the duty cycle of OUT OUT will initially be high When half the ini tial count has expired OUT goes low for the remain der of the count Mode 3 is periodic the sequence above is repea
23. V INP PortAddress V AND 223 OUT PortAddress V 4 10 set a single bit in a port OR the current value of the port with the value b where b 298 Example Set bit 3 in a port Read the current value of the port OR it with 8 8 2 and then write the resulting value to the port In Pascal this is programmed as V Port PortAddress V VOR 8 Port PortAddress V Setting or clearing more than one bit at a time is accomplished just as easily To clear multiple bits in a port AND the current value of the port with the value b where b 255 the sum of the values of the bits to be cleared Note that the bits do not have to be consecutive Example Clear bits 2 4 and 6 in a port Read in the current value of the port AND it with 171 171 255 2 2 25 and then write the resulting value to the port In C this is programmed as inportb port_address v amp 171 outportb port address v To set multiple bits in a port OR the current value of the port with the value b where b the sum of the individual bits to be set Note that the bits to be set do not have to be consecutive Example Set bits 3 5 and 7 in a port Read in the current value of the port OR it with 168 168 2 25 27 and then write the resulting value back to the port In assembly language this is programmed as mov dx PortAddress in al dx or al 168 out dx al Often assigning a ran
24. and trimpot TR1 is used for gain adjustment This calibration procedure is performed with the board set up for a 0 to 10 volt input range Before making these adjustments make sure that the jumpers on P8 are set for 10V and and the jumper on P9 is set for Use analog input channel 1 and set it for a gain of 1 while calibrating the board Connect your precision voltage source to channel 1 Set the voltage source to 1 22070 millivolts start a conversion and read the resulting data Adjust trimpot TR4 until it flickers between the values listed in the table at the top of the next page Next set the voltage to 9 49829 volts and repeat the procedure this time adjusting TR1 until the data flickers between the values in the table Note that the value used to adjust the full scale voltage is not the ideal full scale value for a 0 to 10 volt input range This value is used because it is the maximum value at which the A D converter is guaranteed to be linear and ensures accurate calibration results Table 5 1 A D Converter Bit Weights Unipolar Straight Binary 1111 1111 1111 1000 0000 0000 0100 0000 0000 0010 0000 0000 0001 0000 0000 0000 1000 0000 0000 0100 0000 0000 0010 0000 0000 0001 0000 0000 0000 0100 0000 0000 0010 0000 0000 0001 0000 0000 0000 5 4 Data Values for Calibrating Unipolar 10 Volt Range 0 to 10 volts Offset TR4 Converter Gain TR2 Input Voltage 1 22070 mV Inp
25. that order of a Counter s CLK input TRIGGER a rising edge of a Counter s GATE in put COUNTER LOADING the transfer of a count from the CR to the CE refer to the Functional Descrip tion MODE 0 INTERRUPT ON TERMINAL COUNT Mode 0 is typically used for event counting After the Control Word is written OUT is initially low and will remain low until the Counter reaches zero OUT then goes high and remains high until a new count or a new Mode 0 Control Word is written into the Coun ter GATE 1 enables counting GATE 0 disables counting GATE has no effect on OUT After the Control Word and initial count are written to a Counter the initial count will be loaded on the next CLK pulse This CLK pulse does not decrement the count so for an initial count of N OUT does not go high until N 1 CLK pulses after the initial count is written If a new count is written to the Counter it will be loaded on the next CLK pulse and counting will con tinue from the new count If a two byte count is writ ten the following happens 1 Writing the first byte disables counting OUT is set low immediately no clock pulse required 2 Writing the second byte allows the new count to be loaded on the next CLK pulse 3 91 This allows the counting sequence to be synchroniz ed by software Again OUT does not go high until N 1 pulses after the new count of is written If an initial count is written while GATE
26. this line goes low At this time the analog input channel can be changed allowing maximum throughput for scanning channels through software A write starts conversion data written is irrelevant End of Convert 0 2 no EOC 1 conversion done P3 TRIG Status monitors the TRIG line selected on P3 A D CONVERTER Status 0 converting 1 not converting DMA Done P3 PCLK Status ROS 0 not done monitors the PCLK line IRQ Status 1 DMA done selected on P3 0 No IRQ 1 IRQ BA 1 Read A D Data Update DAC Outputs Read Write Two successive reads provide the LSB first followed by the MSB for each A D conversion as defined below When jumpers on P8 and 9 set for bipolar conversions the data word s four most significant bits match the most significant bit of the A D converted data bit 11 This is necessary to provide the correct twos complement representation of the converted data When P8 and P9 are set for unipolar conversions these top four bits 0 A write simultaneously starts a D A conversion in both DACs data written is irrelevant If the data written to either channel has not been updated since the last conversion the output of the corresponding DAC will not change Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB Bit11 Biti1 Bit11 Bitil Bit11 Bit10 Bit9 Bit 8 MSB 0 0 0 0 Bit11 10 Bit9 Bit 8 2 Reset Write Only Resets internal
27. 82 55 WAVEFORMS Continued MODE 1 STROBED INPUT INPUT FROM __ PERIPHERAL 231256 24 MODE 1 STROBED OUTPUT 231256 25 3 145 intel 82 55 WAVEFORMS Continued MODE 2 BIDIRECTIONAL DATA FROM 3060 8255 7 y DATA FROM DATA FROM PERIPHERAL TO 8256 8258 TO PERIPHERAL DATA FROM 8265 TO 8080 231256 26 Note Any sequence where WR occurs before ACK AND STB occurs before RD is permissible INTR IBF MASK e STB RD e MASK WR WRITE TIMING READ TIMING HIGH MPEDANCE 231256 28 2 0 2 0 gt gt rest roms C gt 180 pF 0 8 231256 29 231256 30 Testing Inputs Are Driven At 2 4V For A Logic 1 And 0 45V For A Logic 0 Timing Measurements Are Made At 2 0V For A Vexr Is Set At Various Voltages During Testing To Guarantee Logic 1 And 0 8 For A Logic 0 The Specification C Includes Jig Capacitance 3 146 D 1 APPENDIX D WARRANTY LIMITED WARRANTY Real Time Devices Inc warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from REAL TIME DE VICES This warranty is limited to the original purchaser of product and is not transferable During the one year warranty period REAL TIME DEVICES will repair or replace at its option any defective
28. A D Data LSB D A Converter 1 LSB 0 4 9 BA 13 A D Data MSB D A Converter 1 MSB 2 444 440 1032 00 000000 4 9 BA 14 Clear IRQ Status D A Converter 2 LSB Read Write eee eeeeeeeee ennt tnnt 4 9 BA 15 Clear DMA Done Flag D A Converter 2 MSB Read Write eese 4 9 Programming the 2210 2310 iiie eret nee E Re PAREN P aa 4 10 Clearing and Setting Bits in a Port 2 4440 0 a ia in iare 4 10 A D Conversio nes LE 4 12 Initializing the 8255 PPI C nennen 4 12 Clearing the Board 5 4 12 Selecting Channel seine 4 12 Setting 4 13 Enabling and Disabling the External Trigger 4 13 Enabling and Disabling Interrupts cssssssssessssseccscersssscenessesesesssnsosseneseseesescesessecesceessesesssesansvsases 4 13 Ba cod I iniciando di A ii 4 13 Starting an A D Conversion 0 4 15 Monitoring Conversion Status DMA Done or End of Convert eese 4 15 Reading the Converted Data 4 16 Programming the Pacer Clock 22 il id Eine 4 17 iur DE 4 18 What Is an Interruptor
29. Divider 1 Timer Counter 0 and Divider 2 Timer Counter 1 shown in the diagram The formulas for making this calculation are as follows Pacer clock frequency Clock Source Frequency Divider 1 x Divider 2 Divider 1 x Divider 2 Clock Source Frequency Pacer Clock Frequency To set the pacer clock frequency at 100 kHz using the on board 8 MHz clock source this equation becomes Divider 1 x Divider 2 8 MHz 100 kHz gt 80 8 MHz 100 kHz After you determine the value of Divider 1 x Divider 2 you then divide the result by the least common denomi nator The least common denominator is the value that is loaded into Divider 1 and the result of the division the quotient is loaded into Divider 2 In our example above the least common denominator is 2 so Divider 1 equals 2 and Divider 2 equals 80 2 or 40 The table below lists some common pacer clock frequencies and the counter settings using the on board 8 MHz clock source After you calculate the decimal value of each divider you can convert the result to a hex value if it is easier for you when loading the count into the 16 bit counter To set up the pacer clock on the board follow these steps 1 Select a clock source the 8 MHz on board clock or an external clock source 2 Program Timer Counter 0 for Mode 2 operation 3 Program Timer Counter 1 for Mode 2 operation 4 Load Divider 1 LSB 5 Load Divider 1 MSB 6 Load Divider 2 LSB 7 Load Divider 2 MSB The pace
30. Help 2 oorr A i 4 CHAPTER 1 BOARD SETTINGS sssseseonenenessnnenenensnsenenensenenensnnonennensnenssnenansenonsenonunnenensensesenessenee L 1 Factory Configured Switch and Jumper Settings 0 cssccessscssssssssssssssessssssecscsesescsceresssvsesesecstensesssasacassnsssesacaeas 1 3 8254 Timer Counter Sources Factory Settings See Table 1 1 amp Figure 1 2 1 4 P4 Interrupt Channel Select Factory Setting Jumper Interrupt Channel Disabled 1 5 P5 DMA Request and DMA Acknowledge Channel Factory Setting Disabled 1 6 DAC 1 Output Voltage Range Factory Setting 5 to 5 volts 2 1 7 P7 DAC 2 Output Voltage Range Factory Setting 5 to 5 volts 1 7 P8 Analog Input Voltage Range and Polarity Factory Setting 5 to 5 Volts 1 8 P9 A D Data Word Bit State Set Factory Setting ccsscsscssssesesssssssssscecscssscscscseseevsestssssansssseeaeesaeees 1 8 P10 Single Ended Differential Analog Inputs Factory Setting Single Ended 1 9 S1 Base Address Factory Setting 300 hex 768 decimal essetis 1 9 Pull up Pull down Resistors on Digital VO Lines eese tette ttt 1 10 Gm Gain Multiplier
31. Read count value Load count register 9 8254 Timer Counter 2 Available for external use Read count value Load count register BA 10 8254 Timer Counter Control Word Reserved Program counter mode BA 11 D A Converter 1 LSB Read A D converted data LSB Program DAC1 LSB ADA only 12 D A Converter 1 MSB Read A D converted data MSB Program DAC1 MSB ADA only BA 13 13 Clear IRQ D A Converter 2 LSB Clear IRQ status Program DAC2 LSB ADA only BA 14 Clear DMA Done D A Converter 2 MSB Clear DMA done flag Program DAC2 MSB ADA only BA 15 BA Base Address BA 0 Read Status Start Convert Read Write A read provides the six status bits defined below The end of convert bit goes high when a conversion is complete and does not go low until the data is read useful information when using external triggering to start conversions The DMA done bit goes high when you are in the DMA mode and the DMA transfer is complete The IRQ status bit goes high when an interrupt has occurred and stays high until a clear IRQ command is sent BA 14 D3 shows the status of the burst trigger source jumpered at P3 TRIG D6 shows the status of the PCLK line jumpered at P3 Unlike the EOC status at bit 0 the A D converter status D7 goes low when a conversion starts and then goes high as soon as the conversion is completed When the input has been sampled and a conversion is in progress
32. and the number of channels sampled is set by the data written to BA 3 and the starting channel is set by the data written to BA 5 Clear Board Program Pacer Clock Select Scan Mode amp Starting Channel Number of Channels to Scan Start Conversion Check End of Convert 1 Read MSB Read LSB Fig 4 10 Scan Flow Diagram No Stop Program 4 33 Interrupts Flow Diagram Figure 4 11 This flow diagram shows you how to program an interrupt routine for your board The diagram parallels the interrupts discussion included earlier in this chapter You can use this diagram in conjunction with the detailed text in this chapter to develop an interrupt program for your board Clear Board Save startup value Select IRQ source Save startup interrupt vector Clear IRQ bit in IMR Set IRQ bit in IMR Body of user program Vector new interrupt service routine ISR Restore startup interrupt vector Restore startup IMR value Stop Program Fig 4 11 Interrupts Flow Diagram Program interrupt Source 4 34 D A Conversion Flow Diagram Figure 4 12 This flow diagram shows you how to generate a voltage output through the D A converter ADA2210 and ADA2310 only A conversion is initiated each time the high byte MSB is written to the D A converter Stop Program Fig 4 12 D A Conversion Flow Diagram 4 35
33. are first trying your board is address contention Some of your computer s I O space is already occupied by internal I O and other peripherals When the board attempts to use I O address locations already used by another device contention results and the board does not work To avoid this problem the 2210 2310 has an easily accessible five position DIP switch S1 which lets you select any one of 32 starting addresses in the computer s I O Should the factory setting of 300 hex 768 decimal be unsuitable for your system you can select a different base address simply by setting the switches to any one of the values listed in Table 1 2 The table shows the switch settings and their corresponding decimal and hexadecimal in parentheses values Make sure that you verify the order of the switch numbers on the switch 1 through 5 before setting them When the switches are pulled forward they are OPEN or set to logic 1 as labeled on the DIP switch package When you set the base address for your board record the value in the table inside the back cover Figure 1 12 shows the DIP switch set for a base address of 300 hex 768 decimal Fig 1 12 Base Address Switch S1 Table 1 2 Base Address Switch Settings 51 Table 1 2 Base Address Switch Settings SI Decimal Hex 54321 Decimal Hex 54321 seres ooro ses 10101 zog ori 11111 0 closed 1 open Pull up Pull down Resistors on
34. causes erratic behavior and an eventual system crash You must check to see if your buffer straddles a page boundary if it does take action to prevent the DMA controller from trying to write to the portion that continues on the next page You can reduce the size of the buffer or try to reposition the buffer However this can be difficult when using large static data structures and often the only solution is to use dynamically allocated memory 4 23 Setting the DMA Page Register Oddly enough you do not inform the DMA controller directly of the page to be used Instead you put the page to be used into the DMA page register which is separate from the DMA controller as shown in the table below The location of this register depends on the DMA channel being used DMA Channel Location of Page Register The DMA Controller The DMA controller is a complex chip that occupies the first 16 bytes of the PC s I O port space A complete discussion on how it operates is beyond the scope of this manual only relevant information is included here The DMA controller is programmed by writing to the DMA registers in your PC The table below lists these registers Note that when you write 16 bit values to any of these registers such as to the Count registers you must write the LSB first followed by the MSB If you are using DMA channel 1 write your page offset and count to ports 02H and 03H if you are using channel 3
35. easiest is to the DMA done bit in the 2210 2310 status register BA 0 While DMA is in progress the bit is clear 0 When DMA is complete the bit is set 1 The second way to check is to use the DMA done signal to generate an interrupt An interrupt can immediately notify your program that DMA is done and any actions can be taken as needed Both methods are demonstrated in the sample and Pascal programs the polling method the program named DMA and the interrupt method in DMASTRM Common DMA Problems Make sure that your buffer is large enough to hold all of the data you program the DMA controller to transfer Check to be sure that your buffer does not straddle a page boundary Remember that the number of bytes for the DMA controller to transfer is equal to twice the number of samples This is because each sample is two bytes in size If you terminate sampling before the DMA controller has transferred the number of bytes it was programmed for be sure to disable DMA by setting the mask bit in the single mask register Make sure that the board is not running too fast for DMA transfers D A Conversions ADA Boards Only The two D A converters can be individually programmed to convert 12 bit digital words into a voltage in the range of 5 10 0 to 5 or 0 to 10 volts DACI is programmed by writing the 12 bit digital data word to BA 8 DAC2 is identical with the data word written to BA 10 The following table
36. grammed That counter is automatically unlatched when read but other counters remain latched until they are read If multiple count read back commands are issued to the same counter without reading the intel 82654 count all but the first are ignored the count which will be read is the count at the time the first read back command was issued The read back command may also be used to latch status information of selected counter s by setting STATUS bit D4 0 Status must be latched to be read status of a counter is accessed by a read from that counter The counter status format is shown in Figure 11 Bits D5 through DO contain the counter s programmed Mode exactly as written in the last Mode Control Word OUTPUT bit D7 contains the current state of the OUT pin This allows the user to monitor the counter s output via software possibly eliminating some hardware from a system Ds 02 Di Do Dg NULL oun ois eve wo co 71 Out Pin is 1 Out Pin is 0 Dg 1 Null count 0 Count available for reading Ds Do Counter Programmed Mode See Figure 7 Figure 11 Status Byte NULL COUNT bit D6 indicates when the last count written to the counter register CR has been loaded into the counting element CE The exact time this happens depends on the Mode of the counter and is described in the Mode Definitions but until the count is loaded into the counting element CE it can t be read f
37. is written to the START CONVERT port 0 software trigger The active channel is the one specified in the CHANNEL GAIN SELECT port This is the easiest of all conversions It can be used in a wide variety of applications such as sample every time a key is pressed on the keyboard sample with each iteration of a loop or watch the system clock and sample every five seconds Figure 4 2 shows a timing diagram for single conversions See the SOFTTRIG sample program in C and Pascal and the SINGLE program in BASIC on the example programs disk included with your board START CONVERT So u as memi SAMPLE TAKEN TL SAMPLED CHANNEL 1 1 1 Fig 4 2 Timing Diagram Single Conversion Multiple Conversions In this mode conversions are continuously performed at the pacer clock rate The pacer clock can be internal or external depending on the setting of the PCLK jumper on P3 The maximum rate supported by the board is 125 kHz If you use the internal pacer clock you must program it to run at the desired rate This mode is ideal for filling arrays acquiring data for a specified period of time and taking a specified number of samples Figure 4 3 shows a timing diagram for multiple conversions See the MULTI sample programs in C and Pascal on the example programs disk included with your board PAcERCLOCK TL SAMPLE TAKEN 1 1 1 1 1 1 1 1 1 SAMPLED CHANNEL 1 1 1 1 1 1 1 1 1
38. only a single Counter will be described The internal block diagram of a single counter is shown in Figure 5 The Counters are fully independent Each Counter may operate in a different Mode The Control Word Register is shown in the figure it is not part of the Counter itself but its contents de termine how the Counter operates 82 54 i 1 1 comma ERR Er 231244 6 Figure 5 Internal Block Diagram of a Counter The status register shown in the Figure when latched contains the current contents of the Control Word Register and status of the output and null count flag See detailed explanation of the Read Back command The actual counter is labelled CE for Counting Ele ment It is 16 bit presettable synchronous down counter OLm and OL are two 8 bit latches OL stands for Output Latch the subscripts M and L stand for Most significant byte and Least significant byte respectively Both are normally referred to as one unit and called just OL These latches normally fol low the CE but if a suitable Counter Latch Com mand is sent to the 82C54 the latches latch the present count until read by the CPU and then return to following the CE One latch at a time is enabled by the counter s Control Logic to drive the internal bus This is how the 16 bit Counter communicates over the 8 bit internal bus Note that the CE itself cannot be read whenever you read t
39. registers so that the board is ready to start conversions The data written is irrelevant the act of writing to this address clears the board A reset command sets the internal byte pointer to read the LSB on the next read resets the DRQ and IRQ registers clears the EPLD scan burst circuitry and resets clears the DMA done bit BA 0 bit 1 BA 3 Scan Burst Read Write Bits DO through D3 program the number of consecutive analog input channels to be scanned or bursted The channel scan or burst begins with the channel selected at BA 5 Bits D4 and DS program one of four IRQ sources available for generating interrupts The IRQ channel is set by the jumper on P4 The IRQ is enabled at bit 7 BA 5 Bits D6 and D7 enable the scan or burst mode Each time you start a new scan or burst you should first reset the board by writing to BA 2 or by programming these bits to disable scan burst and then follow that step by enabling the scan or burst mode This ensures that the EPLD scan burst counter circuitry is cleared Scan Burst Enable IRQ Source Select Number of 00 disabled 00 A D start convert Channels Scanned 01 not used 01 DMA done 0000 1 channel 1000 9 channels 10 scan enabled 11 burst enabled 10 trigger P3 TRIG 11 pacer clock P3 PCLK 0001 2 channels 0010 3 channels 0011 4 channels 0100 5 channels 0101 6 channels 0110 7 channels 0111 2 8 channels 1001 10 channels 1010 2 11 chan
40. two byte count is writ ten the following happens 3 93 82 54 1 Writing the first byte has no effect on counting 2 Writing the second byte allows the new count to be loaded on the next CLK pulse This allows the sequence to be retriggered by software OUT strobes low N 1 CLK pulses after the new count of N is written 18 56 3 FF ala Sf CWels 1 8 3 EIE gy e Lujaa u s sisalik L3B 3 058 2 3 2 1 2 1 0 FF 231244 12 Figure 19 Mode 4 MODE 5 HARDWARE TRIGGERED STROBE RETRIGGERABLE OUT will initially be high Counting is triggered by a rising edge of GATE When the initial count has ex pired OUT will go low for one CLK pulse and then go high again 3 94 After writing the Control Word and initial count the counter will not be loaded until the CLK pulse after a trigger This CLK pulse does not decrement the count so for an initial count of N OUT does not strobe low until N 1 CLK pulses after a trigger A trigger results in the Counter being loaded with the initial count on the next CLK pulse The counting sequence is retriggerable OUT will not strobe low for 1 CLK pulses after any trigger GATE has no effect on OUT If a new count is written during counting the current counting sequence will not be affected If a trigger occurs after the new count is written but be
41. use any DOS functions or routines that call DOS functions from within an ISR DOS is not reentrant that is a DOS function cannot call itself In typical programming this will not happen because of the way DOS is written But what about when using interrupts Then you could have a situation such as this in your program If DOS function X is being executed when an interrupt occurs and the interrupt routine makes a call to DOS function X then function X is essentially being called while it is already active Such a reentrancy attempt spells disaster because DOS functions are not written to support it This is a complex concept and you do not need to understand it Just make sure that you do not call any DOS functions from within your ISR The one wrinkle is that unfortunately it is not obvious which library routines included with your compiler use DOS functions A rule of thumb is that routines which write to the screen or check the status of or read the keyboard and any disk I O routines use DOS and should be avoided in your ISR The same problem of reentrancy exists for many floating point emulators as well meaning you may have to avoid floating point real math in your ISR Note that the problem of reentrancy exists no matter what programming language you are using Even if you are writing your ISR in assembly language DOS and many floating point emulators are not reentrant Of course there are ways around this problem such as those which in
42. 16 single ended software selectable analog input channels The following paragraphs describe the A D circuitry Analog Inputs The input voltage range is jumper selectable for 5 to 5 volts 10 to 10 volts or 0 to 10 volts Software programmable binary gains of 1 2 4 and 8 let you amplify lower level signals to more closely match the board s input ranges These gains can be customized for even greater input control by adding a gain multiplying resistor circuit as described in Chapter 1 Overvoltage protection to 35 volts is provided at the inputs A D Converter The AD678 12 bit successive approximation A D converter accurately digitizes dynamic input voltages in 5 microseconds for a maximum throughput rate of 200 kHz for the converter alone The AD678 contains a sample and hold amplifier a 12 bit A D converter a 5 volt reference a clock and a digital interface to provide a complete A D conversion function on a single chip Its low power CMOS logic combined with a high precision low noise design give you accurate results Conversions are initiated through software internally triggered or by using an external trigger brought onto the board through the I O connector An on board or external pacer clock can be used to control the conversion rate Conversion modes are described in Chapter 4 Board Operation and Programming 3 3 Data Transfer The converted data can be transferred through the PC data bus to PC memory in on
43. 2 0 0 D 0 D D D O CONTROL WORD 613 0 0 0 D D D D D Operating Modes MODE 1 Strobed input Output This functional configuration provides a means for transferring 1 data to or from a specified port in conjunction with strobes or handshaking signals in mode 1 Port A and Port B use the lines on Port C to generate or accept these handshaking signals CONTROL WORD 14 0 0 D D 0 0 D D CONTROL WORD 18 D 0 0 0 0 D 231256 12 Mode 1 Basic functional Definitions Two Groups Group A and Group Each group contains one B bit data port and one 4 bit control data port The 8 bit data port can be either input or output Both inputs and outputs are latched The 4 bit port is used for control and status of the 8 bit data port RR 3 133 intel 82C55A Input Control Signal Definition MODE 1 PORT STB Strobe Input low on this input loads data into the input latch CONTROL WORD D D D D 0 D D Le t at 1 gt INPUT IBF Input Buffer Full F F A high on this output indicates that the data has been loaded into the input latch in essence an ac knowledgement IBF is set by STB input being low and is reset by the rising edge of the RD input INTR interrupt Request MODE 1 PORT 8 A high on this output can be used to interrupt the CPU when an input device is requesting service
44. A page register Program the DMA controller Program device generating data 2210 2310 Wait until DMA is complete Disable DMA 9 Oo tA Each step is detailed in the following paragraphs Choosing a DMA Channel There are a number of DMA channels available on the PC for use by peripheral devices The 2210 2310 can use either DMA channel 1 or DMA channel 3 The factory setting is DMA disabled You can arbitrarily choose one or the other by setting the jumpers on P5 as described in Chapter 1 in most cases either choice is fine Occasionally though you will have another peripheral device for example a tape backup or Bernoulli drive that also uses the DMA channel you have selected This will certainly cause erratic results and can be hard to detect The best ap proach to pinpoint this problem is to read the documentation for the other peripheral devices in your system and try to determine which DMA channel each uses 4 21 Allocating a DMA Buffer When using DMA you must have a location in memory where the DMA controller will place data from the board This buffer can be either static or dynamically allocated Just be sure that its location will not change while DMA is in progress The following code examples show how to allocate buffers for use with DMA In Pascal Var Buffer Array 1 10000 of Byte static allocation Of Var Buffer Byte dynamic allocation Buffer GetMem 10000 In C
45. BA 0 A write programs the DAC2 LSB eight bits BA 15 Clear DMA Done Flag D A Converter 2 MSB Read Write A read clears the DMA done flag at bit 1 BA 0 A write programs the DAC2 MSB four bits into DO through D3 D4 through D7 are irrelevant news or os os v or oo Bit 7 BitS Bit4 Bits Bit2 Bit 1 Bit 0 Bit11 Bit10 Bit9 Bit 8 Programming the 2210 2310 This section gives you some general information about programming and the board and then walks you through the major programming functions These descriptions will help you as you use the example programs included with the board and the programming flow diagrams at the end of this chapter All of the program descriptions in this section use decimal values unless otherwise specified The 2210 2310 is programmed by writing to and reading from the correct port locations on the board These ports were defined the previous section Most high level languages such as BASIC Pascal C and C and of course assembly language make it very easy to read write these ports The table below shows you how to read from and write to I O ports using some popular programming languages ume wie Assembly mov dx Address mov dx Address in al dx mov al Data out dx al In addition to being able to read write the ports the board you must be able to perform a variety of operations that you might not normally use in your program
46. Before AB Y 45 9 NCAA EE CS Stable Before RD Address Hold Time After ADT 0 taa RDPuseWidn 150 tp Data Delay from AD tao Data Delay from Address tr ADT to Data Floating 5 ty Command Recovery Time 200 NOTE 1 AC timings measured at 2 0 Vor 0 8V 3 96 intel 82C54 CHARACTERISTICS Continued WRITE CYCLE Address Stable Before WR CS Stable Before WR twA Address Hold Time After WR H Pulse Width Data Setup Time Before WR ata Hold Time After WR T mmand Recovery Time gt il ct SEES 5 RV CLOCK AND GATE 5 g Parameter Clock Period tom High Pulse win 99 Low Pulse Width ex 505 a lock Rise Time lock Fall Time ate Width High ate Width Low ate Setup Time to CLK T ate Hold Time AfterCLKT 500 utput Delay from CLK utput Delay from Gate two CLK Delay for Loading 4 0 Gate Delay for Sampling 4 5 E 40 4 mp i o 0 OUT Delay from Mode Write CLK Set Up for Count Latch teL NOTES 2 In Modes 1 and 5 triggers are sampled on each rising clock edge A second trigger within 120 ns 70 ns for the 82C54 2 of the rising clock edge may not be detected 3 Low going glitches that violate tpwr tpw may cause errors requiring counter reprogrammi
47. CLK OUT GATE CLK 231244 7 Figure 6 82C54 System Interface intel 82 54 OPERATIONAL DESCRIPTION General After power up the state of the 82654 is undefined The Mode count value and output of all Counters are undefined How each Counter operates is determined when it is programmed Each Counter must be programmed before it can be used Unused counters need not be programmed Control Word Format Ay Ao 11 cS 0 RD 1 0 De 05 C1 04 Programming the 82654 Counters are programmed by writing a Control Word and then an initial count The control word format is shown in Figure 7 All Control Words are written into the Control Word Register which is selected when Ay Ag 11 The Control Word itself specifies which Counter is being programmed By contrast initial counts are written into the Coun ters not the Control Word Register The Ay in puts are used to select the Counter to be written into The format of the initial count is determined by the Control Word used D3 D2 D Do sor sco pws rwo m1 mo co SC Select Counter SC1 SCO lo 0 SelcCowterO 0 1 SelectCoumeri 3 0 SeectCoute2 1 Read Back Command See Read Operations RW Read Write RW1 RWO Counter Latch Command see Read Operations fo Read Write least significant byte only een Read Write most significant byte only 1 1 Read Write least
48. D D 05 D D 0 O 0 DIVX 82C55A MODE 2 AND MODE 0 OUTPUT CONTROL WORO D 0 Os D D Dz 0 D fo C 29 Y INPUT 0 OUTPUT MODE 2 AND MODE 1 INPUT CONTROL WORD 0 0 Os D 0 0 D Do 231256 21 Figure 16 MODE Y Combinations 3 138 Mode Definition Summary Special Mode Combination Considerations There are several combinations of modes possible For any combination some or all of the Port C lines are used for control or status The remaining bits are either inputs or outputs as defined by a Set Mode command During a read of Port C the state of all the Port C lines except the ACK and STB lines will be placed on the data bus In place of the ACK and STB line states flag status will appear on the data bus in the PC2 PC4 and PC6 bit positions as illustrated by Figure 18 Through a Write Port C command only the Port C pins programmed as outputs in a Mode 0 group be written No other pins can be affected by a Write Port C command nor can the interrupt enable flags be accessed To write to any Port C output pro grammed as an output in a Mode 1 group or to 82C55A GROUP A ONLY MODE 0 OR MODE 1 ONLY change an interrupt enable flag the Set Reset Port C Bit command must be used With a Set Reset Port C Bit command any Port C line programmed as an output including INTR IBF and OBF can be written or an interrupt enable flag ca
49. Digital I O Lines The 8255 programmable peripheral interface provides 16 TTL CMOS compatible digital I O lines which can be interfaced with external devices These lines are divided into three groups eight Port A lines four Port C Lower lines and four Port C Upper lines The eight lines of Port B are used for internal board functions You can install and connect pull up or pull down resistors for any or all of these three groups of lines You may want to pull lines up for connection to switches This will pull the line high when the switch is disconnected Or you may want to pull lines down for connection to relays which control turning motors on and off These motors turn on when the digital lines controlling them are high The Port A lines of the 8255 automatically power up as inputs which can float high during the few moments before the board is first initialized This can cause the external devices connected to these lines to operate erratically By pulling these lines down when the data acquisition system is first turned on the motors will not switch on before the 8255 is initialized To use the pull up pull down feature you must first install resistor packs in any or all of the three locations near the 8255 labeled PA PCL and PCH PA takes a 10 pin pack and PCL and PCH take 6 pin packs Figure 1 13 shows a blowup of the PA PCL and PCH resistor pack locations After the resistor packs are installed you must connect them into the circu
50. GES EXPENSES LOST PROFITS LOST SAVINGS OR OTHER DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PRODUCT SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSE QUENTIAL DAMAGES FOR CONSUMER PRODUCTS AND SOME STATES DO NOT ALLOW LIMITA TIONS ON HOW LONG AN IMPLIED WARRANTY LASTS SO THE ABOVE LIMITATIONS OR EXCLU SIONS MAY NOT APPLY TO YOU THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS AND YOU MAY ALSO HAVE OTHER RIGHTS WHICH VARY FROM STATE TO STATE D 3
51. HoldTimeafterROT o tmm RDPuseWidh 150 tao DataDelayfromADL _ 120 tr RD T to Data Floating 10 75 Recovery Time between RD WR 20 trv WRITE CYCLE Parameter 82C55A2 Eod WEG A Address Stable Before WR Test Conditions Ports A amp B WA Pulse Width tw Data Setup Time Before WR T LN Data Hold Time After WA T 30 3 142 intel 82C55A OTHER TIMINGS Parameter 82C55A2 Units Conditions WR 1 to Output Peripheral Data Before RD Peripheral Data After RD ACK Pulse Width STB Pulse Width 100 Per Data Before STB High Per Data After STBHigh K gt gt SIE A 5 8 5 A 1 to Output Float 1100 010 OBF 1 B 1 gt 150 s a te AD 1wier 0 Fe Me re C E ro Ee o cc A on Momo mE WR Oto INTR 0 ls soenoe Reset Pulse Width NOTE 1 INTR may occur as early as WR 2 Pulse width of initial Reset pulse after power on must be at least 50 uSec Subsequent Reset pulses may be 500 ns minimum 3 143 inter 82C55A WAVEFORMS MODE 0 BASIC INPUT CE A1 A0 m HANA tao u 231256 22 MODE 0 BASIC OUTPUT nn a 2 3 144 intel
52. NTER CLK UE X l I VO CONNECTOR 8254 1 JE e P2 l 5 c 8 MHz N CLOCK url PIN 45 EXT CLK 1 PIN 41 EXT GATE 1 I 1 1 i l 1 i l I l 1 1 PIN 42 OUT 1 I cu 1 I 0 I Q I 1 o L 8M 1 timers t COUNTER CLK I 2 1 1 i GATE l 1 i PIN 44 4 T C OUT 2 l 1 i i I i Q Q 5 od PIN 39 TRIGGER IN TRIG L 1 amp 1 l Q O 1 l PIN 46 EXT GATE 2 1 1 Fig 3 2 8254 Timer Counter Circuit Block Diagram 3 4 Each timer counter has two inputs CLK in and and one output timer counter OUT They can be programmed as binary or BCD down counters by writing the appropriate data to the command word as described in Chapter 4 The command word also lets you set up the mode of operation The six programmable modes are Mode 0 Event Counter Interrupt on Terminal Count Mode 1 Hardware Retriggerable One Shot Mode 2 Rate Generator Mode 3 Square Wave Mode Mode 4 Software Triggered Strobe Mode 5 Hardware Triggered Strobe Retriggerable These modes are detailed in the 8254 Data Sheet reprinted from Intel in Appendix C Digital I O Programmable Peripheral Interface The programmable peripheral interface PPI is used for digital I O functions This high performance TTL CMOS compatible chip has 24 digit
53. Port B is set up as a Mode 0 output port This is done by writing this data to the PPI control word at I O address BA 7 X don t 1 x x X X 0 0 x or os os os 02 br oo Clearing the Board It is good practice to start your program by resetting the board You can do this by writing to the RESET port at BA 2 The actual value you write to this port is irrelevant After resetting the board following power up you must take an A D reading and throw it away to make sure the converter is initialized and contains no unwanted data Selecting a Channel To select a conversion channel or the starting channel for a scan or burst you must assign values to bits 0 through 3 in the PPI Port B port at BA 5 The table below shows you how to determine the bit settings Channels 9 16 are available in single ended operation only Note that if you do not want to change the gain setting also programmed through BA 5 you must preserve it when you set the channel x x x x cur rs Channel CH3 CH2 CH1 CHO Channel CH3 CH2 CHO Setting the Gain You may choose among the various levels of programmable gain by setting bits 4 and 5 in the PPI Port B port BA 5 The table below shows you how to determine the bit settings for the gain you need Note that if you do not want to change the channel setting also programmed through BA 5 you must preserve it
54. TUS INTERRUPT REGISTER INTERRUPT CLR Fig 1 5 Pulling Down the Interrupt Request Line P5 DMA Request and DMA Acknowledge Channel Factory Setting Disabled This header connector shown in Figure 1 6 lets you select channel 1 or 3 for DMA transfers by installing two jumpers one on the DMA request line and one on the DMA acknowledge line The DMA request line DRQ must be set to the same channel as the DMA acknowledge line DACK The factory setting is DMA disabled jumpers in a stored position Note that if any other device in your system is already using your selected DMA channel channel contention will result causing erratic operation DRQ DACK QQ 9 P5 Fig 1 6 DMA Request amp DMA Acknowledge Channel Jumpers P5 1 6 P6 DAC 1 Output Voltage Range Factory Setting 5 to 5 volts This header connector shown in Figure 1 7 sets the output voltage range for DAC 1 at 0 to 5 5 0 to 10 or 10 volts Two jumpers must be installed one to select the range and one to select the multiplier The top two jumpers select the range bipolar 5 or unipolar 5 The bottom two jumpers select the multiplier X2 or X1 When a jumper is on the X2 multiplier pins the range values become 10 and 10 The table below shows the four possible combinations of jumper settings and the diagram shows the two bipolar settings This header does not have to be set the same as P7 Ber Top to Bottom Voltage Ra
55. ads and the output goes high again This process repeats indefinitely Mode 4 Software Triggered Strobe The output is initially high When the initial count expires the output goes low for one clock pulse and then goes high again Counting is triggered by writing the initial count Mode 5 Hardware Triggered Strobe Retriggerable The output is initially high Counting is triggered by the rising edge of the gate input When the initial count has expired the output goes low for one clock pulse and then goes high again I P3 vo CONNECTOR I 1725 1 8 MHz 9 clock O PIN 45 NEXT CLK 1 1 5 V PIN 41 EXT GATE 1 1 l l l COUNTER l GATE eut PIN 42 OUT 1 1 cu ftc I Q Q 1 8 MHz 1 CLOCK Q Q 1 1 1 PIN 44 A T C OUT 2 1 l MEE 1 1 o o PIN 39 TRIGGER IN i TAG i O i O O 1 TRIGGER PIN 46 EXT GATE 2 INPUT 1 GT2 l Fig 4 7 8254 Programmable Interval Timer Circuit Block Diagram Digital O The 16 8255 PPI based digital I O lines can be used to transfer data between the computer and external devices The digital input lines can have pull up or pull down resistors installed as described in Chapter 1 4 28 Example Programs and Flow Diagrams Included with the board is a set of example programs that demonstrate the use of many of the board s
56. al I O lines divided into two groups of 12 lines each Group Port A 8 lines and Port Upper 4 lines Group B Port B 8 lines and Port C Lower 4 lines Port A and Port are available at the external I O connector P2 Port B is dedicated to on board functions and is not available for your use You can use the 16 lines of Ports A and C in one of these three PPI operating modes Mode 0 Basic input output Lets you use simple input and output operation for a port Data is written to or read from the specified port Mode 1 Strobed input output Lets you transfer I O data from Port A in conjunction with strobes or hand shaking signals Mode 2 Strobed bidirectional input output Lets you communicate bidirectionally with an external device through Port A Handshaking is similar to Mode 1 These modes are detailed in the 8255 Data Sheet reprinted from Intel in Appendix C 4 BOARD OPERATION AND PROGRAMMING This chapter shows you how to program and use your 2210 2310 board It provides a complete description of the I O map a detailed description of programming operations and operating modes and flow diagrams to aid you in programming The ex ample programs included on the disk in your board package are listed at the end of this chapter These programs written in Turbo C Turbo Pascal and BASIC include source code to simplify your applications programming Defini
57. ater than the equivalent HMOS product The 82C54 is available in 24 pin DIP and 28 pin plastic leaded chip carrier PLCC packages x WA o GATE 1 40 O OT A OUT 1 OUTO GATEO GNO NC OUT1 GATE1CLK1 231244 3 PLASTIC LEADED CHIP CARRIER cs CLK 2 WORD GATE 2 REGISTER 231244 1 Figure 1 82C54 Block Diagram 231244 2 Diagrams for pin reference only Package sizes are not to scale Figure 2 82C54 Pinout September 1989 3 83 Order Number 231244 005 intel 82054 Table 1 Pin Description gt me Pec Data Bidirectional tri state data bus lines connected to system data bus cuo o 9 t Ciocko Clockinputot Countro ouro 10 O GaTEO 11 13 1 Gate 0 Gate input of Counter 0 12 14 Ground Power supply connection ouri 13 36 O Out 1 of Counter 1 GarE1 14 17 1 Gatei GateinputofConter 15 38 1 Clocki ClockimputofCountert Gate2 16 19 1 Gate2 GateinputofCounter2 oura 17 2 O Outz Output of Counter 2 c k2 18 2 Glock 2 ClockinputofCounter2 Counter 2 A1 Ap 20 19 Address Used to select one of the three Counters or the Control Word Register for read or write operations Normally connected to the system address bus Control Word Register cs Chip Select A low on this input enables the 82 54 to r
58. char Buffer 10000 static allocation Or char Buffer dynamic allocation Buffer calloc 10000 0 In BASIC DIM BUFFER 5000 Calculating the Page and Offset of a Buffer Once you have a buffer into which to place your data you must inform the DMA controller of the location of this buffer This is a little more complex than it sounds because the DMA controller uses a page offset memory scheme while you are probably used to thinking about your computer s memory in terms of a segment offset scheme Paged memory is simply memory that occupies contiguous non overlapping blocks of memory with each block being 64K one page in length The first page page 0 starts at the first byte of memory the second page page 1 starts at byte 65536 the third page page 2 at byte 131072 and so computer with 640K of memory has 10 pages of memory The DMA controller can write to or read from only one page without being reprogrammed This means that the controller has access to only 64K of memory at a time If you program it to use page 3 it cannot use any other page until you reprogram it to do so When DMA is started the DMA controller is programmed to place data at a specified offset into a specified page for example start writing at byte 512 of page 3 Each time a byte of data is written by the controller the offset is automatically incremented so the next byte will be placed in the next memory location The
59. ck into place and put the cover back on your computer The board is now ready to be connected via the external I O connector at the rear panel of your computer External I O Connections Figure 2 1 shows the 2210 2310 s P2 I O connector pinout Refer to this diagram as you make your VO connections OFF 5 DIFF S E AIN2 AIN2 AIN3 AIN3 AIN4 AINA AINS AINS AIN6 AING AIN7 AIN7 AINB AIN8 AOUT 1 AOUT 2 ANALOG GND 6 5 4 2 1 9 3 9 99 e e a 99 E a 9 TRIGGER IN DIGITAL GND EXT GATE 1 T C OUT 1 TRIGGER OUT 43 OUT 2 EXT CLK 49 EXT GATE 2 12 VOLTS 62 5 VOLTS 12 VOLTS 69 DIGITAL GND Fig 2 1 P2 VO Connector Pin Assignments 2 3 Connecting the Analog Input Pins The analog inputs on the board can be set for single ended or differential operation NOTE It is good practice to connect all unused channels to ground as shown in the following diagrams Failure to do so may affect the accuracy of your results Single Ended When operating in the single ended mode connect the high side of the analog input to one of the analog input channels AIN1 through AIN16 and connect the low side to an ANALOG GND pins 18 and 20 22 on P2 Figure 2 2 shows how these connections are made CONNECTOR P2 0 IS et 0
60. ck or by a software or hardware trigger burst mode They are started by the first pulse present after the trigger has been enabled Monitoring Conversion Status DMA Done or End of Convert The A D conversion status can be monitored through the DMA done flag or through the end of convert EOC bit in the STATUS port at BA 0 When doing transfers you will want to monitor the DMA done flag for a transition from low to high This tells you when the DMA transfer is complete and data has been placed in the PC s memory The line is available for monitoring conversion status when performing single conversions not using DMA transfer When the EOC goes from low to high the A D converter has completed its conversion and the data is ready to read The EOC line stays high following a conversion until the data has been read Then the line goes back to low until the next conversion is complete 4 15 Reading the Converted Data Two successive reads of port BA 1 provide the LSB and MSB of the 12 bit A D conversion in the format defined in the I O map section at the beginning of this chapter The LSB must always be read first followed by the MSB The converted data can also be read at BA 12 LSB and 13 MSB This allows you to use a read word command on an XT computer to automatically read both ports using one command The output code and the resolution of the conversion vary depending on the input voltage range select
61. command was issued Both count and status of the selected counter s may be latched simultaneously by setting both COUNT and STATUS bits D5 04 0 This is func tionally the same as issuing two separate read back commands at once and the above discussions ap ply here also Specifically if multiple count and or status read back commands are issued to the same counter s without any intervening reads all but the first are ignored This is illustrated in Figure 13 If both count and status of a counter are latched the first read operation of that counter will return latched status regardless of which was latched first The next one or two reads depending on whether the counter is programmed for one or two type counts return latched count Subsequent reads return un latched count Results Figure 13 Read Back Command Example 82 54 c a walaa 1 o Write into Countero Lo o 1 Write into Counters oli oli Write into Counter 2 fo 1 o Write Control word oloJ Jolo Read from Counter 0 foo t 0 7 Readtrom Counters fo 1 Read trom Counter Lo o 1 1 NoOperation 3 State No Operation 3 State o 1 1 x x No Operation 3 State Figure 14 Read Write Operations Summary Mode Definitions The following are defined for use in describing the operation of the 82C54 CLK PULSE a rising edge then a falling edge in
62. d C The 82C55A contains three 8 bit ports A and C All can be configured in a wide variety of functional characteristics by the system software but each has its own special features or personality to further enhance the power and flexibility of the 82C55A Port A One 8 bit data output latch buffer and one 8 bit input latch buffer Both pull up and down bus hold devices are present on Port A Port B One 8 bit data input output latch buffer Only pull up bus hold devices are present on Port B Port C One 8 bit data output latch buffer and one 8 bit data input buffer no latch for input This port can be divided into two 4 bit ports under the mode control Each 4 bit port contains a 4 bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B Only pull up bus hold devices are present on Port C See Figure 4 for the bus hold circuit configuration for Port A B and C 3 126 intel 82C55A BIDIRECTIONAL DATA BUS INTERNAL DATA IN INTERNAL DATA OUT EXTERNAL PORT INTERNAL DATA NOTE 231256 4 Port pins loaded with more than 20 pF capacitance may not have their logic level guaranteed following a hardware reset Figure 4 Port A B C Bus hold Configuration gt 3 127 7S nen un intel 82 55 82 55 OPERATIONAL DESCRIPTION Mode Selection There are t
63. d High Leakage Current Vour 3 0V Ports A B C sr Vout 0 8V Port Hold High Overdrive Current 350 pa EL EEE Notice Stresses above those listed under Abso lute Maximum Ratings may cause permanent dam age to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the opera tional sections of this specification is not implied Ex posure to absolute maximum rating conditions for extended periods may affect device reliability a 2 5 mA lou 100 pA Vin Voc to OV Note 1 ERE Vcc to OV ER 2 300 Vout 1 0V Port A only Vout 3 0V Note 3 Vcc 5 5V Vin Voc or GND Port Conditions If I P Open High O P Open Only With Data Bus High Low CS High Reset Low Pure Inputs Low High 3 141 tw ps om ene 2 NM intel 82C55A CAPACITANCE 25 C GND OV symbol Min max unts Cw imputGapacitanee w pr 5 Sampled not 100 tested Test Conditions Unmeasured pins returned to GND fe 1 MHz A C CHARACTERISTICS Ta 0 to 70 C 5V 10 GND OV Ta 40 C to 85 C for Extended Temperature BUS PARAMETERS READ CYCLE Parameter Min tan Address Stable Betore ADJ in Address
64. d at the edges and do not touch the components or connectors Before installing the board in your computer check the jumper and switch settings Chapter 1 reviews the factory settings and how to change them If you need to change any settings refer to the appropriate instructions in Chapter 1 Note that incompatible jumper settings can result in unpredictable board operation and erratic response To install the board 1 2 Turn OFF the power to your computer Remove the top cover of the computer housing refer to your owner s manual if you do not already know how to do this Select any unused short or full size expansion slot and remove the slot bracket 4 Touch the metal housing of the computer to discharge any static buildup and then remove the board from its antistatic bag Holding the board by its edges orient it so that its card edge bus connector lines up with the expansion slot connector in the bottom of the selected expansion slot After carefully positioning the board in the expansion slot so that the card edge connector is resting on the computer s bus connector gently and evenly press down on the board until it is secured in the slot NOTE Do not force the board into the slot If the board does not slide into place remove it and try again Wiggling the board or exerting too much pressure can result in damage to the board or to the computer After the board is installed secure the slot bracket ba
65. ded from a table that exists in the lowest 1024 bytes of memory This table is referred to as the interrupt vector table and each entry is called an interrupt vector Once the new CS and IP are loaded from the interrupt vector table the processor begins executing the code located at CS IP When the interrupt routine is completed the CS IP and flags that were pushed on the stack when the interrupt occurred are now popped from the stack and execution resumes from the point where it was interrupted Using Interrupts in Your Programs Adding interrupts to your software is not as difficult as it may seem and what they add in terms of performance is often worth the effort Note however that although it is not that hard to use interrupts the smallest mistake will often lead to a system hang that requires a reboot This can be both frustrating and time consuming But after a few tries you ll get the bugs worked out and enjoy the benefits of properly executed interrupts In addition to reading the following paragraphs study the INTRPTS source code included on your program disk for a better understanding of interrupt program development Writing an Interrupt Service Routine ISR The first step in adding interrupts to your software is to write the interrupt service routine ISR This is the routine that will automatically be executed each time an interrupt request occurs on the specified IRQ An ISR is different than standard routines that you writ
66. e First on entrance the processor registers should be pushed onto the stack BEFORE you do anything else Second just before exiting your ISR you must clear the interrupt status of the board and write an end of interrupt command to the 8259 controller Finally when exiting the ISR in addition to popping all the registers you pushed on entrance you must use the IRET instruction and not a plain RET The IRET automatically pops the flags CS and IP that were pushed when the interrupt was called If you find yourself intimidated by interrupt programming take heart Most Pascal and C compilers allow you to identify a procedure function as an interrupt type and will automatically add these instructions to your ISR with one important exception most compilers do not automatically add the end of interrupt command to the procedure you must do this yourself Other than this and the few exceptions discussed below you can write your ISR just like any other routine It can call other functions and procedures in your program and it can access global data If you are writing your first ISR we recommend that you stick to the basics just something that will convince you that it works such as incrementing a global variable NOTE If you are writing an ISR using assembly language you are responsible for pushing and popping registers and using IRET instead of RET There are a few cautions you must consider when writing your ISR The most important is do not
67. e 10 Channei 2 11 cascade 11 Channel 3 Offset Counter 0 increment Read Write 1 decrement 01 write 10 read not used with 2210 2310 Programming the DMA Controller To program the DMA controller follow these steps 1 Clear the byte pointer flip flop 2 Disable DMA on the channel you are using 3 Write the DMA mode register to choose the DMA parameters 4 Write the LSB of the page offset of your buffer 5 Write the MSB of the page offset of your buffer 6 Write the LSB of the number of bytes to transfer 7 Write the MSB of the number of bytes to transfer 8 Enable DMA on the channel you are using Programming the Board for DMA Once you have set up the DMA controller you must program the board for DMA The following steps list this procedure 1 Set up the 8255 PPI for Port B output 2 Set up the timer counters for the desired transfer rate 3 Enable DMA and external trigger 4 Monitor DMA done bit NOTE If the DMA is set up in the single transfer mode each DMA transfer takes two read cycles to com plete Therefore in single transfer you can run the board at speeds up to about 100 kHz so the DMA transfer rate can keep up with the board s conversion rate The demand mode supports even higher transfer rates However rates faster than 125 kHz even in the demand mode may give unreliable results 4 25 Monitoring for Done There are two ways to monitor for DMA done The
68. e Programming Sequences Read Operations It is often desirable to read the value of a Counter without disturbing the count in progress This is easi ly done in the 82C54 There are three possible methods for reading the counters a simple read operation the Counter 3 88 Latch Command and the Read Back Command Each is explained below The first method is to per torm a simple read operation To read the Counter which is selected with the A1 AO inputs the CLK input of the selected Counter must be inhibited by using either the GATE input or external logic Other wise the count may be in the process of changing when it is read giving an undefined result intel 82 54 COUNTER LATCH COMMAND The second method uses the Counter Latch Com mand Like a Control Word this command is written to the Contro Word Register which is selected when As Ag 11 Also like a Control Word the SCO SC1 bits select one of the three Counters but two other bits D5 and DA distinguish this command from a Control Word Ay Ap 11 CS 0 RD 1 WR 0 D7 Ds D4 D Dy Do sci x x 5 1 5 0 specify counter be latched SC1 SCO Counter Read Back Command 05 04 00 designates Counter Latch Command X don t care NOTE Don t care bits X should be 0 to insure compatibility with future Intel products Figure 9 Counter Latching Command Format The selected Counter s outp
69. e oftwo ways by using the microprocessor or by using direct memory access Data bus transfers take more processor time to execute They use polling and interrupts to determine when data has been acquired and is ready for transfer DMA places data directly into the PC s memory one byte at a time with minimal use of processor time DMA transfers are managed by the DMA controller as a background function of the PC letting you operate at higher throughput rates The maximum throughput rate of the board is 125 kHz D A Converters ADA Boards Only Two independent 12 bit analog output channels are included on the ADA2210 and ADA2310 The analog outputs are generated by two 12 bit D A converters with independent jumper selectable output ranges of 5 10 0 to 5 or 0 to 10 volts The 10 volt range has a resolution of 4 88 millivolts the 5 and 0 to 10 volt ranges have a resolution of 2 44 millivolts and the 0 to 5 volt range has a resolution of 1 22 millivolts Timer Counters An 8254 programmable interval timer provides three 16 bit 8 MHz timer counters to support a wide range of timing and counting functions Two of the timer counters TCO and are cascaded so that they can be used for the pacer clock The pacer clock is described in Chapter 4 You can use the remaining timer counter TC2 for counting applications or cascade it to TCO and for timing applications Figure 3 2 shows the timer counter circuitry COU
70. e three pairs of pins labeled CLK2 These pins are used to select the clock source for TC2 OUT connects the output of TC1 the pacer clock output to the clock input of TC2 Installing a jumper here cascades all three timer counters a feature necessary when using SIGNAL MATH or SIGNAL VIEW software for data acquisition and control XTAL is the on board 8 MHz clock and XCK is connected to the same external clock source as CLKO XCK 2 45 The next group of pins on this header PCLK lets you use the on board internal pacer clock or an external pacer clock connected through the TRIGGER IN pin on the I O connector P2 39 to control A D conversions A jumper must be placed on PCK in order to use the internal pacer clock output from TC1 Or you can place the jumper across XTRIG and connect any external pacer clock source to P2 39 to trigger the A D converter The TRIG pins select the hardware source used to trigger the burst mode when the external trigger enable bit at BA 5 is enabled Bursts can be triggered from one of three hardware sources XTRIG an external trigger signal routed onto the board through P2 39 OUT2 the output from timer counter 2 or EG2 an external gate EXT GATE 2 signal routed onto the board through P2 46 When the trigger enable bit at BA 5 is disabled bursts are triggered through software The last group of pins GT2 select the gate source for timer counter 2 s gate input This jumper is provided so that you can d
71. ed Bipolar conversions are in twos complement form and unipolar conversions are straight binary When a bipolar value is read you must first convert the result to straight binary and then calculate the voltage The conversion formula is simple for values greater than 2047 you must subtract 4096 from the value to get the sign of the voltage For example if your output is 2048 you subtract 4096 2048 4096 2048 This result corresponds to 5 volts or 10 volts depending on your binary range For values of 2047 or less you simply convert the result The key digital codes and their input voltage values are given for each range in the three tables which follow 5V twos complement Input Voltage 14 908 volts 72 500 volts 00244 volts 5 000 volts 1 LSB 2 44 millivolts 10V twos complement Input Voltage 9 995 volts 5 000 volts 00488 volts 10 000 volts 1 LSB 4 88 millivolts 0 to 10V straight binary Input Voltage 3 99756 volts 75 00000 volts 1 LSB 2 44 millivolts 4 16 Programming the Pacer Clock Two of the three 16 bit timer counters in the 8254 programmable interval timer are cascaded to form the on board pacer clock shown in Figure 4 6 When you want to use the pacer clock for continuous A D conversions you must program the clock rate To find the value you must load into the clock to produce the desired rate you first have to calculate the value of
72. ee Chapter 1 or system contention will result NOTE When cascading boards the sampling uncertainty is less than 50 nanoseconds If this level of uncer tainty is too great for your application you can connect the trigger signal to the trigger input of each board In this configuration the boards are not cascaded but rather driven by the same trigger pulse at the same time and the sampling uncertainty is reduced to less than 5 nanoseconds If you apply an external trigger to the board s trigger in pin note that a jumper should be installed on PCLK XTRIG on P3 see Chapter 1 The board is triggered on the positive edge of the pulse and the pulse duration should be at least 100 nanoseconds 2 5 CONNECTOR P2 BOARD 1 MASTER BOARD 2 SLAVE SIGNAL x SOURCE 2 our Fig 2 4 Cascading Two Boards for Simultaneous Sampling Connecting the Analog Outputs ADA Boards Only For each of the two D A outputs connect the high side of the device receiving the output to the AOUT channel P2 17 or P2 19 and connect the low side of the device to an ANALOG GND P2 18 or P2 20 Connecting the Timer Counters and Digital For all of these connections the high side of an external signal source or destination device is connected to the appropriate signal pin on the P2 I O connector and the low side is connected to any DIGITAL GND Running the 2210DIAG Diagnostics Program Now that your board is ready
73. ens to bits 6 and 7 but we can say for sure that bit 5 ends up cleared instead of being set A similar problem happens when you use subtraction to clear a bit in place of the method shown above Now that you know how to clear and set bits we are ready to look at the programming steps for the board functions 4 11 Conversions The following paragraphs walk you through the programming steps for performing A D conversions Detailed information about the conversion modes is presented in this section You can follow these steps on the flow dia grams at the end of this chapter and in our example programs included with the board In this discussion BA refers to the base address Initializing the 8255 PPI The eight Port B lines of the 8255 PPI control the channel selection programmable gain programmable IRQ and external trigger and DMA enable Port is programmed at I O address location BA 5 Analog Input IRQ Enable Channel Select 0 IRQ disabled 0000 channel 1 1000 channel 9 1 IRQ enabled 0001 channel2 1001 channel 10 Channel Gain 0010 channel3 1010 channel 11 EXT TRIG 00 x1 0011 channel 4 1011 channel 12 Enable 01 x2 0100 channel 5 1100 channel 13 0 Disabled 10 4 0101 channel 6 1101 channel 14 1 Enabled 11 x8 0110 channel 7 1110 channel 15 0111 channel 8 1111 channel 16 To use Port B for these control functions the 8255 must be initialized so that
74. es 1 2 3 and 5 the GATE input is rising edge sensitive In these Modes a rising edge of GATE trigger sets an edge sensi tive flip flop in the Counter This flip flop is then sam pled on the next rising edge of CLK the flip flop is reset immediately after it is sampled this trigger will be detected no matter when it occurs a high logic level does not have to be maintained until the next rising edge of CLK Note that in Modes 2 and 3 the GATE input is both edge and level sensi tive In Modes 2 and 3 if a CLK source other than the system clock is used GATE should be pulsed immediately following WR of a new count value COUNTER New counts are loaded and Counters are decre mented on the falling edge of CLK The largest possible initial count is 0 this is equiva lent to 216 for binary counting and 104 for BCD counting The Counter does not stop when it reaches zero In Modes 0 1 4 and 5 the Counter wraps around to the highest count either FFFF hex for binary count ing or 9999 for BCD counting and continues count ing Modes 2 and 3 are periodic the Counter reloads itself with the initial count and continues counting from there 3 95 intel 82054 ABSOLUTE MAXIMUM RATINGS Notice Stresses above those listed under Abso lute Maximum Ratings may cause permanent dam Ambient Temperature Under Bias 0 C to 70 age to the device This is a stress rating only and Storage Te
75. espond to RD and WR signals RD and WR are ignored otherwise Read Control This input is low during CPU read operations Write Control This input is low during CPU write operations Voc 24 28 Power power supply connection t151525 NoComet Counter 0 Counter 1 9 FUNCTIONAL DESCRIPTION sired delay After the desired delay the 82C54 will interrupt the CPU Software overhead is minimal and variable length delays can easily be accommodated Genera Some of the other counter timer functions common The 82 54 is a programmable interval timer counter to microcomputers which be implemented with designed for use with Intel microcomputer systems the 82 54 are It is a general purpose multi timing element that can be treated as an array of I O ports in the system software Real time clock Even counter Digital one shot Programmable rate generator Square wave generator Binary rate multiplier Complex waveform generator Complex motor controller The 82C54 solves one of the most common prob lems in any microcomputer system the generation of accurate time delays under software control In stead of setting up timing loops in software the pro grammer configures the 82C54 to match his require ments and programs one of the counters for the de 3 84 82 54 Block Diagram DATA BUS BUFFER This 3 state bi directional 8 bit buffer i
76. f count 20000 a a a 2 020002 gt NOTE struction sequence is required Any programming sequence that follows the conventions above is ceptable A new initial count may be written to a Counter at any time without affecting the Counter s pro grammed Mode in any way Counting will be affected as described in the Mode definitions The new count must follow the programmed count format If a Counter is programmed to read write two byte counts the following precaution applies A program must not transfer control between writing the first and second byte to another routine which also writes into that same Counter Otherwise the Counter will be loaded with an incorrect count Control Word Control Word Control Word LSB of count MSB of count LSB of count MSB of count LSB of count MSB of count Counter 2 Counter 1 Counter 0 Counter 2 Counter 2 Counter 1 Counter 1 Counter 0 Counter 0 00001 2 1 o0o 00 gt Control Word Control Word LSB of count Control Word LSB of count MSB of count LSB of count MSB of count MSB of count Counter 1 Counter 0 Counter 1 Counter 2 Counter 0 Counter 1 Counter 2 Counter 0 Counter 2 0 200 0 gt 200020229 In all four examples all counters are programmed to read write two byte counts These are only four of many possible programming sequences Figure 8 A Few Possibl
77. features These examples are written in C Pascal and BASIC Also included is an easy to use menu driven diagnostics program 2210DIAG which is especially helpful when you are first checking out your board after installation and when calibrating the board Chapter 5 Before using the software included with your board make a backup copy of the disk You may make as many backups as you need C and Pascal Programs These programs are source code files so that you can easily develop your own custom software for your board In the C directory 2210 H and 2210 INC contain all the functions needed to implement the main C programs H defines the addresses and INC contains the routines called by the main programs In the Pascal directory 2210 PNC contains all of the procedures needed to implement the main Pascal programs Analog to Digital SOFTTRIG Demonstrates how to use the software trigger mode for acquiring data EXTTRIG Similar to SOFTTRIG except that an external trigger is used MULTI Shows how to fill an array with data using a software trigger Timer Counters TIMER A short program demonstrating how to program the 8254 for use as a timer Digital VO DIGITAL Simple program that shows how to read and write the digital I O lines Digital to Analog DAC Shows how to use the DACs Uses A D channel 1 to monitor the output of DACI WAVES A more complex program that shows how to use the 8254 timer and the DACs as a waveform generator I
78. fore the current count expires the Counter will be loaded with the new count on the next CLK pulse and counting will continue from there Fe 0 MESE 11 4 o 3 CWz A 68 3 11 11 lel CWs A 5843 158 5 N N N alalsloleristisia 231244 13 Figure 20 Mode 5 82 54 Signal Low Status Or Going Disables Enables counting counting 1 Initiates counting 2 Resets output after next clock 1 Disables counting Initiates Enables 2 Sets output counting counting immediately high 1 Disables counting 2 Sets output immediately high Disables Enables counting counting Initiates counting Enables counting Initiates counting Figure 21 Gate Pin Operations Summary MIN MAX Moe Sor 0 is equivalent to 216 for binary counting and 104 for BCD counting Figure 22 Minimum and Maximum initial Counts Operation Common to All Modes Programming When a Control Word is written to a Counter all Control Logic is immediately reset and OUT goes to a known initial state no CLK pulses are required for this GATE The GATE input is always sampled on the rising edge of CLK In Modes 0 2 3 and 4 the GATE input is level sensitive and the logic level is sampled on the rising edge of CLK In Mod
79. ge of bits is a mixture of setting and clearing operations You can set or clear each bit individually or use a faster method of first clearing all the bits in the range then setting only those bits that must be set using the method shown above for setting multiple bits in a port The following example shows how this two step operation is done Example Assign bits 3 4 and 5 in a port to 101 bits 3 and 5 set bit 4 cleared First read in the port and clear bits 3 4 and 5 by ANDing them with 199 Then set bits 3 and 5 by ORing them with 40 and finally write the resulting value back to the port In C this is programmed as v inportb port address v v amp 199 40 outportb port_address final note Don t be intimidated by the binary operators AND and and try to use operators for which you have a better intuition For instance if you are tempted to use addition and subtraction to set and clear bits in place of the methods shown above DON T Addition and subtraction may seem logical but they will not work if you try to clear a bit that is already clear or set a bit that is already set For example you might think that to set bit 5 of a port you simply need to read in the port add 32 2 to that value and then write the resulting value back to the port This works fine if bit 5 is not already set But what happens when bit 5 is already set Bits 0 to 4 will be unaffected and we can t say for sure what happ
80. gt 10011010 10011011 154 155 Input g n Set Reset Bit Set Reset Function Bit O set bit to O 0 active Bit Select 1 set bit to 1 000 001 PC1 010 2 PC2 011 100 4 101 5 110 6 111 PC7 4 7 For example if you want to set Port C bit 0 to 1 you would set up the control word so that bit 7 is 0 bits 1 2 and 3 are 0 this selects PCO and bit 0 is 1 this sets PCO to 1 The control word is set up like this 0 X X X 0 0 0 1 Sets PCO to 1 written to BA 7 X don t care Set Reset Set PCO Function Bit Bit Select 000 PCO 8 8254 Timer Counter 0 Read Write A read shows the count in the counter and a write loads the counter with a new value Counting begins as soon as the count is loaded This counter is cascaded with TC1 to form the 32 bit on board pacer clock BA 9 8254 Timer Counter 1 Read Write A read shows the count in the counter and a write loads the counter with a new value Counting begins as soon as the count is loaded This counter is cascaded with TCO to form the 32 bit on board pacer clock BA 10 8254 Timer Counter 2 Read Write read shows the count in the counter and a write loads the counter with a new value Counting begins as soon as the count is loaded This counter be cascaded to TCO and or it can be used independently BA 11 8254 Control Word Write Only Accesses the 8254 contr
81. he CPU DIT SETMESET The interrupt request signals generated from port C can be inhibited or enabled by setting or resetting the associated INTE flip flop using the bit set reset BIT SELECT function of port C JABODEDA 011 011 0 1 011 60 This function allows the Programmer to disallow or Bes At allow a specific 1 device to interrupt the CPU with out affecting any other device in the interrupt struc ture INTE flip flop definition 231256 7 BIT SET INTE is SET Interrupt enable is RESET Interrupt disable Figure 7 Bit Set Reset Format Note All Mask flip flops are automatically reset during mode selection and device Reset 3 129 intel 82 55 Operating Modes Mode 0 Basic Input Output This functional con figuration provides simple input and output opera tions for each of the three ports No handshaking is required data is simply written to or read from a specified port MODE 0 BASIC INPUT Mode 0 Basic Functional Definitions Two 8 bit ports and two 4 bit ports Any port be input or output Outputs are latched Inputs are not latched 16 different Input Output configurations are pos sible in this Mode ee a _ gE a tao MODE 0 BASIC OUTPUT 3 130 pr 231256 8 231256 9 intel 82C55A MODE 0 Port Definition GRoupA GROUP B PORT PORT PORTA
82. he count it is the OL that is being read Similarly there are two 8 bit registers called CRm and CR for Count Register Both are normally referred to as one unit and called just CR When a new count is written to the Counter the count is 3 86 stored in the CR and later transferred to the CE The Control Logic allows one register at a time to be loaded from the internal bus Both bytes are trans ferred to the CE simultaneously and CR are cleared when the Counter is programmed In this way if the Counter has been programmed for one byte counts either most significant byte only or least significant byte only the other byte will be zero Note that the CE cannot be written into whenever a count is written it is written into the CR The Control Logic is also shown in the diagram CLK n GATE n and OUT n are all connected to the out side world through the Control Logic 82C54 SYSTEM INTERFACE The 82C54 is treated by the systems software as an array of peripheral 1 ports three are counters and the fourth is a control register for MODE program ming Basically the select inputs Ao Ay connect to the Ag A4 address bus signals of the CPU The CS can be derived directly from the address bus using a linear select method Or it can be connected to the output of a decoder such as an Intel 8205 for larger sys tems A Ay own 82054 COUNTER COUNTER COUNTER 0 1 2 fon py pr OUT GATE CLK OUT GATE
83. hows the board layout and the locations of the factory set jumpers The following paragraphs explain how to change the factory settings Pay special attention to the setting of 51 the base address switch to avoid address contention when you first use your board in your system Table 1 1 Factory Settings Switch Factory Settings Jumper Function Controlled Jumpers Installed Jumpers installed on CLKO XTAL CLK2 OUT1 PCLK PCK TRIG OUT2 GT2 EG2 Sets the clock sources for the 8254 timer counters selects A D trigger source selects GATE 2 source Jumper installed on G ground for buffer interrupt channels Connects one of four software selectable interrupt sources to an interrupt channel pulls tri state buffer to ground G for multiple interrupt applications disabled Sets the DMA request DRQ and DMA acknowledge DACK channel Disabled Sets the D A output voltage range for DAC 1 P7 Sets the D A output voltage range for DAC 2 5 to 5 volts P8 Sets the analog input voltage range and polarity 5 to 5 volts P Sets the state of the top 4 bits the bits not used by the 12 bit Bipolar converter of the 16 bit A D output word must be the same as P8 Single ended jumpers installed P10 Selects single ended or differential analog input type on three SE pins Sets the base address 300 hex 768 decimal BASE ADORESS oooon aa Be B ias premens a CE
84. hree basic modes of operation that can be selected by the system software Mode 0 Basic input output Mode 1 Strobed Input output Mode 2 Bi directional Bus When the reset input goes high all ports will be set to the input mode with all 24 port lines held at a logic one level by the internal bus hold devices see Figure 4 Note After the reset is removed the 82C55A can remain in the input mode with no addi tional initialization required This eliminates the need for pullup or pulldown devices in all CMOS de signs During the execution of the system program any of the other modes may be selected by using a single output instruction This allows a single 82C55A to service a variety of peripheral devices with a simple software maintenance routine The modes for Port A and Port can be separately defined while Port C is divided into two portions as required by the Port A and Port B definitions All of the output registers including the status flip flops will be reset whenever the mode is changed Modes may be combined so that their functional definition can be tailored to almost 1 structure For instance Group B can be programmed in Mode 0 to monitor simple switch closings or display computa tional results Group A could be programmed Mode 1 to monitor a keyboard or tape reader on an interrupt driven basis PB 8 CONTROL CONTROL OR VO me A 170 BI DIRECTIONAL Pe
85. ing measurements are made at 2 0V tor a logic 1 and 0 8V for a logic 0 231244 19 150 pF C includes Jig capacitance 3 99 Intel 82C55A Programmable Peripheral Interface Data Sheet Reprint P Intel 82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE B Compatible with all Intel and Most m Control Word Read Back Capability Other Microprocessors Direct Bit Set Reset Capability m High Speed Zero Wait State bil Operation with 8 MHz 8086 88 E 80186 188 i Pi 44 m 24 Programmable 1 Pins m Available in 40 DIP and 44 Pin PLCC m Available in EXPRESS Low Power CHMOS Standard Temperature Range m Completely TTL Compatible Extended Temperature Range The Intel 82 55 is a high performance CHMOS version of the industry standard 8255A general purpose programmable 1 device which is designed for use with all Intel and most other microprocessors It provides 24 1 0 pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation The 82C55A is pin compatible with the NMOS 8255A and 8255A 5 In MODE 0 each group of 12 1 pins may be programmed in sets of 4 and 8 to be inputs or outputs In MODE 1 each group may be programmed to have 8 lines of input or output 3 of the remaining 4 pins are used for handshaking and interrupt control signals MODE 2 is a strobed bi directional bus configuration
86. ining your IRQ s bit After setting the bit write the new value to VO port 21H With the startup IMR saved and the interrupts on your IRQ temporarily disabled you can assign the interrupt vector to point to your ISR Again you can overwrite the appropriate entry in the vector table with a direct memory write but this is a bad practice Instead use either DOS function 25H set interrupt vector or if your compiler provides it the library routine for setting an interrupt vector Remember that vector 8 is for IRQO vector 9 is for IRQ1 and so on 4 20 If you need to program the source of your interrupts do that next For example if you are using the program mable interval timer to generate interrupts you must program it to run in the proper mode and at the proper rate Finally clear the bit in the IMR for the IRQ you are using This enables interrupts on the IRQ Restoring the Startup IMR and Interrupt Vector Before exiting your program you must restore the interrupt mask register and interrupt vectors to the state they were in when your program started To restore the IMR write the value that was saved when your program started to I O port 21H Restore the interrupt vector that was saved at startup with either DOS function 35H get interrupt vector or use the library routine supplied with your compiler Performing these two steps will guarantee that the interrupt status of your computer is the same after running
87. ion Flow Diagram ccccscsssscsecsssessseseseeeseeesseseseseseseseesnsasscssseseseseacscacstsesescavavevsceeaees 4 31 DMA Flow Diagram a page elect 4 32 Scan Pow bruce 4 33 Interrupts Flow Diagram neuster i dn 4 34 D A Conversion Flow Diagram enennsesssesesssssnenssonsnenenssessnnnnnsnenennnnnennnennnnennnanenenenennannunnnenennnnsnnnenannn 4 35 Board Layout EE 5 3 INTRODUCTION The 2210 and 2310 Advanced Industrial Control boards turn your IBM or compatible into high speed high performance data acquisition and control system Both the 2210 and 2310 are functionally identical with the 2310 requiring 5 volts only for operation Installed within a single expansion slot in the computer each 2210 2310 series board features 8 differential or 16 single ended analog input channels 12 bit 5 microsecond analog to digital converter with 125 kHz throughput 5 10 or 0 to 10 volt input range Programmable gains of 1 2 4 and 8 with an on board gain multiplier circuit Programmable automatic channel scanning Programmable burst mode DMA transfer Trigger in and trigger out for external triggering or cascading boards 16 TTL CMOS 8255 based digital I O lines which can be configured with pull up or pull down resistors Three 16 bit timer counters two cascaded for pacer clock
88. isconnect the GATE input for the third timer counter from the EXT GATE 2 pin at the I O connector and tie the gate high if you are using the EXT GATE 2 pin as a trigger source P3 XTAL XCK OUT1 XTAL XCK PCK PCLK CLK2 XTRIG XTRIG OUT2 EG2 EG2 45V TRIG Fig 1 2 8254 Timer Counter Sources Jumpers P3 I I CONNECTOR 1 CLKO P2 1 l 46 8 MHz 1 1 CLOCK PIN 45 EXT CLK COUNTER xum Q 0 i ane PIN 41 GATE 1 l 1 1 I 1 I I I l 1 1 I I l timer 1 1 COUNTER CLK 1 1 I 1 I GATE J our I PIN 42 AT C OUT 1 l I I I I l cu l eta O O 8 MHz I TIMER 1 Shock COUNTER CLK 0 2 l 1 PIN 44 OUT 2 l i pelk gen 1 O PIN 39 TRIGGER IN TRIG 1 Cae 1 1 O O i O TRIGGER 5 1 46 2 INPUT I GT2 i r 6 1 OS v I ccce Fig 1 3 8254 Timer Counter Circuit Diagram P4 Interrupt Channel Select Factory Setting Jumper G Interrupt Channel Disabled This header connector shown in Figure 1 4 lets you connect any one of four software selectable interrupt sources to any of six interrupt channels IRQ2 highest priority channel through IRQ7 lowest priority channel To activate a channel you must insta
89. it as pull ups or pull downs Locate the three hole pads on the board below the resistor packs They are labeled G for ground on one end and V for 45V on the other end The middle hole is common PA is for Port A PCL is for Port C Lower and PCH is for Port C Upper Figure 1 13 shows these pads To operate as pull ups solder a jumper wire between the common pin middle pin of the three and the V pin For pull downs solder a jumper wire between the common pin middle pin and the G pin Figure 1 14 shows Port A lines with pull ups Port C Lower with pull downs and Port C Upper with no resistors 000000 2 55 000000 22 28 786 roms 4 N 5 ERE 5562 0079 20000000000000 end s 0000060 000000000000 741 574 0000 vo 741 574 000000 000000 00000000 00000000 oum oo oo 00 00 00000000 000000 0000000000 00000000 21090000900 o ee 0000 De 5 Dre Boe og 0 9000000000 0000000000 3000000000 9 9 E Oe eam CD CD CDA Fig 1 13 Pull up Pull down Resistor Circuitry 1 11 00000000 onm 00000000 0 7 Fig 1 14 Adding Pull ups and Pull downs t
90. k register IMR and how to send the end of interrupt EOI command to the 8259 Interrupt Mask Register IMR Each bit in the interrupt mask register IMR contains the mask status of an IRQ line bit 0 is for IRQO bit 1 is for IRQ and so on If a bit is set equal to 1 then the corresponding IRQ is masked and it will not generate an interrupt If a bit is clear equal to 0 then the corresponding IRQ is unmasked and can generate interrupts The IMR is programmed through port 21H mar as es as nes oo voran For all bits IRQ unmasked enabled 1 IRQ masked disabled End of Interrupt EOD Command After an interrupt service routine is complete the 8259 interrupt controller must be notified This is done by writing the value 20H to VO port 20H What Exactly Happens When an Interrupt Occurs Understanding the sequence of events when an interrupt is triggered is necessary to properly write software interrupt handlers When an interrupt request line is driven high by a peripheral device such as the 2210 2310 the 4 18 interrupt controller checks to see if interrupts are enabled for that IRQ and then checks to see if other interrupts are active or requested and determines which interrupt has priority The interrupt controller then interrupts the proces sor The current code segment CS instruction pointer IP and flags are pushed on the stack for storage and a new CS and IP are loa
91. ll a jumper vertically across the desired IRQ channel Figure 1 4a shows the factory setting Figure 1 4b shows the interrupt source connected to IRQ3 When jumpered the leftmost pair of pins on P4 labeled G connects a pull down resistor to the output of a high impedance tri state driver which carries the interrupt request signal This pull down resistor drives the interrupt request line low whenever interrupts are not active Whenever an interrupt request is made the tri state buffer is enabled forcing the output high and generating an interrupt You can monitor the interrupt status through bit 2 in the status word I O address location BA 0 After the interrupt has been serviced the reset command returns the IRQ line low disabling the tri state buffer and pulling the output low again Figure 1 5 shows this circuit Because the interrupt request line is driven low only by the pull down resistor you can have two or more boards which share the same IRQ channel You can tell which board issued the interrupt request by monitoring each board s IRQ status bit NOTE When you use multiple boards that share the same interrupt only one board should have the G jumper installed The rest should be disconnected Whenever you operate a single board the G jumper should be installed 1 5 oe c Oo QN gt qu 4 4 Fig 1 4a IRQ Disabled Fig 1 4b IRQ3 Selected Fig 1 4 Interrupt Channel Jumper P4 INT SOURCE IRQ STA
92. m 00000 cu ooooooooooooon pct 22 00 000 829 7 cao 005 000 00000000000000 6 0 8 onn cas 000000000000 y Utt ooooooooonrcy ooooooooon n wooooooo 99990900000 000 00105 000000 5555 3000089 ze EAM 00000000 00000000 3 FERE 333322 amp I O O O O O O 25 99 82C55 25 00000000 0000000000 u7 77775 kt 9000000000 0000000000 0000000000 prore ___ eprweme __ ehrsene 99 0000000000 0000000000 9 221072310 e OD 00 Go Copyright 893 Real Time Devices Inc et Fig 1 1 Board Layout Showing Factory Configured Settings 1 3 P3 8254 Timer Counter Sources Factory Settings See Table 1 1 amp Figure 1 2 This header connector shown in Figure 1 2 lets you select the clock sources for the 8254 timer counters TCO and 2 TCO and are cascaded to form the pacer clock This header is also used to configure the pacer clock input trigger input and GATE 2 sources Figure 1 3 shows a block diagram of the timer counter circuitry to help you in making these connections The clock source for TCO and is selected by placing a jumper on XTAL or XCK in the CLKO section of the header XTAL is the on board 8 MHz clock and XCK is an external clock source you can connect through the external I O connector P2 45 Below the CLKO pins ar
93. mida 4 18 Interrupt Request Lines eese 4 18 8259 Programmable Interrupt Controller uenessssssssesusnsnsesesssssnsnnnsunnnenesnensnsnonennsnnnnsnnosennnensssnnsnnenssnnnennn 4 18 Interrupt Mask Register ia a eo eeik Siei aei 4 18 End of Interrupt EOD Command ccecescssescsssessesssscsscssesesseseessessscesscscsecsacusscsscecsessssevsesensenecenseeseceaenace 4 18 What Exactly Happens When an Interrupt Occurs eese 4 18 Using Interrupts in Your Programs 4 19 Writing an Interrupt Service Routine ISR eese sete tntnttrtetne tete teens 4 19 Saving the Startup Interrupt Mask Register IMR and Interrupt Vector 4 20 Restoring the Startup IMR and Interrupt Vector eese 4 21 Common Interrupt Mistakes 0422444 eese ente entente shine rats 4 21 Data Transfers Using DMA essen anlagen ano soon tada 4 21 Choosing a DMA Channel 4 21 Allocating a DMA Buffer ans 4 22 Calculating the Page and Offset of a Buffer 4 22 Setting the DMA Page 4 24 The DMA C
94. ming The table below shows you some of the operators discussed in this section with an example of how each is used with Pascal C and BASIC Note that the modulus operator is used to retrieve the least significant byte LSB of a two byte word and the integer division operator is used to retrieve the most significant byte MSB amp a b c a b c a b amp c MOD DIV AND OR a bMODc a bDIVc a bANDc a bORc BASIC MOD backslash AND OR a bMODc a b c a bANDc azbORc Many compilers have functions that can read write either 8 or 16 bits from to an I O port For example Turbo Pascal uses Port for 8 bit port operations and PortW for 16 bits Turbo C uses inportb for an 8 bit read of a port and inport for a 16 bit read Be sure to use only 8 bit operations with the 2210 and 2310 Clearing and Setting Bits in a Port When you clear or set one or more bits in a port you must be careful that you do not change the status of the other bits You can preserve the status of all bits you do not wish to change by proper use of the AND and OR binary operators Using AND and OR single or multiple bits can be easily cleared in one operation To clear a single bit in a port AND the current value of the port with the value b where b 255 m Example Clear bit 5 in a port Read in the current value of the port AND it with 223 223 255 25 and then write the resulting value to the port In BASIC this is programmed as
95. mperature 65 to 150 C functional operation of the device at these or any Supply Voltage 0 5to 8 0V other conditions above those indicated in the opera Operating Voltage 4Vto 7V tional sections of this specification is not implied Ex Voltage any GND 2Vto 6 5V posure to absolute maximum rating conditions for Voltage on any Output GND 0 5V to Vcc 0 5V extended periods may affect device reliability Power Dissipation 1 Watt CHARACTERISTICS Ta 0 C to 70 C Voc 5V 10 GND 0V TA 40 C to 85 C for Extended Temperature symbol Parameter Max Unte TestConditions vea 08 N input Voltage 20 veros V Vo voltage os VL ip 25mA 0 4 V lon 100 pA Pix input Load Current 20 pa Mor Output Float Leakage Curent 10 A Vour Vooto0 0V Voc Supply Current mA 8MHz 82054 10MHz 82C54 2 Vcc Supply Current Standby ICCSP1 Vcc Supply Current Standby CLK Freq DC CS All Other Inputs Pins Van Outputs Open Input Capacitance 1 Capacitance Output Capacitance CHARACTERISTICS Ta 0 C to 70 C Voc 5V 10 GND 0V TA 40 C to 85 C for Extended Temperature BUS PARAMETERS Note 1 READ CYCLE 0 te Mn Me Mm Address Stable
96. n be either set or reset Port C lines programmed as inputs including ACK and STB lines associated with Port C are not affected by a Set Reset C Bit command Writing to the corresponding Port C bit positions of the ACK and STB lines with the Set Reset Port C Bit command will affect the Group A and Group B interrupt enable flags as illus trated in Figure 18 Current Drive Capability Any output on Port A B or C can sink or source 2 5 mA This feature allows the 82 55 to directly drive Darlington type drivers and high voltage displays that require such sink or source current 3 139 intel 82C55A Reading Port C Status INPUT CONFIGURATION D De Ds D4 Ds 0 0 Do In Mode 0 Port C transfers data to or from the pe INTE INTRA INTER IBFe INTR ripheral device When the 82C55A is programmed to function in Modes 1 or 2 Port C generates or ac UPA GROUP B cepts hand shaking signals with the peripheral de vice Reading the contents of Port allows the pro OUTPUT SUN TORE grammer to test or verify the status of each pe De Ds Dg D3 Do ripheral device and change the program flow ac olvoliNTRA INTE INTR cordingly er ie vo or res rea GROUP A GROUP B There is no special instruction to read the status in formation from Port C A normal read operation of Figure 17a MODE 1 Status Word Format Port C is executed to perform this function De Ds D
97. nels 1011 12 channels 1100 13 channels 1101 14 channels 1110 15 channels 1111 16 channels A read tells you the bit settings BA 4 PPI Port A Digital I O Read Write Transfers the 8 bit Port A digital input and digital output data between the board and an external device A read transfers data from the external device through P2 and into PPI Port A a write transfers the written data from Port A through P2 to an external device BA 5 PPI Port B Channel Gain Board Functions Select Read Write A write programs the analog input channel and gain and enables the IRQ and external trigger Note that because some of the Port B bits are built into the EPLD writing to the 8255 control word does not automatically set the Port B bits to zero as it does in a typical 8255 configuration Therefore you must write a zero to Port B to ensure all bits are zero whenever you desire to reset this port Reading this register shows you the current settings Analog Input Channel Select IRQ Enable 0000 channel 1 1000 channel 9 0 IRQ disabled 0001 channel 2 1001 channel 10 1 IRQ enabled 0010 channel3 1010 channel 11 Channel Gain 0011 channel 4 1011 channel 12 EXT TRIG 00 x1 0100 channel5 1100 channel 13 Enable 01 2 0101 channel 6 1101 channel 14 0 Disabled 10 x4 0110 channel 7 1110 channel 15 1 Enabled 11 8 0111 8 1111 channel 16 BA 6 PPI P
98. ng 4 Except tor Extended Temp See Extended Temp A C Characteristics below 5 Sampled not 100 tested 25 C 6 If CLK present at Twc min then Count equals N 2 CLK pulses Two max equals Count N 1 CLK pulse Twc min to max count will be either N 1 or N 2 CLK pulses 7 In Modes 1 and 5 if GATE is present when writing a new Count value at Twa min Counter will not be triggered at max Counter will triggered 8 If CLK present when writing a Counter Latch or ReadBack Command at min CLK will be reflected in count value latched at Tc max CLK will not be reflected the count value latched Writing a Counter Latch or ReadBack Command between min and max will result in a latched count vallue which is one least significant bit EXTENDED TEMPERATURE Ta 40 C to 85 C for Extended Temperature ee ee two Clk Delay for Loading 25 25 25 25 ms _GateDelaytorSamping 25 25 25 5 ns intel 82C54 WAVEFORMS WRITE DATA BUS 231244 14 DATA BUS 231244 15 RECOVERY 231244 16 3 98 intel 82054 CLOCK AND GATE ta oo 231244 17 Last byte of count being written TESTING INPUT OUTPUT WAVEFORM TESTING LOAD CIRCUIT INPUT OUTPUT DEC 231244 18 A C Testing Inputs are driven at 2 4V for a logic 1 and 0 45V for a logic 0 Tim
99. ng the The I O map for the 2210 and 2310 is shown in Table 4 1 below As shown the board occupies 16 consecutive I O port locations The base address designated as can be selected using DIP switch S1 as described in Chapter 1 Board Settings This switch can be accessed without removing the board from the computer S1 is factory set at 300 hex 768 decimal The following sections describe the register contents of each address used in the I O map Table 4 1 2210 2310 Map Address Register Description Read Function Pone Read Status Start Convert Read status word 0 0 Read converted data LSB first Simultaneously update DAC 1 Read Data Update DACs then MSB and DAC 2 ADA only 1 Resets board so that it is ready Reserved to start A D conversions BA 2 Programs number of scan burst channels enables scan burst Scan Burst Read current settings selects IRQ source BA 3 Program Port A digital output 8255 PPI Port A Read Port A digital input lines lines BA 4 8255 PPI Port B Program channel amp gain Channel Gain Board external trigger enable IRQ Functions Read Port bits enable BA 5 Program Port C digital output ESSE PPI Port C Read Port C CREER input lines lines BA 6 8255 PPI Control Word Control Word Reseved Program PP configuration 8254 Timer Counter O Used for pacer clock Read count value Load count register BA 8 8254 Timer Counter 1 Used for pacer clock
100. nge O IA EA Lese or e gt 5 O 3 5 1 2 6 Fig 1 7 1 Output Voltage Range Jumper P6 P7 DAC 2 Output Voltage Range Factory Setting 5 to 5 volts This header connector shown in Figure 1 8 sets the output voltage range for DAC 2 at 0 to 5 5 0 to 10 or 10 volts Two jumpers must be installed one to select the range and one to select the multiplier The top two jumpers select the range bipolar 5 or unipolar 5 The bottom two jumpers select the multiplier 2 or 1 When a jumper is on the X2 multiplier pins the range values become 10 and 10 The table below shows the four possible combinations of jumper settings and the diagram shows the two bipolar settings This header does not have to be set the same as P6 or o o on ow or om m or ov o on zova X1 X2 P7 Fig 1 8 DAC 2 Output Voltage Range Jumper P7 P8 Analog Input Voltage Range and Polarity Factory Setting 5 to 5 Volts This header connector shown in Figure 1 9 sets the analog input voltage range and polarity Two jumpers are installed to select one of three input ranges as shown in the diagram 5 10 and 0 to 10 volts Note that the jumper on P9 must match the polarity selected on P8 for proper board operation 33 33 33 TES T lt lt lt l
101. nterrupts INTRPTS Shows the bare essentials required for using interrupts INTSTRM A complete program showing interrupt based streaming to disk DMA DMA Demonstrates how to use DMA to transfer acquired data to memory buffer Buffer can be written to disk and viewed with the included VIEWDAT program DMASTRM Demonstrates how to use DMA for disk streaming Very high continuous acquisition rates can be obtained BASIC Programs These programs are source code files so that you can easily develop your own custom software for your board Analog to Digital SINGLE Demonstrates how to use the single convert internal trigger mode for acquiring data EXTTRIG Demonstrates how to use the external trigger to acquire data SCAN Demonstrates how to scan channels to acquire data Timer Counters TIMER A short program demonstrating how to program the 8254 for use as a timer 4 29 Digital VO DIGITAL Simple program that shows how to read and write the digital lines Digital to Analog DASCAN Demonstrates D A conversion DMA DMA Shows how to take samples and transfer them to PC memory using DMA 4 30 Flow Diagrams The following paragraphs provide descriptions and flow diagrams for some of the 2210 2310 s A D and D A conversion functions These diagrams will help you to build your own custom applications programs Single Convert Flow Diagram Figure 4 8 This flow diagram shows you the steps for taking a
102. o Digital I O Lines Gm Gain Multiplier Circuitry The 2210 2310 has software programmable binary gains of 1 2 4 and 8 A gain multiplier circuit Gm is provided so that you can easily configure special gain settings for a specific application Note that when you use this feature and set up the board for a gain of other than 1 all of the input channels will operate only at your custom gain settings In other words if you install circuitry which gives you a gain multiplier of 10 then the four programmable gains available are 10 20 40 and 80 Gm is derived by adding resistors R14 and R15 trimpot TR7 and capacitor C32 all located in the upper center and right areas of the board The resistors and trimpot combine to set the gain as shown in the formula in Fig 1 15 Capacitor C32 is provided so that you can add low pass filtering in the gain circuit If your input signal is a slowly changing one and you do not need to measure it at a higher rate you may want to add a capacitor at C32 in order to reduce the input frequency range and in turn reduce the noise on your input signal The formula for setting the frequency is given in the diagram Figure 1 15 shows how the Gm circuitry is configured As shown in Figure 1 15 a solder short must be removed from the board to activate the Gm circuitry This short is located on the bottom side of the board under U17 AD712 IC Figure 1 16 shows the location of the solder short 1 12 Remove
103. oes low and the Counter is reloaded with the initial count minus one Succeeding CLK pulses decrement the count by two When the count expires OUT goes high again and the Counter is reloaded with the initial count minus one The above process is repeated indefinitely So for odd counts OUT will be high for N 1 2 counts and low for N 1 2 counts 8504 gat 77 7 D USE MER woe trenes cse aa T Iste SE AS CWet 6825 Virus ul JUVUUUVUUVUVUVUL oar eee eec lea ppal TEL E ESTE EE CWs 6824 Inlet 231244 11 GATE transition should not one clock prior to terminal count Figure 18 Mode 3 MODE 4 SOFTWARE TRIGGERED STROBE OUT will be initially high When the initial count ex pires OUT will go low for one CLK pulse and then go high again The counting sequence is triggered by writing the initial count GATE 1 enables counting GATE 0 disables counting GATE has no effect on OUT After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse This CLK pulse does not decrement the count so for an initial count of N OUT does not strobe low until N 1 CLK pulses after the initial count is written If a new count is written during counting it will be loaded on the next CLK pulse and counting will con tinue from the new count If a
104. ol Each 4 bit port contains a 4 bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B PCo 3 14 17 16 19 WO PORTC PINS 0 3 Lower nibble of Port C PBo 7 20 22 VO PORT B PINS 0 7 An 8 bit data output latch buffer and an 8 24 28 bit data input buffer vec 26 29 SYSTEMPOWER 5V Power Supply 07 0 27 34 DATA BUS Bi directional tri state data bus lines connected to system data bus RESET RESET A high on this input clears the control register and all ports are set to the input mode WR WRITE CONTROL This input is low during CPU write operations PA7_4 37 40 41 44 PORT A PINS 4 7 Upper nibble of 8 bit data output latch buffer and an 8 bit data input latch 1 12 No Connect 23 34 3 125 osa inte 82C55A 82C55A FUNCTIONAL DESCRIPTION General The 82C55A is a programmable peripheral interface device designed for use in Intel microcomputer sys tems Its function is that of a general purpose 1 component to interface peripheral equipment to the microcomputer system bus The functional configu ration of the 82C55A is programmed by the system software so that normally no external logic is neces sary to interface peripheral devices or structures Data Bus Buffer This 3 state bidirectional 8 bit buffer is used to inter face the 82C55A to the system data b
105. ol register to directly control the three timer counters BCD Binary 0 binary 1 BCD Counter Select 00 Counter 0 01 Counter 1 Counter Mode Select 000 Mode 0 event count 10 Counter2 Read Load 001 Mode 1 programmable 1 shot 11 read back setting 00 latching operation 010 Mode 2 rate generator 01 read load LSB only 011 Mode 3 square wave rate generator 10 read load MSB oniy 100 Mode 4 software triggered strobe 11 read load LSB then MSB 101 Mode 5 hardware triggered strobe 12 Data LSB D A Converter 1 LSB Read Write A read provides the A D converter LSB the same data which can be read at BA 1 This option is included with your board to take advantage of the XT computer s ability to perform a word read with a single command When using the word read command at an even numbered address the XT will read the byte at the first address and then automatically increment and read the byte at the next address In this case a word read at BA 12 will provide the LSB followed by the MSB at BA 13 A write programs the DACI LSB eight bits BA 13 A D Data MSB D A Converter 1 MSB Read Write A read provides the A D converter MSB the same data which can be read at BA 1 A write programs the DAC1 MSB four bits into DO through D3 D4 through D7 are irrelevant BA 14 Clear IRQ Status D A Converter 2 LSB Read Write A read clears the IRQ status bit at bit 2
106. ompatibility 4422244 tenete TTL CMOS Configurable with optional I O pull up pull down resistors High level output voltage 00 4 2V min Low level output voltage cc eesccseccscessessssssscsecscssecsecsessceesereseeesterscsacsas 0 45V max High level input voltage 00 2 2V min 5 5V max Low level input voltage 0 00 224 4240 0 10 0 3V min 0 8V max Inputiload 10 A Input capacitance Mila r 10 pF Output capacitance G OUT Q FE1MEG ra rennen eie CTS 20 pF D A Converter ADA2210 ADA2310 AD7237 Analog OUtpUts coner eri Innern itta eco ere pe 2 channels A O 12 bits Output ranges une iin date to 5 5 or O to 10 volts Guaranteed linearity across output ranges 5 5 and 0 to 9 2 volts Relative accuracy REM 1 bit max Full scale accuracy 5 bits max Nonclinearily 1 c racer hene eterni ense de Tut bep ea t1 bit max Seling time enden ee dci negas Doce Dude aano seas 10 usec max Timer Counters Lee Leere Lee Lee eer
107. ontroller en trece Selena anna 4 24 DMA Single Mask Register isra n 4 24 DMA Mode ti 4 25 Programming the DMA Controller sssini K 4 25 Programming the Board for 20 Monitoring for DMA Common DMA Problems 2 kennst D A Conversions ADA Boards Only 20222020200000220000000ennonnoneosnnnennnsosnnnnnenonsansnnrsnnsnnssnssnnsnnennensnsennerern Mihi rS i r Digital ecce gebe epe one ume ee ete xe PEN CRM Example Programs and Flow Diagrams C and Pascal Programs dee H H BASIC Programs IM C H Flow Diagrams EET DU Single Convert Flow Diagram Figure 4 8 eese eese eee enses tenens DMA Flow Diagram Figure 4 9 222 2 11 040 002 0 20 Scan Flow Diagram Figure 4 10 esee eeeeseseeee senses te tenete enis tint inse nas Interrupts Flow Diagram Figure 4 11 2 D A Con
108. ort C Digital Read Write Transfers the two 4 bit Port C digital input and digital output data groups Port C Upper and Port C Lower between the board and an external device A read transfers data from the external device through P2 and into PPI Port a write transfers the written data from Port through P2 to an external device BA 7 8255 PPI Control Word Write Only When bit 7 of this word is set to 1 a write programs the PPI configuration The PPI must be programmed so that Port B is a Mode 0 output port as shown below X don t care Mode Set Flag Port CL u 1 active eu Mode Select 1 input 00 mode 0 01 mode 1 Port B 102mode2 output input Port A 0 output Mode Select 1 input mode 0 mode 1 essc 0 output 1 input Dru _ The table below shows the control words for the 16 possible Mode 0 Port combinations The control words which set Port B as an input cannot be used on the 2210 2310 8255 Port YO Flow Direction and Control Words Mode 0 EORR eee es sl Upper Port Lower Binary oen eere ja Fon Output 10001010 138 10001011 139 10010001 145 10010010 46 10010011 7 10011000 152 10011001 153 Input Output
109. ost significant byte 4 Write new most significant byte If a Counter is programmed to read write two byte counts the following precaution applies A program must not transfer control between reading the first and second byte to another routine which also reads from that same Counter Otherwise an incorrect count will be read READ BACK COMMAND The third method uses the Read Back command This command allows the user to check the count value programmed Mode and current state of the OUT pin and Null Count flag of the selected coun ter s The command is written into the Contro Word Reg ister and has the format shown in Figure 10 The command applies to the counters selected by set ting their corresponding bits D3 D2 D1 1 WR A0 A1 11 CS 0 D Ds Ds D4 D3 D2 Di Do L1 1 COUNT STATUS 1 curo o D 1 0 Ds 0 Latch count of selected counter s Da O Latch status of selected counter s 1 Select counter 2 02 1 Select counter 1 D 1 Select counter 0 Do Reserved for future expansion must be 0 Figure 10 Read Back Command Format The read back command may be used to latch multi ple counter output latches OL by setting the COUNT bit D5 0 and selecting the desired coun ter s This single command is functionally equiva lent to several counter latch commands one for each counter latched Each counter s latched count is held until it is read or the counter is repro
110. problem for you when programming these values is figuring out what the corresponding page and offset are for your buffer Most compilers contain macros or functions that allow you to directly determine the segment and offset of a data structure but not the page and offset Therefore you must calculate the page number and offset yourself Probably the most intuitive way of doing this is to convert the segment offset address of your buffer to a linear address and then convert that linear address to a page offset address The table at the top of the next page shows functions macros for determining the segment and offset of a buffer 4 22 7 FP_SEG FP_OFF s FP_SEG amp Buffer o FP_OFF amp Buffer Seg Ofs S Seg Buffer O Ofs Buffer BASIC VARSEG VARPTR S VARSEG BUFFER O VARPTR BUFFER Once you ve determined the segment and offset multiply the segment by 16 and add the offset to give you the linear address Make sure you store this result in a long integer or DWORD or the results will be meaningless The page number is the quotient of the division of the linear address by 65536 and the offset into the page is the remainder of that division Below are some programming examples for Pascal C and BASIC In Pascal Segment SEG Buffer Offset OFS Buffer Linear Address Segment 16 Offset Page LinearAddress DIV 65536 get segment of buffer get offset of buffer
111. products or parts at no additional charge provided that the product is returned shipping prepaid to REAL TIME DEVICES replaced parts and products become the property of REAL TIME DEVICES Before returning any product for repair customers are required to contact the factory for an RMA number THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY PRODUCTS WHICH HAVE BEEN DAM AGED AS A RESULT OF ACCIDENT MISUSE ABUSE such as use of incorrect input voltages improper or insufficient ventilation failure to follow the operating instructions that are provided by REAL TIME DEVICES acts of God or other contingencies beyond the control of REAL TIME DEVICES OR AS A RESULT OF SERVICE OR MODIFICATION BY ANYONE OTHER THAN REAL TIME DEVICES EXCEPT AS EX PRESSLY SET FORTH ABOVE NO OTHER WARRANTIES ARE EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND REAL TIME DEVICES EXPRESSLY DISCLAIMS ALL WARRANTIES NOT STATED HEREIN ALL IMPLIED WARRANTIES INCLUDING IMPLIED WARRANTIES FOR MECHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE LIMITED TO THE DURATION OF THIS WARRANTY IN THE EVENT THE PRODUCT IS NOT FREE FROM DEFECTS AS WARRANTED ABOVE THE PURCHASER S SOLE REMEDY SHALL BE REPAIR OR REPLACEMENT AS PROVIDED ABOVE UNDER NO CIRCUMSTANCES WILL REAL TIME DEVICES BE LIABLE TO THE PURCHASER OR ANY USER FOR ANY DAMAGES INCLUDING ANY INCIDENTAL OR CONSEQUENTIAL DAM A
112. quest A high on this output can be used to interrupt the CPU for input or output oper ations Output Operations OBF Output Buffer Full The OBF output will go low to indicate that the CPU has written data out to port A ACK Acknowledge A low on this input enables the tri state output buffer of Port A to send out the data Otherwise the output buffer will be in the high impedance state INTE 1 The INTE Flip Flop Associated with OBF Controlled by bit set reset of PCg Input Operations STB Strobe Input A low on this input loads data into the input latch IBF Input Buffer Full F F A high on this output indicates that data has been loaded into the input latch INTE 2 The INTE Flip Flop Associated with IBF Controlled by bit set reset of 3 136 intel 82C55A CONTROL WORD D D D D D D D ID PORTE 17 INPUT 0 OUTPUT GROUP B MODE 0 MODE 1 MODE 1 231256 18 Figure 13 MODE Control Word 231256 19 Figure 14 MODE 2 231256 20 Figure 15 MODE 2 Bidirectional NOTE EN a Any sequence where WR occurs before ACK and STB occurs before RD is permissible e INTR IBF MASK e STB RD OBF e MASK e WR nn 3 137 MODE 2 AND MODE 0 INPUT CONTROL WORD D D Dy D Dj 0 D Do 5 of ro 1 INPUT 0 OUTPUT MODE 2 AND MODE 1 OUTPUT CONTROL WORD
113. r clock starts running as soon as the last divider is loaded A D conversions can be started and stopped by enabling and disabling the external trigger Timer Counter 1 Divider 2 Timer Counter 0 8 MH 7 Divider 1 Pacer Clock Fig 4 6 Pacer Clock Block Diagram Divider 1 Divider 2 Pacer Clock decimal hex decimal hex 3211902 io 0028 TIT 4000 46000740 4 17 Interrupts What Is an Interrupt An interrupt is an event that causes the processor in your computer to temporarily halt its current process and execute another routine Upon completion of the new routine control is returned to the original routine at the point where its execution was interrupted Interrupts are very handy for dealing with asynchronous events events that occur at less than regular intervals Keyboard activity is a good example your computer cannot predict when you might press a key and it would be a waste of processor time for it to do nothing while waiting for a keystroke to occur Thus the interrupt scheme is used and the processor proceeds with other tasks Then when a keystroke does occur the keyboard interrupts the processor and the processor gets the keyboard data places it in memory and then returns to what it was doing before it was interrupted Other common devices that use interrupts are modems disk drives and mice Your board can interrupt the processor when a variet
114. rom the counter If the count is latched or read before this time the count value will not reflect the new count just written The operation of Null Count is shown in Figure 12 Command gt D3 02 Dy Do Description Read back count and status of Count and status latched Counter 0 for Counter 0 o _ aeter Gor 1 Read back status of Counters 2 1 Status latched for Counter 2 but not Counter 1 i ensures Read back count and status of Count latched for Counter 1 Counter 1 but not status Read back status of Counter 1 Command ignored status already latched for Counter 1 CAUSES Nuli count 1 THIS ACTION A Write to the control word register 111 B Write to the count register CR l2 C New count is loaded into CE CR CE Null count 1 Null count 0 1 Only the counter specified by the control word will have its null count set to 1 Null count bits of other counters are unaffected 12 if the counter is programmed for two byte counts least significant byte then most significant byte null count goes to 1 when the second byte is written Figure 12 Null Count Operation If multiple status latch operations of the counter s are performed without reading the status all but the first are ignored i e the status that will be read is the status of the counter at the time the first status read back
115. s ceessesessesesesesscsesescnearsececseucsessseaescsesesesessseacssessacsnececssscevscseacavevas 2 4 Differential Input Connections eee esses entente teeth tnnt tese theta tbt epe piss ssp 2 5 Cascading Two Boards for Simultaneous Sampling sees tette tenete 2 6 2210 2310 Block Diagram 4 2222220 eese entente n 3 3 8254 Timer Counter Circuit Block Diagram ccssssscsssessssssesssesecesescsssssscsescsessscssssescesestsensaesecaeaseceuenes 3 4 A D Conversion Timing Diagram All Modes s ccssssssssessecescsesesessessscsescaescecsesescscssesscsuscseseeseencnsaes 4 13 Timing Diagram Single Conversion sssssssssssssecseseceseesecesessessssssesesesesesscseseessesseseseeressssnsesssaveenes 4 14 Timing Diagram Multiple Conversions sssessssssssssssssssssssessssssssescseseseenestscesscessescscevscssacnescavanaenees 4 14 Timing Diagram Channel Scanning cc scecscsssesesesssecesesesesescscesesescoesesssesessescesssessessscasssnacavavacaseees 4 15 Timing Diagram Burst ccccsssssesceesssssssssssssesssssssscsesececscscsceevsssussesssesesesesetsesessesseseatseseatsssseususcsssces 4 15 Pacer Clock Block Diagram 0sccssssssscscssscssesssossssssssecacscacseessnssesscsessearsestessnscusceussessessasesseceaesonsuces 4 17 8254 Programmable Interval Timer Circuit Block Diagram 222 4 28 Single Convers
116. s trigger digital events or activate solid state relays These lines are provided by the on board 8255 programmable peripheral interface chip Pads for installing and activating pull up or pull down resistors are included on the board Installation procedures are given near the end of Chapter 1 Board Settings What Comes With Your Board You receive the following items in your board package AD2210 ADA2210 AD2310 or ADA2310 interface board Software and diagnostics diskette with Turbo Pascal Turbo C and BASIC source code User s manual If any item is missing or damaged please call Real Time Devices Customer Service Department at 814 234 8087 If you require service outside the U S contact your local distributor Board Accessories In addition to the items included in your board package Real Time Devices offers a full line of software and hardware accessories Call your local distributor or our main office for more information about these accessories and for help in choosing the best items to support your board s application Application Software and Drivers Our custom application software packages provide excellent data acquisition and analysis support Use SIGNAL MATH for integrated data acquisition and sophisticated digital signal processing and analysis or SIGNAL VIEW for monitoring and data acquisition rtdLinx and rtdLinx NB drivers provide full featured high level interfaces between the board and custom or third par
117. s an A D trigger or for counting functions The timer counters can be programmed to operate in one of six modes depending on your application The following paragraphs briefly describe each mode Mode 0 Event Counter Interrupt on Terminal Count This mode is typically used for event counting While the timer counter counts down the output is low and when the count is complete it goes high The output stays high until a new Mode 0 control word is written to the timer counter Mode 1 Hardware Retriggerable One Shot The output is initially high and goes low on the clock pulse following a trigger to begin the one shot pulse The output remains low until the count reaches 0 and then goes high and remains high until the clock pulse after the next trigger 4 27 Mode 2 Rate Generator This mode functions like a divide by N counter and is typically used to generate a real time clock interrupt The output is initially high and when the count decrements to 1 the output goes low for one clock pulse The output then goes high again the timer counter reloads the initial count and the process is repeated This sequence continues indefinitely Mode 3 Square Wave Mode Similar to Mode 2 except for the duty cycle output this mode is typically used for baud rate generation The output is initially high and when the count decrements to one half its initial count the output goes low for the remainder of the count The timer counter relo
118. s list the key digital codes and corresponding output voltages for the D A converters me se m9 es 4 26 T Os o o9 _ a 9 Timer Counters An 8254 programmable interval timer provides three 16 bit 8 MHz timer counters for timing and counting functions such as frequency measurement event counting and interrupts Two of the timer counters are cascaded and can be used for the pacer clock The remaining timer counter is available for your use Figure 4 7 shows the timer counter circuitry Each timer counter has two inputs CLK in and GATE in and one output timer counter OUT They can be programmed as binary or BCD down counters by writing the appropriate data to the command word as described in the I O map section at the beginning of this chapter One of two clock sources the on board 8 MHz crystal or the external clock P2 45 can be selected as the clock input to TCO or TC2 The diagram shows how these clock sources are connected to the timer counters Two gate sources are available at the I O connector P2 41 and P2 46 When a gate is disconnected an on board pull up resistor automatically pulls the gate high enabling the timer counter The output from timer counter 1 is available at the T C OUT 1 pin P2 42 and timer counter 2 s output is available at T C 2 OUT P2 44 where they can be used for interrupt generation a
119. s used to in terface the 82 54 to the system bus see Figure 3 z COUNTER EN E e 3 2 x z z E z Figure 3 Diagram Showing Data Bus Buffer and Read Write Logic Functions READ WRITE LOGIC The Read Write Logic accepts inputs from the sys tem bus and generates control signals for the other functional blocks of the 82C54 A and Ag select one of the three counters or the Control Word Regis ter to be read from written into A low on the RD input tells the 82C54 that the CPU is reading one of the counters A low on the WR input tells the 82054 that the CPU is writing either a Control Word or an initial count Both RD and WR are qualified by CS RD and WR are ignored unless the 82C54 has been selected by holding CS low 3 85 CONTROL WORD REGISTER The Control Word Register see Figure 4 is selected by the Read Write Logic when Ay Ap 11 If the CPU then does a write operation to the 82C54 the data is stored in the Control Word Register and is interpreted as a Control Word used to define the operation of the Counters The Control Word Register can only be written to status information is available with the Read Back Command DATA Bus BUFFER a gt a x x z 5 z 231244 5 Figure 4 Block Diagram Showing Control Word Register and Counter Functions COUNTER 0 COUNTER 1 COUNTER 2 These three functional blocks are identical in opera tion so
120. significant byte first then most significant byte NOTE Don t care bits X should be 0 to insure compatibility with future Intel products MODE EN Binary Counter 16 bits Binary Coded Decimal BCD Counter 4 Decades Figure 7 Control Word Format 3 87 ntel 82 54 Write Operations The programming procedure for the 82C54 is very flexible Only two conventions need to be remem bered 1 For each Counter the Control Word must be written before the initial count is written 2 The initial count must follow the count format specified in the Control Word least significant byte only most significant byte only or least sig nificant byte and then most significant byte Since the Control Word Register and the three Counters have separate addresses selected by the A4 Ag inputs and each Control Word specifies the Counter it applies to SCO SC1 bits no special in Counter 0 Counter 0 Counter 0 Counter 1 Counter 1 Counter 1 Counter 2 Counter 2 Counter 2 Control Word LSB of count MSB of count Control Word LSB of count MSB of count Control Word LSB of count MSB of count 2200 00 002222009 Counter 0 Counter 1 Counter 2 Counter 2 Counter 1 Counter 0 Counter 0 Counter 1 Counter 2 Control Word Counter Word Control Word LSB of count LSB of count LSB of count MSB of count MSB of count MSB o
121. single sample on a selected channel A sample is taken each time you send the Start Convert command All of the samples will be taken on the same channel and at the same gain until you change the value in the PPI Port B register BA 1 Changing this value before each Start Convert command is issued lets you take the next reading from a different channel at a different gain Program 8255 PPI Port B out Clear Registers Reset Yes Select Channel amp Gain Change Channel or Gain Start Conversion Check End of Convert EOC z 1 Read LSB Read MSB Stop Program Fig 4 8 Single Conversion Flow Diagram Yes 4 31 DMA Flow Diagram Figure 4 9 This flow diagram shows you how to take samples and transfer the data directly into the computer s memory You can use DMA channel 1 or 3 to transfer data to the computer s memory The pacer clock can be used to set the sampling interval Program 8255 PPI Port B out Clear Registers Reset Program 8254 TCO amp TC1 for desired transfer rates Select Channel amp Gain Program DMA Controller Enable DMA amp External Trigger DMA Done 1 Stop Program Fig 4 9 DMA Flow Diagram 4 32 Scan Flow Diagram Figure 4 10 This flow diagram shows you how to take samples from a sequence of channels without selecting the channel each time a conversion is started The scan mode is enabled
122. solder short see Figure 1 16 R15 To calculate Gm Gm TR7 R14 R15 1 To calculate frequency f 12nC32 R14 TR7 Fig 1 15 Gain Circuitry and Formulas for Calculating Gm and f Remove Solder Short Between These 2 Pads on Bottom Side of Board o 600000000000 9 TOO ACO mo os 0000050 0600060000004 0000 un 74574 0000000000 86095099 000000 00000000 oo oo ous 22 0000000000 00000000 GORRA 00000 00000 v us a 0000000000 500000 Sam Seren E 040990999000 ero 22107230 Copyrig Resi Tene Devices ine Fig 1 16 Diagram for Removal of Solder Short 1 14 2 ______ BOARD INSTALLATION The 2210 2310 is easy to install in your IBM PC XT AT or compatible computer It can be placed in any slot short or full size This chapter tells you step by step how to install and connect the board After you have installed the board and made all of your con nections you can turn your system on and run the 2210DIAG board diagnostics program included on your example software disk to verify that your board is working 2 1 Board Installation Keep the board in its antistatic bag until you are ready to install it in your computer When removing it from the bag hold the boar
123. t P8 P8 P8 Fig 1 9a 5 to 5 volts Fig 1 9b O to 10 volts Fig 1 9c 10 to 10 volts Factory Setting Fig 1 9 Analog Input Voltage Range and Polarity Jumper P8 P9 A D Data Word Bit State Set Factory Setting This header connector shown in Figure 1 10 sets the state of the unused four bits in the 8 bit MSB of the 16 bit A D data word This header ensures that these four topmost bits are set at O for unipolar conversions and at the same state as the most significant bit of the 12 bit A D converted data for bipolar conversions Chapter 4 BA 1 explains this in more detail NOTE 8 and P9 must be set the same for proper board operation P9 Set P8 to the same polarity Fig 1 10 Data Word Bit State Set Jumper 9 1 8 P10 Single Ended Differential Analog Inputs Factory Setting Single Ended This header connector shown in Figure 1 11 configures the board for 8 differential or 16 single ended analog input channels When operating in the single ended mode three jumpers must be installed across the SE pins When operating in the differential mode three jumpers must be installed across the D pins DO NOT install jumpers across both SE and D pins at the same time P10 SE D SE D SE D Fig 1 11 Single Ended Differential Analog Input Signal Type Jumpers P10 S1 Base Address Factory Setting 300 hex 768 decimal One of the most common causes of failure when you
124. t trigger After writing the Control Word and initial count the Counter is armed A trigger results in loading the Counter and setting OUT low on the next CLK pulse thus starting the one shot pulse An initial count of N will result in a one shot pulse N CLK cycles in dura tion The one shot is retriggerable hence OUT will remain tow for N CLK pulses after any trigger The one shot pulse can be repeated without rewriting the same count into the counter GATE has no effect on OUT If a new count is written to the Counter during a one shot pulse the current one shot is not affected un less the Counter is retriggered In that case the Counter is loaded with the new count and the one shot pulse continues until the new count expires 12 158 3 letefulm md sdadtiolels CWx 12 158 31 12 158 2 0 FF o oj 4 3 231244 9 Figure 16 Mode 1 3 92 MODE 2 RATE GENERATOR This Mode functions like a divide by N counter It is typicially used to generate a Real Time Clock inter rupt OUT will initially be high When the initial count has decremented to 1 OUT goes low for one CLK pulse OUT then goes high again the Counter re loads the initial count and the process is repeated Mode 2 is periodic the same sequence is repeated indefinitely For an initial count of N the sequence repeats every N CLK cycles GATE 1 enables counting GATE 0 disables counting
125. tact our Technical Support Department 814 234 8087 during regular business hours eastern standard time or eastern daylight time or send a FAX requesting assistance to 814 234 5218 When sending a FAX request please include your company s name and address your name your telephone number and a brief description of the problem 1 m ia N nal i a ERE BOARD SETTINGS The 2210 and 2310 boards have jumper and switch settings you can change if necessary for your application The board is factory configured as listed in the table and shown on the diagram in the beginning of this chapter Should you need to change these set tings use these easy to follow instructions before you install the board in your computer Note that by installing resistor packs at three locations around the 8255 PPI and soldering jumpers in the associated pads you can configure the 16 available digital lines to be pulled up or pulled down This procedure is explained near the end of this chapter Also note that by installing components at R14 R15 TR7 and C32 you can add your own gain multiplier to the software pro grammable binary gains of 1 2 4 and 8 The gain multiplier circuitry is described at the end of this chapter 1 1 Factory Configured Switch and Jumper Settings Table 1 1 lists the factory settings of the user configurable jumpers and switch on the 2210 and 2310 boards Figure 1 1 s
126. ted indefinitely An initial count of N results in a square wave with a period of N CLK cycles GATE 1 enables counting GATE 0 disables counting If GATE goes low while OUT is low OUT is set high immediately no CLK pulse is required A trigger reloads the Counter with the initial count on the next CLK pulse Thus the GATE input can be used to synchronize the Counter After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse This allows the Counter to be synchronized by software also Writing a new count while counting does not affect the current counting sequence If a trigger is re ceived after writing a new count but before the end of the current half cycle of the square wave the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count Otherwise the new count will be loaded at the end of the current half cycle 3 is implemented as follows Even counts OUT is initially high The initiat count is loaded on one CLK pulse and then is decremented by two on succeeding CLK pulses When the count expires OUT changes value and the Counter is re loaded with the initial count The above process is repeated indefinitely Odd counts OUT is initially high The initial count minus one an even number is loaded on one CLK pulse and then is decremented by two on succeed ing CLK pulses One CLK pulse after the count ex pires OUT g
127. the channel specified at BA 5 The number of channels to be scanned is specified at BA 3 When using burst you must set bits D6 and D7 at BA 3 for the burst mode A burst can be triggered using the Start Convert command at BA 0 or by the hardware source exter nal trigger timer counter out 2 or external gate 2 set at TRIG on P3 If the external trigger enable bit D6 at BA 5 is disabled the busrt will be software triggered If this bit is enabled the burst will be hardware triggered The pacer clock internal or external sets the time between each sample in the burst Burst is used when you want one sample from a specified number of channels for each trigger Figure 4 5 shows a timing diagram for burst sampling Often the burst mode can be used for near simultaneous sampling from multiple input channels For critical simultaneous sampling applications a simultaneous sample and hold board can be used SS4 four channel and 558 eight channel boards are available from Real Time Devices BURST TRIGGER MES 2 A BURST CLOCK TU SAMPLE PORN PLL SAMPLED CHANNEL i ae sg E M Fig 4 5 Timing Diagram Burst Starting an A D Conversion Software triggered single conversions are started by writing to the START CONVERT port at BA 0 The value you write is irrelevant For single conversions you must write to this port to initiate every conversion Multiple conversions triggered by the pacer clo
128. to 10 volts change the range jumper on 8 so that it is installed across the 20V pins Leave the other jumper on P8 at and make sure the P9 jumper is on Then set the input voltage to 5 0000 volts and adjust TR3 until the output matches the data in the table below Data Value for Calibrating Bipolar 20 Volt Range 10 to 10 volts TR3 Input Voltage 5 0000V A D Converted Data 0100 0000 0000 D A Calibration ADA2210 amp ADA2310 The D A converter requires no calibration for the X1 ranges 0 to 5 and 5 volts The following paragraph describes the calibration procedure for the X2 multiplier ranges To calibrate for X2 0 to 10 or 10 volts set the DAC output voltage range to 0 to 10 volts jumpers on X2 and 5 on AOUTI or P7 AOUT2 Then program the corresponding D A converter DAC1 DAC2 with the digital value 2048 The ideal DAC output for 2048 at X2 0 to 10 volt range is 5 0000 volts Adjust TRS for AOUTI and TR6 for AOUT until 5 0000 volts is read at the output Table 5 3 lists the ideal output voltages per bit weight for unipolar ranges and Table 5 4 lists the ideal output voltages for bipolar ranges Table 5 3 D A Converter Unipolar Calibration Table Ideal Output Voltage in millivolts D A Bit Weight 0 to 10 V 4095 Max Output 4998 8 5 6 5 7 APPENDIX A 2210 2310 SPECIFICATIONS
129. to use you will want to try it out An easy to use menu driven diagnostics program 2210DIAG is included with your example software to help you verify your board s operation You can also use this program to make sure that your current base address setting does not contend with another device 3 HARDWARE DESCRIPTION This chapter describes the features of the 2210 2310 hardware The major circuits are the A D the D A the timer counters and the digital I O lines 3 1 The 2210 2310 board has four major circuits the A D the D A ADA boards only the timer counters and the digital I O lines Figure 3 1 shows the block diagram of the board This chapter describes the hardware which makes up the major circuits and hardware selectable interrupts 16 ANALOG INPUTS 8 DIFF 16 S E DM 5V TO 45V CON A RANGE 0 TO 10V TROL 12 817 SELECT RESISTOR PROGRAMMABLE 10V TO 10V CONFIGURABLE AND mM A D 25 VOLTS SELECT 7 converten 0 TO 10 VOLTS GAIN ae 10 VOLTS Ed TRIGGER SELECT Je MEI MEET TRIGGER OUT CHANNEL SCAN BURST CIRCUITRY PULL UP DOWN RESISTORS TIMER COUNTER VO ANO PACER CLOCK SELECT CONNECTOR ADDRESS DECODE CONTROL RANGE SELECT 5 VOLTS 0 TO 5 VOLTS CONVERTER 0 TO 10 VOLTS 210 VOLTS Fig 3 1 2210 2310 Block Diagram A D Conversion Circuitry The 2210 2310 performs analog to digital conversions on up to 8 differential or
130. ty software including Labtech Notebook Notebook XE and LT Control rtdLinx source code is available for a one time fee Hardware Accessories Hardware accessories for the 2210 2310 include the MX32 analog input expansion board which can expand a single input channel on your board to 16 differential or 32 single ended input channels MR series mechanical relay output boards OP series optoisolated digital input boards the OR16 mechanical relay optoisolated digital I O board the TS16 thermocouple sensor board the 50 terminal board and 50 prototype terminal board for prototype development and easy signal access EX XT and EX AT extender boards for simplified testing and debugging of prototype circuitry and the XT50 twisted pair flat ribbon cable assembly for external interfacing Using This Manual This manual is intended to help you install your new board and get it running quickly while also providing enough detail about the board and its functions so that you can enjoy maximum use of its features even in the most complex applications We assume that you already have an understanding of data acquisition principles and that you can customize the example software or write your own applications programs When You Need Help This manual and the example programs in the software package included with your board provide enough information to properly use all of the board s features If you have any problems installing or using this board con
131. ur program or if for some reason sampling is halted before the DMA controller has transferred all the data it was programmed to transfer If you leave DMA enabled and it has not transferred all the data it was programmed to transfer it will resume transfers the next time data appears at the A D converter This can spell disaster if your program has ended and the buffer has be reallocated to another application 4 24 VO Port OAH Channel Select Mask Bit 00 Channel 0 O unmask 01 Channel 1 1 mask 10 2 11 Channel 3 DMA Mode Register The DMA mode register is used to set parameters for the DMA channel you will be using The read write bits are self explanatory the read mode cannot be used with the 2210 2310 Autoinitialization allows the DMA control ler to automatically start over once it has transferred the requested number of bytes Decrement means the DMA controller should decrement its offset counter after each transfer the default is increment You can use either the demand or single transfer mode when transferring data The demand mode transfers data to the PC on demand for fastest transfer rate The single transfer mode forces the DMA controller to relinquish every other cycle so that the processor can take care of other tasks Port OBH Transfer Mode Channel Select Autoinitialization 00 demand 0 disabl 00 Channel 0 01 single transfer see 01 Channel 1 10 block 1 enabl
132. us Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU Control words and status information are also transferred through the data bus buffer Read Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words It accepts inputs from the CPU Address and Control busses and in turn issues commands to both of the Control Groups Group A and Group B Controls The functional configuration of each port is pro grammed by the systems software In essence the CPU outputs a control word to the 82C55A The control word contains information such as mode bit set bit reset etc that initializes the func tional configuration of the 82C55A um nn Each of the Control blocks Group and Group accepts commands from the Read Write Control Logic receives control words from the internal data bus and issues the proper commands to its as sociated ports Control Group A Port A and Port C upper C7 C4 Control Group Port and Port C lower C3 CO The control word register can be both written and read as shown in the address decode table in the pin descriptions Figure 6 shows the control word format for both Read and Write operations When the control word is read bit D7 will always be a logic 1 as this implies control word mode information Ports A B an
133. ut Voltage 9 49829 V 0000 0000 0000 1111 0011 0010 A D Converted Data 0000 0000 0001 1111 0011 0011 Bipolar Calibration Bipolar Range Adjustments 5 to 5 Volts Two adjustments are made to calibrate the A D converter for the bipolar range of 5 to 5 volts One is the offset adjustment and the other is the full scale or gain adjustment Trimpot TR2 is used to make the offset adjustment and trimpot TR1 is used for gain adjustment Before making these adjustments make sure that the jumpers on P8 are set for 10V and and the jumper on P9 is set for Use analog input channel 1 and set it for a gain of 1 while calibrating the board Connect your precision voltage source to channel 1 Set the voltage source to 4 99878 volts start a conversion and read the resulting data Adjust trimpot TR2 until it flickers between the values listed in the table below Next set the voltage to 4 99634 volts and repeat the procedure this time adjusting TR1 until the data flickers between the values in the table Data Values for Calibrating Bipolar 10 Volt Range 5 to 5 volts Offset TR2 Converter Gain TR1 Input Voltage 4 99878V Input Voltage 4 99634V 1000 0000 0000 0111 1111 1110 A D Converted Data 1000 0000 0001 0111 1111 1111 Table 5 2 Converter Bit Weights Bipolar Twos Complement 5 5 Bipolar Range Adjustments 10 to 10 Volts To adjust the bipolar 20 volt range 10
134. ut latch OL latches the count at the time the Counter Latch Command is received This count is held in the latch until it is read by the CPU or until the Counter is reprogrammed The count is then unlatched automatically and the OL returns to following the counting element CE This allows reading the contents of the Counters the fly without affecting counting in progress Multiple Counter Latch Commands may be used to latch more than one Counter Each latched Coun ter s OL holds its count until it is read Counter Latch Commands do not affect the programmed Mode of the Counter in any way If a Counter is latched and then some time later latched again before the count is read the second Counter Latch Command is ignored The count read will be the count at the time the first Counter Latch Command was issued With either method the count must be read accord ing to the programmed format specifically if the Counter is programmed for two byte counts two bytes must be read The two bytes do not have to be read one right after the other read or write or pro 3 89 gramming operations of other Counters may be in serted between them Another feature of the 82C54 is that reads and writes of the same Counter may be interleaved for example if the Counter is programmed for two byte counts the following sequence is valid 1 Read least significant byte 2 Write new least significant byte 3 Read m
135. version Flow Diagram Figure 4 12 CHAPTER 5 CALIBRATION 2 1 5 1 eee obe is 5 3 A D Cali Bratton PEE 5 4 Unipolar Calibration rettet pct 5 4 1 serie 5 5 Bipolar Range Adjustments 5 to 5 Volts ccsscseccscsessesesscseesecssesensssessccsnssesscseasesessesecscecsteesecescesaceseeserets 5 5 Bipolar Range Adjustments 10 to 10 Volts esee eese retten 5 6 D A Calibration ADA2210 amp ADA2310 24444 0 000000 2600600 eetnthtntnentt ta tete tete these tete entn eese th 5 6 APPENDIX A 2210 2310 SPECIFICATIONS C APPENDIX B P2 CONNECTOR PIN ASSIGNMENTS B 1 APPENDIX C COMPONENT DATA SHEETS C 1 APPENDIX D WARRANTY PA D 1 iii 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 1 10 1 11 1 12 1 13 1 14 1 15 1 16 2 1 2 2 2 3 2 4 3 1 3 2 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 4 10 4 11 4 12 5 1 Board Layout Showing Factory Configured Settings
136. volve checking to see if any DOS functions are currently active when your ISR is called but such solutions are well beyond the scope of this discussion 4 19 second major concern when writing your ISR is to make it as short as possible in terms of execution time Spending long periods of time in your ISR may mean that other important interrupts are being ignored Also if you spend too long in your ISR it may be called again before you have completed handling the first run This often leads to a hang that requires a reboot Your ISR should have this structure Push any processor registers used in your ISR Most and Pascal interrupt routines automatically do this for you Put the body of your routine here Clear the interrupt bit on the board by writing any value to BA 2 Issue the EOI command to the 8259 interrupt controller by writing 20H to port 20H Pop all registers pushed on entrance Most C and Pascal interrupt routines automatically do this for you The following C and Pascal examples show what the shell of your ISR should be like In C void interrupt ISR void Your code goes here Do not use any DOS functions outportb BaseAddress 2 0 Clear 2210 2310 interrupt outportb 0x20 0x20 Send EOI command to 8259 In Pascal Procedure ISR Interrupt begin Your code goes here Do not use any DOS functions Port BaseAddress 2 0 Clear 2210 2310 interrupt
137. when you set the gain 1 110 8 Enabling Disabling the External Trigger The external trigger enable bit at BA 5 enables the A D trigger source When this bit is enabled in the scan mode A D conversions are controlled by the on board or external pacer clock depending on the setting of the PCLK jumper at P3 When disabled A D conversions are triggered from software Start Convert command for all modes except burst When this bit is disabled in the burst mode bursts are triggered by software and each conver sion in the burst is triggered by the on board or external pacer clock again depending on the setting of the PCLK jumper at P3 When enabled in the burst mode bursts are triggered by an external trigger the output of timer counter 2 or a signal brought onto the board through the EXT GATE 2 pin on P2 depending on the setting of the TRIG jumper at P3 Enabling and Disabling Interrupts Any time you use interrupts this bit at port BA 5 must be set high to enable the IRQ circuitry Types of Conversions The board can perform single and multiple conversions channel scanning and bursts Figure 4 1 shows the basic timing diagram for a conversion lt q 5 usec Trigger End of Convert 1 LC um Read Fig 4 1 A D Conversion Timing Diagram All Modes 4 13 Single Conversion In this mode a single specified channel is sampled whenever a value
138. write your page offset and count to ports 06H and 07H The page offset is simply the offset that you calculated for your buffer see discussion above Count indicates the number of bytes that you want the DMA controller to transfer Remember that each digitized sample from the 2210 2310 consists of 2 bytes so the count that you write to the DMA controller should be equal to the number of samples x 2 1 The single mask register and mode register are described below The clear byte pointer sets an internal flip flop on the DMA controller that keeps track of whether the LSB or MSB will be sent next to registers that accept both LSB and MSB Ordinarily you never need to write to this port but it is a good habit to do so before programming the DMA controller Writing any value to this port clears the flip flop Address hex decimal Register Description 02 02 Channel 1 Page Offset write 2 bytes LSB first Mode Register write only Clear Byte Pointer Flip Flop write only DMA Single Mask Register The DMA single mask register is used to enable or disable DMA on a specified DMA channel You should mask disable DMA on the DMA channel you will be using while programming the DMA controller After the DMA controller has been programmed and the 2200 has been programmed to sample data you can enable DMA by clearing the mask bit for the DMA channel you are using You should manually disable DMA by setting the mask bit before exiting yo
139. y an on board pacer clock or by an external trigger brought onto the board through the I O connector The converted data can be transferred through the PC data bus to PC memory in one of two ways by using the microprocessor or by using direct memory access DMA The mode of transfer is software selectable and the DMA channel is chosen by jumper settings on the board The PC data bus is used to read and or transfer data to PC memory In the DMA transfer mode you can make continuous transfers directly to PC memory without going through the processor Digital to Analog Conversion ADA Boards Only The digital to analog D A circuitry on the ADA2210 and ADA2310 features two independent 12 bit analog output channels with individually jumper selectable output ranges of 5 to 5 volts 10 to 10 volts 0 to 5 volts or 0 to 10 volts Both outputs are simultaneously updated by writing to an VO port Access through DMA is not available 8254 Timer Counter An 8254 programmable interval timer contains three 16 bit 8 MHz timer counters to support a wide range of timing and counting functions Two of the timer counters are cascaded and can be used internally for the pacer clock The third is available for counting applications or it can be cascaded to the other two timer counters Digital I O The 2210 2310 has 16 TTL CMOS compatible digital I O lines which can be directly interfaced with external devices or signals to sense switch closure
140. y of conditions are met By using these interrupts you can write software that effectively deals with real world events Interrupt Request Lines To allow different peripheral devices to generate interrupts on the same computer the PC bus has eight different interrupt request IRQ lines A transition from low to high on one of these lines generates an interrupt request which is handled by the PC s interrupt controller The interrupt controller checks to see if interrupts are to be acknowledged from that IRQ and if another interrupt is already in progress it decides if the new request should supersede the one in progress or if it has to wait until the one in progress is done This prioritizing allows an interrupt to be interrupted if the second request has a higher priority The priority level is based on the number of the IRQ IRQO has the highest priority IRQ1 is second highest and so on through IRQ7 which has the lowest Many of the IRQs are used by the standard system resources IRQO is used by the system timer IRQ is used by the key board IRQ3 by 2 IRQ4 by COM1 and IRQ6 by the disk drives Therefore it is important for you to know which IRQ lines are available in your system for use by the board 8259 Programmable Interrupt Controller The chip responsible for handling interrupt requests in the PC is the 8259 Programmable Interrupt Controller To use interrupts you need to know how to read and set the 8259 s interrupt mas
141. your program as it was before your program started running Common Interrupt Mistakes Remember that hardware interrupts are numbered 8 through 15 even though the corresponding IRQs are numbered 0 through 7 Two of the most common mistakes when writing an ISR are forgetting to clear the interrupt status of the board and forgetting to issue the EOI command to the 8259 interrupt controller before exiting the ISR Data Transfers Using DMA Direct Memory Access DMA transfers data between a peripheral device and PC memory without using the processor as an intermediate Bypassing the processor in this way allows very fast transfer rates All PCs contain the necessary hardware components for accomplishing DMA However software support for DMA is not included as part of the BIOS or DOS leaving you with the task of programming the DMA controller yourself With a little care such programming can be successfully and efficiently achieved The following discussion is based on using the DMA controller to get data from a peripheral device and write it to memory The opposite can also be done the DMA controller can read data from memory and pass it to a periph eral device There are a few minor differences mostly concerning programming the DMA controller but in general the process is the same The following steps are required when using DMA Choose a DMA channel Allocate a buffer Calculate the page and offset of the buffer Set the DM

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