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1. a Structure window opens labeled sim This window displays the hierarchical structure of the design as shown in Figure 3 6 You can navigate within the design hierarchy in the Structure sim window by clicking on any line with a expand or contract icon ModelSim Tutorial v6 6c 19 Basic Simulation Load the Design Figure 3 6 The Design Hierarchy sim Ee lea bes Flinstance Design unit Design unit type visibility 4 SS FF test_counter best counter Fask Module acc dut counter Fast Module acc T 2g increment counter Fast Function acc g FALWAYS 35 counter Fast Process A INITIAL 17 best counter Fast Process g FINITIAL 23 best counter Fask Process A INITIAL 430 best counter Fast Process ex ysim Capacity Foreign acc El sim Sim 4 d In addition an Objects window and a Processes window opens Figure 3 7 The Objects window shows the names and current values of data objects in the current region selected in the Structure sim window Data objects include signals nets registers constants and variables not declared in a process generics parameters The Processes window displays a list of HDL processes in one of four viewing modes Active In Region Design and Hierarchical The Design view mode is intended for primary navigation of ESL Electronic System Level designs where processes are a foremost consideration By default this window displays the
2. the variable and its current value in a Source Examine window Figure 3 14 24 ModelSim Tutorial v6 6c Basic Simulation Set Breakpoints and Step through the Source Figure 3 14 Parameter Name and Value in Source Examine Window Source Examine x test_counter dut ALWAYS 35 tpd reset_to count 3 ok e use the examine command at the VSIM gt prompt to output a variable value to the Transcript window 1 e examine count 5 Try out the step commands a Click the Step icon on the Main window toolbar i This single steps the debugger Experiment on your own Set and clear breakpoints and use the Step Step Over and Continue Run commands until you feel comfortable with their operation Lesson Wrap Up This concludes this lesson Before continuing we need to end the current simulation 1 Select Simulate gt End Simulation 2 Click Yes when prompted to confirm that you wish to quit simulating ModelSim Tutorial v6 6c 25
3. window active and selecting File gt Close from the menus b Select both counter v and tcounter v modules from the Compile Source Files dialog and click Compile The files are compiled into the work library c When compile is finished click Done ModelSim Tutorial v6 6c 17 Basic Simulation Load the Design Figure 3 3 Compile Source Files Dialog Compile Source Files 7 x Library work Look in E basicSimulation de to counter ey EE OT Ecounter File name boounter w counter w Compile HOL Files ove vile vhs vile vho hdl s Files of type Done Compile selected files together Default Options Edit Source 2 View the compiled design units a Inthe Library window click the icon next to the work library and you will see two design units Figure 3 4 You can also see their types Modules Entities etc and the path to the underlying source files Figure 3 4 Verilog Modules Compiled into work Library Library tame Type Path o O o work Library work k counter Module C imodeltech_6 6xtexamplesitutorials i besk counter Module Cilmodeltech 6 6x examples tuborials Hi FloatFixlib Library MODEL_TECH fFloatFixlib Hi mecz _lib Library MODEL_ TECHS mecz _lib H mkiaynn Library MODEL TECH fayvm mti Library MODEL_TECH fovm 2 0 3 H mtiP A Library MODEL_TECH pa_lib H mtivipr Library MODEL_TECH fupf lib Se
4. Chapter 3 Basic Simulation Introduction In this lesson you will go step by step through the basic simulation flow 1 Create the Working Design Library 2 Compile the Design Units 3 Load the Design 4 Run the Simulation Design Files for this Lesson The sample design for this lesson is a simple 8 bit binary up counter with an associated test bench The pathnames are as follows Verilog lt install_dir gt examples tutorials verilog basicSimulation counter v and tcounter v VHDL lt install_dir gt examples tutorials vhdl basicSimulation counter vhd and tcounter vhd This lesson uses the Verilog files counter v and tcounter v If you have a VHDL license use counter vhd and tcounter vhd instead Or if you have a mixed license feel free to use the Verilog test bench with the VHDL counter or vice versa Related Reading User s Manual Chapters Design Libraries Verilog and SystemVerilog Simulation and VHDL Simulation Reference Manual commands vlib vmap vlog vcom view and run Create the Working Design Library Before you can simulate a design you must first create a library and compile the source code into that library 1 Create a new directory and copy the design files for this lesson into it Start by creating a new directory for this exercise in case other users will be working with these lessons ModelSim Tutorial v6 6c 15 Basic Simulation Create the Working Design Library Verilog Copy coun
5. active processes in your simulation Active view mode Figure 3 7 The Object Window and Processes Window H7 reset 4 count INITIAL 1 Initial FINITIAL 23 Initial INITIAL 30 Initial 20 ModelSim Tutorial v6 6c Basic Simulation Run the Simulation Run the Simulation We re ready to run the simulation But before we do we ll open the Wave window and add signals to it 1 Open the Wave window a Enter view wave at the command line The Wave window opens in the right side of the Main window Resize it so it is visible You can also use the View gt Wave menu selection to open a Wave window The Wave window is just one of several debugging windows available on the View menu 2 Add signals to the Wave window a Inthe Structure sim window right click test counter to open a popup context menu b Select Add gt To Wave gt All items in region Figure 3 8 All signals in the design are added to the Wave window Figure 3 8 Using the Popup Menu to Add Signals to Wave Window MEE H7 Objects E test_counter Peet inba Ea Modul dk dut j reset x View instantiation iol oe KXXXXXXX Hj increment aLwarse35 Wave T INTIAL 17 INTIAL 23 Copy Expand Selected 3 Run the simulation a Click the Run icon The simulation runs for 100 ns the default simulation length and waves are i drawn in the Wave window b Enter run 500 at the VSIM gt prompt in the Tran
6. am tl aTh a e tae At tenn a eS n EEn Load the Design 1 Load the test counter module into the simulator a Inthe Library window click the sign next to the work library to show the files contained there b Double click test counter to load the design 18 ModelSim Tutorial v6 6c Basic Simulation Load the Design You can also load the design by selecting Simulate gt Start Simulation in the menu bar This opens the Start Simulation dialog With the Design tab selected click the sign next to the work library to see the counter and test counter modules Select the test counter module and click OK Figure 3 5 Figure 3 5 Loading Design with Start Simulation Dialog Start Simulation x Design HEL Verilog Libraries SDF Others alal Mame Type Name o work hii counter My test counter Hil Floatfixlib Library Module Module Library Library Library Library Library Library EHI mti vm Hi ritiovm Hii mtivPr i H sy std Hii vitalzoo0 MODEL_TECH jFloatfivlib MODEL TECH ave MODEL_TECH fovmn 2 0 MODEL_TECH jupF_lib MODEL_TECH s _std MODEL_TECH vital2000 el Path z work Ci Tutorialfexamples tutorials verilog basicSir Tutorialfexamples tutorials verilog basicSin Design Unitts Resolution hrork test comter default kd Optimization Enable optimization Optimization Options OK Cancel When the design is loaded
7. asic Simulation Set Breakpoints and Step through the Source b Click the Restart button in the Restart dialog c Click the Run All icon The simulation runs until the breakpoint is hit When the simulation hits the breakpoint it stops running highlights the line with a blue arrow in the Source view Figure 3 12 and issues a Break message in the Transcript window Figure 3 12 Blue Arrow Indicates Where Simulation Stopped h Tutorialfexamples tutorials verilog basicSimulation counter a o U O Oa ae end a endfunction 34 ae always posedge clk or posedge reset 3 6 if reset oT Count tpd reset to count o hoo 30 else 39 count lt tpd clk to count increment counti gt 40 tz ih counter w 4 B When a breakpoint is reached typically you want to know one or more signal values You have several options for checking values e look at the values shown in the Objects window Figure 3 13 Figure 3 13 Values Shown in Objects Window tod reset_to count 3 Parameter Internal tod_ dk to count Parameter Internal count KXXKKKKK Packed Array Out ot Net In oti Net In e set your mouse pointer over a variable in the Source window and a yellow box will appear with the variable name and the value of that variable at the time of the selected cursor in the Wave window e highlight a signal parameter or variable in the Source window right click it and select Examine from the pop up menu to display
8. ber column next to the line number A red ball appears in the line number column at line number 36 Figure 3 10 indicating that a breakpoint has been set 22 ModelSim Tutorial v6 6c Basic Simulation Set Breakpoints and Step through the Source Figure 3 10 Setting Breakpoint in Source Window hi Tutorialfexamples tutorials verilog basicSimulation icounter i Lo al endfunction 34 oo always posedge clk or posedge reset 308 if reset Jy Count tpd reset to count oe HOG 36 else ao count lt tpd clk to count increment count 40 4 gal wave lh counter w al 3 Disable enable and delete the breakpoint a b G d Click the red ball to disable the breakpoint It will become a black ball Click the black ball again to re enable the breakpoint It will become a red ball Click the red ball with your right mouse button and select Remove Breakpoint 36 Click in the line number column next to line number 36 again to re create the breakpoint 4 Restart the simulation a time to zero Click the Restart icon to reload the design elements and reset the simulation The Restart dialog that appears gives you options on what to retain during the restart Figure 3 11 Figure 3 11 Setting Restart Functions List Format Wave Format Breakpoinks Logged Signals Virtual Definitions Assertions Cover Directives ATY Format Cancel ModelSim Tutorial v6 6c 23 B
9. m 16 ModelSim Tutorial v6 6c Basic Simulation Compile the Design Units ModelSim also adds the library to the Library window Figure 3 2 and records the library mapping for future reference in the ModelSim initialization file modelsim ini Figure 3 2 work Library Added to the Library Window Library FiName SST ype Path Library work d Library MODEL_TECH A gt A Hi floattixlib mtiAvm Library SMODEL_TECH f mvm Library SMODEL_TECH om HI mtiuPF Library MODEL_TECH H sv_std Library MODEL_TECH sil Hi vital2zo00 Library MODEL_TECH Y jeee Library a Hi modelsim_lib Library i When you pressed OK in step 3c above the following was printed to the Transcript window vlib work vmap work work These two lines are the command line equivalents of the menu selections you made Many command line equivalents will echo their menu driven functions in this fashion Compile the Design Units With the working library created you are ready to compile your source files You can compile by using the menus and dialogs of the graphic interface as in the Verilog example below or by entering a command at the ModelSim gt prompt 1 Compile counter v and tcounter v a Select Compile gt Compile This opens the Compile Source Files dialog Figure 3 3 If the Compile menu option is not available you probably have a project open If so close the project by making the Library
10. script window The simulation advances another 500 ns for a total of 600 ns Figure 3 9 ModelSim Tutorial v6 6c 21 Basic Simulation Set Breakpoints and Step through the Source Figure 3 9 Waves Drawn in Wave Window PS wave ES me Mow 1000 ns D Cursort 862s Al itest counter telh oO 4 thest counterfreset 0 E gt festicountercoune 0070 CCC CCC AAAA AAAA AAAA AAAA A A AAAA c Click the Run All icon on the Main or Wave window toolbar m The simulation continues running until you execute a break command or it hits a statement in your code e g a Verilog stop statement that halts the simulation d Click the Break icon to stop the simulation Set Breakpoints and Step through the Source Next you will take a brief look at one interactive debugging feature of the ModelSim environment You will set a breakpoint in the Source window run the simulation and then step through the design under test Breakpoints can be set only on executable lines which are indicated with red line numbers 1 Open counter v in the Source window a Select View gt Files to open the Files window b Click the sign next to the sim filename to see the contents of vsim wi f dataset c Double click counter v or counter vhd if you are simulating the VHDL files to open the file in the Source window 2 Seta breakpoint on line 36 of counter v or line 39 of counter vhd for VHDL a Scroll to line 36 and click in the Ln line num
11. ter v and tcounter v files from lt install_dir gt examples tutorials verilog basicSimulation to the new directory VHDL Copy counter vhd and tcounter vhd files from lt install_dir gt examples tutorials vhdl basicSimulation to the new directory 2 Start ModelSim if necessary a Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows Upon opening ModelSim for the first time you will see the Welcome to ModelSim dialog Click Close b Select File gt Change Directory and change to the directory you created in step 1 3 Create the working library a Select File gt New gt Library This opens a dialog where you specify physical and logical names for the library Figure 3 1 You can create a new library or map to an existing library We ll be doing the former Figure 3 1 The Create a New Library Dialog Create a New Library xX reate I anen library a map to an existing library anew library and a logical mapping to it Library Marne hiro rE Library Physical Marne lwo rk OK Cancel b Type work in the Library Name field if it isn t already entered automatically c Click OK ModelSim creates a directory called work and writes a specially formatted file named _ info into that directory The info file must remain in the directory to distinguish it as a ModelSim library Do not edit the folder contents from your operating system all changes should be made from within ModelSi
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