User Manual - IMS B008 User Guide and Reference
Contents
1. WAAAY Vtt PHA 5 A Reset Analyse and Error to TRAMs 1 9 Reset Analyse and Error to TRAMs 0 9 Figure 6 Two Cascaded Boards Board 1 should be set up exactly as described in section 2 4 1 It is then necessary to connect board 1 SUBSYSTEM port to the board 2 UP port This enables TRAMO on board 1 to control all the transputers on board 2 The pipeline between the two boards must also be set up Thus board 1 Pipetail must be connected to board 2 PatchLink1 and the patch area on board 2 must be altered such that PatchLink1 is connected to Pipehead ConfigDownLink from the IMS T212 on board 1 must be connected to Con figUpLink of the IMS T212 on board 2 This means that the patch area on board 2 must be changed so that the ConfigUpLink on its IMS 212 is brought to the 37 way D connector via PatchLink0 Therefore board 1 Con figDownLink should be connected to board 2 PatchLink0 Fig 7d shows the patch connections required The pinout of the 37 way D connector is given in appendix G The signals 14 2 V 3 2 BOARD 2 TRAMO 4 27 2 52220 BOARD 2 5 bsyslem vi f _ jum 1812 ____ 9 1 2 TRAM9 6559595554455 that need connec2. 5 v HOF UIUI POW 54 T3hONUTTRPOR OUPWNUTTEI eg vr OjnONUTTEI Tinoxut us3egd Zo Turwurdus1ed are Ge 530080715384 619 ourwurdusi3egd 020 19539 Het 1n05x2012208d nra NI2072 UTNUTTGnBT ue5 0820 3hONUTTHAET UOS 889 ONUTT0BOR 750 OF C ourxurd0pow 9 9149112705 rerssdsi 1 27 5 2395 7 BILERETAN 507 100 MNI3 82 100 8 SNIT 5 FER 1212 2 1no NI NI ino BE NNIT PRE NI 5 eva ord 929 50 9 5 8861 72350 BABY 8008 SWI LE or 425 42 3 691 4755743 EE 09 55 sx m 3 601 5 5805 ed eeu NMOO NMOO 13538 605774 OTIL SSATEUVUMOd10U 548808 Zd 3SATWNV Od
3. ConfigDown Link 2 ConfigDown Link 2 5 5 5 5 LI 5 5 5 5 5 Figure 3 IMS T212 Configuration Pipeline 2 2 3 Module Motherboard Software 52 The 52 is a piece of software written by INMOS that simplifies the task of configuring a system of motherboards Each motherboard is defined using hardware description language called HL1 the IMS B008 HL1 description is given in appendix D The required IMS C004 softwired connections are then defined in similar manner by the user 52 interprets these commands and sends the appropriate configuration data down the IMS T212 chain Further details of its operation can be found in the 52 User Manual A number of example transputer networks together with their associated softwire descriptions are contained in appendix E At present the 52 is supplied as part of the IMS B008 product At a later date it is intended that the MMS2 will be included within the Transputer Development System TDS 2 3 Multi Transputer Systems Clearly very large and very powerful systems can be built Therefore it becomes necessary to establish the control hierarchy of the system For example when using the TDS to develop and debug some software one might run the TDS on TRAM in slot 0 and run the application on a network of TRAMs under the control of the TRAM in slot 0 Obviously one does not w
4. BOHH3 d 13538 18538 30 JJ3SS0DOW30U 39S9HSSODO 0 d eaasaniou 51 0 ss 888m35u 02 8 3ueunoog ezrs 830IS 8008 SWI SOMNI EUTsuT EP OW lt aout epon lt O3no3uT 75519 0 1 10 GOWLIG HOBB3LON Dry HOBH3ION T attest Hi 1 8 TEPON 8 YT ORRSINET 3 lt E EPON 1 TNIXNIT ONDINE ONINNII SINE pep 1 ENIXNIA ELDONNIT ENIINIA E ENDINIT ENIXNIA H eae GOWLIG 13838 13536 aSA NY 3SATVNV HWS ZHWS lt TTSEPSH 9 Em VWID3SdSHNID O1nONNI TNDINIA ONDINE FARONTE ONINNIA TLNONNIT ELNOJNIT lt gurur po ENINNIA 1 Sane Ba 30155
5. 2 5 The IBM Bus 2 5 wk oak cec m RR ee 2 5 2 Direct Memory Access DMA 2 5 3 Example Programs 2 6 Interrupis uh 1 3 2 6 1 Why Interrupts 2 6 2 IMS B008 Interrupt Capability 2 6 3 Examples a Sane eo Be uo 21 Whe Patchy Area a oa aie eek Bolas 2 8 Link Speed Selection Configuration 3 1 Default Switch and Jumper Settings 3 1 1 Board Address 3 1 2 Interrupt 3 1 3 DMA Channel Setting 3 1 4 Link Speed 3 15 Jumper Unpacking and Handling 4 1 Unpacking the IMS B008 4 2 Handling Precautions 4 3 TRAM Fitting and Handling 4 4 Installing an IMS B008 with a single TRAM fitted 23 23 23 23 24 24 24 Testing Oo Powering pu se we Pe 5 2 Running the test software Switch Settings DMA Channel Switches 122 2 Interrupt Channel Switch 3 Board Address Switches 5 6 Link Speed
6. Reset Analyse and Errorto TRAMs 0 9 Hlerarchy of TRAMs EDGE DOWN JP2 JP1 eee PC SUBSYS b Jumper plug 1 c Jumper plug 2 C012 Linkin TRAMO LinkOuto C012 LinkOut TRAMO PipeHead Linkin ConfigUp LinkOut PipeHead LinkOut ConfigUp Linkin clarity other links are not shown LinkIn2 TRAMA LinkOut LinkOut 2 TRAMA 1 d Patch area connections Figure 5 Single Board Target Configuration Jumper plug 1 should be set to PC as shown in Fig 5b This allows control of TRAMO from the IBM bus Jumper plug 2 should be connected to DOWN as shown in Fig 5c This ensures the signals controlling TRAMO propagate directly to TRAMs 1 9 as well as the IMS T212 Thus the program running on the IBM PC can 13 reset and analyse all the TRAMs at once Similarly the content of the error location as read by the PC is the logical OR of the error signals coming from all the transputers in the network The ConfigUp link of the IMS T212 should be connected to link 1 Pipehead PC then has to pass the IMS C004 configuration data to the IMS T212 via TRAMO The connection is made on the patch area as shown in Fig 5d 2 4 3 Cascaded Boards simple example of cascading will be described here two boards connected together with the TDS running on TRAMO of one board The block dia gram is shown in Fig 6 PC bus
7. following procedure should be followed 1 Remove the TRAM that is to run the TDS from its protective pack aging observing the appropriate handling precautions 2 Plug this TRAM into slot 0 of the IMS B008 Ensure that the pin 1 indicator on this TRAM lines up with the triangle on TRAM slot 0 of the IMS B008 Note that the 16 pins on the TRAM that carry the signals should plug into the required slot Thus for example a size 4 TRAM to plug into slot 0 will occupy slots 0 4 7 and 3 see Fig 11a a size 2 TRAM to plug into slot 1 will occupy slots 1 and 5 see Fig 11b 3 Insert link jumper plugs on top of this in all the slots that do not carry any signals This is to ensure continuity of the pipeline jumper is required at one end of each empty slot only with its marker band lining up with the triangle on the motherboard This is also illustrated by Fig 11 If T RAMs are to be stacked on top of each other the link jumpers have to be removed from the slots which are to be used for stacking 4 Fill the other slots on the IMS B008 with TRAMs as required They need not be filled in numerical order so long as the pipe is maintained using pipe jumpers 5 Fit link jumper plugs supplied into the slots on the motherboard that are not being used This stops the pipeline from being broken This is illustrated in Fig 11c in which the empty slots 8 and 9 have been jumped out to complete the pipeline 6 Remo
8. Inputs 1 544 PIN 2 545 PIN 3 SA6 PIN 4 SAT 5 548 6 549 PIN 7 AEN PIN 8 SELO 9 SEL1 PIN 11 DACK PIN 13 direction PIN 14 SAO PIN 15 541 Outputs PIN 12 RSO PIN 17 notSYS PIN 18 notLADP PIN 19 RS1 FIELD IBMaddr SA9 SA4 FIELD Select SEL1 SELO Define Board Address Spaces notLADP 1 150 amp Select 1 amp AEN IBMaddr 200 amp Select 2 amp AEN IBMaddr 300 amp Select 3 amp AEN DACK notSYS IBMaddr 160 amp Select 1 amp AEN IBMaddr 210 amp Select 2 amp AEN IBMaddr 310 4 Select 3 amp Generate 50 and RS1 for link adaptor Normal access RSO SAO RS1 SA1 54 DMA access RSO direction RS1 0 For B008 gt IBM direction 0 for gt B008 direction 1 RSO SAO amp DACK direction amp DACK RS1 SA1 amp DACK NAME IC6 interface REVISION 01 DATE 17 6 87 DESIGNER C Cytera COMPANY Inmos Ltd ASSEMBLY 8 DEVICE P22V10 Inputs PIN 1 PCIk PIN 2 1 PIN 3 notLADP PIN 4 notSYS PIN 5 notIOR PIN 6 notIOW PIN 7 notIBMError PIN 8 nc2 PIN 9 SAO 10 SA1 11 ModOnotError Outputs PIN 14 notBoardError PIN 15 write
9. MlONH TE 5 ES ANILNALAO ose 2446 91928 sa 07 5 O33dS NI3 81 NI32072 8 sv T 13938 59 7 5 uozv Ez SANINGVS za 8T 2 EM 00 6 HY 2755 99 36 98 38s9us BB6T BY _Asenuer lt Stor pow lt ATOEDOR 08704 ausunoog ezrs 5 8 eeuy 5 SA3H 8008 SWI 5 Dn o tror 4 5 6 5 SOMNI 172 8607 5 32312 242 4173 IN LIVMWAW TSYMWIWLON OGHMW3WLON Stv Wan trv LV gv TV 60 4 EG 57 5 22 2 555320 ry these H 075 aro eta Snnddvo T MOVLNBAS 12 Hy ON9 WOdWOH 1008 T
10. OWVHL 01216 ese 9 6 gt ie 2 S oz 40 01 8 0 2121 peeds yur sdqw oz 10 sdqw 01 Ile peeds 10 008 002 OSI 55 eseq 8 8 10 jeuueuo 1dnueyu zijeseg 10 jeuueuo seuouMs 1dnueju c o eseg 645 Ly sesn inq 584 8 snq od Wall 2 1 1 and Pipetail The link entering the first TRAM of the pipeline TRAMO link 1 is termed Pipehead and the link leaving the last TRAM TRAMOS link 2 is called Pipetail Pipehead is connected to the patch area so that the source of data entering the pipeline may be selected from the IBM PC via the IMS C012 or another transputer board via the 37 way D connector Pipetail is taken to the 37 Way D connector so that it may also be connected to another transputer board In this way a pipeline of many motherboards each con taining many transputers can very easily be constructed More sophisticated processing structures can also be built by using the remaining links of the TRAMs links 0 and 3 See section 2 2 2 1 2 Physical Location The physical location of the TRAM slots on the IMS 8008 is as shown Fig 2 The alternate orientation of adjacent T RAM slots is to improve the cooling effect of the air flow over the TRAMs It also means that if at any stage in the future a need is identified for
11. 0 DO WRITELN Finished polling WRITELN END PROCEDURE polllntflag BEGIN WRITELN Waiting for interrupt WHILE flagint FALSE DO WRITELN Interrupt complete WRITELN END PROCEDURE DMAwrite BEGIN flagint FALSE setupDMAC IBMtoBOO8 stringlength SEG datablock 0 OFS datablock 0 WRITELN C Transferring data to B008 PORT DMArequest writeDMA Trigger off DMA transfer polllntFlag Wait for interrupts END PROCEDURE DMARead Read the data block back from the T414 using DMA VAR strcount BYTE 41 msgback text msgbackarr ARRAY 0 maxlength OF BYTE ABSOLUTE msgback BEGIN flagint FALSE setupDMAC BOO8toIBM stringlength SEG msgbackarr 0 msgbackarr 0 WRITELN Reading data from B008 PORT DMArequest readDMA Trigger off DMA transfer pol1DMAC WRITELN Message received is msgback IF msgback teststring THEN WRITELN C Transfer counter successful END PROCEDURE drawswitches dmach badd intch INTEGER This procedure draws the appropriate switch settings but is not produced here because it is excessively long and drawn out Details of the source code can be found on the Test Examples Disc PROCEDURE switches Input the board setup and adjust constants accordingly BEGIN WRITE Base address of board 150 200 or 300 gt READLN boardbase WHILE boardbase
12. tink 4 Hardwired links Links softwired through IMS C004 Figure 13 Cube 46 Petersen Graph All ten slots are used by this network which does not leave a slot for a TRAM to run the TDS and MMS Therefore a second IMS B008 or another transputer board is required for this purpose No HL1 description for this network is included PipeTail Edge Link 0 Edge Link 2 Edge Edge Link 7 O Link 4 Ede PipeHead je Link 1 Edge Link 6 Edge Link 5 Link Hardwired links Links softwired through IMS C004 Figure 14 Petersen Net 47 Patch Area Pin Out This appendix shows the links which go to the 24 pin patch header and the default connections If any changes need to be made new header should be plugged in with the new connections made C012 Linkin C012 LinkOut PipeHead Linkin PipeHead LinkOut C004 LinkIn28 C004 LinkOut28 C004 Linkin29 C004 LinkOut29 C004 LinkinO C004 LinkOutO Linkin2 LinkOut 2 TRAMO LinkOutO TRAMO Linkino ConfigUp LinkOut ConfigUp Linkin Patch Patch LinkOut Patch Linkin1 LI Patch LinkOut1 EI T2 T2 TRAMA LinkOutt TRAMA Linkin1 Figure 15 24 way Patch Header Connections D Connector Pin Out notUpReset notUpError EdgeLinklIno EdgeLinkin1 EdgeLinkOut2 EdgeLinkOut3 EdgeLinkOut4 GND EdgeLinkin5 EdgeLinkin6 EdgeLinkin7 Patc
13. Jumper plug 1 should therefore be connected to PC as shown in Fig 4b TRAMS 1 9 as well as the IMS T212 must be connected as a subsystem of TRAMO This means that can reset and analyse all the other transputers in the system as well as read their error status facilitate this jumper plug 2 should be connected to SUBSYS as shown in Fig 4 The ConfigUp link of the IMS T212 link 1 must be connected directly to link 1 of TRAMO This link is known as Pipehead This enables the TRAM running the TDS and 52 to feed configuration data directly to the IMS T212 which passes it on to the IMS C004 This connection is made via the patch area as shown in Fig 4d A full description of the patch area is given in appendix F The IMS C012 link is connected to link 0 of TRAMO so that TRAMO always 12 boots down this link This connection is also shown in Fig 4d The other essential patch area connection is that of link 2 to TRAMA link 1 This is part of the pipeline which is routed through the patch area 2 4 2 A Single Board as a Target System In this application a bootable code file is sent directly to the transputer network from the IBM PC All the TRAMs are on the same level of hierarchy all under control of the PC A block diagram of this scheme is shown in Fig 5a Dnne 3 Xik2 11 2 1 3 N i M Subsystem
14. NI SNIT LNO OE DNI NI OE DINI ipo Be 823 0 s 2 1100 NIT 100 28 comm Pon ora 21100 92 62 de NT NIT 6 a 1 0 S2 ge a NI mi Um Qm 52 0 170 XNIT 2 0 NI INIT ren 1no INIT 9 Oe NI ino NI NI 100 DNI NI O2 NI1 100 6 NI 67 NIT 8T ANIT LNO 27 NI LY ANIT ino 9T DNI NI INIT 821 gt lt _EUTAUTASp Ot gt uuo ino NI ino NI 100 NI 100 NI 100 NI ino NI 100 NI ino NI 100 NI 100 NI 100 NI 100 NI 100 NI 100 NI ino NI 170 NI SY 51 vt 33 o OO Q mov OOD 51 21014221 gl 024014 55 255 15 40 53 OUINUTJSDON lt EGER PRSE D Ip gt OOZzF CO JMZzO2 OOZF TOJ em RT I PAL Equations NAME 105 IBM Address Select REVISION 01 DATE 17 6 87 DESIGNER C Cytera COMPANY Inmos Ltd ASSEMBLY 8 DEVICE P16L8
15. a lt Enter gt Then type Enter Messages should appear indicating the progress of the transfer which is repeated twice If the transfer is unsuccessful check the switch and jumper settings 19 Source code is also included on the Test Examples disc so that these procedures can be incorporated into user programs The occam source for the buffer is called buffer tar and should be manipulated with the INMOS folding editor It has been compiled and made into a bootable code file see TDS documentation called buffer bcf which is loaded into the transputer on TRAMO by the Turbo Pascal program Any popular editor e g Wordstar can be used on the pascal source for the DMA controller program The software has been written to use channel 0 If it is desired to use a different channel enter the channel number when the program is run The switch settings must also be changed to select the channel of your choice See appendix A for details 2 6 Interrupts 2 6 1 Why Interrupts It is sometimes undesirable to tie up CPU time on the IBM PC by contin uously polling the IMS B008 status registers Clearly it may be useful to put the host processor to work while the transputer array on the IMS B008 is running code For example the CPU on the PC could be updating the graphics screen while the transputer array performs a awesome number crunching computation The array could then signal the end of the compu tation with a
16. ErrIntSelect amp writeInt SDO amp writelnt DMAIntSelect amp writeInt Define Interrupt Signals IRQ InputInt amp InIntSelect OutputInt amp OutIntSelect notIBMError amp ErrIntSelect EndDMALatched amp DMAIntSelect IRQ3 IRQ IRQ5 IRQ Exclusively Enable Relevant Interrupt line IntEnable InIntSelect 8 OutIntSelect 8 ErrIntSelect DMAIntSelect IRQ3 oe IntLevelSelect amp IntEnable IRQ5 oe IntLevelSelect amp IntEnable NAME IC8 DMA control REVISION 01 DATE 17 6 87 DESIGNER C Cytera COMPANY Inmos Ltd ASSEMBLY 8 DEVICE P16L8 Inputs PIN 1 DACKO PIN 2 500 PIN PIN 4 DACK3 PIN 5 inputInt PIN 6 outputInt PIN 7 PIN 8 writeDMA 9 DMASe110 PIN 11 EndDMAFallEdge PIN 14 resetDRV 58 PIN 17 DMASel1 Outputs PIN 12 DACK PIN 13 DRQ3 PIN 15 DMAactive PIN 16 direction 0 IBM gt 012 1 C012 gt IBM PIN 18 DRQ1 PIN 19 DRQO Make field for switches as follows DMASeli DMASe10 Channel 0 enabled Channel 1 enabled DMA disabled Channel 3 enabled FIELD SWITCH 5 10 5 11 Latch direction of transfer direction SDO amp writeDMA direction amp writeDMA SDO amp direction Select acknowledge for channel being used DACK DACKO
17. This is to enable link 0 to be connected to the IBM bus via the IMS C012 device if so required Full details of the patch area are given in section 2 7 and appendix F The IMS C004 has 32 link inputs 32 link outputs and a configuration link Any of the 32 links may be connected to any other by sending the appropriate control data to the IMS C004 along its configuration link Thus link 0 or 3 of any TRAM on the board maybe connected to any other In addition since 8 links are taken from the IMS C004 to the 37 way D connector in addition to Pipetail it is possible to interconnect links from a great many boards in a very complex manner 2 2 2 Control of the IMS C004 The configuration link of the IMS C004 is connected to an IMS T212 16 bit transputer Links 1 and 2 of the IMS T212 are taken to the D connector so that they can be pipelined in the same manner as the TRAMs Configu ration data is passed in on link 1 and then passed out again on link 2 to the next IMS T212 and the next board in the chain Any configuration data appropriate to the board is sent to the IMS C004 on link 3 This mechanism is illustrated in Fig 3 On the first board in the chain ConfigUp is connected to Pipehead so that the configuration data is passed into the IMS T212 chain from the IBM PC via the TRAM in slot 0 This architecture is maintained on all INMOS motherboards so that a pipeline can be constructed from a variety of different boards
18. Turbo Pascal code for this is PORT DMArequest 0 Writing a 1 to this register starts a transfer in the other direction The request register is located at boardbase 12 where boardbase is the base address of the board as selected by SW4 and SW5 see appendix A As described previously two techniques can be used to determine the end of a transfer interrupt can be set up to occur when a transfer terminates in the example program this method is used to signal the end of the transfer to the IMS B008 With this method it is essential that bit 0 of the interrupt enable register on the IMS 008 is reset to 0 from within the interrupt service routine This clears the interrupt line as well as disabling DMA interrupts This bit must then be set back to 1 outside the service routine to re enable interrupts suitable place to do this is immediately before a DMA transfer is triggered off see the DMA write procedure in listing III appendix C An interrupt is asserted again when another DMA transfer completes second method of detecting the end of transfer is to poll the status register of the DMA controller See an 8237 data sheet for details For this technique to be successful a master reset command must be sent to the 8237 after each transfer This is done in the setupDMAC procedure shown in listing III appendix C In order to run the programs insert the examples disc and type
19. new address will have to be specified when the TDS is invoked from MS DOS The required format is TDS2 1 address where address is the base address of the board If the parameters are omitted then the base address defaults to 150 N B Throughout this manual the symbol is used to indicate a hexadecimal number However MS DOS does not recognise this notation and a 7 2 symbol must be used for this purpose in the address term above 3 1 2 Interrupt Setting board as supplied is set to use interrupt channel 3 If required channel 5 can be selected by switching Switch to OFF This should not be done 23 if the board is being used in a PC XT because channel 5 is used by the hard disc It is important to ensure that the interrupt line used by the IMS B008 is not used by any other device present in the PC In order to enable the IMS 008 to assert an interrupt its interrupt control register must be accessed See section 2 6 2 for details 3 1 3 DMA Channel Setting DMA channel 0 is selected by default This will not operate on the PC XT because channel 0 is not available on the XT bus However this default setting will not affect the normal operation of the PC XT Only channel 1 can be used by the IMS B008 on a PC XT but only if SDLC or another networking system which uses this channel is not present Channels 0 and 3 are normally free on the PC AT As with the PC XT channel 1 is reserved by IBM for
20. talk directly to the IBM T2LinkO This is the spare link of the T212 Its speed may be set indepen dently of the other links on the board see section 2 8 TRAMS3Link2 TRAMaALink1 These two links enable the 10 slot pipeline to be broken between TRAMs 3 and 4 if so required see section 2 1 A pin out of the patch area header block can be found in appendix F 2 8 Link Speed Selection The link speed of all the TRAMs on a board is switchable between 10 Mbits s and 20 Mbits s by means of the switch labelled Boardspeed However link 0 22 of the IMS T212 can run at a different speed to the TRAMs either 5 Mbits s 10 Mbits s or 20 Mbits s This could be useful for communicating with an external system whose links run at a different speed to that of the TRAMs Appendix shows the combinations possible 3 Configuration 31 Default Switch and Jumper Settings switches and jumpers on the IMS 8008 enable a large variety of oper ating modes The default settings are shown in Fig 10 and are described in the following sections 51514151 OFF Figure 10 Default Switch Settings 3 1 1 Board Address As supplied the board is set up to use locations 150 to 16F a sign indicates a hexadecimal number in the I 0 address space of the PC If this clashes with other cards present in your PC then the appropriate switch settings will have to be changed Refer to appendix A for details If the address is changed the
21. 1 Analyse register write only boardbase 10 Error location read only boardbase 12 request register boardbase 13 Interrupt control register Table 7 IMS B008 Register Memory Location 30 B 2 Functional Description A description of the IMS C012 registers the first four IMS B008 address locations can be found in the Transputer Reference Manual The other registers which are specific to the IMS 008 are described below B 2 1 Reset Register Setting bit 0 to 1 asserts the Reset signal Resetting bit 0 to 0 deasserts the Reset signal B 2 2 Analyse Register Setting bit 0 to 1 asserts the Analyse signal Resetting bit 0 to 0 deasserts to Analyse signal B 2 3 Error Location Reading a 1 in bit 0 indicates that Error is asserted Reading a 0 in bit 0 indicates that Error is not asserted B 2 4 DMA Request Register Writing 0 into bit 0 triggers a DMA transfer from the PC to the IMS B008 Writing 1 into bit 0 triggers a DMA transfer to the PC from the IMS 008 B 2 5 Interrupt Control Register Four bits are used in this register the functions of which are as follows Bit 0 Enable interrupt on DMA end Bit 1 Enable interrupt on error Bit 2 Enable interrupt when IMS B008 is ready to receive byte OutputInt on IMS C012 is active Bit 3 Enable interrupt when IMS B008 is ready to send byte Inputlnt on IMS C012 is active Table 8 Func
22. 9 askavny as Avay 9 SATYNY 8 1 81 45 7 4 2 1 V VIOSdSMNI1 OLNONNID TNIMNIT T ONDINE 1 ONDINIA ELDOXNIT 2 ENINNIA EL 28 41 W GOWLIG BOBH3SLON EL 2 5 ZHWS ZHWS 5 VWID3SdSHNID V 7IVIO3dSMNIT OLnOXNI1 TNIXNII ONIXNIA TIDONNIA ONTANI T 1 ELAOWNIT ENINNIA ENIMNIT ELDOXNIA W 222225 e GOWLIG pssdspJjuog HOHH310N 085310 13 5 S1VI93dSMNIT S1VIO3dSXNIA VYVIOSdSXNIA O1nOXNI1 TNIXNIA O1nOXNI1 ONIANII TLNOJNIT ELDOXNI ENINNI1 HEH 1 26 Bon 52 sr 0 2 0 nl 250 412 2 5 0 a xor 228 82H HOT 958 668 100 YE
23. E outByte b BYTE BEGIN Port outputData b WHILE NOT ODD Port outputStatus DO BEGIN END END PROCEDURE loopFor i INTEGER BEGIN WHILE i lt gt 0 DO iS 1 END PROCEDURE doReset BEGIN Port analyseT414 0 loopFor 800 Port resetT414 1 loopFor 3000 Port resetT414 0 loopFor 1000 END 38 PROCEDURE loadT4code VAR data BYTE bootcode FILE OF BYTE BEGIN ASSIGN bootcode buffer bcf RESET bootcode WRITELN Loading boot code to transputer REPEAT READ bootcode data outByte data UNTIL EOF bootcode TRUE WRITELN C Loaded code END PROCEDURE add24bit segment offset INTEGER VAR byteO bytei byte2 BYTE Produce a 24 bit address from a 16 bit segment and 16 bit offset Pass the result out as three bytes using variable parameters VAR result temp INTEGER a b carry BYTE BEGIN temp segment SHL 4 Bottom 12 bits of segment a temp AND FF b offset AND FF result byteO result AND FF carry result SHR 8 a temp SHR 8 b offset SHR 8 result a b carry bytel result AND FF carry result SHR 8 temp segment SHR 12 4 bits of segment byte2 temp carry END 39 PROCEDURE setupDMAC readnotwrite BYTE length segdata ofsdata INTEGER VAR addrO addri addr2 direction BYTE PROCEDURE addressandcount addrch pagech word
24. IMS 008 User Guide and Reference Manual User Manual INMOS Limited January 1988 72 TRN 138 00 You may not 1 Modify the Materials or use them for any commercial purpose or any public display performance sale or rental 2 Remove any copyright or other proprietary notices from the Materials This document is distributed in the hope that it will be useful but WITHOUT ANY WARRANTY without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE INMOS IMS OCCAM are trademarks of INMOS Limited INMOS Limited is a member of the SGS THOMSON Microelectronics Group Contents 1 Introduction 2 Hardware Description 2 11 Processor Pipeline 211 Pipehead and Pipetail 2 1 3 Physical Location 2 1 3 Pipe Jumpets und dE 2 2 The IMS C004 the IMS T212 and Softwired Links 2 2 1 The IMS C004 spina ae be he OR E 2 2 3 Control of the IMS C004 aaa aaa aaa 2 2 3 The Module Motherboard Software 52 2 3 Multi Transputer Systems 2 3 1 TRAM 24 Examples Bk Wak BoP 241 Single Board for Developing Software 2 4 2 Single Board as Target System 2 43 Cascaded Boards 2 4 4 Cascading more boards
25. INK 18 TO SLOT 8 LINK CA O LINK 9 TO SLOT 9 LINK C4 O LINK 19 TO SLOT 9 LINK 44 C4 O LINK 20 TO EDGE C4 O LINK 21 TO EDGE C4 O LINK 22 TO EDGE C4 O LINK 23 TO EDGE C4 O LINK 24 TO EDGE C4 O LINK 25 TO EDGE C4 O LINK 26 TO EDGE C4 O LINK 27 TO EDGE C4 O LINK 28 TO EDGE C4 O LINK 29 TO EDGE END o 1o0014 E Example Transputer Networks This appendix contains some example transputer networks together with their HL1 descriptions See the MMS User Manual for a description of HL1 E 1 Square SOFTWIRE SLOT 1 LINK 3 TO SLOT 6 LINK O SLOT 1 LINK O TO EDGE O SLOT 2 LINK O TO EDGE 1 SLOT 2 LINK 3 TO EDGE 2 SLOT 5 LINK O TO EDGE 3 SLOT 5 LINK 3 TO EDGE 4 SLOT 6 LINK 3 TO EDGE 5 END E 2 Cube SOFTWIRE SLOT 1 LINK O TO SLOT 4 LINK 3 SLOT 2 LINK O TO EDGE O SLOT 3 LINK O TO EDGE 1 SLOT 4 LINK O TO EDGE 2 SLOT 5 LINK O TO SLOT 8 LINK 3 SLOT 6 LINK O TO SLOT 3 LINK 3 SLOT 7 LINK O TO SLOT 2 LINK 3 SLOT 8 LINK O TO SLOT 1 LINK 3 SLOT 5 LINK 3 TO EDGE 3 SLOT 6 LINK 3 TO EDGE 4 SLOT 7 LINK 3 TO EDGE 5 END 45 Edge Link 0 Edge Link 1 TRAM 3 and TRAM 4 are jumped out To Pipetail via pipe jumpers 2 Edge Link 5 Edge Link 4 Hardwired links Links softwired through IMS C004 Figure 12 Square 0 Edge Link 2 Link To Pipetail via pipe jumpers Edge Link 5 Edge Link 1 Edge Link
26. Int PIN 16 notIBMReset PIN 17 notIBMAnalyse PIN 18 notWrite 19 notCS PIN 20 SDO PIN 21 writeDMA PIN 22 notStatWR FIELD Register 541 540 FIELD output notIBMReset notIBMAnalyse notStatWR Turn off asynchronous reset output ar 2590 55 Turn off synchronous preset output sp 200 Read and Write Declarations readsys notIOR amp notSYS writesys notlIOW amp notSYS readlink notIOR amp notLADP writelink notIOW amp notLADP writeReset writesys amp Register 0 writeAnalyse writesys amp Register 1 writeDMA writesys amp Register 2 writeInt writesys amp Register 3 Staticise notIOW notStatWR d Link Adaptor Timing Logic notCs writelink amp notStatWR readlink InotLADP amp notStatWR writelink notWrite Buffer wired or error signal to go off board notBoardError ModOnotError Error Flag Propogation to SDO notIBMError 5 0 readsys Latch reset and analyse registers from IBM bus notIBMReset d notIBMAnalyse d SDO amp writeReset notIBMReset amp writeReset SDO amp writeAnalyse notIBMAnalyse amp writeAnalyse NAME IC7 Interrupt control REVISION 01 DATE 17 6 87 DESIGNER C Cytera COMPANY Inmos Ltd ASSEMBLY DEVICE P22V10 Input
27. SDLC but again it may be used if this or another network is not fitted See appendix A for details of the switch settings required to select the ap propriate DMA channel Alternatively DMA may be disabled altogether 3 1 4 Link Speed Selection links are set to run at 20 Mbits s See appendix A for information on changing the link speed settings 3 1 5 Jumper Positions It is assumed that at this stage the TDS is being run on a TRAM plugged into slot 0 In this case the jumper blocks and patch area should not be disturbed For details of other possible board configurations see section 2 3 1 4 Unpacking and Handling 4 1 Unpacking the IMS 008 When you open the packing box in which the IMS 008 is shipped you will find 24 1 packing list which you should check against the box contents imme diately 2 A documentation pack including this manual 3 A floppy disk entitled IMS B008 Examples Test which contains some example routines and some test software 4 An anti static bag containing the IMS B008 board 5 A link breakout board 6 An IMS cable set Do not open the bag containing the IMS B008 until you have read the section on handling 4 2 Handling Precautions To prevent damage from static discharge certain precautions should be taken when removing the board from its protective bag 1 While holding the board in one hand still in its bag touch metal part of your PC with
28. Selection Switches 6 8 IMS 008 Registers Location in Memory B 2 Functional Description 2 1 2 2 2 3 2 4 2 5 Reset Register Analyse Error 1 0 ix Lec 5 wu turae Request Register Interrupt Control Program Listings Listing I Basic Data Transfer Routines C 2 Listing Occam Buffer Program Listing DMA Transfer Program Description of IMS 008 Link Connections Example Transputer Networks E Square ox eee Eee euge reas E 2 Cube Petersen Patch Area Pin Out D Connector Pin Out Circuit Diagram PAL Equations 32 32 33 34 44 45 45 45 47 48 48 49 54 Preface IMS B008 is TRAM TRAnsputer Module motherboard that enables users to build multi transputer systems that can be plugged into an IBM PC XT or PC AT The board is member of a family of TRAM motherboards which have a compatible architecture External signals are available which enable it to control a subsystem of motherboards or to be a component of such a subsystem For a general description of TRAMs and motherboards refer to the speci fication Dual In Line Transputer Modules TRAMs publish
29. Single In Line TRAMs they would be compatible with the existing motherboards Figure 2 IMS B008 TRAM Slot Location 2 1 3 Pipe Jumpers Some TRAMs physically cover more than one slot on the IMS 8008 al though they only connect to the signals of one position In most cases it is possible to stack other TRAMs on top so that the covered slots are not wasted However if stacking is not required the pipeline will be broken at the slots that are underneath the larger TRAMs Special 8 pin plugs called pipe jumpers are provided to combat this problem These plug into the unused slot and connect the signals for links 1 and 2 together thus contin uing the pipeline through to the next TRAM in the chain pipe jumper is required at one end of each empty slot only with its marker band lining up with the triangle on the motherboard 2 2 IMS 004 the IMS T212 and Softwired Links Links 1 and 2 of each TRAM slot are used in the formation of the processor pipeline This leaves links 0 and 3 of each TRAM for connection to other processors so that more topologically complex systems can be constructed The method of control of these connections is explained in the following sections 2 2 1 The IMS C004 The IMS B008 has been designed such that TRAMO link 3 and TRAMs 1 9 links 0 and 3 are taken directly to the IMS C004 a 32 way link switch In fact TRAMO link 0 can also be connected to the IMS C004 but only via the patch area
30. Thus when the DMA controller transfers data to the IMS 008 the queue fills up It is then emptied by transfer from the IMS B008 to the PC program on the IBM is also required to load up TRAMO with the buffer program set up the DMA controller and initiate the transfer outline of this program is as follows Set up constants Initialise interrupt vectors and controller chip Reset on IMS B008 Initialise IMS C012 on IMS 008 Boot up TRAMO with buffer program REPEAT TWICE Enable interrupts from IMS B008 Set up controller for transfer to IMS 008 Trigger transfer to IMS 008 Wait for interrupt to signal transfer complete Set up DMA controller for transfer to IBM PC Trigger DMA transfer to IBM PC Poll DMA controller status to determine end of transfer Compare received data with original transmitted data code is written in Turbo Pascal and shown in appendix C listing Ill setupDMAC procedure initialises the various registers of the 8237 for the required mode of operation No attempt will be made here to describe 18 these modes 16 is simply advised that this procedure is copied for user applications Detailed information can be found in an 8237 data sheet Once the 8237 has been set up a DMA transfer is triggered by writing to a single register on the IMS B008 Writing a 0 to the request register initiates write transfer to the IMS B008 The
31. amp SWITCH O DACK1 amp SWITCH 1 DACK3 amp SWITCH 3 Set DMAactive when writeDMA is active Clear DMAactive at end of DMA cycle or at power on DMAactive writeDMA DMAactive amp EndDMAFallEdge resetDRV Generate DMA requests DRQ inputInt amp direction outputInt amp direction amp DMAactive DRQ amp SWITCH O 2801 DRQ amp SWITCH 1 DRQ3 DRQ amp SWITCH 3 DRQO oe SWITCH O 0801 SWITCH 1 0803 SWITCH 3 59
32. at a lower hierarchical level 2 4 Examples In order to aid the understanding of the way in which a hierarchy is es tablished the selection of TRAM hierarchy on a single board will first be explained Three examples of board hierarchy are then described in the sections which follow 2 4 1 Single Board for Developing Software A block diagram of an IMS B008 configured in this way is shown in Fig 4a This is the configuration in which the board is supplied and is explained in the following paragraphs It is assumed that the Transputer Development System TDS is being used for software development T DS should be run on TRAM plugged into TRAM slot 0 of the IMS B008 Consequently the reset analyse and error functions of this must be under control of a program running the 11 5 N 5 5 5 N 2 gt 2 2 2 H H 2 2 2 D D 7 2 2 2 2 2 2 2 2 Hierarchy of TRAMs EDGE DOWN eee eee BIR 4 JP1 4 JP2 PC SUBSYS b Jumper plug 1 c Jumper plug 2 C012 Linkin TRAMO LinkOut C012 LinkOut TRAMO PipeHead Linkin ConfigUp LinkOut PipeHead LinkOut ConfigUp Linkin For tsk not shown TRANS Linkin2 TRAMA LinkOutt LinkOut 2 TRAMA Linkin1 d Patch area connections Figure 4 Single Development Board Configuration IBM PC
33. cessor memory and peripheral functions and which communicate with the outside world by means of INMOS serial links arranged in a standard DIL pin out Links 1 and 2 from each of the TRAM slots are hard wired on the IMS B008 such that the T RAMs when plugged in form a pipeline of processing elements The remaining links can be soft wired using an INMOS IMS C004 programmable link switch incorporated on the IMS B008 This arrangement allows a large variety of networks to be created under software control full block diagram of the IMS 8008 is shown in Fig 1 IMS C004 device is controlled by an IMS T212 16 bit transputer Con figuration data for the IMS C004 is fed into link 1 of the IMS T212 which then passes it on to the IMS C004 on link 3 T he same data is also passed out of the IMS T212 link 2 to the 37 way D connector on the edge of the board In this way IMS B008 boards can be cascaded with the IMS T212 s forming a chain Configuration data passes down this chain with each IMS T212 sending the appropriate data to the IMS C004 to which it is connected An interface to the IBM bus is provided so that a program running on the IBM PC can control the TRAMs on the IMS B008 and pass data to or from them Data communication can take place by means of a software routine which uses polling or via DMA mechanism which gives a higher data rate Different events on the IMS 008 selectable by the programmer can generate an inter
34. ch BYTE Set up start address and length of transfer DMAC for apt channel BEGIN port port port addrch addrch 1 pagech addr2 wordch wordch port port END BEGIN PORT DMAmastclr 0 add24bit segdata CASE DMAchannel OF Set up address ls byte Set up address middle byte Put address msb in page reg length AND FF Length of data block length SHR 8 Reset DMAC ofsdata addrO addri addr2 0 addressandcount addrch0 0 wordch0 1 addressandcount addrchi pagechi wordch1 3 addressandcount addrch3 pagech3 wordch3 END case PORT DMAmode Binary mode word PORT DMAcommand 00 00 OR readnotwrite OR DMAchannel Set up mode register chO select read or write transfer autoinit disable address increment demand mode 0000 10cc IBM gt 008 0000 01 008 gt Set up command register mem to mem off chO address hold disable controller enable normal timing fixed priority late write DREQ active high 40 DACK active low Binary command word 0000 0000 PORT DMAallmask 0 Clear apt channel mask bit END PROCEDURE poliDMAC 11 DMAC status register until transfer has completed VAR chanmask BYTE BEGIN chanmask 1 SHL DMAchannel WRITELN Polling DMA controller Bit for apt channel WHILE PORT DMAstatus AND chanmask
35. ection The transfer proceeds with the IMS B008 making a DMA request for a single byte at a time In this way a byte is transferred in between the execution of each instruction of the processor the PC Therefore this processor appears to be running code at the same time as the DMA transfer is taking place It is mainly for this reason that it is difficult to specify the improvement in data throughput One example will be given for an 8 MHz iAPX 286 CPU 17 and 5 MHz controller transfer has approximately twice the data rate of an optimised assembly code routine which uses polling This figure was derived with the processor doing nothing other than waiting for the end of the DMA transfer end of the transfer is signalled in one of two ways controller can be polled by reading its status register This gives informa tion about which DMA channels have a transfer pending and which have completed a transfer See an 8237 datasheet for further information Alter natively an interrupt can be set up to signal the end of a DMA transfer See section 2 6 2 5 3 Example Programs A buffer process written in occam runs on the transputer on TRAMO Its source code is given in appendix C listing II T his process inputs data down link 0 and stores it in memory as a queue When another device in this case the IMS C012 on the IMS B008 becomes ready to read this data TRAMO sends it back down link 0
36. ed as INMOS Technical Note 29 and the Module Motherboard Architecture manual For information on the transputer itself refer to the Transputer Reference Man ual The IMS B008 is designed to be compatible with the Transputer Develop ment System TDS and the Module Motherboard Software 52 These can run either on a suitable TRAM plugged into the IMS B008 or on an other piece of hardware connected to the IMS B008 via an INMOS link Reference should be made to the TDS User Manuals and the MMS2 User Manual for details of how to compile and load programs onto networks of TRAMs plugged into motherboards NOTE Details of how to unpack and install the IMS 008 are given in chapter 4 This chapter should be read carefully before any power is applied to the board Disclaimer Every effort has been made to test the correct operation of this product INMOS reserves the right to make changes in specifications at any time and without notice The information furnished by INMOS in this publication is believed to be accurate but no responsibility is assumed for its use nor any infringements of patents or other rights of third parties resulting from its use No licence is granted under any patents trademarks or other rights of the INMOS group of companies 1 Introduction IMS B008 is TRAM motherboard which plugs into the PC or PC AT It has slots for up to ten TRAMs TRAMs are board level transputers that integrate pro
37. elect the base location in the I 0 address space at which the IMS 008 appears or to disable the board from the IBM bus altogether The following table shows the options available SW4 SW5 Address hexadecimal ON ON Not selected OFF ON 150 ON OFF 200 OFF OFF 300 Table 5 Base Address Selection 29 4 Link Speed Selection Switches 6 8 All the TRAMs and the IMS C004 must have identical link speeds The IMS T212 can however have its link 0 running at different speeds Table 6 shows the combinations possible SW6 SW7 SW8 T212 Link 0 Other Links ON ON ON 10 Mbits s 10 Mbits s ON ON OFF 5 Mbits s 10 Mbits s ON OFF ON 10 Mbits s 10 Mbits s ON OFF OFF 20 Mbits s 10 Mbits s OFF ON ON NON FUNCTIONAL OFF ON OFF NON FUNCTIONAL OFF OFF ON 10 Mbits s 20 Mbits s OFF OFF OFF 20 Mbits s 20 Mbits s Table 6 Link Speed Selection B IMS BO008 Registers This appendix contains a summary of the registers of the IMS B008 and the locations in the I O address space at which they appear In Table 7 boardbase is as selected by SW4 and SW5 see appendix B 1 Location in Memory Board address Register boardbase 00 Input data register boardbase 01 Output data register boardbase 02 Input status register boardbase 03 Output status register boardbase 4 10 Reset register write only boardbase 1
38. etails of how to use this interface the operation of the IMS C012 link adapter must be understood details of this device are included the Transputer Reference Manual Example procedures for accessing the IMS 008 written in Turbo Pascal are given in appendix C listing I source code is also included on the Test Examples disc with the filename ladp pas Before any data can be sent to the IMS 8008 the board must first be reset by software This can be done by using the procedure called doReset in appendix C listing I For a summary of the IMS 8008 registers and where they appear in the 1 0 address space see appendix B 2 5 2 Direct Memory Access For higher data rates a DMA interface has been incorporated into the IMS B008 In order to use this mechanism it is useful to understand the operation of the 8237 DMA controller chip present in the IBM PC Details can be found in an 8237 data sheet Once the DMA controller has been initialised the DMA interface may be used in several different ways In the example software appendix C a process is started on to input and output data down its link 0 which is connected to the PC bus via the IMS C012 transfer is then triggered off by the program running on the PC which must write to the control register on the IMS B008 value 0 is written to transfer from the PC to the IMS B008 717 is written to transfer in the other dir
39. hLinkOutO PatchLinkOut1 notSubSystemReset notSubSystemError PipeTailLinkIn ConfigDownLinkin notDownAnalyse 1 GND 20 2 notUpAnalyse 21 sd 3 22 4 EdgeLinkin1 23 5 GND 24 6 EdgeLinkIn2 25 7 EdgeLinkin3 26 8 EdgeLinkin4 27 9 EdgeLinkOut5 28 10 EdgeLinkOut 29 11 EdgeLinkOut7 30 12 GND 31 13 PatchLinkInO 32 14 PatchLinkInt 33 54 15 notSubSystemAnalyse 16 PipeTailLinkOut 35 17 ConfigDownLinkOut 36 18 notDownReset 37 notDownError Figure 16 37 way D Connector Pin Out 48 lagram 388uS BB6T et Kjenusr J8equnN aueunaogjezrs 92e 403UI WEI 8008 SWI 9 75 SOWNI IN v E TMS d 5 2 i 0138SVWG oS lt lt wor 6 18 su 029 6 ATS 4580 8GB 658 EDHI 8 081 8 0880 6 49 ircuit D H C issu 5 8 BOILON MOTION 45 13065 35 gt SOHHSIONOOOR XL jSssungpisu 236 ura srg 714 50 ano 5 9 33A jo 2109 GN901030H SOLON I z xe H lt 3noxurTgr02 5 5
40. hes WRITELN switch settings on the board should be as follows WRITELN drawswitches DMAchannel boardbase intchannel WRITE CPress ENTER when switches are correctly set READLN default initConst initINT transfers 0 teststring This is DMA test doReset 012 loadT4code FOR counter 1 TO 2 DO BEGIN WRITELN abe ie cer 2 WRITELN PORT INTenable DMAInt Enable interupts DMAwrite DMAread 43 END END D Description of IMS B008 Link Connections SIZES T2 1 C4 1 SLOT 10 EDGE 10 END T2 CHAIN T2 0 LINK 3 C4 O END HARDWIRE SLOT O LIN SLOT 1 LIN SLOT 2 LI SLOT 3 LI SLOT 4 11 SLOT 5 LI SLOT 6 LI SLOT 7 11 SLOT 8 LIN TO SLOT 1 LINK TO SLOT 2 LINK TO SLOT 3 LINK TO SLOT 4 LINK TO SLOT 5 LINK TO SLOT 6 LINK TO SLOT 7 LINK TO SLOT 8 LINK TO SLOT 9 LINK C4 O LINK 10 TO SLOT O LINK O LINK 1 TO SLOT 1 LINK O LINK 11 TO SLOT 1 LINK C4 O LINK 2 TO SLOT 2 LINK C4 O LINK 12 TO SLOT 2 LINK O LINK 3 TO SLOT 3 LINK C4 O LINK 13 TO SLOT 3 LINK O LINK 4 TO SLOT 4 LINK C4 O LINK 14 TO SLOT 4 LINK O LINK 5 TO SLOT 5 LINK C4 O LINK 15 TO SLOT 5 LINK O LINK 6 TO SLOT 6 LINK C4 O LINK 16 TO SLOT 6 LINK O LINK 7 TO SLOT 7 LINK C4 O LINK 17 TO SLOT 7 LINK C4 O LINK 8 TO SLOT 8 LINK C4 O L
41. ish to reset every time the application network is reset The hierarchical structure of a system is defined by the source of the notRe 10 set and notAnalyse control signals JP1 determines the control of TRAMO while JP2 determines the control of TRAMs 1 9 2 3 1 TRAM Hierarchy The TRAM in slot 0 may be reset and analysed by either the IBM PC or by another board via the 37 way D connector This choice is made by selecting the position of JP1 Three jumpers are provided one for each of the notReset notAnalyse and notError signals Setting JP1 to PC see Fig 4b gives the PC the ability to reset and analyse TRAMO In addition the PC will also be able to read the error flag of TRAMO Alternatively all these functions can be controlled via the 37 way D connector by setting JP1 to EDGE Fig 7b Similarly the TRAMs in slots 1 9 maybe controlled by the subsystem port of or they may be put on the same hierarchical level as in which case their control depends upon the position of JP1 Setting JP2 to SUBSYS Fig 4c puts the reset analyse and error functions of TRAMS 1 9 under control of TRAMO Setting JP2 to DOWN Fig 5c puts TRAMS 1 9 at the same level as TRAMO It is defined in Dual In Line Transputer Modules TRAMs Technical Note 29 that any TRAM that has a subsystem port must reset that port if it is itself reset Thus reset signal will always propagate to all TRAMs
42. l interrupts are disabled altogether 21 2 7 The Patch Area patch area consists of a 24 pin DIL header block that can be wired ac cording to the users requirements INMOS link is a two wire connection implying that 12 links are taken to the patch area These are C012Link TRAMOLinkO These two links should be connected together when it is intended that the IMS 008 is to transfer data between itself and the IBM bus In order to maintain compatibility with IN MOS software it is highly recommended that C01121 ink is only ever connected to TRAMOLink0 and never to Pipehead which is in effect TRAMoOLink1 Pipehead This is TRAMOLink1 the beginning of the pipeline of proces 8018 ConfigUp This is IMS T212 link1 It is the link upon which the IMS C004 configuration data is received It may be connected via the patch area to either one of the 37 way D connector links or to Pipehead if the configuration data is to come from the IBM bus via TRAMO PatchLink0 PatchLink1 These two links are connected to the 37 way D connector Generally if they are used they are connected to ConfigUp and Pipehead respectively although they may be connected to any of the other links available CO004Link0 COOA4Link28 COOALink29 These three links are connected to the IMS C004 link switch can be used for example to provide extra IMS C004 links to the D connector or to connect TRAMOLink0 to the IMS C004 on a board which does not
43. link transfer which can be made to interrupt the host CPU from its mundane task and tell it that the answer to the question is now available 2 6 2 IMS 008 Interrupt Capability The IMS B008 can interrupt the IBM PC on any of four events 1 A DMA transfer has completed 2 An error has occurred on the IMS B008 3 The IMS 008 is ready to receive a byte of data via the IMS C012 4 IMS 008 is ready to send a byte of data via the IMS C012 The interrupt control register located at boardbase 13 is used to deter mine which of these events cause an interrupt Four bits in this write only register are used one for each event see Table 2 20 Bit 0 Enable interrupt end Bit 1 Enable interrupt on error Bit 2 Enable interrupt when IMS B008 is ready to receive byte OutputInt on IMS C012 is active Bit 3 Enable interrupt when IMS B008 is ready to send byte on IMS C012 is active Table 2 Interrupt Control Register Function other bits at this location are unused In all cases setting a bit to 71 enables interrupts the corresponding event Clearing a bit disables interrupts on that event Note that any number of these events can be programmed to cause an interrupt but that the interrupt will occur on the same channel regardless of the event It is a simple matter for the interrupt service routine to read a few status registers to determine the cause of the inte
44. lt gt 150 AND boardbase lt gt 200 AND boardbase lt gt 300 DO BEGIN WRITE Base address of board 150 200 or 300 gt READLN boardbase END WRITE channel selected 0 1 or 3 gt READLN DMAchannel WHILE 1 lt gt 0 AND DMAchannel lt gt 1 AND DMAchannel lt gt 3 DO BEGIN WRITE channel selected 0 1 or 3 gt READLN DMAchannel END WRITE CInterrupt level 3 or 5 READLN intchannel WHILE intchannel lt gt 3 AND intchannel lt gt 5 DO BEGIN WRITE Interrupt level 3 or 5 42 READLN intchannel END WRITELN END BEGIN Program Body WRITELN This software is designed to test the DMA operation WRITELN the INMOS IMS B008 module motherboard In order WRITELN to run the test it is necessary to provide the WRITELN software with the base address of the board and the WRITELN and interupt channels used WRITELN The default values for these parameters are WRITELN WRITE C Base address CASE boardbase OF 150 WRITELN 21509 200 WRITELN 72009 300 WRITELN 73009 END WRITE C DMA channel WRITELN DMAchannel WRITE C Interupt channel WRITELN intchannel WRITELN WRITE CDo you wish to change these default values READLN default IF default yes OR default YES default y OR default Y THEN switc
45. of hierarchy can be controlled by on one board The boards on the same level should be linked by connecting the DOWN port of one to the UP port of the next See Fig 8 Multiple levels of hierarchy can be created by extending the principles outlined earlier in this chapter See Fig 9 PC bus System registers 1 BOARD2 ee MET BOARD4 9 c sss P222 P224 Figure 8 Two level board cascade PC bus System registers BOARD 1 M SUBSYSTEM DOWN UP BOARD E BOARD 3 SUBSYSTEM Eee 22 up DOWN DOWN UP BOARD4 SS BOARD 5 BOARD 6 N Mss ASA RAS rz gt gt M 9 9595 Figure 9 Multiple levels of hierarchy 16 2 5 IBM Bus Interface 2 5 1 Polling This is the simplest method of data transfer between the IBM PC and the IMS B008 Earlier INMOS boards the IMS B004 for example have this as the only data transfer mechanism interface on the IMS B008 is completely compatible with these For d
46. rogram PROC listener declarations VAL LinkOout IS O 33 VAL Linktout IS 1 VAL Link2out IS 2 VAL Link3out IS 3 VAL LinkOin 154 VAL Linklin IS 5 VAL Link in IS 6 VAL Link3in IS 7 VAL size IS 50 CHAN OF BYTE 0 012 012 size 1 CHAN OF BYTE pipes PLACE to CO12 AT LinkOout PLACE from CO12 AT LinkOin PAR PAR i O FOR size Create one process BYTE data per queue position WHILE TRUE SEQ pipes i data Shift character up in queue pipes i 1 data PAR BYTE data SEQ WHILE TRUE SEQ 012 7 data Get data from 0012 pipes 0 data Put at bottom of queue BYTE data SEQ WHILE TRUE SEQ pipes size data Take data off top of queue to C012 data Send data to C012 PLACED PAR PROCESSOR O T4 listener O C 3 Listing III DMA Transfer Program PROGRAM dma This program sands a string of characters to the transputer on 34 the IMS 8 via the interface then reads them back and prints them out A buffer process sits on the transputer which inputs characters and puts them into a queue It also takes characters out of the other end of the queue and sends them back to the link adaptor This process is present on the examples floppy as a bootable code file it is sent to TRAMO on the IMS 008 by the turbo pascal procedure called loadT4code CONST B008 registers boardbase inputData outputData inputStatus outputStat
47. rrupt The error flag OutputInt and InputInt are all status bits present in IMS B008 registers see appendix Interrupt on end of can be detected by reading the status register of the 8237 DMA controller Note that when the IMS B008 powers up all these control bits are at 0 In this situation the selected IMS B008 interrupt line is tri stated As soon as any of the control bits are set to 1 the selected line is driven to logic 0 It is driven to logic 1 when the chosen event occurs It is therefore important that this register is not written to if other peripherals in your PC use interrupt lines 3 and 5 The IMS B008 may be damaged if this instruction is not followed Switch 3 should be ON to select IRQ3 OFF to select IRQ5 2 6 3 Examples Section 2 5 3 illustrates how to use interrupts to signal the end of the DMA transfer It is vitally important that the interrupt service routine clears bit 0 of the interrupt control register to disable the interrupt signal If this bit is then set back to 1 outside the service routine interrupt on DMA is re enabled but not reasserted until another DMA transfer completes Interrupts can also be used to signal when the IMS 8008 has data to transfer to the IBM PC InputInt from IMS C012 is asserted or when it is ready to receive data OutputInt asserted In both cases the interrupt line will re main asserted until the data has been read from or written to the IMS 008 or unti
48. rupt on the IBM PC This eliminates the need for the processor in the PC to continuously poll status registers on the IMS 008 so that the PC can carry on with other tasks while programs are running on the IMS B008 2 Hardware Description 2 1 Processor Pipeline IMS B008 TRAM motherboard has 10 TRAM slots sufficient to ac commodate a maximum of 10 TRAMs The IMS 8008 is hard wired such that TRAM N link 2 is connected to TRAM N 1 link 1 producing a 10 TRAM pipeline configuration However link 2 and TRAMA link 1 are taken to the patch area so that this pipeline can be broken if the user application so demands peuorjounjg 8009 SINT T q ze op lt _ gt 4 f 7 7 7 7 0j Dowrwoied 2 98068060 211 SWI 0 7 9 1 1 1 snqwg 2 1eModsowe _ jepee lt gt 8 UDIMS 7009 SII 3 3d Syul eseu snq Wa 1 syu 10 27 ueAup s 0 19501 1 pele 5 yed 4 4 f v 101S f 2 Xn 101 peeyedid L 2 2 T gt gt puruyored 1 4 2121 SWI pue 0 25 6 0 5 OI Jesoy 1 21015 1015 0105 2109 1 5 0 WYYL urejs sqng m m oie
49. s 56 PIN 1 PClk PIN 2 500 PIN 3 8 1 4 8 2 PIN 5 503 PIN 6 notIOW PIN 7 EndDMA PIN 8 writeInt PIN 9 InputInt PIN 10 OutputInt PIN 11 notIBMError PIN 13 IntLevelSelect 0 gt IRQ3 1 gt IRQ5 utputs PIN 14 InIntSelect PIN 15 OutIntSelect PIN 16 ErrIntSelect PIN 17 DMAIntSelect PIN 18 StatEndDMA 19 IntEnable PIN 20 EndDMAFallEdge PIN 21 IRQ5 PIN 22 IRQ3 PIN 23 EndDMALatched FIELD output InIntSelect OutIntSelect ErrIntSelect DMAIntSelect notStatWR StatEndDMA EndDMAFallEdge EndDMALatched Switch off all async resets output ar b 0 Switch off all sync presets output sp 250 Have to write this out again because of yet another CUPL bug output ar b 0 Staticise EndDMA pulse StatEndDMA d EndDMA Produce pulse on falling edge of EndDMA EndDMAFallEdge d StatEndDMA amp EndDMA 57 Set EndDMALatched on EndDMAFallEdge clear it when software clears DMAIntSelect bit EndDMALatched d DMAIntSelect amp EndDMAFallEdge EndDMALatched Interrupt source selection latches InIntSelect d OutIntSelect d ErrIntSelect d DMAIntSelect d SD3 amp writelnt 8 InIntSelect 4 writeInt 502 amp writelnt OutIntSelect amp writeInt 501 amp writelnt 8
50. se 11 DMArequest boardbase 12 INTenable boardbase 13 CASE intchannel OF 5 BEGIN intmask DF intvec 34 eoi 65 END 5 3 36 intmask F7 intvec 920 eoi 63 END 3 END case END PROCEDURE IntDMA Interrupt service routine for end of DMA transfer Sets flagint TRUE BEGIN INLINE 50 53 51 52 56 57 1E 06 FB Stack registers flagint TRUE Flag that DMA has ended PORT INTenable 0 Toggle INTenable to clear interrupt PORT PICbase eoi Send specific EOI to PIC INLINE 07 1F 5F 5E 5A 59 5B 58 CF Unstack END PROCEDURE initINT Set up interrupt stuff VAR IntServAddr INTEGER OldMask BYTE BEGIN IntServAddr OFS IntDMA spurioustuff MEM 0000 intvec 0 MEM 0000 intvec 1 MEM 0000 intvec 2 MEM 0000 intvec 3 IntServAddr AND FF IntServAddr SHR 8 CSEG AND FF CSEG SHR 8 OldMask PORT PICbase 1 Clear mask for IRQ3 or 5 PORT 1 OldMask AND IntMask PORT INTenable 0 Disable interrupts from 008 END PROCEDURE initC012 37 Port inputStatus Port outputStatus END 2 Enable inputInt 2 Enable outputInt FUNCTION dataPresent BOOLEAN BEGIN dataPresent ODD Port inputStatus END FUNCTION outputReady BOOLEAN BEGIN outputReady ODD Port outputStatus END PROCEDUR
51. slot 0 c Alternate orlentation of adjacent TRAMs Figure 11 TRAM Installation lt Enter gt to continue The program then tests various parts of the board in sequence It is not exhaustive but it will check whether the board has been set up and installed correctly If the program reports that it cannot find TRAMO check the orientation of TRAMO and the address switch settings Any other error messages should bear an obvious relation to the relevant switch settings If all is well it is time to use the test software which explores the IMS B008 and finds all the TRAMs present The TDS must therefore be installed refer to the TDS literature for instructions Full details of using the TDS and 28 the 52 are given in the appropriate manuals This is the correct time to examine those manuals and try some programming examples Return to this manual when more advanced features specific to the IMS 008 are to be used e g cascading boards and using the DMA interface Switch Settings A 1 DMA Channel Switches 1 2 This is selected according to Table 3 SW1 SW2 DMA Channel ON ON 0 OFF ON 1 ON OFF DMA disabled OFF OFF 3 Table 3 DMA Channel Selection A 2 Interrupt Channel Switch 3 This is selected according to Table 4 SW3 Interrupt Channel ON 3 OFF 5 Table 4 Interrupt Channel Selection A 3 Board Address Switches 5 6 Two switches are used to s
52. the other hand 2 Carefully remove the board from the bag holding the board by the edges only Avoid touching any components or connections 3 While manipulating switches and jumpers on the board and when inserting it into the PC hold the board by its edges only 4 If the board is being stored or shipped standard anti static handling precautions should be observed N B Under no circumstances plug or unplug a TRAM with power applied to the IMS B008 Permanent damage to both the and the motherboard could occur 4 3 TRAM Fitting and Handling TRAMs must be carefully installed and removed from the IMS B008 taking special care not to bend any of the TRAM s pins The slots on the IMS B008 have pin 1 marked on the board by a silk screened legend a triangle Pin 1 the TRAM to be installed will also be marked in a similar manner 25 Plugging in TRAM the wrong way round may result in the destruc tion of the TRAM or the motherboard IMS B008 has some components mounted on the top as opposed to the underside of the board in the positions occupied by some TRAM slots slots 8 and 9 When plugging a TRAM into these positions it will be necessary to fit stand off strips to the TRAM pins These are 8 way pin strips which plug into the IMS B008 and raise the T RAM above the motherboard These stand off strips are supplied fitted to INMOS TRAMs 4 4 Installing an IMS 008 with a single TRAM fitted
53. ting together are shown in Table 1 Board 1 Pin No Board 2 Pin No notSubSystemReset 33 notUpReset 20 notSubSystemAnalyse 15 notUpAnalyse 2 notSubSystemError 34 notUpError 21 PipetailLinkOut 16 PatchLinklnl 14 PipetailLinkln 35 PatchLinkOut1 32 ConfigDownLinkOut 17 PatchLinkln0 13 ConfigDownLinkln 36 PatchLinkOut0 31 Table 1 NOTE Switches 6 7 and 8 may have to be adjusted if these same OFF Switch settings EDGE DOWN Sussvs b Jumper plug 1 c Jumper plug 2 PipeheadLinkin ConfigUpLinkOut PipeheadLinkOut ConfigUpLinkin PatchLinkOutt E cai d Patch area connections Figure 7 Cascaded Boards Board 2 Switch and Jumper Settings Board 2 should be invisible to the IBM bus Its link adapter and system registers should therefore be disabled This is done by setting switches 4 and 5 to ON as shown in Fig 7a on board 2 should be controlled by the signals coming in on the UP port Hence jumper plug 1 should be set to UP as shown in Fig 7b 15 In this example the IMS T212 and TRAMs 1 9 on board 2 are on the same level of hierarchy as Therefore jumper plug 2 should be set to DOWN as shown in Fig 2 4 4 Cascading more boards More boards may of course be cascaded Other INMOS boards e g IMS B004 IMS B012 can be present in the cascade Many boards on the same level
54. tional Description of the Interrupt Control Register 31 C Program Listings C 1 Listing I Basic Data Transfer Routines 15 is a set of procedures for communicating with the IMS 008 via the IMS 0012 link adaptor CONST linkBase 0150 inputData 0150 outputData 0151 inputStatus 0152 outputStatus 0153 resetT414 0160 analyseT414 0161 PROCEDURE initC012 BEGIN Port inputStatus 0 finputInt disabled Port outputStatus 0 foutputInt disabled END FUNCTION dataPresent BOOLEAN BEGIN dataPresent ODD Port inputStatus END FUNCTION outputReady BOOLEAN BEGIN outputReady ODD Port outputStatus END PROCEDURE outByte b INTEGER BEGIN Port outputData b WHILE NOT ODD Port outputStatus DO BEGIN END END 32 FUNCTION inByte INTEGER BEGIN WHILE NOT ODD Port inputStatus DO BEGIN END inByte Port inputData END PROCEDURE loopFor i INTEGER BEGIN WHILE i lt gt 0 DO i i114 END PROCEDURE doAnalyse BEGIN Port analyseT414 loopFor 10000 Port resetT414 loopFor 10000 Port resetT414 loopFor 10000 Port analyseT414 0 loopFor 5000 END 1 gt PROCEDURE doReset BEGIN Port analyseT414 0 loopFor 800 Port resetT414 1 loopFor 3000 Port resetT414 0 loopFor 1000 END C 2 Listing II Occam Buffer P
55. us resetT414 analyseT414 DMArequest INTenable useful writeDMA readDMA maxlength IBMtoB008 BOOStoIBM chanO chant chan3 DMAchannel MAstatus MAcommand MAffclear MAmastclr MAallmask addrchO wordchO addrch wordchi addrch3 wordch3 pagechO 1 D D 5 DMAsingmask D D D D I s H H H H H NTEGER NTEGER NTEGER NTEGER NTEGER NTEGER NTEGER NTEGER NTEGER lt 7 constants 0 1 3 maxlength length of string 1 INTEGER 0 08 08 09 0B 0C 0D 0F 00 01 02 03 06 07 87 IBM DMA controller registers 35 pagechi 83 pagech3 82 Interrupt constants PICbase 20 spurioustuff 7 DMAInt 1 Intchannel BYTE 3 intmask BYTE F7 intvec BYTE 2C eoi BYTE 63 flagint BOOLEAN FALSE int count INTEGER 0 intdata BYTE 0 TYPE text STRING maxlength VAR teststring default text datablock ARRAY 0 maxlength OF BYTE ABSOLUTE teststring i j x transfers counter blocklength INTEGER stringlength BYTE ABSOLUTE teststring switchpic ARRAY 1 9 1 35 OF CHAR PROCEDURE initConst Initialise typed constants BEGIN inputData boardbase outputData boardbase 1 inputStatus boardbase 2 outputStatus boardbase 3 resetT414 boardbase 10 analyseT414 boardba
56. ve the cover of the IBM PC 7 Choose the expansion slot into which the IMS 008 is to be inserted Do not use the slot nearest the edge in a PC AT because it does not 26 provide the full set of signals from the bus If the board is being used in a PC XT then the smaller set of edge connectors will hang in mid air Don t panic This does no harm 8 Remove the expansion slot cover from the chosen slot Retain the fixing screw 9 Carefully holding the board by its edges insert it into the chosen expansion slot 10 Secure the bracket on the IMS 8008 to the chassis of the PC using the fixing screw 11 Replace the cover on the PC 5 Testing 5 1 Powering up Switch the PC on If it fails to boot up then either the selected IMS B008 address or DMA channel clashes with another device present Check the settings described in appendix A 5 2 Running the test software Insert the Examples Test disc into drive a and select this drive by typing a lt Enter gt The test program can now be run by typing test Enter prompt will appear asking whether the default switch settings have been changed If not press Enter Otherwise type yes Enter and enter the board setup according to the prompts received diagram will then appear on the screen indicating how the switch settings should look Press 27 Pipe jumpers AS c 7 3 R 1 a Size 4 TRAM in
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