Home

Precision Synthesis Reference Manual

1. 00 6 9 Precision Synthesis Installation Guide 2003c Update 1 xiii March 2004 Table of Contents List of Tables cont XIV Precision Synthesis Installation Guide 2003c Update1 March 2004 Chapter 1 Introduction Invoking Precision Synthesis Invoking the Graphical User Interface You invoke the Precision RTL Synthesis GUI with the precision command You invoke the Precision Physical Synthesis GUI with the precision physical command Other optional command switches allow you to customize the invocation The precision command usage is fully documented in the section titled Commands starting on page 3 1 Invoking Precision Synthesis from a Shell You can invoke Precision RTL Synthesis in non GUI mode by using the command precision Shell You can invoke Precision Physical Synthesis in non GUI mode by using the command precision shell physical In this mode you can source Tcl scripts or you can interactively enter commands from the shell prompt The details about using the precision command are documented in the section titled Commands starting on page 3 1 Precision Synthesis Installation Guide 2003c Update 1 1 March 2004 The Tcl Command Interface Introduction The Tcl Command Interface The Precision Synthesis Graphical User Interface is based on the Tcl language Standard Tcl Commands provide a foundation for the command structure Precision Synthesis Tcl command extensions provide the major synthesis proces
2. Type Arguments list lt file_ list gt lt pathname_list gt lt file_type gt lt library_name gt string integer lt position_number gt Options format lt file_type gt Specifies the file type for file names that don t have the proper extension Valid values are vhdl verilog edif syn lib tcl xnf xdb sdf If this option is not used and a valid extension exists then the file type will be automatically detected work lt library_name gt Specifies the name of the work library for compiling the content of the file If not specified then the work library name work is assumed exclude You can use this switch when you wish to add one or more files to the input_file_list but exclude them from the compile phase Files marked with the exclude attribute are copied into the implementation directory after the synthesis phase is completed Also files of an unknown type are automatically marked as exclude and copied to the implementation directory This mechanism is handy for passing a file such as a place and route control file around the synthesis process and onto the physical implementation tools 3 16 Precision Synthesis Installation Guide 2003c Update March 2004 Commands add_input_file reset This switch clears the entire input_file_list before adding the specified input files s insert_before lt position_number gt Files in the input_file_list are numbered sequentially st
3. ccsccccccsscssnsssecsnssnsseeeees 9 17 Inferring READ_FIRST Mode One Clock Style 1 ceneeeeeees 9 18 Inferring READ_FIRST Mode One Clock Style 2 00 eeeeeeseeeeeeeeeees 9 19 Inferring READ_FIRST Mode Two CLOCKS cece ccecneneneeneeeeeeeeeeeeees 9 20 Inferring NO_CHANGE Mode One Clock Style 1 0 eeeeeceeeeeeeees 9 21 Inferring NO_CHANGE Mode One Clock Style 2 0 0 0 eeeeeeeceeeeeeeees 9 22 Interrme NO ANGE Mode Two OCG vcsciocietctetiedcrlaretetecnteicwetens 9 23 Tri Port RAM Sync Write Sync Read Sync Read One Clock 9 24 Tri Port RAM Sync Write Sync Read Sync Read Two Clocks 00 9 25 Tri Port RAM Sync Write Async Read Async Read Async Read 9 26 Tri Port RAM Sync Read Write Sync Read Sync Read ce eeeeeeeeeeeeeees 9 27 Tri Port RAM Sync Read Write WRITE_FIRST Mode cece 9 28 Tri Port RAM Port A Sync Read Write READ_FIRST Mode 9 29 Tri Port RAM Port A Sync Read Write NO_CHANGE Mode 0 0 9 30 Running the Xilinx ISE BnvitOninient ssciveriiscrivienercscieentiiee mines 9 31 Analyzing the Xilinx Place and Route Results 00 0 ccccnenseeereeseeeeeeeeeees 9 32 Setting Xilinx ISE Place and Route Options 2 0 eeeccececcceceeeeeeeeeeeeceeeeeneees 9 33 Setting Xilinx ISE Constraint File OptionS eeseseeseseeeessssssssseeseressssssseseeeees 9 35 Precision Synthesis Installation Guide 2003c Update1 March 2004 Table of Cont
4. reset_path gt This option removes existing point to point exception information on the specified paths Only information of the same rise fall or setup hold type is reset 3 174 Precision Synthesis Installation Guide 2003c Update1 March 2004 Commands set_false_path SDC design lt rtl gatelevel gt Tells the tool whether to look for the object in the RTL or the gatelevel view Description The set_false_path command adds a false path attribute to all specified paths By default Precision Synthesis analyzes all paths through a circuit except those paths that the application determines to be false The types of paths that are automatically eliminated as false are paths that cross between asynchronous clock domains paths that are disabled by a constant level definition This type of path can be a direct path a path that starts from the pin to which the constant level definition is attached or a side input path such as a data path through a multiplexer whose select pin has a constant level definition attached paths that go in both directions through a bidirectional pin For example a path that goes through a bidirectional pin in one direction then loops back around the pin in the opposite direction as occurs in transceivers connected to a data bus To avoid the unnecessary analyses and reporting of paths in which you are not interested you can eliminate any path from analysis by defining the path as
5. name lt clock name gt waveform lt edge_list gt domain lt domain_name gt design rtl gatelevel tring a Arguments Options period lt period_value gt The period of the clock in library time units lt port_pin_list gt 3 40 O O If set attaches the clock definition to the specified pins Any number of pins can be specified If no pins are specified then the clock is considered a virtual clock which can be used as a reference clock in Arrival or Setup constraints Each pin can be specified using one of the following methods top level port name hierarchical pathname to the pin name on a specific instance One or more pin names can be specified A pin name is specified as a string that must contain the hierarchical path and netlist name of the pin The use of asterisk and question mark characters is supported Asterisks within pathnames are evaluated as wildcards within a single hierarchy level Precision Synthesis Installation Guide 2003c Update1 March 2004 Commands create_clock SDC o One or more pin objects can be specified Each pin object is specified using a sdc_find pin command or a loop variable created by a Tcl foreach command operating on a pin sequence object that was created by a get_pins command domain Sets the clock domain name The clock domain name is specified as a string By default all clocks without a specified domain name are assign
6. lt fan out value gt Specifies the maximum capacitance that the specified net or port can drive lt port_net gt Specifies the driving port or net This value must be a hierarchical pathname Description The set_fanout_load command defines the maximum capacitance that the driving port or net can have This value overrides the library default value set by the vendor This command may be used to prevent buffering or logic replication on non timing critical nets This command is often used to decrease the maximum fanout on a net in a critical path This command sets the fanout_load attribute on the object This command is only valued for actel and quicklogic technologies For technologies like Altera and Xilinx you must use set_max_fanout which limits the number of driven pins because the FPGA libraries specify pin capacitance You can use the report_net command to view the capacitance and fanout loading information of a specific net s Related Commands 3 178 Precision Synthesis Installation Guide 2003c Update1 March 2004 Commands set_hierarchy_separator set_hierarchy_separator Set the separator character for hierarchy pathnames to the specified symbol Example set_hierarchy_separator Syntax set_hierarchy_separator Arguments 5 1 Specify one of these symbols as the hierarchy pathname separator Description This command is used to set the symbol for sepa
7. pin Matches pins port Matches ports net Matches nets matchcase Match names with the exact case wholeword Match whole words only regexp Allow TCL regular expressions to be in the search string Precision Synthesis Installation Guide 2003c Update 3 55 March 2004 find Commands Description The find command is a Tcl scripting command allows you to search through the in memory database for all the matching objects The return type is a TCL list You can use this list in other commands like foreach This find command itself can be used as an argument to another command forcing that command to apply not to a single item but to the entire set of object that are identified by the database search Related Commands find_ clocks find_outputs find_inputs 3 56 Precision Synthesis Installation Guide 2003c Update March 2004 Commands find_clocks find clocks Return hierarchical pathnames for all clocks in the design Example The following example sets all clocks in the design to 20 ns This may be useful to quickly get a design that has several internal clocks before you have time to analyze them create_clock name sys_clk period 15 0 find_clocks top create clock name int_clk period 30 0 find_clocks internal The following example prints the fanout on each clock in the design foreach clk find clocks Outs clk Sebk Panoul fexoriLllengthm last conn port clk 1 J Syn
8. iat eH He HE 0 _max_delay _max_delay _max_delay _max_delay _max_delay _max_delay 1 10 10 10 10 10 00 00 00 00 00 00 itt Ht Ht Ht HH HT from from from from from from set_max_delay 10 00 from reg_framingerr U0 CLK to framingerr reg_tx U0 CLK to tx reg_overrun U0 CLK to overrun reg_txdatardy U0 CLK to txrdy reg_parityerr U0 CLK to parityerr reg_rxdatardy U0 CLK to rxrdy rx to i2f8ex3 U0 D reg_rxstop U0 D reg_hunt U0 D Selecting Military Operating Conditions Precision RTL Synthesis and Actel s Designer software let you specify operating conditions for static timing analysis Synthesis libraries contain an appropriate process derating for military operating conditions and physical libraries allow for more detailed specification of voltage and temperature range With Precision Synthesis military operating conditions can be selected by issuing the command setup_design cim mil as part of the project setup Actel supports three temperature range options commercial industrial and military For example enter the following to set the military temperature range option setup_design cim military Supported Actel Devices All Actel technologies including the new Axcelerator family of devices are supported Precision Synthesis Installation Guide 2003c Update 6 11 March 2004 Supported Act
9. lt U output U OUEL 0 reg 0 mem 0 31 A 32 x 8 bit memory array reg 10 Cel out2 0U always posedge wclk begin if wen mem addr1l lt datain outi lt mem addrl out2 lt mem addr2 out3 lt mem addr3 end endmodule Port A Synchronously Written and Read in NO_CHANGE Mode The NO_CHANGE write mode for port A refers to the write mode in which the RAM output on port A is unchanged when port A is synchronously written Precision Synthesis Installation Guide 2003c Update 9 29 March 2004 Handling Xilinx Design Issues Designing with Xilinx For Virtex Precision infers a set of dual port distributed rams for ports A and B and another set of dual port distributed rams for ports A and C For Virtex II Precision by default infers a set of dual port block rams for ports A and B and another set of dual port block rams for ports A and C when both port B and port C are read synchronously with the same clock Precision sets the property WRITE_MODE_A to NO_CHANGE on these dual port block rams the clock associated with port B and C can be the same as or different from the clock associated with port A synchronous reading of port B or C can also be described by explicitly clocking the read address When the block_ram attribute is set to false on the RAM distributed RAM s are inferred instead Port A Synchronously Written and Read in NO_CHANGE Mode In code Figure 9 27 infers a tri port RAM with
10. set_hierarchy_separator Set the separator character for hierarchy pathnames to the specified symbol set_impl_property Set the name or comment value of an implementation set_input_delay SDC Set input delay on pins or input ports relative to a clock signal Set the relative path names when adding input files Set the attributes on the specified input file set_max_delay SDC Set the maximum total path delay for a timing path that is constrained by a clock set_max_fanout SDC Limit the maximum number of pins that a net or port can drive set_min_delay SDC Set the minimum total path delay for a timing path that is constrained by a clock set_multicycle_path SDC Modify the single cycle timing relationship of a constrained path set_output_delay SDC Set output delay on output ports or pins relative to a clock set_preference Set a Precision preference indicating whether new projects will be saved to a temp directory set_project_property Set a Precision property indicating whether the current project will use a temp directory for its active implementation the next time the project is opened set_propagated_clock SDC Specifies the cell delays in the clock network should be used set_results_dir Set explicitly where output files will be written when not using projects set_working_dir Deprecated Set the working directory to the specified pathname Use the following commands instead cd set_input_dir set_r
11. Interactive Command Line Shell set_attribute net net_internal name max fanout value 10 nobuff Prevents the specified signal from being buffered Verilog pragma attribute net_internal nobuff true VHDL attribute nobuff boolean attribute nobuff of net_internal signal is true Interactive Command Line Shell set_attribute net net_internal name nobuff type boolean value true Precision Synthesis Installation Guide 2003c Update 2 17 March 2004 Pre Defined User Attributes Attributes nopad Prevents the placement of an I O pad on the specified port when the design is mapped to the technology Verilog pragma attribute lt port_name gt nopad true VHDL attribute nopad boolean attribute nopad of lt port_name gt signal is true Interactive Command Line Shell set_attribute port lt port_name gt name nopad value true outff Tells Precision Synthesis whether or not to map the candidate register in the output path to a register in the IOB By default Precision maps the register to the IOB 1f this attribute is not present The attribute is applied to the output port Verilog pragma attribute data_out 1 outff false VHDL attribute outff boolean attribute outff of data_out 1 signal is false Interactive Command Line Shell set_attribute port data_out 1 name outff value false You can also set this attribute by right clicking on an input port in the Design Hierarchy pane of
12. You can also set this attribute by right clicking on an instance in the Design Hierarchy pane of the GUI and selecting Preserve or Flatten inff Tells Precision Synthesis whether or not to map the first register in the input path to a register in the IOB By default Precision maps the first register to the IOB 1f this attribute is not present The attribute is applied to the input port Verilog pragma attribute data_in 1 inff false VHDL attribute inff boolean attribute inff of data_in 1 signal is false Interactive Command Line Shell set_attribute port data_in 1 name inff value false You can also set this attribute by right clicking on an input port in the Design Hierarchy pane of the GUI and selecting Force Input flop onto Input Pad gt FALSE input delay Obsolete This attribute is no longer supported An input delay is now specified as a timing constraint For conceptual and procedural information about setting an input delay constraint refer to Specifying Input Delay in the Precision RTL Synthesis User s Manual See also set_input_delay SDC in Chapter 3 Commands Precision Synthesis Installation Guide 2003c Update 2 15 March 2004 Pre Defined User Attributes Attributes lob Specifies that the placement of the register is to be forced into the IO block This may increase the IO frequency at the possible expense of the internal chip frequency For bi directional ports you can individually c
13. 2 If running on Windows Linux or Solaris executes the following command SXILINX bin lt os gt ngc2edif bd lt bus_format gt lt ngc_file gt lt ndf_file gt o lt os gt 1s the operating system sub path lt bus_format gt lt ngc_file gt lt ndf_file gt O lt bus_format gt 1s either paren default or angle Xilinx PCI core flow when ngo file is in the input file list Precision Synthesis Installation Guide 2003c Update 9 5 March 2004 Handling Xilinx Design Issues Designing with Xilinx O lt ngc_file gt is the filename without the ngc extension of the ngc file in the implementation directory O lt ndf_file gt is the filename with the nd extension of the EDIF file in the implementation directory 3 Reads the EDIF netlist from the resulting nd file 4 Places a dont_touch attribute on the block This step is omitted if dont_touch properties are inherited from parent to child 5 Places an attribute on each block such that its contents do not get written out to the final synthesized top level EDIF netlist Remember the LUTs in these subblocks are missing their INIT properties Precision will re expand them from the ngc file during place and route As before a dont_touch attribute is placed on the top level edn design Post compiled GUI View The following figure shows a sample of how the Design Center window might appear after compiling a design using hierarchical coregens Figur
14. CE gt get_pins hier CE txX Leq a lt CE txreg b CE ExX axIZ23 CE Concrol CE rPx red a CE x reg DCE The following two examples returns all CE pins on instances starting with reg that are in the tx instance at the top of the design The second example uses the current_instance command to change the starting point in hierarchy of the search Notice that the wildcard only applies to the one level of hierarchy the wildcard is terminated by the hierarchical separator gt get_pins tx reg CE tx reg_a CEHK tx reg_b CkE gt current instance tx gt get_pins reg CE tx reg_a CE tx reg_b CE Syntax get_pins hierarchical hsc lt separater gt lt patterns gt lt pallerns gt lt separator gt Options hierarchical search entire hierarchy level by level for lt patterns gt This argument is only valid if the pattern only contains a pin name instance names or hierarchical separators hsc lt string gt Defines the hierarchical separator that is used in instance pathname of the specified pattern You can use any of the following separators The default separator is Description The get_pins command searches for the specified pattern in the design relative to the current_instance and returns a list of instance pin pathnames This command returns the absolute instance path with the pin name with respect to the top of the design hierarchy 3 76 Precision Synthesis Installation Gu
15. family Returns the family name setting for the current technology part Returns the part name setting for the current technology speed Returns the speed grade setting for the current technology package Returns the package name setting for the current technology cim Return the process setting either Commercial Industrial or Military btw Return the process conditions setting either Best case Typical case or Worst case addio Return the setting for whether or not to add IO pads to the design ports vhdl Return the setting for whether or not to write out a VHDL netlist verilog Return the setting for whether or not to write out a Verilog netlist edif Return the setting for whether or not to generate an EDIF netlist file vhdl_filename Return the pathname for the VHDL output file verilog_filename Return the pathname for the Verilog output file edif_filename Return the pathname for the EDIF output file constraint_filename Return the pathname for the generated SDC output file yvendor_constraint_file Return the setting for whether or not to generate a vendor constraint file 3 150 Precision Synthesis Installation Guide 2003c Update March 2004 Commands report_project design Returns the setup_design design Setting for the entity name or module name that represents the top of the design architecture Returns the setting for he name of the root architec
16. 2 6 2 20 preserve_z 2 3 2 20 Propagating clocks 4 10 Propagation 4 7 Quartus II running from Precision 6 1 R radhard 2 22 RadHard Designs 6 6 Index 3 Index Index cont radhardmethod Actel 2 3 2 4 2 21 RAMs 4 5 Register Retiming 4 12 remove remove_clock 3 116 3 117 remove_attribute 3 114 remove_clock 3 116 remove_clock_latancy 3 117 remove_clock_transition 3 118 remove_clock_uncertainty 3 119 remove_design 3 120 remove_input_delay 3 122 remove_input_file 3 124 remove_output_delay 3 125 remove_propagated_clock 3 127 report report_area 3 129 report_constraints 3 135 report_delay 3 154 report_rename_rules 3 146 report_analysis 3 128 report_area 3 129 report_attributes 3 131 report_connections 3 133 report_constraints 3 135 report_design_impl_list 3 137 report_input_file_list 3 138 report_io_registers 3 139 report_library 3 140 report_license 3 142 report_memory_utilization 3 143 report_missing_constraints 3 144 report_net 3 146 report_output_file_list 3 148 report_project 3 149 report_technologies 3 153 report_timing 3 154 Resource sharing 4 7 Retiming 4 13 4 14 Retiming Algorithm 4 15 Precision Synthesis Installation Guide 2003c Update March 2004 Retiming Rules 4 17 Run Script 1 3 S safe_fsm 2 3 2 22 save_impl 3 159 save_path_definition_sets 3 160 save_physical 3 161 save_project 3 162 Script Running from the GUI 1 3 select
17. 2003c Update 3 191 March 2004 set_min_delay SDC Commands set_min_delay SDC Set the minimum total path delay for a timing path that is constrained by a clock Example s t min delay 11 0 from input_A input_B Syntax set_min_delay lt delay_value gt from lt from_list gt through lt through_list gt to lt to_list gt rise fall reset_path design rtl gatelevel float lt delay_value gt list lt trom_aist gt xto li st gt lt through list gt Arguments lt delay_value gt Specifies the minimum path delay of the timing path s in which the specified port s or pin s or cell s reside You must specify the lt delay_value gt in units consistent with the technology library used during optimization If a path start point is on a sequential device clock skew is included in the computed delay If a path start point has an input delay specified that delay value is included in the total path delay If a path endpoint is on a sequential device clock skew and library setup time are included in the computed delay If the endpoint has an output delay specified that delay is included in the total path delay Options from lt from_list gt A list of names of ports internal pins or cell names in the current design to use to find path start points If you specify a cell name one path start point on that cell is affected All paths from these start points to the endpoints in the to_list
18. 3 You can set attributes using a Precision Synthesis SDC constraint file Specifying Attributes in VHDL The following syntax can be used for the declaration of a VHDL attribute attribute lt attribute_name gt lt attribute_type gt The following syntax describes how to set an attribute on a VHDL component attribute lt attribute_name gt of lt object_name gt component is lt attribute value gt 2 6 Precision Synthesis Installation Guide 2003c Updatet March 2004 Attributes How to Set Attributes Note Set on component which is corresponding to view attribute lt attribute_name gt of lt object_name gt label is lt attribute_value gt Note Set on a label which is corresponding to an instance VHDL Example entity example is port inp clk an std_logic outp out std_logic inoutp inout std_logic attribute buffer_sig string attribute buffer_sig of clk signal is CLOCK BUFFER end example All Precision attributes are defined in the mgc_attributes package file at MGC_HOME pkgs techdata vhdl mgc_attr vhd You can either use this file as examples for defining attributes in your design or reference this file in your VHDL code Precision automatically reads this file during compile USE work mgc_attributes all Specifying Attributes in Verilog Use the following directive for Verilog attributes pragma attribute lt object_name gt lt attribute_name gt lt attribute_value gt
19. 3 downto 0 Signal mem mem_type begin PROCESS CLK BEGIN IF CLK EVENT AND CLK 1 THEN IF WEA 1 THEN DOA lt DIA mem conv_integer ADDRA lt DIA ELSE DOA lt mem conv_integer ADDRA END IF DOB lt mem conv_integer ADDRB END IF END PROCESS end rtl Figure 9 12 shows another recommended VHDL coding style for inferring the WRITE_FIRST mode In this example the write and read address ADDRA associated with Port A is 9 14 Precision Synthesis Installation Guide 2003c Update1 March 2004 Designing with Xilinx Handling Xilinx Design Issues explicitly registered while the read operation is done with the concurrent assignment statement following the process Both ports are driven by the same clock Figure 9 12 Inferring WRITE_FIRST Mode One Clock Style 2 Library LEEES use IEEFEF std_logic_1164 all use IEEEF std_logic_unsigned all entity V2RAM is port DOA 7 out Std rogi vector 3 downto 0 gt DEA 2 im Std Logie yveecror 3 GONnEO ON DOB out std_logic_vector 3 downto 0 ADDRA t in 6rd logue vector 12 downto 073 ADDRB IA sta logue vector 1 2 downto 0 WEA Ti Sta LOG 16 CLK 4 In Std Log ies end V2RAM architecture rtl of V2RAM is type mem_type is array 8191 downto 0 of STD_LOGIC_VECTOR 3 downto 0 Signal mem mem_type Signal ADDRA_INT std_logic_vector 12 downto 0 begin Signal assignments Component instances PROCESS CLK BEG
20. Automated Physical Synthesis Flow sections in Chapter 2 of the Precision Physical Synthesis Users Manual Precision Synthesis Installation Guide 2003c Update 1 3 21 March 2004 add_placement_file Commands The tool may display the following messages pdb Tile is missing Lloorplan_ only 1s false Error Could not find file lt pdb file name gt Placement file lt macro file name gt has not been added tdo file is missing Error Could not find file lt fdb file name gt Related Commands add_macro_file 3 22 Precision Synthesis Installation Guide 2003c Updatet March 2004 Commands alias alias Define an alternative command for a set of command s Example alias rmc report_missing_constraints This command defines an alias named rmc for the command report_missing_constraints If you are interactively entering this command frequently in the command line this alias will eliminate a lot of typing Syntax alias lt alias_name gt lt script_expansion gt lt script_expansion gt Arguments lt alias name gt Name of an alias to define or to display If you omit this argument the alias command lists all defined aliases This is a string type of argument lt script_expansion gt Tcl script sequence of commands that is executed in place of the alias If spaces occur in script put braces around it as in any Tcl script If you specify alias_name and omit script the existing defin
21. CLK i std logic end V2RAM architecture rtl of V2RAM is pignal declarations type mem_type is array 8191 downto 0 of STD_LOGIC_VECTOR 3 downto 0 signal mem mem_type begin PROCESS CLK BEGIN IF CLK EVENT AND CLK 1 THEN IF WEA 1 THEN mem conv_integer ADDRA lt DIA ELSE DOA lt mem conv_integer ADDRA END IF DOB lt mem conv_integer ADDRB END IF END PROCESS end rtl Precision Synthesis Installation Guide 2003c Update1 9 21 March 2004 Handling Xilinx Design Issues Designing with Xilinx Figure 9 19 shows a style of RAM where the B read address is explicitly registered and the read operation is achieved with the concurrent signal assignment statement that follows the process Both ports are driven by the same clock Figure 9 19 Inferring NO CHANGE Mode One Clock Style 2 library IEEE use IEEF std_logic_1164 all use IEEEF std_logic_unsigned all entity V2RAM is port DOA out std_logic_vector 3 downto 0 DIA in std_logic_vector 3 downto 0 DOB out std_logic_vector 3 downto 0 ADDRA in std_logic_vector 12 downto 0 ADDRB in std_logic_vector 12 downto 0 WEA in std logic CLK i std logic end V2RAM architecture rtl of V2RAM is type mem_type is array 8191 downto 0 of STD_LOGIC_VECTOR 3 downto 0 signal mem mem_type Signal ADDRB_INT std_logic_vector 12 downto 0 begin PROCESS CLK BEGIN IF CLK EVENT AND CLK 1 THEN IF WEA
22. Description The get_false_paths command returns a list of previously defined false paths This command is useful to generate a temporary constraint SDC file for what if scenarios during static timing analysis Related Commands get_cells SDC get_lib_cells SDC get_clocks SDC get_lib_pins SDC get_designs get_multicycle_paths get_lib_cells SDC get_nets SDC get_lib_cells SDC get_path_definition_set get_ports SDC Precision Synthesis Installation Guide 2003c Update 3 65 March 2004 get_impl_ property Commands get_impl_ property Return the name or comment value of an implementation Example get_impl_ property name Returns the value of the name property of the active implementation Syntax get_impl_ property impl lt impl_name gt name comment ting Arguments name comment Returns either the name or the comment string of the target implementation Options impl lt impl_name gt Specifies the name of an inactive implementation in the current project If impl is not used the active implementation is queried Description The get_impl_property command is a project manager command available only when a project is loaded It returns the value of either the name property or the comment property of the active implementation Use the impl option to query a non active implementation Related Commands activate_impl new_impl copy_impl save_impl delete_impl set_impl_property ge
23. Eldo EldoNet ePartners EPartsi EPlanner EProduct Designer EProduct Services Empowering Solutions Engineer s Desktop EngineerView Enterprise Librarian ENRead EN Write EsSim Exemplar ExemplarLogic Expedition Explorer CAECO Layout Explorer CheckMate Explorer Datapath Explorer Lsim Explorer Lsim C Explorer Lsim S Explorer Ltime Explorer Schematic Explorer VHDLsim Expressl O EZwave FabLink Falcon Falcon Framework PastScan FastStart FIRE First Pass Design Success First Pass Success FlexSim PlexTest FOL Plow Definition Language FlowTabs FlowX pert FORMA FormalF mo FPGA Advantage FPG Advisor FPGA BoardLink FPGA Builder FPPGASim FPGA Station FPGA Xchange FrameConnect Fusion Galileo GateStation GateGraph GatePlace GateRoute Gemini GDT GDT Core GDT Designer GDT Developer GENIE Gen Ware Geom Genie HOL2Graphics HDL Architect HDL Architect Station HDL Assistant HDL Author HDL Designer HOL Designer Series HDL Detective HDL Inventor HDL Link HDL Pilot HDL Processor HDOLSim HDLWrite Hierarchial Injection Hierarchy Injection HIC rules Hardware Modeling Library HotPlot Hybrid Designer Hybrid Station HyperLinx HyperSuite IC Design Station IC Designer IC Layout Station IC Station Streamview ICbasic Cblocks Ccheck Ccompact ICdevice Cextract CGen Ceraph CLink IClister ICplan IERT Controller Leompiler Crules Ctrace C verify Cview ICX 1ICX
24. FITNESS FOR A PARTICULAR PURPOSE MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL INDIRECT SPECIAL OR CONSEQUENTIAL DAMAGES WHATSOEVER INCLUDING BUT NOT LIMITED TO LOST PROFITS ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED INIT EVEN IF MENTOR GRAPHICS CORPORATION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES RESTRICTED RIGHTS LEGEND 03 97 U S Government Restricted Rights The SOFTWARE and documentation have been developed entirely at private expense and are commercial computer software provided with restricted rights Use duplication or disclosure by the U S Government or a U S Government subcontractor is subject to the restrictions set forth in the license agreement provided with the software pursuant to DFARS 227 7202 3 a or as set forth in subparagraph c 1 and 2 of the Commercial Computer Software Restricted Rights clause at FAR 52 227 19 as applicable Contractor manufacturer is Mentor Graphics Corporation 8005 S W Boeckman Road Wilsonville Oregon 97070 7777 This is an unpublished work of Mentor Graphics Corporation Table of Contents Table of Contents Chapter 1 Introduction Done eg pec Oy dsl es Ria LINN Sc Meee nneee een Ment ee ne E l 1 Invoking the Graphical User Interface nneeseeeseeennsssssesereesrssssssseersresssssssereressssssseeeesesses l 1 hoyokmne Precision Sess TOM a Smell essien l 1 The a A seiniin ienaa EEEE EEEO EE RE 1 2 E Ee N a
25. Handling Xilinx Design Issues Designing with Xilinx Figure 9 15 shows a recommended style for inferring the READ_FIRST mode Both ports are driven by the same clock During the same cycle process the old content of the addressed cell is assigned to the output latches of Port A while the new data is written to the addressed cell Figure 9 15 Inferring READ_FIRST Mode One Clock Style 1 library IEEE use IEEE std_logic_1164 all use IEEE std_logic_unsigned all entity V2RAM is port DOA out std_logic_vector 3 downto 0 DIA in std_logic_vector 3 downto 0 DOB out std_logic_vector 3 downto 0 ADDRA in std_logic_vector 12 downto 0 ADDRB in std_logic_vector 12 downto 0 WEA in std logic CLK i std logic 7 end V2RAM architecture rtl of V2RAM is Component declarations Signal declarations type mem_type is array 8191 downto 0 of STD_LOGIC_VECTOR 3 downto 0 Signal mem mem_type begin PROCESS CLK BEGIN IF CLK EVENT AND CLK 1 THEN IF WEA 1 THEN mem conv_integer ADDRA lt DIA END IF DOA lt mem conv_integer ADDRA DOB lt mem conv_integer ADDRB END IF END PROCESS end rtl 9 18 Precision Synthesis Installation Guide 2003c Update1 March 2004 Designing with Xilinx Handling Xilinx Design Issues The code is Figure 9 16 shows a style of RAM where the B read address is explicitly registered and the read operation is achieved with the concurrent sig
26. If more than one object is specified the objects must be enclosed in quotes or in braces clock lt clock_name gt This required switch specifies the reference clock may be a virtual clock to which the specified delay is related The delay is relative to the rising edge of the clock unless the clock_fall option is specified If clock is not specified the delay is relative to time zero for combinational designs For sequential designs the delay 1s considered relative to a new 3 200 Precision Synthesis Installation Guide 2003c Update March 2004 Commands set_output_delay SDC clock with the period determined by considering the sequential cells in the transitive fanout of each port Options clock_fall Specifies that the delay is relative to the falling edge of the clock named by clock The default is the rising edge rise Specifies that lt delay_value gt refers to a rising transition on specified ports in the current design If neither rise nor fa11 is specified rising and falling delays are assumed to be equal fall Specifies that lt delay_value gt refers to a falling transition on specified ports in the current design If neither rise nor fa11 is specified rising and falling delays are assumed to be equal offset Modifies the clock edge separation for slack violations in cases where the destination clock is different than the source clock This value on constrains paths from to registe
27. MACH4A M4A3 682 32 64 32 64 64 96 48 128 64 192 96 256 128 256 160 256 192 384 160 512 160 512 192 512 256 MACH4A M4A5 2 32 64 32 64 64 96 48 128 64 192 96 256 128 256 160 256 192 384 160 512 160 512 192 512 256 Packages 4PLcc 44T QFP 48TQFP 100TQFP 144TQFP 208PQFP MACHS M5 384 184 384 192 512 120 512 160 512 184 512 192 512 192 Precision Synthesis Installation Guide 2003c Update 1 13 March 2004 Lattice CPLD Devices Supported Designing with Lattice Devices MACHS5 M5LV 384 184 384 192 512 120 512 160 512 184 512 192 512 256 Low Voltage MACHSA MSA 384 120 384 160 384 192 512 120 512 160 512 192 512 256 Packages JLOOPQFP 144PQFP 160PQFP 208PSEP 240PQFP 256BGA 352BGA NOTE The devices for MACH 1 and MACH 2 are currently not listed pLSI 1000 Devices pLSI 1000 Devices ispLSI1016 60LH44 883 60LJ44 60LI441 80LJ44 90LJ44 60LT44 60LT44I1 SOLT44 90LT44 ispLSI1O16E 80LJ44 8OLJ441 100LJ44 125LJ44 830LT44 80LT44I1 100LT44 125LT44 ispLSI1024 60LH68 883 60LJ68 60LJ68I 80LJ68 9OLJ68 6OLT100 6OLT100I lt lt 9OLT 100 ispLSI1032 60G84 883 ispLSI1032E OLJ84 70LJ84I 100LJ84 125LJ84 70LT100 7OLT1001 1OOLT100 125LT100 ispLSI1048C OLG133 883 ispLSI1048E OLT128 70LT128 90LT128 100LY 128 125LT128 50LQ128 0LQ128I 70LQ128 70LQ12I 90LQ128 100LQ128 125LQ128 pLSI 2000 Devices pLSI 2000 Devices ispLSI2064VE 100LJ44 135LJ44 180LJ44 100LT44 135
28. March 2004 Commands all_ outputs SDC all_ outputs SDC Return a list of all output ports in the current design The search can be limited to input ports that have constraints relative to a given clock Example all outputs Work tCOp data path clock cIkA clk B short Syntax all_outputs lt design gt clock lt clock_name s gt short list lt clock_name s gt Arguments lt design gt Name of the design Options clock lt clock_name s gt Print only outputs that are related to the specified clock s short Print only short names not the full path to objects Description The all_outputs command is a reporting command that returns a list of all output ports of the top level of the design as determined by the current_design command The value of current_instance does not affect the result of this command This command 1s typically used with the set_ commands to specify timing constraints on ports similar to wildcards You can limit the top level outputs included in the list by using the clock option This switch examines the timing paths from all outputs at the top level of the design to sequential elements that are clocked by the clock names specified in the clock switch Precision Synthesis Installation Guide 2003c Update 3 29 March 2004 all_ outputs SDC Commands If a timing path exists from the sequential element to the output port Precision Synthesis includes the
29. Mentor Graphics grants to you a nontransferable nonexclusive license to reproduce and distribute executable files created using ESD compilers including the ESD run time libraries distributed with ESD C and C compiler Software that are linked into a composite program as an integral part of your compiled computer program provided that you distribute these files only in conjunction with your compiled computer program Mentor Graphics does NOT grant you any right to duplicate or incorporate copies of Mentor Graphics real time operating systems or other ESD Software except those explicitly granted in this section into your products without first signing a separate agreement with Mentor Graphics for such purpose 3 BETA CODE Portions or all of certain Software may contain code for experimental testing and evaluation Beta Code which may not be used without Mentor Graphics explicit authorization Upon Mentor Graphics authorization Mentor Graphics grants to you a temporary nontransferable nonexclusive license for experimental use to test and evaluate the Beta Code without charge for a limited period of time specified by Mentor Graphics This grant and your use of the Beta Code shall not be construed as marketing or offering to sell a license to the Beta Code which Mentor Graphics may choose not to release commercially in any form If Mentor Graphics authorizes you to use the Beta Code you agree to evaluate and test the Beta Code under no
30. Options ports List all the ports of lt list_of_designs gt This argument is valid only if lt list_of_designs gt is one or more views nets List all the nets of lt list_of_designs gt This argument is valid only if lt list_of_designs gt is one or more views 3 88 Precision Synthesis Installation Guide 2003c Update March 2004 Commands list_design clocks List all the primary clocks of lt list_of_designs gt This argument is valid only if lt list_of_designs gt is one or more views internal clocks List all the internal clocks of lt list_of_designs gt This argument is valid only if lt list_of_designs gt is one or more views instances default List all the instances in lt list_of_designs gt This argument is valid only if lt list_of_designs gt iS one or more views If lt list_of_designs gt indicates a view and you omit other arguments the 1ist_design command uses the instances argument references List all the instances pointing to lt list_of_designs gt This argument is valid only if lt list_of_designs gt is one or more views direction Valid only with ports option The direction option takes the port direction IN OUT or INOUT and prints only the ports of given direction If this option is not provided with port all the ports will be printed hdl List the design units stored in HDL libraries If you omit this argument this command lists object
31. Precision maps the first register to the IOB if this attribute is not present The attribute is applied to the input port This attribute is no longer supported An input delay is now specified as a timing constraint Specifies that the placement of the register is to be forced into the IO block This may increase the IO frequency at the possible expense of the internal chip frequency For bi directional ports you can individually control the movement of flops using the inff outff and triff attributes Allows you to change the fanout limit on the specified net Prevents the specified signal from being buffered Prevents the placement of an I O pad on the specified port when the design is mapped to the technology Tells Precision Synthesis whether or not to map the candidate register in the output path to a register in the IOB By default Precision maps the register to the IOB if this attribute is not present The attribute is applied to the output port Precision Synthesis Installation Guide 2003c Update March 2004 Attributes Alphabetical List of User Attributes Table 2 1 Alphabetical Attribute Summary continued This attribute is no longer supported An output delay is output_delay Obsolete now specified as a timing constraint Specifies which technology specific I O cell to used for a specific port Assigns a specific device pin number to a specific port in the design pin_number Prese
32. Specifies as string which is the format of the back annotation file that will be generated by the implementation tools Possible options are Verilog EDIF or VHDL The default is VHDL Altera Quartus II Command Names cl default Run the vendor place and route flow in the background command line mode Use the options specified in the setup_place_and_route command Send a transcript of the executed commands to the Transcript window gen_vcf Write a Vendor Constraint File to the active implementation directory Altera Quartus II Command Arguments The arguments you specify here are the same options that may have been already set with the setup_place_and_route command They may be specified here to change a setup option on the fly when you execute the place_and_route command install_dir lt vendor_implementation_directory_pathname gt Specifies the pathname to the Quartus II installation tree 3 104 Precision Synthesis Installation Guide 2003c Update March 2004 Commands place_and_route no exec This option is primarily used to debug the Precision place_and_route script that drives the implementation tools The commands in the script are echoed to the Precision Transcript window without the commands actually being executed by the implementation tools ba_format lt format gt Specifies as string which is the format of the back annotation file that will be generated by the imple
33. get_project_impls Commands get_project_impls Return a list of implementations in the current project Syntax get_project_impls Description The get_project_impls command is a project manager command available only when a project is loaded It returns a list of all implementations in the current project Related Commands activate_impl get_project_name copy_impl new_impl delete_impl save_impl get_impl_property set_impl_property 3 80 Precision Synthesis Installation Guide 2003c Update March 2004 Commands get_project_name get_project_name Return the name of the current project Syntax get_project_name Description The get_project_name command is a project manager command available only when a project is loaded It returns the name of the currently loaded project Related Commands activate_impl get_project_impls copy_impl new_impl delete_impl save_impl get_impl_property set_impl_property Precision Synthesis Installation Guide 2003c Update 3 81 March 2004 get_results_dir Commands get_results dir Return the path of the current results directory Syntax get_results_dir Description The get_results_dir command returns the pathname of the current results directory This command is only available after the results directory has been set A results directory is set either by the calling set_results_dir command or by activating an implementation when a project is open When an implementation is activa
34. lt active_implementation_comment gt lt freq_mhz gt lt input_delay_value gt lt output_delay_value gt lt operatorname limit gt lt method gt Precision Synthesis Installation Guide 2003c Update 3 211 March 2004 setup design Commands list lt search_pathnames gt Arguments lt library_name gt The library name is the internal name for the technology library that is found in the devices ini file This file is located at the following pathname lt precision install directory gt pkgs psr techlibs devices ini This argument is normally specified when the user selects the technology from the GUI Options addio Add IO buffers to this design The default is t rue If you are synthesizing an internal block for example and wish to set this switch to false then you should use the following syntax addio false advanced_fsm_optimization Enables the advanced FSM optimization algorithms The default 1s true You may want to turn this off 1f you have custom coded your statemachine s If you wish to set this switch to false then you should use the following syntax advanced_fsm_optimization false architecture lt root_arch_name gt Specifies the name of the root architecture VHDL only for the design top 1f more than one architecture is possible If not specified the last architecture compiled for the top entity is used basename lt output_file_leafname gt Specifies the leaf name of the gener
35. report_input_file_list setup_design remove_input_file remove_design set_input_dir add_input_file Precision Synthesis Installation Guide 2003c Update 3 187 March 2004 set_max_delay SDC Commands set_max_delay SDC Set the maximum total path delay for a timing path that is constrained by a clock Example s t max delay 11 0 from input_A input_B Syntax set_max_delay lt delay_value gt from lt from_list gt through lt through_list gt to lt to_list gt rise fall reset_path design rtl gatelevel float lt delay_value gt list lt trom_aist gt xto li st gt lt through list gt Arguments lt delay_value gt Specifies the total path delay of the timing path s in which the specified port s or pin s or cell s reside You must specify the lt delay_value gt in units consistent with the technology library used during optimization If a path start point is on a sequential device clock skew is included in the computed delay If a path start point has an input delay specified that delay value is included in the total path delay If a path endpoint is on a sequential device clock skew and library setup time are included in the computed delay If the endpoint has an output delay specified that delay is included in the path total delay Options from lt from_list gt A list of names of ports internal pins or cell names in the current design to use to find path start points
36. tools Possible options are Verilog or VHDL layout_mode std tmgdrv A string specifying the layout mode std Standard or tmgdrv Timing Driven The default is std Standard layout maximizes the average performance for all paths Standard layout treats each part of the design equally for performance optimization Standard layout uses net weighting or criticality to influence the results The primary goal of Timing Driven layout is to meet delay constraints set in Timer an SDC file Axcelerator family only a DCF file non Axcelerator families or a GCF file for Pro ASIC and Pro ASICPLUS devices Timing Driven layout s secondary goal is to produce high performance for the rest of the design Delay constraint driven design is more precise and typically results in higher performance Note Timing Driven Layout is only available after you have entered timing constraints layout_runtime lt boolean gt The default is 0 If you specify layout_runtime 1 then the extended runtime attempts to improve the layout quality by using a greater number of iterations during optimization An extended run layout can take up to 5 times as long as a normal layout Note This advanced option is available for all ONO Families Precision Synthesis Installation Guide 2003c Update 3 219 March 2004 setup _place_and_route Commands effort_level lt string gt This variable specifies the duration of the timing driven phase of optimizati
37. 0 DIA in std_logic_vector 3 downto 0 DOB out std_logic_vector 3 downto 0 ADDRA in std logic vector 12 downto 0 ADDRB in std logic vector 12 downto 0 WEA 7 an std logic CLKA 4 in std logic CLKB in std logic end V2RAM architecture rtl of V2RAM is Signal declarations type mem_type is array 8191 downto 0 of STD_LOGIC_VECTOR 3 downto 0 Signal mem mem_type begin PROCESS CLKA BEGIN IF CLKA EVENT AND CLKA 1 THEN IF WEA 1 THEN mem conv_integer ADDRA lt DIA END IF DOA lt mem conv_integer ADDRA END IF END PROCESS PROCESS CLKB BEGIN IF CLKB EVENT AND CLKB 1 THEN DOB lt mem conv_integer ADDRB END IF END PROCESS end rtl 9 20 Precision Synthesis Installation Guide 2003c Update1 March 2004 Designing with Xilinx Handling Xilinx Design Issues Figure 9 18 shows a recommended style for inferring the NO_CHANGE mode Both ports are driven by the same clock The output latches of Port A are never assigned a value during a write operation so the old value remains Figure 9 18 Inferring NO_CHANGE Mode One Clock Style 1 library IEEE use IEEF std_logic_1164 all use IEEEF std_logic_unsigned all entity V2RAM is port DOA out std_logic_vector 3 downto 0 DIA in std_logic_vector 3 downto 0 DOB out std_logic_vector 3 downto 0 ADDRA in std_logic_vector 12 downto 0 ADDRB in std_logic_vector 12 downto 0 WEA in std logic
38. 1 THEN mem conv_integer ADDRA lt DIA ELSE DOA lt mem conv_integer ADDRA END IF ADDRB_INT lt ADDRB END IF END PROCESS DOB lt mem conv_integer ADDRB_INT end rtl 9 22 Precision Synthesis Installation Guide 2003c Updatet March 2004 Designing with Xilinx Handling Xilinx Design Issues Figure 9 20 illustrates a RAM that is driven by different clocks Port A is used to both read and write with the NO_CHANGE mode inferred Port B is used for read operations only Figure 9 20 Inferring NO_ CHANGE Mode Two Clocks Library TEER use IEEFF std_logic_1164 all use IEEEF std_logic_unsigned all entity V2RAM is port DOA out std_logic_vector 3 downto 0 DIA z in std logic vector 3 downto 0 DOB out std_logic_vector 3 downto 0 ADDRA an std Logic vectori downto 0 ADDRB ian std logig vector 12 downto 0 WEA in std_logic CORA im std logic CLKB in std logic 7 end V2RAM architecture rtl of V2RAM is Signal declarations type mem_type is array 8191 downto 0 of STD_LOGIC_VECTOR 3 downto 0 Signal mem mem_type begin PROCESS CLKA BEGIN IF CLKA EVENT AND CLKA 1 THEN IF WEA 1 THEN mem conv_integer ADDRA lt DIA ELSE DOA lt mem conv_integer ADDRA END IF END IF END PROCESS PROCESS CLKB BEGIN IF CLKB EVENT AND CLKB 1 THEN DOB lt mem conv_integer ADDRB END IF END PROCESS end rtl Precision Synthesis Installation Gu
39. 2 Precision Synthesis Installation Guide 2003c Update 8 5 March 2004 Altera MAX PLUS II Integration Designing with Altera Devices Setting Altera MAX PLUS Il Options As shown in Figure 8 4 you can change pre set options from the Tools gt Set Options pull down menu The option settings are explained in the paragraphs that follow Figure 8 4 Setting MAX PLUS II Options H Input Optimization Altera website J MAX PLUS II g Integrated Place and Route L External Place and Route Path to MaxPlus2 installation tree Max2_HOME m Generate Vendor Constraint File Do not run commands H Session Settings F Schematic Wiewer Timing Analysis C Input Output Delay Setup Hold Register Performance W Setup Max PLUS Il Create ACF File Auto Fast 1 0 Auto Register Packing Auto Implement in EAB Show verbose information while generating the ACF file Back annotation netlist format Yerlog EDIF tf VHDL Cancel Apply Help Altera Logo If your web browser is active click on this logo to bring up the Altera website home page http www altera com 8 6 Precision Synthesis Installation Guide 2003c Update March 2004 Designing with Altera Devices Altera MAX PLUS II Integration Path to MAX PLUS II installation tree Specify the pathname to the MAX PLUS II installation tree for example D maxplus2 Do not run commands This switch is primarily used for debugging the Precision script th
40. 3 163 Sequential Elements 4 4 set set_attribute 3 165 Set Attributes using the design switch 2 8 set_attribute 3 165 set_clock_latency 3 167 set_clock_transition 3 169 set_clock_uncertainty 3 171 set_false_path 3 173 set_fanout_load 3 178 set_hierarchy_separator 3 179 set_impl_property 3 180 set_input_delay 3 181 set_input_dir 3 185 set_input_file 3 186 set_max_delay 3 188 set_max_fanout 3 191 set_min_delay 3 192 set_multicycle_path 3 195 set_output_delay 3 200 set_preference 3 203 set_project_property 3 204 set_propagated_clock 3 205 set_results_dir 3 206 set_working_dir 3 207 setup_analysis 3 209 setup_design 3 211 setup_place_and_route 3 218 Index 4 Index Index cont Shell 1 1 slew 2 22 Standard Layout 6 4 Supported Devices Actel 6 19 Synopsys Design Constraints 6 10 synthesis_clearbox 2 3 2 23 synthesize 3 227 T Tcl Command Interface 1 2 Running Script on Invocation 1 5 Script 1 3 1 5 Technology Library 4 1 Timing Weight 6 5 Timing Driven Layout 6 4 tmpfile 3 228 triff 2 3 2 5 2 23 type_encoding_ style 2 3 2 23 U UCF files 9 2 unalias 3 229 ungroup 3 230 update_constraint_file 3 232 uselowskewlines 2 3 2 6 2 24 utility scripts 3 27 3 29 V view_floorplan 3 233 view_ schematic 3 234 X Xilinx Coregen Generated Modules 9 3 Design Issues 9 1 Devices Supported Virtex II 9 36 ISE Environment 9 31 Precision Synthesis Instal
41. 5 6 7 10 Devices Supported 9536 PC44 CS48 VQ44 VQ64 9572 PC44 CS48 VQ64 VQ44 TQ100 95144 Q100 TQ144 CS144 95288 Q144 PQ208 FG256 CS280 Xilinx CPLD Family Xilinx 9500XV 3 Speed Grades supported 3 4 5 7 10 Devices Supported 9536xv PCA CS48 VQ44 9572xv ss PC44 VQ44 TQ100 CS48 95144xv TQ100 TQ144 CS144 Q144 PQ208 FG256 CS280 Precision Synthesis Installation Guide 2003c Update1 9 41 March 2004 Xilinx Devices Supported Designing with Xilinx 9 42 Precision Synthesis Installation Guide 2003c Update1 March 2004 Index Index A Actel 6 1 Actel Antifuse Devices Supported 6 13 Actel Designer Integration 6 1 Actel Flash Devices Supported 6 12 Actel Mature Products 6 16 Actel Script File 6 4 Handling Actel Design Issues 6 6 Path to Actel Designer installation tree 6 4 Process Derating factors 6 19 Quality of Results and Runtime Improvements 6 9 RadHard Designs 6 6 Running the Actel Designer Environment 6 2 Setting Actel Designer Options 6 3 Supported Actel Devices 6 11 activate_impl 3 15 add_input_file 3 16 add_macro_file 3 19 add_placement_file 3 21 alias 3 23 Aliasing 1 4 all_clocks SDC 3 24 all_inouts 3 26 all_inputs SDC 3 27 all_ outputs SDC 3 29 all_registers 3 31 Altera Altera MAX PLUS II Integration 8 4 Design Issues 8 1 Devices Supported 8 12 Megafunction Blocks 8 10 Memory Inferencing 8 2 Quartus II v2 X and v3 0 Support 8 9 running
42. Active ICX Plan ICX Pro IEX Sentry ICX Tau ICX Verify ICX Vision ICX Custom Model ICX Custom Modeling ICX Project Modeling ICX Standard Library IDEA Series Idea Station IKOS In All The Right Places INFOR M IFX Inexia Innovate PCB Innoveda Integrated Product Development Integra Station Integration Tool Kit IT INTELLITEST Interactive LAYOUT Interconnect Table Interface Based Design IB Inventra Inventra IPX Inventra Soft Cores IP Engine IF Evaluation Kit IP Factory IP PCB IP QuickUse PSim 15 Analyzer 15 Floorplanner 1S MultiBoard IS Optimizer IS Synthesizer iSolve IV locity Language Neutral Licensing Latium LAYOUT LNL LBIST LBISTArchitect Le Lcore Leaf Cell Toolkit Led LED Layout Leonardo Leonardolnsight LeonardoSpectrum Librarian Library Builder LineSim Logic Analyzer on a Chip Logic Builder Logical Cable LogicLib logio Lsim Lsim DSM Lsim Gate LsimNet Lsim Power Analyst Lsim Review Lsim Switch Lsim XL Mach PA Mach TA Manu factureView Manufacturing Advisor Manufacturing Cable MaskCompose MaskKPE MBIST MBISTArchitect MBIST Full Speed MBISTFlex MBIST In Place MBIST Manager MCM Designer MCM Station MOV MeeaFunction Memory Builder Memory Builder Conductor Memory Builder Mozart Memory Designer Memory Model Builder Mentor Mentor Graphics MicroPlan MicroRoute Microtec Mixed Signal Pro ModelEditor ModelSim ModelSim LN ModelSim VHDL ModelS
43. Commands get_path_definition_set Returns a previously defined Path Definition set Applies only to Precision Physical Example gt get_path_definition_set name route2 from pl Syntax get_path_definition_set name lt path_definition_set_name gt from thru to gt lt path_definition_set_name gt Arguments name path_definition_set_name Name of the path definition set Options from lt from_list gt Specifies the name of the first net in the list thru lt thru_list gt Specifies the name of the final net in a thru list to lt to_list gt Specifies the name of the final net in a from to list Description This command returns a previously defined Path Definition set It will return either a from lt from_list gt thru lt thru_list gt to lt to_list gt list when no options are specified a lt from_list gt list when from option is specified a lt thru_list gt list when a thru option is specified or a lt to_list gt list when to list option is specified 3 74 Precision Synthesis Installation Guide 2003c Update1 March 2004 Commands get_path_definition_set Related Commands create_path_definition_set Precision Synthesis Installation Guide 2003c Update 3 75 March 2004 get_pins SDC Commands get_pins SDC Return a list of instance pins Examples The following example displays all the instance pins in the entire design named
44. Compiles the Design How Precision Compiles Designs Implements Finite State Machines If your state machine uses state variables that are enumerated types Precision will assign bit values to these variables encoding The encoding method that is used depends of the number of states in the FSM For example the one hot encoding technique requires more flip flops than the other encoding techniques but yields better performance because it contains fewer and less complex levels of logic Therefore one hot encoding is beneficial for FPGA designs because flip flops are cheaper in that technology Precision generates a FSM report in the FSM work directory in the implementation directory for the project for each state machine in the design A summary of the encoding values is displayed in the transcript Performing Pre optimization After the generic RTL data base is created Precision Synthesis does what is called pre optimization technology independent optimization During this process the following 1s accomplished Components are extracted Objects such as counters decoders RAMs and ROMs are separated from generic logic New views of these items are created Operators that are disjoint only used in different clock cycles are shared Unused logic logic that doesn t affect the output signals is removed Wide XORs and comparators are optimized by removing common sub expressions The boundary of each module i
45. Designing with Actel Devices Supported Actel Devices 42MX Family 42MX Family Default Speed Grade 3 Speed Grades supported 3 2 1 STD STDV F FV 3V 2V 1V A42MX36 CQ208 PQ208 PQ240 CQ256 BG272 40MX Family 40MX Family Default Speed Grade 3 Speed Grades supported 3 2 1 STD F Devices Supported A40MX02 PL44 PL68 PQ100 VQ80 A40MX04 PL44 PL68 PL84 PQ100 VQ80 eX Family gt X Family Default Speed Grade P Speed Grades supported F P STD Precision Synthesis Installation Guide 2003c Update 6 15 March 2004 Supported Actel Devices Designing with Actel Devices Actel Mature Products 3200DX Family A32300DX RQ208 RQ240 CQ256 VRQ208 VRQ240 ACT2 1200XL Family ACT2 1200XL Family Default Speed Grade 2 Speed Grades supported 1 2 STD F Devices Supported Al225XL PG100 PL84 PQ100 VQ100 VPL384 VVQ100 A1240XL VPL84 VTQ176 PG132 PL84 PQ144 TQ176 PQ100 A1280XL CQ172 CP176 PL84 PQ160 TQ176 PQ208 VPL84 VTQ176 6 16 Precision Synthesis Installation Guide 2003c Update March 2004 Designing with Actel Devices Supported Actel Devices Act3 Family Al415A PG100 PL84 CP100 80 200 104 96 PQ100 VQ100 PL84 70 200 104 96 A14V15A PL84 VQ100 BG225 CQ196 CP207 PQ160 PQ208 TQ176 BG225 PQ160 PQ208 TQ176 BG313 CQ256 CP257 RQ208 RQ208 CQ256 BG313 RQ208 BG313 Act3RT Family Act3RT Family Default Speed
46. E Memntere nny teaemer Che renner rem ners ret 1 2 Precision Syninenis Tol C OmIDANI S earainn a a aa 1 2 E A E ET TEA EE R 1 2 Methods for Using Commands With a Tcl Script 20 0 ceccccccccecceeesseeeeeeceeceeeeseseeeeseeeeeeeaes 1 3 Conon Loe Done Apa E EE ETER 1 4 Po arene E e 1 5 Toe Leni Da M ected pee eee ee ences 1 6 Chapter 2 Attributes Pavesi cic ci ite ll Gels ee ig Ble ges Cal y 2 1 c h ee eee nner eee mneT eee eens een enone ern ee 2 1 Fronc onal Lat or Ur ADUE i See nee nee ene et ners Roles nD Iver a ai eaei 2 4 E arti ri en E E 2 6 Sy RIM ENV Aes n y HDL eea E 2 6 SPCT ne ADS TOE rE EO ene 2 7 Specifying Attributes on the Command Line or in scripts eesssssseoeeeessssssssserersssssseseeees 2 8 Specifying Attributes using the design ccd ccc diaercerelaeneeneedas 2 8 Mapping Other Attributes to Precision ssssssssoeeesesssssseeererrssssssssceressssssesseresssssssesseeresssses 2 9 EDOR Ee Oo gee ding 151 ok a E kee nrer ore nen amen ee ne nnONT cnr yt temney em eetr Sree 2 9 aroy Pii Amber NO cesar cesta 2 9 e a eS LUN Le Mneneenna aren nen cre nUNT erate rte eye ST eer E t apa tes hice er Rene Serr nT tT on mrrt ery Yoerere Te tere 2 10 OE Ck Bh b one eee eee ee eee eeee eT bean eee penne ere meee TCS eR een T Tee Reese Serer Trees et cere reer Sete eee 2 10 ELC ge EE EE IIA ATE EE ter sts Ure AET EEA yee rr er AET TEETE 2 11 Gedicated mt 0 0ccesosceeccecscesrecocscerescessoccesencosevconcssc
47. ES Transcript 4 Design Center Input Directory C Precision Synthesis Installation Guide 2003c Update 1 9 31 March 2004 The Xilinx ISE Environment Designing with Xilinx Xilinx Post Place and Route Analysis Figure 9 29 shows the Precision GUI after the design is implemented Notice that icons for addition ISE analysis tools are displayed in the Design Bar A number of Xilinx output files are also written to the implementation directory and you may view the content by double clicking on each file Figure 9 29 Analyzing the Xilinx Place and Route Results aS pseudorandom Mentor Graphics Precision Physical Synthesis Design Center ioj x File View Tools Window Help alins VIRTES 2403144 6 Frequency 100 MHZ Project Files Design Hierarchy E Project pseudorandom F pseudorandom rtl RTL J Impl pseudorandom _impl_1 Eg Clocks E Impl pseudorandom_impl_2 uns P a8 Constraint Files FE pseudorandom _constraints sde l A user_constraints uct Excluded J Script Files l EE nat Files a T ia ae ile Warnings 5 Infos 7 E gt write oe g yz Schematic oO H A seediz4 0 Place amp Route Fad Technology Schematic re init a dal Dhveical Database Ee Outputs Cy Click to view the placed prt H E Nets nS i St routed qesign port Seen Instances Rey Timing Violation Report Fy Blocks LA Click to run power analysis Peport DF 10 dlatrg_25 JES gt on the routed design m edf AD N priority_e
48. Grade 3 Speed Grades supported 1 2 3 STD Devices Supported RT1425A CQ132 RT1460A CQ196 RP14100A CQ256 Precision Synthesis Installation Guide 2003c Update 6 17 March 2004 Supported Actel Devices Act2 Family Designing with Actel Devices A1225 A1225A A1225XL A1225XLV A1240 A1240A A1240XL A1240XLV A1280 RH1280 A1280A RP1280A RT1280A A1280XL A1280XLV 6 18 Precision Synthesis Installation Guide 2003c Update March 2004 Designing with Actel Devices Supported Actel Devices Act1 Family Default Speed Grade 2 Speed Grades supported 1 2 STD Devices Supported PL44 PL68 CP84 PQ100 PL44 PL68 PL84 CP84 CQ84 PQ100 PG84 PL44 PL68 PQ100 VQ80 A1020B CP84 CQ84 PL44 PL68 PL84 PQ100 VQ100 VQ80 A10V10B PL68 VQ80 A10V20B PL68 PL84 VQ80 RH1020 CQ84 RT1020 CQ84 gt R TI Q 3 lt A1010A A1020A A1010B Actel Process Derating Factors The following tables list process derating factors for these Actel families Act 1 Act 2 Act 3 1200XK A3200DX and A3265DX Command Line Definitions BC best case TC typical case WC worst case STD standard 1 2 F speed grade V low voltage MIL military COM commercial IND industrial A3265DX Devices Derating Factors lt BCITCIWC gt lt STDI 1I 2 3 gt _3265 Value of Process Operating Conditions Speed Grade Options BC F best case F TC F typical F WC F worst case F BC 3 best case 3 TC 3 typical 3 WC
49. I O This often reduces area requirements but can slow internal circuitry This option corresponds directly to the Automatic Fast I O option in the Altera MAX PLUS I GUI Default is O false auto_register_packing A boolean value specifying whether or not to allow the MAX PLUS II compiler to maximize efficient device usage automatically implementing register packing by placing a combinational logic function and a register with a single data input in the same logic cell This option corresponds directly to the same option in the Altera MAX PLUS II GUI Default is O false auto_tmplement_in_eab A boolean value specifying whether or not to allow the MAX PLUS II compiler to automatically implement some logic in Flex 10K EABs This option corresponds directly to the same option in the Altera MAX PLUS II GUI Default is O false acf_verbose A boolean value specifying whether or not to transcript the complete messaging while generating an ACF file Default is O false ba_format lt format gt Specifies as string which 1s the format of the back annotation file that will be generated by the implementation tools Possible options are Verilog EDIF or VHDL The default is VHDL Altera Quartus II Command Names Integrated Place and Route Set the options specified in the Integrated Place and Route dialog box Generate Vendor Constraint File Set the options specified in the Generate Vendor Constraint File dialo
50. ISE tools The commands in the script are echoed to the Precision Transcript window without the commands actually being executed by the implementation tools Precision Synthesis Installation Guide 2003c Update 9 35 March 2004 Xilinx Devices Supported Designing with Xilinx Enable Auto Offset Relaxation in Vendor Constraint File If an input constraint on a port is too tight place and route may fail This option allows Precision Synthesis to automatically relax such a constraint in order to let P amp R finish A warning message is written to the transcript when a constraint is relaxed The default is 1 true Use UCF Timing Constraints This switch has meaning when you have timing constraints in an UCF file that you have added to the Input File List By default the timing constraints in the input UCF file will be written to the generated UCF file after synthesis no matter how you may have manually changed the timing constraints on the in memory design In effect the content of the generated output UCF file will be identical to that specified input UCF file This ensures that you maintain the original golden timing constraints for place and route If you turn this switch off the timing constraints that are currently applied to the in memory design are written to the generated UCF file This includes any changes to the original UCF timing constrants that you may have made through the GUI Xilinx Devices Supported Virtex ll P
51. If you specify a cell name one path start point on that cell is affected All paths from these start points to the endpoints in the to_list are constrained to the delay_value If you don t specify a to_list all paths from the from_list are affected This list cannot include output ports If you include more than one object you must enclose the objects in quotes or in braces to lt to_list gt A list of names of ports internal pins or cells in the current design to use to find path endpoints All paths to the specified endpoints are constrained to the specified 3 188 Precision Synthesis Installation Guide 2003c Update March 2004 Commands set_max_delay SDC delay_value If you don t specify a from_list all paths to the specified to_list are affected This list cannot include input ports If you specify a cell name one path endpoint on that cell is affected If you include more than one object you must enclose the objects in quotes or in braces Clock pins are not valid endpoints for max_delay through lt through_list gt A list of path throughpoints port pin or cell names in the current design The maximum delay value applies only to paths that pass through one of the points in the through_list If you include more than one object you must enclose the objects in quotes or in braces If you specify the through option multiple times the maximum delay values apply to paths that pass through a member o
52. Installation Guide 2003c Update March 2004 Commands report_technologies report_technologies Generate a report listing technology libraries that are being used in the current design Example report_technologies Syntax report_technologies single_level List technology libraries in this level only Related Commands setup_design list_technology Precision Synthesis Installation Guide 2003c Update 1 3 153 March 2004 report_timing report_timing Run the PreciseTime Timing Analyzer and return information about the design Example report_timing summary Syntax report_timing lt report_file_name gt append_ replace num_paths lt number_of_paths gt capacitance fanout show_schematic limit value lt slack value gt through lt through_points gt from lt start_points gt to lt end_points gt setup_flag physical critical_paths end_points start_points longest clock_frequency clock_list lt list_of_clocks gt hold_flag all_clocks nworst lt number_of_paths gt npaths_per_startpoint lt number_of_paths gt margin_limit_slack lt slack_value gt summary more_paths source_clock_path clock_domain_crossing index lt path_index gt test_tech_cell_char histogram hist_num bins lt number_of_bins gt hist_max_slack lt slack_value gt hist_min_slack lt s
53. OR ITS LICENSORS BE LIABLE FOR INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES INCLUDING LOST PROFITS OR SAVINGS WHETHER BASED ON CONTRACT TORT OR ANY OTHER LEGAL THEORY EVEN IF MENTOR GRAPHICS OR ITS LICENSORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES IN NO EVENT SHALL MENTOR GRAPHICS OR ITS LICENSORS LIABILITY UNDER THIS AGREEMENT EXCEED THE AMOUNT PAID BY YOU FOR THE SOFTWARE OR SERVICE GIVING RISE TO THE CLAIM IN THE CASE WHERE NO AMOUNT WAS PAID MENTOR GRAPHICS AND ITS LICENSORS SHALL HAVE NO LIABILITY FOR ANY DAMAGES WHATSOEVER LIFE ENDANGERING ACTIVITIES NEITHER MENTOR GRAPHICS NOR ITS LICENSORS SHALL BE LIABLE FOR ANY DAMAGES RESULTING FROM OR IN CONNECTION WITH THE USE OF SOFTWARE IN ANY APPLICATION WHERE THE FAILURE OR INACCURACY OF THE SOFTWARE MIGHT RESULT IN DEATH OR PERSONAL INJURY INDEMNIFICATION YOU AGREE TO INDEMNIFY AND HOLD HARMLESS MENTOR GRAPHICS AND ITS LICENSORS FROM ANY CLAIMS LOSS COST DAMAGE EXPENSE OR LIABILITY INCLUDING ATTORNEYS FEES ARISING OUT OF OR IN CONNECTION WITH YOUR USE OF SOFTWARE AS DESCRIBED IN SECTION 7 INFRINGEMENT 9 1 Mentor Graphics will defend or settle at its option and expense any action brought against you alleging that Software infringes a patent or copyright or misappropriates a trade secret in the United States Canada Japan or member state of the European Patent Office Mentor Graphics will pay any costs and damages finally awarded against you that a
54. PT For example if the value is set to 35 the Optimizer stops collapsing equations when it exceeds 35 PT This option works the opposite of Splitting Max Product Term Precision Synthesis Installation Guide 2003c Update 1 3 March 2004 The Lattice isoLEVER Environment Max PTerm Limit Max Fanin Specifies the maximum fanin Max Symbols FMax Logic Level 1 4 Designing with Lattice Devices Precision Synthesis Installation Guide 2003c Update March 2004 Designing with Lattice Devices The Lattice ispLEVER ORCA Environment The Lattice ispLEVER ORCA Environment As shown in Figure 7 3 the Lattice ispLEVER ORCA environment is integrated into the Precision RTL Synthesis environment After Synthesis the technology mapped design is written to the current implementation directory as an EDIF netlist file To run the automated Place and Route flow just click Launch ispLEVER ORCA icon in the ispLEVER ORCA Tool Bar The ispTOOLS uses the current implementation directory as the project directory After the design is compiled you may invoke the ispLEVER ORCA GUI manually and open the project From that point you can view reports run analysis tools and manually drive the physical implementation to completion Figure 7 3 Running the Lattice ispoLEVER ORCA Environment us Simplemath Mentor Graphics Precision Physical Synthesis Design Center Ee xj b File View Tools Window Help Lattice OR CA 4E orfeQ2BAS52C 3 B
55. Planner Signal Spy Signal Vision SignaMask OPC Signature Synthesis Simulation Manager SimPilot SimView Smartgrid SmartMask SmartParts SmartRouter SmartScripts Smartshape SNX SneakPath Analyzer SpeedGate SpeedGate DSV Speed Wave SOS Initiative Source Explorer SpiceNet SST Velocity Standard Power Model Format SP MP Structure Recovery Super C Super IC Station Supermax ECAD Symbol Genie Symbolscript SymGen SYMED SynthesisWizard System Architect System Design Station System Modeling Blocks Systems on Board Initiative SystemVision TargetManager Tau TeamPCB TeraCell TeraPlace TeraPl ace GF TechNotes TestKompress Test Station Test Structure Builder The Ultimate Site For HDL Simulation The Ultimate Tool For HDL Simulation TimeCloser Timing Builder TNX ToolBuilder Tran sable Truetiming Utopia Vlog V Express V Net VHDLnet VWHDLwrite Verinex View Base ViewDraw ViewCreator ViewLogic ViewSim ViewWare Viking Virtual Library VirtuaLogic Virtual Target Virtual Test Manager TOP Virtual Wire Voyager VETA VETA me VRTXoc VRTXsa VRTX32 VStation VStation 30M Waveform DataPort We Make TMN Easy Wiz o matic WorkX pert xCalibre xCalibrate Xconfig AlibCreator XMLZ2AXEL Xpert Apert API XperBuilder Apert Dialogs Xpert Profiler XRAY XRAY MasterWorks XSH Xtrace Xtrace Daemon A trace Protocol Xtreme Design Client Xtreme Design Session Atrem
56. QFP caBGA fpBGA ispmach5000B Devices ispmach5000B Devices spmachS000BDeviess OOO Packages QFP PQFP fpBGA isomach5000VG Devices ispmach5000VG Devices LC5768VG 1OF256C 10F484C LCS51024VG 10F484C 10F676C LC1536VG 10F676C Packages fpBGA ispXPGA Devices ispXPGA Devices LFX 1200B 02 F9OOOI FE6801 LFX 1200B 03 F9OOC F9OOI FE680C FE6801 iILFX1200B 04 F9OOC F9OOI FE680C FEA6801 LFX1200B 05 F900C FE680C 7 12 Precision Synthesis Installation Guide 2003c Update1 March 2004 Designing with Lattice Devices Lattice CPLD Devices Supported LFX 1200C 02 F9OOOI FE6801 LFX 1200C 03 F900C F9OOI FE680C FE6801 iLFX 1200C 04 F900C F9OOI FE680C FE6801 LFX1200C 05 F900C FE680C Packages fpBGA fpSBGA isoXPLDS000MX Devices ispXPLD5000MX Devices AQ208C 5Q208C 75Q208C 5Q208I1 75Q208I1 10Q2081 4F256C F256C 75F256C 5F2561 75F2561 10F2561 4F484C 5F484C SF484C 5F484I 75F4841 10F484I AQ208C 5Q208C 75Q208C 5Q208I1 75Q208I1 10Q2081 4F256C F256C 75F256C 5F2561 75F2561 10F2561 4F484C 5F484C SF484C 5F484I 75F484I1 10F484I AQ208C 5Q208C 75Q208C 5Q208I 75Q208I1 10Q2081 4F256C F256C 75F256C 5F2561 75F2561 10F2561 4F484C 5F484C SF484C 5F484I 75F4841 10F484I Packages MACH Devices MACH Devices MACH4 M4 32 32 64 32 96 48 128N 64 128 64 196 96 256 128 MACH4 MA4LV 32 32 64 32 96 48 128N 64 128 64 196 96 256 128 Low Voltage
57. STD low voltage Act1 Devices Derating Factors lt BCITCIWC gt lt STDI FI 11 21l 3 gt VIRHOIRH3 Value of Process Operating Speed Grade Options Conditions BCSTDRHO best case RHO TCSTDRHO typical RHO WCSTDRHO worst case RHO BCSTDRH3 best case RH3 TCSTDRH3 typical RH3 WCSTDRH3 worst case RH3 BCSTDV best case STD low voltage TCSTDV typical STD low voltage WCSTDV worst case STD low voltage BC 3 best case 3 TC 3 typical 3 WC 3 worst case 3 BC 2 best case 2 TC 2 typical 2 WC 2 worst case 2 Precision Synthesis Installation Guide 2003c Update 1 6 21 March 2004 Supported Actel Devices Value of Process BC 1 TC 1 WC 1 BCSTD TCSTD WCSTD Operating Conditions best case typical worst case best case typical worst case Act3 Devices Derating Factors lt BCITCIWC gt lt STDI 1I 2 3 gt V Value of Process BCSTDV TCSTDV WCSTDV BC 3 TC 3 WC 3 BC 2 TC 2 WC 2 BC 1 TC 1 WC 1 BCSTD TCSTD WCSTD 6 22 Operating Conditions best case typical worst case best case typical worst case best case typical worst case best case typical worst case best case typical worst case Designing with Actel Devices Speed Grade Options Speed Grade Options STD low voltage STD low voltage STD low voltage Precision Synthesis Installation Guide 2003c Update March 2004 Chapter 7 Designing with Lattice Devices The Lattice isoLEVER Environment As shown in Figure 7 1
58. Synthesis Installation Guide 2003c Update1 March 2004 Commands get_cells SDC get_cells SDC Get cells instances from the current design relative to the current instance Example gt get_cells reg tx reg_a tx reg_b Syntax get_cells lt patterns gt lt pacterns gt Description The get_cells command searches for the specified pattern in the design relative to the current_instance and returns a list of instance pathnames This command returns the absolute instance path from the top of the design regardless of the value of current_instance The search pattern can include the absolute instance pathnames or pathnames relative to the current_instance The value of current_instance is only used as the relative top of hierarchy to begin the search By default the current_instance 1s set to current_design top of the design hierarchy You can also use wildcards and all object names are case sensitive Wildcards do not imply descending into hierarchy For example get_cells t returns the instances inside any hierarchical block beginning with t on the current level of hierarchy defined by current_instance The wildcard string is terminated by the hierarchical separator If you omit the search pattern Precision Synthesis returns an error Related Commands get_clocks SDC get_lib_cells SDC get_designs get_lib_pins SDC get_false_paths get_multicycle_paths get_lib_cells SDC get_nets SDC
59. TEST REE Seem eo nevEEy Core tere carn free A 4 12 Pe Bee AE EEEE AEA EEEE EE AT IEA ET AE EIEE E 4 17 Understanding the In Memory Design Data Model snnnneesssssssooenessssssessrerssssssessseressssssss 4 18 Chapter 5 Files Reference Understanding toe Piles ina Working DP SCIOly eemnrcrinennineormnanioriainmienaiinnwu 5 1 DBT Te cause Cs N15 al gil foal eS 4 55 6 cls eee eee nn eo eene PST ETE Tee eT ONE COR TEESE NT SESE TCT TA MEE ORE TEST Ten tent Herne ret rt 5 2 Precision Synthesis Installation Guide 2003c Update 1 vii March 2004 Table of Contents Table of Contents cont eo Boe SHG aE D a LO al ee en ee ee E eee Oe E E E AE N teers T ent cee 5 4 Prescon mOn PAU 01 O nen eee ee ee ee nae Pee one ae ee ee eee ere emer ne Aree e Serr ererey 5 4 Chapter 6 Designing with Actel Devices a ee ier REEE eerie etal 6 1 Seme Act Derner ONONE esros cea Tmt E aiaa 6 3 Br Oer ee O a S eaen 6 6 Panan FoG DSS 127 e NASS 6 6 bae a gie n e e a A AE E erie EAE A eerie ee eens 6 7 Quality of Results and Runtime Improvements for Actel Technologies ceeeeeeeeeeees 6 9 Consina Ce ee NVA ried and Layo eeina 6 9 Usinge Synopsys Desin Constraints usisirsiiiniraiies ins i nn a rna easiness 6 10 Seleena Miltary poranne ONIONS yenienn E E E 6 11 E E T a T A E EAE 6 11 ACEL r DOV ces SUPPO ori EEE E E 6 12 Ack AnG e Doros oO A eR ert Permanente teriee Phare tn caren t Seren near one 6 13 Actel Fr sanetsen teppei cre tessa sean Eii
60. Update1 March 2004 Table of Contents Table of Contents cont AE csv a eest ay ed eee eee 7 13 Ud ES 8 2B oi E ene eee ee rere er ne E O etry ne ene a ae 7 14 EA ATE T EEN PE aries ea a oer P EA wed E EA deen 7 14 oy err EES 7 16 Chapter 8 Designing with Altera Devices Hondius Altan Donien ee capensis ae i ET 8 1 Et Kereta O POE erain E a asi meena 8 1 Assigning an Altera LogicLock Region to a Blo CK s ssssseeesssssssseeceesessssssecereessssssseeceressss 8 1 How Memory Inferencing Works for Altera cccccccessssesceececcecaesesssesceeeeeseeeeseseseeeeeeneas 8 2 PMA dD eoe U Die aa Rememer eee eenne nee reeeN rere Teme renter aU nveE Ter mir tTURrnenrernt terrier entice rtttnrr 8 4 ellis Alena NAA Aa PLL H Ct ccoscccctsinsriasioriaioriavstanssiassaseiientnenenaatshieenabian 8 6 Aera ROL cig L o e 10l 6 a E AETR 8 8 aoc MEZAT paces escent A A AA A A A A trae 8 9 Soie ANa ars OUDON sersan EEEE R 8 9 Lime Aler ay BIOO eneee E denier 8 10 Altera Devices OO ccnersnicetssnstdrieanesinderiiddeieie iier rar kas EnA AEA E En EAEE 8 12 se Mies SB a a a E REE TEE 8 12 SPAGA Devices tense eiciseei ion eeneorenuneaene 8 13 Bt Dorea Sa a aE RA 8 13 T EET ST a EEE Eye renn eee pent ey emer 8 13 ee arm Der a a 8 14 Morcar petra p seco reen EREE EAEE AEN EERE EA 8 15 ATERTU EO e E EA 8 15 AFEA AEE DO O SO EEA 8 16 APEA JULE DEVDI E eE 8 16 APEA AOK Dorice SOPO eea EES Ts 8 17 FLEA aR ee oot SUPONE pE ea RDE 8 17 FEES COOU TOOU
61. and destination clocks against which the arrival time Setup constraint and Hold constraint are referenced are determined by looking at the ideal waveform of the clocks from which the source and destination clocks are propagated The source and destination clocks must be in the same domain and can be propagated from the same or different clocks The combination of the source clock edge time the destination clock edge time and the destination pin Setup and Hold times produce a window of time during which the signal transition must arrive at the destination required time window Precision Synthesis assumes that the required time window will occur within a single cycle of the destination clock If by design the delay in a path is long enough to cause the data signal to arrive after the required time window then a Setup violation occurs If by design the delay is short enough to cause the data signal to arrive before the required time window then a Hold constraint violation occurs To avoid erroneous errors the path can be defined as a multicycle path by moving the clock edges against which the Setup Hold or Setup and Hold constraints are measured by a specified number of cycles Figure 3 10 illustrates a multicycle required time window for a signal at the destination pin of a path between a typical pair of positive edge triggered flip flops driven by the same clock Precision Synthesis Installation Guide 2003c Update 3 197 March 2004 set_m
62. are constrained to the delay_value If you don t specify a to_list all paths from the from_list are affected This list cannot include output ports If you include more than one object you must enclose the objects in quotes or in braces to lt to_list gt A list of names of ports internal pins or cells in the current design to use to find path endpoints All paths to the specified endpoints are constrained to the specified 3 192 Precision Synthesis Installation Guide 2003c Update March 2004 Commands set_min_delay SDC delay_value If you don t specify a from_list all paths to the specified to_list are affected This list cannot include input ports If you specify a cell name one path endpoint on that cell is affected If you include more than one object you must enclose the objects in quotes or in braces through lt through_list gt A list of path throughpoints port pin or leaf cell names in the current design The minimum delay value applies only to paths that pass through one of the points in the through_list If you include more than one object you must enclose the objects in quotes or in braces If you specify the through option multiple times the minimum delay values apply to paths that pass through a member of each through_list in the order the lists were given In other words the path must first pass through a member of the first through_list then through a member of the second list and so
63. both rising and falling delays are affected Fall refers to a falling value at the path endpoint setup hold setup indicates that path_multiplier is used for setup calculations hold indicates that path_multiplier is used for hold calculations Precision Synthesis Installation Guide 2003c Update 1 3 195 March 2004 set_multicycle_path SDC Commands start end Indicates whether the multicycle information 1s relative to the period of the start clock or the end clock These options are only needed for multi frequency designs otherwise start and end are equivalent The start clock is the clock source related to the register or primary input at the path startpoint The end clock is the clock source related to the register or primary output at the path endpoint The default 1s to move the setup check relative to the end clock and the hold check relative to the start clock A setup multiplier of 2 with end moves the relation forward one cycle of the end clock A setup multiplier of 2 with start moves the relation backward one cycle of the start clock A hold multiplier of 1 with start moves the relation forward one cycle of the start clock A hold multiplier of 1 with end moves the relation backward one cycle of the end clock from lt from_list gt A list of names of clocks ports pins or cells to use to find path startpoints If you specify a clock either user defined or automatically derived clockname all registe
64. clock edge of the destination flop If fall value 1s not specified the rise value will be used for both edges fall Specify latency for falling clock edge of the destination flop If rise value is not specified the fall value will be used for both edges source Inform Precision that the specified time 1s the clock latency prior to the defined clock pin design lt rtl gatelevel gt Tells the tool whether to look for the object in the RTL or the gatelevel view Precision Synthesis Installation Guide 2003c Update 3 167 March 2004 set_clock_latency SDC Commands Description The set_clock_latency command specifies the delay from the pin of the specified clock to the clock pin on the register By default Precision uses zero clock latency unless you propagate the clock set_propagated_clock where Precision will use the delays through the cells in the clock path You can specify different latency values for falling and rising edge clocks using the fall and rise switches Using the source switch you can specify the clock latency that occurred prior to the pin of the specified clock This switch 1s typically used to specify off chip clock delays when you are only analyzing part of the design Related Commands set_false_path SDC set_false_path SDC set_input_delay SDC set_multicycle_path SDC set_output_delay SDC report_missing_constraints 3 168 Precision Synthesis Installation Guide 2003c Update March
65. design If neither rise nor fa11 is specified rising and falling delays are assumed to be equal fall Specifies that lt delay_value gt refers to a falling transition on specified output ports in the current design If neither rise nor fa11 is specified rising and falling delays are assumed to be equal add_delay Specifies whether to add information to the existing output delay specification or to overwrite the value The add_delay option enables you to capture information about multiple paths leading to an output port that are relative to different clocks or clock edges design lt rtl gatelevel gt Tells the tool whether to look for the object in the RTL or the gatelevel view Description The remove_output_delay command is primarily used by the GUI to remove an output delay constraint that was previously set on an in memory design object Related Commands set_output_delay SDC remove_input_delay report_constraints 3 126 Precision Synthesis Installation Guide 2003c Update March 2004 Commands remove_propagated_ clock remove_propagated_clock Do not propagate clock latency values through the specified clocks Example remove_propagated_clock all_clocks Syntax remove_propagated_clock lt clock_name gt Arguments and Options design rtl gatelevel design lt rtl gatelevel gt Tells the tool whether to look for the object in the RTL or the gatelevel view Description The
66. false You define a path as false by attaching a false path definition to the start from through through and or end to points of the path The following rules apply when attaching a false path definition to a path You must specify at least one point on the path from through or to You can specify all or any combination of the three points If you specify a from point only then all paths starting from the specified point and ending at a primary output bidirectional data port output or input data pin of any edge triggered flip flop or level sensitive latch are considered false A from point can be a pin a clock all primary inputs and bi directional ports all inputs or the output data pin of any edge triggered flip flop or level sensitive latch all registers If you specify multiple through points then only those paths that flow through at least one pin in the set are considered false If you specify a to point only then all paths that end at the specified point and begin at a primary input bidirectional data port input or output data pin of any edge triggered flip flop or level sensitive latch are considered false A to point can be a pin a clock all primary outputs and bi directional ports all outputs or the input data pin of any edge triggered flip flop or level sensitive latch all registers For slack path analysis a path must star
67. flop If fall value is not specified the rise value will be used for both edges fall Specify uncertainty for falling clock edge of the destination flop If rise value 1s not specified the fall value will be used for both edges setup Apply clock uncertainty to only setup checks hold not supported yet Specify clock uncertainty for hold checks design lt rtl gatelevel gt Tells the tool whether to look for the object in the RTL or the gatelevel view Description The set_clock_uncertainty command allows you set specify skew to flops that are clocked by defined clocks The skew can be defined on either all paths leading to the destination flop or you can use the from and to switches to specify the relative clock skew between two defined clocks within the same clock domain Clocks that are not in the same clock domain are not considered during timing analysis This command can also be used to adjust the margin of the clock approaches during timing analysis Related Commands set_false_path SDC set_false_path SDC set_input_delay SDC set_multicycle_path SDC set_output_delay SDC report_missing_constraints 3 172 Precision Synthesis Installation Guide 2003c Updatet March 2004 Commands set_false_path SDC set_false_ path SDC Ignore slack values on the specified paths Example set_false_path from reset set_false_path from alu reg_mult to alu reg_mult Syntax set_false_pa
68. get_lib_cells SDC get_path_definition_set get_ports SDC Precision Synthesis Installation Guide 2003c Update 3 61 March 2004 get_clock_domains Commands get_clock_domains Return a list of clock domains in the current design Example get_clocks_domains Syntax get_clock_domains lt patterns gt lt patterns gt Description The get_clocks command returns a list of defined clocks that were previous specified using the create_clock command If you need a list of hierarchical pathnames to the sources of the clocks in the design use the find_clocks command You can also use wildcards and all object names are case sensitive Defined clocks do not contain hierarchy If you omit the search pattern Precision Synthesis returns an error Returns a list of clock domains in the current design Related Commands get_cells SDC get_lib_cells SDC get_clocks SDC get_lib_pins SDC get_designs get_multicycle_paths get_false_paths get_nets SDC get_lib_cells SDC get_path_definition_set get_lib_cells SDC get_ports SDC 3 62 Precision Synthesis Installation Guide 2003c Update March 2004 Commands get_clocks SDC get_clocks SDC Return a list of defined clocks in the current design Example get_clocks Syntax get_clocks lt patterns gt lt patterns gt Description The get_clocks command returns a list of defined clocks that were previous specified using the create_clock command If yo
69. has a set of inputs tied high TRUE The effect of these connections is that the circuit resolves to a smaller set of gates resulting in a smaller area for this design portion When this example gets mapped to a technology later in the process the result is a three input NAND gate After constant propagation Precision expands the operators that exist in the design which is described below Before After EB lt D DD Result T Technology Specific Result Figure 4 2 Constant Propagation Example Resource sharing Resource sharing is the process of restructuring a generic design by sharing operators that are used in mutually exclusive situations in order to create an optimal design The tool only performs resource sharing if you have not disabled this feature and if the view has generic Precision Synthesis Installation Guide 2003c Update1 4 7 March 2004 How Precision Synthesizes the Design How Precision Compiles Designs operators Figure 4 3 shows an example using VHDL code and the results of resource sharing select select If select 1 THEN al result lt a1 a2 ELSE result lt a1 a2 result gt result END IF a2 VHDL Code Before Resource Sharing After Resource Sharing Figure 4 3 Resource Sharing Results To perform resource sharing Precision executes the following steps 1 Identifies operator configurations within the netlist that have the potential to be shared with other configur
70. if the value is set to 35 the Optimizer splits equations if it has more than 35 PT This option works the opposite of Collapsing Max Product Term max_pterm _collapse lt string gt This option lets you control the Fitter optimization process by setting a maximum limit on the number of Product Terms PT in each equation In other words the Optimizer shapes the equations relative to the set number of PT For example if the value is set to 35 the Optimizer stops collapsing equations when it exceeds 35 PT This option works the opposite of Splitting Max Product Term max_pterm_limit lt string gt This option lets you control the Fitter optimization process by setting a maximum limit on the number of Product Terms PT in each equation max_fanin lt string gt Specifies the maximum fanin max_symbols lt string gt fmax_logic_levels lt string gt Lattice isoLEVER ORCA Command Names Integrated Place and Route Set the options specified in the Integrated Place and Route dialog box Precision Synthesis Installation Guide 2003c Update 3 223 March 2004 setup _place_and_route Commands Launch ispLEVER Set the options specified in the Launch ispLEVER dialog box Generate ORCA Preference File Set the options specified in the Generate ORCA Preference File dialog box Lattice isoLEVER ORCA Command Arguments install_dir lt vendor_installation_directory_pathname gt Specifies the pathname
71. implementation tools After the Precision output files are generated you can invoke the automatic Place and Route flow click Place amp Route do a floor plan by hand click Design Planner or invoke the Xilinx Project Navigator click Launch ISE and manually step through the implementation process The ISE tools use the current implementation directory as the Xilinx project directory and pick up the design files as appropriate Figure 9 28 Running the Xilinx ISE Environment Pt pseudorandom Mentor Graphics Precision Physical Synthesis Design Center Pa File View Tools Window Help Dekses e oa e v zl Project lins VIR EXD A 4ics 144 6 Frequency 100 MHZ Editor Project Files Design Hierarchy Design A eL a Deoiact orandom E F pseudorandom trtl_ R TL Click to launch the Fa E e Clocks Design Analysis Floorplanner _ dorandom impl 2 unsi E Ports E E Input Files H EI Nets EE Constraint Files H E Instances FE pseudorandom _constraints sde user_constraints uck Excluded J Script Files Output Files You may pass a UCF tt Lal Log File Infos 7 from the Input File List to j i ti i he ISE tool a ene Click to automatically hematic the ISE tools Place and Route chnology Schematic rea Report Rei Timing Report ei Timing Violation Report The ISE tools work p REJ Constraints Report these two files DE pseudorandom edf ailin User Constraint File 4
72. information on the specified paths If used with to only all paths leading to the specified endpoints are reset If used with from only all paths leading from the specified startpoints are reset If used with from and to only paths between those points are reset Only information of the same rise fallsetup hold type is reset This is equivalent to using the reset_path command with similar arguments before the set_multicycle_path is issued design lt rtl gatelevel gt Tells the tool whether to look for the object in the RTL or the gatelevel view 3 196 Precision Synthesis Installation Guide 2003c Update March 2004 Commands set_multicycle_path SDC Description The set_multicycle_path command adds a multicycle path attribute to all data paths defined by the specified pins or ports When calculating slack Precision Synthesis compares the time at which a signal transition arrives at a pin arrival time to the time at which the signal transition is required to arrive at the pin required time The arrival time is determined by the calculated or specified arrival time value and the circuit delay measured from the rising or falling edge of the clock that produces the signal transition The clock to which the arrival time is referenced 1s called the source clock The required time is based on the specified Setup and Hold constraints referenced to the edges on a clock called the destination clock The edges of the propagated source
73. insensitive name value pairs for the attributes of indicated objects This command is intended to be used in Tcl scripts You can however assign the result to a Tcl variable You can then use the variable in any other Tcl command for example a foreach loop More Examples report_attributes This example lists the attributes of the current design and their values report_attributes work This example lists the attributes and their values of the library called work Precision Synthesis Installation Guide 2003c Update 3 131 March 2004 report_attributes Commands report_attributes work top INTERFACE This example lists the attributes and their values of the view INTERFACE of the cell top in the library work report_attributes port inport 1 This example lists the attributes and their values of the port inport 1 in the current design report_attributes inst u This example lists the attributes and their values for all instances whose names starts with a u Related Commands list_design Known Bugs Limitations You cannot use file I O redirection with this command because it returns a Tcl list and no standard output There is no command that returns the value of a single attribute on an object 3 132 Precision Synthesis Installation Guide 2003c Update March 2004 Commands report_connections report_connections Generate a report containing objects that are connected to the specified object s Example repor
74. is available for all ONO Families effort_level lt string gt This variable specifies the duration of the timing driven phase of optimization during layout Its value specifies the duration of this phase as a percentage of the default duration The default value is 100 and the selectable range is within 25 500 Reducing the effort level also reduces the run time of Timing Driven place and route TDPR With an effort level of 25 TDPR will be almost four times faster With fewer iterations however performance may suffer Routability may or may not be affected With an effort level of 200 TDPR will be almost two times slower This variable does not have much effect on timing Note This advanced option is only available for the SX SX A and eX families 3 102 Precision Synthesis Installation Guide 2003c Update March 2004 Commands place_and_route timing_weight lt string gt Setting this option to values within a recommended range of 10 150 changes the weight of the timing objective function thus biasing TDPR in favor of either routability or performance The timing weight value specifies this weight as a percentage of the default weight i e a value of 100 will have no effect If you use a value less than 100 more emphasis will be placed on routability and less on performance Such a setting would be appropriate for a design that fails to route with TDPR In case more emphasis on performance is desired set this variable to a v
75. name inst_name lt instance_name gt Name of the new instance formed from the instances indicated by the value of list_of_instances The group command automatically generates a name for the new instance The instance name must be a simple name not a formalized name Precision Synthesis Installation Guide 2003c Update 3 85 March 2004 group Commands Description The group command moves a list of instances with their connected nets from one view to a new view in a new cell thus creating a new level of hierarchy With this command you can define the name of the instance the view and the cell where the new view resides The group command is useful to cluster logic that should be optimized as a single view For example if two instances of two views share much of the same logic or interconnect 1t makes sense to group them into a new level of hierarchy and to ungroup the hierarchy inside the new group This way subsequent optimization operations can minimize the logic shared between the two original views resulting in smaller or faster designs Related Commands ungroup 3 86 Precision Synthesis Installation Guide 2003c Update March 2004 Commands help help Give help on commands Example Syntax help lt search_string gt lt search_string gt Arguments lt search_string gt Regular expression used to search for a full text informational message about that match the search_string pattern
76. new project will have no implementation You can create a new implementation later by calling the new_impl command 3 96 Precision Synthesis Installation Guide 2003c Update March 2004 Commands Related Commands activate_impl close_project copy_impl delete_impl get_impl_property new_project get_project_impls get_project_name new_impl Open_project save_impl Precision Synthesis Installation Guide 2003c Update March 2004 3 97 open_project Commands open_project Open an existing project Example open_project C designs uart_top psp Syntax open_project lt project_pathnemt gt lt project_pathname gt Arguments lt project_pathname gt The full path and filename of the project to open Include the psp filename extension Description The open_project command loads the specified project file and restores the saved state of the design Upon loading the project it will activate an implementation under the following conditions 1 The project contains only one implementation 2 The project was last closed with an implementation still active In this case that implementation is reactivated The open_project command can be used only when no project is currently open Related Commands activate_impl get_impl_property close_project get_project_impls copy_impl get_project_name delete_impl new_project save_impl 3 98 Precision Synthesis Installation Guide 2003c Update March 2004 Commands p
77. on cells in a previously loaded library You must include the library cell and port name with a hierarchical separator You can also use wildcards and all object names are case sensitive The wildcard string is terminated by the hierarchical separator For example get_lib_pins xcve CLK returns the CLK pins on any cell in the previously loaded xcve library If you omit the search pattern Precision Synthesis returns an error Related Commands get_cells SDC get_lib_cells SDC get_clocks SDC get_multicycle_paths get_designs get_nets SDC get_false_paths get_path_definition_set get_lib_cells SDC get_ports SDC get_lib_cells SDC 3 68 Precision Synthesis Installation Guide 2003c Update March 2004 Commands get_libs SDC get_libs SDC Return a list of currently loaded libraries that match the search pattern Example The following example lists all of the currently loaded libraries gt get_libs PRIMITIVES a42mx work OPERATORS Syntax get_libraries lt patterns gt lt paLllerns gt Description The get_libs command returns a list of currently loaded libraries that match the search pattern To get a list of available library use the Setup Design icon in the Design Bar or use the setup_design list_tech command In most designs Precision Synthesis creates a set of libraries during the synthesis process PRIMITIVES At invocation Precision Synthesis automatically loads the P
78. on for every through_list specified If you use the through option in combination with the from or to options the minimum delay applies only 1f the from or to conditions are satisfied and the through conditions are satisfied You cannot use hierarchical cell names as through points You should use hierarchical pins on a cell instead rise fall Specifies whether endpoint rising or falling delays are delays that are constrained If neither rise nor fall is specified then both are constrained reset_path Tells PreciseTime to remove existing point to point exception information on the specified paths Only information of the same rise fall type is reset design lt rtl gatelevel gt Tells the tool whether to look for the object in the RTL or the gatelevel view Description The set_min_delay command is a point to point timing exception command that overrides the default single cycle timing relationship for one or more timing paths Other point to point timing exception commands include set_multicycle_path SDC set_max_delay SDC and set_false_path SDC This command specifies that the minimum path length for any start point in from_list to any endpoint in to_list must be less than delay_value Individual minimum delay targets are automatically derived from clock waveforms and port input or output delays For more information refer to the create_clock SDC set_input_delay SDC and set_output_delay S
79. operations you can enable retiming with the following command setup_design retiming And you can disable retiming with the following command setup_design retiming false Retiming can also be disabled on a register by register basis or on a module basis If a generic RTL register has the dont_retime attribute set the register will not be retimed Further if a hierarchical module has a dont_retime attribute set then all logic within that module will not be retimed These attributes can be set in the Design Browser or in the Schematic by using the popup menu Set attributes on the Right Mouse button From a script use the set_attribute command to selectively disable retiming For example set_attribute reg_dat25 instance name dont_retime value true Attributes can also be set in the source VHDL attribute dont_retime boolean attribute dont_retime of dat25 signal is true Or in Verilog Wire dat25 synthesis attribute dat25 dont_retime true Retiming can also be disabled on a register by register basis If the generic RTL register has the dont_retime attribute set the register will not be retimed Further if the output signal of a register has the preserve_signal attribute set this will also prevent the register from being retimed These attributes can be set in the Design Browser or in the Schematic by using the popup menu on the Right Mouse button From a script you can use the set_attribute command to sel
80. output port in the return list You must use the clock names specified in the create_clock command and not the instance pathname to the clock pin If you need to determine the names of the output ports of a lower level block you can either use the Design Browser tool and navigate to the block in hierarchy or you can use the get_ports command to specify the instance pathname and return the instance ports Related Commands all_inputs SDC all_registers all_ inouts all clocks SDC 3 30 Precision Synthesis Installation Guide 2003c Update1 March 2004 Commands all_ registers all_ registers Return a list of all sequential elements or sequential pins in the current design Example all_registers Syntax all_ registers flip_flops latches Options flip_flops This option limits the search to only return the names of flip flops in the top level of hierarchy in a technology mapped design latches This option limits the search to only return the names of latches in the top level of hierarchy in a technology mapped design Description The all_registers command returns a list of sequential cells in the current design Related Commands all_inputs SDC all_ outputs SDC all _inouts all clocks SDC Precision Synthesis Installation Guide 2003c Update 1 3 31 March 2004 auto_ write Commands auto write Writes an intermediate netlist or constraint file Example auto_write filter_compil
81. overview of some of the techniques that Precision Synthesis uses to synthesize a design Precision Synthesis uses this process whenever you execute the synthesize command Implement operators During synthesize Precision Synthesis implements the operator blocks based on the vendor supplied netlists After the operators are implemented Precision flattens the operator block and adds a xmplr_dont_change attribute to the instances used to implement the operator Since the operators use the fastest implementations there is not use in attempting to optimize these instances during synthesize Manipulate Hierarchy Precision does smart auto dissolving of instances to keep as much hierarchy as possible to aid debugging which removing any hierarchy that may constrain the optimizer from generating the best possible results Based on the value of the hierarchy attribute Bubble Tristates This allows you and Precision Synthesis more flexibility in handling implementing tristates By default Precision Synthesis will not move tristate drivers across hierarchy because it would require changing the port interface on the hierarchical block to pass the enable signal You can explicitly do this using the bubble_tristates command You should also be aware of whether your target technology has tristate cells available internally and or in the IO ring For example Altera technologies only have tristates on the IO ring no internal tristates How Preci
82. provided by three separated commands as described in the following table Although set_working_dir Note is still supported you should use the alternate commands instead because set_working_dir may become unsupported at some future release In addition the behavior of set_working_dir has been modified so that it properly supports both 2003c and pre 2003c environments The current behavior is described in below Alternate Command Functionality ea Changes the currently working directory set_input_dir Set the relative path names when adding input files Precision Synthesis Installation Guide 2003c Update 3 207 March 2004 set_working_dir Deprecated Commands set_results_dir Set explicitly where output files will be written when ot using projects The set_working_dir command configures the following Precision settings to the specified pathname Current Working Directory The current working directory CWD can be changed at any time by using the cd command either from the command line or from within Tcl scripts The CWD 1s used by Precision Synthesis to resolve partial pathnames to files other than input files and results files Input Directory The input directory location can be reset be calling the set_input_dir command Precision Synthesis uses the input directory to resolve partial pathnames to input files Results Directory The behavior of set_working_dir with respect to the results directory settin
83. remove_propagated_clock command informs Precision to use the ideal clock latency values Ideal clock latency is zero or the value set by set_clock_latency The remove_propagated_clock command also works for derived clocks When this command is issued for a derived clock it turns OFF clock skew analysis For example if you issue the following command for the derived clock in the example then no clock delay is reported for this clock remove_propagated_clock A B C DCM CLKDV Related Commands create_clock SDC report_timing Precision Synthesis Installation Guide 2003c Update 3 127 March 2004 report_analysis Commands report_analysis Return information on how the specified timing report options are set Example report_analysis num_critical_paths This command returns the number of critical paths that will be reported in PreciseTime Syntax report_analysis clock_frequency num_summary_paths critical_ paths num_critical_paths timing_violations net_fanout clock_domain_crossing missing_constraints Description The report_analysis command returns information on how the timing report configuration options are set Related Commands setup_analysis 3 128 Precision Synthesis Installation Guide 2003c Update March 2004 Commands report_area report_area Report the accumulated area of the current design Example report_area area_leafs rpt all_leafs Syntax report_area lt repo
84. sends the report to the Transcript window The library must have been previously loaded in memory with the setup_design command If you prefer you can specify the file option to write the report to a file Related Commands report_area report_net report_attributes report_timing report_missing_constraints Precision Synthesis Installation Guide 2003c Update1 3 141 March 2004 report_license Commands report_license Return a list of the license features that are currently in use Example report_license Syntax report_license pid Options pid Return of the product ID of each feature in use Description The report_license command returns a list of the license features that are currently in use how many of each feature is available and the type floating or fixed The name of the feature is returned by default If you specify the pia switch the feature s product ID is returned Knowing the product ID can be useful information to someone who is experienced in troubleshooting licensing problems Related Commands 3 142 Precision Synthesis Installation Guide 2003c Updatet March 2004 Commands report_memory_utilization report_memory_utilization Generate a report detailing the amount of memory being used by the tool Example report_memory_utilization Syntax report_memory_utilization detailed Options detailed Returns a more detailed report on memory utilization Description The repor
85. sent eT 3 29 UE C2 a1 5 c Mee eee eee oer eee TE lett men rerree teva rarer reat rer 3 31 LCE Ae 5 a nn oe ee eee eee ee eee even em ene eee ern ee ne eer ye eee Te ee aan Teer 3 32 a aca ect tepscsannss EE E S E kenandtadenspetasuneialinasas 3 34 fe ee or Ge 8 1 eee eee ee ee ee Tee REMY ree TEN ERT eee rene eeRCy a ny cent MERTEN Tee Oe Ver eee ee tee 3 35 ics encore paves esse E E cade siiusa seed E A AA 3 36 B09 TRI E A EA EAA AA E EA 3 37 SOR L B a a OEI PAAA A O AAE OAA A 3 39 a e EEEE EE AEA 3 40 Sc ioma e E gt T E EEE AE E A T rete 3 44 e a bal tm T E E renee mrrtT There te rove e 3 45 Cg be UMM EG 08 11 ca SLA ee nn ne eee ee eee eer ene een oe nnn ee een 3 46 i io OIII ENIA PA ORERE PIEI E NE EIA EE I A eine eens 3 47 e a a O 3 48 Precision Synthesis Installation Guide 2003c Update1 March 2004 Table of Contents Table of Contents cont GF pte gs sd hee mae eg va ected meet A baat sae ened gd aneen enone siete reste 3 49 BI agendas eae caesar E pw se gnc dt ene es nae Rioee 3 50 ater enhance etc tcc 3 51 Fie et PEE eas ETE PATES AAEE AAE EEEE AEE EEEN A AET 3 52 HADAL E e E E E E E E E E EE A A NEE E EE E AE TN 3 53 if 1c EANET EEEE TEIA A SE A EI AEE MIAE A EE V EA TE EE N 3 54 a E A 3 57 O E r rA EAE A AAEE A AE EE E EE E E EE A ETAS 3 59 aoe e OAE A AA EENET ATEA E E E EIE EEA TEEST E E 3 60 le WE E D E E E EA TEE LEE A T EE TEE EE A SATS 3 61 B A Cele E E O EE 3 62 R a i B a PENE AA E NAAA S EN EN EN PENA AOAN OA
86. technologies by entering the command setup_design list_technology from the Interactive Command Line Shell output_delay lt output_delay_value gt Specifies the global output delay in ns This is normally set when the user enters an Output Delay value from the Setup Design dialog box This optional default value serves as a starting point for setting I O constraints After the Compile step you will be able to select each I O port in the Design Hierarchy pane and adjust the constraint accordingly operator_preserve lt operatorname limit gt Sends a list all known synthesis libraries in the Transcript window package lt package_name gt Package name for this design as specified in the INI_FILE for the current technology This argument is normally set when the user selects a package option from the Setup Design dialog box in the GUI 3 214 Precision Synthesis Installation Guide 2003c Update1 March 2004 Commands setup design part lt part_name gt Part name as specified in the INI_FILE for the current technology This argument is normally set when the user selects a part option from the Setup Design dialog box in the GUI partition_size lt xxxx gt o Sets the size of a partition in a design Setting a partition size lets you partition a large design which may help with synthesis radhardmethod lt method gt Sets the radiation tolerant method to use on supported Actel technologies This value applies
87. that was previously set on an in memory design object Related Commands set_input_delay SDC remove_output_delay report_constraints Precision Synthesis Installation Guide 2003c Update 3 123 March 2004 remove_input_file Commands remove_input_file Remove one or more input files from the input_file_list Example remove_input_file address_decode v cpu_interface v Syntax remove_input_file lt input_file_name gt all lt input_file name gt Arguments lt input_file_name gt The name of one or more input files to remove from the input_file_list You may specify just the leaf name of the file not the entire pathname This is an argument of type list Options all Tells Precision Synthesis to remove all files from the input_file_list Description The remove_input_file command is normally used by the Precision Synthesis GUI to remove input files at the direction of the user For example if the user right clicks on the Input Files folder and selects Remove All Input Files from the popup menu then the following command is executed remove_input_file all Related Commands add_input_file set_input_file move_input_file setup_design report_input_file_list remove_design 3 124 Precision Synthesis Installation Guide 2003c Update1 March 2004 Commands remove_output_delay remove_output_ delay Remove the Output Delay on the specified pins or output ports Example remove_outp
88. the GUI and selecting Force Input Flop onto Output Pad gt FALSE The equivalent attribute for non Xilinx technologies is map_complex 2 18 Precision Synthesis Installation Guide 2003c Update1 March 2004 Attributes Pre Defined User Attributes output_delay Obsolete This attribute is no longer supported An output delay is now specified as a timing constraint For conceptual and procedural information about setting an output delay constraint refer to Specifying Output Delay in the Precision RTL Synthesis User s Manual See also set_output_delay SDC in Chapter 3 Commands pad Specifies which technology specific I O cell to used for a specific port Verilog pragma attribute rst pad ibuf VHDL attribute pad string attribute pad of rst signal is ibuft Interactive Command Line Shell set_attribute port rst name pad value ibuf pin_number Assigns a specific device pin number to a specific port in the design Verilog pragma attribute clk pin _number P10 VHDL attribute pin_number string attribute pin_number of clk signal is P10 Interactive Command Line Shell set attribute port clk name pin number value P10 preserve driver Preserves the specified signal and the driver in the design Specifies that both a signal and the signal name must survive synthesis Precision Synthesis Installation Guide 2003c Update 1 2 19 March 2004 Pre Defined User Attributes Attribut
89. the curly braces may need to be escaped from a shell command line as curly braces are characters that have special meaning to shell languages precision file test1 tcl Xilinx true 64 logfile lt file_pathname gt Specifies the new leaf name and pathname of the Log File The default leaf name is precision log and its default location is the current working directory The Log File is a Tcl compliant transcript of the current session and may be used as a command file regclear Clear out the registry Default FALSE Typically used during an uninstall procedure reginit Initialize the registry Default FALSE Returns the tool to the same state as though it was just installed force Force regclear and reginit do not ask questions act in silent mode Default FALSE version When used with the shell option version displays Precision version information and exits If shell is not specified Precision invokes normally in GUI mode help Bring up the help a dialog box Description This command invokes Precision RTL Synthesis from a Unix Shell command line or DOS command prompt For Windows users the option switches may also be specified after the leaf name precision exe in the Target pathname on a Windows Shortcut Examples Cr Fprecision shell lt file Fe my project run tel The command above invokes Precision RTL Synthesis in the non GUI mode and sources the Tcl file run tcl Itis assumed
90. the selectable range 1s within 25 500 Reducing the effort level also reduces the run time of Timing Driven place and route TDPR With an effort level of 25 TDPR will be almost four times faster With fewer iterations however performance may suffer Routability may or may not be affected With an effort level of 200 TDPR will be almost two times slower This variable does not have much effect on timing Note This advanced option is only available for the SX SX A and eX families Timing Weight Setting this option to values within a recommended range of 10 150 changes the weight of the timing objective function thus biasing TDPR in favor of either routability or performance The timing weight value specifies this weight as a percentage of the default weight 1 e a value of 100 will have no effect If you use a value less than 100 more emphasis will be placed on routability and less on performance Such a setting would be appropriate for a design that fails to route with TDPR In case more emphasis on performance is desired set this variable to a value higher than 100 In this case routing failure is more likely A very high timing value weight could also distort the optimization process and degrade performance A value greater than 150 is not recommended Note This advanced option is only available for the SX SX A and eX families Precision Synthesis Installation Guide 2003c Update 6 5 March 2004 Handling Actel Design Issues
91. the specified technology library Example report_library file F reports lib_wireloads rep wire_loads Syntax report_library lt library_name gt file lt report_file _pathname gt auto_ wire loads selection wire_ loads operating_conditions all string lt library_name gt lt report_file_pathname gt Arguments lt library_name gt Specifies the internal name of the technology library You can generate a list of all the supported libraries by executing setup_design list from the Interactive Command Line Shell Options file report_file_pathname Pathname of the file for which to write the library report If you specify a leaf name the file is written to the current working directory The rep extension is not required but identifies the file as a report file If you omit this argument the report is written to the Transcript window auto_wire_loads_selection Report on the automatic wire load selection tables wire_loads Report on the wire load tables operating_conditions Report on the operating conditions 3 140 Precision Synthesis Installation Guide 2003c Update1 March 2004 Commands report_library all Generates a very detailed report on each cell in the library If you are sending the report to the Transcript window it may take a few moments to complete Description The report_library command generates a report on the specified technology library and
92. to be edited If only the leaf name of the file is specified then Precision Synthesis looks in the current directory for the file Options linenum lt line_number gt Sets the edit cursor to the specified line number for editing Description The edit command is primarily used to edit files from the Interactive Command Line If you are operating the tool by entering commands from the Interactive Command Line you can use Unix like commands to view the content of the current directory Is move up or down in the directory structure cd and 1f you see a file you wish to edit type something like the following edit mydesignfile vhd line 102 Related Commands 3 50 Precision Synthesis Installation Guide 2003c Update March 2004 Commands exec_interactive exec_ interactive Spawn an interactive child process from the precision shell command prompt Example alias vi exec_interactive vi Syntax exec interactive lt command gt lt command gt Arguments lt command gt The interactive command that is to be from the Precision shell Description The exec_interactive command is primarily used to spawn a child process for interactive programs from the precision shell This command is basically the same as the Tcl command exec except that logging it turned off In other words the transcript of the user interaction with a spawned program such as vi is not sent to the precision 1log file Related Commands Pr
93. to products by using trademarks Marks owned by a third party and such use is not an attempt to indicate Mentor Graphics as a source of that product but is intended to indicate a product from or associated with a respective third party Use of third party Marks is intended to inure to the benefit of the respective third party Rev 040109
94. to the entire design You can override this design wdie value on individual hierarchical blocks or flop instances by setting the radhardmethod attribute on a specified object The value must be one of cec tmr tmr_cc or none as described below o cc Combinatorial Combinatorial This method provides a way to avoid using a radiation soft S module flip flip by combining two combinatorial cells with feedback o tmr Triple Module Redundancy triple voting This is a register implementation technique whereby each register is implemented by three flip flops or latches that vote to determine the true state of the register o trm_cc Triple Module Redundant C C is a module redundancy technique where each voting register is composed of combinatorial cells with feedback instead of S module flip flop or latch primitives reset Deprecated option use close_project or close_results_dir command instead Returns the options of this command to their default values and clears all the input file entries from the Project Files pane of the Design Center window resource_sharing Enable resource sharing The default is t rue If you wish to set this switch to false then you should use the following syntax resource_sharing false Resource sharing is an optimization technique that attempts to mux large operators so they may be shared for mutually exclusive operations Resource sharing occurs when multiple arit
95. value Wild cards and lists are accepted If you omit this argument the remove_attribute command operates on the current design Options port net instance This is an indicator that object_name refers to a port net or an instance respectively If you omit this option the remove_att ribute command assumes that object_name refers to an instance unless object_name refers to a library cell or view global Remove this attribute from nets globally all levels of hierarchy name lt attribute_name gt This 1s the name of the attribute that is being removed Attribute names are case insensitive 3 114 Precision Synthesis Installation Guide 2003c Update1 March 2004 Commands remove_attribute type lt attribute_type gt This specifies the data type of the attribute that is being remove Valid values such as string or boolean depend on the attribute specified with the name option design lt rtl gatelevel gt Tells the tool whether to look for the object in the RTL or the gatelevel view Description The remove_attribute command removes an attribute from one or more objects in the in memory design database This command is primarily used by the Precision Synthesis GUI to remove attributes at the direction of the user More Examples remove_attribute port clk name PIN_NUMBER Remove attribute P IN_NUMBER on port clk of the RTL design implied when the design option is not specified remo
96. work or call save_impIl prior to calling close_project Related Commands Open_project save_impl new_project 3 34 Precision Synthesis Installation Guide 2003c Update March 2004 Commands close_ results dir close_results_ dir Unload the currently loaded design Available only when no project is open Syntax close results dir Description The close_results_dir command unloads the currently loaded design and frees all associated memory This command is only available after the results directory is set by calling set_results_dir command This command is not available while a project is open Related Commands get_results_dir set_results_ dir Precision Synthesis Installation Guide 2003c Update 3 35 March 2004 compile Commands compile Compile the design that is specified by the input_file_list Example compile Syntax compile Arguments and Options None Description The compile command reads the source files that are specified in the input_file_list and creates a generic non technology mapped in memory data base Related Commands set_working_dir Deprecated synthesize setup_design remove_design add_input_file 3 36 Precision Synthesis Installation Guide 2003c Update March 2004 Commands copy_impl copy_impl Create a copy of an existing implementation within the project Example copy impl name clock 2 from clock _1 Creates and makes active a copy of implementation clock_1 The copy is
97. write port while the input data is being written to the memory location NO_CHANGE The output latches of the port remain unchanged during the write operation Detailed information on these memory modes can be found in the Virtex II Platform FPGA User Guide and the Virtex II Pro Platform FPGA User Guide Precision Synthesis Installation Guide 2003c Update 9 13 March 2004 Handling Xilinx Design Issues Designing with Xilinx Precision RTL Synthesis can infer the Block SelectRAM memory mode from the style of your VHDL The examples that follow illustrate the recommended styles that infer the write modes Figure 9 11 shows the recommended VHDL style for inferring a dual port RAM where Port A is the write port and Port B is the read port Both ports are driven by the same clock The default write mode WRITE_FIRST is inferred You can see from the code that during the write operation the input data DIA is written to the output port DOA Figure 9 11 Inferring WRITE_FIRST Mode One Clock Style 1 library LEEE use IEFEF std_logic_1164 all use IEEE std_ logic unsigned all entity V2RAM is port DOA out std_logic_vector 3 downto 0 DIA 4 in std logic vector 3 downto 0 DOB out std logic vector 3 downto 0 ADDRA in std_logic_vector 12 downto 0 ADDRB in std_logic_vector 12 downto 0 WEA in std_logic CLK im std logic 7 end V2RAM architecture rtl of V2RAM is type mem_type is array 8191 downto 0 of STD_LOGIC_VECTOR
98. you Note should use the alternate commands instead because remove_design may become unsupported at some future release gt Beginning with release 2003c the functionality performed by the The remove_design command causes Precision Synthesis to delete some or all on the compiled in memory data base However the input_file_list is retained so you can recompile the design 1f you wish Related Commands remove_input_file save_impl Precision Synthesis Installation Guide 2003c Update 3 121 March 2004 remove_input_delay Commands remove_input_delay Remove the Input Delay on the specified pins or input ports Example remove_input_delay clock sysclk 6 data_in Syntax remove_input_delay lt delay_value gt lt port_pin_list gt clock lt clock_ name gt clock_fall rise fall add_delay design rtl gatelevel Type Arguments float lt delay_value gt string lt clock_name gt list lt Por pin osr Arguments lt delay_value gt Specifies the delay value to be removed from the specified lt port_pin _list gt lt port_pin_list gt A list of input port name s or internal pin name s in the current design to which lt delay_value gt 1s to be removed If more than one object is specified the objects must be enclosed in quotes or in braces Options clock lt clock_name gt Specifies the reference clock to which the specified delay is related If clock_fall1 is used
99. 0 SB432 speed grades 6 and 7 also supported ORCA 3C Family Lattice ORCA 3C Family Speed Grades supported 4 5 6 7 Devices Supported ORCA 3T Family Lattice ORCA 3T Family Speed Grades supported 4 5 6 7 Devices Supported 7 8 Precision Synthesis Installation Guide 2003c Updatet March 2004 Designing with Lattice Devices Lattice ORCA Devices Supported or3tl65SB 432 ORCA 4E Family 2 9 9 OR4E021 IBA352 DB BC432 DB BM416 DB BM680 DB FS256 BM OR4E022 IBA352 DB BC432 DB BM416 DB BM680 DB FS256 BM OR4E023 IBA352 DB BC432 DB BM416 DB BM680 DB FS256 BM N g m alls lt jojy z AIZIE E e aIla nlala llo ciola l Slal2ls Sic Q S o 5 ae ole amp a amp pel e E W ias Precision Synthesis Installation Guide 2003c Update 1 1 9 March 2004 Lattice CPLD Devices Supported Designing with Lattice Devices Lattice CPLD Devices Supported isoGDX Devices ispGDX Devices ispGDX 160 B272 5Q208 7B272 7Q208 ispGDX80A T100 7T100 ispGDX120A Q160 5T176 7Q160 7T176 ispGDX 160A B272 5Q208 7B272 7Q208 Packages BGA PQFP TQFP ispLSI5000VE Devices 8OLT100I 80LT128I1 80LF256I 80LB272I 1OOLT100 1OOLTIO0I 100LB272 100OLB272I 1OOLB256 1OOLB256I 1OOLT128 1OOLT128I 125LT100 125LT100I1 125LB272 125LB2721 125LF256 125LF256I 125LT128 125LT128 165LT100 165LT128 165LF256 165LB272 100LB272 100LB272I 1OOLB256 1OOLB256
100. 003c Update March 2004 Commands place_and_route install_dir lt vendor_installation_directory gt Specifies the directory where the ISE implementation tools are located no exec This option is primarily used to debug the Precision place_and_route script that drives the implementation tools The commands in the script are echoed to the Precision Transcript window without the commands actually being executed by the implementation tools par_ol lt overall_effort gt The place and route overall effort level is specified as a string 1 5 The default is 1 1 Lowest 2 Low 3 Normal 4 High 5 Highest mode lt place_and_route_run_mode gt You can specify Xilinx PAR modes Normal and High or Simulation The default 1s Normal ba_format lt format gt Specifies as string which is the format of the back annotation file that will be generated by the implementation tools Possible options are Verilog VHDL or EDIF The default is Verilog guide_mode lt list gt Available Xilinx PAR modes are Exact and Leverage Exact mode specifies not to make any changes to the layout and 1s used only to make minor changes like replacing a cell Leverage mode uses the current NCD file as a starting point to improve the placement and routing on the next pass You may include an NCD file in your Input File List Precision will mark it as Exclude and pass it through to
101. 10 Infer Sequential Elements 4 4 inff 2 5 2 15 In Memory Design Data Model 4 18 input_delay Obsolete 2 5 2 15 Interactive Command Line Shell 1 3 IO buffers 4 12 iob 2 2 2 5 2 16 1ostandard 2 16 L Lattice CPLD Devices 7 10 ispLEVER Environment 7 1 ispLEVER ORCA Environment 7 5 ORCA Devices 7 7 Timing Analysis 7 3 Layout Mode 6 4 list list_attributes 3 128 3 131 3 137 list_connection 3 133 list_design 3 88 list_technologies 3 39 3 153 list_design 3 88 M map_complex 2 17 max_fanout 2 6 2 17 Military Operating Conditions 6 11 N new_impl 3 95 new_project 3 96 nobuff 2 2 2 6 2 17 nopad 2 2 2 6 2 18 O open_project 3 98 Operators 4 5 4 10 Precision Synthesis Installation Guide 2003c Update March 2004 Optimization Boundary Optimization 4 6 Pre optimization 4 6 outff 2 2 2 5 2 18 output_delay Obsolete 2 3 2 5 2 19 P pad 2 3 2 5 2 19 Path to Precision Synthesis 1 3 physical_synthesis 3 99 pin_number 2 3 2 5 2 19 Pipeline Multipliers 6 7 Place and Route running Altera Quartus II from Precision 6 1 place_and_route 3 101 Precision How Precision Compiles the Design 4 1 How Precision propagates clocks 4 10 How Precision Synthesizes the Design 4 8 precision 3 111 Precision Initialization File Files Precision Initialization File 5 4 Precision Synthesis Invoking 1 1 Tcl Commands 1 2 preserve_driver 2 3 2 6 2 19 preserve_signal 2 3
102. 2003c Update 3 173 March 2004 set_false_path SDC Commands If you specify a clock all path startpoints related to the specified clock are affected If you specify an internal pin the pin must be a path startpoint the clock pin of a flip flop for example If a cell is specified one path startpoint on that cell is affected Any number of from points can be specified You can explicitly set the hierarchical pathname to the port pin or you can nest any of the reporting commands e g get_cells all_inputs in square brackets All paths that end at the data outputs of each register synchronized by a clock can be specified using a defined clock not a hierarchical pathname or a derived clockname A single from pin can be specified using a hierarchical port or pin name One or more pin names can be specified A pin 1s specified as a string the must contain the hierarchical path and netlist name of the pin The netlist name of a bus pin is specified using the following nomenclature bus_name pin_number or bus_name specifies any bus pin 0 through 9 The use of asterisk and question mark wildcard characters is supported Asterisks within pathnames are evaluated as wildcards within a single hierarchy level Multiple bus pins can be specified using the following nomenclature bus_name specifies all pins on bus through lt through_list gt A list of path through points port pin or leaf cell names o
103. 2004 Commands set_clock_transition SDC set_clock_transition SDC Override the clock slew values from the library Example set_clock_transition sysclk 2 set_clock_transition 0 all_clocks Syntax set_clock_uncertainty lt value gt object_name rise fall design rtl gatelevel lt object_name gt lt clock_list gt Arguments lt value gt Number of nanoseconds for the slew value object_name List of defined clocks specified with the create_clock command Options rise Specify uncertainty for rising clock edge of the destination flop If fall value is not specified the rise value will be used for both edges fall Specify uncertainty for falling clock edge of the destination flop If rise value is not specified the fall value will be used for both edges design lt rtl gatelevel gt Tells the tool whether to look for the object in the RTL or the gatelevel view Description The set_clock_transition command allows you override the library values on transition slew time on defined clocks Precision Synthesis Installation Guide 2003c Update 1 3 169 March 2004 set_clock_transition SDC Commands This command is used for overriding unrealistic slew values on clock pins This command only applies to ideal clocks If you propagate the clock set_propagated_clock then the slew times from the library are always used Related Commands set_false_path SDC s
104. 3 March 2004 Pre Defined User Attributes Attributes drive Sets the value to be associated with a drive Verilog pragma attribute port_tx drive 24 VHDL attribute DRIVE integer attribute DRIVE of port_tx signal is 24 Interactive Command Line Shell set_attribute design gatelevel name DRIVE value 24 port type integer tx extract_mac Controls the mapping of multiply accumulate logic to Altera DSP blocks You can affect all instantiations of the DSP block by specifying the attribute on the entity To affect an individual instance you must specify the extract_mac attribute on the specific instance Verilog pragma attribute Mult12x12_I0 extract_mac false VHDL attribute extract_mac boolean attribute extract_mac of Mult12x12_ 10 label is FALSE attribute extract_mac of Mult12x12_ 11 label is TRUE Interactive Command Line Shell set_attribute net u3 u2 Mult12x12 10 name extract _mac value false hierarchy Tells Precision Synthesis to maintain the hierarchy of the module Valid values are preserve or flatten This attribute is applied to instances Verilog pragma attribute Il hierarchy preserve 2 14 Precision Synthesis Installation Guide 2003c Update1 March 2004 Attributes Pre Defined User Attributes VHDL attribute hierarchy string attribute hierarchy of Il label is flatten Interactive Command Line Shell set_attribute instance Il name hierarchy value preserve
105. 3 117 Precision Synthesis Installation Guide 2003c Update1 March 2004 vi Table of Contents Table of Contents cont removye_clock_transition 0 eensneesnsoseseseserosesesesesesessseresssososesososesesoscsososeseresesersssrerseso 3 118 emoe aee a 2 VEE 4 aE E 3 119 SR Ucn J POVAT ENIO AA E EE E E N PE EA A EEN EIEN AT A E 3 120 Se a a r EE ET 3 122 rene T a AA E nee ect ter ter mre here Trem mtr erro ernie ere 3 124 Pone a a e E eE 3 125 o a L E a E 3 127 OEE a AEA EOI OA A AAE A AOE AEE NAAA E 3 128 iy 0 8 GAME o EPAI AEE ANAT EA ATA T E E IA AE I EE ETE T ATE Teeny te 3 129 e E E E cee aa eS enmeRE Mt earner e 3 131 Uo 8 8 BME CLG EW O o A eer nee eee eeee ren Ten TE ape een ere teeter E ty tere sate rerren 3 133 oh S E E T EEA E a ee AA hee ean en ne nee nan ae eer eee em ete ee eet an ee ar 3 135 a Fa arrainean ir EE ERRE 3 137 roro E SE T A EE en eee terrentrnt 3 138 sy 5024 O Ten e AOE EE reer reryr eer ter et rere 3 139 ee AEE ses ea set ee po eee 3 140 aac teenth piconets O ES 3 142 a8 UR ETON ae La Le S een ey pereee ree earn ner n ene eae Den mn Tne ce Men er eee ntn nner er era nirwenre i ssmeT rcrtrecety 3 143 ie 0 6 MEL Te Ons A Senne ers eee are EE ene rae EAA 3 144 152 2 A 2 ene ne ener aw ae a renee een NaEa Reet matey nT Te IONE Ser et Te wert arenes nOrer remnant ee erer nw rt rrr 3 146 I case tet E EEA E EAE E NE EAEE EEE EE 3 148 ero MEE E a E EE E EE 3 149 is 6 97 4 MMR Toi a s l EE
106. 3 worst case 3 BC 2 best case 2 TC 2 typical 2 Precision Synthesis Installation Guide 2003c Update 6 19 March 2004 Supported Actel Devices Designing with Actel Devices Value of Process Operating Conditions Speed Grade Options WC 2 worst case 2 BC 1 best case 1 TC 1 typical 1 WC 1 worst case 1 BCSTD best case STD TCSTD typical STD WCSTD worst case STD A3265DX Devices Low Voltage Derating Factors lt INDICOM gt lt BCITCIWC gt lt STDI 11 21 3 gt V Value of Process Operating Speed Grade Options Conditions INDBCSTDV IND best case STD low voltage INDTCSTDV IND typical STD low voltage INDWCSTDV IND worst case STD low voltage COMBCSTDV COM best case STD low voltage COMTCSTDV COM typical STD low voltage COMWCSTDV COM worst case STD low voltage A3200DX Devices Derating Factors lt BCITCIWC gt lt STDI FI 11 2I 3 gt V Value of Process Operating Conditions Speed Grade Options BC F best case F TC F typical F WC F worst case F BC 3 best case 3 TC 3 typical 3 WC 3 worst case 3 BC 2 best case 2 TC 2 typical 2 6 20 Precision Synthesis Installation Guide 2003c Update March 2004 Designing with Actel Devices Supported Actel Devices Value of Process Operating Conditions Speed Grade Options WC 2 worst case 2 BC 1 best case 1 TC 1 typical 1 WC 1 worst case 1 BCSTD best case STD TCSTD typical STD WCSTD worst case STD BCSTDV best case STD low voltage TCSTDV typical STD low voltage WCSTDV worst case
107. 4 GC280 BC356 ARC208 ARI208 ARC240 ARI240 ABC356 8 22 Precision Synthesis Installation Guide 2003c Update1 March 2004 Designing with Altera Devices Altera Devices Supported MAX 7000S Family Default Speed Grade 5 Speed Grades supported 5 6 7 10 15 Devices Supported EPM7032S LC44 L144 TC44 T144 EPM7064S LC44 L144 TC44 T144 LC84 L184 TC100 TI100 EPM7128S LC84 LI84 QC100 QI100 TC100 TI100 QC160 QI160 EPM7160S LC84 LI84 TC100 TI100 QC160 QI160 EPM7192S QC160 QI160 EPM7256S RC108 RI208 QC208 MAX 9000 Family Default Speed Grade 10 Speed Grades supported 10 15 20 Devices Supported EPM9320 LC84 L184 RC208 RI208 GC280 BC356 ALC84 ALI84 ARC208 ARI208 ABC356 EPM9400 LC84 RC208 RC240 EPM9480 RC208 RC240 EPM9560 RC208 RI2Z08 RC240 RI240 RC304 RI304 GC280 BC356 ARC208 ARI208 ARC240 ARI240 ABC356 oO Precision Synthesis Installation Guide 2003c Update1 8 2 March 2004 Altera Devices Supported Designing with Altera Devices 8 24 Precision Synthesis Installation Guide 2003c Update1 March 2004 Chapter 9 Designing with Xilinx Handling Xilinx Design Issues Handling Clock Resources Automatically Inserting a Xilinx CLKDLL Configuration At your direction Precision will automatically insert the following two Virtex CLKDLL configurations into your design If your design is targetted to Virtex II or Virtex II Pro the Xilinx implementation tools will repla
108. 6 16 Pekel Potoa Doce POT cease easo es mnssi psu ec nen eee 6 19 Chapter 7 Designing with Lattice Devices The Lattice ispLEVER Environment se sssssssesrrissessssssrrrssssisssnisressranararnrssrannradarinsradareisnisen snes 7 1 Sne PLETER 916 161 i RA AR 7 2 The Lattice ispLEVER ORCA Environment esesssseseeeesssesssssserersssssssserersrssssesseeesrsssssses 7 5 Soe OPLEVER ORLA PION iriri NEA 7 6 Lao URCA Devricer Mir seene nea ENARE Ap NST Ri 7 7 Oe BPM ariel aeereee emer ren ereaen nant rrent error e recente naman nmpnr aprre npr iarEtervTan eamrer remy teenr penta 7 7 Daa WAEN l stands aces A EEE T PTE AT AE AA E ETN ETTA 7 7 Ee 9 i EESE E E e arte ant Onn A A ern ne ern mew AE E IE ee te rreratnt karen E fe 7 8 Daae Da l y PONEN EEEE E AAIEN SIO EIIE TA 7 8 ees ERIS ccataespacesapvecantacn E AA E 7 9 Lam eL PED Devices a n R eens 7 10 eG MID 30 a A E E 7 10 PES T E T E aa A E E eas 7 10 By UPS DOVII oirrsrrjrrori thini rre EETA yaieneedaeneeinesiaties 7 11 Eoaea 001s gl Bick 5 rr A R 7 11 Koe DET E E SN 7 11 T ee sha LUIE a gt PERAE N SN ie OE E EE EAA EATA EA EA OE NETA TEA 7 12 e o w ALEE Sal PEEN E EE EAA AEE NEE E EOE EAEE OE 7 12 11 Bh og GMI O a er PCC ER RUE tT PORE T eT ETT eeen Te Ter ne STEELE Re eT EIT NTT Sree were re ereT srr rer ern yee 7 12 cee 4g Ble TAE Ibo es n nen men eee mene RCE MER Ee TanOnETS eter erteT Vane ret Mey Miyeerer Were rr ra rete 7 13 vill Precision Synthesis Installation Guide 2003c
109. 6OLTIOOI 80LT100 60LQ160 80LQ160 60LT176 6OLT1761 80LT176 ispLSI2128VE LOOLT100 135LT100 135LT100I 180LT100 100LB100 135LB100 180LB100 100LQ160 135LQ160 180LQ160 1OOLT176 135LT176 135LT176I 180LT176 100LB208 135LB208 180LB208 ispLSI2192VE 1OOLT128 135LT128 180LT128 100LB 144 135LT144 180LB144 ispLSI2032 80LJ44 8OLJ44I 110LJ44 135LJ44 150LJ44 180LJ44 SOLT44 80LT44I 110LT44 135LT44 1SOLT44 180LT44 SOLT48 80LT48I 110LT48 135LT48 1SOLT48 180LT48 Precision Synthesis Installation Guide 2003c Update 1 7 15 March 2004 Lattice CPLD Devices Supported Designing with Lattice Devices 110LJ44 135LJ44 180LJ44 200LJ44 225LJ44 11OLT44 135LT44 180LT44 200LT44 225LT44 L1OLT48 135LT48 180LT48 200LT48 ispLSI2064 80LJ84 80LJ84I1 100LJ84 125LJ84 80LT100 80LT100I LOOLT100 125LT100 ispLSI2064E 1OOLT100 135LT100 200LT100 ispLSI2096 80LQ128 80LQ128I 100LQ128 125LQ128 80LT128 80LT128I ieee ace 125LT128 ispLSI2096E 100LQ128 100LQ128 135LQ128 180LQ128 100LT128 135LT128 180LT128 180LQ128 LOOLT128 100LQ128 135LQ128 180LQ128 100LT128 135LT128 180LT128 180LT128 ispLSI2128 80LQ160 100LQ160 80LT176 80LT176I 1OOLT176 ispLSI2128E 1O00LT176 135LT176 180LT176 pLSI 3000 Devices pLSI 3000 Devices ispLSI3 160 OLM208 100LM208 125LM208 70LQ208 100LQ208 125LQ208 OLB272 1OOLB272 125LB272 ispLSI3192 OLM240 70LM240I 100LM240 70LB272 1OOLB272 i
110. ASS EC Frequency 100 MHZ Project Files Design Hierarchy E Project simplemath Fl simplerath top main RTL Sie FImpl simplemath impl_1 1 28 Clocks 2e U AUE Click to automatically es E E Ports Place and Route Aint Files 1 a Mets o 5 simplemath sde H E Instances E implernath_top_constra Click to launch the Files isoLEVER Software ut Files Ca 4 Lad Log File Warnings 1 1 FBA RTL Schematic Technology Schematic Rei 4rea Report Rei Timing Report Rei Timing Violation Report Rei Constraints Report Ei simplemath top edf PA ORCA Preference File a ES Transcript 4 Design Center Precision Synthesis Installation Guide 2003c Update 7 5 March 2004 The Lattice isoLEVER ORCA Environment Designing with Lattice Devices Setting isoLEVER ORCA Options As shown in Figure 7 4 you can change pre set options from the Tools gt Set Options pull down menu The option settings are explained in the paragraphs that follow Figure 7 4 Setting isoLEVER ORCA Options Integrated Place and Route t Input Optimization J Analysis TEO Click to bring up the H ii a r amp Lattice website gt a TLI C ce Se ispLEVER ORLA pe Imiceanductor fe Integrated Place and Route Launch ispLEVER Path to isp TOOLS installation tree FOUNDRY Bal Generate ORCA Preference File H Session Settings F Schematic viewer Back annotation netlist format C Verilog EDIF f WHOL
111. Block SelectRAM cannot be implemented using Distributed SelectRAM 9 8 Precision Synthesis Installation Guide 2003c Update March 2004 Designing with Xilinx Handling Xilinx Design Issues Mapping Single Port RAM to Block RAM Figure 9 6 shows the recommended VHDL style for inferring a single port RAM This RAM is mapped to Block RAM unless you set the block_ram attribute on the array signal to false Figure 9 6 Inferring Xilinx Single Port RAM from VHDL library IEEE use JTREF std_locic 1164 alLl use IEEE std logic unsigned all entity sync_ram_singleport is generic data_width natural addr_width natural port clk i in std logic we ain std logic addr in std logic vector addr width 1 downto 0 data _ in in std logic vector data_width 1 downto 0 data out out std logic vector data_width 1 downto 0 7 end sync_ram_singleport architecture rtl of sync_ram_singleport is type mem type is array 2 addr_width downto 0 of std_logic_vector data_width 1 downto 0 Signal mem mem_type Signal addr_reg std_logic_vector addr_width 1 downto 0 attribute block _ram boolean attribute block_ram of mem signal is true begin Singleport process clk begin if clk event and clk 1 then if we 1 then mem conv_integer addr lt data_in end if 3 addr_reg lt addr end if end process singleport data_out lt mem conv_integer addr_reg end rtl Precision Syn
112. Calibre Interactive Calibre MDPview Calibre xRC CAM Station Capital Capital Analysis Capital Archive Capital Bridges Capital Documents Capital H Capital H the complete desktop engineer Capital Harness Capital Harness Systems Capital Insight Capital Integration Capital Manager Capital Manufacture Capital Support Capital Systems Capture Station Celaro Cell Builder Cell Station CellPloor CellGen CellGraph Cell Place CellPower CellRoute Centricity CEOC Chase X Check Mate CHEOS Chip Station ChipGraph ChipLister Circuit PathFinder Co Veri fication Environment COLsim Code lab CommLib CommLib BMC Concurrent Design Environment Connectivity Dataport Continuum Continuum Power Analyst Core Alliance CoreBIST Core Builder Core Factory CTI ntegrator DataCentric Model DataFusion Datapath Data Solvent BUG Debug Detective DC Analyzer Deltacore DeltaV Design Architect Design Architect 1C Design Architect Elite Design Capture Design Exchange Design Manager Design Station DesignBook Design View DesktopASIC Destination PCB Destiny RE DPTAdvisor DPTArchitect DFTInsight DMS Xchange DxAnalog DxDataBook DxDesigner DxLibraryStudio DxParts Dx PDF Dx ViewOnly Dx VariantManager Direct System Verification DSW Documentation Station DSS Decision Support System Dx Analog Dx DataManager Dx Designer Dx Enterprise for Agile DxMatrix Dx ViewDraw ESLcable EDA Tech ForumEDT
113. D RIGHTS NOTICE Software was developed entirely at private expense and is commercial computer software provided with RESTRICTED RIGHTS Use duplication or disclosure by the U S Government or a U S Government subcontractor is subject to the restrictions set forth in the license agreement under which Software was obtained pursuant to DFARS 227 7202 3 a or as set forth in subparagraphs c 1 and 2 of the Commercial Computer Software Restricted Rights clause at FAR 52 227 19 as applicable Contractor manufacturer is Mentor Graphics Corporation 8005 SW Boeckman Road Wilsonville Oregon 97070 7777 USA THIRD PARTY BENEFICIARY For any Software under this Agreement licensed by Mentor Graphics from Microsoft or other licensors Microsoft or the applicable licensor is a third party beneficiary of this Agreement with the right to enforce the obligations set forth in this Agreement AUDIT RIGHTS With reasonable prior notice Mentor Graphics shall have the right to audit during your normal business hours all records and accounts as may contain information regarding your compliance with the terms of this Agreement Mentor Graphics shall keep in confidence all information gained as a result of any audit Mentor Graphics shall only use or disclose such information as necessary to enforce its rights under this Agreement CONTROLLING LAW AND JURISDICTION THIS AGREEMENT SHALL BE GOVERNED BY AND CONSTRUED UNDER THE LAWS OF OREGON USA IF YOU ARE LOCATED IN NO
114. DC get_clocks SDC get_designs get_false_paths get_lib_cells SDC 3 70 Precision Synthesis Installation Guide 2003c Update March 2004 Commands get_multicycle_paths get_multicycle_paths Return a list of previously defined multicycle paths Example get_multicycle_ paths gt temp sdc Syntax get_multicycle paths lt patterns gt lt Dal lerns Description The get_multicycle_paths command returns a list of previously defined multicycle paths This command is useful to generate a temporary constraint SDC files for what if scenarios during static timing analysis Related Commands get_cells SDC get_lib_cells SDC get_clocks SDC get_lib_pins SDC get_designs get_nets SDC get_false_paths get_path_definition_set get_lib_cells SDC get_ports SDC get_lib_cells SDC Precision Synthesis Installation Guide 2003c Update 3 71 March 2004 get_nets SDC Commands get_nets SDC Return a list of hierarchical net pathnames Example get_nets gt foreach net get_nets hier gt set conns expr llength list_connection hier net net 1 J gt if 1 expr Sconms gt 16 4 gt puts Net net gt puts Fanocur scons gt puts Driver list_connection dir DRIVER hier net Ser gt gt Net sys_clk_int Fanout 321 Driver xcv2 BUFG Syntax get_nets lt patterns gt Dal lerns Description The get_nets co
115. DC reference man pages If a path satisfies multiple timing exceptions the following rules are used in order to determine which exceptions take effect 1 If both exceptions are set_false_paths there 1s no conflict Precision Synthesis Installation Guide 2003c Update 3 193 March 2004 set_min_delay SDC Commands 2 If one exception is a set_max_delay and the other is set_min_delay there is no conflict 3 If one exception is a set_multicycle_path hold and the other is set_multicycle_path setup there is no conflict 4 If one exception is a set_false_path and the other 1s not the set_false_path takes precedence 5 If one exception is a set_min_delay and the other is not the set_min_delay takes precedence 6 If one exception is a set_min_delay and the other is not the set_min_delay takes precedence 7 If one exception has a from pin or from cell and the other does not the former takes precedence 8 If one exception has a to pin or to cell and the other does not the former takes precedence 9 If one exception has any through points and the other does not the former takes precedence 10 The exception with the more restrictive constraint then takes precedence For set_min_delay and set_multicycle_path setup this is the constraint with the lower value For set_min_delay and set_multicycle_path hold itis the constraint with the higher value Related Commands set_false_path SDC set_multicycle_pa
116. DRA_INT lt ADDRA ADDRB_INT lt ADDRB END IF END PROCESS DOA lt mem conv_integer ADDRA_INT DOB lt mem conv_integer ADDRB_INT end rtl 9 16 Precision Synthesis Installation Guide 2003c Update1 March 2004 Designing with Xilinx Handling Xilinx Design Issues Figure 9 14 illustrates a RAM that is driven by different clocks Port A is used to both read and write with the WRITE_FIRST mode inferred Port B is used for read operations only Figure 9 14 Inferring WRITE_FIRST Mode Two Clocks library LEER use IEBEEE std_logic_1164 all use IEBEE std_logic_unsigned all entity V2RAM is port DOA out std logic vector 3 downto 0 DIA in std_logic_vector 3 downto 0 DOB out std logic vector 3 downto 0 ADDRA gt am std logic vector 12 downto Uj ADDRB gt in std logic vector 12 downto 0 WEA in std_logic CLRKA r in scd logic CLKB lt an std logig 7 end V2RAM architecture rtl of V2RAM is type mem_type is array 8191 downto 0 of STD_LOGIC_VECTOR 3 downto 0 Signal mem mem_type begin PROCESS CLKA BEGIN IF CLKA EVENT AND CLKA 1 THEN IF WEA 1 THEN DOA lt DIA mem conv_integer ADDRA lt DIA ELSE DOA lt mem conv_integer ADDRA END IF END IF END PROCESS PROCESS CLKB BEGIN IF CLKB EVENT AND CLKB 1 THEN DOB lt mem conv_integer ADDRB END IF END PROCESS end rtl Precision Synthesis Installation Guide 2003c Update1 March 2004
117. Design Constraint file in the input_file_list This file will contain set_attribute commands that set attributes on design objects Set attributes on objects in the VHDL or Verilog design source code You will typically select this method when you know that the attribute will always be there and is unlikely to change Related Commands report_area report_net report_library report_timing report_missing_constraints 3 136 Precision Synthesis Installation Guide 2003c Update March 2004 Commands report_design_impl_list report_design_impl list Returns a list of design implementations Example report_design_impl_list This command returns a list of all implementations in the design Syntax report_design_impl_list count active Options count Returns the number of implementations in the current project active Returns the name of the active implementation Description The report_design_impl_list command returns the name of each implementation in the current project including a comment line that may be associated with an implementation Related Commands setup_design impl Precision Synthesis Installation Guide 2003c Update 3 137 March 2004 report_input_file_list report_input_file_ list Return a list of the current input files Example report input iile list count Syntax report_input_file_list count Options count Commands Returns the number of files in the input_file
118. Designing with Actel Devices Handling Actel Design Issues Handling RadHard Designs Precision maps radiation hardened circuitry use C module pairs to implement flip flops or TMR circuitry using either S or C modules for even greater tolerance to increased radiation environments Based on previous characterizations of their devices heavy ion response Actel recommends three techniques for implementing the logic of sequential elements in radiation hardened FPGAs Combinatorial Combinatorial C C Triple Module Redundancy TMR and Triple Module Redundant C C TMR_CC Combinatorial Combinatorial C C provides a way to avoid using the radiation soft S module flip flop by combining two combinatorial cells with feedback Triple Module Redundancy TMR or triple voting is a register implementation technique whereby each register is implemented by three flip flops or latches that vote to determine the true state of the register Triple Module Redundant C C TMR_CC is also a triple module redundancy technique where each voting register 1s composed of combinatorial cells with feedback instead of S module flip flop or latch primitives In order to create a radiation hardened implementation you can set a radhardmethod attribute either on the reg signal being driven by the flop the flop instantiation itself or on an entire module instantiation If you set this attribute in your HDL code apply it to the signal If you s
119. Devices Up ON d ri aes 8 19 ACELEA Dorice SUpPOrICU sisisi rerehane EE EEEE ase anees 8 19 MAX Panuiy Doritos SOPOTU screena re eee 8 20 Chapter 9 Designing with Xilinx Handling Xilinx Design ISSUES sssssssssesssssssssnsisssssssssnrrussssssanirrstsssaranertetsrsareatitirsssasorerseissssoss 9 1 Maru E OE E S E eter tat Mere ear corre ey 9 1 kenra Ua O E ANA E ey A E EN E T EE E TTO EE ETEN 9 2 Including Xilinx Coregen Generated Modules neneessseeenesessssssesseresssssssssrersesssssssseeereessss 9 3 POL Reristear to IO Ba ren dacoecnanrersnteassiarcennininecss k p RAAEN Siaina E ISOPEN Ann Eiaa 9 8 AEN mOn NDE E nE EEEE E 9 8 ER Pa I a E eoaminteecenins 9 31 Precision Synthesis Installation Guide 2003c Update 1 Ix March 2004 Table of Contents Table of Contents cont Pils Post PFlace and Koute Analysis icenticetcneecisiviedertereniniinrneeneee 9 32 Seting Ailn ISE Place and Route OPHONS cna sisccrrscarsssonunscunransusacnancasdnctneiasiadesceeiiabundinnnens 9 33 Seinna Ailn ESE Constraint File OOS ssissicsatcninriccrnsarde ieee EIEEE E 9 35 Pe e eo Eai ie i E E IE EE A ENS I AEA EE T 9 36 yee Po Le es S e Beene peeenn ete terrae tee i cert ot mmercr Unt neon ant ren teen rettcnn ent eeertee tT 9 36 Me recess tapas etcesesancnctese te isicontdis anne eteissricwesiee arens 9 37 Ro lates Clog Blok g ior get jn t 6 ig lcs Renee nnn a een en are men ater en rte Tourer tenneett er cmitTe Tree mny re tern ne tran eny tenn 9 38 bae Ab
120. E OP eee ET E ES E NEE EA EE EEE TE E 3 153 a a E E E 3 154 E i MANEI I Y VEIRA AE AREA A E A E E O ee EE A E 3 159 saro paN denon DOl ensidis nnie E a EEE EETA 3 160 Da E o E SE EEEE E TI EA E SS EET EN A E EE 3 161 e a o O Ea a E 3 162 DE ak EEE 3 163 e E a E i EEE EAE P EEE PE EEEE EEEE AAS EELA AS EEE 3 165 el MBE 186 QE ead on ae S DE aa EE 3 167 sol clock ACCT NCE bel Ge eee eee Reem ners tered aeettmin EEE 3 169 oie ole Mg LTE TO soe 10 Lg Gu ke Oe rene nn en eater teen pcre e eter etre y ener rene eE ye trrrn etatrertre re nrrtrers terry ter 3 171 To E EEE EAI E E AEA A E A A 3 173 oe E T a oe ne meee nO wet Seen ee enon T mney Resets ea eer ee 3 178 Br sree rete er etern ee etter ieee 3 179 sok mmp ODOT CRE Pee RCT Tee RT EEEE T 3 180 BE E a E D B E AAE NAA VNA ena cee 3 181 A a EE EE EAE ARA ten een 3 185 E T E N 3 186 a RS ol Oh ge a eE T tar rier Tir ce 3 188 oe MBL CAIN BLE ATAT 3 191 e a era EE 3 192 Precision Synthesis Installation Guide 2003c Update1 March 2004 Table of Contents Table of Contents cont Se MUSLIN LOG a ode sie etn Gey Deen tee keene E E E erent E re EE Tee Meme er tr ret renee 3 195 ovaries dita en EE E EET ewan A E 3 200 o i noe ne i E EEIE EERE nes O A EP EOE AEAN A E ENE IA AEE TE 3 203 BE a rE ER E 3 204 e O God Gs Memengrt rene nner tamer eer ean yen mate meh ner ote rst Tenn irr rrr air sewn m carte at smn tm 3 205 wo MR oc a 2 eee a eee Oe eee eee eee eee ers Ete ee ee ee
121. EX 20K Devices Supported EP20K100 C144 QC208 QC240 FC324 BC356 EP20K200 RC208 RC240 RI240 BC356 FC484 EP20K400 BC652 BI652 FC672 APEX 20K Speed Grades Default Speed Grade 1 Speed Grades supported 3 2 1 1X 2X 1V I XV 2V 2XV 3V FLEX 10K Devices Supported FLEX 10K Family Default Speed Grade 2 Speed Grades supported 1 2 3 4 Devices Supported EPF10K10 LC84 TC144 QC208 EPF10K20 C144 RC208 RC240 EPF10K30 RC208 RC240 BC356 EPF10K40 RC208 RC240 EPF10K50 RC240 BC356 GC403 EPF10K70 RC240 GC503 EEPF10K 100 C503 FLEX 10KA Family Default Speed Grade 2 Speed Grades supported 1 2 3 4 Devices Supported Precision Synthesis Installation Guide 2003c Update 8 17 March 2004 Altera Devices Supported Designing with Altera Devices EPFIOKIOA C100 TC144 QC208 FC256 EPFIOK30A C144 QC208 QC240 FC256 BC356 FC484 EPF10K50V RC240 RI240 QC240 QI240 BC356 BI256 FC484 EPF10K100A RC240 BC356 FC484 BC600 EPF10K130V C599 BC600 EPF10K250A C599 BC600 FLEX 10KB Family Default Speed Grade 11 Speed Grades supported 1 2 3 4 Devices Supported EPF10K100B QC240 QC208 FLEX 10KE Family Default Speed Grade 1 Speed Grades supported 1 2 3 1X 2X Devices Supported EPF10K30E C144 TI144 QC208 QI208 FC256 FI256 FC484 EPF10K50E C144 TI144 QC208 QC240 QI240 FC256 FI256 FC484 EPF10K50S C144 QC208 QI208 QC240 FC256 BC356 FC484 F1484 EPF10K100E QC208 QI208 QC240 QI240 FC256 FI256 BC356
122. F netlist file along with a MAX PLUS II Configuration File To run the automated Place and Route flow just click the Run MAX PLUS IT icon in the MAX PLUS II Tool Bar MAX PLUS II uses the current implementation directory as the project directory After the design is compiled you may invoke the MAX PLUS II GUI 8 4 Precision Synthesis Installation Guide 2003c Update1 March 2004 Designing with Altera Devices Altera MAX PLUS II Integration manually and open the project From that point you can view reports run analysis tools and manually drive the physical implementation to completion Figure 8 3 Running the Altera MAX PLUS II Environment tt simplemath Mentor Graphics Precision Physical Synthesis Design Center Pa File View Tools Window Help ae ije Altera MAX 9000 EPMS400LC84 15 Frequency 200 MHZ Project Files Design Hierarchy El Project simplemath simplemath main_XRTL Click to automatically WARNEN Taa Place and Route plemath hd Infos my H E Constraint Files e math constraints sde Click to launch the T MAX PLUS II GUI ae s iles Lad Log File Infos 7 FEM RTL Schematic OO B dan EBJ Technology Schematic o m E e 3 0 PEAS edi RANE Re Area Report fk ay FGS 03 Sy Outputs RP Timing violation Report H I yi7 Rei Constraints Report H E Nets i simplemath edf H EI Instances AE Altera MAX PLUS II Config f Es Transcript P4 Design Center Input Directory 1 4
123. F1020C 5 Frequency 100 MHZ Design a a AREE E F pseudorandom frtl XRTLI gt i 4 dom impl H e Clocks E e Wevlis UL as tepi pseudorandom yhd Constraint Files H Instances S 5 pseudorandom_constra ga Blocks cel E Script Files Eb 10 fdlatrg_25 Run Gluartus I oe Output Files a Lid Log File Warnings 1 f G 8 8 Precision Synthesis Installation Guide 2003c Update March 2004 Designing with Altera Devices Altera Quartus II Integration Quartus Il v2 X and v3 0 Support Precision supports both the v2 X and v3 0 releases of Quartus II By default Precision generates a Quartus II project file that is compatible with both v2 X and v3 0 Quartus II v3 0 is compatible with the old v2 X project files Quartus I v3 0 uses a new set of modular place route tools and a new constraint file format The following command can be used to inform Precision to create a project file that can only be read by Quartus II v3 0 setup_place_and_route flow Quartus II 3 0 This command creates a project file that can calls the modular place route tools within Quartus II v3 0 and add constraints in the new format If you need to use Quartus I v3 0 you must execute this command prior to running the integrated place route within Precision You can also use the the Precision generated project file in the new Quartus II v3 0 batch shell guartus_shell t lt project_file gt Setting Altera Quartus II Options As s
124. FC484 FI484 EPF10K130E QC240 QI240 BC356 BI356 FC484 FI484 FC672 BC600 EPF10K200E C599 BC600 FC672 EPF10K200E RC240 BC356 BI356 FC484 BC600 FC672 FI672 P ah co Precision Synthesis Installation Guide 2003c Update1 March 2004 Designing with Altera Devices Altera Devices Supported FLEX 6000 8000 Devices Supported FLEX 6000 Family Devices Supported C100 TI100 TC144 C144 T1144 QC208 QI208 QC240 BC256 C100 TI100 TC144 T1144 QC208 QI208 FC100 FC256 C144 QC208 QI208 QC240 BC256 BI256 FC256 FI256 ACEX Devices Supported EP1K10 C100 TI100 TC144 T1144 FC256 FI256 QC208 Precision Synthesis Installation Guide 2003c Update 8 19 March 2004 Altera Devices Supported Designing with Altera Devices C144 TI144 QC208 FC256 FI256 C144 QC208 QI208 FC256 FI256 FC484 FI484 QC208 QI208 FC256 FI256 FC484 FI484 a iol NININA Ch Uo Gy Go MAX Family Devices Supported MAX 3000A Family Default Speed Grade 10 Speed Grades supported 4 5 6 7 10 Devices Supported EPM3032A LC44 TC44 EPM3064A LC44 TC44 TC100 EPM3128A C100 TC144 EPM3256A C144 QC208 EPM3512A QC208 FC256 MAX 7000 Family Default Speed Grade 10 Speed Grades supported 6 7 10 12 15 15T 20 Devices Supported EPM7032 LC44 LI44 QC44 QI44 TC44 T144 VLC44 VTC44 VTI44 EPM7064 LC44 LI44 TC44 LC68 LI68 LC84 LI84 QC100 QI100 EPM7096 LC68 LI68 LC84 LI84 QC100 QI100 MAX 7000A Family D
125. Find only the inputs with respect to the specified clock s Description The find_inputs command is a reporting command that locates inputs that drive logic to non clock pins on sequential elements You can limit the return list by specifying one or more defined clocks previously specified with the create_clock command Using the clock switch informs Precision Synthesis to only return input ports that drive logic on the non clock pins of sequential elements that are clocked by the defined clock Related Commands find find_outputs find_clocks Precision Synthesis Installation Guide 2003c Update 3 59 March 2004 find_outputs Commands find outputs Find all of the outputs in the current design Example find outputs clock clkA cikB Syntax find outputs clock lt clock_names gt lt clock_names gt Options clock lt clock_names gt Find only the outputs with respect to the specified clock s Description The find_outputs command is a reporting command that locates outputs that are driven by logic from the outputs of sequential elements You can limit the return list by specifying one or more defined clocks previously specified with the create_clock command Using the clock switch informs Precision Synthesis to only return output ports that are driven by logic on the output of sequential elements that are clocked by the defined clock Related Commands find find_inputs find_clocks 3 60 Precision
126. Generate BitGen File Do not run commands Cancel Apply Help Lattice Logo If your web browser is active click on this logo to bring up the Lattice website home page http www latticesemi com Path to the ispTOOLS installation tree Specify the pathname to the ispTOOLS installation tree for example C apps ispTOOLS 7 6 Precision Synthesis Installation Guide 2003c Updatet March 2004 Designing with Lattice Devices Lattice ORCA Devices Supported Do not run commands This switch is primarily used for debugging the Precision script that drives the ispLEVER ORCA tools The commands in the script are echoed to the Precision Transcript window without the commands actually being executed by the implementation tools Back annotation netlist format Specify Verilog EDIF or VHDL for the annotation netlist format Lattice ORCA Devices Supported ORCA 2CA Family ORCA 2TA Family Lattice ORCA 2TA Family Default Speed Grade 4 Speed Grades supported 2 3 4 5 Precision Synthesis Installation Guide 2003c Update 7 7 March 2004 Lattice ORCA Devices Supported Designing with Lattice Devices Devices Supported or2t04a M84 T100 T144 J160 S208 or2t06a M84 T100 T144 J160 S208 S240 B256 or2t08a M84 J160 S208 S240 B256 or2tl 0a M84 J160 S208 S240 B256 B352 or2t 2a M84 S208 S240 B256 B352 or2tl5a M84 S208 S240 B256 B352 SB432 or2t26a PS208 PS240 B352 SB432 speed grades 6 and 7 also supported or2t40a PS208 PS24
127. I 125LB272 125LB272I 125LF256 125LF2561 165LF256 165LB272 80LF256I1 80LB2721 80LB272I 80LB388I 80LF256I 80LF388I 1O00LB272 1OOLB272I 1OOLB380 1OOLB380I 1OOLF256 1LOOLF256I LOOLT128I LOOLF388 1LOOLF388I 125LB272 125LB272I 125LF256 125LF256 125LF388 125LF388I 125LB388 125LB388I 155LB172 155LB388 155LF256 155LF388 ispLSIS5512VE 1O00LB388 LOOLB388I 1OOLB272 100LB256 Packages BGA TQFP 7 10 Precision Synthesis Installation Guide 2003c Updatet March 2004 Designing with Lattice Devices Lattice CPLD Devices Supported ispLSIS5000VE_UPS Devices ispLSISOOOVE_UPS Devices ispLSIS128VE 1OOLT128 UPS LOOLT128I UPS ispLSIS256VE 1O00LB272 UPS 100LB272I UPS 100LB256 UPS 1OOLB256I UPS 1OOLT128 UPS LOOLT128I UPS ispLSIS384VE 100LB272 UPS 100LB272I UPS 100LB256 UPS 1OOLB256I UPS ispLSIS5512VE 100LB388 UPS LOOLB388I UPS 100LB272 UPS 100LB256 UPS Packages BGA TQFP isomach4000B Devices ispmach4000B Devices spmach40O0BDeviess OO Packages QFP caBGA fpBGA ispmach4000C Devices ispmach4000C Devices LC4032C 5T44C 75T48C LC4064C ST44C 75T48C 75T49C 75T100C 75C100C LC4128C SC49C 75T100C 75C100C LC4256C ST1O0C 75C100C 75T176C 75F256C Precision Synthesis Installation Guide 2003c Update 7 11 March 2004 Lattice CPLD Devices Supported Designing with Lattice Devices LC4384C ST176C 75F256C LC45 12C ST176C 75F256C Packages
128. IN IF CLK EVENT AND CLK 1 THEN IF WEA 1 THEN mem conv_integer ADDRA lt DIA END IF ADDRA_INT lt ADDRA DOB lt mem conv_integer ADDRB END IF END PROCESS DOA lt mem conv_integer ADDRA_INT end rtl Precision Synthesis Installation Guide 2003c Update 1 9 15 March 2004 Handling Xilinx Design Issues Designing with Xilinx The code in Figure 9 13 shows a third style of RAM where both the A and B addresses are explicitly registered and the read operations are carried on by the concurrent signal assignment statements that follow the process Both ports are driven by the same clock Figure 9 13 Inferring WRITE_FIRST Mode One Clock Style 3 library IEEE use IEEFF std_logic_1164 all use IEEEF std_logic_unsigned all entity V2RAM is port DOA out std_logic_vector 3 downto 0 DIA in std_logic_vector 3 downto 0 DOB out std_logic_vector 3 downto 0 ADDRA in std_logic_vector 12 downto 0 ADDRB in std_logic_vector 12 downto 0 WEA 2 in std logic CLK i std logic a end V2RAM architecture rtl of V2RAM is Component declarations Signal declarations type mem_type is array 8191 downto 0 of STD_LOGIC_VECTOR 3 downto 0 signal mem mem_type signal ADDRA_INT std logic vector 12 downto 0 signal ADDRB INT std logic veactor 12 downto 0 begin PROCESS CLK BEGIN IF CLK EVENT AND CLK 1 THEN IF WEA 1 THEN mem conv_integer ADDRA lt DIA END IF AD
129. If you omit this argument the help command displays a one line description of all commands Description The help command provides descriptions and usages of Precision Synthesis commands More Examples help create_clock This example produces a usage message for the create_clock command help file This example produces a usage message for all Precision Synthesis commands that end with the characters file such as add_input_file and remove_input_file Related Commands Precision Synthesis Installation Guide 2003c Update 3 87 March 2004 list_design Commands list_design Return a list of objects in the specified design libraries in the root cells in a library views in a cell etc Example list_design instances Syntax list_design lt list_of_designs gt ports nets clocks internal_clocks instances references direction lt port_direction gt hd1 short string lt list_of_designs gt Arguments lt list_of_designs gt Name of the library cell or view for which you want to retrieve a listing of the contents You can use absolute or relative object names and wildcards are accepted Object names are case sensitive If you omit this argument the list_design command returns a list of the contents of the design objects in the current design If lt list_of_designs gt indicates a view and you omit other arguments the 1ist_design command uses the instances argument
130. Input File List Precision will mark it as Exclude and pass it through to the active implementation directory The Xilinx PAR tools will pick it up as the Leverage NCD file bits Generates a Xilinx bit file that programs the target Xilinx device To specify true use the syntax bits 1 The default is 0 bitgen_cmd_file lt inputfile gt Specifies a command file that will be executed by BitGen This command file can be included in the Input File List Precision will mark the file as exclude and pass it through to the active implementation directory enable_auto_offset_relaxation If an input constraint on a port is too tight place and route may fail This option allows Precision Synthesis to automatically relax such a constraint in order to let P amp R finish A warning message is written to the transcript when a constraint is relaxed The default is 1 true Related Commands place_and_route setup_design 3 226 Precision Synthesis Installation Guide 2003c Update March 2004 Commands synthesize synthesize Synthesize the current in memory design Example synthesize Syntax synthesize Description The synthesize command creates a technology mapped design from the currently compiled in memory RTL data base and writes the appropriate output files to the active implementation directory in the working directory There are no arguments or options to this command The output files that are written
131. LT44 180LT44 1OOLT128 135LT128 180LT128 ispLSI2032VL 110LJ44 135LJ44 180LJ44 110LT44 135LT44 135LT44I 180LT44 LIOLT48 135LT48 180LT48 110LB49 135LB49 180LB49 1 14 Precision Synthesis Installation Guide 2003c Update March 2004 Designing with Lattice Devices Lattice CPLD Devices Supported ispLSI2064VL 1OOLJ44 135LJ44 165LJ44 1OOLT100 135LT100 135LT100I 165LT100 100LB100 135LB100 165LB100 ispLSI2Z096VL 1OOLT128 135LT128 135LT128I 165LT128 ispLSI2128VL LOOLT100 135LT100 135LT100I ISOLT100 100LB100 135LB100 150LB100 100LQ160 135LQ160 1I50LQ160 1OOLT176 135LT176 135LT176I ISOLT176 100LB208 135LB208 150LB208 ispLSI2192VL 1OOLT128 135LT128 1ISOLT128 ispLSI2032V 60LJ44 60LJ441 80LJ44 100LJ44 H0LT44 60LT44I 80LT44 1OOLT44 ispLSI2032VE 110LJ44 135LJ44 180LJ44 200LJ44 225LJ44 L1OLT44 135LT44 180LT44 180LT44I 200LT44 225LT44 110LT48 135LT48 180LT48 200LT48 225LT48 110LB49 135LB49 180LB49 200LB49 225LB49 ispLSI2064V 6H0LJ44 80LJ44 100LJ44 H0LT44 60LT44I 80LT44 1OOLT44 6H0LIJ84 80LJ84 LOOLJ84 H0LT100 6OLTIOOI 80LT100 1OOLT100 ispLSI2064VE 1OOLJ44 135LJ44 200LJ44 1OOLT44 135LT44 135LT44I 200LT44 1OOLT100 135LT100 135LT100I1 200LT100 1O0LB100 135LB100 200LB 100 a 60LQ128 80LQ128 60LT128 6OLT128I 80LT128 ispLSI2096VE 1OOLT128 100LT128 135LT128 135LT1281 200LT128 135LT128I 100LT128 135LT128 135LT1281 200LT128 ispLSI2128V 60LT100
132. Precision Synthesis Reference Manual 2003c Update March 2004 Copyright Mentor Graphics Corporation 2002 2004 All rights reserved This document contains information that is proprietary to Mentor Graphics Corporation The original recipient of this document may duplicate this document in whole or in part for internal business purposes only provided that this entire notice appears in all copies In duplicating any part of this document the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information End User License Agreement Trademark Information This document is for information and instruction purposes Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice and the reader should in all cases consult Mentor Graphics to determine whether any changes have been made The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in written agreements between Mentor Graphics and its customers No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OR MERCHANTABILITY AND
133. Quartus II from Precision 6 1 Setting Altera MAX PLUS II Options 8 6 array_pin_number VHDL only 2 1 2 4 2 9 async_reg Xilinx 2 1 2 4 2 10 Attributes 1 2 2 1 Precision Synthesis Installation Guide 2003c Update March 2004 block_ram Xilinx 2 1 inff 2 2 input_delay Obsolete 2 2 Mapping other Attributes to Precision 2 9 max_fanout 2 2 Pre defined User Attributes 2 9 Specifying in Verilog 2 7 Specifying in VHDL 2 6 Specifying on the command line or script 2 8 auto_write 3 32 B Back annotation netlist format 6 4 block_ram Xilinx 2 4 2 10 Bubble Tristates 4 10 buffer_sig 2 1 2 5 2 11 C CLI Commands allocate 3 54 3 163 Clock definitions root 3 41 close_project 3 34 close_results_ dir 3 35 Command Line Description 1 4 Command Line Help 1 4 Command Syntax 1 5 Commands Command Summary Table 3 1 Constraint Commands Table 3 9 Functional Command List Table 3 8 Object Access Commands Table 3 11 Report Commands Table 3 10 SDC Commands Table 3 12 3 14 compile 3 36 Compiling a design 4 1 Constant Propagation 4 7 Constraining for Synthesis and Layout 6 9 Index 1 Index Index cont copy_impl 3 37 correlate_reports 3 39 create_path_definition_set 3 44 Critical Paths 4 12 current_design SDC 3 45 current_instance SDC 3 46 D dedicated_mult 2 2 2 12 delete_impl 3 47 delete_path_definition_set 3 48 Design Analyzing the Design 4 2 Elaborating the De
134. RIMITIVES library This library contains the simple generic cells that are used during compile Technology libraries also use cells from the PRIMITIVES library to define the functionality of technology specific cells OPERATORS The OPERATORS library contains the blackbox cells of arithmetic and relational operators that were inferred during compile The cell names in the OPERATORS library typically refer to the type of operator and the bit width of the input and output ports e g ADD_8u_8u_0 implies an 8 bit unsigned adder with no carry in work This library contains the design implementation Although the name of the library is typically work you can set the library name with the add_input_file command During compile Precision Synthesis typically creates two or more additional libraries OPERATORS and work technology During synthesize Precision Synthesis loads the technology library Each cell in the technology library contains the pin names pin capacitance size and timing information for each cell in the library Although you can load multiple technology libraries you can only target one technology for core logic cells and optionally a different library for IO cells Precision Synthesis Installation Guide 2003c Update 3 69 March 2004 get_libs SDC Commands Related Commands get_lib_cells SDC get_lib_pins SDC get_multicycle_paths get_nets SDC get_path_definition_set get_ports SDC get_cells S
135. ROM You can implement ROM behavior in the HDL source code with CASE statements or you can specify the ROM as a table Precision RTL Synthesis infers both synchronous and asynchronous ROM The circuit is first mapped to technology independent LPM ROM module then to an EAB Embedded Array Block if possible or to a combination of elements in the LEs By default the minimum size of a detected ROM 1s 64 Precision Synthesis Installation Guide 2003c Update 8 3 March 2004 Altera MAX PLUS II Integration Designing with Altera Devices LPM Mapping The detected ROM network is mapped to a parameterized library module as shown in the following table uted ished The target Altera place and route tool then maps the LPM ROM to the appropriate logic element s in the technology ROM Data File Precision RTL Synthesis generates a ROM data file that contains the ROM programming data as part of the LPM ROM instantiation This data is in the Intel Hex Object File format which is supported by Altera tools The following example is for a 32x5 ROM 7020000040000fa 08000000030f1 fOf030T1 f1 f68 08000800071f001f0107011f83 0800100010701 0f071f0f0f6e 08001 8000f07070f1 fOf0f1 f58 00000001 ff Altera MAX PLUS II Integration As shown in Figure 8 3 the MAX PLUS II environment is integrated into the Precision RTL Synthesis environment After Synthesis the technology mapped design is written to the current implementation directory as an EDI
136. RTH OR SOUTH AMERICA AND THE LAWS OF IRELAND IF YOU ARE LOCATED OUTSIDE OF NORTH AND SOUTH AMERICA All disputes arising out of or in relation to this Agreement shall be submitted to the exclusive jurisdiction of Dublin Ireland when the laws of Ireland apply or Wilsonville Oregon when the laws of Oregon apply This section shall not restrict Mentor Graphics right to bring an action against you in the jurisdiction where your place of business is located SEVERABILITY If any provision of this Agreement is held by a court of competent jurisdiction to be void invalid unenforceable or illegal such provision shall be severed from this Agreement and the remaining provisions will remain in full force and effect MISCELLANEOUS This Agreement contains the parties entire understanding relating to its subject matter and supersedes all prior or contemporaneous agreements including but not limited to any purchase order terms and conditions except valid license agreements related to the subject matter of this Agreement which are physically signed by you and an authorized agent of Mentor Graphics either referenced in the purchase order or otherwise governing this subject matter This Agreement may only be modified in writing by authorized representatives of the parties Waiver of terms or excuse of breach must be in writing and shall not constitute subsequent consent waiver or excuse The prevailing party in any legal action regarding the subject matt
137. RTL Synthesis Figure 6 4 Design Constraints File for Synthesis with Precision Synthesis HHH EH HHH HH HHH EH EH Clocks HHH EH HHH HH HHH EH EH create_clock clkx16 name clkx16 period 10 00 waveform 0 00 5 00 create_clock write name write period 100 00 waveform 0 00 50 00 create_clock reg_txclk U0 Q name reg_txclk out period 20 00 waveform 0 00 10 00 create_clock reg_rxclk U0 Q name reg_rxclk out period 20 00 waveform 0 00 10 00 itt tHe tH HH HE OEE EH EEE HE False Paths Multicycles HHH EH HE HE HE HEH EH EH EH HE Ht EH FH set_max_delay 10 00 to framingerr set_max_delay 10 00 to tx set_max_delay 10 00 to overrun set_max_delay 10 00 to txrdy set_max_delay 10 00 to parityerr set_max_delay 10 00 to rxrdy 6 10 Precision Synthesis Installation Guide 2003c Update March 2004 Designing with Actel Devices Supported Actel Devices Design Constraints File for Layout HH t HH HH HHH HH Ht EH FH Clocks HH H HH Ht HH HH HH Ht EH FH create clock create clock Cre Cre ate clock ate clock clkx16 period 10 00 waveform 0 00 5 00 write period 100 00 waveform 0 00 50 00 reg_txclk U0 Q period 20 00 waveform 0 00 10 00 reg_rxclk U0 Q period 20 00 waveform 0 00 10 00 HEH HEE EHH EH EEE EH HE EE HE EE EH False Paths Multicycles set set set set set set
138. Return a list of hierarchical net pathnames get_path_definition_set Return a list of instance pins get_ports SDC Return a list of hierarchical port pathnames get_project_impls Return a list of implementations in the current project get_project_name Return the name of the current project get_results_dir Return the path of the current results directory get_selected Return a list of objects that are currently selected get_version Returns the current product version number Group a list of instances into one instance of a new view NOTE This is an advanced command that should group only be used from a script after all constraints have been applied to the in memory design help Give help on commands list_design Return a list of objects in the specified design load_project Deprecated Actually calls the open_project command logfile Configure the logfile name and location Precision Synthesis Installation Guide 2003c Update 3 3 March 2004 Command Summary Commands Table 3 1 Alphabetical Command Summary continued move_input_file Move a file either up or down in the input_file_list Create and activate a new implementation in the current project new_impl new_project Create and open a new project Open_project Open an existing project Perform physical timing optimization and placement improvement on a design physical_synthesis place_and_route Run the integrated place and route tools p
139. S Design Library Cell Library Ya Figure 4 2 Design Database The in memory netlist which is called a view within the database resides within a design library as part of the general design database as shown on the facing page These elements are defined as Libraries All design and technology information resides in a library A library can contain design data technology cells or primitive cells The primitive cell library contains a generic set of combinational and sequential logic cells that Leonardo uses in order to represent HDL descriptions as gate level networks Cells Within each library is a set of cells that represent either technology information for primitive and technology libraries or levels of design hierarchy A cell is a collection of views Views A view contains interface information and might also contain a netlist In summary the following objects are typically contained within a view and are used to represent netlists and hierarchies in a design Precision Synthesis Installation Guide 2003c Update 4 19 March 2004 Understanding the In Memory Design Data Model How Precision Compiles A view has ports nets and instances A port is a terminal of a view An instance is a pointer to a view A net is aconnection between ports and or port instances pointer to the port of the view under an instance 4 20 Precision Synthesis Installation Guide 2003c Update1 March 2004 Cha
140. Synchronously Written and Asynchronously Read Distributed Ram is inferred when port A is synchronously written but asynchronously read regardless of whether port B and C are synchronously or asynchronously read Precision Synthesis Installation Guide 2003c Update 9 25 March 2004 Handling Xilinx Design Issues Designing with Xilinx The Verilog code in Figure 9 23 uses a single write clock for Port A The read operation on all three ports is asynchronous Precision infers a set of dual port Distributed RAMs for port A and B and a set of dual port Distributed RAMs for port A and C Figure 9 23 Tri Port RAM Sync Write Async Read Async Read Async Read module swar_ar_ar wclk wen addrl addr2 addr3 outl out2 out3 datain input Write clock input Write enable input addri input addrz Input adds CouLpUL i OUE O tCpu t DUTA output DUC input i datain reg 7 mem 0 31 A 32 x 8 bit memory always posedge wclk begin if wen mem addrl datain end assign outi mem addrl assign out2 mem addr2 assign out3 mem addr3 endmodule Port A Synchronously Written and Read in WRITE FIRST Mode As explained on page page 9 13 Virtex II and Virtex II Pro Block SelectRAM is a True Dual Port memory and supports three possible write modes for each port The WRITE_FIRST write mode for Port A refers to the write mode where the location addressed is written first before it is read Th
141. T TEA 3 63 I OESIE A IEI ENNE IE IE NEEN E EAA EIA AEE os 3 64 Arl D 11 E EE EE E EAT AIEEE T E TETEE EEA ET TETE tee TETE 3 65 Por Dp MONON aieri EE 3 66 eR E oA Dg Gu E Oot E O EE N E EAEE EA E A A IE TEE EET 3 67 n DE Dn LE pr E R EE 3 68 aer ilo D a E la ani Terme cer nt rerr rey nem 3 69 ea aadi ac ras ere tse eine nee etnies 3 71 GM el a cs 1 D genet ne tent eet AA EEA Tense ts Ne een AE renner nr enn nme ce aren wr rete 3 72 ro E IEAA A A E E E 3 74 T cg Oe Ol a E ete E E EEE EAE 3 76 a ae a EA T E E E E E E E S AAT 3 78 E T a 19 8 aE E T rT nr nner yer ce 3 80 oe MBL ea e E 8 1 eee O anne E O ee E AE Sm ne eet renee ene Perc N 3 81 pecs an E E E E EENE eae 3 82 S TE AE E ETENE EEA E P AAE EA IE AEE TE O TET 3 83 oer Lol oa A E E 3 84 E LOSEER I AIENEA EI IEAA AAA diated PI TEPEE OEE A E A T PEE PN O E ATENE 3 85 2 ee cece peste gen EPEA E TECNA PENEAN TEELE VETRI A ANE ANET 3 87 Jak ga od EE AE ENAA ESE AEE E E EE AAE AE E EIEEE T A er 3 88 waa pa o re hane AE 3 91 P acacia E AAA EEE EAA AA EAE E A 3 92 OTe en E EA E EA O AEE AA EEE EET 3 94 Hea ge 12 e E E E E E E AE ar tte ern 3 95 eE 212 E E TEE A ESAE eee EI E E ATTE EE A A E A AI EATE TS 3 96 2 123 ME a T T 3 98 a E a E AEA TAR 3 99 De a O a A TEN E E AE EN R 3 101 E 01 PEATE EEEE ETETE E E A E E eee net EETA mre TOE EE TEE TEE AA 3 111 remove a neia EOE ETRE 3 114 Call E E 5 AEE EEEN A PERE AAEE EAT NEE TE A EE EEE EEEE EANES 3 116 GG ea E E E E
142. Verilog Example example module expr a b c outl out2 input 15 0 a b Cj output 15 0 outi out2 assign outl a b assign out2 b C pragma attribute expr dont touch true endmodule In this example the fastest Precision Synthesis modgen operator is used for the out 1 assignment Precision Synthesis Installation Guide 2003c Update 2 March 2004 How to Set Attributes Attributes Specifying Attributes on the Command Line or in scripts Sometimes it is desirable to avoid setting attributes in the HDL source files and instead set attributes by sourcing a Tcl script or typing a command directly from the Interactive Command Line Shell You can use the set_attribute command to add an attribute to an in memory design object and the remove_attribute command to remove an attribute You can use the following Tcl syntax for example if you do not want to modify your Verilog or VHDL code set_attribute lt obj_type gt lt obj_name gt name lt attribute_name gt value lt attribute value gt Interactive Command Line Shell Example set_attribute instance abc name noopt type boolean value TRUE remove_attribute instance abc name noopt where type is boolean string array etc Specifying Attributes using the design Switch When running the Precision tool you can specify whether you want attributes applied to the RTL design or to the gatelevel technology view Before synthesis the to
143. _list Description The report_input_file_list command returns a list of the files that are in the current input_file_list Status information is also provided such as the position of the file in the list the full file pathname the file type and the name of the work library into while the file will be compiled If you specify the count switch only the number of files in the input_file_list is returned Related Commands add_input_file move_input_file remove_input_file 3 138 set_input_file setup_design remove_design Precision Synthesis Installation Guide 2003c Update March 2004 Commands report_io_registers report_io_registers Returns a list of all ports in the top level of the design that were mapped to IOB registers Example report_io_registers Syntax report_io_ registers lt filename gt Options filename Writes the IOB mapping table to the named file Description The report_io_registers command returns a table of how Precision mapped any registers connected to the top level port in the design For each port the table lists the port direction and whether an register was moved into the IOB of the port If you do not specify the lt filename gt Precision writes the report to the transcript at the end of each synthesis run Related Commands report_area Precision Synthesis Installation Guide 2003c Update 3 139 March 2004 report_library Commands report_library Report information on
144. _memory_utilization Generate a report detailing the amount of memory being used by the tool report_missing_constraints report_technologies Generate a report listing technology libraries that are being used in the current design report_timing Run the PreciseTime Timing Analyzer and return information about the design save_impl Save the state of the active implementation to disk save_path_definition_sets Saves the in memory physical database to the active implementation directory save_physical Saves the in memory physical database to the active implementation directory save_project Obsolete This command has been replaced by the save_impl command Calls to save_project will actually execute the save_impl command select Select a list of objects set_attribute Create or set an attribute on the specified object s set_clock_latency SDC Specifies delay from pin where clock 1s defined to register clock pin set_clock_transition SDC Override the clock slew values from the library set_clock_uncertainty SDC Specify the source and destination clocks to calculate inter clock uncertainty between defined clocks set_false_path SDC Ignore slack values on the specified paths Precision Synthesis Installation Guide 2003c Update 3 5 March 2004 Command Summary Commands Table 3 1 Alphabetical Command Summary continued set_fanout_load SDC Limit the capacitance in library units that a net or port can drive
145. a property in the EDIF netlist Figure 8 1 Assigning a LogicLock Region to a Block Altera Strate 5 Frequency 80 MHZ Project Files Design Hierarchy E Design Filter_impl_1 LE Filter rtl S Input Files H E Clocks fil adder vhd H E Ports pan mult hd E E Wets Trace to Hierarchy pran Filter hd ely imetances Trace to HDL Source F Constraint Files Fy Blocks Set Attributes E Output Files 1 Select block H 4 mult i0 mult Don t Touch A Log File me led WI fe TO mult it mult Preserve Hiera 2 g RTL Schematic AO mult j RUE Paca iev T Constraints Report H mu ae Repent Tim Logie Loc k 3 Enter LogicLock region Select Attribute Name LUIZ LUCE Attribute alue malta OF Cancel How Memory Inferencing Works for Altera As explained on page 9 8 Precision RTL Synthesis detects a RAM or ROM from the style of the RTL code at a technology independent level then maps the element to a generic LPM module in the in memory RTL data base at Compile time If a RAM is detected the element is mapped to a RAM_DQ or RAM_IO module If a ROM is detected the element is mapped to a LPM ROM module The LPM Library of Parameterized Modules Standard is an extension of EDIF and is used to transfer technology independent netlists between Mentor Graphics EDA tools and Altera inplementation software During the technology mapping phase of synthesis Precision RTL Synthesis maps the generi
146. adders multipliers muxes When compiling HDL descriptions these operators are generated when needed In summary the following objects are typically contained within a view and are used to represent netlists and hierarchies in a design A view has ports nets and instances A port is a terminal of a view An instance is a pointer to a view 1 6 Precision Synthesis Installation Guide 2003c Update1 March 2004 Introduction The Design Data Model A net is aconnection between ports and or port instances pointer to the port of the view under an instance The following code example is a small VHDL description that represents a primitive AND function entity and2 is Ore ay Dko O70 Dii end and2 architecture contents of and2 is begin o lt a AND b end contents Precision Synthesis then creates a cell called and2 in the default library work The cell contains a view called contents The view contains three ports a b and o The view also contains an instance of a view in the Precision Synthesis PRIMITIVES library This is an instance of a primitive AND The name of the instance is created by Precision Synthesis The view also contains three nets a b and o connecting the instance to the ports of the view All objects libraries cells views ports nets and instances can contain attributes Precision Synthesis Installation Guide 2003c Update 1 7 March 2004 The Design Data Model Introduction 1 8 Pre
147. ain crossing flops for gate level simulation dedicated_mult Specifies that an instance should be mapped to the dedicated multiplier resource in place route dont_retime Specifies that the Retiming algorithm can be disabled on a register by register basis or on a module basis dont_touch Tells Precision Synthesis to pass the module through synthesis without optimizing or unmapping extract_mac Controls the mapping of multiply accumulate logic to Altera DSP blocks hierarchy Tells Precision Synthesis to maintain the hierarchy of the module Valid values are preserve or flatten This attribute is applied to instances synthesis_clearbox Specifies that Precision should generate timing models for Altera blackboxes using Altera s clearbox timing generator This will have a noticeable affect on runtime but it provides more accurate timing reports This attribute can be applied to the top of the design or to individual hierarchical blocks radhardmethod Actel Creates a radiation hardened implementation block_ram Xilinx Allows you to disable the mapping of a particular RAM instance to block RAM in Xilinx technologies Table 2 3 I O Port Attributes array_pin_number VHDL only This VHDL only attribute makes it easier to assign pin numbers to buses drive Sets the value to be associated with a drive 2 4 Precision Synthesis Installation Guide 2003c Update1 March 2004 Attributes Functional Lists of User Attribu
148. al port RAM with independent input and output synchronous ports Figure 9 9 Inferring Xilinx Dual Port RAM from VHDL library IEEE use IEEE std_logic_1164 all use IEEE std_logic_unsigned all entity sync_ram_dualport is generic data_width natural addr _width natural port clk in lt 2m std logic Clk ome in Sed logic we zin std logic j addr_in in std logic vector addr_width 1 downto addr_out in std logico vector addr_width 1 downto data_in in std_ logic vector data_ width 1 downto data_out out std_logic _ vector data_width 1 downto 7 end sync_ram_dualport architecture rtl of sync_ram_dualport is type mem type is array 2 addr_width downto 0 of std_logic_vector data_width 1 downto 0 Signal mem mem_type attribute block _ram boolean attribute block_ram of mem signal is true begin write process clk_in begin if clk_in event and clk_in 1 then if we 1 then mem conv_integer addr_in lt data_in end if end if end process write read process clk_out begin if clk_out event and clk_out 1 then data_out lt mem conv_integer addr_out end if end process read end rtl 9 12 Precision Synthesis Installation Guide 2003c Updatet March 2004 Designing with Xilinx Handling Xilinx Design Issues Figure 9 10 is the recommended Verilog style for an inferred dual port RAM with independent input and output synchronous ports Figure 9 10 I
149. alue higher than 100 In this case routing failure is more likely A very high timing value weight could also distort the optimization process and degrade performance A value greater than 150 1s not recommended Note This advanced option is only available for the SX SX A and eX families Altera MAX PLUSII Command Names cl default Run the vendor place and route flow in the background command line mode Use the options specified in the setup_place_and_route command Send a transcript of the executed commands to the Transcript window gui Invoke the Actel Designer gen_vcf Write a Vendor Constraint File to the active implementation directory Altera MAX PLUSII Command Arguments The arguments you specify here are the same options that may have been already set with the setup_place_and_route command They may be specified here to change a setup option on the fly when you execute the place_and_route command install_dir lt vendor_implementation_directory_pathname gt Specifies the pathname to the MAX PLUS II installation tree nNO exeCc This option is primarily used to debug the Precision place_and_route script that drives the implementation tools The commands in the script are echoed to the Precision Transcript window without the commands actually being executed by the implementation tools tim_an ta_dely ta_setup ta_reg This option causes MAX PLUS II to perform timing analysis You may create either an I
150. am control 3 ng Ea Vendor E hly D OCU ments a 2 Select netlists file filter History MGC C File name Cancel Files of type ik Precision recognizes the ngc file suffix as a coregen netlist file As such an ngc file will by default not be excluded from compile except on HP it will be set as type Xilinx NGC and displayed with its own icon for NGC files Precision Synthesis Installation Guide 2003c Update March 2004 Designing with Xilinx Handling Xilinx Design Issues Input Files within the GUI The following figure shows an example of how coregen input files appear in the Physical RTL graphical user interface Figure 9 3 Coregen input files in the GUI l JJ T Milns VIR TEX 2W40cs1 44 6 Frequency 1 MHZ Project Files Design Hierarchy So Project Files J carn ony impl i gt cam ony a Netlist files listed with their own icon not excluded from compile by default pen Ned i cam_caminput_i nge H cam_cam_encode_2 nge a Mai cam_cam_control_ 3 mge fi cam edn a ole cam_only yv T Constraint Files T Script Files A Output Files m Lad Log File Warnings 3 Infos 4 Pg Design Center Compiling Hierarchical Coregens During compilation Precision performs the following steps on each ngc file in turn 1 Copies the ngc file to the implementation directory for later expansion during place amp route
151. and set the file property exclude FALSE The exclude setting is applied to an input file through the file pop up menu properties dialog box 9 2 Precision Synthesis Installation Guide 2003c Update1 March 2004 Designing with Xilinx Handling Xilinx Design Issues From the command line the UCF file can be excluded using the exclude switch on the set_input_file command as follows set_input_file traffic ucf exclude false By default Precision excludes UCF files added to projects This means that the timing constraints will not be converted to SDC and used for Synthesis If you unset the exclude flag the UCF constraints will be used to generate SDC constraints and will still be passed to place and route When the UCF file is added to a project and not excluded then those constraints will be applied to the synthesis database and override any conflicting SDC constraints Although these timing constraints have been annotated onto Precision s database you may specify that the original UCF file timing constraint text be used in the Precision generated UCF file This functionality can be controlled from the pulldown tools gt options form Precision allows you to control what happens to the UCF timing constraints when it is added to a project Placement constraints and attributes will always be copied to the final UCF file If the desire is to use UCF constraints to constraint synthesis then do not exclude the UCF file from the
152. ands activate_impl new_impl delete_impl save_impl set_impl_property get_impl_property get_project_impls 3 38 Precision Synthesis Installation Guide 2003c Update March 2004 Commands correlate_reports correlate_reports Compares slack and path delay values between Precision and Xilinx Example correlate_reports user bruces cpuf pr cpuf twr Syntax correlate_reports twr_file Specifies path to Trce s timing report Description This command reads the twr file for the Xilinx TRCE tool analyzes each path listed in the twr file in Precision and generates a report showing the from to point slack and path delay values from Xilinx and slack and path delay values from Precision By default Precision uses the twr file in the current implementation directory You can also explicitly specify the pathname to the twr file This command is extremely useful for investigating timing correlation issues between Precision Physical and Xilinx place route Based on the information in this report you can adjust timing constraints to improve timing correlation Related Commands report_timing Precision Synthesis Installation Guide 2003c Update 3 39 March 2004 create_clock SDC Commands create_clock SDC Define a new clock for the current design Example Syntax create_clock period 10 waveform 0 5 name sys_clk clkd1ll1 Ud1l1l clk2x create_clock period lt period_value gt lt portu pan list gt
153. ansion during place and route _ Precision Synthesis Installation Guide 2003c Update 9 7 March 2004 Handling Xilinx Design Issues Designing with Xilinx Mapping Registers to IO Blocks Based on your timing constraints Precision will move registers into the I OBs You can manually control which registers get moved to the IOB using the 10b attribute You can also control the individual flop on bi directional ports using the inff outff and triff attributes After you synthesize the design Precision reports which register ports are mapped into the IOB using the report_io_registers command Xilinx Memory Mapping This section illustrates how to map synchronous memory elements to Xilinx Virtex Virtex II and Virtex II Pro memory resources Inferring Single Port RAM By default synchronous single port RAM that is mappable to Block RAM is mapped to Block RAM You can disable the mapping of a particular RAM instance to block RAM by specifying a block_ram attribute in the HDL source as shown in Figure 9 6 and setting the attribute value to false In this case the RAM is implemented using distributed SelectRAM if possible Restrictions when Mapping to Block RAM The following restrictions apply to the mapping of memory elements to Block RAM Block RAM supports the RST reset and ENA enable pins However Precision does not infer RAM that use this functionality The variant of single port RAM that is implemented using
154. are relative to different clocks or clock edges design lt rtl gatelevel gt Tells the tool whether to look for the object in the RTL or the gatelevel view 3 182 Precision Synthesis Installation Guide 2003c Update March 2004 Commands set_input_delay SDC Description Input Delay Defined Input delay is the delay consumed outside of the current design before the data signal arrives at the input port or pin Input delay is equivalent to the term arrival time that may be used in other Mentor Graphics tool environments As shown in the following illustration if the reference clock period 1s 10 ns and the input delay is specified as 6 ns then Precision Synthesis will constrain the combinational path from the input port data_in to the first register to 4 ns delay 6 ns constraint outside desi virtual circuit current aesign data_in clock period 10 ns set_input_delay clock clkl 6 data i What the Command Does The set_input_delay command adds an input delay constraint to the specified input port or pin The constraint specifies the amount of delay from the reference clock transition to the time that the rising and falling edges of the data signal arrive at the specified data pin s Input ports are assumed to have zero input delay unless otherwise specified The reference clock which could be a virtual clock must be defined prior to executing this command For inout bidirectional ports
155. are specified by setting switches in the setup_design command Related Commands compile Precision Synthesis Installation Guide 2003c Update 3 227 March 2004 tmpfile Commands tmpfile Create a temporary file in the system s temporary file directory Example tmorile surrix vhd Syntax tmpfile seed lt file name gt suffix lt file suffix gt string lt file_name gt lt file suffix gt Options seed lt file_name gt Specifies the basename of the temporary file If you don t provide a seed name the seed name precision 1s used suffix lt file_suffix gt Specifies the file suffix For example a suffix might be edf v or vhd Description The tmpfile command is primarily used in scripts to create a temporary file in your system s temporary file directory If you don t provide a seed name the seed name precision 1s used You can also specify a file suffix for files of a specialized format like edf v or vhd Related Commands 3 228 Precision Synthesis Installation Guide 2003c Update March 2004 Commands unalias unalias Remove the specified alias Example unalias Syntax unalias lt alias_ name gt Arguments lt alias name gt Alias name to be removed Description The unalias command removes an alias previously created with the alias command You can generate a list of currently defined alias names by entering the alias command with no arguments fr
156. arting with 0 This option tells Precision Synthesis to insert the new file before the specified position number Once inserted the position numbers are re assigned to account for the new file insert_after lt position_number gt Files in the input_file_list are numbered sequentially starting with 0 This option tells Precision Synthesis to insert the new file after the specified position number Once inserted the position numbers are re assigned to account for the new file replace This option tells Precision Synthesis to replace the attributes of the specified file with the new attributes For example the following command changed the work library to work2 for the specified file add_input_file F Uart src uart_top v work work2 replace search_path Specifies additional directories that are used with the global include search path specified in the setup_design command If you enter directories with this command the tool will search them for included hdl files For more information see the set_input_dir and set_input_file commands Searching for Verilog include files Ifa Verilog file is being added and additional files are referenced via the include directive then the search for the include file is conducted in the following order 1 The directory of the file that specifies the include directive 2 The directories that are specified as an argument to this search_path switch 3 The directories that are specifie
157. ary named work list all entities packages and modules analyzed into the HDL library work list all ports on the view contents of the cell and2 in the library work list all libraries in the data base list the contents of the current design If the current design is a view list the instances list the ports of the current design list the references instances of the current design list all cells in all libraries list all the nets in the current design return the view name to which the instance xyz is pointing list views contained in the instance x in the current design list the nets in the current design that start with letter n report_connections report_area report_attributes Precision Synthesis Installation Guide 2003c Update March 2004 Commands load_project Deprecated load_ project Deprecated Actually calls the open_project command Example load_project E my_design controller psp Source a Tcl file named E my_designcontroller psp Syntax load_project lt file _pathname gt lt file_pathname gt Arguments lt file_pathname gt Specifies the file pathname of a project file that will be sourced The file extension is not required however the psp extension will make the file visible in the Open Project dialog box If the file is in the current working directory you only have to specify the file leaf name Description Beginning with release 2003c the functionality perfo
158. as multiple components each driving a single load refer to the following figure Logic replication results in a mapping that often makes it easier to meet your timing requirements since some delays can be eliminated on critical nets This switch allow you to to turn off logic replication Use f lt command file gt options with BitGen Allows you to specify a command file that will be executed by BitGen Seconds to delay after generating NPL file The default is 5 seconds 9 34 Precision Synthesis Installation Guide 2003c Update March 2004 Designing with Xilinx The Xilinx ISE Environment Setting Xilinx ISE Constraint File Options As shown in Figure 9 31 you can change pre set ISE options from the Tools gt Set Options pull down menu The option settings are explained in the paragraphs that follow Figure 9 31 Setting Xilinx ISE Constraint File Options t Input Optimization F Analysis E Vendor Constraint File User Constraint File session Settings Do not run commands H Schematic Viewer Fl Physical M Enable Auto Offset Relaxation in Vendor Constraint file W Use UCF Timing Constraints from the Input UCF File Enable to use timing e from original UCF input file Cancel Apply Help User Constraint File Enter the pathname of a Xilinx UCF file to be used during Place and Route Do not run commands This switch is primarily used for debugging the Precision script that drives the Xilinx
159. as unsaved work and the discard option is not specified You can either discard the unsaved work or call save_impl prior to calling copy_impl Related Commands activate_impl get_project_impls copy_impl save_impl delete_impl set_impl_property get_impl_property Precision Synthesis Installation Guide 2003c Update 3 95 March 2004 new_project Commands new_ project Create and open a new project Example new_project name uart_top folder C designs createimpl Syntax new_projyect name lt project_name gt folder lt folder_path gt createimp1 lt project_name gt lt folder_path gt Arguments name lt project_name gt Name of the new project folder lt folder_path gt The full pathname to the directory in which the project will reside Returns an error if the specified directory does not exit Options createimpl Create and open an implementation The implementation name is constructed by concatenating the project name with the _impl_1 suffix Description The new_project command is a project manager command that creates and opens a project of the specified name and at the specified path It is unavailable if a project is currently open It first creates the project file psp and a session log file precision log in the project folder Next if the createimpl option is specified a default implementation is created in the project folder If createimpl is not specified the
160. asynchronous registration flow This attribute is used in Xilinx to flag flip flops as clock domain crossing flops for gate level simulation This is a simulation enhancement that lets you specify a signal flip flop as being a clock domain crossing flip flop This would require that there is already proper metastability protection circuitry in place and setup hold checks can be disabled for that particular flop such that an X is never propogated from that flip flop The AS YNC_REG flows can be entered as a TCL constraint or a VHDL label TCL Constraint Example Setting attributes in a constraint file set attribute name ASYNC_REG value TRUE instance reg resyne fifo full VHDL Example Setting the attribute on a flop instantiation through a VHDL attribute attribute async_reg string attribute async_reg of Ul_resync_fifo_full label is true block_ram Xilinx Allows you to disable the mapping of a particular RAM instance to block RAM in Xilinx technologies Block RAMs are highly area efficient because they use dedicated on chip resources but may result in additional delay The use of Block RAMs can cause timing problems in two areas First the clock to out path of a Block RAM is roughly 20 slower than the equivalent Distributed RAM implementation Second Block RAMs must be placed in specific areas of the Xilinx Virtex II die If you use block RAMs check the post layout timing reports in Xilinx to insure that poor pla
161. at drives the MAX PLUS II tools The commands in the script are echoed to the Precision Transcript window without the commands actually being executed by the implementation tools Timing Analysis Input Output Delay Create an Input to Output Delay matrix Setup Hold Create a Setup Hold matrix Register Performance Create a Register Performance report Setup MAX PLUS Il Create ACF File Specifying whether or not to generate an ACF Altera Assignment amp Configuration file Auto Fast I O This boolean allows the MAX PLUS II compiler to implement registers in Fast I O This often reduces area requirements but can slow internal circuitry This option corresponds directly to the Automatic Fast I O option in the Altera MAX PLUS II GUI Auto Register Packing This option specifies whether or not to allow the MAX PLUS II compiler to maximize efficient device usage automatically implementing register packing by placing a combinational logic function and a register with a single data input in the same logic cell This option corresponds directly to the same option in the Altera MAX PLUS II GUI Precision Synthesis Installation Guide 2003c Update 8 7 March 2004 Altera Quartus II Integration Designing with Altera Devices Auto Implement in EAB This option specifies whether or not to allow the MAX PLUS II compiler to automatically implement some logic in Flex 10K EABs This option corresponds directly to the same option in the A
162. ated output file If this option 1s not specified the leaf name of the last HDL input file to be read 1s used btw lt bestltypicallworst gt This argument specifies the process conditions either best case typical case or worst case and is normally set when the user selects technology options from the Setup Design dialog box in the GUI cim lt commercial industrial military gt This process argument is normally set when the user selects the technology from the Setup Design dialog box in the GUI design lt design_top gt Specifies the entity name or module name that represents the top of the design if more than one top 1s possible 3 212 Precision Synthesis Installation Guide 2003c Update1 March 2004 Commands setup design edif Generate an EDIF netlist file The default is true If you wish to set this switch to false then you should use the following syntax edif false If more than one output format switch is set true then an output file in each of the specified formats will be generated family lt library_name gt Family name as specified in the file lt precision install directory gt pkgs psr techlibs devices ini This argument is normally specified when the user selects the technology family from the Setup Design dialog box in the GUI fault_tolerant If set to true Precision does decoding for out of range Verilog index values This option is designed such that you exactly match RTL
163. ath analysis a path must start on a primary input pin or on the clock or data output pin of a register and end at a primary output pin at the data input pin of a register or on any pin having a Setup or Hold timing parameter attached A through switch declaration is usually sufficient in cases where single pin definitions are desired Related Commands set_false_path SDC report_attributes set_input_delay SDC report_missing_constraints set_output_delay SDC set_false_path SDC Precision Synthesis Installation Guide 2003c Update 3 199 March 2004 set_output_delay SDC Commands set_output_delay SDC Set output delay on output ports or pins relative to a clock Example set_output_delay 8 0 all_outputs set_output_delay 2 0 get_ports fout clock sysclk set_output_delay 2 5 get_ports fout clock wclk add_delay Syntax set_output_delay lt delay_value gt lt port_pin_list gt clock lt clock_ name gt clock_fall rise fall offset add_delay design rtl gatelevel list spor pin list gt Arguments lt delay_value gt Specifies the path delay from output port of the current design to the data pin of the first register in the device being driven The lt delay_value gt must be in units consistent with the technology library used during optimization lt port_pin_list gt A list of output port or internal pin names in the current design to which lt delay_value gt IS assigned
164. ations 2 Performs netlist modifications to implement a more efficient version of the netlist based on knowledge of the functionality relative size and speeds of all the operators 3 Removes duplicate operators that share all inputs with another operator 4 Restructures adders and multiplier chains based on Verilog option choices for interpretation of Case statements 5 Performs constant propagation at the operator level For example the tool replaces an adder that has one input connected to a constant 1 value with an incrementer that possesses a smaller area cost Even though the operator is yet to be implemented constant propagation at this point in the process makes operator expansion more efficient After Precision performs resource sharing it propagates constants through the entire design as described below How Precision Synthesizes the Design Precision Synthesis preforms global area optimization and critical path timing optimization separately on each module in the design Area optimization 1s automatically run first followed by critical path optimization if required to meet a timing constraint that may be optionally specified 4 8 Precision Synthesis Installation Guide 2003c Update1 March 2004 How Precision Compiles Designs How Precision Synthesizes the Design Precision Synthesis uses different techniques during optimization Depending on the options chosen and algorithms run a design can fall at different point
165. ations revisions copies documentation and design data Software are copyrighted trade secret and confidential information of Mentor Graphics or its licensors who maintain exclusive title to all Software and retain all rights not expressly granted by this Agreement Mentor Graphics grants to you subject to payment of appropriate license fees a nontransferable nonexclusive license to use Software solely a in machine readable object code form b for your internal business purposes and c on the computer hardware or at the site for which an applicable license fee is paid or as authorized by Mentor Graphics A site is restricted to a one half mile 800 meter radius Mentor Graphics standard policies and programs which vary depending on Software license fees paid or service plan purchased apply to the following and are subject to change a relocation of Software b use of Software which may be limited for example to execution of a single session by a single user on the authorized hardware or for a restricted period of time such limitations may be communicated and technically implemented through the use of authorization codes or similar devices c support services provided including eligibility to receive telephone support updates modifications and revisions Current standard policies and programs are available upon request 2 ESD SOFTWARE If you purchased a license to use embedded software development ESD Software
166. available for the SX SX A and eX families vcf_file lt string gt Set to the pathname of a vendor constraint file Altera Max PLUS II Command Names Integrated Place and Route Set the options specified in the Integrated Place and Route dialog box External Place and Route Set the options specified in the External Place and Route dialog box Generate Vendor Constraint File Set the options specified in the Generate Vendor Constraint File dialog box Altera Max PLUS II Command Arguments install_dir lt vendor_installation_directory_pathname gt Specifies the pathname to the MAX PLUS II installation tree 3 220 Precision Synthesis Installation Guide 2003c Update March 2004 Commands setup_place_and_route NO XeC This option is primarily used to debug the Precision place_and_route script that drives the implementation tools The commands in the script are echoed to the Precision Transcript window without the commands actually being executed by the implementation tools tim_an ta_dely ta_setup ta_reg This option causes MAX PLUS II to perform timing analysis You may create either an Input to Output Delay matrix a Setup Hold matrix or a Register Performance report generate_acf A boolean value specifying whether or not to generate an ACF Altera Assignment amp Configuration file Default is 1 true auto_fast_io This boolean option allows the MAX PLUS II compiler to implement registers in Fast
167. b tcl xnf xdb sdf and sdc The sdc constraint files should be listed last so the constraints can be added to an already compiled in memory design Related Commands add_input_file set_input_file report_input_file_list setup_design remove_input_file remove_design 3 94 Precision Synthesis Installation Guide 2003c Update March 2004 Commands new_impl new_impl Create and activate a new implementation in the current project Example new_impl name uart_top_impl_1l Syntax new_impl name lt impl name gt discard ss Options impl lt impl_name gt Name of the implementation to create discard Discard any unsaved work in the implementation being deactivated Description The new_imp1 command is a project manager command available only when a project is open It closes the active implementation then creates and activates a new implementation with the specified name In the file system a new implementation directory is immediately created including a new implementation file psi and log file precision log The new implementation contains no information about design settings nor input files If the name option is omitted a default implementation name is constructed by concatenating the name of the project and the _impl_ lt n gt suffix where lt n gt is an integer that is incremented to ensure uniqueness within the project An error occurs if the currently active implementation h
168. base Operators in the netlist are represented as black boxes that contain only information about the operator function To do this Precision uses the modgen library which is a library of module generators corresponding to HDL operators such as and Each operator can produce a number of different architectures that vary in area and delay characteristics from small and slow to large and fast Each blackbox operator uses a naming convention to convey parameter information such as type size sign carry for example add_16u_16u_0 16 bit adder unsigned operands no carryout gte_ 8s 8s 8 bit greater than signed operands Before optimization Precision prepares operator instances as follows Instances are unpadded by removing constants from MSBs of operands Mixed width operators can also be created to save area For example if one operand is 16 bits and another is 32 bits Modgen does not pad the 16 bit operand to 32 bits Instead it generates an architecture for a 16 by 32 bit operator Infer RAMs RAMs are inferred during the elaborate phase as long as they follow the HDL guidelines outlined in the HDL style guide Although a RAM may be inferred Precision can not guarantee it can be implemented in a technology ram cell until the synthesize process Some technologies do not support all RAM implementations that Precision can infer Precision Synthesis Installation Guide 2003c Update 1 4 5 March 2004 How Precision
169. ble 3 3 Synthesis Flow Commands compile Compile the design that is specified by the input_file_list Synthesize the current in memory design place_and_route Run the integrated place and route tools report_timing Run the PreciseTime Timing Analyzer and return information about the design Table 3 4 Constraint Commands create_clock SDC Define a new clock for the current design remove_attribute Run the integrated place and route tools remove_clock Remove the clock information from the specified object s Precision Synthesis Installation Guide 2003c Update 3 9 March 2004 Command Summary Commands Table 3 4 Constraint Commands continued remove_design Remove a list of designs or libraries from the in memory database remove_input_delay Remove the Input Delay on the specified pins or input ports remove_output_delay Remove the Output Delay on the specified pins or output ports Report the accumulated area of the current design Create or set an attribute on the specified object s set_false_path SDC Ignore slack values on the specified paths set_fanout_load SDC Limit the capacitance in library units that a net or port can drive set_input_delay SDC Set input delay on pins or input ports relative to a clock signal set_max_delay SDC Set the maximum total path delay for a timing path that is constrained by a clock set_max_fanout SDC Limit the maximum number of pins that a net or port can
170. bles for various die sizes instance counts and they determine the values in the route tables based on the statistical analysis of die size and fanout Larger die sizes and fanouts yield higher net capacitance 3 Determines the number of net connections Precision must also determine the number of net connections in order to reference the net capacitance in the route table Output ports on hierarchical blocks are not counted in the number of net connections 4 References the total net capacitance Each net connection type has a unique section within the route table Precision determines the net capacitance by summing the net capacitance value referenced for each net connection type in the route table Precision Synthesis Installation Guide 2003c Update 4 11 March 2004 How Precision Synthesizes the Design How Precision Compiles Designs 5 Determines whether a net is connected to an output port If the net is connected to an output port Precision adds the value of the user defined output capacitance Because the input capacitance limit constraint defines the drive strength of a port not the capacitance load on a port Precision ignores input capacitance constraints for this step 6 Sums the pin output capacitance constraint and under some circumstances the net capacitance values The sum of these capacitance sources yields the capacitance loading effect on the specific net ASIC vendors specify whether Precision uses the net capacitance i
171. c LPM module to the equivalent Altera LPM cell or to the most optimal primitive cells for the target technology 8 2 Precision Synthesis Installation Guide 2003c Update1 March 2004 Designing with Altera Devices Handling Altera Design Issues Specifying the Block Size for Stratix TriMatrix Memory After a memory block is inferred and targetted for Stratix TriMatrix Memory you may specify the target Block Size from the Precision GUI as shown in Figure 8 2 Specifying the Block Size for Stratix TriMatrix Memory ndom Mentor Graphics Precision RTL Synthesis Design Center Tools Window Help Altera Stratis EPTS25F 10200 5 Frequency 100 MHZ Project Files Design Hierarchy Sy Project pseudorandom E F pseudorandom rel a Impl pseudorandom impl cE a Clocks E Input Files H Wii pseudorandom yhd 2H Constraint Files Shien Instances FE pseudorandom_constra Blocks E Script Files H Id dlatrg 255 a Output Files E Ii priority encoder 25 5 lod Log File Warnings 2 I Iz ram 6 5 oe RTL Schematic i B Rr Constraints Report RRP Missing Constraint 1 Select and El Instances Right Click B mem fram dg inc lo Le k _readadde Ik ed Trace bo Hierarchy Set Attributes Don t Touch 2 Select Repork Thinning ALTO Maile Stee Copy Query Info to Clipboard MegaR AM Sort by name q Instance mem Ea Transcript FY Design Center Mapping Infered
172. ccessful place and route Project Files Design Hierarchy Ella Project my_fifo F my_fifo INTERFACE_ amp RTL E a Impl my _fifo impl 1 H 2 Clocks I a Input Files tm bb E J Nets 3 ny a 2 Instances E E Black Boxes ve Constraink Files fifo inst fifo al C Script Files ek a Output Files oe Lad Log File warnings 1 Infos 12 E RTL Schematic Em Technology Schematic E Area Report REJ Timing Report RE Constraints Report vee Eii my Fio edf a Quartus II Compilation Report Aih Quartus II Project Configuration Script E The flow for using VHDL megafunctions is similar except that the MegaWizard does not create a Verilog black box module definition but does create a VHDL implementation file instead of Verilog For this flow you incorporate the component declaration and instantiation template now VHDL as opposed to Verilog into the parent entity declaration then add the VHDL implementation file to the input file list and have it excluded from compile as before Altera Devices Supported Stratix Hardcopy Support You can specify a Hardcopy device in the Setup Design phase using either the GUI or command line GUI Select the hardcopoy device with the HARDCOPY suffix in the device list Command Line use the setup_design command to specify the hardcopy part For example setup_design manufacturer Altera family Stratix part EP1IS80F1020C_HARDCOPY speed 6 8 12 Pre
173. ce the CLKDLL configuration or the equivalent DCM Digital Clock Manager configuration Low frequency BUFGDLL configuration shown below CLADLL CLKO CLKSO CLK180 CLK2TO CLK2X CLKEDYV LOCKED This configuration supports a maximum input frequency of 160 Mhz for Virtex I speed grades 7 and 8 A max input frequency of 135 Mhz is supported for speed grade 6 High frequency BUFGDLLHE configuration A maximum input frequency of 320 Mhz is supported for Virtex I speed grades 7 and 8 and a maximum input frequency of 260 Mhz for speed grade 6 In both cases only the CLKO output from the DLL is supported Precision Synthesis Installation Guide 2003c Update 1 9 1 March 2004 Handling Xilinx Design Issues Designing with Xilinx Directing the Automatic Insertion of CLKDLL Cells 1 After the design 1s Compiled select a clock port in the Design Hierarchy window and choose Set Input Constraints 2 In the Clock Buffer dialog box choose either BUFGDLL or BUFGDLLHF This action creates a constraint command in the generated SDC file similar to the following set_attribute port work my_design rtl clk name PAD value BUFGDLLHF To keep this constraint as part of your design you should use a text editor to cut this command from the generated constraint file and paste it into your Master Constraint File Instantiating Clock Management Cells in the HDL Source For other Virtex I II clock management configurations you
174. cement of the block RAMs did not result in excessive routing delays to and from the Block RAM cell 2 10 Precision Synthesis Installation Guide 2003c Update1 March 2004 Attributes Pre Defined User Attributes By default RAMs that are mappable to block RAMs are mapped to block RAMs You can disable the mapping of a particular RAM instance to block RAM by setting the following attribute on the RAM array signal to false Verilog module dpmemo64 din wen rdaddr wraddr clk oclk dout input 730 dirn input wen clk oclk tmoue 5 0 rdaddr wraddrs output 7 0 dout reg 7 0 dour integer i reg 7 0 mem 63 0 pragma attribute mem block_ram false assign dout mem rdaddr VHDL architecture rtl of dualp_ram is type mem type is array 5 downto QO of std logic vector 7 downto QO Signal mem mem_type attribute block ram boolean attribute block_ram of mem signal is false begin Interactive Command Line Shell set_attribute instance Il name block_ram value false From the command line the attribute must be set on the generated generic RAM instance RTL database before it is mapped to a technology cell buffer_sig Specifies that a signal a net in the design is to be buffered with a technology specific buffer Verilog pragma attribute data_sum buffer_sig ibuf VHDL attribute buffer sig string attribute buffer_sig of data_sum signal is ibuf Interactive Command Line Shell s
175. cision Synthesis Installation Guide 2003c Update1 March 2004 Chapter 2 Attributes An attribute is information that is attached to owned by an object in the Precision Synthesis in memory design database An attribute has a name a type a value and an owner An attribute s value typically describes a characteristic about the design object The concept of an attribute in an HDL language is the same The attribute is a name value pair that is associated with attached to set on or owned by a design object in the design In VHDL the attribute construct may be used to associated a design object with an attribute value and in Verilog a pragma attribute directive may be use If these attributes are declared in the source files the HDL attributes are converted to attributes on objects in the in memory database and may be translated as EDIF properties during an EDIF netlisting operation and or passed to the vendor s implementation software via a user constraint file In Precision Synthesis setting attributes 1s used as a control mechanism to guide the synthesis process The syntax and methods for applying attributes to your in memory design are described in this chapter Alphabetical List of User Attributes Table 2 1 contains a summary of the User attributes that Precision Synthesis supports Table 2 1 Alphabetical Attribute Summary array_pin_number VHDL only This VHDL only attribute makes it easier to assi
176. cision Synthesis Installation Guide 2003c Update1 March 2004 Designing with Altera Devices Altera Devices Supported StratixGX Devices Supported Precision Synthesis supports the following StratixGX devices StratixGX Speed Grades Default Speed Grade 5 Speed Grades supported 5 6 7 Cyclone Devices Supported Precision supports the following Cyclone devices EP1C20 F324C F400C Cyclone Speed Grades Default Speed Grade 6 Speed Grades supported 6 7 8 Stratix Devices Supported The new Stratix device family is Altera s next generation system on a programmable chip SOPC solution The Stratix architecture features eight times more RAM bits as well as dedicated DSP functionality on chip termination resistors and advanced system clock management features Precision supports the following Stratix devices Precision Synthesis Installation Guide 2003c Update 8 13 March 2004 Altera Devices Supported Designing with Altera Devices Stratix Devices B672C F484C F672C F780C B672C F484C F672C F780C B672C F672C F780C F1020C F780C B956C F1020C B956C F780C F1020C F1508C B956C F1020C F1508C B956C F1508C PO e me Al NI NI NI NI N MN CO ON B I wolnNnityi nil e od CS a olo Stratix Speed Grades Default Speed Grade 5 Speed Grades supported 5 6 7 8 Excalibur Arm Devices Supported Excalibur Mips Speed Grades Default Speed Grade 1 Speed Grades
177. ck_latency sys_clock90 Syntax remove_clock_latancy lt object_name gt source string lt object_name gt lt attribute_type gt Arguments lt object_name gt Name of the object defined clock port or net that owns a clock attribute Wild cards and lists are accepted Options source Specify the clock rise and fall source latency to remove Description The remove_clock_latency command removes the latency constraint for any previously defined clock If the constraint is removed Precision calculates clock latency using library values Related Commands set_attribute Precision Synthesis Installation Guide 2003c Update 3 117 March 2004 remove_clock_transition Commands remove_clock_transition Removes the defined clock transition overrides Precision will use library values Example create_clock name sys_clk90 ul udcm Q remove_clock_transition sys_cl1k90 Syntax remove _ clock transition lt clock name gt Arguments and Options None Description The remove_clock_transition command removes the constraint for any previously defined clock If the constraint is removed Precision calculates the clock transition times using library values Related Commands create_clock SDC report_timing 3 118 Precision Synthesis Installation Guide 2003c Update March 2004 Commands remove_clock_uncertainty remove_clock_uncertainty Removes the defined clock skew overrides Precision will use
178. ct delete_impl Delete an implementation in the current project implementation Actually calls the open_project command move move_inputfile file Move a file either up or down 1n the input_file_list and activate a new implementation in the current project Open_project Open an existing project remove_design Remove a list of designs or libraries from the in memory database save_project Obsolete This command has been replaced by the save_impl command Calls to save_project will actually execute the save_impl command 3 8 Precision Synthesis Installation Guide 2003c Update March 2004 Commands Command Summary Table 3 2 Project and File Management Commands continued projects will be saved to a temp directory set_project_propert Set a Precision property indicating whether the current proj property l property gw l project will use a temp directory for its active implementation the next time the project is opened set_results_dir Set explicitly where output files will be written when not using projects set_working_dir Deprecated Set the working directory to the specified pathname Use the following commands instead cd set_input_dir set_results_dir setup_analysis Setup the PreciseTime timing report setup_design Setup the design environment update_constraint_file Update the output constraint file with the constraints that have been entered during the current session Ta
179. ct Terms PT in each equation In other words the Optimizer shapes the equations relative to the set number of PT For example if the value is set to 35 the Optimizer splits equations if it has more than 35 PT This option works the opposite of Collapsing Max Product Term 3 224 Precision Synthesis Installation Guide 2003c Update1 March 2004 Commands setup_place_and_route max_pterm _collapse lt string gt This option lets you control the Fitter optimization process by setting a maximum limit on the number of Product Terms PT in each equation In other words the Optimizer shapes the equations relative to the set number of PT For example if the value is set to 35 the Optimizer stops collapsing equations when it exceeds 35 PT This option works the opposite of Splitting Max Product Term max_pterm_limit lt string gt max_fanin lt string gt Specifies the maximum fanin max_symbols lt string gt fmax_logic_levels lt string gt Xilinx ISE 5 1 Command Names Integrated Place and Route Set the options specified in the Integrated Place and Route dialog box Generate Vendor Constraint File Set the options specified in the Generate Vendor Constraint File dialog box Xilinx ISE 5 1 Command Arguments The arguments you specify here are the same options that may have been already set with the setup_place_and_route command They may be specified here to change a setup option on the fly when you execute the p
180. d as an argument to the setup_design search switch Assume for example that the file being added is located in the directory F design sre and this search path is set to the following C my_include_files F more_include_files During the compile operation for this file Precision Synthesis first searches for any specified include files starting in directory F design src then C my_include_files then directory F more_include_files Ifthe file is not found the directories specified by the search switch of the setup_design command are searched As soon as the file is found the search ends Searching for VHDL files When the file being added is compiled and it references a VHDL library or a package that has not yet been compiled a search is conducted for this package file by that library or Precision Synthesis Installation Guide 2003c Update 3 17 March 2004 add_input_file Commands package name so it can be compiled first Assume for example that this input file contains the following the clause use lib my_package selection When the file is compiled Precision Synthesis looks in the library work to see if my_package has been compiled If not a search begins in the directory where this input file resides then the directories that are specified by this switch The search continues in the directories specified by the search switch of the setup_design command and finally the directory lt precision install directory
181. d by the current_design command The value of current_instance does not affect the result of this command This command is typically used with the set_ commands to specify timing constraints on ports similar to wildcards You can limit the top level inputs included in the list by using the clock option This switch examines the timing paths from all inputs at the top level of the design to sequential elements that are clocked by the clock names specified in the clock switch If a timing path exists from the input port to the sequential element Precision Synthesis includes the input port in the return list You must use the clock names specified in the create_clock command and not the instance pathname to the clock pin If you need to determine the names of the input ports of a lower level block you can either use the Design Browser tool and navigate to the block in hierarchy or you can use the get_ports command to specify the instance pathname and return the instance ports More Examples gt ell anputs clock sys clk ERROR No constraints of input ports found Need create_clock first gt create_clock period 10 waveform 0 5 name sys_clk sys_clk gt ei anpurs clock sys _clk select k_ data 3 k data 2 k _data 1l k_data 0 gt set_input_delay 3 0 all_inputs clock sys_clk Related Commands all_outputs SDC all_registers all_inouts all_ clocks SDC 3 28 Precision Synthesis Installation Guide 2003c Update
182. d file Spawn an interactive child process from the precision shell command prompt exec_interactive exit Exit from the current session of Precision export_settings Saves export implementation settings to a TCL script find find_clocks Find the specified objects in the in memory design Return hierarchical pathnames for all clocks in the design find_inputs Find all of the inputs in the current design find_outputs Find all of the outputs in the current design get_cells SDC Get cells instances from the current design relative to the current instance 3 i N Precision Synthesis Installation Guide 2003c Update1 March 2004 Commands Command Summary Table 3 1 Alphabetical Command Summary continued Command Description get_clock_domains Return a list of clock domains in the current design get_clocks SDC Return a list of defined clocks in the current design get_designs Return a list of cells used in the current design get_false_paths Return a list of previously defined false paths Return the name or comment value of an implementation get_impl_property Return a list of library pins on cells in a previously get_lib_cells SDC get_lib_pins SDC Return a list of cells in a loaded library loaded library get_libs SDC Return a list of currently loaded libraries that match the search pattern get_multicycle_paths Return a list of previously defined multicycle paths get_nets SDC
183. d into memory Related Commands current_instance SDC Precision Synthesis Installation Guide 2003c Update 3 45 March 2004 current_instance SDC Commands current_instance SDC Set the working instance in the design hierarchy which will allow other commands to set or get attributes from that instance Example Current instance UL U5 ix2 Syntax current_instance instance_pathname Arguments instance_pathname Name of the instance pathname to be set as the current instance The top level of the design the root is referenced as If instance U1 1s instantiated in the top level view then it s instance pathname is U1 If the view for U1 has an instance U5 and the view for U5 has an instance 1x2 then the pathname for 1x2 is U1 U5 1x2 Description The current instance is the working instance in the current design hierarchy Setting the current instance set the focus for other commands to set or get attributes from that instance If you enter this command without an argument then the focus is set to the top_level If you set the current instance to a level in the hierarchy and want to know the instances in that view then enter the command get_cells More Examples current _instance Returns the pathname of the current instance The current instance is not changed current_instance Moves the current instance up one level in the design hierarchy Related Commands cur
184. d maintained by the Project Manager This file stores information about the implementations within the project lt design_name gt tcl A command file that has been created by the user with a common text editor or generated by the user from the Transcript window The following file types are generated by Precision RTL Synthesis and placed in an implementation sub directory Table 5 3 Output File Extensions File Extension File Description The synthesized design netlist in EDIF format input file The synthesized design in Mentor Graphics binary format A generated constraints file that contains the constraints that you manually entered or changed from the GUI constraint file A Precision Synthesis report file output file Precision Synthesis Installation Guide 2003c Update 5 3 March 2004 Precision Initialization File Files Reference Figure 5 2 Hierarchical Project File Structure Master project file created Project Folder a by new_project command lt project_name gt psp precision log 4 lt project_name gt _impl_1 lt project_name gt _temp_1 precision log lt name gt _impl_2 psi lt output_file gt Project s temporary lt output_file gt results directory Implementation directory with user specified name lt impl_name gt Default Implementation Pe Implementation Log File Session log file Implementation File created by the project Specifying Output Files Preci
185. de files starting in directory F design src then C my_include_files then directory F more_include_files Ifthe file is not found the directories specified by the search switch of the setup_design command are searched As soon as the file is found the search ends Searching for VHDL files When the file being added is compiled and it references a VHDL library or a package that has not yet been compiled a search is conducted for this package file by that library or package name so it can be compiled first Assume for example that this input file contains the following the clause use lib my_package selection When the file is compiled Precision Synthesis looks in the library work to see if my_package has been compiled If not a search begins in the directory where this input file resides then the directories that are specified by this switch The search continues in the directories specified by the search switch of the setup_design command and finally the directory lt precision install directory gt pkgs techdata vhdl is searched As soon as the file 1s found the search ends the package file 1s compiled and the specified input file file is compiled If the package file 1s not found Precision Synthesis issues an error message Description The set_input_file command is primarily used by the GUI to reset the attributes on a file that has already been added to the input_file_list Related Commands move_input_file set_input_file
186. der the instance y Instance x is unaffected since instance x 1s a parameter of the except option ungroup x In this example the ungroup command ungroups only instance x in the current design Additional hierarchy under the view pointed to by x remains in place Related Commands group current_design SDC Precision Synthesis Installation Guide 2003c Update 3 231 March 2004 update_constraint_file Commands update_constraint_file Update the output constraint file with the constraints that have been entered during the current session Example update_constraint_file Syntax update_constraint_file Description Primarily used by the GUI to update the generated output constraint file with the constraints that have been entered during the current session Related Commands add_input_file report_project 3 232 Precision Synthesis Installation Guide 2003c Update March 2004 Commands view_floorplan view_floorplan Invoke PreciseView on the current in memory physical database Example view_floorplan Syntax view_floorplan Description The view_floorplan command is primarily used by the GUI to invoke Precise View on the current in memory physical database and open a Device window for user viewing and editing Related Commands compile physical_synthesis Precision Synthesis Installation Guide 2003c Update 3 233 March 2004 view_schematic Commands view_schematic Display a schematic view of the current d
187. drive set_min_delay SDC Set the minimum total path delay for a timing path that 1s constrained by a clock set_multicycle_path SDC Modify the single cycle timing relationship of a constrained path set_output_delay SDC Set output delay on output ports or pins relative to a clock Table 3 5 Report Commands report_analysis Return information on how the specified timing report options are set report_timing Run the PreciseTime Timing Analyzer and return information about the design teport_constraints constraints List user specified constraints on any object a Report missing constraints on the external ports report_attributes Report information on the specified net s 3 10 Precision Synthesis Installation Guide 2003c Update March 2004 Commands Command Summary Table 3 5 Report Commands continued report_license Return a list of the license features that are currently in use Table 3 6 Object Access Commands all_clocks SDC Return a list of all clocks in the current design Return a list of all inout ports in the current design all_inputs SDC Return a list of all input ports in the current design The search can be limited to input ports that have constraints relative to a given clock all_outputs SDC Return a list of all input ports in the current design The search can be limited to input ports that have constraints relative to a given clock all_registers Return a list of all sequen
188. e 1 2 23 March 2004 Pre Defined User Attributes Attributes VHDL attribute triff boolean attribute trifr of data incou ut 1 signal ws talse Interactive Command Line Shell set attribute port data_inout l1 name triff value false You can also set this attribute by right clicking on a tristate port in the Design Hierarchy pane of the GUI and selecting Force Tristate Flop onto Pad gt FALSE uselowskewlines Tells the implementation tools to assign the specified signal to a low skew route line Verilog pragma attribute internal_clk uselowskewlines true VHDL attribute uselowskewlinesl boolean attribute uselowskewlines of internal_clk signal is true Interactive Command Line Shell set_attribute net internal clk name uselowskewlines value true 2 24 Precision Synthesis Installation Guide 2003c Update1 March 2004 Chapter 3 Commands The Precision Synthesis command interface is based on the Tcl command language The commands listed in this section are extensions to the basic Tcl language and provide support for the Precision Synthesis flow Command Summary Table 3 1 contains a summary of Precision Synthesis specific Tcl commands Table 3 1 Alphabetical Command Summary alias Define an alternative command for a set of command s all_ clocks SDC Return a list of all clocks in the current design Return a list of all inout ports in the current design all_inputs SDC Return a list of all in
189. e 9 4 Coregen files after compilation 22 lala ling VIR TES 44002144 gt 6 Frequency 1 MHZ Project Files Design Hierarchy Project Files H cam_only _impl_1 i 8 cam_only_impl 2 H E Ports EJ al Clocks Input Files Nets se Nal cam cam_inpuk_i nge E Instances Mal Cam_cam_encode_2 ngc H E Blacks see Nil cam cam control 3 ngc CI cam gi cam edn H E Pins a wel cam_only a Mets E Constraint Files EI Instances Script Files H E Flip Flops Output Files A E Block Lol Log File Infos 4 Te BUZ cam_cam_imput_1 BET BUSS cam cam encode 7 BUS9S fcam_cam_control_3 Hierarchical sub blocks displayed as having a dont_touch attribute working Directory HierarchicalCoregen FA 9 6 Precision Synthesis Installation Guide 2003c Update1 March 2004 Designing with Xilinx Handling Xilinx Design Issues After compilation the synthesis tool should be able to perform technology mapping timing optimization and timing analysis Using Hierarchical Coregen on the HP Platform Hierarchical coregen requires the following steps to run on an HP platform The first step is to run ngc2edif manually Next add the NGC and NDF files to the input file list The Precision tool will run the following steps for you 1 Ifa naf file is read in as EDIF an attribute is placed on that block such that its contents do not get written out to the final top l
190. e Precision will save output files Description The set_results_dir command sets the results directory to the specified path The results directory is where Precision saves output files The specified directory is created if it does not already exist The set_results_dir command 1s not available while a Precision project 1s open Setting the results directory allows you to work without Precision s project manager All project manager commands will be unavailable until the close_results_dir command is executed Deactivating the Project Manager is desirable in situations where Precision is being driven by scripts exclusively Related Commands close_project get_project_name close_results_ dir get_results_dir Open_project 3 206 Precision Synthesis Installation Guide 2003c Update March 2004 Commands set_working_dir Deprecated set_working_dir Deprecated Set the working directory to the specified pathname Use the following commands instead ed set_input_dir set_results_dir Example set_working_dir E designs controller Syntax set_working_dir lt directory_pathname gt create lt directory_pathname gt Arguments lt directory_pathname gt Specifies a full pathname of a directory Options create Tells Precision Synthesis to create the specified working directory if none exists Description Beginning with release 2003c the three functions performed by the set_working_dir command are now
191. e aOR n Te rem cree et eens ee tee 3 206 a a e 3 207 oTe a Ee EEE E EATA E E ENA E O E ES 3 209 Vo NOL E E AEEA EEA AES 3 211 lt li e Le aay E E E E ee Ree E E AE A TE AEE T T 3 218 a E e o EAE EPEE EE AE T EAN EEE T ETEN E TA E E AE ET TT 3 227 ESEE E OOR E ISEA E AAN OEN A AI ENEE A EA O A AE AINEA 3 228 T POPPERIN FANOR APT VEA IIIN MOREEN E EITEN A I AO PNA IE AIA AT 3 229 a e E AEA AER 3 230 updat constralnt DiE seirinin en rE AE S 3 232 a Re a EESE S E EAA EN OIIE enna A EN S E I E E 3 233 R a 1 APRENE AEI S EAEN AN AP IN ENE OEE EN 3 234 Chapter 4 How Precision Compiles Designs Hov Pecman Compiles the DENEI is ater anan aE E 4 1 Loa ie et LID sinr AIE RS 4 1 Pa cA Wa Lista tiled e T EE A E EEE A rent A E E E eunernre rine 4 2 Eromi E aa EEE E A aeamiareenteens 4 3 E E E a tae Cenen ceem eel ere nennt ener eer tr eae eet net nen ant Tew erence are teter ryrtr 4 6 How Frocision Synihesizes the re ih 5 seshiviusiineteniehi elena 4 8 naeli bile Raa e L a gape ene er Demet IIIA re eta ene IITE IEPA TE E E eee me AIE IPEA a hee E vr mete 4 10 Dne a ile 10 1h sn a eee eae ee A ere eee ner een 4 10 cas ea es pcg tee encore EAE atc ecw es aes ae edenegieaes 4 10 BE eet 4 10 DEL TO BE a kena srsndeiwid cada bidsviciaki ennai enna piae lbs aneeeesieha dives 4 1 Face iCGs ty cag Apt E etre eee eTs Mere tere S 4 12 Toon o A resto tga ssc cnsn E 4 12 Tey EI A sorts catego sci wasn tis bud and centre ee ein E 4 12 PeP Col 511111 ee ROE cen
192. e default is t rue To set false you should use the following syntax clock false Summary Generate a summary timing report The default 1s true To set false you should use the following syntax summary false num_summary_paths lt integer gt Specifies the number of timing paths that are reported The default is 10 critical_paths Report critical paths The default is true To set false you should use the following syntax critical_paths false num_critical_paths lt integer gt Specifies the number of critical timing paths that are reported The default is 3 timing_violations Report timing violations The default is true To set false you should use the following syntax timing_violations false net_fanout Show net fanout The default is false To set true you should use the following syntax net_fanout true Precision Synthesis Installation Guide 2003c Update 3 209 March 2004 setup analysis Commands clock_domain_crossing Show clock domain crossings The default is false To set true you should use the following syntax clock_domain_crossing true missing_constraints Report missing constraints The default is false To set true you should use the following syntax missing_constraints true Description The setup_analysis command allows you to configure the timing report Related Commands set_working_dir Deprecated report_analysis 3 210 Precision Synthesis Installati
193. e e eea a i ANE ET SSE AA EAA E A 9 38 ere tae R o e e eee ete ieee 9 39 SPLE Dovicer Si erties 9 39 SPa Ler es 101 6 13 1 a E aS 9 40 Ahok CPLD Pomii Devices SUPOT perseri nS 9 40 Precision Synthesis Installation Guide 2003c Update1 March 2004 Table of Contents List of Figures Figure 3 1 Relationship of Edge Position to Initial Value cccennneeteeeeeeeeeeeeees 3 43 ai ica a P a ut eS 3 176 Pome i Te T a ers ieee eden eee eee 3 198 Figure 4 1 Reading Your Input Design aneccstisannasserconsneenateesnaasumbiccansacgsnansnestadanennazensakesadassaeet 4 1 Fomes d Conant FProparaion E omp Esses 4 7 Figure 4 3 Resource Simrin Reili S sercinsnienissiidtinn nei a inina R ipini EONS nE TEA 4 8 Powe a A Piom iy Darrai sne 4 9 Figure 4 5 Simple Circuit before Retiming Slack 0 44 nS ssseseessssssssssrssssssssssseresrsssses 4 14 Figure 4 6 Simple Circuit after Retiming Slack 0 55 ns oe ececccccccceceeeeeeeeeeeeeeeeeeeneas 4 14 Figure 4 7 Enabling the Register Retiming Algorithm 2 0 0 0 cecccccceceeceeneeeeeeesteeeeeeeeees 4 15 Pa es Reset ra C hangos tO PPE ae E ER 4 17 Po D T operetta eene eres 4 19 Figure 5 1 Files im the Project Directory ssissrsrsssrirdsrinrssriisrsdkorsrntntts ktt ti VAn naV NA NAE EE 5 1 Peun d Heonreiuical Projo Pil STUci esne E 5 4 Figure 6 1 Running the Actel Designer Environment esseessssesssssssesereerereressssssssssssssssesee 6 2 Figure 5 4 Sotine ACS Desicener IIe sssisisenseri
194. e file 1s written to the current working directory The rep extension is not required but it identifies the file as a report file If you omit this argument the report is written to the Transcript window summary Generate a summary report all nets Report on all nets in the current design Description The report_net command sends a report on the specified nets to the Transcript window You can specify a file option to write the report to a file 3 146 Precision Synthesis Installation Guide 2003c Update1 March 2004 Commands report_net To execute this command from the GUI you can right click on the Nets folder in the Design Hierarchy pane and select Report Nets Related Commands report_area report_missing_constraints report_attributes report_timing report_library Precision Synthesis Installation Guide 2003c Update 3 147 March 2004 report_output_file_list Commands report_output_file_ list Return a list of the current output files Example report_output_file_list count Syntax report_output_file list count impl lt implementation_name gt Options count Returns the number of files in the output_file_list impl lt implementation_name gt Specifies the name of an implementation on which to report Only the implementation leafname may be specified Description The report_output_file_list command returns a list of the files that are in the output_file_list of the activ
195. e is a default waveform is assumed that has a rise edge of 0 0 and a fall edge of period_value 2 If an edge position occurs at zero then the waveform transitions away from the initial level of zero effectively making the initial edge falling instead of the default value of rising If an edge position occurs at the clock period then the waveform transitions toward the initial level of zero design lt rtl gatelevel gt Tells the tool whether to look for the object in the RTL or the gatelevel view Description The create_clock command adds or enables the editing of a root clock definition in the current design This command can be used to define a root clock A root clock can be an external clock applied to an input port of a circuit a clock signal that is applied to an internal pin of the circuit or a virtual clock signal Note that using create_clock on an existing clock overwrites the Precision Synthesis Installation Guide 2003c Update 3 41 March 2004 create_clock SDC Commands attributes previously set on the clock object Precision Synthesis uses two different types of clocks Real Clocks are clock definitions that apply to actual ports or instance pins within the design These types of clocks are used to define clock information for internal registers latches memories and blackboxes Virtual Clocks can be created to represent an off chip clock for input or output delay specification If no lt port_pin_list gt
196. e or optionally specified implementation Status information is also provided such as the position of the file in the list the full file pathname the file type and the name of the work library into while the file will be compiled If you specify the count switch only the number of files in the output_file_list is returned Related Commands report_input_file_list 3 148 Precision Synthesis Installation Guide 2003c Update March 2004 Commands report_project Generate a report on the current project Example report_project Syntax report_project libname manufacturer family part speed package cim btw addio vhdl1 verilog edif vhdl_filename verilog_filename edif_filename constraint_filename vendor_constraint_file design architecture basename lt string gt frequency input_delay output_delay search_path retiming transformations resource_sharing advanced_fsm_optimization operator_preserve lt string gt Options libname report_project Returns the name of the current technology library This name is specified in the file that is located at the following pathname lt precision install directory gt pkgs psr techlibs devices ini Precision Synthesis Installation Guide 2003c Update March 2004 3 149 report_project Commands manufacturer Returns the manufacturer s name of the current technology
197. e set number of PT For example if the value is set to 35 the Optimizer stops collapsing equations when it exceeds 35 PT This option works the opposite of Splitting Max Product Term max_pterm_limit lt string gt max_fanin lt string gt Specifies the maximum fanin max_symbols lt string gt fmax_logic_levels lt string gt Lattice isoLEVER ORCA Command Names cl default Run the vendor place and route flow in the background command line mode Use the options specified in the setup_place_and_route command Send a transcript of the executed commands to the Transcript window 3 106 Precision Synthesis Installation Guide 2003c Update March 2004 Commands place_and_route gui Invoke the ispLEVER ORCA Graphical User Interface GUI gen_vecf Write a Vendor Constraint File to the active implementation directory Lattice isoLEVER ORCA Command Arguments install_dir lt vendor_installation_directory_pathname gt Specifies the pathname to the ispLEVER installation tree for example C ispTOOLS NO exeCc This option is primarily used to debug the Precision place_and_route script that drives the implementation tools The commands in the script are echoed to the Precision Transcript window without the commands actually being executed by the implementation tools op_for spdys sdpnol spdfmax spdyes speed yes Collapses all nodes up to the set Product Term limit globally optimized without regard f
198. e v Syntax auto write lt file name gt format lt format name gt downto PRIMITIVES silent single_level design lt design_name gt Type Arguments string lt format_name gt lt design_name gt lt file name gt Arguments lt file_ name gt Name of the output file file_name can be a local filename a relative path name or an absolute path name If you use a dash character for file_name the output appears on the standard output screen Always use the forward slash character to separate directory names in a path even on the PC Precision interprets the back slash character as a TCL escape character Options format The format of the output file Valid values are as follows edif sdf verilog vhdl and xdb If you omit this option Precision determines the file format based on the file extension as shown in the following table Table 3 9 File Format mapping for auto_write command File Extension File Format edf edif eds 3 32 Precision Synthesis Installation Guide 2003c Update1 March 2004 Commands auto_write Table 3 9 File Format mapping for auto_write command File Extension File Format If the output file has a filename extension that the auto_write command does not recognize you must specify the format explicitly downto PRIMITIVES Do not write technology cells in the output netlist With this option Precision writes the design in ve
199. ePCB ATK Zeelan Zero Tolerance Verification and Libs are trademarks or registered trademarks of Mentor Graphics Corporation or its affiliated companies in the United States and other countries The following are service marks of Mentor Graphics Corporation A World of Learning ADAPT AppNotes Assess2000 BIST Compiler BIST In Place BIST Ready Concurrent Board Process DirectConnect ECO Immunity EDGE Engineering Design Guide for Excellence Expert2000 FastTrack Consulting IntraStep ISD Creation It s More than Just Tools Knowledge Center Knowledge Sourcing Mentor Graphics Support CD Mentor Graphics SupportBulletin Mentor Graphics SupportCenter Mentor Graphics SupportPax Mentor Graphics SupportNet Email Mentor Graphics SupportNet FTP Mentor Graphics SupportNet Telnet Mentor Graphics We Mean Business MTPI Online Knowledge Center OpenDoor Reinstatement 2000 SiteLine2000 SupportNet KnowlegeBase Support Services BaseLine Support Services ClassLine Support Services Latitudes Support Services OpenLine Support Services PrivateLine Support Services SiteLine SupportServices TechLine Support Services RemoteLine and VR Process Mentor Graphics trademarks may only be used with express written permission from Mentor Graphics Fair use of Mentor Graphics trademarks in advertising and promotion of Mentor Graphics products requires proper acknowledgement Nutcracker is a registered trademark of MKS Mentor sometimes refers
200. ecision Synthesis Installation Guide 2003c Update 3 51 March 2004 exit Commands exit Exit from the current session of Precision Example exit Syntax exit force Options force Force the exit immediately without issuing a prompt and without saving the workspace Description The exit command is primarily a command that is used by the GUI to exit the current session A prompt messages 1s to issued in the GUI asking if you really want to exit The force switch forces an immediate exit This command is also aliased with the quit command Related Commands 3 52 Precision Synthesis Installation Guide 2003c Update March 2004 Commands export_settings export_settings Saves export implementation settings to a TCL script Example export_settings uartdsgn tcl Syntax export_settings lt file name gt lt file name gt Arguments lt file name gt The pathname of the file where implementation settings are to be saved Description The export_settings command is used to save the current implementation file list and settings to a TCL script Related Commands Precision Synthesis Installation Guide 2003c Update 3 53 March 2004 find Commands find Find the specified objects in the in memory design Example 1 find gen Find all objects with the sub string gen in the name Example 2 set_input_delay 7 find arbit port Apply an input delay of 7 ns to all ports that con
201. ecision tcl Precision Synthesis Installation Guide 2003c Update 5 5 March 2004 Precision Initialization File 5 6 Files Reference Precision Synthesis Installation Guide 2003c Update1 March 2004 Chapter 6 Designing with Actel Devices Actel Designer Integration As shown in Figure 6 1 the Actel Designer environment is integrated into the Precision RTL Synthesis environment After Synthesis the technology mapped design is written to the current implementation directory as an EDIF netlist file along with an Actel Designer Command File To run the automated Place and Route flow just click the Place amp Route icon in the Actel Designer Tool Bar Actel Designer uses the current implementation directory as the Actel Designer project directory After the design is compiled you may invoke the Actel Designer GUI manually and open the project From that point you can view reports run analysis tools and manually drive the physical implementation to completion Precision Synthesis Installation Guide 2003c Update 1 6 1 March 2004 Actel Designer Integration Designing with Actel Devices Figure 6 1 Running the Actel Designer Environment tt simplemath Mentor Graphics Precision Physical Synthesis Design Center Pa File View Tools Window Help Actel ACT A10104 2 44 PLCC Frequency 180 MHZ Ela Project simplemath simplemath main _ RTL Design Analysis z ERS Empl simplemath_impl_1 1 mA Clocks lick to launc
202. ectively disable retiming For example set attribute reg_dat25 instance name DONT_TOUCH value TRUE set_attribute dat25 net name PRESERVE SIGNAL value TRUE Attributes can also be set in the source VHDL attribute PRESERVE SIGNAL boolean attrib te PRESERVE SIGNAL OF Gat25 signal ts true Or in Verilog Wire dat25 exemplar attribute dat25 PRESERVE_SIGNAL true 4 16 Precision Synthesis Installation Guide 2003c Update March 2004 How Precision Compiles Designs How Precision Synthesizes the Design Retiming Rules For retiming to occur it must be possible to perform the transformation without modifying the function of the circuit at the boundary pins An important consideration 1s that the initial state reset state of the register be maintained Additionally it is important that design latency not change the same number of register stages must exist before and after retiming For retiming to occur the following must be true Registers must have the proper timing budgets to be retimed One example is having positive slack in on one side and negative slack on the other All inputs of a LUT must have registers for a move to be possible to maintain latency Registers with both set and reset cannot be retimed While control signals must be consistent to allow retiming control signals may change based on the function of the combinatorial logic In Figure 4 8 you see an example of retiming a register thro
203. ed by a clock set_max_fanout SDC Limit the maximum number of pins that a net or port can drive set_min_delay SDC Set the minimum total path delay for a timing path that is constrained by a clock set_multicycle_path SDC Modify the single cycle timing relationship of a constrained path set_output_delay SDC Set output delay on output ports or pins relative to a clock set_propagated_clock SDC Specifies the cell delays in the clock network should be used Precision Synthesis Installation Guide 2003c Update 3 13 March 2004 Command Summary Commands Table 3 8 Precision Physical Commands add_macro_file Add one or more file s to the macro_file_list add_placement_file Add one or more placement file s to the design create_path_definition_set Define and add a Path Definition Set which is a set of from through and to lists delete_path_definition_set Deletes a previously defined Path Definition set or all sets get_path_definition_set Returns a previously defined Path Definition set physical_synthesis Perform physical timing optimization and placement improvement on a design precision A shell level command that invokes Precision RTL Synthesis as well as Precision Physical Synthesis save_path_definition_sets Saves the defined Path Definition sets into an external file save_physical Saves the in memory physical database to the active implementation directory view_floorplan Invoke PreciseView on the c
204. ed to a domain called main Clocks in the same domain are considered synchronous All clocks originating from the same physical source such as a crystal based clock generator or a single clock port on an IC should be assigned to the same domain Clocks in different domains are considered asynchronous having no phase or frequency relationship Clocks that do not originate from the same common source or do not interact in the design should be assigned to different domains name lt clock_name gt Sets the clock name The clock name is specified as a unique string of characters Although you can use any name for the clock the user interface defaults to the port name for top level clocks and the net name of the driving instance for internal clocks If you fail to specify a name from the command line entry Precision Synthesis will name the clock virtual_default waveform lt edge_list gt Sets the rise and fall edges of the clock signal over an entire clock period There must be a non zero even number of edges and they are assumed to be alternating rise and fall The first value in the list is a rising transition typically the first rising transition after time zero The position of any edge can be equal to or greater than zero but must be equal to or less than the clock period The position of each edge is specified as a floating point number in library units If waveform edge_list is not specified but period period_valu
205. efault Speed Grade 6 Speed Grades supported 6 7 10 12 8 20 Precision Synthesis Installation Guide 2003c Update March 2004 Designing with Altera Devices Altera Devices Supported Devices Supported EPM7128A LC84 LI84 TC100 TI100 FC100 TC144 T1144 FC256 EPM7256A C100 TI100 TC144 T1144 QC208 QI208 FC256 FI256 MAX 7000AE Family Default Speed Grade 4 Speed Grades supported 4 5 6 7 10 12 Devices Supported EPM7032AE LC44 TC44 TI44 EPM7064AE LC44 LI44 TC44 TI44 TC100 TI100 FC100 EPM7128AE LC84 TC100 TI100 FC100 FI100 TC144 T1144 FC256 EPM7256AE QC208 QI208 TC100 TI100 FC100 FI100 TC144 T1144 FC256 FI256 EPM7512AE C144 QC208 QI208 FC256 FI256 BC256 BI256 MAX 7000B Family Default Speed Grade 3 Speed Grades supported 3 4 5 6 7 10 EPM7256B C100 FC100 TC144 UC169 QC208 QI208 FC256 FI256 EPM7512B C144 UC169 QC208 BC256 FC256 FI256 MAX 7000E Family Default Speed Grade 7 Speed Grades supported 7 10 10P 12 12P 15 20 Precision Synthesis Installation Guide 2003c Update 1 8 21 March 2004 Altera Devices Supported Designing with Altera Devices EPM7256E QC160 RC208 RI208 GC192 GI192 EPM7256S RC208 RI208 QC208 EPM9320 LC84 LI84 RC208 RI208 GC280 BC356 ALC84 ALI84 ARC208 ARI208 ABC356 EPM9400 LC84 RC208 RC240 EPM9480 RC208 RC240 EPM9560 RC208 RI2Z08 RC240 RI240 RC304 RI30
206. egin process clk rst begin if rst 1 then a_int lt others gt 0 b_int lt others gt 0 product_int 0 lt others gt 0 for i in 1 to level 1 loop product_int i lt others gt 0 end loop elsif clk event and clk 1 then a_int lt signed a b_int lt signed b product_int 0 lt a_int b_int for i in 1 to level 1 loop product_int i lt product_int i 1 end loop end if end process product lt std logic vector product int level 1 6 8 Precision Synthesis Installation Guide 2003c Update March 2004 Designing with Actel Devices Constraining for Synthesis and Layout The following table demonstrates results from synthesizing a 16 bit by 18 bit multiplier targeting the AX250FG256 in the 1 speed grade using MIL operating conditions Note that these results are from unconstrained synthesis and layout runs Better results may be achieved with constraints The data illustrates the potential benefit from pipelining when R cells are not in short supply they can be put to good use in balancing delay through the multiplier Note that the number of C cells remains unchanged as synthesis is merely adding extra pipelining stages into the existing operator implementation In this way a 73 increase in overall clocking frequency is achievable with only a 19 increase in overall logic cells Table 6 1 Comparing area vs delay for various multiplier implementation
207. el Devices Designing with Actel Devices Actel Flash Devices Supported ProASICPLUS Family ProASICpius Family 9 ProASIC a500k Family ProASIC a500K Family Speed Grades supported STD Devices Supported AS00KO050 PQ208 PQ208I1 BG272 BG2721 A500K130 PQ208 PQ208I BG272 BG272I BG456 BG456l AS500K180 PQ208 PQ208I BG456 BG456I AS500K270 PQ208 PQ208I BG456 BG456I 6 12 Precision Synthesis Installation Guide 2003c Updatet March 2004 Designing with Actel Devices Supported Actel Devices Actel Antifuse Devices Supported Axcelerator Family AX2000 FG896 FG1152 Precision Synthesis Installation Guide 2003c Update 6 13 March 2004 Supported Actel Devices Designing with Actel Devices 54SXA Family 4SXA Family Speed Grades supported 1 2 3 STD Devices Supported A54SX08A FB144 PQ208 TQ100 TQ144 A54SX16A FB144 FB256 PQ208 TQ100 TQ144 A54SX32A BG329 CQ208 CQ256 FB144 FB256 FB484 PQ208 TQ100 TQ144 TQ176 AS54SX72A CQ208 CQ256 FB256 FB484 PQ208 54SX Family 4SX Family Default Speed Grade 3 Speed Grades supported 1 2 3 STD Devices Supported A54SX08 FB144 PL84 VQ100 TQ144 TQ176 PQ208 A54SX16P _ VQ100 TQ176 CQ208 PQ208 PQ240 CQ256 VQ100 TQ 144 TQ176 PQ208 A54S X32 TQ144 TQ176 CQ208 PQ208 CQ256 BGA313 BGA329 RT54SXS Family RT54SX72S COFP208 CQFP256 6 14 Precision Synthesis Installation Guide 2003c Updatet March 2004
208. ently used aliases and Tcl procedures And because this file is in your home directory you can update your Precision Synthesis software tree without overwritting this file Command Syntax Definitions The command list character symbols are defined as follows optional arguments lt gt fields to be completed with your names or symbol indicates mutually exclusive arguments In the read command the add_input_file lt file_pathname s gt field is replaced with your file pathname s For example add_input_file fsm vhd datapath vhd top vhd In this case only the file leaf names are specified so the files are assumed to be in the current working directory You should always use the forward slash character to separate directory names in a path even on the PC Precision Synthesis interprets the back slash character as a Tcl escape character Precision Synthesis Installation Guide 2003c Update 1 1 5 March 2004 The Design Data Model Introduction Precision Synthesis turns your HDL code into an in memory design data base while Schematic Viewing provides a tool for exploring and interacting with this design data base The following section provides a brief tour of the design database and describes methods for using commands on the interactive Command Line Shell The Design Data Model The Precision Synthesis in memory design data base is modeled after the EDIF design data model All design data is stored in a
209. ents List of Tables Table 221s Alphabetical Attribute SUmniary eves etncdatasrit ied nani eres 2 1 Mel ee Tose itl N eannne een anne tenn lear ee eee nnitne eee Or arr Ene TE nny tener neeneer ener ever OnE yn toners 2 4 Tee ee saa schacaieneioeiaperes ects nea an ee eae 2 4 Ra Te eG Satine canaries setae E S E E E 2 5 Table 2 5 dedicated multi attributes 00esessseeeseresesscssesecscsssesesssesossscsesssesesssseeresseseseresesese 2 12 Table 3 1 Alphabetical Command Summary cicsiicsassccsccivistcanncazateoieicevasnsaatinstbentenstansissaeentorts 3 1 Table 3 2 Project and File Management Commands iiccnascemnrterminenieemniaiensanedes 3 8 TaD coy COn OAE ea EE a EREE 3 9 Ae yanes carrie isis R 3 9 I eee cise metered aerate a nieneniciie items 3 10 Tabie S C 8 OS en nearer 3 11 EED tc a ree ey etnies ieee 3 12 Table 3 8 Precision Physical Commands 5 0ss lt oessiaccssersecesesessserseveaiarbinrnnieanriescserisandeeervaseanss 3 14 Table 3 9 File Format mapping for auto_write command cccceccesssseseeeeeeceeaeseeeseeseeees 3 32 Table 4 1 Technologies Supported by Register Retiming ccesesesceeceeceeeeseeeeseseeees 4 13 Tapo l Moo rie E E aa etnies steno eee artes 5 2 Table 3 2 Prec son S peche TIES srsssidEsiron innir reinste ani AARI E aR eE nAn TAES 5 3 Toeto Cun Pie EEES serrr a CET nent sr nnaent ame remeron et hey ity tt ee 5 3 Table 6 1 Comparing area vs delay for various multiplier implementations
210. er you should check Actel documentation for further information Standard Standard layout maximizes the average performance for all paths Standard layout treats each part of the design equally for performance optimization Standard layout uses net weighting or criticality to influence the results Timing Driven The primary goal of Timing Driven layout is to meet delay constraints set in Timer an SDC file Axcelerator family only a DCF file non Axcelerator families or a GCF file for ProASIC and ProASICpLus devices Timing Driven layout s secondary goal is to produce high performance for the rest of the design Delay constraint driven design is more precise and typically results in higher performance Note Timing Driven Layout is only available if you have entered timing constraints in the Precision tool 6 4 Precision Synthesis Installation Guide 2003c Update1 March 2004 Designing with Actel Devices Actel Designer Integration Extended Layout Runtime Mode Extended run attempts to improve the layout quality by using a greater number of iterations during optimization An extended run layout can take up to 5 times as long as a normal layout Note This advanced option is available for all ONO Families Effort Level This variable specifies the duration of the timing driven phase of optimization during layout Its value specifies the duration of this phase as a percentage of the default duration The default value is 100 and
211. er of this Agreement shall be entitled to recover in addition to other relief reasonable attorneys fees and expenses Rev 020826 Part Number 214231 Trademark Information The following are trademarks of Mentor Graphics Corporation 3D Desion ABIST Arithmetic BIST Accelerated Technology AccuPARTner AccuParts AccuSim ADEPT ADVance ADVance MS ADVanceRFIC AMPLE Analog Analyst Analog Station Ares ARTerid ArtRouter ARTshape ASICPlan ASIC Vector Interfaces Aspire AuthEx press AutoActive AutoCells AutoDissolve AutoF ilter AutoPlow AutoLib AutoLinear AutoLink AutoLogic AutoLogic BLOCKS AutoLogic FPGA AutoLogic VHDL AutomotiveLib AutoPAR AutoTherm AutoTherm Duo Auto ThermMCM AutoView Autowire Station AXEL AXEL Symbol Genie BISTArchitect BLAST Blaze BlazeRouter Board Station Consumer Board Architect Board Designer Board Layout Board Process Library BoardSim Board Station BOLD Administrator BOLDBrow ser BOLD Composer BSDArchitect BSPBuilder Buy on Demand Cable Analyzer Cable Station CAECO Designer CAEFOR M Calibre Calibre DRC Calibre DRC H Calibre DESIGNrev Calibre CB Calibre PFRACTUREh Calibre FRACTURE Calibre PFRACTUREm Calibre FRACTURE Calibre PFRACTURER Calibre LITHOview Calibre LVS H Calibre MTflex Calibre OPCsbar Calibre OPCpro Calibre ORC Calibre PRINTimage Calibre PSMegate Calibre PSMcheck Calibre TDope Calibre WOR Kbench Calibre RVE Calibre MGC
212. es Verilog pragma attribute rst_int preserve_driver true VHDL attribute preserve_driver boolean attribute preserve_driver of rst_int signal is true Interactive Command Line Shell set attribute net rst_int name preserve_driver value true preserve_signal Preserves the specified signal in the design Specifies that the signal must survive synthesis Verilog pragma attribute rst_int preserve_signal true VHDL attribute preserve_signal boolean attribute preserve_signal of rst_int signal is true Interactive Command Line Shell set_attribute net rst_int name preserve_signal value true preserve Z Prevents tri states from being mapped to MUX logic Tri state logic is used for two primary purposes when designing FPGAs bi directional IO ports and to implement internal busses with multiple drivers In the case of the latter the tri state logic is used rather than a MUX structure to save chip area which typically comes at a performance cost For this reason Precision will automatically convert tri state logic on critical paths into MUX structures which will generally improve performance Verilog pragma attribute data_sum preserve_z true 2 20 Precision Synthesis Installation Guide 2003c Updatet March 2004 Attributes Pre Defined User Attributes VHDL attribute preserve_z string attribute preserve_z of data_sum signal is true Interactive Command Line Shell set attribu
213. es and other costs related to the action upon a final judgment 9 4 THIS SECTION 9 STATES THE ENTIRE LIABILITY OF MENTOR GRAPHICS AND ITS LICENSORS AND YOUR SOLE AND EXCLUSIVE REMEDY WITH RESPECT TO ANY ALLEGED PATENT OR COPYRIGHT INFRINGEMENT OR TRADE SECRET MISAPPROPRIATION BY ANY SOFTWARE LICENSED UNDER THIS AGREEMENT TERM This Agreement remains effective until expiration or termination This Agreement will automatically terminate if you fail to comply with any term or condition of this Agreement or if you fail to pay for the license when due and such failure to pay continues for a period of 30 days after written notice from Mentor Graphics If Software was provided for limited term use this Agreement will automatically expire at the end of the authorized term Upon any termination or expiration you agree to cease all use of Software and return it to Mentor Graphics or certify deletion and destruction of Software including all copies to Mentor Graphics reasonable satisfaction EXPORT Software is subject to regulation by local laws and United States government agencies which prohibit export or diversion of certain products information about the products and direct products of the products to certain countries and certain persons You agree that you will not export any Software or direct product of Software in any manner without first obtaining all necessary approval from appropriate local and United States government agencies RESTRICTE
214. es to a cell and the VHDL architecture contents translates to a view By default the cell is stored in an EDIF style library called work by default You can change the name of this library if you wish Many standard VHDL libraries and packages are build into Precision Synthesis and don t have to be specified in the Open file list If your design references custom libraries and packages then you must Open these package source files for reading before your design files are read The methods for doing this are fully discussed in the Precision Synthesis HDL Style Guide starting on page 4 4 When you load a technology library into Precision Synthesis it becomes an EDIF type library in the design database which contains all of the cells of that technology Your design in the work library will reference this technology library as an external EDIF library Precision Synthesis creates an EDIF style library of PRIMITIVES automatically This library represents all primitive logic functions that Precision Synthesis may require when compiling or elaborating HDL VHDL and Verilog descriptions Precision Synthesis also automatically creates an OPERATORS library This library contains operator cells adders multipliers muxes When compiling HDL descriptions these operators are generated when needed Precision Synthesis Installation Guide 2003c Update March 2004 How Precision Compiles Designs Understanding the In Memory Design Data PRIMITIVE
215. esign Generally speaking you do not need to read this chapter to be able to use Precision on a design How Precision Compiles the Design After the libraries and packages are loaded design files are compiled in a two phase process First a file 1s analyzed checked for proper syntax then elaborated synthesized into an in memory database composed of generic gates and black box operators The compile command does both analyze and elaborate automatically Precision Synthesis inputs your design when you click on the Compile button As shown in Figure 4 1 the compile is accomplished in four phases load technology library analyze elaborate and pre optimize Figure 4 1 Reading Your Input Design RTL generic gate design Working Directory Load the Technology Library In order for Precision to recognize technology cell instantiations and map your design to a specific technology Precision must first load the library This library includes the technology Precision Synthesis Installation Guide 2003c Update 4 1 March 2004 How Precision Compiles the Design How Precision Compiles Designs specific cell definitions custom operator implementation and symbol libraries Precision provides a number of FPGA libraries with Precision from Actel Altera Lattice Xilinx and many other vendors These technology libraries contain information about both the library cells names ports functions timing pin loading and global libra
216. esign default or of the specified design Example view_schematic rtl Displays an RTL schematic of the current design Syntax view_schematic lt design_name gt symlib lt symbol_library_name gt rt1 clone log lt logfile_pathname gt string lt design_name gt lt symbol_library_name gt lt logfile_pathname gt Arguments lt design_name gt Name of the design for which to display the schematic Options symlib lt symbol_library_name gt Specifies the pathname of the symbol library file ril Display the RTL schematic for the named design clone Clone the schematic 1f it is already displayed log Log the schematic viewer command to the specified file Description The view_schematic command is primarily used by the GUI to display a schematic of the current design You can also use the command to invoke the schematic viewer manually from the Interactive Command Line Shell 3 234 Precision Synthesis Installation Guide 2003c Update1 March 2004 Commands view_schematic Related Commands Precision Synthesis Installation Guide 2003c Update 3 235 March 2004 view_schematic Commands 3 236 Precision Synthesis Installation Guide 2003c Update March 2004 Chapter 4 How Precision Compiles Designs This chapter provides information for more advanced usage of Precision This information is intended to explain some of the underlying actions taken by Precision as it synthesizes a d
217. essucsceccetosccscessesevecssercerescetsesercoecs 2 12 ATH ME No 0 EN gt Ree ea mR Eee EE ee Peers ATE ROE e ORNS PERIMETER Oe a 7 ee CeO en Se aCe 2 13 a EO 16 eee ee Menor e ne anee EME MET MORES ET ONE Pee rrnr eet eneyeNrneyent rete ver sree ted ereeeet rrr reer ee rite a oreteekre eerie ree 2 13 11 oe Tn ee em NAAA E eee Sener eee ee E IA AT rere AAE E E ere errr 2 14 S110 OLE a en on ee eee ee Ore enn ee nee NS a ene eae Tee emer em re TT nr 2 14 apace cist nearness E EEE ER 2 14 11 Ran Eee eMC anna een Ertan nT ER smanee A E tiene rarer rcone heaven rer te wien l nr errete Mertens ener ere 2 15 e LMR eos Ea al ck De eee ere ne OPE E oe AEE ART nner nan ner ETTA ee 2 15 BO seperate aac gent one sae sagan dns E E 2 16 e a 1a PEIE IEAA EA E AO E IE AAAA A E AEA A 2 16 DEO E ra T EA A AAE TE NT 2 17 max ce arenes as cco neces osc TEE eee 2 17 Precision Synthesis Installation Guide 2003c Update 1 lil March 2004 Table of Contents Table of Contents cont 182 ee ee a eae eee eae ee eee ee AEA ane ERTE Ree EE ee ne mee Te tere ee 2 17 1 5 2121 EE EE AIS OR E ORANET ET eee ent Te Neem ROME ey EET VOORTAAN ea TUN Cer AE PAAA rey te an 2 18 S11 A ee ee ene E POA re TEA nme eer I eer eer eter ee arene eee eer ne eee meer ee ter 2 18 cra tegen cians enna E E E 2 19 e Ree CSM ere ERE TE EI een E EEIE eer terre see Mame E Mer wen Meer ES A tent er nr E E ore creme 2 19 Do KK 8 ot a te wen Petre ReleCar ee mMERe rar tye tre Te
218. esults directory is not set impl_comment lt active_implementation_comment gt Deprecated option use set_impl_property comment command instead Specifies a value for comment property on the active implementation in the Project Browser You may also specify an inactive implementation for example setup_design impl_comment smallest impl filter_impl_3 increment Deprecated option use copy_impl command instead Tells Precision Synthesis to make a copy of the active implementation Precision first saves any changes in the active implementation then makes a copy of it and finally activates the new implementation input delay lt input_delay_value gt Specifies the global input delay in ns This is normally set when the user enters an Input Delay value from the Setup Design dialog box This optional default value serves as a starting point for setting I O constraints After the Compile step you will be able to select each I O port in the Design Hierarchy pane and adjust the constraint accordingly list_technology Sends a list of all known synthesis libraries in the Transcript window manufacturer lt manufacturer s_name gt Manufacturer s name as specified in the file lt precision install directory gt pkgs psr techlibs devices ini This argument is normally specified when the user selects the technology from the Setup Design dialog box in the GUI However if you prefer you can generate a list of supported
219. esults_dir setup_analysis Setup the PreciseTime timing report 3 6 Precision Synthesis Installation Guide 2003c Update March 2004 Commands Command Summary Table 3 1 Alphabetical Command Summary continued Command Description setup_design Setup the design environment setup_place_and_route Setup the place and route environment synthesize Synthesize the current in memory design Create a temporary file in the system s temporary file directory tmpfile unalias Remove the specified alias Flatten out the hierarchy NOTE This is an advanced command that should only be used from a script after ungroup all constraints have been applied to the in memory design Update the output constraint file with the constraints update_constraint_file that have been entered during the current session Invoke Precise View on the current in memory physical database view_floorplan view_schematic Display a schematic view of the current design default or of the specified design Precision Synthesis Installation Guide 2003c Update 3 7 March 2004 Command Summary Commands Functional Command List Table 3 2 Project and File Management Commands Activate the specified implementation add_input_file Add one or more file s to the input_file_list close_results_dir Unload the currently loaded design Available only when no project is open copy_impl Create a copy of an existing implementation within the proje
220. et this attribute in Precision set it on the flop Each design object is able to inherit radhardmethod attributes from it s parent In addition a radiation hardened implementation can be set for the entire design by issuing the command setup_design radhardmethod one of ce tmr tmr_cc or none Precision RTL Synthesis offers the highest possible level of control over radiation hardened implementation by allowing the designer to tailor attributes per design object instance This method provides significantly better control than competing solutions which only allow setting one implementation method for all instantiations of a design object by instrumenting synthesis metacomments in the HDL code Not only does the Precision RTL Synthesis solution remove the dependency on instrumenting HDL code by allowing attributes to be set in TCL scripts the implementation offers far more flexibility in exploring trade offs with highly folded designs 6 6 Precision Synthesis Installation Guide 2003c Update March 2004 Designing with Actel Devices Targeting Pipeline Multipliers Example TCL constraints set_attribute name radhardmethod value tmr_cc instance Ul reg_dataout Setting attribute on a module set_attribute name radhardmethod value tmr instance U2 Setting RadHard method for the entire design setup_design radhardmethod cc Example Verilog Code Setting the attribute on a reg through a Verilog synthe
221. et_attribute net data_sum name buffer sig type string value ibuf Precision Synthesis Installation Guide 2003c Update 2 11 March 2004 Pre Defined User Attributes Attributes dedicated mult Specifies that an instance should be mapped to the dedicated multiplier resource in place route The values for the dedicated_mult attribute are different depending on what technology you are using Table 2 5 dedicated_multi attributes attribute Xilinx Altera value Maps to Block pm_mult_someNumber cell with the Altera Multiplier default DEDICATED_MULTIPLIER_CIRCUITRY attribute set to YES OFF Maps to LUT s lpm_mult_someNumber cell with the Altera DEDICATED MULTIPLIER CIRCUITRY attribute set to NO AUTO No Affect Ipm_mult_someNumber cell without the Altera DEDICATED MULTIPLIER CIRCUITRY attribute LCELL No Affect implementation using LCELLs rather than a Ipm_mult_someNumber cell Verilog pragma attribute dl dedicated_mult AUTO VHDL attribute dedicated_mult string attribute dedicated_mult of dl signal is OFF attribute dedicated_mult of d2 signal is ON Interactive Command Line Shell set_attribute name dedicated mult value OFF instance mult_inst modgen_mult_0 2 12 Precision Synthesis Installation Guide 2003c Updatet March 2004 Attributes Pre Defined User Attributes dont retime Specifies that the Retiming algorithm can be disabled on a register by register basis or on a modu
222. et_multicycle_path SDC set_input_delay SDC report_missing_constraints set_output_delay SDC 3 170 Precision Synthesis Installation Guide 2003c Update March 2004 Commands set_clock_uncertainty SDC set_clock_uncertainty SDC Specify the source and destination clocks to calculate inter clock uncertainty between defined clocks Example set_clock_uncertainty sysclk setup rise 2 set_clock_uncertainty sysclk setup fall 2 5 Syntax set_clock_uncertainty lt value gt object_name from lt cilock 11st to lt clock list gt rise fall setup hold design rtl gatelevel lt object_name gt lt clock_list gt Arguments lt value gt Number of nanoseconds for the skew value object_name List of defined clocks specified with the create_clock command Options from lt clock_list gt Specify source clock to calculate inter clock uncertainty between defined clocks This option only applies if the source and destination registers are clocked by different defined clocks to lt clock_list gt Specify destination clock to calculate inter clock uncertainty between defined clocks This option only applies if the source and destination registers are clocked by different defined clocks Precision Synthesis Installation Guide 2003c Update1 3 171 March 2004 set_clock_uncertainty SDC Commands rise Specify uncertainty for rising clock edge of the destination
223. et_output_delay SDC Commands constraint output delay ad dea outside current aesign virtual circuit Logic Cloud data _out clock period 10 ns set_output_delay clock clkl 4 data out What this Command Does The set_ouput_delay command adds an output delay constraint to the specified output port or pin The constraint specifies the amount of delay from the reference clock transition to the time that the rising and falling edges of the data signal arrive at the specified output data pin s Output ports are assumed to have zero output delay unless otherwise specified The reference clock which could be a virtual clock must be defined prior to executing this command For inout bidirectional ports you can specify the output delay with this set_output_delay command and specify the input delay with the set_input_delay command To describe a path delay from a level sensitive latch you should use the level_sensitive option If the latch is positive enabled set the input delay relative to the rising clock edge if it is negative enabled set the input delay relative to the falling clock edge If time is being borrowed at that latch add that time borrowed to the path delay from the latch when determining output delay You can use the report_constraints command to list the output delays associated with ports Related Commands set_input_delay SDC report_attributes set_false_path SDC report_missing_constraints
224. evel EDIF netlist 2 Ifa ngc file is added to the input file list but is excluded from compile ngc2edif is not launched Instead a copy of the file is placed in the implementation directory in the usual manner for excluded files 3 By default a ngc file added to the input file list is excluded from compile on HP platform Input Files GUI View HP Platform The following figure shows an example of how hierarchical coregens look on an HP system after following the steps described in the previous section Figure 9 5 Coregen files after compilation slins VIR TES A 40c 44 gt 6 Frequency 1 MHZ Project Files Design Hierarchy E E Project Files H 4 cam only INTERFACE A cam only impl 1 Fl Clocks a cam_ only impl 2 E E Ports a a pi Files H B Mets EM cam_cam_encode_ ndF H E Instances i cam cam input_i ndF Blocks a Ei cam_cam_control_3 ndr CI carn Ee H B Pins H B Mets i I Instances m D H Flip Flops ib are l E Blocks i rer Constraint Files l H 4 BUZ cam_cam_inpuk_1 LI Script Files BUSS fram cam encode 7 J E Output Files ae BUS96 fcam cam control 3 e e eenig 3 Infos 4 Netlist files added to input file list Netlist file conversion smatic with their own icon but excluded manually preformed ort from compile such that they are just by the user ndf files added to input file list PA Mi saim aba copied to implementation directory for exp
225. f each through_list in the order the lists were given In other words the path must first pass through a member of the first through_list then through a member of the second list and so on for every through_list specified If you use the through option in combination with the from or to options the maximum delay applies only if the from or to conditions are satisfied and the through conditions are satisfied You cannot use hierarchical cell names as through points You should use hierarchical pins on a cell instead rise fall Specifies whether endpoint rising or falling delays are delays that are constrained If neither rise nor fall is specified then both are constrained reset_path Tells PreciseTime to remove existing point to point exception information on the specified paths Only information of the same rise fall type is reset design lt rtl gatelevel gt Tells the tool whether to look for the object in the RTL or the gatelevel view Description The set_max_delay command is a point to point timing exception command that overrides the default single cycle timing relationship for one or more timing paths Other point to point timing exception commands include set_multicycle_path SDC set_min_delay SDC and set_false_path SDC This command specifies that the maximum path length for any start point in from_list to any endpoint in to_list must be less than delay_value Individual maximum delay ta
226. f the current design If set specifies the groups of pins through which a path must flow in order to be considered false One or more pin names can be specified A pin name is specified as a string that must contain the hierarchical path and netlist name of the pin The use of asterisk and question mark wildcard characters is supported Asterisks within pathnames are evaluated as wildcards within a single hierarchy level If multiple pins or instances are specified then only those paths that include at least one pin are considered false The order of the pins specified does not have to match the order of the pins in the path to lt to_list gt If set specifies the end points clocks ports pins or cells of paths to be disabled during timing analysis To points can include clocks pins or instances Any number of to points can be specified One or more names can be specified All paths that end at the data outputs of each register synchronized by a clock can be specified using a defined or derived clock name For general information on derived clocks see the Clock Overview section in the Precision RTL Synthesis User Guide A single to pin can be specified using a hierarchical pin name A pin object is a Tcl object that contains a single pin Multiple to pins can be specified using pin names pin objects or pin sequence objects A pin sequence object is a Tcl object that contains one or more pins
227. fault The precision 1log file contains the commands and messages from the current session The psp file is a Precision RTL Synthesis Project File that is created when Precision created the project directory This file stores information about all of the implementations belonging to the project You might also create one or more Tcl control files for various purposes Refer to the section The Tcl Command Interface on page 1 2 for information on creating a Tcl startup script NOTE PSP files are not operating system independent If you create a PSP file using Windows then you must load it from Windows If you create a PSP file using UNIX then you must load it from UNIX The generated output files on the right are kept in an implementation directory You can create multiple implementations in order to experiment with different sets of constraints during different synthesis runs and save the results in different sub directories In this case the ea file is an EDIF netlist of the technology mapped design the xab file is a binary version of the synthesized design an area report and timing report are contained in the rep files and the constraints that you manually entered or changed from the GUI are saved in the sac file If you choose to run the vendors implementation tools from the Precision RTL Synthesis GUI the vendor generated files are also placed in this implementation directory Understanding File Extensions Precision RTL Synthesis v
228. file lt fdb file name gt pdb file is missing f loorplan_only is false Warning Could not tind file lt pdb file name gt Related Commands add_placement_file 3 20 Precision Synthesis Installation Guide 2003c Update March 2004 Commands add_placement_file add_placement_file Add one or more placement file s to the design Applies to Precision Physical only Example add_placement_file E src routing xdb Syntax add_placement_file path_to_prefix floorplan_only lt path_to_prefix gt Arguments lt path_to_prefix gt This is the full pathname plus prefix of the pdb fdb file This is extended by these suffixes to resolve to the corresponding files Multiple invocations of this command are allowed Options floorplan_only If this switch is specified only the fdb is used which contains the relative placements and region constraints If no fdb file exists the command fails with an error If this switch is not specified both pdb and fdb files are searched for and if found are made part of the additive placement file list If neither exist the command fails with an error Description This command is used to add one or more placement file s to the design The following define the file extensions pdb PreciseView placement database file fdb Precise View floorplanning database file For more information on these files see the RTL Synthesis Output Files and Step 3 Run the
229. fix timing violations that are exposed after some retiming moves have occurred Up to 10 iterations can occur on a circuit but the process will terminate when timing is met or improvements are no longer possible Registers that are retimed are renamed by adding _FRT as shown in the retiming report The signal that 1s driven will also be renamed in the same manner This is to remind the user that the register will not have the same function as it would in the RTL design Enabling the Retiming Algorithm By default Register Retiming 1s turned off To enable retiming from the GUI open the Project Setting dialog box shown in Figure 4 7 by either clicking on the Setup Design icon on the Design Bar or right clicking on the implementation in the Project Files pane of the Design Center window and choosing Seup Design from the popup menu If the selected device does not support register retiming the Retiming option will be disabled greyed out Figure 4 7 Enabling the Register Retiming Algorithm Project Settings x Technology Desi i gn Frequency 100 MHz H Altera Lattice wiling Default Input Delay g ne CoolRunner XPLA3 CPLD CoolRunner CPLO s Deja Cue Diels rt ne SPARTAN SPARTANZE SPARTANS M Aun Retiming eVd40csl44 Speed Grade Precision Synthesis Installation Guide 2003c Update1 4 15 March 2004 How Precision Synthesizes the Design How Precision Compiles Designs For batch
230. g lt object_name gt lt attribute_name gt lt attribute_type gt lt attribute value gt Z Arguments lt object_name gt Name of the object library cell view port net or instance for which the set_attribute command sets an attribute value Wild cards and lists are accepted If you omit this argument the set_attribute command operates on the current design Options port net instance Indicator that object_name refers to a port net or an instance respectively If you omit this argument the set_attribute command assumes that object_name refers to an instance unless object_name refers to a library cell or view global Apply this attribute to nets globally all levels of hierarchy name lt attribute_name gt Simple name for the attribute whose value is being set Attribute names are case insensitive Precision Synthesis Installation Guide 2003c Update 3 165 March 2004 set_attribute Commands type lt attribute_type gt Data type of the attribute whose value 1s being set Valid values depend on the attribute indicated with the name option value lt attribute _value gt Alphanumeric string to assign to named attribute design lt rtl gatelevel gt Tells the tool whether to look for the object in the RTL or the gatelevel view Description The set_attribute command assigns a value to an attribute on an object in the in memory design database If the object alread
231. g Mentor Graphics competitors whose job performance requires access You shall take appropriate action to protect the confidentiality of Software and ensure that any person permitted access to Software does not disclose it or use it except as permitted by this Agreement Except as otherwise permitted for purposes of interoperability as specified by applicable and mandatory local law you shall not reverse assemble reverse compile reverse engineer or in any way derive from Software any source code You may not sublicense assign or otherwise transfer Software this Agreement or the rights under it whether by operation of law or otherwise attempted transfer without Mentor Graphics prior written consent and payment of Mentor Graphics then current applicable transfer charges Any attempted transfer without Mentor Graphics prior written consent shall be a material breach of this Agreement and may at Mentor Graphics option result in the immediate termination of the Agreement and licenses granted under this Agreement The provisions of this section 4 shall survive the termination or expiration of this Agreement LIMITED WARRANTY 5 1 Mentor Graphics warrants that during the warranty period Software when properly installed will substantially conform to the functional specifications set forth in the applicable user manual Mentor Graphics does not warrant that Software will meet your requirements or that operation of Software will be uninte
232. g box Precision Synthesis Installation Guide 2003c Update 3 221 March 2004 setup _place_and_route Commands Altera Quartus II Command Arguments install _dir lt vendor_installation_directory_pathname gt Specifies the pathname to the Quartus IJ installation tree no exec This option is primarily used to debug the Precision place_and_route script that drives the implementation tools The commands in the script are echoed to the Precision Transcript window without the commands actually being executed by the implementation tools ba_format lt format gt Specifies as string which is the format of the back annotation file that will be generated by the implementation tools Possible options are Verilog VHDL or EDIF The default is Verilog Lattice isoLEVER Command Names Integrated Place and Route Set the options specified in the Integrated Place and Route dialog box Launch ispLEVER Set the options specified in the Launch ispLEVER dialog box Launch ispExplorer Set the options specified in the Launch ispExplorer dialog box Lattice isoLEVER Command Arguments install _dir lt vendor_installation_directory_pathname gt Specifies the pathname to the ispLEVER installation tree for example C ispTOOLS no exec This option is primarily used to debug the Precision place_and_route script that drives the implementation tools The commands in the script are echoed to the Precision Tra
233. g depends on which state Precision Synthesis is in o If no project is open and the results directory is not set then set_working_dir creates a default project and a default implementation directory in the CWD The implementation directory name is impl_ lt n gt where lt n gt is an integer that incremented to make the directory name unique within the CWD o Ifa project is open or a result directory is set then set_working_dir issues a warning and does not change the results directory setting If the specified directory does not exist you can specify the create option and Precision Synthesis will create the directory After the directory is set Precision Synthesis moves the session log file precision log to that location Related Commands add_input_file set_input_dir load_project Deprecated set_results_dir logfile setup_design save_project Obsolete remove_design 3 208 Precision Synthesis Installation Guide 2003c Update March 2004 Commands setup_analysis setup analysis Setup the PreciseTime timing report Example setup_analysis num_critical_paths 10 net_fanout true Syntax setup_analysis clock_frequency summary num_summary_ paths lt integer gt critical_ paths num_critical_paths lt integer gt timing_violations net_fanout clock_domain_crossing missing constraints Options clock_frequency Report all clock frequencies Th
234. g instance in the design hierarchy which will allow other commands to set or get attributes from that instance get_cells SDC Get cells instances from the current design relative to the current instance get_clocks SDC Return a list of defined clocks in the current design get_lib_cells SDC Return a list of cells in a loaded library get_lib_pins SDC Return a list of library pins on cells in a previously loaded library 3 12 Precision Synthesis Installation Guide 2003c Updatet March 2004 Commands Command Summary Table 3 7 SDC Commands continued get_libs SDC Return a list of currently loaded libraries that match the search pattern get_nets SDC Return a list of hierarchical net pathnames get_ports SDC Return a list of hierarchical port pathnames set_clock_latency SDC Specifies delay from pin where clock is defined to register clock pin set_clock_transition set_clock transition SDC Override the clock slew values from the library set_ a _uncertainty SDC Specify the source and destination clocks to calculate inter clock uncertainty between defined clocks set_false_path SDC Ignore slack values on the specified paths set_fanout_load SDC Limit the capacitance in library units that a net or port can drive set_input_delay SDC Set input delay on pins or input ports relative to a clock signal set_max_delay SDC Set the maximum total path delay for a timing path that is constrain
235. gister in the IOB By default Precision maps the register to the IOB if this attribute is not present The attribute is applied to the inout port Table 2 4 Net Attributes buffer_sig Specifies that a signal a net in the design is to be buffered with a technology specific buffer Precision Synthesis Installation Guide 2003c Update 2 5 March 2004 How to Set Attributes Attributes Table 2 4 Net continued Attributes dedicated_mult Specifies that an instance should be mapped to the dedicated multiplier resource in place route extract_mac Controls the mapping of multiply accumulate logic to Altera DSP blocks Allows you to change the fanout limit on the specified net Prevents the specified signal from being buffered nopad Prevents the placement of an I O pad on the specified port when the design is mapped to the technology Preserves the specified signal and the driver in the design Preserves the specified signal in the design radhardmethod Actel Creates a radiation hardened implementation uselowskewlines Tells the implementation tools to assign the specified signal to a low skew route line How to Set Attributes This section provides examples of various ways to set attributes 1 You can declare and set attributes in your VHDL or Verilog source files 2 You can use the set_attribute and remove_attribute commands in the Interactive Command Line Shell to set and remove attributes on in memory design objects
236. gn pin numbers to buses async_reg Xilinx Allows you to specify an asynchronous registration 7 g y pecily y flow This attribute is used in Xilinx to flag flip flops as clock domain crossing flops for gate level simulation block_ram Xilinx Allows you to disable the mapping of a particular RAM instance to block RAM in Xilinx technologies buffer_sig Specifies that a signal a net in the design is to be buffered with a technology specific buffer Precision Synthesis Installation Guide 2003c Update 2 1 March 2004 Alphabetical List of User Attributes Attributes Table 2 1 Alphabetic Attribute dedicated_mult dont_retime dont_touch extract_mac hierarchy inff input_delay Obsolete 10b max_fanout nobuff nopad outff 2 2 al Attribute Summary continued Specifies that an instance should be mapped to the dedicated multiplier resource in place route Specifies that the Retiming algorithm can be disabled on a register by register basis or on a module basis Tells Precision Synthesis to pass the module through synthesis without optimizing or unmapping Controls the mapping of multiply accumulate logic to Altera DSP blocks Tells Precision Synthesis to maintain the hierarchy of the module Valid values are preserve or flatten This attribute is applied to instances Tells Precision Synthesis whether or not to map the first register in the input path to a register in the IOB By default
237. gt pkgs techdata vhdl is searched As soon as the file is found the search ends the package file is compiled and the specified input file file is compiled If the package file 1s not found Precision Synthesis issues an error message Description The input_file_list is an internal list of files that Precision Synthesis recognizes as the design to be compiled This add_input_file command is the main mechanism for adding input files to the input_file_list It is also used to add attributes to each input file such as the name of the work library into which it will be compiled the file type and a supplemental search path for directories where Verilog include files and uncompiled VHDL package files may be found Related Commands move_input_file set_input_file report_input_file_list setup_design remove_input_file remove_design 3 18 Precision Synthesis Installation Guide 2003c Update March 2004 Commands add_ macro file add _ macro file Add one or more file s to the macro_file_list Applies only to Precision Physical Example add_macro_file G src design xdb Syntax add_macro_file path_to_prefix floorplan_only lt path_to_prefix gt Arguments lt path_to_prefix gt This is the full pathname plus prefix of the xdb pdb fdb files representing the macro This is extended by these suffixes to resolve to the corresponding files Multiple invocations of this command are allowed Note that if the path is the c
238. h the Actel Designer Alcatel Designer Software EY simplernath_canstraints amp J Script Files aa Click to automatically iles E E Flip Flops Launch Designer Place and Route ile Infos 5 Ea reg_add_regf 0 RTL Schematic H reg_add reg DFF D EB Technology Schematic H E reg_add_reg 6 DFF ee Rei Area Report nEs reg_add regiS DFF Basch hi Rei Timing Report GAD reg_add_reg 4 DFF Rei Timing Violation Report ASDF reg_add_regi3 DFF RP Constraints Report l E reg_add regi DFF Ei simplemath edf E reg_add_regii DFF a Actel Designer Cormmany reg_add regi0 OFF 0 reg mul regi7 0 J reg sub regf3 0 FL Operators Blocks ab Ut shatemachine I Primitives ES Transcript F Design Center Input Directory IF 2 6 2 Precision Synthesis Installation Guide 2003c Update1 March 2004 Designing with Actel Devices Actel Designer Integration Setting Actel Designer Options As shown in Figure 6 2 you can change pre set Designer options from the Tools gt Set Options pull down menu This example shows the Integrated Place and Route menu The options for this tab and the other two tabs Launch Designer and Generate Actel Script File are explained in the paragraphs that follow Figure 6 2 Setting Actel Designer Options Input a Optimization ated Place and Route F Analysis Click to bring up the 3 Actel website Actel Desig
239. hardmethod of dataout signal is tmr cc Setting the attribute on an instantiated module through a VHDL attribute attribute radhardmethod string attribute radhardmethod of U2 label is tmr Verilog Setting the attribute on a reg through a Verilog synthesis directive reg 7 0 dataout pragma attribute dataout radhardmethod tmr_cc Precision Synthesis Installation Guide 2003c Update1 2 21 March 2004 Pre Defined User Attributes Attributes Setting the attribute on an instantiated module through a Verilog synthesis directive pragma attribute U2 radhardmethod tmr safe _fsm Specifies that the Finite State Machine should be built as a safe FSM Refer to the Precision Synthesis RTL Style Guide for more information VHDL ARCHITECTURE rtl OF safel IS TYPE state t Ior Sil SIZ Sis S14 Sis J SIGNAL state nxstate state_t attribute SAFE FSM boolean attribute SAFE FSM of state_t type is true slew Specifies the slew value Verilog pragma attribute port_tx SLEW SLOW VHDL attribute SLEW string attribute SLEW of port_tx signal is SLOW Interactive Command Line Shell set attribute design gatelevel name SLEW value SLOW port tx 2 22 Precision Synthesis Installation Guide 2003c Update1 March 2004 Attributes Pre Defined User Attributes synthesis clearbox Specifies that Precision should generate timing models for Altera blackboxes u
240. he setup_design command Precision lets you set a global include search path with setup_design search_path You can set an include search path for each input file The tool concatenates the two when reading an input file For example if a script included the following setup_design search_path c hdl a add input tile cr7hdl b 7too w search path c hdl c aod input file c hdl b bar v search path ci hdl d then both c hdl c and c hdl a would be searched for any included hdl files in foo v And both c hdl d and c hdl a would be searched for any included files in bar v 3 186 Precision Synthesis Installation Guide 2003c Update March 2004 Commands set_input_file Searching for Verilog include files Ifa Verilog file is being added and additional files are referenced via the include directive then the search for the include file is conducted in the following order 1 The directory of the file that specifies the include directive 2 The directories that are specified as an argument to this search_path switch 3 The directories that are specified as an argument to the setup_design search switch Assume for example that the file being added is located in the directory F design src and this search path is set to the following C my_include_files F more_include_files During the compile operation for this file Precision Synthesis first searches for any specified inclu
241. hmetic or logical operations are combined within a single case or 1f then statement Precision performs resource sharing automatically in every possible case it 1s not timing driven If you notice that Precision has used resource sharing in your critical paths you may want to disable resource sharing retiming Causes the advanced retiming algorithms to be run The default is false Precision Synthesis Installation Guide 2003c Update 3 215 March 2004 setup design Commands search_path lt search_pathnames gt Set the input search path This may be one or more pathnames of directories to be searched in a global search for files The value is specified as a Tcl list for example C my_special_files F more_special_files speed lt speed_grade gt Speed grade for this design as specified in the INI_FILE for the current technology This argument is normally set when the user selects a speed grade option from the Setup Design dialog box in the GUI transformations Transform Set Reset on DFFs to Latches The default is true If you wish to set this switch to false then you should use the following syntax transformations false use_safe_fsm Safe FSMs are FSMs that have no illegal states Safe FSM can also be specified from the tools gt options gt input dialog box The Safe FSM option is implemented as follows If the SAFE_FSM attribute also FSM_COMPLETE is used in VHDL on an enumerated
242. hown in Figure 8 6 you can change pre set options from the Tools gt Set Options pull down menu The option settings are explained in the paragraphs that follow Figure 8 6 Setting Quartus II Options Input Optimization J si i Analysis Click to bring up the Altera website Quartus IT g Integrated Place and Route eneee na Eile Path to Quartus II installation tree QUARTUS_HOME H session Settings Do not run commands Schematic viewer a Physical Back annotation netlist format Verilog f VHDL f EDIF Precision Synthesis Installation Guide 2003c Update 8 9 March 2004 Altera Quartus II Integration Designing with Altera Devices Altera Logo If your web browser is active click on this logo to bring up the Altera website home page http www altera com Path to Quartus II installation tree Specify the pathname to the Quartus II installation tree for example D quartus2 Do not run commands This switch is primarily used for debugging the Precision script that drives the Quartus II tools The commands in the script are echoed to the Precision Transcript window without the commands actually being executed by the implementation tools Back annotation netlist format Specifies Verilog EDIF or VHDL for the annotation netlist format Using Altera Megafunction Blocks The Altera MegaWizard Plug In Manager allows you to create optimized building blocks for logic arithmetic storage and in
243. hysical_ synthesis physical_ synthesis Perform physical timing optimization and placement improvement on a design Example physical_synthesis routing_list Syntax physical synthesis _ from lt from_list gt thru lt thru_list gt to lt to_list gt slack_margin lt number gt effort Normal High lt object_list gt Objects from lt from_list gt The From Points list is a list of any number of timing synchronization points that can be start points of timing paths If the from points are omitted all from points will be considered by the optimizer to lt to_list gt The To Points list is a list of any number of synchronization points that can be end points of timing paths If the to points are omitted all to points will be considered by the optimizer thru lt thru_list gt The Thru Points list is a list of any number of points within the circuit This instructs the tool on the range of points to consider slack_margin lt number gt Specifies a real number instructing the tool to continue optimizing the timing path until slack exceeds this number effort lt Normal High gt A Normal effort indicates to continue the optimization as long as the most critical path can be improved A High effort indicates to continue the optimization to reduce the overall number of violations even if the most critical path cannot be improved object_list A lis
244. ide 2003c Update March 2004 Commands get_pins SDC regardless of the value of current_instance To limit the search to a lower block of hierarchy you can use absolute instance pathnames or pathnames relative to the current_instance The value of current_instance is only used as the relative top of hierarchy that is searched By default the current_instance is set to current_design top of the design hierarchy You can also use wildcards and all object names are case sensitive Wildcards do not imply descending into hierarchy For example get_pins reg_ returns the pins names of instances beginning with reg_ on the current level of hierarchy defined by current_instance The wildcard string is terminated by the hierarchical separator If you omit the search pattern Precision Synthesis returns an error Related Commands get_cells SDC get_lib_cells SDC get_clocks SDC get_lib_pins SDC get_designs get_multicycle_paths get_false_paths get_nets SDC get_lib_cells SDC get_ports SDC get_lib_cells SDC Precision Synthesis Installation Guide 2003c Update 3 77 March 2004 get_ports SDC Commands get_ports SDC Return a list of hierarchical port pathnames Example The following example displays all the ports in the top of the design starting with clk gt g et_ports clk clk 100mhz clk 20mhz The following example uses the get_ports command to set an input delay of all bits of an add
245. ide 2003c Update 1 9 23 March 2004 Handling Xilinx Design Issues Designing with Xilinx Inferring Tri Port RAM This section describes the recommended coding style for inferring tri port RAM Of the three ports in the ram only one port can be written synchronously this port can be written only or can also be read synchronously or asynchronously this port is referred to as port A for the purpose of this discussion The other two ports are read either synchronously or asynchronously and are referred to as port B and port C respectively Port A Written Only Block RAM are inferred when both port B and port C are read synchronously with the same clock the clock which synchronizes the reading of port B and C can be the same as or different from the clock associated with port A synchronous reading of port B or C can also be described by explicitly clocking the read address When the block_ram attribute on the RAM model is set to false Distributed RAM are inferred instead of Block RAM Tri Port RAM with One Clock and a Synchronous Write on Port A The Verilog code in Figure 9 21 infers a tri port RAM where all ports operate as synchronous and are clocked by one clock The RAM is mapped to a set of dual port Block RAMs for port A and B and another set of dual port Block RAMs for port A and C Figure 9 21 Tri Port RAM Sync Write Sync Read Sync Read One Clock module swe sro sre clk wen addril addr7 addr out2 Cuts Gateain in
246. ide 2003c Update 3 105 March 2004 place_and_route Commands spdfmax Causes the Logic Optimizer to automatically identify all critical paths between any pair of registers from clock pin of one register to data pin of the other register or the same register The Logic Optimizer then attempts to collapse combine the logic nodes along the critical paths reduce the logic level and allow the chip to run at a higher frequency If you specify an empty string the default then ispLEVER determines the best optimization for placement ba_format lt format gt Specifies as string which is the format of the back annotation file that will be generated by the implementation tools Possible options are Verilog VHDL EDIF or None The default is VHDL max_pterm_split lt string gt This option lets you control the Fitter optimization process by setting a maximum limit on the number of Product Terms PT in each equation In other words the Optimizer shapes the equations relative to the set number of PT For example if the value is set to 35 the Optimizer splits equations if it has more than 35 PT This option works the opposite of Collapsing Max Product Term max_pterm _collapse lt string gt This option lets you control the Fitter optimization process by setting a maximum limit on the number of Product Terms PT in each equation In other words the Optimizer shapes the equations relative to th
247. iews the following file types as valid input files It is common to place these files in a separate sub directory to keep them isolated from tool generated files Table 5 1 Input File Extensions File Extension File Description vhd Design source file in VHDL format Design source file in Verilog format xdb A design in Mentor Graphics binary format sdc Design constraints file in Synopsys Design Constraints SDC format 5 2 Precision Synthesis Installation Guide 2003c Update1 March 2004 Files Reference Understanding File Extensions The following file types are generated by Precision RTL Synthesis and placed directly in the working directory These file types are common to the project during every synthesis run Table 5 2 Precision Specific Files File Extension File Description precision log Precision writes two log files a session log and an implementation log The session log records all commands and output during the Precision session and is stored in the Project Directory The implementation log records commands and output during the time the implementation 1s active and is stored in the implementation directory Each can be used as a command file to repeat the run lt design_name gt psi A implementation file created and maintained by the Project Manager This file stores all information about the state of the design contained in the implementation directory lt project_name gt psp A project file created an
248. im VLOG ModelSim SE ModelStation Model Technology Model Viewer Model ViewerPlus MODGEN Monet Mslab Msview MS Analyzer MSArchitect MS Ex press MSIMON Nanokernal NetCheck NETED Nucleus Nucleus All You Need Opsim OutNet P amp RIntegrator PACKAGE PADS PARADE ParallelRoute Autocells ParallelRoute MicroRoute Parts SpeciaList PathLink PCB Gen PCB Generator PCB IGES PCB Mechanical Interface POLSim PE GMAC PE MAC Personal Learning Program Physical Cable Physical Test Manager SITE PLA Lcompiler Platform Express PX PLDSynthesis PLD Synthesis I Power Analyst Power Analyst Station Power To Create PowerLogic PowerPCB Precision Pre Silicon ProjectXpert ProtoBoard ProtoView QDS QO Net QualityIBIS QuickCheck QuickFault QuickConnect QuickGrade QuickKHDL QuickKHDL Express QuickHDL Pro QuickPart Builder QuickPart Tables QuickParts QuickPath QuickSim QuickStart QuickUse QuickUse Development System QuickVHDL Quiet Quiet Ex pert RAM Lcompiler RC Delay RC Reduction RapidEx pert REAL Time Solutions Registrar Reliability Advisor Reliability Manager REMEDI Renoir RF Architect RF Gateway RISE ROM Lcompiler RTL X Press Satellite PCB Station scaleable Models Scaleable Verification SCAP Scan Sequential Scepter Scepter DFF Schematic View Compiler SVC Schemgen SDF Software Data Formatter SDL2000 Leompiler Seamless Seamless ASAP Seamless C Bridge Selective Promotion Sheet
249. is specified but a lt clock_name gt is given a virtual clock 1s created For more information about input and output delay refer to the set_input_delay and set_output_delay command descriptions This command also defines the specified lt port_pin_list gt as clock sources in the current design A pin or port can be a source for a single clock Defining the Waveform You also use the create_clock command to define the waveform for the clock The clock can have multiple pulses per period Setup and hold path delays are automatically derived from the clock waveforms of the path startpoint and endpoint The waveform of each clock is defined in terms of an initial level a period and edge positions The period is the time required for an entire clock cycle to occur A clock period can have any even non zero number of edges An edge occurs whenever the level of a waveform changes and is defined in terms of the ideal position in time at which the level change should occur An edge can occur at the start or end of a clock cycle If an edge occurs at the start of a clock cycle time 0 then the waveform transitions away from the initial level If an edge occurs at the end of a clock cycle time period then the waveform transitions toward the initial level Figure 3 1 illustrates the relationship between the edge positions and initial levels of a waveform 3 42 Precision Synthesis Installation Guide 2003c Updatet March 2004 Commands create_c
250. is write mode is the default write mode and is the only write mode for Virtex Block SelectRAM For both Virtex II and Virtex Precision by default infers a set of dual port block rams for ports A and B and another set of dual port block rams for ports A and C when both port B and port C are read synchronously with the same clock the clock which synchronizes the reading of port B and C can be the same as or different from the clock associated with port A synchronous 9 26 Precision Synthesis Installation Guide 2003c Update March 2004 Designing with Xilinx Handling Xilinx Design Issues reading of port B or C can also be described by explicitly clocking the read address When the block_ram attribute 1s set to false on mem Distributed RAMS are inferred Tri Port RAM Port A Sync Write Read Sync Read Async Read One Clock The code in Figure 9 24 illustrates the recommended coding style where the write mode for port A is WRITE_FIRST The memory is mapped to Distributed RAM because the block_ram attribute set to false On mem Figure 9 24 Tri Port RAM Sync Read Write Sync Read Sync Read module swsr sr sr welk wen addrl addr2 addrs outl out2z outs datain input wclk Write clock input wen Write enable input addrl INpuL addr input addr3 j output Out ls output out2 output lt Cul Aput datain reg 7 0 mem 0 31 A 32 x 8 bit memory pragma attribute mem block ram false reg 7 0 o
251. it from the program rtl physical physical sa These options specify which configuration of Precision Synthesis functionality is invoked assuming the corresponding license features are installed The rtl option default invokes Precision RTL without integrated Precision Physical functionality Conversely the physical_sa option invokes Precision Physical stand alone without the Precision RTL features Use physical to invoke Precision Synthesis with both RTL and Physical Synthesis functionality file lt file_pathname gt Specifies a Tcl file that is automatically sourced after Precision Synthesis is invoked Although only one file may be specified other Tcl files may be called from within the specified file by using the source command The file option accepts either just the filename or a list that includes the filename and any arguments that need to be passed to the tcl file These extra arguments will be set as a list value to TCL variable argv For example invoking precision as precision file testl tcl will set argv to empty list and source the file test1 tcl Invoking precision as precision file testl tcl Xilinx true 64 Precision Synthesis Installation Guide 2003c Update 3 111 March 2004 precision Commands will set TCL variable argv to the list Xilinx true 64 and then source the file test1 tcl In the file then you can access argv as a list e g length argv for this will give you 3 Note that
252. ition of the alias is displayed Description The alias command defines a new command that executes either a built in Precision Synthesis command or a Tcl script When you use an alias any added arguments are appended to the script for that execution only the script itself 1s not modified The alias command is very suitable for the simple redefinition of commands When you need scripts with multiple commands or when arguments cannot be simply appended to an alias script it is easier to write a Tcl procedure with the Tcl proc command rather than create an alias Related Commands help unalias Precision Synthesis Installation Guide 2003c Update 3 23 March 2004 all_ clocks SDC Commands all_ clocks SDC Return a list of all clocks in the current design Example all clocks short Syntax all clocks lt design_name gt short internal lt design_name gt Arguments lt design_name gt Name of the design Options short Print only short names not the full path to objects internal Print only internal clock names Description The all_clocks command is a reporting command that returns a list of clocks that where previously defined using the create_clock command The al1_clocks command only returns the name of the clock it does not return the instance pathname to the clock If you need the instance pathname use the find_clocks command More Examples In the following example
253. kxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxkxxk xx xx k Number Number Number Number of of of of Total accumulated area Number Number Number Number OF of of of Related Commands report_attributes report_library ports 2 nets 35 instances 32 references to this view O CLB Flip Flops 3 H Function Generators 2 Packed CLBs 9 FG Function Generators 17 report_net report_timing report_missing_constraints 3 130 Precision Synthesis Installation Guide 2003c Update1 March 2004 Commands report_attributes report_attributes Generate a report that lists attributes on the specified objects Example Syntax report_attributes lt list_of_objects gt port net instance Arguments lt list_of_objects gt Arguments lt list_of_objects gt Names of attributes applied to any objects library cell view port net instance you want listed Object names are case sensitive and you can use wildcards If you omit this argument the report_attributes command lists the attributes of the current design Options port net instance Indicator that the object name s refer to ports nets or instances respectively If you omit this argument the report_attributes command assumes that the objects in object_list are instances unless object_list explicitly refers to libraries cells or views Description The report_attributes command returns a Tcl list of case
254. lace_and_route command install_dir lt vendor_installation_directory_pathname gt Specifies the directory where the ISE implementation tools are located no exec This option is primarily used to debug the Precision place_and_route script that drives the implementation tools The commands in the script are echoed to the Precision Transcript window without the commands actually being executed by the implementation tools par_ol lt overall_effort gt The place and route overall effort level is specified as a string 1 5 The default is 1 1 Lowest 2 Low 3 Normal 4 High 5 Highest Precision Synthesis Installation Guide 2003c Update 3 225 March 2004 setup _place_and_route Commands mode lt place_and_route_run_mode gt You can specify Xilinx PAR modes Normal and High or Simulation The default is Normal ba_format lt format gt Specifies as string which is the format of the back annotation file that will be generated by the implementation tools Possible options are Verilog VHDL or EDIF The default is Verilog guide_mode lt list gt Available Xilinx PAR modes are Exact and Leverage Exact mode specifies not to make any changes to the layout and is used only to make minor changes like replacing a cell Leverage mode uses the current NCD file as a starting point to improve the placement and routing on the next pass You may include an NCD file in your
255. lack_value gt Commands 3 154 Precision Synthesis Installation Guide 2003c Update1 March 2004 Commands report_timing Type Arguments report tile name gt lt slack_value gt lt SbLare pornLs gt Send points gt lt Ehrough port s gt lt l1ist OF ehbockse gt lt number_of_paths gt lt path_index gt lt number_of_bins gt Arguments lt report_file_name gt Name of the file in which to write the delay report report_file_name can be a local file name a relative path name or an absolute path name If you omit this argument the report is sent to the Transcript window Options append Append report data to the existing report file if present replace Replace the existing report file af present num_paths lt number_of_paths gt Number of paths to report in descending order of criticality If this option is omitted the 10 worst critical paths are reported capacitance Show capacitance values in the report fanout Include fanout paths in the report show_schematic Show critical path schematic s show_nets Include net names in the report cell_names Include cell names in the report slew Include slew values in the report Precision Synthesis Installation Guide 2003c Update 1 3 155 March 2004 report_timing Commands limit_value lt slack_value gt Show only paths with a slack less than the specified value through lt through_points gt Rep
256. lation Guide 2003c Update1 March 2004 Mapping Dual Port RAM to Block RAM 9 12 Mapping Registers to IO Blocks 9 8 Mapping Single Port RAM to Block RAM 9 9 Memory Mapping 9 8 Post Place and Route Analysis 9 32 UCF files 9 2 Xilinx Technologies 4 13 Index 5 Index Index cont Index 6 Precision Synthesis Installation Guide 2003c Update March 2004 End User License Agreement IMPORTANT USE OF THIS SOFTWARE IS SUBJECT TO LICENSE RESTRICTIONS CAREFULLY READ THIS LICENSE AGREEMENT BEFORE USING THE SOFTWARE This license is a legal Agreement concerning the use of Software between you the end user either individually or as an authorized representative of the company acquiring the license and Mentor Graphics Corporation and Mentor Graphics Ireland Limited acting directly or through their subsidiaries or authorized distributors collectively Mentor Graphics USE OF SOFTWARE INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH IN THIS AGREEMENT If you do not agree to these terms and conditions promptly return or if received electronically certify destruction of Software and all accompanying items within five days after receipt of Software and receive a full refund of any license fee paid END USER LICENSE AGREEMENT 1 GRANT OF LICENSE The software programs you are installing downloading or have acquired with this Agreement including any updates modific
257. le basis If a generic RTL register has the dont_retime attribute set the register will not be retimed Further if a hierarchical module has a dont_ret ime attribute set then all logic within that module will not be retimed These attributes can be set in the Design Browser or in the Schematic by using the popup menu Set Attributes on the Right Mouse button From a script you can use the set_attribute command to selectively disable retiming VHDL attribute dont_retime boolean attribute dont_retime of dat25 signal is true Verilog Wire dat25 synthesis attribute dat25 dont_retime true Interactive Command Line Shell set attribute reg_dat25 instance name dont_retime value true dont touch Tells Precision Synthesis to pass the module through synthesis without optimizing or unmapping The presence of this attribute on an instance indicates dont_touch regardless of the boolean value true or false You must remove the attribute completely with the remove_attribute command to remove the dont_touch status Verilog pragma attribute I1 d nt touch VHDL attribute dont_touch boolean attribute dont_touch of I1 label is true Interactive Command Line Shell set_attribute instance Il name dont touch value true You can also set this attribute by right clicking on an instance in the Design Hierarchy pane of the GUI and selecting Don t Touch Precision Synthesis Installation Guide 2003c Update 2 1
258. library values Example create_clock name sys_clk90 ul udcm Q remove_clock_uncertainty sys_clk90 Syntax remove_clock_uncertainty lt clock_name gt Arguments and Options None Description The remove_clock_uncertainty command removes the skew constraint override for the defined clock If the constraint is removed Precision calculates the clock skew times using library values Related Commands create_clock SDC report_timing Precision Synthesis Installation Guide 2003c Update 3 119 March 2004 remove_design Commands remove_design Remove a list of designs or libraries from the in memory database Example remove_design Syntax remove_design lt design_list gt hierarchy designs all Deprecated quiet lt design_list gt Arguments lt design_list gt A list of designs to be removed from the in memory design database Options hierarchy Remove all lower hierarchy designs Remove the design but keep the technology libraries all This option is deprecated Use close_project or close_results_dir instead Remove the design and the technology libraries quiet Remove the design but keep the technology libraries 3 120 Precision Synthesis Installation Guide 2003c Update March 2004 Commands remove_design Description remove_design command is now provided by the commands close_project and close_results_dir Although remove_design is still supported
259. lock SDC period 100 edges 50 100 initial value 1 Falling Edge 50 0 100 O 150 0 A edge somes period waveform transitions toward initial level at edge period 100 edges 0 50 4 initial value O Rising Edge 0 0 50 0 100 0 150 0 B edge position 0 waveform transitions away from initial level at edge Figure 3 1 Relationship of Edge Position to Initial Value Isolating Clock Interaction Precision Synthesis enables you to relate clocks together using a domain name A domain can contain multiple clocks All clocks contained in the same domain are considered synchronous and are referenced to the same zero time although the clocks can have different periods and edge positions Clocks contained in different domains are considered asynchronous and are treated as unrelated having no phase or frequency relationship When performing slack analysis Precision Synthesis analyzes all paths that exist between clocks within the same domain All paths between clocks in different domains are automatically ignored during slack analysis Examining Clock Relations You can use the all_clocks command to get a list of all clock sources in the current design You can use the all_registers command to return a list of all sequential cells related to a given clock Related Commands all_clocks SDC remove_clock find_clocks report_area get_clocks SDC Precision Synthesis Installation Guide 2003c Update 3 43 Ma
260. ltera MAX PLUS II GUI Show verbose information while generating the ACF file This option specifies whether or not to transcript the complete messaging while generating an ACF file Back annotation netlist format Specifies Verilog EDIF or VHDL for the annotation netlist format Altera Quartus II Integration As shown in Figure 8 5 the Altera Quartus I environment is integrated into the Precision RTL Synthesis environment After Synthesis the technology mapped design is written to the current implementation directory as an EDIF netlist file along with a Quartus II Project Configuration File Tcl Script To run the automated Place and Route flow just click the Run Quartus icon in the Quartus I Tool Bar Quartus II uses the current implementation directory as the Quartus II project directory After the design is compiled you may invoke the Quartus IJ GUI manually and open the project using the generated Quartus II project file quartus From that point you can view reports run analysis tools and manually drive the physical implementation to completion After the completion of the Quartus I run Precision displays the relavent placement and timing files from the Place Route runn in the output files list for the given implementation Figure 8 5 Running the Altera Quartus II Environment ls pseudorandom Mentor Graphics Precision Physical Synthesis Design Center Pa File View Tools Window Help ACANA Altera Stratis EP1525
261. ly N worst paths per endpoint npaths_per_startpoint lt number_of_paths gt Report only N worst paths per startpoint margin_limit_slack lt slack_value gt Report only paths with a worse slack than indicated summary Generate a summary timing report more_paths get more less critical paths source_clock_path Provide a detailed report for the path index indicated clock_domain_crossing Display the clock domain crossing path list index lt path_index gt Show detail for a path index test_tech_cell_char This is a test option to test a technology cell characterization histogram Generate a histogram of slack paths hist_num_bins lt number_of_bins gt Number of bins for histogram default is10 hist_max_slack lt slack_value gt Maximum slack for histogram default 1s the actual maximum slack hist_min_slack lt slack_value gt Minimum slack for histogram default actual max slack Description The report_timing command invokes the PreciseTime timing analyzer and does a static timing analysis on the technology mapped in memory design Precision Synthesis Installation Guide 2003c Update 3 157 March 2004 report_timing Commands Related Commands report_area report_missing_constraints report_attributes report_net report_library 3 158 Precision Synthesis Installation Guide 2003c Update March 2004 Commands save_impl save_impl Save the state of the active im
262. mentation tools Possible options are Verilog VHDL or EDIF The default is Verilog Lattice isoLEVER Command Names cl default Run the vendor place and route flow in the background command line mode Use the options specified in the setup_place_and_route command Send a transcript of the executed commands to the Transcript window gui Invoke the ispLEVER Graphical User Interface GUI ispexplorer Invoke the ispExplorer tool Lattice isoLEVER Command Arguments The arguments you specify here are the same options that may have been already set with the setup_place_and_route command They may be specified here to change a setup option on the fly when you execute the place_and_route command install_dir lt vendor_implementation_directory_pathname gt Specifies the pathname to the ispLEVER installation tree for example C ispTOOLS no exec This option is primarily used to debug the Precision place_and_route script that drives the implementation tools The commands in the script are echoed to the Precision Transcript window without the commands actually being executed by the implementation tools op_for spdys sdpno spdfmax spdyes speed yes Collapses all nodes up to the set Product Term limit globally optimized without regard for the path spdno speed no Collapses all nodes up to the set Product Term limit without increasing area cost Precision Synthesis Installation Gu
263. milies Precision Synthesis Installation Guide 2003c Update 6 7 March 2004 Targeting Pipeline Multipliers Designing with Actel Devices Pipelining should be considered for costly operators such as multipliers The following figure provides an example circuit that synthesizes to a combinatorial or pipelined multiplier depending on the value of the level generic Precision RTL Synthesis can automatically extract pipelined operators and provide area efficient implementations that better balance the delay across the pipeline stages Figure 6 3 Sample VHDL Code for a Pipelined Multiplier library ieee USE ieee std_logic_1164 all USE ieee std_logic_arith all entity mults is generic a_size integer 16 b_size integer 18 ileveli dictates the amount of pipelining 1 non pipelined multiplier single register at output 2 single pipelined multiplier 3 dual pipelined multiplier level integer 2 5 port clk in std_logic rst in std_logic a in std_logic_vector a_size 1 downto 0 b in Std logic vector b_size 1 downto 0 product out std_logic_vector a_size b_size 1 downto 0 1 end mults architecture mentor of mults is type pipeline_stages is array level 1 downto 0 of signed a_sizetb_size 1 downto 0 signal a_int signed a_size 1 downto 0 signal b_int signed b_size 1 downto 0 signal product_int pipeline_stages b
264. mines the elaboration order of the design Since Precision implement designs in a bottom up order this steps determines any VHDL packages and include files that must be read first 4 Resolves generics or parameters 4 2 Precision Synthesis Installation Guide 2003c Update1 March 2004 How Precision Compiles Designs How Precision Compiles the Design Generics and parameters are often to create re usable blocks Because they could potentially affect the implementation of the cell e g if the parameter defines the width of the output port Precision generates unique cell names for cells with generics or parameters that implement lower level logic by appending the generic names to the entity or module name If the cell is a black box and the generic parameter does not affect the port widths then Precision assumes the cell is a technology instantiation and does not append the generic names so that the cell will continue to be recognized by downstream tools 5 Detect the top level of the design 6 The top level is a module or entity that is not instantiated in any other block in the design You can override the auto top level detection Designs can be read into Precision Synthesis in any order Precision Synthesis supports auto top detection which automatically locates the top level module so no particular file order is required Although it is typically a good idea to move the top level file to the bottom of the file list because the out
265. mmand searches for the specified pattern in the design relative to the current_instance and returns a list of hierarchical net pathnames This command returns the absolute instance path with the net name with respect to the top of the design hierarchy regardless of the value of current_instance To limit the search to a lower block of hierarchy you can use absolute instance pathnames or pathnames relative to the current_instance The value of current_instance is only used as the relative top of hierarchy that is searched By default the current_instance is set to current_design top of the design hierarchy You can also use wildcards and all object names are case sensitive Wildcards do not imply descending into hierarchy For example get_nets tx returns the net names in instances beginning with tx on the current level of hierarchy defined by current_instance The wildcard string 1s terminated by the hierarchical separator If you omit the search pattern Precision Synthesis returns an error 3 2 Precision Synthesis Installation Guide 2003c Updatet March 2004 Commands Related Commands get_cells SDC get_clocks SDC get_designs get_false_paths get_lib_cells SDC get_lib_cells SDC get_lib_cells SDC get_lib_pins SDC get_multicycle_paths get_path_definition_set get_ports SDC Precision Synthesis Installation Guide 2003c Update March 2004 get_nets SDC 3 73 get_path_definition_set
266. mmand syn executes the synthesize command If the command is still ambiguous Precision Synthesis produces an error message For example the command current displays the following ambiguous command name current current_design current_instance The Precision Synthesis commands also allow abbreviated options you do not need to type the options in full only type the part that makes the option unambiguous For example all_clocks i enables the internal option for the all_clocks command Aliasing Precision Synthesis offers an alias command which allows you to define your own name for commonly used command strings For example if you frequently need to know what clock constraints are missing then you may want to write an alias alias rmc report Missing constraints clock4 If you now type the command rmc Precision Synthesis executes the command report_missing_constraints 0 100k Command Line Help You can display information about commands by using the help command The help command uses a regular expression a name with or without wildcards and prints usage for commands that match the regular expression For example you can type help to bring up a transcript list of all commands Typing help report displays information about all commands that start with the string report Also every command takes help switch as an option setup_design help is the same as help setup_design 1 4 Precision Synthesis Installatio
267. must use a method where you manually instantiate Xilinx clock primitives in your HDL source code For Virtex I designs refer to the Xilinx Application Note titled Using the Virtex Delay Locked Loop This App Note is located on the Xilinx web site at location http www xilinx com xapp xapp 132 pdf For Virtex II designs refer to the Virtex II Platform FPGA User Guide For Virtex II Pro designs refer to the Virtex II Pro Platform FPGA User Guide NOTE If you specify global clock constraints on an input to the DCM for example Precision RTL Synthesis will propagate the timing constraints to the outputs of the DCM including transferring the proper constraints to the clock multiplier and divider ports Working with UCF files Precision Synthesis uses Xilinx UCF files as both inputs and outputs during synthesis When using UCF files as an input Precision will read and interpret the user created UCF constraints and regenerate the UCF information in a variety of formats depending on user specifications Precision will segment the constraints in a UCF file into the 3 following categories Timing constraints Placement constraints Attributes Precision has the ability to convert user defined UCF constraints into the Synopsys Design Constraint SDC format and apply them during synthesis All current UCF timing constraints are supported for this conversion process To enable this functionality simply add the UCF file to the Precision project
268. n either at top level ports or on internal pins This constraint is used to check for setup Precision Synthesis Installation Guide 2003c Update 6 9 March 2004 Constraining for Synthesis and Layout Designing with Actel Devices violations on associated register to register timing paths When setting clock constraints in Precision Synthesis you should place all clocks in the same clock domain main since Actel s create_clock implementation does not support the domain extension to SDC Actel s current implementation of set_max_delay requires fully specifying both the from and to path endpoints In the case of an input port the from argument should be the input port and the to the data input pin of the capturing register In the case of an output port the from argument should be the clock input pin of the launching register and the to the output port When referencing internal netlist objects be careful to refer to the post compiled netlist object The compile phase of Actel s Designer software substitutes soft macros for complex registers thus adding an extra level of hierarchy Refer to the design examples below for more detailed information Using Synopsys Design Constraints The following figures demonstrate how a small UART design might be constrained for synthesis and layout targeting Axcelerator This basic UART design is one of the example circuits included in Precision
269. n Guide 2003c Update1 March 2004 Introduction The Tcl Command Interface Tcl Scripting Language Precision Synthesis accepts all commands of the Tcl language Tcl supports commands that include variable assignment handling of lists and arrays sorting string manipulation arithmetic operations if case foreach while statements and procedures Tcl is VERY handy for writing scripts for Precision Synthesis The Tcl command source lt my_tcl_script gt enables you to source execute script files from Precision Synthesis or from within other script files This feature allows you to write customized portions of design flows or any other sequence of commands that you may want to execute A feature inherited from Tcl is autoexec all UNIX and many DOS commands available from your path can be run from the Precision Synthesis command line Another helpful Tcl feature is history tracking Type the command history to view your previous commands Any previous command can be re executed using NUMBER or for re execution of the last command Automatically Running a Tcl Startup Script on Invocation If you place a Tcl script file named precision tcl in your home directory HOME on Unix or in your user profile folder in Windows c documents and Settings lt username gt then Precision Synthesis will first read and execute the commands in that file each time the tool is invoked This is a handy way for you to automatically define frequ
270. n determining fanout violations for a specific technology You can use the report_net command to get the fanout cap and slew on any net in the design Adding IO buffers Precision Synthesis adds I O buffers on all top level ports that are not driven by IO buffers Technology mapping After the design has been optimized to a minimal area it is mapped into a technology Determine Critical Paths perform STA using CTE and characterize hierarchical blocks Register Retiming Precision Synthesis includes a powerful optimization algorithm called register retiming for improving performance in FPGA designs Retiming allows the optimizer to move registers across combinatorial logic to improve circuit performance Improvements of up to 50 are not uncommon when using this algorithm Performing register retiming on a design will not change the functionality at the primary ports but may effect the observability of internal registers during post synthesis simulation For this reason register retiming is not enabled by default you must select Retiming through the optimization options form If observing internal registers during gate level simulation is not an issue you can feel comfortable enabling register retiming to solve timing issues The retiming process will add registers to a design These additional registers do not add pipeline stages to a design and therefore do not add clock latency to a designs performance The FPGA architectures fr
271. nal assignment statement that follows the process Both ports are driven by the same clock Figure 9 16 Inferring READ_FIRST Mode One Clock Style 2 library IEEE use IEEE std_logic_1164 all use IEEE std_logic_unsigned all entity V2RAM is port DOA out std logic vector 3 downto U DIA in std logic vector 3 downto 0 DOB out std_logic_vector 3 downto 0 ADDRA in std logic vector 12 downto 0 ADDRB in std_logic_vector 12 downto 0 WEA in std_logic CLK in std logic end V2RAM architecture rtl of VARAM is type mem_type is array 8191 downto 0 of STD_LOGIC_VECTOR 3 downto 0 Signal mem mem_type Signal ADDRB_INT std_logic_vector 12 downto 0 begin PROCESS CLK BEGIN IF CLK EVENT AND CLK 1 THEN IF WEA 1 THEN mem conv_integer ADDRA lt DIA END IF DOA lt mem conv_integer ADDRA ADDRB_INT lt ADDRB END IF END PROCESS DOB lt mem conv_integer ADDRB_INT end rtl Precision Synthesis Installation Guide 2003c Update 1 9 19 March 2004 Handling Xilinx Design Issues Designing with Xilinx Figure 9 17 illustrates a RAM that is driven by different clocks Port A is used to both read and write with the READ_FIRST mode inferred Port B is used for read operations only Figure 9 17 Inferring READ_FIRST Mode Two Clocks library IEEE use IEBEE std_logic_1164 all use IEEE std_logic_unsigned all entity V2RAM is port DOA out std logic vector 3 downto
272. named clock_2 This command aborts if clock_1 has unsaved changes Syntax copy_impl name lt impl_name gt from lt inactive_impl_name gt discard lt impl_name gt lt inactive_impl_name gt Arguments Options name lt impl_name gt The name of the new implementation from lt src_impl_name gt The name of an implementation in the current project discard Discard any unsaved work in the active implementation Description The copy_impl command is a project manager command available only when a project is open It closes the active implementation then creates and activates a new implementation with the specified name In the file system a new implementation directory is created and all of the output files in the source directory are copied into the new implementation directory 99 If the name option is omitted the name of the source implementation is used and the _ lt n gt suffix is incremented If the source name does not have the suffix then _1 1s appended to the new name The active implementation is copied unless the from option is used to specify an inactive implementation Precision Synthesis Installation Guide 2003c Update 3 37 March 2004 copy_impl Commands An error occurs if the currently active implementation has unsaved work and the discard option is not specified You can either discard the unsaved work or call save_impl prior to calling copy_impl Related Comm
273. ncoder viin Floorplanner Ebb 2 ram_8_5 View Placement Ve silin Timing Report H H Fins H kilin Pad Report oi H Nets g oo yilin PAR Report 2 Instances Run XPower E Xilinx Mapping Report O EA 14 lfsr_8 ailinx User Constraint File H A 15 divide by nS oS ilins DLY File J E ilins XOL File Floorplanner 4 ese Dehli Input Directory 2 9 32 Precision Synthesis Installation Guide 2003c Update1 March 2004 Designing with Xilinx The Xilinx ISE Environment Setting Xilinx ISE Place and Route Options As shown in Figure 9 30 you can change pre set ISE options from the Tools gt Set Options pull down menu The option settings are explained in the paragraphs that follow Figure 9 30 Setting Xilinx ISE Place and Route Options Input Optimization Hl Analysis Qutpue ISE 6 1 fee Integrated Place and Route Generate vendor Constraint File Session Settings H Schematic viewer Hl Physical XILINX Logo grated Place and Route r Ma n Click to bring up the Xilinx website Path to ilins installation tree SKILIN By 4 ISE 5 high ISE 6 1 Place and Route Run Mode lr Normal f High Simulation Back annotation netlist format C Verilog EDIF f WHOL Do not un commands Place and Aoute Overall Effort Guide File Usage Mode f ExactMode f Leverage Mode Generate BitGen File jv Disable logic replication in MAP Use f c
274. nd before the associated place_and_route flow command can be executed The command argument specifies the Vendor tool or flow and the lt arguments gt specify the Vendor s options for the tool or flow These are the same options that may have been already set with the setup_place_and_route command They may be specified here to change an option on the fly when you execute the place_and_route command Actel Actel Designer Command Names cl default Run the vendor place and route flow in the background command line mode Use the options specified in the setup_place_and_route command Send a transcript of the executed commands to the Transcript window gui Invoke the Actel Designer gen_vcf Write a Vendor Constraint File to the active implementation directory Actel Actel Designer Command Arguments The arguments you specify here are the same options that may have been already set with the setup_place_and_route command They may be specified here to change a setup option on the fly when you execute the place_and_route command Precision Synthesis Installation Guide 2003c Update 3 101 March 2004 place_and_route Commands install_dir lt vendor_implementation_directory_pathname gt Specifies the pathname to the Actel Designer installation tree no exec This option is primarily used to debug the Precision place_and_route script that drives the implementation tools The commands in the script are ech
275. ner i Launch Designer Integrated Place and Route Path to Actel Designer installation tree 4CTEL_HOME Bl Generate Actel Script File i Session Settings J Schemate tiener Back annotation netlist format C Verilag f WHOL Layout Mode f Standard Timing Driven Do notun commands Extended Layout Runtime Mode Effort Level i OU Timing weight i 0g Cancel Apply Help Actel Logo If your web browser is active you can click on this logo to bring up the Actel website home page http www actel com Precision Synthesis Installation Guide 2003c Update 6 3 March 2004 Actel Designer Integration Designing with Actel Devices Actel Script File Specify the pathname to an Actel script file Path to Actel Designer installation tree Specify the pathname to the Actel Designer installation tree for example C actel designer If the environment variable ACTEL_HOME is set to point to the Actel Designer installation tree Precision will automatically import the path Do not run commands This switch is primarily used for debugging the Precision script that drives the Designer implementation tools The commands in the script are echoed to the Precision Transcript window without the commands actually being executed by the implementation tools Back annotation netlist format Specify Verilog or VHDL for the back annotation netlist format Layout Mode This section provides information on various Actel modes Howev
276. never be optimized away It is very important to verify the number of flops is as expected Latch insertion Precision searches for combinational feedback loops in each view on a single level of hierarchy and attempts to replace the loops with transparent latches and appropriate logic in order to correctly optimize the design During latch insertion the tool issues messages in the transcript stating the view names and the number of inserted latches Typically a complex feedback loop occurs when you fail to specify the default operation of a conditional statement in VHDL or Verilog When optimization reports that it is inserting latches you should recheck your HDL code for conditional statements that have a missing case 4 4 Precision Synthesis Installation Guide 2003c Update March 2004 How Precision Compiles Designs How Precision Compiles the Design Infer Operators When Precision Synthesis reads an HDL design it infers arithmetic and relational operators e g adders and implements the operators as blackboxes there is no underlying functionality in the design Precision Synthesis does not implement operators until global area optimization when it replaces these blackboxes with technology specific netlists from the Modgen Library Keeping operators as blackboxes reduces the database size and reading runtime For each inferred operator Precision generates a reference cell in a library called OPERATORS in the in memory data
277. nferring Xilinx Dual Port RAM from Verilog module sync ram dualport clk_in clk_out we addr in addr_out data_in data_out parameter data_width 8 parameter addr_width input Elk an input clk out input we input addr_width addr_in input addr_width addr_out input data_width data_in output data_width data_out reg data_width 1 0 data_out reg data_width 1 0 mem 2 addr_width 1 0 pragma attribute mem block_ram true always posedge clk_in begin if we mem addr_in lt data_in end always posedge clk_out begin data_out lt mem addr_out end endmodule NOTE You should be careful not to specify a memory that is too large for the target chip For example if you specify a wide address bus greater than 23 bits large amounts of virtual memory may be consumed on your machine during the inferencing process and the memory may be built out of LUTs using SelectRAM instead of using the built in BlockRAM Inferring Virtex Il Virtex Il Pro Memory Write Modes The Virtex II Virtex II Pro Block SelectRAM is a True Dual Port memory and supports three different write modes for each port The three possible write modes are WRITE_FIRST the default mode The data being written to the addressed cell is also written to the output latches of the write port during the write cycle READ_FIRST The data previously stored at the addressed location appears at the output latches of the
278. nput to Output Delay matrix a Setup Hold matrix or a Register Performance report generate_acf A boolean value specifying whether or not to generate an ACF Altera Assignment amp Configuration file Default is 1 true Precision Synthesis Installation Guide 2003c Update 3 103 March 2004 place_and_route Commands auto_fast_io This boolean option allows the MAX PLUS II compiler to implement registers in Fast I O This often reduces area requirements but can slow internal circuitry This option corresponds directly to the Automatic Fast I O option in the Altera MAX PLUS II GUI Default is O false auto_register_packing A boolean value specifying whether or not to allow the MAX PLUS II compiler to maximize efficient device usage automatically implementing register packing by placing a combinational logic function and a register with a single data input in the same logic cell This option corresponds directly to the same option in the Altera MAX PLUS II GUI Default is O false auto_implement_in_eab A boolean value specifying whether or not to allow the MAX PLUS II compiler to automatically implement some logic in Flex 10K EABs This option corresponds directly to the same option in the Altera MAX PLUS II GUI Default is O false acf_verbose A boolean value specifying whether or not to transcript the complete messaging while generating an ACF file Default is O false ba_format lt format gt
279. nscript window without the commands actually being executed by the implementation tools op_for spdys sdpno spdfmax spdyes speed yes Collapses all nodes up to the set Product Term limit globally optimized without regard for the path spdno speed no Collapses all nodes up to the set Product Term limit without increasing area cost 3 222 Precision Synthesis Installation Guide 2003c Update1 March 2004 Commands setup_place_and_route spdfmax Causes the Logic Optimizer to automatically identify all critical paths between any pair of registers from clock pin of one register to data pin of the other register or the same register The Logic Optimizer then attempts to collapse combine the logic nodes along the critical paths reduce the logic level and allow the chip to run at a higher frequency If you specify an empty string the default then ispLEVER determines the best optimization for placement ba_format lt format gt Specifies as string which is the format of the back annotation file that will be generated by the implementation tools Possible options are Verilog VHDL EDIF or None The default is VHDL max_pterm_split lt string gt This option lets you control the Fitter optimization process by setting a maximum limit on the number of Product Terms PT in each equation In other words the Optimizer shapes the equations relative to the set number of PT For example
280. ntegration fifo cmp The VHDL component declaration fifo inc Include file AHDL function definition fifo v The Verilog implementation file for expansion in Quartus IT In this example the user has created a top level module called my_fifo v which instantiates the FIFO by using the instantiation template provided To take this design through the basic flow add the Verilog black box declaration and implementation files to the input file list along with the rest of the design files in this case just my_fifo v Right click on the Verilog implementation file in the input file list and select Properties In the input file properties dialog shown in Figure 8 7 check the checkbox marked Exclude file from Compile Phase and click OK Figure 8 7 Excluding the Implementation File from the Compile Phase Input File Properties Ee x File Type veio mI work Library Jor Include File S Search Path Add Before a The input file list in the will now display Excluded to the right of the filename as shown in Figure 8 8 to signify that this file is being excluded from compile Again instead of trying to compile this file Precision simply makes a copy of it in the proper directory in so that the downstream tool can properly expand the design during place and route Precision Synthesis Installation Guide 2003c Update1 8 11 March 2004 Altera Devices Supported Designing with Altera Devices Figure 8 8 Su
281. ock sysclk set_input_delay 2 5 get_ports addr clock rclk set input delay 1 3 get ports ader clock welk Syntax set_input_delay lt delay_value gt lt port_pin_list gt clock lt list gt clock_fall level_sensitive rise fall max min offset add_delay design rtl gatelevel a at Kelockname gt O OO lt Por Pia LISU Arguments lt delay_value gt Specifies the path delay typically from the clock pin of a register outside the current design to the specified input port or pin The lt delay_value gt must be in units consistent with the technology library used during optimization lt port_pin_list gt A list of input port name s or internal pin name s in the current design to which lt delay_value gt 1s assigned If more than one object 1s specified the objects must be enclosed in quotes or in braces Options clock lt list gt This required switch specifies the reference clock may be a virtual clock to which the specified delay is related The delay is relative to the rising edge of the clock unless the optional clock_fall1 option is specified If you are specifying the input delay for a Precision Synthesis Installation Guide 2003c Update 3 181 March 2004 set_input_delay SDC Commands combinational input to output path you must create a virtual clock and use the virtual clock as the reference clock for the input delay value The delay 1s rela
282. oed to the Precision Transcript window without the commands actually being executed by the implementation tools ba_format lt format_list gt Specifies the format of the back annotation file that will be generated by the implementation tools Possible options are Verilog or VHDL layout_mode std tmgdrv A string specifying the layout mode std Standard or tmgdrv Timing Driven The default is std Standard layout maximizes the average performance for all paths Standard layout treats each part of the design equally for performance optimization Standard layout uses net weighting or criticality to influence the results The primary goal of Timing Driven layout is to meet delay constraints set in Timer an SDC file Axcelerator family only a DCF file non Axcelerator families or a GCF file for Pro ASIC and Pro ASICPLUS devices Timing Driven layout s secondary goal is to produce high performance for the rest of the design Delay constraint driven design is more precise and typically results in higher performance Note Timing Driven Layout is only available after you have entered timing constraints layout_runtime lt boolean gt The default is 0 If you specify layout_runtime 1 then the extended runtime attempts to improve the layout quality by using a greater number of iterations during optimization An extended run layout can take up to 5 times as long as a normal layout Note This advanced option
283. oject commands the tool does not use files in temp directories for that project s implementation Note set_preference will be used for other preferences later project usetempdir is the only preference at this time Related Commands set_project_property Precision Synthesis Installation Guide 2003c Update 1 3 203 March 2004 set_project_property Commands set_project_property Set a Precision property indicating whether the current project will use a temp directory for its active implementation the next time the project is opened Example set_project_property usetempdir false Syntax set_project_property usetempdir lt string gt Options usetempdir lt string gt Indicates whether the current project use a temp directory Valid options are true or false Description The set_preject_property command indicates whether the current project will use a temp directory The temp directory is used to store the results for the active implementation until you save the implementation using the save_impl command When you save the results are copied for the temp directory and replace the contents of the impl directory For example if there is an impl named project_14_impl_1 in project_14 then IF temp dirs are enabled for the project a temp directory named project_14_temp_1 will be created to hold the results of project_14_impl_1 until you save Once you save the results are copied back to the p
284. ol applies information only to the RTL design After synthesis the tool creates a technology gatelevel view To indicate that you want attributes applied to the RTL or gatelevel view you must include the design switch and indicate RTL or gatelevel design lt rtl gatelevel gt Tells the tool whether to look for the object in the RTL or the gatelevel view The following example indicates that set_attribute switches should be applied to the gatelevel view set_attribute design gatelevel instance abc name noopt type boolean value TRUE The design switch applies to the following commands report_attributes report_constraints set_attribute set_clock_latency 2 8 Precision Synthesis Installation Guide 2003c Update1 March 2004 Attributes Pre Defined User Attributes set _clock transition set_clock_uncertainty set_false_path set_input_delay set_max_delay set_min_delay set_multicycle_path Mapping Other Attributes to Precision Precision automatically maps other attributes to it s predefined set The following table shows this mapping Syn_keep Preserve_signal A combinatorial signal is defined by this attribute so that this signal is not optimized out during synthesis Syn_preserve Preserve_driver A registered signal is defined by this attribute so that this signal is not optimized out during synthesis Syn_maxfan Max_fanout Sets an individual input port or register output fanout limit in he HDL code S
285. om Xilinx and Altera are register rich and easily accommodate the additional registers inserted through retiming 4 12 Precision Synthesis Installation Guide 2003c Update March 2004 How Precision Compiles Designs How Precision Synthesizes the Design How Retiming Works A circuit with very critical timing will contain many non critical paths that easily meet timing This excess time available for data propagation is called slack and will be unevenly distributed with some circuit paths having negative slacks and some having positive slacks Retiming will be carried out if the proper slack budget is obtained through the proprietary budgeting algorithms If the structure of the circuit is appropriate it is possible to move a register forward or backwards effectively moving some of the delay through the register without affecting the functionality of the design at the primary output ports Ideally the result will be positive slack on both sides of the register Supported Xilinx Technologies Table 4 1 Technologies Supported by Register Retiming Fr APEX 20K 20KC 20KE Virtex VirtexE ea Excalibur Arm Virtex II Pro Stratix StratixGX Spartan H Spartan ITE Note When retiming is enabled for a non supported technology a message will appear in the Transcript Window indicating that Retiming has been turned off Precision Synthesis Installation Guide 2003c Update 4 13 March 2004 How Precision Synthesizes the Design How Preci
286. om the Interactive Command Line Shell More Examples unalias rmc Removes the alias definition of rmc for remove_missing_constraints Related Commands alias help Precision Synthesis Installation Guide 2003c Update 3 229 March 2004 ungroup Commands ungroup Flatten out the hierarchy NOTE This is an advanced command that should only be used from a script after all constraints have been applied to the in memory design Example ungroup ali hierarchy In this example the ungroup command removes all hierarchy under the current design After this command the current design will be a flat netlist of primitives or technology cells Syntax ungroup lt instance_list gt all hierarchy simple_names except lt exclude_instance_list gt force Arguments lt instance_list gt lt exclude_instance_list gt Arguments lt instance_list gt Name or names of instances to decompose into non hierarchical instances You can use names of any existing instances including those created previously with the group command Wildcards are allowed You may use the a11 option in place of specifying instance list Options hierarchy Remove all levels of hierarchy under all instances identified in instance_list then remove hierarchy recursively under each new instance until all levels of hierarchy have been removed simple_names Use original non hierarchical names for new ins
287. ommand file gt option with Bithen Seconds to delay atter generating NPL File E Cancel Apply Help If your web browser is active click on this logo to bring up the Xilinx website home page http www xilinx com Path to Xilinx installation tree Specify the pathname to the Xilinx installation tree for example D Xilinx Precision Synthesis Installation Guide 2003c Update March 2004 9 33 The Xilinx ISE Environment Designing with Xilinx Do not run commands This switch is primarily used for debugging the Precision script that drives the Xilinx ISE tools The commands in the script are echoed to the Precision Transcript window without the commands actually being executed by the implementation tools Place and Route Effort Level Select Normal effort or High effort Back annotation netlist format Specify Verilog EDIF or VHDL for the annotation netlist format Guide File Usage Mode Exact Mode specifies not to make any changes to the layout Used only to make minor changes like replacing a cell Leverage Mode uses the specified guide file as a starting point to improve the placement and routing on the next pass Generate BitGen File Click to generate a Xilinx bit file that will program the Xilinx device Disable logic replication in MAP MAP performs logic replication Logic replication is an ISE optimization method in which MAP operates on a single driver that 1s driving multiple loads and maps it
288. on Guide 2003c Update 3 83 March 2004 get_version Commands get_version Returns the current product version number Syntax get_version Description The get_version command returns the current product version Related Commands 3 84 Precision Synthesis Installation Guide 2003c Update March 2004 Commands group group Group a list of instances into one instance of a new view NOTE This is an advanced command that should only be used from a script after all constraints have been applied to the in memory design Example Syntax group lt list_of_instances gt cell name lt cell name gt vilew_ name lt view_ name gt inst name lt instance_name gt string lt cell_name gt lt view_name gt lt instance_name gt lt list_of_instances gt Arguments lt list_of_instances gt Names of design instances that the group command uses to form a single instance of a new view All instance names must be from the same view test Options cell_name lt cell name gt Name of a new cell to contain the new view If you omit this option the group command automatically generates a name for the new cell The cell name must be a simple name view_name lt view_name gt Name of a new view to contain list_of_instances If you omit this option the lt Command Filename gt group lt list_of_instances gt command automatically generates a name for the new view The view name must be a simple
289. on Guide 2003c Update March 2004 Commands setup design setup design Setup the design environment Syntax setup_design lt library_name gt addio advanced_fsm_optimization architecture lt root_arch name gt basename lt output_file basename gt btw lt best typical worst gt cim lt commercial industrial military gt design lt design_top gt edif family lt library_name gt fault tolerant frequency lt freg_mhz gt impl lt implementation_name gt Deprecated option impl_comment lt active_implementation_comment gt Deprecated option increment Deprecated option input_delay lt input_delay_value gt list_technology manufacturer lt manufacturer s name gt operator_preserve lt operatorname limit gt output_delay lt output_delay_value gt package lt package_name gt part lt part_name gt partition_size xxxx radhardmethod lt method gt reset Deprecated option resource_sharing retiming search_path lt search_pathnames gt speed lt speed_grade gt transformations use_safe_ fsm vendor constraint file verilog vhdl string lt library_name gt lt manufacturer s name gt lt part_name gt lt speed_grade gt lt package_name gt lt commercial industrial military gt lt best typical worst gt lt design_top gt lt root_arch_name gt lt output_file_basename gt lt implementation_name gt
290. on during layout Its value specifies the duration of this phase as a percentage of the default duration The default value is 100 and the selectable range is within 25 500 Reducing the effort level also reduces the run time of Timing Driven place and route TDPR With an effort level of 25 TDPR will be almost four times faster With fewer iterations however performance may suffer Routability may or may not be affected With an effort level of 200 TDPR will be almost two times slower This variable does not have much effect on timing Note This advanced option is only available for the SX SX A and eX families timing_weight lt string gt Setting this option to values within a recommended range of 10 150 changes the weight of the timing objective function thus biasing TDPR in favor of either routability or performance The timing weight value specifies this weight as a percentage of the default weight 1 e a value of 100 will have no effect If you use a value less than 100 more emphasis will be placed on routability and less on performance Such a setting would be appropriate for a design that fails to route with TDPR In case more emphasis on performance is desired set this variable to a value higher than 100 In this case routing failure is more likely A very high timing value weight could also distort the optimization process and degrade performance A value greater than 150 1s not recommended Note This advanced option is only
291. ontrol the movement of flops using the inff outff and triff attributes You can also set this attribute in the GUI by right clicking on the port and selecting the Force Register into IO item in the popup Verilog pragma attribute data_sum iob true VHDL attribute iob String attribute iob of data_sum signal is true Interactive Command Line Shell set_attribute net data_sum name iob value true liostandard Specifies the IO standard to be used Verilog pragma attribute port tx IOSTANDARD LVTTL VHDL attribute IOSTANDARD string attribute IOSTANDARD of port_tx signal is LVITL Interactive Command Line Shell set_attribute design gatelevel name IOSTANDARD value LVTTL port tx 2 16 Precision Synthesis Installation Guide 2003c Update1 March 2004 Attributes Pre Defined User Attributes map_complex Obsolete You should use the technology independent iob attribute max_fanout Allows you to change the fanout limit on the specified net The default fanout limit is normally set in the technology library Precision Synthesis attempts to maintain reasonable fanouts by replicating the driver which results in net splitting If replication is not possible then the signal is buffered This may make the wire slower by adding intrinsic delays Verilog pragma attribute net_internal max_fanout 10 VHDL attribute max_fanout integer attribute max_fanout of net_internal signal is 10
292. or the path spdno speed no Collapses all nodes up to the set Product Term limit without increasing area cost spdfmax Causes the Logic Optimizer to automatically identify all critical paths between any pair of registers from clock pin of one register to data pin of the other register or the same register The Logic Optimizer then attempts to collapse combine the logic nodes along the critical paths reduce the logic level and allow the chip to run at a higher frequency If you specify an empty string the default then ispLEVER determines the best optimization for placement ba_format lt format gt Specifies as string which is the format of the back annotation file that will be generated by the implementation tools Possible options are Verilog VHDL EDIF or None The default is VHDL max_pterm_split lt string gt This option lets you control the Fitter optimization process by setting a maximum limit on the number of Product Terms PT in each equation In other words the Optimizer shapes the equations relative to the set number of PT For example if the value is set to 35 the Optimizer splits equations if it has more than 35 PT This option works the opposite of Collapsing Max Product Term Precision Synthesis Installation Guide 2003c Update 3 107 March 2004 place_and_route Commands max_pterm _collapse lt string gt This option lets you control the Fitter optimization process by se
293. ort only those paths through these nets or instances from lt start_points gt Reports paths that originate at the indicated input ports port_inst s or clock s If you enter the following command you can observe paths that have as their source or destination the specified clock report timing irom CO Chk to lt end_points gt Reports paths that end at these output ports port_inst s or clock s If you enter the following command you can observe paths that have as their source or destination the specified clock report timing i rom bo CLRI See the Clock Overview section in the Precision RTL Synthesis User Manual for more information on what the tool reports based on clock names setup_flag Provide a setup slack path detail report physical Provide physical placement information critical_paths Provide information on critical paths end_points Provide summary information on end points start_points Provide summary information on start points clock_frequency Report the clock frequency estimates clock_list lt list_of_clocks gt Report clock frequencies on the list of clocks if all clocks are unset hold_flag Provide a hold slack path detail report 3 156 Precision Synthesis Installation Guide 2003c Update March 2004 Commands report_timing all_clocks Report the worst path for each clock group nworst lt number_of_paths gt Report on
294. oute command settings can be specified from the GUI in the Tools gt Set Options lt P amp R Flow gt dialog box If you are executing commands from a shell command line you can override one of these preset options when you execute the place_and_route command Flow Arguments lt flow_name gt The name of the place and route flow Currently the following flows are supported Actel Designer Max PLUS IT Quartus II LSOLEVER ispLEVER ORCA ISE 5 1 3 218 Precision Synthesis Installation Guide 2003c Update March 2004 Commands setup_place_and_route Actel Actel Designer Command Names Launch Designer Set the options specified in the Launch Designer dialog box Integrated Place and Route Set the options specified in the Integrated Place and Route dialog box Generate Actel Script File Set the options specified in the Generate Actel Script File dialog box Actel Actel Designer Command Arguments install_dir lt vendor_installation_directory_pathname gt Specifies the pathname to the Actel Designer installation tree No exec This option is primarily used to debug the Precision place_and_route script that drives the implementation tools The commands in the script are echoed to the Precision Transcript window without the commands actually being executed by the implementation tools ba_format lt format_list gt Specifies the format of the back annotation file that will be generated by the implementation
295. plementation to disk Syntax Save_impl Description The save_imp1 command is a project manager command available only when a project is loaded and an implementation is active This command saves any unsaved work in the active implementation The outstanding changes are written to the implementation directory in the project folder Related Commands activate_impl get_project_impls copy_impl new_impl delete_impl Oopen_project get_impl_property set_impl_property Precision Synthesis Installation Guide 2003c Update 3 159 March 2004 save_path_definition_sets Commands save_path_definition_sets Saves the defined Path Definition sets into an external file Applies only to Precision Physical Example save_path_definition_sets pathdef Syntax save_path_definition_sets lt file_ name gt Description This command saves the defined Path Definition sets into an external file If lt file name gt 1s omitted the sets are saved into the lt design_name_pds gt tcl file in the design directory The source Tcl command is used to load a previously saved Path Definitions file source lt fiile name pds gt tol Related Commands get_path_definition_set delete_path_definition_set create_path_definition_set 3 160 Precision Synthesis Installation Guide 2003c Update1 March 2004 Commands save_physical save_physical Saves the in memory physical database to the active implementation directory Example save_physical Synta
296. project If the desire is to have Precision automatically generate the UCF timing constraints regardless of the source then disable the UCF flow If the UCF Timing Constraint option is enabled Precision will copy the user created timing constraints in the UCF file into the inplimentation folder for use by ISE Unless you have a specific need to constrain or generate the UCF timing constraints through synthesis then use the default flow Synthesis will be constrained by the translated UCF constraints and the generated UCF file from this flow will preserve the original UCF timing Including Xilinx Coregen Generated Modules Xilinx high performance cores may be delivered in a hierarchical fashion The following figure shows an example of coregen files that you might have in a design Figure 9 1 Coregen Files cam_input_1 ngce cam_control_3 ngc Precision Synthesis Installation Guide 2003c Update 9 3 March 2004 Handling Xilinx Design Issues Designing with Xilinx Adding Input Files You start working with Coregen files by creating a directiory for the hierarchical coregen files then adding all coregen files including the ngc files to an input file list as shown in the following example Figure 9 2 Adding Coregen input files Look ir E HierarchicalCoregen de t F lt Icam only impl 1 sete getCam edn Benchmarks a cam_cam_input_1 ngc 1 Add netlist Fz cam_cam_encode_2 nqge fil ies a cam c
297. pter 5 Files Reference Understanding the Files in a Working Directory The working directory 1s the place where you will normally keep all your design source files and where Precision RTL Synthesis places all generated output files When you work in project management mode the working directory is referred to as the Project Folder Since there are many files to keep organized it is common to divide the files into sub directories or sub folders The following figure illustrates one way to organize the files in a working directory This structure is very similar to the directory structure created by Precision s project management system Figure 5 1 Files in the Project Directory Project Directory precision log lt design_name gt psp a vhd PUN sl lt design_name gt edf b vhd lt design_name gt xdb Cevna top vhd lt design_name gt _area rep lt design_name gt _timing rep constraints sdc l lt design_name gt _info sdc The files on the left are design source files and are typically keep in a separate sub directory The Master Constraint File listed last is read in with the design and serves as a starting point for setting or modifying additional constraints manually from the GUI Precision Synthesis Installation Guide 2003c Update 5 1 March 2004 Understanding File Extensions Files Reference The files in the center are generated by Precision RTL Synthesis and are always placed in the project directory by de
298. put Write clock input Write enable input addr input gt addr2 input addr3 output QUCA output Outa input datain reg 0 mem 0 31 A 32 x 8 bit memory array reg outar OUES always posedge clk begin if wen begin mem addr1l lt datain end out2 lt mem addr2 out3 lt mem addr3 end endmodule 9 24 Precision Synthesis Installation Guide 2003c Update1 March 2004 Designing with Xilinx Handling Xilinx Design Issues Tri Port RAM Sync Write Sync Read Sync Read Two Clocks In the Verilog code in Figure 9 22 one clock is used for the write operation on Port A and a separate clock is used for the read operations on Ports B and C A set of dual port Block RAMs are inferred for port A and B and another set of dual port Block RAMs for port A and C Figure 9 22 Tri Port RAM Sync Write Sync Read Sync Read Two Clocks module swe _ srel srel celki clk2 wen eddril addrz addrs out2 out3 datain inp t ciki Write clock input clkz input wen Write enable input 4 addr 4 addr2 input inpu rt 4 addr3 CuTpPUL 7 G ta output iss outa input datain reg 0 mem 0 31 A 32 x 8 bit memory array reg 0J o ut2 Out 3s always posedge clk1 begin if wen begin mem addrl1 lt datain end end always posedge clk2 begin out2 lt mem addr2 out3 lt mem addr3 end endmodule Port A Both Written and Read Port A
299. put files are generated based on the root name of the last file in the list Elaborating the Design During the elaborate phase Precision Synthesis converts the HDL into an EDIF like in memory database The design is composed of generic gates and the black box operators In the synthesize process these cells will be replaced with efficient technology specific operators from a vendor supplied modgen library The elaborated design is placed in the working library You can have more than one working library in the database Typically the working library is called work The following list shows that types of logic that is elaborated during the compile process Generating Hierarchy on page 4 3 Infer Sequential Elements on page 4 4 Infer Operators on page 4 5 Infer RAMs on page 4 5 Implements Finite State Machines on page 4 6 Generating Hierarchy Precision generates a hierarchical block whenever it encounters an instantiation Hierarchy is obtained by creating instances of other modules a top module is one that is not instantiated by another module Precision has the ability to detect one or more top modules automatically as Precision Synthesis Installation Guide 2003c Update 4 3 March 2004 How Precision Compiles the Design How Precision Compiles Designs it reads them in Each top module is compiled and synthesized the last top module detected is synthesized last and set to the cur
300. put ports in the current design The search can be limited to input ports that have constraints relative to a given clock all_outputs SDC Return a list of all output ports in the current design The search can be limited to input ports that have constraints relative to a given clock all_registers Return a list of all sequential elements or sequential pins in the current design Precision Synthesis Installation Guide 2003c Update 1 3 1 March 2004 Command Summary Commands Table 3 1 Alphabetical Command Summary continued close_project Close the current project close_results_dir Unload the currently loaded design Available only when no project is open Compile the design that is specified by the compile input_file_list copy_impl Create a copy of an existing implementation within the project create_clock SDC Define a new clock for the current design create_path_definition_set Define and add a Path Definition Set which 1s a set of from through and to lists current_design SDC Set the current design current_instance SDC Set the working instance in the design hierarchy which will allow other commands to set or get attributes from that instance delete_impl Delete an implementation in the current project delete_path_definition_set Execute a Tcl script and print a message as each command in the script is executed edit Invoke the Precision Synthesis text editor on the specifie
301. q240 v800 bg432 bg560 fg676 fg680 hq240 v1000 bg560 cg560 fg680 lt N 38 Precision Synthesis Installation Guide 2003c Update1 March 2004 Designing with Xilinx Xilinx Devices Supported Spartan lll Devices Supported Spartan III Devices Supported Internal Library Name xis3 xc3s5000 fg900 fg1156 Spartan III Speed Grades Default Speed Grade 4 Speed Grades supported 4 Spartan llIE Devices Supported Spartan ITE Devices Supported Internal Library Name xis2e 2s100e t256 fg456 pq208 tq144 2s150e ft256 fg456 pq208 2s300e fg256 fg456 pq208 2s400e fg256 fg456 fg676 2s600e fg456 fg676 2s200e fg256 fg456 pq208 Precision Synthesis Installation Guide 2003c Update 9 39 March 2004 Xilinx Devices Supported Designing with Xilinx Spartan IIE Speed Grades Default Speed Grade 7 Speed Grades supported 6 7 Spartan ll Devices Supported Spartan IT Devices Supported Internal Library Name xis2 28200 fg256 fg456 pq208 Spartan II Speed Grades Default Speed Grade 6 Speed Grades supported 5 6 Xilinx CPLD Family Devices Supported 95108 PC84 PQ100 PQ160 TQ100 40 Precision Synthesis Installation Guide 2003c Update1 March 2004 Designing with Xilinx Xilinx Devices Supported 95144 PQ100 PQ160 TQ100 95216 PQ160 HQ208 BG352 95288 HQ208 BG352 Xilinx CPLD Family Xilinx XC9S00XL Default Speed Grade 5 Speed Grades supported
302. r example you could enter the following set_input_dir c temp design precision agd_inout file blackbox bbl v add inouct_tile hal top v When a project is opened the project directory is the default input directory The input directory can be changed for each implementation Related Commands add_input_file remove_input_file move_input_file report_input_file_list Precision Synthesis Installation Guide 2003c Update 3 185 March 2004 set_input_file Commands set_input_file Set the attributes on the specified input file Example set_input_file F design src statemachine vhd Syntax set_input_file file pathname format lt file type gt work lt library_name gt exclude search_path lt pathname_list gt Type list lt file pathname gt lt pathname_list gt lt file_type gt lt library_name gt Options format lt file_type gt Specifies the file type for a file that doesn t have the proper extension Valid values are vhdl verilog edif syn lib tel xnf xdb sdf If this option is not used and a valid extension exists then the file type will be automatically detected work lt library_name gt Specifies the name of the work library for compiling the content of the file If not specified then the work library name work is assumed search_path Specifies additional include search paths that are pre pended to the global include search path that is specified in t
303. raint with the lower value For set_min_delay and set_multicycle_path hold itis the constraint with the higher value Related Commands set_false_path SDC set_multicycle_path SDC set_input_delay SDC set_min_delay SDC set_output_delay SDC 3 190 Precision Synthesis Installation Guide 2003c Update March 2004 Commands set_max_fanout SDC set_max_fanout SDC Limit the maximum number of pins that a net or port can drive Example set_max_fanout 3 alu mult_en set _max fanout 10000 reset Syntax set_max_fanout lt value gt lt port_net gt Arguments lt value gt Specifies the maximum number of pins that the specified net or port can drive lt port_net gt Specifies the driving port or net This value must be a hierarchical pathname Description The set_fanout_load command defines the maximum number of pins that the driving port or net can have This value overrides the library default value set by the vendor This command may be used to prevent buffering or logic replication on non timing critical nets This command is often used to decrease the maximum fanout on a net in a critical path This command also sets the fanout_load for Actel and Quicklogic technologies or the lut_max_fanout of technologies like Altera and Xilinx You can use the report_net command to view the capacitance and fanout loading information of a specific net s Related Commands Precision Synthesis Installation Guide
304. rating levels in a hierarchy description The default is dot Precision Synthesis Installation Guide 2003c Update 3 179 March 2004 set_impl_ property Commands set_impl_ property Set the name or comment value of an implementation Example s t impl property impl new_clock_2 name new_clock_3 Syntax set_impl_property impl lt impl_name gt name comment lt impl_name gt Options impl lt impl_name gt Specifies the name of an inactive implementation in the current project If impl is not used the command operates on the active implementation name comment o The name option changes the name of the implementation file psi and the implementation directory to the specified name o The command option sets the comment property to the specified string Description The set_impl_property command is a project manager command available only when a project is loaded It sets the value of either the name property or the comment property of the active implementation Use the impl option to set a property of an inactive implementation Related Commands activate_impl get_project_impls copy_impl new_impl delete_impl save_impl get_impl_property 3 180 Precision Synthesis Installation Guide 2003c Update March 2004 Commands set_input_delay SDC set_input_delay SDC Set input delay on pins or input ports relative to a clock signal Example set_input_delay 3 0 all_inputs cl
305. rch 2004 Commands report_constraints report_constraints List user specified constraints on any object Example report_constraints port Syntax report_constraints lt design_name gt hierarchy net design rtl gatelevel Arguments lt design_name gt Name of the design for which to report constraints If you omit this argument the command operates on the current design This argument is valid only if the design is a view Options port Report constraints on ports only If you omit this argument both port and net constraints are reported net Report constraints of nets only If you omit this argument both port and net constraints are reported hierarchy Report constraints on all levels of hierarchy in the design If you omit this option only constraints at the top level of hierarchy are reported design lt rtl gatelevel gt Tells the tool whether to look for the object in the RTL or the gatelevel view Precision Synthesis Installation Guide 2003c Update 3 135 March 2004 report_constraints Commands Description The report_constraints command returns a list of the currently defined SDC constraints Design constraints are modeled as attributes on design objects like ports nets and instances You can use the following methods to set constraints Use the Precision Synthesis GUI to right click on objects in the Design Hierarchy pane Include an SDC Synopsys
306. rch 2004 create_path_definition_set Commands create_path_ definition set Define and add a Path Definition Set which is a set of from through and to lists Applies only to Precision Physical Example create_path_definition_set name design_list from D1 thru D5 Syntax create_path_definition_set name lt path_definition_set_name gt from lt from list gt thr lt tnhr list gt to lt to List gt j Arguments name path_definition_set_name Name of the path definition set Options from lt from_list gt Specifies the name of the first net in the list thru lt thru_list gt Specifies the name of the final net in a thru list to lt to_list gt Specifies the name of the final net in a from to list Description Use this command to add a path definition set which 1s a list of from and through lists Related Commands delete_path_definition_set get_path_definition_set 3 44 Precision Synthesis Installation Guide 2003c Update1 March 2004 Commands current_design SDC current_design SDC Set the current design Example current_design Syntax current_design top Options top Sets the current design to the top level of the hierarchy Presently the current design can only be set to the top level of hierarchy Description The current_design command returns the name of the current design At this time there can only be one current design loade
307. re attributable to the infringement action You understand and agree that as conditions to Mentor Graphics obligations under this section you must a notify Mentor Graphics promptly in writing of the action b 10 11 12 13 14 15 16 17 provide Mentor Graphics all reasonable information and assistance to defend or settle the action and c grant Mentor Graphics sole authority and control of the defense or settlement of the action 9 2 If an infringement claim is made Mentor Graphics may at its option and expense a replace or modify Software so that it becomes noninfringing b procure for you the right to continue using Software or c require the return of Software and refund to you any license fee paid less a reasonable allowance for use 9 3 Mentor Graphics has no liability to you if infringement is based upon a the combination of Software with any product not furnished by Mentor Graphics b the modification of Software other than by Mentor Graphics c the use of other than a current unaltered release of Software d the use of Software as part of an infringing process e a product that you make use or sell f any Beta Code contained in Software g any Software provided by Mentor Graphics licensors who do not provide such indemnification to Mentor Graphics customers or h infringement by you that is deemed willful In the case of h you shall reimburse Mentor Graphics for its attorney fe
308. recision A shell level command that invokes Precision RTL Synthesis as well as Precision Physical Synthesis remove_attribute Remove an attribute from the specified object s Remove the clock information from the specified object s remove_clock Remove a list of designs or libraries from the in memory database remove_design remove_input_delay Remove the Input Delay on the specified pins or input ports Remove one or more input files from the input_file_list remove_input_file Remove the Output Delay on the specified pins or output ports remove_output_delay Return information on how the specified timing report options are set report_analysis report_area Report the accumulated area of the current design Generate a report that lists attributes on the specified objects report_attributes report_connections Generate a report containing objects that are connected to the specified object s report_constraints List user specified constraints on any object report_design_impl_list Returns a list of design implementations Go I 4 Precision Synthesis Installation Guide 2003c Update1 March 2004 Commands Command Summary Table 3 1 Alphabetical Command Summary continued report_input_file_list Return a list of the current input files report_library Report information on the specified technology library report_license Return a list of the license features that are currently in use report
309. ren ven Tse nt 1 terete tere est rcenne Terese 2 19 Ss baker foe E EIEEE A enone Taree nee eet ee Meee TEE AN PENA E E A 2 19 A se aeencn casa E E EENE EEE OEA AAE A A E EA 2 20 i ola E a A E E A EEA 2 20 a n e aaa Bs Us lo PE E EEE PEE EE AAEE EALE TENEO EAEE PEETA I TEET 2 21 LS T A AAS 2 22 SS Le ne ee ene ne ee an ee nae ne ne ee eT eT een ee eee arene eee eae oe Te me 2 22 a O ae dad rE E ETE nies ae ees 2 23 Sib Mee O68 a cee Eat gee Seen ee ee Me ane Stan EA ren rer ONT een enrer ere yr creer tamer tre eTe ert ttre 2 23 ai U peepee vc PEN EEAS EEEF AES kv ands cat etic eas gn TITTIES AILIS ESOPE eee 2 23 Nee ER gL 22 EEIE oe eo oe ae een area ere eee en ee eee eee St Mare A E A trae 2 24 Chapter 3 Commands Corman S AT rire ceneriarssrmintesenreancenengabcaaharteeasisoensean E denna 3 1 Fonciona i Lisi sios ER 3 8 D l e a E N R 3 15 GD EO A E A E ating 3 16 ada macto TIS capes wecnacevecaawicsceetineenires A AER EAA EEE EE EE EAER 3 19 a E Aer Teen T naeR enn Meigen Manne ene Mer Cheer ee ener ere 3 21 gs senescence ees een ese ghee ced nd ace nace ee dense sn ete 3 23 E sel 2g td Be Sg Re nnn ee te ee ene nee ane EO EEEE eee ee NAAA AE ey mane eee arte re 3 24 BU E erecacease tesco ssc Gam ate et pnts cast a atk ssc penton in mney nse nso 3 26 SIRE the bo BGS e erence eee ante tenner averse na rinn tanner ery teres y erst hater eens Theos tr Senet rrr Ter srerer 3 27 R Cie Le be Ge E ae es eer A E reer et ae ae T E EE N A rn ens ieee
310. rent view 1 e the current module in Precision memory You can use the top lt module_name gt command line option to force module_name as the only module to be synthesized Handling empty cells After Precision reads a VHDL or Verilog design the design might initially contain empty cells that Precision attempts to map to actual cells Precision represents these cells as black boxes Empty cells can result when you use the following techniques Performing incremental synthesis Precision allows you to synthesize a portion of a design while leaving empty cells for blocks that you have not yet created Mapping to Library primitives Your VHDL or Verilog code can directly instantiate technology specific primitives Library cells must match the cell name number of ports and port names including case In order to use the preceding techniques empty cells must result from one of the following Empty Verilog modules A VHDL component declaration with without an associated entity but no architecture After reading VHDL or Verilog Precision also represents operators as empty cells until they are automatically converted to technology specific implementations during optimization Therefore empty operator cells are not discussed in this section Infer Sequential Elements Flip flops Flips are inferred from always blocks in verilog and process statements in VHDL As long as the flop eventually affects the output of the design it will
311. rent_design SDC 3 46 Precision Synthesis Installation Guide 2003c Update March 2004 Commands delete_impl delete_impl Delete an implementation in the current project Example delete_impl impl uart_top_impl_1l Deletes the implementation named uart_top_imp1_1 which may be the active implementation Syntax delete_impl impl lt impl_name gt ae Options impl lt impl_name gt The name of an implementation in the current project If impl is not specified the active implementation is deleted Description The delete_imp1 command is a project manager command available only when a project is open It deletes the currently active implementation or the implementation specified by the impl option This command immediately deletes the implementation folder and all files in that folder and removes the implementation from the project If the active implementation is deleted then no implementation is active until you activate one by calling the activate _impl command Related Commands activate_impl new_impl copy_impl save_impl get_impl_property set_impl_property get_project_impls Precision Synthesis Installation Guide 2003c Update 3 47 March 2004 delete_path_definition_set Commands delete_path_definition_set Deletes a previously defined Path Definition set or all sets Applies only to Precision Physical Example gt delete path definition set name route2 Syntax get_path_definition_se
312. ress bus gt set_input_delay 5 get_ports addr_bus clock clk_100mhz The following example returns all c k ports on instances within current level of hierarchy set by current_instance gt Geb _ porte cLlk Uxeclk sys rx clk voo clk 100mhzZ voo cLk our Example get_ports addr_bus Syntax get_ports lt patterns gt Description The get_ports command searches for the specified pattern in the design relative to the current_instance and returns a list of ports If the port 1s at a different level of hierarchy this command returns the absolute instance path with the port name regardless of the value of current_instance You can use absolute instance pathnames or pathnames relative to the current_instance The value of current_instance is only used as the relative top of hierarchy that 1s searched By default the current_instance is set to current_design top of the design hierarchy You can also use wildcards and all object names are case sensitive If you omit the search pattern the tool returns an error 3 78 Precision Synthesis Installation Guide 2003c Update March 2004 Commands Related Commands get_cells SDC get_clocks SDC get_designs get_false_paths get_lib_cells SDC get_lib_cells SDC get_lib_cells SDC get_lib_pins SDC get_multicycle_paths get_nets SDC get_path_definition_set Precision Synthesis Installation Guide 2003c Update March 2004 get_ports SDC 3 79
313. rgets are automatically derived from clock waveforms and port input or output delays For more information refer to the create_clock SDC set_input_delay SDC and set_output_delay SDC reference pages If a path satisfies multiple timing exceptions the following rules are used in order to determine which exceptions take effect 1 If both exceptions are set_false_paths there 1s no conflict 2 If one exception is a set_max_delay and the other is set_min_delay there is no conflict Precision Synthesis Installation Guide 2003c Update 3 189 March 2004 set_max_delay SDC Commands 3 If one exception is a set_multicycle_path hold and the other is set_multicycle_path setup there is no conflict 4 If one exception is a set_false_path and the other 1s not the set_false_path takes precedence 5 If one exception is a set_max_delay and the other is not the set_max_delay takes precedence 6 If one exception is a set_min_delay and the other is not the set_min_delay takes precedence 7 If one exception has a from pin or from cell and the other does not the former takes precedence 8 If one exception has a to pin or to cell and the other does not the former takes precedence 9 If one exception has any through points and the other does not the former takes precedence 10 The exception with the more restrictive constraint then takes precedence For set_max_delay and set_multicycle_path setup this is the const
314. rilog primitives or basic VHDL operators AND OR XOR If you omit this option Precision writes the netlist with instantiated technology cells silent Do not write any warning or informational messages format lt format_ name gt Specify the format vhdllveriloglediflxdblsdf single_level Write only the current top level of hierarchy set by current_design If you omit this option Precision writes the contents of the entire hierarchical tree Description By default the synthesize command writes the technology netlist and constraints file at the end of optimization The auto_write command is usually used to write additional netlists e g in an additional format or to write netlists at intermediate stages of the synthesis process e g after compile Related Commands set_working_dir Deprecated synthesize setup_design Precision Synthesis Installation Guide 2003c Update 3 33 March 2004 close_project Commands close_project Close the current project Example close_project Close the current project and the active implementation Syntax close_project discard Options discard Discard any unsaved work in the active implementation Description The close_project command is a project manager command available only when a project is loaded It closes the current project An error occurs if the currently active implementation has unsaved work Use the discard option to discard the unsaved
315. rmal conditions as directed by Mentor Graphics You will contact Mentor Graphics periodically during your use of the Beta Code to discuss any malfunctions or suggested improvements Upon completion of your evaluation and testing you will send to Mentor Graphics a written evaluation of the Beta Code including its strengths weaknesses and recommended improvements You agree that any written evaluations and all inventions product improvements modifications or developments that Mentor Graphics conceives or made during or subsequent to this Agreement including those based partly or wholly on your feedback will be the exclusive property of Mentor Graphics Mentor Graphics will have exclusive rights title and interest in all such property The provisions of this subsection shall survive termination or expiration of this Agreement 4 RESTRICTIONS ON USE You may copy Software only as reasonably necessary to support the authorized use Each copy must include all notices and legends embedded in Software and affixed to its medium and container as received from Mentor Graphics All copies shall remain the property of Mentor Graphics or its licensors You shall maintain a record of the number and primary location of all copies of Software including copies merged with other software and shall make those records available to Mentor Graphics upon request You shall not make Software available in any form to any person other than employees and contractors excludin
316. rmed by the load_project command is now provided by the open_project command Although load_project is still supported you should use open_project Note instead because load_project may become unsupported at some future release The load_project command sources a Tcl file that is able to restore the project settings from a previous session When sourced from the File gt Open Project dialog box or from the command line this file will set the working directory restore the design environment through a series of setup_design commands add the input files and add any constraint files that are present When the file is finished executing the design 1s ready to compile Related Commands Open_project report_project Precision Synthesis Installation Guide 2003c Update 3 91 March 2004 logfile Commands logfile Configure the logfile name and location Example logfile open name logfile_pass2 Syntax logfile open move name lt file_name gt append close save_commands Valid argument combinations logfile open name lt file_name gt append logfile open name lt file_name gt append logfile close logfile save_commands name lt file_name gt Options string lt file_name gt open Creates a new logfile move Changes the logfile to the specified new name name lt file_name gt Specifies the name of the new log file append Append the content of
317. ro Devices Supported 9 36 Precision Synthesis Installation Guide 2003c Update March 2004 Designing with Xilinx Xilinx Devices Supported 2VP125 f1696 ff1704 2VPX20 f896 2VPX70 ff81517 ff1704 IRTEX IT Pro Speed Grades Default Speed Grade 7 Speed Grades supported 5 6 7 Virtex Il Devices Supported irtex II Speed Grades Default Speed Grade 6 Speed Grades supported 4 5 6 4s1 5s1 Precision Synthesis Installation Guide 2003c Update 9 37 March 2004 Xilinx Devices Supported Designing with Xilinx Virtex E Devices Supported Virtex E Devices Supported Default Speed Grade 8 Speed Grades supported 6 7 8 v50e s144 pq240 fg256 v100e s144 pq240 bg352 fg256 v200e s144 pq240 fg256 fg456 bg352 fg456 v300e pq240 bg352 bg432 fg256 fg456 v400e pq240 bg432 bg560 fg676 v405e bg560 fg676 v600e hq240 bg432 bg560 fg676 fg900 fg680 v1000e hq240 bg560 fg900 fg1156 fg680 fg860 v1600e pg560 fg900 fg1156 fg680 fg860 v2000e bg560 fg1156 fg680 bg860 v812e bg560 fg900 v2600e fg1156 v3200e Virtex Devices Supported Virtex Devices Supported Default Speed Grade 4 Speed Grades supported 4 5 6 0 bg256 pq240 cs144 tq144 fg256 v100 bg256 cs 144 fg256 pq240 tq144 cb228 v150 0g352 fg256 fg456 pq240 bg256 v200 Dg352 fg456 pq240 bg256 fg256 v300 0g352 bg432 fg456 pq240 cb228 v400 Dg432 bg560 fg676 hq240 bg432 bg560 v600 bg432 bg560 fg676 fg680 h
318. roject_14_impl_1 folder set_project_property is used to indicate whether the current project should use temp directories for the active implementation results The command saves your choice in the project s psp file and restores it when the project is next loaded Related Commands set_preference 3 204 Precision Synthesis Installation Guide 2003c Update March 2004 Commands set_propagated_clock SDC set_propagated_ clock SDC Specifies the cell delays in the clock network should be used Example set_propagated_clock sys_clk90 set_propagated_clock all_clocks Syntax set_propagated_clock object_name Arguments object_name Description The set_propagated_clock command allows Precision to use the cell delays in the clock network If this command is not set for a defined clock then Precision uses the ideal clock latency of zero This command is typically used with Precision Physical Related Commands set_false_path SDC set_multicycle_path SDC set_input_delay SDC report_missing_constraints set_output_delay SDC Precision Synthesis Installation Guide 2003c Update 3 205 March 2004 set results dir Commands set_results dir Set explicitly where output files will be written when not using projects Example set_results_dir C designs Syntax set_results_dir lt results_dir_path gt lt results_dir_path gt Arguments lt results_dir_path gt A full pathname to a directory wher
319. rrupted or error free The warranty period is 90 days starting on the 15th day after delivery or upon installation whichever first occurs You must notify Mentor Graphics in writing of any nonconformity within the warranty period This warranty shall not be valid if Software has been subject to misuse unauthorized modification or installation MENTOR GRAPHICS ENTIRE LIABILITY AND YOUR EXCLUSIVE REMEDY SHALL BE AT MENTOR GRAPHICS OPTION EITHER A REFUND OF THE PRICE PAID UPON RETURN OF SOFTWARE TO MENTOR GRAPHICS OR B MODIFICATION OR REPLACEMENT OF SOFTWARE THAT DOES NOT MEET THIS LIMITED WARRANTY PROVIDED YOU HAVE OTHERWISE COMPLIED WITH THIS AGREEMENT MENTOR GRAPHICS MAKES NO WARRANTIES WITH RESPECT TO A SERVICES B SOFTWARE WHICH IS LICENSED TO YOU FOR A LIMITED TERM OR LICENSED AT NO COST OR C EXPERIMENTAL BETA CODE ALL OF WHICH ARE PROVIDED AS IS 5 2 THE WARRANTIES SET FORTH IN THIS SECTION 5 ARE EXCLUSIVE NEITHER MENTOR GRAPHICS NOR ITS LICENSORS MAKE ANY OTHER WARRANTIES EXPRESS IMPLIED OR STATUTORY WITH RESPECT TO SOFTWARE OR OTHER MATERIAL PROVIDED UNDER THIS AGREEMENT MENTOR GRAPHICS AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND NON INFRINGEMENT OF INTELLECTUAL PROPERTY LIMITATION OF LIABILITY EXCEPT WHERE THIS EXCLUSION OR RESTRICTION OF LIABILITY WOULD BE VOID OR INEFFECTIVE UNDER APPLICABLE LAW IN NO EVENT SHALL MENTOR GRAPHICS
320. rs and primary inputs related to that clock are used as path startpoints to lt to_list gt A list of names of clocks ports pins or cells to use to find path endpoints If you specify a clock either user defined or automatically derived clockname all registers and primary outputs related to that clock are used as path endpoints If you specify a register one path endpoint on that cell is affected For general information on derived clocks see the Clock Overview section in the Precision RTL Synthesis User Guide through lt through_list gt A list of path throughpoints port pin or leaf cell names of the current design The multicycle values apply only to paths that pass through one of the points in the through_list If more than one object is included the objects must be enclosed either in quotes or in braces If you specify the through option multiple times the multicycle values apply to paths that pass through a member of each through_list in the order the lists were given In other words the path must first pass through a member of the first through_list then through a member of the second list and so on for every through list specified If the through option is used in combination with the from or to options the multicycle values apply only if the from or to conditions are satisfied and the through conditions are satisfied reset_path Indicates to remove existing point to point exception
321. rs that have the same clock propagated regardless of the setting of the domain switch in the create_clock command Precision considers derived clocks such those that pass through DCMs the same clock Clock division or multiplication at the destination registers do not effect edge separation This switch is an SDC extension to allow better modeling of the Xilinx OFFSET constraint and greatly improve the timing correlation between Precision and Xilinx add _delay Specifies whether to add delay information to the existing output delay or to overwrite the value The add_delay option enables you to capture information about multiple paths leading to an output port that are relative to different clocks or clock edges design lt rtl gatelevel gt Tells the tool whether to look for the object in the RTL or the gatelevel view Description Output Delay Defined Output delay is the delay required outside of the current design in order to properly clock the driven device Output delay is the inverse of the term required time that may be used 1n other Mentor Graphics tool environments As shown in the following illustration 1f the reference clock period is 10 ns and the output delay is specified as 4 ns then Precision Synthesis will constrain the combinational path from the clock pin of the internal register of the current design to the specified output port to 6 ns Precision Synthesis Installation Guide 2003c Update 3 201 March 2004 s
322. rt_file_name gt cell_ usage hierarchy all leafs lt report_file name gt Arguments lt report_file_name gt Name of the output file in which to write the design area report If you omit this argument the report goes to standard output screen Options cell_usage Report cell usage per instance in design hierarchy Report all levels of hierarchy separately all_leafs Report on all leaf cells including black boxes autoselect Autoselect the part based on port count and area Description The report_area command is a general purpose area reporting routine For a technology independent not optimized design the report_area all_leafs command gives an overview of the complexity of the design prior to technology mapping Precision Synthesis Installation Guide 2003c Update 3 129 March 2004 report_area Commands The report includes the total number of primitives AND OR and operators add subtract multiply and a count of the black boxes On a mapped optimized design the same command produces a report that includes technology specific area information function generators and flip flops for Xilinx designs combinational and sequential modules for Actel designs More Examples PRECISION report area KKEKKKKKKKKKKKKKKKKRKEKKKRKRKKKKKKKKKKKK KKK KKK KKRKKKKKKKKKEKKKE Cell traffic View precision Library work kkxkxkxkxkxkxkxkxkxkxkxkxkxkxk xkxkxkxkxkxkxkxkxkxkx
323. rves the specified signal and the driver in the design preserve_signal Preserves the specified signal in the design preserve_z Prevents tri states from being mapped to MUX logic radhardmethod Actel Creates a radiation hardened implementation safe_fsm Specifies that the Finite State Machine should be built as a safe FSM preserve_driver synthesis_clearbox Specifies that Precision should generate timing models for Altera blackboxes using Altera s clearbox timing generator This will have a noticeable affect on runtime but it provides more accurate timing reports This attribute can be applied to the top of the design or to individual hierarchical blocks type_encoding_style Specifies the style of encoding for a Finite State Machine triff Tells Precision Synthesis whether or not to map the candidate register in the path to a register in the IOB By default Precision maps the register to the IOB if this attribute is not present The attribute is applied to the inout port uselowskewlines Tells the implementation tools to assign the specified signal to a low skew route line Precision Synthesis Installation Guide 2003c Update 2 3 March 2004 Functional Lists of User Attributes Attributes Functional Lists of User Attributes Table 2 2 Module Attributes async_reg Xilinx Allows you to specify an asynchronous registration flow This attribute is used in Xilinx to flag flip flops as clock dom
324. ry defaults route tables loading temperature voltage Precision loads the library that you specified with the setup_design technology command Precision uses the following search order to locate compiled technology libraries 1 Current working directory 2 MGC_HOME pkgs precision techlib syn The libraries that appear in the user interface are specified in the devices ini file Precision loads the cell library into the in memory database The library name in the database is typically the same as the syn file Currently the initial release of Precision only allows you to load a single technology library Analyzing the Design After the technology library is loaded Precision analyzes all of the files in the input file list The files in this list can be a combination of VHDL EDIF verilog or xdb files During design analysis Precision performs the following tasks 1 Parses the HDL syntax check 2 Locate referenced libraries and cells If you design files reference a standard library or package such as an IEEE library then Precision Synthesis will automatically load open and load that library or package file which is located in the directory MGC_HOME pkgs precision data When Precision encounters a cell instantiation it uses the following process to determine the proper reference library a Work library in current Precision memory b Technology in current Precision memory 3 Checks Dependencies In this step Precision deter
325. s Pipeline stages Area Delay through C cells R cells multiplier None Combinatorial 68 22 17 ns Single stage 247 12 81 ns 879 314 12 48 ns Quality of Results and Runtime Improvements for Actel Technologies Precision RTL Synthesis Quality of Results for the Actel ProASICPLUS and Axcelerator families have been improved with the addition of support for module generators modgens for these technologies The current modgen support for the ASOOK family has also been enhanced The additional modgen support allows FPGA vendor optimized implementations of certain arithmetic and datapath functions to be used within your design This results in significant improvements in quality of results f area and runtime Constraining for Synthesis and Layout Precision RTL Synthesis fully supports the Synopsys Design Constraint language the de facto standard method for chip designers to communicate their design constraints In addition the Actel Designer software supports a growing subset of this language for constraining its layout algorithms Currently the Actel Designer software supports two SDC constraints create_clock and set_max_delay Together these two constraints can be used to constrain both the period of on chip register to register paths and the time required for signals to propagate on and off chip through I O pad cells Actel s create_clock implementation lets you create real clocks at any point in your desig
326. s in the design short Display only short path names not full path names of design objects Description The list_design command returns a Tcl list of the contents of one or more designs indicated by the lt list_of_designs gt argument The returned Tcl list contains formalized names If the lt list_of_designs gt is relative the list returns relative names If the lt list_of_designs gt 1S absolute the list returns absolute names Although an instance does not contain any objects itself it does point to a view For that reason the list_design command returns the formal name of the view if lt list_of_designs gt itself indicates an instance The command does not operate recursively through a design hierarchy For example executing list_design where lt list_of_designs gt is a library returns only the names of cells in library but not the names of views within the cells Use the report_area command to generate a report Precision Synthesis Installation Guide 2003c Update 3 89 March 2004 list_design More Examples list_design list_design work list_design work hdl DoOLrL work and2 contents list_design list design list design list design list_design list_design list_design list_design list_design DOCA ref net yZ inst x nets n Related Commands all clocks SDC all_inputs SDC all_ outputs SDC 3 90 Commands list all cells in the libr
327. s on the area performance curve Optimization is a process of partitioning the circuit running specific algorithms and testing to see if improvements are made Each of the optimization passes runs a specific set of algorithms starting with the unmapped generic primitives from synthesis design Examples of optimization algorithms include BDD construction A Binary Decision Diagram BDD decomposes the logic into a tree of decision blocks Sometimes Precision Synthesis does not build a BDD for certain types of circuits such as very large multipliers or circuits that are very large A BDD tends to grow in size ina linear manner as the number of inputs increase which makes it an efficient means for representing data unlike truth tables or PLA representations Figure 4 4 A Binary Decision Diagram Truth Table Binary Decision Diagram oO T 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Or O OF O02 0 O ooooo oot O0O00 00 IN Factoring combining like terms to reduce area Circuit Restructuring a more global technique Remapping utilizing wider gates Each pass iterates through a series of algorithms and measures the results The actual operations performed in each pass are not released as this is viewed as a trade secret Precision Synthesis Installation Guide 2003c Update 4 9 March 2004 How Precision Synthesizes the Design How Precision Compiles Designs The following paragraphs provide an
328. s optimized see explanation below Boundary Optimization Given a hierarchical design the inputs to a hierarchical module may contain constants inputs tied high or low By propagating the constants across the boundary into the low level hierarchy the design can be optimized more effectively Similarly unused outputs of a hierarchical module can be disconnected and common nets connecting multiple ports can be merged into single net This propagation occurs in both upward and downward directions By default hierarchical modules are checked for the usages at the boundary Next the modules are grouped based on the common usage for boundary optimization The created views are given the context names based on the higher level cell instance and its view name lt cellname_instancename_viewname gt 4 6 Precision Synthesis Installation Guide 2003c Update1 March 2004 How Precision Compiles Designs How Precision Compiles the Design You may observe that some lower level hierarchical modules have unused output ports or nets that are merged together Constant Propagation Precision continues the optimization preparation process by propagating the effects of TRUE and FALSE nets across the hierarchical boundaries of the generic design to reduce the initial circuit complexity The tool performs this task again during area and performance optimization Figure 4 2 shows a simple example of constant propagation A partial section of the design
329. saastaasenidansatnniensn 8 12 hn CO pease E AEE 9 3 Pire 9 2 AUE ororen mue TEE essesi r NEER 9 4 Poe ki Coran opni nes mn me GU iaa S 9 5 Fiure 9 4 ore cen iles alter CONIDIA OM ierciricscrcigesesornsennnncernarommienserenenemnaanaevent 9 6 Pig 9 3 Coregen Des ailer OE scree cco aiaa edn 9 7 Figure 9 6 Inferring Xilinx Single Port RAM from VHDL ceessseeeeeeeeeeeeeeeeeeeees 9 9 Figure 9 7 Inferring Xilinx Single Port RAM from Verilog ccecnecteeeeeeeeeeeeeeeeees 9 10 Figure 9 8 Using the Precision GUI to Direct the Mapping of Memory cccceeeeee 9 11 Figure 9 9 Inferring Xilinx Dual Port RAM from VHDL sseeeeeeseesssssesssssssesrrereresesssssssssse 9 12 Figure 9 10 Inferring Xilinx Dual Port RAM from Verilog sesssessesssesseeseseerererssesssssssssss 9 13 Figure 9 11 Inferring WRITE_FIRST Mode One Clock Style 1 ee eeeeeeeeeee 9 14 Figure 9 12 Inferring WRITE_FIRST Mode One Clock Style 2 0 eeeeeeeeeeeee 9 15 Figure 9 13 Inferring WRITE_FIRST Mode One Clock Style 3 0 eeeeeeeeeeeeee 9 16 Xi Precision Synthesis Installation Guide 2003c Updatet March 2004 Figure 9 14 Figure 9 15 Figure 9 16 Figure 9 17 Figure 9 18 Figure 9 19 Figure 9 20 Figure 9 21 Figure 9 22 Figure 9 23 Figure 9 24 Figure 9 25 Figure 9 26 Figure 9 27 Figure 9 28 Figure 9 29 Figure 9 30 Figure 9 31 xii Table of Contents List of Figures cont Inferring WRITE_FIRST Mode Two CI0cks
330. scribes a characteristic about the design object The concept of an attribute in an HDL language is the same The attribute is a name value pair that is associated with attached to set on or owned by a design object in the design In VHDL the attribute construct may be used to associated a design object with an attribute value and in Verilog a pragma attribute directive may be used If these attributes are declared in the source files the HDL attributes are converted to attributes in the in memory database and many time are translated as EDIF properties during an EDIF netlisting operation You can attach an attribute to an in memory design object by using the set_attribute command in the interactive command line window Executing the remove_attribute command removes the attribute Sometimes setting a variable also sets the associated attribute 1 2 Precision Synthesis Installation Guide 2003c Updatet March 2004 Introduction The Tcl Command Interface Methods for Using Commands With a Tcl Script After you create a Tcl script you can source your Tcl script from Precision Synthesis as follows The Interactive Command Line Shell The GUI Menu Bar File gt Run Script The Shell Command Line with a Path to Precision Synthesis Note The Precision Synthesis log file is a Tcl script file that you can use after making the necessary edits You can also generate a Tcl command file by right clicking in the Transcrip
331. set of EDIF type libraries which start at the root A library contains a list of cells and a cell contains a list of views In comparison to VHDL a ce11 is equivalent to an ENTITY and a view 1s equivalent to an architecture Just as most VHDL entities have only one architecture most cells have only one view Views are the basic building blocks of your design and are equivalent to a schematic sheet A view can have three types of objects ports nets and instances A view is the implementation or contents of a single level of hierarchy Examples When you read a VHDL description into Precision Synthesis your VHDL entity translates to a cell and the VHDL architecture contents translates to a view By default the cell is stored in an EDIF style library called work by default You can change the name of this library if you wish When you load a technology library into Precision Synthesis it becomes an EDIF type library in the design database which contains all of the cells of that technology Your design in the work library will reference this technology library as an external EDIF library Precision Synthesis creates an EDIF style library of PRIMITIVES automatically This library represents all primitive logic functions that Precision Synthesis may require when compiling or elaborating HDL VHDL and Verilog descriptions Precision Synthesis also automatically creates an OPERATORS library This library contains operator cells
332. set_false_path SDC remove_output_delay set_multicycle_path SDC 3 202 Precision Synthesis Installation Guide 2003c Update March 2004 Commands set_preference set_preference Set a Precision preference indicating whether new projects will be saved to a temp directory Example set_preference pref project usetempdir value true Syntax set_preference pref lt string gt value lt string gt Options pref lt string gt The pref option specifies the preference to set The project usetempdir preference is used to indicate whether new projects will use a temp directory for active implementations value lt string gt The value option specifies the preference value For the project usetempdir valid options are true or false By default the tool sets this preference to true and projects will automatically use a temp directory You can override this setting by entering the command with a value false string Description The set_preference command with the project usetempdir preference indicates whether the project is saved to a temp directory for active implementations When a new project is created the preference is stored in the project file as a project property By default new projects use a temp directory You may override this setting by entering a value false setting If default projects are created by running a script without using the open_project or new_pr
333. sign 4 3 How Precision Synthesizes the Design 4 8 Design Data Model 1 6 design Switch 2 8 Devices Supported Actel 6 19 dofile 3 49 dont_retime 2 2 2 4 2 13 dont_touch 2 2 2 4 2 13 DRC Resolving 4 11 drive 2 14 E edit 3 50 Effort Level 6 5 Empty cells 4 4 exec_interactive 3 51 exit 3 52 export_settings 3 53 Extended Layout Runtime Mode 6 5 extract_mac 2 2 2 14 F Files File Extensions 5 2 Files in the Project Directory 5 1 Files Reference 5 1 Precision Synthesis Installation Guide 2003c Update1 March 2004 Hierarchical Project File Structure 5 4 Precision Specific Files 5 3 Understanding the Files in a Working Directory 5 1 find 3 54 find_clocks 3 57 find_inputs 3 59 find_outputs 3 60 Finite State Machines 4 6 G Generating Hierarchy 4 3 get_cells SDC 3 61 get_clocks SDC 3 63 get_clocks_domains 3 62 get_designs 3 64 get_false_paths 3 65 get_impl_property 3 66 get_lib_cells SDC 3 67 get_lib_pins SDC 3 68 get_libs SDC 3 69 get_multicycle_paths 3 71 get_nets 3 72 get_path_definition_set 3 74 get_pins 3 76 get_ports 3 78 get_project_impls 3 80 get_project_name 3 81 get_results_dir 3 82 get_selected 3 83 get_version 3 84 Graphical User Interface 1 1 group 3 85 H Help 1 4 help 3 87 Hierarchical Project File Structure 5 4 Hierarchy 2 2 2 4 Manipulate 4 10 Index 2 Index Index cont I Implement operators 4
334. simulation when writing to an indexed array with an index that is larger than the scope of the array Consider a 16 bit databus where you selectively write to each bit based on an index value If the index were to be larger than the scope of the databus say a 6 bit value then when simulating attempting to write to 111111 would not actually change the value However Verilog allows us to wrap around and basically discard the top two bits A fault tolerant netlist explicitly decodes every index input and does not permit wrap around for bad coding Example module fault _tolerant clk data index result input clk data input oso andex j output 15 0 result reg data_ff reg 15 0 result always posedge clk begin result index data_ff data_ff data end endmodule frequency lt freq_mhz gt Specifies the global design frequency in MHz This is normally set when the user enters a global frequency from the Setup Design dialog box impl lt implementation_name gt Deprecated option use set_impl_property name instead Tells Precision to rename the current implementation to the specified name If the following conditions are true then impl will create a default project and create a default implementation of the specified name o setup_design is the first command in a script Precision Synthesis Installation Guide 2003c Update 3 213 March 2004 setup design Commands o No project is open o The r
335. sing Altera s clearbox timing generator This will have a noticeable affect on runtime but it provides more accurate timing reports This attribute can be applied to the top of the design or to individual hierarchical blocks Verilog pragma attribute fir _filter synthesis _clearbox true VHDL attribute synthesis_clearbox string attribute synthesis_clearbox of fir_filter label is true Interactive Command Line Shell set_attribute name synthesis _clearbox value true type _encoding_style Specifies the style of encoding for a Finite State Machine Refer to the State Machine Synthesis chapter in the Precision Synthesis RTL Style Guide for more information including how to specify the style of encoding for a Finite State Machine in Verilog VHDL type encoding_style is BINARY ONEHOT TWOHOT GRAY RANDOM attribute TYPE_ENCODING_STYLE encoding_style Declare your state machine enumeration type type my_state_type is s0 sl s2 s3 s4 Set the type_encoding_style of the state type attribute TYPE_ENCODING_STYLE of my_state_type is ONEHOT triff Tells Precision Synthesis whether or not to map the candidate register in the path to a register in the IOB By default Precision maps the register to the IOB if this attribute is not present The attribute is applied to the inout port Verilog pragma attribute data_inout 1 triff false Precision Synthesis Installation Guide 2003c Updat
336. sing power You can exercise further control over the process when you set constraints and attributes on design objects For example you can set an input delay constraint on an input port to specify how much of the clock cycle 1s consumed outside the chip before the signal arrives In another example you can specify a dont_touch attribute on a block possibly an IP block to prevent the block from being optimized during synthesis You will set most constraints and attributes by right clicking on objects in the GUI and selecting a menu item In this case you select Don t Touch from the menu Standard Tcl Commands Precision Synthesis accepts all standard commands of the Tcl language Tcl supports commands that include variable assignment handling of lists and arrays sorting string manipulation arithmetic operations if case foreach while statements and procedures Precision Synthesis Tcl Commands Mentor Graphics has added a number of command extensions to the Tcl language to handle and support the synthesis process These commands are built in and are executed the same as the standard Tcl commands Setting Attributes An attribute is information that is attached to owned by an object in the Precision Synthesis in memory design database The ability to set attributes gives you a mechanism to control and fine tune the synthesis process An attribute has a name a type a value and an owner An attribute s value typically de
337. sion Compiles Designs Results of Retiming Figure 4 5 shows a circuit as it might be implemented after normal optimization Figure 4 5 Simple Circuit before Retiming Slack 0 44 ns The combinatorial logic between the 2 register banks was coded in such a manner that two serial LUTs were required to implement the logic The critical path for this circuit goes through these 2 LUTs As implemented this design does not meet timing Contrast this with the circuit shown in Figure 4 6 Note that the two registers at the input have been merged into one register The LUT2 has been moved behind the merged register Retiming this circuit has resulted in one less LUT on the critical path which causes the design to meet timing Figure 4 6 Simple Circuit after Retiming Slack 0 55 ns 4 14 Precision Synthesis Installation Guide 2003c Update March 2004 How Precision Compiles Designs How Precision Synthesizes the Design Register retiming will change the function of a local register It can add new registers and merge existing registers In all of these cases circuit debugging can become more difficult To aid you in the debugging process all register moves are reported in the Transcript window and in the Log file Retiming is performed iteratively Circuit constraints are initially loosened to focus the first iteration on the most critical paths Once this 1s complete constraints are slightly tightened In this manner it is possible to
338. sion propagates clocks In designs with logic or flip flops between the top level port and instance clock pins it is important to understand how Precision propagates clocks to all register Precision only propagates clocks through UNATE gates Unate gates are gates where a given transition on an input pin causes a fixed transition on the output pin For example an AND gate is positive UNATE A rise transition on the input can cause no change or a rise on the output A NOR gate is negative UNATE A fall transition on an input can cause no change or a rise on the output An XOR gate a MUX or a LATCH are examples of non unate gates On these gates a rise on the input can cause arise or a fall on the output depending on the states of the other pins After compiling design Precision propagates clocks from the clock pins on all registers until it encounters a top level port or non unate gate 4 10 Precision Synthesis Installation Guide 2003c Update March 2004 How Precision Compiles Designs How Precision Synthesizes the Design In cases where a clock is gated with a non unate gate the user set a clock constraint on the output pin of the non unate gate in order to constrain the flops driven by this clock DRC Resolving Precision performs the following Design Rule Checks after optimization All three of these checks are attempting to create an easily routable design by minimizing fanout while avoid large loads in the critical path Fano
339. sion provides you complete control over the naming and location of output files This is accomplished through the setup_design and set_working_dir commands To specify the location and name of an output file use the following commands gt set_working_dir c designs uart gt Setup_design impl uart_imp_1 gt Setup_design basename my_design This will place the output EDIF file into c designs uart uart_imp_1 my_design edf Note Precision uses TCL for a scripting language TCL requires the use of forward slashes to specify directory structures even on Windows OS Precision Initialization File 1 Use a common text editor to create a file named precision tcl Or precision tcl 2 Enter a ed command in the file and specify the lt pathname gt to your working directory For example cd F my_designs 3 If you are a Unix user you should place the precision tcl or precision tcl file in your HOME directory If you are a Windows user you should place the file in your 5 4 Precision Synthesis Installation Guide 2003c Updatet March 2004 Files Reference Precision Initialization File personal Profiles directory A typical pathname might be Profiles lt username gt precision tcl NOTE On some Windows platforms the environment variable USERPROFILE is not automatically set You can set this variable in the autoexec bat file to point to your user profile or you can place the precision tcl file on the C drive Cc pr
340. sis directive reg 7 0 dataout pragma attribute dataout radhardmethod tmr_cc Setting the attribute on an instantiated module through a Verilog synthesis directive pragma attribute U2 radhardmethod tmr Example VHDL Code Setting the attribute on a registered signal through a VHDL attribute attribute radhardmethod string attribute radhardmethod of dataout signal is tmr_cc Setting the attribute on an instantiated module through a VHDL attribute attribute radhardmethod string attribute radhardmethod of U2 label is tmr You can also set the radhardmethod attribute on an object block or instance using the GUI 1 Select the design object in the Precision GUI schematic design browser 2 Display the Set Attribute dialog box by right clicking on the design object and selecting Set Attributes 3 Under User Attributes select New 4 Enter radhardmethod as the attribute name and set its value appropriately Targeting Pipeline Multipliers Precision RTL Synthesis provides proven operator implementations that can take advantage of the programmable logic fabric The tool supports a wide range of operators providing area efficient implementations for counters adders pipelined and combinatorial multipliers typically found in higher performance applications Pipelined multiplier operator implementations are offered for the ProASIC L and Axcelerator device fa
341. spLSI3256A 0LM160 5OLM160I 70LM160 90LM160 70LQ160 70LQ160I 90LQ160 ispLSI3256E OLM304 100LM304 70LB320 1OOLB320 ispLSI3320 OLQ208 100LQ208 70LM208 100LM208 70LB320 100LB320 ispLSI3448 OLB432 90LB432 7 16 Precision Synthesis Installation Guide 2003c Update1 March 2004 Chapter 8 Designing with Altera Devices Handling Altera Design Issues Mapping Registers to IO Blocks Based on your timing constraints Precision will move registers into the I OBs You can manually control which registers get moved to the IOB using the 10b attribute You can also control the individual flop on bi directional ports using the inff outff and triff attributes After you synthesize the design Precision reports which register ports are mapped into the IOB using the report_io_registers command Assigning an Altera LogicLock Region to a Block Altera Quartus II software supports a LogicLock block based design flow that enables you to assign blocks of logic to regions on a device As shown in Figure 8 1 below the Precision GUI allows you to assign a LogicLock region to a block in the compiled design In this example the selected multiplier is assigned to region mult3 which is a region of Auto size in a Floating state Precision Synthesis Installation Guide 2003c Update 8 1 March 2004 Handling Altera Design Issues Designing with Altera Devices Precison attaches a LOGICLOCK attribute to the block which is passed to Quartus II as
342. ssing output delay values If you specify a file pathname argument the report is written to a file in an already existing directory If you only specify a leaf name the file is written to the current working directory 3 144 Precision Synthesis Installation Guide 2003c Update1 March 2004 Commands report_missing_constraints You can execute this command from the GUI by right clicking on the design_top icon in the Design Hierarchy pane of the Design Center window and select Report Missing Constraints A report window is generated containing all the missing constraints If you right click on the missing constraints report and select Save the report is written to a file to the active implementation directory named lt t op_design gt _missing_constraints rep Related Commands report_area report_net report_attributes report_timing report_library Precision Synthesis Installation Guide 2003c Update 3 145 March 2004 report_net Commands report_net Report information on the specified net s Example report_net file F reports missing_clocks rep Syntax report_net lt list_of_nets gt file lt report_file pathname gt summary all nets lt report_file pathname gt lt list_of_nets gt Arguments lt list_of_nets gt Specifies one or more nets on which to report Options file report_file_pathname Pathname of the file for which to write the nets report If you specify a leaf name th
343. supported 1 2 3 8 14 Precision Synthesis Installation Guide 2003c Update1 March 2004 Designing with Altera Devices Altera Devices Supported Mercury Devices Supported Mercury Devices EP1M350F780C Mercury Speed Grades Default Speed Grade 5 Speed Grades supported 5 6 7A 8A APEX II Devices Supported EP2A70 B724C F1508C APEX IT Speed Grades Default Speed Grade 7 Speed Grades supported 7 8 9 Precision Synthesis Installation Guide 2003c Update 8 15 March 2004 Altera Devices Supported Designing with Altera Devices APEX 20KC Devices Supported EP20K1000 B652C CF672C CF33C CF33I APEX 20KC Speed Grades Default Speed Grade 7 Speed Grades supported 7 8 9 APEX 20KE Devices Supported APEX 20KE Devices Supported C144 QC208 FC144 FI144 FC324 C144 QC208 QI208 QC240 FC144 FC324 BC356 C144 QC208 QC240 FC144 FI144 FC324 FI324 BC356 C144 QC208 QC240 FC484 FI484 BC356 EP20K200E QC208 QC240 QI240 BC356 FC484 FI484 BC652 FC672 EP20K300E QC240 BC652 FC672 FI672 EP20K400E BC652 B1652 FC672 FI672 EP20K600E BC652 B1652 FC672 FI672 FC33 EP20KI1000E BC652 FC672 FC33 EP20KI500E BC652 FC33 EP20K30E EP20K60E EP20K 100E EP20K160E APEX 20KE Speed Grades Default Speed Grade 1 Speed Grades supported 3 2 1 1X 2X 8 16 Precision Synthesis Installation Guide 2003c Update March 2004 Designing with Altera Devices Altera Devices Supported APEX 20K Devices Supported AP
344. t name lt path_definition_set_name gt lt path_definition_set_name gt Arguments name lt path_definition_set_name gt Name of the path definition set Description This command deletes one Path Definition set or all sets If no name is specified all Path Definition sets will be deleted Related Commands create_path_definition_set get_path_definition_set 3 48 Precision Synthesis Installation Guide 2003c Update March 2004 Commands dofile dofile Execute a Tcl script and print a message as each command in the script is executed Example dofile runl tcl Syntax dofile lt file_pathname gt lt file_pathname gt Arguments lt file_pathname gt The pathname of a Tcl file to be executed If only the leaf name of the file is specified then Precision Synthesis looks in the current working directory for the file Description The dofile command is an extension of the Tcl source command In addition to executing a Tcl file the dofile command sends a message to the standard output device as each command executes This is very helpful when debugging a Tcl script Related Commands Precision Synthesis Installation Guide 2003c Update 3 49 March 2004 edit Commands edit Invoke the Precision Synthesis text editor on the specified file Example edit top vhd Syntax edit lt file pathname gt integer lt line number gt Arguments e lt file_pathname gt The pathname of a text file
345. t window and selecting Save Command File Interactive Command Line Shell Type the following syntax to source your Tcl script source lt my_tcl_script gt or type the following command to execute your Tcl script dofile lt my_tcl_script gt The dofile command is similar to the source command in that it executes the Tcl commands that are specified in the file In addition dofile sends a message to the standard output device each time a Tcl command is executed This is an excellent tool that you can use to help debug the Tcl script GUI Menu Bar File gt Run Script On the menu bar click on File gt Run Script Type in your Tcl script name or click on the button and choose a Tcl script file Your script file runs in the GUI Information window Command Line with Path to Precision Synthesis Bring up your PC or UNIX window Type the appropriate argument to source your Tcl script For Precision RTL Synthesis lt precision install directory gt bin precision shell file lt my_tcl_script gt For Precision Physical Synthesis lt precision install directory gt bin precision shell physical file lt script gt Precision Synthesis Installation Guide 2003c Update 1 3 March 2004 The Tcl Command Interface Introduction Command Line Description Command and Option Abbreviation Precision Synthesis allows abbreviated Tcl commands you only need to spell out a command until the command meaning is unambiguous For example the co
346. t distributed rams for port A and C For Virtex II Precision by default infers a set of dual port block rams for port A and B and another set of dual port block rams for port A and C when both port B and port C are read synchronously with the same clock Precision sets the property WRITE_MODE_A to 9 28 Precision Synthesis Installation Guide 2003c Update1 March 2004 Designing with Xilinx Handling Xilinx Design Issues READ_FIRST on these dual port block rams the clock associated with port B and C can be the same as or different from the clock associated with port A the synchronous reading of port B or C can also be described by explicitly clocking the read address When the block_ram attribute is set to false on the RAM distributed RAM s are inferred instead Port A Synchronously Written and Read in READ_FIRST Mode In Figure 9 26 the write mode for port A is READ_FIRST Precision sets the property WRITE _MODE_A to READ_FIRST on these dual port block rams For Virtex Precision infers a set of dual port distributed rams for port A and B and a set of dual port distributed rams for port A and C Figure 9 26 Tri Port RAM Port A Sync Read Write READ_FIRST Mode timescale 100 ps 10 ps module swsr sr sr iwelk wen addril addr2 addrs outi out2 outs datain input wceclk Write clock input wen Write enable adder Ls addr2 addr3 input input input Cul OLS datain output CUT pDuL input
347. t of registers on which the tool will perform optimizations Precision Synthesis Installation Guide 2003c Update 3 99 March 2004 physical_ synthesis Commands Description The physical_synthesis command performs automated Precision Physical design flow to improve timing This command can only be run after place and route has been performed and the resulting placement loaded into Precision Physical If this command is issued with no options the entire design will be affected Optimization will stop when the most critical timing path can no longer be improved Various optimization algorithms including register retiming register replication and placement optimization are applied to the design as needed to achieve optimal timing You must have a valid Precision Physical Synthesis license to run this command Related Commands compile save_physical 3 100 Precision Synthesis Installation Guide 2003c Update March 2004 Commands place_and_route place_and_route Run the integrated place and route tools Example place_and_route cl Run the vendor place and route flow in the background command line mode Syntax place_and_route lt command_name gt lt arguments gt lt command_name gt lt arguments gt Description The place_and_route command is primarily used by the Precision Synthesis GUI to launch Vendor implementation tools The Vendor technology and part number must be specified with the setup_design comma
348. t on a primary input pin or on the data output pin of a register and end at a primary output pin at the clock or data input pin of a register Precision Synthesis Installation Guide 2003c Update 3 175 March 2004 set_false_path SDC Commands Care must be taken when specifying hierarchical pins as the from or to points of a slack path because they might not always be valid start or endpoints For example consider the circuit shown in Figure 3 2 INST1 INST2 Figure 3 2 Hierarchical Pins The hierarchical port INST1 W is not the start of any slack path since it is driven by INST 1 buf1 Therefore the command set_false_path from INST1 W does not block any slack paths The command set_false_ path through INST1 W 3 176 Precision Synthesis Installation Guide 2003c Update March 2004 Commands set_false_path SDC OLr set_false_path from all_registers INST1 does block both delay and slack paths Related Commands set_input_delay SDC set_multicycle_path SDC set_output_delay SDC report_missing_constraints report_attributes Precision Synthesis Installation Guide 2003c Update 3 177 March 2004 set_fanout_load SDC Commands set fanout load SDC Limit the capacitance in library units that a net or port can drive Example set_fanout_load 0 5 alu timing mult_en set_fanout_load 10 0 reset Syntax set_fanout_load lt fanout_value gt lt port_net gt Arguments
349. t_connections port clk Returns the name of the net to which the port clk is connected Syntax report_connections lt list_of_objects gt port net instance direction lt net_direction gt hierarchical lt list_of_objects gt Arguments lt list_of_objects gt Names of the objects for which the report_connections command lists network connections Object names are case sensitive and wildcards are accepted Options port net instance Indicator that the object name refers to ports nets or instances If you omit this argument the report_connections command assumes that the objects in list_of_objects are nets direction lt net_direction gt This is for nets only direction DRIVER DRIVEN hierarchical List all objects connected hierarchically to the ones in lt list_of_objects gt The report_connections command lists objects at each level of hierarchy below the objects in report_connection If you omit this argument only the connections to objects in one view are listed Precision Synthesis Installation Guide 2003c Update 3 133 March 2004 report_connections Commands Description The report_connections command returns a Tcl list of formal names of connections for the indicated objects If the object list denotes a port or port instance the net connected to the port or port instance is returned If the object list denotes a net a list of ports and port instances connected
350. t_memory_utilization command returns a report on the amount of memory that is being utilized by the tool This report might be useful in determining when to add more memory if you are working an a large design Related Commands Precision Synthesis Installation Guide 2003c Update 3 143 March 2004 report_missing_constraints Commands report_missing constraints Report missing constraints on the external ports Example report_missing_constraints F reports missing_clocks rep clock Syntax report_missing_ constraints lt report_file_pathname gt clock input_delay output_delay lt report_file pathname gt Arguments lt report_file_pathname gt Pathname of the file for which to write the missing constraints If you only specify a leaf name the file is saved to the current working directory The rep extension is not required but it identifies the file as a report file If you omit this argument the report is written to the Transcript window Options clock Report missing constraints on clock ports only input delay Report missing input delay constraints on input or inout ports only output_delay Report missing output delay constraints on output or inout ports only Description The report_missing_constraints command generates a report file on missing external port constants By using the option switches you can limit the report to just missing clocks missing input delay values and mi
351. t_project_impls 3 66 Precision Synthesis Installation Guide 2003c Update March 2004 Commands get_lib_cells SDC get_lib_ cells SDC Return a list of cells in a loaded library Example get_lib cells work get_lib_cells OPERATORS Syntax get_lib cells lt lib_list gt lt cell_list gt lt lin ligt lt cell lict Description The get_lib_cells command returns a list of cells in a previously loaded library You must include both the library and cell name with the hierarchical separator You can also use wildcards and all object names are case sensitive The wildcard string is terminated by the hierarchical separator For example get_lib_cells t returns the cells inside any loaded library beginning with t If you omit the search pattern Precision Synthesis returns an error Related Commands get_cells SDC get_lib_pins SDC get_clocks SDC get_multicycle_paths get_designs get_nets SDC get_false_paths get_path_definition_set get_lib_cells SDC get_ports SDC get_lib_cells SDC Precision Synthesis Installation Guide 2003c Update 1 3 67 March 2004 get_lib_pins SDC Commands get_lib_ pins SDC Return a list of library pins on cells in a previously loaded library Example get_lib_ pins xcve CLK Syntax get_lib cells lt lib_list gt lt cell_list gt lt lib ist S lt Cell laste lt port pin list gt Description The get_lib_pins command returns a list of pins
352. tain the string arbit Syntax find lt object gt object to search for start lt starting_point gt hierarchy show_scope all library cell view inst net matchcase wholeword regexp string lt starting_point gt Arguments lt object gt Name of a design object in the in memory data base 3 54 Precision Synthesis Installation Guide 2003c Update1 March 2004 Commands find Options start lt string gt Name of the starting point for the search This can be the name of a library cell view or instance If this argument is not set the current design is used hierarchy For hierarchical designs this switch tells Precision Synthesis to search the defining view of each instance as well as the instance itself The default 1s FALSE all Match all objects This 1s the default TRUE If any other match criteria 1s set this is turned off library Matches libraries cell Matches cells view Matches views inst Matches instances An instance will match if one of three things is true 1 if the instance name matches 2 if the defining view s name matches or 3 if the defining view s owner cell s name matches This allows you to search for DFF and find all instances who s cells are DFF Or in another case you can search for and find all instances with a defining view SmallAndFast
353. tances If you omit this argument the ungroup command generates names automatically The format for new instance and net names is as follows lt ungrouped instance name gt ungroup lt original name gt The default for the variable ungroup is the underscore _ character 3 230 Precision Synthesis Installation Guide 2003c Update March 2004 Commands ungroup For example suppose a view TOP contains an instance called x x points to a view v Suppose also that v contains a net N and an instance 1 If you execute the command ungroup x when the current design is TOP the instance x will be removed and the contents in the view that x is pointing to v will be copied to Top and get new names Netw in v will be copied to a net called X_N in TOP Instance 1 in v will be copied to instance x_I in TOP all Decompose every instance in the current level of hierarchy of the current design The a11 option is equivalent to using the character for instance_list and may be used in place of specifying instance_list except lt exclude_instance_list gt Exclude the named instances in instance_list from the ungroup operation force Flatten out cells even noopt or technology cells Description Remove one or more levels of hierarchy from a design by decomposing the instances named in instance list More Examples ungroup x y except x hierarchy In this example the ungroup command ungroups all hierarchy un
354. tax find clocks top internal derived Options top Find only the clocks at the top level of the current design internal Find all of the internal clocks derived Find all of the derived clocks Description The find_clocks command is a reporting command that allows you easily locate the source of all clocks in the design To find top level clocks Precision Synthesis traces each top level port through hierarchy until it reaches either a non unate gate or a sequential cell If this path ends at a clock pin then Precision Synthesis considers the top level port a clock To find internal derived clocks Precision Synthesis traces from each clock pin in the design up through hierarchy until it reaches a non unate gate top level port or blackbox If this path does not terminate at a top level port then Precision Synthesis returns the termination point of the path as the source of an internal clock Precision Synthesis Installation Guide 2003c Update 3 57 March 2004 find_clocks Related Commands create_clock SDC remove_clock all_ clocks SDC report_area get_clocks SDC Commands 3 58 Precision Synthesis Installation Guide 2003c Update March 2004 Commands find_inputs find_inputs Find all of the inputs in the current design Example find inputs clock clkA GLKB Syntax find_inputs clock lt clock_names gt lt clock names gt Options clock lt clock_names gt
355. te net data_sum name preserve_z value true radhardmethod Actel Creates a radiation hardened implementation You can set a radhardmethod attribute either on the reg signal being driven by the flop the flop instantiation itself or on an entire module instantiation If you set this attribute in your HDL code apply it to the signal If you set this attribute in Precision set it on the flop Each design object is able to inherit radhardmethod attributes from it s parent In addition a radiation hardened implementation can be set for the entire design by issuing the command setup_design radhardmethod one of ce tmr tmr_cc or none Precision RTL Synthesis offers the highest possible level of control over radiation hardened implementation by allowing the designer to tailor attributes per design object instance This method provides significantly better control than competing solutions which only allow setting one implementation method for all instantiations of a design object by instrumenting synthesis metacomments in the HDL code Not only does the Precision RTL Synthesis solution remove the dependency on instrumenting HDL code by allowing attributes to be set in TCL scripts the implementation offers far more flexibility in exploring trade offs with highly folded designs VHDL Setting the attribute on a registered signal through a VHDL attribute attribute radhardmethod string attribute rad
356. te1 7 1 March 2004 The Lattice isoLEVER Environment Designing with Lattice Devices Setting isoLEVER Options As shown in Figure 7 2 you can change pre set options from the Tools gt Set Options pull down menu The option settings are explained in the paragraphs that follow Figure 7 2 Setting Lattice isoLEVER Options Input Optimization F Analysis Output Click to bring up th 2 ere G Lattice website attice fe Integrated Place and Route Launch ispLEVER Path to ispTOOLS installation tree FOUNDRY z Launch ispExplorer F Session Settings a Schemakic Viewer Optimize placement for C Speed Area FMax amp Default Back annotation netlist format C Verilog EDIF f WHOL f None Max Pterm Split Donot run commands Max Pterm Collapse Max Fterm Limit Max Fanin Max Symbols Fmas Logic Level Cancel Apply Help Lattice Logo If your web browser is active click on this logo to bring up the Lattice website home page http www latticesemi com Path to the isp TOOLS installation tree Specify the pathname to the ispTOOLS installation tree for example C apps ispTOOLS 1 2 Precision Synthesis Installation Guide 2003c Updatet March 2004 Designing with Lattice Devices The Lattice isoLEVER Environment Do not run commands This switch is primarily used for debugging the Precision script that drives the ispLEVER tools The commands in the script are echoed
357. ted Precision automatically sets the results directory to the location of the temporary output directory in the project directory Deleting the active implementation unsets the results directory You cannot change the results directory when a project is open Related Commands activate_impl open_project close_project set_results_dir close_results_ dir 3 82 Precision Synthesis Installation Guide 2003c Update March 2004 Commands get_selected get_selected Return a list of objects that are currently selected Example get_selected Syntax get_selected lt patterns gt ports pins nets designs instances direction lt port_direction gt long string lt port_direction gt Options ports pins nets designs instances Filter the list to include only the specified object type direction For pins and port list only Specify IN OUT or INOUT long Return the full pathname of each selected object The default is false Description The get_selected command returns a list of objects that are currently selected The objects could have been selected by using the select command or selected by the user from the GUI Related Commands get_cells SDC get_lib_pins SDC get_designs get_multicycle_paths get_false_paths get_nets SDC get_lib_cells SDC get_path_definition_set get_lib_cells SDC get_ports SDC get_lib_cells SDC select Precision Synthesis Installati
358. terfaces Precision offers a seamless flow for including these optimized blocks in Quartus II integrated place and route The MegaWizard creates a black box or component declaration file an instantiation template and implementation files for place and route Typically you will incorporate the VHDL component declaration file into the parent entity declaration or add the Verilog black box file to the input file list The instantiation template can be pasted into the parent module declaration where its port connections can then be edited to describe proper connectivity Of the remaining files created by the MegaWizard the implementation file s are the only files required downstream for place and route To direct Precision to make these files available for place and route you can add them to the input file list then activate the file properties dialog for those files and specify that they be excluded from the compile phase Precision will then place a copy of the file alongside the top level EDIF netlist for use by the place and route tool The following example is for a FIFO called fifo that was created in Verilog The MegaWizard outputs the following files fifo_bb v The Verilog black box module pinout declaration fifo_inst v An example module instantiation fifo bsf Block Symbol File for Quartus IT 8 10 Precision Synthesis Installation Guide 2003c Update March 2004 Designing with Altera Devices Altera Quartus II I
359. tes Table 2 3 I O Port Attributes inff Tells Precision Synthesis whether or not to map the first register in the input path to a register in the IOB By default Precision maps the first register to the IOB if this attribute is not present The attribute is applied to the input port input_delay Obsolete This attribute is no longer supported An input delay is now specified as a timing constraint 1ob Specifies that the placement of the register is to be forced into the IO block This may increase the IO frequency at the possible expense of the internal chip frequency For bi directional ports you can individually control the movement of flops using the inff outff and triff attributes iostandard Specifies the IO standard to be used outff Tells Precision Synthesis whether or not to map the candidate register in the output path to a register in the IOB By default Precision maps the register to the IOB 1f this attribute is not present The attribute is applied to the output port output_delay Obsolete This attribute is no longer supported An output delay is now specified as a timing constraint Specifies which technology specific I O cell to used for a specific port Assigns a specific device pin number to a specific port in pin_number the design Prevents tri states from being mapped to MUX logic triff Tells Precision Synthesis whether or not to map the candidate register in the path to a re
360. th rise fall setup hold from lt from_list gt through lt through_list gt to lt to_list gt reset_path design rtl gatelevel lt r rom last lt Chro ugh list gt lt to list gt Options rise fall The rise option marks the rising delays false as measured on the path endpoint The fall option marks falling delays false as measured on the path endpoint If you don t specify either rise or fall rise and fall timing are marked false setup hold The setup option marks setup maximum paths false for setup slack analysis The setup option disables setup checking for specified paths The hold option marks hold minimum paths false The hold option disables hold checking for specified paths If you don t specify either setup or hold setup and hold timing are marked false Currently Precision Synthesis does not support hold time analysis from lt from_list gt If set specifies the points where the disabled paths must start If you don t specify a from_list all paths to end points in to_list are disabled From points can include clocks pins or ports When a port or portinst is used in a to or from specification this refers to paths which originate at or terminate at the port or portinst When a clock name is used it refers to paths which are clocked by the clock rather than paths which originate or terminate at the clock pin Precision Synthesis Installation Guide
361. th SDC set_input_delay SDC set_max_delay SDC set_output_delay SDC 3 194 Precision Synthesis Installation Guide 2003c Update March 2004 Commands set_multicycle_path SDC set_multicycle_path SDC Modify the single cycle timing relationship of a constrained path Example set_multicycle_path 3 from reg_alu to reg_mult Syntax set_multicycle path lt path_mutiplier gt rise fall setup hold start end from lt from_list gt to lt to_list gt through lt through_list gt reset_path design rtl gatelevel lt path_multiplier gt lt rom list gt lt ta list gt lt chrough list gt Arguments lt path_muliplier gt Specifies the number of cycles that the data path must have for setup or hold relative to the startpoint or endpoint clock before data is required at the endpoint If you use setup this value is applied to setup path calculations If you use hold this value 1s applied to hold path calculations If you don t specify setup or hold path_multiplier 1s used for setup and 0 1s used for hold Note that changing the multiplier for setup affects the hold check as well Options rise fall Indicates that rising path delays are affected by path_multiplier The default is that both rising and falling delays are affected Rise refers to a rising value at the path endpoint Indicates that falling path delays are affected by path_multiplier The default is that
362. that a cd command in the script will set the working directory before that synthesis run is executed In this case the first command in the script is probably ed Fijmy Project precision exe force file Csy projects precis10n do tel 3 112 Precision Synthesis Installation Guide 2003c Update1 March 2004 Commands precision The command line above clears and initializes the Precision RTL Synthesis product to its default settings invokes the GUI and sources the Tcl file precision_do tcl C gt precision Shell physical The command above invokes Precision Physical Synthesis in the non GUI mode if the proper license features are installed Related Commands exit Precision Synthesis Installation Guide 2003c Update 3 113 March 2004 remove_attribute Commands remove attribute Remove an attribute from the specified object s Example remove_attribute design gatelevel net net_internal name max_fanout Remove the attribute max_fanout from the net net_internal of the gatelevel design Syntax remove_attribute lt object_name gt port net instance global type lt attribute_type gt name lt attribute _name gt design rtl gatelevel string lt object_name gt lt attribute_name gt lt attribute_type gt Arguments lt object_name gt Name of the object library cell view port net or instance for which the set_attribute command sets an attribute
363. the Lattice ispLEVER environment is integrated into the Precision RTL Synthesis environment After Synthesis the technology mapped design is written to the current implementation directory as an EDIF netlist file To run the automated Place and Route flow just click the Place amp Route icon in the ispLEVER Tool Bar ispLEVER uses the current implementation directory as the project directory After the design is compiled you may invoke the ispLEVER GUI manually and open the project From that point you can view reports run analysis tools and manually drive the physical implementation to completion Figure 7 1 Running the Lattice ispLEVER Environment tt simplemath Mentor Graphics Precision Physical Synthesis Design Center Pa File View Tools Window Help Onsale e le al A z U Lattice iip PGA LF 1200B 05FE680C Frequency 100 MHZ Project Files Design Hierarchy Project simplemath 1 0 simplemath_top main_ RTL aE 1 EA R EE Clocks Click to automatically Fl C Ports Place and Route i H E Nets GE simplemath sde H E Instances lermath top constra Click to launch the ispLEVER Software L iles Lad Log File Infos 10 Click to launch the 2chematic ispExplorer chnology Schematic Area Report Rei Timing Report Rei Timing Violation Report Constraints Report Ei simplemath_top edf Ea Transcript P Design Center Precision Synthesis Installation Guide 2003c Upda
364. the RTL version of the current design All is the default add Add the items to the selection list db Brings up a Design Browser hierarchy view of the selected objects hds Brings up an HDL Designer Series view of the selected objects edit Bring up an edit window on the associated file s Precision Synthesis Installation Guide 2003c Update 1 3 163 March 2004 select Commands clear Unselects all selected objects Description This Tcl scripting command can be run in one of two ways The first way allows you to select a list of objects in the current in memory data base The second allows you to select objects associated with a file and list of line numbers The select command by default does not start any windows So unless you have already started a client you must use the appropriate switch to bring the window up Related Commands view_schematic 3 164 Precision Synthesis Installation Guide 2003c Update March 2004 Commands set_attribute set attribute Create or set an attribute on the specified object s Example set_attribute design rtl net net_internal name max_fanout value 10 Set the attribute max_fanout to 10 for the net net_internal of the rt1 design Syntax set_attribute lt object_name gt port net instance global name lt attribute name gt type lt attribute_type gt value lt attribute value gt design rtl gatelevel strin
365. the active implementation directory The Xilinx PAR tools will pick it up as the Leverage NCD file bits Generates a Xilinx bit file that programs the target Xilinx device To specify true use the syntax bits 1 The default is 0 bitgen_cmd_file lt inputfile gt Specifies a command file that will be executed by BitGen This command file can be included in the Input File List Precision will mark the file as exclude and pass it through to the active implementation directory Precision Synthesis Installation Guide 2003c Update 1 3 109 March 2004 place_and_route Commands More Examples place_and_route view_placement Launch the Vendor Floor Planner on the routed design for user viewing place_and_route cl bits false Launch the Xilinx ISE tools on the current design but don t generate a BitGen file Related Commands setup_place_and_route setup_design 3 110 Precision Synthesis Installation Guide 2003c Update March 2004 Commands precision precision A Shell level command that invokes Precision RTL Synthesis as well as Precision Physical Synthesis Syntax precision shell rtl physical physical sa file lt file pathname gt logfile lt file _pathname gt regclear reginit force help string lt file_pathname gt Options Shell Causes Precision Synthesis to be invoked in a non GUI command line mode You can use the quit command to ex
366. the existing logfile to the new logfile close Closes the current logfile 3 92 Precision Synthesis Installation Guide 2003c Update March 2004 Commands logfile save_commands Saves the commands from an active logfile to a new file Description The logfile command is normally used by the GUI to configure the logfile name and specify its location Related Commands set_working_dir Deprecated Precision Synthesis Installation Guide 2003c Update 3 93 March 2004 move_input_file Commands move_input_file Move a file either up or down in the input_file_list Example move_input_file from 2 to 6 Syntax move_input_file from lt position_number gt to lt position_number gt integer lt position_number gt Arguments from lt position_number gt Specifies the position number of the file to be moved t0 lt position_number gt Specifies the position number where the file is to be moved Description The move_input_file command is normally used by the Precision Synthesis GUI when the user Selects an input file and graphically drags it up or down in the input_file_list Ifa VHDL file is moved to the bottom of the list then the file is marked as Top You can get the current position number of each file by executing a report_input_file_list command The first position in the list is position 0 The input_file_list may contain files of the following type vhdl verilog edif syn li
367. the write mode for port A are NO_CHANGE sync read for port B and async read for port C Figure 9 27 Tri Port RAM Port A Sync Read Write NO CHANGE Mode module swsr_sr_ar wclk wen addrl addr2 addr3 outl out2 out3 datain input wclk Write clock input wen Write enable input 4 0 addr input 4 0 addr2 input 4 0 addr3 output Lis ouc 1 p urcput 7 out output Outs input datain Te T3 reg 7 0 0 31 A 32 x 8 bit memory array reg 7 0 outi out2 always posedge wclk begin if wen mem addrl lt datain else outl lt mem addrl out2 lt mem addr2 end assign out3 mem addr3 endmodule 9 30 Precision Synthesis Installation Guide 2003c Update1 March 2004 Designing with Xilinx The Xilinx ISE Environment The Xilinx ISE Environment As shown in Figure 9 28 the Xilinx ISE environment is seemlessly integrated into the Precision RTL Synthesis environment After Synthesis the technology mapped design is written to the current implementation directory as an EDIF netlist file and the SDC constraints are written to a Xilinx UCF user constraint file file As shown in Figure 9 28 you may also choose to include a Xilinx UCF user constraint file in the Input File List This filet may include additional constraints such as placement locations Precision marks files like this as Exclude and passes them through to the current implementation directory to be picked up by the
368. then clock lt clock_name gt must be specified If clock is not specified the delay is relative to time zero for combinational designs For sequential designs the delay is considered relative to a new clock with the period determined by considering the sequential cells in the transitive fanout of each port clock_fall Specifies that the delay is relative to the falling edge of the clock The default is the rising edge 3 122 Precision Synthesis Installation Guide 2003c Updatet March 2004 Commands remove_input_delay rise Specifies that lt delay_value gt refers to a rising transition on specified ports in the current design If neither rise nor fa11 is specified rising and falling delays are assumed to be equal fall Specifies that lt delay_value gt refers to a falling transition on specified ports in the current design If neither rise nor fa11 is specified rising and falling delays are assumed to be equal add_delay Specifies whether to add information to the existing input delay specification or to overwrite the value The add_delay option enables you to capture information about multiple paths leading to an input port that are relative to different clocks or clock edges design lt rtl gatelevel gt Tells the tool whether to look for the object in the RTL or the gatelevel view Description The remove_input_delay command is primarily used by the GUI to remove an input delay constraint
369. thesis Installation Guide 2003c Update 9 9 March 2004 Handling Xilinx Design Issues Designing with Xilinx Figure 9 7 is the recommended Verilog style for an inferred synchronous single port RAM A pragma can be used to disable the mapping to block SelectRam Figure 9 7 Inferring Xilinx Single Port RAM from Verilog module sync_ram_singleport clk we addr data_in data_out parameter addr_width parameter data_width input clk input we input addr_width addr input data_width data_in output data_width data_out reg laddr width 1 addri reg data_width 1 mem 32 bl lt lt addr_width pragma attribute mem block_ram true always posedge clk begin if we mem addr data_in addri addr end assign data_out mem addri endmodule Using the Precision GUI to Map RAM to Distributed RAM If you prefer you can use the Precision GUI to direct the mapping of RAM elements to Select Distributed RAM instead of block RAM As shown in Figure 9 8 after the Compile step you can right click on a memory element in the Design Hierarchy pane and select Use Distributed 9 10 Precision Synthesis Installation Guide 2003c Update March 2004 Designing with Xilinx Handling Xilinx Design Issues RAM from the popup window If you then select the Set Attributes em from the same menu you can see that the block_ram attribute has been set to FALSE on the object Figure 9 8 Using the Precision GUI
370. three clocks are defined then the clock names are returned when the all clocks command is executed gt create_clock period 10 waveform 0 5 name sys_clk sys_clk gt create_clock period 10 waveform 0 5 name tx_clk tx clk_dll out gt create_clock period 10 waveform 0 5 gt all clocks short Sys clk Tz Clk te Clk name rx_clk rx reg_clkb out 3 24 Precision Synthesis Installation Guide 2003c Updatet March 2004 Commands all_ clocks SDC Related Commands all inouts create_clock SDC all_registers find_clocks all_inputs SDC all_outputs SDC Precision Synthesis Installation Guide 2003c Update 3 25 March 2004 all_ inouts Commands all inouts Return a list of all inout ports in the current design Example all_inouts work Cop data parth short Syntax all_inouts lt design_name gt short Arguments lt design_name gt Name of the design Options short Print only short names not the full path to objects Description The all_inouts command is a reporting command that returns a list of all bi directional ports of the top level of the design as determined by the current_design command The value of current_instance does not affect the output of this command If you need to determine the names of the bi directional ports of a lower level block you can either use the Design Browser tool and navigate to the block in hierarchy or you can use the get_por
371. tial elements or sequential pins in the current design get_cells SDC Get cells instances from the current design relative to the current instance get_lib_cells SDC Return a list of currently loaded libraries that match the search pattern get_lib_cells SDC Return a list of cells in a loaded library Precision Synthesis Installation Guide 2003c Update 3 11 March 2004 Command Summary Commands Table 3 6 Object Access Commands continued get_lib_pins SDC Return a list of library pins on cells in a previously loaded library find Find the Find the specified objects in the in memory design objects in the in Find the specified objects in the in memory design design a clocks Return hierarchical pathnames for all clocks in the design Find all of the inputs in the current design find_outputs Find all of the outputs in the current design Table 3 7 SDC Commands all_ clocks SDC Return a list of all clocks in the current design all_inputs SDC Return a list of all input ports in the current design The search can be limited to input ports that have constraints relative to a given clock all_ outputs SDC Return a list of all output ports in the current design The search can be limited to input ports that have constraints relative to a given clock create_clock SDC Define a new clock for the current design current_design SDC Set the current design current_instance SDC Set the workin
372. tive to time zero for combinational designs clock_fall Specifies that the delay is relative to the falling edge of the clock named by clock The default is the rising edge level_sensitive Specifies the level sensitive latch or flip flop to be used rise fall Specifies that lt delay_value gt refers to a rising or falling transition on specified ports in the current design If neither rise nor fa11 is specified rising and falling delays are assumed to be equal max min Specifies that delay_value refers to the longest path max or shortest path min offset Modifies the clock edge separation for slack violations in cases where the destination clock is different than the source clock This value on constrains paths from to registers that have the same clock propagated regardless of the setting of the domain switch in the create_clock command Precision considers derived clocks such those that pass through DCMs the same clock Clock division or multiplication at the destination registers do not effect edge separation This switch is an SDC extension to allow better modeling of the Xilinx OFFSET constraint and greatly improve the timing correlation between Precision and Xilinx add_delay Specifies whether to add information to the existing input delay specification or to overwrite the value The add_delay option enables you to capture information about multiple paths leading to an input port that
373. tnrntirisiterei nnn ira EN AE a 6 3 Figure 6 3 Sample VHDL Code for a Pipelined Multiplier eeseeseesesseeeeeeeeeeeees 6 8 Figure 6 4 Design Constraints File for Synthesis with Precision Synthesis 006 6 10 Figure 7 1 Running the Lattice ispLEVER Environment 0c cccccsseesseseeeeeeseeeeceeeeeeees 7 1 Piers 2 Sete Lace PLE VER UPU ONE erpe 7 2 Figure 7 3 Running the Lattice isppLEVER ORCA Environment 0 cccceseeseeeeeeeeeees 7 5 Figure 7 4 Setting ispLEVER ORCA Options esssssssserersssesssssserersssssssserersrssssesseeesrssssssse 7 6 Figure 8 1 Assigning a LogicLock Region to a Block sesesessesssssssssssssssssesererressressssssssssssesse 8 2 Figure 8 2 Specifying the Block Size for Stratix TriMatrix Memory ccccseeeeeeeeeees 8 3 Figure 8 3 Running the Altera MAX PLUS II Environment cc eeeesseseseeeeseeeeeeeeeeeees 8 5 Figure 8 4 Setting MAX PLUS II Options ccssssssseseececceecccccceneeeessssssssssseseeesescees 8 6 Figure 8 5 Running the Altera Quartus IT Environment ccccnnnteeeeeseeeseeeeseeeeeeeees 8 8 Figure 5 0 Setting Quartus I 515 615 seeeeneneeenne ernst enter mettre hte ber arene rr etr rr Unty eMorentrer tuner eran er renter 8 9 Figure 8 7 Excluding the Implementation File from the Compile Phase 006 8 11 Figure 5 8 Successful place and TOULE ai caersccssmesiesirencrsaatcasswnsnenssanadduenensccend
374. to Direct the Mapping of Memory ndom Mentor Graphics Precision RTL Synthesis Design Center joj xi Tools Window Help e x ls ees e lo e z slins VIRAT Eel Atces 1 44 6 Frequency 100 MHZ Project Files Design Hierarchy E E Project pseudorandom E F pseudorandom rtl ce Impl pseudorandom impl c Clocks Input Files H E Ports il pseudorandom yhd H B d e Constraint Files See Instances E EE pseudorandom constra Ea Blocks on 9 Script Files DF 10 fdlatrg_25 Secon Output Files I1 priority encoder 75 5 wid Log File Warnings 2 Ei Iz tram 6 5 RTL Schematic fe Rr Constraints Report m _ Nets 1 Select and By Instances Right Click Memory Prom am dc indock readaddched fe 14 flFsr_ H A I5 divid _ Primitives Set Attributes Don t Touch 2 Select Report Tinim Trace bo Hierarchy Sort by name Copy Query Info to Clipboard Instance mem Ea Transcript P Design Center Input Directory Crsblexamples Sc 4 Inferring Dual Port RAM A dual port RAM such as a FIFO type RAM with a separatly clocked input and ouput is often used to buffer data transfers between two clock domains that are operating at difference frequencies Precision Synthesis Installation Guide 2003c Update 9 11 March 2004 Handling Xilinx Design Issues Designing with Xilinx Mapping Dual Port RAM to Block RAM Figure 9 9 is the recommended VHDL style for an inferred du
375. to the Precision Transcript window without the commands actually being executed by the implementation tools Timing Analysis Speed Collapses all nodes up to the set Product Term limit globally optimized without regard for the path Area Collapses all nodes up to the set Product Term limit without increasing area cost FMax Causes the Logic Optimizer to automatically identify all critical paths between any pair of registers from clock pin of one register to data pin of the other register or the samer egister The Logic Optimizer then attempts to collapse combine the logic nodes along the critical paths reduce the logic level and allow the chip to run at a higher frequency Default If you specify an empty string the default then ispLEVER determines the best optimization for placement Max Pterm Split This option lets you control the Fitter optimization process by setting a maximum limit on the number of Product Terms PT in each equation In other words the Optimizer shapes the equations relative to the set number of PT For example if the value is set to 35 the Optimizer splits equations if it has more than 35 PT This option works the opposite of Collapsing Max Product Term Max Pterm Collapse This option lets you control the Fitter optimization process by setting a maximum limit on the number of Product Terms PT in each equation In other words the Optimizer shapes the equations relative to the set number of
376. to the ispLEVER ORCA installation tree for example C ispTOOLS NO XeC This option is primarily used to debug the Precision place_and_route script that drives the implementation tools The commands in the script are echoed to the Precision Transcript window without the commands actually being executed by the implementation tools op_for spdys sdpnol spdfmax spdyes speed yes Collapses all nodes up to the set Product Term limit globally optimized without regard for the path spdno speed no Collapses all nodes up to the set Product Term limit without increasing area cost spdfmax Causes the Logic Optimizer to automatically identify all critical paths between any pair of registers from clock pin of one register to data pin of the other register or the same register The Logic Optimizer then attempts to collapse combine the logic nodes along the critical paths reduce the logic level and allow the chip to run at a higher frequency If you specify an empty string the default then ispLEVER determines the best optimization for placement ba_format lt format gt Specifies as string which is the format of the back annotation file that will be generated by the implementation tools Possible options are Verilog VHDL EDIF or None The default is VHDL max_pterm_split lt string gt This option lets you control the Fitter optimization process by setting a maximum limit on the number of Produ
377. to the net is returned If the object list denotes an instance a list of all port instances associated with the instance is returned In a netlist ports and port instances can be connected to a net and nets can be connected to multiple ports and multiple port instances The report_connections command enables you to browse through the netlist finding netlist connections step by step The hierarchical argument extends the returned list of all connections from the indicated objects downward through the hierarchy within the same view More Examples report connections net Netl15 This example returns the list of the ports and port instances to which the net Net 15 is connected in the current design report_connections port 1145 out This example returns the name of the net to which the port instance i145 out is connected that is the port out on the view to which the instance i145 1s pointing report_connections instance i This example returns the list of the port instances for all the instances whose names starts with an i in the current design report connecLrions port clk hrer This example returns the list of nets to which the port clk is connected all the way down through the hierarchy Related Commands list_design Known Bugs Limitations You cannot use file I O redirection with this command because it returns a Tcl list and no standard output 3 134 Precision Synthesis Installation Guide 2003c Update Ma
378. ts command to specify the instance pathname and return the instance ports Related Commands all_inputs SDC get_ports SDC all_ outputs SDC all_registers all_ clocks SDC 3 26 Precision Synthesis Installation Guide 2003c Update March 2004 Commands all_ inputs SDC all_ inputs SDC Return a list of all input ports in the current design The search can be limited to input ports that have constraints relative to a given clock Example all 1nputs work top data path clock clkA clk B short Syntax all_inputs lt design_name gt clock lt clock_name s gt level_sensitive edge_triggered short lt clock_name s gt Arguments lt design_name gt Name of the design Options clock lt clock_name s gt Print only inputs that are related to the specified clock s level_sensitive not yet supported Print only input ports affecting logic that drive latches level sensitive related to the specified clock s edge_triggered not yet supported Print only input ports affecting logic that drive flip flops edge_triggered related to the specified clock s short Print only short names not the full path to objects Precision Synthesis Installation Guide 2003c Update 1 3 2 March 2004 all_ inputs SDC Commands Description The all_inputs command is a reporting command that returns a list of all input ports of the top level of the design as determine
379. ts options from the Setup Design dialog box in the GUI The Design Settings as specified in the Tools gt Set Options dialog boxes Once these setting are captured in a script you can hand modify a setting by editing the script You must issue two separate setup_design commands The first execution of setup_design sets the technology library information e g family xcve The second execution of the setup_design command sets the design information e g retiming verilog Related Commands set_working_dir Deprecated remove_design add_input_file compile save_project Obsolete synthesize load_project Deprecated remove_attribute Precision Synthesis Installation Guide 2003c Update 3 217 March 2004 setup _place_and_route Commands setup place _and_ route Setup the place and route environment Example setup_place_and_route flow ISE 5 1 command Integrated Place and Route bits 0 Do not generate a BitGen file in the Xilinx ISE 5 1 flow Syntax setup_place_and_route flow lt flow_name gt command lt command_name gt lt option gt help_command lt flow_name gt lt command_name gt Description The setup_place_and_route command 1s the mechanism that the Precision GUI uses to setup the place and route environment The setup options are unique for each flow command combination Therefore the technology must be specified with the setup_design command before this command is used The setup_place_and_r
380. tting a maximum limit on the number of Product Terms PT in each equation In other words the Optimizer shapes the equations relative to the set number of PT For example if the value is set to 35 the Optimizer stops collapsing equations when it exceeds 35 PT This option works the opposite of Splitting Max Product Term max_pterm_limit lt string gt max_fanin lt string gt Specifies the maximum fanin max_symbols lt string gt fmax_logic_levels lt string gt Xilinx ISE 5 1 Command Names cl default Run the vendor place and route flow in the background command line mode Use the options specified in the setup_place_and_route command Send a transcript of the executed commands to the Transcript window design_planner Bring up the Vendor Floor Planner for manual placement activity timing_analysis Run the Vendor Timing Analyzer on the routed design view_placement Launch the Vendor Floor Planner on the routed design for user viewing xpower Launch the Xilinx XPower power analysis application on the routed design gen_vcf Write a Vendor Constraint File to the active implementation directory Xilinx ISE 5 1 Command Arguments The arguments you specify here are the same options that may have been already set with the setup_place_and_route command They may be specified here to change a setup option on the fly when you execute the place_and_route command 3 108 Precision Synthesis Installation Guide 2
381. ture VHDL only for the design top if more than one architecture is possible basename frequency Returns the setting for the global design frequency in MHz This is normally set when the user enters a global frequency from the Setup Design dialog box input delay Returns the global setting for input delay output_delay Returns the global setting for output delay search_path Returns the setting for the input file search path This may be one or more pathnames of directories to be searched in a global search for files retiming Returns the setting for whether or not run the retiming algorithms The default 1s false transformations Returns the setting for whether or not to transform Set Reset on DFFs to Latches The default is true resource_sharing Returns the setting for whether or not to enable resource sharing The default 1s true advanced_fsm_optimization Returns the setting for whether or not to enable the advanced FSM optimization algorithms The default is t rue operator_preserve lt operator_name gt Sends a list all known synthesis libraries in the Transcript window Description The report_project command returns a report showing how the options are set for the current project Precision Synthesis Installation Guide 2003c Update 3 151 March 2004 report_project Commands Related Commands close_project setup_design Open_project 3 152 Precision Synthesis
382. type or if the SAFE_FSM option is selected from the graphical user interface and 1f there is a useful when others clause in a case statement assigning to the state vector then the following occurs 1 If you did not specify an encoding style a BINARY encoding is chosen and the when others statement is implemented 2 If you specified an encoding style onehot twohot gray binary random the states are encoded in the specified style and the when others is implemented vendor_constraint_file Specifies whether or not to generate a vendor constraint file The default 1s t rue If you wish to set this switch to false then you should use the following syntax vendor constraint file false verilog Write out a Verilog netlist The default is false If more than one output format switch is set true then an output file in each of the specified formats will be generated vhdl Write out a VHDL netlist The default is false If more than one output format switch is set true then an output file in each of the specified formats will be generated 3 216 Precision Synthesis Installation Guide 2003c Update March 2004 Commands setup design Description The setup_design command is the mechanism that the GUI uses to setup the design and technology environment The setup options are divided into Implementation Settings and Design Settings Implementation Settings are typically first captured as the user selec
383. u need a list of hierarchical pathnames to the sources of the clocks in the design use the find_clocks command You can also use wildcards and all object names are case sensitive Defined clocks do not contain hierarchy If you omit the search pattern Precision Synthesis returns an error Related Commands get_cells SDC get_lib_cells SDC get_designs get_lib_pins SDC get_false_paths get_multicycle_paths get_lib_cells SDC get_nets SDC get_lib_cells SDC get_path_definition_set get_ports SDC Precision Synthesis Installation Guide 2003c Update 3 63 March 2004 get_designs Commands get_designs Return a list of cells used in the current design Example get_designs Syntax get_designs lt patterns gt lt patterns gt Description The get_designs command returns a list of non library cells that are referenced in the current design This depth first search list contains library and cell names Related Commands get_cells SDC get_lib_cells SDC get_clocks SDC get_lib_pins SDC get_false_paths get_multicycle_paths get_lib_cells SDC get_nets SDC get_lib_cells SDC get_path_definition_set get_ports SDC 3 64 Precision Synthesis Installation Guide 2003c Update March 2004 Commands get_false_paths get_false_ paths Return a list of previously defined false paths Example get_false_paths gt temp sdc Syntax get_false_ paths lt patterns gt lt patterns gt
384. ugh inverting logic Note that the original reset signal must be implemented as preset logic to maintain the same initial state at the outputs Figure 4 8 Reset Signal Changes to Preset The Precision Synthesis in memory database is created by reading one or more HDL source files into memory Source files for all HDL libraries and packages must be read first then the design files are read Standard VHDL libraries and packages are loaded automatically if they are referenced in the design files Precision Synthesis Installation Guide 2003c Update 4 17 March 2004 Understanding the In Memory Design Data Model How Precision Compiles Understanding the In Memory Design Data Model The LeonardoSpectrum in memory design data base is modeled after the EDIF design data model All design data is stored in a set of EDIF type libraries which start at the root A library contains a list of cells and a cell contains a list of views In comparison to VHDL a ce11 is equivalent to an ENTITY and a view 1s equivalent to an architecture Just as most VHDL entities have only one architecture most cells have only one view Views are the basic building blocks of your design and are equivalent to a schematic sheet A view can have three types of objects ports nets and instances A view is the implementation or contents of a single level of hierarchy Examples 4 18 When you read a VHDL description into Precision Synthesis your VHDL entity translat
385. ull OULA OuLS always posedge wclk begin if wen begin outl lt datain mem addrl1 lt datain end else outl lt mem addrl out2 lt mem addr2 out3 lt mem addr3 end endmodule Precision Synthesis Installation Guide 2003c Update 1 9 27 March 2004 Handling Xilinx Design Issues Designing with Xilinx Tri Port RAM Port A Sync Read Write WRITE_FIRST Mode The Figure 9 25 write mode for port A is WRITE_FIRST recommended coding style sync read for port B and async read for port C Figure 9 25 Tri Port RAM Sync Read Write WRITE_FIRST Mode module swsr sr_ ar iweclk wen addril addrz addrs outl outz2 ours datain input welk Write clock input Write enable input addr input addrz2 input addr3 ouLpUL Ouc1 out pur OuUEZ output OUt input datain reg 0 0 31 A 32 x 8 bit memory array reg 20 Oulc Ly Ouz always posedge wclk begin if wen begin outl lt datain mem addrl lt datain end else outl lt mem addrl out2 lt mem addr2 end assign out3 mem addr3 endmodule TPort A Synchronously Written and Read in READ_FIRST Mode When port A is written and read synchronously at the same time the READ_FIRST write mode for port A refers to the write mode in which the location addressed is read first before it is written For Virtex Precision infers a set of dual port distributed rams for port A and B and another set of dual por
386. ulticycle_path SDC Commands Signal arrives at destination during this time window a Destination Data Signal Arrival Time Triggering edge for data arrival ma Source Clock i Edge 0 Edgb 1 Fidge 2 I Single cycle destination setup edge setup constraint Destination Single c _ cape hold constraint Hold ti nage ig Time Destination Ba Clock Edge 0 I Edge 1 Edge 2 Signal must arrive at destination Cycle during this time window Multicycle Required Arrival Window Multicycle destination Figure 3 10 Multicycle Timing 3 198 Precision Synthesis Installation Guide 2003c Update March 2004 Commands set_multicycle_path SDC If the path is defined by a single pin then either or both the Setup and Hold edges can be moved forward or backward in time thereby shifting the required arrival time window forward or backward in time Moving the Setup edge forward and or the Hold edge backward in time stretches the required arrival time window across multiple destination clock cycles If the path is defined by multiple pins then the Setup constraint can only be moved forward in time and the Hold constraint can only be moved backward in time It is possible to assign different multicycle definitions to different pins along the same path During analysis the most optimistic cycle numbers are used to analyze the path along which more than one multicycle definition is encountered For the purposes of slack p
387. urrent directory only the prefix is needed The following define the file extensions xdb output design file in Mentor Graphics binary format pdb PreciseView placement database file fdb Precise View floorplanning database file For more information on these files see the RTL Synthesis Output Files and Step 3 Run the Automated Physical Synthesis Flow sections in Chapter 2 of the Precision Physical Synthesis Users Manual Options floorplan_only Specifies the macro s relate only to floorplanning If this switch 1s specified for fully relocatable macros only xdb and fdb files are used Otherwise xdb pdb and fdb files are used Note When a pdb file is missing and the floorplan_only option is not specified the following warning message is issued Precision Synthesis Installation Guide 2003c Update 3 19 March 2004 add_ macro file Commands Could not find Tile path to prerix podb Description The Macro Builder project requires that you specify macros that will be used to overlay the design These macros require an XDB and optionally a PDB and or FDB It is not expected that the same macro would be specified more than once but the last one specified is the message that is used The tool may display the following messages xdb file is missing Error Could not find file lt xdb file name gt Macro file lt macro file name gt has not been added fdb file is missing Warning Could not find
388. urrent in memory physical database 3 14 Precision Synthesis Installation Guide 2003c Update1 March 2004 Commands activate_impl activate_impl Activate the specified implementation Example activate impl impl uart_ top impl 1 Syntax activate_impl impl lt impl_name gt discard ni Arguments impl lt impl_name gt Name of the implementation to activate Options discard Discard any unsaved work in the implementation being deactivated Description The activate_imp1 command is a project manager command available only when a project is loaded It activates the named implementation within the current project An error occurs if the currently active implementation has unsaved work Use the discard option to discard the unsaved work or call save_impl prior to calling activate_impl Related Commands copy_impl new_impl delete_impl save_impl get_impl_property set_impl_property get_project_impls Precision Synthesis Installation Guide 2003c Update 3 15 March 2004 add_input_file Commands add_input_file Add one or more file s to the input_file_list Example add_input_file F src statemachine vhd F src datapath vhd Syntax add_input_file lt file_list gt format lt file type gt work lt library_name gt exclude insert_ before lt position_number gt insert_after lt position_number gt replace search path lt pathname_list gt
389. ut Check all technologies All output ports on technology cells define the maximum number of loads that the cell can drive This value is set by the vendor Typically the library will also have a global fanout limit e g max_fanout Transition Time Check Actel technologies only The output pin on every cell in the technology library has a maximum transition slew If the driven net exceed this maximum slew Precision will either replicate the driving logic or buffer the net in an effort to decrease the loading on the net Capacitance Loading Check Actel technologies only Some technologies also specify a maximum capacitance load that an output pin on an internal cell can drive If a driven net exceed this value Precision will usually address the problem by buffering the driven net The following process describes how Precision determines load capacitance on a net only for Actel and ASIC technologies 1 Sums pin capacitance For each library cell pin connected to the net Precision sums the Capacitance property value attached to the pin Vendors define the pin capacitance property on every input pin and optionally on every output pin for each cell in the library 2 Determines which route table to use Because the actual net capacitance cannot be determined until a design goes to layout Precision uses a set of route tables created by the technology vendor to estimate the net capacitance Technology vendors provide route ta
390. ut_delay clock sysclk 4data_out Syntax remove_output_delay lt delay_value gt lt port_pin_list gt clock lt clock_ name gt clock_fall rise fall add_delay design rtl gatelevel Type Arguments float lt delay_value gt string lt clock_name gt list lt Por pin osr Arguments lt delay_value gt Specifies the delay value to be removed from the specified lt port_pin _list gt lt port_pin_list gt A list of output port name s or internal pin name s in the current design to which lt delay_value gt is to be removed If more than one object is specified the objects must be enclosed in quotes or in braces Options Clock lt clock_name gt Specifies the reference clock to which the specified delay is related If clock_fa11 is used then clock lt clock_name gt must be specified If clock is not specified the delay is relative to time zero for combinational designs For sequential designs the delay is considered relative to a new clock with the period determined by considering the sequential cells in the transitive fanout of each port clock_fall Specifies that the delay is relative to the falling edge of the clock The default is the rising edge Precision Synthesis Installation Guide 2003c Update 3 125 March 2004 remove_output_delay Commands rise Specifies that lt delay_value gt refers to a rising transition on specified output ports in the current
391. ve_attribute work name Version Remove the attribute Version that is set on the library work remove_attribute design gatelevel name DONT_TOUCH Remove the attribute DONT_TOUCH on the gatelevel design Related Commands set_attribute Precision Synthesis Installation Guide 2003c Update 3 115 March 2004 remove_ clock Commands remove_clock Remove the clock information from the specified object s Example Syntax remove _ clock name lt clock name gt all lt object_name gt lt attribute_type gt Arguments name lt object_name gt Name of the object port or net that owns a clock attribute Wild cards and lists are accepted If you omit this argument the remove_clock command operates on the current design Options all These options act as a filter to remove clock attributes from some of the objects in the port_pin list The port option type lt attribute_type gt This specifies the data type of the attribute that 1s being remove Valid values such as string or boolean depend on the attribute specified with the name option Description Remove the clock information on an object s Related Commands set_attribute 3 116 Precision Synthesis Installation Guide 2003c Update March 2004 Commands remove_clock_latency remove_clock_latency Remove the clock latency information from the specified object s Example create_clock name sys_clock90 ul udcm Q remove_clo
392. x save_physical Description The save_physical command saves the in memory physical database to the active implementation directory You must have a valid Precision Physical Synthesis license to run this command In addition to saving the physical database the tool writes out the following files Xilinx pdb fdb edf ucf Altera pdb fdb edf xrf _placement tcl tcl Related Commands setup_design physical_synthesis compile Precision Synthesis Installation Guide 2003c Update 3 161 March 2004 save_project Obsolete Commands save_project Obsolete This command has been replaced by the save_imp command Calls to save_project will actually execute the save_impl command 3 162 Precision Synthesis Installation Guide 2003c Update March 2004 Commands select select Select a list of objects Example select U db Bring up the Design Browser and select all objects that start with U Syntax select lt objects gt ports pins nets instances pd rtl all add db hds edit clear Arguments lt objects List of object to be selected Options file lt file_name gt The name of a schematic file to view linenum list A select the line numbers of the file specified by the file option ports pins nets instances pd rtl all Select pins ports nets instances the current design pd or
393. y has an attribute with the same name as that indicated by the name option the set_attribute command overwrites the existing value with the newly specified value Although a user can define and attach any named attribute to a design object Precision Synthesis only responds to certain attributes A list of general purpose and vendor specific attributes can be found in Chapter 2 Attributes More Examples set_attribute port clk name PIN NUMBER value P14 Set attribute PIN_NUMBER on port clk of the current design to the string P14 set_attribute work name Version value My library version 3 0 Set the attribute Version on the library work to the string My library version 3 0 set _attribute name NOOPT value TRUE Set attribute noopt on the current design to TRUE Related Commands remove_attribute 3 166 Precision Synthesis Installation Guide 2003c Update March 2004 Commands set_clock_latency SDC set_clock_latency SDC Specifies delay from pin where clock is defined to register clock pin Example set_clock_latency sysclk rise 2 set_clock_latency sysclk fall 2 5 Syntax set_clock_latency lt delay gt object_name rise fall source design rtl gatelevel ist lt clock_list gt Arguments lt value gt Number of nanoseconds for the delay value object_name List of defined clocks specified with the create_clock command Options rise Specify latency for rising
394. ynuseioff useioff Inff outff triff Specifies to use I O flip flops to improve timings Syn_useenables Use_dffenables Prevents generation of registers with clock enables Syn_hier hierarchy Specifies in HDL code about the way the compiler should handle hierarchy Syn_encoding encoding e xplicitly defines FSM encoding Pre Defined User Attributes The following is a list of pre defined User attributes that you can set from the Verilog or VHDL source code a Tcl script or by using the Interactive Command Line Shell once the design is read into memory array_pin_number VHDL only This VHDL only attribute makes it easier to assign pin numbers to buses VHDL Example entity sync_ram is port data in in UNSIGNED 7 downto 0 address in UNSIGNED 15 downto 0 we in Std logici Precision Synthesis Installation Guide 2003c Update 2 9 March 2004 Pre Defined User Attributes Attributes clk lt am std logic data_out in UNSIGNED 7 downto 0 type mentor_string_array is array natural range lt gt natural range lt gt of character attribute array_pin_number mentor_string_array attribute array_pin_number of data_out signal is H2 F H4 E4 DpyL P ae Ga lees i D5 C4 A8 r end sync_ram In the above example the pin numbers are assigned left to right H2 is assigned to data_out 7 H4 is assigned to data_out 6 and so on async_reg Xilinx Allows you to specify an
395. you can specify the input delay with this set_input_delay command and specify the output delay with the set_output_delay command To describe a path delay from a level sensitive latch you should use the level_sensitive option If the latch 1s positive enabled set the input delay relative to the rising clock edge if it 1s negative enabled set the input delay relative to the falling clock edge If time is being borrowed at that latch you should add that time borrowed to the path delay from the latch when determining input delay Precision Synthesis Installation Guide 2003c Update 1 3 183 March 2004 set_input_delay SDC Commands Related Commands set_false_path SDC report_attributes set_output_delay SDC report_missing_constraints set_false_path SDC remove_input_delay set_multicycle_path SDC 3 184 Precision Synthesis Installation Guide 2003c Update March 2004 Commands set_input_dir set_input_dir Set the relative path names when adding input files Example set_input_dir C designs src Syntax set_input_dir lt input_dir_path gt lt xinput dir path gt Arguments lt input_dir_path gt A full pathname to a directory Description The set_input_dir command sets the absolute path used to resolve the relative path names when adding input files You can set the input directory using the set__input_dir command and then use the add_input_f ile command to add relative paths from the input directory Fo

Precision Synthesis Reference Manual

Contents

Download Pdf Manuals

Related Search

Related Contents