DNA-SL-504 Product Manual - United Electronic Industries
Contents
1. A HB Copyright 2012 Tel 508 921 4600 www ueidaq com Vers 4 5 United Electronic Industries Inc Date November 2012 DNx Al 504 Chap3 fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter3 30 Programming with the Low level API 3 3 2 Sending and DqAdv504SendFrame is used to send a frame and Receiving DgAdv504RecvFrame is used to receive a frame HDLC Frames Both functions have similar parameters int DqgAdv504SendFrame int hd int devn int chnl int flags uint8 data int rq size int written int available int DgAdv504RecvFrame int hd int devn int chnl int flags uint8 data int rq size int received int available int hd handle to the IOM int devn device number int chnl device channel int flags behavior modification flags uint8 data data to send intrq size number of bytes to write or size of the receive buffer int written or received number of bytes written or received or error code int available number of frame entries left available Both functions are working with one frame at a time Internally the Z16C32 is programmed to take advantage of DMA operations between its bus and the PSRAM chip on the layer By default sixteen 4096 bytes frames are2. J JJH sl Tel 508 921 4600 www ueidaq com Date November 2012 Copyright 2012 United Electronic Industries Inc Table 1 1 DNx SL 504 Technical Specifications Port Specifications Number ports 4 independently configurable UART type Zilog Z16C32 Interface types RS 232 RS 422 423 RS 485 Protocols Async HDLC SDLC FIFOs 32byte input and output per port Baud rate generator RS 232 specifications RS 232 Asynchronous Programmable 9 6 kbaud to 4 Mbaud 256 kbaud 600 kbaud Tx TXCLK Out Rx RxCLK In CTS Sync DCD RS 232 Synchronous RS 232 Signals RS 485 422 specifications RS 485 422 Async 1 Mbaud RS 485 422 Synchronous 4 Mbaud RS 485 422 Signals Tcr Dc TXCLK TXCLK RX RX RxCLK RxCLK CTS CTS DCD DCD General Specifications Isolation 350 V port to port ESD protection 15 kV Power Consumption 2 5W RS 485 mode with max current drive Operating Temperature Tested 40 to 85 C Operating Humidity 0 95 non condensing Vibration IEC 60068 2 6 5 g 10 500 Hz sinusoidal IEC 60068 2 64 5 g rms 10 500 Hz broad band random Shock IEC 60068 2 27 50 g 3 ms half sine 18 shocks 6 orientations 30g 11 ms half sine 18 shocks 6 orientations MTBF 290 000 hours Vers 4 5 DNx SL 504 Chap1x fm
3. 16 MBytes SRAM oz Optical Isolation Boundary Figure 1 4 Logic Block Diagram DNA DNR SL 504 Overview The DNx SL 504 is equipped with four software controlled EXAR SP506 single chip multi mode serial line transceivers one per channel that select the type of DTE to DCE connectivity to be used for the physical layer communication The SP506 chip also provides an internal loop back feature that eliminates the need for a loopback plug In loopback mode driver outputs are internally connected to receiver inputs creating an internal path for diagnostic testing This chip is an integrated design that also provides any necessary termination hardware that may be needed The interface modes supported by the SP506 chip are RS 232 RS 422 EIA 530 EIA 530A RS 449 V 35 V 36 and RS 485 It achieves differential transmission rates of more than 20 Mbps In the SL 504 the modes offered are RS 232 RS 422 and RS 485 The SP506 Transceiver is controlled by an FPGA the board control chip The FPGA works in conjunction with the core module logic of the DNA or DNR chassis The SL 504 Module consists of two PC boards one of which is a 61x Base Board and another which is the four port 504 specific I O board The 504 specific board plugs into a bus connector on the base board Copyright 2012 f Tel 508 921 4600 www ueidaq com Vers 4 5 United Electroni Industriesyine Date November 2012 DN
4. Position The base board of a DNA SL 504 module layer has a jumper block that assigns the position of the module within a PowerDNA Cube The jumpers must be set to match the physical position of an I O board or layer in the Cube Board position jumpers are not provided with the DNR versions of the SL 504 The physical position of the board within the DNR RACKTangle enclosure is determined automatically by the system All layers are assembled in Cubes before shipment with identifying labels so you should never have to change a jumper setting unless you have to change a layer from one physical position to another in the field Figure 1 6 shows the physical layout of DNA SL 504 Board highlighted to show the 16 pin jumper block for setting the board position within a PowerDNA Cube DNA SL 504 PC 61x EA l See fig 1 7 for placement of jumpers for various board positions in a Cube 10 12 14 16 O 0 0O OjO Ojo oO oo ololo ojo 0 9 n 13 15 Figure 1 6 Jumper Block for DNA SL 504 Board Position A diagram of the jumper block is shown in Figure 1 7 To set the board position jumpers place jumpers as shown in Figure 1 7 Layer s Position as marked on the Faceplate 1 01 1 0 2 1 0 3 1 0 4 1 05 1 0 6 9 10 oo oo oo oo 11 12 o0 oo oo 13 14 oo oo oo oo 15 16 cm All I O Layers are sequentially enumerated from top t
5. 36 56 14 35 SHIELD GND 62 42 21 Iis wn lu Figure A 1 Pinout and photo of DNA STP 62 screw terminal panel Tel 508 921 4600 Date November 2012 www ueidaq com Vers 4 5 DNx Al 504 AppxA fm 35 DNA DNR SL 504 Synchronous Serial Line Communication Module 36 Index B J Block diagram 12 Jumper Settings 15 C L Cable s 35 Layer Position Jumper Settings 15 Capabilities 13 Low level API 22 Cleaning up the Session 21 Cleaning up the session 21 Configuring the Resource String 16 Conventions 2 S Creating a Session 16 O Organization 1 Screw Terminal Panels 35 H Setting Operating Parameters 4 High Level API 16 Support ii l W Isolation 3 Wiring 14 Copyright 2012 Tel 508 921 4600 www ueidaq com Vers 4 5 eit Elecironig industries Ine Date November 2012 DNx SL 504 ManuallX fm
6. timing mode the Timing A message is represented by an array of bytes The SL 504 can be programmed to wait for a certain number of bytes to be received before notifying the session It is also possible to program the maximum amount of time to wait for the specified number of bytes before notifying the session The following sample shows how to configure the messaging I O mode to be notified when 10 bytes have been received or every second whichever is less Note that if the serial port receives less than 10 bytes per second it will return whatever number of bytes are available every second configure timing of serial port session ConfigureTimingForMessagingIO 10 1 0 2 4 Read Data Reading data from the SL 504 is done using a reader object As there is no multiplexing of data contrary to what s being done with Al DI or Cl sessions you need to create one reader object per serial port to be able to read from each port in the port list 2 4 4 Asynchronous The following sample code shows how to create a reader object tied to port 1 Mode and read up to 10 bytes from the serial port Create a reader and link it to the session s stream port 1 reader new CUeiSerialReader slSession GetDataStream 1 we ll want to store for 10 bytes char sized Unsigned char bytes 10 read up to 10 bytes numBytesRead contains the number of bytes actually received reader gt Read 10 bytes amp numBytesRead 2 4 2 HDLC
7. define SL504 HDLC BIPHASE LEVEL 7L 0 fy biphase encoding used with DPLL define SL504 HDLC BIPHASE DIFF 8L 0 Fi biphase encoding used with DPLL NRZ non return to zero encoding requires synchronous clock Thus both TxD and TxC and or RxD and RxC pairs need to be used One is represented by one physical level Zero is represented by another level usually a positive voltage Actual one and zero representation depends on the physical interface selected In NRZI Space One is represented by no change in physical level Zero is represented by a change in physical level In clock language the level transitions on the trailing clock edge of the previous bit to represent a zero Copyright 2042 Tel 508 921 4600 www ueidaq com Vers 4 5 United Electronic Industries Inc Date November 2012 DNx Al 504 Chap3 fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter3 26 Programming with the Low level API 3 3 NRZI Mark This change on zero is often used by High Level Data Link Control HDLC Encoding avoids long periods of no transitions even when the data contains long sequences of 1 bits by using zero bit insertion HDLC transmitters insert a 0 bit after five contiguous 1 bits except when transmitting the frame delimiter 01111110 The receiver automatically detects and deletes inserted zeros NRZI Inverted is another form of the NRZ encoding The two level NRZI signal has a
8. 0 User is responsible for inserting and checking CRC define SL504 HDLC CRC 16 CCITT 2L 0 16 f bit CCITT CRO is used define SL504 HDLC CRC 16 3L 0 16 bit polynomial CRC is used define SL504 HDLC CRC 32 4L lt lt 0 32 bit Eth CRC is used 16 bit CCITT CRC uses the x x 2 x 1 polynomial 16 bit ANSI CRC uses the x16 x15 x 1 polynomial 32 bit CRC uses x22 x26 234224 164 124 114 10484 7 X9 4X X2 1 HDLC protocol allows filtering of the received packets by its lt hdlc_flt_mode gt which selects the type of filtering to use selection of the type of filtering is application dependent define SL504 HDLC FLT NONE OL 0 No filtering define SL504 HDLC FLT A 16 1L 0 16 bits into RxFIFO if Addr matches or B C as 2 bytes define SL504 HDLC FLT A 24 2L lt lt 1 24 bits into RxFIFO if Addr matches or B C as 3 bytes define SL504 HDLC FLT A 32 6L 1 32 bits into RxFIFO if Addr matches or B C as 4 bytes define SL504 HDLC FLT EA LS 7L 1 Places bytes while LS 0 then byte with LS 1 then 16 bits as 2 bytes into RxFIFO if EA matches or B C define SL504 HDLC FLT EA 24 3Lh 1 Places 24 bits as 3 bytes into RxFIFO if EA matches or B C define SL504 HDLC FLT EA MS 11L lt lt 1 Places bytes while MS 0 then byte with MS 1 then 8 bits as 1 byte into RxFIFO if Ext Addr matche
9. 2012 DNx SL 504 Chap1x fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter 1 Introduction 10 Structure The contents of an HDLC frame are shown below Flag Address Control Information FCS Flag 8 bits 8 or more bits 8 or 16 bits Variable length 0 or more bits 16 or 32 bits 8 bits Note that the end flag of one frame may be the beginning flag of the next frame Data is usually sent in multiples of 8 but not in all cases The FCS is a 16 bit CRC or 32 bit CRC computed over the Address Control and Information fields Its purpose is to detect errors introduced during transmission of the frame Since the probability of an undetected error occurring increases with data length the FCS implicitly limits the practical size of the frame If the receiver calculated FCS does not match that of the sender the receiver either sends a negative acknowledge packet or sends nothing The sender can then retransmit the failed frame SDLC was originally designed to connect one computer with multiple peripherals in a master slave relationship in which the computer primary terminal gives each peripheral secondary terminal permission to speak in turn Only one address that of the secondary terminal is used Commands and responses are the same they only difference between them is the direction of transmission In HDLC normal response mode allows operation over half duplex links provided the prima
10. 5 1 6 What is Serial Communicati on Copyright 2012 United Electronic Industries Inc DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter 1 Introduction A serial port sends and receives data one bit at a time over one line composed of a send a receive and one common ground wire RS 232 is a standard for serial binary data interconnection between a DTE data terminal equipment and a DCE data communication equipment and normally operates in a bipolar range of 10V to 10V RS is an abbreviation for Recommended Standard RS 485 a k a EIA 485 is a physical layer electrical specification of a two wire half duplex multipoint serial connection A full duplex RS 485 system can be constructed by using two twisted pair connections transmit receive pairs together as shown in Figure 1 2 UART data frames for RS 232 and RS 485 are shown in Figure 1 3 RS 422 is a standard specification for serial communication for information sent bit by bit on a single transmission line as in RS 232 The difference between the two is that RS 422 is a balanced differential signal RS 422 signal lines consist of two wires preferably twisted to reduce noise The voltage difference difference between the two lines represents the signal value rather than the voltage level alone This eliminates a lot of noise induced by external sources and therefore permits higher data rates and cable lengths than RS 232 There are more
11. Coordination a na saa aaaea 7 1 8 What is Synchronous Serial Communica tion 0 2200 20 e eee 8 1 9 Architecture oo eter Wie Gd eee ee RE Rs ea de Oe ca 12 1 10 Module Capabilities 222i 13 1 11 Wiring amp Connectors 0 2 0 lh n 14 1 12 Jumper Settings for Board Position aaua aaaea 15 Chapter 2 Programming with the High Level API 000 e eee eee eee eee 16 2 1 Creating a Session uum ke a le ge hx ERR E xr ee el 16 2 2 Configuring the Resource String 2 0 0 eae 16 2 2 1 Asyncronous serial port 2 0 eee 16 2 2 2 HDLC POM cc cide pee a bette eed Dict has bodied eae eee 18 2 3 Configuring the Timing 0 0 cee I n 20 24 FROG Da tinea PH TT 20 2 4 1 Asynchronous Mode cesserit teere ariaa ees 20 2 4 2 HDLC Mode 0200 a a a E a G tenes 20 2 5 Wite Data ox bec RE dae xd oa ee Mea UE Qu PRXLEN EE Pado Rar d LS 21 2 5 1 Asynchronous Mode 00 cece nn 21 2 5 2 HDLC MOd i 4 0c n2 eet xw auo eda selena REEERIMEGW ARRA SEES ene 21 2 6 Cleaning up the Session lille 21 Chapter 3 Programming with the Low level API 0c e eee eee eee 22 3 1 HDLC SDLC Mode 0 0 cc eee 23 3 2 Asynchronous Mode 2 6200 scire redau eae PEE sx R9 eee 24 3 2 1 Setting the configuration 0 cee eee 24 3 3 NRZI Mark Encoding 0 00 eect e 27 3 3 1 Enabling Operations 1 0 0 0 00 ce eae 30 3 3 2 Sending and Receiving
12. ONE 2L 0 all ones define SL504 HDLC PRMB FLAG 3L lt lt 0 all flags define SL504 HDLC PRMB 10 4L 0 alter nating 1 and 0 define SL504 HDLC PRMB 01 5L lt lt 0 alternating 0 and 1 HDLC is different from many other protocols in the fact that it continuously transmits idle characters when there is no data to transmit Idle character can be selected from one of the following define SL504 HDLC IDLE FLAG OL 0 Jf continuous flags 0x7E define SL504 HDLC IDLE ZERO 1L 0 ii continuous zeroes define SL504 HDLC IDLE ONE 2L 0 JJ continuous ones define SL504 HDLC IDLE MARK 3L lt lt 0 idle chars are marks define SL504 HDLC IDLE SPACE AL 0 idle chars are spaces define SL504 HDLC IDLE MS 5L 0 If alternating Mark and Space define SL504 HDLC IDLE 01 6L 0 a lternating 0 and 1 Most implementations use flag Ox7E as an idle character Copyright 2042 Tel 508 921 4600 www ueidaq com Vers 4 5 United Electronic Industries Inc Date November 2012 DNx Al 504 Chap3 fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter3 29 Programming with the Low level API When asynchronous mode is selected HDLC related fields should be zero and vice versa In asynchronous mode use the following fields to program mode of operation async baud select baud rate 2400 baud to 256kbaud async char sz Select
13. allocated for each channel for transmit and receive separately The maximum number of frames is 256 On transmission a new frame is added to the list of filled frames and the number of empty frames is returned The firmware stops accepting new frames when of the frames are used At this point DqgAdv504SendFrame returns zero in the written field Please notice when si504_ PHY _NOECHO flag is used the number of Tx frames is limited to one With this flag firmware disables receiver from the moment the frame is sent to the moment DMA informs firmware via interrupt that the transmission is completed On reception receiver stops when all frames are used up 3 3 3 Sending and pgadvs04SendMessage is used to send a frame and Receiving DqAdv504RecvMessage is used to receive a frame Asynchronou s Data Both functions have similar parameters int DqAdv504SendMessage int hd int devn int chnl int flags uint8 data int rq size int written int available int DqAdv504RecvMessage int hd int devn int chnl int flags uint8 data int rq size int received int available int hd Handle to the IOM int devn device number int chnl device channel Copyright 2012 Tel 508 921 4600 www ueidaq com Vers 4 5 United Electronic Industries Inc Date November 2012 DNx Al 504 Chap3 fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter3 31 Programming with the Low level API int flags behavior
14. differences between RS 422 and RS 232 than maximum data speed and cable length RS 232 was specifically defined as an interface between computers printers and terminals with modems Furthermore where the RS 232 line driver is only designed to serve one receiver a RS 422 line driver can serve up to 10 receivers in parallel This allows one central control unit to send commands in parallel to as manay as ten slave devices Unfortunately those slave devices cannot send information back over a shared interface line RS 422 allows a multi drop network topology rather than a multipoint network where all nodes are sonsidered equal and all nodes have send and receive capabilities over the same line If you need multi point communication rather than multi drop use RS 485 with a maximum of 32 parallel send and 32 receive units parallel on one communication channel Slave 1 Slave 2 Slaven SL 504 Master TX I 4 i ohm RX RX gt gt 5 A 240 ohm i 4 Two wire Twisted Pair Half Duplex Network with 240 ohm Terminating Resistors Slave 1 Slave 2 Slave n Ii 240 ohm SL 504 Master TX 7 LH zi Le lt f T 240 ohm zo 4 5 a RX NE RX Four wire Twisted Pair Full Duplex Network with 240 ohm Terminating Resistors Figure 1 2 RS 485 Topologies Tel 508 921 4600 www ueidaq com Vers 4 5 Date November 2012 DNx SL 504 Chap1x
15. for clock resynchronization This is because the transmitter inverts NRZI space data for every zero bit and there are never more than five one bits in succession within a frame Since the flag matching hardware operates without regard for character bound aries bit oriented synchronous protocols can handle any number of bits in length The current implementation of the SL 504 card allows the transmission of multiple of 8 bit character and reception of any number of bits It limits the maximum frame size of both receiver and transmitter to 4096 8 bit characters not including CRC Copyright 2012 f Tel 508 921 4600 www ueidaq com Vers 4 5 Moreo Eleone OCA EID Date November 2012 DNx AI 504 Chap3 fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter3 23 Programming with the Low level API 3 2 Asynchronous Asynchronous mode supports both RS 232 and RS 485 protocols The user can Mode select the number of start and stop bits parity mode and number of data bits per each character 3 2 1 Setting the DqAdv504SetConfig is used to set up channel configuration configuration DqAdv504SetConfig int handle int devn int channel SL504 SETCFG config SL504 SETCFG is defined as follows typedef struct uint32 protocol protocol used HDLC sync async flags uint32 modeflags additional flags for mode selection uint32 physical physical interface RS 232 422 485 fill the following sec
16. modification flags uint8 data data to send intrq size number of bytes to write or size of the receive buffer int written or received number of bytes written or received or error code int available number of bytes left available In the current implementation the size of transmit and receive FIFOs is 32 characters 3 3 4 Obtaining To obtain the link status the function Link Status int DgAdv504GetStatus handle device pSL504 INT STAT status is used to retrieve accumulated link statistics Interface status typedef struct int cts number of CTS transitions int ded number of DCD transitions int tx bytes transmitted int ftx frames transmitted int rx bytes received int frx frames received int frm err frame errors int ovr err overrun errors Rx int und err underrun error Tx int prt err parity errors int tx_abort Tx frame aborts int rx abort Rx frame aborts int short err Rx frames too short to be valid int long err Rx frames too long 54096 to be valid int lines current line state int err stat most recent error status int brk number of breaks int exithunt ditto exited hunt mode int rxidle ditto idle int rsv3 int rsv4 int rsv5 int rsv6 int rsv7 there are a few important registers to return for debug purposes uintl16 tdmr Tranmit DMA status reguster uintl6 rdmr Receive DMA status reguster uintl16 cc
17. polarity is the same or is different from the previous value this makes synchronization even easier Finally if the high and low states have the same voltage with opposite polarity coded signals have zero average DC voltage thus reducing the necessary transmitting power and minimizing the amount of electromagnetic noise produced by the transmission line All these positive aspects are achieved at the expense of doubling clock frequency hdlc baud used to select baud rate hdlc clk src defines where receiver and transmitter receive clock from define SL504 HDLC FLAG RXC RXCPIN 1L 0 RxClk from RxC pin default define SL504 HDLC FLAG RXC DPLL 2L 0 RxClk from DPLL define SL504 HDLC FLAG RXC BRG 3L 0 RxClk from BRGO define SL504 HDLC FLAG TXC BRG 1L 2 TxClk from BRGO default define SL504 HDLC FLAG TXC DPLL 2L 2 TxClk from DPLL define SL504 HDLC FLAG TXC RXCPIN 3L 2 TxClkfromRxC pin define SL504 HDLC FLAG DPLL DIV8 1L 4 DPLL divider 8 define SL504 HDLC FLAG DPLL DIV16 2L 4 DPLL divider 16 There are three main sources of the clock available for both transmitter and receiver Both of them can be programmed to use any of these clocks J A O HxHC O t Copyright 2012 Tel 508 921 4600 www ueidaq co
18. 2 32 bits into RxFIFO if Addr matches or B C as 4 bytes UeiHDLCPortFilterEALS Places bytes while LS 0 then byte with LS 1 then 16 bits as 2 bytes into RxFIFO if EA matches or B C UeiHDLCPortFilterEA24 Places 24 bits as 3 bytes into RxFIFO if EA matches or B C UeiHDLCPortFilterEAMS Places bytes while MS 0 then byte with MS 1 then 8 bits as 1 byte into RxFIFO if Ext Addr matches or B C UeiHDLCPortFilterEAMS16 Places bytes while MS 0 then byte with MS 1 then 16 bits as 2 bytes into RxFIFO if Ext Addr matches or B C Disable filter pPort gt SetFilterMode UeiHDLCPortFilterNone Filter address The address to filter Set address to filter pPort gt SetFilterAddress 0x52 Idle flags The pattern to transmit when the link is idle UeiHDLCPortldleFlag continuous flags UeiHDLCPortldleZero continuous zeroes UeiHDLCPortldleOne continuous ones UeiHDL CPortldleMark idle chars are marks UeiHDLCPortldleSpace idle chars are spaces Copyright 2012 f Tel 508 921 4600 www ueidaq com Vers 4 5 United Electronic Industries ine Date November 2012 DNx SL 504 Chap2x fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter 2 20 Programming with the High Level API UeiHDLCPortldleMS alternating Mark and Space UeiHDL CPortldle01 alternating O and 1 Set idle pattern pPort gt SetidleCharacter UeiHDLCPortIdleOne 2 3 Configuring The application must configure the SL 504 to use the messaging
19. 508 921 4600 www ueidag com Vers 4 5 United Electronic Industries ine Date November 2012 DNx SL 504 Chap2x fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter2 19 Programming with the High Level API In addition you can set the following parameter using the channel object meth ods under LabVIEW use property node Termination Select whether to enable or disable termination resistors enable termination resistor pPort EnableTerminationResistor true Echo suppression Select whether to suppress echo in half duplex mode RS 422 Disable echo pPort EnableHDEchoSuppression true Loopback Select whether transmitter and receiver of the same port are tied Disable loopback pPort gt EnableLoopback false Abort Symbol The symbol used to abort UeiHDLCPortAbort7 Send Ox7F to abort UeiHDLCPortAbort15 Send Ox7FFF to abort Set abort symbol to Ox7F pPort gt SetAbortSymbol UeiHDLCPortAbort7 Underrun Action The action taken when underrun condition is detected UeiHDLCPortUnderrunFinish Close the frame by adding CRC to it UeiHDLCPortUnderrunFlags Send flags Set underrun action pPort gt SetUnderrunAction UeiHDLCPortUnderrunFinish Filter Mode The filter setting UeiHDLCPortFilterNone No filtering UeiHDLCPortFilterA16 16 bits into RxFIFO if Addr matches or B C as 2 bytes UeiHDLCPortFilterA24 24 bits into RxFIFO if Addr matches or B C as 3 bytes UeiHDLCPortFilterA3
20. HDLC Frames 0 0000 cee eee 31 3 3 3 Sending and Receiving Asynchronous Data 20 0 ee eae 31 3 3 4 Obtaining Link Status 0 0 ec eae 32 3 3 5 Aborting Transmission 00 00000 eh 34 as ur ieu Tel 508 921 4600 www ueidaq com Vers 4 5 A d CDM E Date November 2012 DNx SL 504 ManualTOC fm DA To I E o gy o NOORA ON gt Copyright 2012 United Electronic Industries Inc DNA DNR SL 504 Synchronous Serial Line Communication Module Figures List of Figures The DNA SL 504 Serial Layer c ic se adiecta da v ha dua 4 RS 485 Topologies ssssssssssssseeee eene eere nennen enne nenne 6 UART Data Frames for RS 232 and RS 485 sse enne 7 Logic Block Diagram DNA DNR SL 504 Overview see 12 DNx SL 504 Connection Diagram esses 14 Jumper Block for DNA SL 504 Board Position sssssssssseee 15 Diagram of DNA SL 504 Board Position Jumper Settings 15 Pinout and photo of DNA STP 62 screw terminal panel sssssssssssss 35 Tel 508 921 4600 www ueidaq com Vers 4 5 Date November 2012 DNx SL 504 ManualLOF fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter 1 Introduction Chapter 1 Introduction This document outlines the feature set of the DNR and DNA SL 504 layer and its use for synchronous serial line communications applications 1 4 Organization T
21. I For HDLC mode protocol can be selected from protocols define SL504 PROT HDLC 1 HDLC protocol support define SL504 PROT ASYNC 2 Async mode char based define SL504 PROT SYNC 3 reserved Bit synchronous external sync no framing or synchronization define SL504 PROT ISOCHRONOUS 4 reserved isochronous mode define SL504 PROT NINEBIT 5 reserved 9th bit address mode define SL504 PROT RESVO 6 lt reserved gt define SL504 PROT BIMONOSYNC 7 reserved monosync or bisync mode define SL504 PROT T BISYNC 8 reserved transparent bisync mode define SL504 PROT S MONOSYNC 10 reserved slaved monosync mode Only two protocols are currently implemented SL504 PROT HDLC Works with HDLC and SDLC protocol SL504 PROT ASYNC Works with asynchronous protocol Once a protocol is selected there are a few protocol modifiers for HDLC mode modeflags define SL504 HDLC LOOP 1L 0 HDLC loop mode define SL504 USE CTS 1L 4 CTS input this controls transmission define SL504 USE DCD 1L 5 DCD enables receiver define SL504 INHIBIT TX 1L 6 Do not enable transmitter define SL504 INHIBIT RX 1L 7 Do not enable receiver The SL 504 layer has two inputs per channel one is CTS and the second one is DCD By selecting bits 4 and 5 the user gives control over transmission enable to CTS input a
22. Mode The following sample code shows how to create a reader object tied to port 1 and read up to 10 bytes from that HDLC port Create a reader and link it to the session s stream port 1 reader new CUeiHDLCReader hdlcSession GetDataStream 1 we ll want to store for 10 bytes char sized uInt8 bytes 10 read up to 10 bytes reader gt Read 10 bytes amp numBytesRead Copyright 2012 i Tel 508 921 4600 www ueidaq com Vers 4 5 United Electronic Industries Inc Date November 2012 DNx SL 504 Chap2x fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter 2 21 Programming with the High Level API 2 5 Write Data Writing data to the SL 504 is done using a writer object As there is no multiplexing of data contrary to what s being done with AO DO or CO sessions you need to create one writer object per serial port to be able to write to each port in the port list 2 5 4 Asynchronous The following sample code shows how to create a writer object tied to port 2 Mode and send one byte to the serial port Create a writer and link it to the session s stream port 2 writer new CUeiSerialWriter session GetDataStream 2 store the one byte we want to write out unsigned char bytes 2 0x23 0 write 1 byte numBytesWritten contains number of bytes actually sent writer Write 1 bytes amp numBytesWritten 2 5 2 HDLC Mode The following sample code shows how to create a writer object
23. SL 504 Chap1x fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter 1 Introduction HDLC Protocol HDLC the current ISO standard synchronous data link layer protocol supports three types of transfer modes whereas SDLC supports only one Normal Response Mode NRM The three modes supported by HDLC are e Normal response mode NRM secondaries cannot communicate with a primary until the primary has given permission e Asynchronous response mode ARM Secondaries can initiate communi cation with a primary without receiving permission e Asynchronous Balanced Mode ABM In this mode the node can act as a primary or secondary depending on the situation All communication occurs between multiple combined nodes Any combined station can initiate data transmission without permission from any other Framing HDLC frames can be transmitted over synchronous or asynchronous links As they have no means for marking the beginning or end of a frame these points are identified by a frame delimiter or flag which is a unique sequence of bits guaranteed not to be seen inside a frame The sequence is 01111110 Ox7E hex Each frame begins and ends with a frame delimiter A frame delimiter at the end of a frame may also mark the start of the next frame A sequence of 7 or more consecutive 1 bits within a frame causes the frame to be aborted When no frames are being transmitted over a simplex or full duplex synchronous
24. ZN United Electronic wy Industries The High Performance Alternative DNx SL 504 User Manual 4 Channel RS 232 or RS 422 423 485 serial port layer for the PowerDNA Cube and PowerDNR RACKtangle with support for Synchronous Serial Data Communcation protocols SDLC HDLC async bisync protocols Release 4 5 November 2012 PN Man DNx SL 504 1112 Copyright 1998 2012 United Electronic Industries Inc All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form by any means electronic mechanical by photocopying recording or otherwise without prior written permission Information furnished in this manual is believed to be accurate and reliable However no responsibility is assumed for its use or for any infringement of patents or other rights of third parties that may result from its use All product names listed are trademarks or trade names of their respective companies See the UEI website for complete terms and conditions of sale http www ueidaq com cms terms and conditions Contacting United Electronic Industries Mailing Address 27 Renmar Avenue Walpole MA 02081 U S A For a list of our distributors and partners in the US and around the world please see http www ueidaq com partners Support Telephone 508 921 4600 Fax 508 668 2350 Also see the FAQs and online Live Help feature on our web site Internet Support Suppor
25. angle chassis The board is an ideal interface to a wide variety of serial based data acquisition and control interfaces as well as general purpose serial I O The DNx SL 504 is based on the Zilog Z16C32 serial controller chip and supports most popular synchronous serial protocols including HDLC and SDLC The HDLC SDLC interface provides full access to the serial frames User code can then determine how to handle retry or protocol corrections The RS 485 422 implementation provides transmit and receive data synch and clock interfaces The RS 232 configuration also supports CTS signals The maximum transfer rate in RS 485 422 and RS 232 modes are 4Mbaud and 600kbaud in synchronous mode respectively The DNx SL 504 support standard asynchronous serial transfer rates up to 2 Mbaud in RS 485 mode or up to 256 kbaud in RS 232 mode It also supports communications at 12 12 5 and 50 kbaud with better than 0 196 data rate accuracy The UART supports 5 6 7 or 8 data bits plus optional even or odd parity The transmitters will also supply 1 2 or fractional stop bits per character and can provide a break output at any time Summarized as follows are supported modes e HDLC with synchronous and asynchronous framing e Asynchronous and synchronous serial byte oriented like SL 508 parity none even odd mark space Raw mode user controlled FIFO based synchronous The DNx SL 504 are compatible with RS 422 point to point or RS 485 network appl
26. cm long weight of 9 49 ounces or 269 grams up to 10ft 305cm and 20ft 610cm DNA STP 62 The STP 62 is a Screw Terminal Panel with three 20 position terminal blocks JT1 JT2 and JT3 plus one 3 position terminal block J2 The dimensions of the STP 62 board are 4w x 3 8d x1 2h inch or 10 2 x 9 7 x 3 cm with standoffs The weight of the STP 62 board is 3 89 ounces or 110 grams DB 62 female JT3 20 position terminal block to JT1 to JT2 J2 SHED GND 62 42 21 JTI 20 41 61 19 40 60 18 39 59 17 38 58 16 37 57 15 36 56 14 35 JT2 55 13 34 54 12 33 53 11 32 52 10 31 51 9 30 50 8 29 49 7 62 pin Connector JT3 COKDICDEKCDKDEDIOKDIEDKDIODICDKDEDIOIKDIDIKGDIODIC 22 1 43 23 2 44 24 3 45 25 4 46 26 5 47 27 6 48 28GND i0 0j0 ojo ojo ojo o o o o o o o o o O O 22 1 43 23 2 44 24 3 45 25 4 46 26 5 47 27 6 48 28 GND JT2 20 position terminal block 55 13 34 54 12 33 53 11 32 52 10 31 51 9 30 50 8 29 49 y i0 0j 0 o 0 oj0 o o o o o o o o Oo o O O O JT1 20 position J2 5 position terminal block terminal block i0 0j0 ojo oj0 ojo o o o o o o o o O O O 20 41 61 19 40 60 18 39 59 17 38 58 16 37 57
27. fm 6 DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter 1 Introduction 7 Example of UART Data Frame 0x09 8 Data Bits Odd Parity 1 Stop Bit Data 170 0 1 1 0 140 Idle S 0 3 4 5 67 P S Ide RS 232 5V JU LOILILL RS 485 5V UN ULI UU OV 5V sa JU LILI ov Figure 1 3 UART Data Frames for RS 232 and RS 485 1 7 OSI Layer 1 Referring to the OSI 7 layer model for network communication Layer 1 is the and Layer 2 Physical Link layer or hardware connection between sender and receiver Layer Coordination 2 s the Data Link Layer the next higher layer in the 7 layer hierarchy In the UEI SL 504 Synchronous Serial Communication module s the physical layer is implemented as an RS 232 RS 422 or RS 485 hardware link Software selection of the specific serial line topology is handled on the fly in the 504 by a single chip the EXAR SP506 Multi mode Serial Tranceiver The higher level synchronous communication functions associated with Layer 2 the Data Link Layer are handled by high level data protocols such as SDLC and HDLC running over the physical connections Copyright 2012 f Tel 508 921 4600 www ueidaq com Vers 4 5 United Electronic Industries ine Date November 2012 DNx SL 504 Chap1x fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter 1 Introduction 1 8 Whatis Synchronous Serial Communication as the name implies is bit or byte Synchronous oriented serial communicati
28. generally represents text that should be entered verbatim For instance it can represent a command as in the following example You can instruct users how to run setup using a command such as setup exe Text formatted in ixed typeface generally represents source code or other text that should be entered verbadim into the source code initialization or other file Examples of Manual Conventions Before plugging any I O connector into the Cube or RACKtangle be sure to remove power from all field wiring Failure to do so may cause severe damage to the equipment Usage of Terms Throughout this manual the term Cube refers to either a PowerDNA Cube product or to a PowerDNR RACKtangle rack mounted system whichever is applicable The term DNR is a specific reference to the RACKtangle DNA to the PowerDNA I O Cube and DNx to refer to both Copyright 2012 f Tel 508 921 4600 www ueidaq com Vers 4 5 United Electronic Industries Inc Date November 2012 DNx SL 504 Chap1x fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter1 3 Introduction 1 2 The SL 504 The DNA and DNR SL 504 layer is a 4 port serial communications interface Interface Cube RACKtangle I O chassis respectively Each port is independently Board configurable as RS 232 RS 485 RS 422 423 as well as set for synchronous or asynchronous communications Each port is fully isolated from the other three ports as well as from the Cube or RACKt
29. his SL 504 User Manual is organized as follows of Manual Introduction This section provides an overview of the SL 504 synchronous serial line communication interface features device architecture and connectivity Programming with the High Level API This chapter provides an overview of the how to create a session configure the session and format relevant data with the Framework API Programming with the Low Level API Describes low level API commands for configuring and using the SL 504 series layer for serial operating modes Appendix A Accessories This appendix provides a list of accessories available for use with the DNx SL 504 serial line communication interface board Index This is an alphabetical listing of the topics covered in this manual Copyright 2012 f Tel 508 921 4600 www ueidaq com Vers 4 5 UnitedrElecirenie Industries nos Date November 2012 DNx SL 504 Chap1x fm 1 DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter 1 Introduction Manual Conventions To help you get the most out of this manual and our products please note that we use the following conventions Tips are designed to highlight quick ways to get the job done or to reveal good ideas you might not discover on your own NOTE Notes alert you to important information CAUTION Caution advises you of precautions to take to avoid injury data loss and damage to your boards or a system crash Text formatted in bold typeface
30. ications The ports are based on the Exar SP506CM L series drivers and provide a wide variety of I O configurations The DNx SL 504 is supported by the UEIDAQ Framework providing a simple and complete software interface to all popular Windows programming languages and data acquisition control application packages such as LabVIEW MATLAB Simulink DASYLAB or any application that supports ActiveX or OPC servers Support is also provided for all popular non Windows operating systems including Linux VXworks QNX RTX INtime and more As with all UEI PowerDNA boards the DNx SL 504 can be operated in harsh environments and has been tested at 5g vibration 50g shock 40 to 85 C temperature and altitudes up to 70 000 feet Each board provides 350 Vis Isolation between channels and also between the board and its enclosure or any other installed boards as well as electro shock discharge ESD isolation Copyright 2012 f Tel 508 921 4600 www ueidaq com Vers 4 5 United Electronic Industries ine Date November 2012 DNx SL 504 Chap1x fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter 1 4 Introduction 1 3 Features The common features of the DNx SL 504 are listed below e Four 4 independent serial communication ports e Each port software configurable as RS 232 or RS 422 423 485 Completely independent bit rate settings for every port e 350V isolation between ports ports and circuitry 15kV ESD Compatible wi
31. ing UeiHDLCPortEncodingNRZIMark NRZI encoding invert state for 1 UeiHDLCPortEncodingNRZlSpace NRZI encoding invert state for 0 UeiHDLCPortEncodingBiphaseMark biphase encoding with DPLL UeiHDLCPortEncodingBiphaseSpace biphase encoding with DPLL UeiHDLCPortEncodingBiphaseLevel biphase encoding with DPLL UeiHDLCPortEncodingBiphaseDiff biphase encoding used with DPLL e CRC the method used to calculate the cyclic redundancy code UeiHDLCPortCRCNone CRC is not checked neither for transmit nor receive UeiHDLCPortCRCUser User responsible for inserting amp checking CRC UeiHDLCPortCRC16CCITT use 16 bit CCITT CRC x 15 x 12 x 5 1 UeiHDLCPortCRC16 16 bit polynomial UeiHDLCPortCRC32 32 bit polynomial TX clock source clock source used to synchronize transmitter UeiHDLCPortClockExternalPin Take clock from TxC pin default UeiHDLCPortClockBRG Take clock from baud rate generator UeiHDLCPortClockDPLL Take clock from DPLL divided by 32 UeiHDLCPortClockDPLLDiv8 Take clock from DPLL divided by 8 UeiHDLCPortClockDPLLDiv16 Take clock from DPLL divided by 16 e RX clock source clock source used to synchronize receiver UeiHDLCPortClockExternalPin Take clock from RxC pin default UeiHDLCPortClockBRG Take clock from baud rate generator UeiHDLCPortClockDPLL Take clock from DPLL divided by 32 UeiHDLCPortClockDPLLDiv8 Take clock from DPLL divided by 8 UeiHDLCPortClockDPLLDiv16 Take clock from DPLL divided by 16 Copyright 2012 Tel
32. link a frame delimiter is continuously transmitted on the link Using the standard NRZI encoding from bits to line levels this generates one of two continuous waveforms depending on the initial state as shown below 01111110 0111111001111110 01111110 0111111001111110 This is used by modems to synchronize their clocks using phase locked loops Some protocols allow the 0 bit at the end of a frame to be used as the start of the next frame s delimiter For half duplex or multi drop communication a receiver will see continuous idling 1 bits in the inter frame period when no transmitter is active To avoid detecting a false frame delimiter the receiver must recognize that it has occurred and restore the original data stream before the information is passed to higher layer protocols On synchronous links this is accomplished with bit stuffing Asynchronous Framing When using asynchronous serial communication as in standard RS 232 ports bits are sent in groups of 8 and bit stuffing becomes inconvenient In such situations byte or octet stuffing is used instead inserting a sequence for 7E hex or 7D hex when required If either appears an escape octet is sent followed by the original data octet with bit 5 inverted Asynchronous framing is not supported in the current version Copyright 2012 f Tel 508 921 4600 www ueidaq com Vers 4 5 United Electroni Industriesyine Date November
33. m Vers 4 5 te eee Date November 2012 DNx Al 504 Chap3 fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter3 27 Programming with the Low level API The first source is the baud rate generator which is a part of the Zilog Z16C32 chip It can be programmed to generate a clock of a certain frequency derived from the clock synthesizer chip There are three main clocks pre selected for operations 14 745600MHz 15 991223MHz and 20 002039MHz Firmware minimizes error between requested and actual clock by selecting the best combination of clock and divider The second source is the RxC pin RxC pin is a standard clock source for reception when encoding without embedded clock is used NRZ The RxC pin can be also a source of Tx clock The third source is a DPLL clock extracted from the data line transmission when encoding with embedded clock is used Biphase encoding SL504 HDLC FLAG DPLL DIV8 and SL504 HDLC FLAG DPLL DIV16 are used to select a DPLL divider lower than the standard one of 32 DPLL is used in the clocking scheme when RxD provides data without RxC In this case BRG1 is programmed as a clock source and RxC is recovered from RxD and used as RxC and optionally TxC clock DPLL mode in HCR is dependent on the encoding used hdlc crc mode defines CRC mode used with HDLC protocol define SL504 HDLC CRC NONE OL lt lt 0 CRC is not checked for transmit or receive define SL504 HDLC CRC USER 1L
34. nd or for receiver enable to DCD line User can also force transmitter and or receiver into disabled state if appropriate flags are added to the lt modeflags gt word physical applies to all modes of operation and selects the physical interface the SL 504 board uses to communicate with other devices define SL504 PHY RS232 1 RS 232 up to 230k baud define SL504 PHY RS485 2 RS 485 up to 4Mbit define SL504 PHY RS422 3 RS 422 multidrop define SL504 PHY V35 4 balanced current data and clock and unbalanced voltage DCD and CTS define SL504 PHY TERM 0x40 enable termination in RS 485 and RS 422 modes define SL504 PHY LOOP 0x80 enable loopback in the selected mode define SL504 PHY NOECHO 0x100 suppress echo in RS 422 423 modes For the above mode definitions i A e amp t Copyright 2012 Tel 508 921 4600 www ueidaq com Vers 4 5 United Electronic Industries Inc Date November 2012 DNx Al 504 Chap3 fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter3 25 Programming with the Low level API SL504 PHY TERM enables termination on RS 485 or RS 422 bus e SL504 PHY LOOP Sets Tx chip into loopback mode so all transmitted data is received by the receiver without a need fo
35. nd tears down links and manages each while it is operational Secondaries can transmit only if the primary grants permission The SDLC frame has 6 fields Flag Initiates and terminates error checking Address Contains the SDLC address of the secondary station source of the frame A primary is either a communication source or a destination elim inating the need to include the primary address Control e Information Frame I Carries upper layer and control information Sends and receives frame sequence numbers the poll final P F bit performs flow and error control The send sequence number defines the number of the next frame to be sent The receive sequence number pro vides the number of the frame to be received next The P F bit tells the primary station whether or not it requires an immediate response It is also used to tell a primary that the current frame is the last one in the current response Supervisory Frame S An S frame can request and suspend trans mission report on status and acknowledge receipt of frames S frames do not have information fields Unnumbered Frame U Used to initialize secondaries Some U frames have an information field e Data Contains path or ID information Frame Check Sequence FCS This is a CRC calculation remainder used to detect errors Copyright 2012 f Tel 508 921 4600 www ueidaq com Vers 4 5 United Electroni Industriesyine Date November 2012 DNx
36. ng web URL device class gt lt IP address Device Id Subsystem Channel list For PowerDNA and RACKtangle the device class is pdna For example the following resource string selects serial ports 0 2 3 on device 1 at IP address 192 168 100 2 pdna 192 168 100 2 Dev1 Com0 2 3 The SL 504 is programmed using the subsystem com to configure channels in asynchronous mode or hdlc to configure channels in HDLC mode 2 2 4 Asyncronous Use the method CreateSerialPort to configure one or more channel s in serial port asynchronous mode The following call configures the ports 0 and 1 of an SL 504 set as device 1 Configure session s ports slSession CreateSerialPort pdna 192 168 100 2 Dev1 Com0 1 UeiSerialModeRS232 UeiSerialBitsPerSecond57600 UeiSerialDataBits8 UeiSerialParityNone UeiSerialStopBits1l termination quc M H C SM RR HU v P rH Le r a ey Copyright 2012 f Tel 508 921 4600 www ueidaq com Vers 4 5 United Electronic Industries ine Date November 2012 DNx SL 504 Chap2x fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter2 17 Programming with the High Level API The string configures the following parameters Serial port mode The physical interface used to transmit serial bytes UeiSerialModeRS232 RS 232 UeiSerialModeRS485HalfDuplex RS 422 2 wires UeiSe
37. not to send more data until further notice REJ requests immediate retransmission starting with N R SREJ requests retransmission of only the frame N r U Frames U frames are used for link management but can also be used to transfer user data Codes bit fields indicate the type of U frame For more detailed information about HDLC its command and response repertoire basic operations and functional extensions refer to readily available resources such as wikipedia and similar communication reference material Note that the SL 504 provides only a means to send and receive frames but does not implement control part of HDLC SDLC protocol layer 3 quec M n Ue ccr i cc eme s cCUE Mec o amp o cu c i ea ae remm Copyright 2012 f Tel 508 921 4600 www ueidaq com Vers 4 5 United Electronic Industries ine Date November 2012 DNx SL 504 Chap1x fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter 1 12 Introduction 1 9 Architecture The architecture of the DNx SL 504 is illustrated in the block diagram shown in Figure 1 4 eas E abu l PONI N RS 232 485 Z16C32 Transceiver Scc l l P1 a RS 232 485 N 216C32 2 Transceiver y SCC a E N c 5 P2N 8 RS 232 485 Z16C32 D e i Transceiver V SCC a T 2 Br RS 232 485 216c32 i Transceiver SCC
38. number of bits before parity bit from 5 to 8 if 9 bitis selected it is inserted after parity bit 9 bit asynchronous mode sometimes used in multi drop protocols to distinguish between device address and device data async start number of start bits 0 is default means 1 bit async stop number of stop bits 20 is default means 1 bit async parity Selects whether to insert a parity bit after the data bits and define DQ SL504 PARITY NONE OL lt lt 0 none parity field is not populated define DQ SL504 PARITY EVEN 1L 0 1 if sum of data bits is even define DQ SL504 PARITY ODD 2L lt lt 0 1 if sum of data bits is odd define DQ SL504 PARITY SPACE 3L lt lt 0 always space constant 0 define DQ SL504 PARITY MARK 4L 0 always mark constant 1 Fields lt async_msglen gt watermark level defines message length and async tout timeout forces to transmit everything accumulated in ms are reserved for messaging and asynchronous event modes Configuration should be set for each channel regardless of whether it is used for Rx or Tx or both 3 3 4 Enabling The function DgAdv504Enable handle device chan mask is used to Operations enable and disable operations on the channel If the bit in the channel mask 1 channel number is one the channel is enabled If itis zero the channel is disabled
39. o the bottom of the Cube o o Open ENS Closed Figure 1 7 Diagram of DNA SL 504 Board Position Jumper Settings Dm UGNESEEOEGEDO O OE cO GE A NL MM c w PLC NUES cA CALCE c M On um EE LL LUN Wm m m k Copyright 2012 Tel 508 921 4600 www ueidaq com Vers 4 5 United Electronic Industries Inc Date November 2012 DNx SL 504 Chap1x fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter 2 16 Programming with the High Level API Chapter2 Programming with the High Level API This section describes how to control the DNx SL 504 using the UeiDaq Frame work High Level API UeiDaq Framework is object oriented and its objects can be manipulated in the same manner from different development environments such as Visual C Visual Basic or LabVIEW The following section focuses on the C API but the concept is the same no matter what programming language you use Please refer to the UeiDaq Framework User Manual for more information on use of other programming languages 2 4 Creating a The Session object controls all operations on your PowerDNx device Therefore Session the first task is to create a session object create a session object for input and a session object for output CUeiSession slSession 2 2 Configuring UeiDaq Framework uses resource strings to select which device subsystem the Resource and channels to use within a session The resource string syntax is similar to a Stri
40. on in which timing is controlled by an internal or Serial external clock Referring to the OSI 7 layer model of a network synchronous serial communications is classed as a Level 2 Data Link Layer Its function is to transfer data between network entities and also to correct errors that may occur in the Physical Layer Level 1 below Communica tion SDLC Protocol The first data link layer protocol based on synchronous bit oriented operation called Synchronous Data Link Control SDLC was developed by IBM in the mid 1970s for use in its Systems Network Architecture in which it was widely used IBM later submitted SDLC to various standards committees which eventually resulted in development of a modified SDLC called High Level Data Link Control HDLC protocol HDLC became the basis for development of several other protocols adopted as standards by the ISO CCITT IEEE and other agencies SDLC however remains the primary link layer protocol for SNA environments and WAN links even today SDLC can be used with a variety of link types and systems such as point to point and multipoint links half duplex and full duplex transmission and circuit Switched and packet switched networks SDLC identified two types of network nodes primary and secondary Primary nodes control operation of secondary nodes polling them in a predetermined order When polled a secondary can transmit if it has outgoing data to send The primary node sets up a
41. perating DMA waits to send 5 BUSY continues to send data to the transmitter The channel DMA is fetching information from the 4 INITG linked list or stopped while doing so The channel DMA has reached the end of the linked 3 EOL list there is no more data to transfer The channel DMA has finished sending current frame 2 EOB data 1 HAbort The channel stopped due to the firmware issued Abort 0 SAbort The channel stopped due to the Abort command The following status bits are useful in Receive DMA Register Bit Name Description of RDMR bit Firmware has issued a Start Continue command after 7 Cont loading next buffer address The channel DMA is reading next address in the linked 6 GLink list The channel is operating DMA waits to receive 5 BUSY continues to receive data from the receiver The channel DMA is fetching information from the 4 INITG linked list or stopped while doing so Copyright 2012 United Electronic Industries Inc Tel 508 921 4600 Date November 2012 Vers 4 5 DNx Al 504 Chap3 fm www ueidaq com 3 3 5 Aborting Transmission Copyright 2012 United Electronic Industries Inc DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter 3 Programming with the Low level API The channel DMA has reached the end of the linked 3 EOL list there are no more buffers to store data The channel DMA has finished receiving current frame data o
42. pinout for the SL 504 is provided below 21 2A 0202020808008080080 0 SSeS eee 62 1 e e e o e e o Hz 43 Pin signal Pin signal Pin signal 1 RESERVEDO1 22 GND CHO 43 RxC a 0 2 TxC b 0 23 TxC a 0 44 RxC b 0 3 DCD a 0 24 DCD b 0 45 GND CHO 4 RxD b 0 25 RxD a 0 46 RESERVED11 5 _TxD b 0 26 TxD a 0 47 CTS b 0 6 GND CH1 27 CTS a 0 48 RESERVED17 7 RxC b 1 28 RxC a 1 49 DCD b 1 8 TxC b 1 29 TxC a 1 50 DCD a 1 9 RxD b 1 30 RxD a 1 51 GND CH1 10 TxD b 1 31 TxD a 1 52 CTS a 1 11 RESERVED33 32 CTS b 1 53 RxC a 2 12 TxC b 2 33 TxC a 2 54 RxC b 2 13 DCD b 2 34 GND CH2 55 GND CH2 14 RxD b 2 35 RxD a 2 56 DCD a 2 15 TXD b 2 _ 36 TxD a 2 57 CTS b 2 16 GND CH3 l 37 CTS a 2 58 RESERVED49 17 RxC b 3 38 RxC a 3 59 DCD b 3 18 TxC b 3 39 TxC a 3 60 RESERVED55 19 DCD a 3 40 GND CH3 61 RxD a 3 20 TxD b 3 41 TxD a 3 62 RxD b 3 21 CTS a 3 42 CTS b 3 Figure 1 5 DNx SL 504 Connection Diagram Copyright 2012 United Electronic Industries Inc Date Novem Tel 508 921 4600 ber 2012 www ueidaq com Vers 4 5 DNx SL 504 Chap1x fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter 1 15 Introduction 1 12 Jumper This section briefly describes how to change jumper positions that indicate Settings for logical layer positioning in the uncommon case that you must physically swap Board layers on the PowerDNA I O Cube not PowerDNR RACKtangle
43. r an external dongle e SL504 PHY NOECHOs gt is used to disable the receiver in RS 422 mode while the transmitter transmits data on the bus Since this feature is implemented in the software it only works without queuing of transmit packets thus the depth of the transmit DMA FIFO becomes one frame hdlc flags define how to handle HDLC protocol define SL504 HDLC ABORT 7 0L 0 send 0x7 as an abort symbol define SL504 HDLC ABORT 15 1L lt lt 0 send Ox7fff as an abort symbol define SL504 HDLC FINISH UNDER 2L 0 Ji an underrun condition close the frame by adding CRC to it define SL504 HDLC FLAGS UNDER 3L 0 f im underrun condition start sending flags define SL504 HDLC SHARED ZEROES 1L 6 send idle flags with shared zeroes hdlc encod selects what type of encoding is used The most popular type of encoding is NRZ other types of encodings are rarely used define SL504 HDLC NRZ OL lt lt 0 NRZ encoding define SL504 HDLC NRZB 1L lt lt 0 Pa inverted NRZ encoding define SL504 HDLC NRZI 2L 0 NRZI encoding define SL504 HDLC NRZI MARK 3L 0 NRZI encoding invert state for 1 define SL504 HDLC NRZI SPACE 4L 0 NRZI encoding invert state for 0 define SL504 HDLC BIPHASE MARK 5L 0 df biphase encoding used with DPLL define SL504 HDLC BIPHASE SPACE 6L 0 2j biphase encoding used with DPLL
44. r frame is too long and the end of buffer is 2 EOB reached 1 HAbort The channel stopped due to the firmware issued Abort 0 SAbort The channel stopped due to the Abort command The following status bits are useful in Channel Command Status Register Bit Name Description of CCSR bit RCC FIFO Overflow should not occur if DMA is 15 RCCF Overflow working properly and frames are read on time RCC FIFO has data DMA takes care of emptying the 14 RCCF Avail FIFO 12 DPLL Sync DPLL is in sync with the input clock embedded in RxD 11 DPLL 2Miss DPLL has seen two consecutive missing clocks 10 DPLL 1Miss DPLL has seen a missing clock Finally to abort a HDLC frame transmission you can call int DqgAdv504AbortTx int hd int devn int channel uint32 status This function issues abort commands to the transmitter and clears all frames of the existing data The status returned is the content of Z16C32 TCSR register Tel 508 921 4600 Date November 2012 www ueidaq com Vers 4 5 DNx Al 504 Chap3 fm 33 A Accessories to J2 Copyright 2012 United Electronic Industries Inc DNA DNR SL 504 Synchronous Serial Line Communication Module Appendix A DNA CBL 62 This is a 62 conductor round shielded cable with 62 pin male D sub connectors The following cables and STP boards are available for the SL 504 layer on both ends It is made with round heavy shielded cable 2 5 ft 75
45. rialModeRS485FullDuplex RS 485 4 wires Bits per second The number of bits per second to transmit To set a custom baud for a serial port obtain a reference the session s channel then set the configuration in the relevant section For example in C UeiDaq SerialPort p SerialPort session GetChannel 0 p SetCustomSpeed 230400 set to 230400 baud Data bits The number of data bits per serial byte UeiSerialDataBits5 5 bits of data UeiSerialDataBits6 6 bits of data UeiSerialDataBits7 7 bits of data UeiSerialDataBits8 8 bits of data e Parity The parity used to verify data integrity UeiSerialParityNone No parity bit UeiSerialParityOdd parity bit set to 1 if number of bits set to 1 is odd UeiSerialParityEven parity bit set to 1 if number of bits set to 1 is even UeiSerialParityMark parity bit is always 1 UeiSerialParitySpace parity bit is always 0 Stop bits The number of stop bits sent at the end of each character UeiSerialStopBits1 1 stop bit UeiSerialStopBits1 5 1 5 stop bits UeiSerialStopBits2 2 stop bits Termination termination string that marks the end of transmission not used on SL 504 In addition you can set additional parameters using the channel object methods under LabVIEW use property node Termination resistors Select whether to enable or disable termination resistors enable termination resistor pPort EnableRxTerminationResistor true Echo suppression Select whether to s
46. ry station is aware that it cannot transmit when it has given permission to a secondary Asynchronous response mode is an HDLC addition for use with full duplex links It allows a secondary station to transmit at any time Asynchronous balance mode added the concept of a combined terminal both primary and secondary There are three basic types of HDLC frames I Information Frames S Supervisory Frames and U Unnumbered Frames I frames transport user data from the network layer combined with flow and error control information S frames do not have information fields but are used for flow and error control when no data is sent U frames are used for miscellaneous purposes such as link management and may contain an information field P F Bit Poll Final is a single bit with two names Poll when set by the primary station to get a response from a secondary and Final when set by a secondary station to indicate a response or the end of transmission Otherwise it is clear The bit is used as a token passed back and forth between stations Only one can exist at a time The secondary only sends a Final when it has received a poll from the primary The primary only sends a poll when it has received a Final from the secondary or after a timeout indicating a lost bit In normal response mode NRM possession of the token also grants the secondary permission to transmit The secondary sets the F bit in its last response frame and give
47. s Each port has independently programmable e Baud bit rate e HDLC format Short flag Idle character Encoding e Clocking scheme CRC Filtering Type e Preamble size and type quec Au M e d c sc HUNG J ue IO en uc pe c r C NEM ae ce memi Copyright 2012 f Tel 508 921 4600 www ueidaq com Vers 4 5 United Electronic Industries ine Date November 2012 DNx SL 504 Chap1x fm DNA DNR SL 504 Synchronous Serial Line Communication Module 1 11 Wiring amp Connectors Signals on DB 62 Connector Chapter1 14 Introduction The following signals are located at the DB 62 connector on the SL 504 module The 62 pin female D Sub connector on the SL 504 module is divided into four 9 pin serial ports as shown in the pinout of Figure 1 5 A user can connect four serial lines to this connector either through a custom made cable or by connecting to a DNA DNR STP 62 accessory panel see Appendix page 35 In the pinout of Figure 1 5 the following abbreviations are used Name 232 422 485 Description RS 422 485 TxD RxD single ended a b a b Transmit Receive Data pair CTS single ended Clear to send input DCD single ended Data Carrier Detect input TxC single ended a b Transmit Clock output RxC single ended a b Receive Clock input GND single ended Common Ground Table 1 2 Abbreviations for pinout with a high b low The
48. s or B C X m X Copyright 2012 Tel 508 921 4600 www ueidaq com Vers 4 5 United Electronic Industries Inc Date November 2012 DNx Al 504 Chap3 fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter3 28 Programming with the Low level API define SL504 HDLC FLT EA MS16 15L 1 Places bytes while MS 0 then byte with MS 1 then 16 bits as 2 bytes into RxFIFO if Ext Addr matches or B C The hdlc filter field contains an 8 bit filter address value if filtering is allowed in lt hdlc_f1t_mode gt HDLC protocol can operate with different preamble sizes defined in lt hdlc_prmb1_sz gt if preamble is selected in lt hdlc_preamble gt field define SL504 HDLC PRMBSZ 16 0L 0 16 bit preamble is used define SL504 HDLC PRMBSZ 32 1L lt lt 0 32 bit preamble is used define SL504 HDLC PRMBSZ 64 2L lt lt 0 64 bit preamble is used The HDLC preamble pattern is programmed in the ndlc preamble field and can be one of the following which is allowed by the protocol In most cases no preamble is used define SL504 HDLC PRMB NONE 0L 0 no preamble define SL504 HDLC PRMB ZERO 1L 0 all zeroes define SL504 HDLC PRMB
49. s up the token In the other modes ARM and ABM the P bit forces a response If no response to a P bit is received in a reasonable time the primary times out and sends P again Copyright 2012 f Tel 508 921 4600 www ueidaq com Vers 4 5 United Electroni Industriesyine Date November 2012 DNx SL 504 Chap1x fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter 1 11 Introduction The P F bit is the heart of the basic checkpoint retransmission scheme required by HDLC Whenever a station receives a P F bit it can assume that any frames sent before it transmitted the P F bit and not acknowledged will never arrive and so should be retransmitted N R Both and S frames contain a receive sequence number N R It provides a positive acknowledgement that N S numbers up to N R 1 have been received and indicates the N S value of the next frame it expects to receive I Frames user data l frames transport user data from the network layer and also include flow and error control information S Frames control S frames are primarily used for flow and error control S frames do not have information fields All S frames include a P F bit and a receive sequence number There is no difference between a command S frame and a response S frame The first 2 bits mean it is an S frame and identify its type RR RNR REJ or SREJ RR indicates the sender is ready to receive more data RNR indicates a request
50. sr Channel commmand status register uinti6 tcsr Transmit commmand status register uintl6 rcsr Receive commmand status register uint16 rsv10 uintl16 rsv11 uintl16 rsv12 SL504 INT STAT pSL504 INT STAT Copyright 2012 Tel 508 921 4600 www ueidaq com Vers 4 5 United Electronic Industries Inc Date November 2012 DNx Al 504 Chap3 fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter 3 Programming with the Low level API Most fields are either collected when Z16C32 receives or sends frames or read directly from the chip registers The following status bits are useful in the Transmit Command Status Register Bit Name Description of TCSR bit 7 PreSent Transmitter has finished sending preamble 6 IdleSent Transmitter has sent idle condition 5 AbortSent Transmitter has sent Abort 4 EOF Transmitter has sent end of frame 3 CRCSent Transmitter has sent CRC code 2 AllSent Last frame bit has gone out of transmitter Transmitter has encountered underrun condition 1 TxUnder starts sending idle character by default 0 TxEmpty TxFIFO is empty The following status bits are useful in the Transmit DMA Register Bit Name Description of TDMR bit Firmware has issued a Start Continue command after 7 Cont loading next buffer address The channel DMA is reading next address in the linked 6 GLink list The channel is o
51. t support ueidag com Web Site www ueidag com FTP Site ftp ftp ueidag com Product Disclaimer WARNING DO NOT USE PRODUCTS SOLD BY UNITED ELECTRONIC INDUSTRIES INC AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS Products sold by United Electronic Industries Inc are not authorized for use as critical components in life support devices or systems A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness Any attempt to purchase any United Electronic Industries Inc product for that purpose is null and void and United Electronic Industries Inc accepts no liability whatsoever in contract tort or otherwise whether or not resulting from our or our employees negligence or failure to detect an improper purchase Specifications in this document are subject to change without notice Check with UEI for current status DNA DNR SL 504 Synchronous Serial Line Communication Module Contents Table of Contents Chapter 1 Introduction uuulleleseeseeseeeeeee Ren 1 1 1 Organization of Manual llli nn 1 1 2 The SL 504 Interface Board 1 nee 3 1 3 run ETT 4 1 4 elect ac EEUU 4 1 5 Specification i ocu deed ARR RR x AI ue P au Row eR RUE ROC RIA oa Red ed 5 1 6 What is Serial Communication 0 00 0 6 1 7 OSI Layer 1 and Layer 2
52. th RS 422 networks when used in RS 485 mode e Half and full duplex support for RS 485 e Supports HDLC SDLC and asynchronous Protocols Tested to withstand 5g Vibration 50g Shock 40 to 85 C Temperature and Altitude up to 70 000 ft or 21 000 meters e Weight of 136 g or 4 79 oz for DNA SL 504 817 g or 28 8 oz with PPC5 e UEI Framework Software API may be used with all popular Windows programming languages and most real time operating systems such as RT Linux RTX or QNX and graphical applications such as LabVIEW MATLAB DASYLab and any application supporting ActiveX or OPC 1 4 Indicators A photo of the SL 504 unit is illustrated below The front panel has two LED indicators e RDY indicates that the layer is receiving power and operational e STS can be set by the user using the low level framework DNA bus connector RDY Leb STS LED DB 62 female 62 pin I O connector Figure 1 1 The DNA SL 504 Serial Layer Sea ea a a c i a U oM a aa a C a a a Y Copyright 2012 i Tel 508 921 4600 www ueidaq com Vers 4 5 United Electronic Industies Ine Date November 2012 DNx SL 504 Chap1x fm DNA DNR SL 504 Synchronous Serial Line Communication Module Introduction Chapter 1 1 5 Specification The technical specification for the SL 504 is provided in the table below i
53. tied to port 2 and send a frame of 128 bytes to the HDLC port Create a writer and link it to the session s stream port 2 writer new CUeiSerialWriter session GetDataStream 2 store 128 bytes that we want to write out unsigned char bytes 128 memset bytes 0x34 128 write 128 byte numBytesWritten contains number of bytes actually sent writer Write 128 bytes amp numBytesWritten 2 6 Cleaning up The session object will clean itself up when it goes out of scope or when it is the Session destroyed To reuse the object with a different set of channels or parameters you can manually clean up the session as follows clean up the sessions slSession CleanUp CUm EAE TUNE MEC E C ee c i Copyright 2012 Tel 508 921 4600 www ueidaq com Vers 4 5 United Electronic Industries Inc Date November 2012 DNx SL 504 Chap2x fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter3 22 Programming with the Low level API Chapter 3 Programming with the Low level API This chapter illustrates how to program the PowerDNA cube using the low level API The low level API offers direct access to PowerDNA DAQBios protocol and also allows you to access device registers directly However we recommend that when possible you use the UeiDaq Framework High Level API because it is easier to use You should need to use the low level API only if you are using an operating system other than Windows For addi
54. tion for HDLC or RawSync modes uint32 hdlc flags additional synchronous mode flags uint32 hdlc encod encoding type NRZ MII etc uint32 hdlc baud RxC or TxC clock rate in baud uint32 hdlc clk src Which clock to synchronize Tx from uint32 hdlc crc mode None CRC 16 32 CCITT user supplied or automatic uint32 hdlc flt mode Filter type uint32 hdlc filter HDLC address filter value 8 bits uint32 hdlc preamble preamble uint32 hdlc prmbl sz size of preamble uint32 hdlc idle ch idle character default 0x7E fill the following section for asynchronous mode uint32 async baud baud rate uint32 async char sz 5 to 8 bits before parity bit Sth bit is after parity uint32 async_start number of start bits 0 is default means 1 bit uint32 async stop number of stop bits 0 is default means 1 bit uint32 async parity parity used uint32 async msglen watermark level defines msg len uint32 async tout timeout forces to transmit everything accumulated in ms SL504 SETCFG pSL504 SETCFG This structure is used for all modes of operation albeit only a part of it is valid for each mode Copyright 2012 Tel 508 921 4600 www ueidaq com Vers 4 5 United Electronic Industries Inc Date November 2012 DNx Al 504 Chap3 fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter3 24 Programming with the Low level AP
55. tional information about low level programming of the SL 504 please refer to the PowerDNA API Reference Manual document under Start Programs UEI PowerDNA Documentation 3 4 HDLC SDLC The HDLC protocol was developed in 1970s to facilitate synchronous transmis Mode sion of data packets or frames over the RS 485 or RS 232 physical interface Since this is a synchronous protocol either clock amp data lines or an encoding with embedded clock can be used effectively cutting bandwidth by half for the same baud rate When an HDLC transmitter is enabled it constantly sends Idle characters on the bus When a transmitter needs to start transmission it sends a Flag sequence Ox7E Six continuous ones on the bus signals a receiver that this is a start of the frame A frame is a group of sequential characters ending with CRC to verify its correctness While sending a frame an HDLC transmitter continually checks whether any sequence of data bits could look like a Flag to the receiver It does this without regard for character boundaries Whenever the data presented to a transmitter includes a zero followed by five ones the transmitter adds an extra zero bit after a fifth one bit The receiver monitors the serial data stream as well and removes a trailing zero for any sequence that looks like 0111110 regardless of character boundaries HDLC protocol matches up well with NRZI Space encoding to ensure data trans missions
56. transition at a clock boundary if the bit being transmitted is a logical 1 and does not have a transition if the bit being transmitted is a logical 0 One is represented by a transition of the physical level Zero has no transition Biphase encoding does not require a synchronous clock to be used since the clock is embedded into the data signal Biphase encoding is a code in which data and clock signals are combined to form a single 2 level self synchronizing data stream It is a differential encoding using the presence or absence of transitions to indicate logical value A transition is guaranteed at least once every bit allowing the receiving device to perform clock recovery The Z16C32 chip uses an integrated digital phase lock loop DPLL to recover clock and uses it instead of external clock The symbol rate is twice the bit rate of the NRZ signal Each bit period is divided into two half periods clock and data The clock half period always begins with a transition from low to high or from high to low The data half period makes a transition for one value and no transition for the other value Differential Manchester is self synchronizing since there is a change in the signal at least every two bits It is not necessary to know the polarity of the sent signal since the information is not kept in the actual values of the voltage but in their change In other words it does not matter whether a logical 1 or 0 is received but only whether the
57. uppress echo in half duplex mode Disable echo pPort gt EnableHDEchoSuppression true Error reporting Select whether to report errors such as framing or par ity errors Enable error reporting pPort gt EnableErrorReporting true Sane a a I a a a a ea i a ey Copyright 2012 f Tel 508 921 4600 www ueidaq com Vers 4 5 United Electronic Industries ine Date November 2012 DNx SL 504 Chap2x fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter 2 18 Programming with the High Level API 2 2 2 HDLC Port Use the method CreateHDLCPort to to configure one or more channel s in asynchronous mode The following call configures ports 2 and 3 of a SL 504 set as device 1 Configure session s ports hdlcSession CreateHDLCPort pdna 192 168 100 2 Dev1 hd1lc2 3 UeiHDLCPortRS232 100000 UeiHDLCPortEncodingNRZ UeiHDLCPortCRCNone UeiHDLCPortClockBRG UeiHDLCPortClockExternal It configures the following parameters Physical interface the physical interface used to transmit serial bytes UeiHDLCPortRS232 RS 232 UeiHDLCPortRS422 RS 422 2 wires UeiHDLCPortRS485 RS 485 4 wires UeiHDLCPortV35 V35 Bits per second the number of bits per second transmitted of the syn chronous port Encoding the method used to encode bits over synchronous serial line UeiHDLCPortEncodingNRZ NRZ encoding UeiHDLCPortEncodingNRZB inverted NRZ encoding UeiHDLCPortEncodingNRZI NRZI encod
58. x SL 504 Chap1x fm DNA DNR SL 504 Synchronous Serial Line Communication Module Chapter 1 13 Introduction 216C32 IUSC Integrated Universal Serial Controller The Z16832 IUSC Integrated Universal Serial Controller is a multi protocol data communications device with on chip dual channel DMA Integration of a high speed serial data comm channel with high performance DMA affords a higher data throughput than can be achieved with discrete components The Z16C32 chip manufactured by Zilog is software configurable to satisfy a wide variety of serial communications applications The high speed data rate and multi protocol support make it ideal for today s application and speed requirements The chip offers many advanced functions in an integrated design such as two baud rate generators a digital phase locked loop character counters and 32 byte FIFOs for both receiver and transmitter The IUSC handles asynchronous formats and synchronous bit oriented formats such as HDLC This device supports virtually any serial data transfer application The chip can generate and check CRC in any synchronous mode Complete access to the CRC value allows system software to resend or manipulate the CRC as needed in various applications 1 10 Module Using the RS 232 or RS 485 standard the controller is capable of Capabilities communicating at speeds of 256Kbaud for RS 232 and 4Mbaud for RS 485 When in RS 485 mode the SL 504 is also compatible with RS 422 network
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