SiP12116 Reference Board User Manual for SiP12116 (3 A)
Contents
1. l PK lout 9 5 x RIPPLE_MAX 2 Lx lour t 9 5 x IRippLe_ max 2 2 Vex Vout Where l pk is the peak inductor current IrippLe max is the maximum current ripple lour is the maximum output current and VPK is the output voltage plus the rise on load release Cour MIN Input Capacitance In order to keep the design compact and minimize parasitic elements ceramic capacitors will be chosen The initial requirement for the input capacitance is decided by the maximum input voltage 15 V in this case however a 35 V rated capacitor will be chosen of the X7R variety In order to determine the minimum capacitance the input voltage ripple needs to be specified Vcinpp lt 150 mV is a suitable starting point This magnitude is determined by the final application specification The input current needs to be determined for the lowest operating input voltage OUT IcIN RMS Vu x Wout x Vin Vout The minimum input capacitance can then be found DC 1 DC VcINPP X fgw Snubber Provision has been made for a snubber on the underside of the board which the user might need to consider populating if a higher input voltage is required LAYOUT CONSIDERATIONS The SiP12116 offers the designer a compact buck regulator solution If the below layout recommendations are followed the same layout can be used to cover a wide range of output currents and voltages without any changes to the board design and only minor ch2. 20 crow MSHAY Cr T CF 002 455ko oowoo vishy pe F w ik cRowoaoa2a9KrKED vsa pe o ms ssm IHLP2020ZER R3MOI vishy po f tif oto ran Vs O Pr oo asa ooo MISMA Ce r F w e CROW0402249KEKED vsa Ca 1 F oo we crown MSHAY a a aae oe OOo gt 902006 vo pas 2 me enw 2828342 TECONNEOTVTY Note Only needed for reference board Revision 03 Sep 14 6 Document Number 63419 For technical questions contact powerictechsupport vishay com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS SET FORTH AT www vishay com doc 91000
3. VISHAY w www vishay com SiP12116 Vishay Siliconix Reference Board User Manual for SiP12116 3 A PRODUCT SUMMARY Input Voltage Range Output Voltage range Operating Frequency Continuous Output Current Package DESCRIPTION The SiP12116 is a high frequency current mode constant on time CM COT synchronous buck regulator with integrated high side and low side power MOSFETs The SiP12116 is capable of 3 A continuous current This regulator provides an adjustable output voltage which in standard setup can output 5 V down to 0 6 V to accommodate a variety of applications including computing consumer electronics telecom and industrial The CM COT architecture delivers ultra fast transient response with minimum output capacitance and tight ripple regulation at very light load The parts are stable with any capacitor type and no ESR network is required for loop stability The regulator integrates a full protection feature set it also has UVLO for the input rail and an internal soft start The SiP12116 is available in lead Pb free power enhanced 3 mm x 3 mm DFN 10 package SPECIFICATIONS This reference board allows the end user to evaluate the SiP12116 chip for its features and all functionalities It can also be a reference design for a user s application ORDERING INFORMATION BOARD PART NUMBER MAX OUTPUT CURRENT SiP12116DB 3 A Revision 03 Sep 14 FEATURES e 4 5 V to 15 V input voltage e Adj
4. anges to the component values in the schematic The reference design has a majority of the components placed on the top layer This allows for easy assembly and straightforward layout Figure 1 outlines the pointers for the layout considerations and the explanations follow Revision 03 Sep 14 3 10 11 SiP12116 Vishay Siliconix Fig 1 Reference Design Pointers Place input ceramic capacitors close to the voltage input pins with a small 10 nF 100 nF placed as close as the design rules will allow This will help reduce the size of the input high frequency current loop and consequently reduce the high frequency ripple noise seen at the input and the LX node Place the setup and control passive devices logically around the IC with the intention of placing a quiet ground plane beneath them on a secondary layer lt is advisable to use ceramic capacitors at the output to reduce impedance Place these as close to the IC Penp and output voltage node as design will allow Place a small 10 nF 100 nF ceramic capacitor closest to the IC and inductor loop The loop between LX Vour and the IC GND should be as compact as possible This will lower series resistance and also make the current loop smaller enabling the high frequency response of the output capacitors to take effect The output impedance should be small when high current is required use high current traces multiple layers can be used with
5. been applied to Vin enabling the device Bootstrap Circuit A bootstrap capacitor of 100 nF will be sufficient for this circuit with a switching frequency of 600 kHz A series resistor has been added in order to slow down the low side switch and minimize overshoot without adding a snubber This is user adjustable This can be reduced to OR to improve efficiency Vpp Decoupling The Vpp pin will need to be decoupled in order to provide a stable voltage internally and externally The value for this capacitor is recommended as gt 1 pF Current Limit The current limit is set internally to 4 8 A This will include the output current plus half of the ripple current If the output current is greater than this value the current limit will be activated Document Number 63419 For technical questions contact powerictechsupport vishay com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS SET FORTH AT www vishay com doc 91000 Gy VISHAY www vishay com Output Capacitance The output capacitance will be determined by the ripple voltage requirement Voltage mode COT topology can work with very small values of capacitor ESR however a ripple injection network will also be required for stable operation The overall capacitance needs to be calculated next The following equations are used to calculate the size needed to meet a transient load response
6. ded simply change the value of Vour and solve for R3 based on the following formula Vout VFB VfB Where Veg is 0 6 V for the SiP12116 Output Ripple Voltage R3 R4 x Output ripple voltage is measured with a tip and barrel measurement across Cour Typically output ripple voltage is set to 3 to 5 of the output voltage but an all ceramic output solution can bring output ripple voltage to a much lower level since the ESR of ceramics is very small If ceramics or a combination of ceramics and bulk capacitors are used it may be necessary to add a voltage injection network Inductor Selection The choice of inductor is specific to each application and quickly determined with the following equations Vout Vin MAX X sw a Vin Vout X ton lout max X k t on Where k is a percentage of maximum output inductor ripple current required The designer can quickly make a choice if the ripple percentage is already decided based on the system design it should be noted that the SiP12116 uses an internal current sense mechanism which translates as the voltage ripple component The SiP12116 requires a Revision 03 Sep 14 2 SiP12116 Vishay Siliconix reasonable ripple current we recommend around 50 as a start point Other than the inductance the DCR and saturation current parameters are key values The DCR causes an I R loss which will decrease the system efficiency and generate heat The saturation current ha
7. many vias if the design allows Use many vias when multiple layers are involved This will have the effect of lowering the resistance between layers and reducing the via inductance of the PCB nets The quiet Agnp should be connected to the Penp plane near to the input GND at one connection only of at least 1 mm width Panp Can be used on internal layers if the resistance of the PCB is to be small this will also help remove heat Use extra vias if needed but be mindful to allow a path between the vias A quiet plane should be employed for the Acnp this is placed under the small signal passives This can be placed on multiple layers if needed for heat removal The LX copper can also be used on multiple layers use a number of vias The copper area beneath the inductor has been removed on all layers in this design to reduce the inductive coupling that occurs between the inductor and the GND trace No other voltage planes should be placed under this area Document Number 63419 For technical questions contact powerictechsupportOvishay com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS SET FORTH AT www vishay com doc 91000 Gy l VISHAY _ O Z o O y Si1216 www vishay com Vishay Siliconix PCB LAYOUT Fig 2 Top Layer Fig 4 Inner Layer 2 Fig 3 Inner Layer 1 Fig 5 Bottom Layer Revision 03 Sep 14 4 Docu
8. ment Number 63419 For technical questions contact powerictechsupport vishay com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS SET FORTH AT www vishay com doc 91000 ay VISHAY SiP1 21 16 www vishay com aa u Vishay Siliconix SCHEMATIC N ze oO O TN 0 A TE E Ka om D amp S ir EE E Cad gt 5 jhe 8 8 0p m ag EIR 3 0 e m gt 00 N cO l 5 3 32 fk O gt e AND ano S _ 3 AND 0 a o D N gt x LO O 035 a aa LO X SES E I i _ Oe E 5 3 N N T 8 x IIZ N QU ES o 8 a x N N S oO cO O A E Revision 03 Sep 14 5 Document Number 63419 For technical questions contact powerictechsupport vishay com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS SET FORTH AT www vishay com doc 91000 Ty VISHHAy _ SiP1216 www vishay com Vishay Siliconix BILL OF MATERIAL V 12 V Vout 3 3 V few 600 kHz PCB ITEM REFERENCE FOOTPRINT VALUE VOLTAGE PART NUMBER MANUFACTURER a Gre o ow 35V oocom KEMEr 3 CG 0 TF ov CO402C1OSMBPACTU KEMT Pas 002 TOOnF 35V CGazeaxreivicaxosoas Vishay pe e w
9. s to be higher than the maximum output current plus 1 2 the ripple current In over current condition the inductor current may be very high All this needs to be considered when selecting the inductor On this board Vishay IHLP series inductors are used to meet cost requirement and high efficiency a part that utilizes a material that has incredible saturation levels compared to competing products Output Capacitor Selection Voltage rating ESR transient response overall PCB area and cost are requirements for selecting output capacitors The types of capacitors and there general advantages and disadvantages are covered next Electrolytic have high ESR dry out over time so ripple current rating must be examined and have slower transient response but are fairly inexpensive for the amount of overall capacitance Tantalums can come in low ESR varieties and high capacitance value for its overall size but they fail short when damaged and also have slower transient response Ceramics have very low ESR fast transient response and overall small size but come in low capacitance values compared to the others above A combination of technology is sensible Enable Pin Voltage The ENL pin will need to be set to enable the part This pin accepts an input voltage up to 5 V On the reference design the pin has a voltage divider from Vin There is also a jumper P3 which shorts the pin to GND this can be removed when a suitable voltage has
10. ustable output voltage down to 0 6 V e 3 Acontinuous output current e Operational frequency 600 kHz e 95 peak efficiency e Stable with any capacitor No external ESR network required e Ultrafast transient response e Current mode constant on time e Power saving scheme for increased light load efficiency e 2 accuracy Of Vout setting e Cycle by cycle current limit e Fully protected with OTP SCP UVP OVP e Pcoop indicator e 40 C to 125 C operating junction temperature APPLICATIONS e Point of load regulation for low power processors network processors DSPs FPGAs and ASICs e Low voltage distributed power architectures with 5 V or 12 V rails e Computing broadband networking LAN WAN optical test and measurement e A V high density cards storage DSL STB DVR DTV industrial PC CONNECTION AND SIGNAL TEST POINTS Power Sockets Vin GND P1 input voltage source with Vin to be positive Connect to a voltage source SiP12116 3 V to 15 V Vout GND P2 output voltage with Vour to be positive Connect to a load that draws no more than SiP12116 3A SELECTION JUMPERS Enable P3 this needs a jumper in place to disable the part When the jumper is removed the part will enable It is advisable to apply Vin and then enable the part SIGNALS AND TEST LEADS Input Voltage Sense Vin sense GNDin_ sense P6 this allows the user to measure the voltage at the input of the regulator and remove an
11. y losses generated due to the connections from the measurement This can also be used by a power source with sense Capability Document Number 63419 For technical questions contact powerictechsupport vishay com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS SET FORTH AT www vishay com doc 91000 Gy VISHAY www vishay com Output Voltage Sense Vout sense GNDout sense P5 this allows the user to measure the voltage at the output of the regulator and remove any losses generated due to the connections from the measurement This can also be used by an active load with sense capability Power Good Indication PGD P4 is an open drain output and is pulled up with a 10 KQ resistor to Vin When Veg is within 50 percent of the set voltage this pin will go HI to indicate the output is okay POWER UP PROCEDURE To turn on the reference board apply 12 V to ViN with the P3 jumper is in position this disables the part To enable the part remove P3 a voltage can now be observed at the output Note e Note When applying higher than 12 V to the input it is reasonable to install a RC snubber from LX to GND There are place holders on the reference board R7 and C10 for the snubber Values of 10 Q and 1 nF are a reasonable starting point ADJUSTMENTS TO THE REFERENCE BOARD Output Voltage Adjustment If a different output voltage is nee
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