User Manual for C²I² Systems 8-Channel Serial I/O PMC
Contents
1. Unimplemented Base Address Register Unimplemented Base Address Register Unimplemented Base Address Register Reserved 0x38 Max Latency 0x00 Min Grant 0x00 Interrupt Pin 0x01 Interrupt Line The location of the configuration registers is defined by the host board The host board assigns a specific address line to the module interface by connecting it to the IDSEL pin on the PMC interface To determine the configuration registers locations refer to the manual of the host board CCII LCP 6 MAN 003 2003 10 29 Issue 1 1 WALCPITECHIMANICLCMANOS WPD Page 3 of 26 3 3 PCI Interrupts The 8 Channel Serial O PMC Adapter supports interrupts on the INTA pin only This is reflected in the Interrupt Pin Register of the Configuration Space as defined in 3 2 3 4 PMC Connectors The 8 Channel Serial I O PMC Adapter is fitted with two connectors P11 and P12 to implement the 32 bit PMC interface The board may be fitted with a either connector P14 required for back plane connection to the interface signals or the front panel connector J2 The front and rear panel configurations are shown in Figure 2 and Figure 3 respectively P11 P12 Figure 2 Front panel I O Configuration P14 P11 P12 Figure 3 Rear Panel I O Configuration COMLCP MANIO03 7008 10 26 WALCPITECHIMANICLCMANOS WPD Page 4 of 26 3 5 PMC Pin Assignments The 8 Channel Serial I O PMC Adapter has the following PMC connections2. O Atleast one byte is written to the transmit FIFO or transmit holding register 12 Transmitter holding register is empty indicating that the UART is ready to accept a new character If the THRE interrupt is enabled when THRE is set to 1 an interrupt is generated THRE is set to 1 when the contents of the transmitter holding register are transferred to the transmitter shift register LSR 6 O When either the transmitter holding register or the transmitter shift register contains a data character 1 Transmitter holding register and the transmitter shift register are both empty LSR 7 O In the 16C450 this bit is always reset to O 1 In the FIFO mode at least one parity framing or break error in the FIFO It is cleared when the microprocessor reads the LSR and there are no subsequent errors in the FIFO Modem Status Register MSR The modem status register is an 8 bit register that provides information about the current state of the control lines from the modem data set or peripheral device to the Host Additionally four bits of this register provide CCII LCP 6 MAN 003 2003 10 29 Issue 1 1 WALCPITECHIMANICLCMANOS WPD Page 20 of 26 4 4 10 change information when input from the modem Changes State the appropriate bit is set to 1 All four bits are reset to 0 when the Host reads the modem status register MSR 0 O No change to CTS input 1 Indicates that the CTS input has changed state since the
3. CKT NO 6 pas NA 628B O CKT NO B3 CKT NO 120 CKT NO 62 O 3 120 CKT NO 32 T 2 M5x0 9 8 60 E 3 2 N ais JE METRIC FINE SCREW THREADS Figure 5 MOLEX Connector Pin Out Issue 1 1 2003 10 29 CCII LCP 6 MAN 003 e N o wt N o D A W LCP TECH MAN CLCMANO3 WPD Figure 6 MOLEX Connector Pin Out Detail WALCPITECHIMANICLCMANO3 WPD Page 25 of 26 A 2 Ordering Information J2 the front panel connector on the PMC adapter is a shielded right angle connector manufactured by MOLEX A mating connector is supplied with the PMC adapter However should the need arise to obtain more mating connectors the ordering information is given below Plug Assembly Mating Connector Molex Part No 55032 1200 Cover Assembly Mating Connector Molex Part No 58423 1200 Threaded Screw Mating Connector Molex Part No 59811 0000 Above parts obtainable from below Agents Arrow Altech Distribution 27 21 555 1884 Email info arrow altech co za www arrow altech co za Avnet Kopp 27 21 689 4141 Email sales avnet co za www avnet co za The ordering information for the required ribbon cable is as follows 1mm Pitch Ribbon Cable 50Way Part Number CABFAWG2850M Above parts obtainable from below Agent Component Sources 27 11 314 6844 Email info componentsources co za www componentsources co za CCII LCP 6 MAN 003 2003 10 29 Issue 1 1 WALCPITECHIMANICLCMANOS
4. 4 4 3 UART Register Description Transmitter Holding Register THR The transmitter section consists of a transmitter holding register THR and a transmitter shift register TSR The THR is actually a 16 byte FIFO Transmitter section control is a function of the UART line control register The UART THR receives data off the internal data bus and when the shift register is idle moves itinto the TSR The TSR serializes the data and outputs it at TX In the 160450 mode if the THR is empty and the transmitter holding register empty THRE interrupt is enabled IER 1 1 an interrupt is generated This interrupt is cleared when a character is loaded into the register In the FIFO mode the interrupts are generated based on the control setup in the FIFO control register Receive Holding Register RHR The receiver section of the UART consists of a receiver shift register RSR and a receiver Holding register RHR The RHR is actually a 16 byte FIFO Timing to receive holding register is supplied by the 16x receiver clock Receiver section control is a function of the UART line control register The UART RHR receives serial data from RX The RSR then concatenates the data and moves it into the RHR FIFO In the 16C450 mode when a character is placed in the receiver holding register and the received data available interrupt is enabled IER O 1 an interrupt is generated This interrupt is cleared when the data is read out of the receiver holding
5. 14 44 5 FIFO Control Register FOR s ssa gach ener pb EPPLeLL vies EY et SE ALA seek SA dE 16 4 4 6 Line Control Register LCR cccccccs uh 17 4 4 7 Modem Control Register MCR 0000 cette teen tees 18 4 4 8 Line Status Register LSR 2 0 0 0 ccc eee 19 4 4 9 Modem Status Register MSR 00 c cect tte 20 4 4 10 Scratch Pad Register SPR 0 000 cect teen eee 21 4 4 41 Programmable Baud Rate Generator 20 00 eect ees 22 4 4 12 FIFO Interrupt Mode Operation 0 000 cect eee eee 22 4 4 13 Register Reset Conditions 2 0 ccc hen 23 APPENdIX A 2 53 ort Vice Lot A A a Ne BOO Mc Maya Bauska cs e Riad kun ee vee ER 24 MOLEX Connector Pin Locations and Ordering Information 0000 c cece eee eens 24 CCII LCP 6 MAN 003 2003 10 29 Issue 1 1 WALCPITECHIMANICLCMANOS WPD Page iv of v BIST CCII CD CS CTS DSR DTR FIFO y o INT IRQ LSB MSB PCI PMC RI RTS RX TX UART Abbreviations and Acronyms Built In Self Test Register CCII Systems Pty LTD Carrier Detect Chip Select Clear to Send Data Set Ready Data Terminal Ready First In First Out memory structure Input Output Interrupt Interrupt Request Least Significant Bit Most Significant Bit Peripheral Component Interconnect PCI Mezzanine Card Ring Indicator Request To Send Receive Transmit Universal Asynchronous Receiver Transmitter CCII LCP 6 MAN 003
6. CT Systems CCII Systems Pty Ltd Registration No 1990 005058 07 Communications Computer Intelligence Integration g User Manual for C Systems 8 Channel Serial I O PMC Adapter C Systems Document No CCII LCP 6 MAN 003 Document Issue Issue Date 2003 10 29 Print Date 2003 10 29 File Name WALCPITECHIMANICLCMANOS WPD Distribution List No C4 Systems The copyright of this document is the property of C2l Systems The document is issued for the sole purpose for which it is supplied on the express terms that it may not be copied in whole or part used by or disclosed to others except as authorised in writing by C I Systems Document prepared by and for C I Systems Cape Town Signature Sheet Completed by Project Engineer LCP C l Systems Accepted b penn lt gt ae tww io t S US DE Comm Project Manager LCP C P Systems 10 9 Y Keuge Quali surance RepYesentative e B d 2 Systems CCII LCP 6 MAN 003 2003 10 29 Do isse 11 W LCP TECH MAN CLCMANO3 WPD Amendment History Updated to new template 2003 07 16 Poa cd 1 1 Added Ordering Information and Part Number of the Molex 2003 10 29 CCII LCP 6 ECP 009 Front Panel Connector Mating Connector and Ribbon Cable CCII LCP 6 MAN 003 2003 10 29 Issue 1 1 WALCPITECHIMANICLCMANOS WPD Page iii of v Contents 1 Introduction and Scope exu psc te ahaa QUERN EE Ee vid CE Ea ees Rees E LE 1 1 1 SCOPE PE C IL
7. UART E Read FIFO UART E Write FIFO UART channel F registers UART F Read FIFO UART F Write FIFO UART channel G registers 16C550 compatible 64 bytes of RX FIFO 64 bytes of TX FIFO Read Only Write Only 16C550 compatible 64 bytes of RX FIFO 64 bytes of TX FIFO Read Only Write Only 16C550 compatible 64 bytes of RX FIFO 64 bytes of TX FIFO Read Only Write Only 16C550 compatible Read Only Write Only UART G Read FIFO UART G Write FIFO 64 bytes of RX FIFO 64 bytes of TX FIFO Read Only 64 bytes of RX FIFO Write Only 64 bytes of TX FIFO OxE00 OxE07 OxF00 OxF00 UART channel H registers UART H Read FIFO UART H Write FIFO CCII LCP 6 MAN 003 W LCP TECH MAN CLCMANO3 WPD 2003 10 29 Issue 1 1 Page 11 of 26 The UART channel configuration registers which are 16C550 compatible are given in the table below LCR 7 0 LCR 7 1 Base RBR THR DLL Receiver Buffer Transmit Holding Divisor Latch LSB Base 1 IER DLM Interrupt Enable Divisor Latch MSB Base 2 IIR FCR IIR FCR Interrupt FIFO Control Interrupt FIFO Control Identification Identification Base 3 LCR Line Control Base 4 MCR Modem Control Base 5 LSR LSR Line Status Line Status NOT USED NOYUSED Base 6 MSR MSR Modem Status Modem Status Base 7 SPR Scratch Pad CCII LCP 6 MAN 003 2003 10 29 Issue 1 1 WALCPITECHIMANICLCMANOS WPD Page 12 of 26 44 4 4 1 4 4 2
8. WPD Page 26 of 26
9. a character into THR register or reading IIR register if source of interrupt Modem Status Change Reading MSR register will clear this interrupt IIR 3 O In the 16C450 mode In FIFO mode this bit is set along with IIR 2 to indicate that a time out interrupt is pending CCII LCP 6 MAN 003 2003 10 29 Issue 1 1 WALCPITECHIMANICLCMANOS WPD Page 14 of 26 IIR 4 This bit is not used always reset at 0 IIR 5 O 16C450 550 mode 16 byte FIFO mode 1 Enhance FIFO mode 64 byte FIFO mode enabled IIR 6 7 0 1 In the 16C450 mode When FCR 0 is set CCII LCP 6 MAN 003 2003 10 29 Issue 1 1 WALCPITECHIMANICLCMANOS WPD Page 15 of 26 4 4 5 FIFO Control Register FCR The FIFO control register FCR is a write only register The FCR enables and clears the FIFO sets receive FIFO trigger level and selects the type of DMA signaling FCR 0 0 1 16C450 mode disables the transmitter and receiver FIFO Enables the transmitter and receiver FIFO This bit must be set to 1 when other FCR bits are written to or they are not programmed Changing this bit clears the FIFO FCR 1 O Normal operation 1 Clears all bytes in the receiver FIFO and resets its counter logic to O The shift register is not cleared The 1 that is written to this bit position is self clearing FCR 2 0 1 Normal operation Clears all bytes in the transmit FIFO and resets its counter logic to 0 The shift re
10. ease neal acme ee ete a see aden 1 1 2 Introduction 2 pese Ohne ee IE oe eee Pees Bho ate eae Hanh eee ee Pad 1 1 3 System Overview 0 nee nee eee 1 2 Applicable and Reference Documents 000 0 eee eee 2 2 1 Applicable Documents a a a RO eee e hn 2 2 2 Reference Documents 0 0 cece ee eae 2 2 3 SPECINCALI OMS cR EET 2 9 PMG PGI Inlerace sono ns sr tetendit GEER dra uei tb ien e Sa ra 3 3 1 OVEIVIOW DEC m 3 3 2 Gonfig ratlon Space esee Pani E MERERETUR ala ao TODAS PS aa ER Dae Dec Ex 3 3 3 POL IMemUpis ras oct eodeni QOEM SERO TEE eu pet CY Rcd CUR I EA EI LUE 4 3 4 PMGOSGORIOTSCIO S Saiar veiut Lala Tas sad a we stes Etsi Gy Pic pa Meer REIR OR ME RU Ed ern dica 4 3 5 PMG Pin Assignments RIMREREEEEERRUREMUEEEREEMRBu ee A GLa de MATO REM ES 5 4 Serial Interface codo bosser eor o Tap UP E Coens PESE Ep essc ea OP OE 8 4 1 OVEIVIOWs assar Aisle penais Ca Sader TTL ita Coal s DESERT 8 4 2 Line Driver Selection lslisilleesesseseeleee ehh 10 4 3 Memory Map uere eer nne coim e a Medea E ag qe eoe Coe JR a id EE a fg Soft a E E qo 11 4 4 UART Register Description 0 0 RR s 13 4 4 4 Transmitter Holding Register THR sssleeeeeeeeeee eee ae 13 4 4 2 Receive Holding Register RHR isssleseeeeee 13 4 4 3 Interrupt Enable Register IER venu srianan durr cece eee ae 13 4 4 4 Interrupt Identification Register IIR 6 2 0 0 teas
11. note that P14 is only for the rear panel configuration ara NRI Dom T Swamm SwaMme mo CS SS Ground 3 DS o m 08 Do TO mom o 9 S 8 a Hem 9 m Meg wed E RC NN ZINEE AD 21 7 poko 8 Domo vo om a CS ee ed Ground a ss ow 8 ES DES SDONE SBO Ground L 3 vw ms 8 EO E CT ip Ground C BE 0 DS Do 59 ma 60 CCII LCP 6 MAN 003 2003 10 29 Issue 1 1 WALCPITECHIMANICLCMANOS WPD Page 5 of 26 fo PRSignals ER Dm Sesmm Swamm O o 9m remm 9 9 rem em 9 27 3 3V AD 20 28 29 AD 18 Ground 30 sone CBE Ground 3 3V SERR E 1 De sem 99m AD 14 AD 13 Ds Sew wem O CCII LCP 6 MAN 003 2003 10 29 Issue 1 1 WALCPITECHIMANICLCMANOS WPD Page 6 of 26 P14 Signals Rear Panel Configuration Only Signal Name Signal Name Note P14 Signals are configured such that the adapter channels function as Data Terminal Equipment DTE This specifies the I O direction of the adapter s signals as follows TxD is an output RxD is an input RTS is an output e CTS is an input DTR is an output DSR is an input RI is an input e CD is an input CCII LCP 6 MAN 003 2003 10 29 Issue 1 1 WALCPITECHIMANICLCMANOS WPD Page 7 of 26 4 Serial Interface 4 1 Overview The 8 Channel Serial I O PMC Adapter has eight asynchronous RS 232 or RS 422 485 switchable serial ports
12. register In the FIFO mode the interrupts are generated based on the control setup in the FIFO control register Interrupt Enable Register IER The interrupt enable register enables each of the five types of interrupts and INT pin response to an interrupt generation The interrupt enable register can also be used to disable the interrupt system by clearing IER O 3 The contents of this register are described below IER 0 0 Disable the received data available interrupt 1 Enables the received data available interrupt IER 1 0 Disable the transmitter holding register empty interrupt 1 Enable the transmitter holding register empty interrupt IER 2 O Disables the receiver line status interrupt 1 Enables the receiver line status interrupt IER 3 0 Disables the modem status interrupt 1 Enables the modem status interrupt IER 4 O Standard 16C450 550 mode Sleep mode is disabled 1 Enables sleep mode The UART is always awake when there is a byte in the transmitter activity on the RX or either Delta CTS Delta DSR Delta CD Delta RI is are set to logic 1 or when the device is in the loopback mode IER 5 O Standard 16C450 550 mode Power down mode is disabled 12 Enables the power down mode Power down mode functions similar to sleep mode except oscillator section CCII LCP 6 MAN 003 2003 10 29 Issue 1 1 WALCPITECHIMANICLCMANOS WPD Page 13 of 26 IER 6 7 Thes
13. 0 Dated April 4 1995 2 3 3 Draft Standard for a Common Mezzanine Card Family CMC P1386 Draft 2 0 Dated April 4 1995 CCII LCP 6 MAN 003 2003 10 29 Issue 1 1 WALCPITECHIMANICLCMANOS WPD Page 2 of 26 3 1 3 2 PMC PCI Interface Overview The 8 Channel Serial I O PMC Adapter conforms to the PMC interface specification which is based on the PCI bus interface standard The PMC interface standard defines the physical and environmental aspects of the PCI mezzanine card interface The 8 Channel Serial I O PMC Adapter implements a single width module that can provide I O through either a 120 pin MOLEX front panel connector Refer to Appendix A for part number and ordering information or through the back plane connector The PCI interface standard defines the electrical aspects of the interface The 8 Channel Serial I O PMC Adapter provides a PCI compliant slave interface allowing the host board to transfer data to and from the serial interface controller The PCI interface is implemented using a PCI based eight channel UART bridge Configuration Space The PCI interface defines a standard programming model for the configuration of PCI devices This interface is defined as the Configuration Space The table below shows the Configuration Space as defined by the PCI bus specification AD31 23 AD22 16 AD15 8 AD7 0 Address Device ID 0x0158 Vendor ID 0x13AB DO Sus coma om Class Code 0x070002 Revision ID 0x01 0x08
14. 0 during a read or write to the receiver holding the transmitter holding register or the interrupt enable register Modem Control Register MCHR The modem control register is an 8 bit register that controls an interface with a modem data set or peripheral device that is emulating a modem MCR O0 O Sets the DTR output pin to the mark high state 1 Sets the DTR output pin to the space low state MCR 1 0 1 Sets the RTS output pin to the mark high state Sets the RTS output pin to the space low state MCR 2 0 Sets the OP1 to the mark high state during loop back mode 1 Sets the OP1 to the space low state during loop back mode MCR 3 0 Disables UART interrupt Sets the OP2 to mark high state during loop back mode 1 Enables UART interrupt This bit is gated with IER 0 3 Sets the OP2 to the space low state during loop back mode CCII LCP 6 MAN 003 2003 10 29 Issue 1 1 WALCPITECHIMANICLCMANOS WPD Page 18 of 26 4 4 8 MCRI4 O Normal operation 1 Internal loop back mode Provides a local loop back feature for diagnostic testing of the UART When LOOP is set to 1 the following occurs The transmitter TX pin is set to the mark high state The receiver RX pin is disconnected The output of the transmitter shift register is looped back into the receiver shift register input The four modem inputs CTS DSR CD and RI pins are disconnected The four modem outpu
15. 2003 10 29 W LCP TECH MAN CLCMANO3 WPD Issue 1 1 Page v of v 1 Introduction and Scope 1 1 Scope This document serves as a user manual for C I Systems 8 Channel Serial I O PMC Adapter 1 2 Introduction The 8 Channel Serial I O PMC Adapter provides eight full duplex asynchronous serial ports All eight ports are capable of transmitting and receiving data using either RS 232 or RS 422 485 standards The 8 Channel Serial I O PMC Adapter adheres to the electrical requirements of the PCI interface specification and to the mechanical requirements of the PMC interface standard 1 3 System Overview The block diagram of the adapter is shown in Figure 1 Serial I O Serial I O gt PMC Bus Configuration EEPROM optional Channel1 User Selectable RS 232 RS 422 Level Converter 8 Channel UART with PCI Interface User Selectable mem RS 232 RS 422 Level Converter Bus Mode PAL Figure 1 Block diagram of the 8 Channel Serial I O PMC Adapter CCII LCP 6 MAN 003 W LCP TECH MAN CLCMANO3 WPD 2003 10 29 Issue 1 1 Page 1 of 26 2 Applicable and Reference Documents 2 1 Applicable Documents None 2 2 Reference Documents None 2 3 Specifications 2 3 1 PCI Local Bus Specification Revision 2 1 Dated June 1 1995 2 3 2 Draft Standard Physical and Environmental Layers for PCI Mezzanine Cards PMC P1386 1 Draft 2
16. Programming registers for these ports are compatible with the 16C550 UART Each ports is configured by DIP switches located on the PMC Adapter board On the rear panel PMC Adapter the signals are available at P14 as detailed in 3 5 On the front panel PMC Adapter the signals are available at J2 as shown in 3 4 J2 is a 120 pin shielded right angle connector manufactured by MOLEX Refer to Appendix A for part number and ordering information The pinout is as show in the table below see Appendix A for the physical pin locations J2 Signals Front Panel Configuration Only Signal Name Signal Name WALCPITECHIMANICLCMANO3 WPD Page 8 of 26 Note J2 Signals are configured such that the adapter channels function as Data Terminal Equipment DTE This specifies the I O direction of the adapter s signals as follows e TxDis an output RxD is an input RTS is an output e CTS is an input DTR is an output DSR is an input RI is an input e CD is an input CCII LCP 6 MAN 003 2003 10 29 Issue 1 1 WALCPITECHIMANICLCMANOS WPD Page 9 of 26 4 2 Line Driver Selection All eight channels can be individually configured to use RS 232 or RS 422 485 line drivers This is achieved by setting the appropriate DIP switches located on the 8 Channel Serial I O PMC Adapter as shown in Figure 4 DRIVER SELECT PORT AB PORT EF RS 422 R3 Rx Tarmination Rx Termination PORT CO PORT C H Rx Termination Rx Ter
17. ata without affecting any other UART operation CCII LCP 6 MAN 003 2003 10 29 Issue 1 1 WALCPITECHIMANICLCMANOS WPD Page 21 of 26 4411 4 4 12 Programmable Baud Rate Generator Each UART has its own Baud Rate Generator BRG with a prescaler for the transmitter and receiver The prescalar is controlled by a software bit in the MCR register MCR 7 sets the prescalar to divide the on board clock by 1 or 4 The output of the prescalar clocks the BRG The BRG further divides the clock to a programmable divisor between 1 and 2 1 to obtain a 16x or 8x sampling clock of the serial data rate The sampling clock is used by the transmitter for data bit shifting and receiver for data sampling The BRG divisor DLL and DLM registers defaults to a random value upon power up Therefore the BRG must be programmed during initialization to the operating data rate Baud Rate Generator Programming Baud Rate Baud Rate Divisor for 16X Clock MCR 7 1 MCR 7 0 Hex 10 FIFO Interrupt Mode Operation When the receiver FIFO and receiver interrupts are enabled FCR 0 1 IER 0 1 IER 2 1 a receiver interrupt occurs as follows The received data available interrupt issued to the microprocessor when the FIFO has reached its programmed trigger level It is cleared when the FIFO drops below its programmed trigger level The IIR receive data available indication also occurs when the FIFO trigger level is reached and like the interru
18. e bits are not used always set to 0 4 4 4 Interrupt Identification Register IIR The UART has an on chip interrupt generation and prioritization capability IIR O O An interrupt is pending Used either in a hardware prioritized or polled interrupt system 1 No interrupt is pending IIR 1 2 The UART provides four prioritized levels of interrupts Priority 1 Receiver line status highest priority Priority 2 Receiver data ready Priority 2 Receiver character time out Priority 3 Transmitter holding register empty Priority 4 Modem status lowest priority When an interrupt is generated the interrupt identification register indicates that an interrupt is pending and encodes the type of interrupt in its three least significant bits IIR 0 2 Interrupt Priority decode Interrupt source Receive Data Error Receive Data Ready Receive Time Out Transmit Holding Empty Modem Status Change These bits are used to identify the highest priority interrupt pending IR O will be set when no interrupt is pending To clear the interrupts it is necessary to perform reads from the following registers as required Receive Data Error Reading LSR register will clear this interrupt User should save LSR value after reading the register to maintain the error condition Receive Data Ready Reading RHR register till FIFO becomes empty Receive Timeout Reading entire characters from RHR Transmit Holding Empty Writing
19. er holding register is written to 1 to 64 CCII LCP 6 MAN 003 2003 10 29 Issue 1 1 WALCPITECHIMANICLCMANOS WPD Page 22 of 26 characters may be written to transmit FIFO while servicing this interrupt or the IIR is read The first transmitter interrupt after changing FCR is immediate if it is enabled The transmitter empty indicator is delayed one character time when there has not been at least two bytes in the transmitter FIFO at the same time since the last time that TEMT 1 TEMT is set after the stop bit has been completely shifted out The transmitter FIFO empty indicator works the normal way in this mode and is not delayed Character timeout and receiver FIFO trigger level interrupts have the same priority as the current received data available interrupt 4 4 13 Register Reset Conditions The value of the registers at reset is given below Reset Conditions Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RHR X X X X X X X THR X X X X X X X IER 0 0 0 0 0 0 0 FCR 0 0 0 0 0 0 0 IIR 0 0 0 0 0 0 0 LCR 0 0 0 0 0 0 0 MCR 0 0 0 0 0 0 0 LSR 1 1 0 0 0 0 0 MSR X X X X 0 0 0 SPR 1 1 1 1 1 1 1 CCII LCP 6 MAN 003 2003 10 29 Issue 1 1 WALCPITECHIMANICLCMANOS WPD Page 23 of 26 Appendix A MOLEX Connector Pin Locations and Ordering Information MOLEX Conector J2 Pin Locations A 1 PITCH A 5946 foa Ad 29988 8 O4 X AA 328 CKT NO 59 uu T O eee h i a A O rA VA x NU ANT E 7 6 MB
20. gister is not cleared The 1 that is written to this bit position is self clearing FCR 3 O Mode 0 Supports single transfer DMA 16C450 mode in which a transfer is made between Host bus he tee 1 Supports multi transfer DMA in which multiple transfers are made continuously until the receiver FIFO has been emptied FCR 5 4 These bits are not used FCR 6 7 These bits are used to set the trigger level for receive FIFO interrupt Receive Trigger Levels Bytes FCR 7 FCR 6 RX FIFO Trigger Level CCII LCP 6 MAN 003 2003 10 29 W LCP TECH MAN CLCMANO3 WPD 4 4 6 Line Control Register LCR The system programmer controls the format of the asynchronous data communication exchange through the line control register In addition the programmer is able to retrieve inspect and modify the contents of the line control register this eliminates the need for separate storage of the line characteristics in system memory LCR O 1 These two bits specify the number of bits in each transmitted or received serial character Word Length LCR 1 LCRI 0 Word Length o Jo w U Lap L0 LCR 2 This bit specifies 1 1 1 2 or 2 stop bits in each transmitted character When LCR 2 is reset to 0 one stop bit is generated in the data When LCR 2 is set to 1 the number of stop bits generated is dependent on the word length selected with LCR 0 1 The receiver clocks only the first sto
21. in the line control register PE is reset every time the Host reads the contents of the line status register In the FIFO mode this error is associated with the particular character in the FIFO to which it applies This error is revealed to the Host when its associated character is at the top of the FIFO LSR 3 O Normal operation No framing error 12 Itindicates that the received character did not have a valid stop bit FE is reset every time the Host reads the contents of the line status register In the FIFO mode this error is associated with the particular character in the FIFO to which it applies This error is revealed to the Host when its associated character is at the top of the FIFO The UART tries to re synchronize after a framing error To accomplish this it is assumed that the framing error is due to the next start bit LSRI4 O Normal operation 1 It indicates that the received data input was held in the logic low state for longer than a full word transmission time A full word transmission time is defined as the total time to transmit the start data parity and stop bits Bl is reset every time the Host reads the contents of the line status register In the FIFO mode this error is associated with the particular character in the FIFO to which it applies This error is revealed to the Host when its associated character is at the top of the FIFO When a break occurs only one 0 character is loaded into the FIFO LSR 5
22. last time it was read by the Host When interrupt is enabled a modem status interrupt is generated MSR 1 0 No change to DSR input 1 Indicates that the DSR input has changed state since the last time it was read by the Host When interrupt is enabled a modem status interrupt is generated MSR 2 O No change to RI input 1 Indicates thatthe Rlinput has changed from the space low state to the mark high state When Rl is set to the mark high state and the modem status interrupt is enabled a modem status interrupt is generated MSR 3 O No change to CD input 1 Indicates that the CD input has changed state since the last time it was read by the Host When interrupt is enabled a modem status interrupt is generated MSR A Complement of the clear to send CTS input When the UART is in the diagnostic test mode this bit is equal to RTS MSR 5 Complement of the data set ready DSR input When the UART is in the diagnostic test mode this bit is equal to DTR MSR 6 Complement of the ring indicator RI input When the UART is in the diagnostic test mode this bit is equal to nOP1 MSR 7 Complement of the data carrier detect CD input When the UART is in the diagnostic test mode this bit is equal to nOP2 Scratch Pad Register SPR The scratch pad register is an 8 bit register that is intended for programmer use as a scratch pad in the sense that it temporarily holds the programmer d
23. mation to the Host concerning the status of data transfers The line status register is intended for read operations only writing to this register is not recommended MCR 1 4 are the error conditions that produce a receiver line status interrupt LSR O0 0 No data in receive holding or FIFO 12 Data ready indicator for the receiver This bit is set to 1 whenever a complete incoming character has been received and transferred into the receiver holding register or the FIFO It is reset to 0 by reading all of the data in the receiver holding register or the FIFO CCII LCP 6 MAN 003 2003 10 29 Issue 1 1 WALCPITECHIMANICLCMANOS WPD Page 19 of 26 4 4 9 LSR 1 O Normal operation No overrun error 1 Itindicates that before the character in the receiver holding register was read it was over written by the next character transferred into the register OE is reset every time the Host reads the contents of the line status register If the FIFO mode data continues to fill the FIFO beyond the trigger level an overrun error occurs only after the FIFO is full and the next character has been completely received in the shift register An overrun error is indicated to the Host as soon as it happens The character in the shift register is overwritten but it is not transferred to the FIFO LSR 2 O Normal operation No parity error 1 It indicates that the parity of the received data character does not match the parity selected
24. mination V Figure 4 DIP Switch Location S4 is used to select between RS 232 and RS 422 485 line drivers for channels A H When switched to the ON position RS 232 line drivers are selected otherwise RS 422 485 line drivers are selected 1 S2 S3 and S5 are used to switch in 100 Q line termination resistors required for RS 422 485 receivers When switched to the ON position the line termination is switched in It is crucial that these termination resistors NOT be switched in when RS 232 drivers have been selected on S4 in other words these switches must not be in the ON position when RS 232 line drivers have been selected CCII LCP 6 MAN 003 2003 10 29 Issue 1 1 W LCP TECH MAN CLCMANO3 WPD Page 10 of 26 4 3 Memory Map The memory map for the device configuration registers are given in the table below UART channel A registers Po 16C550 compatible UART A Read FIFO Read Only 64 bytes of RX FIFO UART A Write FIFO 64 bytes of TX FIFO UART B Read FIFO Read Only UART B Write FIFO Write Only UART C Read FIFO Read Only UART C Write FIFO Write Only Offset Address 0x000 0x007 0x100 0x200 0x207 0x300 0x300 16C550 compatible 64 bytes of RX FIFO 64 bytes of TX FIFO 16C550 compatible 64 bytes of RX FIFO 64 bytes of TX FIFO 0x900 OxA00 0xA07 0xB00 0xB40 0xB7F 0xC00 0xC07 UART channel D registers UART D Read FIFO UART D Write FIFO UART channel E registers
25. p bit regardless of the number of stop bits selected The number of stop bits generated in relation to word length and LCR 2 Stop Bits LCR 2 Word Length Stop Bit s LCR 3 O Parity is disabled No parity is generated or checked 12 Parity bit is generated in transmitted data between the last data word bit and the first stop bit In received data parity is checked LCRI4 0 ODD parity select bit When parity is enabled by LCR 3 a 1 in LCR 4 produces odd parity an odd number of 1 s in the data and parity bits 1 Even parity select bit When parity is enabled by LCR 3 a 1 in LCR 4 produces even parity an even number of 1 s in the data and parity bits LCR 5 O Stick parity is disabled 1 2 Stick parity bit When LCR 3 5 are set to 1 the parity bit is transmitted and checked as a 0 When LCR 3 and LCR 5 are 1 s and LCR 4 is a 0 the parity bit is transmitted and checked as 1 CCII LCP 6 MAN 003 2003 10 29 Issue 1 1 WALCPITECHIMANICLCMANOS WPD Page 17 of 26 4 4 7 Parity Selection x px pe mwa o o o 3 owr OC o TE 3 LCR 6 O Normal operation Break condition is disabled and has no effect on the transmitter logic 1 Force a break condition A condition where TX is forced to the space low state LCR T O Normal operation 1 Divisor latch enable Must be set to 1 to access the divisor latches of the baud generator during a read or write LCR 7 must be reset to
26. pt itis cleared when the FIFO drops below the trigger level The receiver line status interrupt has higher priority than the received data available interrupt The data ready bit LSR 0 is set when a character is transferred from the shift register to the receiver FIFO It is reset when the FIFO is empty When the receiver FIFO and receiver interrupts are enabled FIFO time out interrupt occurs when the following conditions exist Atleast one character is in the FIFO The most recent serial character was received more than four continuous character times ago if two stop bits are programmed the second one is included in this time delay The most recent microprocessor read of the FIFO occurred more than five continuous character times ago When a time out interrupt has occurred it is cleared and the timer is reset when the microprocessor reads one character from the receiver FIFO When a time out interrupt has not occurred the timeout timer is reset after a new character is received or after the microprocessor reads the receiver FIFO When the transmitter FIFO and THRE interrupt are enabled FCR 0 1 IER 1 1 transmit interrupts occur as follows The occurrence of transmitter holding register empty interrupt is delayed one character time minus the last stop bit time when there have not been at leasttwo bytes in the transmitter FIFO at the same time since the last time the transmitter FIFO was empty It is cleared as soon as the transmitt
27. ts DTR RTS nOP1 and nOP2 pins are internally connected to the four modem inputs The four modem outputs are forced to the mark high state In the diagnostic mode data that is transmitted is immediately received This allows the processor to verify transmit and receive data paths to the UART The receiver and transmitter interrupts are fully operational The modem control interrupts are also operational but the modem control interrupt sources are now the lower four bits of the modem control register instead of the four modem control inputs All interrupts are still controlled by the interrupt enable register MCR 5 O 16C450 550 mode Hardware flow control is disabled 1 Enable hardware flow control RTS CTS Flow Control MCR 5 MCR 1 Flow Control RTS becomes active low when the receiver is empty or the threshold has not been reached When receiver FIFO level reaches a trigger level of 1 4 8 and 14 RTS is de asserted mark state RTS is automatically reasserted once the receiver FIFO is empty by reading receive holding register The transmitter circuitry checks CTS before sending the next data byte When CTS is active space state the transmitter sends the next byte To stop the transmitter from sending the next byte CTS must be released before the middle of the last stop bit that is currently being sent MCR 6 7 These bits are not used Line Status Register LSR The line status register provides infor
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