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HUNT ENGINEERING HERON

1. DDR SDRAM Signal name FPGA Description pin SDRAM A AO AA SDRAM Address bit output SDRAM A Al Y8 SDRAM Address bit output SDRAM A A2 Y10 SDRAM Address bit output SDRAM A A3 AA10 SDRAM Address bit output SDRAM A A4 AC7 SDRAM Address bit output SDRAM A A5 AC9 SDRAM Address bit output SDRAM A A6 AB 9 SDRAM Address bit output SDRAM A A7 AE6 SDRAM Address bit output SDRAM A A8 AD6 SDRAM Address bit output SDRAM A A9 AF9 SDRAM Address bit output SDRAM A A10 AE9 SDRAM Address bit output SDRAM A All AD8 SDRAM Address bit output SDRAM A A12 AC8 SDRAM Address bit output SDRAM A A13 AC11 SDRAM Address bit output NOT USED FOR 128MBYTES SDRAM_A DQO WE SDRAM Data bit in out SDRAM A DQ1 WI SDRAM Data bit in out SDRAM A DQ2 V6 SDRAM Data bit in out SDRAM A DQ3 V5 SDRAM Data bit in out SDRAM A DQ4 W7 SDRAM Data bit in out SDRAM A DQ5 V7 SDRAM Data bit in out SDRAM A DQ6 WEI SDRAM Data bit in out SDRAM A DQ7 W6 SDRAM Data bit in out SDRAM A DQ8 Y2 SDRAM Data bit in out SDRAM A DQ9 Y1 SDRAM Data bit in out SDRAM_A DQ10 AAA SDRAM Data bit in out SDRAM A DQ11 AA3 SDRAM Data bit in out SDRAM A DQ12 AB1 SDRAM Data bit in out 60 HUNT ENGINEERING HERON FPGA12 USER MANUAL SDRAM A DQ13 AAT SDRAM Data bit in out SDRA
2. DIFOCONT2 E24 I P FIFO 0 Empty Flag active low input DIFOCONT3 H23 I P FIFO 0 Almost Empty flag active low input DIF1CONTO F20 I P FIFO 1 Read enable active high output DIF1CONT1 F24 I P FIFO 1 output enable active low output DIF1CONT2 E25 I P FIFO 1 Empty Flag active low input DIF1CONT3 H24 I P FIFO 1 Almost Empty flag active low input DIF2CONTO C25 I P FIFO 2 Read enable active high output DIF2CONT1 D25 I P FIFO 2 output enable active low output DIF2CONT2 G23 I P FIFO 2 Empty Flag active low input DIF2CONT3 G25 I P FIFO 2 Almost Empty flag active low input DIF3CONTO C26 I P FIFO 3 Read enable active high output DIF3CONT1 D26 I P FIFO 3 output enable active low output DIF3CONT2 G24 I P FIFO 3 Empty Flag active low input DIF3CONT3 G26 I P FIFO 3 Almost Empty flag active low input DIF4CONTO C23 I P FIFO 4 Read enable active high output DIF4CONT1 H21 I P FIFO 4 output enable active low output DIF4CONT2 E26 I P FIFO 4 Empty Flag active low input DIF4CONT3 H25 I P FIFO 4 Almost Empty flag active low input DIF5CONTO D23 I P FIFO 5 Read enable active high output DIF5CONT1 H22 I P FIFO 5 output enable active low output DIF5CONT2 F26 I P FIFO 5 Empty Flag active low input DIF5CONT3 H26 I P FIFO 5 Almost Empty flag active low input These FIFO signals should be used via the supplied HIL VHDL and are only mentioned here for completeness
3. Signal name FPGA Description pin UMIO CUL Uncommitted Module interconnect UMI1 D11 Uncommitted Module interconnect UMI2 C15 Uncommitted Module interconnect UMI3 C14 Uncommitted Module interconnect 64 HUNT ENGINEERING HERON FPGA12 USER MANUAL User interface between HSB device and FPGA N B Some signals also used during configuration of FPGA Signal name FPGA Description pin Data0 AD13 Data Bit for read write via HSB Datal AC13 Data Bit for read write via HSB Data2 AC15 Data Bit for read write via HSB Data3 AC16 Data Bit for read write via HSB Data4 AA11 Data Bit for read write via HSB Data5 AA12 Data Bit for read write via HSB Data6 AD14 Data Bit for read write via HSB Data7 AC14 Data Bit for read write via HSB VINIT AA15 Rising edge strobes the 8 bit address from the Data pins VCS AB13 Low to show an access in progress VWRITE AA16 State of this pin when Data Strobe is active defines whether the operation is read High or write low VBUSY AA13 The FPGA asserts this signal low when either a during a Write to the FPGA the data has been latched b during a read from the FPGA the data has been driven These signals should be used via the HIL VHDL supplied by HUNT ENGINEERING and are only mentioned here for completeness 65 HUNT ENGINEERING HERON FPGA12 USER MANUAL Appendix 3 Creating Your Own DDR Interface The FPGA support pr
4. 20 HUNT ENGINEERING HERON FPGA12 USER MANUAL Creating the Bitstream for Example1 Once the project has been opened as described above 1 In the Sources in project window Project Navigator highlight s ng e click on the entity top Common top vhd This is extremely important Otherwise nothing will work 2 Double click on the Generate Programming File item located in the Processes for Current Source This will trigger the following activity Complete synthesis using all of the project s source files Since warnings are generated at this stage you should see a yellow exclamation mark appear besides the Synthesize item in the Processes window Complete Implementation Translation Mapping Placing Routing 3 Creation of the bitstream Note that this stage runs a DRC check which can potentially detect anomalies created by the Place and route phase When the processing ends the proper bitstream file with extension rbt can be found in the project directory This file MUST be called top rbt If it is not then you have synthesised a small part of your design because you did not properly highlight top vhd in step1 4 In the Pad Report verify a few pins from the busses like the LED pins against the ucf file To do this you need to open implement design in the processes window then open Place and Route Then double click on the pad report to open it If you see different assignme
5. Also the Digital I Os and UMI pins on the module connector could be used as a clock input if another module in the system is programmed to drive that clock onto the UMI connection HERON FIFOS The HERON module can access up to 6 input FIFOs and up to another 6 output FIFOs Each FIFO interface is the same as the others using common clocks and data busses The input and output interfaces are separate though allowing data to be read and written at the same time by a module like the HERON FPGA12 While it is possible to read one FIFO and write another FIFO at the same time the use of shared pins means no more than one can be written or read at the same time i e in the same clock cycle For each interface input or output there is a FIFO clock that must be a constant frequency and running constantly There may be some minimum and maximum frequency requirements for a particular Module Carrier card that the designer of the FPGA contents must be sure to comply with This is because the FIFO clocks are generated by the FPGA probably based on one of the clock inputs to the part Each FIFO interface has a separate enable signal that is used to indicate which FIFO is accessed using the clock edge Input FIFOs The six input FIFOs use a common data bus that is driven onto the HERON module It is important to ensure that no more than one of the FIFOs are read at the same time but more importantly that no more than one has its output
6. These banks have 51R DCI resistors fitted so DCI formats can also be used LVDS It should be noted that Virtex 4 FPGAs don t support 3 3V LVDS but only 2 5V LVDS The input buffers for LVDS25 do not require Veco so are possible They even support the Differential Termination option of Virtex 4 However the LVDS25 output buffers require that the Veco is set to 2 5V This means that the HERON FPGA12 module cannot support LVDS output signals Module and Carrier ID The HERON specification assigns pins on the HERON module that give a HERON module access to the carrier ID of the carrier that it is plugged into and a unique HERON slot identifier These IDs are used by the configuration FPGA so that the module is addressed on HERON Serial Bus HSB using this information These signals are also connected to the User FPGA so a user program can use them if required General Purpose LEDs There are some LEDs on the HERON FPGA12 that are connected to some of the FPGA I O pins There ate five such LEDs which can be used by the FPGA program to indicate various states of operation Done LEDs There are two Done LEDs labelled DONE and CNT DONE They are illuminated if the relevant FPGA is not configured LED DONE is connected to the user Virtex 4 FPGA LED CNT DONE is connected to the Control FPGA 15 HUNT ENGINEERING HERON FPGA12 USER MANUAL This means that the CNT DONE should flash at power on and t
7. The SDRAM used is Micron part number MT46V32M16TG 5B FLASH Memory The HERON FPGA12 provides a 16Mbyte FLASH PROM directly connected to the I O pins of the FPGA It is intended to be used to store boot code for the Power PC core but the user is free to connect it and use it however they want It is organised as a byte wide memory bank of 16M locations It is an Intel Flash memory part number 28F128 3 In order to use the FLASH memory correctly an appropriate FLASH memory controller function is required inside the FPGA The FLASH then requires some protocols to be followed in order to unlock the writing of the part 14 HUNT ENGINEERING HERON FPGA12 USER MANUAL If the FLASH memory is used as intended connected to the Power PC core Xilinx provide a Core that will directly connect to and control this FLASH memory Xilinx also provide a large amount of driver software to take account of the protocols Users can develop their own uses of this FLASH memory in which case they will need to refer to the Intel documentation for this memory Digital UO The HERON FPGA12 connects 60 of the FPGAs I O pins to connectors This allows them to be configured as digital Inputs and Outputs as chosen by the user s FPGA program For the HERON FPGA12 Veco is always connected to 3 3V for the banks where the Digital I Os are connected Therefore all FPGA I O pins used with the Digital I O connectors can only use I O formats with a 3 3V Vcco settings
8. As long as the software has been installed using the installation program supplied on the HUNT ENGINEERING CD there should be little problem with the software installation If you have problems then return to one of the example programs supplied with the system 53 HUNT ENGINEERING HERON FPGA12 USER MANUAL CE Marking HUNT ENGINEERING have performed testing on its products to ensure that it is possible to comply with the European CE marking directives The HERON FPGA12 cannot be CE marked as it is a component in a system but as long as the following recommendations are followed a system containing the HERON FPGA12 could be CE marked The immense flexibility of the HUNT ENGINEERING product range means that individual systems should be marked in accordance with the directives after assembly 1 The host computer or housing in which the HERON FPGAS is installed is properly assembled with EMC and LVD in mind and ideally should itself carry the CE mark 2 Any cabling between boards or peripherals is either entirely inside the case of the host computer or has been assembled and tested in accordance with the directives The HERON FPGA12 digital I Os ARE protected against Static discharge so if the cabling does exit the case there is suitable protection already fitted HUNT ENGINEERING are able to perform system integration in accordance with these directives if you are unsure of how to achieve compliance yourself 54 HUNT ENGINEERI
9. CONNA 14 IO L4N GC LC 4 AF10 CONNA 15 IO L5P GC LC 4 AE14 CONNA 16 IO L5N GC LC 4 AE13 CONNA 17 IO L N GC LC 4 AD10 CONNA 18 User Oscillators The OSCO socket on the HERON FPGA12 accept a plastic bodied 3 3V oscillator such as the SG531 type from Seiko Epson The package is a 0 3 8 pin DIL type body but with only 4 pins The socket has four pins as shown VCC O P O O O O NIC GND These devices are available in TTL and 3 3V versions A 3 3V version must be used in this socket The socket provides 3 3v supply OSC3 is a surface mount locations that can be populated at build time It is powered from 3 3V and the output is buffered before connection to the FPGA OSC3 is fitted with a commercial grade 100ppm 100MHz oscillator at the factory The above part number is just an example of the oscillator type that can be fitted and the exact specification of the oscillator should be chosen carefully for the application it will be used for For example the tolerance jitter and temperature dependence might be important considerations for some applications 43 HUNT ENGINEERING HERON FPGA12 USER MANUAL Digital UO Connectors The Digital I O connectors provide the possibility to have digital I Os connected directly to the User FPGA device UO Characteristics The characteristics of the I O are governed by what is programmed into the FPGA However only certain formats are possible with each voltage lev
10. FPGA and HERON processor modules that carry various other members of the TMS320C6000 family of DSP processors from TI In addition to these modules the HERON specification is a super set of the pre existing HUNT ENGINEERING GDIO module so the GDIO modules from our C4x product range can also be used in HERON systems The HERON FPGA12 has connections to the HERON module pins that are not 5V tolerant This means it cannot be used in a module carrier boatd like the HEPC8 where some signals are tied to 5V rather than 3 3V Anyone designing their own module slots for the HERON FPGA12 must be careful to not connect 5V to any of the module signal pins of course the 5V power supply pins must still be driven The HERON module connects to the carrier board through several standard interfaces e The first is a FIFO input interface and a FIFO output interface This is to be used for the main inter node communications It is usually also used for connection to the HOST computer if any e The second is the HERON Serial Bus used for loading FPGAs and for non real time configuration messages e The last is the general control such as reset power and General Purpose IO HUNT ENGINEERING defined the HERON modules in conjunction with HEART the Hunt Engineering Architecture using Ring Technology This is a common architecture that we have adopted for our HERON carriers that provides good real time features such as low latency and high bandwidth
11. HERON module is 4 0 inches by 2 5 inches overall The 5mm limit on component height under the module is not violated by the HERON FPGA12 The maximum height of the HERON FPGA12 above the module including mating connectors and cables is 6 5mm This means that the assembly of a HERON module carrier and the HERON FPGA12 is less than the 20mm single slot spacing of PCI cPCI and VME 37 HUNT ENGINEERING HERON FPGA12 USER MANUAL Power Requirements of the HERON FPGA12 The HERON FPGA12 only uses power from the 5V HERON supply The 3 3V 2 5V and 1 2V supplies required by the FPGA are generated on board from this 5V The maximum power consumption of the HERON FPGA12 is determined by the number of gates and the FPGA program loaded The non FPGA circuitry of the HERON FPGA12 consumes the following 5V 3 3V 2 5V 1 2V 50mA 115mA 400mA 10mA The Switch mode circuits on the HERON FPGA12 can supply 4A at each of 3 3 V 2 5V and 1 2V These circuits are at least 85 efficient FPGA Power Consumption Dissipation The power consumption of an FPGA is governed by the number of signal transitions per second This means that it depends not only on the configuration loaded into it and the clock frequency but also on the data being processed The flexibility of a Xilinx FPGA means that determining the possible power consumption is not a trivial task an estimate can be obtained by using the Xilinx XPower software packag
12. Place and Route tool included but users of the other tools require the Xilinx Alliance tool The FPGA design can be entered using VHDL Design Files for the FPGA The FPGA design can be downloaded onto the FPGA12 in two ways Via the Configuration serial bus which requires a rbt file or hcb file or via the Flash PROM on the JTAG chain which requires a mcs file 33 HUNT ENGINEERING HERON FPGA12 USER MANUAL Generating Design Files Files for HERON Utility rbt The sections in this document titled Creating a Project and Inserting your own logic lead up to the generation of a rbt file which can be downloaded via the Configuration serial bus using the HERON Utility Before generating the rbt file right click on generate Program File in the processes for Current Source window in ISE select Properties on the menu and then select General Options Check that create ASCII Configuration File has been selected Process Properties ES Startup options Readback options Encryption options General Options Configuration options Property Hame Value Run Design Rules Checker DRC Create Bit File fe Create ASCII Configuration File IS Enable BitStream Compression fC Enable Debugging of BitStream CT Enable Cyclic Redundancy Checking CRC IS Cancel Default Help Also from Process Properties select the Start up Options and
13. SDRAM used is capable of transferring two data items on each consecutive clock cycle This means the absolute maximum data rate possible is 1 6 Gbytes second There are two main factors that will reduce this bandwidth These factors will vary from application to application Firstly DDR SDRAM uses one shared data bus for read accesses and write accesses This means at any one time only a read burst or a write burst can be in progress For applications that are both reading and writing concurrently the total bandwidth will be shared between the read and write Secondly the DDR SDRAM cannot instantaneously present read data or accept write data There are a small number of clock cycles either side of a data burst that are required to open the DDR SDRAM memory row and then close the memory row The smaller the burst the more impact this row open and close time will have 52 HUNT ENGINEERING HERON FPGA12 USER MANUAL Troubleshooting The following sections attempt to cover all likely problems Please check through this section before contacting technical support Hardware If the Hardware has been installed according to the Instructions there is very little that can be wrong e Has the DONE LED gone out if not then the FPGA is not configured e Perhaps you do not have a FIFO clock being driven from your FPGA Design e Not driving the UDPRES signal high in your FPGA Design will result in unpredictable behaviout Software
14. The first code that you will see at the beginning of this file is a VHDL Package named config which is used to configure the design files according to the application s requirements See the next section of this manual for a description of these items 19 HUNT ENGINEERING HERON FPGA12 USER MANUAL Below the package section you will see the User_Ap1 s VHDL code This is where you will insert your own code when you make your own design We provide a system which is built in such a way that the user should not need to edit any other file than User_Ap and the entities that this module instantiates In particular the user should NOT modify the HE files even when creating new designs for the FPGA Setting up the Configuration Package At the top of the file USER_APx VHD where x indicates the example number there are settings that you can change to affect your design in this case the example The idea is that settings that are often changed are found here In the case of the HERON FPGA12 there is only one setting in the config package 1 FIFO Clocks You must decide whether you will have a single common clock for driving the input and output FIFOs Normally a design is simpler if the same clock is used for input and output FIFOs but the module design allows you to use different frequencies or phases if that is more convenient for the design of your system Whether you use a common clock or separate clocks will affect your d
15. User_AP your module The top level and the other modules make the system work but you do not have to understand nor modify them in any way Let us see all of the Inputs Outputs Ports of your User_Ap module Note that the names used for these ports are effectively reserved even if the user does not connect to that signal This means the user must be careful not to re use the same name for 23 HUNT ENGINEERING HERON FPGA12 USER MANUAL a signal that should not connect to these ports Port Direction Description in User_Ap GENERAL RESET In Asynchronous module reset active high CONFIG In System config signal active low MOD_HAS_PROC Out Module output to assert whether the module should be treated as a processor module or not see HERON specification UMI_ENJ 0 3 Out Uncommitted Module Interconnect enables FPGA output driven when low UMI_INJ0 3 In Uncommitted Module Interconnects in UMI_OUT 0 3 Out Uncommitted Module Interconnects out MID 0 3 In Module ID of this module slot CID 0 3 In Carrier ID of this carrier UDPRES Out Optional reset to system Drive to 1 if not used LED 0 4 Out 5 x LEDs can be used for any purpose CLOCK SOURCES OSCH In External Clock from OSCO oscillator OSC3 In External Clock from OSC3 oscillator FIFO CLOCK INTERFACE FCLK_RD In Read FIFO Clock to be used in this module only when F
16. along with software reconfigurability of the communication system multicast multiple board support etc etc However it is not a requirement of a HERON module carrier that it implements such features In fact our customers could develop their own module carrier and add our HERON modules to it Conversely our customers could develop application specific HERON modules themselves and add them to our systems The HERON FPGA12 is HERON module that can be used for hardware signal processing or for flexible I O 6 HUNT ENGINEERING HERON FPGA12 USER MANUAL The HERON FPGA12 provides a Virtex 4 FX FPGA Xilinx part number xc4vfx12 For mote part information refer to the Xilinx web site at http www xilinx com This FPGA provides user programmable logic along with an embedded Power PC core The HERON FPGA12 connects all of the HERON module signals except JTAG to the FPGA allowing flexible use of the module s resources The HERON FPGA12 provides a total of 128Mbytes of SDRAM directly connected to the pins of the Xilinx FPGA This memory is organised as a 32 bit wide bank which can be used as general purpose memory by the FPGA or connected to the Power PC core The HERON FPGA12 provides 16Mbytes of FLASH memory directly connected to the pins of the Xilinx FPGA This memory is intended to hold boot code for the Power PC in embedded applications The HERON FPGA12 also provides 60 of the FPGA I Os connected to connectors on the module
17. and programmed using the HERON module s serial bus It is addressed according to the Carrier number and the slot number of the HERON slot that it is fitted to The FPGA configuration data will have been generated using the Xilinx development tools HUNT ENGINEERING provide examples for the HERON FPGA modules in the correct format for use with the Xilinx ISE software HUNT ENGINEERING also provides software for the Host PC that will allow the output files from the Foundation software to be loaded onto a HERON FPGA module If you use the Power PC core in the FPGA you will also need the Xilinx Embedded Developers Kit EDK If you are using the module on an embedded module carrier where there is no connection to a host machine you can use a Xilinx Parallel 4 or USB cable plugged into the JTAG connector on the module to download your FPGA design This connection can also be used to debug the FPGA design using the Xilinx Chipscope software and to debug the Power PC code using the GNU debugger supplied in the Xilinx EDK Follow the Starting your FPGA development tutorial from the HUNT ENGINEERING CD and then the general FPGA examples found in the same place on the CD It could be possible to use the HERON FPGA12 as an I O or memory module using one of the example bit streams In this case it is not necessary to be concerned how to program the FPGA simply load the example bit stream and use it Standard Intellectual Property IP HU
18. asserted accesses can be made on every clock but after it is asserted it is better to make one access only then check the full flag on the next clock before deciding if another access is possible FIFO clocks The FIFO clocks are provided by the user FPGA but are buffered externally using an LV T245 buffer that is able to provide the drive current required on these signals To enable circuitry internal to the FPGA to be designed to use the actual clock that is applied to the FIFO the buffered FIFO clock signals are connected to GCLK inputs to the FPGA This allows DLLs to be used to provide a clock internal to the FPGA that has the same phase as that applied to the FIFOs on the carrier board This is implemented inside the Hardware Interface Layer H I L VHDL supplied with the module DDR SDRAM The HERON FPGA12 provides a128Mbyte banks of 200MHz Double Data Rate DDR SDRAM directly connected to the I O pins of the FPGA The DDR SDRAM is organised as a 32 bit wide memory bank of 32M locations allowing a total bandwidth of 1 6Gbytes second In order to use the DDR SDRAM correctly an appropriate DDR SDRAM controller function is required inside the FPGA This controller must correctly initialise the DDR SDRAM and provide a constant refresh mechanism An appropriate DDR SDRAM controller is provided in the Hardware Interface Layer VHDL support from HUNT ENGINEERING The bank of DDR SDRAM is built from two pieces of 512Mbit Micron SDRAM
19. can be used to perform powerful Digital Signal Processing It is beyond the scope of this manual and indeed not part of the normal business of HUNT ENGINEERING to teach you how to do this There is however a simple way to build Signal Processing systems for the Xilinx FPGAs Xilinx supply as part of their tool set something called a Core Generator This provides a simple way of generating filters FFTs and other standard signal processing elements using a simple graphical interface It results in a block that can be included in your design and connected like any other component Typically it will have a clock input that will be subject to the pipeline speed constraints and clock enables to allow flow control Using the Core Generator you can quickly build up signal processing systems but for more complex systems you should take a course on Signal Processing theory and perhaps attend a Xilinx course on DSP using FPGAs 32 HUNT ENGINEERING HERON FPGA12 USER MANUAL Software The software for use with your FPGA will consist of several parts FPGA Development tool The application contents of the FPGA will be generated using FPGA development tools Xilinx ISE is the recommended tool along with ModelSim if you require simulation It is possible to use alternative FPGA synthesis tools such as Leonardo Spectrum or Synplicity but ultimately the Place and Route stage will be performed by the same tool Users of ISE have the
20. commands Module Enquiry The HERON FPGA12 can receive a message requesting its module type Master to FPGA module module type query 01 gt address of requestor It will then send a reply as follows FPGA module to original mastet module query response 02 gt module address from gt module type 02 gt family number 05 gt option gt String byte 0 gt String byte1 String byte26 The string is the string that Xilinx put into their bitstream files It is always 27 bytes long but can actually be null terminated before that The HERON FPGA12 returns 4vfx12ff668 11 FPGA Configuration The Configuration transaction will be Master to FPGA module Configure 03 gt address of requestor gt first config byte gt 2nd config byte last config byte After which the FPGA module will reply FPGA module to original master configuration success 05 configuration fail 06 gt module address 56 HUNT ENGINEERING HERON FPGA12 USER MANUAL User UO Any further use of the HSB will be defined by the bit stream supplied to the module The actual use of these messages cannot be defined here but the format of them must be Master to FPGA module user write 08 gt address of requestor gt register address byte gt value byte gt optional value byte gt optional value byte In this way single or multiple bytes can be written starting from the address given Nothing is returned from a write request Th
21. completeness FLASH MEMORY Signal name FPGA Description pin FLASH AO F10 FLASH Address bit output FLASH Al E10 FLASH Address bit output FLASH A2 A6 FLASH Address bit output FLASH A3 A5 FLASH Address bit output FLASH A4 E9 FLASH Address bit output FLASH_A5 F9 FLASH Address bit output FLASH A6 B6 FLASH Address bit output FLASH_A7 C6 FLASH Address bit output FLASH A8 G10 FLASH Address bit output FLASH A9 G9 FLASH Address bit output FLASH A10 F8 FLASH Address bit output FLASH All G8 FLASH Address bit output FLASH A12 B7 FLASH Address bit output FLASH A13 C7 FLASH Address bit output 61 HUNT ENGINEERING HERON FPGA12 USER MANUAL FLASH A14 C5 FLASH Address bit output FLASH AIS D5 FLASH Address bit output FLASH A16 A9 FLASH Address bit output FLASH_A17 B9 FLASH Address bit output FLASH A18 A3 FLASH Address bit output FLASH A19 B3 FLASH Address bit output FLASH A20 A4 FLASH Address bit output FLASH A21 B4 FLASH Address bit output FLASH A22 C4 FLASH Address bit output FLASH A23 D4 FLASH Address bit output FLASH A24 E7 FLASH Address bit output FLASH DO D10 FLASH Data bit in out FLASH D1 C10 FLASH Data bit in out FLASH D2 D9 FLASH Data bit in out FLASH_D3 C8 FLASH Data bit in out FLASH D4 A8 FLASH Data bit in out FLASH D5 A7 FLASH Data bit in out FLASH D6 D
22. enable selected By properly asserting the read enable and output enable signals relative to the clock the FPGA can access the FIFO of its choice at a rate up to one 32 bit word per clock cycle For the timing of those signals refer to the HERON module specification Each input FIFO interface provides Flags that indicate the state of the FIFO An empty flag shows that there is no data to be read an almost empty flag shows that there are at least 4 words left While the almost flag is not asserted accesses can be made on every clock but after it is asserted it is better to make one access only then check the empty flag on the next clock before deciding if another access is possible 13 HUNT ENGINEERING HERON FPGA12 USER MANUAL Output FIFOs The six output FIFOs use a common data bus that is driven by the HERON module It is important to ensure that no more than one of the FIFOs is written at the same time unless that is required by your system By properly asserting the write enable signals relative to the clock the user FPGA can access the FIFO of its choice at a rate up to one 32 bit word per clock cycle For the timing of those signals refer to the HERON module specification Each output FIFO interface provides Flags that indicate the state of the FIFO A full flag shows that there is no room left to write an almost full flag shows that there are at least 4 words of space left While the almost flag is not
23. file provided means you do not need to enter the pin constraints at all It is expected that every user will start by following the Getting Started example Example1 which is supplied on the HUNT ENGINEERING CD By working through the Getting Started example you will be able to see how the User FPGA is configured how a simple example can be built and a new bitstream generated In this way you can use Examplel to check your understanding of how the module works and you can also use the example as a sanity check that your hardware is functioning correctly 17 HUNT ENGINEERING HERON FPGA12 USER MANUAL Working through Example 1 All HERON modules that have FPGAs have an Example1 provided for them It is a simple example that connects data from the input FIFO interface to the output FIFO interface and also exercises the HSB interface This example is fully described in the Starting your FPGA development tutorial on the HUNT ENGINEERING CD The tutorial works through running the example and then modifying and re building it The tutorial assumes that you are using the latest version of the ISE Foundation tool set from Xilinx If you are using a different version of ISE Foundation you will simply need to convert the project as described in the application note provided by HUNT ENGINEERING titled Using Different Versions of ISE There is also an application note on the HUNT ENGINEERING CD that describes using design flows tha
24. pin OSCO C13 User Oscillator input from socketed Xtal Osc OSC3 AF12 User Oscillator input from surface mount Xtal Osc Repeated from above SDRAMA CLKP AC6 SDRAM A Clock pair positive SDRAMA CLKN AB6 SDRAM A Clock pair negative SDRAMA CLKIN AE10 200MHz clock input for SDRAM LEDs Signal name FPGA Description pin LEDO AA14 General Purpose LED LED1 AB14 General Purpose LED LED2 AC12 General Purpose LED LED3 F11 General Purpose LED LED4 F16 General Purpose LED Control connections to HERON connectors Signal name FPGA Description pin MOD_HAS_PROC F15 Signal that indicates if a module has a processor or not UDPRES D13 This module can drive this to reset the carrier YOU MUST DRIVE THIS SIGNAL HIGH IF NOT USING IT RESET D14 Reset input from Carrier card 63 HUNT ENGINEERING HERON FPGA12 USER MANUAL CONFIG D15 Open collector signal Carrier and Module ID Signal name FPGA Description pin CIDO D16 Carrier ID driven by the carrier board CID1 C16 Carrier ID driven by the carrier board CID2 E13 Carrier ID driven by the carrier board CID3 D12 Carrier ID driven by the carrier board MIDO F14 Module ID driven by the carrier board MID1 F13 Module ID driven by the carrier board MID2 F12 Module ID driven by the carrier board MID3 E14 Module ID driven by the carrier board Uncommitted Module Interconnects
25. possible from the I O connectors Any of these can be used as clocks in the FPGA design as can clocks provided on any of the other I Os One technique for example could be to use one of the UMI pins as a clock input which can be driven by the timer of a DSP module or possibly another FPGA module driving a clock onto that UMI This type of use though is system specific and we cannot supply a generic example for that The examples that we provide for the module assume a clock is fitted to OSC3 and use that as the only clock in the design Flow Control Because the processing speed of the FPGA will almost never be the same as every other component in your system it will be necessary to use some flow control in your design The most general way to implement this is to use Clock enables to enable the processing only when it is possible for data to flow through the system Otherwise some type of data storage like FIFOs must be implemented to ensure that data is never lost or generated erroneously When data is read from the HERON Input FIFOs there are FIFO flags to indicate when there is data to be read Reading from the FIFO when the flags indicate that there is no data to read will result in false data being fed through your system Thus your design must either a only assert the read signal when the Empty Flag EF is not asserted or b use the EF as a clock enable for the logic in the design thus preventing the invalid data caused by readi
26. used to generate c1k0 c1k180 and wclk BUFG WCLK BUFG SDRAM_CLKIN CLKIN CLKO a CLKO CLKFB CLK180 fe CLK180 BUFG DCM_X1Y0 The DCM used in the HUNT ENGINEERING clock scheme gives two signals c1k0 and c1k180 separated by half a clock cycle The DCM is set to give a phase shift of 5 to give a known phase shift between the signal wclk and the DCM outputs The correct phase shift value is important in meeting write data timings on the external memory The FPGA control outputs sdram_a_a lt 12 0 gt sdram_a_ba lt 1 0 gt sdram_a_ras sdram_a_cas and sdram_a_we are all driven using output flip flops flip flops assigned to IOBs These output flip flops are clocked by the signal c1k180 The signals sdram_a_clk_p and sdram_a_clk_n are generated as shown below With IOB flip flops clocked in this manner this creates a situation where the control signals for address ras cas and we change exactly half way between rising edges of the DDR clock input WE DO Q sdram_a_clk p vo D1 CLKO co CLK180 CI FDDRRSE vo DO Q sdram_a_clk n 1 D1 CLKO CO CLK180 C1 FDDRRSE 69 HUNT ENGINEERING HERON FPGA12 USER MANUAL The write data signals and write data mask signals are clocked by the signal wclk as shown below Write data is data sent from the FPGA to the external DDR memory write rising d lt n gt DO Q sdram_a_dq lt n gt write falling d lt n gt D1 welk co wclkb el FDDRRSE mask _rising_d lt m gt DO Q
27. 28 Ihserting VOUT OWN TORIC sr sisii rin 29 KE 29 User Timing Constraints aas r anaE A AR A A A ERE 29 HINTS FOR EPGA DESIGNS reei an ien aaao aes EEE EERE EEE EE EE e AE EEEE EEEa 30 TEE 30 PossibleSourC s 0f Clocks ii ee oes Bias Bek lav Bio avi Dish nae coc 31 ett e 31 Pipeline Length or tee ees Eege ENEE Eet 32 T O5FROM THEE RGA cuatros 32 DSP WITH YOURSEPGA nico tf Lota Eee droit E 32 EPGA DEVELOPMENTTOOEL cutre e E R E EREE 33 DESIGN FILES FORTHE FPGA AAA dE ee ee 33 GENERATING DESIGN FILES isisi isini ern n e ee ean Eh gen aaa ETE E EErEE E EENE ERE EE is 34 Files for HERON Utility CKb ia 34 Files for PROMS Em E E ons dak E R Ea 35 3 HUNT ENGINEERING HERON FPGA12 USER MANUAL POWER PC SORT WARES in Eech Eeer BRI RB ee 35 HERON_FPGA CONFIGURATION TOOL eoii iE i ERR EEA E a A i i 35 HUNT ENGINEERING HOST API nooo nn cnnnncnnnnnnnncnnn nc nn ncnnnannn coins 35 HUNT ENGINEERING HERON APT 35 HERON MODULE TYPE uc a E ed 36 HARDWARE RESET WEE 36 SOFTWARE RESET VIA SERIAL Bus 36 CONFIG rl 37 PHYSICAL DIMENSIONS OF THE Mont 37 POWER REQUIREMENTS OF THE HERON FbOATI nn cnn nnncnnns 38 FPGA POWER CONSUMPTION DISSIPATION s nssnssnnsseossooseeeoeeoeeeeeseesstesseesresstesetereosseesstesseesseesseesrerees 38 Choosing an Appropriate Heatsink and Fon 39 How the Power Limit is Calculated ccccccccccccccsseeccsccccccusssscescceccessssssssccccessessssssescuessssssseceeceessnssaas 39 FIP OS A EE ENEE Seege 41 D
28. 3 General purpose I O with selectable I O format A18 L5N 4 AD10 General purpose I O with selectable I O format A19 L10P_ 5 B24 General purpose I O with selectable I O format A20 L10N_5 B23 General purpose I O with selectable I O format A21 L11P_5 F18 General purpose I O with selectable I O format A22 L11N_5 El8 General purpose I O with selectable I O format A23 L22P 5 H20 General purpose I O with selectable I O format A24 L22N 5 G20 General purpose I O with selectable I O format A25 L20N_6 cI General purpose I O with selectable I O format A26 L21P_6 H8 General purpose I O with selectable I O format A27 L21N_ 6 H7 General purpose I O with selectable I O format A28 L22P 6 D3 General purpose I O with selectable I O format 62 HUNT ENGINEERING HERON FPGA12 USER MANUAL A29 L22N 6 E4 General purpose I O with selectable I O format BO L18P 6 E6 General purpose I O with selectable I O format B1 L18N 6 E5 General purpose I O with selectable I O format B2 L19P 6 F7 General purpose I O with selectable I O format B3 L19N 6 G7 General purpose I O with selectable I O format B4 L26P 6 El General purpose I O with selectable I O format B5 L26N 6 Fl General purpose I O with selectable I O format B6 L27P_5 F4 General purpose I O with selectable I O format B
29. 7 L27N 6 F3 General purpose I O with selectable I O format B8 L28P 6 G4 General purpose I O with selectable I O format B9 L28N_ 6 G3 General purpose I O with selectable I O format B10 L29P 6 H6 General purpose I O with selectable I O format B11 L29N 6 H5 General purpose I O with selectable I O format B12 L30P 6 G2 General purpose I O with selectable I O format B13 L30N 6 G1 General purpose I O with selectable I O format B14 L31P 6 H4 General purpose I O with selectable I O format B15 L31N 6 H3 General purpose I O with selectable I O format B16 L32P 6 H2 General purpose I O with selectable I O format B17 L32N_6 H1 General purpose I O with selectable I O format B18 L6P_7 Y25 General purpose I O with selectable I O format B19 L6N_7 Y26 General purpose I O with selectable I O format B20 L7P_7 AB24 General purpose I O with selectable I O format B21 L7N_7 AB25 General purpose I O with selectable I O format B22 L22P_7 AA19 General purpose I O with selectable I O format B23 L22N 7 AA20 General purpose I O with selectable I O format B24 L26P_7 AF24 General purpose I O with selectable I O format B25 L26N_7 AE24 General purpose I O with selectable I O format B26 L31P 7 AF18 General purpose I O with selectable I O format B27 L31N_7 AE18 General purpose I O with selectable I O format B28 L32P_7 AE21 General purpose I O with selectable I O format B29 L32N_7 AD21 General purpose I O with selectable I O format Clocks Signal name FPGA Description
30. 8 FLASH Data bit in out FLASH D7 D7 FLASH Data bit in out FLASH CEN D6 FLASH CHIP ENABLE FLASH WEN E3 FLASH WRITE ENABLE FLASH OEN E2 FLASH OUTPUT ENABLE FLASH_RPN D2 FLASH RESET POWERDOWN FLASH VP D1 FLASH PROGRAM ENABLE FLASH ST C2 FLASH STATUS IO on Connectors Signal name FPGA Description pin AO L4P 3 B13 General purpose I O with selectable I O format Al L4N 3 B12 General purpose I O with selectable I O format A2 L5P 3 A16 General purpose I O with selectable I O format A3 L5N 3 A15 General purpose I O with selectable I O format A4 L6P 3 A10 General purpose I O with selectable I O format A5 L6N 3 B10 General purpose I O with selectable I O format A6 L7P 3 B17 General purpose I O with selectable I O format A7 L7N 3 A17 General purpose I O with selectable I O format A8 L8N 3 C12 General purpose I O with selectable I O format AQ LIN 4 AE12 General purpose I O with selectable I O format A10 L2P 4 AC10 General purpose I O with selectable I O format A11 L2N 4 AB10 General purpose I O with selectable I O format A12 L3P 4 AB17 General purpose I O with selectable I O format A13 L3N 4 AC17 General purpose I O with selectable I O format Al4 L4P 4 AF11 General purpose I O with selectable I O format A15 L4N 4 AF10 General purpose I O with selectable I O format A16 L5N 4 AE14 General purpose I O with selectable I O format A17 L6N 4 AE1
31. CLK_G_DOMAIN FALSE SRC_FCLK_ RD Out Input FIFO Clock source for the top level only when FCLK_G_DOMAIN FALSE FCLK_WR In Output FIFO Clock to be used in this module only when FCLK_G_DOMAIN FALSE SRC_FCLK_ WR Out Output FIFO clock source for the top level only when FCLK_G_DOMAIN FALSE FCLK_G In Common FIFO clock to be used in this module only when FCLK_G_DOMAIN TRUE SRC_FCLK_G Out Common FIFO clock source for the top level only when FCLK_G_DOMAIN TRUE 24 HUNT ENGINEERING HERON FPGA12 USER MANUAL INPUT FIFOs INFIFO_READ_REQJ5 0 Out Input FIFO Read Request INFIFO_DVALID 5 0 In Input FIFO Data Valid INFIFO_SINGLEJ5 0 In Input FIFO Single Word Available INFIFO_BURSTT 5 0 In Input FIFO Burst Possible INFIFOO_D 31 0 In Input FIFO 0 Data INFIFO1_D 31 0 In Input FIFO 1 Data INFIFO2_D 31 0 In Input FIFO 2 Data INFIFO3_D 31 0 In Input FIFO 3 Data INFIFO4_D 31 0 In Input FIFO 4 Data INFIFO5_D 31 0 In Input FIFO 5 Data OUTPUT FIFOs OUTFIFO_READY 5 0 In Output FIFO Ready for Data OUTFIFO_WRITE 5 0 Out Output FIFO Write Control OUTFIFO_D 31 0 Out Data written into Output FIFO HE_USER I F MSG_CLK Out Clock to HE USER interface logic MSG _DIN 7 0 In Data received from HSB MSG _ADDR 7 0 In address received from the HSB MSG WEN In Write access from the HSB MSG _REN In Read access from the HSB M
32. D_ADDR_AF In DDR Port A Read Address Almost Full DDR_A_RD_RISE_REN Out DDR Port A Read Rising Data Enable DDR_A_RD_RISE_EF In DDR Port A Read Rising Data Empty DDR_A_RD_RISE_AE In DDR Port A Read Rising Data Almost Empty DDR_A_RD_FALL_REN Out DDR Port A Read Falling Data Enable DDR_A_RD_FALL_EF In DDR Port A Read Falling Data Empty DDR_A_RD_FALL_AE In DDR Port A Read Falling Almost Empty Hardware Interface Layer All of the signals listed above are connected between the User_Ap interface and the pins of the FPGA via the Hardware Interface Layer The Hardware Interface Layer includes logic that correctly interfaces many different functional parts of the FPGA from HERON FIFO interfaces DDR SDRAM interface to clock inputs and outputs to digital I O and serial I O For a complete description of the Hardware Interface Layer HIL please read the document Using the Hardware Interface Layer in your FPGA Design Important The FPGA sets any I O pins of the device that are not listed in the design to have a 50 150K pull down Most of the HERON module signals are pulled to their inactive state by 10K resistors so this 50K will have no effect However the UDPRES signal does not and setting this signal low will cause your whole board to be reset Thus it is important that the UDPRES pin is driven high by the FPGA if it is not being used It is also advised to do the same with the LED pins to prevent them becoming illum
33. FIFO Data bit input DI4 B18 HERON FIFO Data bit input DI5 A18 HERON FIFO Data bit input DI6 D20 HERON FIFO Data bit input DI7 D19 HERON FIFO Data bit input DI8 E17 HERON FIFO Data bit input DES F17 HERON FIFO Data bit input DI10 C21 HERON FIFO Data bit input DI11 B21 HERON FIFO Data bit input DI12 C19 HERON FIFO Data bit input DI13 D18 HERON FIFO Data bit input DI14 A24 HERON FIFO Data bit input DI15 A23 HERON FIFO Data bit input DI16 G18 HERON FIFO Data bit input DI17 G17 HERON FIFO Data bit input DI18 E21 HERON FIFO Data bit input DI19 D21 HERON FIFO Data bit input DI20 A20 HERON FIFO Data bit input DI21 A19 HERON FIFO Data bit input DI22 D22 HERON FIFO Data bit input DI23 C22 HERON FIFO Data bit input DI24 A22 HERON FIFO Data bit input DI25 A21 HERON FIFO Data bit input DI26 D24 HERON FIFO Data bit input DI27 C24 HERON FIFO Data bit input DI28 G19 HERON FIFO Data bit input DI29 F19 HERON FIFO Data bit input DI30 E23 HERON FIFO Data bit input DI31 E22 HERON FIFO Data bit input FLCLK B14 I P FIFO Clock output to input of buffer Use to drive correct frequency DICLK GCLKx B15 I P FIFO Clock output of buffer use with DLL for internal logic DIFOCONTO E20 I P FIFO 0 Read enable active high output DIFOCONT1 F23 I P FIFO 0 output enable active low output 59 HUNT ENGINEERING HERON FPGA12 USER MANUAL
34. HERON FPGA12 can be used it must be reset This reset initialises the Heron Serial Bus circuitry into a state where it can be used Depending on the way that the user FPGA was last configured it may also reset some functions in the user FPGA This reset DOES NOT cause the user FPGA to require re configuration This signal is driven by the HERON module Carrier and must NOT be left unconnected as this will cause the HERON FPGA12 to behave erratically It must also NEVER be driven by the user FPGA on the HERON FPGA12 Software Reset via Serial Bus The Serial configuration bus has a reset command that is executed at the beginning of a bit stream download This must never be confused with the system hardware reset provided on the HERON pin it is not the same thing The Serial bus reset simply resets the internal configuration of the FPGA but will NOT perform a hardware reset It cannot affect the HERON carrier board FIFOs or any other module in the system 36 HUNT ENGINEERING HERON FPGA12 USER MANUAL Config There is a system wide Config signal that is open collector and hence requires a pull up to be provided by the motherboard The HERON FPGA12 can drive this signal active low or inactive if required or can use it as an input to disable data transfer during a DSP booting phase If the FPGA program does nothing with this signal the signal will be pulled high by the carrier board Physical Dimensions of the Module A size 1
35. HUNT ENGINEERING aa Neste Chestnut Court Burton Row treme AD m Brent Knoll Somerset TA9 4BP UK Tel 44 0 1278 760188 Fax 44 0 1278 760199 Email sales hunteng co uk http www hunteng co uk http www hunt dsp com HUNT ENGINEERING HERON FPGA 12 HERON Module with XC4VFX12 Virtex 4 FPGA Digital YO and 128Mbytes of SDRAM USER MANUAL Hardware Rev A Document Rev A P Warnes 22 02 06 COPYRIGHT This documentation and the product it is supplied with are Copyright HUNT ENGINEERING 2006 All rights reserved HUNT ENGINEERING maintains a policy of continual product development and hence reserves the right to change product specification without prior warning WARRANTIES LIABILITY and INDEMNITIES HUNT ENGINEERING warrants the hardware to be free from defects in the material and workmanship for 12 months from the date of purchase Product returned under the terms of the warranty must be returned carriage paid to the main offices of HUNT ENGINEERING situated at BRENT KNOLL Somerset UK the product will be repaired ot replaced at the discretion of HUNT ENGINEERING Exclusions If HUNT ENGINEERING decides that there is any evidence of electrical or mechanical abuse to the hardware then the customer shall have no recourse to HUNT ENGINEERING ot its agents In such circumstances HUNT ENGINEERING may at its discretion offer to repair the hardware and charge for that repair Limitations of Liability HUNT ENGINEE
36. M A DQ14 AC4 SDRAM Data bit in out SDRAM A DQ15 AB4 SDRAM Data bit in out SDRAM A DQ16 AC5 SDRAM Data bit in out SDRAM A DQ17 AB5 SDRAM Data bit in out SDRAM A DQ18 AC2 SDRAM Data bit in out SDRAM A DQ19 AC1 SDRAM Data bit in out SDRAM A DQ20 AF3 SDRAM Data bit in out SDRAM A DQ21 AE3 SDRAM Data bit in out SDRAM A DQ22 AD2 SDRAM Data bit in out SDRAM A DQ23 AD1 SDRAM Data bit in out SDRAM A DQ24 AE4 SDRAM Data bit in out SDRAM A DQ25 AD3 SDRAM Data bit in out SDRAM A DQ26 AC3 SDRAM Data bit in out SDRAM A DQ27 AF6 SDRAM Data bit in out SDRAM A DQ28 AF5 SDRAM Data bit in out SDRAM A DQ29 AAT SDRAM Data bit in out SDRAM A DQ30 AA9 SDRAM Data bit in out SDRAM A DQ31 Y9 SDRAM Data bit in out SDRAM A DQSO Y4 SDRAM Byte strobe 0 SDRAM A DQS1 Y3 SDRAM Byte strobe 1 SDRAM A DQS2 Y6 SDRAM Byte strobe 2 SDRAM A DQS3 Y5 SDRAM Byte strobe 3 SDRAM A DMO W5 SDRAM Data Mask 0 SDRAM A DM1 AB3 SDRAM Data Mask 0 SDRAM A DM2 AF4 SDRAM Data Mask 0 SDRAM A DM3 AD5 SDRAM Data Mask 0 SDRAM A BAO AF8 SDRAM Bank address bit output SDRAM A DAT AF7 SDRAM Bank address bit output SDRAM_A RAS AE7 SDRAM Row address strobe output SDRAM A CAS AD7 SDRAM Column address strobe output SDRAM A WE AD4 SDRAM Write enable output SDRAM A CLKP AC6 SDRAM Clock pair positive SDRAM A CLKN AB6 SDRAM Clock pair negative SDRAM _ CLKIN AE10 200MHz clock input for SDRAM These SDRAM signals should be used via the supplied HIL VHDL and are only mentioned here for
37. N CONNA 11 IO L3P GC LC 4 AB17 6P CONNA_12 IO L3N GC LC 4 AC17 6N CONNA 13 IO L4P GC LC 4 AF11 7P CONNA 14 IO L4N GC LC 4 AF10 7N CONNA 15 IO L5P GC LC 4 AE14 8P CONNA_16 IO L5N GC LC 4 AE13 8N CONNA 17 IO L6N GC LC 4 AD10 CONNA_18 IO LIOP 5 B24 9P CONNA 19 IO LION 5 B23 9N CONNA 20 IO LIIP 5 F18 OP CONNA 21 IO LIIN 5 E18 10N CONNA 22 IO L22P 5 H20 1P CONNA 23 IO L22N 5 G20 TIN CONNA 24 IO L20N_VREF 6 C1 CONNA 25 IO L21P 6 H8 12P CONNA_26 IO LIN 6 H7 2N CONNA_27 IO L22P 6 D3 13P CONNA 28 IO L22N 6 E4 3N CONNA 29 IO L18P 6 E6 14P CONNB_0 IO LI8N 6 E5 4N CONNB 1 IO L19P 6 F7 15P CONNB 2 IO LION 6 G7 5N CONNB 3 IO L26P 6 El 16P CONNB 4 IO L26N 6 F1 6N CONNB_5 IO L27P 6 F4 17P CONNB 6 IO L27N 6 F3 7N CONNB_7 IO L28P 6 G4 18P CONNB_8 IO L28N VREF 6 G3 8N CONNB 9 Io L29P 6 H6 19P CONNB_ 10 IO L29N 6 H5 9N CONNB 11 IO_L30P_6 G2 20P CONNB 12 IO L30N 6 Gl 20N CONNB_13 IO L31P 6 H4 21P CONNB 14 IO LIN 6 H3 21N CONNB 15 IO L32P 6 H2 22P CONNB_16 IO L32N 6 H1 22N CONNB_17 IO L6P 7 Y25 23P CONNB 18 IO L6N 7 Y26 23N CONNB_ 19 IO L7P 7 AB24 24P CONNB 20 IO UN AB25 24N CONNB 21 IO L26P_SM6 7 AA19 25P CONNB 22 IO L26N_SM6 7 AA20 25N CONNB_23 IO L22P 7 AF24 26P CONND 24 IO L22N 7 AE24 26N CONNB 25 IO L31P_SM2 7 AF18 27P CONNB 26 IO L3IN_SM2 7 AE18 27N CONNB 27 IO L32P SM1 7 AE21 28P CONNB 28 IO L32N SMI 7 AD21 28N CONNB_29 46 HUNT ENGINEERING HERON FPGA12 USER MANUAL Resistor Packs These resistor
38. NG HERON FPGA12 USER MANUAL Technical Support Technical support for HUNT ENGINEERING products should first be obtained from the comprehensive Support section http www hunteng co uk support index htm on the HUNT ENGINEERING web site This includes FAQs latest product software and documentation updates etc Or contact your local supplier if you are unsure of details please refer to http www hunteng co uk for the list of current re sellers HUNT ENGINEERING technical support can be contacted by emailing support hunteng co uk calling the direct support telephone number 44 0 1278 760775 ot by calling the general number 44 0 1278 760188 and choosing the technical support option 55 HUNT ENGINEERING HERON FPGA12 USER MANUAL Appendix 1 HERON Serial Bus Commands Module Address The HERON FPGA12 is configured to respond to Heron Serial Bus HSB commands addressed to it using the combination of the Board number and slot number that the module is fitted to In this way multiple HERON FPGA modules can be uniquely addressed in the same system The HSB address is a 7 bit address that is formed by the bottom three bits of the slot number slots 1 to 4 are valid 001 010 011 100 with the 4 bits from the board number switch forming the top 4 bits of the seven e g on board number 1 slot 2 the address would be board number lt lt 3 slot 2 0 which is 0x06 The HERON FPGA12 can respond to three different types of serial bus
39. NT ENGINEERING provides examples for the HERON FPGA12 that perform different functions It is possible to use these standard configurations directly if they fit your needs It could be possible to request a new standard example from HUNT ENGINEERING which could avoid the need to purchase and learn how to use the FPGA development tools Depending on the complexity of your request HUNT ENGINEERING may choose not to offer it or to charge for it New IP for the HERON FPGA12 will be posted on the HUNT ENGINEERING web site in the user area whenever it becomes available HERON FPGA12 usets can then take advantage of that IP free of charge 9 HUNT ENGINEERING HERON FPGA12 USER MANUAL Module Features This section describes the features of the HERON FPGA12 and why they are provided FLASH Power aie Supply Cct 60 bits Digital I O JTAG PROM FPGA XC4VFX12 Clock options Configuration control FPGA HERON FIFO CONNECTIONS HERON CONTROLS HERON Serial Bus User Programmable FPGA with Embedded Power PC The Virtex 4 FX FPGA on the HERON FPGA12 offers both user programmable hardware in the form of Virtex 4 FPGA architecture and a Power PC processor core that is embedded in silicon The HERON FPGA12 allows the user to program the FPGA logic and Power PC processor using the tools provided by Xilinx The module design does not place any restriction on how the FPGA program can be configured There are many examples and tutorials
40. O AF23 O P FIFO 1 Write enable active high output DOF1CONT1 AC21 O P FIFO 1 Full Flag active low input DOF1CONT2 AB20 O P FIFO 1 Almost full flag active low input DOF2CONTO Y21 O P FIFO 2 Write enable active high output DOF2CONT1 AC19 O P FIFO 2 Full Flag active low input 58 HUNT ENGINEERING HERON FPGA12 USER MANUAL Signal name FPGA Description pin DOF2CONT2 AB18 O P FIFO 2 Almost full flag active low input DOF3 CONTO Y20 O P FIFO 3 Write enable active high output DOF3CONT1 AD19 O P FIFO 3 Full Flag active low input DOF3CONT2 AC18 O P FIFO 3 Almost full flag active low input DOF4CONTO Y18 O P FIFO 4 Write enable active high output DOF4CONT1 AA17 O P FIFO 4 Full Flag active low input DOF4CONT2 AF22 O P FIFO 4 Almost full flag active low input DOF5CONTO AA18 O P FIFO 5 Write enable active high output DOF5CONT1 Y17 O P FIFO 5 Full Flag active low input DOF5CONT2 AF21 O P FIFO 5 Almost full flag active low input These FIFO signals should be used via the supplied HIL VHDL and are only mentioned here for completeness Data In FIFO Signal name FPGA Description pin DIO C17 HERON FIFO Data bit input DI1 D17 HERON FIFO Data bit input DI2 C20 HERON FIFO Data bit input DI3 B20 HERON
41. O Data bit output DO3 W26 HERON FIFO Data bit output DO4 W21 HERON FIFO Data bit output DO5 W22 HERON FIFO Data bit output DO6 W23 HERON FIFO Data bit output DO7 W24 HERON FIFO Data bit output DO8 W20 HERON FIFO Data bit output DO9 V20 HERON FIFO Data bit output DO10 AA24 HERON FIFO Data bit output DO11 Y24 HERON FIFO Data bit output DO12 AC25 HERON FIFO Data bit output DO13 AC26 HERON FIFO Data bit output DO14 AB26 HERON FIFO Data bit output DO15 AA26 HERON FIFO Data bit output DO16 AD25 HERON FIFO Data bit output DO17 AD26 HERON FIFO Data bit output DO18 Y22 HERON FIFO Data bit output DO19 Y23 HERON FIFO Data bit output DO20 AC22 HERON FIFO Data bit output DO21 AB22 HERON FIFO Data bit output DO22 AB23 HERON FIFO Data bit output DO23 AA23 HERON FIFO Data bit output DO24 AD22 HERON FIFO Data bit output DO25 AD23 HERON FIFO Data bit output DO26 AC23 HERON FIFO Data bit output DO27 AC24 HERON FIFO Data bit output DO28 AF19 HERON FIFO Data bit output DO29 AF20 HERON FIFO Data bit output DO30 Y19 HERON FIFO Data bit output DO31 W19 HERON FIFO Data bit output FCLKO AD11 O P FIFO Clock output to input of buffer Use to drive correct frequency DOCLK GCLKx AD12 O P FIFO Clock output of buffer use with DLL for internal logic DOFOCONTO AE23 O P FIFO 0 Write enable active high output DOFOCONT1 AB21 O P FIFO 0 Full Flag active low input DOFOCONT2 AC20 O P FIFO 0 Almost full flag active low input DOF1CONT
42. ORSDRAM A A EE 41 USERFPGA E LEE 42 Tirso a E titi 43 DIGITAL VO CONNECTOR Site EEN 44 Ke EA 44 LVAD eth Aosta Pe tates hao te Selatan otis aes ie tes iF enh E he ce tae mT Lee 44 Using Digitally Controlled Impedance DCH 44 Differential Termination eer A A dee vtech einer 44 DIGITAL I O n Connector Tune 45 DIGITAL I O n Connector Pin Out ccccccccccccccssssssscccccscssssssscecccccssssssssscesscsesssssssesseceesssssseeceseess 45 Differential POTES A AA it AAA A AAA A i i iiaa 45 RESTO ERAS ba oe dal 47 EA 48 Differential Termination eet leie lets A Taba AE ele Ae tesche 48 VIIDE 201110 A EEEE E AE e ee ER 48 USING THE JTAG PROGRAMMABLE CONFIGURATION PROM 49 BOOT FROM PROM JUMPER e E E EE T 49 UNCOMMITTED MODULE INTERCONNECTS ooocccccoooccnononnncnnnononcnnnnnnnnonnnnnnnnnnnncnnnn nn nono nnnnnnnnnnrnnnnnnnnnannnncnnns 50 GENERAL PURPOSE LEDS 000 A oe ae 50 OTHER HERON MODULE SIGNAL 00000 i 50 FITTING MODULES TO YOUR CARRIER ccccssscssssssesssssscsccssscsseessesssees DL ACHIEVABLE SYSTEM THROUGHPUT ccccsssssssssscssesssssessesssssssesescssossees IZ FIP OPEHROUGHPUT eebe EE 52 DDR SDRAM THROUGHPUT ais gege da 52 THAR D WARE os 25 8 Si EE Eer 53 SOFTWARE A el aiii tata 53 TECHNICAL SUPPORT gege deene Ee APPENDIX 1 HERON SERIAL BUS COMMANDS ssessssessesseseecosoeseeeossesoeseeeesses D I MODULE ADDRESS eerst ees 56 MODULE ENQUIRY cosita io pille 56 FPGA CONFIGURATION ta 56 U
43. RING makes no warranty as to the fitness of the product for any particular purpose In no event shall HUNT ENGINEERING S liability related to the product exceed the purchase fee actually paid by you for the product Neither HUNT ENGINEERING nor its suppliers shall in any event be liable for any indirect consequential or financial damages caused by the delivery use or performance of this product Because some states do not allow the exclusion or limitation of incidental or consequential damages or limitation on how long an implied warranty lasts the above limitations may not apply to you TECHNICAL SUPPORT Technical support for HUNT ENGINEERING products should first be obtained from the comprehensive Support section http www hunteng co uk support index htm on the HUNT ENGINEERING web site This includes FAQs latest product software and documentation updates etc Or contact your local supplier if you are unsure of details please refer to http www hunteng co uk for the list of current re sellers HUNT ENGINEERING technical support can be contacted by emailing support hunteng demon co uk calling the direct support telephone number 44 0 1278 760775 or by calling the general number 44 0 1278 760188 and choosing the technical support option Version A initial document 2 HUNT ENGINEERING HERON FPGA12 USER MANUAL TABLE OF CONTENTS PHYSICAL LOCATION OF ITEMS ON THE HERON FPGA12 8 STANDARD INTELLECTUAL PROPERTY
44. SER 8 E 57 APPENDIX 2 FPGA PINOUT FOR DEVELOPMENT TOOLS 00002 58 APPENDIX 3 CREATING YOUR OWN DDR INTERFACE sscsssoeseees D I 4 HUNT ENGINEERING HERON FPGA12 USER MANUAL How MEMORY IS CONNPCTEDTOTHEFPOA no nnnconononnananonos 66 THE DDR CLOCK SCHEME CONTROLLING VREF GENERATION 71 HUNT ENGINEERING HERON FPGA12 USER MANUAL Introduction The HERON module is a module defined by HUNT ENGINEERING to address the needs of our customers for real time DSP systems The HERON module is defined both mechanically and electrically by a separate HERON module specification that is available from the HUNT ENGINEERING CD via the user manuals section from the CD browser or online from http www hunteng co uk and going to the application notes section in the user area The HERON module specification also defines the features that a HERON module carrier must provide HERON stands for Hunt Engineering ResOurce Node which tries to make it clear that the module is not for a particular processor or I O task but is intended to be a module definition that allows nodes in a system to be interconnected and controlled whatever their function In this respect it is not like the TIM 40 specification which was specific to the C4x DSP As the HERON FPGA12 was developed HUNT ENGINEERING have already developed HERON modules carriers like the HEPC9 a range of HERON FPGA modules that use the Virtex IT
45. SG DONE In Message was successfully transmitted used when initiating HSB messages MSG COUNT In Counter enable when initiating HSB messages MSG _CLEAR In Asynchronous clear for address counter when initiating HSB messages MSG _READY Out to acknowledge an access from the HSB MSG _SEND Out Message send command used when initiating HSB messages MSG _CE Out to control speed operation MSG _DOUT 7 0 Out Data to be sent to HSB MSG _SEND_ID Out Indicates when a byte should be replaced by Own ID used when initiating HSB messages MSG _LAST_BYTE Out To indicate when the last byte to be sent is presented when initiating HSB messages 25 HUNT ENGINEERING HERON FPGA12 USER MANUAL DIGITAL I O CONN_A_EN 29 0 Out Digital I O enables for connector A FPGA output pin driven when low CONN_A_IN 29 0 In Digital 1 O in for connector A CONN_A_OUT 29 0 Out Digital I O out for connector A CONN_B_EN 29 0 Out Digital I O enables for connector B FPGA output pin driven when low CONN_B_IN 29 0 In Digital I O in for connector B CONN_B_OUT 29 0 Out Digital I O out for connector B FLASH I F FLASH_ADDR 23 0 Out FLASH Address FLASH_INT 7 0 In FLASH Data In FLASH_OUT 7 0 Out FLASH Data Out FLASH_EN 7 0 Out FLASH Data Enable FPGA output pin driven with FLASH Data Out when low FLASH_CE Out FLASH Chip Enable FLASH_WE O
46. This allows the FPGA to be configured for a variety of I Os The HERON FPGA12 uses the HERON module s serial bus to download configuration bit streams into the FPGA allowing the user to configure it with standard functions provided by HUNT ENGINEERING or functions that they have developed themselves using the Xilinx development tools It is also possible for the module to configure the FPGA from a PROM This is intended to simplify the deployment of systems after the FPGA functions have been fully developed 7 HUNT ENGINEERING HERON FPGA12 USER MANUAL Physical Location of Items on the HERON FPGA12 2 5V Power good LED 1 2V Power good LED 3 3V Power good LED User FPGA boot from prom jumper General Purpose User FPGA LEDs Control DONE LED FPGA CNT DONE LED 8 HUNT ENGINEERING HERON FPGA12 USER MANUAL Getting Started The HERON FPGA12 is a module that plugs into a HERON module carrier The HERON FPGA12 should be fitted to the carrier card along with any other modules that your system has and their retaining nuts fitted see a later section of this manual for details The HERON FPGA12 following reset will enter a state where it can be interrogated
47. a gentle force is needed to push the module home check to make sure that it is correctly aligned Take care not to apply excessive pressure to the centre of the module as this could stress the module s PCB unnecessarily Normally the primary fixings will be enough to retain the modules simply fit the nylon bolts supplied in the accessory kit to the top thread of each mounting pillar pe HERON module Nylon nut If the environment demands the secondary fixing pillars can be fitted to modules that allow their use 51 HUNT ENGINEERING HERON FPGA12 USER MANUAL O Secondary pillars Achievable System Throughput In a HERON system there are many factors that can affect the achievable system throughput It must be remembered at all times that the part of the system that has the lowest limit on bandwidth will govern the throughput of the system FIFO Throughput The HERON FPGA12 can access the HERON carriers FIFOs in 32 bit mode It can with the right contents transfer one 32 bit word in and another out in the same clock cycle For example running at a FIFO clock speed of 100MHz the HERON FPGA12 can transfer 400Mbytes sec in at the same time as transferring 400Mbytes sec out The use of other clock speeds for the FIFOs will of course result in other maximum data rates DDR SDRAM Throughput The DDR SDRAM memory on the HERON FPGA12 is organised as 32 bit wide memory and is designed to operate at 200MHz The DDR
48. ardware Details HERON Module Type The HERON FPGA12 module implements all four of the HERON connectors which means it is a 32 bit module that can access all twelve of the possible HERON FIFOs For a complete description of the HERON interfaces signal definitions and connector types and pin outs refer to the separate HERON specification document This can be found on the HUNT ENGINEERING CD accessed through the documentation viewer or from the HUNT ENGINEERING web site at http www hunteng co uk The HERON FPGA12 does not have a processor outside the FPGA so does not normally assert the Module has processor pin as defined in the HERON specification This signal is however connected to an I O of the FPGA so that when the module is configured as a processor module that can be loaded using the HUNT ENGINEERING Server Loader it can assert this pin The HERON FPGA12 does not support C6000 processor JTAG so does not normally assert the Module has JTAG pin as defined in the HERON specification It is possible to connect the FPGA JTAG pins to this JTAG interface via the Control FPGA For this reason the control FPGA is connected to this pin so that it can drive it if this functionality is implemented The HERON FPGA12 has a serial bus so asserts the Module has serial bus pin as defined in the HERON specification The HERON FPGA12 has a 32 bit interface so asserts the 32 16 pin low Hardware Reset Before the
49. are Interface Layer to manage the FIFO clocking IO_L6P_GC_CC_LC_4 is driven with the DDR SDRAM clock input allowing a DCM to be used to generate all of the clocks required for the Hardware Interface Layer to manage the DDR SDRAM clocking IO_L8P_GC_LC_3 and IO_L1P_GC_LC_4 are driven by OSCO and OSC3 respectively This allows the correct frequency to be driven from an oscillator and the DCM to be used to distribute the clock with known phase The following GLCK signals are I O pins on Digital I O Connector A This allows the user to connect differential or single ended external clocks to these pins and have efficient routing to the DCM and Clock buffer resources of the FPGA These I Os can also be used as general purpose I Os if they are not used for clocks Other I Os can also be used to provide clocks to the FPGA but with less tightly controlled routing delays 42 HUNT ENGINEERING HERON FPGA12 USER MANUAL Xilinx I O name Xilinx pin ref Digital I O signal 1O_14P_GC_LC_3 B13 CONNA_0 IO L4N GC LC 3 B12 CONNA 1 IO L5P GC LC 3 A16 CONNA 2 IO L5N GC LC 3 A15 CONNA 3 IO L6P GC LC 3 A10 CONNA 4 IO L N GC LC 3 B10 CONNA 5 IO L7P GC LC 3 B17 CONNA 6 IO LN GC LC 3 A17 CONNA 7 IO L8N_GC LC 3 C12 CONNA 8 IO L4IN_ GC LC 4 AE12 CONNA 9 IO L2P GC LC 4 AC10 CONNA_10 IO L2N GC LC 4 AB10 CONNA II IO L3P GC LC 4 AB17 CONNA 12 IO L3N GC LC 4 AC17 CONNA 13 IO L4P GC LC 4 AF11
50. ble An option in the JTAG download software can cause the FPGA to be configured on completion of the PROM being programmed 11 HUNT ENGINEERING HERON FPGA12 USER MANUAL Clocking of the FPGA The Xilinx FPGA used on the HERON FPGA12 does not have a single clock input but rather it can use any one of its pins to provide a clock input This means you can have many sources of clocks each of which can be used inside your FPGA design You can even divide these clocks using flip flops or even multiply using digital clock manager DCM components Necessary clocks gt Output FIFO clock feedback Input FIFO clock lt feedback SDRAM clock Clock Options OSC3 100Mhz Ue ORCO gt Your FPGA design SDRAM CLK IN 200Mhz Digital I Os UMI0 1 2 amp 3 _ The simplest way to manage your FPGA design is to use just one clock throughout your design However the FPGA must drive both of the HERON FIFO clocks at a frequency that is suitable for your module carrier see the documentation for your module carrier for details of its restrictions The FPGA must also drive the SDRAM clock at a frequency suitable for the SDRAM 200MHz The FPGA may also need to use clocks for the digital I Os The frequency for these might be limited by the equipment that it is connected to or by the needs of your signal processing The needs for these clocks can only be determined by looking carefully at the needs
51. cabling supplied that suits your needs If your requirements change then HUNT ENGINEERING will be able to supply assemblies or component parts to meet your needs but a charge will apply DIGITAL I O n Connector Pin out The connector sits against the top surface of the PCB facing upwards away from the board Where n is the Connector letter A or B Differential Pairs The HERON FPGA12 uses a Virtex 4 device that supports differential signalling formats The allocation of pins on the I O connectors have been carefully chosen so that in most cases adjacent pins on an I O connector form the positive and negative halves of a differential pair This makes it possible to use up to 28 differential pairs as follows Xilinx name Xilinx pin Differential Pair Digital I O signal IO_L4P_GC_LC_3 B13 1P CONNA_0 IO L4N GC LC 3 B12 IN CONNA_1 IO L5P GC LC 3 Al6 2P CONNA 2 IO L5N GC LC 3 A15 2N CONNA 3 IO L6P GC LC 3 A10 3P CONNA 4 IO L6N GC LC 3 B10 3N CONNA 5 IO L7P GC LC 3 B17 4P CONNA 6 IO L7N GC IC 3 A17 4N CONNA 7 IO L8N GC LC 3 C12 CONNA 8 IO L41IN GC LC 4 AE12 CONNA 9 IO L2P GC LC 4 AC10 5P CONNA 10 45 HUNT ENGINEERING HERON FPGA12 USER MANUAL IO L2N GC LC 4 AB10 5
52. check that CCLK has been selected for the Start Up Clock This is the default used in the example projects provided Process Properties EZ General Options Configuration options Startup options Readback options Encryption options Property Hame Value Start Up Clock i Enable Internal Done Pipe Bo Done Output Events Default 4 Enable Outputs Output Events Default 5 Release WWrite Enable Output Events Default 6 Release DLL Output Events Defaut Novvait Match Cycle Default NovWait Cancel Default Help 34 HUNT ENGINEERING HERON FPGA12 USER MANUAL Files for PROMs mcs The Flash PROM on the FPGA12 can be programmed and reprogrammed via the JTAG chain using mcs files These files are generated by the Xilinx PROM File Formatter after the rbt file has been generated Please read the document Using iMPACT with FPGA modules for a detailed description of how to create the correct mes file for your design Power PC software The Xilinx EDK tools provide a GNU compiler that has been specially ported to the embedded Power PC core in the Virtex 4 devices There is also a port of the GNU debugger that can be used to develop your program There is a HUNT ENGINEERING document separate from this user manual that guides you through using those tools to develop and load a Power PC program with a HERON system HERON_FPGA Conf
53. ck both elements This specification which may be supplied in units of time or units of frequency will be automatically used by the tool to check that the circuit will run at the specified speed This leaves you free to focus on the functionality of the signals while the Xilinx implementation tools work on achieving your specified time constraints If at the end of your implementation the tools tell you that your timing constraints have been achieved then the combination of all setup hold and routing delays are such that your design will operate at the frequency you defined What this means for your design is that when you place a library component you need to consider whether signals are set high or low correctly on each clock edge note all library components ate positive rising edge clocked What you do not need to worry about is the timing issues of each signal beyond having applied a time constraint on to the clock net that is applied to those components and the connected logic Use of Clocks Because of the assumption that the design is a pipeline the development tools will allow you to enter a specification for the clocks used in the design This allows you to specify the frequency that you need the resulting design to operate at 30 HUNT ENGINEERING HERON FPGA12 USER MANUAL Simple designs will use only one clock and all parts of the design will use that clock It is usual for every part of the design to use the rising edg
54. d 9 USER PROGRAMMABLE FPGA WITH EMBEDDED POWER DU 10 SERIAL CONFIGURATION OF THE USER FPGA ocooccconcoconncononnononononononnonananan nono nanoronon nono rononnonnranan no nnciness 10 USERERLGA BORM ed Ales 10 CLOCKING OF THE EPOA Eed iaa 12 HERON FIFOS ease 13 DDRESDRAM EE 14 FEASH MEMORY eher 14 DIGITAL VO DEE 15 E DEE 15 MODULE AND CARRIER ID iy cssccstecs E E E EEEN 15 GENERAL PURPOSE LEDS reoot etnea n aS eera ARE E neeaae aa aa AEE Danni oasis nadar e 15 DONE LEDS raoiroi n e e iE R E E NE EE th aes 15 GETTING STARTED ON YOUR FPGA DESIGN oococconccccocosnnccccossanaccccncnnccocccnarass L7 WORKING THROUGH EXAMPEE Lian bp Ei 18 RreparinS ISE ee ZE eg 18 Copying the examples from the HUNT ENGINEERING CD 19 e 19 The Project s Functional Dorameterg ooo 19 Setting up the Configuration PACKAGE cccccccecccecsceseteseescetseeeetesecesecsessaecsaesseecseeeseeeseenseseseenseesees 20 User Timing CONST GINS 2 5ce ie seincsceekben iba deet Eege deefe 20 Creating the Bitstream for Example ooo 21 Simulating the Complete Desen 22 MAKING YOUR OWN FPGA DESIGN occccccconocccoconnoccccnononcccconocccococnnccccnncnncccccnnacos ZO SERAP INTERFACE edd eege deed Eed 23 HARDWARE INTERFACE LAYER vienen violino reir ici tue veh NEES ACEN 2 IMPORTAN Tiida ii dd ida 27 OTHER EXAMPLES vit A A A a le acid 28 HOW TOMAK A NPV DESIGN i5sscceressussensonseccensstes sasacssiesnesnedyesstuetenessdsipadacunseressestenitedsinsessertsestenenntop
55. e It is still difficult to get an accurate measure because you need to describe the real data values and timings to be able to estimate correctly When using the HERON FPGA12 at an ambient temperature of 50 C the bare package is capable of dissipating 2 9 Watts When using the heatsink we would offer fitted to the FPGA the power that can be dissipated becomes 3 24 Watts With both the recommended heatsink and fan the power that can be dissipated becomes 12 5 Watts The HERON FPGA12 power supplies are capable of delivering 4 0 Amps 1 2 Volts 4 8 Watts 4 0 Amps 2 5 Volts 10 Watts 4 0 Amps 3 3 Volts 13 2 Watts Total 28 Watts This is well above the bare package maximum power dissipation This means that the first limit on power consumption of the HERON FPGA12 is determined by the FPGA package It is always a good idea to have some airflow past the package and normally a Fan fitted to the Case of the PC is sufficient to provide this The dissipation limit of the package can be increased by fitting a heatsink and possibly a fan 5V and GND connections are provided next to the FPGA in case you need to power a local heatsink fan Depending on the performance of this heatsink your FPGA design could 38 HUNT ENGINEERING HERON FPGA12 USER MANUAL then reach the limit of the power supply circuits on the module In the unlikely event that this second limit is reached it will be necessary to modify the module to use external pow
56. e SDRAM clock input and will synchronise the internal FPGA logic correctly to that clock Different carrier boards have different requirements for the FIFO clocks If they can all be the same then this is the simplest case and a single clock input to the FPGA is needed If the rates of those clocks need to be different but can be derived from each other then the design can still be kept quite simple but sometimes it will be necessary to have several completely independent clocks presented to the FPGA To allow a large amount of flexibility the HERON FPGA12 offers a user oscillator socket There are also other possibilities like the Digital I O signals or the UMI pins of the HERON module Clocks inputs can be used directly in your FPGA design but Xilinx provide Digital Clock Managers DCMs These can be used for a number of purposes such as clock multipliers or to align the phase of an internal clock with that of a clock signal on an I O pin of the device This second way is used by the Hardware Interface Layer to guarantee data access times on some of the interfaces IO_L8P_GC_CC_LC_4 is driven from the buffered Output FIFO clock allowing a DCM to be used to synchronise the internal logic to that clock This is used by the Hardware Interface Layer to manage the FIFO clocking IO_L1P_GC_CC_LC_3 is driven from the buffered Input FIFO clock allowing a DCM to be used to synchronise the internal logic to that clock This is used by the Hardw
57. e of this clock This makes it very simple for the development tools to determine the maximum possible frequency that design could be used at Adding too much combinatorial logic between pipeline stages will reduce the maximum possible clock rate This gives rise to a hint If your design will not run fast enough add some mote pipelining to areas where lots of combinatorial logic is used Typically development tools will give a report stating the maximum clock rate that can be used in a particular design and will probably raise errors if that is slower than the specification that you have provided for the clock used in the design More complicated designs would use several clock nets which may be related in frequency ot phase or may be completely independent In such a design you must be careful when outputs from logic using one clock are passed to logic using a different clock It is often useful to add a FIFO which allows input and output clocks to be completely independent Possible Sources of Clocks As you can see from the section above an FPGA design may require one or more clock frequencies to achieve the job it needs to do How you implement your design governs the number and frequencies of the clocks you need The design of the module has been made to give you as much flexibility as possible but ultimately it is up to you which will be used On the HERON FPGA12 there are two possible Crystal oscillator modules and external clocks
58. el on the Vcco pins of an I O bank On the HERON FPGA12 the Veco is fixed at 3 3V for all of the Digital I Os NOTE VIRTEX 4 I Os ate not 5v tolerant If you wish to connect 5V input signals to the HERON FPGA12 it is possible to fit series resistors to the signals so that the input clamp diodes and the overvoltage protection devices can limit the FPGA input to 3 3V with the remaining input voltage to be dropped across the series resistors You can request these resistors to be fitted when you order your module LVDS It should be noted that Virtex 4 FPGAs don t support 3 3V LVDS but only 2 5V LVDS The input buffers for LVDS25 do not require Veco so are possible They even support the Differential Termination option of Virtex 4 However the LVDS25 output buffers require that the Veco is set to 2 5V This means that the HERON FPGA12 module cannot support LVDS output signals Using Digitally Controlled Impedance DCH The Virtex 4 architecture allows the use of DCI to control the impedance of certain I O pins Each bank of the FPGA uses a pair of resistors connected to the VRN and VRP FPGA that the FPGA uses to set the impedance of multiple drivers and receivers To use DCI the appropriate buffer must be placed in the FPGA design On the HERON FPGA12 there are 51R resistors connected to the VRN and VRP pins of each bank This means that the I Os on Digital I O connectors A and B can use DCI without changes to the board Different
59. er supplies for your system Choosing an Appropriate Heatsink and Fan Fitting a heatsink can increase the dissipation limit of the package and if fitting a heatsink alone does not increase the power dissipation enough then the next option is to use a heatsink together with a miniature DC fan to force air through the fins of the heatsink A heatsink made by HS Marston CP464 030 030 04 S 2 can be attached to the top of the FPGA either with a thermal adhesive or tape A 5Volt 25mm square miniature fan made by Multicomp KDE502PEB1 8 can be attached to the heatsink using a self adhesive fan gasket and will allow more power to be dissipated The heatsink and gasket 936 881 and fan 306 2545 are available from Farnell This makes the height of the FPGA and fan assembly 2 25 15 5 6 0 23 75mm above the surface of the HERON FPGA12 pcb or 31 35mm above the surface of the motherboard peb The thermal resistance of the heatsink alone is 10 C Watt The thermal resistance of the combined heatsink and fan is 2 C Watt How the Power Limit is Calculated From the Xilinx Virtex 4 Packing and pinout specification document UG075 we can see that the junction to ambient thermal resistance Oja has a minimum of 12 in still air The Oja value can be used to determine the maximum power that is safe to dissipate However in order to do this we need to choose a maximum junction temperature for correct operation and an ambient temperature for
60. esign but it also affects the use of clocks in the Hardware Interface Layer Set FCLK_G_DOMAIN to True if you have the same clock driving both FIFOs This is the default option for the Examples If you are unsure select this choice In that case you provide a frequency for that clock on the signal SRC_FCLK_G For module carriers like the HEPC9 HECPCI9 and HERON BASE2 this clock must be greater than or equal to 60Mhz and less than or equal to 100Mhz If you have another carrier card please check it s user documentation for the limits of it s FIFO clock frequency The signal FCLK_G must then be used in your FPGA design as the correct phase of this clock to sample the FIFO data with If you have different input and output FIFO clocks then select FCLK_G_DOMAIN as False and then you use the individual SRC_FCLK signals to drive the frequencies and the FCLK signals to clock your logic User Timing Constraints As with all FPGA designs it is necessary to apply some timing constraints to the design to ensure that the tools generate a design that will operate at the frequency that you require Example has these defined in the ucf file In the case of the provided examples you do not need to change any of the timing constraints When you make changes to the design however you may find that you introduce more clock nets that need to be added to the ucf file For more details on Timing Constraints please refer to the Xilinx tools documentation
61. hen go out showing that the control FPGA is ready to accept a configuration stream for the User FPGA After downloading a bitstream to the user User FPGA LED DONE should also go out 16 HUNT ENGINEERING HERON FPGA12 USER MANUAL Getting Started on your FPGA Design HUNT ENGINEERING provide a comprehensive VHDL support package for the HERON FPGA12 This package consists of a VHDL top level with corresponding user constraints file VHDL sources and simulation files for the Hardware Interface Layer and User VHDL files as part of the examples The Hardware Interface Layer correctly interfaces with the Module hardware while the top level top vhd defines all inputs and outputs from the FPGA on your module Users should not edit these files unless a special digital I O format is required see the later section Digital I O from the FPGA The file user_ap vhd is where you will make your design for the FPGA using the simplified interfaces provided by the Hardware Interface Layer Entire FPGA design VHDL top level top vhd User An user VHDL level Hardware Interface Layer Organisation of VHDL support for FPGA modules After synthesising your design you will use the Place and Route tools from Xilinx These tools will use the User Constraints File ucf to correctly define the correct pins and timing parameters You will need to minimally edit this file to have the timing constraints that you need but the
62. ial Termination DCI termination can be used for differential signals but it results in a parallel termination on each of the differential inputs That creates a path for supply current to flow in each of the terminations As more and more of these terminations is used it causes a significant power to be drawn from the power supply with the resulting heat dissipation issues that come with that The Virtex 4 architecture offers a differential termination option for differential signal formats which provided the correct termination without the increased power requirements For this teason it is recommended that the DIFF_TERM attribute is used to terminate differential inputs Refer to Xilinx documentation for full details of this attribute 44 HUNT ENGINEERING HERON FPGA12 USER MANUAL DIGITAL I O n Connector Type The Digital I O connectors ate surface mount 1mm pitch connectors They ate arranged as 25 pins in each of 2 rows It is supplied by Hirose and its part number is DF20G 50DP 1V 55 This connector has polarisation against incorrect insertion and mechanical retention of the mating half The mating connector is also supplied by Hirose and has part number DF20A 50DS 1C which requires crimp contacts part number DF20B 2830SCFA These crimps are only available from Hirose in large quantities and require special tooling Usually if you have explained at the time of ordering how you will be using your HERON FPGA12 module there will be
63. iguration Tool HUNT ENGINEERING provides a tool to allow you to load the FPGAs in your system with rbt files that you create or copy from the CD For details about using this tool refer to the Starting your FPGA development tutorial on the HUNT ENGINEERING CD The windows tool actually calls a program with command line parameters set according to your choices The program is HRN_FPGA exe which will have been installed on your DSP machine in the directory YHEAPI_DIR utils For help using that program directly type hrm_fpga h in a DOS box HUNT ENGINEERING HOST API The HOST API provides a consistent software interface to all HERON Module carriers from a number of operating systems While the FPGA development tools can only be run under Windows on a PC some can be obtained in Unix versions for a workstation It is possible to deploy your system from a number of different Host operating systems In these cases the HOST API and the FPGA loader tool can allow you to use your system even if you cannot make your FPGA development there Refer to the tutorials documentation and examples for the HOST API on the HUNT ENGINEERING CD HUNT ENGINEERING HERON API If you have C6000 DSPs in your system you can use HERON API to communicate with the FPGA modules via the HERON FIFOs Refer to the tutorials documentation and examples for the HERON API on the HUNT ENGINEERING CD 35 HUNT ENGINEERING HERON FPGA12 USER MANUAL H
64. inated erroneously 27 HUNT ENGINEERING HERON FPGA12 USER MANUAL Other Examples There ate some other examples source and bitstream files provided for the HERON FPGA12 on the HUNT ENGINEERING CD Follow Getting Started and then Starting with FPGA Choose General FPGA Examples and click on the directory for the fpga12 The examples are in the directories Memory_Test ex2 SDRAM_FIFO ex3 etc These examples have pdf documents that describe their function The second example Memory_Test is useful for users who wish to validate that the DDR SDRAM memory fitted to their module is good The third example SDRAM_FIFO is provided for users who need the SDRAM to behave like a big FIFO Please note that as with the examples any user work should be done in the user_ap section 1 e do not put your own logic into the hardware interface layer but simply include them into your own design This enables your design to be protected from hardware specific details like pin out and also allows you to benefit from any new versions that HUNT ENGINEERING might make available without having to re work your part of the design How to Make a New Design For any new design that you make it is important that you start from the examples provided on the HUNT ENGINEERING CD When making a new design for the HERON FPGA12 by starting from one of the examples you will already have a project that is correctly set u
65. ing courses exist which can help you acquire quickly the required skills and techniques Search locally for courses in your local language Preparing ISE Before beginning work with Examplel you will need to make sure ISE is properly installed In addition you should ensure that you have downloaded the latest service pack from the Xilinx website for the version of ISE you are using 18 HUNT ENGINEERING HERON FPGA12 USER MANUAL Copying the examples from the HUNT ENGINEERING CD On the HUNT ENGINEERING CD under the directory fpga you can find directories for each module type In the case of the HERON FPGA12 the correct directory is fpgal2v1 There ate two ways that you can copy the files from the CD 1 The directory tree with the VHDL sources bit streams etc can be copied directly from the CD to the directory of your choice In this case there is no need to copy the zip file but the files will be copied to your hard drive with the same read only attribute that they have on the CD In this case all files in the example directories need to be changed to have read write permissions Examplel camera examples and SDRAM example directories It is a good idea to leave the permissions of the Common directory set to read only to prevent the accidental modification of these files 2 To make the process more convenient we have provided the zip file which is a zipped image of the same tree you can see on the CD If you
66. is will result in the 8 bit address being written into the application FPGA using an address strobe then one or more data bytes being written to the application FPGA using a data strobe and qualified by a write signal It is therefore the responsibility of the application FPGA to support auto incrementing addresses if required by its function For a read request Master to FPGA module user read 09 gt address of requestor gt register address byte gt length byte In this way single or multiple bytes can be requested starting from the address given The reply will be FPGA module to original master user read response 10 gt module address gt data byte gt optional data byte This will result in the 8 bit address being written into the application FPGA using an address strobe then one or more data bytes being read from the application FPGA using a data strobe and qualified by the absence of write signal 57 HUNT ENGINEERING HERON FPGA12 USER MANUAL Appendix 2 FPGA Pinout for Development Tools The following is the pin out of the FPGA so that the signals can be connected in the Xilinx development tools Data Out FIFO Signal name FPGA Description pin DOO v21 HERON FIFO Data bit output DO1 V22 HERON FIFO Data bit output DO2 W25 HERON FIF
67. line It is possible to apply asynchronous logic to signals but the FPGA concept assumes that logic is between registers in the pipeline This pipeline gives rise to two things that you need to consider One is the maximum clock frequency that that pipeline can operate at and the other is the number of pipeline stages in the design As with any component in your FPGA design components from the HERON FPGA12 HIL operate synchronously That is any control or data signal that you connect to the library component must be generated from logic that uses the same clock signal that is connected to the library component Similarly logic that is connected to outputs of the library component will need to be clocked by the same clock signal For a conventional circuit design you would normally need to consider the signal delays from the output of one synchronous element to the input of the next element By adding up a clock to output delay from the output of the first element adding routing delays and the setup to clock delay for the input of the second element you would have a timing figure to match against the clock period If the calculated figure is found to be too large the circuit must be slowed down or logic must be simplified to reduce the calculated value to one that fits the requirements When creating a design using the Xilinx development tools however you only need to add a timing specification to the clock net that is used to clo
68. memory is 128Mbytes The DDR SDRAM requires a specific sequence of events to be completed after power up before the memory can be accessed The DDR SDRAM also requires a constant memory refresh command However the DDR SDRAM should always be used via the DDR SDRAM controller in the Hardware Interface Layer or a Power PC DDR controller These controllers will automatically take care of the power up control sequence and issuing of memory refresh commands All you will to do in your design is simply read and write data through the read and write ports of the DDR SDRAM controller in order to read and write the external DDR SDRAM memory 41 HUNT ENGINEERING HERON FPGA12 USER MANUAL User FPGA Clocking As has been said elsewhere in this manual the clocking of the FPGA can be a complex issue The FPGA does not have such a thing as a clock pin but rather can use an I O pin as a clock for almost any part of the FPGA design Your design will be simpler if a single clock is used or even if there are several clocks used but they are derived from each other However the FPGA must drive the input and output FIFO clocks and the SDRAM clock In each case the logic that interfaces to each must be clocked from the same clock as the interface When the HERON FPGA12 is shipped there is a 100MHz oscillator fitted to User OSC3 The DDR SDRAM interface should always be run at 200MHz The DDR SDRAM controller will automatically generate 200MHz from th
69. n network uses a series resistor of 22R and parallel resistor to the termination voltage Vtt of 47R Signals are routed such that all signals within a byte lane are kept together For each signal in a byte lane the PCB trace length has been controlled to keep total trace lengths close to being equal Where resistor packs ate used these are grouped together to cover signals within one byte lane A byte lane consists of 8 bits of data one data strobe signal and one data mask signal as follows Byte Lane 0 sdram_a_dq lt 7 0 gt sdram_a_dqs lt 0 gt sdram_a_dm lt 0 gt Byte Lane 1 sdram_a_dq lt 15 8 gt sdram_a_dqs lt 1 gt sdram_a_dm lt 1 gt Byte Lane 2 sdram_a_dq lt 23 16 gt sdram_a_dqs lt 2 gt sdram_a_dm lt 2 gt Byte Lane 3 sdram_a_dq lt 31 24 gt sdram_a_dqs lt 3 gt sdram_a_dm lt 3 gt It is important when creating the DDR interface logic inside the FPGA that the byte lane groups are kept All signals within one byte lane must be kept together in order to be able to control the timing requirements of DDR operation at 200MHz 67 HUNT ENGINEERING HERON FPGA12 USER MANUAL The DDR Clock Scheme The most important design element of the DDR interface is the control of DDR clock signals There are several clock signals that must be generated within the FPGA and the frequency and phase of those signals must be very tightly controlled in order to enable operation at 200MHz Described below is
70. nactive state by 10K resistors so this 50K will have no effect However the UDPRES signal does not and setting this signal low will cause your whole board to be reset Thus it is important that the UDPRES pin is driven high by the FPGA if it is not being used It is also advised to do the same with the LED pins to prevent them becoming illuminated erroneously 50 HUNT ENGINEERING HERON FPGA12 USER MANUAL Fitting Modules to your Carrier Fitting HERON modules to your carrier is very simple Ensure that the module carrier does NOT have power applied when fitting modules and normal anti static precautions should be followed at all times Each HERON slot has four positions for fixing pillars O Primary pillars HERON module The Carrier card will probably only have spacing pillars fitted to the primary location for each HERON slot The pillars for the secondary locations will be supplied as an accessory The reason for this is that the legacy GDIO modules cannot be fitted if the secondary pillars are in place The HERON modules are asymmetric about their connectors so if a module is fitted entirely the wrong way round the module does not line up with the markings on the carrier card In particular notice the triangles on the silk screen of the HERON modules and the HERON slots of the carrier card These should be overlaid when the module is fitted The HERON connectors are polarised preventing incorrect insertion So if more than
71. ng an empty FIFO from being propagated through the design The actual method used will depend on the needs of the design When data is written to the HERON Output FIFOs there are flags to indicate when it is possible to write new data Writing to the FIFO when the flags indicate there is no room will result in data being lost from your system Thus your design must not assert the Write enable signal when the Full Flag FF is asserted 31 HUNT ENGINEERING HERON FPGA12 USER MANUAL Pipeline Length or latency The latency of your design will be determined by the length of the pipeline used in your FPGA design The simplest way to determine this is to count the Flip Flops in your data path but whichever tools you are using might provide a more elegant way For example the Core Generator will state the pipeline steps used with each core and will even let you specify a maximum in some cases UO from the FPGA In addition to the FIFO SDRAM and HSB interfaces of the HERON FPGA12 there ate some General purpose Digital I O connectors and some options for serial interfaces The use of these interfaces will be specific to a particular design so they have not been included in the examples supplied The pins to use are defined in the top vhd and the locations are already defined in the ucf files The choice of buffer type and the time specs of those interfaces must be taken care of by the designer DSP with your FPGA The FPGA
72. ng the send bitstream command over HSB with a zero length bitstream When the FPGA configuration file is downloaded to the PROM via JTAG it is possible to select Load FPGA on the Program Options then when the configuration has been downloaded to the PROM the FPGA is automatically configured This is a useful option in systems that do not have a serial configuration bus More information on this can be found in the Downloading Files via JTAG section of this document The module will have a JTAG connector fitted that is a Hirose 1mm 5x2 connector of part number DF20G 10DP 1V 55 The mating half that is required for cabling is also a Hirose part the housing is DF20A 10DS 1C and crimp part number DF20B 2830SCFA The pinout is OO GND 4 OO 3 3 3V TDO 6 POO 5 TCK TMS 8 PO O 7 TDI OO Top view of connector The cable supplied is as follows AA RARO Which can be fitted to a Xilinx JTAG cable such as Xilinx parallel cable 4 or USB cable and used to connect to the PROM and the FPGA on the module Boot from PROM Jumper The Boot from PROM BFPROM jumper is used to select if the FPGA boots from the ROM or via HSB For normal operation HSB the jumper should NOT be fitted but actually even if it is the HSB download will overwrite the FPGA contents that were originally loaded from the PROM ra A L P LN CJ CO OO 49 HUNT ENGINEERING HERON FPGA12 USER MANUAL Uncommitted Module Interco
73. nnects There are some Uncommitted Interconnect signals defined by the HERON specification which are simply connected to all modules These are intended to connect control signals between modules for example a processor module can via software drive one of these signals with one of is timer outputs Then if an I O module can accept its clock input from one of these signals it is possible to implement a system with a programmable clock There will be other uses for these signals that are module design dependent The HERON FPGA12 connects these signals to FPGA I O pins allowing the user configuration to use these if required General Purpose LEDs There are some general purpose LEDS on the HERON FPGA12 which are driven by the FPGA The LEDs labelled 0 to 4 are driven by the FPGA pins LEDO to LED4 respectively The LED will illuminate when the FPGA drives the pin low Other HERON module signals There are many signals that are connected between the FPGA on the HERON FPGA12 and the HERON module connectors Most of these signals will only be used by advanced users of the HERON FPGA12 The FPGA pinning of these signals is shown in the appendix of this manual and their use in a system is described in the HERON module specification found on the HUNT ENGINEERING CD and Web Site The FPGA sets any I O pins of the device that are not listed in the design to have a 50 150K pull down Most of the HERON module signals are pulled to their i
74. nts STOP HERE and verify the UCF file selected for the project You can download this file on your FPGA board and see how it wotks See a later section of this manual Note that the user_ap level includes a very large counter that divides the main system clock and drives the LED 4 It is then obvious to see if the part has been properly programmed and downloaded the LED should flash The hardware will probably require a reset after configuration before the LED starts to flash If the LED does not flash we recommend that you shut down the PC or reprogram the device using a safe bitstream Otherwise some electrical conflicts may happen see below Possible causes for the device failure to operate are 1 Wrong or no UCF file This happens for example if you select the XST version of the UCF with a Leonardo Spectrum or Synplify synthesis The pin assignment for all the vectors busses will be ignored and these pins will be distributed in a quasi random fashion 21 HUNT ENGINEERING HERON FPGA12 USER MANUAL 2 Wrong parameters in the CONFIG package 3 Design Error If nothing seems obvious rerun the confidence tests then return to the original example 1 Simulating the Complete Design To generate the bitstream as above you did not need to do any simulation However if you start modifying the provided examples and add your own code verification can soon became an important issue If you need to simulate your de
75. of your system Clock Options OSC3 100Mhz Necessary clocks User OSCO Output FIFO clock SDRAM CLK IN 200Mhz feedback Digital I Os Input FIFO clock UMI 0 1 2 amp 3 feedback SDRAM clock Example design If these clocks cannot be the same then the next best situation is to have one clock derived from the other In that way the relationship between the clock edges will be known The most difficult case for your FPGA design is to have many clocks from different sources that are all used in the same design Then you must carefully manage signals that cross from one clock domain to another This can be handled by FIFOS or by multiple registering to prevent metastability problems Refer to texts on digital design to understand these issues Our standard examples actually use separate clock domains for the HERON FIFOs and the DDR SDRAM You can see in those standard designs that FIFOs have 12 HUNT ENGINEERING HERON FPGA12 USER MANUAL been used to pass data between those two clock domains The HERON FPGA12 provides a highly flexible set of choices for the clocking of the FPGA The HERON FPGA12 has a socket for a 3 3V user oscillator Default shipping state is to have a 100MHz oscillator fitted to one of the surface mount sites driving 100MHz on UserOsc3 This is a standard commercial oscillator module that is 100ppm accuracy If you require higher accuracy clocks then you should use one of the other clock sources
76. ovided by HUNT ENGINEERING includes a VHDL component that interfaces user logic within the FPGA to external Double Data Rate DDR SDRAM HUNT ENGINEERING recommend that all users who wish to access SDRAM do so through the interface component HE_DDR that is provided for the HERON FPGA12 This component handles all SDRAM management including initial memory set up routines auto refresh and burst read and write memory access For those usets who need to create their own tailor made interface to DDR SDRAM this appendix is provided to detail all of the major design points that must be considered when doing so How Memory is Connected to the FPGA The HERON FPGA12 has a single bank of DDR SDRAM 128Mbytes in size The bank is built from two pieces of 512Mbit Micron SDRAM The SDRAM part that has been used is Micron part number MT46V32M16TG 5B The SDRAM signals connected to the FPGA are FPGA Signal Name DDR Function Signal Direction sdram_a_a lt 12 0 gt 13 bit Address FPGA Output sdram_a_dq lt 31 0 gt 32 bit Data Bi directional sdram_a_dqs lt 3 0 gt 4 bit Data Strobe Bi directional sdram_a_dm lt 3 0 gt 4 bit Data Mask FPGA Output sdram_a_ba lt 1 0 gt 2 bit Bank Address FPGA Output sdram_a_ras RAS Command Input FPGA Output sdram_a_cas CAS Command Input FPGA Output sdram_a_we WE Command Input FPGA Output sdram_a_clk p Positive Clock Input FPGA Output sdram_a_clk_n Negative Clock Input FPGA Out
77. p to use the supplied Hardware Interface Layer The project will already include the correct settings and user constraints In fact in all situations you should start development from one of the examples on the HUNT ENGINEERING CD even if you intend to develop the FPGA in a way that is completely different to any of the examples In the case where you are to make a new design that does not match a standard example you should start development from Examplel and add your own logic in place of the existing Examplel VHDL By doing this you will automatically inherit the proper ISE settings user constraints and project structure When your are creating a new design from one of the standard CD examples you will need to be sure that the version of ISE design tools you are using matches the version of ISE for which the example projects were created If you are using a different version of ISE then you must work through the HUNT ENGINEERING application note Using Different Versions of ISB In developing new VHDL there are proper training courses that exist to help you quickly acquire the required skills and techniques Search locally for suitable training on these subjects You may also consider sub contracting part or whole of the new FPGA design 28 HUNT ENGINEERING HERON FPGA12 USER MANUAL Inserting your own Logic When making a new design you will create and insert your own logic inside the USER_AP module From here you can inte
78. packs are fitted on the HERON FPGA12 and allow a series resistor in each of the I O lines of the Digital I O connectors The standard build of the HERON FPGA12 is to fit OR for the serial resistor packs making the Digital I O NOT 5V tolerant 100R or other available value can be requested if necessary for a particular application The resistor packs are labelled in the photograph and the table gives the relationship to the Digital I O connector and signals O ooo oo oo0boo 9000 DIODOS FODIVOIO YY o ooo oa00 a Ko 20000000 o o ES o oo HERON FPGA12 Digital I O resistor packs AO A A0 A1 A2 A3 BO B B0 B1 B2 B3 Al A A4 A5 A6 A7 B1 B B4 B5 B6 B7 A2 A A8 A9 A10 A11 B2 B B8 B9 B10 B11 A3 A A12 413 A14 A15 B3 B B12 B13 B14 B15 A4 A A16 A17 A18 A19 B4 B B16 B17 B18 B19 47 HUNT ENGINEERING HERON FPGA12 USER MANUAL AN A A20 A21 A22 A23 B5 B B20 B21 B22 B23 AG A A24 A25 A26 A27 B6 B B24 B25 B26 B27 B7 A amp B A28 A29 B28 B29 Voltage Levels The HERON FPGA12 has the option of having series Resistors fitted in all I O lines The FPGA side of these resistors is connected to the over voltage protection which for the FPGA12 is set at 3 3V Fitting 100R series resistors allows the module to accept 5V or 3 3V signals without damaging the FPGA The standard build of the HERON FPGA12 is to fit OR for these resistor pack
79. provided by Xilinx that help you to use the architecture including the embedded Power PC HUNT ENGINEERING provides an application note separate from this user manual that guides you through the use of the embedded Power PC in a HERON system Serial Configuration of the User FPGA The HERON FPGA12 usually has the configuration of the user FPGA downloaded using the HERON module s serial configuration bus This allows the use of standard configurations as supplied on the HUNT ENGINEERING CD or of user defined configurations without the need to return the module to the factory It is imagined that as the standard set of functions grows that they be made available to users of HERON FPGA modules via the HUNT ENGINEERING web site or CD update requests Also HUNT ENGINEERING will have the possibility to provide semi custom configurations for a charge via email USER FPGA boot ROM As an alternative to the serial configuration download it is possible to configure the FPGA from a Flash based configuration PROM However if a system is being deployed with a 10 HUNT ENGINEERING HERON FPGA12 USER MANUAL host machine such as a PC it might be preferable to continue to use the serial configuration method as this will make in field upgrades and bug fixes simpler to deploy The PROM fitted to the FPGA12 is Flash based XCFO8P and can be programmed and re programmed using a Xilinx JTAG cable such as the Parallel Cable 4 or the USB ca
80. put sdram_clkin none FPGA Input There is a 14th address connection so that in the future 1Gbit DDR memories could be fitted For all of the signals listed in the table above it is important that they are placed on the correct pins of the device To ensure this is always done the pin out information supplied in the User Constraint Files of the HUNT ENGINEERING examples must be used according to the signal names presented This information is also repeated in Appendix 2 of this document 66 HUNT ENGINEERING HERON FPGA12 USER MANUAL When connecting to the DDR signals it is very important that the correct Xilinx Select I O format is used For the 200MHz clock source input the correct I O standard is LVTTL For all FPGA DDR signals that ate outputs only the correct I O standard is SSTL2_1 For all FPGA DDR signals that are bi directional the correct I O standard is SSTL2_11 On the HERON FPGA12 PCB all of the signals in the following table are routed directly between the FPGA and memory with no other components connected to the signal Directly Connected Signals sdram_a_a lt 12 0 gt sdram_a_ba lt 1 0 gt sdram_a_ras sdram_a_cas sdram_a_we For the clock signals sdram_a_clk_p and sdram_a_clk_n the 32 bits of data 4 bits of data strobe and 4 bits of data mask signals are routed using a termination network suitable for SSTL2 Class II This terminatio
81. quites a DCM of which we only have four to choose from This will leave one less DCM free for other design requirements Secondly multiplication with a DCM will add significant jitter to the original signal For DDR memory this jitter is too large The HERON FPGA12 has a 200MHz clock source with very low jitter driven onto the FPGA It is therefore strongly recommended that all clock schemes use this signal as the 200MHz clock source for DDR interfacing This signal is sdram_clkin In order to meet the control signal timing requirements at the memory the HUNT ENGINEERING clock scheme uses two clock signals that have a phase difference of 180 degrees The first clock signal clk0 is used to create the DDR clock input signal The second clock signal c1k180 is used to clock control signals onto the memory The signal c1k180 forms the main system clock for controlling DDR interface operation inside the FPGA The signal wclk is used to clock data written to memory The phase difference between the c1k180 signal and wclk signal must be controlled in order to meet data set up and hold times The signal c1k180 is used to clock data received from memory For read data the phase difference of the data must be controlled through the use of Virtex 4 IOB Delay components in order to meet data set up and hold times 68 HUNT ENGINEERING HERON FPGA12 USER MANUAL The following diagram shows how the 200MHz clock source sdram_clkin is
82. rface to the HERON FIFOs the SDRAM the HSB and the general purpose digital I Os When these interfaces are simple you may code the proper logic directly in the USER_AP module For more complex interfaces you may code separate entities in separate source files and instantiate these entities within USER_AP as was done in the Examples Important the first thing to edit in the user_ap vhd file is the package section where generic parameters are set to match your configuration and your design Important The HE_USER interface cannot be left entirely unconnected If you have a design that does not use the features of this interface you must be certain to connect the following The Clock of the HE_USER must be running The inputs MSG_SEND MSG_SEND_ID MSG_LAST_BYTE and MSG_CS must be connected to 0 The MSG_READY must be connected to 1 Special format Digital I Os The top level defines all of the I O pins from the FPGA Some of them are not used in the examples but have buffers instantiated in the top vhd Some of those pins can have alternative signal formats that require a different Xilinx primitive to be instantiated for the buffers Refer to the hardware details section of this manual to learn which pins are suitable for which use If the buffers that are already instantiated in top vhd usually LVTTL are suitable for your needs then there is no need to modify top vhd you can simply use the signals that are connected as po
83. rts to the user_ap file If you need different buffer types then it is necessary to edit top vhd The method to do that is Make a copy of the original TOP vhd file from Common and work on this copy Each I O pin has a buffer type instantiated in top vhd Edit the instantiation to use the proper Xilinx Buffer primitive You may sometimes have to insert attributes in the UCF file to qualify the IO Modify the User_Ap entity to make these signals visible Add the signals in the User_Ap instantiation port map User Timing Constraints As with all FPGA designs it is necessary to apply some timing constraints to the design to ensure that the tools generate a design that will operate at the frequency that you require These will be defined in the ucf file The ucf file provided as a template has some timing constraints already but when you make changes to the design you may find that you introduce more clock nets that need to 29 HUNT ENGINEERING HERON FPGA12 USER MANUAL be added to the ucf file For more details on Timing Constraints please refer to the Xilinx tools documentation Hints for FPGA Designs Having said that we cannot support you in making your FPGA design we always try to make your development easy to get started so this section outlines some things that you need to think about The FPGAs are basically synchronous devices that is they register data as it passes through the device making a processing pipe
84. s making the Digital I O NOT 5V tolerant This allows the Digital I O connectors to support any of the voltage formats provided by the Virtex 4 with a Veco of 3 3V 100R or other available value can be requested if necessary for a particular application but this precludes the use of some of the other I O standards supported by the Virtex 4 Differential Termination The Virtex 4 FPGA has the possibility to add differential termination between input pairs as an option in the configuration With previous FPGA families the only option available was to use parallel termination which raises the FPGA power consumption significantly so there were differential termination resistor packs offered by the module design The addition of the differential termination in the FPGA means these resistor packs are not necessary for the HERON FPGA12 ESD Protection All of the Digital I Os are protected against Electro Static Discharge and over voltage The devices used are Harris SP720 or SP723 parts This protects the inputs to 1EC1004 2 level 4 and provides over voltage limiting to the range 0 to 5V 48 HUNT ENGINEERING HERON FPGA12 USER MANUAL Using the JTAG Programmable Configuration PROM The module has been built with a JTAG programmable FLASH based PROM for the user FPGA so that your FPGA design can be programmed into this PROM Then the user FPGA can be configured with your FPGA design on power up and re configuration can be forced usi
85. sdram_a_dm lt m gt mask falling d lt m gt D1 welk co wclkb cl FDDRRSE When data is sent from the FPGA to the external memory the FPGA must drive the data strobe signal DQS The timing relationship created between the data and the data strobe is very important as the memory device will use the DQS signal to clock data onto the device The HUNT ENGINEERING DDR interface controls the DQS signal during data writes as follows ER DO Q sdram_a_dqs lt m gt vo D1 clko co c1k180 CI FDDRRSE sdram_a_dq lt n gt read rising data lt n gt read falling data lt n gt C1k180 IDDR The IDELAY component is used to control the read data timing An IOBDELAY value of 33 is required for all DDR data inputs 70 HUNT ENGINEERING HERON FPGA12 USER MANUAL Controlling Vref Generation DDR memory uses the general purpose memory bus standard SSTL2 SSTL2 requires differential amplifier input buffers and push pull output buffers The SSTL2 differential amplifier input buffer stage has two inputs Vref and the input signal Vref must be set at 1 25V and the input signal must vary within OV and 2 5V The HERON FPGA12 generates both the Vtt termination supply voltage and the Vref input reference voltage The Vref signal is connected to all Vref pins of the DDR memory and all Vref pins of FPGA bank 8 71 HUNT ENGINEERING HERON FPGA12 USER MANUAL
86. sign you will need to install a VHDL simulator such as ModelSim available in Xilinx Edition Personal Edition or Special Edition The example projects provided on the HUNT ENGINEERING CD include simulation files that provide a starting point for simulating your own design If you wish to work through the simulation examples provide please read the document Simulating HERON FPGA Designs 22 HUNT ENGINEERING HERON FPGA12 USER MANUAL Making your own FPGA Design The actual contents of the User FPGA on the HERON FPGA12 are generated by the user While making this development requires some knowledge of Digital Design techniques it is made quite simple by the development environment that you use We recommend the Foundation ISE series software available from Xilinx because that is what we use at HUNT ENGINEERING and any examples and libraries we provide are tested in that environment However there are other tools available from third parties that can also be used The use of VHDL sources for our Hardware Interface Layer and examples means that virtually any FPGA design tool could be used Any development tool will eventually use the Xilinx Place and Route tool where the user constraints file that we supply will ensure that the design is correctly routed for the module There are application notes on the HUNT ENGINEERING CD that describe how other tools might be used The best way to learn how to use your development tools is to follo
87. t are different from ISE titled Using VHDL tools other than ISFE The example is quite simple but demonstrates the use of the interfaces found in the Hardware Interface Layer supplied with the module The example is supplied in two ways Firstly there is a ready to load bitstream supplied in the Hunt Compressed Bitstream file format or hcb format This is the file format used by the HUNT ENGINEERING configuration tool Secondly there is an examplel project supplied for ISE enabling the design to be rebuilt and a new bitstream downloaded The bitstream file is provided to allow you to load the example1 onto the hardware without having to re build it This is a useful confidence check to see if any problems you are experiencing are due to changes you have made or the way you have built the design If the bitstream from the CD fails to behave then the problem is more fundamental To make things easier we have created the proper ISE project files for the examples Using these projects will allow you to run the complete design flow from RTL VHDL source files to the proper bitstream ready to download on your Heron FPGA board No special skills are required to do this However if you want to write your own code and start designing your own application you must make sure that you have acquired the proper level of expertise in VHDL language Digital Design Xilinx FPGAs ISE environment and design flow Proper train
88. ted is calculated as follows P T a P 85 50 0 7 01 10 P 3 24 Watts The same calculation can be repeated when using a heatsink and fan by replacing the Osa figure for that of the combined heatsink and fan When using a heatsink and fan combination with Osa of 2 C Watt the maximum power that can be dissipated is calculated as follows P T Oa P 85 50 0 7 0 1 2 P 12 5 Watts 40 HUNT ENGINEERING HERON FPGA12 USER MANUAL FIFOs The HERON FIFO connections are shown in the table of FPGA pin out The timing of the signals can be found in the HERON module specification which is on the HUNT ENGINEERING website and CD The design implemented in the user FPGA MUST drive a constant clock onto the FIFO clock pins The clock driven by the FPGA on O P FIFO clock and I P FIFO clock is buffered with an LVT245 buffer that has enough current drive for the carrier board clock signal The actual phase of the clock on the FIFO will be the same as the inputs on the GCLK pins so DLLs can be used to use that same clock to drive logic in the FPGA There may be a minimum and maximum frequency imposed by the module carrier that the module is fitted to However it is not necessary to look up any of this information as we supply Hardware Interface Layer VHDL that guarantees to correctly access the HERON FIFOs DDR SDRAM The DDR SDRAM bank on the HERON FPGA12 is organised as a 32 bit wide memory bank of 32M locations In total the
89. the clock scheme used by HUNT ENGINEERING Although users are free to change the clock scheme understanding this clock scheme will help in understanding high speed DDR operation In order to read and write DDR SDRAM three clock signals are required by the system One clock signal must be generated to drive the input clock pin of the external DDR memory A second clock signal must be generated to clock control signals out of the FPGA such that they meet the set up and hold requirements at the memory The third clock signal is needed to time write data onto the memory Por the HERON FPGA12 the control signal clock is also used to receive read data from the memory Given the control data data mask and strobe connections that exist on the PCB between FPGA and memory there will be specific phase differences required between each of these four clock signals for data transfer to work correctly The first timing consideration to meet is that a clean free running 200MHz clock signal is provided to the external DDR memory This clock signal must have as low jitter as possible With a clock period of 5ns any jitter value in the order of 100 s of picoseconds will have a significant effect on data timing On the HERON FPGA12 a 200MHz clock signal could be generated in many ways One option might be to use a lower frequency clock inside the FPGA and use a DCM to multiple that frequency to obtain 200MHz This option has two drawbacks Firstly it re
90. the environment in which the Virtex 4 FPGA is to be used In fact the particular ambient temperature Ta and desired maximum junction temperature Tj max will vary from application to application The figures that have been given for the power dissipation have been based on an ambient temperature of 50 C and a maximum junction temperature of 85 C When choosing a maximum junction temperature it is important to understand that for commercial grade Virtex 4 silicon the speed grade information must be derated beyond 85 C and therefore this is the value we have chosen for the calculations presented here This figure can be raised if you use appropriately derated speed information when building your own design For a Virtex II 4 without heatsink or fan the maximum power that can be dissipated is calculated as follows P T 0j P 85 50 12 P 2 9 Watts When adding a heatsink the equation must be modified such that Oja reflects the combined thermal resistance of FPGA and heatsink In this situation Oja is calculated as follows Oja Ojc Ocs Osa Where Ojc is the junction to case thermal resistance of the FPGA Ocs is the thermal resistance of the adhesive assumed here as 0 1 C used to fix the heatsink and Osa is the thermal resistance of the heatsink For the FF668 package Ojc is 0 7 C Watt 39 HUNT ENGINEERING HERON FPGA12 USER MANUAL For a Virtex 4 with heatsink rated at 10 C Watt the maximum power that can be dissipa
91. unzip this archive to a directory of your choice you will have the file permissions already set correctly Opening the Example1 Project Let us start with Examplel In the tree that you have just copied from the CD open the Examplel sub directory You should see some further sub directories there ISE holds the ISE project files Src holds the application specific Source files Sim holds the simulation scripts for ModelSim Leo San holds the synthesis scripts for Leonardo Spectrum and Synplify users You may ignore this directory in this chapter Open the Xilinx ISE Project Navigator If a project pops up from a previous run then close it Use File gt Open project Select Example1 ISE XXXXX ise and click on the Open button After some internal processing the Sources window of the Project Navigator will display the internal hierarchy of the Example1 project If you are encountering errors at this stage you should verify that The example files have been correctly copied onto your hard disk and especially the Common and ExamplellSrc directories The correct version of ISE has been successfully installed Be sure to have installed XST VHDL synthesis and the support for the Virtex II Pro family The Project s Functional Parameters Double click on user_ap1 in the Sources window This opens the VHDL colour coded text editor so that you can see the part of the project where you can enter your own design
92. ut FLASH Write Enable FLASH_OE Out FLASH Output Enable FLASH_RP Out FLASH Reset Power Down FLASH_VPEN Out FLASH Program Enable FLASH_STS In FLASH Status DDR SDRAM I F DDR_A_USER_CLK Out DDR Pott A User Clock Source DDR_A_USER_RST Out DDR Port A Data Count User Reset DDR_A DATA COUNT In DDR Port A Data Count 31 0 DDR_A_WR_DATA 71 0 Out DDR Port A Write Data DDR_A_WR_ADDR 24 0 Out DDR Port A Write Address DDR A WR _ADDR_ Out DDR Port A Write Address Enable WEN DDR_A WR _ADDR_FF In DDR Port A Write Address Full DDR_A WR AIDDR Ab In DDR Port A Write Address Almost Full DDR A WR RISE WEN Out DDR Port A Write Rising Data Enable DDR_A_WR_RISE_FF In DDR Port A Write Rising Data Full DDR_A_WR_RISE_AF In DDR Port A Write Rising Data Almost Full 26 HUNT ENGINEERING HERON FPGA12 USER MANUAL DDR_A_WR_FALL_WEN Out DDR Port A Write Falling Data Enable DDR_A_WR_FALL_FF In DDR Port A Write Falling Data Full DDR_A_WR_FALL_AF In DDR Port A Write Falling Data Almost Full DDR A WR DN WEN Out DDR Port A Write Data Mask Enable DDR A WR DM Fb In DDR Port A Write Data Mask Full DDR A WR DM AF In DDR Port A Write Data Mask Almost Full DDR_A_RD_DATA 63 0 In DDR Port A Read Data DDR_A_RD_ADDR 24 0 Out DDR Port A Read Address DDR_A_RD_ADDR_WEN Out DDR Port A Read Address Enable DDR_A_RD_ADDR_FF In DDR Port A Read Address Full DDR_A_R
93. w any tutorials provided with them or to take up a training course run by their vendors ALL NEW PROJECTS SHOULD START FROM ONE OF THE PROVIDED EXAMPLES that way all of the correct settings are made and files included Your design should take place entirely within the User Ap level except in the case of needing to change the I O formats of the Digital I Os in which case it is necessary to minimally edit the top vhd file see a later section in this manual for details It is assumed that you are able to use your tools and follow the simplest of Digital Design techniques HUNT ENGINEERING cannot support you in these things but are happy to field questions specific to the hardware such as how could I trigger my A D from a DSP timer or How can I use the FIFO interface component to do User_Ap Interface This section describes the Interface between the User_Ap central module or entity using VHDL terminology and the external Interface hardware This is the part where you connect your FPGA design to the resources of the module In other words 1 The Clocks system 2 How your application can communicate with the external world Digital I Os HSB interface FIFOs and SDRAM You need to understand this interface in order to properly connect your processing logic The complete FPGA project consists of a Top level in which many sub modules entities are placed mstantiated and interconnected One of these modules is

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