CATCH-X Users Manual
Contents
1. SW2 SW1 x 2 e JNS S LINK LSC e F3 x F7 St i e lo ri CATCH Mezzanine Card JN1 JN2 F1 ASYNC JP28 F6 Figure 4 Positions of fuses jumpers and switches on CATCH X 22 5 Appendix 5 1 CMC HOTlink The CMC HOTLink cards serve as a general interface to the front end boards e Each CMC cards connects up to four front end boards e Receive data through HOTLink deserialiser chips at a maximum rate of 40 MByte s on each of the four channels e Convert data from 8 bit HOTLink transmission format to 24 or 32 bits 1 word depending on front end board e Word boundaries are automatically resynchronized at each received SYNC character e The most significant byte is received first bits 31 24 e Receive errors are marked by special error codes e Store data in four independent 1k x 4byte FIFOs for final event building e Maximum CMC output rate 160 MByte s 5 1 1 Connector and LEDs Each CMC HOTLink has four RJ 45 connectors for CAT5 cable Table 17 to the front end board The ports are number from top to bottom 1 to 4 Details on the connection can be found in Ref 5 The four red LEDs correspond to port 1 to 4 counted from left to right They are lit in case of errors are transmitted through the cable During normal operation the LEDs are off Table 17 RJ 45 front end board connector Pin C 0 N EH Oo N eA Ot 5 1 2 Data2. Ju a EISE Ct i p Grand ni FFB Be 9v E 0 PEN Im SS Bed o HE Q C BEEEEE rese o 25 eu s dese SX AB HE Q Ss O E 5 a c mm ae J Q Ee S e ES a ER on lt c c E c OY OU OY OY GE Aaa BY Co Col Co Co GO DO DO DO DO RO N CO Od BY DO CM CO GD BY dO Ol CO GD BY dO olo MY rojo pru 19 Er REH 5 RE SECH BEJ SE EA 39 ar CS CS ar SE ECH CS CS Sa SH ar 65 N 20 4 3 Power and Fuses The board uses 5V 12V and 12V from the VME P1 and P2 connector The voltages 12V and 12V are only provided for the CMC board and not used by the motherboard A DC DC converter produces 3 3V from the 5V supply The types of the different fuses are given in table 16 while its positions on the CATCH X is shown in figure 4 Table 16 Fuses Name Value Voltage Used for F1 250mA 5V FPGA JTAG CMC JTAG F2 250mA 5V FGPA PROG CPLD JTAG F3 5A 5V VCC F4 05A 4 12V CMC F5 0 5 A 12V CMC F6 0 5 A 5 V VCC PECL F7 5A 3 3 V Power supply 21 Nor 2 neoer 02020280 n2 Loan 53259595 5555555 le
3. bin Linux for MVME PowerPCs and Intel VMIC respectively 3 1 VME Access The CATCH X can be accessed through a standard VME interface using the A32 D32 address mode The base address is in hexadecimal notation EO ab 00 00 where the byte ab can be selected by the two address selectors on the board Switch 1 and 2 are corresponding to the value a and b respectively In the following tables 2 10 all registers are described together with their offset to the base address and whether read or write access is possible Do not try to access any other addresses as this may hang your software Note that some registers are only available after programming the FPGAs Tab 3 9 The spy buffer can be read out using normal transfers or block transfers In case the spy buffer is empty a 0x00 00 00 00 is returned It is recommended to check the flags and or the number of values in the spy buffer before reading a block of data 3 2 User Interface For the convenience of the user two types of interfaces are provided A full screen interface written in tcl tk named CatchX o Matic provides access to all reg isters through a several windows Details can be found in ref 10 Through a command line interface each register can be read or written to vme_read address vme_write address value where address and value is given as a hexadecimal value Do not forget the base address OxEO 00 00 00 of the CATCH For example the command vme read E00A0000 re
4. TCK TDL TMS 1 enable CMC JTAG pins TCK TDI TMS 1 disable CMC JTAG pins TCK TDI TMS Send 32 bits of programming data to FPGA via DIN CCLK TCK 1 JTAG interface to FPGAs TCK 0 DIN 1 DIN 0 TMS 1 TMS 0 TCK 1 JTAG interface to CMC TCK 0 DIN 1 DIN 0 TMS 1 TMS 0 1 enable FPGA programming DIN CCLK 1 disable FPGA programming DIN CCLK CCLK 1 CCLK 0 DIN 1 DIN 0 Reset FPGAs 10 Table 3 SERIAL FPGA VME registers available after FPGA programming Read Write Bits Offset 04 00 04 10 04 04 04 14 04 08 04 18 04 0C 04 1C 223344222 11 11 11 11 11 11 11 11 oooooooo Description Serial setup bits 23 12 for 1st FE board store bits Serial setup bits 11 0 for 1st FE board send all 24 bits Serial setup bits 23 12 for 2nd FE board store bits Serial setup bits 11 0 for 2nd FE board send all 24 bits Serial setup bits 23 12 for 3rd FE board store bits Serial setup bits 11 0 for 3rd FE board send all 24 bits Serial setup bits 23 12 for 4th FE board store bits 0 Serial setup bits 11 0 for 4th FE board send all 24 bits Table 4 CONTROL FPGA VME registers available after FPGA programming Offset 08 00 08 00 Read Write R W Bits 0 7 8 9 10 11 12 13 0 3 4 7 8 9 10 11 12 13 Description CONTROL FPGA design version number BUSMODE of CMC card IS24 CMC HOTLINK receiving 24 bit data BUSY 0 serial interface 0
5. Format Description 38 88 MHz clock PECL 38 88 MHz clock PECL 4 10 Mbaud serial line active low signal 10 Mbaud serial line 4 5 V power supply for opto coupler Trigger User coded 25 100 ns LVDS Trigger User coded 25 100 ns LVDS 400 MHz HOTLink PECL 400 MHz HOTLink PECL The data format is defined according to Ref 5 23 5 2 TDC CMC The TDC CMC contains four F1 TDC chips numbered from 0 to 3 Channels 0 7 are connected to TDC 0 whereas channels 24 31 are connected to TDC 3 The details of the TDC operation can be found in Ref 4 5 2 1 Connector and LEDs A 68 pin connector from Robinson Nugent has been chosen as the input interface to the four F1 TDCs on the TDC CMC Two 34 wire twisted pair cables AWG 28 0 05 fit to a single socket A special latching eject mechanism facilitates mating and unmating The socket which goes on the cable is available from Robinson Nugent part number P50E 0685 TGF or CERN self service number 09 55 21 071 4 The four red LEDs show the following signals from left to right FIFO full Token PLL locked TDC Be INIT Upon power on reset all four LEDs are on Table 18 TDC CMC 68 pin Robinson Nugent input connector If the F1 TDC CMC board is used in the high resolution mode only the pins marked by are active All other inputs will be ignored Pin Signal Pin Signal Input level is either LVDS LVPECL or differential TTL second line 2 5
6. The read out buffers combine data which belong to one event check consistency of the data and perform sub event building In a next step they transmit the sub events via Gigabit Ethernet to filter computers Here the final event building is performed and events are recon structed The filter farm will reduce the data based on physics cuts by a factor of 5 to 10 and a continuous rate of 12 to 30 MB s will be transfered to the central data recording facilities at CERN 1 2 CATCH X Merge amp Filter Formatting Control Sort Merge Trigger amp Clock distr VME Interface Figure 2 CATCH X schematic with HOTLink mezzanine card The CATCH X is designed similar to the CATCH but as a 6U VME module This reduces the maximum number of inputs by a factor of four compared to the 9U sized CATCH Figure 2 shows a block diagram of the CATCH X overall architecture with the HOTLink mezzanine card The CATCH X module with HOTLink mezzanine card performs the setup trigger and clock distribution to the front end boards and the data transfer from the FE boards 4 via CAT 54 Ethernet cable The data from 4 connected front end boards are received at a rate of up to 40 MByte s per link Alternative mezzanine cards are available for data trans mission through optical fibres for time to digital conversion on the CATCH and deadtime free scalers Trigger timing is received from a trigger control system mezzanine card For standalone operati
7. as generated by flconf boardid is the CATCH X board id in hex port is the input port number 3 5 Data Format The format of the output data is given in Tab 11 The data in the Data Block depends on the connected front end electronics and the version of the format programmed in the FPGAs For details see 7 Table 11 Format of data send through the S Link or spy buffer The event size counts all words 32 bit excluding the two CTRL words first and last word 0000000 28 ev type 5 source ID 10 event size excl CTRL words 16 spill nr 11 event nr 20 Format Identifier format version 8 err words 8 TCS error 8 status 8 Data Block Data format defined by format version SLINK Trailer CFED120 28 0 CTRL 4 4 Hardware 4 1 Front Panel and LEDs O FPF 297 B S LINK MEZZANINE LSC ID O es TCS TRG 24 000 1234 CATCH MEZZANINE UNIVERSITAT FREIBURG Figure 3 CATCH X front panel and module On the front panel are several LEDs as described in table 12 a cutout for the S LINK LSC CMC a reset button and a cutout for the CATCH Mezzanine Card Reset switch 16 Name PWR VME PRG ID TCS TRG 24 OFF IDs FF color green yellow red green red green yellow red red red Table 12 LEDs on front panel Description 5 V Power available Board is currently accessed through VME If lit the FPGA
8. busy BUSY 1 serial interface 1 busy BUSY 2 serial interface 2 busy BUSY 3 serial interface 3 busy LED 1 4 OFF on LED 1 4 IDs on reset CMC card reset SLINK FPGA reset TCS FPGA reset FORMAT FPGA reset MERGE FPGA reset SERIAL FPGA Table 5 FORMAT FPGA VME registers available after FPGA programming Offset 10 00 10 04 10 08 10 0C 10 10 10 14 Read Write R R W R W R W R W R W Bits 0 7 8 15 0 9 0 15 0 15 0 7 8 15 0 7 Description Formatter FPGA design version number Data format identification source id as given in the S link header Following numbers need to be set for begin of run event CMC id CATCH S N TCS design version SLINK design version MERGE design version 11 Table 6 TCS FPGA VME registers available after FPGA programming Part I Offset 14 00 14 04 14 00 14 04 14 08 14 0C 14 10 14 14 14 18 14 1C Read Write W W A F Bits 0 1 0 1 Status Register 0 7 8 9 10 11 12 13 0 15 0 15 0 7 8 15 0 4 9 15 0 15 0 3 8 15 DO Nn On ct KRWN Fr L Fi th H C2 NR Cc Description 0 USR3 End of Burst 1 USR3 Pretrigger 1 TCS dummy connected select ONLY when TCS clock a 1 send USRA 25 ns front end reset 1 send USRA 400 ns front end reset for CMC TCS FPGA design version number Pretrigger as USR3 encoded USR signal output enable TCS Ready TCS Error Currently Burst RESET trigger cou
9. for TCS receiver Note that signal C12 Receiver Ready can be switched from active low to active high by setting bit 1 in register 0x14 00 Pin Active I O Symbol Symbol I O Active Pin PECL clock GND PECL clock GND GND GND Data 0 Datal Data 2 Data3 Data 4 Data5 Data 6 Data Address 0 Address 1 Address 2 Address 3 Header ready Header enable TTL clock Status enable Data mode Receiver ready Synch Start of burst End of burst Synch Trigger PreTrigger Synch Reset Error Skip data Asynch Trigger H H H H H H L H L H H L L PE EE ERE En 18 Table 14 Pin definitions of the CATCH mezzanine card 9 Pin Symbol Seen Data outputs O Data outputs DX 3 0 Data extension Additional bits used for TT UE TL RCLK Read clock I The rising edge clocks data D DX out of the pun cuc module when REN 3 0 is LOW E OF Output enable When OE is LOW D DX drive the bus SUN 014 rene qun when HIGH D DX are in high impedance state EF 3 0 Empty flag When LOW no data available CH Programmable When LOW almost no ES available empty flag synchronized to RCLK the minimum amount of available data has to be specified 3 0 Z7 Full flag When LOW internal buffers are full E es FRSTE Ree T Asynchronous eet FBUSMODED BusmodeT O Pusmode identifies card type LDEVST Device status O TFLOW signal error condition of card SNDJB 0 Serial input I Four independent 10 Mbaud seri
10. COMPASS Note 2000 12 CATCH X Users Manual H Fischer J Franz A Gr nemaier F H Heinsius L Hennig K Konigsmann M Niebuhr T Schmidt H Schmitt J Urban Fakult t f r Physik Universit t Freiburg 79104 Freiburg Germany July 19 2000 The CATCH X module is a 6U one mezzanine version of the 9U four mezzanine CATCH module The CATCH module is used in the COMPASS experiment as the driver of the front end boards and serves as a data concentrator and mini event builder before the data are transmitted to the readout buffer The CATCH X module facilitates the testing of the readout of the front end electronics It can be used either with the COMPASS trigger control system or independently of it e g for test beam activities Contents 1 Introduction and Overview 3 ld COMPASS readout on era xw wei wei ace WeOxY coi Xe 01 Xe 3 58 3 DA Ne S MN ETC TL 4 635 Contes a e lin een cdit ceste te et Bete A P eb es 5 WA Loterat be sound wk Beg Af ek E a a a ue ues e edi ecu 5 2 Installation 6 2 4 CATCH Mezzanine Card 6 2 22 TES RECEIVED A ense 6 2 3 A e A xo eee Dee rS I Rer IS T 2 4 Jumper and Switches 265 ned ge 25444844 240445 T 3 Software 9 Bek EE rs Yr aer A eb EE EEN 9 3 2 User Interface sce eae cw opo a omm go om om Oh ek a oi qw ox P ois 9 3 9 EE fiie roma fee cedes eg de ote poe ese E 9 SAY FliainitialiSatioM Rogo komo eX oet Wed o Dm Wed co ob0R os dob 7h xus A ii 15 3 5 Data Format cen Etc xa
11. Rate Experi ments Fifth Workshop on Electronics for LHC Experiments Snowmass September 20 24 1999 4 Braun et al A 8 channel time to digital and latch integrated circuit for the COMPASS experiment at CERN Universitat Freiburg 1999 5 Braun et al Designing Front End Boards for use with the CATCH HOTLink Interface COMPASS note 1999 7 Universitat Freiburg 1999 6 G Braun et al CATCH and CMC HOTLink Readout Driver Specification COMPASS note 1999 15 Universit t Freiburg 1999 7 H Fischer et al The COMPASS Online Data Format COMPASS note 2000 8 Universit t Freiburg TU M nchen 2000 8 IEEE P1386 Draft 2 0 04 APR 1995 Standard for a Common Mezzanine Card Family CMC the CMC Standard 25 9 Braun et al Draft Standard for CATCH Mezzanine Cards CATCH OPEN Universit t Freiburg 1999 10 Braun et al Catch X o Matic User Manual HTML http hpfr02 physik uni freiburg de hennigla manual 26
12. V fixed On board input termination 3 6kQ to 5V 7 1kQ to GND between and 1002 Robinson Nugent Europe B V P O Box 70062 NL 5201 DZ s Hertogenbosch The Netherlands http www robinsonnugent com 24 5 2 2 Data Format The 24 bit output data of the TDC chips as described in the F1 TDC manual LU are mapped to bits 8 31 Bit 0 3 indicates whether the TDC 0 1 2 or 3 is locked active high Bits 4 7 are always zero Table 19 Incoming TDC data format Shown is the format of the header and data For each event one header is followed by n data words and one trailer which has the same format and event number as the header The event data may be intercepted by more headers e g in case of the trigger buffer overflow error is set 10 13 corresponds to the TDC locked signals of TDC 0 to 3 31 30 29 24 23 15 14 13 12 9 8 74 3 2 1 0 trigger End ue me XOR peer P 13 12 11 10 overflow number time address ich we det measured aee 12 11 10 address to e reference signal References 1 Bowle et al The S LINK Interface Specification http www cern ch HSI s link ECP Dvision CERN 1997 2 G Braun et al TDC Chip and Readout Driver Developments for COMPASS and LHC Experiments Fourth Workshop on Electronics for LHC Experiments Rome September 21 25 1998 CERN LHCC 98 36 3 G Braun et al An Eight Channel T me to Digital Converter Chip for High
13. ads the identification and serial number of the CATCH X whose the address switch is set to 10 While the command vme write E0010800 100 resets the CMC card mounted on the CATCH X with the address set to 1 3 3 FPGA Programming The functionality of the CATCH X board is provided through the use of six field programmable gate arrays FPGA Because the programming is stored in RAM they have to be repro grammed after every power up The programming is done by executing the command 9 Offset 00 00 00 04 00 10 00 20 00 40 00 80 01 00 02 00 Table 2 VME registers always available in CPLD Read Write R R 3423233423334342 Bits 0 15 16 31 27 26 25 24 23 22 21 20 19 18 17 16 15 00 I C E ZN On OO VG k CO VG Ga H Fa TOR GO h k Cl OTK WN k Description CATCH X serial number CA01 CATCH X identification TRIGGER unused CATCH X status FPGA pin TDO JTAG CMC pin TDO JTAG FPGA programming busy FPGA INIT programming pin FPGA DONE programming pin Spy buffer FIFO 1 2 empty Spy buffer FIFO almost empty 4 words Spy buffer FIFO half full 2048 words Spy buffer FIFO almost full 4092 words Spy buffer FIFO full Number if words in Spy FIFO 4 2 Enable FPGA programming pins PROG 1 Disable FPGA programming pins PROG 1 set FPGA PROG pin low 1 reset FPGA PROG pin high 1 enable FPGA JTAG pins TCK TDI TMS 1 disable FPGA JTAG pins
14. al links engem a y TOK time clock 1 Time distribution 38 88 MHz TTL clock DICER L t Tien Tov fite Trier oo 3 0 User signals Trigger time zero and user SE USRC User coded Length coded USR 3 0 signals PIDO Test data output O ITAGTDO Test data clock JTAG TCK TRSTA 19 Table 15 Connector pin outs of the CATCH mezzanine card 9 niet 1 Pni a Pin Signal Name Signal Name Pin Pin Signal Name Signal Name Pin aprox EEN ey TRSTR 12 gt 3 Goemd Im Dm Dm oE P 6 TD Gwwd fe T BUSMODEIE 5V 8 T Gmud LVDS Tow 8 s pevip foso o S9 USRB LVDShigh Ir ir Grud USR i2 M BUSMODEZ 433V J 13 ROLE Comi ii 18 RST BUSMODESZ 14 i Grumd DXB i6 19 33Y BUSMODE4 16 g V 18 I7 USRB Hs ID ao 19 DB pp J2 3 Dp Ground 2 2 iav wi Rep 26 2 Se WEE EIDE Df C Com gt 7 35 PAERE Im JI 37 Ground FRR 38 39 PARSE Gru 0 4 s3v vsr Je 3 RENE Crom a Clm om e ir Grund o 48 ps 333v Jo Dy SNDg 9 paa Spi T9 lem Gru 96 orar SNDg s 39 Gemd Calmus 333v o Goma brar for az lt Der mL o i bo w Oo es ne z No 00 QI N mL Q 3 i a LA e SS OS 3k DCL bo bo nol ERST 2u J d J N
15. g a ge tapes o dede 15 4 Hardware 16 4j Front Panelsand LEDS rita 0 4 ie OS ere ee A A ee ded 16 22 PE Out Tables xd a mette eet Ste uet NEAR ud IS ds 18 AS sPowerand Buses ek 2 rai a id a Mele dax uu 21 5 Appendix 23 Bal EM ECO TI lt A A A A RC EUER gg 23 5 1 1 Connector and LE 23 5 12 Data Format uos ssla m te DE a e a e a e en 23 Dl IDEM Ee a e a A o ti Las 24 5 2 1 Connector and LE 24 5 2 2 Data Boriab eet D eR pure ex band e e S 25 References 25 1 Introduction and Overview 1 1 COMPASS readout The CATCH X CATCH COMPASS Accumulate Transfer and Control Hardware a mul tipurpose frontend electronic driver and readout module has been developed in the scope of the COMPASS experiment located at CERN This state of the art fixed target spectrometer is capable of standing beam intensities of up to 2 10 particles spill At a maximum trigger rate of 10 events s several Gigabyte of data has to be read every second with negligible dead time The readout architecture of the SAT LAT Calorimeter RICH COMPASS experiment is summa APV 6 ASD8b ave GASSIPLEX rized in Figure 1 Data are digi F1 TDC DSP tized right at the detector by the front end electronics wherever pos 1 16 ible T f 1 d h FE boards sible In case ol analog readout the 4 detector mounted pedestal subtraction and zero sup pression is performed by the front T gue t m end at the detector To supp
16. ith RJ 45 connector for cable interface e HOTLink CMC with fibre interface development in cooperation with Trieste group e TDC CMC with four F1 chips e Fast dead time free scaler on FPGA Some features of the HOTLink CMC and the TDC CMC are summarised in the Appendix 5 1 and 5 2 respectively Details on the CATCH mezzanine card specification can be found in 9 2 2 TCS Receiver The trigger control system interface TCS can be plugged into the P2 connector on the back The TCS receiver transient card gets the trigger and timing information from the Compass trigger distribution system via optical fibre This board has outputs for the main clock 38 88 MHz trigger reset begin of burst end of burst data enable and error bits as well as data bits Alternatively a TCS dummy receiver can be plugged into the P2 backplane connector This board has NIM inputs including trigger begin end of burst reset and one local 38 88 MHz clock to provide TCS functionality in standalone operations It is pin compatible to the Com pass TCS receiver card Table 13 2 3 S Link LSC The CATCH X board is designed such that a standard duplex S LINK Link Source Card LSC can be plugged in at the upper part of the CATCH X and connects through one mezzanine plug to the main board Details can be found in the S LINK interface specifications 1 The pin out can be found in that documentation in table 21 page 49 The size of these cards are based on
17. l and latch integrated circuit for the COMPASS experiment at CERN 4 e The front end board connection to the CATCH CATCH X through the HOTLink Designing Front End Boards for use with the CATCH HOTLink Interface COMPASS note 1999 7 5 e The specifications of the CATCH 9U version em CATCH and CMC HOTLink Readout Driver Specification 6 e The COMPASS Online Data Format COMPASS Note 2000 8 7 The newest software and documentation can be found on the web page http hpfr02 physik uni freiburg de compass 2 Installation Before the installation of the CATCH X 6U VME board one has to mount the following cards The input is provided through the CATCH Mezzanine Cards Currently one has the option between a CMC HOTLink card to connect front end boards via twisted pair cables and a TDC CMC which provides up to 32 TDC channels The output data stream can either flow through the S Link LSC card mounted on top or through the VME bus in which case the S Link card is not required The trigger and synchronisation signals are either received through the standard COMPASS trigger control system TCS and the TCS Receiver or through NIM pulses converted in the TCS Dummy receiver 2 1 CATCH Mezzanine Card CATCH mezzanine cards have the size of standardized common mezzanine cards 8 and are mounted on the lower part of the CATCH X to which it connects through two mezzanine connectors Several types are currently foreseen e HOTLink CMC w
18. nter in current spill trigger counter in last spill TCS receiver id TCS status register after last error 7 numbers below are from current event trigger mask spill number event number bit 0 15 event number bit 16 19 error word skip current event mode of current event Status FIFO empty Status FIFO full Data FIFO empty Data FIFO full FILLED TCS data ready for current event EREADY Merge ready FREADY Format ready HDEF Header buffer empty flag MEVTRDY Event number ready flag THREADY TCS Header ready MEVTSEL Merger HDREN Formatter 12 Table 7 TCS FPGA VME registers available after FPGA programming Part II Offset Read Write Bits Description 14 20 R 0 3 addr 0 from tcs fifo 4 7 addr 1 from tcs fifo 8 11 addr 2 from tcs fifo 12 15 addr 3 from tcs fifo 14 24 R 0 3 addr 4 from tcs fifo 4 7 addr 5 from tcs fifo 8 11 tcs data fifo counter 12 15 status fifo counter 14 28 R 0 15 TCS header in counter in last spill 14 2C R 0 15 TCS header out counter in last spill Table 8 SLINK FPGA VME registers available after FPGA programming Offset Read Write Bits Description 18 00 W 0 1 0 Spymode write 1 event if FIFO empty 1 Spymode write events until FIFO full 2 Spymode write every 4 event until FIFO full 3 Spymode write every 8 event until FIFO full send URESET send 3 testwords send UTEST 32x SLINK test pattern Reset spy FIFO 7 SLINK FPGA design version number HeaderEF DataEF SpyEF LFF link f
19. on a Dummy TCS card with NIM input and local clock is available The trigger time synchronization reset and one user signal are distributed to the front end boards The event number is added to the event header Programmable logic chips perform event sorting header suppression adding of geographic identifications and mini event building Formatted events are sent to the readout buffers using S link with a rate of about 100 MByte s All or prescaled events can be sent through the VME bus at a speed of 10 MByte s 1 3 Contents This document describes the CATCH X for the general user and can be used mainly as a reference guide Chapter 2 shows the required steps before installing the module in a VME crate An introduction to the software to control the module via the VMEbus and a list of registers can be found in chapter 3 Also the current version of the output data format can be found here The chapter 4 lists the pin assignments for all connectors the front panel fuses switches and jumpers As a quick reference the HOTLink Mezzanine card and the TDC mezzanine card is docu mented in the Appendix 1 4 Literature For further reading the following literature is recommended e An introduction to the COMPASS readout scheme TDC Chip and Readout Driver Developments for COMPASS and LHC Experiments 2 e The description of the F1 TDC An Eight Channel Time to Digital Converter Chip for High Rate Experiments 3 and A 8 channel time to digita
20. ress background for time measurements m be res only those hits are transfered to the y ATUM Ill ll 9U VME Setup data x s E VMEbus data recording units which have a correlation to a trigger time 150 m The data are transmitted from the front end to the CATCH mod ules through twisted pair cables or optical fibres The FPGA based VME module serves as an interface between the front end of the detec tor systems and an optical S LINK which transmits the data to the Readout Buffer ROB It also acts Central as an fan out for the COMPASS trig Data Fre GigaBit Switch ger distribution and time synchroni Recording 5km sation system TCS The readout uv d driver monitors the trigger and data flow to and from the front ends In Fiter Filter Fiter Fitter addition a specific data buffer struc S Link max 100 MB s link ROB GigaBit 100 MB s link ra ES ee trol is used to pursue local pre event readout building At startup the module con trols all necessary front end initial isations From the CATCH data are transmitted via a standardized link to the read out buffers ROB which can store all data from at least one spill The backbone of this data transfer is the S link 1 interface and the S LINK data transfer protocol Presently about 128 S LINK 3 connections are foreseen to transmit data with a maximum total bandwidth of about 12 GB s
21. s are not correctly programmed if FPGAs are not programmed Otherwise shows the selected board address lower 4 bits Red if the synchronisation clock is generated internally Off if the clock is received through the TCS system On if triggers are received from the TCS system On if CATCH Mezzanine card produces 24 bit data e g from TDC Off if 32 bit data is received e g through HOTLink from RICH On if port 1 2 3 or 4 is disabled On if setup data is received on port 1 4 of the HOTlink CMC On if the FIFO on port 1 4 is full 17 4 2 Pin Out Tables On the mother board are connectors for initial programming and debugging of the programmable logic chips as well as the connectors to the mezzanine cards e JTAG port for Xilinx CPLD programming 9 pins CPLD JTAG e Program connectors for Xilinx FPGAs X Checker and JTAG cable 18 pins FPGA PROG FPGA JTAG e A JTAG port to the CATCH mezzanine card 9 pin CMC JTAG e An ISP Port to program the Lattice ispGAL 4 pins SCLK GAL MODE SDO SDI e Two 64 pin connectors for the CATCH mezzanine card see table 14 and 9 e One 64 pin connector for the S Link card In the OU CATCH module the J3 connector is used Additionally standard VME backplane connectors are used to implement A32 D32 data transfers No VME interrupts are generated The TCS card is connected via the VME J2 backplane connector Signal names are listed in table 13 Table 13 P2 connector pin assignment
22. single size Common Mezzanine Cards as defined in Ref 8 The S Link card provides a fibre connection to the spill buffer PCI cards which reside in the readout buffer PCs ROB The S Link card is optional alternatively the data can be read out via VME bus at a lower speed 2 4 Jumper and Switches The jumpers have to be set according to table 1 to the default positions except for the TDC CMC which requires jumper 3 in position 2 3 The base address of the board can be selected by two rotary switches SW1 and SW2 For specifics refer to section 3 Table 1 CATCH X jumper positions The default positions are for the CMC HOTLink and the TDC CMC except jumper 3 which has to be set to position 2 3 for the TDC CMC For the locations of the jumpers see figure 4 default 2 3 4 5 Jumper JP 1 JP 2 JP28 JP 3 open 2 3 1 2 description no VME Interrupt no VME Interrupt Sync Trigger async Trigger for RICH CMC TCLK 40 MHz local osc CMC TCLK 38 88 MHz from TCS For on board clock distribution debugging only JP16 JP 8 JP 4 JP 5 JP 6 JP 7 JP 9 JP10 JP12 JP11 JP18 JP13 JP14 JP15 JP17 JP19 JP20 JP22 JP21 1 2 open open open open open open open open open open open open open open open open open open 3 Software A compilation of the software mentioned here can be found in the compass project space at afs cern ch compass online util catch Executables are available in bin bin AIX
23. ull flag LDOWN link down 18 00 R 18 04 R NID Ou E O O Ot cra 13 Table 9 MERGE FPGA VME registers available after FPGA programming Offset Read Write Bits 20 00 20 10 20 10 20 20 20 30 20 30 Offset 80 00 8F FF R 0 7 W 0 3 R 0 3 4 7 8 9 10 11 12 13 14 15 15 0 15 0 5 0 Eie Description MERGE FGPA design version number 0 for FIFO on 1 for FIFO off Status FIFO on 1 or off 0 Status FIFO empty 1 or not 0 1 Is TDC CMC l Is HOTLink CMC Is HOTFibre CMC Is Scaler CMC 0 TDC locked 1 TDC not locked debug FIFO 0 last debug FIFO 1 last debug FIFO 2 last 16 bit id of the CMC card 16 bit of number of received events definition of trailer for TDC readout 24 bit Table 10 Spy buffer readout Read Write Bits Description R 0 31 Read data from spy buffer block transfer possible 14 progcatch ca ch z n nn hez boardid on the command line of the VME computer The file catch x n nn hex is provided with the user interface software The boardid is the CATCH X board id in hex as selected by the two rotary switches It can take values between 0 and FF In case the PROG LED lits red an error has occurred Check that you have used the correct file and not interrupted the programming 3 4 Fl initialisation A F1 frontend board or TDC CMC connected to the CATCH X can be initialised by the command fisetup tdc f1 boardid port where tdc f1 is the file
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