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USER`S MANUAL

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1. int lt lt Q ant C 6NI LNI 9NI ase Lie 12 71 99 t 4 62 V 9 2 414405 83A0d H31IAS 3 3339410830 198915 ANdNI 96 1 B6v 12H trol ve 27 4627 483 996 1191051 7184915 104 1 A u INi 5 19 BE ON Iyi fo AMAA lt cfe 9 a m 2 5 mmi 1 1 1 5 S UU 3 5 5 UU 3 G SED ET 16 13 42 190 2 1 52 13 2 1 0 x 88 2 A lt 4115 1 lt x lt x x 3 5 lt 5 1 x 120 SIHI Otho 6823 SHI CHI 842 6861 sunny enue ZIC HNAX 4 JO IPAS 212 2 tent lt scat lt azni lt lt zni C gent lt sent lt lt lt lt lt lt lt AL U OEE enba sanea 1015159 UCICHWAX O36 enba 20151523 UCICHWAX ALON IZNI LANI INT lt lt lt Su33N00830 79915 104 1 96840138 1009 y 1008 6506 96 v12H 984 2 0119705 1 798916 INANI C woo se zur 1CHI 08 230 z ICHI 99 23 2 09 23 lt 2
2. S THE LEADER IN INDUSTRIAL XVME 212 6U 32 Channel Digital Input Module USER S MANUAL INCORPORATED Tel 248 295 0885 30765 South Wixom Road Fax 248 624 9234 P O BOX 437 Email xembeddedsales acromag com Wixom MI 48393 7037 U S A Copyright 2012 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 967B Revision Record Revision Description A Manual Released B Manual Updated Trademark Information Brand or product names are registered trademarks of their respective owners Copyright Information This document is copyrighted by Xycom Incorporated Xycom and shall not be reproduced or copied without expressed written authorization from Xycom The information contained within this document is subject to change without notice xycom xycom Technical Publications Department 750 North Maple Road Saline MI 48176 1292 313 429 4971 phone 313 429 1010 fax 212 Manual August 1989 TABLE CONTENTS CHAPTER TITLE PAGE 1 INTRODUCTION 1 1 Introduction 1 1 1 2 Manual Structure 1 1 1 3 Operational Block Diagram 1 2 1 4 Features of Xycom s Standard I O Architecture 1 2 1 5 X VME 212 Module Specifications 1 3 2 INSTALLATION 2 1 Introduction 2 1 2 2 System Requirements 2 1 2 3 Location of Components Relevant to Installation 2 1 2 4 Jumpers Switches 2 3 2 4 1 Base Address Selection Switches S1 1 t
3. 100 usec max 10 25 usec typ On to off 600 usec max 150 usec typ Minimum Detectable Pulse Width Positive pulse 100 usec max 10 25 usec typ Negative 0600 usec max 150 usec typ Maximum Input Frequency 3 4 KHz typical Debounce Time T Jumper selectable from 4 5 usec to 18 msec 8 possible settings Reverse Bias Protection XVME 212 50 V max Reverse Bias Protection 2 12 2 65V max Power Requirements 45V 5 1 7 Amp typ 2 0 Amp max 2 12 Manual August 1989 Table 1 1 XVME 2 12 Module Specifications cont d Characteristic Specification Isolation 300 VDC channel to channel 300 VDC channel to VMEbus ground Board Dimensions board size 160mm x 233 4mm Environmental Specifications Temperature Operating n 0 to 65 C 329 to 1499F Non operating 40 to 85 409 1589F Humidity 5 to 95 RH non condensing Extremely low humidity conditions may require special protection against static discharge Altitude Operating Sea level to 20 000 ft 6096m Non operating S
4. at zwr lt 2 42 9 230 6 230 26 230 12 207 82 230 42 230 2H2 92 20 2 230 22 240 61 290 gz zxr 51 230 1282 91 247 1 230 1 230 s 230 6182 61 200 2 230 a z 2w v 230 1 182 Z 230 913W C vua 6861 sn3ny enue ZI HINAX 212 Manual August 1989 Appendix D QUICK REFERENCE GUIDE EVEN ODD Base 00H Module Reserved Identification Data 3EH 40H Undefined Status Control Interrupt Ack Vector Data Register 1 Change Register 3 Undefined 7EH 80H 82H 88H Register 3 8 Change Register 1 01H read only 3FH 41H 7FH read write 83H write only 89H read only 8DH 8FH 3FFH Figure D 1 XVME 212 I O Interface Block and its Possible Locations in Short I O Address Space 212 Manual August 1989 Table D 1 XVME 212 Jumper Switch List Address Switches S1 S1 8 Must be closed to select the Short I O Address space S1 7 The XVME 212 will respond to one of the following AM codes depending on the setting of this switch OPEN Supervisory or Non Priveleged CLOSED Supervisory only S1 0 to S1 6 Sets the base address of the XVME 212 S1 6 A15
5. AC FAILURE Open collector driven signal which indicates that the AC input to the power supply is no longer being provided or that the required input voltage levels are not being met INTERRUPT ACKNOWLEDGE IN Totem pole driven signal IACKIN and IACKOUT signals form a daisy chained acknowledge The IACKIN signal indicates to the VME board that an acknowledge cycle is in progress INTERRUPT ACKNOWLEDGE OUT Totem pole driven signal IACKIN and IACKOUT signals form a daisy chained acknowledge The IACKOUT signal indicates to the next board that an acknowledge cycle is in progress ADDRESS MODIFIER bits 0 5 Three state driven lines that provide additional information about the address bus such as size cycle type and or DTB master identification ADDRESS STROBE Three state driven signal that indicates a valid address is on the address bus 1 212 Manual August 1989 Signal emonic A01 A23 24 31 BBSY BCLR BGOIN BG3IN BGOOUT BG30UT Table B l Connector and Pin Number 1A 24 30 1 15 30 2B 4 11 1B 1 2 1 4 6 8 10 VMEbus Signal Identification cont d Signal Name and Description ADDRESS BUS bits 1 23 Three state driven address lines that specify a memory address ADDRESS BUS bits 24 31 Three state driven bus expansion address lines BUS BUSY Open collector driven signal generated by the current DTB master t
6. Data Register 2 Data Register 3 8 read only 8 Change Register 0 Change Register 1 8DH 8EH I Change Register 2 Change Register 3 Undefined 3FEH 3FFH Figure 3 1 XVME 212 I O Interface Block and its Possible Locations in Short I O Address Space 3 2 212 Manual August 1989 3 3 LO INTERFACE BLOCK The Interface Block of XVME 212 contains the following programming locations as shown in Figure 3 1 which are defined in greater detail later in the chapter I D information base OlH to base 3FH These locations provide information specifying model number manufacturer and revision level e Extended Status Register base 80H Status Control Register base 8 These locations enable disable interrupts from each of the four ports indicate if an interrupt is pending and control the Pass and Fail LEDs 2 Interrupt Acknowledge IACK Vector Register base 83H which holds the vector to be driven on the VMEbus when a VMEbus interrupt generated by the XVME 2 12 is acknowledged Data Registers which hold the data from the four ports Change registers which indicate whether data on any channel has changed Note Reading or writing to undefined locations may make application software incompatible with future versions of this module 34 MODULE IDENTIFICATION DATA Base 0IH to odd byte locations only The Xycom module identification scheme provides a unique method of registe
7. Manufacturer s I D always XYC for XYCOM modules 3 characters Module Mode Number 3 characters and 4 trailing blanks NEN oxx amp lt Number of byte blocks of I O space occupied by this module 1 character Major functional revision level with leading blank if single digit Minor functional revision level with trailing blank if single digit Undefined Manufacturer Dependent Information Reserved for future use The module has been designed so that it is only necessary to use odd backplane addresses to access the I D data Thus each of the 32 bytes of ASCII data has been assigned to the first 32 odd 1 Interface Block bytes odd bytes 1H 3FH The I D information can be accessed by addressing the module base offset by the specific address for the character s needed For example if the base address of the board is jumpered to 1000H and access to the module model number is wanted I O interface block locations 11H 13H 15H 17H 19H 1BH and IDH Add the offset address to each base address to read the hex coded ASCII value at each location In this example the ASCII values which make up the module model number are found sequentially at locations 1011H 1013H 1015H 1017H 1019H 101BH and 101DH within the system s short I O address space A 5 212 Manual August 1989 MODULE OPERATIONAL STATUS CONTROL XVME intelligent I
8. CJ H SOL 12315 o oll 83131008 5534009 5 3400 mro 82 214 819 26541 3345 12 314 1189 92 214 19 957 EZ e 62 214 civ e 7 2 314 viv 6425744 aid civ 255794 56551 209879 Tw 310008 0 1 985191 22 214 19 T 12 214 civ a 61 214 619 A 81 214 314 112214 129 59 0351 11 Nid 61 214 czv Fi Ta 905141 T 2 135398 c csTv 5 951080 2 z euu388 lt 913534545 vests z sue C OTEL 77 59 99251 4 4257 4 2 evovias lt 2910 yasasa lt 313545 263 265191 59972 1508 v 4 050 gp sez lt eNIYOUI 6 ASS 492579 6861 Isnsny owner lt J 834308 1UNSIS 108102 PWN 21 1 10 z 3 46 NIC ZIZ 3WAX C esve 1 inoy2er 22 914 2 2 3 4 cin hi d gt 34 1f0X29UI lt 0 lt 1808 1 0391 E 2 1 73508 lt lt 29108 1 euwzee 1 C 08 1 s e 313423 lt M3ZINOWHO3NAS 3903 43719445 123135 08908 9 111981 123135 08608 5 ints lt C wnmow 1 sc eivisQu lt 7 131IUA 1 uou lt 9508 1 oaa lt 20574 ewrxow 1 u eouivQQu lt 208 01 08 2 8 lt
9. A properly installed controller subsystem An example of such a control subsystem is the Xycom XVME 010 System Resource Module OR B host processor which incorporates an on board controller subsystem 23 LOCATION OF COMPONENTS RELEVANT TO INSTALLATION The jumpers switches and connectors on the XVME 212 are illustrated in Figure 2 1 2 212 Manual August 1989 moomoo k NO S SSS 48 J9 JII o IL TL IL TL TT IL IT ID ID TL IT fo COMPONENT SIDE Figure 2 1 XVME 212 jumpers switches and connectors 2 2 212 Manual August 1989 2 4 JUMPERS SWITCHES Prior to installing 212 it is necessary to choose several jumper switch selectable options These options fall into two categories VMEbus related options and debounce period jumpers MEbus Options Module base address selected by switches 1 6 of the Address Switches SI Privilege level required to access the module selected by Switch 7 of the Address Switches SI VMEbus interrupt level selected by the Interrupt Level Switches S2 Whether to use or bypass the IACK daisy chain selected by Jumpers and 7 Debounce Period Jumpers The length of the debounce period is selected by Jumpers J4 and 1 2 3 212 Manual August 1989 Table 2 1 XVME 212 Jumper Switch List Jumper Switch Use Address Switches SI SI switches 1 6 Module Base Address Select SI switch 7 This switch determines w
10. 51 5 18 51 4 13 Open Logic 1 51 3 12 Closed Logic 0 51 2 All 81 1 10 Interrupt Level Switches 52 S2 3 S2 2 52 1 VMEbus Interrupt Level OPEN OPEN OPEN OPEN OPEN CLOSED OPEN CLOSED OPEN OPEN CLOSED CLOSED CLOSED OPEN OPEN CLOSED OPEN CLOSED CLOSED CLOSED OPEN CLOSED CLOSED CLOSED None interrupts disabled Use Use bypass IACK daisy chain 31 32 B uses IACK daisy chain A A Module bypasses chain Must be in B position to select the Short I O Address space These jumpers determine the debounce period T min T max 3 5 us 4 5 us 7 us 9 us install 14 us 18 us only 28 us 36 us one 112 us 144 us 448 us 576 1 8 2 3 ms 14 ms 18 ms D 2
11. This ensures that the data read from the Change and Data Registers is from the same scan when a Change Register read is followed D a Data Register read If the scanner were allowed to run a Change Register bit could be set after the Change register was read but before the Data Register is read Because reading a Data Register zeros the Change Register any Change Register bits set between the two reads would be lost Stopping the scanner in this fashion ensures that no change Register bits will be lost 3 9 3 Restarting the Scanner If the scanner is stopped due to reading the Change Register it can be restarted by reading the Data Register the Extended Status or the Status Control Register The scanner is also started up automatically after the XVME 212 is reset 3 10 VMEbus INTERRUPTS Each of the four Change Registers has an interrupt enable bit in the Status Control Register bits 4 7 When this bit is set a VMEbus interrupt will be generated when any bit of the corresponding Change Register is set and the VMEbus Interrupt Enable bit bit 3 of the Satu Contro Register is set This alerts the CPU that an input has changed state since the last time the CPU read the data registers Figure 3 5 illustrates the logic involved in generating a VMEbus interrupt Reading the corresponding Data Register will reset the VMEbus interrupt because reading the Data Registers will reset the corresponding Status Control bit 8 11 When the VMEbus int
12. cen 2590719003 9999 99 S s 59151952 6861 suny ZI HIWAX L Jo 12946 gt 5 NIC ZIZ H3WAX 2 180 32015 z emus C 0123A NIYI Ch Ch 6108 64 lt gt y 83151938 501915 3118 N3A3 96115792 lao 11883558 1884 LON 301953439 32015 32800830 46651981 666519 d 37949 gi 5 865191 2 lt ain 99251791 4 9925792 alk 99251941 066519 123130 642519 95191 lt 985191 521 995151 951 L 82 OBAMA 9508 1508 191 cue 2 37 298 lm 198 N34NI C C 1 1154 C conna C C C C tonna C N3ISSNH3 C sonna 312423 91915034 nnn 6861 sn3ny PWN CIC HINAX 1 JO 9 NIC ZTZ 3WAX AO 9q UAOUS se K quiesse Jo wed 104 31A UTITINAX T ALON UAOUS SE qA IZICHINAX ILON OEE s n eA 10151523 UCICSNAX G X6 Tenba 10151593 VCICHWAX ALON t 8 2 e v Cs zn Cer zur SNI CNI ZNI ONI
13. 31 1 A32 1B 32 1 32 2B 1 13 32 1C 31 1A 31 Signal Name and Description SYSTEM FAIL Open collector driven signal that indicates that a failure has occurred in the system It may be generated by any module on the V us SYSTEM RESET Open collector driven signal which when low will cause the system to be reset WRITE Three state driven signal that specifies the data transfer cycle in progress to be either read or written A high level indicates a read operation a low level indicates a write operation VDC STANDBY This line supplies 5 VDC to devices requiring battery backup 5 VDC POWER Used by system logic circuits 12 VDC POWER Used by system logic circuits 12 VDC POWER Used by system logic circuits B 5 212 Manual August 1989 BACKPLANE CONNECTOR The following table lists the PI pin assignments by pin number order The connector consists of three rows of pins labeled rows A B and C Table B 2 P1 Pin Assignments Row A Row C Pin Signal Signal Number Mnemonic Mnemonic BBSY BCLR 09 ACFAIL 10 BGOIN D11 BGOOUT 12 BGIN D13 BGIOUT 14 BG2IN D15 BG2OUT GND SYSFAIL BG3QUT BERR BRO SYSRESET BRI LWORD BR2 5 BR3 A23 AMO A22 AMI A21 2 20 19 GND A18 SERCLK I A17 IACKOUT SERDAT 1 A16 AM4 GND A15 A07 IRQ7 Al4 A06 IRQ6 13 05 IRQS A12 A04 IRQ4 All A03 IRQ3 A10 A02 IRQ2 A09 A01 IRQI A08 12V
14. 4 83 aon A81S0NK Om 12 xoe1080 5 lt kista c 1 65291080 lt 19135348 1 ee v 60304015 lt 298 1 risu C ve 1 C ve t zes 1 lt sva C ove 1 301953439 9NIMI1 31242 TA ONY 300330 5530009 eva 4 C eva 6861 3808 V ENEN ZIC HINAX 16 823 9 2 JO 1 45 2rieurSups NIG ZIZ 3WAX 22 824 21 824 ans 2 824 6 214 2 814 Tata XI UUE NIC98 gi aia Y Py d wa 51 914 100288 6814 n 865192 Lx ps 7 3 51 914 ONS 11298 C 812 ecc 5082 MU 11 919 11 98 1 teu 158 IDL 1130 9813 C 8122 25 824 lt N1998 8td 8314 83 82 lt m LANA 2 26 214 6 Perm H Cw 25 814 AS TL Av AM H zr 26 914 s tru p I AAA go C 8 914 H n 1 6 957 4 58833308 Ast 508 9190 C eii 1 C 17 214 A a A Es 2 314 enous 2 840 5234 C mwa zi 7314 H ed zve t 6190 9 314 via 25514 H C sia 8 214 lt vs lt sve 621526 9084 4313144301 310008 62191353886 1 C wu 2 au Vk lt 191508 z 4 C
15. O modules are designed to perform diagnostic self tests on power up or reset For non intelligent modules the user must provide the diagnostic program The self test provision allows the user to verify the operational status of a module by either visually inspecting the two LEDs which are mounted on the front panel as in Figure A 3 or by reading the module status byte located at module base address 81H Figure 3 shows the location of the status LEDs on the module front panel The two tables included in the figure define the visible LED states for the module test conditions on both the intelligent I O modules and the non intelligent I O modules XXXX XVME XXX Status OFF Module not yet tested OFF Module failed test Inactive module Module undergoing test Module passed test Invalid and undefined Red LED Green LED Status Bits LEDs 0 G Red SYSFAIL Status Module failed or not yet tested Inactive module Module undergoing test Module passed test NON INTELLIGENT MODULE STATUS FRONT VIEW Figure A 3 Module LED Status A 6 212 Manual August 1989 The module status control register found at module base address intelligent XVME modules provides the current status of the module self test in conjunction with the current status of the front panel LEDs The status register on intelligent modules is a Read Only register and it can be read by software to determine if the boa
16. the opto isolator s response time So selecting this time will essentially defeat the debounce circuitry for users concerned about speed and not concerned about bounce 25 INSTALLATION The Xycom VMEbus modules are installed in a standard VMEbus backplane Figure 2 3 2 9 212 Manual August 1989 shows standard chassis and typical configuration Two rows of backplane connectors are depicted the P1 backplane and the P2 backplane However the X VME 212 uses only the P1 backplane GUIDE SLOT SOLDER SIDE PI BACKPLANE COMPONENT SIDE GUIDE SLOT P2 BACKPLANE Figure 2 3 VMEbus Chassis 212 Manual August 1989 2 5 1 Installation Procedure CAUTION Never attempt to install or remove any boards before turning off the power to the bus and all related external power supplies Prior to instaling a module determine and verify all relevant jumper configurations and all connections to external devices or power supplies Please check the jumper configuration against the diagrams and lists in this manual To install a board in the card cage perform the following steps 2 26 Make sure the cardcage slot which will hold the module is clear and accessible Center the board on the plastic guides in the slot so that the solder side is facing to the left and the component side is facing to the right refer to Figure 2 3 Push the board slowly towar
17. will reset the Change Register bits Each Change Register bit will be set again when the input state is different from the image in the Data Registers This alerts the CPU that an input has changed state since the CPU last read the Data Registers because the Change Register was zeroed the last time the Data Register was read The Data Registers should be read again to clear the corresponding Change Register bits 3 8 CHANGE REGISTERS These four read only registers contain the change bits for the 32 input channels These bits are set by the scanner when it detects a state transition in an input channel Each input channel has one change bit see Figure 3 4 Each Change Register corresponds to one Data Register compare with Figure 3 3 3 9 212 Manual August 1989 port port 1 base gt base 8BDH 15 4 54 32 3139 29 ze 27 26 25 24 23 22 21 20 17 16 base base 8FH port 2 port 3 Figure 3 4 Change Registers read only These bits are reset when the corresponding data register is read These registers may be read as either words or bytes 39 SCANNER The scanner consists of circuitry which monitors the input channels and detects state transitions When a state transition is detected in any input channels the Change Register bit for that channel will be set Both on to off and off to on transitions will be detected
18. word or as two 8 bit bytes 3 5 2 12 Manual August 1989 3 5 1 0 1 Extended Status and Status Control Register Bit Definitions Red LED Green LED These bits control the red and green LEDs The red and green LEDs provide visual indication of a module status A logic 0 turns on the red LED 00 A logic 1 turns on the green LED DI The LEDs should be used to indicate the following status Table 3 2 as set forth by the Xycom architecture described in Appendix Table 3 2 LED Status LI SYSFAIL Staus OFF ON ON Module failed or not yet tested OFF OFF OFF Inactive module ON JON ON Module undergoing test ON OFF Module passed test Note The XVME 212 is non intelligent module so all diagnostics must be performed by the system host I VMEbus Interrupt Pending This read only bit reads 1 whenever BOTH of the following conditions are met One or more of the Change Register n Interrupt Enable bits bits 4 7 of the Status Control been set to 1 D A bit in one of the interrupt enabled Change Registers associated with a port has the value 1 A bit value of 1 in a Change Register indicates that a change of state has occurred on a specified input channel VMEbus Interrupt Enable This bit enables VMEbus interrupts from the XVME 212 module l VMEbus interrupt will be generated automatically whenever the XVME 212 sets bit 2
19. words or bytes For example to read all channels on the board as words the correct sequence is 1 read Change Registers and I as one word 2 read Data Registers 0 and 1 one word 3 read Change Registers 2 and 3 as one word 4 read Data Registers 2 and 3 as one word p the time that the scanner is stopped no changes in state will be detected and the Data Registers are not updated In systems which must keep up with the fast changing inputs the time that the scanner is stopped must be minimized It is therefore necessary to read the Extended Status Status Control or Data Registers restarting the scanner quickly after the Change Register is read stopping the scanner is suggested that the user disable all CPU interrupts between the two reads If an interrupt is taken after the Change Register read but before the data status registers are read the scanner would be off for the duration of the interrupt service routine The following chart shows the relationship of input channel signals with respect to stopping the scanner 3 13 212 Manual August 1989 latch the inputs for scan latch the inputs for scan n 2 latch the inputs for scan 1 latch the inputs for 3 scan scan scan scan 2 6 1 21 3 scenner activity lt scanner stopped 5 Channel x outputs 1 eee from chennel y 1 1 debounce circuitru FL v A chan
20. 1 0 1 1 2C00H 0 0 1 1 0 0 3000H 0 0 1 1 0 1 3400H 0 0 1 1 1 0 3800H 0 0 1 1 1 1 3C00H 0 1 0 0 0 0 000 0 1 0 0 0 1 4400H 0 1 0 0 1 0 4800H 0 1 0 0 1 1 amp C00H 0 1 0 1 0 0 5000H 0 1 0 1 0 1 5400H 0 1 0 1 1 0 5800H 0 1 0 1 1 1 5C00H 0 1 1 0 0 0 6000H 0 1 1 0 0 1 6400H 0 1 1 0 1 0 6800H 0 1 1 0 1 1 6C00H 0 1 1 1 0 0 7000H 0 1 1 1 0 1 7400H 0 1 1 1 1 0 7800H 0 1 1 1 1 1 7C00H 1 0 0 0 0 0 8000H 1 0 0 0 0 1 8400H 1 0 0 0 1 0 8800H 1 0 0 0 1 1 8C00H 1 0 0 1 0 0 9000H 1 0 0 1 0 1 9400H 1 0 0 1 1 0 9800H 1 0 0 1 1 1 9C00H 1 0 1 0 0 0 A000H 1 0 1 0 0 1 400 1 0 1 0 1 0 A800H 1 0 1 0 1 1 AC00H 1 0 1 1 0 0 1 0 1 1 0 1 B400H 1 0 1 1 1 0 B800H 1 0 1 1 1 1 BC00H 1 1 0 0 0 0 C000H 1 1 0 0 0 1 C400H 1 1 0 0 1 0 C800H 1 1 0 0 1 1 CC00H 1 1 0 1 0 0 D000H 1 1 0 1 0 1 D400H 1 1 0 1 1 0 D800H 1 1 0 1 1 1 DC00H 1 1 1 0 0 0 000 1 1 1 0 0 1 E400H 1 1 1 0 1 0 E800H 1 1 1 0 1 1 EC00H 1 1 1 1 0 0 F000H 1 1 1 1 0 1 F400H 1 1 1 1 1 0 F800H 1 1 1 1 1 1 FC00H NOTE Open Logic 1 2 6 Closed Logic 0 212 Manual August 1989 2 4 2 Address Space Selection 3 The XVME 212 be placed in VMEbus Short I O or Standard Meno Space The selection is made by configuring Jumper J3 and Switch 8 of Switch Bank see Figure 2 2 as shown in Table 2 3 below Table 2 3 Addressing Options J3 Switch 8 SD Option Selected JA Open Standard Data Access Operation Closed Short I O Access Operatio
21. 24223 lt we s C s e lt 6 N3I09NHO lt lt 6 N3II9NH3 lt lt 1 6 lt S c lt 04251912 83151938 108102 2570 401943439 C 58 1 93151934 501915 ZHH 8 6 gog S 08 _2 2 lt cour v2 814 1 62 814 6 92 814 8 evour 12 818 H Qeni CD M D i i gt 1 24 A 22 11 11771 55 W3AIHO 4300930 140883181 Sols m 9229 I IN 6861 suny trecom PWN CIC HINAX CJ 135299 1 h 3 46 LWS NIC ZIZ HWAX 108102 V3NNU2S zu 03 4015 D OH9NH20H O19NH208 oH1UQQH g 0714004 lt 1508 1 O lt e sos 1 1081802 83151938 39NUH2 0832 s108 008 lt 2 583151938 9190 583 51938 39NUHJ ne os C ienr CHINO ET SR3IITHS 7 A leoi C 7 OZNI lt cant C szni lt sent C vant r s lt cant 29 C 1 ay 13 2 U C lt mr s CONHIC lt gt C lt C zin C lt lt lt 9 9 9 9 9 9 2 lt _ ONT SNI NI NI ZNI BE uu
22. 2V DC supply is available for use with mechanical switches The 12V supply s positive terminal is connected to the terminal of each input channel The 12V supply s return terminal is connected to pins 49 and 50 of the JK connectors see Table 2 9 The external switch should be connected between the terminal of the particular input channel and pins 49 50 When the switch closes the 12V return is connected to the terminal of the input channel which turns the input channel on No external supplies are required Note that all input channels have their terminals connected together they all connected to the 12V supply Some users will want electrical isolation between channels To facilitate this break points are available for all 32 input channels When the breakpoint is cut the input channels terminal is disconnected from the isolated supply and the other input channels The 12V supply cannot be used on a channel when its break point is cut however These break points are labeled as CHO CH31 on the board and are easily accessible from the circuit side of the board under the 32 W resistors Pads are uae on either side of the break point to allow reconnection if required The 300V channel to channel isolation specification applies to channels which have their break point cut The 300V channel to VMEbus isolation is maintained whether the break points are cut or not because the 12V supply is isolate
23. 5V STDBY 12V 5V 5V 5V NO Oo 1 O CA 212 Manual August 1989 Appendix SCHEMATICS AND DIAGRAMS Block Diagram CHANNELS CHANNELS 0 15 16 31 JK1 JK2 OPTICAL ISOLATOR DEBOUNCING STANDARD VO INTERFACE SCANNER CHANGE REGISTERS DATA REGISTERS VMEbus INTERFACE VMEbus 212 Manual August 1989 Drawing 32 3 a 2 5 8 Suas Suea Suez Sus 5549 Sure Turi Tura 5473 Tura 5573 55751 510 5978 575 5 Fa COMPONENT SIDE 2 FO IPAS NIA 212 4 213808 2 4291080 2 199 289 tus lt ou sez zye lt sev 832914 89 SdIHO 21 01 18329808 sez ces sou 132814 QNU A8G 3017 389 5492 559418 Z cz ws 199 gu XG Av 1 SHHO NI 389 580151538 31383510 719 nm 80989308 1 NI 389 5801199499 TW z lt 1031413345 3SIAM3HIO 5531 0 71 2191 5534009 z we 62 314 cav ej v A 1049 gr ase 2 vg lt CN ez enira C 92 914 1314 2 lt 91 814 ouv 645744 21 814 tue HILO zu vue sue Fo 2095744 31242 AIWA 4251 4 N 572 2 4 IN
24. ME 212 I O Interface Block and its Possible 3 2 Locations in Short I O Address Space 3 2 Extended Status and Status Control Registers 3 5 3 3 Data Registers read only 3 9 3 4 Change Registers read only 3 10 3 5 Generating a VMEbus Interrupt 3 12 3 6 Relationship of Input Channel Signals with 3 14 Respect to Stopping the Scanner LIST OF TABLES TABLE TITLE PAGE 1 1 XVME 212 Module Specifications 1 3 2 1 XVME 212 Jumper Switch List 2 4 2 2 Module Base Addresses 2 6 2 3 Addressing Options J3 2 7 ii 212 Manual August 1989 LIST TABLES cont d TABLE TITLE Privilege Options Address Modifier Code Options Interrupt Level Switches S2 IACK Enable Jumpers Debounce Period Jumpers Input Connector Signal Definitions t t t t ty 1 Identification Data 2 LED Status iii 212 Manual August 1989 Chapter 1 INTRODUCTION 11 INTRODUCTION 212 is 32 channel opto isolated digital input interface designed to be compatible with the VMEbus structure The XVME 212 is capable of receiving 32 digital inputs at frequencies up to 3 4 KHz To ensure signal integrity the design incorporates integrated switch debouncing well as the protection provided by the optical isolation of the channel inputs from the m bus structure In addition an on board scanner can be programmed to generate a bus interrupt when any input changes state thus eliminating the need to pol
25. The Change Register bit remains set even if the input channel reverts to its original state providing the ability to detect pulses in any of the input channels The Change Register bits can be interrogated to determine which individual channel experienced a pulse 3 9 1 Scanner Operation The scanner sequentially executes scans in which the input channels are checked one nibble four inputs at a time for state transitions Eight nibbles 32 input channels must be checked to complete one scan The architecture of the scanner does not allow it to be stopped in the middle of a scan The scanner must complete its scan and stop before meaningful information can be read from the Data or Change registers The assertion of DTACK is delayed until the scanner completes its scan and stops when the VMEbus reads the Data or Change registers The scanner requires 1 25 us to execute one scan The delay introduced into a given bus cycle is random value between 0 and 1 125 us in 125 us increments If the registers are read at the point where the scanner is at the end of a scan no delay will result If the registers are read at the point where the scanner just started the maximum delay will be encountered 3 9 2 Stopping the Scanner Reading the Change or Data Register forces the scanner to stop The scanner is restarted immediately after a Data Register is read However it remains stopped after a Change 212 Manual August 1989 Register is read
26. ated The level of the VMEbus interrupt is determined by the setting of Switch bank 52 see Section 2 4 5 Section 3 8 describes in detail how interrupts are generated 36 INTERRUPT ACKNOWLEDGE VECTOR REGISTER base 83H This write only register holds the vector to be driven on the VMEbus when a VMEbus interrupt generated by the XVME 212 is acknowledged 37 DATA REGISTERS Four read only Data Registers hold the state of the XVME 212 s four input ports see Figure 3 3 3 8 212 Manual August 1989 port 0 port 1 base 88H lt base 89H 15 14 13 ej 54 3 21 9 3130 29 28 27 26 2s 24 23 22 21 20 6 17 16 base base port 2 port 3 NOTE The Data Registers can be accessed as either words or bytes Figure 3 3 Data Registers read only The numbers in each bit position indicate the input channel associated with each bit of the data registers When an input channel is on voltage greater than 10V for XVME 212 1 or greater than 2 0 for XVME 212 2 its state will be read as 1 When an input channel is off voltage less than 1V for XVME 212 1 and less than 81V for XVME 212 2 its state will be read as 0 When Data Registers are read the corresponding Change Registers 8 change bits will be zeroed This is true for word or byte data reads This is the only mechanism with the exception of VMEbus resets which
27. d how it relates to the VMEbus short I O address space This example shows an Interface Block that occupies a IK segment of short I O Address Space It should be noted that some modules the XVME 164 MBMM for example will occupy up to a 4K segment of short I O Address Space Notice that any location in the I O Interface Block may be accessed by simply using the address formula Module Base Address Relative Offset Desired Location A 3 212 Manual August 1989 Short Address Space BASE 00H Module Identification Status Control Module Dependent For use with Interprocessor Communication Protocol Figure A 2 XVME I O Module Address Map MODULE SPECIFIC IDENTIFICATION DATA The module identification scheme provides a unique method of registering module specific information in an ASCII encoded format The LD data is provided as 32 ASCII encoded characters consisting of board type manufacturer identification module model number number of 1 Kbyte blocks occupied by the module and model functional revision level information This information can be studied by the system processor on power up to verify the system configuration and operational status Table 1 defines the identification information locations 212 Manual August 1989 Table A 1 Module I D Data Offset Relative to Contents ASCII oe Module Base in hex ID PROM identifier always VMEID 5 characters
28. d the rear of the chassis until the connector engage the board should slide freely in the plastic guides Apply straightforward pressure to the handle on the panel front until the connector is fully engaged and properly seated NOTE It should not be necessary to use excessive force or pressure to engage the connectors If the board does not properly connect with the backplane remove the module and inspect all connectors and guide slots for possible damage or obstructions Once the board is properly seated secure it to the chassis by tightening the two machine screws at the extreme top and bottom of the board DIGITAL INPUT CONNECTIONS The module is capable of receiving 32 separate digital inputs The inputs are accessible on the front edge of the board in the form of two 50 pin ribbon headers The connectors are labeled and JK2 see Figure 2 The following table shows the pin designations for connectors and JK2 2 11 XVME212 Manual August 1989 Table 2 9 Input Connector Signal Definitions Connector 1Connection Connection CH31 CH31 12V Return 212 1 0 Return 212 1 Ground XVME 2 12 2 Ground XVME 2 12 2 12V Return 212 12VReturn XVME 212 l Ground XVME 2 12 2 Ground XVME 2 12 2 2 12 212 Manual August 1989 2 7 MECHANICAL SWITCH RELAY OPERATION 2 7 1 XVME 212 1 With the XVME 212 an isolated 1
29. d to 300 2 7 2 XVME 212 2 With the XVME 212 2 the 5V supply of the VME backplane is used with the mechanical switches Each terminal of the input channels is connected to 5V with reference to logic ground while pins 49 and 50 of the JK ports are connected to logic ground See Table 2 9 The external switch should be connected between the terminal of the particular input channel and pins 49 50 When the switch closes logic ground is connected to the terminal of the input channel which then turns on the input channel Note that all input channels have their terminals connected together they are all connected to 5V Some users will want electrical isolation between channels To facilitate this break points are available for all 32 input channels When the breakpoint is cut the input channel s terminal is disconnected from the 5V supply and the other input channels The 5V cannot be used on a channel once its break point is cut however These break points are labeled CHO CH31 on the board and are easily accessible from the circuit side of the board Pads are provided on either side of the break point to allow reconnection if required The 300V channel to channel and the 300V channel to VMEbus isolation applies ONLY to channels which have their break point cut 2 13 212 Manual August 1989 Chapter 3 PROGRAMMING 31 INTRODUCTION This chapter provides the information require
30. d to program the XVME 212 including the following e Discussion of base addressing and I O module address space Presentation of module address map showing programming locations 3 2 BASE ADDRESSING The XVME 212 operates as an I O module in VMEbus systems and is located in the 64K VMEbus Short I O Address Space or the upper 64K of the Standard Address space It can be located at any one of 64 base addresses at IK intervals within this address space The base address is selected via the switches described in Section 2 4 1 When located at its base address the XVME 212 is allotted a 1K block of address space for its own use This IK block of address space is termed the I O Interface Block and contains all of the module s programming locations Figure 3 1 shows the I O Interface Block of the XVME 212 and relation to the address space When accessing locations in the I O Interface Block the addresses shown in Figure 3 1 must be added to the module s base address For example if the XVME 212 is located at Short I O Base Address 0400H the address of the Control Status register is 0481H base 81H 3 1 212 Manual August 1989 ODD Base 00H 01H Module Reserved Identification read only Data 3EH 3FH 40H 41H Undefined 7EH 7 80H Extended Status Status Control 81H read write 82H Undefined Interrupt Ack Vector 83H write only Undefined Undefined 88H Data Register 0 Data Register 1 89H
31. des on a 1 boundary Thus the module base address for each I O Interface Block resides on any one of 64 possible 1 boundaries within the Short I O Address space or any 1K boundaries within the Standard Address Space s upper 64 The module base address is selected by using the switches labeled 1 6 in DIP switch bank S1 Figure 2 2 shows the Switch bank S1 and how the individual switches 1 6 relate to the base address bits A10 A11 A12 A13 A14 A15 5 4 6 7 8 LO LO Le Lel 1 2 3 LO LO Le Figure 2 2 Switch Bank 1 Base Address Switches When a switch is in the closed position 1 when it is pushed in on the opposite end of the switch bank from the open label the corresponding base address bit will be logic 0 When a switch is set to the open position the corresponding base address bit will be logic 1 Table 2 2 shows a list of the 64 1K boundaries which can be used as module base addresses in the Short I O Address space and the corresponding switch settings switches 1 6 from 1 2 5 212 Manual August 1989 Table 2 2 Base Address Switch Options Switches VME base address in VME 6 15 5 14 4 A13 3 A12 2 A11 1 A10 Short I O Address space 0 0 0 0 0 0 0000H 0 0 0 0 0 1 0400H 0 0 0 0 1 0 0800H 0 0 0 0 1 1 0C00H 0 0 0 1 0 0 1000H 0 0 0 1 0 1 1400H 0 0 0 1 1 0 1800H 0 0 0 1 1 1 1C00H 0 0 1 0 0 0 2000H 0 0 1 0 0 1 2400H 0 0 1 0 1 0 2800 0 0
32. e and word transfers that a data transfer will occur on data bus lines D0 D1 5 DATA TRANSFER ACKNOWLEDGE Open collector driven signal generated by a DTB slave The falling edge of this signal indicates that valid data is available on the data bus during a read cycle or that data has been accepted from the data bus during a write cycle DATA BUS bits 0 15 Three state driven b amp directional data lines that provide a data path between the DTB master and slave GROUND 3 212 Manual August 1989 Signal Mnemonic IRQI IRQ7 LWORD RESERV ED SERCLK SERDAT SYSCLK Table VMEbus Signal Identification cont d Connector and Pin Number 1 A20 1 24 30 1C 13 2B3 21 18 22 1A 10 Signal Name and Description INTERRUPT ACKNOWLEDGE Open collector or three state driven signal from any master processing an interrupt request It is routed via the backplane to slot 1 where it is looped back to become slot 1 IACKIN in order to start the interrupt acknowledge daisy chain INTERRUPT REQUEST 1 7 Open collector driven signals generated by interrupter which carry prioritized interrupt requests Level seven is the highest priority LONGWORD Three state driven signal indicates that the current transfer is a 32 bit transfer RESERVED Signal line reserved for future VMEbus enhancements This line must not be used A reserved signal which wil
33. e dependent Module dependent Module dependent Module dependent Module dependent Module dependent Module dependent Module dependent Figure A 4 Status Register Bit Definitions A 8 2 12 Manual August 1989 INTERRUPT CONTROL Interrupts for non intelligent modules can be enabled or disabled by setting clearing the Interrupt Enable bit in the module status KE The status of pending on board interrupts can also be read from this register Interrupt control for intelligent modules is handled by the Interprocessor Communications Protocol Communications Between Processors Communications between an intelligent master and an intelligent slave I O module is governed by XYCOM s Interprocessor Communication IPC Protocol This protocol involves use of 20 byte Command Block data structures located anywhere in the shared global RAM or dual access RAM on an I O module to exchange commands and data between a host processor and an module THE KERNEL To standardize its I O modules XYCOM has designed them around kernels common from module to module Each different module type consists of a standard kernel combined with module dependent application circuitry Module standardization results in more efficient module design and allows the implementation of the Standard I O Architecture The biggest benefit of standardization for intelligent modules is that it allows the use of a common command language or
34. e operation of all XYCOM modules MODULE ADDRESSING The XYCOM I O Architecture Design Specification recommends that modules should be addressed within the VMEbus defined 64K short I O address space restriction of I O modules to the short I O address space provides separation of program data address space and the I O address space This convention simplifies software design and minimizes hardware and module cost while providing 64K of address space for I O modules 1 212 Manual August 1989 Base Addressing Since each 1 module connected to the bus must have its own unique base address the base addressing scheme for 1 modules has been designed to be jumper switch selectable Each 1 module installed in the system requires at least a 1K byte block of the short I O Address Space Thus each I O module has a base address which starts on a 1K boundary As a result the XYCOM I O modules have all been implemented to decode base addresses in 400H increments Figure A 1 shows abbreviated view of the short I O memory Short Address Space Base Address Jumper Options 0CO00H BENE HE Jumper J5 J Module base address in VME 2 S LLL 1000H pal 1400H Figure A 1 64K Short I O Address Space for Modules Occupying a 1K Block 212 Manual August 1989 Standardized Module 1 0 Map The block of short I O addresses called the I O Int
35. ea level to 50 000 ft 15240m Vibration Operating 5 to 2000 Hz O 15 peak to peak displacement 25g peak acceleration Non operating W 5 to 2000 Hz 090 peak to peak displacement 5 0 g peak maximum acceleration Shock Operating 30 g peak acceleration 1 msec duration 50 g peak acceleration 11 msec duration 2 12 Manual August 1989 Table 1 1 2 12 Module Specifications cont d Characteristic Specification VMEbus Compliance e Fully compatible with VMEbus standard Al 6016 Data transfer bus slave Base address jumper selectable within 64K short I O address space Occupies IK consecutive byte locations I 1 to I 7 Interrupter STAT with programmable vector Includes Xycom s standard I O module interface NEXP 212 Manual August 1989 Chapter 2 INSTALLATION 2 1 INTRODUCTION This chapter provides the information needed to configure the XVME 212 and to install it in a VMEbus backplane card cage 2 SYSTEM REQUIREMENTS The XVME 212 is a double high VMEbus compatible module operate it must be properly installed in a VMEbus backplane The minimum system requirements or operation of the XVME 212 are one of the following either or B below A A host processor properly installed on the same backplane
36. erface Block allocated to each XVME module is mapped with a standardized format in order to simplify programming and data access The locations of frequently used registers and module specific identification information are uniform For example the module identification information is always found in the first 32 odd bytes of the module memory block These addresses are associated with the jumpered address 1 Module I D data address base odd bytes IH The byte located at base address 81H on each module contains a Status Control register provides the results of diagnostics for verification of the module operational condition The next area of the module I O Interface Block base address 82H up to is module specific varying in size from one module to the next It is in this area that the module holds specific I O status data and pointer registers for use with IPC protocol All intelligent XVME I O modules have an area of their I O Interface Blocks defined as dual access RAM This area of memory provides the space where XVME slave I O modules access their command blocks and where XV master modules could access their command blocks i e master modules can also access global system memory The remainder of the Interface Block is then allocated to various module specific tasks registers buffers ports etc Figure A 2 shows an address map of an XVME I O module interface block an
37. errupt enable bit 3 is reset no bus interrupt will be generated By using the interrupt mechanism the VMEbus is relieved of the traffic required to constantly poll the module The level of the VMEbus interrupt generated pA the XVME 212 is determined by the setting of Switch bank S2 see Section 2 4 5 e IACK vector is determined by the contents of the IACK Vector Register at location base 83H see Section 3 6 3 1 212 Manual August 1989 0 1 5 Interrupt 3 e g The numbered bits are located in the Extended Status and Status Control Registers base 080 See Figure 3 2 Figure 3 5 Generating a VMEbus Interrupt 3 12 212 Manual August 1989 3 11 PROGRAMMING CONSIDERATIONS Use the following procedure to ensure that no change bits in a Change Register are zeroed before they are read Change Register must be read first which wil stop the scanner Then the Data Register is read which will zero the Change Register and restart the scanner The reason for this sequence is explained in Section 392 Reading any Change Register stops the scanner and reading any Data Register restarts it The user should therefore read the Data registers as logical pairs 1 read Change Register 3 then Data Register 3 not Change Register 3 then Data Register 2 These logical pairs may be
38. hether the module will respond only to supervisory accesses or to both supervisory and non privileged accesses 51 switch 8 This switch works in conjunction with Jumper J3 to determine whether the board operates with address modifiers for Short Address Space or those for Standard Address space See note below Interrupt Level Switches 52 Selects the interrupts to be generated by a change of state on input lines JI J2 Selects whether to use or bypass the IACK daisy chain n This jumper works in conjunction with 4 Switch 8 for address space selection ie Short I O Address Space or Standard Address Space See note below J4 Jil Determines the debounce period Note See also Section 2 4 2 Switch 8 of Switch Bank SI 241 Base Address Selection Switches 51 1 to 51 6 XVME 212 module is designed to be addressed within either the VMEbus Short I O or Standard Memory Space Since each I O module connected to the bus must have its own unique base address the base addressing scheme for the I O modules has been designed to be switch or jumper selectable When the XVME 212 module is installed in the system it will occupy a 1 Kbyte block of the Short I O Memory or Standard Address Space called the module I O Interface Block 2 4 212 Manual August 1989 The base address decoding scheme 1 modules is such that the starting address for each I O Interface Block resi
39. ing the module base offset by the specific address for the character s needed For example if the base address of the board is jumpered to 1000H and if you wish to access the module model number 1 0 interface block locations 11H 13H 15H 17H 19H 1BH and IDH you will individually add the offset addresses to the base addresses to read the hex coded ASCII value at each location Thus in this example the ASCII values which make up the module model number are found sequentially at locations 1011H 1013H 1015H 1017H 1019H 101BH and 101DH 35 EXTENDEDSTATUS base 80H and STATUS CONTROL REGISTERS base 8 1H Writing to the Status Control Register controls the red and green LEDs enables disables interrupts from any of the four ports and indicates whether or not an interrupt is pending base 080H YTKF base 081 12 15 SEE 16151 1 Jo Red LED SYSFAIL Green LED VMEbus Interrupt Pending VMEbus Interrupt Enable Change Register 0 Interrupt Enable Change Register 1 Interrupt Enable Change Register 2 Interrupt Enable Change Register 3 Interrupt Enable Change Register 0 Status Change Register 1 Status Change Register 2 Status Change Register 3 Status Read only Bit Not Used Read Write Bit Figure 3 2 Extended Status 080H and Status Control Registers 081H Note The Extended Status and Status Control Registers can be accessed as a single 16 bit
40. l be used as the clock for a serial communication bus protocol which is still being finalized A reserved signal which will be used as the transmission line for senal communication bus messages SYSTEM CLOCK A constant 16 MHz clock signal that is independent of processor speed or timing It is used for general system timing use 4 2 12 Manual August 1989 Table VMEbus Signal Identification cont d Connector Signal and Mnemonic Pin Number SYSFAIL SYSRESET WRITE V STDBY 1B 31 45V A32 32 1 32 2B 1 13 32 1C31 1 31 Signal Name and Description SYSTEM FAIL Open collector driven signal that indicates that a failure has occurred in the system It may be generated by any module on VMEbus SYSTEM RESET Open collector driven signal which when low will cause the system to be reset WRITE Three state driven signal that specifies the data transfer ae in progress to be either read or written A high level indicates a read operation a low level indicates a write operation 5 VDC STANDBY This line supplies 5 VDC to devices requiring battery backup 5 VDC POWER Used by system logic circuits 12 VDC POWER Used by system logic circuits 12 VDC POWER Used by system logic circuits B 5 XVME 212 Manual August 1989 SYSFAIL SYSRESET WRITE V STDBY V Table VMEbus Signal Identification cont d Connector and Pin Number 18
41. l the input module Each digital 15 protected and 18 of maximum reverse bias of 50V DC 212 or 65V DC XVME 212 2 Also the board be jumpered to occupy any IK block within the short I O address space The following two versions of the XVME 212 are available 212 The 1 version of the XVME 212 comes with an on board 12V DC isolated power supply The 12V supply is factory connected to the input of each channel thus permitting the system to monitor 12V relay contacts and switches without an external wer supply Voltages other than the 12V may be applied to the inputs within the 10V OV input range I some board modification will be necessary ie cutting the well identified and easily accessible PC traces to the 12V on board supply 212 2 The 2 version of the XVME 212 is very similar to the version except for the range of allowable input voltage and the absence of an on board 12 DC power supply The XVME 212 2 has TIL level inputs with a 65V maximum input In addition the 12 isolated on board power supply is not available replaced by wire jumpers to the existing 45V supply of the backplane 1 22 MANUAL STRUCTURE This first chapter provides a functional overview of the XVME 212 and presents the features of Standard I O architecture Operational aspects of XVME 212 then explained in the following fashion Chapter 2 In
42. n If Jumper is installed Switch 8 on Switch bank 51 must be set to OPEN If Jumper J3B is installed Switch 8 must be set to CLOSED The Standard I O Architecture recommends that the XVME 212 operate within the Short I O Address Space in order to take of the Standard Architecture s various features which are described Appendix If required XVME 212 operate in the Standard Address pow Note that in this mode the XVME 212 will always reside within the Eu 64 of the Standard Memory Address Space 1 the address range 000H is FFFFFFH SI switches 1 through 6 then determines which IK block of the upper 64 Kbyte segment is to be occupied 2 4 3 Supervisory N on Privileged Mode Selection The XVME 212 can be configured to respond only to supervisory access or to both non gue and supervisory accesses by selecting the poe of Switch 7 located in witch Bank Sl see Figure 2 2 as shown in Table 2 4 below Table 2 4 Privilege Options Privilege Mode Selected Closed Supervisory or Non privileged Open Supervisory Only 2 4 4 Address Modifier Reference Table 2 5 below indicates the actual VMEbus Address Modifier code that the XVME 212 will respond to based on the position of the options discussed in the previous two sections 2 7 212 Manual August 1989 Table 2 5 Address Modifier Code Options Jumper XVME 212 J3 Address Modifier Code Normal 29H or 2DH Shor
43. nel 2 point point B Change Register resd Date register read causing the scanner to stop causing the scenner to restert after the current scan Figure 3 6 Relationship of Input Channel Signals with Respect to Stopping the Scanner The Data and Change Registers contain the following data at the end of the designated Scan Change Register bits Data Register bits After scan X Y n 0 0 1 n 2 n 3 Change Register read at point A Data Register read at point B Please note the following 1 The pulse on line z was undetected because its rising AND falling edge occurred while the scanner was stopped 2 The pulse on line x is detectable by the host even though the line reverted to its original state during scan n 2 because Change Register bit x remained set 212 Manual August 1989 3 The read at point was the data present at the start of scan because the data registers are not updated while the scanner is stopped 4 The data read at point B caused Change Register bit y to clear Polled operation is enhanced by bits 8 1 of the Extended Status Register These bits are set when the scanner detects any change bit set in a Change Register These bits can be polled to quickly determine whether any of the input channels have changed state since the CPU last read the Data Registers f bits 8 11 are zero then no input channels have changed since the CPU last read the Data Registers and the
44. o S1 6 2 4 2 4 2 Address Space Selection J3 2 7 2 4 3 Supervisory Non privileged Mode Selection 2 7 2 4 4 Address Modifier Reference 2 7 2 4 5 Interrupt Level Switches S2 2 8 2 4 6 IACK Enable Jumpers 71 12 2 8 2 4 7 Debounce Period Jumpers J4 J11 2 9 2 5 Installation 2 9 2 5 1 Installation Procedure 2 11 2 6 Digital Input Connections 2 11 2 7 Mechanical Switch Relay Operation 2 13 2 7 1 212 1 2 13 2 7 2 212 2 2 13 3 PROGRAMMING 3 1 Introduction 3 1 3 2 Base Addressing 3 1 3 3 I O Interface Block 3 3 3 4 Identification 01 to 3FH 3 3 3 5 Extended Status and Status Control Registers 3 5 3 5 1 Extended Status and Status Control Register 3 6 Bit Definitions 3 6 Interrupt Acknowledge IACK Vector Register 3 8 3 8 Change Registers 3 9 3 9 Scanner 3 10 3 9 1 Scanner Operation 3 10 3 9 2 Stopping the Scanner 3 10 3 9 3 Restarting the Scanner 3 11 3 10 VMEbus Interrupts 3 11 212 Manual August 1989 TABLE CONTENTS cont d CHAPTER TITLE PAGE 3 11 Programming Considerations 3 13 3 12 Resetting the Module 3 15 APPENDICES XYCOM STANDARD I O ARCHITECTURE VMEbus CONNECTOR PIN DESCRIPTION SCHEMATICS AND DIAGRAMS gt QUICK REFERENCE GUIDE LIST OF FIGURES FIGURE TITLE PAGE 1 1 Operational Block Diagram of the 212 1 2 2 1 X VME 212 Jumpers Switches and Connectors 2 2 2 2 Switch Bank 51 Base Address Switches 2 5 2 3 VMEbus Chassis 2 10 3 1 XV
45. o indicate that it is using the bus BUS CLEAR Totem pole driven signal generated by the bus arbitrator to request release by the DTB master if a higher level is requesting the bus BUS ERROR Open collector driven signal generated by a slave It indicates that an unrecoverable error has occurred and the bus cycle must be aborted BUS GRANT 0 3 IN Totem pole driven signals generated by the Arbiter or Requesters Bus Grant In and Out signals form a daisy chained bus grant The Bus Grant In signal indicates to this board that it may become the next bus master BUS GRANT 0 3 OUT Totem pole driven signals enerated by Requesters These signals indicate that a TB master in the daisy chain requires access to the bus B 2 2 12 Manual August 1989 Signal Mnemonic BR0 BR3 DS0 DSI DTACK 200 015 GND Table B l Connector and Pin Number 1 12 15 1 13 1 12 1A 16 Q 4544 1A 9 11 15 17 19 1B 20 23 IC 9 2B 2 12 223 VMEbus Signal Identification cont d Signal Name and Description BUS REQUEST O 3 Open collector driven signals generated Requesters ese signals indicate that a DTB master in the daisy chain requires access to the bus DATA STROBE 0 Three state driven signal that indicates during byte and word transfers that a data transfer will occur on data buss lines D00 D07 DATA STROBE 1 Three state driven signal that indicates during byt
46. ock contains all of the module s programming registers and ID data Within the I O Interface Block the offsets are standardized so that the user may expect to find the same registers and data at the same offsets across the entire Xycom VMEbus line 1 2 2 12 Manual August 1989 Module identification XVME 212 has ID information which provides its name model number manufacturer and revision level at a location that is consistent with other Xycom modules Status Control Register This register is always located at address base 8 and the lower four bits two Test Status bits and a red and green LED bit are standard from module to module A detailed description of Xycom Architecture is presented in Appendix A at the rear of this manual 1 5 XVME 212 MODULE SPECIFICATIONS Table 1 1 XVME 2 12 Module Specifications Characteristic Specification Number of Channels q 3 Input Voltage Range 212 50V DC max Logic 1 10 to 50 DC Logic 0 0 to IV DC Typical threshold 3V DC Input Voltage Range XVME 212 2 65V DC max Logic 1 2 to 65V DC Logic 0 0 to 08V DC Typical threshold 12V DC Input Impedance XVME2 12 1 39K 5 Input Impedance 2 12 2 330 5 Propagation Delay with fastest debounce selected Of f to on
47. protocol Interprocessor Communication Protocol in this case The intelligent kernel is based around either 68000 microprocessor or a 68809 microprocessor the XVME 164 MBMM This design provides the full complement of VMEbus Requester and Interrupter options for master slave interfacing as well as all of the advantages provided by the various facets of the XYCOM Standard I O Architecture as covered earlier in this appendix The non intelligent kernel provides the circuitry required to receive and generate all of the signals for a VMEbus defined 16 bit slave module The non intelligent kernel also employs the features of XYCOM Standard Architecture as described earlier in this Appendix A 9 212 Manual August 1989 Appendix VMEbus CONNECTOR PIN DESCRIPTION XVME 212 Processor Module is a double high VMEbus compatible board There is one 96 pin bus connector on the rear edge of the board labeled refer to Chapter 2 Figure 2 1 for the location The signals carried by connector PI are the standard address data and control signals required for a Pl backplane interface as defined by the VMEbus specification Table B l identifies and defines the signals carried by the PI connector Table Pl VMEbus Signal Identification Signal Mnemonic ACFAIL IACKIN IACKOUT 0 5 5 Connector and Pin Number B 3 IA21 1A 22 Signal Name and Description
48. rd is operating properly On non intelligent XVME I O modules the status control register is used to indicate the state of the front panel LEDs and to set and verify module generated interrupts The LED status bits are Read Write locations which provide the user with the indicators to accommodate diagnostic software The Interrupt Enable bit is also Read Write location which must be written to in order to enable module generated interrupts The Interrupt Pending bit is a Read Only bit indicating a module generated pending interrupt 7 212 Manual August 1989 Figure 4 shows the status control register bit definitions for both intelligent and intelligent I O modules INTELLIGENT NON INTELLIGENT MODULES MODULES RED LED RED LED GREEN LED GREEN LED TEST STATUS INTERR PENDING TEST STATUS INTERR ENABLE MODULE DEPENDENT Non Intelligent Modules 1 Intelligent Modules Read Write Red LED Read Only Red LED 0 Red LED On 0 Red LED ON 1 Red LED Off 1 Red LED Off Read Write Green LED Read Only Green LED 0 Green LED Off 0 Green LED Off 1 Green LED On 1 Green LED On Read Only Interrupt Pending Read Only Test Status Indicators 0 No Interrupt Bit3 Bit2 1 Interrupt Pending 0 Self test not started 1 Self test in progress 0 Self test failed 1 Self test passed Read Write Interrupt Enable 0 Interrupts Not Enabled 1 Interrupts Enabled Modul
49. re is no need to read the Data Registers again Polling the Extended Status Register instead of the Change Registers has two advantages First because the scanner is not stopped it doesn t have to be restarted after the read Secondly Status Register reads are faster because the scanner does not have to be stopped before DTACK is asserted It is therefore suggested that bits 8 1 of the Extended Status be polled instead of polling the Data or Change Registers directly It is not necessary to read the Change Registers at all if the user is not concerned about which individual bit in the change register is set In these cases the user would simply read the Data Registers when the module generated an interrupt in interrupt driven environments or when the status bits 8 11 indicate a change has occurred in polled environments 3 12 RESETTING THE MODULE The module is reset by the assertion of the VMEbus reset signal In response to a reset the module will do the following bits of the Extended Status and Control Status Registers will be reset to zero Note that this resets all Interrupt Enable bits of the Status Control Register so the VMEbus interrupt currently opu generated by the XVME 212 will be negated and the SYSFAIL will be asserted on the VMEbus because bit O is reset to zero The scanner is stopped and the Data and Change Registers are reset to zero After the reset signal is aed the scanner will start scanning Before the first
50. ring module specific information in an ASCII encoded format The I D data is provided as 32 ASCII encoded characters consisting of the board type manufacturer identification module model number number of IK byte blocks occupied by the module and module functional revision level information This information can be read by the system rocessor on power up to verify the system configuration and operational status Table defines the identification information locations 3 3 212 Manual August 1989 Table 3 1 Identification Data Offset Relative to Contents ASCII Encoding Module Base in hex ID PROM identifier always VMEID 5 characters Manufacturer s I D always XYC for XYCOM modules 3 characters Module Model Number 3 characters and 4 trailing blanks NEN Oxx OTMe lt Number of byte blocks of space occupied by this module 1 character Major functional revision level with leading blank if single digit Minor functional revision level with trailing blank if single digit Manufacturer Dependent Information Reserved for future use 3 4 212 Manual August 1989 The module has been designed so that it is only necessary to use odd backplane addresses to access the L D data Thus each of the 32 bytes of ASCII data has been assigned to the first 32 odd I O Interface Block bytes i e odd bytes 1H 3FH In this way I D information can be accessed by address
51. scan all Data and Change Registers will be zero Therefore after a reset when an input channel is detected as on its corresponding Change Register bit will be set 212 Manual August 1989 Appendix XYCOM STANDARD 1 0 ARCHITECTURE INTRODUCTION The purpose of this appendix is to define XYCOM s Standard I O Architecture for IO modules This Standard Architecture has been incorporated on all programming for the entire module line The I O Architecture specifies the logical aspects of bus interfaces as opposed to the physical or electrical aspects as defined in the VMEbus specifications The module elements which are standardized by the XYCOM Architecture are the following Module Addressing Where a module is positioned in the I O address space and how soltware can read from it or write to it Module Identification How software can identify which modules installed in a system 3 Module Operational Status How the operator can through software determine the operational condition of specific modules within the system 4 Interrupt Control How software is able to control and monitor the capability of the module to interrupt the system 2 Communication between Modules How master host processors and intelligent I O modules communicate through shared global memory or the dual access RAM on the modules 6 The I O Kernel How intelligent and non intelligent kernels facilitate th
52. stallation Information required to position the jumpers and switches on the XVME 212 and install the module in a VMEbus chassis Chapter 3 Programming Information required to program the XVME 212 and read digital input signals The appendices at the end of this manual provide information 8 Standard I O Architecture VMEbus connector pin descriptions module schematics as well as a quick reference guide to the module s jumpers and registers 141 212 Manual August 1989 13 OPERATIONAL BLOCK DIAGRAM Figure 1 1 shows operational block diagram of the 212 CHANNELS CHANNELS 0 15 16 31 CONNECTOR JK1 CONNECTOR JK2 OPTICAL ISOLATOR DEBOUNCING STANDARD VO INTERFACE SCANNER CHANGE REGISTERS DATA REGISTERS VMEbus INTERFACE VMEbus Figure 1 1 Operational Block Diagram of the X VME 212 1 4 FEATURES OF XYCOM S STANDARD I O ARCHITECTURE The XVME 212 and all Xycom I O modules conform to the unique Xycom VMEbus Standard I O Architecture This architecture is intended to make the programming of Xycom VMEbus I O modules simple and consistent The following features apply to the operation of the X VME 212 Module address space 212 and VMEbus modules controlled by writing to addresses within the 64K Short 1 Address space VMEbus module can be switched to occupy any of the 64 available 1K blocks This block known as the I O Interface Bl
53. t 2DH only Standard 39H or 3DH Address 3DH only 2 45 Interrupt Level Switches S2 The three Interrupt Level Switches select which VMEbus interrupt level is to be used by the module The XVME 212 can be programmed to generate an interrupt whenever a of state is detected input line these switches will determine level of that interrupt Interrupt Level Switches are defined in Table 2 6 Table 2 6 Interrupt Level Switches 52 VMEbus Intemupt Level OPEN OPEN OPEN OPEN OPEN CLOSED OPEN CLOSED OPEN OPEN CLOSED CLOSED CLOSED OPEN OPEN CLOSED OPEN CLOSED CLOSED CLOSED OPEN CLOSED CLOSED CLOSED None interrupts disabled 2 4 6 IACK Enable Jumpers J2 When operating in an interrupt environment the module uses the VMEbus IACK daisy chain to determine which module gets acknowledged if two or more modules share one of the interrupt request lines When the module is never going to be used in an interrupt environment the daisy chain through the module can be bypassed to speed up the IA arbitration This is controlled by Jumpers and J2 as shown in Table 2 7 Table 2 7 IACK Enable Jumpers Module uses IACK daisy chain Module bypasses IACK daisy chain 2 8 212 Manual August 1989 When in the position the module cannot respond to interrupts because IACKIN is not monitored is connected directly to IACKOUT instead When used in this configura
54. tion all poles of S2 should be closed to ensure that a programming bug does not generate VMEbus interrupts When interrupts are going to be used the jumpers must be in the B position 2 4 7 D ebounce Period Jumpers J4 J 11 When a mechanical switch closes several contact bounces can be expected Several transitions or quickly changing input images can appear while the switch bounces To eliminate these bounces circuitry is provided which works as follows When a change is detected in an input the change is not immediately reported to the scanner Instead a timer with time period T will start accumulating time During this time T if the input reverts to its original state bounces the timer is restarted and the change is not reported If the input does not bounce for the duration of time T the change will be reported to the scanner at the end of time period T This means that the input must assume the new state and stay in the new state without bouncing for time T before the change is reported to the scanner The value of time T is selectable via eight on board jumpers One and onlv one jumper must be installed This jumper defines the time T to be used by all 32 channels The following table shows the available selections Table 2 8 Debounce Period Jumpers Note One and only one of the above jumpers must be installed for proper module operation Note that the time associated with is very short with respect to
55. to 1 2 no VMEbus interrupt will be generated 3 6 212 Manual August 1989 4 1 Change Register n Interrupt Enable These bits individually enable the Change Registers to generate VMEbus interrupts whenever any bit in a Change Register is set Writing a 1 in one of these bits enables interrupts from a specific Change Register writing 0 disables interrupts from the register Bit 4 Enables disables Change Register 0 Bit 5 Enables disables Change Register 1 Bit 6 Enables disables Change Register 2 Bit 7 Enables disables Change Register 3 3 7 2 12 Manual August 1989 8 11 Change Register n Status Change Register Status bits Bit 8 Status of Change Register 0 Bit 9 Status of Change Register 1 Bit 10 Status of Change Register 2 Bit 11 Status of Change Register 3 When the scanner detects a bit set in a Change Register it will set the appropriate above bit to 1 These bits are reset to zero when the corresponding Data Register is read These bits may be polled to quickly determine whether any Change Registers have bits set These bits are not conditioned by any one of the interrupt enable bits 4 7 12 15 Not used 3 5 2 Generating VMEbus Interrupts Bits 4 7 of the Status Control Register are individually ANDed with bits 8 11 The results of the ANDs are ORed together to produce bit 2 Bit 2 is ANDed with bit 3 and when the result of this AND is 1 a VMEbus interrupt will be gener

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