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2. 8 oss Pri 9 3 a 6 TxD GND 10 45 u 35 V2727 G28 V28 12 23 24 12 85 TXDB 4 5i 5 GND 11 86 36 INT4 GND RST V2929 amp 30 GND 25 5 626 GND 07 4 VRAM 12155 apy 37 WR 7RD GND 3131 5 232 32 HDRD26 1 49 vcc 8 vec Yok LTC485 7 vcc 13 yec 38 P14 3333 6 34 GND 2127 wp GND U23 vec GND 14 ae jog 39 15 GND V3535 lt lt 36 GND 3 55 sci 222 RXDB 1 amp 5 vcc 89 GND 15120 55 40 A13 GND 37 38 GND GND 4 sUa P29 XTAL2 ND p BXD GND 16 33 4l RST 39 5 G40 12VI x3 3 bg AL S BXD A4 17 23 wr 42 GND GND GND HDRD40 24 045 iL 9 4 D 5 18105 43 D1 DO go Z 16 2 19 44 D3 D2 1 STE TERN LEST AA LTC485 20 4 D5 D4 U16 10K 7 R1 11 DO 21 46 D7 D6 Title GND 1 C15 LC p 22 59 27 GND V3 5 GNG 4 vec TED D2 23 D1 D8 48 Do R Drive Version L with 100M Ethernet vec VV INT2 9 680 24 02 09 49 pio Size Document Number REV 1 7 vorr 1 2 GND 25 WE 010 115 o ETT CD2 GND RL MAN SCH Date December 9 2003 Sheet war 1
3. 29F40R HEX will erase the remaining sectors for downloading your application HEX file 4 3 Chapter 4 Software RL ACTF Utility Debug Kernel re40 115 OxFA000 0x80000 0x20000 4 512K SRAM 128K SRAM Beginning of 0x08000 application in STEP 1 amp 2 0x00000 For production the user must produce an ACTF downloadable HEX file for the application based on the DV P The application HEX file can be loaded into the on board Flash starting address at 0x80000 or 0xC0000 The on board EE must be modified with G80000 or GC0000 command while in the ACTF PC HyperTerminal Environment The STEP2 jumper J2 pins 38 40 must be installed for every production version board All files needed to erase write flash and debug kernels are found in the tern 186 rom re directory Step 1 settings In order to correctly download a program in STEPI with Paradigm C C the RL must meet these requirements 1 re40_115 hex must be pre loaded into Flash starting address Oxfa000 re80_115 hex for 80MHz version 2 The SRAM installed must be large enough to hold your program For a 128K SRAM the physical address is 0x00000 0x01 ffff For a 512K SRAM the physical address is 0x00000 0x07ffff 3 The on board EE must have a correct jump address for the 40 115 HEX with starting address of Oxfa000 4 The STEP2 jumper must be installed on J2 pins 38 40 4 4 RL Chapter 4 Softwa
4. For more detailed information refer to the SC26C92 data sheets Phillips Semiconductors or on the CD in the tern docs parts directory Sample programs for the SC26C92 can be found in the c tern 186 samples r1 directory See tern 186 samples rl rl ide 3 7 Other Devices A number of other devices are also available on the RL Some of these are optional and might not be installed on the particular controller you are using For a discussion regarding the software interface for these components please see the Software chapter 3 8 RL Chapter 3 Hardware On board Supervisor with Watchdog Timer The MAX691 LTC691 U6 is a supervisor chip With it installed the RL has several functions watchdog timer battery backup power on reset delay power supply monitoring and power failure warning These will significantly improve system reliability Watchdog Timer The watchdog timer 1s activated by setting a jumper on J9 of the RL The watchdog timer provides a means of verifying proper software execution In the user s application program calls to the function hitwd a routine that toggles the P29 WDI pin of the MAX691 should be arranged such that the pin is accessed at least once every 1 6 seconds If the J9 jumper is on and the WDI pin is not accessed within this time out period the watchdog timer pulls the WDO pin low which asserts RESET This automatic assertion of RESET may recover the application program if something is w
5. after init function call Input with pull up J2 pin 13 Input with pull up Input with pull up J2 pin 31 Input with pull up Input with pull up J2 pin 5 Input with pull up Input with pull up J2 pin 3 Input with pull up Input with pull down N A Output Input with pull down J2 pin9 Input with pull up Input with pull up J2 pin 17 Input with pull up Input with pull up J2 pin 18 Input with pull up Input with pull up J2 pin 4 Input with pull up Input with pull up J2 pin 34 Input with pull up J2 pin 32 S6 CLKSEL1 Input with pull up J9 pin 2 Input with pull up INT4 Input with pull up U9 pin 14 Input with pull up INT2 Input with pull up U9 pin 16 Input with pull up Note P6 P26 and P29 must NOT be forced low during power on or reset Table 3 1 I O pin default configuration after power on or reset The 32 PIO lines PO P31 are configurable via two 16 bit registers PIOMODE and PIODIRECTION The settings are as follows MODE PIOMODE reg PIODIRECTION reg PIN FUNCTION 0 0 0 Normal operation 1 0 1 INPUT with pull up pull down 2 1 0 OUTPUT 3 1 1 INPUT without pull up pull down RL initialization on PIO pins in ae init is listed below outport Oxff78 0xc7bc PIODIRI TxD RxD 16 50 P17 PCS1 outport Oxff76 0x2040 PIOMI outport Oxff72 0xec73 PDIRO P12 OUTPUT P2 PCS6 P3 PCS5 outport Oxff70 0x 1040 PIOMO P6 INPUT P7 A17 P8 A18 The C function in the lib
6. poke is used for writing 16 bits at a time and pokeb is used for writing 8 bits The process of placing data into memory space means that the appropriate address and data are placed on the address and data bus and any memory space mappings in place for this particular range of memory will be used to activate appropriate chip select lines and the corresponding hardware component responsible for handling this data peek peekb Arguments unsigned int segment unsigned int offset Return value unsigned int unsigned char data 4 Chapter 4 Software RL These functions retrieve the data for a specified address in memory space Once again the segment address is shifted left by four bits and added to the offset to find the 20 bit address This address is then output over the address bus and the hardware component mapped to that address should return either an 8 bit or 16 bit value over the data bus If there is no component mapped to that address this function will return random garbage values every time you try to peek into that address outport outportb Arguments unsigned int address unsigned int unsigned char data Return value none This function is used to place the data into the appropriate address in I O space It is used most often when working with processor registers that are mapped into I O space and must be accessed using either one of these functions This is also the function used in most cases when dealing with user configur
7. 2 Mode Select Command Word The RL maps US the 82C55 uPD71055 at base I O address 0x1A0 The ports registers are offsets of this I O base address The command register 0x1A6 Port 0 0x1A0 Port 1 0x1A2 Port 2 Ox1AA The following code example will set all ports to output mode outportb 0x1A6 0x80 mode 0 output all pins outportb 0x1A0 0x55 Port 0 alternating high low on pins outportb 0x1A2 0x55 Port 1 alternating high low on pins outportb 0x1A4 0x55 Port 2 alternating high low on pins To set all ports to input mode outportb 0x1A6 9 mode 0 input all pins 3 7 Chapter 3 Hardware RL You can read the ports with inportb 0x1A0 port 0 inportb 0x1A2 port 1 inportb 0x1A4 port 2 This returns an 8 bit value for each port with each bit corresponding to the appropriate line on the port where the most significant bit refers to Ix7 and the least significant bit refers to Ix0 PPI lines are routed to high voltage drivers at U11 U12 and U13 with the corresponding high voltage outputs routed to See section on high voltage drivers for alternate configurations 127 124 are routed to the J2 pin header Real time Clock DS1337 The DS1337 serial real time clock is a low power clock calendar with two programmable time of day alarms and a programmable square wave output Address and data are transferred serially via a 2 wire bidirectional bus The clock calendar provides
8. 4 Software void intx init Arguments unsigned char i void interrupt far intx isr Return value none These functions can be used to initialize any one of the external interrupt channels for pin locations and other physical hardware details see the Hardware chapter The first argument i indicates whether this particular interrupt should be enabled or disabled The second argument is a function pointer which will act as the interrupt service routine The overhead on the interrupt service routine when executed is about 20 us By default the interrupts are all disabled after initialization To disable them again you can repeat the call but pass in 0 as the first argument The NMI Non Maskable Interrupt is special in that it can not be masked disabled The default ISR will return on interrupt void intO init unsigned char i void interrupt 0 isr void intl init unsigned char i void interrupt intl isr void int2 init unsigned char i void interrupt int2 isr void int3 init unsigned char i void interrupt ints 15r void int4 init unsigned char i void interrupt int4 isr void nmi init void interrupt far nmi isr 4 3 3 VO Initialization Two ports of 16 I O pins each are available on the RL Hardware details regarding these PIO lines can be found in the Hardware chapter Several functions are provided for access to the PIO lines At the beginning of any application where you choose to use the PIO pin
9. 767 1 092 1 492 1 242 5 E Hoeonooooooonooooo orooOcoOooQGoOLooodgIII z aGDODDOGGOGODD QODDDODOOGOGODODOGODODL AD 0 2 0 433 acODDOoDnOGOODOODDDOOn COD 4 85 0 967 1 275 0 208 3 525 0 208 3 70 0 133 0 00 0 00 1 2 vec 1 Ul 29F800 U3 U18 U21 vcc 1 2 011 GND 40 39 vec vec 1 2 GND A16 l iis aie 48 A17 Al 1f a5 15 44 16 A5 1 c5 i kare 169 TXDO 3 2 e Ac Mir dll galien P4 38 2 e 37 P14 3 2 4 CLK A15 2 47 VCC A2 2 43 A15 2 v 2 15 GND 7RXDO 5 6 116 2 15 V2 36 35 P6 5 6 GND a gt A14 BY Al 14 v GND 2B 2C A14 3 213 46 CND A3 325 a13 A2 A14 3 C5 3 1 14 7 7 6 6 9 115 3 55 c L14 V3 5 e 33 7 5 8 00 A13 4 412 515 29 D15 A4 4 43 JOE 41 RD C2 4 65 13 GND 9 10 114 4 13 v4 RXDO 32 OO 31 P19 9 DO 10 Di A12 5 p 43 07 AS 5 20 5 c2 mio 12 113 5 5 12 V5 P5 30 G 29 BHE 11 0 12 p2 A11 61210 6 39 AO RST 6 612 LLLLIXDA 1 9 o2 112 6 V6 28 5 o 27 P2 D1513 5 14 03 A10 pe 2206 157 7 56 pis 38 015 T J4TXDO 7 10 IXDO TXDA 3 5 G4 7 75 7 10 V7 RXDA26 5 o 25 19 RST15 16 D4 A9 8 41 D13 D6 8 37 D14 5 7 CF RXD0 8 9 RXDO RXDA 5 6 8 9 K 24 23 P15 RST 17 18 D5 9 28 P13 40 ps ps 9 P1
10. A18 A17 P2 PCS6 outport 0xff70 0x1000 PIOMO P3 PCS5 The chip select lines are set to 15 wait states by default This makes it possible to interface with many slower external peripheral components If you require faster I O access you can modify this number down as needed Some TERN components such as the Real Time Clock might fail if the wait state is decreased too dramatically A function is provided for this purpose void io wait Arguments char wait Return value none This function sets the current wait state depending on the argument wait wait 0 wait states 0 I O enable for 100 ns wait 1 wait states 1 I O enable for 100 425 ns wait 2 wait states 2 I O enable for 100 50 ns wait 3 wait states 3 I O enable for 100475 ns wait 4 wait states 5 I O enable for 1004125 ns wait 5 wait states 7 I O enable for 1004175 ns wait 6 wait states 9 I O enable for 100 225 ns wait 7 wait states 15 I O enable for 100 4375 ns 4 3 2 External Interrupt Initialization There are up to six external interrupt sources on the RL consisting of five maskable interrupt pins INT4 INTO and one non maskable interrupt NMI There are also an additional eight internal interrupt sources not connected to the external pins consisting of three timers two DMA channels both asynchronous serial ports and the NMI from the watchdog timer For a detailed discussion involving the ICUs the user should r
11. As a result your PC may hang up In extreme cases a power reset may be required to restart your PC For your reference be aware that our system is remote kernel interrupt driven for debugging The run time environment on TERN controllers consists of an I O address space and a memory address space I O address space ranges from 0x0000 to Oxffff or 64 KB Memory address space ranges from 0x00000 to Oxfffff in real mode or 1 MB These are accessed differently and not all addresses can be translated and handled correctly by hardware I O and memory mappings are done in software to define how translations are implemented by the hardware Implicit accesses to I O and memory address space occur throughout your program from TERN libraries as well as simple memory accesses to either code or global and stack data You can however explicitly access any address in I O or memory space and you will probably need to do so in order to access processor registers and on board peripheral components which often reside in I O space or non mapped memory This is done with four different sets of similar functions described below poke pokeb Arguments unsigned int segment unsigned int offset unsigned int unsigned char data Return value none These standard C functions are used to place specified data at any memory space location The segment argument is left shifted by four and added to the offset argument to indicate the 20 bit address within memory space
12. P10 12 11 P13 WR 29 30 A6 10 9 P23 RD 31 32 5 INTO 8 7 NMI D11 33 34 A4 INTI 6 5 SCLK D10 35 36 A3 P26 4 3 SDAT D9 37 38 A2 GND 2 1 D8 39 40 Al Table 3 3 Signals for J2 and J1 20x2 expansion ports RL Chapter 4 Software Chapter 4 Software Please refer to the Technical Manual of the C C Development Kit for TERN 16 bit Embedded Microcontrollers for details on debugging and programming tools An IDE project for the RL has been pre built for your convenience It is located in the tern 186 samples rl directory The filename is rl ide It includes sample code linked to the correct libraries ready to run and access RL hardware Guidelines awareness and problems in an interrupt driven environment Although the C C Development Kit provides a simple low cost solution to application engineers some guidelines must be followed If they are not followed you may experience system crashes PC hang ups and other problems The debugging of interrupt handlers with the Remote Debugger can be a challenge It is possible to debug an interrupt handler but there is a risk of experiencing problems Most problems occur in multi interrupt driven situations Because the remote kernel running on the controller is interrupt driven it demands interrupt services from the CPU If an application program enables interrupt and occupies the interrupt controller for longer than the remote debugger can accept the debugger will time out
13. P10 P17 SEL80 SELAO AVR SELCO jap SELFO PCSO P20 P27 Figure 3 1 Interface the RL to external I O devices The function ae_init by default initializes the PCSO line at base I O address starting at 0x00 You can read from the 82C55 with inportb 0x020 or write to the 82C55 with outportb 0x020 dat The call to inportb 0x020 will activate PCSO as well as putting the address 0x00 over the address bus The decoder will select the 82C55 based on address lines A5 7 and the data bus will be used to read the appropriate data from the off board component Programmable Peripheral Interface 82C55A U5 PPI 82C55 is a low power CMOS programmable parallel interface unit for use in microcomputer systems It provides 24 I O pins that may be individually programmed in two groups of 12 and used in three major modes of operation In MODE 0 the two groups of 12 pins can be programmed in sets of 4 and 8 pins to be inputs or outputs In MODE 1 each of the two groups of 12 pins can be programmed to have 8 lines of input or output Of the 4 remaining pins 3 are used for handshaking and interrupt control signals MODE 2 is a strobed bi directional bus configuration See data sheet for details on different mode tern_docs parts 82c55a pdf 3 6 RL Chapter 3 Hardware Command 0 Bit Select manipulation 1 Mode Select Figure 3
14. The Am186ER from AMD uses times four crystal frequency while the R1100 from RDC uses times eight The RL uses a 10MHz system clock giving the Am186ER a CPU clock of 40MHz and the R1100 CPU clock of 830MHz Both CPUs operate at 3 3V with lines 5V tolerant The RDC 1100 supports the same 80C188 microprocessor instruction set but uses an internal RISC core architecture 3 2 Am186ER Introduction The Am186ER is based on the industry standard x86 architecture The Am186ER controllers are higher performance more integrated versions of the 80C188 microprocessors In addition the Am186ER has new peripherals The on chip system interface logic can minimize total system cost The Am186ER has one asynchronous serial port one synchronous serial port 32 PIOs a watchdog timer additional interrupt pins DMA to and from serial ports a 16 bit reset configuration register and enhanced chip select functionality In addition the Am186ER has 32KB of internal volatile RAM This provides the user with access to high speed zero wait state memory In some instances users can operate the RL without external SRAM relying only on the Am186ER s internal RAM 3 3 RDC R1100 Introduction The RDC 1100 is based on RISC internal architecture while still supporting the same 80C188 microprocessor instruction set It provides faster operation than the Am186ER allowing it to operate at up to 80MHZ based a 10MHz system clock and times eight crystal oper
15. format that must be followed for all calls to SER2 4 Other SCC functions are similar to those for SERO and SERI sn close serhitn clean_sern 4 17 Chapter 4 Software RL 4 6 Functions in AEEE OBJ The 512 byte serial EEPROM 24C04 provided on board allows easy storage of non volatile program parameters This is usually an ideal location to store important configuration values that do not need to be changed often Access to the EEPROM 15 quite slow compared to memory access on the rest of the controller Part of the EEPROM is reserved for TERN use specifically for this purpose Addresses 0x00 to 0x1f on the EEPROM is reserved for system use including configuration information about the controller itself jump address for Step Two and other data that is of a more permanent nature The rest of the EEPROM memory space 0x20 to Ox1ff is available for your application use ee wr Arguments int addr unsigned char dat Return value int status This function is used to write the passed in dat to the specified addr The return value is 0 in success ee rd Arguments int addr Return value int data This function returns one byte of data from the specified address 4 7 File System TERN libraries support FAT12 16 file system for the Compact Flash interface Refer to Chapter 4 of the FlashCore technical manual tern docswnanualsMlashcore pdf for a summary of the available routines The libraries and header files are as follo
16. its operation and software drivers The following section will discuss SER1 2 and SERA B which pertain to the external SCC26C92 UARTs SER 1 2 A B will be easier to implement in applications as they can be directly debugged in the Paradigm C C environment TERN interface functions make it possible to use one of a number of predetermined baud rates These baud rates are achieved by specifying a divisor for 1 16 of the processor frequency The following table shows the function arguments that express each baud rate to be used in TERN functions for SERO ONLY SERI and SER2 have baud rated based upon different arguments These are based on a 40 MHz CPU clock the 80MHz version will have these rates doubled Chapter 4 Software RL Function Argument Baud Rate 4800 9600 19 200 default 38 400 57 600 115 200 250 000 500 000 1 250 000 28 800 Table 4 1 Baud rate values for ser0 only As of January 25 2004 the new baud rate 28 000 was added The corresponding functional argument is 16 0x10 If the 80Mhz RE is used the baud rate will become 57 600 After initialization by calling sO_init SERO is configured as a full duplex serial port and is ready to transmit receive serial data at one of the specified 15 baud rates An input buffer 5 in buf whose size is specified by the user will automatically store the receiving serial data stream into the memory by DMAO operation In terms of receiving there is no softw
17. o4 2 CND Al 125 C35 RD TXD A ZRD ost c34 Tit 9 312 12 116 V 127 126 0 10 RXDB TXDB 10K RXD2 TXD2 c2 0 1UF 2 10 101 11 252506 C4 09 vec R9 63 Di P2 l ck svL29 RN768 IV GND 0 1UF L 36 12VI 12V RST 2177 19 1 c4 0 1UF 1NT03 5 6 18 INT V1 1 4 2 v2 C38 1N5817 2 4 13 5 17 1 3 oO 4 V4 J3 v 0 1UF eg 1M2575 12V INT2 5 7 6 46 INT2 V5 5 5 amp 5 V6 IN 1 o 2 IN2 XTAL3 U24 CFB INT3 15 63 45 INT3 V7 7 8 IN3 3 5 6 4 INA 06 x6 x5xs 1i cpi b2 INTA7 2 CAINTA V9 9 5 19 vio IN5 5 5 G6 ING MAX691 Jl 32K X6 2 2153 pii E27 eu INTS8 r 5 o1 43 P13 Vilil 0 12 Vi2 IN7 7 5 6 8 IN8 1 pgp 16 VOFF 3 pig 28 p12 INT6 9 73 42 NMI v1313 5 0 14 vi4 IN9 9 5 amp 10 110 VRAM 2 0 15 _ RST xb 4 4 5 pis 22 213 1015 yor Lii 15 15 16 V16 IN11 11 12 IN12 VCC 3 vec woo 14 DO 10K Sloe pia Peo 1717 9 C i8 vis INI3 13 9 14 IN14 4 xD LL3 LC8 xL DS1337 D7 6 55 pis 31015 C27 PAL16V8 visis 9 20 20 v20 INI5 15 9 16 6 S Son LL2 ZRAM 9 002 ckycE2 22_ V2121 2 c 22 V22 IT1 17 2 18 IT2 6 LL WDI 11 wpri 1 2 29 RXDB 1 ko vce 89 GND 8 A10 VS1 33 V23 23 oO 24 V24 IT319 20 ost pro HDRD2 GND 21 IXD RD 91 om 34 1 5817 V2525 G 26 V26 IV 21 5 2 22 IV
18. onboard The CPU s internal UART is used for remote debugging but is also available for user application Two Dual UARTs SC26C92 provide 4 more UARTs All UARTs have deep FIFOs to minimize receiver overrun and to reduce interrupt overhead One RS232 port can be converted to RS485 or RS422 Five power Darlington array chips ULN20034A are installed in five DIP sockets providing a total of 35 high voltage sinking drivers Each driver is capable of sinking 350 mA at 50V per line They can directly drive solenoids relays or lights In place of the ULN20034A s resistor packs or DAC chips with modification can be optionally installed to provide TTL I O or up to 10 analog outputs A total of 20 opto couplers are on board to provide isolation for high voltage inputs Furthermore some control applications need to trigger an event under combined conditions of several sensors switches As a result four of the 20 opto couplers are routed to an on board PAL allowing flexible hardware configurable input logic to trigger interrupts An additional 20 TTL I O lines are available on the J2 pin header including bi directional I Os from the PPI 82C55 and multifunctional CPU internal PIOs 1 1 Chapter 1 Introduction RL Optional high efficient Switching Regulator LM2575 provides an external control pin to shutdown 5V and enter pA standby mode waking up on an active low signal The RL requires 8 5V to 12V DC power supply with default linear regulato
19. out MENU over SERO at 19200 N 8 1 to Hyperterminal of Windows95 98 Text command or download new codes Process Commands See ACTF kit and Functions for detail RUN the program starting at the CS IP The C function prototypes supporting Am186ER hardware can be found in header file ae h in the c tern 186 include directory Read EE for the jump address CS IP Sample programs can be found in the c tern 186 samples ae c tern 186 samples re and tern 186 samples r1 directories There is no ROM socket on the RL The user s application program must reside in SRAM for debugging in STEPI reside in battery backed SRAM for the standalone field test in STEP2 and finally be programmed into Flash for a complete product The on board Flash 29F400BT has 256K words of 16 bits each It is divided into 11 sectors comprised of one 16KB two 8KB one 32KB and seven 64KB sectors The top one 16KB sector is pre loaded with ACTF boot strip the one 8KB sector starting 0xfa000 is for loading remote debugger kernel and the reset all sectors are free for application use The top 16KB ACTF boot strip is protected Two utility HEX files 1 debug HEX L_29F40R HEX are designed for downloading into SRAM starting at 0x04000 with ACTF PC HyperTerminal Use the D command to download and use the command to run DEBUG HEX will erase the 8KB sector and load a 40 115 HEX or 80 115
20. that allow you to check and set the value of these I O pins appropriate for whatever form of flow control you wish to implement Before using these functions you should once again be aware that the peripheral pin function you are using might not be selected as needed For details please refer to the Am186ES User s Manual char cts void Retrieves value of CTS pin void 5 rts char b Sets the value of RTS to b Completing Serial Communications After completing your serial communications you can re initialize the serial port with s1 init to reset default system resources sn close Arguments COM c Return value none This closes down the serial port by shutting down the hardware as well as disabling the interrupt The asynchronous serial I O port available on the Am186ER processor have many other features that might be useful for your application If you are truly interested in having more control please read Chapter 12 of the manual for a detailed discussion of other features available to you 4 5 Functions in SERIR OBJ The functions found in this object file are prototyped in serlr h in the tern 186 include directory In addition prototypes for SER are found in terznN186NincludeNrl h n The routines are the same as found in serlr h except the names of the routines use 3 4 instead of 1 2 For example 51 becomes s3 init and s4 init All discussion in this section about SER1 and SER2 is applicable to to SE
21. the MPO pin on the J1 header can be used for RTS For a sample file showing 5232 full duplex communications please see rl scc c in the directory tern 186 samples r1l RS485 is slightly more complex to use than RS232 RS485 operation is half duplex only which means transmission does not occur concurrently with reception The RS485 driver will echo back bytes sent to the SCC As a result if the RS 485 configuration is used for SER receive must be disabled while transmitting While transmitting the RS485 driver must be placed in transmission mode as well While receiving data the RS485 driver will need to be placed in receive mode sn send e sn rec e Arguments none Return value none This function enables transmission or reception on the SCC26C92 UART for channel where n can be 1 or 2 After initialization both of these functions are disabled by default If you are using RS485 only one of these two functions should be enabled at any one time Transmission and reception of data using the SCC is in most ways identical to SERO The functions used to transmit and receive data are similar For details regarding these functions please refer to the previous section putsern putsersn getsern getsersn The above functions work for both SER1 SER2 SERA and SERB yet it is still important to remember that any function call to SER2 SER4 must pass both COM arguments Refer to the full definition of s2 init and s4 init for the
22. the output buffer manually incrementing the head and tail buffer pointers appropriately If you do not call one of the following functions however the driver interrupt for the appropriate serial port will be disabled which means that no values will be transmitted This allows you to control when you wish the transmission of data within the outbound buffer to begin Once the interrupts are enabled it is dangerous to manipulate the values of the outbound buffer as well as the values of the buffer pointer putsern Arguments unsigned char outch COM c Return value int return_value This function places one byte outch into the transmit buffer for the appropriate serial port The return value returns one in case of success and zero in any other case putsersn Arguments char str COM c Return value int return_value This function places a null terminated character string into the transmit buffer The return value returns one in case of success and zero in any other case DMA transfer automatically places incoming data into the inbound buffer serhitm should be called before trying to retrieve data serhitn Arguments COM c Return value int value This function returns 1 as value if there is anything present in the in bound buffer for this serial port getsern Arguments COM c Return value unsigned char value This function returns the current byte from sn buf and increments the in tail pointer Once again thi
23. 436 Ree 7 0 O78 vec FE i25 22 2 0 21 124 1619 9 Q 20 ps 4 NC D5 D2 D13 101 pi 29_ 12 10 55 12 35 212 74HC138 MAX232D GND 9 10 N ULN2003 PO 20 19 D1421 22 D7 WR TT pa L38 DF 11 voc cnp 34 U22 vec U12 25 31839 OT r24 51323 9 0 51 RST 12 37 VCC GND 12 33 VRAM RN1 vec C34 1 169 1 2 I10 1 16 V8 127 16 2 0 15 126 25 2 0 26 13 Beni D3 13 CUPS VOC E32 D11 c 1209 ve 2131 uuo 15 TXDi 3 e 123 215 as v9 Pil 12 S c T3 Pls D1227 e 28 A7 14 L33 3 D2 14 p5 D10 1 D10 6 21519 19 152 C3 3 c 14 1 2 RXD1 5 6 122 3 14 Vio pig 12 11 WR 29 o 6 30 15 y pio 34 D10 15 po 30 IP5 313185 18 IS6 air RXD2 To 21s 4 ze 13 10 5 9 P23 RD31 32 5 16 52 88 D2 16 55 pa 22 D8 41715 17 155 4 5 c mio Li2 RXD2 GND 9 19 120 5 55 gc 12 12 INTO 8 7 MI D1133 5 6 34 A4 A18 17 315 po L32 D9 WR 17 jug uc L28 IP3 5 16 154 6 vir 02 107 6 25 ec Lll 16 5 SCLK D1035 5 36 18 537 A618 5 A12 27 1 6 210 15 153 XXDl 7 559 21 Li0 IXDi 1 o 2 106 7153 7 10 vi4 26 4 2 3 SDAT DI 37 5 o 38 2 A7 19 46 30 D8 719 26 12 7 514 14 181 RXD1 8 257 R20 L9 RX
24. 50 mA at 50V The maximum power dissipation allowed is 2 20 W per chip at 25 degrees C C The common substrate G is tied to ground by default For inductive loads K J3 pin 39 connects to the protection diodes in the ULN2003 chips and should be tied to highest voltage in the external load system K can be connected to a user provided voltage at J3 pin 40 ULN2003 is a sinking driver not a sourcing driver An example of typical application wiring is shown in 0 Solenoid Power Supply GND SUB ULN2003 TinyDrive Figure 3 3 Drive inductive loads with high voltage current drivers By design the sockets at locations U11 U15 only allow sinking drivers Sourcing drivers are not allowed However if TTL level I Os are needed the ULN2003s can be replaced by resistor pack ICs U11 U13 are accessed by the U5 PPI 82C55 and with resistor packs installed can provide user programmable TTL level inputs and or outputs Locations U14 and 015 are accessed via the output ports of the SC26C92s and with resistor packs installed can provide only TTL level outputs Ethernet Module The RL supports an i2Chip W3100A which is an LSI of hardware protocol stack that provides an easy low cost solution for high speed internet connectivity for digital devices by allowing simple installation of TCP IP stack in the hardware The i2Chip offers a quick and easy way to add Ethernet networking functionality to embedded controllers It can completely offl
25. 6C92 UART is located in position U4 and U10 For more information about the external UART SCC26C92 please refer to the section in this manual on the SCC26C92 Timer Control Unit The timer counter unit has three 16 bit programmable timers Timer0 Timerl and Timer2 Timer0 and Timer are connected to four external pins 0 output P10 J2 pin 12 Timer0 input Pll 2 pin 14 Timerl output P1 J2 pin 29 1 input P0 J2pin20 These two timers can be used to count or time external events or they can generate non repetitive or variable duty cycle waveforms Timer2 is not connected to any external pin It can be used as an internal timer for real time coding or time delay applications It can also prescale timer 0 and timer 1 or be used as a DMA request source The maximum rate at which each timer can operate is 10 MHz Timer inputs take up to six clock cycles to respond to clock or gate events See the sample programs timer0 c and ae_cnt0 c in the samples ae directory PWM outputs The and Timerl outputs can also be used to generate non repetitive or variable duty cycle waveforms The timer output takes up to 6 clock cycles to respond to the clock input Thus the minimum timer output cycle is 25 ns x 6 150 ns Each timer has a maximum count register that defines the maximum value the timer will reach Both TimerO and Timerl have secondary maximum count registers for variable duty cycle output Using
26. DI IXD23 5 G4 8 9 GND 2 o 1 vec 39 5 6 40 Al A6 20 35 2900 2820 47 25 11 tnTS 8 515 180 Ee ZRXD2 5 5 L e A5 21 28 RD A921 24 A10 INT6 9 12 INT1 MAX232D 7 8 ULN2003 HDRD40 HDRD40 AA A8 A9 SS 912 o 0 A4 22113 27600 1722 316 aly 18 6 101541 11 7INTO GND 9 10 HO AA223 2 Ze 1 2 GND 24 21 25 RAM44 RN768 U13 o HDRD2 105 1 5 16 15 030 104 2 2556 15 16 21 1 1 16 220 U32 3138 c 214 V17 INI oi 2569 I9 1 77 gi 16 1599 102 41 28 213 18 12 3 12 A IPl 1 9 2 oi 15 6 55g 5c 42 vi9 IN2 12 o2 13 I10 3 i2 02 14 153 VBAT RXDA TXDA I00 6 88 LLL 20 13 5 3 22 IP2 IN104 2 55 13 GND 7 55 4c V21 INI 6 13 11 GND I11 5 15 12 152 8 9 K 7 10 IP3 IN116 11 GND G K I4 4 I3 03 INA 8 2 GND 112 7 74 Oa 19 153 N ULN2003 IN128 r 04 9 GND U14 PS2506 52 l igic L246 V22 U31 PS2506 054 2 25 oc 15 23 15 1057 oi 16 U33 DDDDNDDDDV os6 3 3g 14 V24 INS 2 11 o1 i5 GND 213 1 744 16 154 LWR WR 0123C45 67D p17 117 IP240 4 4c 113 25 16 3 15 o2 14 1 5 I1N132 o1 152 GND 107 41 j65 T 27 116 IP641 2 5 28 5c 12 V26 1 6 4 15 55 1 GND 114 3 15 65 14 155 106 12 pi
27. Dual UART tch oe Step 2 Jumper J2 pins 38 amp 40 SERO debug port Regulator 3 3V Regulator We 2 2 200 nU c iL i J2 Header ER Interrupts x C l k PIOs mr Ba x ti 50 pin CF 2 socket 12V Input 2 0 100 Base T Ss Ethernet port 20 Opto a isolated PP reme un cw o wc eee eee inputs pee a oe gt UR EA TELE Kui EZCII EXIIT EI III crx rxGcnE ase ee oon z C 11870104 RE V1 1 J3 Header ee PPI HV I O cate cs Opto isolators 24 bi directional TTL level I Os Figure 1 1 Physical layout of the RL 1 3 Chapter 1 Introduction RL Power On or Reset Step 2 jumper STEP 2 set Go to Application Code CS IP CS IP in EEPROM 0x10 CS high byte 0x11 CS low byte 0x12 IP high byte 0x13 IP low byte STEP 1 ACTF menu sent out through ser0 at 19200 baud Figure 1 2 Flow chart for ACTF operation The ACTF boot loader resides in the top protected sector of the 256K W on board Flash chip 29F 400 At power on or RESET the ACTF will check the STEP 2 jumper If STEP 2 jumper is not installed the ACTF menu will be sent out from serial 0 at 19200 baud If STEP 2 jumper is installed the jump address located in the on board serial EEPROM will be read out and the CPU will jump to that address A DEBUG kernel 40 115 hex re80_115 hex when using the 80MH
28. EX file 5 Use G command to modify CS IP to point to application in flash type G80000 at menu 6 Set step 2 jumper 1 5 Chapter 1 Introduction RL 1 6 Minimum Requirements for RL System Development 1 6 1 Minimum Hardware Requirements PC or PC compatible computer with serial COMXx port that supports 115 200 baud RL controller PC V25 serial cable RS 232 DB9 connector for PC COM port and IDE 2x5 connector for controller center negative wall transformer 9V 500 mA and power jack adapter sent with EV P DV P kit 1 6 2 Minimum Software Requirements e TERN EV P Kit installation CD and a PC running Windows 95 98 NT ME 2000 XP With the EV P Kit you can program and debug the RL in Step One and Step Two but you cannot run Step Three In order to generate an application Flash file and complete a project you will need the Development Kit DV P Kit 1 6 RL Chapter 2 Installation Chapter 2 Installation 2 1 Software Installation Please refer to the Technical manual for the C C Development Kit and Evaluation Kit for TERN Embedded Microcontrollers for information on installing software The README TXT file on the TERN EV P DV P CD ROM contains important information about the installation and evaluation of TERN controllers 2 2 Hardware Installation Overview e Connect Debug serial cable For debugging STEP 1 place IDE connector on SERO with red edge of cable at pin 1 e Connect wall
29. RA and SERB 4 15 Chapter 4 Software RL The SCC26C92 is a component that is used to provide a two additional asynchronous ports It uses a 3 6864 MHz crystal different from the system clock speed for driving serial communications This means the divisors and function arguments for setting up the baud rate for SER1 and SER 2 are different than for SERO The SCC26C92 component has its own 3 6864 MHz crystal providing the clock signal This allows for the generation of industry standard baud rates Function Argument Baud Rate 28 800 4 800 9 600 19 200 38 400 57 600 115 200 Table 4 2 Baud rate values for SER1 and SER 2 Unlike the other serial ports DMA transfer is not used to fill the input buffer for SCC Instead an interrupt service routine is used to place characters into the input buffer If the processor does not respond to the interrupt because it is masked for example the interrupt service routine might never be able to complete this process Over time this means data might be lost in the SCC as bytes overflow Initialization occurs in a manner otherwise similar to SERO A COM structure is once again used to hold state information for the serial port The in bound and out bound buffers operate as before and must be provided upon initialization sl init Arguments unsigned char b unsigned char ibuf int isiz unsigned char obuf int osiz COM c Return value none This function initializes SERI with th
30. RL M 16 bit Controller with 16 bit SRAM amp Flash 100 Base T Ethernet Opto couplers RS232 485 422 and 2GB CompactFlash Interface Based on the 40MHz Am186ER or 80MHz RDC R1100 t 5c c bs uf c NES N L 5 OALE 0 Godd ads su 22 erererrerer ararafaF LUIT516 43 0303M nn o amp o RR OR aras de o o HNOIOA REUNI Technical Manual Trery 1724 Picasso Avenue Davis CA 95616 0547 USA Tel 530 758 0180 Fax 530 758 0181 Email sales tern com http www tern com COPYRIGHT R Engine RL A Engine A Core86 A Core 1386 Engine MemCard A MotionC and ACTF are trademarks of TERN Inc Am186ER is a trademark of Advanced Micro Devices Inc Paradigm C C is a trademark of Paradigm Systems Windows95 98 2000 NT ME XP are trademarks of Microsoft Corporation Version 1 1 June 3 2004 No part of this document may be copied or reproduced in any form or by any means without the prior written consent of TERN Inc 2002 TERN 1724 Picasso Avenue Davis CA 95616 0547 USA Tel 530 758 0180 Fax 530 758 0181 Email sales tern com http www tern com Important Notice TERN is developing complex high technology integration systems These systems are integrated with software and hardware that are not 100 defect free TERN products are not des
31. are overhead or interrupt latency for user application programs even at the highest baud rate DMA transfer allows efficient handling of incoming data The user only has to check the buffer status with serhitO and take out the data from the buffer with getser0 if any The input buffer is used as a circular ring buffer as shown in Figure 4 1 However the transmit operation is interrupt driven ibuf in tail in head ibuftisiz v MEE Figure 4 1 Circular ring input buffer The input buffer ibuf buffer size isiz and baud rate baud are specified by the user with 50 init with a default mode of 8 bit 1 stop bit no parity After 50 init you can set up a new mode with different numbers for data bit stop bit or parity by directly accessing the Serial Port 0 Control Register SPOCT if necessary as described in chapter 12 of the Am186ER manual for asynchronous serial ports Due to the nature of high speed baud rates and possible effects from the external environment serial input data will automatically fill in the buffer circularly without stopping regardless of overwrite If the user does not take out the data from the ring buffer with getser0 before the ring buffer is full new data will overwrite the old data without warning or control Thus it is important to provide a sufficiently large buffer if large amounts of data are transferred For example if you are receiving data at 9600 baud a 4 KB buffer will be a
32. ation The RDC R1100 does not offer internal RAM like the Am186ER so external SRAM is mandatory if using the RDC R1100 3 4 Am186ER Features Clock Due to its integrated clock generation circuitry the Am186ER microcontroller allows the use of a times four crystal frequency The design achieves 40 MHz CPU operation while using a 10 MHz crystal The R1100 offers times eight crystal frequency achieving 80MHz operation based on 1OMHz crystal The system CLKOUTA signal is routed to pin 4 default 40 MHz The CLKOUTB signal is not connected in the RL CLKOUTA remains active during reset and bus hold conditions The RL initial function ae_init disables CLKOUTA and CLKOUTB with clka_en 0 and clkb_en 0 You may use clka en 1 to enable CLKOUTA CLK JI pin 4 Asynchronous Serial Port The Am186ER and R1100 CPU has one asynchronous serial channel It support the following 3 1 Chapter 3 Hardware RL Full duplex operation 7 bit and 8 bit data transfers Odd even and no parity One or two stop bits Error detection Hardware flow control transfers to and from serial port Am186ER ONLY Transmit and receive interrupts Maximum baud rate of 1 16 of the CPU clock speed Independent baud rate generators The software drivers for the asynch serial port implement a ring buffered DMA receiving and ring buffered interrupt transmitting arrangement See the sample file tern 186 samples ae s0_echo c An external SCC2
33. ble to store data for approximately four seconds However it is always important to take out data early from the input buffer before the ring buffer rolls over You may designate a higher baud rate for transmitting data out and a slower baud rate for receiving data This will give you more time to do other things without overrunning the input buffer You can use serhitO to check the status of the input buffer and return the offset of the in head pointer from the in tail pointer A return value of 0 indicates no data is available in the buffer 4 12 RL Chapter 4 Software You can use getserO to get the serial input data byte by byte using FIFO from the buffer The in tail pointer will automatically increment after every getserO call It is not necessary to suspend external devices from sending in serial data with RTS Only a hardware reset sO_close can stop this receiving operation For transmission you can use putser0 to send out a byte or use putsersO to transmit a character string You can put data into the transmit ring buffer 50 out buf at any time using this method The transmit ring buffer address obuf and buffer length osiz are also specified at the time of initialization The transmit interrupt service will check the availability of data in the transmit buffer If there is no more data the head and tail pointers are equal it will disable the transmit interrupt Otherwise it will continue to take out the data
34. both the primary and secondary maximum count registers lets the timer alternate between two maximum values MAX COUNT A MAX COUNT B 3 2 RL Chapter 3 Hardware Power save Mode The RL is an ideal core module for low power consumption applications The power save mode of the Am186ER reduces power consumption and heat dissipation thereby extending battery life in portable systems In power save mode operation of the CPU and internal peripherals continues at a slower clock frequency When an interrupt occurs it automatically returns to its normal operating frequency The DS1337 on the RL has a VOFF signal routed to H1 pin 1 VOFF is controlled by the battery backed DS1337 The VOFF signal can be programmed by software to be in tri state or to be active low The DS1337 can be programmed in interrupt mode to drive the VOFF pin at 1 second 1 minute or 1 hour intervals With the Switching Regulator installed optional the user can use VOFF to release VOFF and shut down the on board switching regulator By default the VOFF option is disabled by tying VOFF to Ground The user can also use the VOFF line to control an external switching power supply that turns the power supply on off 3 5 Am186ER PIO lines The Am186ER has 32 pins available as user programmable I O lines Each of these pins can be used as a user programmable input or output signal if the normal shared function is not needed A PIO line can be configured to operate as an inp
35. buffe unsigned char out buf Outp buffer int out tail Output buffer TAIL ptr int out head Output buffer HEAD ptr int out size Output buffer size unsigned char out full Output buffer FLAG unsigned cha out mt Output buffer MT unsigned char tmso transmit macro service operation unsigned char rts unsigned char dtr unsigned char en485 unsigned char err unsigned char node unsigned char cr Scc CR register unsigned char slave unsigned int in segm input buffer segment unsigned int in offs input buffer offset unsigned int out segm output buffer segment Hh H Hh HH c r c Cr 6r K BRA b b b b T3 TE 4 13 Chapter 4 Software RL unsigned int out offs output buffer offset unsigned char byte delay V25 macro service byte delay COM sn init Arguments unsigned char b unsigned char ibuf int isiz unsigned char obuf int osiz COM c Return value none This function initializes either SERO with the specified parameters b is the baud rate value shown in Table 4 1 Arguments ibuf and isiz specify the input data buffer and obuf and osiz specify the location and size of the transmit ring buffer The serial ports are initialized for 8 bit 1 stop bit no parity communication There are a couple different functions used for transmission of data You can place data within
36. by the MAX691 or LTC691 offers an excellent way to monitor improper program execution If the watchdog timer J9 jumper is set the function hitwd must be called every 1 6 seconds of program execution If this is not executed because of a run time error such as an infinite loop or stalled interrupt service routine a hardware reset will occur void hitwd Arguments none Return value none Resets the supervisor timer for another 1 6 seconds void led Arguments int ledd Return value none Turns the on board LED on or off according to the value of ledd Real Time Clock The real time clock can be used to keep track of real time Backed up by a lithium coin battery the real time clock can be accessed and programmed using two interface functions There is a common data structure used to access and use both interfaces typedef struct unsigned cha unsigned cha unsigned cha unsigned cha unsigned cha unsigned cha unsigned cha unsigned cha unsigned cha unsigned cha unsigned cha unsigned cha unsigned cha TIM secl One second digit secl0 Ten second digit minl One minute digit minl10 Ten minute digit hourl One hour digit hourl0 Ten hour digit dayl One day digit dayl0 Ten day digit One month digit 0 Ten month digit yearl One year digit yearl0 Ten year digit wk Day of the week V3 T3 DX UR 23 E DX 738 int rtc rd Arguments TIM r R
37. couplers can be used for digital inputs relay contact monitoring or powerline monitoring Each opto coupler has a 3us ON time and 5 5 OFF time The status of the opto couplers is read via the input ports of the SC26C92s and CPU PIOs 14 from the two SC26C92s and 2 from PIO lines inputs to the opto couplers are routed to the J3 header The user is required to provide supply voltage to the opto couplers The RL is shipped from the factory with the supply voltage tied to 12VI via jumper on the J3 header The output lines of the opto couplers IS0 IS6 IPO IP6 P11 and PO are pulled high via 10K ohm resistor network making the opto coupler OFF by default Pulling input lines low will turn the opto coupler ON and pull output lines low See sample project c tern 186 samples rl rl ide for example program rl opto c 3 9 Chapter 3 Hardware RL High Voltage High current drivers The ULN2003 has high voltage high current Darlington transistor arrays consisting of seven silicon NPN Darlington pairs on a common monolithic substrate There are five ULN2003s on the RL in locations U11 015 providing a total of 35 channels channels feature open collector outputs for sinking 350 mA at 50V and integral protection diodes for driving inductive loads Peak inrush currents of up to 500 mA sinking are allowed These outputs may be paralleled to achieve high load capability although each driver has a maximum continuous collector current rating of 3
38. ction is similar to delayO but the passed in argument is in units of milliseconds instead of loop iterations Again this function is highly dependent upon the processor speed unsigned int crc16 Arguments unsigned char wptr unsigned int count Return value unsigned int value This function returns a simple 16 bit CRC on a byte array of count size pointed to by wptr void ae reset Arguments none Return value none This function is similar to a hardware reset and can be used if your program needs to re start the board for any reason Depending on the current hardware configuration this might either start executing code from the DEBUG ROM or from some other address 4 4 Functions in SERO OBJ The functions described in this section are prototyped in the header file 0 in the directory tern 186 include The Am186ER only provides one asynchronous serial port The RL comes standard with the SCC26C92 providing two additional asynchronous ports The serial port on the Am186ER will be called SERO and the two UARTs from the SCC26C92 will be referred to as SERI and SER2 This section will discuss functions in ser0 h only as SERO pertains to the Am186ER By default SERO is used by the DEBUG kernel re40 115 hex for application download debugging in STEP 1 and STEP 2 The following examples that will be used show functions for SERO but since it 1s used by the debugger you cannot directly debug SERO This section will describe
39. d J2 38 40 3 ACTF menu sent to hyper terminal 4 Type D enter Send tern 186 rom re L_debug hex 5 Type G04000 to run debug hex 6 Send tern 86 rom re re40_115 hex re80_115 hex with 80MHz version Starts at OxFA000 7 Type GFAO000 enter Set Step 2 jumper J2 38 J2 40 8 On board LED blinks twice then stays on Step 1 Debug Mode 1 Launch Paradigm C C 2 Open rl ide in the tern 186 samples rl directory 3 Run samples 4 Use samples to build application in C C 5 Single step set breakpoints debug code 6 Debug kernel must be running each time to download 7 At power up if LED does not blink twice then stay on repeat steps 1 3 and 7 10 of above section Step 2 Standalone Mode 1 Run standalone mode away from PC Application resides in battery backed SRAM Set CS IP to point to application 2 Power on RL without step 2 jumper set 3 See menu at hyper terminal 19 200 N 8 1 4 Type G08000 to jump to and execute code in SRAM 5 Set step 2 jumper cycle power Will execute code in SRAM at every power up 6 Test application 7 Return to Step 1 as necessary Step 3 Production 1 Generate application HEX file with Paradigm based on field tested source code 2 Power on board with step 2 jumper removed See menu at hyper terminal 3 Use D command to download _29f40r hex in the tern 186 rom re directory Will prepare flash 4 Send application H
40. e of the 32 PIO lines 0 31 mode refers to one of four modes of operation e 0 normal operation 4 7 Chapter 4 Software RL 1 input with pullup down 2 output e 3 input without pull unsigned int pio rd Arguments char port Return value byte indicating PIO status Each bit of the returned 16 bit value indicates the current I O value for the PIO pins in the selected port void pio wr Arguments char bit char dat Return value none Writes the passed in dat value either 1 0 to the selected PIO 4 3 4 Timer Units The three timers present on the RL can be used for a variety of applications All three timers run at of the processor clock rate which determines the maximum resolution that can be obtained Be aware that if you enter power save mode the timers will operate at a reduced speed as well These timers are controlled and configured through a mode register that is specified using the software interfaces The mode register is described in detail in chapter 10 of the AMD AM186ER User s Manual The timers can be used to time execution of your user defined code by reading the timer values before and after execution of any piece of code For a sample file demonstrating this application see the sample file timer c in the directory tern 86lsamples ae Two of the timers Timer0 and 1 can be used to do pulse width modulation with a variable duty cycle These timers contain two max counters where the outp
41. e specified parameters b is the baud rate value shown in Table 4 2 Arguments ibuf and isiz specify the input data buffer and obuf and osiz specify the location and size of the transmit ring buffer s2 init Arguments unsigned char b unsigned char ibuf int isiz unsigned char obuf int osiz ca COM cb Return value none This function initializes SER2 with the specified parameters b 1s the baud rate value shown in Table 4 1 Arguments ibuf and isiz specify the input data buffer and obuf and osiz specify the location and size of the transmit ring buffer NOTE The only difference between functions for SER1 and SER2 is that SER2 functions requires both COM arguments 4 16 RL Chapter 4 Software As a part of initializing the serial port the function call also sets up the interrupt service routine that handles the data transfer between the SCC26C92 and the AM186ER The SCC26C92 UART takes up external interrupt INT0 U4 and INT3 U10 on the CPU As a part of the serlr h 51 isr 53 isr for U10 UARTS has been created to automatically handle the need for an interrupt service routine Since both channels on the SCC26C92 use the same interrupt there 1s no need for an ISR for SER2 By default the SCC26C92 15 enabled for both transmit and receive This will allow for the use of an RS 232 in full duplex mode Once this is done you can transmit and receive data as needed If you do need to do limited flow control
42. ed peripheral components When dealing with processor registers be sure to use the correct function Use outport if you are dealing with a 16 bit register inport inportb Arguments unsigned int address Return value unsigned int unsigned char data This function can be used to retrieve data from components in I O space You will find that most hardware options added to TERN controllers are mapped into I O space since memory space is valuable and is reserved for uses related to the code and data Using I O mappings the address is output over the address bus and the returned 16 or 8 bit value is the return value For a further discussion of I O and memory mappings please refer to the Hardware chapter of this technical manual 4 1 Programming Overview The ACTF loader in the RL 256KW Flash will perform the system initialization and prepare for new application code download or immediately run the pre loaded code A remote debugger kernel can be loaded into the Flash located starting Oxfa000 Debugging at baud rate of 115 200 re40 115 HEX for the Am186ER and re80 115 HEX for the R1100 is available A loader file 1 debug hex and both debugger files re40 115 hex and 80 115 are included in the EV P DV P CD under the c tern 186 rom re directory A functional diagram of the ACTF embedded in the RL is shown below 4 2 RL Chapter 4 Software Power on or Reset STEP2 Jumper on J2 pin 38 P4 GND SEND
43. efer to Chapter 7 of the AMD Am186ER Microcontroller User s Manual Or the R1100 user s manual both available on the CD under the amd docs directory Some interrupt lines on the RL are reserved for system use These include INTO INT3 and INT4 TERN provides functions to enable disable all of the 6 external interrupts The user can call any of the interrupt init functions listed below for this purpose The first argument indicates whether the particular interrupt should be enabled and the second is a function pointer to an appropriate interrupt service routine that should be used to handle the interrupt The TERN libraries will set up the interrupt vectors correctly for the specified external interrupt line At the end of interrupt handlers the appropriate in service bit for the IR signal currently being handled must be cleared This can be done using the Nonspecific EOI command At initialization time interrupt priority was placed in Fully Nested mode This means the current highest priority interrupt will be handled first and a higher priority interrupt will interrupt any current interrupt handlers So if the user chooses to clear the in service bit for the interrupt currently being handled the interrupt service routine just needs to issue the nonspecific EOI command to clear the current highest priority IR To send the nonspecific EOI command you need to write the EOI register word with 0x8000 outport 0xff22 0 8000 4 6 RL Chapter
44. eturn value int error code This function places the current value of the real time clock within the argument r structure The structure should be allocated by the user This function returns 0 on success and returns 1 in case of error such as the clock failing to respond int rtc rds Arguments char realTime Return value int error code Chapter 4 Software RL This function is slightly different from the rtc rd function It places the current value of the real time clock into a character string instead of TIM structure making it a more convenient function than rtc rd This function places the current value of the real time clock in the char realTime The string has a format of week 10 year month10 month day10 day hour10 hourl min10 minl second10 second The rtc rds function also places a null terminating character at the end of the time string It is important to note that you must be sure to make the destination character string long enough to hold the real time clock value plus the null character A destination character string that is too short will result in the data immediately following the character string in memory to be overwritten causing unknown results For example 3040503 142500 0 represents Wednesday May 3 2004 at 02 25 00 pm There are only two positions for the year so the user must decide how to determine the hundreds and thousands digit of the year Here we just assume 04 correlates t
45. from the out buffer and transmit After you call putserO and transmit functions you are free to do other tasks with no additional software overhead on the transmitting operation It will automatically send out all the data you specify After all data has been sent it will clear the busy flag and be ready for the next transmission The sample program ser1_0 c demonstrates how a protocol translator works It would receive an input HEX file from SERI and translate every character to The translated HEX file is then transmitted out of SERO This sample program can be found in tern 186 samples ae Software Interface Before using the serial ports they must be initialized There is a data structure containing important serial port state information that 1s passed as argument to the TERN library interface functions The COM structure should normally be manipulated only by TERN libraries It is provided to make debugging of the serial communication ports more practical Since it allows you to monitor the current value of the buffer and associated pointer values you can watch the transmission process typedef struct unsigned char ready E when ready unsigned char baud unsigned char mode unsigned char iflag interrupt s unsigned char in buf Input buffe int in tail Input buffe int head Input buffe int in size Input buffe int in cront Input lt CR gt unsigned char in mt Input buffe unsigned char in full input
46. igned intended authorized or warranted to be suitable for use in life support applications devices or systems or in other critical applications TERN and the Buyer agree that TERN will not be liable for incidental or consequential damages arising from the use of TERN products It is the Buyer s responsibility to protect life and property against incidental failure TERN reserves the right to make changes and improvements to its products without providing notice RL Chapter 1 Introduction Chapter 1 Introduction 1 1 Technical Manual Organization This technical manual will require special organization to accommodate the possibility of configuring the RL with two different CPUs The CPUs are very similar yet they do have a few differences For purposes of organization it will be assumed that throughout this technical manual all information given is accurate for both CPUs unless otherwise stated In general it will be written referring to the Am186ER but will implicitly apply to the R1100 When information may deviate between CPUS it will be explicitly shown 1 2 Functional Description The is a controller designed for industrial machine control applications This industrial embedded controller integrates 20 isolated opto coupler inputs 35 solenoid drivers 100 Base T Ethernet connection 5 RS232 485 422 serial ports and CompactFlash mass data storage support on a single PCB It is ideal for industrial process control high
47. nitialize LCS Lower Chip Select for use with the SRAM It is configured so that Address space starts 0x00000 with a maximum of 512K RAM Three wait state operation Reducing this value can improve performance Disables PSRAM and disables need for external ready outport Oxffa2 Ox7fbf LMCS base Mem address 0 0000 e Initialize MMCS and MPCS so that 0 and PCS0 PCS6 except for PCS4 are configured so MCS0 is mapped also to a 256K window at 0x80000 If used with MemCard this chip select line is used for the I O window Sets up PCS5 6 lines as chip select lines with three wait state operation outport Oxffa8 0xa0bf 58 3 wait states outport Oxffa6 Ox81ff CSOMSKH Initialize PACS so that PCS0 PCS3 are configured so that Sets up PCS0 3 lines as chip select lines with fifteen wait state operation The chip select lines starts at I O address 0x0000 with each successive chip select line addressed 0x100 higher in I O space 4 5 Chapter 4 Software RL outport Oxffa4 0 007 CSOMSKL 512K enable CSO for RAM e Configure the two ports for default operation pins are set up as default input except for P29 used for driving the LED and peripheral function pins for SERO as well as chip selects for the PPI outport 0xff78 0xe73c TxDO RxDO 16 0 P17 PCS1 outport Oxf 76 0x0000 outport 0xff72 0xec7b PDIRO P12 Output
48. o the year 2004 The length of char realTime must be at least 14 characters 13 plus one null terminating character This function returns 0 on success and returns 1 in case of error such as the clock failing to respond Void rtc init Arguments char t Return value none This function is used to initialize and set a value into the real time clock The argument t should be a null terminated byte array that contains the new time value to be used The byte array should correspond to weekday year10 year1 month10 month1 day10 dayl hour10 hourl minute10 minutel second10 secondl 0 If for example the time to be initialized into the real time clock is June 5 1998 Friday 13 55 30 the byte array would be initialized to unsigned char t 14 Delay In many applications it becomes useful to pause before executing any further code There are functions provided to make this process easy For applications that require precision timing you should use hardware timers provided on board for this purpose void delay Arguments unsigned int t Return value none This function is just a simple software loop The actual time that it waits depends on processor speed as well as interrupt latency The code is functionally identical to While t t Passing in a t value of 600 causes a delay of approximately 1 ms void delay ms Arguments unsigned int Return value none 4 10 RL Chapter 4 Software This fun
49. oad internet connectivity and processing standard protocols from the host system reducing development time and cost It contains TCP IP protocol stacks such as TCP UDP IP ARP and ICMP protocols as well as Ethernet protocols such as Data Link Control and MAC protocol The full datasheet is provided on the TERN tern_docs parts w3100a datasheet 3 1 pdf Also find sample programs for accessing the module in the 3 10 RL Chapter 3 Hardware RL sample project c tern 186 sampels rl rl ide Sample programs include i2chip c and i2 dma c The module is accessed by P14 MCSO midrange chip select The chip select can be mapped into memory by initializing MMCS and MPCS registers See chapter 5 of the Am186ER technical manual amd docs am186er 3 8 Headers and Connectors Expansion Headers and J2 There are two 20x2 0 1 spacing headers for RL expansion Most signals are directly routed to the Am186ER processor These signals are 3 3V signals but are 5V tolerant Any voltages above 5V will certainly damage the board J2 Signal JI Signal GND 40 39 1 2 GND P4 38 37 P14 3 4 CLK 36 35 P6 5 6 GND 34 33 7 8 32 31 19 9 10 DI P5 30 29 Pl BHE 11 12 D2 TxDA 28 27 P2 D15 13 14 D3 RxDA 26 25 A19 RST 15 16 D4 24 23 P15 RST 17 18 D5 125 22 21 124 16 19 20 D6 20 19 D14 21 22 D7 P25 18 17 P24 D13 23 24 GND 127 16 15 126 25 26 12 11 14 13 18 D12 27 28 7
50. r or up to 30V DC power input with switching regulator without generating excessive heat 1 3 Features e Dimensions 4 9 x 3 5 x 0 3 inches e Temperature 40 C to 80 C 40 MHz 16 bit CPU Am186ER Intel 80x86 compatible OR 80 MHz 16 bit R1100 e 32KB internal RAM Am186ER ONLY e Easy to program in C C e Power consumption 200 mA at 5V Standby mode 50u A e Power input 9V to 12V unregulated DC with default linear regulator 9V to 30V unregulated DC with optional switching regulator e Up to 256 KW 16 bit SRAM 256 KW 16 bit Flash e Up to 2GB CompactFlash with FAT 16 File system support e Flexible hardware configurable input logic e Hardware TCP IP stack for 100 Base T Ethernet e Suitable for protected industrial control applications 35 Solenoid Drivers 20 Opto coupler inputs e 16 bit external data bus expansion port e 5 serial ports 1 from Am186ER four from 2 SCC2692 support full duplex 7 8 or 9 bit asynchronous communication only SCC2692 supports 9 bit 2 high speed PWM outputs e 6 external interrupt inputs 3 16 bit timer counters e 32 multifunctional I O lines from Am186ER e 24 bi directional I O lines from 82C55 PPI e 512 byte serial EEPROM e Supervisor chip 691 for reset and watchdog Real time clock 051337 lithium coin battery 1 2 RL Chapter 1 Introduction 1 4 Physical Description The physical layout of the RL 1s shown in Figure 1 1 SCC2692 re
51. rary re_lib can be used to initialize PIO pins void pio_init char bit char mode Where bit 0 31 and mode 0 3 see the table above Example pio_init 10 2 will set P10 as output pio init 1 0 will set P1 as Timer output void pio_wr char bit char dat pio_wr 10 1 set P10 pin high if P10 is in output mode pio_wr 10 0 set P12 pin low if P10 is in output mode 3 4 RL Chapter 3 Hardware unsigned int pio rd char port pio rd 0 return 16 bit status of PO P15 if corresponding pin is in input mode pio rd 1 return 16 bit status of P16 P31 if corresponding pin is in input mode Some of the I O lines are used by the RL system for on board components Table 3 2 We suggest that you not use these lines unless you are sure that you are not interfering with the operation of such components 1 if the component is not installed Clock input for U9 PAL Chip select for U4 SC26C92 Step Two jumper Never use for application Never use for application Chip select for Ethernet module Chip Select for U18 decoder Synchronous serial interface for RTC EEPROM RxD0 Reserved for EEPROM LED RTC and Watchdog timer U4 SC26C92 UART interrupt U10 SC26C92 UART interrupt Interrupt for Ethernet module Table 3 2 I O lines used for on board components 3 6 I O Mapped Devices VO Space External I O devices can use I O mapping for access You can access such I O devices with inportb port or outportb por
52. re 4 2 RE LIB RE LIB 15 a C library for basic operations It includes the following modules AE OBJ SERO OBJ and AEEE OBJ You need to link RE LIB in your applications and include the corresponding header files in your source code The following is a list of the header files PPI timer counter RTC Watchdog Internal serial port 0 External UART SCC26C92 on board EEPROM 4 3 Functions in AE OBJ 4 3 1 RL Initialization ae init This function should be called at the beginning of every program running on RL core controllers It provides default initialization and configuration of the various I O pins interrupt vectors sets up expanded DOS I O and provides other processor specific updates needed at the beginning of every program There are certain default pin modes and interrupt settings you might wish to change With that in mind the basic effects of ae init are described below For details regarding register use you will want to refer to the AMD Am186ER Microcontroller User s manual e Initialize the upper chip select to support the default ROM The CPU registers are configured such that Address space for the ROM is from 0x80000 Oxfffff to map MemCard I O window 512K ROM Block size operation Three wait state operation For details see the UMCS Upper Memory Chip Select Register reference in the processor User s manual outport Oxffa0 0x80bf UMCS 512K ROM 0x80000 0xfffff e I
53. rong After the RL is reset the WDO remains low until a transition occurs at the WDI pin of the MAX691 When controllers are shipped from the factory the J9 jumper is off which disables the watchdog timer The Am186ER has an internal watchdog timer This is disabled by default with ae init Battery Backup Protection The backup battery protection protects data stored in the SRAM and RTC The battery switch over circuit compares VCC to VBAT 3 V lithium battery positive pin and connects whichever is higher to the VRAM power for SRAM and RTC Thus the SRAM and the real time clock DS1337 are backed up In normal use the lithium battery should last about 3 5 years without external power being supplied When the external power is on the battery switch over circuit will select the VCC to connect to the VRAM EEPROM A serial EEPROM of 512 bytes 24C04 is be installed in U7 The RL uses the P22 and P29 to interface with the EEPROM The EEPROM can be used to store important data such as a node address calibration coefficients and configuration codes It typically has 1 000 000 erase write cycles The data retention is more than 40 years EEPROM can be read and written by simply calling the functions ee rd and ee_wr A range of lower addresses in the EEPROM is reserved for TERN use 0x00 0 1 The addresses 0x20 to Ox1FF are for user application Opto couplers The RL supports 20 opto couplers in 5 PS2501 4 packages These opto
54. s 26 115 1 5 42 OPA 6 25 Ll1L V27 I7 5 15 os 126 IN144 15 Q5 13 GND 105 43 505 PPIS L25 114 1 4 43 OP6 7 55 4c 40 V28 6 13 11 GND I15 5 15 05 12 156 104 44 504 05 24 vec 44 8 x 9 K Gap IN15 6 i3 Lll GND 1 PPI8255 22 i INS 8 o4 2 GND 116 7 74 103 32 555 pip 22 112 A1 2 2 N ULN2003 IN16 8 14 04 9 GND 102 3 502 pii 21 111 183 3 3 U15 PS2506 101 4501 pio 20110 A2 4 4 57 l igic 16 29 52506 100 5 poo 12_123_ IP1 5 R T 5 T os5 2 2 15 v30 RN2 u34 RD 6 G P PPPPP 18 122 A3 6 I X XOOOO 18 D1 A3 6 I X XOOOO 18 D1 053 14 v31 T1 1 20 IVE Tp oe A 16 INT1 RD CNAA2N22 222 P22 A2 APWRDNDPPPpP Di A2 APWRDNDPPPP Di osi a 13 v32 12 2 2 11 01 5 6ND SD107C65401 30RDBCB1357 30RDBCB1357 4B 4C 219 Il ol C54 OPT 5 sc 12 vee 131 E Aan 18 m E Toh Dow 14 1NT2 R12 985 23 Lii V 217 Ill4 IT 12 o2 13 GND Ja o o 1213 a o o el 12 3 d s d7 AA 2 3as os 4c L10 v35 155 5 516 16 112 T3 5 734 934 42 INT5 PPI 121 A4 OP 7 10K A4 087 5 0 10 8 6 lt 75 15 113 IT3 6 93 11 GND GND 120 C3 IPO 5 TXD R13 150 055 2 I7 7 314 14 114 7 Tad Da 10 INT6 A2 124 7WR Ria 220 7WR 053 012003 183 8 473 13 115 8 4
55. s function assumes that serhitz has been called and that there 15 a character present in the buffer 4 14 RL Chapter 4 Software getsersn Arguments COM c int len char str Return value int value This function fills the character buffer str with at most len bytes from the input buffer It also stops retrieving data from the buffer if a carriage return ASCH 0x0d is retrieved This function makes repeated calls to getser and will block until len bytes are retrieved The return value indicates the number of bytes that were placed into the buffer Be careful when you are using this function The returned character string 1s actually a byte array terminated by a null character This means that there might actually be multiple null characters in the byte array and the returned value is the only definite indicator of the number of bytes read Normally we suggest that the getsers and putsers functions only be used with ASCII character strings If you are working with byte arrays the single byte versions of these functions are probably more appropriate Miscellaneous Serial Communication Functions One thing to be aware of in both transmission and receiving of data through the serial port is that TERN drivers only use the basic serial port communication lines for transmitting and receiving data Hardware flow control in the form of CTS Clear To Send and RTS Ready To Send is not implemented There are however functions available
56. s as input output you will probably need to initialize these pins in one of the four available modes Before selecting pins for this purpose make sure that the peripheral mode operation of the pin is not needed for a different use within the same application You should also confirm the PIO usage that is described above within ae_init During initialization several lines are reserved for TERN usage and you should understand that these are not available for your application There are several PIO lines that are used for other on board purposes These are all described in some detail in the Hardware chapter of this technical manual For a detailed discussion toward the I O ports please refer to Chapter 14 of the AMD Am186ER User s Manual Please see the sample program ae_pio c in tern 186 samples ae You will also find that these functions are used throughout TERN sample files as most applications do find it necessary to re configure the PIO lines The function pio_wr and pio_rd can be quite slow when accessing the PIO pins Depending on the pin being used it might require from 5 10 us The maximum efficiency you can get from the PIO pins occur if you instead modify the PIO registers directly with an outport instruction Performance in this case will be around 1 2 us to toggle any pin The data register 15 Oxff74 for PIO port 0 and Oxff7a for PIO port 1 void pio_init Arguments char bit char mode Return value none bit refers to any on
57. seconds minutes hours day date month and year information The data at the end of the month is automatically adjusted for months with fewer than 31 days including corrections for leap year The clock operates in either 24 hour or 12 hour format with AM PM indicator The RTC is accessed via software drivers rtc_init and rtc_rds Refer to sample code in the tern 186 samples re directory for re rtc c See tern 186 samples rl rl ide It is also possible to configure the real time clock to raise an output line attached to an external interrupt at 1 64 second 1 second 1 minute or 1 hour intervals This can be used in a time driven application or the VOFF signal can be used to turn on off the controller using an external switching power supply UART SC26C92 Two dual UARTs SC26C92 Phillips U4 and U10 are installed on the RL providing 4 UARTs Each SC26C92 includes two independent full duplex asynchronous receiver transmitters a quadruple buffered receiver data register an interrupt control mechanism programmable data format selectable baud rate for the receiver and transmitter a multi functional and programmable 16 bit counter timer an on chip crystal oscillator and a multi purpose input output including RTS and CTS mechanism A 3 6864 MHz external crystal is installed as the default crystal for the dual UARTS By default all UARTs are configured with RS 232 drivers One port can be optionally configured to RS 485 or RS 422
58. speed LAN or remote communication machine control applications The RL utilizes a high performance programmable 186 generation CPU 80MHz R1100 or 40 MHz AMISG6ER with a 16 bit external data bus supporting fast code execution It has 256KW 16 bit Flash and 256KW 16 bit battery backed SRAM Three CPU internal timer counters can be used to count or time external events or to generate non repetitive or variable duty cycle waveforms as PWM outputs A real time clock 051337 Dallas provides clock calendar with two time of day alarms A 50 pin CompactFlash receptacle allows access to mass storage CompactFlash cards up to 2 GB TERN C C programmable software packages with FAT16 file system libraries are available An i2Chip Fast Ethernet Module can be installed to provide 100M Base T network connectivity allowing the RL to work with high bandwidth modern Ethernet networks This Module implements TCP IP UDP ICMP and ARP with a combination of hardware software It has 16KB internal transmit and receiving buffer which is mapped into host processor s direct memory The host can access the buffer via high speed DMA transfers The hardware Ethernet module releases internet connectivity and protocol processing from the host processor It supports 4 independent stack connections simultaneously at a 4Mbps protocol processing speed An RJ45 8 pin connector is on board for connecting to 10 100 Base T Ethernet network Five RS232 serial ports are
59. t dat These functions will transfer one byte or word of data to the specified I O address The external I O space is 64K ranging from 0x0000 to Oxffff The default I O access time is 15 wait states You may use the function void io wait char wait to define the I O wait states from 0 to 15 The system clock is 100 ns for both CPUs while the CPU clock is 25ns for the Am186ER and 12 5ns for the R1100 Details regarding this can be found in the Software chapter and in the Am186ER User s Manual Slower components such as most LCD interfaces might find the maximum programmable wait state of 15 cycles still insufficient Due to the high bus speed of the system some components need to be attached to I O pins directly For details regarding the chip select unit please see Chapter 5 of the Am186ER User s Manual The table below shows more information about I O mapping 0x0000 0x00ff J1 pin 19 P16 USER 0x0100 0x01 ff 18 4 018 decoder 0x0200 0x02ff J2 pin 13 P18 USER 0x0300 0x03ff J2 pin 31 P19 USER 3 5 Chapter 3 Hardware RL 0x0400 0x04ff Reserved 0x0500 0x05 ff J2 pin 15 P3 SC26C92 0x0600 0x06ff 09 1 PAL PCSO may be used for other TERN peripheral boards such as UR8 P100 etc To illustrate how to interface the RL with external I O boards a simple decoding circuit for interfacing to an 82C55 parallel I O chip is shown in Figure 3 1 74HC138 82 55 RST T P00 P07 A6 SEL20 T A7 SEL40 SEL60 SEL20
60. transformer Connect 9V wall transformer to power and plug into power jack adapter which installs into green screw terminal Hardware installation for the RL consists primarily of connecting it to your PC and to power As mentioned above it requires installing the debug cable onto SERO and plugging the output of the wall transformer into the power jack adapter The following diagram shows the RL with power applied and connected to the debug cable 2 1 Chapter 2 Installation RL 2 2 1 Connecting the RL to power and debug cable The red edge of the serial cable should align with pin 1 of the 5x2 pin header of SERO Pin 1 of any header can be located as the pin closest to the name of the header In other words the white characters printed on the PCB that identify each header indicate pin 1 of that header To DB9 connector Connect to COMI of PC Output of wall transformer SERO Use power jack adapter Red edge of cable aligned supplied with EV P kit with pin 1 of header H c p c c With the connections shown above RL is ready to communicate with the PC either through a hyper terminal or with Paradigm 2 2 RL Chapter 3 Hardware Chapter 3 Hardware 3 1 Am186ER AND RDC R1100 The RL is compatible with two different CPUs Both offer and support the same on board peripherals as well as the on the CPU itself aside from a few differences
61. ut is high until the counter counts up to maxcount before switching and counting up to maxcount B 012 AD7852 uses Timer output P1 J2 29 as ADC clock up to SMHz It is also possible to use the output of Timer2 to pre scale one of the other timers since 16 bit resolution at the maximum clock rate specified gives you only 150 Hz Only by using Timer2 can you slow this down even further The sample files timer02 c and timer12 c located in tern 86lsampleslae demonstrate this The specific behavior that you might want to implement is described in detail in chapter 10 of the AMD AMIS6ER User s Manual void t0 init void t1 init Arguments int tm int ta int tb void interrupt far t isr Return values none Both of these timers have two maximum counters MAXCOUNTA B available These can all be specified using ta and tb The argument tm is the value that you wish placed into the TOCON TICON mode registers for configuring the two timers The interrupt service routine t isr specified here is called whenever the full count is reached with other behavior possible depending on the value specified for the control register void t2 init Arguments int tm int ta void interrupt far t isr Return values none Timer2 behaves like the other timers except it only has one max counter available 4 8 RL Chapter 4 Software 4 3 5 Other library functions On board supervisor MAX691 or LTC691 The watchdog timer offered
62. ut or output with or without a weak pull up or pull down or as an open drain output pin s behavior either pull up or pull down is pre determined and shown in the table below After power on reset PIO pins default to various configurations The initialization routine provided by TERN libraries reconfigures some of these pins as needed for specific on board usage as well These configurations as well as the processor internal peripheral usage configurations are listed below in Table 3 1 Function Power On Reset RL Initial status after init function call Timerl in Input with pull up J2 pin 20 Input with pull up Timer out Input with pull down J2 pin 29 Input with pull up PCS6 A2 Input with pull up J2 pin 27 PAL PCSS A1 Input with pull up U4 pin 39 SCC2692 select DT R Normal J2 pin 38 Input with pull up Step 2 DEN DS Normal J2 pin 30 Input SRDY Normal J2 pin 35 Input A17 Normal N A A17 A18 Normal N A A18 A19 Normal J2 pin 25 A19 Timer0 out Input with pull down J2 pin 12 Input with pull down TimerO in Input with pull up J2 pin 14 Input with pull up DRQO Input with pull up J1 pin 26 Output DRQI Input with pull up J2 pin 11 Input with pull up MCSO Input with pull up JP1 pin 2 Input with pull up MCSI Input with pull up J2 pin 23 Input with pull up PCSO Input with pull up J1 pin 19 PCSO PCS1 Input with pull up N A PCS1 3 3 Chapter 3 Hardware RL PIO Function Power On Reset RL Initial status
63. ws fileio h filegio h filesy16 lib mm16 lib Idef lib Libraries are found in the tern 186 lib directory and header files in the tern 186 include directory The sample project c tern 186 samples rl rl ide contains an example of how to access the CF interface via FAT file system Download fs cmdsl1 axe and full speed run Link SER1 to a PC running a hyper terminal configured to 19 200 N 8 1 and type m for menu A properly formatted must be formatted in FAT FAT32 NOT allowed CF card must be installed before running the sample 4 18 Chapter 4 Software 4 19 RL Appendix A RL Layout Appendix A RL Layout The RL measures 4 92 x 3 52 inches All dimensions are in inches All measurements are from the center of pins or mounting holes 1 492 3 35 2 392 335 3 292 3 35 0 592 3 35 4 092 3 35 4 92 3 52 wRecoo neee ag I a 4 75 3 383 0 20 3 383 See E E mimi ne B8 ee 8 E 4 692 3 142 nil 0 10 1 933 H 9e La miii _ E C oo m oo Ru 1 wy 999992929 un TT z e mild patur ams i 6909 4
64. z version can be downloaded to a starting address of OxFA000 of the 256KW on board flash chip There is no ROM socket on the RL The user s application program must reside in SRAM for debugging in STEPI reside in battery backed SRAM for the standalone field test in STEP2 and finally be programmed into Flash for a complete product For production the user must produce an ACTF downloadable HEX file for the application based on the DV P Kit The STEP2 jumper J2 pins 38 40 must be installed for every production version board Step 1 settings In order to communicate with the RL with Paradigm C the RL must meet these requirements See next section Prepare for Debug Mode By default steps 1 3 are done at the factory 1 RE40 115 re80_115 hex with 80MHz version must be pre loaded into Flash starting address Oxfa000 2 The on board EE must have the jump address for the RE40 115 HEX with starting address of Oxfa000 3 The STEP2 jumper must be installed on J2 pins 38 40 4 The SRAM installed must be large enough to hold your program For a 64 KW SRAM the physical address 15 0x00000 0x01 ffff For a 256 KW SRAM the physical address is 0x00000 0x07ffff For further information on programming the RL refer to the Software chapter 1 4 RL Chapter 1 Introduction 1 5 RL Programming Overview Preparing for Debug Mode 1 Connect RL to PC with RS 232 link at 19 200 N 8 1 2 Power on RL with step 2 jumper remove

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