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UG936 - Xilinx

1. Artix 7 AC701 Evaluation Platform xilinx com artix7 ac701 1 0 xc7a200tfbc Kintex 7 KC705 Evaluation Platform xilinx com kc705 S gt _xc7k325tffgit Virtex 7 VC707 Evaluation Platform xilinx com vc707 1 1 xc7vx485tffi Virtex 7 VC709 Evaluation Platform xilinx com vc709 1 0 xc7vx690tffi ZYNQ 7 ZC702 Evaluation Board xilinx com zc702 1 0 xc7z020clg _ a qia 7C706 Evaluation Raard xilinx cam 70706 1 1 xc77N45ffas lt Hy Figure 129 Choosing the Kintex 7 KC705 Evaluation Platform board Programming and Debugging www xilinx com 109 UG936 v2015 1 May 18 2015 Send Feedback XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 9 In the New Project Summary page click Finish f New Project New Project Summary Q A new RTL project named jtag_2_axi_tutorial will be created A No source files or directories will be added Use Add Sources to add them later No Configurable IP files will be added Use Add Sources to add them later No constraints files will be added Use Add Sources to add them later Q The default part and product family for the new project Default Board Kintex 7 KC705 Evaluation Platform Default Part xc7k325tffg900 2 Product Kintex 7 Family Kintex 7 Package ffg900 Speed Grade 2 VIVADO To create the project click Finish Figure 130 New Project Summary Programming and Debugging www xilinx com 110 UG936
2. ID code 33651093 IR lenath 6 k 4 il ol General Properties Figure 156 ILA Core Instances in the Hardware Window 11 You can communicate with the JTAG to AXI Master core with Tcl commands only You can issue AXI read and write transactions using the run_hw_axi command However before issuing these transactions it is important to reset the JTAG to AXI Master core Because the aresetn input port of the jtag _ axi 0 core instance is not connected to anything you need to use the following Tcl commands to reset the core Programming and Debugging www xilinx com 131 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions reset hw axi get hw axis hw axi 1 INFO Labtools 27 2154 Reading 11443712 bytes from file C jtag_2_axi_tutorial jtag_2_axi_tutorial jtag_axi_O example jtag_axi_O_examp a INFO Labtools 27 32 Done pin status HIGH program_hwoidevices Time s cpu 00 00 05 slapsed 00 00 11 Memory MB peak 2014 715 gain 40 832 refresh_hw_device lindex get_hw_devices 6 INFO Labtools 27 2024 Device xc7k325t JTAG device index 0 has 1 JTAG_AXI cores INFO Labtools 27 1432 Device xcTk325t JTAG device index 0 is programmed with a design that has 1 ILA core s in it reset hw axi get_hw axis hw axi 1 Figure 157 Reset JTAG to AXI core 12 The next step is to create a 4 word AXI burst tran
3. e debounce vhd e fsm vhd e sinegen vhd e sinegen demo vhd e sine high sine high xci e sine low sine low xci e sine mid sine mid xci e sinegen demo kc 05 xdc Lab 2 This lab goes over the details of marking nets for debug in the source HDL HDL instantiation method as well as instantiating an ILA core in the HDL Following are the required files e debounce vhd e fsm vhd e sinegen vhd e sinegen demo inst vhd e ila 0 ila 0 xci sine highysine high xci e sine low sine low xci e sine mid sine mid xci e sinegen demo ke 05 xdc Lab 3 You can test your design even if the hardware is not physically accessible using a VIO core This lab walks you through the steps of instantiating and customizing a VIO core that you will hook to the I Os of the design Following are the required files e debounce vhd e fsm vhd e sinegen vhd e sin egen demo inst vio vhd e sine high sine high xci e sine low sine low xci gine mid sine mid xe1 Programming and Debugging www xilinx com 9 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Debugging in Vivado Tutorial e ila 0 ila 0 xci e sinegen demo kc 05 xdc Lab 4 Nets can also be marked for debug in a third party synthesis tool using directives for the synthesis tool This lab walks you through the steps of marking nets for debug in the Synplify tool and then using Vivado to perform the rest of the debug Following are the required files e dds
4. Project Summary x IP Catalog x Search Q JTAG to AXI 1 match l Name AXI4 Status License VLNV Debug amp Verification bH S Debug cs LF JTAG to AXI Master AXIS k i a Hi Production Included xilinx com _ all of Details Figure 132 JTAG to AXI Master IP Core Programming and Debugging www xilinx com 112 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 12 Double click JTAG to AXI Master core The Customization dialog of the core appears Accept the default core settings by clicking OK F Customize IP JTAG to AXI Master 1 0 Documentation IP Location 3 Switch to Defaults __ Show disabled ports Pnet an AXI Frotocol AXI4 AXI Data Width 32 AXI ID Width 1 Write Transaction Queue Length 1 Read Transaction Queue Length 1 Figure 133 JTAG to AXI Master Customization Dialog Programming and Debugging www xilinx com 113 UG936 v2015 1 May 18 2015 Send Feedback XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 13 In the Generate Output Products dialog click Generate d Generate Output Products Lx The following output products will be P generated ir Preview Q E E jtag_axi_0 xci 00C per IP O Instantiation Template Ol Synthesized Checkpoint dcp E Behavioral Simulation Synthesis Options Global Out of c
5. UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links 8 When the Generate Output Products dialog box opens click Generate g Generate Output Products x The following output products will be P generated ea Preview OQ EHE ibert_7series_gtx_0 xci Global fl Instantiation Template E0 RTL Sources A Change Log Synthesis Options Global Out of context per IP Run Settings Number of jobs 8 amp 8 Figure 99 Generate Output Products 9 In the Project Manager window right click the IP and select Open IP Example Design Programming and Debugging www xilinx com 86 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links Project Manager ibert_tutorial E Project Su il Search l ber Name a Le Constraints Source Node Properties Ctri E EH Simulation Sources 1 a Re customize P l H 6 sim_1 1 Generate Output Products Reset Output Products Hierarchy IP Sources Libr Template Copy File Into Pr oject Copy All Files Into Project Alt I Source File Properties Remove File from Project Delete an Blr Enable File Alt Equals if ibert_7series_gtx_O xci Disable File Alt Minus IF name IBERT 7 Series Hierarchy Update i Version 3 0 Rev 8 Refresh Hierarchy
6. Under New Project Summary ensure that all the settings are correct Click Finish Once the project has been created in Vivado Flow Navigator under the Project Manager folder click Project Settings In the pop up dialog box in the left panel click Synthesis From the pull down menu on the right panel set flatten_hierarchy to none Click OK In Vivado IDE Flow Navigator under Synthesis Folder click Run Synthesis When synthesis completes the Synthesis Completed dialog box appears Select Open Synthesized Design and click OK Now you need to write the netlist file for all the components used in the sinegen block The four netlist files used in this tutorial are already provided as a part of the source files However you can overwrite them by using your own netlist files To do this use the following Tcl command in the Tcl console of Vivado IDE write edif force Vivado Debug src lab4 sinegen edn Ensure that the path specified to the src folder is correct At this point you should see four edn files in the Vivado_Debug src folder as shown below Oo dds compiler vo O viv edn oO dds compiler vo O0 viv parameterizedlsedn o dds compiler vo 0 viv parameteri z6d gt edn Oo sinegen edn 14 Click File gt Exit in Vivado IDE When the OK to exit dialog box pops up click OK Programming and Debugging www xilinx com 45 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 4 Using Synplify P
7. 2 0 axi a awsize axl awvalid O s0 axa Did axi bready 120 Jax Dresp axi bvalid ol 20 ax1 rdata O SO haa tid axi Plast axi rready 120 axi Presp axi rvalidy ol 20 axi wdata axi wlast axl wready 3 O axi_wstrb axi wvalid jtag axi o v file 20 In the Flow Navigator on the left side of the Vivado window click Run Synthesis 21 Open the synthesized design by selecting Open Synthesized Design and clicking OK Programming and Debugging UG936 v2015 1 May 18 2015 Synthesis Completed hx i Synthesis successfully completed Next Run Implementation Open Synthesized Design View Reports Don t show this dialog again ox ean www xilinx com Figure 138 Open Synthesized Design Send Feedback 117 XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 22 Once the synthesized design opens do the following a Select the Debug layout in the main toolbar of the Vivado IDE File Edit Flow Tools Window Layout View Help iS eE eBRhk x gt DP HAS OG RK ZG S debug Rer Flow Navigator Synthesized Design xc7k325titg900 ones ee _ 25 Clock Planning atic x exampl d Project Manager La a 3 5 Floorplanning 2 V0 Ports l example_jtag_axi_0 Project Settings HHD Nets 270 SF Add Sources HHS Leaf Cells 11 Language Templates HHE axi_bram_ctrl_inst axi_bram_ctrl TF PP Catal F dbg
8. Description The IBERT 7 eae for evaluating q s transceivers checkers that a l d ports and the d Set Used I CTY trancranrs a p 4 il Edit Constraints Sets General Properties Edit Simulation Sets eames Add Sources Design Runs Report IP Status OQ Name COTS OI LOTS TOUTES Figure 100 Open Example IP Design Menu Item Programming and Debugging www xilinx com 87 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links 10 In the Open IP Example Design dialog box ensure that the Overwrite existing example project is selected and click OK g Open IP Example Design X Specify a location where the example project directory ibert_7series_gtx_0_example will be placed Location Put example project directory here _tutorial_example ibert_7series_gqtx_0_example IV Overwrite existing example project ok J canei Figure 101 Open IP Example Design Dialog Box Step 3 Synthesize Implement and Generate Bitstream for the IBERT design 1 Click Generate Bitstream in the Flow Navigator When the No Implementation Results Available dialog box appears Click Yes No Implementation Results Available gx _ There are no implementation results available OK to launch synthesis and implementation Generate Bitstream will automatically start when synthesis and implementation completes Don t show this dialog
9. Figure 110 Hardware Window Showing the XC7K325T Device on the KC705 Board 94 Programming and Debugging www xilinx com UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links 6 Select XC7K325T_0 0 in the Hardware window right click and select Program Device XADC System Monitor F amp Add Configuration Memory Device Hardware Device Properties Export to Spreadsheet Figure 111 Program Target Device 7 The Program Device dialog box opens Make sure that the correct bitfile is selected and click OK Program Device Select a bitstream programming file and download it to your hardware device You can optionally select a debug probes file that corresponds to the debug cores contained in the bitstream programming file Bitstream file xample ibert_7series_gt_0_example runs impl_1 example_ibert_ series_gqt lt _0 bit Debug probesfle o O Enable end of startup check Figure 112 Program Device Dialog Box Programming and Debugging www xilinx com 95 UG936 v2015 1 May 18 2015 Send Feedback XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links 8 Click No in response to Do you want to auto detect serial I O links for IBERT cores Auto detect Serial I O Links Lx Do you want to auto detect serial I O links f
10. Vivado Design Suite Tutorial Programming and Debugging UG936 v2015 1 May 18 2015 2 XILINX ALL PROGRAMMABLE amp XILINX ALL PROGRAMMABLE Revision History The following table shows the revision history for this document ew vein ee 05 18 2015 2015 1 Updates to the tutorials to reflect the 2015 1 Vivado software changes Programming and Debugging www xilinx com 2 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Table of Contents REVON ISCO aoe errec E seacnecataan ese crmaincen eos ciea E meat vive E E ecareenacoanean 2 Bye 910 re424 ical NAANA Be 180 a gt meen nee eee ore ne arn eg E T ee eee ee 5 WACO CIC TOI aea ba depnumnnunseunea sat ineresueietaea E E E 5 Oe oe e E pesca este ve os tas ee ney ca E wesc one erate apne ea sarau ene E E 5 GST Sie E e PEE OENE E E EE EEE E EERE EEE 6 Lab 1 Using the Netlist Insertion Method for Debugging a Design cccccecccceececeeececenececeneseeeeceseueceeeueceeeueeeeens 11 POOU O erer son E E E A E E T E E EE E E A TA E 11 Step 1 Creating a Project with the Vivado New Project Wizard sssssssesssssrssersnssrrserresrrresrrsererssrresrrrerrreerresns 11 SCI 2 VE Ne E DE E Meene E ES 12 Step Probing and Adding Debug IF sssiessnitecasesuna ena ER 14 Step 4 Implementing and Generating BitsStream cccccccccccseccccseccceeececeeecceseeseuececeueceseeceeeuseeeuaceeeueseeeueseeeness 24 Lab 2 Using the HDL Instantia
11. amp Constraints Wizard A Edit Timing Constraint I Set Up Debug i RIX PS EBR GABAA S Select an object to see properties Debug om m A ES Report Timing Summa A l My Report Clock Networks z E Driver Cell i ub labtools_xsdbm_v1 a E Report Clock interactio TT dae yale labtools_xsdbslavelib_v2 5 Report DRC E Unassigned Debug Nets 202 3 FE Report Noise oy ti axi_araddr 32 EDRE Me J axi_araddr 0 FDRE Report Utilization T2 axi_araddr 1 EDRE SD Report Power wk 1 ax_araddr 2 FDRE F e axi_araddr 3 FDRE 2H Schematic a J2 axi_araddr 4 FDRE d io in To avi araddr S cnoec 4 Implementation Implementation Settings D Pun Imnlamantation Debug Cores Debug Nets A Td Console gt Messages l EJ Log A Reports gt gt Design Runs Debug Figure 140 Debug Window in the Vivado IDE Programming and Debugging www xilinx com 119 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions c Click the Set up Debug toolbar button to launch the Set up Debug wizard Set Up Debug Set Up Debug V VADO ran This wizard will guide you through the process of 1 Choosing nets and connecting them to debug cores 2 Associating a clock domain with each of the nets chosen for debug 3 Choosing additional features on the debug cores like Data Depth Advanced
12. ssesesssssesssesreserrsrrrereeresrerereserrererereseerserseeeseee 80 Step 2 Adding an IBERT core to the Vivado Project ccccccseccccsececenececenscceencsseuecsceueceeeeceeeueeseueceseueceseueeeeeness 81 Step 3 Synthesize Implement and Generate Bitstream for the IBERT GeSIQN ccccceeeccceseeceeeseceeeceeeeeseeeness 88 Step 4 Interact with the IBERT core using Serial I O Analyzer ccccccccccccccccececseeeeseeeeceecececsscseeeeeeeeueeeeseeeeeeeess 90 Lab 6 Using Vivado ILA core to Debug JTAG AXI TransactiOns ccsccccssseccccesececeesececeusececseeceeeeeeceeteuesetseneess 107 HACE OCUCTI e chet toundonanrssnnceieneieesuncinecsts andes E EE E 107 BSS ISS Cl IO rsatncrecvennmesouctiesdaneinansqucinwnasveinneaecaiousquunncea auden E EE 108 Step 1 Opening the JTAG to AXI Master IP Example Design and Configuring the AXI Interface Debug CS CNOA este ct geese cee csc E ea ettnss pane E E A 108 Step 2 Program the KC705 Board and Interact with the JTAG to AXI Master Core cccccceessceeeseeeeeseeeneseeees 126 Step 3 Using ILA Advanced Trigger Feature to Trigger on an AXI Read Transaction ccccceeccesecceseeeeeeeeeuss 133 LAN IN CCG OS r E E EEE EE EEE E AE AE EE AE AAEE AE EAE EE EE E 139 Please Read Impor ant Legal NOU CCS rinse cssnesasuescrasnsctcosaacoeaesacucocenesuisucsnanccesonce E sawed enaousacoaas 139 Programming and Debugging www xilinx com 4 UG936 v2015 1 May 18 2015 Send Feedback amp
13. Expand Unassigned Debug Nets folder The following figure shows those debug nets that were tagged in sinegen_ demo vhd with mark_debug attributes l 62 Add mark debug attributes to show debug nets in 638 attribute mark debug string 648 attribute mark debug of GPIO BUTTONS db signal is true 65 attribute mark debug of GPIO BUTTONS dly signal is true 668 attribute mark debug of GPIO BUTTONS re signal is true 67 attribute mark debug of DONT EAT signal is true 66 69 70 component ginegen 71 Port T2 TA clk z in std logic 74 reset in std logic 75 ael z in std logic vector 1 downto 0 76 aine out std logic vector 19 downto 0 TT IE TE 79 end component Figure 5 VHDL Example Using MARK_DEBUG Attributes Name Driver Cell EBD Unassigned Debug Nets 6 J GPIO_BUTTONS_db 2 FDRE J GPIO_BUTTONS_db 0 FDRE J GPIO_BUTTONS_db 1 FDRE JP GPIO_BUTTONS_dly 2 FORE T GPIO_BUTTONS dly 0 FORE T GPIO_BUTTONS_dly 1 FORE 5 GPIO_BUTTONS_re 2 FDRE J GPIO_BUTTONS_re 0 FDRE J GPIO_ BUTTONS ref1 FDRE Debug Cores Debug Nets Figure 6 Unassigned Debug Nets Post Synthesis 4 Select the Netlist tab and expand Nets Select the following nets for debugging shown in the following figure o GPIO BUTTONS IBUF 0 and GPIO BUTTONS IBUF 1 Nets folder under the top level hierarchy o sel 2 Nets folder under the U_SINEGEN hierarchy Programming and Debugging
14. Retrigger mode the ILA core does the following repetitively until you disable the Auto Retrigger mode option o Arms the trigger o Waits for the trigger o Uploads and displays waveforms 4 On the KC705 board press the Sine Wave Sequencer button until you see multiple transitions on the GPIO_BUTTONS_1_IBUF signal this could take 10 or more tries This is a visualization of the glitch that occurs on the input An example of the glitch is shown in the following two figures CAUTION You may have to repeat the previous 2 steps repeatedly to see the glitch Once you can see the glitch you may observe signal glitches are not at exactly the same location as shown tn the figure below Programming and Debugging www xilinx com 65 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware hw _ila_data_1 wecig AE U SINEGEN sal 1 0 oe 4 GPO _BUTTONS_re 1 0 oe ES GPIO_BUTTONS_dly 1 0 Figure 72 GPIO_BUTTONS BUF1 Signal Glitch hw _ila_data_1 wecig A E U SINEGEN sel 1 0 SA GPIO_BUTTONS_re i 0 EA E GPIO_BUTTONS_dly 1 0 A T E GPIO BUTTONS _db 1 0 IE GFIO_BUTTONS_IBUF 0 0 oe 4 GPIO_BUTTONS_IBUF_1 1 1 Figure 73 GPIO Buttons_1_re Signal Glitch magnified Fixing the Signal Glitch and Verifying the Correct State Machine Behavior The multiple transition glitch or bounce occurs because the mechanical button is making and breaking el
15. XILINX ALL PROGRAMMABLE Debugging in Vivado Tutorial Introduction This document contains a set of tutorials designed to help you debug complex FPGA designs The first four labs explain different kinds of debug flows that you can chose to use during the course of debug These labs introduce the Vivado debug methodology recommended to debug your FPGA designs The labs describe the steps involved in taking a small RTL design and the multiple ways of inserting the Integrated Logic Analyzer ILA core to help debug the design The fifth lab is for debugging high speed serial I O links in Vivado The sixth lab is for debugging JTAG AXI transactions in Vivado The first four labs converge at the same point when connected to a target hardware board Example RTL designs are used to illustrate overall integration flows between Vivado logic analyzer ILA and Vivado Integrated Design Environment IDE In order to be successful using this tutorial you should have some basic knowledge of Vivado Design Suite tool flow TRAINING Xilinx provides training courses that can help you learn more about the concepts presented in this document Use these links to explore related courses e Vivado Design Suite Hands on Introductory Workshop Training Course e Vivado Design Suite Tool Flow Training Course e Essentials of FPGA Design Training Course e Vivado Design Suite User Guide Programming and Debugging UG908 Objectives These tutorials e Show
16. gt push_button_reset PROBE OUTO 1 gt push_button_vio Figure 27 VIO Instantiation in the Top Level Design At this point the Sources window should look as shown in the following figure x 2 Ai Be 6 Design Sources 1 4 sinegen_demo_inst_vio hdl_inst_vio sinegen_ce amp U_DEBOUNCE_0 debounce Mixed debounce vhe g U_DEBOUNCE_1 debounce Mixed debounce vhd H U_SINEGEN sinegen kintex sinegen vhd p A U_FSM fsm Mixed fsm vhd Simulation Sources 1 Hierarchy IP Sources Libraries Compile Order Figure 28 Instantiated VIO Core in the Sources Window Programming and Debugging www xilinx com 34 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 3 Using a VIO Core for Debugging a Design in Vivado 16 Double click sinegen_demo_inst vhd in the Sources window to open it and inspect the instantiation and port mapping of the ILA core in the HDL code U ILA ila 0 port map CLK gt clk PROBEO sineSel PROBE1 gt sine PROBE2 push_button_reset push_button_vio PROBES GPIO BUTTONS re PROBE4 GPIO BUTTONS dly Figure 29 Hook signals that need to be debugged in the ILA Step 2 Synthesize Implement and Generate Bitstream 1 From the Program and Debug drop down list in Flow Navigator click Generate Bitstream This synthesizes implements and generates a bitstream for the design 2 The No Implementation Results
17. lt MGT_XOY12 RX xc7k325t_0 Quad_118 gt MGT_X0 13 TX xc7k325t_0 Quad_118 MGT_X0Y13 RX xc7k325t_0 Quad_118 E gt MGT_X0Y14 TX xc7k325t_0 Quad_118 lt MGT_XOY14 RX xc7k325t_0 Quad_118 E MGT_XOY15 TX xc7k325t_0 Quad_118 lt q MGT_XOY15 RX xc7k325t_0 Quad_118 New Links Press the e button to Add Link Create link group Link group description Link Group 1 Open Serial I O Analyzer layout Figure 116 Selecting the Transceiver Pairs for Creating New Links Click the green button add a new link In the Link group description field type Link Group SMA Select the Internal Loopback check box Programming and Debugging www xilinx com UG936 v2015 1 May 18 2015 Send Feedback 98 amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links b Create Links To create a new link select a TX GT and or an RX GT then click the Add button on the New Links toolbar TX GTS RX GTS Search a Search Cl MGT_X0Y10 TX xc7k325t_0 Quad_117 MGT_X0Y10 RX xc7k325t_0 Quad_117 E MGT_XOY11 TX xc7k325t_0 Quad_117 lt MGT_XOY11 RX xc7k325t_0 Quad_117 E gt MGT_XOY12 TX xc7k325t_0 Quad_118 lt A MGT_XOY12 RX xc7k325t_0 Quad_118 E MGT_X0Y13 TX xc7k325t_0 Quad_118 lt MGT_XOY13 RX xc7k325t_0 Quad_118 gt MGT_X0Y14 TX xc7k325t_0 Quad_118 lt MGT_XOY14 RX xc7k325t_0 Quad_118 gt MGT_XOY15 TX xc7k325t_0 Quad_118 lt q MGT_XOY15 RX xc7k325t_0 Quad_118 New
18. sineSel input probe by right clicking PROBE_INO 0 and PROBE_INO 1 and selecting LED VIO Probes A Name Value Activity Direction VIO push_button_reset_1 i hw_vio_1 sineSel_ 1if1 0 rHin sineSel_1 1 Debug Probe Properties Ctri E sineSel_1 0 a GPIO_BUTTONS_re_1 1 1 E Text ta push_button_vio_1 _ Radix Activity Persistence X Remove Delete Export to Spreadsheet Figure 89 Change sineSel to LED 24 In the Select LED Colors dialog box pick the Low Value Color and the High Value Color of the LEDs as you desire and click OK Select LED Colors amp Low Value Color O Gray High Value Color Red Figure 90 Pick the Low Value and High Value Color of the LEDs Programming and Debugging www xilinx com 77 UG936 v2015 1 May 18 2015 Send Feedback XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware 25 When finished your VIO Probes window in the Hardware Manager should look similar to the following figure VIO Probes A Name Value Activity Direction lt 1 4 GPIO_BUTTONS_re_i 1 1 B 0 r Eis sineSel_1 1 0 H 1 x J sineSel_1 1 J sineSel_1 0 Q lt j ta push_button_reset_1 a push_button_vio_1 0 Output Figure 91 Input and Output VIO Signals Displayed 26 To cycle through each different sine wave output frequency using the virtual push_button_vio from the VIO core follow the following simple steps a Toggle the va
19. Available dialog box appears Click Yes 3 After bitstream generation completes the Bitstream Generation Completed dialog box appears Open Implemented Design is selected by default Click OK 4 Inspect the Timing Summary report and make sure that all timing constraints have been met Qe a 2 X 4 Design Timing Summary General Information gt Timer Settinas Setup Hold Pulse Width Timing Summan Worst Negative Slack WNS 1 274 ns Worst Hold Slack WHS 0 059 ns Worst Pulse Width Slack WPWS 1 732 ns Clock Summary 4 Total Negative Slack TNS 0 000 ns Total Hold Slack THS 0 000 ns Total Pulse Width Negative Slack TPWS 0 000 ns Check Timing Intra Clock Paths Number of Failing Endpoints 0 Number of Failing Endpoints 0 Number of Failing Endpoints 0 Inter Clock Paths Total Number of Endpoints 3679 Total Number of Endpoints 3679 Total Number of Endpoints 2012 Other Path Groups User Ignored Paths All user specified timing constraints are met Unconstrained Paths Timing Summary timing_1 x Figure 30 Report Timing Summary Dialog Box 5 Proceed to Using Vivado Logic Analyzer to Debug Hardware chapter to complete the rest of the steps for debugging the design Skip forward to Verifying the VIO Core Activity Only applicable to Lab 3 section to complete the rest of this lab Programming and Debugging www xilinx com 35 UG936 v2015 1 May 18 2015 Send Feedback amp XILI
20. Create a Post Synthesis Project in Vivado IDE ccccccssecccsecccesecceeececeececeueceeeeceeeeeseueceeeueceteneeeeenses 46 Step 5 Add more Debug Nets to the Project eessseresesrrssrresesrrressrtresrrressrtresrreresrtrrsrrressrtresrreeserereserressreress 48 Step 6 Implementing the Design and Generating the Bitstream esssesssesssssrsssrrrsrrrrsrresrrrssrrnsrressrresrresrrreerreses 50 Using Vivado Logic Analyzer to Debug Hardware ccccccsccccseccccsecscenececeneceeeseeeeuecsceueceeeuesseeeeeeenceseuaceesueceesueeeeens 51 MOOC TI OIA e E E E T E E A E E EE E R 51 Step 1 Verifying Operation of the Sine Wave Generator cccccccccseecccseecccesesceuececeeceeeeceeeueeeeunceseueceteneseeeness 51 Step 2 Debugging the Sine Wave Sequencer State Machine Optional esesssessssesresesrrssrrereerrrssrrereerrresrreren 62 Programming and Debugging www xilinx com 3 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Verifying the VIO Core Activity Only applicable to Lab 3 ceeccccccccccccssesseeeccceeeeeeeeseeeceeeessaeaesseeeeeeeseuaaneses 67 Lab 5 Using Vivado Serial Analyzer to Debug Serial LINKS cccccessccccssececeesececeeeceeceescceceeececsenecesseeceeteeeeeeeas 79 PTOI TON dece carseneucd tenes neces ann euos nnecs cat cnceeoumneeeseusueiencistneeetemoieaunneresduc merstuenenas E 79 BSS ADES TrID I Oae A E NEA 79 Step 1 Creating Customizing and Generating an IBERT Design
21. Figure 56 Active Target Hardware 8 Next program the XC7K325T device using the bit bitstream file that was created previously by right clicking the XC7K325T device and selecting Program Device as shown in the following figure _ Hardware Manager localhost xilinx_tcf Digilent 210203327962A There are no debug cores Program device Refresh device sinegen vhd a zese bi gt gt mi C Vivado_Debt N 5 164 sa oe tatus 165 age localhost 1 Connected Ol 166 m a E Me xilinx_tcf Digilent 210203327962A 1 _ Open sae XC 2 LO 1 active Hardware Device Properties Refresh Device Add Configuration Memory Device Export to Spreadsheet Figure 57 Program Active Target Hardware Programming and Debugging www xilinx com 56 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX Using Vivado Logic Analyzer to Debug Hardware ALL PROGRAMMABLE 9 In the Program Device dialog box verify that the bit file is correct for the lab that you are working on and click Program to program the device as shown in the following figure id J f Program Device wa Select a bitstream programming file and download it to your hardware device You can optionally select a debug probes file that corresponds to the debug cores contained in the bitstream programming file Bitstream file C Vivado_Debug proj_netlist proj_netlist runs impl_1 sinegen_demo bit Debug Probes file C Vivado_Debug proj_netlist proj_netli
22. Links Description TX RX Internal Loopback Link 1 MGT_XOY9 TX xc7k325t_0 Quad_117 MGT_XOY9 RX xc7k325t_0 Quad_117 w Create link group Link group description Link Group SMA Open Serial I O Analyzer layout Figure 117 Create Links Dialog Box For the first link group call this Link Group SMA as this is the only transceiver channel that is linked through the SMA cables The new link shows up in the Links window TX RX Status Bits Errors i amp v MGT _X0Y8 TX MGT_X0Y8 RX 8 000 Gbps 2 167 0E0 Figure 118 Create Link Groups for Other Transceiver Pairs Programming and Debugging www xilinx com 99 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links Click Create Link again to create link groups for the rest of the transceiver pairs To do this ensure that the transceiver pairs are selected and click the sign icon add new link repeatedly until all the links have been added to the new link group called Link Group Internal Loopback Click OK g Create Links To create a new link select a TX GT and or an RX GT then click the Add button on the New Links toolbar TX GTS RX GTS Search Search New Links ate Description TX RX Internal Loopback Link 1 MGT_XO 9 TX xc7k325t_0 Quad_117 MGT_XOY9 RX xc7k325t_0 Quad_117 Link 2 MGT_XO0V10 TX xc7k325t_0 Quad_117 MGT_XOY10 RX xc7k3
23. Netlist DONT_EAT2 J DONT_EAT3 J DONT_EAT4 DONT_EATOO DONT_EATOO_out J DONT_EAT10 J DONT_EAT20 JS DONT_EAT30 J DONT_EAT40 GPIO_ BUTTONS _IBUF O gee aGPIO BUTTONS IBUF 1 GPIO_SWITCH GPIO_SWITCH_IBUF S I J n_0_DONT_EAT_reg JS n_0_GPIO_BUTTONS_dly 0 _i_1 J n_O_GPIO_BUTTONS_dly 1 _i_1 J n_0_GPIO_BUTTONS_re 0 _i_1 J n_0_GPIO_BUTTONS_re 1 _i_1 n_0_U_FSM 1 U_FSM _3_U_SINEGEN _U_SINEGEN _U_SINEGEN 2_U_SINEGEN 6_U _4 8 J J ei mf J 1 1 SINEGEN Figure 10 Netlist View of Nets Marked for Debug Programming and Debugging www xilinx com UG936 v2015 1 May 18 2015 19 Send Feedback XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design Running the Set Up Debug Wizard 7 From the Debug window or Tools menu select Set Up Debug The Set up Debug wizard opens l Driver Cell Unassigned Debug Nets 31 i GPIO_BUTTONS_db 2 RE ie T GPIO_BUTTONS_db 0 i st GPIO_BUTTONS_db 1 are GPIO_BUTTONS_dly 2 ad m Launch wizard for choosing nets and connecting them to debug cores Ti GPIO_BUTTONS_re 1 I U_SINEGEN sel 2 bi Tau A 20 lea 3 el AAAA R We GPIO BUTTONS IBUF 2 Ji GPIO_BUTTONS_IBUF O gt GPIO BUTTONS _IBUF 1 Debug Cores Debug Nets Figure 11 Launching the Set up Debug Wizard Programming and Debugging www xilin
24. PROBES gt GPIO_BUITIONS re PROBE4 gt GPIO BUTTONS dly PROBES gt GPIO BUITONS Figure 18 Hook Signals that Requiring Debugging in the ILA Step 2 Synthesize Implement and Generate Bitstream 1 From the Program and Debug drop down list in Flow Navigator click Generate Bitstream This will synthesize implement and generate a bitstream for the design 4 Program and Debug os ae Wich csr a Ad coh a a 5 Bitstream Settings lt iW Y Generate piser General Properties a gt Open Hardware Ji Generate Bitstream ae Launch iMPACT Generate a programming file after implementation XC7k325tffg900 Figure 19 Generate Bitstream 2 The No Implementation Results Available dialog box appears Click Yes 3 After bitstream generation completes the Bitstream Generation Completed dialog box appears Open Implemented Design is selected by default Click OK 4 Inthe Report Timing Summary dialog box Make sure that all timing constraints are met Click OK Programming and Debugging www xilinx com 27 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 2 Using the HDL Instantiation Method for Debugging a Design in Vivado ake 4 Design Timing Summary hei La G This isa saved report x setup Hold Pulse Width General Informati feaneaea Worst Negative Slack WNS 1 218 ns Worst Hold Slack WHS 0 069 ns Worst Pulse Width Slack WPWS 1 732 ns z Total Negative Slack TNS
25. PROBE_IN1 255 0 m Input Registers PROBE_OUT1 0 0 ee OS and Activity Output Registers iia PROBE_IN255 31 0 a Detectors PROBE_OUT255 127 0 Interface to JTAG through Debug Hub Figure 21 VIO Block Diagram This lab walks you through the steps of instantiating and configuring the VIO core It walks you through the steps of connecting the I Os of the design to the VIO core This way you can debug your design when you do not have access to the hardware or the hardware is remotely located The following ports are created e One 4 bit PROBE_INO port This has two bits to monitor the 2 bit Sine Wave selector outputs from the finite state machine FSM and other two bits to mimic the state of the other two LEDs on the Programming and Debugging www xilinx com 29 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 3 Using a VIO Core for Debugging a Design in Vivado board We will configure these 4 bit signals as LEDs during run time to mimic the LEDs displayed on the KC705 board One 2 bit PROBE_OUTO port to drive the input buttons on the FSM We will configure it so one bit can be used as a toggle switch during run time to mimic the PUSH_BUTTON SW3 and second bit will be used as the PUSH_BUTTON SW6 Step 1 Creating a Project with the Vivado New Project Wizard To create a project use the New Project wizard to name the project to add RTL source files and constraints and to specify t
26. Set Up Debug wizard e Implement and open the design e Generate the bitstream Adding Debug Nets to the Project Following are some ways to add debug nets using the Vivado IDE e Add mark_debug attribute to HDL files VHDL attribuce mark debug 1 string attribute keep string attribute mark debug of sine gt Signal is true artribu te Mark debug Of sine sel Signal i Crue Verilog mark debug true wire sine mark debug true wire Simeno Programming and Debugging www xilinx com 14 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design This method provides lets you probe signals at the HDL design level This can prevent optimization that might have otherwise occurred to that signal It also lets you pick up the signal tagged for post synthesis so you can insert these signals into a debug core and observe the values on this signal during FPGA operation This method gives you the highest probability to preserve HDL signal names after synthesis e Right click and select Mark Debug or Unmark Debug on a synthesized netlist This method is flexible since it allows probing the synthesized netlist in the Vivado IDE and allowing you to add remove MARK_DEBUG attribute at any hierarchy in the design In addition this method doesn t require HDL source modification However there may be situations where synthes
27. Trigger mode and Capture Control Note This setup wizard does not apply to the VIO IBERT or JTAG to AXEMaster debug cores Please refer to Vivado Design Suite User Guide Programming and Debugging UG908 for further instructions on how to use these IPs To continue click Next Finish Figure 141 Set Up Debug Wizard 23 Once the Set up Debug wizard pops up click Next Programming and Debugging www xilinx com 120 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 24 In the next page of the Setup Debug wizard note that some of the nets that you would like to debug have no detectable clock domains selected Click the more info link in the message banner La Qe La The nets below will be debugged with ILA cores To add nets click Find Nets to Add You can also select D nets in the Netlist or other windows then drag them to the list or click Add Selected Nets E Some net s do not have a clock domain more info i p pean Missing Clock Domain x aa JF axi arburst 2 To show only nets that do not have a clock domain click 72 nets a rs S axi_arlen 8 t B H axi_awburst 2 To assign the same clock domain to all nets click Assign All Clock Domains L 4 axi_awlen 8 3 SUE 4 axi_rdata 32 3 m F axi wdata 32 To assign a clock domain to specified nets select the nets and
28. Vivado IP Catalog 3 Double click IBERT 7 Series GTX IP This brings up the customization GUI for the IBERT 4 In the Customize IP dialog box choose the following options in the Protocol Definition tab a Type the name of the component in the Component Name field In this case leave the name as the default name ibert_7series_gtx_0 b Ensure that the Silicon Version is selected as General ES Production c Ensure that the Number of Protocols option is set to 1 d Change the LineRate Gbps to 8 e Change DataWidth to 40 f Change Refclk MHz to 125 g Ensure that the Quad Count is set to 2 h Ensure Quad PLL box is selected Programming and Debugging www xilinx com 82 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links F Customize IP x IBERT 7 Series GTX 3 0 g wi Documentation C IF Location C3 Switch to Defaults Show disabled ports Component Name fibert_7series_gtx_0 Protocol Definition Protocol Selection Clock Settings Summary Silicon Version General ES Production Initial ES RXN_I 3 0 The maximum number of quads available for this device is 4 RXP_I 3 0 TXN_O 3 0 Number of Protocols 1 F7 GTREFCLKO_I 0 0 TXP_O 3 0 Protocol LineRate Gbps DataWidth Refclk MHz Quad Count Quad PLL SYSCLK_I ox _ cancel _ Figure 95 Setting the Protocol Definition on the IBERT Core 5 Under the Protocol Selection t
29. again Figure 102 No Implementation Results Available Dialog Box Programming and Debugging www xilinx com 88 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links 2 When the bitstream generation is complete the Bitstream Generation Completed dialog box appears Select Open Hardware Manager Click OK Bitstream Generation Completed GD bitstream Generation successfully completed Open Implemented Design E View Reports Open Hardware Manager Don t show this dialog again Cena Figure 103 Bitstream Generation Completed Dialog Box 3 The Hardware Manager window appears as shown in the following figure Programming and Debugging www xilinx com UG936 v2015 1 May 18 2015 Send Feedback 89 amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links ibert_7series_gtx_0_example c Vivado_Debug 2015 1 ibert_tutorial ibert_7series_gtx_0_example ibert_Jseries gt lt _0 a amp x File Edit Flow Tools Window Layout View Help Q Search commands 200 X gt gt HGK XG E Seria yo analyzer 7 Hg e a Flow Nawigator 4 Project Manager 5 Project Settings B7 Add Sources Language Templates F IP Catalog ae gt gt a IP Integrator No content Create Block Design B Open Block Design Generate Block Design Simulation 4 Simulation Settings T Run Si
30. box asking you to create a non existing directory click OK lt gt Synplify Pro The directory C tutorials ug936 does not exist Do you wish to create it A Figure 32 Synplify Pro project Confirmation Dialog Box 3 In the left panel of the Synplify Pro window click Add File as shown in the following figure Synplify Pro I 2013 09 1 C Vivado_Debug synopsys synplify_1 prj File Edit View Project Import Run Analysis HDL Analyst Options Window Tec Sf amp a PAM OVE SLI EH SD SH PRRRS22322 4 2 B we EB ws Reels Pro i Run Ready amp Open Project Project Files Design Hierarchy Bi Close Project synplify_1 rev_i Xilinx Kintex7 XC7K70T FBG676 ial gt synplify_1 C Vivado_Debug synopsys synplify_1 prj dy S N rev_1 ES Change File Figure 33 Adding Files to a Synplify Pro Project 4 In the Add Files to Project dialog box change the Files of Type to HDL File Navigate to C Vivado Debug src Lab4 which shows all the VHDL source files needed for this lab Select the following three files by pressing the Ctrl key and clicking on them e debounce vhd e fsm vhd e sinegen demo vhd Click Add Programming and Debugging www xilinx com 37 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design Add Files to Project Look in C Vivado_Debug src Lab4 JQOO
31. compiler vo 0 viv edn e dds compiler vo 0 viv parameter zedl edn e dds compiler vo 0 viv parameterized gt edn e debounce vhd e fsm vhd Sine Digi xci e sine low xc1 e sine mid xci e sinegen edn e sinegen synplify vhd synolity 1 sdc e sinegen demo kc 05 xdc Lab 5 Debug high speed serial I O links using the Vivado Serial I O Analyzer This lab uses the Vivado IP example design Lab 6 Using Vivado ILA core to debug JTAG to AXI transactions This lab uses the Vivado IP example design Connecting the Boards and Cables 1 Connect the Digilent cable from the Digilent cable connector to a USB port on your computer 2 Connect the two SMA cables for lab 5 only as follows a Connect one SMA cable from J19 TXP to J17 RXP b Connect the other SMA cable from J20 TXN to J66 RXN The relative locations of SMA cables on the board are shown in Figure 1 KC705 Board Showing Key Components Programming and Debugging www xilinx com 10 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design Introduction In this lab you will mark signals for debug in the source HDL as well as the post synthesis netlist Then you will create an ILA core and take the design through implementation Finally you will use Vivado to connect to the KC705 target board and debug your design using Vivado Integrated Logic Analyzer Step 1 Creat
32. debug are located The attribute and the nets selected for debug are shown in the following figure fH Attributes that are needed to mark debug the nets that are needed to be viewed in ILA define attribute comment Mark sinegen as black box v iwork sinegen syn_black box 1 define attribute comment Set no prune on sinegen v work sinegen syn_noprune 1 define attribute comment Mark entire bus for debug 1 sinegen sine mark debug true define attribute comment Mark entire bus for debug 1 sinegen sel mark_debug true Figure 41 Synplify Pro Constraints in CDC Files In the above constraints sinegen has been defined as a black box by using the syn_black_box attribute Second the syn_no_prune attribute has been used so that the I Os of this block are not optimized away Finally two nets sine 20 0 and sel 1 0 have been assigned the mark_debug attribute such that these two nets should show up in the synthesized design in Vivado IDE for further debugging For further information on these attributes please refer to the Synplify Pro User Manual and Synplify Pro Reference Manual Step 2 Synthesize the Synplify Project 1 Before implementing the project you need to set the name for the output netlist file By default the name of the output netlist file is synplify_l edf To change the name of the output file type the following command at the Tcl command prompt eprojyect result file rev 1 sin gen de
33. dialog box opens 12 On the General Options tab leave the Component Name to its default value of vio_0 set Input Probe Count to 1 Output Probe Count to 1 and select the Enable Input Probe Activity Detectors check box Programming and Debugging www xilinx com 31 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 3 Using a VIO Core for Debugging a Design in Vivado F Customize IP VIO Virtual Input Output 3 0 Documentation IP Location CJ Switch to Defaults Show disabled ports Component Name To configure more than 64 probe ports use Vivado Tcl Console General Options PROBE_IN Ports 0 0 PROBE_OUT Ports 0 0 r Input Probe Count 1 0 256 srobe_in0 0 0 probe_out0 0 0 Output Probe Count 1 0 256 V Enable Input Probe Activity Detectors Figure 23 Configure General Options of the VIO Core 13 On the PROBE _IN Ports tab set Probe Width to 4 bits wide F Customize IP VIO Virtual Input Output 3 0 Documentation IP Location CJ Switch to Defaults Show disabled ports Component Name To configure more than 64 probe ports use Vivado Tcl Console General Options PROBE_IN Ports 0 0 PROBE_OUT Ports 0 0 Probe Port Probe Width PROBE_ING 4 Figure 24 Configure PROBE_IN Ports of the VIO Core Programming and Debugging www xilinx com 32 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABL
34. file and download it to your hardware device You can optionally select a PE debug probes file that corresponds to the debug cores contained in the bitstream programming file Bitstream file 15 1 jtag_axi_ 0_example jtag_axi_0_example runs impl_1 example_jtag_axi_0 bit awa Debug probes file Debug 2015 1 jtag_axi_0_example jtag_axi_0_example runs impl_1 debug_nets ltx luca v Enable end of startup check Boman cones Figure 155 Select Bitstream File to Download Note Wait for the program device operation to complete This may take few minutes 10 Verify that the JTAG to AXI Master and ILA cores are detected by locating the hw_axi_1 and hw_ila_1 instances in the Hardware Manager window Hardware Manager localhost xilinx_tcf Xilinx Port_ 0001 Hub_ 0001 x Hardware E hw il OQ mh me i i Di gt gt E Settings hw_ila_l O X Status hw_ila_1 Name Status Trigger Mode Settings amp Core status E localhost 1 Connected EE wait 4 ge xilinx_tcf Xilinx Port_ 0 Open Trigger mode BASIC_ONLY b gt Waiting for Trigger Post Trigger BE xc7k325t 0 3 cir ian XADC System Moni te aa O lle Capture Mode Settings Trigger Setup hw_ila_1 E ma Capture Setup hw_ila_1 Capture mode Number of windows Window data depth i ee Hardware Device Properties Ow x D roy Trigger position in window 4 VY e xc7k325t_0 General Settings Waveform hw_ila_1 Name xc7k325t_0 z Refresh rate sols Part xc7k325t
35. is equal to 1 just as the trigger state machine program intended Programming and Debugging www xilinx com 137 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to example_jtag_axi_0 v X ILA hw_ila_1 x hw_ila_data_l wcfg x EE O O Qh axi_rdata 31 0 OS Em axi_arprot 2 0 fom EE axi_arcache 3 0 A axi_arburst 1 0 mi axi_arsize 2 0 Iq axi_arlen 7 0 bl mi axi_araddr 31 0 re axi_bresp 1 0 be es ea axi_wstrb 3 0 af axi_wdata 31 0 axi_awprot 2 0 axi_awcache 3 0 axi_awburst 1 0 mae Ea axi_awsize 2 0 4 axi_awaddr 31 0 axi_awlen 7 0 axi_arid l axi_arlock axi_arready l axi_arvalid l axi_awid l axi_awlock i axi_awready i axi_avwvalid h axi_bid h axi_bready i axi_bvalid axi_rid l axi_rlast h axi_rready axi_rvalid Programming and Debugging UG936 v2015 1 May 18 2015 00000000 0 f 00000000 oop00000 0 0 0 0 0 0 2 2 00000000 IOV 00 Debug JTAG AXI Transactions Figure 162 Waveform window www xilinx com 138 Send Feedback amp XILINX ALL PROGRAMMABLE Legal Notices Please Read Important Legal Notices The information disclosed to you hereunder the Materials is provided solely for the selection and use of Xilinx products To the maximum extent permitted by applicable law 1 Materials are made availabl
36. setup work you will use Vivado logic analyzer to verify that the sine wave generator is working correctly Your two primary objectives are to verify that e All sine wave selections are correct e The selection logic works correctly Target Board and Server Set Up Connecting to the target board remotely If you plan to connect remotely you will need to make sure you have KC705 hardware plugged into a machine and you are running an hw_server application on that machine If you plan to connect locally skip steps 1 4 below and go directly to the Connecting to the Target Board Locally section 1 Connect the Digilent USB JTAG cable of your KC705 board to a USB port on a Windows system 2 Ensure that the board is plugged in and powered on 3 Power cycle the board to clear the device 4 Turn DIP switch positions pin 1 on SW13 De bounce Enable to the OFF position Programming and Debugging www xilinx com 51 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware 5 Assuming you are connecting your KC705 board to a 64 bit Windows machine and you will be running the hw_server from the network instead of your local drive open a cmd prompt and type the following lt xXilinx Install gt Vivado 2015 1 bin hw server Leave this cmd prompt open while the hw_server is running Note the machine name that you are using you will use this later when opening a connection
37. the nets marked for debug have the same clock domain Step 6 Implementing the Design and Generating the Bitstream 1 In the Flow Navigator under the Program and Debug drop down list click Generate Bitstream 2 In the Save Project dialog box click Save 3 When the Bitstream generation finishes the Bitstream Generation Completed dialog box pops up and Open Implemented Design is selected by default Click OK 4 If you get a dialog box asking to close the synthesized design before opening the implemented design click Yes 5 Proceed to Using Vivado Logic Analyzer to Debug Hardware to complete the rest of this lab Programming and Debugging www xilinx com 50 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware Introduction The final step in debugging is to connect to the hardware and debug your design using the Integrated Logic Analyzer Before continuing make sure you have the KC705 hardware plugged into a machine In this step you learn e How to debug the design using the Vivado logic analyzer e How to use the currently supported Tcl commands to communicate with your target board KC705 e How to discover and correct a circuit problem by identifying unintended behaviors of the push button switch e Some useful techniques for triggering and capturing design data Step 1 Verifying Operation of the Sine Wave Generator After doing some
38. using the Vivado Logic Analyzer tool e Pattern Generator Each GTX transceiver enabled in the IBERT design has both a pattern generator and a pattern checker The pattern generator sends data out through the transmitter e Error Detector Each GTX transceiver enabled in the IBERT design has both a pattern generator and a pattern checker The pattern checker takes the data coming in through the receiver and checks it against an internally generated pattern i Interface Pattern TXN TXP TX ES Generator External Serial Kintex 7 GTX Loopback via Transceiver SMA Cables Error Rx ES RxN RxP Detector GTX Port Detector Spore Figure 92 IBERT Design Flow Step 1 Creating Customizing and Generating an IBERT Design To create a project use the New Project wizard to name the project to add RTL source files and constraints and to specify the target device Programming and Debugging www xilinx com 80 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links 1 Invoke the Vivado IDE 2 In the Getting Started screen click Create New Project to start the New Project wizard Click Next 3 In the Project Name page name the new project ibert_tutorial and provide the project location C ibert tutorial Ensure that Create Project Subdirectory is selected Click Next In the Project Type page specify the Type of Project to create as RTL Pr
39. v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 10 In the leftmost panel of the Flow Navigator under Project Manager click IP Catalog amp Create Block Design BF Open Block Design Generate Block Desig 4 Simulation Simulation Settings Gi Run Simulation 4 RTL Analysis 4 Synthesis Synthesis Settings Run Synthesis gt BB Open Synthesized Dy 4 Implementation Implementation Sett gt Run Implementation gt B Open Implemented 4 Program and Debug 5 Bitstream Settings Y Generate Bitstream gt gt Open Hardware Mar amp jtag_2_axi_tutorial C Vivado_Debug 2015 1 jtag_2_axi_tutorial jtag_2_axi_tutorial xpr Vivado 2015 1 File Edit Flow Tools Window Layout View Help Q Search commands 5 Elaboration Settings gt E Open Elaborated De Hierarchy Libraries Com 4 amp Sources 9 Templates Properties ee en P E3 h 2 aeRh X gt D lS XE G E defautt Layout JRRD Ready Flow Navigator Project Manager jtag_2_axi_tutorial x a ope Sources OL XxX Project Summary X m i i r i aael kadeni T project settings a 5 Project Settings Sp cnr Project name jtag_2_axi_tutorial BF Add Sources S E Simulation Sources Project location _C Vivado_Debug 2015 1 jtag_2_axi_tutorial Y Language Templates sim_1 Product family Kintex 7 LF IP Catalog Project part Kintex 7 KC705 E
40. you how to take advantage of integrated Vivado logic analyzer features in the Vivado design environment that make the debug process faster and simpler e Provide specifics on how to use the Vivado IDE and the Vivado logic analyzer to debug common problems in FPGA logic designs e Provide specifics on how to use the Vivado Serial I O Analyzer to debug high speed serial links Programming and Debugging www xilinx com 5 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Debugging in Vivado Tutorial After completing this tutorial you will be able to e Validate and debug your design using the Vivado Integrated Design Environment IDE and the Integrated Logic Analyzer ILA core e Understand how to create an RTL project probe your design insert an ILA core and implement the design in the Vivado IDE e Generate and customize an IP core netlist in the Vivado IDE e Debug the design using Vivado logic analyzer in real time and iterate the design using the Vivado IDE and a KC705 Evaluation Kit Base Board that incorporates a Kintex 7 device e Analyze high speed serial links using the Serial I O Analyzer Getting Started Setup Requirements Before you start this tutorial make sure you have and understand the hardware and software components needed to perform the labs included in this tutorial as listed below Software e Vivado Design Suite 2015 1 Hardware e Kintex 7 FPGA KC705 Evaluation Kit Base
41. 0 000 ns Total Hold Slack THS 0 000 ns Total Pulse Width Negative Slack TPWS 0 000 ns Clock Summary 4 Number of Failing Endpoints 0 Number of Failing Endpoints 0 Number of Failing Endpoints 0 Check Timing 7 l l G Intra Clock Paths Total Number of Endpoints 3657 Total Number of Endpoints 3657 Total Number of Endpoints 2023 Inter Clock Paths P P P Other Path Groups a All user specified timing constraints are met Timing Summary impl_1 x Figure 20 Review Timing Summary 5 Proceed to Using Vivado Logic Analyzer to Debug Hardware chapter to complete the rest of this lab Programming and Debugging www xilinx com 28 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 3 Using a VIO Core for Debugging a Design in Vivado Introduction The Virtual Input Output VIO core is a customizable core that can both monitor and drive internal FPGA signals in real time The number and width of the input and output ports are customizable in size to interface with the FPGA design Because the VIO core is synchronous to the design being monitored and or driven all design clock constraints that are applied to your design are also applied to the components inside the VIO core Run time interaction with this core requires the use of the Vivado logic analyzer feature The following figure is a block diagram of the new VIO core VIO CLK PROBE _ NO 0 0 PROBE OUTO 255 0
42. 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design 7 Inthe same dialog box set Files of type to Compiler Directives File This shows the synplify 1 cdc file Select the file and click Add as shown in the following figure Click OK Add Files to Project Look in C Vivado_Debug src Lab4 JO O0 WA My Computer R ndutta File name synplify_1 cdc Files of type VHDL Verilog lib y Files to add to project 5 file s selected Y Use relative paths Y Add files to Folders Folder Options src Lab4 debounce vhd lt Add All src Lab4 fsm vhd src Lab4 sinegen_demo vhd A src Lab4 synplify_l sdc m Asrc Lab4synplify_1 cdc Remove All gt Figure 36 Adding CDC Constraints File to the Synplify Pro Project Programming and Debugging www xilinx com 40 UG936 v2015 1 May 18 2015 Send Feedback XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design 8 Now you need to set the implementation options Click Implementation Options in the Synplify Pro window as shown in the following figure Se Dya Sa A GS a a TP ISS TIE ro I 2013 09 1 C Vivado_Debug synopsys synplify_1 File Edit View Project Import Run Analysis HDL Analys ee gt AA amp OD s MM PRRR SS 2B we Bw BR es Synplify Pro Open Project Project Files Design Hierarc
43. 2 Open Hardware Target Programming and Debugging www xilinx com 129 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions ALL PROGRAMMABLE Once the connection to the hardware target is made the dialog shown in the following figure appears Note The Hardware tab in the Debug view shows the hardware target and XC7K325T device that was detected in the JTAG chain Status Connected He xilinx_tcf Digilent 210203327962A 1 Open Not programmed xc7k325t_0O 1 active i XADC System Monitor Figure 153 Hardware Target and XC7K325T Device 8 Next program the XC7K325T device using the bit bitstream file that was created previously by right clicking the XC7K325T device and selecting Program Device as shown in the following figure eS xc7k325t 0 1 active es F XADC System Monitor amp Add Configuration Memory Device Export to Spreadsheet Hardware Device Properties i lid Tn Figure 154 Program Active Target Hard 130 Programming and Debugging www xilinx com UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 9 In the Program Device dialog box verify that the bit file is correct for the lab that you are working on Click the OK to program the device Program Device bx Select a bitstream programming
44. 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware 21 Set the push_button_reset output probe by right clicking push_botton_reset and select Toggle Button This will toggle the output driver from logic from 0 to 1 to 0 as you click It is similar to the actual push button behavior though there is no bouncing mechanical effect as with a real push button switch _ VIO Probes Dush_button_reset gemma r His sineSel_1 1 0 ww GPIO_BUTTONS _re x ta push_button_vio_1 qi Value Activity Direction VIO Ctrl E Debug Probe Properties Text Active High Button Active Low Button Delete Export to Spreadsheet Figure 87 Toggle the push_button_reset Signal The Value field for push_button_reset is highlighted Click in the Value field to change its value to 1 VIO Frobes A Name gi r g push_button_reset_1 c ig sineSel_1 1 0 o Input x 8 GPIO_BUTTONS_re_1 1 1 B 0 Input ta push_button_vio_1 oO Value Activity Direction VIO Sa Ce hw_vio_1 hw_vio_1 Output hw_vio_1 Figure 88 Toggle the Value of push_button_reset Programming and Debugging UG936 v2015 1 May 18 2015 www xilinx com 76 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware 22 Follow the step above to change the push_button_vio to Toggle button as well 23 Set these two bits of the
45. 25t_0 Quad_117 S Link 3 MGT_XOV11 TX xc7k325t_0 Quad_117 MGT_XO 11 RX xc7k325t_0 Quad_117 Link 4 MGT_XO 12 TX xc7k325t_0 Quad_118 MGT_XOY13 RX xc7k325t_0 Quad_118 Link 5 MGT_XO0V13 TX xc7k325t_0 Quad_118 MGT_XOY13 RX xc7k325t_0 Quad_118 Link 6 MGT_XO0Y14 TX xc7k325t_0 Quad_118 MGT_X0Y14 RX xc7k325t_0 Quad_118 Link 7 MGT_XOY15 TX xc7k325t_0 Quad_118 MGT_XOY15 RX xc7k325t_0 Quad_118 RREREERIS Create link group Link group description Link Group Internal Loopback Open Serial I O Analyzer layout Figure 119 Create Link Dialog Box to Create the Second Link Group Programming and Debugging www xilinx com 100 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links 11 Once the links have been created they are added to the Links window as shown A Name TX RX Status B its Errors BER BERT Reset a Ungrouped Links 0 ra E Link Group SMA 1 h Link 0 MGT _XOY8 TX MGT_XOY8 RX 8 000 Gbps 2 023E12 3 34E 1 651E 10 Reset Link Group Intern __ Reset Ge Link 1 MGT_XOYS TX MGT_XO0Y9 RX 8 000 Gbps 2 023E12 9 599E11 4 744E 1 CE Reset Oy Link 2 MGT_X0Y10 TX MGT_XOY10 RX 8 000 Gbps 27 024E12 1 007E12 4 95E 1 lesel Link 3 MGT_X0Y11 TX MGT_X0Y11 RX 8 000 Gbps 2 024E12 9 603E11 4 744E 1 2 Reset Link 4 MGT_X0 12 TX MGT_XOY12 RX 8 000 Gbps 7 025E12 1 002E12 4 95E 1 Reset Link 5 MGT_X0Y13 TX MG
46. 8 Output Sine Wave Displayed in Analog Format Mixed Frequency Note As you sequence through the sine wave selections you may notice that the LEDs do not light up in the expected order You will debug this in the next section of this tutorial For now verify for each LED selection that the correct sine wave displays Also note that the signals in the Waveform window have been re arranged in the previous three figures Step 2 Debugging the Sine Wave Sequencer State Machine Optional As you were correcting the sine wave display the LEDs might not have lit up in sequence as you pressed the Sine Wave Sequencer button With each push of the button there should be a single cycle wide pulse on the GPIO_BUTTONS_re 1 signal If there is more than one the behavior of the LEDs becomes irregular In this section of the tutorial use Vivado logic analyzer to probe the sine wave sequencer state machine and to view and repair the root cause of the problem Before starting the actual debug process it is important to understand more about the sine wave sequencer state machine Sine Wave Sequencer State Machine Overview The sine wave sequencer state machine selects one of the four sine waves to be driven onto the sine signal at the top level of the design The state machine has one input and one output The following figure shows the schematic elements of the state machine Refer to this diagram as you read the following description and as you perf
47. Board e Digilent Cable e Two SMA Sub miniature version A cables Programming and Debugging www xilinx com 6 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Debugging in Vivado Tutorial Sra Wem E s s umn apenas 6 Selection i indicator USB JTAG SS FAO ira Connector PMP ATBIAD ee Debounce Him ss ws oe Enable i X Neo Reset B er ee Sine Wave s Sequencer x14596 Figure 1 KC705 Board Showing Key Components Tutorial Design Components Labs 1 through 4 include A simple control state machine Three sine wave generators using AXI Streaming interface native DDS Compiler Common push buttons GPIO_BUTTON DIP switches GPIO_SWITCH LED displays GPIO_LED VIO Core Lab 3 only Push Button Switches Serve as inputs to the de bounce and control state machine circuits Pushing a button generates a high to low transition pulse Each generated output pulse is used as an input into the state machine DIP Switch Enables or disables a de bounce circuit De bounce Circuit In this example when enabled provides a clean pulse or transition from high to low Eliminates a series of spikes or glitches when a button is pressed and released Programming and Debugging www xilinx com 7 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Debugging in Vivado Tutorial Sine Wave Sequencer State Machine Captures and decodes input fro
48. Ctrl T ma Show Hierarchy Fo E Highight tighlight Ctrl M J GPIO_BUTTONS_IBUF Ctrl Shift M Figure 8 Adding Nets from the Netlist Tab 6 Next mark nets for debug in the Tcl console Mark nets sine 20 under the U_SINEGEN hierarchy for debug by executing the following Tcl command Seu property Mark debug true Get mets hier list sine FFI TIP In the Debug window you can see the unassigned nets you just selected In the Netlist window you can also see the green bug icon next to each scalar or bus which indicates that a net has the attribute mark debug true as shown the following two figures Programming and Debugging www xilinx com 18 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design Name his Unassigned Debug Nets 31 Sp GPIO_BUTTONS_db 2 e J GPIO_BUTTONS_db 0 e a GPIO_BUTTONS_db 1 GPIO_BUTTONS_dly 2 te _ amp GPIO_BUTTONS_dly 0 i PIO_BUTTONS_dly 1 J GPIO_BUTTONS_re 2 EE PIO_BUTTONS_re 0 ea GPIO_BUTTONS_re 1 H P U_SINEGEN sel 2 H P U_SINEGEN sine 20 al DONT_EAT GPIO_BUTTONS_IBUF 2 J GPIO_BUTTONS_IBUF O GPIO_ BUTTONS _IBUF 1 Debug Nets A i F at ae Tcl Console Messages Gl Log Reports 3 Design Runs 4 1 Driver Cell IBUF IBUF Figure 9 Newly Added Nets for Debug from the Synthesized
49. Driver Pin sine 8 sine 9 1 Schematic S44guggyyge Figure 47 Mark Additional Signals for Debug 3 In the Confirm Debug Net s dialog box click OK 4 You should be able to see all the nets that are marked for debug as shown in the following figure Name Debug Core Instance Debug Core Type Debug Port Clock Domain Driver Cell Driver Name Assigned Debug Nets Ge Unassigned Debug Nets 30 a GPIO_BUTTONS_c 2 TEU Multiple GPIO_BUTTONS_db 2 Fpa GPIO_BUTTONS_dly_1 2 Multiple fh GPIO_BUTTONS_re_i 2 Multiple Hm sine 20 HFa sineSel 2 Debug Nets Debug Cores Figure 48 Nets Added for Debug through the Synplify Pro Flow in Vivado IDE Programming and Debugging www xilinx com 49 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design Running the Set up Debug Wizard 5 Click the Set up Debug icon in the Debug window or select the Tools menu and select Set up Debug The Set up Debug wizard opens Name Assigned Debug Nets Unassigned Debug Nets 2 kal H GPIO_BUTTONS_c J GPIO_BUTTONS_db 2 i GPIO_BUTTONS_dly_1 D Messages Log Reports amp Design Runs Figure 49 Run the Set up Debug Wizard 6 Click through the wizard to create Vivado logic analyzer debug cores keeping the default settings Note In the Specify Nets to Debug dialog box ensure that all
50. E Lab 3 Using a VIO Core for Debugging a Design in Vivado 14 On the PROBE OUT Ports set Probe Width to 2 bits wide with an initial value of 0 in hex format F Customize IP VIO Virtual Input Output 3 0 ie Documentation 1 IP Location CJ Switch to Defaults _ Show disabled ports Component Name vio_0 To configure more than 64 probe ports use Vivado Tcl Console ik Initial Value in obe in0f3 0 Pre el hex PROBE_OUTO 2 1 256 0x0 Figure 25 Configure the PROBE_OUT Ports of the VIO Core 15 Click OK to generate the IP The Generate Output Products dialog box will appear Click Generate f Generate Output Products X The following output products will be generated Generate Options Generate Synthesized Checkpoint dcp Preview QA 4F vio_0 xci ga Instantiation Template H RTL Sources P Behavioral Simulation Figure 26 Generate Output Products for the VIO Core Programming and Debugging www xilinx com 33 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 3 Using a VIO Core for Debugging a Design in Vivado Output product generation should take less than a minute At this point you have finished customizing the VIO This core has already been instantiated in the top level design as shown in the following figure U_VIO vio_0 port map CLK gt clk PROBE INO gt DONI_EAT GPIO BUTTONS re 1 sineSel PROBE _OUTO 0
51. In the Add Configurable IP dialog box navigate to the src lab1l sine low directory Select XCI source file and click OK Verify that the files are added and Copy Sources into Project is selected Click Next 8 In the Add Constraints optional dialog box the provided XDC file sinegen demo kc705 xdec should automatically appear in the main window Click Next 9 In the Default Part dialog box specify the xc7k325tffg900 2 part for the KC705 platform You can also select Boards and then select Kintex 7 KC705 Evaluation Platform Click Next 10 Review the New Project Summary page Verify that the data appears as expected per the steps above and click Finish Note It could take a moment for the project to initialize Step 2 Synthesizing the Design 1 In the Project Manager click Project Settings as shown in the following figure Programming and Debugging www xilinx com 12 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design a a neg ian ae a AY mS re Pye ee eer ey aoe ae d orc etiist C Vivado Debua nproi netlist oro netlist xori Vivadc File Edit Flow Tools Window Layout View Help Ze a2 Rh Xx 3 DP YB 6 XE B 2 Default Layout Ker Flow Navigator Project Manager proj_netlist Qiks Sources iRise C m et BIE S ae e T EE oya mamaga Mixed sinegen_demo vhd 4 oF Pp Project Settings Configure
52. NX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design Introduction This simple tutorial shows how to do the following Create a Synplify Pro project for the wave generator design Mark nets for debug in the Synplify Pro constraints file as well as VHDL source files Synthesize the Synplify Pro project to create an EDIF netlist Create a Vivado project based on the Synplify Pro netlist Use the Vivado IDE to setup and debug the design from the synthesized design using Synplify Pro Version 2013 3 SP1 Step 1 Create a Synplify Pro Project 1 Launch Synplify Pro and select File gt New Set File Type to Project File Project as highlighted in the following figure In the New File Name box enter synplify_1 Click OK Bj New Y amp File Type Select a type i Verilog File l VHDL File Tcl Script Cancel Identify Design Constraint 4 Text File Xilinx Options File E FPGA Design Constraints 3 Analysis Design Constraints P Project File Project New File Name synplify_1 File Location Help C Vivado_Debug synopsys Full Path C Vivado_Debug synopsys synplify_1 prj Figure 31 Synplify Pro New Project Dialog Box Programming and Debugging www xilinx com 36 UG936 v2015 1 May 18 2015 Send Feedback 2 XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design 2 If you get a dialog
53. O0 f yay My Computer i debounce vhd R ndutta fsm vhd sinegen_demo vhd File name debounce vhd fsm vhd sinegen_demo vhd Files of type HDL Files vhd vhdl v sv vma VHDL Verilog lib v Files to add to project 3 file s selected Y Use relative paths Y Add files to Folders Folder Options Asrc Lab4 debounce vhd lt Add All src Lab4 fsm vhd src Lab4 sinegen_demo vhd Figure 34 Adding VHDL Source Files to the Synplify Pro Project Programming and Debugging www xilinx com 38 UG936 v2015 1 May 18 2015 Send Feedback XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design 6 In the same dialog box set Files of type to Constraints File This shows the synplify 1 sdc file Select the file and click Add as shown in the following figure Add Files to Project Look in J C Wiado_Debug isrqta ti OOO BE W My Computer synplify_1 sdc R ndutta File name synplify_1 sdc Files of type Constraint Files VHDL Verilog lib v Files to add to project 4 file s selected Y Use relative paths Y Add files to Folders Folder Options src Lab4 debounce vhd lt Add All src Lab4 fsm vhd src Lab4 sinegen_demo vhd src Lab4 synplify_l sdc ae Remove All gt Figure 35 Adding SDC Constraints File to the Synplify Pro Project Programming and Debugging www xilinx com 39 UG936 v2015
54. Run in the Design Runs tab right clicking and selecting Force Up to Date Synthesis Run Properties Ctril E E Delete Change Run Settings Save As Strategy Open Run Launch Runs Reset Runs Reset to Previous Step synth_design Force Up to Date Generate Bitstream Display Run Log Display Run Reports Display Run Messages Copy Run Create Runs Open Run Directory Export to Spreadsheet Figure 146 Forcing Synthesis Up To Date 32 In the Flow Navigator on the left side of the Vivado IDE click Generate Bitstream 33 Click Yes to implement the design 34 Wait until the Vivado status shows write_bitstream complete Programming and Debugging www xilinx com 125 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 35 In the Bitstream Generation Completed dialog box select Open Hardware Manager and click OK Bitstream Generation Completed x i Bitstream Generation successfully completed Next Open Implemented Design C View Reports 1 Open Hardware Manager Don t show this dialog again ox cone Figure 147 Open Hardware Manager Step 2 Program the KC705 Board and Interact with the JTAG to AXI Master Core 1 Connect your KC705 board s USB JTAG interface to a machine that has Vivado IDE and cable drivers installed on it and power up the board 2 The Hardware Manager window o
55. TISU TNT iLO Los TODT ESE Figure 136 Open IP Example Design Menu Item E Project Su Gel pig Ae T a Teea aE 31 search i EHS Design Sources 1 ae i n m z 7 z HFA ibert_7series_gt Mm lihar Tearianc Name HHE Constraints Source Node Properties Ctrl E Programming and Debugging UG936 v2015 1 May 18 2015 www xilinx com 115 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 16 In the Open IP Example Design dialog ensure that Overwrite existing example project is selected Click OK f Open IP Example Design X Oo Specify a location where the example project directory jtag_axi_0_example will be placed Location Put example project directory here C jtag_2_axi_tutorial jtag_2_axi_tutorial v Overwrite existing example project Cancel Figure 137 Open IP Example Design Dialog Box 17 Open the example jtag axi 0 v file and notice that the jtag_axi_O module is connected to an axi_bram_ctrl_O AXI BRAM block memory module 18 In the example_jtag_axi_0 v file add the following string to the beginning of the wire declaration for each axi_ signal from lines 72 108 mark debug Note Do not put mark debug on the axi ac1k signal since this might result in Vivado Synthesis adding a LUTI to the clock path which could possibly cause you to not meet timing Lines 72 108 should look like this mark debug wire 3120 ax1 ara
56. T_X0Y13 RX 8 000 Gbps 2 025E12 1 003E12 4 95E 1 2 Reset Link 6 MGT_XO0Y14 TX MGT_XOY14 RX 8 000 Gbps 026E1 9 611E11 4 744E 1 rl Figure 120 Links Window after Link Groups are Created The status of the links indicate an 8 0 Gbps line rate For more information about the different columns of the Links windows refer to Vivado Design Suite User Guide Programming and Debugging UG908 Change the GT properties of the rest of the transceivers as described above 12 Next create a 2D scan Click Create Scan in the Links window Name Link 2 MGT_X0Y9 TX MGT_XO0Y9 RX 8 000 Gbps Link 3 MGT_X0Y10 TX MGT_XOY10 8 000 Gbps Link 4 MGT_XO0Y11 TX MGT_XOY11 8 000 Gbps Link 5 MGT_X0Y12 TX MGT_XOY12 8 000 Gbps MGT_X0Y13 TX MGT_XOY13 8 000 Gbps MGT_X0Y14 TX MGT_X0Y14 8 000 Gbps CT wA CITY MrT WAWR oA Char Figure 121 Creating a 2D Scan for Link 1 The Create Scan dialog box opens In this dialog box you can change the various scan properties In this case leave everything to its default value and click OK For more information on the scan properties see Vivado Design Suite User Guide Programming and Debugging UG908 Programming and Debugging www xilinx com 101 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links g Create Scan Ex Set the description and other properties to create and o
57. V TXDIFFSWING 600 mV 0111 TXPOST 0 00 d8 00000 TXP RXTERM 100 mV TXDIFFSWING 600 mV 0111 TXPOST 0 00 dB 00000 TXP RXTERM 100 mV TXDIFFSWING 600 mV 0111 TXPOST 0 00 d8 00000 TXP RXTERM 100 mV TXDIFFSWING 600 mV 0111 TXPOST 4 08 d8 01111 TXP RXTERM 100 mV TXDIFFSWING 600 mV 0111 TXPOST 4 08 dB 01111 TX RXTERM 100 mV TXDIFFSWING 600 mV 0111 TXPOST 4 08 d8 01111 TXP RXTERM 100 mV TXDIFFSWING 600 mV 0111 TXPOST 12 96 dB 11111 TX RXTERM 100 mV TXDIFFSWING 600 mV 0111 TXPOST 12 96 dB 11111 TX RYXTERM 100 MI TXNIEESWING LAAN mv 0111 TXPNST 17 OF AR 111111 TX Figure 126 Sweep Test Results in the Scans Window Open Area Horzincr Horz Ranc a 0 500 UI 1 0 500 Ul 0 500 UI 0 500 UI 0 500 UT 0 500 UI 0 500 UI 0 500 Ul 0 500 Ul 0 500 UI 0 500 UI 0 500 UI 0 500 UI 0 500 UI 0 500 UI D o D w a o o w w o w wo w w o w w EIEE ED EER EA EER OEE S N SNAN HITE ae 0 500 UII 0 500 UI _ To see the results of any of the scans that have been performed highlight the scan right click and select Display Scan Plots Programming and Debugging Link Link Settings Scan Properties Run Sweep or Scan Write Scan Data fare Curnan 1 Cran a Apply Link Settings E Tcl Console Mess X Delete Figure 127 Displaying Scan Plots UG936 v2015 1 M
58. _hub dbg_hub_Cv arog H 4 jtag_axi_full_inst jtag_axi_0 a IF Integrator Figure 139 Debug Layout in the Vivado IDE Toolbar Programming and Debugging www xilinx com 118 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions b Select the Debug window near the bottom of the Vivado IDE amp jtag_axi_0_example c Vivado_Debug 2015 1 jtag_axi_0_example jtag_axi_0_example xpr Vivado 2015 1 l eg File Edit Flow Tools Window Layout View Help Q Search commands TeBe NARA AS PH A g O S XK LG E Debug dE A S Synthesis Complete Flow Navigator Synthesized Design xc7k325tffg900 2 active x a Netlist OL X i Schematic x example_jtag_axi_0 v x oo ae a oe re J 12 Cells 2X0 Ports 270 Nets 4 Project Manager E gt ers o e example_jtag_axi_0 Project Settings EG Nets 270 B Add Sources HH Leaf Cells 11 Q Language Templates E axi_bram_ctrl_inst axi_bram_ctrl_0 SF P Catalog 4E dbg_hub dbg_hub_Cv 4 jtag_axi_full_inst jtag_axi_0 4 IP Integrator amp Create Block Design BF Open Block Design amp Generate Block Design 4 Simulation 5 Simulation Settings iQ Run Simulation amp Sources B Netlist ti m 4 RTL Analysis Eropa a 5 Elaboration Settings ri pale hey R B Open Elaborated Design 4 Synthesis Synthesis Settings Run Synthesis 4 B Synthesized Design
59. ab update the following selections a For GTX Location QUAD_117 in the Protocol Selected column click the pull down menu and select Custom 1 8 Gbps This should automatically populate Refclk Selection to MGTREFCLKO 117 and TXUSRCLK Source to Channel 0 b For GTX Location QUAD_118 do the following i In the Protocol Selected column click the pull down menu and select Custom 1 8 Gbps il In the Refclk Selection column change the value to MGTREFCLKO 117 iii In the TXUSRCLK Source column change the value to Channel 0 Programming and Debugging www xilinx com 83 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE F Customize IP IBERT 7 Series GTX 3 0 Documentation 25 IP Location C3 Switch to Defaults Show disabled ports RXN_I 0 PRXP_I 7 0 TXN_O 7 0 GTREFCLKO_I 1 0 TXP_O 7 0 GTREFCLK1_I 1 0 RXOUTCLE_OF SYSCLK_I Lab 5 Using Vivado Serial Analyzer to Debug Serial Links a Component Name ibert_ series_gt_0 Protocol Definition Protocol Selection Clock Settings Summary Please select Protocol Quad combination GTX Location Protocol Selected Refclk Selection TXUSRCLK Source eT CT oS Tecra Figure 96 Setting the Protocol Selection on the IBERT Core 6 Click the Clock Settings tab and make the following changes for both QUAD_117 and QUAD_118 a Leave the Source column at its default value of External b Change the I O Standard colu
60. all the scans that have been done for the selected link CAUTION Since there are 81 scans to be done it could be a few minutes before all the scans are complete Programming and Debugging www xilinx com 104 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Sweep 1 Scan 1 E Sweep 1 Scan2 E Sweep 1 Scan 3 E Sweep 1 Scan 4 Sweep 1 Scan 5 E Sweep 1 Scan 6 E Sweep 1 Scan 7 E Sweep 1 Scans E Sweep 1 Scan 9 Link 0 Link 0 Link 0 Link 0 Link 0 Link 0 Link 0 Link 0 Link 0 Link 0 Sweep 1 Scan 10 Link 0 Sweep 1 Scan 11 Link 0 Sweep 1 Scan 12 tink 0 E Sweep 1 Scan 13 Unk 0 E Sweep 1 Scan 14 Link 0 E Sweep 1 Scan 15 Link 0 Sweep 1 Scan 16 Link 0 E Sween 1 Sran 17 link 0 HF TT l Lab 5 Using Vivado Serial Analyzer to Debug Serial Links RXTERM 100 mV TXDIFFSWING 250 mV 0000 TXPOST 0 00 dB 00000 TXP RXTERM 100 mV TXDIFFSWING 250 mV 0000 TXPOST 0 00 dB 00000 TXP RXTERM 100 mV TXDIFFSWING 250 mV 0000 TXPOST 4 08 dB 01111 TXP RXTERM 100 mV TXDIFFSWING 250 mV 0000 TXPOST 4 08 d8 01111 TXP RXTERM 100 mV TXDIFFSWING 250 mV 0000 TXPOST 4 08 dB 01111 TXP RXTERM 100 mV TXDIFFSWING 250 mV 0000 TXPOST 12 96 dB 11111 TX RXTERM 100 mV TXDIFFSWING 250 mV 0000 TXPOST 12 96 dB 11111 TX RXTERM 100 mV TXDIFFSWING 250 mV 0000 TXPOST 12 96 dB 11111 TX RXTERM 100 m
61. ate 500 l Hl b Figure 83 Dashboard Options Adding VIO Note The ILA dashboard now contains the VIO window as well Programming and Debugging www xilinx com 72 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware 18 Adjust the ILA Basic Trigger window and the VIO window so that they are side by side as shown below Settings hw_ila_1 oe Status hw_ila_1 Trigger Mode Settings amp Core status P Trigger mode BASIC_ONLY pb Idle Waiting for Trigger Capture status Post Trigger Full Capture Mode Settings Window 1 of 1 Window sample 0 of 1024 Total sample 0 of 1024 Idle Idle Idle Capture mode AL Number of windows Press the f button to add probes General Settings button to add prob Refresh rate 500 Press the f button to add probes Trigger Setup hw_ila_i Capture Setup hw_ila_1 sineSel 1 0 Or oY Fa sine 19 0 A Figure 84 ILA Basic Trigger Window and VIO Window Adjustment 19 In the VIO Probes window select the green button to put all the probes into the VIO core tab Note the initial values of all the probes Programming and Debugging www xilinx com UG936 v2015 1 May 18 2015 Send Feedback 73 amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware Status hw_ila_i en em s amp Core status e dle o Waiting for Trigger Po
62. ay 18 2015 www xilinx com Delete Send Feedback 105 XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links The Scan Plots window opens showing the details of the scan performed Unit Interval i y ay a a Sl qh ct f 3 gt Summary Metrics Settings Hame SCAN_O Open area 8128 Link settings RXTERM 100 mV TXDIFFSWING 250 mV 0000 TXPOST 0 00 dB 00000 TXPRE 0 00 dB 00000 Description Sweep 1 Scand Horizontal increment 8 Started 2013 O0ct 07 15 10 33 Horizontal range 0 500 Ul to 0 500 UI Ended 2013 0ct 07 15 11 00 Vertical increment a Vertical range 100 Figure 128 Analyzing the Results of Individual Scans Programming and Debugging www xilinx com 106 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AX Transactions Introduction The purpose of this tutorial is to provide a very quick and easy to reproduce introduction to inserting an ILA core into the JTAG to AXI Master IP core example design and using the ILA s advanced trigger and capture capabilities What is the JTAG to AXI Master IP core The LogiCORE IP JTAG AXI core is a customizable core that can generate AXI transactions and drive AXI signals internal to FPGA at run time This supports all memory mapped AXI interfaces except AXI4 Stream and Lite protocol and can be selected using a
63. click the Select Clock Domain s4 m p Ta axi_arid gi button or right click and choose the Select Clock Domain command a T2 axi_arready 7 x T2 axi_arvalid To remove nets select the nets and click the Remove Nets button or press the Delete key k J axi_awid J amp axi_awready 2 J axi_awvalid 3 J amp axi_bid ge amp axi_brea utn rome v v a T axi_bvalid acik FDRE v v s ai awaddr 1 J2 axi_rid aclk FDRE v V a s_ axi_awburst 1 Find Nets to Add Nets to debug 202 p lt 7 sdbm_v1 Figure 142 Missing Clock Domain Dialog Box 25 In the resulting pop up click Assign All Clock Domains Programming and Debugging www xilinx com 121 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 26 In the resulting pop up select the aclk clock net then click OK e T The list below is GLOBAL_CLOCK type of clock net If you want to see the list of different type of clock net s please change the a combobox selection ck Domain There are 72 net s that do not have a clock domain selection Please select a clock 72 nets BC net from the list below to apply to all 72 net s If you want to select different clock 4 domains foreach net click Cancel and follow the instructions in the wizard Jain All Chock Dannin L r f 34 Q amp GLOBAL_CLOCK v Search hierarchical Display unique nets ee sains cd ty Z Di
64. d take several button presses to detect it you will now set up the Vivado logic analyzer tool to Repetitive Trigger Run Mode This setting makes it easier to repeat the button presses and look for the event in the Waveform viewer 1 Open the Debug Probes window if not already open by selecting Window gt Debug Probes from the menu 2 In the ILA Properties window scroll down to the link marked To view editable ILA Properties Open ILA Dashboard and set the following Trigger Mode to BASIC_ONLY b Capture Mode to BASIC c Window Data Depth to 1024 o d Trigger position to 512 e Press the button in the Trigger setup window and add probe GPIO_BUTTONS_IBUF_1 Change the Compare Value field to RX by clicking in the Compare Value column and typing the value RX in the Value field as shown in the following figure Programming and Debugging www xilinx com 63 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware hw_ila_1 x Ew x Settings hw_ila_1 sa mn a Status hw_ila_1 sa lina Trigger Mode Settings amp Core status Trigger mode BASIC_ONLY v DI Idle Waiting for Trigger Post Trigger Full F Capture status Capture Mode Settings Window 1 of 1 Window sample 0 of 1024 Total sample 0 of 1024 Idle Idle Idle Capture mode BASIC z Number of windows 1 Window data depth 1024 v 1 1024 Trigger Setup hw_ila_1 O X Capture Setup h
65. ddr mark debug 7 wire 1 0 axi arbursc gt mark debug wite 3 0 axa arcache mark debug wire 0 0 ax1 arid mark debug wire 7 0 ax1i_arlen mark debug wire axi_arlock mark debug wire 2 0 ax1_arprot mark debug wire 3 0 ax1_arqos mark debug wire axl already mark debug wire 210 axt argiz mark debug wire axi arvalid mark debug wire 31 0 axi_ awaddr mark debug wire 1 0 axi_awburst mark debug wire 3 0 axi_awcache mark debug wire 0 0 axi_awid mark debug wire 7 0 ax1i_awlen mark debug wire 7 0 ax1i_awlen mark debug wire axi_awlock mark debug wire 2 0 ax1_awprot mark debug wire 3 0 ax1_awqos 7 mark debug wire axi awready Programming and Debugging www xilinx com 116 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE mark debug mark debug mark debug mark debug mark debug mark debug mark debug mark debug mark debug mark debug mark debug mark debug mark debug mark debug mark debug mark debug mark debug FF FF FF FF F FF F F HF OF FF FF FF FF F FF F F HF OF F xo Se Noe Ne NA NA NSA NSA NSA NSA NSA NA NA NA NA NA NA wire wire wire wire wire wire wire wire wire wire wire wire wire wire wire wire wire 19 Save changes to example Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions
66. e AS IS and with all faults Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS EXPRESS IMPLIED OR STATUTORY INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY NON INFRINGEMENT OR FITNESS FOR ANY PARTICULAR PURPOSE and 2 Xilinx shall not be liable whether in contract or tort including negligence or under any other theory of liability for any loss or damage of any kind or nature related to arising under or in connection with the Materials including your use of the Materials including for any direct indirect special incidental or consequential loss or damage including loss of data profits goodwill or any type of loss or damage suffered as a result of any action brought by a third party even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications You may not reproduce modify distribute or publicly display the Materials without prior written consent Certain products are subject to the terms and conditions of Xilinx s limited warranty please refer to Xilinx s Terms of Sale which can be viewed at http www xilinx com legal htm tos IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx Xilinx products are not designed or intended to be fail safe or for use in any applicat
67. e Activity 12 Click Run Trigger Immediate to trigger and capture data immediately as shown in shown in the following figure a z eE m Name z EES Run Trigger Immediate localhost ormected __ fe xilinx_tcf Digilent 21020332796 Open hw_ila_1 Idle Figure 61 Run Trigger Immediate Button Programming and Debugging www xilinx com 58 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware 13 In the Waveform window verify that there is activity on the 20 bit sine signal as shown in the following figure i U_SINEGEN sine 19 0 M GPIO_BUTTONS_IBUF 0 0 M GPIO_BUTTONS_IBUF_1 1 1 Figure 62 Output Sine Wave Displayed in Digital Format Displaying the Sine Wave 14 Right click U_SINEGEN sine 19 0 signals and select Waveform Style gt Analog as shown in the following figure 9 TIP The waveform does not look like a sine wave This is because you must change the radix setting from Hex to Signed Decimal as described in the following subsection MA GPIO_BUTTONS_IBUF 0 0 jM GPIO_BUTTONS_IBUF_1 1 1 Figure 63 Output Sine Wave Displayed in Analog Format High Frequency 1 Programming and Debugging www xilinx com 59 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware 15 Right click U_SINEGEN sine 19 0 signals and se
68. e Debug Connections To create a project use the New Project wizard to name the project add RTL source files and constraints and specify the target device L 2 S o pr A Invoke the Vivado IDE In the Getting Started screen click Create New Project to start the New Project wizard Click Next In the Project Name page name the new project jtag_2_axi_tutorial and provide the project location C jtag 2 axi tutorial Ensure that Create Project Subdirectory is selected Click Next In the Project Type page specify the Type of Project to create as RTL Project Click Next In the Add Sources page click Next In the Add Existing IP page click Next In the Add Constraints page click Next Programming and Debugging www xilinx com 108 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 8 In the Default Part page choose Boards and choose the Kintex 7 KC705 Evaluation Platform Click Next g New Project Default Part Choose a default Xilinx part or board for your project This can be changed later Specify Filter Parts Board Vendor All Library All Name All Version Latest Reset All Filters Search Q Bier Board Board Board Board Part Vendor Library Name Version MicroZed Board em avnet com zynq microzed xc7z010clg a ZedBoard Zynq Evaluation and Development Kit em avnet com zynq zed d xc7z020clg
69. ectrical contact just as you press it To eliminate this signal bounce a de bouncer circuit is required 5 Enable the de bouncer circuit by setting DIP switch position on the KC705 board labeled De bounce Enable in Figure 1 KC705 Board Showing Key Components to the ON or UP position 6 Enable the Auto Retrigger mode on the ILA debug core and click RunTrigger on the ILA core and o Ensure that you no longer see multiple transitions on the GPIO_BUTTON_re 1 signal on a single press of the Sine Wave Sequencer button o Verify that the state machine is working correctly by ensuring that the sineSel signal transitions from 00 to 01 to 10 to 11 and back to 00 with each successive button press Programming and Debugging www xilinx com 66 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware Verifying the VIO Core Activity Only applicable to Lab 3 1 From the Program and Debug section in Flow Navigator click Open Hardware Manager 4 Program and Debug aa EV synth_1 Bitstream Settings vV impl_t Generate Bitstream a Open Hardware Manager N I4 Open Hardware Manager Open the hardware program and debug manager Figure 74 Open Hardware Manager 2 The Hardware Manager window opens Click Open a new hardware target Hardware Manager unconnected G No hardware target is open Open target Hardware E Auto Connect S Dl Rece
70. ediate i Stop Trigger Hardware Device Properti Fa m op Py Enable Auto Re trigger xc7k325t_0 Refresh Device Add Configuration Memory Device Name xc7k3 i Boot from Configuration Memory Device Part xc7k3 Program BBR Key ID code 3365 9 ey Clear BBR Key IR lenath 6 z T a p T p Program eFUSE Registers General Properties Export to Spreadsheet Figure 160 Run Trigger Programming and Debugging www xilinx com UG936 v2015 1 May 18 2015 Send Feedback 136 amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 7 Inthe Trigger Capture Status window note that the ILA core is waiting for the trigger to occur and that the trigger state machine is in the wait_for_a_valid state Note that the pre trigger capture of 512 samples has completed successfully Status hw_ila_1 amp Core status Idle Pre Trigger Waiting for Trigger Post Trigger Full E Trigger State Machine Pi Flag 0 Flag 1 Flag 2 Flag 3 Trigger state wait_for_arvalid 0 Capture status Window 1 of 1 Window sample 512 of 1024 Total sample 512 of 1024 8 p rl I Figure 161 Trigger Capture Status Window 8 In the Tcl console run the read transaction that you set up in the previous section of this tutorial run hw axi rt Note The ILA core has triggered and the trigger mark is on the sample where the axi rlast signal
71. elect Hardware Target 5 Leave these settings at their default values Click Next Programming and Debugging www xilinx com 54 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware 6 In the Open Hardware Target Summary page click Finish as shown in the following figure 3 Open New Hardware Target Open Hardware Target Summary Hardware Server Settings o Server localhost 3121 Target Settings o Target xilinx_tcf Xilinx Port_ 0007 Hub_ 0004 o Frequency 6000000 VIVADOS To connect to the hardware described above click Finish Figure 54 Hardware Target Summary 7 Wait for the connection to the hardware to complete The dialog in following figure appears while hardware is connecting g Open Hardware Target W Opening target Figure 55 Open Hardware Target After the connection to the hardware target is made the dialog shown in the following figure appears Note The Hardware tab in the Debug view shows the hardware target and XC7K325T device detected in the JTAG chain Programming and Debugging www xilinx com 55 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware Name Status E E localhost 1 Connected B We xilinx_tcf Digilent 210203327962A 1 Open E xc7k325t_O 1 active Not programmed i XADC System Monitor
72. erties en ee Es B u_ila_o gt Name u_ila_0 Reference name _u_ila_0_CV Type Black Box Debug core type _labtools_ila_v5 Number of cell pins 257 x Properties Debug Core Options Ded gt E Debug W Name E E dbg_hub labtools_xsdbm_v1 gt iE jtag_axi_full_inst labtools_xsdbslavelib_v2 if HD probed 2 H B probel 32 HD probe2 4 HD probe3 8 HD probed 3 H E meahoas 2 Debug Cores Debug Nets We Gy the 2 oe dE PIXXX BIER OOW ALI F Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions Schematic x example_jtag_axi_0 v x 12 Cells 2 1 0 Ports 270 Nets k dbg _hub d _jpat0 a036 Sopot 0 16 3 ipati of0 36 g opati 40 16 dbg_hub_cv Driver Cell _ amp Tcl Console e Messages E Log 3 Reports E Design Runs _ amp Debug Figure 145 ILA Core Inserted into the Design 30 Save the constraints by clicking Save Programming and Debugging UG936 v2015 1 May 18 2015 www xilinx com Send Feedback 124 amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 31 The insertion of debug cores and changing of properties on those debug cores adds constraints to your target XDC constraint file This modification of your target constraints file currently sets your synthesis out of date You can force the design up to date by selecting the
73. ew Hardware Target wizard opens click Next gt Open New Hardware Target Open Hardware Target This wizard will guide you through connecting to a hardware target To connect to a remote hardware target provide the host name and IP port of the remote machine on which the instance of a Vivado Hardware Server is running VIVADO To continue click Next Figure 106 Open New Hardware Target Wizard Programming and Debugging www xilinx com 91 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links 2 Inthe Connect to field choose Local server Click Next Open New Hardware Target Hardware Server Settings Select local or remote hardware server then configure the host name and port settings Use Local server if the target is attached to the local machine otherwise use Remote server Connect to Local server target is on local machine Click Next to launch and or connect to the hw_server port 3121 application on the local machine Figure 107 Vivado CSE Server Name Page Programming and Debugging www xilinx com 92 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links 3 In the Select Hardware Target page click Next There is only one target board in this case to connect to so the default is selected Open New Hardware Ta
74. gative Slack TNS 0 000 ns Total Hold Slack THS 0 000 ns Total Pulse Width Negative Slack TPWS 0 000 ns H Intra Clock Paths Number of Failing Endpoints 0 Number of Failing Endpoints 0 Number of Failing Endpoints 0 HInter Clock Paths Total Number of Endpoints 12287 Total Number of Endpoints 12287 Total Number of Endpoints 6722 Other Path Groups User Ignored Paths All user specified timing constraints are met Unconstrained Paths Timing Summary impl_1 X Timing Summary timing_1 X Figure 16 View the Timing Summary Report Proceed to Using Vivado Logic Analyzer to Debug Hardware to complete the rest of the steps for debugging the design Programming and Debugging www xilinx com 24 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 2 Using the HDL Instantiation Method for Debugging a Design in Vivado Introduction The HDL Instantiation method is one of the two methods supported in Vivado Debug Probing For this flow you will generate an ILA IP using the Vivado IP Catalog and instantiate the core in a design manually as you would with any other IP Step 1 Creating a Project with the Vivado New Project Wizard To create a project use the New Project wizard to name the project to add RTL source files and constraints and to specify the target device 1 Invoke the Vivado IDE 2 In the Getting Started page click Create New Project to start the New Project wizard Cl
75. he target device 1 Invoke Vivado IDE 2 In the Getting Started page click Create New Project to start the New Project wizard Click Next 3 In the Project Name page name the new project proj_hdl_vio and provide the project location C Vivado Debug Ensure that Create project subdirectory is selected Click Next 4 In the Project Type page specify the Type of Project to create as RTL Project Click Next 5 Inthe Add Sources page a Set Target Language to VHDL b Click Add Files c In the Add Source Files dialog box navigate to the src Lab3 directory d Select all VHD source files and click OK e Verify that the files are added and Copy Sources into Project is selected Click Next 6 In the Add Existing IP optional page a Click the Add Files b In the Add Configurable IP dialog box navigate to the src lab1 sine high directory c Select all XCI source files and click OK d In the Add Configurable IP dialog box navigate to the src lab1 sine mid directory e Select all XCI source files and click OK f In the Add Configurable IP dialog box navigate to the src lab1 sine low directory g Select all XCI source files and click OK h In the Add Configurable IP dialog box navigate to the src labl ila 0 directory Programming and Debugging www xilinx com 30 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 3 Using a VIO Core for Debugging a Design in Vivado i Select all XCI s
76. hesis Tool and Vivado for Debugging a Design 12 In the Select Top Module dialog box select sinegen_demo then click OK Select Top Module xE J Select a top module from the list Possible top modules dds_compiler_v6_0_xst__parameterized3 dds_compiler_v6_0_xst dds_compiler_v6_0_xst__parameterized1 sinegen sinegen_demo Co Gana Figure 45 Select the Top Level Module 13 Click OK in the Specify Top Module dialog box after ensuring that the top level module is correct f Specify Top Module Oo Specify the top module name of your design Options Top module name sinegen_demo Cancel Figure 46 Specify sinegen_demo as the Top Level Module Step 5 Add more Debug Nets to the Project 1 In Vivado IDE in the Flow Navigator select Open Synthesized Design from the Netlist Analysis folder 2 Select the Netlist tab in the Netlist window to expand Nets Select the following nets for debugging Programming and Debugging www xilinx com 48 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design e GPIO BUTTONS c 2 e sine 20 e sineSel 2 After selecting all the nets mentioned above click Mark Debug Synthesized Design xc7k325tffg900 2 active HFa GPIO_BUTTONS_re_1 2 IF GPIO_BUTTONS_re_5 2 H LEDS_n 4 Sem sine 20 Bus Net Properties Ctri E eae 7 aX Select
77. hy J Close Project synplify_1 rev_1 Xilinx Kintex7 XC7K oa synplify_ 1 C Vivado_ Debu E Add File 3P Lab4 amp Change File 5 VHDL Add Implementation i K Logic Constraints SDC Implementation Optipas Ai i 2 Implementation Optiras rev 1 BR Add P amp R Implementation Figure 37 Opening Implementation Options in Synplify Pro 9 This brings up the Implementation Options dialog box as shown in the following figure In the Device tab set Technology to Xilinx Kintex7 Part to XC7K325T Package to FFG900 and Speed to 2 Leave all the other options at their default values Click OK Programming and Debugging www xilinx com 41 UG936 v2015 1 May 18 2015 Send Feedback XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design BP implementation Options synplify_1 rev_1 2 amp Device Options Constraints Implementation Results Timing Report __ High Reliability VHD 4 gt Implementations Technology Part Package Speed revi Xilinx Kintex7 of XC7K325T M FFG900 z 2 z Device Mapping Options Option Value Fanout Guide 10000 Disable I O Insertion Disable Sequential Optimizations Update Compile Point Timing Data Click on an option for description System Designer Board File SYNOPSYS Figure 38 Specifying Implementation Options in Synplify Pro 10 You need to preserve the net names that
78. ick Next 3 In the Project Name page name the new project proj_hdl and provide the project location C Vivado Debug Ensure that Create Project Subdirectory is selected Click Next 4 In the Project Type page specify the Type of Project to create as RTL Project Click Next 5 In the Add Sources page a Set Target Language to VHDL b Click Add Files c In the Add Source Files dialog box navigate to the src Lab2 directory d Select all VHD source files and click OK e Verify that the files are added and Copy Sources into Project is selected Click Next 6 6 In the Add Existing IP optional page a Click Add Files b In the Add Configurable IP dialog box navigate to the src labl sine high directory c Select XCI source file and click OK Programming and Debugging www xilinx com 25 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX 7 8 9 ALL PROGRAMMABLE Lab 2 Using the HDL Instantiation Method for Debugging a Design in Vivado d In the Add Configurable IP dialog box navigate to the src lab1 sine mid directory e Select XCI source file and click OK h In the Add Configurable IP dialog box navigate to the src lab1l sine low directory g Select XCI source file and click OK h In the Add Configurable IP dialog box navigate to the src lab1 ila 0 directory i Select XCI source file and click OK j Verify that the files are added and Copy Sources into Project is selected Clic
79. igure Click Next Open New Hardware Target Select a hardware target from the list of available targets then set the appropriate JTAG clock TCK frequency If you do not see the expected devices decrease the frequency or select a different target Hardware Targets Type Port Name JTAG Clock Frequency xilinx_tcf xiliny Port_ 0007 Hub_ 0004 6000000 Hardware Devices for unknown devices specify the Instruction Register IR length Name ID Code IR Length xc7k325t_0 33651093 6 sd Hardware server localhost 3121 Figure 150 Select Hardware Target 5 Leave these settings at their default values as shown Click Next Programming and Debugging www xilinx com 128 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 6 In the Open Hardware Target Summary page click Finish as shown in the following figure E Open New Hardware Target X Open Hardware Target Summary Hardware Server Settings o Server localhost 3121 Target Settings o Target xilinx_tcf Xilinx Port_ 0007 Hub_ 0004 o Frequency 6000000 VIVADO To connect to the hardware described above click Finish Figure 151 Open Hardware Summary 7 Wait for the connection to the hardware to complete The dialog in the following figure appears while hardware is connecting gi Open Hardware Target W Opening target Figure 15
80. include the VIO window This allows you to toggle the VIO output drivers and observe the impact on the ILA waveform window all in one dashboard Slide out the Dashboard Options window Programming and Debugging www xilinx com 70 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware iw Si hw vios X Settings hw_ila_1 Trigger Mode Settings Trigger mode BASIC_ONLY Capture mode ALWAYS Number of windows General Settings Refresh rate 500 Figure 82 Invoking Dashboard Options 17 Add the VIO window to the ILA dashboard Programming and Debugging www xilinx com UG936 v2015 1 May 18 2015 Send Feedback 71 amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware hw_ila_1l xX hw_vios x Dashboard Options Settings hw_ila_1 O X Status hw_ila_1 n Oo amp ob Trigger Mode Settings Core status EHE xc7k325t_0 DI F hw ila 1 1A Trigger mode BASIC_ONLY Idle waiting for Trigger Post Trigger Full iW Status m Capture status v Settings i j g Capture Mode Settings Window 1 of 1 Window sample 0 of 1024 Total sample 0 of 1024 i Trigger Setup Idle Idle Idle V Capture Setup Capture mode AL v Waveform Number of windows 1 7 hw_vio_1 VIO XADC System Monitor Window data depth 10 Trigger position in window 0 General Settings Refresh r
81. ine Figure 158 Setting Trigger Mode to ADVANCED and Trigger Position to 512 in the ILA Dashboard Programming and Debugging UG936 v2015 1 May 18 2015 www xilinx com 134 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 4 In the New Trigger State Machine File dialog box set the name of the state machine script to txns tsm New Trigger State Machine File Save in jtag_2_axi_tutorial 98 pADX l jtag_2_axi_tutorial Recent Directories C jtag_2_axi_tutorial File Preview ia Select a file to preview Desktop d My Documents Computer File name txns ci Network Files of type Trigger State Machine Files tsm Figure 159 Creating a New Trigger State Machine Script 5 A basic template of the trigger state machine script is displayed in the Trigger State Machine gadget Expand the trigger state machine gadget in the ILA dashboard Copy the script below after line 17 of the state machine script and save the file The wait for arvalid state is used to detect the start of the read address phase of the AXI transaction which t Le indicated by the axi arvealid Signal equal to 1 it state wait for arvalid if ax ervalid 1 51 then goto Walt for rready else goto wait for arvalid endif t Ine Wait for rready State is Used to detect the start of the read data phase of the AXI transactio
82. ing a Project with the Vivado New Project Wizard To create a project use the New Project wizard to name the project to add RTL source files and constraints and to specify the target device 1 Invoke the Vivado IDE 2 In the Getting Started screen click Create New Project to start the New Project wizard Click Next 3 In the Project Name screen name the new project proj_netlist and provide the project location C Vivado Debug Ensure that Create Project Subdirectory is selected and click Next 4 In the Project Type screen specify the Type of Project to create as RTL Project Click Next 5 In the Add Sources screen a Set Target Language to VHDL b Click the Add Files button c In the Add Source Files dialog box navigate to the src Labl1 directory d Select all VHD source files and click OK e Verify that the files are added and Copy Sources into Project is selected Click Next Programming and Debugging www xilinx com 11 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design 7 In the Add Existing IP optional dialog box a b C g h Click the Add Files button In the Add Configurable IP dialog box navigate to the src lab1 sine high directory Select XCI source file and click OK In the Add Configurable IP dialog box navigate to the src lab1 sine mid directory Select XCI source file and click OK
83. ing www xilinx com 23 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design Step 4 Implementing and Generating Bitstream 1 Click Generate Bitstream from the Program and Debug drop down list in the Flow Navigator 4 Program and Debug Bitstream Settings Generate Bitstrear a Open Hardwa Generate Bitstream Launch iMPAqd Generate a programming file after implementation N Figure 15 Implement Design and Generate Bitstream 2 In the Save Project dialog box click Save This applies the mark_debug attributes on the newly marked nets You can see those constraints by inspecting the sinegen demo kc705 xdc file 3 When the No Implementation Results Available dialog box pops up click Yes 4 When the bitstream generation completes the Bitstream Generation Completed dialog box pops up Click OK 5 In the dialog box asking to close synthesized design before opening implemented design Click Yes 6 In the Implementation is Out of date dialog box click Yes 7 Examine the Timing Summary report to ensure that all the specified timing constraints are met SUE E 7 eS 4 Design Timing Summary General Information gt Timer Settings Setup Hold Pulse Width Desig an Timing Timing Summary Worst Negative Slack WNS 0 702 ns Worst Hold Slack WHS 0 048 ns Worst Pulse Width Slack WPWS 1 732 ns Clock S 4 eee Tening 2 i Total Ne
84. ion requiring fail safe performance you assume sole risk and liability for use of Xilinx products in such critical applications please refer to Xilinx s Terms of Sale which can be viewed at http www xilinx com legal htm tos Copyright 2015 Xilinx Inc Xilinx the Xilinx logo Artix ISE Kintex Spartan Virtex Zynq and other designated brands included herein are trademarks of Xilinx in the United States and other countries All other trademarks are the property of their respective owners Programming and Debugging www xilinx com 139 UG936 v2015 1 May 18 2015 Send Feedback
85. is may not preserve the signals due to netlist optimization involving absorption or merging of design structures e Usea Tcl prompt to set the mark_debug attribute on a synthesized netlist Set Property mark debug true ost mers fier last bine FI This applies the MARK_DEBUG on the current open netlist This method is flexible since you can turn MARK_DEBUG on and off by modifying the Tcl command In addition this method does not require HDL source modification However there may be situations where synthesis does not preserve the signals due to netlist optimization involving absorption or merging of design structures In the following steps you learn how to add debug nets to HDL files and the synthesized design using Vivado IDE TIP Before proceeding make sure that the Flow Navigator on the left panel is enabled Use Ctrl Q to toggle it off and on 1 In the Flow Navigator under the Synthesis drop down list click Open Synthesized Design as shown in the following figure Properties 4 Synthesis 7 35 Synthesis Settings gt Run Synthesis E Open Synthesized mone Figure 4 Open Synthesized Design Programming and Debugging www xilinx com 15 UG936 v2015 1 May 18 2015 Send Feedback XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design 2 In the Window menu select Layout gt Debug When the Debug window opens Click the window if it is not already selected 3
86. is on the local machine in the Connect to field Open New Hardware Target Select local or remote hardware server then configure the host name and port settings Use Local server if the target is attached to the local machine otherwise use Remote server Connect to Local server target is on local machine Click Next to launch and or connect to the hw_server port 3121 application on the local machine Figure 52 Hardware Server Settings Programming and Debugging www xilinx com 53 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware Note Depending on your connection speed this may take about 10 to 15 seconds 4 If there is more than one target connected you will see multiple entries in the Select Hardware Target page In this tutorial there is only one target as shown in the following figure Click Next Open New Hardware Target Select a hardware target from the list of available targets then set the appropriate JTAG clock TCK frequency If you do not see the expected devices decrease the frequency or select a different target Hardware Targets Type Port Name JTAG Clock Frequency xilinx_tcf xiliny Port_ 0007 Hub_ 0004 6000000 Hardware Devices for unknown devices specify the Instruction Register IR length Name ID Code IR Length xc7k325t_0 33651093 j6 Hardware server localhost 3121 Figure 53 S
87. k Next In the Add Constraints optional page the provided XDC file sinegen demo kc705 xdc should automatically appear in the main window Click Next In the Default Part page specify the xc7k325tffg900 2 part for the KC705 platform You can also select Boards and then select Kintex 7 KC705 Evaluation Platform Click Next Review the New Project Summary page Verify that the data appears as expected per the steps above Click Finish 10 In the Sources window in Vivado IDE expand sinegen_demo_inst to see the source files for this lab Note that tla_O core has been added to the project x fo A BE H Design Sources 1 i sinegen_demo_inst hdl_inst lem U_DEBOUNCE_0 debounce Mixed debounce amp U_DEBOUNCE_1 debounce Mixed debounc U_SINEGEN sinegen kintex sinegen i PG TSm vna wh u u A H Constraints 1 Simulation Sources 1 4 il Hierarchy IP Sources Libraries Compile Order Figure 17 ILA Instantiation in HDL Double click the sinegen_demo_inst vhd file to open it and inspect the instantiation and port mapping of the ILA core in the HDL code Programming and Debugging www xilinx com 26 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 2 Using the HDL Instantiation Method for Debugging a Design in Vivado U_ILA ila_o port map CLK gt clk PROBEO gt sineSel PROBE gt sine PROBE2 gt GPIO BUTTONS db
88. lect Kintex 7 KC705 Evaluation Platform and the right version number for your hardware Click Next Under New Project Summary ensure that all the settings are correct and click Finish 10 In the Sources window select sinegen_demo edf and select Specify Top Module Programming and Debugging www xilinx com 46 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design Project Manager proj_synplify Qazesie2ea kh 6 Design Sources 5 EDF 5 amp F dds_compiler_v6_0_viv__parameterized1 edn top 4A dds_compiler_v6_0_viv edn e sinegen edn a stasinegen_d A dds_comp Source File Properties Ctrl E E Constraints 1 i Open File Alt 0 constrs_1 1 o sinegen_d Replace File Simulation Only S sim_1 Alt I Libraries Compile Or Remove File from Project Delete Source File Properties e gt SiR sinegen_demo edf Disable File Alt Minus Figure 43 Specifying the Top Level Module 11 In the Specify Top Module dialog box click Browse Specify Top Module i Specify the top module name of your design Options Top module name s_compiler_v6_0_viv__parameterized1 Figure 44 Browse to the Top Module Programming and Debugging www xilinx com 47 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synt
89. lect Radix gt Signed Decimal You should now be able to see the high frequency sine wave as shown in the following figure instead of the square wave M4 GPIO_BUTTONS_IBUF 0 0 Mi GPIO_BUTTONS_IBUF_1 1 1 Figure 64 Output Sine Wave Displayed in Analog Format High Frequency 2 Correcting Display of the Sine Wave To view the mid and low frequency output sine waves perform the following steps 16 Cycle the sine wave sequential circuit by pressing the GPIO_SW_E push button as shown in the following figure Figure 65 Sine Wave Sequencer Push Button Programming and Debugging www xilinx com 60 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware 17 Click Run Trigger Immediately again to see the new sine selected sine wave You should see the mid frequency as shown in the following figure Notice that the sel signal also changed from 0 to 1 as expected Figure 66 Output Sine Wave Displayed in Analog Format Mid Frequency 18 Repeat step 17 and 18 to view other sine wave outputs Figure 67 Output Sine Wave Displayed in Analog Format Low Frequency Programming and Debugging www xilinx com 61 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware E a U_SINEGEN sine 19 0 E GPO BUTTONS _IBUF O 0 Mi GPIO_BUTTONS_IBUF_1 1 1 Figure 6
90. lue of the push_button_vio output driver from 0 to 1 to 0 by clicking on the logic displayed under the Value column You will notice the sineSel LEDs changed accordingly 0 1 2 3 0 etc b Click Run Trigger for hw_ila_1 to capture and display the selected sine wave signal from the previous step Programming and Debugging www xilinx com 78 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links Introduction The Serial I O analyzer is used to interact with IBERT debug IP cores contained in a design It is used to debug and verify issues in high speed serial I O links The Serial I O Analyzer has several benefits as listed below e Tight integration with Vivado IDE e Ability to script during netlist customization generation and serial hardware debug e Common interface with the Vivado Integrated Logic Analyzer The customizable LogiCORE IP Integrated Bit Error Ratio Tester IBERT core for 7 series FPGA GTX transceivers is designed for evaluating and monitoring the GTX transceivers This core includes pattern generators and checkers that are implemented in FPGA logic and provides access to ports and the dynamic reconfiguration port attributes of the GTX transceivers Communication logic is also included to allow the design to be run time accessible through JTAG In the course of this tutorial you e Create customize and genera
91. m the two push buttons Provides sine wave selection and indicator circuits sequencing among 00 01 10 and 11 zero to three LED Displays GPIO_LED_O and GPIO_LED_1 display selection status from the state machine outputs each of which represents a different sine wave frequency high medium and low Lab5 includes e AnIBERT core e A top level wrapper that instantiates the IBERT core Board Support and Pinout Information Table 1 Pinout Information for the KC705 Board enone rtoton oesie OOOO GPIO BUTTONS 1 Sine Wave Sequencer Design Files 1 In your C drive create a folder called Vivado Debug 2 Find the tutorial source files at the following location https secure xilinx com webreg clickthrough do cid 385007 CAUTION The tutorial and design files may be updated or modified between software releases You can download the latest version of the material from the Xilinx website 3 Unzip the tutorial source file to the Vivado Debug folder There are five labs that use different methodologies for debugging your design Select the appropriate lab and follow the steps to complete them Programming and Debugging www xilinx com 8 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Debugging in Vivado Tutorial Lab 1 This lab walks you through the steps of marking nets for debug in HDL as well as the post synthesis netlist Netlist Insertion Method Following are the required files
92. mn to DIFF SSTL15 c Change the P Package Pin to AD12 d Change the N Package Pin to AD11 e Leave the Frequency MHz at its default value of 200 00 Programming and Debugging UG936 v2015 1 May 18 2015 www xilinx com Send Feedback 84 amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links F Customize IP IBERT 7 Series GTX 3 0 Documentation IF Location Switch to Defaults Show disabled ports Component Name ibert_7series_gb lt _0 Protocol Definition Protocol Selection Clock Settings Summary RXOUTCLE Probe Add RXOUTCLK Probes Clock Type Source 1 0 Standard P Package Pin N Package Pin Frequency MHz System Clock DIFF SSTL15 TAD ADI 200 00 System Clock Termination Settings GTREFCLKO_I 1 0 TXP_O 7 0 Enable DIFF Term GTREFCLK1_I 1 0 RXOUTCLK_O SYSCLK_I Figure 97 Specifying clock settings for the IBERT Core 7 Click the Summary tab and ensure that the content matches the following figure Click OK LF Customize IP IBERT 7 Series GTX 3 0 Documentation L IF Location Switch to Defaults Show disabled ports Component Name ibert_7series_gtx_0 Protocol Definition Protocol Selection Clock Settings Summary a QUAD Count MMCM Count RefClk Sources S E GTREFCLKO_I 1 0 TxXP_O 7 0 GTREFCLK1_I 1 0 RXOUTCLK_O SYSCLE_I Figure 98 IBERT Core Summary Page Programming and Debugging www xilinx com 85
93. mo edf You will use this file in Vivado IDE 2 With all the project settings in place click the Run button in the left panel of the Synplify Pro window to start synthesizing the design Programming and Debugging www xilinx com 43 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design S Synplify Pro I 2013 09 1 C Vivado_Debug synopsys s t File Edit View Project Import Run Analysis HI t it E RY a kt c H A Ala e ali R R PR PET Synplify Pro R Run hy Open Project R Close Project ae ev_ FE Add File 3 synplify_1 CAViva ES Change File 8 Add Implementation implementation Options BR Add P amp R Implementation __ A Viewtog o synplify_1 sd Figure 42 Synthesize the Design in Synplify 3 During synthesis status messages appear in the Tcl Script tab Warning messages are expected but there should not be any Error messages To see detailed messages click the Messages tab in the bottom left hand corner of the Synplify Pro console 4 When synthesis completes the output netlist is written to the file rev l1 sinegen demo edf Optional To view the netlist select View gt View Result File 5 Click File gt Save All to save the project then click File gt Exit Step 3 Create EDIF Netlists for the Black Box Created in Synplify P
94. mulation gt Bik 4 RTL Analysis 5 Elaboration Settings gt f Open Elaborated Design 1 Synthesis Select an object to see properties 45 Synthesis Settings gt Run Synthesis gt H Open Synthesized Design 4 Implementation Serial I O Links 5 Implementation Settings gt Run Implementation gt E Open Implemented Design 6 Bitstream Settings No content Generate Bitstream a Hardware Manager p Open Target e Program Device E Add Configuration Memo E Tel Console Messages Serial 1 0 Links E Serial 1 0 Scans Figure 104 Hardware Manager Window Step 4 Interact with the IBERT core using Serial I O Analyzer In this tutorial step you connect to the KC705 target board program the bitstream created in the previous step and then use the Serial I O Analyzer to interact with the IBERT design that you created in Programming and Debugging www xilinx com 90 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links Step 1 You perform some analysis using various input patterns and loopback modes while observing the bit error count Hardware Manager unconnected G No hardware target is open Open target Hardware E Auto Connect a El E bih E Recent Targets Name _Open New Target Figure 105 Open a New Hardware Target 1 Click Open a new hardware target When the Open N
95. n which 1s indicated by the axi rready signal equal to 71 state wait for rready if axi ready IDI then goto wait for rlast else goto wait for rready endif Programming and Debugging www xilinx com 135 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions it F Ihe wait for Plast state is used To detect the end of the read data phase of the AXI transaction which 1s indicated by the axi rlast signal equal to l Once the end of the data phase is detected the ILA core will trigger it S tate Wait for flast if ax flast 1 p1 then trigger else goto wait for rlast endif Note The state machine is used to detect the various phases of an AXI read transaction Beginning of the read address phase Beginning of the read data phase End of the read data phase 6 Arm the trigger of the ILA by right clicking the hw_ila_1 core in the Hardware Manager window and selecting Run Trigger Hardware Manager localhost xilinx_tcf Xilinx Port_ 0001 Hub_ 0001 Hardware ee pen A a hw_ila 1 x a 2 amp Pi gt gt Ei Settings hw_ila_1 Name Status Trigger Mode Settings E localhost 1 Connected Be xilinx_tcf Xilinx Port_ 0 Trigger mode ES xc7k325t_0 3 Open Hardware Device Properties Program Device DI Run Trigger b gt Run Trigger Imm
96. nd Debugging www xilinx com 103 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links 14 The Create Sweep dialog box opens as shown below Various properties for the Sweep test can be changed in this dialog box Leave all the values to its default state and click OK g Create Sweep OX Oo Select the sweep properties and values to create and optionally run a set of scans on the selected link Link Link 0 Description Sweep 1 Scan Properties Scan type 2D Full Eyescan Horizontal increment 8 Horizontal range 0 500 UI to 0 500 UI Vertical increment 8 Vertical range 100 Dwell BER 1e 5 Time Sweep Properties For each property select values to be swept The sweep will cover all combinations of property values Sweep mode Semi Custom 7 Set Properties amp Values Preview 81 Scans Property Name Values to Sweep of Values RXTERM 100 mV 550 mV 1100 mV TXDIFFSWING 250 mV 0000 600 mV 0111 1000 mV 1111 TXPOST 0 00 dB 00000 4 08 dB 01111 12 96 dB 11111 TXPRE 0 00 dB 00000 4 08 dB 01111 6 02 dB 11111 v Run sweep Figure 125 Create Sweep Dialog Box Since there are four different Sweep Properties and each of these properties has three different values as seen in the Values to Sweep column a total number of 81 sweep tests are carried out The Scans window shows the results of
97. nt Targets Name Open New Target Figure 75 Connect to a New Hardware Target id The Open New Hardware Target wizard opens Click Next In the Hardware Server Settings page type the name of the server or select Local server if the target is on the local machine in the Connect to field 5 Ensure that you are connected to the right target by selecting the target from the Hardware Targets page If there is only one target that target is selected by default Click Next 6 In the Set Hardware Target Properties page click Next 7 In the Open Hardware Target Summary page verify that all the information is correct and click Finish Programming and Debugging www xilinx com 67 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware 8 Program the device by selecting and right clicking the device in the Sources window and then selecting Program Device Hardware Session cabo ies einen 202035279628 Name E localhost 1 Connected fe xilinx_tcf Digilent 21020332796 Oper Hardware Device Properties Assign Programming File Refresh Device Export to Spreadsheet Figure 76 Program FPGA 9 In the Program Device dialog box ensure that the bit file to be programmed is correct Click OK d Program Device Select a bitstream programming file and download it to your hardware device You can optionally select a g
98. oject Click Next In the Add Sources page click Next In the Add Existing IP page click Next In the Add Constraints page click Next Set oS oS In the Default Part page select Boards and then select Kintex 7 KC705 Evaluation Platform Click Next 9 Review the New Project Summary page Verify that the data appears as expected per the steps above Click Finish Note It might take a moment for the project to initialize Step 2 Adding an IBERT core to the Vivado Project 1 In the Flow Navigator click IP Catalog The IP Catalog opens g ibert_tutorial C ibert_tutorial ibert_tutorial xpr Vivad i File Edit Flow Tools Window Layout View Help A A X gt D N S XIE G Boers Flow Navigator Project Manager ibert_tutc a ra Sources 2 cm a Go Be Design Sources Constraints H Simulation Sources F IP Cataig sim_1 4 Project Manager Project Settings B Add Sources Figure 93 Opening the Vivado IP Catalog Programming and Debugging www xilinx com 81 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links 2 In the search field of the IP Catalog type IBERT to display the IBERT 7 Series GTX IP E Project Summary x FIP Catalog x m Search IBERT 1 match Name Debug amp Verification Debug ol 2s es EN iF IBERT 7 Series GTX Figure 94 Instantiating the IBERT IP from the
99. ollowing INFO habtoGls 2y l47 vese server WRITE DATA 15 i ND DW 3 OOO 2 2222227 2h A I do 15 After creating the transaction you can run it as a read transaction using the run hw axi command run hw axi Drt This command should return the following INFO La abtools 21147 vese Server READ DATA 15S AADAARAASS IS S33 5222727771011 I Step 3 Using ILA Advanced Trigger Feature to Trigger on an AXI Read Transaction 1 In the ILA hw_ila_1 dashboard locate the Trigger Mode Settings area and set Trigger mode to ADVANCED ONLY 2 In the Capture Mode Settings area set the Trigger position to 512 3 In the Trigger State Machine area click the Create new trigger state machine link Programming and Debugging www xilinx com 133 UG936 v2015 1 May 18 2015 Send Feedback XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions example_jtag_axi_0 v x ILA hw_ila_1 x TEMNI ILA Properties Trigger Mode Settings Trigger node NL DVANCED y Trigger state machine Trigger in Trigger out Capture Mode Settings Capture mode ALWAYS v Data depth 1024 v Trigger position 512 0 1023 Ov x Trigger Capture Status 2 oO A Core status lde Pre Trigge Trigger State Machine Flags Flag 0 0 Flag 1 0 0 0 ii Flag 2 Flag 3 Trigger state 0 4 Hl r Trigger State Machine o n inq tri r machin Create new trigger state mach
100. ontext per IP Run Settings Number of jobs 8 so Figure 134 Generate Output Products Dialog Box 14 The jtag_axi_O IP core is inserted into the design Project Manager jtag_2_axi_tutorial a Co S B Har Design Sources 1 mmf jtag_axi_0 jtag_axi_0 xci H S Constraints H Simulation Sources 1 Hierarchy IP Sources Libraries Compile Order 5 Templates Figure 135 Generated JTAG to AXI Master IP in the Design Programming and Debugging www xilinx com 114 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 15 Right click Jtag_axi_O and select Open IP Example Design Project Manager ibert_tutorial EHS Simulation Sources 1 1 4 Re customize IP H sim_i 1 Generate Output Products Reset Output Products Into Project Alt I xX Remove File from Project Delete i r Enable File Alt Equals y LF ibert_7series_qtx_O xci Disable File Alt Minus IP name IBERT 7 Series Hierarchy Update 7 qafi I l Version 3 0 Rev 8 Refresh Hierarchy Description The IBERT 7 5 IP Hierarchy 7 for evaluating 4 transceivers T checkers that a ports and the CTY tranceroaineg Ai Set as Top Set Used In 4 Edit Constraints Sets General Properties Edit Simulation Sets i Add Sources Design Runs Report IP Status S Name TU
101. or IBERT cores Don t show this dialog again Figure 113 Auto Detect Serial I O links 9 The Hardware window now shows the IBERT IP that you customized and implemented from the previous steps It contains two QUADS each of which has four GTX transceivers These components of the IBERT were detected while scanning the device after downloading the bitstream If you do not see the QUADS then select the XC7K325 device right click and select Refresh Device cx e Esa DI bd Name Status localhost 1 Connected Be xilinx_tcf Digilent 210203327962A 1 Open EIS XC7K325T_0 1 active 6 Quad_117 5 COMMON_X0Y2 Locked amp MGT_XOY8 8 000 Gbps 4 MGT_X0Y9 No Link 3 MGT_XO0Y10 No Link 24 MGT_XOY11 No Link amp Quad_118 5 COMMON_X0Y3 Locked MGT_X0Y12 No Link MGT_XO0Y13 No Link 2a MGT_X0Y14 No Link MGT_X0Y15 No Link Figure 114 The Hardware Window Showing the QUADS after Device Programming 10 Next create links for all eight transceivers Vivado Serial I O analyzer is a link based analyzer which allows users to link between any transmitter and receiver GTs within the IBERT design For this tutorial simply link the TX and RX of the same channel To create a link right click the IBERT Core in the Hardware window and click Create Links Programming and Debugging www xilinx com 96 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Name localhost 1 Ge
102. orm the steps to view and repair the state machine glitch e The input is a scalar signal called button When the button input equals 1 the state machine advances from one state to the next e The output is a 2 bit signal vector called Y and it indicates which of the four sine wave generators is selected Programming and Debugging www xilinx com 62 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware The input signal button connects to the top level signal GPIO_BUTTONS re 1 which is a low to high transition indicator on the Sine Wave Sequencer button The output signal Y connects to the top level signal sineSel which selects the sine wave GPIO_BUTTON 1 l GPIO_BUTTON_IBUF_1 Figure 69 Sine Wave Sequencer Button Schematic Viewing the State Machine Glitch You cannot troubleshoot the issue you identified above by connecting a debug probe to the GPIO_BUTTON 1 input signal itself The GPIO_BUTTON 1 input signal is a PAD signal that is not directly accessible from the FPGA fabric Instead you must trigger on low to high transitions rising edges on the GPIO_BUTTON_IBUF signal which is connected to the output of the input buffer of the GPIO_BUTTON 1 input signal As described earlier the glitch reveals itself as multiple low to high transitions on the GPIO_BUTTONS_1_IBUF signal but it occurs intermittently Because it coul
103. ource files and click OK j Verify that the files are added and Copy sources into project is selected Click Next 7 Inthe Add Constraints optional dialog box the provided XDC file sinegen demo kc705 xdec should automatically appear in the main window Click Next 8 In the Default Part page specify the xc7k325tffg900 2 part for the KC705 platform You can also select Boards and then select Kintex 7 KC705 Evaluation Platform Click Next 9 Review the New Project Summary page Verify that the data appears as expected per the steps above Click Finish Note It might take a moment for the project to initialize 10 In the Sources window in Vivado IDE expand sinegen_demo_inst_vio to see the source files for this lab Note that ila 0 core has been added to the project However vio _0 the VIO core is missing a S ma ot a H Design Sources 1 8s sinegen_demo_inst_vio hdl_inst_vio sinege amp U_DEBOUNCE_0 debounce Mixed de e vhd vi U_DEBOUNCE_1 debounce Mixed debounce vhd 8 U_SINEGEN sinegen kintex vi U_FSM fsm Mixed fs iv LA ila Ofila Oo Constraints 1 Simulation Sources 1 Hierarchy IP Sources Libraries Compile Order Figure 22 Missing Source for VIO Core In the following step you will instantiate and configure this VIO core 11 From the Flow Navigator click IP Catalog expand Debug amp Verification then expand Debug and double click VIO The Customize IP
104. parameter The width of AXI data bus is customizable This IP can drive any AXI4 Lite or Memory Mapped Slave directly This can also be connected as master to the interconnect Run time interaction with this core requires the use of the Vivado logic analyzer feature Key Features e AXI4 master interface e Option to select AXl4 Memory Mapped and AXI4 Lite interfaces e User controllable AXI read and write enable e User Selectable AXI datawidth 32 and 64 e User Selectable AXI ID width up to four bits e Vivado logic analyzer Tcl Console interface to interact with hardware Additional Documentation LogiCORE IP JTAG AXI Master v1 0 Product Guide AXI PG174 contains more information the JTAG to AXI Master IP core Programming and Debugging www xilinx com 107 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions Design Description This section has three steps as follows 1 Opening the JTAG to AXI Master IP Example Design project and adding mark_debug to the AXI interface connection Inserting an ILA core into the design and configuring it for advanced trigger is also included in this step Programming the KC705 board and interacting with the JTAG to AXI Master IP core Using the ILA Advanced Trigger Feature to Trigger on an AXI Read Transaction Step 1 Opening the JTAG to AXI Master IP Example Design and Configuring the AXI Interfac
105. pens Click Open a new hardware target The Open New Hardware Target dialog box opens Hardware Manager unconnected G No hardware target is open Open target Hardware E Auto Connect E E Recent Targets Name Open New Target Figure 148 Connect to a Hardware Target 3 In the Connect to field choose Local server and click Next Programming and Debugging www xilinx com 126 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions Open New Hardware Target Select local or remote hardware server then configure the host name and port settings Use Local server if the target is attached to the local machine otherwise use Remote server Connect to Local server target is on local machine Click Next to launch and or connect to the hw_server port 3121 application on the local machine lt Beck Ne gt _ Eich Figure 149 Hardware Server Name Note Depending on your connection speed this may take about 10 to 15 seconds Programming and Debugging www xilinx com 127 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 4 If there is more than one target connected to the hardware serve you will see multiple entries in the Select Hardware Target page In this tutorial there is only one target as shown in the following f
106. ptionally run a scan on the selected link Link Link 1 Description Scan 0 Scan Properties Scan type 2D Full Eyescan Horizontal increment 8 Horizontal range 0 500 UI to 0 500 UI Vertical increment 8 Vertical range 100 Dwell BER 1e 5 Time IV Run scan Figure 122 The Create Scan Dialog Box Programming and Debugging www xilinx com 102 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links The Scan Plot window opens as shown below Unit Interval k A gt Summary Metrics Settings Name SCAN_O Open area 2880 Link settings N A Description Scan 0 Horizontal increment amp Started 2013 Sep 30 10 50 12 Horizontal range 0 500 UI to 0 500 UI Ended 2013 Sep 30 10 50 22 Vertical increment a Vertical range 100 Figure 123 2D Scan Plot The 2D Scan Plot is a heat map of the BER value 13 You can also perform a Sweep test on the links that you created earlier In the Links window highlight Link 0 under the Link called Link Group SMA right click and select Create Sweep Bits 3 2 601E12 Delete Delete Link 1 on 5 2 604E12 Link 2 p 5 2 604E12 Link 3 4 5 2 60512 Link 4 5 2 605E12 Link 5 Create Scan 5 2 605E12 Link 6 l 5 2 606E12 Q link 7 i Create Sweep 1 c01 Link Properties Ctrl E Commit Properties Figure 124 Create a Sweep Test Programming a
107. rget Select a hardware target from the list of available targets then set the appropriate JTAG clock TCK frequency If you do not see the expected devices decrease the frequency or select a different target RXS gt Hardware Targets Type Port Name JTAG Clock Frequency inx_tcf _ Xilinx Port_ 0007 Hub_ 0004 6000000 Hardware Devices for unknown devices specify the Instruction Register IR length Name ID Code IR Length xc7k325t_0 33651093 6 Hardware server localhost 3121 Figure 108 Select Hardware Target Page Programming and Debugging www xilinx com 93 UG936 v2015 1 May 18 2015 Send Feedback XILINX Lab 5 Using Vivado Serial Analyzer to Debug Serial Links ALL PROGRAMMABLE 4 Inthe Open Hardware Target Summary page review the options that you selected Click Finish E Open New Hardware Target Open Hardware Target Summary Hardware Server Settings o Server localhost 3121 Target Settings o Target xilinx_tcf Xilinx Port_ 0007 Hub_ 0004 o Frequency 6000000 To connect to the hardware described above click Finish Figure 109 Open Hardware Target Summary Dialog Box 5 The Hardware window in Vivado IDE should show the status of the target FPGA device on the KC705 board OS SB Di a Name Status Connected localhost 1 Ge xilinx_tcf Digilent 210203327962A 1 Open Not programmed xc7k325t_O 1 active XADC System Monitor
108. ro The black box sinegen created in the Synplify Pro project contains the Direct Digital Synthesizer IP You need to create a synthesized design for this block To do this create an RTL type project in Vivado IDE by following the steps outlined below 1 Launch Vivado IDE 2 Click Create New Project This opens up the New Project wizard Click Next 3 Under Project Name set the project name to proj_synplify_netlist Click Next Programming and Debugging www xilinx com 44 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX 10 11 12 13 ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design Under Project Type select RTL Project Click Next Under Add Sources click Add Files navigate to the Vivado Debug src Lab4 folder and select the sinegen vhd file Set Target Language to VHDL Ensure that Copy sources into project box is selected Click Next Under Add Existing IP click Add Files navigate to the vivado Debug src Lab 4 folder and select the sine high xci sine low xci and sine mid xci files Click Next Under Add Constraints the sac files are automatically added to the project These files are not needed for this step Remove them from this project by clicking Remove Selected File on the right of the dialog box Click Next Under Default Part select Boards and then select the Kintex 7 KC705 Evaluation Platform and correct version for your hardware Click Next
109. ro Synthesis Tool and Vivado for Debugging a Design Step 4 Create a Post Synthesis Project in Vivado IDE ee wW O UP 9 Launch Vivado IDE Click Create New Project This opens up the New Project wizard Click Next Set the Project Name to proj_synplify Click Next Under Project Type select Post synthesis Project Click Next Under Add Netlist Sources click Add Files navigate to the Vivado Debug synopsys rev_ 1 folder and select sinegen_demo edf Click OK Add the four netlist files created in the previous section Click Add Files again navigate to the Vivado Debug src Lab4 folder and select the following files Sinegen edn dds compiler vo 0O viv edn dds compiler vo 0 viv parameterized edn dds Compiler vo 0 viv parameterized gt cdn Click OK in the Add Source Files dialog box In the Add Netlist Sources dialog box ensure that Copy Sources into Project is selected Click Next Under Add Constraints a sdc file should be automatically populated Remove this file by selecting it and clicking Remove Selected File on the right of the dialog box Click Add Files navigate to the Vivado debug src folder and select the sinegen_demo_kc705 xdc file This file has the appropriate constraints needed for this Vivado project Click OK in the Add Constraints File dialog box In the Add Constraints optional dialog box ensure that Copy Constraints into Project is selected Click Next Under Default Part select Boards and then se
110. s bi Trigger position in window 0 General Settings Refresh rate 500 ms Figure 79 ILA Core and VIO Core Dashboards Programming and Debugging www xilinx com 69 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware 11 Click Run Trigger Immediate to capture the data immediately H penae L rie a ardavware X S15 DIN e Name Run Trigger Immediate Status localhost 1 Connected Wo xilinx_tcf Digilent 210203327962A 1 Open S hw_ila_1 1 Idle hw_vio_1 VI OK Outputs Reset XADC mM Figure 80 Run Trigger Immediate 12 Make sure that there is activity on the sine 19 0 signal 13 Select the sine signal in the Waveform window right click and select Waveform Style gt Analog 14 Select the sine signal in the Waveform window again right click and select Radix gt Signed Decimal You should be able to see the sine wave in the Waveform window aa a sine 19 0 push_button_reset_i fog E GPIO_BUTTONS_re 0 0 Mi PROBE_INO_2 2 2 M GPIO_BUTTONS_dly 1 0 Figure 81 Sine Wave after Modifying the Properties of the sine 19 0 Signal 15 Instead of using the GPIO_SW push button to cycle through each different sine wave output frequency you are going to use the virtual push_button_vio toggle switch from the VIO core 16 You can now customize the ILA dashboard options to
111. saction to write to the first four locations of the BRAM set wt create hw axi txn write txn get hw axis hw axi 1 type WRITE address 00000000 len 128 data 44444444 33333333 22222222 11111111 where o write_txn is the name of the transaction o get_hw_axis hw_axi_1 returns the hw_axi_1 object o address 00000000 is the start address o len 4 sets the AXI burst length to 128 words o data 44444444 33333333 _22222222 11111111 is the data to be written Note The data direction is MSB to the left i e address 3 and LSB to the right te address 0 Also note that the data will be repeated from the LSB to the MSB to fill up the entire burst 13 The next step is to set up a 128 word AXI burst transaction to read the contents of the first four locations of the AXI BRAM core set rt create hw axi txn read txn get hw axis hw ax 1 type READ address 00000000 len 128 where o read txn is the name of the transaction o get hw axis hw axi 1 returns the hw_axi_l object o address 00000000 Is the start address o len 128 sets the AXI burst length to 4 words Programming and Debugging www xilinx com 132 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 14 After creating the transaction you can run it as a write transaction using the run_hw_axi command run hw axl Swt This command should return the f
112. splay uniq and click the Select Clock Domain sel m ERTS command ar 7 1 ts button or press the Delete key 234 2 4 al s axi awaddr 14 1 s axi awburst 1 s_axi_awcache 3 1 ebug 202 il s axi aw 3dbm_v1 lJabtools_xsdbslavelib_v2 Figure 143 Select Clock Domain Dialog Box 27 Observe that all of the nets now have an assigned clock domain Click Next Programming and Debugging www xilinx com 122 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 28 In the Trigger and Storage Settings page ensure that Advanced Trigger and Capture Control are selected Click Next Set up Debug ILA Integrated Logic Analyzer General Options Sample of Data Depth 1024 Input Pipe Stages 0 Trigger And Storage Settings v Capture Control v Advanced Trigger lt Back Next gt A F Figure 144 Trigger and Capture Modes Page 29 Click Finish Note See that the ILA core was inserted and attached to the dbg_ hub core Programming and Debugging www xilinx com 123 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Synthesized Design xc7k325tffg900 2 active HHA Nets 324 HA Leaf Cells 11 HHE axi_bram_ctrl_inst axi_bram_ctr _0 dbg_hub dbg_hub_Cv 4 jtag_axi_full_inst jtag_axi_0 E ila 0 u_ila_0 CV _ amp Sources Cell Prop
113. st Trigger Full Capture status Window 1 of 1 Window sample 0 of 1024 Total sample 0 of 1024 Idle Idle Idle Trigger Setup hw_ila_1 a OF a Press the f os button to add probes D Add Probes x GA g m g DA Search Probes for hw_vio_1 5 hi Trigger Setup hw Capture Setup hw_vio_1 Waveform hw_ila_1 M sineSel 1 0 Q eg 3 sine 19 0 my ILA core 3 VIO core 3 utput values in the VIO core s R Conca Figure 85 VIO Add Probes Window Programming and Debugging www xilinx com 74 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware 20 Note the values on all probes in the VIO Probes window Status hw_ila_i nied m amp Core status dle Waiting for Trigger Post Trigger Full Capture status Window 1 of 1 Window sample 0 of 1024 Total sample 0 of 1024 Idle Idle Idle Trigger Setup hw_ila_1 OF x hw_vio_1 OX A Name Value Activity Direction WIO i oF ca te DONT_EAT E 0 Input hw_vio_i vi GPIO_BUTTONS _re 1 1 B 0 Input hw_vio_1 5 th ig sineSel_1 1 0 H 0 Input hw _wvio_ D ress the e button to add probes la push_button_reset Lie Output hw _vio_ ee ian salar ush button vio 1 C a Oe i t Trigger Setup hw_il Capture Setup hw_i 4 Figure 86 VIO Probes Added to VIO Core Window Programming and Debugging www xilinx com 75 UG936 v2015 1 May 18
114. st runs impl_1 debug_nets Itx a Figure 58 Select Bitstream File to Download for Lab 1 CAUTION The file paths of the bitstream to be programmed will be different for different labs Ensure that the relative paths are correct Note Wait for the program device operation to complete This may take few minutes 10 Ensure that an ILA core was detected in the Hardware panel of the Debug view a Zee pi m Status Name Connected E localhost 1 go xilinx_tcf Digilent 210203327962A 1 Open ES xc7k325t_0 2 active hw_ila_1 ILA Idle XADC System Monit Figure 59 ILA Core Detection www xilinx com Programming and Debugging UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware 11 The Integrated Logic Analyzer dashboard opens Settings hw_ila_1 Status hw_ila_1 Trigger Mode Settings amp Core status Trigger mode BASIC_ONLY idle waiting for Trigger Post Trigger Full Capture status a p Window 1 of 1 Window sample 0 of 1024 Total sample 0 of 1024 Capture Mode Settings Idle Idle Idle Capture mode ALWAYS Number of windows 1 Window data depth 1024 1 1024 Trigger Setup hw_ila_1 ape Capture Setup hw_ila_1 Trigger position in window 0 fe General Settings Refresh rate 500 D Waveform hw_ila_1 Figure 60 The Vivado Integrated Logic Analyzer window Verifying Sine Wav
115. synthesis simulation implementation and IP related options 4 IP Integrator 3 Create Block Design Figure 2 Configuring the Project Settings IMPORTANT As an optional step in the Project Settings dialog box select Synthesis from the left and change flatten hierarchy to none The reason for changing this setting to none is to prevent the synthesis tool from performing any boundary optimizations for this tutorial 2 In the Vivado Flow Navigator expand the Synthesis drop down list and click Run Synthesis Note When synthesis runs a progress indicator appears showing that synthesis ts occurring This could take a few minutes 3 In the Synthesis Completed dialog box click Cancel as shown in the following figure You will implement the design later Programming and Debugging www xilinx com 13 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design Synthesis Completed i Synthesis successfully completed Next Open Synthesized Design View Reports Don t show this dialog again Cancel _ Figure 3 Synthesis Completed Dialog Box Step 3 Probing and Adding Debug IP To add a Vivado ILA core to the design take advantage of the integrated flows between the Vivado IDE and Vivado logic analyzer In this step you will accomplish the following tasks e Add debug nets to the project e Run the
116. t debug probes file that corresponds to the debug cores contained in the bitstream programming file Bitstream file _40_Debug 2015 1 proj_hdl_vio proj_hdl_vio runs impl _1 sinegen_demo_inst_vio bit Debug probes file C Vivado_Debug 2015 1 proj_hdl_vio proj_hdI _vio runs impl_1 debug_nets lt B Enable end of startup check Figure 77 Program Device with the sinegen_demo_inst_vio bit File Programming and Debugging www xilinx com 68 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware 10 After the FPGA device is programmed you see the VIO and the ILA core in the Hardware window e Di i Name Status B localhost 1 Connected e xilinx_tcf Digilent 210203327962A 1 Open f XADC Sys f hw_ila_1 IL Idle hw_vio_1 V OK Outputs Reset Figure 78 The ILA and VIO Cores in the Hardware Window You now have two debug dashboards one for the ILA core and the other for the VIO core a ai Settings hw_ila_1 ESN pr 3 Status hw_ila_1 ee pe ee Trigger Mode Settings amp Core status Trigger mode BASIC_ONLY C ide Waiting for Trigger Post Trigger Full 3 Capture status Capture Mode Settings Window 1 of 1 Window sample 0 of 1024 Total sample 0 of 1024 Idle Idle Idle Capture mode ALWAYS Number of windows 1 Trigger Setup hw_ila_1 malhat Window data depth 1024 FO rest e
117. ta J amp GPIO_BUTTONS_db 1 clk FDRE Ir GPIO_BUTTONS_dly 2 clk FDRE I Ta GPIO_BUTTONS dly 0 clk FDRE e 1 GPIO_BUTTONS_dly 1 clk FDRE tt I GPIO_BUTTONS_re 2 clk FDRE U_SINEGEN sel 2 clk FDRE selo clk FDRE i Te self clk FDRE U_SINEGEN sine 20 clk FDRE i De sine 0 clk FDRE sine 1 clk FDRE amp sine 2 clk FDRE amp sine 3 clk FDRE amp sine 4 clk FDRE 7 sine 5 clk FDRE amp sine 6 clk FDRE amp sine 7 clk FDRE 4400404804646 460464604604 6 lt lt oCceCeeeeeeeeeeeeaeas Nets to debug Figure 13 Specify Nets to Debug 10 In the ILA Core Options page go to the Trigger and Storage Settings section Select both the Capture Control and Advanced Trigger settings Click Next Programming and Debugging www xilinx com 22 UG936 v2015 1 May 18 2015 Send Feedback XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design 11 In the Setup Debug Summary page make sure that all the information is correct and as expected Click Finish Set Up Debug Set up Debug Summary V VADO 0 debug cores will be removed 1 debug core will be created Found 1 clock XI NX Open in Debug layout on aa To apply the above changes click Finish Figure 14 Set up Debug Summary Upon clicking Finish the relevant XDC commands to insert the ILA core s are generated Programming and Debugg
118. te an Integrated Bit Error Ratio Tester IBERT core design in the Vivado Integrated Design Suite e Interact with the design using Serial I O Analyzer This includes connecting to the target KC705 board configuring the device and interacting with the IBERT Transceiver IP cores e Perform a sweep test to optimize your transceiver channel and to plot data using the IBERT sweep plot GUI feature Design Description You can customize the IBERT core and use it to evaluate and monitor the functionality of transceivers for a variety of Xilinx devices The focus for this tutorial is on Kintex 7 GTX transceivers Accordingly the KC705 target board is used for this tutorial The following figure shows a block diagram of the interface between the IBERT Kintex 7 GTX core interfaces with Kintex 7 transceivers Programming and Debugging www xilinx com 79 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links e DRP Interface and GTX Port Registers IBERT provides you with the flexibility to change GTX transceiver ports and attributes Dynamic reconfiguration port DRP logic is included which allows the runtime software to monitor and change any attribute in any of the GTX transceivers included in the IBERT core When applicable readable and writable registers are also included These are connected to the ports of the GTX transceiver All are accessible at run time
119. tion Method for Debugging a Design in Vivado sssssssssseesessrresrrrrerrrresrrererreressne 25 AOC ON r A T E T EAE E eyemeneosmnere aunennecunpare 25 Step 1 Creating a Project with the Vivado New Project Wizard sssessssssssrsssrrrssrrssrresrrresrrrsrresrrreerresrrreerresns 25 Step 2 Synthesize Implement and Generate Bitstream cccccceecccsseccceeccceeccceuecsceecscenecseeneeeeunceseueceesueseeensss 27 Lab 3 Using a VIO Core for Debugging a Design in Vivado ssssssssssesssserssrresesrrresrrrrerrrressrereserresereresrrreserereseeresene 29 Mro dU UO ear vaie hasan E E E E EA E 29 Step 1 Creating a Project with the Vivado New Project Wizard sssssssssssesressrssssrrssrrrsrrresrrnsrrrsrrresresrrreerreses 30 Step 2 Synthesize Implement and Generate Bitstream cccccccccssecccseecccesecceecsceueceeeeceeeneeseeeceseueceeeneseeeness 35 Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design cccccseececesesceeeceseeeceeeeeceeeneeeeens 36 IV OCVENG TIO IA cree vyceresnesscoresammecsdoueus wate eat E A E E E iste runn se E EE E Gaerne 36 Step 1 Create a Synplify Pro PIO SCE via ccosicbacecasnsedseaneenessss voxacnsa aes nanausndsendocnsagen denned cevkenan need cess ecpasaeyvewesasanvenacters 36 Step 2 Synthesize the Synplity OC srren nen e EN 43 Step 3 Create EDIF Netlists for the Black Box Created in Synplify Pro sssssssessesesrensesrenesrersssreresrrrsssreressreseseerese 44 Step 4
120. to this instance of the hw_server application Connecting to the Target Board Locally If you plan to connect locally ensure that you have your KC705 hardware plugged into a Windows machine and then perform the following steps 1 Connect the Digilent USB JTAG cable of your KC705 board to a USB port on a Windows system 2 Ensure that the board is plugged in and powered on 3 Power cycle the board to clear the device 4 Turn DIP switch positions pin 1 on SW13 De bounce Enable to the OFF position Using the Vivado Integrated Logic Analyzer 1 In the Flow Navigator from the Program and Debug drop down list select Open Hardware Manager 4 Program and Debug 5 Bitstream Settings Design Runs i Generate Bitstream A Name P ARE EE gt S B Open Hardware Manager eas synth_1 constrs_1 Figure 50 Open Hardware Manager 2 The Hardware Manager window opens Click Open New Target The Open New Hardware Target wizard opens Programming and Debugging www xilinx com 52 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware Hardware Manager unconnected Gi No hardware target is open Open target Hardware E Auto Connect nam O bl O Recent Targets if Open New Target Figure 51 Connect to a Hardware Target 3 In the Hardware Server Settings page type the name of the server or select Local server if the target
121. valuation Platform xc7k325tffg900 2 4 P itegator Top module name Not defined Board Part 5 Kintex 7 KC705 Evaluation Platform xilinx com kc705 part0 1 2 Display name Wi Board part name Repository path V xbuilds 2015 1_0428_1 installs nt64 Vivado 2015 1 data boards board_files URL www xilinx com kc705 Board overview Kintex 7 KC705 Evaluation Platform Programming and Debugging UG936 v2015 1 May 18 2015 Synthesis Implementation 2 Status Not started Status Not started Select an object to see Messages No errors or warnings Messages No errors or warnings properties Part xc7k325tffg900 2 Part xc7k325tffg900 2 Strategy Vivado Synthesis Defaults Strategy Vivado Implementation Defaults Incremental compile None Design Runs PEP es a Name Constraints Status Progress WNS TNS WHS THS TPWS Failed Routes LUT LUTs FF aj es E synth_1 constrs_1 Not started 0 gt impl_1 constrs_1 Not started 0 gt K ad H a lt i gt Tcl Console Messages amp Log Reports gt gt Design Runs Figure 131 Synthesis Completed Dialog Box www xilinx com 111 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 6 Using Vivado ILA core to Debug JTAG AXI Transactions 11 In the Search field on the right of the IP Catalog tab type in JTAG to AXI Note The JTAG to AXI Master core shows up under the Debug amp Verification gt Debug category
122. w_ila_1 ee se Trigger position in window 512 0 102 Q Name Compare Value GPIO BUTTONS IBUF 1 0 B RX incall E GPIO_BUTTONS_IBUF 1 0 Refresh rate 500 ms i D D ss the s button to add probe A GPIO_BUTTONS_re 1 0 i A GPIO_BUTTONS_dly 1 0 xP GPIO_BUTTONS_db 1 0 Figure 70 Setting Trigger Conditions CAUTION For different labs the GPIO_BUTTONS_IBUF may show up differently This may show up as two individual bits or two bits lumped together in a bus Ensure that you are using bit 1 of this bus to set up your trigger condition For example in case of a two bit bus you will set the Value field in the Compare Value dialog box to RX CAUTION The ILA properties window may look slightly different for different labs 3 Enable the Auto Retrigger mode on the ILA debug core as shown below Programming and Debugging www xilinx com 64 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Using Vivado Logic Analyzer to Debug Hardware Hardware Manager localhost xilinx_tef Xilinx Port_ 0001 Hub_ DI m Setti Name Trig B localhost 1 Connected Ge xilinx_tef Xilinx Port_ 0 Open Programmed Ctril E Run Trigger Run Trigger Immediate Stop Trigger Enable Auto Re trigger Dashboard Export to Spreadsheet Figure 71 Enable Auto retrigger When you issue a Run Trigger or a Run Trigger Immediate command after setting the Auto
123. www xilinx com 16 UG936 v2015 1 May 18 2015 Send Feedback XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design o sine 20 Nets folder under the U_SINEGEN hierarchy ax rE 4 sinegen_demo EH Nets 40 EF GPIO_BUTTONS 2 i GPIO_BUTTONS_db 2 H t GPIO_BUTTONS_dly 2 GPIO_BUTTONS_IBUF 2 I GPIO_BUTTONS_IBUF 0 GPIO_BUTTONS_IBUF 1 A GPIO_BUTTONS_re 2 Get LEDS_n 4 A gt LEDS_n_OBUF 2 Figure 7 Add Nets for Debug from the Synthesized Netlist Note These signals represent the significant behavior of this design and are used to verify and debug the design in subsequent steps 5 Right click the selected nets and select Mark Debug as shown in the following figure Programming and Debugging www xilinx com 17 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design 42 Schematic gt pty lg Ea C Users sm 53 signa sinegen_demo EH Nets 40 Geli GPIO_BUTTONS 2 GPIO_BUTTONS_db 2 Ht GPIO_BUTTONS_dly 2 Eig GPIO_BUTTONS_IBUF 2 58 signa ori EE 59 signa p GA ss Signa 56 signa HW 57 signa Ht GPIO_BUTTOI Hi LEDS_n 4 Hi LEDS_n_OBUF 1 be T lt consto gt lt constl gt a Select Driver Pin i eal CLK_ N 2 Schematic F4 Show Connectivity
124. x com 20 UG936 v2015 1 May 18 2015 Send Feedback XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design 8 When the Set up Debug wizard opens click Next f Set up Debug Set up Debug This wizard will guide you through the process of 1 Choosing nets and connecting them to debug cores 2 Associating a clock domain with each of the nets chosen for debug 3 Choosing additional features on the debug cores like Data Depth Advanced Trigger mode and Capture Control Note This setup wizard does not apply to the VIO IBERT JTAG to AXI Master debug cores Please refer to Vivado Programming and Debug User Guide for further instructions on how to use these IPs VIVADO To continue click Next Figure 12 Set up Debug Wizard Programming and Debugging www xilinx com 21 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 1 Using the Netlist Insertion Method for Debugging a Design 9 In the Nets to Debug page ensure that all the nets have been added for debug and click Next Set Up Debug Nets to Debug The nets below will be debugged with ILA cores To add nets click Find Nets to Add You can also select nets in the Netlist or other windows then drag them to the list or click Add Selected Nets 1 as Name Clock Domain Driver Cell TRIG DA a eas I GPIO_BUTTONS_db 2 clk FDRE J amp GPIO_BUTTONS_db 0 clk FDRE
125. xilinx_tcf Digilent 210203327962A 1 Fe xc7k325t_0 2 active Lab 5 Using Vivado Serial Analyzer to Debug Serial Links Status Connected Open Programmed am Quad_117 5 aa COMMON_X0Y2 Pa MGT_XOY8 e K MGT_X0Y9 MGT_XOY10 Pg MGT_XOY11 oy TS Quad_118 5 a COMMON_XOY3 Py MGT_XOY12 Py MGT_XOY13 B4 MGT_X0Y14 BPa MGT_XOY15 Figure 115 Create Links Locked 8 000 Gbps No Link No Link No Link Locked No Link No Link No Link No Link IBERT Core Properties Ctri E Auto detect Links Open Hardware Dashboard Serial 1 0 Links Serial 1 O Scans Commit Properties Refresh Serial I O Objects Select Export to Spreadsheet The Create Links dialog box opens Make sure the first transceiver pairs MGT_XOY8 TX and MGT_XOY8 RX are selected Programming and Debugging UG936 v2015 1 May 18 2015 www xilinx com 97 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 5 Using Vivado Serial Analyzer to Debug Serial Links b Create Links To create a new link select a TX GT and or an RX GT then click the Add button on the New Links toolbar TX GTS RX GTS Search Q Search Q MGT_XOY9 TX xc7k325t_0 Quad_117 MGT_XOY9 RX xc7k325t_0 Quad_117 E gt MGT_XOY10 TX xc7k325t_0 Quad_117 lt MGT_XOY10 RX xc7k325t_0 Quad_117 gt MGT_XOV11 TX xc7k325t_0 Quad_117 lt q MGT_X0Y11 RX xc7k325t_0 Quad_117 gt MGT_XOY12 TX xc7k325t_0 Quad_118
126. you want to debug by putting attributes in the HDL files These attributes are already placed in the sinegen demo vha file of this tutorial Open the sinegen demo vhd file and inspect the lines shown Attributes for Synplify Pro attribute syn_keep boolean attribute syn_keep of GPIO BUTTONS _db Signal is true attribute syn_keep of GPIO BUTTONS dly Signal is true Attribute syn_keep of GPIO_BUTTONS_re Signal is true Figure 39 Specifying Attributes to Preserve Net Names in Synplify 11 You also can specify the mark_debug attributes in the source HDL files to mark the signals for debug as shown in the snippet code from singen demo vha file Add mark_debug attributes to show debug nets in the synthesized netlist attribute mark_debug string attribute mark_debug of GPIO_ BUTTONS db signal is true attribute mark debug of GPIO BUTTONS dly signal is true attribute mark debug of GPIO BUTTONS re signal is true Figure 40 Add Mark_Debug Attribute in HDL File Programming and Debugging www xilinx com 42 UG936 v2015 1 May 18 2015 Send Feedback amp XILINX ALL PROGRAMMABLE Lab 4 Using Synplify Pro Synthesis Tool and Vivado for Debugging a Design 12 The synplify 1 sdc file contains various kinds of constraints such as pin location I O standard and clock definition The synplify 1 cdc file contains directives for the compiler Here is where the nets of interest to us that are marked for

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