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M32171F4VFP M32171F3VFP User`s Manual Preliminary

1. Clock bus Input event bus Output event bus 3210 3210 gt IRQ2 3 5 ci 0 udf 4 F Fo 7 T gt IRQ2 TCLK 0 o TCLKOS 7 gn TOP 1 udf E F1 1 e gt IRQ2 IRQS m TOP 2 udf 4 F F2 o TO 2 L a IRQ2 TIN O TINOS tel shy Ha an TOP 3 o gt 5 gt IRQ2 DRQ7 ld 4 F F4 4 gt IRQ2 5 udf 4 5 o TO 5 gt IRQ1 5 i cl en OP 6 udf 5 F F6 TO6 S i IRQ 7 df ull RUPES S E 7 o 107 uli AS IRQ6 2615 1 4 0 ud 34 sH EFs LoTos Lo 5 fe al IRQ6
2. Clock bus Input event bus Output event bus 3210 3210 0123 TOP 0 Reload register udf PO Down counter F Fo TO 0 A Tes 5 Correction register 16 bits en i 1802 0 O 1TCLKOS 4 1 udf e F F1 O TO 1 IRQ2 pa 1198 2 F F2 o TO 2 BI o 29 1802 tuns ti en ros udf t IRQ2 fe en TOP 4 udf F F4 0 TO 4 1802 5 udf 5 5 m gt IRQ1 US 41 419 en TOP 6 TOOTH 5 6 6 EN S a par 7 rt TOP 7 en 1 HHHSHEE 115 IRQ6 5 en TOP 8 udt 2 x If S H F F8 O TO 8 Lo 4 c 5 IRQ6 She en TOP 9 udf tote S F F9L O TO 9 1 r IRQS 9 en 10 H SH 10 10 3210 3210 0123 F F Output flip S Selector Figure 10 3 1 Block Diagram of TOP Output related 16 bit Timer 10 46 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer 10 3 2 Outl
3. Clock bus Input event bus Output event bus 3210 3210 0123 TMS 0 ovf IRQ7 je M Ik TCLK3 O1TCLKSS te 9 Counter gt Measure register 3 16 bits Measure register 2 m gt Measure register 1 gt Measure register 0 cap3 cap2 cap1 0 1 15 5 5 IRQ7 rr clk TMS 1 ovf gt IRQ10 cap3 cap2 cap1 TIN16 166 et S 0 IRQ10 TIN17 O TIN17S 5 DRQ5 IRQ10 L A TIN18 O TIN18S t LS DRQ6 IRQ10 19 O TIN19S 4 5 3210 3210 0123 Selector Figure 10 5 1 Block Diagram of TMS Input related 16 bit Timer 10 123 Ver 0 10 1 0 TIMERS 10 5 TMS Input related 16 bit Timer 10 5 3 TMS Related Register Map The diagram below shows a TMS related register map Address DO 0 Address D7 D8 1 Address D15 H 0080 03 0 TMS Counter TMSOCT H 0080 03C2 TMSO Measure 3 Register TMSOMR3 H 0080 03 4 TMSO Measure 2 Register TMSOMR2 H 0080 03 6 TMSO Measure 1 Register TMSOMR1 H 0080 03 8 TMSO Measure 0 Register TMSOMRO 50 Control Register 51 Control Register 70080 030R TMSOCR TMS1CR H 0080 03D0 TMS1 Counter TMS1CT H 0080 03D2 TMS1 Measure 3 Register TMS1MR3 H 0080 03D4 TMS1 Measure 2 Register TMS1MR2 H 0080 0306 TMS1 Measure
4. Clock bus Input event bus Output event bus 3210 3210 0123 TMLO 1 2 internal i peripheral 5 Counter Measure register 3 clock 82 bits gt Measure register 2 m gt Measure register 1 Measure register 0 cap3 cap2 cap1 0 IRQ11 E P P TIN20 TIN20S S IRQ11 La TIN21 O TIN21S S IRQ11 l TIN22 O TIN22S S IRQ11 4 7 5 TIN23 TIN23S TML1 4 5 Counter gt Measure register 32 bits Measure register 2 Measure register 1 Measure register 0 cap3 cap2 1 0 mis ds 5 ALS 3210 3210 0123 S Selector Figure 10 6 1 Block Diagram of TML Input related 32 bit Timer 10 6 2 Outline of TML Operation In TML the counter starts counting upon deassertion of reset The counter is a 32 bit up counter where when a measure event signal is entered from an external device the counter value at that point in time is stored in each 32 bit measure register When reset input is deasserted the counter starts operating with a divided by 2 frequency of the internal peripheral clock and cannot be stopped once it has started The counter is idle only when the device remains reset TIN interrupts can be generated by entering an external measurement signal for TMLO only no TIN interr
5. PL RETO 3 SY chive Se oe need oe PX aces She Taek CRDI PESE Se nadie aes EON T tas oe pe ae tt MENOS 5 ca ewe EMEN aa 2 E Vos au ec Lape cam ok le ga m so i gt do gt o wn 9 S S B Z 1 1 O r Z O I E 5 9 o g A o E y 5 WL jl pee de z gt a a eic DN o E RS 5 RS 5 I I CER PB Q ocn DN Pq ie ata ch are ele ur ES m PRg 2 4 BGP ees oc re Y Or cc re e 5 o 5 c z i o ls i E S a z 1 IO 1 e E o e E I lt x O e co lt O m co 16 Ver 0 10 Don t Care 16 15 Circles O above indicate points at which signals are sampled Note 2 BCLK is not output Note 1 Figure 16 3 10 Read Write Timing for Access with 2 Internal Wait Cycles 1 6 WAIT CONTROLLER 16 3 Typical Operation of the Wait Controller
6. DMSS9ITST H 0080 0408 DMS9ITMK H 0080 0409 DMA9UDF Data bus 5 source inputs F F DMA transfer DMITMK9 Jiu Level interrupt 1 ou F F DMA8UDF ke F F DS DMITMK8 O12 F F DMA7UDF DMITST7 F F DE DMITMK7 b13 F F DMA6UDF DMITST6 F F DMITMK6 914 F F DMASUDF DMITSTS F F 9 DMITMK5 015 F F Figure 9 2 4 Block Diagram of DMA Transfer Interrupt 1 9 26 Ver 0 10 9 DMAC 9 3 Functional Description of the DMAC 9 3 Functional Description of the DMAC 9 3 1 Cause of DMA Request For each DMA channel channels 0 to 9 DMA transfer can be requested from multiple sources There are various causes or sources of DMA transfer so that DMA transfer can be started by a request from internal peripheral I O started in software by a program or can be started upon completion of one transfer or all transfers in a DMA channel cascade mode The cause of DMA request is selected using the cause of request select bit provided for each channel REQSLn DMAn Channel Control Register bits D2 D3 The table below lists the causes of DMA requests in each channel Table 9 3 1 Causes of DMA Requests in DMAO and Generation Timings REQSLO Cause of DMA Request DMA Request Generation Timing 0 0 Software start When any data is written to DMAO Software Request or one DMA2 transfer co
7. P64 SBI P221 CRX Data bus DBO DB15 SBI lt 7 P72 HREQ Direction P register 3H Data bus A Port output 4 O DBO DB15 latch PID m 77 Operation 4 mode register HREQ 4 7 Input function enable Note O denotes pins Figure 8 4 2 Port Peripheral Circuit Diagram 2 8 23 Ver 0 10 INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 4 Port Peripheral Circuits P71 WAIT Direction 45 register 1 DP Data bus Port output 4 15 latch m m 77 gt a Operation mode register WAIT lt Input function enable P70 BCLK WR P73 HACK P74 RTDTXD Direction P76 RTDACK register P82 TXD0 Dp P85 TXD1 Data bus_ 4 Port output d 4 O DBO DB15 latch n P93 P97 016 020 La Y gt e 4 P100 P107 TO8 TO15 7 P110 P117 TOO TO7 P174 TXD2 di P220 CTX Operation mode register Peripheral function input Input function enable Note O denotes pins Figure 8 4 3 Port Peripheral Circuit Diagram 3 8 24 Ver 0 10 INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 4
8. Clock bus Input event bus Output event bus 3210 3210 0123 TIO 0 E ge ud 11 IRQ12 16 bits p 4 TIN30 TIN3S 5 1 dr o TO 12 1 udf 155 je SI EFIZ 0 ds j IRQO HSH EF To 13 5 IRQO fr n i 5 14 TO 14 en Hlo tHg IRQ4 Pues ck cap 4 uat eo gt P SHH FIF15 TO 15 1 2 PSCO oO pa internal PSC1 x clock PSC2 o 0 4 4 oo 5 IRQ4 TCLK1 5 e 5 Gk p zs 5 HES F F16 o TO 16 5 5 ar IRO4 CLK2 O74 TCLK2 s lk en cap TIO 6 udf s 5 17 o TO 17 t S ar IRQ4 r p 5 enap MO udfL eHe 18 ep ts IRQS gt tps ck TIO 8 ud ge uS F F19 TO 19 HH S 370 1 1803 ua 5 Ck TIO 9 ud F F20 o TO 20 dr 3210 3210 0123 PSC0 Prescaler F F Output flip flop S Selector Note Reload 1 Register is used in only PWM output mode Figure 10 4 1 Block Diagram of TIO Input Output related 16 bit Timer 10 83 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer 10 4 2 Outline of Each Mode of TIO Each mode of TIO is outlined below For each TIO channel only one of the following modes can be selec
9. 13 19 13 2 6 CAN Error Count Registers ssssssseen 13 20 13 2 7 CAN Baud Rate Prescaler sse 13 21 13 2 8 CAN Interrupt Related Registers 13 22 13 2 9 CAN Mask Registers 13 30 13 2 10 CAN Message Slot Control Registers 13 34 13 2 11 CAN Message 13 38 133 Protocol uiii rir 13 53 19 3 1 CAN Protocol Frame tee eti get nde 13 53 13 4 Initializing the CAN ennt ennt 13 56 13 4 1 Initialization of the CAN 13 56 13 5 Transmitting Data Frames eese nnne 13 59 13 5 1 Data Frame Transmit Procedure 13 59 13 5 2 Data Frame Transmit Operation 13 61 13 5 3 Transmit Abort Function 0 13 62 13 6 Receiving Data Frames 13 63 13 6 1 Data Frame Receive Procedure 13 63 13 6 2 Data Frame Receive Operation 13 65 13 6 3 Reading Out Received Data Frames 13 67 13 7 Transmitting Remote Fra
10. Counter H FFFF Reload register Correction 3 register Interrupt Underflow Note 1 What you actually see in the cycle immediately after reload is the previous counter value and not 7 Note 2 This diagram does not show detail timing information Figure 10 3 17 Example of Counting in TOP Delayed Single shot Output Mode When Count is Corrected When writing to the correction register be careful not to cause the counter to overflow Even when the counter overflows due to correction of counts no interrupt is generated for the occurrence of overflow 10 75 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer Underflow Underflow first time second time Y Y Count clock ae UUL Enable bit E Write to correction register zo HFEF E ER H F000 0008 1 t x ys Counter corrected Counter ES H 0000 2 Ee edt eme Sonst desee o ary Fede gue Eee Reload register H F000 Correction register Indeterminate x H 0008 F F output A Data inverted by Data inverted by underflow underflow 22 TOP interrupt 6 z3 due to underflow Note This diagram does show detail timing information Figure 10 3 18 Typical Operation in TOP Delayed Single
11. 8 bit readout 10 bit readout Shifter ADODTO 10 bit A DO Data Register O ADODT1 10 bit A DO Data Register 1 ADOSIMO 1 Single Mode Register ADODT2 10 bit A DO Data Register 2 ADOSCMO 1 Scan Mode Register ADODTS gt 10 bit A DO Data Register 3 ADODT4 10 bit A DO Data Register 4 ADODTS 4 10 bit A DO Data Register 5 ADODT6 10 bit A DO Data Register 6 ADODT7 m 10 bit A DO Data Register 7 ADODTS8 10 bit A DO Data Register 8 ADODT9 m 10 bit A DO Data Register 9 ADODT10 10 bit A DO Data Register 10 ADODT11 10 bit A DO Data Register 11 ADODT12 10 bit A DO Data Register 12 ADODT13 10 bit A DO Data Register 13 ADODT14 10 bit A DO Data Register 14 Output event bus 3 ADODT15 10 bit A DO Data Register 15 multijunction timer Y Control Circuit 10 bit AD Successive la Mode selection 550 O gt Approximation Hegister Channel selection interrupt request ADOSAR ____ i selection VREFO 2 10 bit D A Converter aep cod DMA transfer request gt DOINO gt DOIN1 5 DOIN2 O gt DOINS O DOIN4 DOIN5 L DOING DOIN7 L2 3 CDI DOIN9 21 3 DON10
12. Read Read 2cycles r gt One cycle 4 12 5 oso osi LLLI TTA WR pn 7 KL 2 DBO DB15 WAT TM Write Write 2 cycles lt One cycle i 4 i BCLK A12 A30 77 50 CS1 2 D 2 RD IH WR E DBO DB15 WAIT Note 1 Circles O above indicate points at which signals are sampled Note 2 BCLK is not output Figure 15 2 5 Read Write Timing for Shortest case External Access 15 10 Ver 0 10 EXTERNAL BUS INTERFACE 15 2 Read Write Operations 15 31 wo Xt xe o gt 522 g ice circ uaa Ea eec eC fe oe a l tc E ss met m edi een ey pe Oe aps Ses tee a A B d MAD RUNE 2 CARERE PY RE Pr ORC m 10 m T e lt 5 m z m m i 6 Q 2 2 E o lt O tn a Don t S o 5 o gt o 5 N Y
13. 8 9 8 3 3 Port Operation Mode Registers 8 10 8 4 Port Peripheral Gircuits erre 8 22 CHAPTER 9 DMAC 9 1 Outline of the DMAC amada nenna 9 2 9 2 DMAC Related Registers 9 4 9 2 1 DMA Channel Control Register 2 9 6 9 2 2 DMA Software Request Generation Registers 9 17 9 2 3 DMA Source Address Registers 9 18 9 2 4 DMA Destination Address Registers 9 19 9 2 5 DMA Transfer Count 9 20 9 2 6 DMA Interrupt Request Status 9 21 9 2 7 DMA Interrupt Mask 9 23 9 3 Functional Description of the DMAC 9 27 9 3 1 Cause of DMA 9 27 9 3 2 DMA Transfer Processing Procedure 9 31 9 3 3 Starting n cer E p i et eo eerie eot 9 32 9 3 4 Channel 9 32 9 3 5 Gaining and Releasing Control of the Internal Bus 9 32 9 3 6 Transfer U
14. When reset Indeterminate gt D BitName Fumton RH 0 PnODT Port PnO data Depending on how the Port Direction Register is set 1 Pn1DT Port Pn1 data When direction bit 0 input mode O 2 Pn2DT Port Pn2 data 0 Port input pin low 3 Pn3DT Port Pn3 data 1 Port input pin high O 4 Pn4DT Port Pn4 data When direction bit 1 output mode 5 Pn5DT Port 5 data 0 Port output latch low O 6 Pn6DT Port Pn6 data 1 Port output latch high 7 Pn7DT Port Pn7 data O O Note 1 The bits listed below have no functions assigned They show a 0 when read writing to these bits has no effect P40 P60 P65 P67 P90 P92 P120 P123 P151 P152 P154 P157 P170 P173 P176 P177 P222 P224 P226 P227 Note 2 Port P64 is available for only input mode Writing to P64DT bit has no effect Note 3 Ports P80 and P81 are available for only input mode Writing to PSODT and P81DT bits has no effect When read P80 and P81 show the MODO and MOD pin levels respectively Note 4 Port P221 is available for only input mode Writing to P221DT bit has no effect Note 5 P14 P16 and P18 P21 do not have data registers 8 8 Ver 0 10 INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 3 Input Output Port Related Registers 8 3 2 Port Direction Registers B PO Direction Register PODIR Address H 0080 0720 E P1 Direction Register P1DIR Address H 0080 0721
15. o n o s 4 4 i 4 4 T E E 5 5 gt Hd EX a A Ry R A gt 8 AAR R RAR A S Y E Y Sin sel e Fei a e NAI mcg 2 gA T g S S o z o E S gt H E aa aa lt 2 2 x LA 8 Sy I s OF A fie x I I P 3 otal ELP on ee PERROS PE 43 E TER Nie ak jr te X 95 8 ES E ig Ez E a en lt lt 5 a a lt 14 L a Joe Lo z e 8 d S 8 c P ES a lt O E 16 Ver 0 10 pn 16 12 Note Circles above indicate points at which signals are sampled Figure 16 3 7 Read Write Timing for Access with 2 Internal and n External Wait Cycles 1 6 WAIT CONTROLLER 16 3 Typical Operation of the Wait Controller 2 When Bus Mode Control Register 1 External read write operations are performed using the address bus data bus and
16. Read ld Read 4 cycles I 3 internal wait cycles lt gt A12 A30 771 TOME a i WR i1 DBO DB15 _ s Wal m M Don t Care Write Write 4 cycles 3 internal wait cycles gt BCLK A12 A30 77 wR IE 7777777777 KL DBO DB15_ war TAT Don t Care Note 1 Circles above indicate points at which signals are sampled Note 2 BCLK is not output Figure 16 3 11 Read Write Timing for Access with 3 Internal Wait Cycles 16 16 Ver 0 10 1 6 WAIT CONTROLLER 16 3 Typical Operation of the Wait Controller Read Read 5 cycles i i 4 internal wait cycles BCLK A12 A30 7 TX 7 cso 51 1 i RD nu c NN WR wH i i DBO DB15 __ 5 TITY bi Don t Care Write Write 5 cycles 4 internal wait cycles BCLK CS0 51 RD EF WR DBO DB15 _ i WAT Don t Care Note 1 Circles O above indicate points at which signals are sam
17. Figure 19 2 1 Configuration of the JTAG Circuit 19 3 Ver 0 10 1 9 JTAG 19 3 JTAG Registers 19 3 JTAG Registers 19 3 1 Instruction Register JTAGIR The Instruction Register JTAGIR is a 6 bit register to hold instruction code This register is set in IR path sequence The instructions set in this register determine the data register to be selected in the subsequent DR path sequence When test is reset to initialize the test circuit the initial value of this register is 6 000010 IDCODE instruction After a test reset the IDCODE Register is selected as the data register until an instruction code is set by an external device In Capture IR state this register always has b 110001 fixed value loaded into it Therefore when in Shift IR state no matter what value was set in this register b 110001 is always output from the JTDO pin sequentially beginning with LSB However this value normally is not handled as instruction code Shown below is outside the scope of guaranteed operations Note that if this operation is performed the device may inadvertently handle b 110001 as instruction code which makes it unable to operate normally Capture IR Exit1 IR Update IR The 32171 s JTAG interface supports the following instructions Three instructions stipulated as essential in IEEE 1149 1 EXTEST SAMPLE PRELOAD BYPASS Device ID register access instruction IDCODE Table 19 3 1 J
18. When reset 00 gt D Bit Name Function R 0 3 No functions assigned 0 4 IRQT2 SIO2 transmit finished 0 Interrupt not requested O A interrupt request status bit 1 Interrupt requested 5 IRQR2 SIO2 receive interrupt 0 Interrupt not requested O A request status bit 1 Interrupt requested 6 7 These bits have no functions assigned 0 W A Only writing a 0 is effective when you write a 1 the previous value is retained Transmit receive interrupt requests from SIO2 are described below Setting the interrupt request status bit This bit can only be set in hardware and cannot be set in software Clearing the interrupt request status bit This bit is cleared by writing a 0 in software Note If the status bit is set in hardware at the same time it is cleared in software the former has priority and the status bit is set When writing to the SIO Interrupt Status Register make sure the bits you want to clear are set to O and all other bits are set to 1 The bits which are thus set to 1 are unaffected by writing in software and retain the value they had before you write 12 9 Ver 0 10 1 2 SERIAL 12 2 Serial I O Related Registers 51003 Interrupt Mask Register SIOSMASK Address H 0080 01012 D8 9 10 11 12 13 14 D15 TOMASK ROMASK RIMASK T2MASK REMASK When reset 00 gt D Bit Na
19. Write BCLK 4 4 Q are a pe FXg sew Vise a gt lt a 02 fr 4 T A lt DES z 5 2 lz c x O m m a Ln Don t Care Circles O above indicate points at which signals are sampled Note 2 BCLK is not output Note 1 Figure 15 2 6 Read Write Timing for Access with 2 Internal and 1 External Wait Cycles Ver 0 10 15 11 1 5 EXTERNAL BUS INTERFACE 15 3 Bus Arbitration 15 3 Bus Arbitration 1 When Bus Mode Control Register 0 When HREQ pin input is pulled low and the hold request is accepted the 32171 goes to a hold state and outputs a low from the HACK pin During hold state all bus related pins are placed in the high impedance state allowing data to be transferred on the system bus To exit the hold state and return to normal operating state release the HREQ signal back high Go i Next bus i 10 i Idle l hold Hold state cycle gt 4 4 gt lt OW cmc 5 25 HREG m O Oe E HACK 12 A30 SS es QN NET rx CS0 CS1
20. DO 1 2 3 4 5 6 D7 519 TINIS18 TINIS17 TINIS16 When reset 00 gt D Bit Name Function R 0 TINIS19 TIN19 interrupt status 0 No interrupt request O A 1 TINIS18 TIN18 interrupt status 1 Interrupt request generated 2 TINIS17 TIN17 interrupt status 3 TINIS16 TIN16 interrupt status 4 7 No functions assigned 0 W A Only writing a 0 is effective when you write a 1 the previous value is retained Bi TIN Interrupt Control Register 5 TINIR5 Address H 0080 023D gt D8 9 10 11 12 13 14 D15 TINIM19 TINIM18 TINIM17 TINIM16 TINIM15 TINIM14 TINIM13 TINIM12 When reset 00 gt D Bit Name Function R 8 19 TIN19 interrupt mask 0 Enables interrupt request 9 18 18 interrupt mask 1 Masks disables interrupt request 10 TINIM17 TIN17 interrupt mask 11 TINIM16 TIN16 interrupt mask 12 TINIM15 reserved Setting this bit has no effect O O 13 TINIM14 reserved 14 TINIM13 reserved 15 TINIM12 reserved 10 42 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer TINIR4 lt H 0080 023C gt 5 lt H 0080 0230 gt TIN19edge Data bus TINIS19 4 source inputs 00 LS MJT input interrupt 3
21. 9 6 H 3FEL 7 9 Ideal conversion characteristic o ZO a Pau lt H 003 2d H 002 i A D conversion characteristic with infinite resolution H 001 H 000 2 VREF VREF VREF VREF 1024 1024 X 1024 1024 1023 VREF VREF 1024 X1022 1024 X1024 gt Analog input voltage V Figure 11 3 4 Ideal A D Conversion Characteristics Relative to the 10 bit A D Converter s Analog Input Voltages 11 37 Ver 0 10 1 1 5 11 3 Functional Description of Converters Full scale Nonlinearity error Actual A D conversion characteristic that contains nonlinearity error gt A D conversion result N Ideal conversion line Full scale gt Along input level Figure 11 3 5 A D Converter s Nonlinearity Error Full scale 3 C i ffset t t onversion line offset to 26 the positive side a a gt E o o a conversion line Conversion line offset to the negative side Offset error Full scale Along input level Figure 11 3 6 A D Converter s Offset Error 11 38 Ver 0 10 CONVERTERS 11 3 Functional Description of Converters Full scale 5 N 9 9 2 o 2 Conversion line where the output 8 code reaches the full scale for analog inp
22. A A D conversion interrupt request or DMA transfer request Figure 11 1 7 Scan Mode Start after Single Mode Execution 11 11 Ver 0 10 1 1 CONVERTERS 11 1 Outline of Converters 3 Conversion restart This special operation mode stops operation being executed in single mode or scan mode and reexecutes the operation from the beginning In the case of single mode the operation being executed is redone by setting Single Mode Register 0 s conversion start bit to 1 again during conversion or comparate operation or by entering a hardware trigger output event bus 3 For scan mode the channel being converted is canceled and A D conversion is restarted from channel 0 by setting Scan Mode Register 075 A D conversion start bit to 1 again during scan operation or by entering a hardware trigger output event bus 3 To restart single mode ADOIN5 conversion Single mode ADOINS 47 conversion restarts A D conversion interrupt request or DMA transfer request ADOIN5 Single mode ADOINS conversion starts Completed 10 bit A DO data register ADODTS Figure 11 1 8 Restarting Conversion during Single Mode Operation To restart operation during ADOIN2 conversion in 4 channel single shot scan mode gt Scan mode restarts m Scan mode 5 conversion starts ADOINO ADOIN1 ADOINO ADOIN1 ADOIN2 ADOIN3 Completed 10 bit A DO data registe
23. ERU IO TORUM j o b CSIO mode with external clock selected Symbol Parameter Condition Rated Value Unit See Figure 21 5 2 3 TOi 0 20 T om 21 15 Ver 0 10 21 ELECTRICAL CHARACTERISTICS 21 5 AC Characteristics 4 Read and write timing T CL eO pue emu fT E LE Valid Read TimeafferBOLK Read Time after BCLK BH VBOLKLSEWE Valid Write Time after BCLK EN BHWL Data Data Output Delay Time after BCLK Delay Time after BCLK ie wre os cup Address Delay Time before Read Chip Select Delay Time before Read Valid Address Time after Read Valid Chip Select Time after Read tpzx RDH DZ Data Output Enable Time after Read td A BLWL Address Delay Time before Write td A BHWL Byte write mode d CS BLWL Chip Select Delay Time before Write d CS BHWL Byte write mode v BLWH A Valid Address Time after Write v BHWH A Byte write mode v BLWH CS Valid Chip Select Time after Write v BHWH CS Byte write mode 21 16 Ver 0 10 21 ELECTRICAL CHARACTERISTICS 21 5 AC Characteristics Read and write timing continued from the preceding page d Data Output Delay Time after Write Byte write mode tv BLWH D Valid Data Output Time after Write tv BHWH D Byte write mode
24. Read Read 4 cycles gt i 3 internal wait cycles gt BCLK 12 0 C80 081 RD BHW BLW DBO DB15 WAT Valley 1 1 Don t Care Write Write 4 cycles zi 3 internal wait cycles 3 n gt BCLK A12 A30 oi LMU RD CH BHW BLW E 26 DB15 WAT C ie viel Don t Care Note Circles O above indicate points at which signals are sampled Figure 16 3 4 Read Write Timing for Access with 3 Internal Wait Cycles 16 9 Ver 0 10 1 6 WAIT CONTROLLER 16 3 Typical Operation of the Wait Controller Read Read 5 cycles gt 4 internal wait cycles a i gt BCLK A12 A30 5 oso os LLLA Me RD BHW BLW DBO DB15 WAT UE Don t Care Write Write 5 cycles 4 internal cycles ita g BCLK A12 A30 3 A RD i BHW BLW C NN DBO DB15 WAT ele vel Pi Don t Care Note Circles O above indicate points at which signals are sampled Figur
25. When reset Indeterminate gt D Bit Name Function R 8 15 DMOTCT DM9TCT DMA transfer count ignored during 32 channel ring buffer mode The DMA Transfer Count Register is used to set the number of times data is transferred in each channel However the value in this register is ignored during ring buffer mode The transfer count is the value set in the transfer count register 1 Because the Transfer Count Register is comprised of a current register the value you get by reading this register is always the current value However if you read this register in a cycle immediately after transfer the value you get is the value that was in the count register before the transfer began When transfer finishes this count register underflows so that the read value you get is H FF If any cascaded channel exists each time one DMA transfer byte or halfword is completed or when all transfers are completed at which the transfer count register underflows transfer in the cascaded channel starts 9 20 Ver 0 10 9 DMAC 9 2 DMAC Related Registers 9 2 6 DMA Interrupt Request Status Registers E DMAO 4 Interrupt Request Status Register DMOAITST Address H 0080 0410 gt DO 1 2 3 4 5 6 D7 DMITST4 DMITST3 DMITST2 DMITST1 DMITSTO When reset 00 gt D Bit Name Function R 0 2 No functions assigned 0 3 DMITST4 DMA4 interrupt request status 0
26. F Fn output data FDn Dn gt F F Note Dn denotes the data Figure 10 2 3 Configuration of the F F Output Circuit 10 22 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer E F F Source Select Register 0 FFSO Address H 0080 0220 DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 EE mmm When reset 0000 gt D Bit Name Function R W 0 2 No functions assigned 0 3 FF15 F F15 source selection 0 TIO4 output O O 1 Output event bus 0 4 FF14 F F14 source selection 0 output O 6 1 Output event bus 0 5 FF13 F F13 source selection 0 TIO2 output 3 1 Output event bus 3 6 FF12 F F12 source selection 0 TIO1 output O O 1 Output event bus 2 7 FF11 F F11 source selection 0 TIOO output O 1 Output event bus 1 8 9 FF10 F F10 source selection OX TOP10 output O O 10 Output event bus 0 11 Output event bus 1 10 11 9 F F9 source selection 0X TOP9 output O O 10 Output event bus 0 11 Output event bus 1 12 13 8 F F8 source selection 00 TOP8 output O O 01 Output event bus 0 10 Output event bus 1 11 Output event bus 2 14 FF7 F F7 source selection 0 TOP7 output O O 1 Output event bus 0 15 FF6 F F6 source selection 0 TOP6 output O O 1 Output event bus 1 Note This register must always be acces
27. 4 pi ing EERO TETAS EEG a ic lt 919 en E z 8 i E a Ao gt og 9 3 oO o S S 2 Write BCLK A12 A30 CSO CS1 DBO DB15 Note Circles above indicate points at which signals are sampled Figure 15 2 2 Read Write Timing for Shortest case External Access Ver 0 10 15 7 15 EXTERNAL BUS INTERFACE 15 2 Read Write Operations Read BCLK A12 A30 CS0 CS1 Write 12 A30 CS0 CS1 Read 4 cycles je gt 2 internal 1 external wait cycles wait cycle i ma gt lt gt 9 Mee dep i Don t Care L Write 4 cycles i gt 2 internal 1 external wait cycles wait cycle FI Ame 4 Don t Care es Note Circles above indicate points at which signals are sampled Figure 15 2 3 Read Write Timing for Access with 2 Internal and 1 External Wait Cycles 15 8 Ver 0 10 1 EXTERNAL BUS INTERFACE 15 2 Read Write Operations 2 When Bus
28. 4 Address H 0080 0071 gt Address H 0080 0072 gt Address H 0080 0073 gt lt Address H 0080 0074 gt Address H 0080 0075 gt Address H 0080 0076 gt Address H 0080 0077 gt Address H 0080 0078 gt Address H 0080 0079 gt Address H 0080 007 gt Address H 0080 007C gt lt Address H 0080 007D gt lt Address H 0080 007E gt B MJT Input Interrupt Control Register 1 IMJTICR1 E MJT Input Interrupt Control Register 2 IMJTICR2 B MJT Input Interrupt Control Register IMJTICR3 B MJT Input Interrupt Control Register 4 IMJTICR4 YS WH 5 9 Ver 0 10 INTERRUPT CONTROLLER ICU 5 3 ICU Related Registers DO 1 2 3 4 5 6 D7 D8 9 10 11 12 13 14 D15 IREQ ILEVEL When reset 07 gt D Bit Name Function R 0 2 No functions assigned 0 8 10 3 IREQ Interrupt request 0 Interrupt is not requested 11 1 Interrupt is requested 4 No functions assigned 0 12 5 7 ILEVEL Interrupt priority level 000 Interrupt priority level 0 Q Q 13 15 001 Interrupt priority level 1 010 Interrupt priority level 2 011 Interrupt priority level 3 100 Interrupt priority level 4 101 Interrupt priority level 5 110 Interrupt priority level 6 111 Interrupt priority level 7 Interrupt disabled state W A Can be set and cleared only when the type of input source is Edge recognized type with only one interrupt source being input
29. gt DOIN11 gt DOIN12L1 DOIN13L1 DOIN14L1 DOIN15Lj gt Successive Approximation type Converter Unit Selector DPPPPPPPPPPPPPPDL Figure 11 1 1 Block Diagram of A DO Converter 11 4 Ver 0 10 1 1 CONVERTERS 11 1 Outline of Converters 11 1 1 Conversion Modes The A D converters have two conversion modes A D conversion mode and Comparator mode 1 A D conversion mode In A D conversion mode the analog input voltage in a specified channel is converted into digital quantity In single mode A D conversion is performed on a channel selected by the Single Mode Register 1 analog input pin select bit In scan mode A D conversion is performed on channels selected by Scan Mode Register 1 according to settings of Scan Mode Register 0 The conversion result is stored in each channel s corresponding 10 bit A D Data Register Also 8 bit A D conversion results can be read from each 8 bit A D Data Register An A D conversion interrupt request or a DMA transfer request can be generated at completion of A D conversion when in single mode or when operating in scan mode at completion of one cycle of scan loop 2 Comparator mode In comparator mode the analog input voltage in a specified cha
30. Figure 10 3 7 Outline Diagram of TOP8 10 Clock Enable Inputs 10 58 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer 10 3 5 Counters TOPOCT TOP10CT TOPO Counter TOPOCT lt Address H 0080 0240 gt E TOP1 Counter TOP1CT Address H 0080 0250 TOP2 Counter TOP2CT Address H 0080 0260 TOP3 Counter Address H 0080 0270 E Counter TOPACT Address H 0080 0280 TOP5 Counter 5 Address H 0080 0290 TOP6 Counter TOP6CT Address H 0080 02 0 gt Counter TOP7CT Address H 0080 02 0 gt E TOP8 Counter TOP8CT Address H 0080 02 0 gt TOP9 Counter TOP9CT Address H 0080 02D0 gt TOP10 Counter TOP10CT Address H 0080 02 0 gt DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 TOPOCT TOP10CT When reset Indeterminate gt D Bit Name Function R 0 15 10 16 bit counter value Note This register must always be accessed halfwords The TOP counters are a 16 bit down counter After the timer is enabled by writing to the enable bit in software or by external input the counter starts counting synchronously with the count clock 10 59 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer 10 3 6 Reload Registers TOPORL TOP10RL TOPO Reload Register TOPORL Address H 0080 0242 E TOP1 Reload Register TOP1RL Address H 0080 0252
31. M Any event other than SBI SBI EIT handler Y Hardware gt Save to stack preprocessing PSW gt 6 PSW y Save PSW to stack h Save general purpose registers to stack System Break Interrupt processing Program being executed N event occurs Program terminated or system reset Processing by EIT handler m ERR y Restore general purpose registers y Hardware B PSW gt PSW Restore PSW postprocessing BPC PC T Restore BPC Figure 4 12 3 Example of EIT Processing 4 24 Ver 0 10 CHAPTER 5 INTERRUPT CONTROLLER ICU 5 1 5 2 5 3 5 4 5 5 5 6 Outline of the Interrupt Controller ICU Interrupt Sources of Internal Peripheral ICU Related Registers ICU Vector Table Description of Interrupt Operation Description of System Break Interrupt SBI Operation INTERRUPT CONTROLLER ICU 5 1 Outline of the Interrupt Controller ICU 5 1 Outline of Interrupt Controller ICU The Interrupt Controller ICU manages maskable interrupts from internal peripheral I Os and a system break interrupt SBI maskable interrupts from internal peripheral I Os are notified to the 2 CPU as external interrupts El There total of 31 interrupt sources for the mask
32. 3 8 3 4 2 Special Function Register SFR 3 8 3 5 EIT Vector ENUY e 3 22 3 6 ICU Vector Table 3 23 3 7 Note about Address Space eese nennen nnn nnn nnn 3 25 CHAPTER 4 EIT 4 1 Outline of 4 2 A D dii mer 4 3 AOA EXCODUOD tet eret tete eiie 4 3 4 2 2 Interr pta tore epe 4 3 4 2 3 Trap iate etit rne ete ed dre Ha cuve ae a ee da 4 3 4 3 EIT Processing Procedure 4 4 4 4 EIT Processing Mechanism 4 6 4 5 Acceptance of EIT 4 7 4 6 Saving and Restoring the PC and 4 8 4 7 EIT Vector ENUY 4 10 4 8 Exception Processing 4 11 4 8 1 Reserved Instruction Exception 4 11 4 8 2 Address Exception
33. 10 15 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer 1 Functions of TCLK input processing control registers Item Function 1 2 internal peripheral clock 1 2 internal peripheral clock gt Rising clock edge TCLK DS LED m Count clock Falling clock edge TCLK Count clock Both edges Low level TCLK PEE 1 2 internal peripheral clock 4 5 Count High level TCLK 1 2internal peripheral clock 10 16 Ver 0 10 10 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer 2 Functions of TIN input processing control registers Item Function Rising edge 4 4 1 TIN 422 Internal edge signal
34. 10 98 Ver 0 10 10 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer E TIO8 Control Register TIO8CR Address H 0080 038A DO 1 2 3 4 5 6 D7 TIO8CKS 5 TIO8M When reset H 00 gt D Bit Name Function R 0 1 TIO8CKS 00 Clock bus 0 TIO8 clock source selection 01 Clock bus 1 10 Clock bus 2 11 Clock bus 3 2 4 TIO8ENS 8 enable measure input source selection 100 101 110 111 selection No selection Input event bus 1 Input event bus 2 Input event bus 3 5 7 TIO8M TIO8 operation mode selection 000 001 010 011 100 101 11X Single shot output mode Delayed single shot output mode Continuous output mode PWM output mode Measure clear input mode Measure free run input mode Noise processing input mode Note Always make sure the counter has stopped and is idle before setting or changing operation modes 10 99 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer TIO9 Control Register 9 lt Address H 0080 038B gt D8 9 10 11 12 13 14 D15 TIO9CKS TIO9ENS TIO9M When reset H 00 gt D Bit Name Function R 8 No functions assigned 0 9 10 9 5 00 Clock bus 0 TIO9 clock source selection 01 Clock bus 1 10 Clock bus 2 11 Clock bus 3 11 1
35. H 0080 0420 DMA1 Channel Control Register DM1CNT DMA1 Transfer Count Register DM1TCT H 0080 0422 DMA1 Source Address Register DM1SA H 0080 0424 Destination Address Register DM1DA H 0080 0426 H 0080 0428 DMA6 Channel Control Register DM6CNT DMAG Transfer Count Register DM6TCT H 0080 042A DMA6 Source Address Register DM6SA H 0080 042C DMA6 Destination Address Register DM6DA H 0080 042 Blank addresses are reserved areas Figure 3 4 8 Register Mapping of the SFR Area 6 3 15 Ver 0 10 3 ADDRESS SPACE 3 4 Internal ROM SFR Area Address 40 Address 1 Address DO H 0080 0430 DMA2 Channel Control Register DM2CNT Transfer Count Register DM2TCT H 0080 0432 DMA2 Source Address Register DM2SA H 0080 0434 DMA Destination Address Register DM2DA H 0080 0436 H 0080 0438 DMA7 Channel Control Register DM7CNT DMA7 Transfer Count Register DM7TCT H 0080 043A DMA7 Source Address Register DM7SA H 0080 043C DMA7 Destination Address Register DM7DA H 0080 043E H 0080 0440 DMAS Channel Control Register DM3CNT DMAS Transfer Count Register DM3TCT H 0080 0442 DMA3 Source Address Register DM3SA 0080 0444 Destination Address Register DM3DA H 0080 0446 H 0080 0448 DMA8 Channel Control Register DM8CNT DMAS Transfer Count Register DM8TCT H 0080 044A DMAS8 Source Address Register DM8SA H 0080 044
36. JTCK JTMS 2 2 9 c o o 7 2 4 5 Tle state o 2 2159 7 oO L 25 JTDI Don t Care Instruction code 6 bits Eos 111 High impedance JTDO 5 1 Don t Care High impedance Shift output from the instruction register is JTDO is output at fall of fixed to b 110001 JTCK in Shift IR state code in the instruction Finished storing instruction register s shift register stage Figure 19 4 3 IR Path Sequence 19 9 Ver 0 10 1 9 JTAG 19 4 Basic Operation of JTAG 19 4 3 DR Path Sequence The data register that was selected during the IR path sequence prior to the DR path sequence is operated on to inspect or set data in it The DR path sequence is performed following the procedure described below 1 Enter JTMS high for a period of one JTCK cycle from Run Test Idle state to go to Select DR Scan state Which data register will be selected at this time depends on the instruction that was set during the IR path sequence performed prior to the DR path sequence 2 Set JTMS low to go to Capture DR state At this time the result of boundary scan test or the fixed data defined for each register is set in the data register s shift register stage 3 Subsequently enter JTMS low to go to Shift DR state In Shift DR state the DR value is shifted right one bit every cycle and th
37. 14 12 14 3 8 Resetting the RTD uiuit perro nette 14 13 14 4 Typical Connection with the 14 14 CHAPTER 15 EXTERNAL BUS INTERFACE 15 1 External Bus Interface Related Signals esses 15 2 15 2 Read Write Operations 15 6 15 3 Bus Arbitration 15 12 15 4 Typical Connection of External Extension Memory 15 14 CHAPTER 16 WAIT CONTROLLER 16 1 Outline of the Wait 16 2 16 2 Wait Controller Related Registers esent 16 4 16 2 1 Wait Cycles Control 16 5 16 3 Typical Operation of the Wait Controller eene 16 6 10 CHAPTER 17 RAM BACKUP MODE ues aerin c re 17 2 17 2 Example of RAM Backup when Power is 17 2 17 2 1 Normal Operating 17 8 17 2 2 Backup State onn eter 17 4 17 3 Example of RAM Backup for Saving Power Consumption 17 5 17 3 1 Normal Operating State sss 17 6 17 3 2 RAM Backup State 17 7 17 3 3 Precautions to Be Observed at Pow
38. 2 Hi Z Ede cx M lt lt Hi Z m cup ecc nl acci cues ec o n 0 15 02 0 CO 1 4 Hi Z gt WAIT Note 1 Circles above indicate points at which signals are sampled Note 2 Hi z indicate the high impedance state Note 3 Idle cycles are inserted only when the hold state is assumed after external lead access Figure 15 3 1 Bus Arbitration Timing 15 12 Ver 0 10 15 EXTERNAL BUS INTERFACE 15 3 Bus Arbitration 2 When Bus Mode Control Register 1 When HREQ pin input is pulled low and the hold request is accepted the 32171 goes to a hold state and outputs a low from the HACK pin During hold state all bus related pins are placed in the high impedance state allowing data to be transferred on the system bus To exit the hold state and return to normal operating state release the HREQ signal back high BCLK HREQ HACK 12 A30 50 CS1 RD WR BHW BLW DBO DB15 WAIT Go Next bus us cycle Idle to Hold state Return cycle p lt don OO 4 AM nam x t pepe ae Sa caria 73 ee e
39. Port P77 operation mode 1 RTDCLK 8 10 Ver 0 10 8 INPUT OUTPUT PORTS AND FUNCTIONS 8 3 Input Output Port Related Registers E P8 Operation Mode Register P8MOD Address H 0080 0748 DO 1 2 3 4 5 6 D7 P82MOD P83MOD P84MOD P85MOD P86MOD P87MOD When reset 00 gt D Bit Name Function R Ww 0 1 No functions assigned 0 2 P82MOD 0 P82 Port P82 operation mode 1 TXDO 3 P83MOD 0 P83 Port P83 operation mode 1 RXDO 4 P84MOD 0 P84 Port P84 operation mode 1 SCLKIO SCLKOO 5 P85MOD 0 P85 O Port P85 operation mode 1 TXD1 6 P86MOD 0 P86 Port P86 operation mode 1 RXD1 7 P87MOD 0 P87 Port P87 operation mode 1 SCLKH SCLKO1 Note Ports P80 and P81 are not accommodated 8 11 Ver 0 10 8 INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 3 Input Output Port Related Registers E P9 Operation Mode Register P9MOD Address H 0080 0749 gt D8 9 10 11 12 13 14 D15 P93MOD P94MOD P95MOD P96MOD P97MOD When reset 00 gt D Bit Name Function R 8 10 No functions assigned 0 11 P93MOD 0 P93 O O Port P93 operation mode 1 TO16 12 P94MOD 0 P94 O O Port P94 operation mode 1 TO17 13 P95MOD 0 P95 Port P95 operation mode 1 TO18 14 P96MOD 0 P96 Port P96 operation mode 1 TO19 15 P97MOD 0 P97 O Port P
40. SIO1 Transmit Buffer Register S1TXB SIO1 Receive Buffer Register S1RXB SIO1 Receive Control Register S1RCNT SIO1 Baud Rate Register S1BAUR C SIO2 Transmit Control Register 52 SIO2 Transmit Receive Mode Register S2MOD 5102 Transmit Buffer Register S2TXB SIO2 Receive Buffer Register S2RXB SIO2 Receive Control Register S2RONT SIO2 Baud Rate Register S2BAUR Blank addresses are reserved Figure 12 2 1 Serial Related Register 12 6 Ver 0 10 1 2 SERIAL I O 12 2 Serial Related Registers 12 2 1 SIO Interrupt Related Registers 1 Selecting the cause of interrupt Interrupt signals sent from each SIO to the ICU Interrupt Controller are broadly classified into transmit interrupts and receive interrupts Transmit interrupts are generated when the transmit buffer is empty Receive interrupts are either receive finished interrupts or receive error interrupts as selected by the Cause of Receive Interrupt Select Register SIO3SEL Note No interrupt signals are generated unless interrupts are enabled by the SIO Interrupt Mask Register after enabling the TEN transmit enable bit or REN receive enable bit for the corresponding SIO 2 Precautions on using transmit interrupts Transmit interrupts are generated when the corresponding TEN transmit enable bit is enabled while the SIO Interrupt Mask Register is set
41. Transmit completed B 0000 0001 Note B 1000 0001 Note When in this state data can be written to the message slot Figure 13 5 2 Operation of the CAN Message Slot Control Register when Transmitting Data Frames 13 5 3 Transmit Abort Function The transmit abort function is used to cancel a transmit request that has once been set This is accomplished by writing H OF to the CAN Message Slot Control Register for the slot concerned When transmit abort is accepted the CAN module clears the CAN Message Slot Control Register s TRSTAT Transmit Receive Status bit to 0 allowing for data to be written to the message slot following shows conditions under which transmit abort is accepted Conditions When the target message is waiting for transmission When a CAN bus error occurs during transmission When the CAN module lost bus arbitration 13 62 Ver 0 10 CAN MODULE 13 13 6 Receiving Data Frames 13 6 Receiving Data Frames 13 6 1 Data Frame Receive Procedure The following describes the procedure for receiving data frames 1 Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the slot in which you want to receive by writing H OO to the register 2 Confirming that reception is idle Read the CAN Message Slot Control Register after being initialized and check the TRSTAT Transmit Receive Status bit to see that reception has stop
42. When data reception is completed or the transmit buffer becomes empty the serial I O can generate a DMA transfer request signal 5 Built in Real Time Debugger RTD The Real Time Debugger RTD provides a function for the M32R E s internal RAM to be accessed directly from an external device The debugger communicates with external devices through its exclusive clock synchronized serial I O By using the RTD you can read the contents of the internal RAM or rewrite its data from an external device independently of the M32R The debugger can generate an RTD interrupt to notify that RTD based data transmission or reception is completed 6 Eight level interrupt controller The interrupt controller manages interrupt requests from each internal peripheral I O by resolving interrupt priority in eight levels including an interrupt disabled state Also it can accept external interrupt requests due to power down detection or generated by a watchdog timer as a System Break Interrupt SBI 7 Three operation modes The M32R E has three operation modes single chip mode extended external mode and processor mode The address space and external pin functions of the M32R E are switched over according to a mode in which it operates The MODO and MOD pins are used to set a mode 8 Wait controller The wait controller supports access to external devices by the M32R In all but single chip mode the extended external area pro
43. Write to Write to transmit transmit Cleared buffer buffer register register data data Transmit buffer empty bit T Transferred from Cleared when transmission transmit buffer to of last data is completed transmit shift register Es transmission starts Transmit status bit First data h4 Next data sTXD7x A X DO SP D7X V XDOY SP Note 4 Upon transmit interrupt Note 2 4 next data is written A Note 2 Note 5 SIO transmit interrupt 9 i T x 5 Note 1 i Interrupt request accepted Note 3 Processing by software ER Interrupt generation Note 1 Change of the Interrupt Controller SIO Transmit Interrupt Control Register interrupt request bit Note 2 When transmit buffer empty interrupt is enabled DMA transfer can also be requested at the same timing Note 3 The Interrupt Controller IVECT register is read or SIO Transmit Interrupt Control Register interrupt request bit cleared Note 4 Transmit interrupt request is generated when transmission is enabled Note 5 Even after transmit data is written to the transmit buffer a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied Figure 12 6 6 Example of UA
44. ee ze H 0005 E000 S bank 94 4Kbytes H 0005 F000 S bank 95 4Kbytes Note 1 If the Pseudo Flash Emulation Enable bit is enabled while the same bank area is set in multiple Pseudo Flash Bank Registers the internal RAM area 8 or 4 Kbytes to be allocated is selected by priority FELBANKO gt FESBANKO gt FESBANK 1 Note 2 When you access the 4 Kbyte area S bank selected by Pseudo Flash S Bank Register 0 1 you actually are accessing the internal RAM area During pseudo flash emulation mode the RAM can be read and written to from both the internal RAM and the selected pseudo flash memory areas Figure 6 7 5 Pseudo Flash Emulation Areas of the M32171F3 Divided in Units of 4 Kbytes 6 43 Ver 0 10 INTERNAL MEMORY 6 7 Virtual Flash Emulation Function L bank flash memory Start address of bank in L bank address LBANKAD bit set value L bank 0 H 0000 0000 H 00 NOTE L bank 1 H 0000 2000 H 02 L bank 2 H 0000 4000 H 04 tt L bank 62 H 0007 C000 L bank 63 H 0007 E000 H 7E Note Set the seven bits A12 A18 of the start address 32 bit of each L bank of flash memory divided every 8 Kbytes in the Virtual Flash L Bank Register s L bank address LBANKAD bits Figure 6 7 6 Values Set in the M32171F4 s Virtual Flash Bank Register when Divided in Units of 8 Kbytes S bank flash memory
45. en OP 9 udf 4 TO9 TE d IRQS en TOP 10 udi e S F F10 O TO 10 RR IRQ12 IRQ0 5 O 11 V rol i F F11 tors 9 ewcap 100 4 5 5 5 IRQO oed en cap TIO 1 udt 4 Lo HS HEF TO 12 S T IRQO nr o 1 458 H EF13I 0 TO 13 enicap 2 udf 2 0 S IRQO dr i n S E F14 0 TO 14 en cap udf 4 0 4 d gt IRQ4 5 cl TIO 4 udt 4 4 en cap t i S HE F15 O TO 15 1 2 internal PSC0 H1 g peripheral t Pset 1 ine clock PSC2 07o 4 i sc IRQ4 TCLK1 O TCLK1S te S T en cap 5 t s F F16 o TO 16 Fi S IRQ4 TCLK2 O TCLK2S S clk 6 ESI EF7 0o TO 17 1 Hs IRQ4 fe 5 CK TIO 7 ud i 15 18 1 5 DRQO 5 TIO 8 ud 1 S H FF1190 TO 19 te S Lo EP l In 9 en cap 9 ud F F20 O TO 20 oF 5 3210 3210 0123 5 0 2 Prescaler F F Output flip flop S Selector Note 1 IRQO 7 and IRQ9 12 are interrupt signals with the same number representing interrupts of the same group see Table 10 1 2 DRQ 0 2 DRQ4 7 DRQ12 and DRQ13 DMA request signals to the DMAC see Table 10 1 3 ADOTRG is a trigger signal to the A D converter see Table 10 1 4 Note 2 Indicates timer input pin edge selection output Note 3 Indicates input
46. 1 IREQ Interrupt Request bit D3 or D11 When an interrupt request from some internal peripheral I O occurs the corresponding IREQ Interrupt Request bit is set to 1 This bit can be set and cleared in software for only edge recognized interrupt sources and not for level recognized interrupt sources Also when the IREQ bit is set by an interrupt request generated by an edge recognized interrupt source it is automatically cleared to 0 by reading out the Interrupt Vector Register IVECT not cleared in the case of level recognized interrupt Sources If the IREQ bit is cleared in software at the same time it is set by an interrupt request generated clearing in software has priority Also if the IREQ bit is cleared by reading out the IVECT register at the same time it is set by an interrupt request generated clearing by a read of IVECT has priority 5 10 Ver 0 10 INTERRUPT CONTROLLER ICU 5 3 ICU Related Registers Interrupt request from each peripheral function set D3 11 set clear Data bus F F Interrupt enabled D5 7 13 15 3 ips Interrupt priority evels 0 resolving circuit Figure 5 3 2 Interrupt Control Register Configuration Edge recognized Type Group Interrupt request from each peripheral function Group interrupt uS Read only circuit Data bus D3 11 12 n di Interrupt enabled
47. 2 Page Program command Flash memory is programmed one page at a time each page consisting of 256 bytes lower addresses H 00 to H FF To write data to the flash memory i e to program the flash memory write the program command H 4141 to any address of the internal flash memory and then the program data to the address to which you want to write With the Page Program command you cannot write to the protected blocks Page Program is automatically performed by the internal control circuit and the completion of programming can be verified by checking the Flash Status Register 1 FSTAT1 FSTAT bit Refer to Section 6 4 2 Flash Status Registers While the FSTAT bit 1 the next programming can not be performed 3 Lock Bit Program command Flash memory can be protected against program erase one block at a time The Lock Bit Program command is provided for protecting memory blocks Write the Lock Bit Program command data H 7777 to any address of the internal flash memory Next write the Verify command data H DODO to the last even address of the block you want to protect and this memory block is protected against program erase To remove protection disable lock bit effectuated protection using the Flash Control Register 2 FCNT2 FPROT bit see Section 6 4 3 Flash Control Registers and erase the block whose protection you want to remove The content of this memory block is also erased The table below lists the target blocks
48. CANO Message Slot 2 Data Length Register COMSL2DLC CANO Message Slot 2 Data 0 COMSL2DTO CANO Message Slot 2 Data 1 COMSL2DT1 CANO Message Slot 2 Data 2 COMSL2DT2 CANO Message Slot 2 Data 3 COMSL2DT3 CANO Message Slot 2 Data 4 COMSL2DT4 CANO Message Slot 2 Data 5 COMSL2DT5 CANO Message Slot 2 Data 6 COMSL2DT6 CANO Message Slot 2 Data 7 COMSL2DT7 CANO Message Slot 2 Time Stamp COMSL2TSP CANO Message Slot Standard IDO COMSL3SIDO CANO Message Slot 3 Standard ID1 COMSL3SID1 CANO Message Slot Extended IDO COMSL3EIDO CANO Message Slot 3 Extended ID1 COMSL3EID1 CANO Message Slot 3 Extended 2 COMSL3EID2 CANO Message Slot 3 Data Length Register COMSL3DLC CANO Message Slot 3 Data 0 COMSL3DTO CANO Message Slot 3 Data 1 COMSL3DT1 CANO Message Slot 3 Data 2 COMSL3DT2 CANO Message Slot 3 Data 3 COMSL3DT3 CANO Message Slot 3 Data 4 COMSL3DT4 CANO Message Slot 3 Data 5 COMSL3DT5 CANO Message Slot 3 Data 6 COMSL3DT6 CANO Message Slot Data 7 COMSL3DT7 CANO Message Slot 3 Time Stamp COMSL3TSP CANO Message Slot 4 Standard IDO COMSL4SIDO CANO Message Slot 4 Extended IDO COMSL4EIDO CANO Message Slot 4 Standard ID1 COMSL4SID1 CANO Message Slot 4 Extended ID1 COMSL4EID1 CANO Message Slot 4 Extended 2 COMSL4EID2 CANO Message Slot 4 Data Length Register COMSL4DLC CANO Message Slot 4 Da
49. Enable bit Enabled by writing to enable bit Underflow Underflow or by external input first time second time Y Y Y Down count E Down count startingfrom reload 0 register i set value H A000 i Down countstarting from reload 1 register t starting from reload 0 register val set value setvalue F F output H A000 H C000 Data inverted Data inverted Data inverted by underflow by underflow by enable 2 lt PWM output period y Note This diagram does not show detail timing information Figure 10 4 11 Typical Operation in PWM Output Mode 10 113 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer 2 Reload register updates in TIO PWM output mode In PWM output mode when the timer remains idle reload 0 and reload 1 registers are updated at the same time data are written to the registers But when the timer is active reload 1 register is updated by updating reload 0 register However when you read reload 0 and reload 1 registers the values you get are always the data written to the registers lt Internal bus Reload 1 TIOnRL1 Reload1WR ReloadOWR Reload 1 Buffer TI
50. PC BPC Hardware PSW gt B PSW preprocessing BPC B PSW and general purpose instruc tion registers saved to stack Program suspended EIT request accepted Program execution restarted Instruction Instruction D processing completed type Instruction processing canceled type El TRAP RIE AE Hardware postprocessing User created EIT handler S System Break Interrupt processing BI Processing registers B PSW handler General purpose RTE and BPC restored from stack ton instruc Program terminated or system is reset Note B PSW denotes the BPSW field of the PSW register Figure 4 3 1 Outline of EIT Processing Procedure B PSW gt PSW PC 4 4 Ver 0 10 4 3 EIT Processing Procedure When an EIT is accepted the M32R E saves the PC and PSW as will be described later and branches to the EIT vector The EIT vector has an entry address assigned for each EIT This is where the BRA branch instruction note that these are not branch address for the EIT handler is written In the M32R E s hardware preprocessing only the contents of the PC and PSW registers are transferred to the backup registers BPC register and the BPSW field of the PSW register and no other operations are performed Therefore please make sure the BPC register the PSW register including the BPS
51. Receive enable bit SIO Receive Control Register i Cleared Y N st X D7X DeX XDOXPARY SP SP eceive status bit Automatically Cleared for each receive operation 2 performed Receive finished bit 6 5 Read from receive buffer AT Receive finished interrupt SIO receive interrupt Note 2 7 Note 1 S be When receive finished interrupt is selected Interrupt request accepted Note 3 When receive error No interrupt request interrupt is selected AA v Processing by software Interrupt generation Note 1 Change of the Interrupt Controller SIO Receive Interrupt Control Register interrupt request bit Note 2 When receive finished interrupt is enabled DMA transfer can also be requested at the same timing Note 3 The Interrupt Controller IVECT register is read or SIO Receive Interrupt Control Register interrupt request bit cleared Figure 12 7 3 Example of UART Reception When Received Normally 12 56 Ver 0 10 12 SERIAL I O 12 7 Receive Operation in UART Mode UART on receive side ud UART on receive side UART on transmit side RXD TXD Receive enable bit SIO Receive Control Register First data reception completed Next data reception completed i STAD7X SLY SPN STA D7X SP Receive buffer not read during this interval Set
52. lt CSIO on transmit side gt SCLKO TXD gt SCLKI External clock selected Transmit clock SCLKO Cleared 4 Set Receive enable bit First data reception Next data reception t completed completed i i RXD DeX Jj X De X j Receive buffer not read during this interval i i Receive finished bit Set Overrun error bit SIO receive interrupt Receive finished interrupt i Overrun error bit cleared Note 4 Note 2 Note 1 When receive finished interrupt is selected When receive error Interrupt request accepted Note 5 AT Receive error interrupt Note 3 T interrupt is selected Processing by software interrupt request bit cleared Interrupt request accepted Note 5 xm Interrupt generation Change of the Interrupt Controller SIO Receive Interrupt Control Register interrupt request bit When receive finished interrupt is enabled When receive error interrupt is enabled Receive enable bit cleared The Interrupt Controller IVECT register is read or SIO Receive Interrupt Control Register Figure 12 4 4 Example of CSIO Reception When Overrun Error Occurred 12 39 Ver 0 10 1 2 SERIAL I O 12 5 Precautions on Using
53. 1 3 CAN MODULE 13 2 CAN Module Related Registers CANOERIST H 0080 1014 CANOERIMK H 0080 1015 CAN bus error occurs Data bus b5 EIS 19 source inputs F F p gt To preceding page EIM b13 F F 2 Level Go to error passive state B ER F F D PIM Go to bus off state of 57 D IM b15 7 E Figure 13 2 7 Block Diagram of CANO Group Interrupts 3 3 13 29 Ver 0 10 13 13 2 9 CAN Mask Registers CANO Global Mask Register Standard 100 COGMSKSO CAN MODULE 13 2 CAN Module Related Registers Address H 0080 1028 2 CANO Local Mask Register A Standard 100 COLMSKASO Address H 0080 1030 CANO Local Mask Register B Standard 100 COLMSKBSO Address H 0080 1038 DO 1 2 3 4 5 6 D7 SIDOM SID1M SID2M SID3M SID4M When reset H 00 gt D Bit Name Function R 0 2 No functions assigned 0 3 7 SIDOM SID4M 0 ID not checked O O Standard IDO to standard ID4 1 ID checked CANO Global Mask Register Standard 101 COGMSKS1 Address H 0080 1029 gt CANO Local Mask Register A Standard 101 COLMSKAS1 Address H 0080 1031 2 E CANO Local Mask Register B Standard ID1 COLMSKBS1 Address H 0080 1039 gt D8 9 10 11 12 13 14 D15 SID5M SID6M SID7M SID8M SID9M SID10M When reset H 00
54. 1 Mbytes 2 H 0030 0000 Y Ghost of Ghost of CS1 area CS1 area 1 Mbytes 1 Mbytes H OOSF FFFF Em S AN TET A lt External extension mode gt lt Processor mode gt Figure 16 1 1 CS0 and CS1 Area Address Map 16 2 Ver 0 10 1 6 WAIT CONTROLLER 16 1 Outline of the Wait Controller When accessing an extended external area the wait controller controls the number of wait cycles to be inserted in bus cycles based on the number of wait cycles set by software and those entered from the WAIT pin The number of wait cycles that can controlled in software is 1 to 4 For external access bus cycles with 1 wait cycle are the shortest bus cycle When the WAIT pin input is sampled low in the last cycle of internal wait cycles set by software the wait cycle is extended as long as the WAIT signal is held low Then when the WAIT signal is released back high the wait cycle is terminated and the next new bus cycle is entered into Table 16 1 2 Number of Wait Cycles that Can be Set by the Wait Controller Extended External Ar a Address Number of Wait Cycles Inserted CSO area H 0010 0000 H 001F FFFF One to 4 wait cycles set by software any number of External extension mode wait cycles entered from WAIT pin H 0000 0000 H 000F FFFF However wait cycles set by software have priority Processor mode Note 1 CS1 area H 0020 0000 H 002F FFFF One to 4 wait cycles set by softwa
55. 12 47 12 6 5 Successive UART Transmission 12 47 12 6 6 Processing at End of UART Transmission 12 48 12 6 7 Transmit 12 48 12 6 8 Transmit DMA Transfer 12 48 12 6 9 Typical UART Transmit Operation 12 50 12 7 Receive Operation in UART Mode seen 12 7 1 Initial Settings for UART Reception 12 52 12 7 2 Starting UART Reception 12 54 12 7 3 Processing at End of UART 12 54 8 12 7 4 Typical UART Receive Operation 12 56 12 8 Fixed Period Clock Output Function esee 12 58 12 9 Precautions on Using UART Mode eene 12 59 CHAPTER 13 CAN MODULE 13 1 Outline of the CAN Module enne nnne nnns 13 2 13 2 CAN Module Related Registers eese 13 4 13 2 1 CAN Control Register 13 8 13 2 2 CAN Status 13 11 13 2 3 CAN Extended ID 13 15 13 2 4 CAN Configuration Register 13 16 13 2 5 CAN Time Stamp Count
56. E P2 Direction Register P2DIR Address H 0080 0722 BW Direction Register P3DIR Address H 0080 0723 E P4 Direction Register PADIR Address H 0080 0724 E P6 Direction Register P6DIR Address H 0080 0726 E P7 Direction Register P7DIR Address H 0080 0727 E P8 Direction Register P8DIR Address H 0080 0728 B P9 Direction Register P9DIR Address H 0080 0729 E P10 Direction Register P10DIR Address H 0080 072A B P11 Direction Register P11DIR Address H 0080 072 gt E P12 Direction Register P12DIR Address H 0080 072C gt E P13 Direction Register P13DIR Address H 0080 072D gt B P15 Direction Register P15DIR Address H 0080 072F gt B P17 Direction Register P17DIR Address H 0080 0731 B P22 Direction Register P22DIR Address H 0080 0736 DO 1 2 3 4 5 6 D7 D8 9 10 11 12 13 14 D15 PnODIR PniDIR Pn2DIR Pn3DIR Pn4DIR Pn5DIR Pn6DIR Pn7DIR Note n 2 0 13 15 17 and 22 not including P5 When reset 00 gt D Bit Name Function R 0 PnODIR Port PnO direction bit 0 Input mode when reset 1 Pn1DIR Port Pn1 direction bit 1 Output mode 2 Pn2DIR Port Pn2 direction bit 3 Pn3DIR Port Pn3 direction bit 4 Pn4DIR Port Pn4 direction bit 5 Pn5DIR Port Pn5 direction bit OO 0 0 OO O OF Or 2 6 Pn6DIR Port Pn6 direction bit 7 Pn7DIR Port directio
57. Leve IRQ10 TINIM19 08 518 d gt TINIM18 b9 F F TIN17edge TINIS17 F F TINIM17 b10 TIN16edge TINIS16 ms 91 16 bii FF Figure 10 2 15 Block Diagram of MJT Input Interrupt 2 10 43 Ver 0 10 10 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer E TIN Interrupt Control Register 6 TINIR6 DO 1 2 Address H 0080 023E gt 3 4 5 6 D7 TINIS23 TINIS22 TINIS21 TINIS20 TINIM23 TINIM22 TINIM21 TINIM20 When reset 00 gt D Bit Name Function R W 0 TINIS23 TIN23 interrupt status 0 No interrupt request O A 1 TINIS22 TIN22 interrupt status 1 Interrupt request generated 2 TINIS21 TIN21 interrupt status 3 TINIS20 TIN20 interrupt status 4 TINIM23 TIN23 interrupt mask 0 Enables interrupt request O O 5 TINIM22 TIN22 interrupt mask 1 Masks disables interrupt request 6 TINIM21 TIN21 interrupt mask 7 TINIM20 TIN20 interrupt mask W A Only writing a 0 is effective when you write a 1 the previous value is retained TINIR6 H 0080 023E gt TIN23edge Data bus TINIS23 4 source inputs MJT input Inpu F F interrupt 3 TINIM23 Level RQ11 b4 TIN22edge TINIS22 b1 F F b INIM22 T b5 F F TIN21edge TINIS21 b2 F F O
58. Table 10 2 3 Signals That Can Be Connected Fed to Each Output Event Bus Line Output Event Bus Connectable Acceptable Signal Note 3 TOP8 4 or TIO8 underflow signal 2 9 or 2 underflow signal 1 TOP7 or TIO1 underflow signal 0 TOP6 or TIOO underflow signal Note For details about the output destinations of output event bus signals refer to Figure 10 1 1 Block Diagram of MJT Timings at which signals are generated to the output event bus by each timer and those generated to the input event bus by TIOS5 6 are shown below Note that they are generated at different timings than those forwarded to output flip flops by timers Table 10 2 4 Timings at Which Signals Are Generated to the Output Event Bus by Each Timer Timer Mode Timings at which signals are generated to the output event bus TOP Single shot output mode When the counter underflows Delayed single shot output mode When the counter underflows Continuous output mode When the counter underflows TIO Note Measure clear input mode When the counter underflows Measure free run input mode When the counter underflows Noise processing input mode When the counter underflows PWM output mode When the counter underflows Single shot output mode When the counter underflows Delayed single shot output mode When the counter underflows Continuous output mode When the counter underflows TMS 16 bit measure input No signal generation function
59. When reset 00 gt D Bit Name Function R 0 MDSEL8 0 Normal mode Selects DMA8 transfer mode 1 Ring buffer mode 1 TREQF8 0 Not requested A DMA8 transfer request flag 1 Requested 2 3 REQSL8 00 Software start Selects cause of DMA8 request 01 MJT input event bus 0 10 Use inhibited 11 Use inhibited 4 TENL8 0 Disables transfer Enables DMA8 transfer 1 Enables transfer 5 TSZSL8 0 16 bits Selects DMA8 transfer size 1 8 bits 6 SADSL8 0 Fixed Selects DMA8 source address direction 1 Incremental 7 DADSL8 0 Fixed O O Selects DMA8 destination 1 Incremental address direction W A Only writing a 0 is effective when you write 1 the previous value is retained 9 14 Ver 0 10 9 DMAC 9 2 DMAC Related Registers E DMAO9 Channel Control Register DM9CNT Address H 0080 0458 DO 1 3 4 5 6 D7 MDSEL9 TREQF9 REQSES TENL9 TSZSL9 SADSL9 DADSL9 lt When reset H 00 gt D Bit Name Function R 0 MDSEL9 0 Normal mode Selects transfer mode 1 Ring buffer mode 1 TREQF9 0 Not requested O A 9 transfer request flag 1 Requested 2 3 REQSL9 00 Software start O O Selects cause of DMA9 request 01 Use inhibited 10 Use inhibited 11 One transfer completed 4 TENL9 0 Disables transfer O Enables 9 transfer 1 Enables transfer 5 TSZSL9 0
60. f the counter stops due to underflow in the same clock period as count is enabled by writing to the enable bit the latter has priority so that count is enabled If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit the latter has priority so that count is disabled Because the internal circuit operation is synchronized to the count clock prescaler output a finite time equal to a prescaler delay is included before F F starts operating after the timer is enabled Write to enable bit Internalclock is A n Prescaler cycle a 4 Count clock 22 22 Enable Delay till prescaler cycle DS F F operation X Figure 10 3 13 Prescaler Delay When writing to the correction register be careful not to cause the counter to overflow Even when the counter overflows due to correction of counts no interrupt is generated for the occurrence of overflow When the counter underflows in the subsequent down count after overflow a false underflow interrupt is generated due to overcounting In the example below the reload register has the initial value H FFF8 set in it When the timer starts the reload register value is loaded into the counter causing it to start counting down In the example diagram here H 0014 is written to the correction register when the counter has c
61. 1 Mbytes Ghost area in 51 1 Mbytes Processor mode gt Figure 3 2 2 M32171F3 Operation Mode and Internal ROM Extended External Areas 3 6 Ver 0 10 3 ADDRESS SPACE 3 3 Internal ROM Extended External Area 3 3 Internal ROM Area and Extended External Area The 8 Mbyte area at addresses H 0000 0000 to H 007F FFFF in the user space accommodates the internal ROM and extended external areas Of this a 4 Mbytes of address space from H 0000 0000 to H 0003 FFFF is the area that the user can actually use All other areas here comprise a 4 Mbytes of ghost area When programming do not use this ghost area intentionally For details on how the internal ROM and extended external areas are located differently depending on the 32171 s operation modes set refer to Section 3 2 Operation Modes 3 3 1 Internal ROM Area The internal ROM is located in the area shown below Also this area has an EIT vector entry and ICU vector table located in it at the beginning Table 3 3 1 Addresses at Which the 32171 s Internal ROM is Located Type Name Size Located address M32171F4 512 Kbytes H 0000 0000 H 0007 FFFF M32171F3 384 Kbytes H 0000 0000 H 0005 FFFF 3 3 2 Extended External Area An extended external area is provided only when extended external mode or processor mode has been selected when setting the 32171 s operation mode For access to this extended external area the 32171 outputs the control signals necessary to a
62. 14 1 2 internal peripheral clock 8MHz 10MHz Figure 18 2 1 Configuration of the Clock Generator Circuit 18 5 Ver 0 10 18 This is a blank page 18 6 OSCILLATION CIRCUIT 18 2 Clock Generator Circuit Ver 0 10 19 1 19 2 19 3 19 4 19 5 19 6 CHAPTER 19 JTAG Outline of JTAG Configuration of the JTAG Circuit JTAG Registers Basic Operation of JTAG Boundary Scan Description Language Precautions about Board Design when Connecting JTAG 19 JTAG 19 1 Outline of JTAG 19 1 Outline of JTAG The 32171 contains a JTAG Joint Test Action Group interface based on IEEE Standard Test Access Port and Boundary Scan Architecture IEEE Std 1149 1a 1993 This JTAG interface can be used as an input output path for boundary scan test boundary scan path For details about IEEE 1149 1 JTAG test access ports refer to the IEEE Std 1149 1a 1993 documentation The functions of JTAG interface related pins mounted on the 32171 are shown below Table 19 1 1 JTAG Pin Functions Note Type Symbol Pin Name yo Function TAP JTCK Test clock Input Clock input to the test circuit JTDI Test data input input Synchronous serial data input pin used to enter test instruction code and test data This input is sampled on rising edges of JTCK JTDO Test data output output Synchronous serial data output pin used to output test instruction code and test data
63. 18 input signal 4 gt selector One DMAt transfer completed Transfer count channel3 Software start Y DN Source Serial 1 00 transmit buffer empty gt request M Serial 1 01 reception completed Ponce Destination MJT TINO input signal gt Transfer count udf channel4 Software start p zi Source 1 One transfer completed aes tas Serial 1 00 reception completed selector gt Destination gt 19 input signal gt Transfer count udf l DMA start Determination block Internal bus arbitration Software start DMA channels One DMAT transfer completed DMA Source All DMAO transfers completed udf gt request Destination 1 Serial 1 02 reception completed selector MJT TIN20 input signal gt DMA channel6 Software start DMA Source Serial l O1 transmit buffer empty j request gt Destination selector One DMAS transfer completed Transfer count udf DMA channel 7 Software start DMA Source Serial 1 02 transmit buffer empty
64. 2 for 16 bit transfer Make sure the DMA Destination Address Register is always accessed in halfwords 16 bits beginning with an even address If accessed in bytes the value read from this register is indeterminate DMODA DM9DA A16 A31 of the destination address By setting this register specify the destination address of DMA transfer in internal space ranging from H 0080 0000 to H 0080 FFFF or in the RAM space The 16 high order bits of the destination address A0 A15 are always fixed to H 0080 Use this register to set the 16 low order bits of the destination address with DO corresponding to A16 and D15 corresponding to A31 9 19 Ver 0 10 9 2 DMAC Related Registers 9 2 5 DMA Transfer Count Registers DMAO Transfer Count Register DMOTCT Address H 0080 0411 2 E DMA1 Transfer Count Register DM1TCT Address H 0080 0421 gt B DMA 2 Transfer Count Register DM2TCT Address H 0080 0431 DMAS Transfer Count Register DM3TCT Address H 0080 0441 gt E DMAA Transfer Count Register DM4TCT Address H 0080 0451 gt E DMAS Transfer Count Register DM5TCT Address H 0080 0419 gt E DMA6 Transfer Count Register DM6TCT Address H 0080 0429 E DMA7 Transfer Count Register DM7TCT Address H 0080 0439 E DMAG Transfer Count Register DM8TCT Address H 0080 0449 gt E Transfer Count Register DM9TCT Address H 0080 0459 gt D8 9 10 11 12 13 14 D15 DMOTCT DM9TCT
65. 21 ELECTRICAL CHARACTERISTICS 21 5 AC Characteristics 88 tr 89 tf 0 8VCCE 0 8VCCE 0 2VCCE 0 2VCCE JTCK JTDI JTMS JRST Note Stipulated values are guaranteed values when the test pin load capacitance CL 80 pF Figure 21 5 10 Input Transition Time on JTAG pins te JTCK gt twUTCKH tw JTCKL JTCK tsu dTDFuTCK 64 thWTCK ITD Data input 0 8VCCE 0 8VCCE JTDI 0 2VCCE 0 2VCCE JTMS td JTCK JTDOV td JTCK JTDOX Data output JTDO tw JTRST JTRST 0 2VCCE Note Stipulated values are guaranteed values when the test pin load capacitance CL 80 pF Figure 21 5 11 JTAG Interface Timing 21 23 Ver 0 10 21 ELECTRICAL CHARACTERISTICS 21 5 AC Characteristics This is a blank page 21 24 Ver 0 10 CHAPTER 22 TYPICAL CHARACTERISTICS 22 1 A D Conversion Characteristics 22 INTERNAL MEMORY 22 1 A D Conversion Characteristics 22 1 A D Conversion Characteristics 1 Test conditions e Ta 40 27 C 125 C Test voltage VCC 5 12 V Double speed mode 2 Measured value Reference value 40 C 512 768 1024 512 758 1024 Vertical axis Conversion error Horizontal axis Analog input
66. 8 TRFIN Transmit Receive Finished bit D7 This bit indicates that the CAN module finished transmitting or receiving When set for transmit slots This bit is set to 1 when the CAN module finished transmitting the data stored in the message slot This bit is cleared by writing a 0 in software However it cannot be cleared when TRSTAT Transmit Receive Status bit 1 When set for receive slots This bit is set to 1 when the CAN module finished receiving normally the data to be stored in the message slot This bit is cleared by writing a 0 in software However it cannot be cleared when TRSTAT Transmit Receive Status bit 1 Note 1 Before you can read received data from the message slot you must clear the TRFIN Transmit Receive Finished bit Note also that if the TRFIN Transmit Receive Finished bit is set to 1 after you read data it means that new receive data was stored while you were reading and the data you read contains an indeterminate value In this case discard the read data clear the TRFIN Transmit Receive Finished bit and read out data again Note 2 The TRFIN Transmit Receive Finished bit has no effect for remote frames so that it is not set when remote frame transmission or reception is completed 13 37 Ver 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers 13 2 11 CAN Message Slots CANO Message Slot 0 Standard 100 COMSLOSIDO Address H 0080 11002 CANO Message Slot 1 Standard IDO COMSL
67. ADOIN12 P132 TIN18 4 ADOIN11 P133 TIN19 54 4 ADOIN10 P134 TIN20 ADOINS P135 TIN21 ADOINS P136 TIN22 ADOIN7 P137 TIN23 ADOING VCCE ADOINS P150 TINO ADOIN4 153 ADOIN3 P41 BLW BLE ADOIN2 P42 BHW ADOIN1 ADOINO VSS AVCCO 43 RD VREFO P44 CS0 P17 DB15 45 CS1 P16 DB14 P46 A13 P15 DB13 PA7 A14 P14 DB12 P220 CTX P13 DB11 a ue yy ovv e 4 4 PN gt gt lt 1 6 18 9 1 P37 A22 lt gt 21 24 lt gt P22 A25 lt gt P23 A26 lt gt P24 A27 4 gt 22 P25 A28 lt gt 23 P26 A29 4 gt 24 PO2 DB2 lt gt 28 P03 DB3 lt gt 29 PO4 DB4 P 30 PO5 DB5 t 31 P06 DB6 4 0 32 P07 DB7 4 gt 33 P10 DB8 9 34 P11 DB9 35 P12 DB10 3 36 P221 CRX Note P225 A12 lt gt OSC VSS OSC VCC P30 A Package 144P6Q 0 5 mm pitch Note Use caution when using these pins because they have a debug event function Figure 1 4 1 Pin Layout Diagram of the M32171FxVFP Top View 1 16 Ver 0 10 Table 1 4 1 Pin Assignments of the M32171FxVFP OVERVIEW 1 4 Pin Layout No Pin Name No Pin Name No Name No Pin Name 1 P221 CRX 41 P17 DB15 81 P73 HACK 121 P126 T
68. Be careful not to clear this bit when no SBI request has been generated Write a 1 and then a 0 to SBIREQ 5 8 Ver 0 10 INTERRUPT CONTROLLER ICU 5 3 ICU Related Registers 5 3 4 Interrupt Control Registers Address H 0080 0060 lt Address H 0080 0067 Address H 0080 0068 Address H 0080 0069 Address H 0080 006 gt lt Address H 0080 006D gt lt Address H 0080 006 gt lt Address H 0080 006F gt lt Address H 0080 0070 gt CANO Transmit Receive amp Error Interrupt Control Register ICANOCR B RTD Interrupt Control Register IRTDCR B 5102 3 Transmit Receive Interrupt Control Register ISIO23CR E DMA5 9 Interrupt Control Register IDMA59CR E A DO Converter Interrupt Control Register IADOCCR Transmit Interrupt Control Register ISIOOTXCR SIOO Receive Interrupt Control Register ISIOORXCR Transmit Interrupt Control Register ISIO1TXCR Receive Interrupt Control Register ISIO1RXCR B 4 Interrupt Control Register IDMA04CR B MJT Output Interrupt Control Register 0 IMJTOCRO E MJT Output Interrupt Control Register 1 IMJTOCR1 E MJT Output Interrupt Control Register 2 IMJTOCR2 E MJT Output Interrupt Control Register IMJTOCR3 W MJT Output Interrupt Control Register 4 IMJTOCR4 E MJT Output Interrupt Control Register 5 IMJTOCR5 B MJT Output Interrupt Control Register 6 IMJTOCR6 E MJT Output Interrupt Control Register 7 IMJTOCR7
69. CANO TEC Register CANO Global Mask Register CANO Local Mask Register A CANO Message Slot 0 15 Control Register CANO Extended ID Register 1 CANO Local Mask CANO Configuration Register B Register CANO Control Register Controller Ver 2 0B CRX 16 bit Timer CANO Time Stamp Register Acceptance Filtering Message Memory Message ID Data length code 1 2 3 Message data 4 Time stamp CANO Slot Status Register CANO Slot Interrupt Control Register CANO Error Interrupt Control Register Interrupt Control Circuit CANO Interrupt gt Figure 13 1 1 Block Diagram of the CAN Module 13 3 Ver 0 10 13 CAN MODULE 13 2 CAN Module Related Registers 13 2 CAN Module Related Registers The diagram below shows a CAN module related register map Address 40 Address 41 Address DO D7 D8 D15 H 0080 1000 CANO Control Register CANOCNT H 0080 1002 CANO Status Register CANOSTAT H 0080 1004 CANO Extended ID Register CANOEXTID H 0080 1006 CANO Configuration Register CANOCONF H 0080 1008 CANO Time Stamp Count Register CANOTSTMP H 0080 100A CANO Receive Error Count Register CANOREC CANO Transmit Error Count Register CANOTEC H 0080 100C CANO Slot Interrupt Status Register CANOSLIST H 0080 100E H 0080 1010 CANO Slot
70. D5 7 13 15 3 ILEVEL c gt Interrupt priority Levels 0 7 resolving circuit Figure 5 3 3 Interrupt Control Register Configuration Level recognized Type 5 11 Ver 0 10 INTERRUPT CONTROLLER ICU 5 3 ICU Related Registers 2 ILEVEL Interrupt Priority Level D5 D7 or D13 D15 These bits set the priority levels of interrupt requests from each internal peripheral I O Set priority level 7 to disable interrupts from some internal peripheral I O or priority levels 0 6 to enable interrupts When an interrupt occurs the interrupt controller resolves priority between this interrupt and other interrupt sources based on ILEVEL settings and finally compares its priority with the IMASK value to determine whether to forward an El request to the CPU or keep it pending The table below shows the relationship between ILEVEL settings and the IMASK values at which interrupts are accepted Table 5 3 1 ILEVEL Settings and Accepted IMASK Values ILEVEL values set IMASK values at which interrupts are accepted 0 ILEVEL 000 Accepted when IMASK is 1 7 1 ILEVEL 001 Accepted when IMASK is 2 7 2 ILEVEL 010 Accepted when IMASK is 3 7 3 ILEVEL 011 Accepted when IMASK is 4 7 4 ILEVEL 100 Accepted when IMASK is 5 7 5 ILEVEL 101 Accepted when IMASK is 6 7 6 ILEVEL 110 Accepted when IMASK is 7 7 ILEVEL 111 Not accepted interrupts disabled 5 12 Ver 0 10 5 INTERRUPT CONTROLLER ICU
71. H gt 56 F F TlOOudf TIOISO mer TIOIMO F F Figure 10 2 9 Block Diagram of MJT Output Interrupt 0 10 36 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer E TIO Interrupt Control Register 1 TIOIR1 Address H 0080 0235 D8 9 10 11 12 13 14 D15 TIOIS7 TIOISe TIOIS5 TIOIS4 TIOIM7 TIOIM6 5 TIOIM4 When reset 00 gt D Bit Name Function R 8 TIOIS7 TIO interrupt status 0 No interrupt request O A 9 TIOIS6 TIO6 interrupt status 1 Interrupt request generated 10 TIOIS5 TIO5 interrupt status 11 TIOIS4 TIO4 interrupt status 12 TIOIM7 TIO7 interrupt mask 0 Enables interrupt request O O 13 TIOIM6 TIO6 interrupt mask 1 Masks disables interrupt request 14 TIOIM5 TIO5 interrupt mask 15 TIOIM4 TIO4 interrupt mask W A Only writing 0 is effective when you write a 1 the previous value is retained TIOIR1 H 0080 0235 TIO7udf Data bus TIOIS7 4 source inputs b8 MJT output F F interrupt 4 TIOIM7 Level IRQ4 b12 F F Opus aL TIOIS6 b9 F F d 26 b13 F F TlO5udf 55 b10 F F d TIOIM 014 TlO4udf TIOIS4 b11 F F d TIOIMA 015 Figure 10
72. H 0080 0000 Boot ae S 16 Kbytes program Space Note 2 H 0080 SFFF H 0080 4000 Ghost area Internal RAM area d 16 Kbytes 0080 7 H 0080 8000 Reserved area 96 Kbytes v T H BFFFFFFF a FFFF HOUBTEFFE H C000 0000 UM 7 H 0080 8000 A Ghost area in System space units of 128 Kbytes M H FFFF FFFF Pol gt HOFF FFFF Notes1 This location varies with chip mode settings 2 The boot program space can read out only when FP 1 MODO 1 MOD1 0 Figure 3 1 2 Address Space of the M32171F3 3 4 Ver 0 10 3 ADDRESS SPACE 3 2 Operation Modes 3 2 Operation Modes The 32171 is placed in one of the following modes by setting its operation mode using MODO and MOD pins For details about the mode used to rewrite the internal flash memory refer to Section 6 5 Programming of Internal Flash Memory Table 3 2 1 Setting Operation Modes MODO MOD 1 Note 1 Operation Mode Note 2 VSS VSS Single chip mode VSS VCC Extended external mode VCC VSS Processor mode FP VSS VCC VCC Reserved cannot be used Notes 1 VCC connects to 5 V and VSS connects to GND 2 For flash rewrite mode FP not listed in the above table refer to Section 6 5 Programming of Internal Flash Memory The internal ROM and extended external areas are located differently depending on the 32171 s operation mode A
73. P77MOD When reset 00 gt D Bit Name Function R 8 P70MOD 0 P70 Port 70 operation mode 1 BCLK 9 P71MOD 0 P71 Port P71 operation mode 1 WAIT 10 P72MOD 0 P72 Port P72 operation mode 1 HREQ 11 P73MOD 0 P73 Port P73 operation mode 1 HACK 12 P74MOD 0 P74 Port P74 operation mode 1 RTDTXD 13 P75MOD 0 P75 Port P75 operation mode 1 RTDRXD 14 P76MOD 0 P76 Port P76 operation mode 1 RTDACK 15 P77MOD 0 P77 Port P77 operation mode 1 RTDCLK 18 3 Ver 0 10 1 8 OSCILLATION CIRCUIT 18 1 Oscillator Circuit 18 1 3 Oscillation Stabilization Time at Power on The oscillator circuit comprised of a ceramic or crystal resonator has a finite time after power on at which its oscillation is instable Therefore create a certain amount of oscillation stabilization time that suits the oscillator circuit used Figure 18 1 2 shows an oscillation stabilization time at power on Oscillation stabilization time OSC VCC RESET nw Lo UU UUUUUUUUUUVUVUAARARUAUVUU Figure 18 1 2 Oscillation Stabilization Time at Power on 18 4 Ver 0 10 1 8 OSCILLATION CIRCUIT 18 2 Clock Generator Circuit 18 2 Clock Generator Circuit The clock generator supplies independent clocks to the CPU and internal peripheral circuits XIN X4 CPU clock 8MHz 10MHz 32MHz 40MHz 1 2 gt BCLK 16MHz 20MHz
74. Refer to Chapter 8 Input Output Ports and Pin Functions 12 52 Ver 0 10 1 2 SERIAL I O 12 7 Receive Operation in UART Mode Initial settings for UART reception Set register to UART mode x Set parity when enabled Set SIO Transmit Receive Mode Register select odd even Set stop bit length Set character length v Set SIO Transmit Control Register e Select clock divider s divide by ratio Serial I O related Set SIO Baud Rate Register Divide by ratio H 00 to H FF Note registers Cause of Receive Interrupt Select Register Set SIO Interrupt Related Registers receive finished receive error Interrupt Mask Register enable disable receive interrupts v Set the interrupt controller Wh naini t SIO Receive Interrupt Control Register When using interrupt v Set DMAC related registers When using DMAC v Set input output port Operation Mode Register wv Initial settings for UART reception finished Note When you selected the clock divider s divide by ratio 1 you are subject to limitations that the baud rate register value you set must be equal to or greater than 7 Figure 12 7 1 Procedure for UART Receive Initialization 12 53 Ver 0 10 1 2 SERIAL I O 12 7 Receive Operation UART Mode 12 7 2 Starting UART Reception When all of the following receive conditi
75. The received frame is discarded and the CAN module goes to the next transmit receive operation without writing to the message slot 13 72 Ver 0 10 CAN MODULE 1 3 13 7 Transmitting Remote Frames B 0000 0000 B 1010 1000 Clear transmit Store received B 1010 1011 Finished storing received data B 0000 1000 CAN bus error occurs Finished transmitting remote frame Finished transmitting remote frame Wait for receive data Store received data Clear receive Finished storing received data B 1010 0001 Store received data je B 0000 0001 Store received data Clear receive request 4 2 0000 0111 1010 0111 o Ko Finished storing z A Store received data data Wait for B 1010 0101 receive data CPU read Finished storing received data a B 0000 0101 Clear transmit B 0000 1011 Finished storing received data B 0000 0001 Figure 13 7 2 Operation of the CAN Message Slot Control Regi Remote Frames ster when Transmitting 13 73 Ver 0 10 CAN MODULE 13 13 7 Transmitting Remote Frames 13 7 3 Reading Out Received Data Frames when Set for Remote Frame Transmission The following describes the procedure for reading out received data frames from the slot when it is set for remote frame transmission 1 Clearin
76. X A2 A2 Write data X RTDTXD ee DX K RTDACK lt gt 3 clock D A1 Read value D A1 Verify value periods before write after write Note An Specified address D An Data at specified address An Figure 14 3 5 Operation of the WRR Command 14 8 Ver 0 10 1 4 REAL TIME DEBUGGER RTD 14 3 Functional Description of the RTD 14 3 4 Operation of VER Continuous Monitor When the VER continuous monitor command is issued the RTD outputs data from the address that has been accessed by the instruction either read or write immediately before receiving the VER command LSB side MSB side 31 20119 18 17 16 15 0 RTDRXD lt X X 0 0 0 0 X X Command VER Note X Don t Care However if issued immediately after the RCV command bits 20 31 must all be set to 1 Figure 14 3 6 VER Continuous Monitor Command Data Format 32 clock 32 clock 32 clock 32 clock periods o gt ahei ook AANA ame RTDRXD X RDR A X VER X VER YI Note 1 i RE RTDTXD e DY Y RTDACK 2 clock D A1 Read value D A1 Latest periods Note 2 read value Note 1 WRR command can also be used Note 2 An Specified address D An Data at sp
77. 0440 0442 0444 0446 0448 044A 044C 044E 0450 0452 0454 0456 0458 045A 045C 045E 0460 0462 0464 0466 0468 0470 0472 0474 0476 0478 A 0 Address 1 Address 29 D8 gos PAN A eae D Count eg eg DMA3 Source Address Register DM3SA DMAS Destination Address Register DM3DA DMA8 Channel Control DMA6G Transfer Count Register DM8CNT Register DM8TCT DMA8 Source Address Register DM8SA DMAS8 Destination Address Register DM8DA DMA4 Channel Control DMAA Transfer Count Register DM4CNT Register DM4TCT DMA4 Source Address Register DM4SA DMA4 Destination Address Register DM4DA DMA9 Channel Control DMA9 Transfer Count Register D Register DM9TCT DMA9 Source Address Register DM9SA DMA9 Destination Address Register DM9DA DMAO Software Request Generation Register DMOSRI DMA1 Software Request Generation Register DM1SRI DMA2 Software Request Generation Register DM2SRI DMAG3 Software Request Generation Register DM3SRI DMAA Software Request Generation Register DM4SRI DMAS Software Request Generation Register DM5SRI DMA6 Software Request Generation Register DM6SRI DMA7 Software Request Generation Register DM7SRI DMA8 Software Request Generation Register DM8SRI DMA9 Software Request Generation Register DM9SRI Blank addresses are
78. 12 3 4 Successive CSIO Transmission 12 28 12 3 5 Processing at End of CSIO Transmission 12 29 12 3 6 Transmit Interrupt en 12 29 12 3 7 Transmit DMA Transfer 12 29 12 3 8 Typical CSIO Transmit Operation 12 31 12 4 Receive Operation CSIO Mode eene 12 4 1 Initial Settings for CSIO Reception 12 33 12 4 2 Starting CSIO Reception 2 12 35 12 4 3 Processing at End of CSIO Reception 12 35 12 4 4 About Successive Reception 12 36 12 4 5 Flags Indicating the Status of CSIO Receive Operation 12 37 12 4 6 Typical CSIO Receive Operation 12 38 12 5 Precautions on Using CSIO Mode eene 12 6 Transmit Operation in UART Mode eene 12 6 1 Setting the UART Baud 12 42 12 6 2 UART Transmit Receive Data Formats 12 43 12 6 3 Initial Settings for UART Transmission 12 45 12 6 4 Starting UART Transmission
79. 12 6 4 Starting UART Transmission When all of the following transmit conditions are met after you finished initialization the serial I O starts transmit operation The SIO Transmit Control Register s TEN transmit enable bit is set to 1 Note Transmit data is written to the SIO Transmit Buffer Register transmit buffer empty bit 0 Note While the transmit enable bit is cleared to 0 writes to the transmit buffer are ignored Always be sure to set the transmit enable bit to 1 before you write to the transmit buffer register When transmission starts the serial transmits data following the procedure below Transfer the content of the SIO Transmit Buffer Register to the SIO Transmit Shift Register Set the transmit buffer empty bit to 1 Note Start sending data synchronously with the shift clock beginning with the LSB Note A transmit buffer empty interrupt request and or a DMA transfer request can be generated when the transmit buffer is emptied 12 6 5 Successive UART Transmission Once data is transferred from the transmit buffer register to the transmit shift register the next data can be written to the transmit buffer register even when transmission of the preceding data is not completed When the next data is written to the transmit buffer before completion of the preceding data transmission the preceding and the next data are successively transmitted To see if data has been transferred from the transmi
80. 16 channel scan 2753 Comparator mode 27 Note 1 For single and comparator modes this shows the time for A D conversion in one channel or for comparate operation For single shot and continuous scan modes this shows the time for A D conversion in one scan loop Note 2 This shows the time from when a write to register cycle is completed to when an A D conversion interrupt request is generated Note 3 This shows the time from when output event bus 3 is actuated to when an A D conversion interrupt request is generated 11 36 Ver 0 10 1 1 CONVERTERS 11 3 Functional Description of Converters 11 3 5 Definition of the A D Conversion Accuracy The following defines the A D conversion accuracy 1 Resolution Number of digital converted codes output by the A D converter 2 Nonlinearity error Deviation from ideal conversion characteristics after the offset and full scale errors are adjusted to 0 Figure 11 3 5 3 Offset error Refers to an amount of dislocation by which the actual digital output code is dislocated from the digital output code obtained from the A D converter s ideal conversion line Figure 11 3 6 4 Full scale error Refers to an amount of dislocation by which the analog input voltage at which the digital output code reached the full scale value is dislocated from the nominal value Figure 11 3 7 2
81. 8 FP7 F F7 protect 9 FP6 F F6 protect 10 FP5 F F5 protect 11 FP4 F F4 protect 12 FP3 F F3 protect 13 FP2 F F2 protect 14 FP1 F F1 protect 15 FPO F FO protect Note This register must always be accessed in halfwords This register controls write to each output F F flip flop by enabling or disabling it When this register is set to disable write to any output F F writing to the F F Data Register has no effect 10 25 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer E F F Protect Register 1 FFP1 Address H 0080 0229 D8 9 10 11 12 13 14 D15 When reset 00 gt D Bit Name Function R 8 10 No functions assigned 0 E 11 FP20 F F20 protect 0 Enables write to F F output bit 12 FP19 F F19 protect 1 Disables write to F F output bit 13 FP18 F F18 protect 14 FP17 F F17 protect 15 FP16 F F16 protect 10 26 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer B F F Data Register 0 FFDO Address H 0080 0226 DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 When reset 0000 gt D Bit Name Function R 0 FD15 F F15 output data 0 F F output data 0 1 FD14 F F14 output data 1 F F output data 1 2 FD13 F F13 output data 3 FD12 F F12 output data 4 FD11 F F11 output data 5 FD10 F F10 outp
82. 9 3 oO o amp 2 Write BCLK A12 A30 CSO CS1 DBO DB15 Note Circles above indicate points at which signals are sampled Figure 16 3 2 Read Write Timing for Access with 1 Internal Wait Cycle Ver 0 10 16 7 WAIT CONTROLLER 16 3 Typical Operation of the Wait Controller 16 o gt o ES z l o 59 N G v EA X e tc A12 A30 CS0 CS1 DBO DB15 Don t Care T TS Y rs o S o pt 2 g eoe aca a a gt 9 c o 2 o N _ ee nnn nn OO 21 VN 3 PORTIO S x to a 2B sg E 6 m a e x 8 5 Pus Don t Care Note Circles O above indicate points at which signals are sampled Figure 16 3 3 Read Write Timing for Access with 2 Internal Wait Cycles Ver 0 10 16 8 1 6 WAIT CONTROLLER 16 3 Typical Operation of the Wait Controller
83. COMSL1DT2 E CANO Message Slot 2 Data 2 COMSL2DT2 CANO Message Slot 3 Data 2 COMSL3DT2 E CANO Message Slot 4 Data 2 COMSL4DT2 CANO Message Slot 5 Data 2 COMSL5DT2 CANO Message Slot 6 Data 2 COMSL6DT2 E CANO Message Slot 7 Data 2 COMSL7DT2 CANO Message Slot 8 Data 2 COMSL8DT2 E CANO Message Slot 9 Data 2 COMSL9DT2 E CANO Message Slot 10 Data 2 COMSL10DT2 E CANO Message Slot 11 Data 2 COMSL11DT2 E CANO Message Slot 12 Data 2 COMSL12DT2 E CANO Message Slot 13 Data 2 COMSL13DT2 E CANO Message Slot 14 Data 2 COMSL14DT2 E CANO Message Slot 15 Data 2 COMSL15DT2 DO 1 2 3 4 CAN MODULE 13 2 CAN Module Related Registers Address H 0080 1108 Address H 0080 1118 Address H 0080 1128 Address H 0080 1138 Address H 0080 1148 Address H 0080 1158 Address H 0080 1168 Address H 0080 1178 Address H 0080 1188 Address H 0080 1198 Address H 0080 11 8 gt Address H 0080 11 8 gt Address H 0080 11C8 gt Address H 0080 1108 gt Address H 0080 11 8 gt Address H 0080 11 8 gt 5 6 D7 COMSLnDT2 D Bit Name 0 7 COMSLnDT2 When reset Indeterminate gt Function R Ww Message slot n data 2 O O These registers are the transmit frame receive frame memory space Note indeterminate value is written to this register 13 46 For receive slots if when storing a data frame the data length DLC value 2 an Ver 0 10 13 CAN
84. CSIO on transmit side data Next data Transmit buffer bit d E X First data Next data Transmit clock 5 SCLKO vivivlecwl el el ele vt Set i Y E i i i Transmit enable bit _ Write to Write to transmit transmit Cleared buffer buffer register register Transmit status bit TXD D7 XD6X DS X DOXD7X Dex D5 X V X po 4 Upon transmit buffer empty Note 3 I Note 2 interrupt next data is written Note 2 Note 4 SIO transmit interrupt 4 gA Note 1 Processing by software E Interrupt generation Note 1 Change of the Interrupt Controller SIO Transmit Interrupt Control Register interrupt request bit Note 2 When transmit interrupt is enabled DMA transfer can also be requested at the same timing Note 3 Transmit interrupt request is generated when transmission is enabled Note 4 Even after transmit data is written to the transmit buffer a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied Figure 12 3 4 Example of CSIO Transmission Successive Transmission with Transmit Buffer Empty and Transmit Finished Interrupts Used 12 32 Ver 0 10 1 2
85. Figure 19 5 7 BSDL Description for the 32171 7 14 19 21 Ver 0 10 19 JTAG 19 5 Boundary Scan Description Language attribute USERCODE REGISTER of M32171F4VFP entity is 0000 0000 0010 0000 amp 0000 amp 0001 amp 0000 amp 0001 attribute REGISTER ACCESS of Bypass Boundary IDCODE USERCODE REG 32 MDM SYSTEM REG 17 MDM CONTROL REG 20 SETUP REG 2 MTM CONTROL REG 4 MON CODE REG 32 MON DATA 32 MON PARAM REG 32 MON ACCESS REG 4 RADDR REG 32 REG 32 REG 3 ACCESS REG 3 RTDENB REG I reserved reserved ROM ISA SDI version M32171FAVFP entity is BYPASS amp SAMPLE EXTEST amp IDCODE amp USERCODE amp MDM SYSTEM amp MDM CONTROL amp SETUP amp MTM CONTROL amp MON CODE amp MON amp MON amp MON ACCESS amp DMA_RADDR amp RDATA amp RTYPE amp ACCESS amp RTDENB attribute BOUNDARY LENGTH of M32171FAVFP entity is 291 attribute BOUNDARY REGISTER of M32171F4VEFP entity is num cell port function safe ccell disval rslt 290 i P103 observe_only X amp 289 BC_ P103 output3 X 288 0 Z amp 288 BC i control 0 amp 287 4 P104 observe only X amp 286 1 104 output3 X 2
86. H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 0080 0082 0084 0086 0088 008A 008C 0090 0092 0094 0096 0098 009A 009C 009E 00A0 00A2 00A4 00A6 00A8 00AA 00AC 00 0 Address D7 D8 1 Address D15 A DO0 Single Mode Register 0 ADOSIMO A DO Single Mode Register 1 ADOSIM1 A DO Scan Mode Register 0 ADOSCMO A DO Scan Mode Register 1 ADOSCM1 E N A DO Successive Approximation Register ADOSAR A D0 Comparate Data Register ADOCMP 10 bit A DO Data Regis 10 bit A DO Data Regis 10 bit A DO Data Regis 10 bit A DO Data Regis 10 bit A DO Data Regis 10 bit A DO Data Regis 10 bit A DO Data Regis 10 bit A DO Data Regis 10 bit A DO Data Regis 10 bit A DO Data Regis 10 bit A DO Data Regis 10 bit A DO Data Regis 10 bit A DO Data Regis 10 bit A DO Data Regis 10 bit A DO Data Regis 10 bit A DO Data Regis Blank addresses are reserved Note The registers enclosed in thick frames must always be accessed in halfwords E er 6 r er 8 er 9 er 10 er 11 er 12 er 13 er 14 er 15 ADODTO ADODT1 ADODT2 ADODT3 ADODT4 ADODT5 ADODT6 ADODT7 ADODT8 ADODT9 ADODT10 ADODT11
87. INTERNAL MEMORY 6 5 Programming of the Internal Flash Memory 8 Read Lock Bit Status command The Read Lock Bit Status command allows you to check whether or not a memory block is protected against program erase Write the command data H 7171 to any address of the internal flash memory Next read the last even address of the block you want to check see Table 6 5 3 Table 6 5 4 and Table 6 5 5 Target Blocks and Specified Addresses and the data you read shows whether or not the target block is protected If the FLBSTO lock bit 0 bit and FLBST1 lock bit 1 bit of the data you read are Os it means that the target memory block is protected If the FLBSTO lock bit 0 bit and FLBST1 lock bit 1 bit are 1s it means that the target memory block is not protected Bi Lock Bit Status Register FLBST When reset Indeterminate gt D Bit Name Function R 0 No functions assigned 1 FLBSTO 0 Protected Lock bit 0 1 Not protected 2 8 No functions assigned 9 FLBST1 0 Protected Lock bit 1 1 Not protected Same content as FLBSTO is output 10 15 functions assigned The Lock Bit Status Register is a read only register which contains said lock bits independently for each block 6 31 Ver 0 10 INTERNAL MEMORY 6 5 Programming of the Internal Flash Memory Follow the procedure described below to write to the lock bits Setting the lock bit to 0 protect the
88. INTERRUPT CONTROLLER ICU 5 4 ICU Vector Table Address DO 0 Address D7 D8 1 Address D15 H 0000 00A4 Blank addresses are reserved for future use Figure 5 4 1 ICU Vector Table Memory Map 1 2 5 14 Ver 0 10 INTERRUPT CONTROLLER ICU 5 4 ICU Vector Table Address 0 Address 1 Address DO D7 D8 D15 H 0000 00 2 H 0000 00 4 H 0000 00 6 H 0000 OOF 4 H 0000 OOF6 H 0000 OOF8 H 0000 OOFA H 0000 H 0000 OOFE H 0000 0100 H 0000 0102 H 0000 0104 H 0000 0106 H 0000 0108 H 0000 010A H 0000 010C CANO Transmit Receive amp Error Interrupt Handler Start Address 0 15 H 0000 010E CANO Transmit Receive amp Error Interrupt Handler Start Address A16 A31 Blank addresses are reserved for future use Figure 5 4 2 ICU Vector Table Memory Map 2 2 5 15 Ver 0 10 INTERRUPT CONTROLLER ICU 5 5 Description of Interrupt Operation 5 5 Description of Interrupt Operation 5 5 1 Acceptance of Internal Peripheral I O Interrupts An interrupt from any internal peripheral I O is checked to see whether or not to accept by comparing its ILEVEL value set by the Interrupt Control Register and the IMASK value of the Interrupt Mask Register If its priority is higher than the IMASK value the interrupt is accepted However when multiple interrupt requests occur simultaneously the interrupt controller resolves priority between these interrupt requests following the proc
89. No interrupt request O A 4 DMITST3 interrupt request status 1 Interrupt requested 5 DMITST2 interrupt request status 6 DMITST1 interrupt request status 7 DMITSTO DMAO interrupt request status W A Only writing a 0 is effective when you write 1 the previous value is retained The DMAO 4 Interrupt Request Status Register lets you know the status of interrupt requests in channels 0 4 If the DMAn interrupt request status bit n 0 to 4 is set to 1 it means that DMAn interrupt request in the corresponding channel has been generated DMITSTn DMAn interrupt request status bit n 0 to 4 Setting the DMAn interrupt request status bit This bit can only be set in hardware and cannot be set in software Clearing the DMAn interrupt request status bit This bit is cleared by writing a 0 in software Note The DMAn interrupt request status bit cannot be cleared by writing a 0 to the Interrupt cause bit of the DMA Interrupt Control Register that the interrupt controller has When writing to the DMAO 4 Interrupt Request Status Register be sure to set the bits you want to clear to 0 and all other bits to 1 The bits which are thus set to 1 are unaffected by writing in software and retain the value they had before you wrote 9 21 Ver 0 10 9 9 2 DMAC Related Registers E DMA5 9 Interrupt Request Status Register DM59ITST Address H 0080 0408 gt DO 1 2 3 4 5 6
90. P05 3 P06 P06 P07 P07 P10 P10 P11 P11 P12 P12 P13 P13 P14 P14 P15 P15 control 0 amp observe only X amp outputs X 164 0 2 amp control 0 amp observe only X amp outputs X 161 0 2 amp control 0 amp observe_only X amp outputs X 158 0 Z amp control 0 amp observe_only X amp outputs X 155 0 2 amp control 0 amp observe only X amp outputs X 152 0 2 amp control 0 amp observe_only X amp outputs X 149 0 2 amp control 0 amp observe_only X amp outputs X 146 0 2 amp control 0 amp observe only X amp outputs X 143 0 2 amp control 0 amp observe only X amp outputs X 140 0 Z amp control 0 amp observe_only X amp outputs X 137 0 2 amp control 0 amp observe only X amp outputs X 134 0 2 amp control 0 amp observe only X amp outputs X 131 0 Z amp control 0 amp observe_only X amp outputs X 128 0 2 amp control 0 amp observe_only X amp outputs X 125 0 2 amp control 0 amp observe_only X amp outputs X 122 0 2 amp control 0 amp observe_only X amp outputs X 119 0 Z amp control 0 amp observe_only X
91. R11 R12 R13 R14 Link register R15 Stack pointer Note Note The stack pointer is switched between an interrupt stack pointer SPI and a user stack pointer SPU depending on the value of the PSW s SM bit Figure 2 2 1 General purpose Registers 2 2 Ver 0 10 2 2 3 Control Registers 2 3 Control Registers There are five control registers Processor Status Word Register PSW Condition Bit Register CBR Interrupt Stack Pointer SPI User Stack Pointer SPU and Backup PC BPC Dedicated MVTC and instructions are used to set and read these control registers Control Registers 0 31 CRO PSW Processor status Word Register CR1 CBR Condition Bit Register CR2 SPI Interrupt Stack Pointer CR3 SPU User Stack Pointer CRn CR6 BPC Backup PC Notes 1 CRn 0 3 6 denotes control register numbers 2 Dedicated MVTC and MVFC instructions are used to set and read the control registers Figure 2 3 1 Control Registers 2 3 Ver 0 10 2 CPU 2 3 Control Registers 2 3 1 Processor Status Word Register PSW CRO The Processor Status Word Register PSW is used to indicate the status of the M32R It consists of a regularly used PSW field and a special BPSW field which is used to save the PSW field when an EIT occurs The PSW field consists of several bits labeled Stack Mode SM Interru
92. S2TCNT DO 1 2 3 4 5 Address H 0080 01102 Address H 0080 0120 Address H 0080 0130 TSTAT CDIV When reset H 12 gt D Bit Name Function R 0 1 No functions assigned 0 2 3 CDIV D2 count source select bit 00 Selects f BCLK 01 Selects divided by 8 f BCLK 10 Selects divided by 32 f BCLK 11 Selects divided by 256 f BCLK 4 No functions assigned 0 5 TSTAT 0 Transmit halted amp no data Transmit status bit in transmit buffer register 1 Transmit in progress or data exists in transmit buffer register 6 TBE 0 Data exists in transmit buffer register O Transmit buffer empty bit 1 No data in transmit buffer register 7 TEN 0 Disables transmit Transmit enable bit 1 Enables transmit 12 13 Ver 0 10 1 2 SERIAL 12 2 Serial I O Related Registers 1 CDIV baud rate generator count source select bits D2 D3 These bits select the count source for the baud rate generator BRG Note If f BCLK is selected as the count source for the BRG make sure when you set BRG that the baud rate will not exceed the maximum transfer rate For details refer to the section of this manual where the BRG register is described 2 TSTAT transmit status bit D5 Set condition This bit is set to 1 by a write to the Transmit Buffer Register when transmit is enabled Clear condition
93. SIN DIX 2 INSTRUCTION PROCESSING TIME Appendix 2 1 M32R E Instruction Processing Time INSTRUCTION PROCESSING TIME Appendix 2 1 32171 Instruction Processing Time Appendix 2 Appendix 2 1 32171 Instruction Processing Time For the M32R the number of instruction execution cycles in E stage normally represents its instruction processing time However depending on pipeline operation other stages may affect the instruction processing time Especially when a branch instruction is executed the processing time in IF instruction fetch and D decode stages not just E execution stage must also be taken into account The table below shows the instruction processing time in each pipelined stage of the M32R Table 2 1 1 Instruction Processing Time of Each Pipeline Stage Number of execution cycles in each stage Note 1 Instruction IF D E MEM WB Load instructions LD LDB LDUB LDH LDUH LOCK R 1 1 R 1 Store instructions ST STB STH UNLOCK R 1 1 Multiply instruction MUL R 1 3 1 Divide remainder instructions DIV DIVU REM REMU R 1 37 1 Other instructions including those for DSP function R 1 1 1 Note For R and W refer to the calculation methods described in the next page Appendix 2 2 Ver 0 10 INSTRUCTION PROCESSING TIME Appendix 2 1 32171 Instruction Processing Time Appendix 2 The following shows the number of memory access cycles in IF and MEM stages Shown here a
94. Software start has been selected for the cause of DMA request DMOSRI DM9SRI DMA software request generate bit A software DMA transfer request is generated by writing any data to this register in halfword 16 bits or in byte 8 bits beginning with an even or odd address when Software is selected as the cause of DMA transfer request by setting the DMA Channel Control Register D2 D3 bits to 00 9 17 Ver 0 10 9 2 3 Source Address Registers DMAO Source Address Register DMOSA E DMA1 Source Address Register DM1SA DMA2 Source Address Register DM2SA E DMAS3 Source Address Register DM3SA DMA4 Source Address Register DM4SA E DMAS Source Address Register DM5SA E DMAG6 Source Address Register DM6SA E DMA7 Source Address Register DM7SA E DMAS Source Address Register DM8SA E DMA9 Source Address Register DM9SA DMAC 9 2 DMAC Related Registers Address Address Address Address Address Address Address Address Address Address H 0080 0412 H 0080 0422 H 0080 0432 H 0080 0442 H 0080 0452 7 H 0080 041A H 0080 042A H 0080 043A H 0080 044A H 0080 045A D Bit Name Function When reset Indeterminate gt 0 15 DMOSA DM9SA 16 1 of the source address A0 A15 are fixed to H 0080 Note This register must always be accessed in halfwords R The Source Address Register is used to set the source addr
95. TOP2 Reload Register TOP2RL Address H 0080 0262 TOP3 Reload Register Address H 0080 0272 Reload Register TOPARL Address H 0080 0282 B TOP5 Reload Register TOP5RL Address H 0080 0292 TOP6 Reload Register TOP6RL Address H 0080 02 2 gt Reload Register TOP7RL Address H 0080 02 2 gt B 8 Reload Register TOP8RL lt Address H 0080 02C2 gt B Reload Register TOP9RL lt Address H 0080 02D2 gt Bi TOP10 Reload Register TOP10RL Address H 0080 02 2 gt DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 TOPORL TOP10RL When reset Indeterminate gt D Bit Name Function R 0 15 TOPORL TOP10RL 16 bit reload register value Note This register must always be accessed halfwords The TOP reload registers are used to load data into the TOP counter registers TOPOCT TOP10CT It is in the following cases that the content of the reload register is loaded in the counter When the counter is enabled in single shot mode When the counter underflowed in delayed single shot or continuous mode Writing data to the reload register does not mean that the data is loaded into the counter simultaneously Note that data reloading after an underflow is performed synchronously with the clock period in which the counter underflowed 10 60 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer 10 3 7 TOP Correction Registers TOPOCC TOP1
96. amp P23 19 amp VCCE_20 20 amp VSS 1 21 24 22 amp P25 23 amp P26 24 amp P27 25 8 amp 00 26 01 27 amp P02 28 amp P03 29 amp P04 30 amp P05 31 amp P06 32 amp 07 38 amp P10 34 amp P11 735 amp P12 36 amp P13 37 amp P14 38 amp P15 739 amp P16 40 amp Figure 19 5 4 BSDL Description for the 32171 4 14 19 18 Ver 0 10 1 9 JTAG 19 5 Boundary Scan Description Language 17 41 amp VREF_42 42 amp AVCC_43 743 amp ADOINO 44 amp ADOIN1 45 amp ADOIN2 46 amp ADOINS 147 amp ADOIN4 48 amp ADOIN5 49 amp ADOING 50 amp ADOIN7 51 amp ADOIN8 52 amp ADOIN9 53 amp ADOIN10 54 amp ADOIN11 55 amp ADOIN12 56 amp ADOIN13 57 amp ADOIN14 58 amp ADOIN15 59 amp AVSS 60 60 amp VCCI 61 61 amp VSS 62 62 amp P174 63 amp P175 64 amp VCCE 65 65 amp P82 66 amp P83 67 amp P84 68 amp P85 69 amp P86 70 amp P87 71 amp VSS 72 172 amp FVCC 73 73 amp P61 74 amp P62 75 amp P63 76 amp P64 77 amp P70 78 amp P71 79 amp P72 80 amp P73 81 amp P74 82 amp P75 83 amp P76 84 amp P77 85 amp P93 86 amp P94 87 amp P95 88 amp P96 89 amp P97 90 a
97. and retain the value they had before you wrote 9 22 Ver 0 10 9 9 2 DMAC Related Registers 9 2 7 DMA Interrupt Mask Registers E DMAO 4 Interrupt Mask Register DMO4ITMK Address H 0080 0401 gt D8 9 10 11 12 13 14 D15 DMITMK4 DMITMKS3 DMITMK2 DMITMK1 DMITMKO When reset 00 gt D Bit Name Function R 8 10 No functions assigned 0 11 DMITMK4 DMA4 interrupt request mask 0 Enables interrupt request 12 DMITMK3 interrupt request mask 1 Masks disables interrupt request 13 DMITMK 2 interrupt request mask 14 DMITMK1 interrupt request mask 15 DMITMKO DMAO interrupt request mask The DMAO 4 Interrupt Mask Register is used to mask interrupt requests in DMA channels 0 4 DMITMKn DMAn interrupt request mask bit n 0 to 4 DMAn interrupt request is masked by setting the DMAn interrupt request mask bit to 1 However when an interrupt request is generated the DMAn interrupt request status bit is always set to 1 irrespective of the contents of this register 9 23 Ver 0 10 9 9 2 DMAC Related Registers E DMA5 9 Interrupt Mask Register DM59ITMK Address H 0080 0409 gt D8 9 10 11 12 13 14 D15 DMITMK9 DMITMK8 DMITMK7 DMITMK6 DMITMK5 When reset 00 gt D Bit Name Function R 8 10 No functions assigned 0 11 DMITMK9 DMAQ interrupt r
98. fourth time and so on after being enabled 4 Single shot output mode without correction function In single shot output mode the timer generates a pulse in width of reload 0 register set value 1 only once and stops without performing any operation When after setting the reload 0 register the timer is enabled by writing to the enable bit in software or by external input it loads the content of reload 0 register into the counter synchronously with the count clock letting the counter start counting The counter counts down clock pulses and stops when it underflows after reaching the minimum count The F F output waveform in single shot output mode is inverted at startup and upon underflow generating a single shot pulse waveform in width of reload 0 register set value 1 only once Also an interrupt can be generated when the counter underflows 5 Delayed single shot output mode without correction function In delayed single shot output mode the timer generates a pulse in width of reload 0 register set value 1 only once with the output delayed by an amount of time equal to counter set value 1 and then stops without performing any operation When after setting the counter and reload 0 register the timer is enabled by writing to the enable bit in software or by external input it starts counting down from the counter s set value synchronously with the count clock The first time the counter underflows the reload
99. low order bits are cleared to 00 when returning to the PC 4 13 Ver 0 10 EIT 4 8 Exception Processing 0 1 Address 7 Address 7 H 00 H 00 Return 04 AE occurred Return H 04 AE occurred address H O8 address H O8 H 0C Figure 4 8 2 Example of Return Address for Address Exception AE 4 Branching to the EIT vector entry Control branches to the address H 0000 0030 in the user space This is the last operation performed in hardware preprocessing by the M32R E 5 Jumping from the EIT vector entry to the user created handler The M32R E executes the BRA instruction written at address H 0000 0030 of the EIT vector entry by the user to jump to the start address of the user created handler At the beginning of the EIT handler you created first save the BPC and PSW registers and the necessary general purpose registers to the stack 6 Returning from the EIT handler Atthe end of the EIT handler restore the general purpose registers and the BPC and PSW registers from the stack and then execute the RTE instruction As you execute the RTE instruction hardware postprocessing is automatically performed by the M32R E 4 14 Ver 0 10 4 EIT 4 9 Interrupt Processing 4 9 Interrupt Processing 4 9 1 Reset Interrupt RI Occurrence Conditions Reset Interrupt RI is unconditionally accepted in any m
100. 0 No selection TML1 measure 1 source selection 1 Input event bus 1 10 TML1SS2 0 No selection TML1 measure 2 source selection 1 Input event bus 2 11 TML1SS3 0 No selection O O TML1 measure 3 source selection 1 Input event bus 3 12 14 functions assigned 0 15 TML1CKS 0 1 2 internal peripheral clock TML1 clock source selection 1 Clock bus 1 The TML1 Control Register is used to select TML1 input event and the counter clock source Note The counter can be written to normally only when the selected clock source is a 1 2 internal peripheral clock When using any other clock source you cannot write to the counter normally Under this condition do not write to the counter 10 135 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 6 TML Input related 32 bit Timer 10 6 5 TML Counters Bi TMLO Counter High TMLOCTH Address H 0080 03 0 gt E TMLO Counter Low TMLOCTL Address H 0080 03E2 gt DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 TMLOCTH 16 high order bits DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 TMLOCTL 16 low order bits When reset Indeterminate gt D Bit Name Function R 0 15 1 32 bit counter value 16 high order bits TMLOCTL 32 bit counter value 16 low order bits Note This register must always be accessed in words 32 bits beginning with the address of TMLOCTH The TMLO Counter is a 32 bit up counter which starts counting upon deassertion of reset The TML
101. 0 Address 1 Address DO D7 D8 D15 H 0080 07E8 Virtual re PELBANKO 17 0 H 0080 07EA H 0080 07EC H 0080 07EE Virtual Flash S Bank Register 0 H 0080 07 0 FESBANKO Virtual Flash S Bank Register 1 H 0080 07F2 FESBANK1 Blank addresses are reserved for future use Figure 6 4 1 Register Map Associated with the Internal Flash Memory 6 3 Ver 0 10 6 INTERNAL MEMORY 6 4 Registers Associated with the Internal Flash Memory 6 4 1 Flash Mode Register E Flash Mode Register FMOD Address H 0080 07 0 gt DO 1 2 3 4 5 6 D7 When reset 0 gt D Bit Name Function R Ww 0 6 No functions assigned 0 7 FPMOD 0 FP pin low External FP pin status 1 FP pin high The Flash Mode Register FMOD is a read only status register with its FPMOD bit indicating the status of the FP Flash Protect pin Write to the flash memory is enabled only when FPMOD 1 Writing to the flash memory when FPMOD 0 has no effect Ver 0 10 6 INTERNAL MEMORY 6 4 Registers Associated with the Internal Flash Memory 6 4 2 Flash Status Registers The 32171 has two registers to indicate the flash memory status one of which is Flash Status Register 1 FSTAT1 located in the SFR area address H 0080 07E1 and the other is Flash Status Register 2 FSTAT2 included in the flash memory itself When programming or erasing the flash memory use these two status registers FSTAT1 FSTAT2 to control th
102. 0000 2000 H 02 S bank 94 H 0005 E000 tt H 5E S bank 95 H 0005 F000 H 5F Note Set the eight bits A12 A19 of the start address 32 bit of each S bank of flash memory divided every 4 Kbytes in the Virtual Flash S Bank Register s S bank address SBANKAD bits Figure 6 7 9 Values Set in the M32171F3 s Virtual Flash Bank Register when Divided in Units of 4 Kbytes 6 45 Ver 0 10 6 INTERNAL MEMORY 6 7 Virtual Flash Emulation Function 6 7 2 Entering Virtual Flash Emulation Mode To enter Virtual Flash Emulation Mode set the Flash Control Register 1 1 FEMMOD bit to 1 After entering Virtual Flash Emulation Mode set the Virtual Flash Bank Register MODEN bit to 1 to enable the Virtual Flash Emulation Function Even during pseudo flash emulation mode the internal RAM area H 0080 4000 through H 0080 7FFF can be accessed as internal RAM C Settings completed Write flash data to RAM Go to Virtual Flash Emulation Mode FEMMOD lt 1 Set RAM location address in Virtual Flash Bank Register LBANKADn lt Address A12 A18 SBANKADn lt Address A12 A19 Enable Virtual Flash Emulation Function MODENLn lt 1 MODENSn lt 1 4 Settings completed Figure 6 7 10 Virtual Flash Emulation Mode Sequence 6 46 Ver 0 10 6 INTERNAL MEMORY 6 7 Virtual Flash Emulation Function 6 7 3 Applic
103. 0080 0312 H 0080 0314 TIO1 Reload Register TIO1RL H 0080 0316 TIO1 Reload 0 Measure Register TIO1RLO H 0080 0318 H 0080 031A TIOO 3 Control Register 0 TIOOSCRO Blank addresses are reserved areas Figure 3 4 6 Register Mapping of the SFR Area 4 3 13 Ver 0 10 Address 0 Address H 0080 031C ADDRESS SPACE 3 4 Internal ROM SFR Area 1 Address TIOO 3 Control Register 1 TIOOSCR1 H 0080 0320 H 0080 0322 TIO2 Counter TIO2CT H 0080 0324 H 0080 0326 TIO2 Reload 0 Meas TIO2 Reload 1 Register TIO2RL1 ure Register TIO2RLO H 0080 0330 Counter H 0080 0332 H 0080 0334 Reload 1 Register TIO3RL1 H 0080 0336 TIOS Reload 0 ure Register TIOSRLO H 0080 0340 TIO4 Coun ter TIO4CT H 0080 0342 H 0080 0344 TIO4 Reload 1 Register TIO4RL1 H 0080 0346 TIO4 Reload 0 ure Register TIO4RLO H 0080 0348 H 0080 034A TIO4 Control Register TIO4CR 05 Control Register 5 H 0080 0350 TIO5 Coun ter TIOSCT H 0080 0352 H 0080 0354 TIO5 Reload 1 Register TIOSRL1 H 0080 0356 5 Reload 0 Meas ure Register TIOSRLO H 0080 0360 TIO6 ter 6 H 0080 0362 H 0080 0364 TIO6 Reload 1 Register TIO6RL1 H 0080 0366 TIO6 Reload 0 Meas ure Register TIO6RLO
104. 1 Register TMS1MR1 H 0080 03D8 TMS1 Measure 0 Register 51 Blank addresses are reserved Note The registers enclosed in thick frames must always be accessed in halfwords Figure 10 5 2 TMS Related Register Map 10 124 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 5 TMS Input related 16 bit Timer 10 5 4 TMS Control Registers The TMS control registers are used to select 50 1 input events and the counter clock source as well as control counter startup Following two TMS control registers are included TMSO Control Register TMSOCR TMS1 Control Register TMS1CR TMSO Control Register TMSOCR lt Address H 0080 03CA gt DO 1 2 3 4 5 6 D7 TMSO 50 50 50 EEKE TSOEN 550 551 552 553 When reset H 00 gt D Bit Name Function R 0 50550 0 No selection 50 measure 0 source selection 1 Input event bus 0 1 TMSOSS1 0 No selection 50 measure 1 source selection 1 Input event bus 1 2 50552 0 No selection 50 measure 2 source selection 1 Input event bus 2 3 50553 0 No selection 50 measure 3 source selection 1 Input event bus 3 4 5 TMSOCKS 00 External input TCLK3 Q D 50 clock source selection 01 Clock bus 0 10 Clock bus 1 11 Clock bus 3 6 No functions assigned 0 7 TMSOCEN 0 Count stops O O TMSO count enable 1 Count starts 10 125 Ver 0 10 1 0 MULTIJ
105. 13 14 015 55 0 55 1 55 2 SSB3 SSB4 55 5 SSB6 SSB7 SSB8 SSB9 SSB105SSB11 SSB12SSB13 SSB14 SSB15 When reset H 0000 gt D Bit Name Function R W 0 SSBO Slot 0 interrupt request status 0 No interrupt request 1 SSB1 Slot 1 interrupt request status 1 Interrupt requested 2 SSB2 Slot 2 interrupt request status 3 SSB3 Slot 3 interrupt request status 4 SSB4 Slot 4 interrupt request status 5 SSB5 Slot 5 interrupt request status 6 SSB6 Slot 6 interrupt request status 7 SSB7 Slot 7 interrupt request status 8 SSB8 Slot 8 interrupt request status 9 55 9 Slot 9 interrupt request status 10 SSB10 Slot 10 interrupt request status 11 SSB11 Slot 11 interrupt request status 12 55 12 Slot 12 interrupt request status 13 SSB13 Slot 13 interrupt request status 14 SSB14 Slot 14 interrupt request status 15 SSB15 Slot 15 interrupt request status W A Only writing a 0 is effective when you write a 1 the previous value is retained 13 22 Ver 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers When using CAN interrupts this register lets you know which slot requested an interrupt Slots set for transmission The bit is set to 1 when the CAN module finished transmitting The bit is cleared by writing a 0 in software Slots set for reception The bit is set to 1 when the CAN module finished receiving and finished storing the received message in the message slot The bit is cleared by writing
106. 16 bits Selects DMA7 transfer size 1 8 bits 6 SADSL9 0 Fixed Selects DMA7 source address direction 1 Incremental 7 DADSL9 0 Fixed Selects 9 destination 1 Incremental address direction W A Only writing a 0 is effective when you write 1 the previous value is retained 9 15 Ver 0 10 DMAC 9 2 DMAC Related Registers The DMA Channel Control Register consists of bits to select DMA transfer mode in each channel set DMA transfer request flag and the bits to select the cause of DMA request enable DMA transfer and set the transfer size and the source destination address directions 1 MDSELn DMAn transfer mode select bit DO This bit when in single transfer mode selects normal mode or ring buffer mode Normal mode is selected by setting this bit to O or ring buffer mode is selected by setting it to 1 In ring buffer mode transfer begins from the transfer start address and after performing transfers 32 times control is recycled back to the transfer start address from which transfer operation is repeated In this case the Transfer Count Register counts in free run mode during which time transfer operation is continued until the transfer enable bit is reset to 0 to disable transfer No interrupt is generated at completion of DMA transfer 2 TREQFn DMAn transfer request flag bit D1 This flag is set to 1 when a DMA transfer request occurs Reading this flag helps to know DMA transfer requ
107. 2 10 Block Diagram of MJT Output Interrupt 4 10 37 Ver 0 10 10 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer E TIO Interrupt Control Register 2 TIOIR2 Address H 0080 0236 DO 1 2 3 4 5 6 D7 TIOIS9 TIOIS8 TIOIM9 TIOIM8 When reset H 00 gt D Bit Name Function R 0 1 No functions assigned 0 2 TIOIS9 9 interrupt status 0 No interrupt request A 3 TIOIS8 TIO8 interrupt status 1 Interrupt request generated 4 5 No functions assigned 0 6 TIOIMO 9 interrupt mask 0 Enables interrupt request O O 7 TIOIM8 TIO8 interrupt mask 1 Masks disables interrupt request W A Only writing a 0 is effective when you write 1 the previous value is retained TIOIR2 H 0080 0236 TlO9udf Data bus TIOIS9 2 source inputs b2 F F MJT output d 2 4 interrupt 3 TIOIM9 Level IRQ3 56 F F TlO8udf TIOIS8 b3 F F 5 TIOIM8 9 F F Figure 10 2 11 Block Diagram of MJT Output Interrupt 3 10 38 Ver 0 10 10 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer E TMS Interrupt Control Register TMSIR D8 9 10 Address H 0080 0237 11 12 13 14 D15 TMSIS1 TMSISO TMSIM1 TMSIMO When reset H 00 gt D Bit Name Funct
108. 2 bits 0 after reset be sure to change it to a value equal to or greater than 2 before you use the CAN module 3 PH1 bits D5 D7 These bits set the width of Phase Segment1 4 PRB bits D8 D10 These bits set the width of Propagation Segment 5 SAM bit D11 This bit sets the number of times each bit is sampled When SAM 0 the value sampled at the end of Phase Segment1 is assumed to be the value of the bit When SAM 1 the value of the bit is determined by a majority circuit from values sampled at three points one sampled at the end of Phase Segment1 one sampled before 1Tq and one sampled before 2Tq Table 13 2 1 Typical Settings of Bit when CPU Clock 40 MHz a 13 18 Ver 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers 13 2 5 CAN Time Stamp Count Register E CANO Time Stamp Count Register CANOTSTMP Address H 0080 1008 DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 CANTSTMP When reset H 0000 gt D Bit Name Function R 0 15 CANSTMP 16 bit counter value Q The CAN module contains 16 bit counter The count period be chosen to be the CAN bus bit period divided by 1 2 3 or 4 by setting the CAN Control Register CANOCNT s TSP Time Stamp Prescaler bits When the CAN module finishes transmitting or receiving it captures the counter value and stores it in a message slot The counter is made to start counting by clearing the CAN Control Regi
109. 32171 has four types of multijunction timers as listed in the table below providing a total of 37 channels of timers Table 10 1 1 Outline of Multijunction Timers Name Type Number of Channels Description TOP Output related 11 One of three output modes can be selected by software Timer Output 16 bit timer With correction function down counter Single shot output mode Delayed single shot output mode Without correction function Continuous output mode TIO Input output related 10 One of three input modes or four output modes can be Timer 16 bit timer selected by software Input Output down counter Input modes Measure clear input mode Measure free run input mode Noise processing input mode Output mode without correction function PWM output mode Single shot output mode Delayed single shot output mode Continuous output mode TMS Input related 8 16 bit input measure timer Timer 16 bit timer Measure Small up counter TML Input related 8 32 bit input measure timer Timer 32 bit timer Measure Large up counter 10 2 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 1 Outline of Multijunction Timers Table 10 1 2 MJT Interrupt Generation Functions of the M32171 Signal Name Source of MJT Interrupt Requested Interrupt Controller ICU Input ICU Cause Input IRQ12 TINS input MJT input interrupt 4 1 IRQ11 20 TIN23 input MJT input interrupt 3 4 IRQ10 TIN16 TIN19 input MJT input
110. 4 13 4 9 Interrupt Processing 4 15 4 9 1 Reset Interrupt 4 4 15 4 9 2 System Break Interrupt 4 16 4 9 3 External Interrupt 4 18 4 10 Trap Processing 4 20 4301 Frap TRAR uet it avi insite ghd 4 20 4 11 EIT Priority enne nnne nnne nnn 4 22 4 12 Example of EIT Processing cerent 4 23 CHAPTER 5 INTERRUPT CONTROLLER ICU 5 1 Outline of Interrupt Controller ICU eese eere 5 2 5 2 Interrupt Sources of Internal Peripheral 5 4 5 3 ICU Related Registers 5 5 5 3 1 Interrupt Vector 5 6 5 3 2 Interrupt Mask Register 5 7 5 3 3 SBI System Break Interrupt Control Register 5 8 5 3 4 Interrupt Control 5 9 5 4 ICU Vector Table 5 rrt terrent tiae punire 5 13 5 5 Description of Interrupt Operation essere 5 16 5 5 1 Acceptance of Internal Peripheral I O Interrupts 5 16 5 5 2 Processing of Internal Peripheral I O Interrupts by Handlers 5 19 5 6 Description of S
111. 4 5 Acceptance of EIT Events 4 5 Acceptance of EIT Event When EIT event occurs the M32R E suspends the program it has hitherto been executing and branches to EIT processing by the relevant handler Conditions under which each EIT event occurs and the timing at which they are accepted are shown below Table 4 5 1 Acceptance of EIT Events EIT Event Type of Processing Acceptance Timing Values Set in BPC Register Reserved Instruction Instruction processing During instruction PC value of the instruction Exception RIE canceled type execution which generated RIE Address Exception AE Instruction processing During instruction PC value of the instruction canceled type execution which generated AE Reset Interrupt RI Instruction processing aborted type Each machine cycle Indeterminate value System Break Interrupt SBI Instruction processing completed type Break in instructions value of the next instruction only word boundaries External Interrupt El Instruction processing completed type Break in instructions value of the next instruction only word boundaries Trap TRAP Instruction processing completed type Break in instructions value of TRAP instruction 4 4 7 Ver 0 10 4 EIT 4 6 Saving and Restoring the PC and PSW 4 6 Saving and Restoring the PC and PSW The following describes operation of the M32R at the time when it accepts an EIT and wh
112. 4 Calculation of the A D Conversion 11 34 11 3 5 Definition of the A D Conversion 11 37 11 4 Precautions on Using A D Converters esee 11 40 CHAPTER 12 SERIAL I O 12 1 Outline of Serial 12 2 12 2 Serial Related Registers ener 12 6 12 2 1 SIO Interrupt Related 12 7 12 2 2 SIO Interrupt Control Registers 12 9 12 2 3 SIO Transmit Control Registers 12 13 12 2 4 SIO Transmit Receive Mode Registers 12 15 7 12 2 5 SIO Transmit Buffer Registers 2 0 12 18 12 2 6 SIO Receive Buffer Registers 12 19 12 2 7 SIO Receive Control Registers 12 20 12 2 8 SIO Baud Rate Registers 12 23 12 3 Transmit Operation in CSIO Mode eene 12 3 1 Setting the CSIO Baud 12 25 12 3 2 Initial Settings for CSIO Transmission 12 26 12 3 3 Starting CSIO Transmission 2 12 28
113. 5 4 ICU Vector Table 5 4 ICU Vector Table The ICU vector table is used to set the start addresses of interrupt handlers for each internal peripheral I O The 22 source interrupts are assigned the following addresses Table 5 4 1 ICU Vector Table Addresses Interrupt Source Input Interrupt 4 Input Interrupt 3 Input Interrupt 2 Input Interrupt 1 ICU Vector Table Address H 0000 0094 H 0000 0097 H 0000 0098 H 0000 009B H 0000 009C H 0000 009 H 0000 00A0 H 0000 00A3 MJT Output Interrupt 7 MJT Output Interrupt 6 MJT Output Interrupt 5 MJT Output Interrupt 4 MJT Output Interrupt 3 MJT Output Interrupt 2 MJT Output Interrupt 1 MJT Output Interrupt 0 H 0000 00A8 H 0000 00AB H 0000 00AC H 0000 00AF H 0000 00B0 H 0000 00B3 H 0000 00B4 H 0000 00B7 H 0000 00B8 H 0000 00BB H 0000 00BC H 0000 00 H 0000 00C0 H 0000 00C3 H 0000 00C4 H 0000 00C7 DMAO 4 Interrupt SIO1 Receive Interruptt SIO1 Transmit Interruptt SIOO Receive Interruptt SIOO Transmit Interruptt A DO Converter Interruptt DMAS5 9 Interruptt SIO2 3 Transmit Receive Interrupt t RTD Interruptt CANO Transmit Receive amp Error Interrupt H 0000 00C8 H 0000 00CB H 0000 00CC H 0000 00 H 0000 0000 0000 0003 H 0000 00D4 H 0000 0007 H 0000 00D8 H 0000 00DB H 0000 00DC H 0000 00DF H 0000 00E8 H 0000 00 H 0000 00 0000 00 H 0000 00 0 0000 00F3 H 0000 010C H 0000 010F 5 13 Ver 0 10
114. 6 2 SBI Processing by Handler When the system break interrupt generated has been serviced always be sure to terminate or reset the system without returning to the program that was being executed when the interrupt occurred SBI System Break Interrupt vector entry H 0000 0010 BRA instructiong SBI System Break o o Interrupt handler a Y Program being executed Processing to dub t terminate the system 7 lt SBI generated Terminate or reset E cs d Note Do not return to the program that was being executed when the interrupt occurred Figure 5 6 1 Typical SBI Operation 5 21 Ver 0 10 INTERRUPT CONTROLLER ICU 5 6 Description of System Break Interrupt SBI Operation This is a blank page 5 22 Ver 0 10 CHAPTER 6 INTERNAL MEMORY 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 Outline of the Internal Memory Internal RAM Internal Flash Memory Registers Associated with the Internal Flash Memory Programming of the Internal Flash Memory Boot ROM Virtual Flash Emulation Function Connecting to A Serial Programmer Precautions to Be Taken When Rewriting Flash Memory 6 INTERNAL MEMORY 6 1 Outline of the Internal Memory 6 1 Outline of the Internal Memory The 32171 internally contains the following types of memory 16 Kbyte RAM 512 Kbyte or 384 Kbyte flash m
115. 8Kbytes H 0007 E000 L bank 63 8Kbytes Note 1 If the Pseudo Flash Emulation Enable bit is enabled while the same bank area is set in multiple Pseudo Flash Bank Registers the internal RAM area 8 or 4 Kbytes to be allocated is selected by priority FELBANKO FESBANKO FESBANK 1 Note 2 When you access the 8 Kbyte area L bank selected by Pseudo Flash L Bank Register 0 you actually are accessing the internal RAM area During pseudo flash emulation mode the RAM can be read and written to from both the internal RAM and the selected pseudo flash memory areas Figure 6 7 2 Pseudo Flash Emulation Areas of the M32171F4 Divided in Units of 8 Kbytes Internal flash H 0000 0000 S bank 0 4Kbytes H 0000 1000 S bank 1 4Kbytes H 0000 2000 5 bank 2 4Kbytes H 0080 4000 8Kbytes Internal RAM akBys H 0080 6000 7 4Kbytes H 0080 7000 o H 0007 E000 S bank 126 4Kbytes H 0007 F000 S bank 127 4Kbytes Note 1 If the Pseudo Flash Emulation Enable bit is enabled while the same bank area is set in multiple Pseudo Flash Bank Registers the internal RAM area 8 or 4 Kbytes to be allocated is selected by priority FELBANKO FESBANKO FESBANK 1 Note 2 When you access the 4 Kbyte area S bank selected by Pseudo Flash S Bank Register 0 1 you actually are accessing the internal RAM area During pseudo flash emulation mode the RAM can
116. 9 10 11 12 13 Address H 0080 02AA 14 015 When 0000 gt Function R 0 No functions assigned 0 1 TOP7ENS 0 Result selected by TOP67ENS bit enable source selection 1 TOP6 output 2 3 TOP7M operation mode selection 00 Single shot output mode 01 Delayed single shot output mode 1X Continuous output mode 4 5 No functions assigned 0 6 7 TOP6M TOP6 operation mode selection 00 Single shot output mode 01 Delayed single shot output mode 1X Continuous output mode 8 No functions assigned 0 gt 9 11 TOP67ENS OXX No selection 6 enable source selection 100 Input event bus 0 101 Input event bus 1 110 Input event bus 2 111 Input event bus 3 12 13 No functions assigned 0 1445 67 5 00 Clock bus 0 6 clock source selection 01 Clock bus 1 10 Clock bus 2 11 Clock bus 3 Note 1 This register must always be accessed in halfwords Note 2 Always make sure the counter has stopped and is idle before setting or changing operation modes 10 55 Ver 0 10 10 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer TIN1 TIN1S Clock bus Input event bus 3210 3210 5 Note This diagram is shown for the explanation of TOP control registers and is partly omitted Selector Figure 10 3 6 Outline Diagram o
117. A DO converter indicating the channel it is converting The value read from these bits during single mode are always B 0000 If A D conversion is halted by setting Scan Mode Register 0 ADOCSTP A DO conversion stop bit to 1 during scan mode execution the bits when read at this time show the value of the channel in which the A D conversion has been canceled Also if halted during single mode conversion in special operation mode Forcible single mode execution during scan mode the bits when read at this time show the value of the channel in which the A D conversion has been canceled in the middle of scan 11 25 Ver 0 10 1 1 5 11 2 Converter Related Registers 11 2 5 A D Successive Approximation Register A DO Successive Approximation Register ADOSAR Address H 0080 0088 DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 When reset Indeterminate D Bit Name Function R 0 5 No functions assigned 0 6 15 ADOSAR successive approximation value A DO successive approximation A D conversion mode value comparison value Comparison value comparator mode Note This register must always be accessed in halfwords The A DO Successive Approximation Register ADOSAR when in conversion mode is used to read out the conversion result of the A DO converter and when in comparator mode it is used to write a comparison value In A D conversion mode the successive appro
118. B Extended 100 COLMSKBEO lt Address H 0080 103A gt DO 1 2 3 4 5 6 D7 EIDOM EID1M EID2M EID3M When reset H 00 gt D Bit Name Function R 0 3 No functions assigned 0 4 7 EIDOM EID3M 0 ID not checked O Extended IDO to extended ID3 1 ID checked CANO Global Mask Register Extended ID1 COGMSKE1 lt Address H 0080 102B gt CANO Local Mask Register A Extended 101 COLMSKAE1 Address H 0080 1033 CANO Local Mask Register B Extended ID1 COLMSKBE1 Address H 0080 103B gt D8 9 10 11 12 13 14 D15 EIDAM 5 EIDeM EID7M EID8M EID9M EID10M EID11M When reset H 00 gt D Bit Name Function R 8 15 EIDAM EID11M 0 ID not checked Extended ID4 to extended ID11 1 ID checked 13 32 Ver 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers CANO Global Mask Register Extended ID2 COGMSKE2 lt Address H 0080 102C gt E CANO Local Mask Register A Extended 102 COLMSKAE2 Address H 0080 1034 CANO Local Mask Register B Extended 102 COLMSKBE2 Address H 0080 103 gt DO 1 2 3 4 5 6 D7 EID12M EID13M EID14M EID15M EID16M EID17M When reset H 00 gt D Bit Name Function R W 0 1 No functions assigned 0 2 7 EID12M EID17M 0 ID not checked Extended 1012 to extended ID17 1 ID checked Three registers are used in acceptance filtering Global Mask Register Local Ma
119. CHAPTER 2 CPU 2 1 GPU R6glslers ten thee A ee 2 2 2 2 General purpose Registers eee 2 2 2 3 Control Registers 2 3 2 3 1 Processor Status Word Register PSW 2 4 2 3 2 Condition Bit Register CBR 2 5 2 3 3 Interrupt Stack Pointer SPI 2 5 User Stack Pointer SPU CR3 2 3 4 Backup PC BPC 6 2 5 2 4 Accum Ulatoi enini 2 6 2 5 Program Counter 1 aana naa ie aeaa oaan iaa tt andaa iiaa 2 6 2 6 Data Formats 2er eue EAA eee 2 7 26 1 Data Types oaii eee heec eee een 2 7 2 6 2 Data oui EE EE EESE 2 8 CHAPTER 3 ADDRESS SPACE 3 1 Outline of Address Space 3 2 3 2 Operation Modes 5 rti erre Lere 3 5 3 3 Internal ROM Area and Extended External 3 7 3 911 Internal ROM Area ie t ene Ue eere 3 7 3 3 2 Extended External Area 3 7 3 4 Internal RAM Area and SFR Area nnn 3 8 3 4 1 Internal RAM
120. Control branches to the address H 0000 0010 in the user space This is the last operation performed in hardware preprocessing by the M32R E 5 Jumping from the EIT vector entry to the user created handler The M32R E executes the BRA instruction written at address H 0000 0010 of the EIT vector entry by the user to jump to the start address of the user created handler The system break interrupt can only be used when some fatal event has occurred to the system Also this interrupt must be used on condition that after processing by the SBI handler control will not return to the program that was being executed when the system break interrupt occurred 4 17 Ver 0 10 4 4 9 Interrupt Processing 4 9 3 External Interrupt EI An external interrupt is generated upon an interrupt request which is output by the 32171 s internal interrupt controller The interrupt controller manages interrupt requests by assigning each one of seven priority levels For details refer to Chapter 5 Interrupt Controller For details about the interrupt sources refer to each section in which the relevant internal peripheral I O is described Occurrence Conditions External interrupts are managed based on interrupt requests from each internal peripheral I O by the 32171 s internal interrupt controller These interrupt requests are notified to the M32R CPU by the interrupt controller The MS2R E checks these interrupt requests at a break in instr
121. DMABS Destination Address Register DM8DA H 0080 044E H 0080 0450 DMA4 Channel Control Register DMACNT DMA4 Transfer Count Register DM4TCT H 0080 0452 DMA4 Source Address Register DM4SA H 0080 0454 DMAA Destination Address Register DM4DA H 0080 0456 H 0080 0458 DMA9 Channel Control Register DM9CNT DMA6 Transfer Count Register DM9TCT H 0080 045A DMA9 Source Address Register DM9SA H 0080 045C DMA9 Destination Address Register DM9DA H 0080 045E H 0080 0460 DMAO Software Request Generation Register DMOSRI H 0080 0462 DMAt1 Software Request Generation Register DM1SRI H 0080 0464 DMA2 Software Request Generation Register DM2SRI H 0080 0466 DMAS Software Request Generation Register DM3SRI H 0080 0468 DMA4 Software Request Generation Register DM4SRI H 0080 0470 DMAS Software Request Generation Register DM5SRI H 0080 0472 DMA6 Software Request Generation Register DM6SRI H 0080 0474 DMA7 Software Request Generation Register DM7SRI H 0080 0476 DMAS Software Request Generation Register DM8SRI H 0080 0478 DMA9 Software Request Generation Register DM9SRI H 0080 0700 PO Data Register PODATA P1 Data Register P1DATA H 0080 0702 P2 Data Register P2DATA Data Register H 0080 0704 P4 Data Register PADATA H 0080 0706 P6 Data Register 6 P7 Data Register H 0080 0708 P8 Data Regis
122. Falling edge to t Internal edge signal Both edges wo 5 e Internal edge signal Low level TCLK PSC x clock width or TCLK x input Internal edge signal High level TIN 1 T PSC x clock width or TCLK x input Internal edge signal 10 17 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer Input Processing Control Register TCLKCR Address H 0080 0210 D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 me When reset H 0000 gt D Bit Name Function R 0 1 No functions assigned 0 2 3 5 00 1 2 internal peripheral clock O O input 01 Rising edge processing selection 10 Falling edge 11 Both edges 4 No functions assigned 0 5 7 1 25 000 Invalidates input O O 2 input 001 Rising edge processing selection 010 Falling edge 011 Both edges 10X Low level 11X High level 8 No functions assigned 0 9 11 TCLK1S 000 Invalidates input input 001 Rising edge processing selection 010 Falling edge 011 Both edges 10X Low level 11X High level 12 13 No functions assigned 0 E 14 15 TCLKOS 00 1 2 internal peripheral clock O O TCLKO input 01 Rising edge processing selection 10 Falling edge 11 Both edges Note This register must always be accessed in halfwords 10 18 Ver 0 10 1 0 MULTIJUNCTION T
123. Finished storing received data Clear receive request Transmit data frame Transmit data frame Clear receive request B 0000 0010 B 0110 0010 Finished Finished transmitting transmitting data frame data frame B 0110 0001 B 0000 0001 received data received data Clear Pse Clear receive requesi request B 00001010 amp B 0110 1010 B 01111010 B 0000 1010 Ce Shige 5 Finished Finished CMM Finished storing storing storing received Cei fec received data received data data ies Write H 70 automatic response enable B 0111 1000 Store received dat B 0111 0000 0000 0000 Figure 13 8 2 Operation of the CAN Message Slot Control Register when Receiving Remote Frames 13 80 Ver 0 10 CHAPTER 14 REAL TIME DEBUGGER RTD 14 1 Outline of the Real Time Debugger RTD 14 2 Pin Function of the RTD 14 3 Functional Description of the RTD 14 4 Typical Connection with the Host 1 4 REAL TIME DEBUGGER RTD 14 1 Outline of the Real Time Debugger RTD 14 1 Outline of the Real Time Debugger RTD The Real Time Debugger RTD is a serial I O through which to read or write to the internal RAM s entire area using commands from outside the microprocessor Because data transfers between the RTD and internal RAM are performed using an internal dedicated bus independently of the M32R CPU operation can be controlled without having the stop the M32R CPU Table 14 1
124. H 0000 6 7 TSP D6 D7 Time stamp prescaler 0 0 Selects CAN bus bit clock 0 1 Selects CAN bus bit clock divided by 2 1 0 Selects CAN bus bit clock divided by 3 1 1 Selects CAN bus bit clock divided by 4 8 9 No functions assigned 0 10 No functions assigned Always write a 0 0 11 FRST 0 Negates rest Forcible reset 1 Forcibly resets 12 BCM 0 Disables BasicCAN function BasicCAN mode 1 BasicCAN mode 13 No functions assigned 0 14 LBM 0 Disables loopback function O O Loopback mode 1 Enables loopback function 15 RST 0 Negates reset O O CAN reset 1 Requests reset W A Only writing a 1 is effective Automatically cleared to 0 in hardware 13 8 Ver 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers 1 RBO Return Bus Off bit D4 Setting this bit to 1 clears the Receive Error Counter CANOREC and Transmit Error Counter and forcibly places the CAN module into an error active state This bit is cleared when an error active state is entered Note After clearing the error counter transmission becomes possible when 11 consecutive recessive bits are detected on the CAN bus 2 TSR Time Stamp Counter Reset bit D5 Setting this bit to 1 clears the value of the CAN Time Stamp Counter Register CANOTSTMP to H 0000 This bit is cleared when the value of the CAN Time Stamp Counter Register CANOTSTMP is cleared to H 0000 3 TSP Time Stam
125. H 0000 007 in the user space This is the last operation performed in hardware preprocessing by the M32R E 5 Jumping from the EIT vector entry to the user created handler The M32R E executes the BRA instruction written at addresses H 0000 0040 through H 0000 007C of the EIT vector entry by the user to jump to the start address of the user created handler At the beginning of the EIT handler you created first save the BPC and PSW registers and the necessary general purpose registers to the stack 6 Returning from the EIT handler Atthe end of the EIT handler restore the general purpose registers and the BPC and PSW registers from the stack and then execute the RTE instruction As you execute the RTE instruction hardware postprocessing is automatically performed by the M32R E 4 21 Ver 0 10 4 EIT 4 11 EIT Priority Levels 4 11 EIT Priority Levels The table below lists the priority levels of EIT events When multiple EITs occur simultaneously the event with the highest priority is accepted first Table 4 11 1 Priority of EIT Events and How Returned from EIT Priority EIT Event Type of Processing Values Set in BPC Register 1 Highest Reset Interrupt RI Instruction processing Indeterminate aborted type Address Exception AE Instruction processing PC of the instruction that canceled type generated AE 5 Reserved Instruction Instruction processing PC of the instruction that Exception RIE
126. H 0080 0368 H 0080 036A TIO6 Control Register TIO6CR TIO7 Control Register TIO7CR H 0080 0370 TIO7 Coun ter 7 H 0080 0372 H 0080 0374 7 Reload 1 Register TIO7RL1 H 0080 0376 TIO7 Reload 0 ure Register TIO7RLO H 0080 0380 TIO8 Coun ter TIO8CT H 0080 0382 H 0080 0384 TIO8 Reload 1 Register TIO8RL1 H 0080 0386 TIO8 Reload 0 Meas ure Register TIO8RLO H 0080 0388 H 0080 038A TIO8 Control Register TIO8CR TIO9 Control Register TIO9CR H 0080 0390 TIO9 ter 9 H 0080 0392 H 0080 0394 TIO9 Reload 1 Register TIO9RL1 H 0080 0396 TIO9 Reload 0 Meas ure Register TIO9RLO 2 Blank are reserved areas Figure 3 4 7 Register Mapping of the SFR Area 5 3 14 Ver 0 10 3 ADDRESS SPACE 3 4 Internal ROM SFR Area Address 0 Address 1 Address 0080 03BC TIOO 9 Enable Protect Register TIOPRO H 0080 03BE 0 9 Count Enable Register TIOCEN H 0080 03 0 TMSO Counter TMSOCT H 0080 03C2 TMSO Measure 3 Register TMSOMR3 H 0080 03C4 TMSO Measure 2 Register TMSOMR2 H 0080 03C6 TMSO Measure 1 Register TMSOMR1 H 0080 03C8 TMSO Measure 0 Register 50 0 H 0080 03CA TMSO Control Register TMSOCR TMS1 Control Register TMS1CR H 0080 0300 TMS1 Counter TMS1CT H 0080 03D2 TMS1 Measure 3
127. Interrupt Mask Register CANOSLIMK H 0080 1012 H 0080 1014 CANO Error Interrupt Status Register CANOERIST CANO Error Interrupt Mask Register CANOERIMK H 0080 1016 CANO Baud Rate Prescaler CANOBRP H 0080 1028 CANO Global Mask Register Standard IDO COGMSKSO CANO Global Mask Register Standard ID1 COGMSKS1 H 0080 102A CANO Global Mask Register Extended 100 COGMSKEO CANO Global Mask Register Extended ID1 COGMSKE1 H 0080 102C CANO Global Mask Register Extended ID2 COGMSKE2 H 0080 102 H 0080 1030 CANO Local Mask Register A Standard IDO COLMSKASO CANO Local Mask Register A Standard ID1 COLMSKAS1 H 0080 1032 CANO Local Mask Register A Extended 100 COLMSKAEO CANO Local Mask Register A Extended ID1 COLMSKAE1 H 0080 1034 CANO Local Mask Register A Extended ID2 COLMSKAE2 H 0080 1036 H 0080 1038 CANO Local Mask Register B Standard IDO COLMSKASO CANO Local Mask Register B Standard ID1 COLMSKAS1 H 0080 103A CANO Local Mask Register B Extended IDO COLMSKAEO CANO Local Mask Register B Extended ID1 COLMSKAE1 H 0080 103C Local Mask Register B Extended ID2 COLMSKAE2 H 0080 1050 CANO Message Slot 0 Control Register COMSLOCNT CANO Message Slot 1 Control Register COMSL1CNT H 0080 1052 CANO Message Slot 2 Control Register COMSL2CNT CANO Message Slot 3 Control Register COMSL3CNT H 0080 1054 CANO Message Slot 4 Control Register COMSL4CNT CANO Message Slot 5 Control Register COMSL5CNT H 0080 1056 CANO Message
128. Kbytes H 8000 3FFF H 007F FFFF H 8000 4000 H 0080 0000 16 Kbytes H 0080 3FFF H 0080 4000 Ghost area iri units of Internal RAM area 16 Mbytes 16 Kbytes H 0080 7FFF H 0080 8000 Reserved area 96 Kbytes Y a SS i H BFFF FFFF ut H BFFF FFFF H 0081 FFFF H C000 0000 Ben 7 H0082 0000 Ghost area System space units of 128 Kbytes H FFFF FFFF d H OOFF FFFF Notes 1 This location varies with chip mode settings 2 The boot program space can read out only when FP 1 MODO 1 and MOD1 0 Figure 3 1 1 Address Space of the M32171F4 3 3 Ver 0 10 3 ADDRESS SPACE 3 1 Outline of Address Space Extended external Logical address space of M32171F3 gt area 4 Mbytes EIT vector entry Logical address H 0000 0000 amp H 0000 0000 A Internal ROM area 16 Mbytes 1 H 0005 FFFF H 0006 0000 Reserved area 640 Kb 640 Kbytes Ho00F FFEF H 0010 0000 6 CSO area B 1 Mby Ghostarea H O01F FFFF in units of H 0020 0000 16 Mbytes H 002F FFFF H 0030 0000 Ghost area in CS1 v F H 003F FFFF H 0040 0000 8000 0000 8000 0000 1 BOOT ROM area 8 Kbytes H 8000 1FFF Ghost area H 8000 2000 4 Mbytes Reserved area 8 eoo 3FFF H 8000 4000 H 007F FFFF
129. Message Slot 13 Standard ID1 COMSL13SID1 H 0080 11D2 CANO Message Slot 13 Extended 00 COMSL13EIDO CANO Message Slot 13 Extended ID1 COMSL13EID1 H 0080 11D4 CANO Message Slot 13 Extended ID2 COMSL13EID2 CANO Message Slot 13 Data Length Register COMSL13DLC H 0080 11D6 CANO Message Slot 13 Data 0 COMSL13DTO CANO Message Slot 13 Data 1 COMSL13DT1 H 0080 11D8 CANO Message Slot 13 Data 2 COMSL13DT2 CANO Message Slot 13 Data 3 COMSL13DT3 H 0080 11DA CANO Message Slot 13 Data 4 COMSL13DT4 CANO Message Slot 13 Data 5 COMSL13DT5 H 0080 11DC CANO Message Slot 13 Data 6 COMSL13DT6 CANO Message Slot 13 Data 7 COMSL13DT7 H 0080 11DE CANO Message Slot 13 Time Stamp COMSL13TSP H 0080 11 0 CANO Message Slot 14 Standard IDO COMSL14SIDO CANO Message Slot 14 Standard ID1 COMSL14SID1 H0080 11E2 Message Slot 14 Extended IDO COMSL14EIDO CANO Message Slot 14 Extended ID1 COMSL14EID1 H0080 1164 CAN Message Slot 14 Extended ID2 14 102 CANO Message Slot 14 Data Length Register COMSL14DLC 0080 1166 CANO Message Slot 14 Data 0 COMSL14DTO CANO Message Slot 14 Data 1 COMSL14DT1 IES CANO Message Slot 14 Data 2 COMSL14DT2 CANO Message Slot 14 Data 3 COMSL14DT3 F10080 tTEA CANO Message Slot 14 Data 4 COMSL14DT4 CANO Message Slot 14 Data 5 COMSL14DT5 H 0080 11EC CANO Message Slot 14 Data 6 COMSL14DT6 CANO Message Slot 14 Data 7 COMSL14DT7 H 0080 11EE CANO Message Slot 14 Time Stamp COMSL14TSP H 00
130. Mode Control Register 1 External read write operations are performed using the address bus data bus and signals CSO CS1 RD BHE BLE WAIT and WR In external read cycle the RD signal goes low and BHE or BLE output for the byte position from which to read is pulled low reading data from only the byte position of the bus In external write cycle the WR signal goes low and BHE or BLE output for the byte position to which to write is pulled low writing data to the necessary byte position When an external bus cycle starts wait cycles are inserted as long as the WAIT signal is low Unless the WAIT signal is needed leave it held high During external bus cycle at least one wait cycle is inserted even for the shortest case access The shortest bus cycle is 2 BCLK periods When not using the WAIT function the pin can be used as P71 by setting the P7 Operation Mode Register P71MOD bit to 0 Bus free state internal bus access i BCLK 12 A30 7 7 CS0 CS1 AD oun WR BEEN BHE BLE MH DBO DB15 _ WAIT Note 1 Hi Z denotes high impedance state Note 2 BCLK is not output Figure 15 2 4 Internal Bus Access during Bus Free State 15 9 Ver 0 10 1 EXTERNAL BUS INTERFACE 15 2 Read Write Operations
131. Mode Register 0 s conversion completion bit is cleared to 0 The content of the Successive Approximation Register is cleared to H 0000 9 The A D Successive Approximation Register s most significant bit D6 is set to 1 The comparison voltage Vref note is fed from the D A converter into the comparator 5 The comparison voltage Vref and the analog input voltage VIN are compared with the comparison result stored in D6 If Vref VIN then D6 1 If Vref VIN then D6 2 0 Operations in steps 3 through above are executed for all other bits from D7 to D15 The value stored in the A D Successive Approximation Register at completion of the comparison of D15 is the final A D conversion result A D Successive Approximation Register ADOSAR D6 7 8 9 10 11 12 13 14 015 1st comparison 1 0 0 0 0 0 0 0 0 0 Vref gt VIN then 0 2nd comparison 19 9199 0 0 0 woarcvlthennX t Result of 1st comparison 3rd comparison n9 n8 1 0 0 0 0 0 0 0 jer Result of 2nd comparison 10th comparison n9 n8 n7 n6 n5 n4 n3 n2 nl 1 n9 n8 n7 n6 n5 n4 n3 n2 ni nO completed Figure 11 3 2 Changes of the A D Successive Approximation Register during A D Convert Operation Note The comparison voltage Vre
132. Output Interrupt Control Register 1 IMJTOCR1 MJT Output Interrupt Control Register 2 IMJTOCR2 MJT Output Interrupt Control Register 3 IMJTOCR3 H 0080 0076 H 0080 0078 H 0080 007A 0080 007C H 0080 007E 0080 0080 0080 0082 0080 0084 0080 0086 0080 0088 0 Successive Approximation Register ADOSAR H 0080 008A 0080 008 MJT Output Interrupt Control Register 4 IMJTOCR4 MJT Output Interrupt Control Register 5 IMJTOCR5 IMJTOCR7 IMJTICR1 MJT Output Interrupt Control Register 6 IMJTOCR6 MJT Output Interrupt Control Register 7 MJT Input Interrupt Control Register 1 MJT Input Interrupt Control Register 2 IMJTICR2 MJT Input Interrupt Control Register 3 IMJTICR3 MJT Input Interrupt Control Register 4 IMJTICR4 A DO Single Mode Register 0 ADOSIMO A DO Single Mode Register 1 ADOSIM1 A DO Scan Mode Register 0 ADOSCMO A DO Scan Mode Register 1 ADOSCM1 H H H A DO Comparate Data Register ADOCMP 10 bit A DO Data Register 0 ADODTO 10 bit A DO Data Register 1 ADODT1 H 0080 0090 H 0080 0092 H 0080 0094 H 0080 0096 H 0080 0098 H 0080 009A H 0080 009C H 0080 009E H 0080 00A0 H 0080 00A2 H 0080 00A4 H 0080 00A6 H 0080 00A8 10 bit A DO Data Register 2 ADODT2 10 bit A DO Data Register ADODT3 10 bit A DO Data Register 4 ADODT4 10 bit Data Register 5 ADODT5 10 bit A DO Data
133. P112 operation mode 1 TO2 11 P113MOD 0 P113 Port P113 operation mode 1 12 P114MOD 0 P114 Port P114 operation mode 1 04 13 P115MOD 0 P115 Port P115 operation mode 1 TO5 14 P116MOD 0 P116 Port P116 operation mode 1 06 15 P117MOD 0 P117 Port P117 operation mode 1 TO7 8 14 Ver 0 10 INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 3 Input Output Port Related Registers E P12 Operation Mode Register P12MOD Address H 0080 074C gt DO 1 2 3 4 5 6 D7 P124MOD P125MOD P126MOD P127MOD When reset 00 gt D Bit Name Function R 0 3 No functions assigned 0 4 P124MOD 0 P124 Port P124 operation mode 1 TCLKO 5 P125MOD 0 P125 Port P125 operation mode 1 TCLK1 6 P126MOD 0 P126 Port P126 operation mode 1 TCLK2 7 P127MOD 0 P127 O Port P127 operation mode 1 TCLK3 Note Ports P120 P123 are not accommodated 8 15 Ver 0 10 8 INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 3 Input Output Port Related Registers E P13 Operation Mode Register P13MOD Address H 0080 074D D8 9 10 11 12 13 14 D15 P180MOD P131MOD P132MOD P133MOD P134MOD P135MOD P136MOD P137MOD When reset 00 gt D Bit Name Function R 8 P130MOD 0 P130 Port P130 operation mode 1 TIN16 9 P131MOD 0 P131 Port P131 operation mode 1 TIN1
134. POWER UP POWER SHUTDOWN SEQUENCE 20 1 Configuration of the Power Supply Circuit 20 2 20 2 Power On Sequence 20 3 20 2 1 Power On Sequence When Not Using RAM Backup 20 3 20 2 2 Power On Sequence When Using RAM Backup 20 4 20 3 Power Shutdown Sequence eese essen nennen nannten 20 5 20 3 1 Power Shutdown Sequence When Not Using RAM Backup 20 5 20 3 2 Power Shutdown Sequence When Using RAM Backup 20 6 CHAPTER 21 ELECTRICAL CHARACTERISTICS 21 1 Absolute Maximum 5 21 2 21 2 Recommended Operating Conditions eere 21 3 21 3 DC Characteristics ciere gener Pea 21 5 21 3 1 Electrical Characteristics 21 5 21 3 2 Flash Related Electrical Characteristics 21 10 21 4 Conversion Characteristics eese 21 11 215 AC Characteristics eie LEAL Liu 21 12 21 5 1 Timing 21 12 21 5 2 Switching Characteristics sees 21 15 21 5 3 AC 21
135. RTDACK signal is pulled low making it possible to verify the communication status When issuing the VER command the RTDACK signal goes low for only one clock period Therefore after sending 32 bits in one frame turn off RTDCLK output and check whether RTDACK is low If RTDACK is low you know that the RTD is communicating normally If you want to identify the type of transmitted command by the width of RTDACK use the 32171 s internal measurement timer to count RTDCLK pulses while RTDACK is low or create a dedicated circuit Transfer of next frame Transfer of 1 frame 32 bits gt lt ean 1 2 ok y T RTDRXD 8 bits X 8 bits X 8 bits RTDTXD X e RTDACK Check the RTDACK signal L level Figure 14 4 2 Typical Operation for Communication with the Host when Issuing VER Command 14 15 Ver 0 10 14 REAL TIME DEBUGGER RTD 14 4 Typical Connection with the Host This is a blank page 14 16 Ver 0 10 CHAPTER 15 EXTERNAL BUS INTERFACE 15 1 External Bus Interface Related Signals 15 2 Read Write Operations 15 3 Bus Arbitration 15 4 Typical Connection of External Extension Memory 1 EXTERNAL BUS INTERFACE 15 1 External Bus Interface Related Signals 15 1 External Bus Interface Related Signals The 32171 comes with external bus interface related si
136. Receive finished bit Overrun error bit SIO receive interrupt A Receive finished interrupt Note 2 T1 Note 5 Overrun error bit cleared Note 4 Note 1 When receive finished interrupt is selected When receive error Interrupt request accepted Note 5 AUR Receive error interrupt Note 3 EE interrupt is selected Note 1 Processing by software XN Interrupt generation Change of the Interrupt Controller SIO Receive Interrupt Control Register interrupt request bit Note 2 When receive finished interrupt is enabled Note 3 When receive error interrupt is enabled Note 4 This is done by clearing the receive enable bit to 0 Note 5 interrupt request bit cleared The Interrupt Controller register is read or SIO Receive Interrupt Control Register Interrupt request accepted Note 5 Figure 12 7 4 Example of UART Reception When Overrun Error Occurred 12 57 Ver 0 10 1 2 SERIAL I O 12 8 Fixed Period Clock Output Function 12 8 Fixed Period Clock Output Function When using SIOO or SIO1 in UART mode you can choose the relevant port P84 or P87 to function as the SCLKOO or SCLKO1 pin In this way a clock derived from BRG output by dividing it by 2 can be output from the SCLKO pin Note This clock is output all the time not just during data transf
137. SERIAL I O 12 3 Transmit Operation in CSIO Mode The following processing is automatically executed in hardware CSIO transmit operation starts Transmit conditions met Note Transmit interrupt Transfer content of transmit buffer to request transmit shift register Ax Transmit DMA Set transmit buffer empty bit to 1 transfer request i Transmit data Transmit conditions met Clear transmit status bit to 0 Y Successive transmission CSIO transmit operation completed Note This applies when transmit interrupt has been enabled by SIO Interrupt Mask Register Figure 12 3 2 Transmit Operation during CSIO Mode Hardware Processing 12 30 Ver 0 10 1 2 SERIAL I O 12 3 Transmit Operation in CSIO Mode 12 3 8 Typical CSIO Transmit Operation The following shows a typical transmit operation in CSIO mode lt CSIO on transmit side gt lt CSIO on receive side gt SCLKO gt SCLKI TXD e NA RXD Internal clock selected External clock selected CSIO on transmit side Transmit clock SCLKO yiviviviviviviv t Set Transmit enable bit Write to transmit buffer register Cleared Transmit buffer empty bit i 4 Content of transmit buffer em register tra
138. Slot Control Register s TRSTAT Transmit Receive Status bit to 1 thereby starting transmission 3 If the CAN module lost bus arbitration or a CAN bus error occurs If the CAN module lost bus arbitration or a CAN bus error occurs while transmitting the CAN module clears the CAN Message Slot Control Register s TRSTAT Transmit Receive Status bit to 0 If the CAN module requested a transmit abort the transmit abort is accepted and writing to the message slot is enabled 4 Completion of data frame transmission When data frame transmission is completed the CAN Message Slot Control Register s TRFIN Transmit Receive Finished bit and the CAN Slot Interrupt Status Register are set to 1 Also a time stamp count value at the time transmission was completed is written to the CAN Message Slot Time Stamp COMSLnTSP and the transmit operation is thereby completed If the CAN slot interrupt has been enabled an interrupt request is generated at completion of transmit operation The slot which has had transmission completed goes to an inactive state and remains inactive neither transmit nor receive until it is newly set in software 13 61 Ver 0 10 CAN MODULE 13 13 5 Transmitting Data Frames B 0000 0000 Note D Transmit aborted Waiting for B 1000 0000 transmission Lost bus arbitration BE bus error occurred Write H 80 Transmit request accepted Transmit aborted B 1000 0010
139. Slot 0 Standard ID1 COMSLOSID1 Address H 0080 1101 CANO Message Slot 1 Standard ID1 COMSL1SID1 Address H 0080 11112 CANO Message Slot 2 Standard ID1 COMSL2SID1 Address H 0080 11212 E CANO Message Slot Standard ID1 COMSL3SID1 Address H 0080 1131 E CANO Message Slot 4 Standard ID1 COMSL4SID1 Address H 0080 1141 E CANO Message Slot 5 Standard ID1 COMSL5SID1 Address H 0080 1151 E CANO Message Slot 6 Standard ID1 COMSL6SID1 Address H 0080 1161 CANO Message Slot 7 Standard ID1 COMSL7SID1 Address H 0080 11712 E CANO Message Slot 8 Standard ID1 COMSL8SID1 Address H 0080 1181 E CANO Message Slot 9 Standard ID1 COMSL9SID1 Address H 0080 1191 E CANO Message Slot 10 Standard 101 COMSL10SID1 Address H 0080 11 1 gt E CANO Message Slot 11 Standard 101 COMSL11SID1 Address H 0080 11 1 gt E CANO Message Slot 12 Standard 101 COMSL12SID1 Address H 0080 11C1 gt E CANO Message Slot 13 Standard 101 COMSL13SID1 Address H 0080 11D1 gt E CANO Message Slot 14 Standard 101 COMSL14SID1 Address H 0080 11 1 gt E CANO Message Slot 15 Standard 101 COMSL15SID1 Address H 0080 11 1 gt D8 9 10 11 12 13 14 D15 SID5 SID6 SID7 SID8 SID9 SID10 When reset Indeterminate gt D Bit Name Function R 8 9 No functions assigned 0 10 15 SID5 SID10 Standard ID5 to standard ID10 Standard ID5 to standard ID10 These registers are the transmit f
140. TINIM21 b6 F F TIN20edge TINIS20 b3 F F A p TINIM20 57 F F Figure 10 2 16 Block Diagram of MJT Input Interrupt 3 10 44 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer 10 3 TOP Output related 16 bit Timer 10 3 1 Outline of TOP TOP Timer Output is an output related 16 bit timer whose operation mode can be selected from the following by mode switching in software Single shot output mode Delayed single shot output mode Continuous output mode The table below shows specifications of TOP The diagram in the next page shows a block diagram of TOP Table 10 3 1 Specifications of TOP Output related 16 bit Timer Item Specification Number of channels 11 channels Counter 16 bit down counter Reload register 16 bit reload register Correction register 16 bit correction register Timer startup Started by writing to enable bit in software or by enabling with external input rising or falling edge or both Mode selection With correction function Single shot output mode Delayed single shot output mode Without correction function Continuous output mode Interrupt generation Can be generated by a counter underflow 10 45 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer
141. TML 32 bit measure input No signal generation function Note 5 6 output underflow signals to the input event bus 10 11 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer Clock bus Input event bus Output event bus 3210 3210 0123 TOP 6 udf S o TCLKO TCLKOS 7 oo 4 TINO TINOS i TOP 8 udf 9 4 TIN3S o t TIO 0 udf o o TIO 1 udf 4 2 TIO 3 udf TIO 4 udf lt 1 2 internal PSCO 1 T m rm peripheral LPSC M clock PSC2 Lo 7o lt 5 5 udf TCLK3 TCLK3S 6 udf e 3210 3210 TO 7 udi TIO 8 udf PSCO Prescaler S Selector 0123 Figure 10 2 2 Conceptual Diagram of the Clock Bus and Input Output Event Bus 10 12 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer The clock bus input output bus control unit has the following registers Clock Bus amp Input Event Bus Control Register CKIEBCR Output Event Bus Control Register OEBCR Clock Bus amp Input Event Bus Control Register CKIEBCR Address H 0080 0201 gt D8 9 10
142. TMLOCR Address H 0080 0 gt D8 9 10 11 12 13 14 D15 TMLOSSO TMLOSS1 TMLOSS2 TMLOSS3 TMLOCKS When reset H 00 gt D Bit Name Function R 8 10550 0 External input TIN23 TMLO measure 0 source selection 1 Input event bus 0 9 TMLOSS1 0 External input TIN22 TMLO measure 1 source selection 1 Input event bus 1 10 TMLOSS2 0 External input TIN21 TMLO measure 2 source selection 1 Input event bus 2 11 TMLOSS3 0 External input TIN20 Q Q TMLO measure 3 source selection 1 Input event bus 3 12 14 functions assigned 0 15 TMLOCKS 0 1 2 internal peripheral clock TMLO clock source selection 1 Clock bus 1 The TMLO Control Register is used to select TMLO input event and the counter clock source Note The counter can be written to normally only when the selected clock source is a 1 2 internal peripheral clock When using any other clock source you cannot write to the counter normally Under this condition do not write to the counter 10 134 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 6 TML Input related 32 bit Timer E TML1 Control Register TML1CR Address H 0080 gt D8 9 10 11 12 13 14 D15 TML1SS0 TML1SS1 TML1SS2 TML1SS3 TML1CKS When reset H 00 gt D Bit Name Function R 8 1550 0 No selection TML1 measure 0 source selection 1 Input event bus 0 9 TML1SS1
143. This signal changes state on falling edges of JTCK and is output only in Shift IR or Shift DR state JTMS Test mode select Input Test mode select input to control the test circuit s state transitions This input is sampled on rising edges of JTCK JTRST Testreset Input Active low test reset input to initialize the test circuit asynchronously To ensure that the test circuit is reset without fail JTMS signal input must be held high while this signal changes state from low to high Note TAP Test Access Port a JTAG interface stipulated in IEEE 1149 1 19 2 Ver 0 10 1 9 JTAG 19 2 Configuration of the JTAG Circuit 19 2 Configuration of the JTAG Circuit The 32171 s JTAG circuit consists of the following blocks Instruction register to hold instruction codes which are fetched through the boundary scan path set of data registers which are accessed through the boundary scan path Test access port abbreviated TAP controller to control the JTAG unit s state transitions Control logic to select input output etc A configuration of the JTAG circuit is shown below M32R E Data register set Boundary scan register Et JTAGBSR Bypass register JTAGBPR ID code register JTAGIDR Decoder 5 JTDO 111111 Instruction register 6 bits JTAGIR JTMS _ JTCK M TAP controller JTRST Q
144. VCCI OV 3 3V FVCC OV 3 3V OSC VCC OV Turn on the 3 3 V power supply after turning on the 5 V power supply After turning on all power supplies and holding the RESET pin low for an oscillation stabilization time release the RESET pin input back high to deactivate reset Note Power on limitations VDD OSC VCC VCCI FVCC VCCE VCCI FVCC OSC VCC Figure 20 2 2 Power On Sequence When Using RAM Backup 20 4 Ver 0 10 20 POWER UP POWER SHUTDOWN SEQUENCE 20 3 Power Shutdown Sequence 20 3 Power Shutdown Sequence 20 3 1 Power Shutdown Sequence When Not Using RAM Backup The diagram below shows a power shutdown sequence 5 0 V 3 3 V power supply of the M32R E when not using RAM backup 5V VCCE ov AVCCO 5V ov VREFO 5V N ov TEE 5V gt RESET ov 3 3V VDD ov 3 3V ov 3 3V FVCC ov 3 3V OSC VCC ov D Pull the RESET pin input low 2 Turn off the 5 V and the 3 V power supply after the RESET pin goes low Note Power shutdown requirements VDD 2 VCCI z FVCC OSC VCC VCCI Figure 20 3 1 Power Shutdown Sequence When Not Using RAM Backup 20 5 Ver 0 10 20 20 3 2 Power Shutdown Sequence When Using RAM Backup The diagram below shows a power shutdown sequence 5 0 V 3 3 V power supply of the M32R E when using RAM backup 5V VCCE N AVCCO 5v N ov VREFO 5V Q ov 5V P
145. WRERR2 1 the operation terminated in an error The condition under which WRERR2 is set to 1 is when the flash memory could not be written to by repeating the write operation a specified number of times Note This status register is included in the internal flash memory itself and can be read out by writing the Read Status Command H 7070 to any address of the flash memory For details refer to Section 6 5 Programming of Internal Flash Memory 6 7 Ver 0 10 6 INTERNAL MEMORY 6 4 Registers Associated with the Internal Flash Memory 6 4 3 Flash Controle Registers E Flash Controle Register 1 FCNT1 Address H 0080 07 2 gt DO 1 2 3 4 5 6 D7 When reset 00 gt D Bit Name Function R 0 2 No functions assigned 0 3 FENTRY 0 Normal read O O Flash mode entry 1 Erase program enable 4 6 No functions assigned 0 mE 7 FEMMOD 0 Normal mode Virtual flash emulation mode 1 Virtual Flash emulation mode The Flash Control Register 1 FCNT1 consists of the following two bits to control the internal flash memory 1 FENTRY Flash Mode Entry bit D3 The FENTRY bit controls entry to flash E W enable mode Flash E W enable mode can be entered only when FENTRY 1 To set the FENTRY bit to 1 write a 0 and then a 1 to the FENTRY bit in succession while the FP pin high The FENTRY bit is cleared in the following cases When the device is reset e When a 0 is written to the FENTRY bit
146. When serial 1 0 transmit buffer is emptied Serial 1 reception completed When serial l O1 reception is completed MJT TINO input signal When MJT s TINO input signal is generated Causes of DMA Requests in DMA4 and Generation Timings Cause of DMA Request DMA Request Generation Timing Software start When any data is written to DMA4 Software Request Generation Register One transfer completed When one DMAS transfer is completed cascade mode Serial 1 00 reception completed When serial 1 0 reception is completed MJT TIN19 input signal When MJT s TIN19 input signal is generated 9 28 Ver 0 10 DMAC 9 3 Functional Description of the DMAC Table 9 3 6 Causes of DMA Requests in 5 and Generation Timings REQSL5 Cause of DMA Request 0 0 Software start or one DMA7 transfer completed DMA Request Generation Timing When any data is written to DMA5 Software Request Generation Register or one DMA7 transfer is completed cascade mode 0 1 DMAO transfers completed When all DMAO transfers are completed cascade mode 1 0 Serial l O2 reception completed When serial 2 reception is completed 1 1 MJT TIN20 input signal When MJT s TIN20 input signal is generated Table 9 3 7 Causes of DMA Requests in DMA6 and Generation Timings REQSL6 Cause of DMA Request 0 0 Software start DMA Request Generation Timing When any data is written to DMA6 Software Request
147. When the FP pin changes state from high to low 6 8 Ver 0 10 INTERNAL MEMORY 6 4 Registers Associated with the Internal Flash Memory When using a program in the flash memory while the FENTRY bit 0 the El vector entry is located at address H 0000 0080 of the flash memory When running a flash rewrite program in RAM while the FENTRY bit 1 the El vector entry is located at address H 0080 4000 of the RAM allowing for flash rewrite operation to be controlled using interrupts Table 6 4 1 Changes of El Vector Entry by FENTRY FENTRY Vector Entry Address 0 Flash memory area H 0000 0080 1 Internal RAM area H 0080 4000 2 FEMMOD Virtual Flash Emulation Mode bit D7 The FEMMOD bit controls entry to Virtual flash emulation mode Virtual flash emulation mode is entered by setting the FEMMOD bit to 1 while the FENTRY bit 0 For details refer to Section 6 7 Virtual Flash Emulation Function 6 9 Ver 0 10 6 INTERNAL MEMORY 6 4 Registers Associated with the Internal Flash Memory E Flash Controle Register 2 FCNT2 Address H 0080 07 gt D8 9 10 11 12 13 14 D15 When reset 00 gt D Bit Name Function R 8 14 functions assigned 0 15 FPROT 0 Protection by lock bit effective O O Unlock 1 Protection by lock bit not effective The Flash Control Register 2 FCNT2 controls invalidation of the internal flash memory protection by a lock bit to disable erasing or programming of t
148. X RDR A1 y RDR A2 y RDR A3 RTDTXD exe DX X D A1 X D A2 4 RTDACK lt gt 2 clock periods Note An Specified address D An Data at specified address An Figure 14 3 2 Operation of the RDR Command 14 5 Ver 0 10 1 4 REAL TIME DEBUGGER RTD 14 3 Functional Description of the RTD LSB side MSB side 31 30 1 0 1031030 Di DO RTDTXD Read data Note Note The read data is transferred LSB first Figure 14 3 3 Read Data Transfer Format 14 6 Ver 0 10 1 4 REAL TIME DEBUGGER RTD 14 3 Functional Description of the RTD 14 3 3 Operation of WRR RAM Content Forcible Rewrite When the WRR RAM content forcible rewrite command is issued the RTD forcibly rewrites the contents of the internal RAM without causing the CPU s internal bus to stop Because the RTD writes data to the internal RAM while no transfers are being performed between the CPU and internal RAM no extra load is levied on the CPU The address to be read from the internal RAM can only be specified on 32 bit word boundaries The two low order address bits specified by a command are ignored Note also that data are written to the internal RAM in units of 32 bits The external host should transmit the command and addre
149. a 0 in software When writing to the CAN slot interrupt status make sure the bits you want to clear are set to 0 and all other bits are set to 1 The bits thus set to 1 are unaffected by writing in software and retain the value they had before you write Note 1 If the automatic response function is enabled for remote frame receive slots the status is set after the CAN module received a remote frame and when it transmitted a data frame Note 2 For remote frame transmit slots the status is set after the CAN module transmitted a remote frame and when it received a data frame Note 3 If the status is set by an interrupt request at the same time it is cleared in software the former has priority so that the status is set 13 23 Ver 0 10 13 CAN MODULE 13 2 CAN Module Related Registers CANO Slot Interrupt Mask Register CANOSLIMK Address H 0080 1010 2 DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 IRBO IRB1 IRB2 IRB3 IRB4 IRB5 IRB6 IRB7 IRB8 IRB9 IRB10 IRB11 IRB12 IRB13 IRB14 IRB15 When reset H 0000 gt D Bit Name Function R 0 IRBO Slot 0 interrupt request mask 0 Masks disables interrupt request 1 IRB1 Slot 1 interrupt request mask 1 Enables interrupt request 2 IRB2 Slot 2 interrupt request mask 3 IRB3 Slot 3 interrupt request mask 4 4 Slot 4 interrupt request mask 5 IRB5 S
150. amp outputs X 116 0 Z amp control 0 amp Figure 19 5 11 BSDL Description for the 32171 11 14 19 25 Ver 0 10 19 JTAG 19 5 Boundary Scan Description Language ARA EAE 62 69 LOLL CX1E9 62 62 02 p OO ee eem e ue gp pPpOmeo DC EUN BONUS 92 69 62 6 09 CC P16 P16 P17 P17 P174 P174 P175 P175 P82 P82 P83 P83 P84 P84 P85 P85 P86 P86 P87 P87 P61 P61 P62 P62 P63 P63 P64 P70 P70 P71 P71 P72 P72 P73 P73 observe only X amp output X 113 0 2 amp control 0 amp observe_only X amp output X 110 0 2 amp control 0 amp observe only X amp output X 107 0 2 amp control 0 amp observe_only X amp output X 104 0 2 amp control 0 amp observe_only X amp output X 101 0 2 amp control 0 amp observe_only X outputs X 98 0 2 amp control 0 amp observe_only X amp output X 95 0 Z amp control 0 amp observe_only X amp output3 X 92 0 Z amp control 0 amp observe_only X amp output X 89 0 2 amp control 0 amp obs
151. and their specified addresses when writing the Verify command data 6 26 Ver 0 10 INTERNAL MEMORY 6 5 Programming of the Internal Flash Memory Table 6 5 3 M32171F4 Target Blocks and Specified Addresses Target Block Specified Address 0 H 0000 3FFE 1 H 0000 5FFE 2 H 0000 7FFE 3 H 0000 FFFE 4 H 0001 FFFE 5 H 0002 FFFE 6 H 0003 FFFE 7 H 0004 FFFE 8 H 0005 FFFE 9 H 0006 FFFE 10 H 0007 FFFE Table 6 5 4 M32171F3 Target Blocks and Specified Addresses Target Block Specified Address 0 H 0000 3FFE 1 H 0000 5FFE 2 H 0000 7FFE 3 H 0000 FFFE 4 H 0001 FFFE 5 H 0002 FFFE 6 H 0003 FFFE 7 H 0004 FFFE 8 H 0005 FFFE 6 27 Ver 0 10 INTERNAL MEMORY 6 5 Programming of the Internal Flash Memory M32171F4 s Internal Flash Memory Area 512KB H 0000 0000 H 0000 3FFF H 0000 4000 H 0000 5FFF H 0000 6000 0000 7FFF H 0000 8000 H 0000 FFFF H 0001 0000 H 0001 FFFF H 0002 0000 H 0002 FFFF H 0003 0000 H 0003 FFFF H 0004 0000 H 0004 FFFF H 0005 0000 H 0005 FFFF H 0006 0000 H 0006 FFFF H 0007 0000 H 0007 FFFF Block 0 Block 1 Block 2 Block 3 Block 4 5 7 6 Block 7 8 9 Block 10 Uneven blocks Even blocks 6 28 Figure 6 5 7 Block Configuration of the M32171F4 Flash Memory Ver 0 10 INTERNAL MEMORY
152. assigned 0 9 ADOCSPD 0 Normal Q Q A DO conversion rate selection 1 x2 10 11 No functions assigned 0 12 15 05 When written to 6 A DO scan loop selection 01XX 4 channel scan 10XX 8 channel scan 11XX 16 channel scan 00 16 channel scan When read during conversion 0000 Converting ADOINO 0001 Converting ADOIN1 0010 Converting ADOIN2 0011 Converting ADOIN3 0100 Converting ADOIN4 0101 Converting ADOIN5 0110 Converting ADOIN6 0111 Converting ADOIN7 1000 Converting ADOIN8 1001 Converting ADOIN9 1010 Converting ADOIN10 1011 Converting ADOIN11 1100 Converting ADOIN12 1101 Converting ADOIN13 1110 Converting ADOIN14 1111 Converting ADOIN15 A DO Scan Mode Register 1 is used to control operation of the A DO converter during scan mode 11 24 Ver 0 10 1 1 5 11 2 Converter Related Registers 1 ADOCSPD A DO conversion rate selection bit D9 This bit selects an A D conversion rate for the A DO converter during scan mode Setting this bit to 0 selects a normal speed and setting this bit to 1 selects a x2 speed two times normal speed 2 ANOSCAN A DO scan loop selection bits D12 D15 The ANOSCAN A DO scan loop selection bits set the channels to be scanned during scan mode of the A DO converter In this case writes to D14 and D15 have no effect The ANOSCAN A DO scan loop selection bits when read during scan operation show the status of the
153. be read and written to from both the internal RAM and the selected pseudo flash memory areas Figure 6 7 3 Pseudo Flash Emulation Areas of the M32171F4 Divided in Units of 4 Kbytes 6 42 Ver 0 10 INTERNAL MEMORY 6 7 Virtual Flash Emulation Function Internal flash H 0000 0000 L bank 0 I 8Kbytes Bc t Internal RAM H 0000 2000 L bank 1 Ee 8Kbytes 8Kbytes H 0080 4000 H 0000 4000 L bank 2 8Kbytes 4Kbytes 4Kbytes m n H 0005 C000 L bank 46 8Kbytes H 0005 E000 L bank 47 8Kbytes Note 1 If the Pseudo Flash Emulation Enable bit is enabled while the same bank area is set in multiple Pseudo Flash Bank Registers the internal RAM area 8 or 4 Kbytes to be allocated is selected by priority FELBANKO gt FESBANKO gt FESBANK 1 Note 2 When you access the 8 Kbyte area L bank selected by Pseudo Flash L Bank Register 0 you actually are accessing the internal RAM area During pseudo flash emulation mode the RAM can be read and written to from both the internal RAM and the selected pseudo flash memory areas Figure 6 7 4 Pseudo Flash Emulation Areas of the M32171F3 Divided in Units of 8 Kbytes Internal flash H 0000 0000 S bank 0 4Kbytes H 0000 1000 S bank 1 4Kbytes Internal RAM H 0000 2000 S bank 2 4Kbytes H 0080 4000 8Kbytes ND ZKoyies 40080 6000 E 4Kbytes H 0080 7000
154. bit and the content of the A DO Successive Approximation Register when read after being stopped shows an intermediate value that was in the middle of conversion No transfers to the A DO Data Register are performed If the A DO conversion start and A DO conversion stop bits are set to 1 simultaneously the A DO conversion stop bit is effective If this bit is set to 1 while single mode operation of special mode is under way forcible execution of single mode during scan mode operation only single mode conversion stops and scan mode operation restarts 11 17 Ver 0 10 1 1 5 11 2 Converter Related Registers 6 ADOSSTT A DO conversion start bit D7 A D conversion of the A DO converter is started by setting this bit to 1 while software trigger has been selected with the ADOSSEL A DO conversion start trigger select bit If the A DO conversion start and A DO conversion stop bits are set to 1 simultaneously the A DO conversion stop bit is effective When this bit is set to 1 during single mode conversion special operation mode Conversion restart is assumed so that conversion in single mode restarts When this bit is set to 1 during A D conversion in scan mode special operation mode Forcible execution of single mode during scan mode operation is assumed so that the channel being converted in scan mode is canceled and single mode conversion is performed When single mode conversion finishes
155. bit are set to 1 Note 1 If a receive finished interrupt has been selected by SIO Cause of Receive Interrupt Select Register neither a receive finished interrupt request nor a DMA transfer request is generated Note 2 If a receive error interrupt has been selected by SIO Cause of Receive Interrupt Select Register a receive error interrupt request is generated when interrupt requests are enabled No DMA transfer requests are generated 12 35 Ver 0 10 1 2 SERIAL I O 12 4 Receive Operation in CSIO Mode 12 4 4 About Successive Reception When the following conditions are met at completion of data reception data may be received successively The receive enable bit is set to 1 Transmit conditions are met No overrun error has occurred CSIO receive operation starts Receive conditions met Receive data Overrun error Set SIO Receive Control Register s Set SIO Receive Control Register s overrun error and receive receive finished bit to 1 sum error bits to 1 Store received data in Receive Buffer Register CSIO receive operation completed Figure 12 4 2 Receive Operation during CSIO Mode Hardware Processing 12 36 Ver 0 10 1 2 SERIAL I O 12 4 Receive Operation in CSIO Mode 12 4 5 Flags Indicating the Status of CSIO Receive Operation Following flags are available that indicate t
156. block Issue the Lock Bit Program command H 7777 to the memory block you want to protect b Setting the lock bit to 1 unprotect the block After setting the Flash Control Register 2 FPROT bit to invalidate lock bit effectuated protection use the Block Erase command H 2020 or Erase All Unprotect Block command H A7A7 to erase the memory block you want to unprotect This is the only way to unprotect a memory block You cannot set the lock bit alone to 1 C Status when the lock bit is reset The lock bit is unaffected by a reset or power outage because it is a nonvolatile bit 9 Execution flow of each command The diagrams below show an execution flow of each command START Write Read Array command H FFFF to any address of internal flash memory Read the internal flash memory address you want to read Figure 6 5 9 Read Array 6 32 Ver 0 10 INTERNAL MEMORY 6 5 Programming of the Internal Flash Memory START Write Page Program command H 4141 to any address of internal flash memory Write data to the internal flash memory address to which you want to write Note 1 Increment the previous write address by 2 and write the next data to the new address Programmed for one page Written to the internal flash memory by Page Program Note 2 1 us wait by hardware timer or software timer R
157. clock Logical address space 4Gbytes linear Extended external area Maximum 4 Mbytes External data bus 16 bits Implementation Five stage pipeline Internal 32 bit architecture for the core Register configuration General purpose register 32 bits x 16 registers Control register 32 bits x 5 registers Instruction set 16 bit and 32 bit instruction formats 83 distinct instructions and 9 addressing modes Built in multiplier accumulator 32 x 16 56 Table 1 2 2 Features of Internal Memory Functional Block RAM Features Capacity 16 Kbytes No wait access when operating with 40 MHz CPU clock By using RTD real time debugger the internal RAM can be accessed for read or rewrite from external devices independently of the M32R Flash memory Capacity M32171F4 512 Kbytes M32171F3 384 Kbytes No wait access when operating with 40 MHz CPU clock Durability Can be rewritten 100 times 1 8 Ver 0 10 OVERVIEW 1 2 Block Diagram Table 1 2 3 Features of Internal Peripheral Functional Block Features DMA 10 channel DMA Supports transfer between internal peripheral I Os and between internal peripheral I O and internal RAM Capable of advanced DMA transfer when operating in combination with internal peripheral I O Capable of cascaded connection between DMA channels DMA transfer in a channel is started by completion of transfer in another Multijunction 37 channel m
158. control registers and is partly Figure 10 4 5 Outline Diagram of 0 4 Clock Enable Inputs 10 92 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer E TIOO 3 Control Register 1 TIOOSCR1 lt Address H 0080 031D gt D8 9 10 11 12 13 14 015 003 5 When reset H 00 gt D Bit Name Function R 8 13 No functions assigned 0 14 15 TIOO3CKS 00 Clock bus 0 0 3 clock source selection 01 Clock bus 1 10 Clock bus 2 11 Clock bus 3 10 93 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer E TIO4 Control Register TIO4CR Address H 0080 034A DO 1 2 3 4 5 6 D7 TIO4CKS TIO4EEN TIOS4ENS 04 When reset H 00 gt D Bit Name Function R 0 1 TIO4CKS 00 Clock bus 0 4 clock source selection 01 Clock bus 1 10 Clock bus 2 11 Clock bus 3 2 TIO4EEN Note 1 0 Disables external input 4 external input enable 1 Enables external input 3 4 TIO34ENS OX No selection TIO3 4 enable measure 10 Input event bus 2 input source selection 11 Input event bus 3 5 7 TIO4M 000 Single shot output mode 4 operation mode selection 001 Delayed single shot output mode 010 Continuous output mode 011 PWM output mode 100 Measure clear input mode 101 Measure free run input mode 11X Noise processing input mode Note
159. conversion result Q This data register stores the 8 bit conversion data from the A DO converter In single mode of the A DO converter the result of A D conversion is stored in the 8 bit A DO Data Register for each corresponding channel In single shot and continuous scan modes the content of the A DO Successive Approximation Register is transferred to the 8 bit A D Data Register for the corresponding channel every time the A D conversion in each channel is completed Each 8 bit A D Data Register retains the last conversion result until they receive the next conversion result transferred allowing the content to be read out at any time 11 29 Ver 0 10 1 1 CONVERTERS 11 3 Functional Description of Converters 11 3 Functional Description of A D Converters 11 3 1 How to Find Along Input Voltages The A D converters use a 10 bit successive approximation method and find the actual analog input voltage from the value digital quantity obtained through execution of A D conversion by performing the following calculation A D conversion result x VREFO input voltage V 1024 Analog input voltage V The A D converters are a 10 bit converter providing a resolution of 1 024 discrete voltage levels Because the reference voltage for the A D converter is the voltage applied to the VREFO pin make sure an exact and stable constant voltage power supply is connected to VREFO Also make sure the analog circuit power
160. counter 1 Also an interrupt can be generated when the counter underflows first time and next The valid count values are the counter set value 1 and reload 0 register set value 1 For details about count operation also see Section 10 3 10 Operation in TOP Delayed Single shot Output Mode With Correction Function 2 Precautions to be observed when using TIO delayed single shot output mode The following describes precautions to be observed when using TIO delayed single shot output mode f the counter stops due to underflow in the same clock period as the timer is enabled by external input the former has priority so that the counter stops f the counter stops due to underflow in the same clock period as count is enabled by writing to the enable bit the latter has priority so that count is enabled f the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit the latter has priority so that count is disabled When you read the counter immediately after reloading it pursuant to underflow the value you get is temporarily H FFFF But this counter value immediately changes to reload value 1 at the next clock edge 10 118 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer Enabled Underflow Underflow by writing to enable bit first time second time or by external input Y Y Y Count clock ecd rs
161. data frame status 1 Receives remote frame status Normal mode 0 Data frame 1 Remote frame 13 34 Ver 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers D Bit Name Function R 5 ML 0 Message lost not occurred Q A Message lost 1 Message lost occurred 6 TRSTAT For transmit slots Transmit receive status 0 Transmission idle 1 Transmit request accepted For receive slots 0 Reception idle 1 Storing received data 7 TRFIN For transmit slots A Transmit receive complete 0 Not transmitted yet 1 Finished transmitting For receive slots 0 Not received yet 1 Finished receiving W AA Only writing a 0 is effective when you write a 1 the previous value is retained 1 TR Transmit Request bit DO To use the message slot as a transmit slot set this bit to 1 To use the message slot as a data frame or remote frame receive slot set this bit to O 2 RR Receive Request bit D1 To use the message slot as a receive slot set this bit to 1 To use the message slot as a data frame or remote frame transmit slot set this bit to 0 If both TR Transmit Request and RR Receive Request bits are set to 1 device operation is indeterminate 13 35 Ver 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers 3 RM Remote bit D2 To handle remote frames in the message slot set this bit to 1 The message slot may be set to handle remote frames in following two ways Set
162. data to the RTDRXD pin synchronously with falling edges of RTDCLK ee oje BET AULA ALL FUL RESET System reset RTDRXD Don t Care ji RDR A1 X RDR A2 ye RTDTXD H 00000000 X 00000000 X 1 D A2 RTDACK p o C Note An Specified address D An Data at specified address Figure 14 3 13 Command Transfer to the RTD after System Reset 14 13 Ver 0 10 1 4 REAL TIME DEBUGGER RTD 14 4 Typical Connection with the Host 14 4 Typical Connection with the Host The host uses a serial synchronous interface to transfer data The clock for synchronous is generated by the host An example for connecting the RTD and host is shown below Host M32R E microprocessor ate m RTDCLK 7 SCLK RTDRXD RXD RTDTXD TXD RTDACK ame PORT Note In this example the RTDACK level is checked between transfer frames Figure 14 4 1 Connecting the RTD and Host 14 14 Ver 0 10 14 REAL TIME DEBUGGER RTD 14 4 Typical Connection with the Host The RTD communication for a fixed length of 32 bits per frame generally is performed in four operations sending 8 bits at a time because most serial interfaces transfer data in units of 8 bits The RTDACK signal is used to verify that communication is performed normally After transmitting a command the
163. desired L bank in the Pseudo Flash L Bank Register LBANKAD bits Then set the Pseudo Flash L Bank Register MODENL bit MODENLO bit to 1 The selected L bank area can be rewritten with the 8 Kbyte content of the internal RAM beginning with its start address Also select one or two of 4 Kbyte blocks or S banks of flash memory using the Pseudo Flash S Bank Registers FESBANKO and FESBANK1 by setting the eight address bits A12 A19 of the start address of each desired S bank in the Pseudo Flash S Bank Register SBANKAD bits Then set the Pseudo Flash S Bank Register MODENSO and MODENS bits to 1 The selected S bank areas can be replaced with 4 Kbytes of the internal RAM for up to two blocks beginning with the address H 0080 6000 In this way one 8 Kbyte block or L bank and two 4 Kbyte blocks or S banks for up to a total of three banks can be selected Note If the Pseudo Flash Emulation Enable bit is enabled while the same bank area is set multiple Pseudo Flash Bank Registers the internal RAM area 8 or 4 Kbytes to be allocated is selected by priority FELBANKO FESBANKO FESBANK 1 6 41 Ver 0 10 INTERNAL MEMORY 6 7 Virtual Flash Emulation Function Internal flash H 0000 0000 L bank 0 8Kbytes H 0000 2000 L bank 1 me Internal RAM 8Kbytes UNS 8Kbytes H 0080 4000 H 0000 4000 L bank 2 8Kbytes 4Kbytes i 4Kbytes uL em H 0007 C000 L bank 62
164. disabling them CAN bus error interrupt requests are enabled by setting this bit to 1 2 PIM Error Passive Interrupt Mask bit D6 This bit controls interrupt requests generated when the CAN module enters an error passive state by enabling or disabling them Error passive interrupt requests are enabled by setting this bit to 1 3 OIM Bus Off Interrupt Mask bit D7 This bit controls interrupt requests generated when the CAN module enters a bus off state by enabling or disabling them Bus off interrupt requests are enabled by setting this bit to 1 13 26 Ver 0 10 13 CAN MODULE 13 2 CAN Module Related Registers Data bus CANOSLIST H 0080 100C gt CANOSLIMK H 0080 1010 Slot 0 transmit receive completed 55 0 19 source inputs F F IRBO F F Slot 1 transmit receive completed J M CANO transmit receive amp error Level interrupts Da bi F F IRB1 bi F F Slot 2 transmit receive completed shoo be F F b2 IRB2 F F Slot 3 transmit receive completed 2 8583 bS F F IRB3 b3 F F Slot 4 transmit receive completed T 55 4 F F IRB4 04 F F Slot 5 transmit receive completed 55 5 05 F F pm IRB5 um F F Slot 6 transmit receive complete
165. during hold are shown below Table 15 1 1 Pin State during Hold Period Pin Name Pin State or Operation A12 A30 DBO DB15 CS0 CS1 RD BHW BLW BLE WR High impedance HACK Outputs a low Other pins e g ports and timer output Normal operation 15 3 Ver 0 10 1 5 EXTERNAL BUS INTERFACE 15 1 External Bus Interface Related Signals 10 Port P7 Operation Mode Register P7MOD The WAIT HREQ and HACK pins are shared with P71 P72 and P73 respectively The Port P7 Operation Mode Register is used to select the function of port P7 Configuration of this register is shown below E P7 Operation Mode Register Address H 0080 0747 D8 9 10 11 12 13 14 D15 P70MOD P71MOD P72MOD P73MOD P74MOD P75MOD P76MOD P77MOD When reset 00 gt D Bit Name Function R 8 P70MOD 0 P70 O Port P70 operation mode 1 BCLK WR 9 P71MOD 0 P71 Port P71 operation mode 1 WAIT 10 P72MOD 0 P72 O O Port P72 operation mode 1 HREQ 11 P73MOD 0 P73 Port P73 operation mode 1 HACK 12 P74MOD 0 P74 O Port P74 operation mode 1 RTDTXD 13 P75MOD 0 P75 O Port P75 operation mode 1 RTDRXD 14 P76MOD 0 P76 Port P76 operation mode 1 RTDACK 15 P77MOD 0 P77 Port P77 operation mode 1 RTDCLK 15 4 Ver 0 10 EXTERNAL BUS INTERFACE 15 1 External Bus Interface Related Signals 15 11 B
166. each time an underflow occurs To stop the counter disable count by writing to the enable bit in software The F F output waveform in continuous output mode is inverted at startup and upon underflow generating consecutive pulses until the timer stops counting Also an interrupt can be generated each time the counter underflows 10 48 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer 10 3 3 TOP Related Register Map The diagram below shows a TOP related register map Address DO 0 Address D7 D8 1 Address D15 H 0080 0240 TOPO Counter TOPOCT H 0080 0242 TOPO Reload Register TOPORL H 0080 0244 H 0080 0246 TOPO Correction Register 22 22 H 0080 0250 1 1 H 0080 0252 1 Reload Register TOP1RL H 0080 0254 H 0080 0256 1 Correction Register TOP1CC 22 22 H 0080 0260 TOP2 Counter TOP2CT H 0080 0262 TOP2 Reload Register TOP2RL H 0080 0264 H 0080 0266 TOP2 Correction Register TOP2CC f N N Blank addresses are reserved Note The registers enclosed in thick frames must always be accessed in halfwords Figure 10 3 2 TOP Related Register Map 1 3 10 49 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer Add 0 Address 1 Address TER DO D7 D8 D15 H 0080 0290 TOP5 Counter 5 H 0080 0292 TOP5 Reload Register T
167. eques Destination selector One 6 transfer completed Transfer count udf DMA channel8 Software start DMA Source request Destination MJT input event bus 0 Selector Transfer count udf DMA channel 9 Software start DMA Source Interrupt I Destination request sele One DMAB transfer Transfer count gt completed DMA start Determination block Internal bus arbitration Figure 9 1 1 Block Diagram of the DMAC 9 3 Ver 0 10 9 DMAC 9 2 DMAC Related Registers 9 2 DMAC Related Registers The diagram below shows a memory map of DMAC related registers 0 Address 1 Address Address DO D7 D8 D15 DMAO 4 Interrupt Request Status DMAO 4 Interrupt Mask 0080 0400 Register 0 041157 Register DMO4ITMK f DMA5 9 Interrupt Request Status DMA5 9 Interrupt Mask H 0080 0408 Register DM59ITST Register DM59ITMK DMAO Channel Control DMAO Transfer Count 608056310 Register DMOCNT Begister DMOTCT H 0080 0412 DMAO Source Address Register DMOSA H 0080 0414 DMAO Destination Address Register DMODA H 0080 0416 i DMAS Channel Control DMAS Transfer Count 0080 0418 Register DM5CNT Register DM5TCT H 0080 041A DMAS Source Address Register DM5SA H 0
168. erase the next block 5 Erase Unlock Block command The Erase All Unlock Block command erases all memory blocks that are not protected To erase all unlock blocks write the command data H A7A7 to any address of the internal flash memory Next write the command data H DODO to any address of the internal flash memory and all of unprotected memory blocks are erased 6 Read Status Register command The Read Status Register command reads out the content of Flash Status Register 2 FSTAT2 that indicates whether flash memory write or erase operation has terminated normally or not To read Flash Status Register 2 write the command data H 7070 to any address of the internal flash memory Next read any address of the internal flash memory and the content of Flash Status Register 2 FSTAT2 is read out 7 Clear Status Register command The Clear Status Register command clears the Flash Status Register 2 FSTAT2 D10 D11 and D12 bits to 0 Write the command data H 5050 to any address of the internal flash memory and Flash Status Register 2 is cleared to 0 If an error occurs when programming or erasing the flash memory and the Flash Status Register 2 FSTAT2 ERASE Auto Erase operating condition or WRERR2 Program operating condition 2 bit is set to 1 you cannot perform the next program or erase operation unless WRERH1 Program operating condition 1 or WRERR2 Program operating condition 2 is cleared to 0 6 30 Ver 0 10
169. external mode flash E W FPMOD enable mode P8DATA H 0080 0708 DO MODODT ee D1 MOD1DT 1 FP pin levels checked Transfer E W program to internal RAM in each mode NONO RUN pee Set Flash Control Register in SFR area FCNT1 H 0080 07E2 flash entry FENTRY bit to 0 aee Set Flash Control Register in SFR area FCNT1 H 0080 07E2 flash entry FENTRY bit to 1 ERN EMEN 1 us wait by hardware timer or software timer RENE NM Execute flash command and various read commands Note Switched to flash E W program Jump to flash memory or apply reset Switched to normal mode END Note For details about each command refer to Section 6 5 3 Programming Procedure to Internal Flash Memory Figure 6 5 6 Procedure for Entering Flash E W Enable Mode 6 24 Ver 0 10 6 INTERNAL MEMORY 6 5 Programming of the Internal Flash Memory 6 5 3 Programming Procedure to the Internal Flash Memory To write to the internal flash memory set the device s operation mode to enter flash E W enable mode first and then use the flash write program that has already been transferred from the flash memory into the internal RAM In flash E W enable mode no data can be read out from the internal flash memory as in normal mode so you cannot execute a program that exists in the internal flash memory Therefore the flash write pr
170. flash write program already stored in the internal flash memory to write to the flash memory For write to the flash memory use the internal peripheral circuits according to your programming system data bus serial and ports can be used The following shows an example for writing to the flash memory by using serial 0 in single chip mode Step 1 FP L or H MODi L MODO L Initial state where the write program already exists in the flash memory Ordinary program in the flash memory is being executed RAM CPU Boot ROM Fash write 5100 Write data program M32R E External device E z Step 2 MOUSE Set the FP pin high the MOD1 pin low and the MODO pin low to place the device single chip flash E W enable mode Flash write After determining the FP pin and MOD1 RAM program levels transfer the flash write program from the flash memory area into RAM Jump to the flash write program in RAM Boot ROM Flash SIOO Write data memory External device M32R E lt Step 3 gt FP H MOD1 L MODO L Using the flash write program in RAM set the n Flash Control Register 1 FCNT1 FENTRY bit to 1 Write data to the internal flash memory using RAM Flash write CPU the flash write program in RAM Program When you finished writing jump to the program
171. for remote frame transmission The data set in the message slot is transmitted as a remote frame When the CAN module finished transmitting the slot is automatically changed to a data frame receive slot However if a data frame is received before the CAN module finished sending a remote frame the data is stored in the message slot and the remote frame is not transmitted Set for remote frame reception Remote frames are received The processing to be performed after receiving a remote frame is selected by RL automatic response inhibit bit 4 RL Automatic Response Inhibit bit D3 This bit is effective when the message slot has been set as a remote frame receive slot It selects the processing to be performed after receiving a remote frame When this bit is set to 0 the message slot automatically changes to a transmit slot after receiving a remote frame and transmits the data set in it as a data frame When this bit is set to 1 the message slot stops operating after receiving a remote frame Note Always set this bit to 0 unless the message slot is set for remote frame reception 5 RA Remote Active bit D4 This bit functions differently for slots 0 13 and slots 14 and 15 Slots 0 13 This bit is set to 1 when the message slot is set for remote frame transmission reception Then it is cleared to 0 when remote frame transmission reception is completed Slots 14 15 The function of this bit differs depending on how the CA
172. function This function allows the data located in an 8 Kbyte block or one or two 4 Kbyte blocks of the internal RAM to be switched for use to or from the L or S bank of flash memory specified by the Pseudo Flash Bank Register Therefore applications that require changes of data during program operation can have data dynamically changed using 8 or 4 Kbytes of RAM area The RAM used for pseudo flash emulation can be accessed for read and write from both the internal RAM and the internal flash memory areas When this function is used in combination with the internal Real Time Debugger RTD the data tables created in the internal flash memory can be referenced or rewritten from outside thus facilitating data table tuning Before writing to the internal flash memory always be sure to terminate this pseudo flash emulation mode H 0080 4000 RAM bank L block 0 FELBANKO 8Kbytes H 0080 6000 RAM bank S block 0 FELBANKO 4Kbytes H 0080 7000 RAM bank S block 1 FESBANK1 4Kbytes H 0080 7FFF Figure 6 7 1 Internal RAM Bank Configuration of the 32171 6 40 Ver 0 10 6 INTERNAL MEMORY 6 7 Virtual Flash Emulation Function 6 7 1 Pseudo Flash Emulation Areas The following shows the areas effective for the pseudo flash emulation function Select one of 8 Kbyte blocks or L banks of flash memory using the Pseudo Flash L Bank Register FELBANKO by setting the seven address bits 12 18 of the start address of the
173. gt D8 9 10 11 12 13 14 D15 COMSLnDT7 lt When reset Indeterminate gt D Bit Name Function R 0 7 COMSLnDT7 Message slot n data 7 These registers the transmit frame receive frame memory space Note For receive slots if when storing a data frame the data length DLC value 7 an indeterminate value is written to this register 13 51 Ver 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers CANO Message Slot 0 Time Stamp COMSLOTSP Address H 0080 110 gt E CANO Message Slot 1 Time Stamp COMSL1TSP Address H 0080 111 gt E CANO Message Slot 2 Time Stamp COMSL2TSP Address H 0080 112 gt E CANO Message Slot 3 Time Stamp COMSL3TSP Address H 0080 113E E CANO Message Slot 4 Time Stamp COMSL4TSP Address H 0080 114 gt E CANO Message Slot 5 Time Stamp COMSL5TSP Address H 0080 115E gt E CANO Message Slot 6 Time Stamp 0 51 6 Address H 0080 116 gt CANO Message Slot 7 Time Stamp COMSL7TSP Address H 0080 117 gt CANO Message Slot 8 Time Stamp COMSL8TSP Address H 0080 118 gt E CANO Message Slot 9 Time Stamp COMSL9TSP Address H 0080 119 gt CANO Message Slot 10 Time Stamp COMSL10TSP Address H 0080 11AE E CANO Message Slot 11 Time Stamp COMSL11TSP Address H 0080 11BE CANO Message Slot 12 Time Stamp COMSL12TSP Address H 0080 11 gt CANO Message Slot 13 Time Stamp COMSL13TSP Address H 0080 11DE gt CANO Message Slot
174. in halfwords The TIO Counters are a 16 bit down counter After the timer is enabled by writing to the enable bit in software or by external input the counter starts counting synchronously with the count clock The counter cannot be written to during PWM output mode 10 101 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer 10 4 6 TIO Reload 0 Measure Register TIOORLO TIO9RLO TIOO Reload 0 Measure Register TIOORLO Address H 0080 0306 E TIO1 Reload 0 Measure Register TIO1RLO Address H 0080 0316 TIO2 Reload 0 Measure Register TIO2RLO Address H 0080 0326 E Reload 0 Measure Register TIOSRLO Address H 0080 0336 E TIO4 Reload 0 Measure Register TIOARLO Address H 0080 0346 TIO5 Reload 0 Measure Register TIOBRLO Address H 0080 0356 E TIO6 Reload 0 Measure Register TIO6RLO Address H 0080 0366 TIO7 Reload 0 Measure Register TIO7RLO Address H 0080 0376 E TIO8 Reload 0 Measure Register TIO8RLO Address H 0080 0386 TIO9 Reload 0 Measure Register TIO9RLO Address H 0080 0396 DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 TIOORLO TIO9RLO When reset Indeterminate gt D Bit Name Function R 0 15 TIOORLO TIO9RLO 16 bit reload register value A W A Write to this register is not accepted is disabled in PWM output mode Note This register must always be accessed in halfwords The TIO Reload 0 Measure Registers serve dua
175. interrupt input Therefore the status flags in the interrupt controller function only as a bit to show whether an interrupt enabled interrupt request occurred and cannot be written to 1 Interrupt request status bit This status bit shows whether an interrupt request occurred When an interrupt request is generated this bit is set in hardware but cannot be set in software The status bit is cleared by writing a 0 but not affected by writing a 1 in which case the bit holds the status intact Because the status bit is unaffected by interrupt mask bits it can also be used to check the operation of peripheral function In interrupt processing make sure that among grouped interrupt flags only the flag for the serviced interrupt is cleared Clearing flags for unserviced interrupts results in the pending interrupt requests also being cleared 10 29 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer 2 Interrupt mask bit This bit is used to disable unnecessary interrupts among grouped interrupt requests Set this bit to 0 to enable interrupts or 1 to disable interrupts Group interrupt Each timer or TIN input interrupt request Set Data 0 Interrupt status Data bus clear E F 4 Interrupt controller Interrupt enable Figure 10 2 4 Interrupt Status Register and Mask Register Example for clearing the interrupt
176. is ignored 2 ADOSSEL A DO conversion start trigger select bit D3 This bit selects whether to apply the A DO conversion start trigger in software or in hardware during single mode When software trigger is selected A D conversion is started by setting the ADOSSTT A DO conversion start bit to 1 When hardware trigger is selected set the ADOSTRG hardware trigger select bit to 1 and specify conversion to be started by MJT output 3 ADOSREQ A DO interrupt request DMA transfer request select bit D4 This bit selects whether to generate an A DO conversion interrupt request or a DMA transfer request at completion of single mode conversion or comparate 4 ADOSCMP conversion comparate complete bit D5 This is a read only bit and is 1 when reset This bit is 0 when the A DO converter in single mode A D conversion or comparate is operating and set to 1 when the operation is completed It also is set to 1 when A D conversion or comparate operation is forcibly terminated by setting the ADOSSTT A DO conversion stop bit to 1 during A D conversion or comparate operation 5 ADOSSTP A DO conversion stop bit D6 The A DO converter in single mode A D conversion or comparate can be stopped by setting this bit to 1 while the converter is operating Manipulation of this bit is ignored while the converter in single mode remains idle or is operating in scan mode Operation is stopped immediately after writing to this
177. is on and outputs a low when the power is down Figure 17 2 1 Typical Circuit for RAM Backup at Power Outage 17 2 Ver 0 10 1 7 RAM BACKUP MODE 17 2 Example of RAM Backup when Power is Down 17 2 1 Normal Operating State Figure 17 2 2 shows the normal operating state of the M32R E During normal operation input on the SBI or ADnINi i 0 15 pin used for RAM backup signal detection remains high De Input Regulator Output 5V system Regulator Output 3 3V system gi ts Power supply T Backup power supply y WDD for power outage Note 1 92 4 VDD VCCI 5 VREFn t detecti n n power outage detection _ pgp Note 3 Power outage __ detection signal SBI 2 Any Note 2 Backup battery M32R E 77 Note 1 Power outage is detected by the DC IN regulator input voltage Note 2 These pins are used to detect a RAM backup signal Note 3 This pin outputs a high when the power is on and outputs a low when the power is down Note 4 Backup power supply 2 0 to 3 3 V Figure 17 2 2 Normal Operating State 17 3 0 10 1 7 RAM BACKUP MODE 17 2 Example of RAM Backup when Power is Down 17 2 2 RAM Backup State Shown in Figure 17 2 3 is the power outage RAM backup state of the M32R E When the power supply goes down the power supply monitor IC starts feeding c
178. lt Address H 0080 0117 gt SIO1 Baud Rate Register S1 BAUR lt Address H 0080 0127 gt SIO2 Baud Rate Register S2BAUR Address H 0080 0137 D8 9 10 11 12 13 14 D15 BRG When reset Indeterminate gt D Bit Name Function R 8 15 Divides the baud rate count source selected Baud rate divide value by SIO Mode Register by n 1 according to the BRG set value n BRG baud rate divide value D8 D15 The SIO Baud Rate Register divides the baud rate count source selected by SIO Mode Register by BRG set value 1 according to the BRG set value In the initial state the BRG value is indeterminate so be sure to set the divide value before serial starts operating The value written to the BRG during transmit receive operation takes effect in the next cycle after the BRG counter finished counting When using the internal clock to output the SCLKO signal in CSIO mode the serial I O divides the internal BCLK using the clock divider Next it divides the resulting clock by BRG set value 1 according to the BRG set value and then by 2 which results in generating a transmit receive shift clock When using an external clock in CSIO mode the serial I O does not use the BRG Transmit receive operations are synchronized to the externally supplied clock 12 23 Ver 0 10 12 SERIAL 12 2 Serial Related Registers In UART mode the serial I O divides the internal BCLK
179. m 5 2 2 3 7 5 T JTDI Don t Care Don t Care LSB value MSB value j High impedance High impedance JTDO JTDO is output at fall of Finished storing setup data in the shift JTCK in Shift DR state register stage of the selected data register Note The shift operation of the data register for the shift register stage is right shifted therefore the output from JTDO is from the LSB side Input to JTDI starts from the value to be set in LSB side Figure 19 4 4 DR Path Sequence 19 11 Ver 0 10 1 9 JTAG 19 4 Basic Operation of JTAG 19 4 4 Examining and Setting Data Registers To inspect or set the data register follow the procedure described below 1 To access the test access port JTAG for the first time enter test reset to initialize the test circuit Test reset can be entered by one of the following two methods Pull JTRST pin input low Drive JTMS pin input high and enter JTCK for 5 cycles or more 2 Set JTMS low to go to Run Test Idle state To continue the idle state hold JTMS input low 3 Set JTMS high to exit Run Test Idle state and perform IR path sequence In IR path sequence specify the data register you want to inspect or set 4 Subsequently perform DR path sequence For the data register specified in IR path sequence enter setup data from the JTDI pin and read out reference data from the JTDO pin 5 If after DR pa
180. message slot Note 2 When receiving standard format frames an indeterminate value is written to the extended ID area Note 3 The data field is not accessed for write Note 4 The RA and bits are cleared to 0 after writing the remote frame received data 4 When receive conditions are not met The received frame is discarded and the CAN module waits for the next receive frame No data is written to the message slot 13 78 Ver 0 10 1 3 CAN MODULE 13 8 Receiving Remote Frames 5 Operation after receiving a remote frame The operation performed after receiving a remote frame differs depending on how automatic response is set When automatic response is disabled The slot which finished receiving goes to an inactive state and remains inactive neither transmit nor receive until it is newly set in software When automatic response is enabled After receiving a remote frame the slot automatically changes to a data frame transmit slot and performs the transmit operation described below In this case the transmitted data conforms to the ID and DLC of the received remote frame Selecting a transmit frame The CAN module checks slots which have transmit requests including remote frame transmit slots every intermission to determine the frame to transmit If there are multiple transmit slots frames are transmitted in order of slot numbers beginning with the smallest Transmitting a data frame After determining the t
181. of the PSW register are updated as shown below Unchanged SM lt 0 IE lt 0 lt 0 3 Saving When the trap instruction is executed the PC value of the TRAP instruction 4 is set in the BPC register For example if the TRAP instruction is located at address 4 the value 08 is set in the BPC register Similarly if the instruction is located at address 6 the value H OA is set in the BPC register In this case the value of the BPC register bit 30 indicates whether the trap instruction resides a word boundary BPC 30 0 or not on a word boundary BPC 30 1 However in either case of the above the address to which the RTE instruction returns after completion of processing by the EIT handler is address 8 This is because the two low order bits are cleared to 00 when returning to the PC Normally when the program has been written in assembler the halfword that immediately follows the TRAP instruction placed at a word boundary has the NOP instruction automatically inserted by the assembler 4 20 Ver 0 10 4 10 Trap Processing Address Address H 00 H 00 H 04 TRAM occurred Return H 04 occurred ode gt H 08 address H 08 H OC H OC Figure 4 10 1 Example of a Return Address for Trap TRAP 4 Branching to the EIT vector entry Control branches to the addresses H 0000 0040 through
182. only status bits which indicate the operating condition of the flash memory 1 FBUSY Flash Busy bit D8 The FBUSY bit is used to determine whether the operation is terminated when programming or erasing the flash memory When FBUSY 0 it means the program or erase operation is being executed when FBUSY 1 the operation is terminated 2 ERASE Auto Erase operating condition bit D10 The ERASE bit is used to determine whether execution of the flash memory erase operation has resulted in an error When ERASE 0 it means the erase operation terminated normally when ERASE 1 the operation terminated in an error 3 WRERR1 Program operating condition bit D11 The WRERR1 bit is used to determine after completion of execution whether the flash memory program operation resulted in an error When WRERR1 0 it means the program operation terminated normally when WRERR 1 the operation terminated an error The condition under which WRERRT1 is set to 1 is when any bit other than those that must be 0 is found to be a 0 by comparison between the write data and the data in the flash memory 6 6 Ver 0 10 INTERNAL MEMORY 6 4 Registers Associated with the Internal Flash Memory 4 WRERR2 Program operating condition bit D12 The WRERR2 bit is used to determine after execution whether the flash memory program operation resulted in an error When WRERR2 0 it means the program operation terminated normally when
183. or DMA transfer request q Conversion E Completed starts n20 15 Note ADOCMP Comparate result A DO comparate ADOCMP 0 ANn gt ADOSAR data register Note Comparate start Started by writing a comparison value to the successive approximation register ADOSAR Figure 11 1 3 Operation in Single Mode Comparate 11 6 Ver 0 10 1 1 CONVERTERS 11 1 Outline of Converters 2 Scan mode In scan mode analog input voltages in multiple selected channels 4 8 or 16 channels are sequentially A D converted There are two types of scan modes Single shot scan mode in which A D conversion is completed by performing one cycle of scan operation and Continuous scan mode in which scan operation is continued until halted by setting the Scan Mode Register A D conversion stop bit to 1 These types of scan modes are selected using Scan Mode Register 0 The channels to be scanned are selected using Scan Mode Register 1 The number of channels and the sequence to be scanned can be selected from three combinations available 4 8 or 16 channels Channels ADOINO to ADOINS are used for 4 channel scan Similarly channels ADOINO to ADOIN7 and channels ADOINO to ADOIN15 are used for 8 channel scan and 16 channel scan respectively An A D conversion interrupt request or a DMA transfer request can be generated at completion of one cycle of scan operation 4 channel scan During continuous scan mode Conver
184. place the device in boot mode flash E W enable mode Deassert reset and start up using the boot program Transfer the flash write program from boot ROM to RAM Jump to the flash write program in RAM Write data External device Step 3 Using the flash write program in RAM set the Flash Control Register 1 FCNT1 FENTRY bit to 1 Write data to the internal flash memory using the flash write program When you finished writing reset MODO low and jump to the flash memory or apply reset to enter normal mode Write data External device Figure 6 5 2 Procedure for Writing to Internal Flash Memory when the write program does not exist in the flash memory 6 18 Ver 0 10 INTERNAL MEMORY 6 5 Programming of the Internal Flash Memory Reset deasserted Boot program starts Reset deasserted Mode selected POWER ON Mode selected Y Y RESET 7 A N MODO UNS MODI NN i Settings by boot i program i bg 1 Writes to flash memory i bootprogram Figure 6 5 3 Internal Flash Memory Write Timings when the write program does not exist in the flash memory 6 19 Ver 0 10 INTERNAL MEMORY 6 5 Programming of the Internal Flash Memory 2 When the write program already exists in the internal flash memory Use the
185. proceeds This mode can be selected from two choices address fixed or address incremental 9 16 Ver 0 10 9 2 2 Software Request Generation Registers DMAO Software Request Generation Register DMOSRI E DMA1 Software Request Generation Register DM1SRI E DMA2 Software Request Generation Register DM2SRI E DMA3 Software Request Generation Register DM3SRI E DMA4 Software Request Generation Register DM4SRI E DMAS Software Request Generation Register DM5SRI E DMAG Software Request Generation Register DM6SRI E DMA7 Software Request Generation Register DM7SRI E DMAS Software Request Generation Register DM8SRI E DMAO9 Software Request Generation Register DM9SRI DMAC 9 2 DMAC Related Registers Address Address Address Address Address Address Address Address Address Address H 0080 0460 gt H 0080 0462 H 0080 0464 gt H 0080 0466 gt H 0080 0468 H 0080 0470 H 0080 0472 H 0080 0474 H 0080 0476 H 0080 0478 14 D15 D Bit Name Function When reset Indeterminate gt 0 15 DMOSRI DM9SRI DMA transfer request is generated Generates DMA software request by writing any data Note This register can be accessed in either bytes or halfwords R The Software Request Generation Register is used to generate transfer requests software A DMA transfer request can be generated by writing any data to this register when
186. reserved Note The registers enclosed in thick frames can only be accessed in halfwords Figure 9 2 2 DMAC Related Register Map 2 2 9 5 Ver 0 10 9 DMAC 9 2 DMAC Related Registers 9 2 1 DMA Channel Control Register E DMAO Channel Control Register DMOCNT Address H 0080 0410 DO 1 3 4 5 6 D7 MDSELO TREQFO REQSTO TENLO TSZSLO SADSLO DADSLO When reset 00 gt D Bit Name Function R 0 MDSELO 0 Normal mode O O Selects DMAO transfer mode 1 Ring buffer mode 1 TREQFO 0 Not requested DMAO transfer request flag 1 Requested 2 3 REQSLO 00 Software start or one DMA2 transfer completed O Selects cause of DMAO request 01 A DO conversion completed 10 MJT TIO8 11 MJT input event bus 2 4 TENLO 0 Disables transfer Enables transfer 1 Enables transfer 5 TSZSLO 0 16 bits Selects DMAO transfer size 1 8 bits 6 SADSLO 0 Fixed Selects DMAO source address direction 1 Incremental 7 DADSLO 0 Fixed Selects DMAO destination 1 Incremental address direction W A Only writing a 0 is effective when you write 1 the previous value is retained 9 6 Ver 0 10 9 DMAC 9 2 DMAC Related Registers E DMA1 Channel Control Register DM1CNT Address H 0080 0420 DO 1 3 4 5 6 D7 MDSEL1 TREQF1 REQSI TENL
187. serial programmer take measures not to affect the system when connecting a serial programmer Ifthe flash memory needs to be protected set an appropriate ID in the flash memory protect ID verification area H 0000 0084 through H 0000 0093 f the flash memory does not require protection fill the entire flash memory protect ID verification area H 0000 0084 through H 0000 0093 with H FF 6 51 Ver 0 10 INTERNAL MEMORY 6 9 Precautions to Be Taken When Rewriting Flash Memory This is a blank page 6 52 Ver 0 10 CHAPTER 7 RESET 7 1 Outline of Reset 7 2 Reset Operation 7 3 Internal State Immediately after Reset Release 7 4 Things To Be Considered after Reset Release 7 RESET 7 1 Outline of Reset 7 1 Outline of Reset The device is reset by applying a low level signal to the RESET input pin The device is gotten out of a reset state by releasing the RESET input back high upon which the reset vector entry address is set in the Program Counter PC and the program starts executing from the reset vector entry 7 2 Reset Operation 7 2 1 Reset at Power on When powering on the device hold the RESET input low until its internal multiply by 4 clock generator becomes oscillating stably 7 2 2 Reset during Operation To reset the device during operation hold the RESET input low for more than four clock periods of XIN signal 7 2 3 Reset Vector Relocation during Flash Rewrite When pla
188. shot Output Mode when Correction Applied 10 76 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer 3 Precautions to be observed when using TOP delayed single shot output mode The following describes precautions to be observed when using TOP delayed single shot output mode f the counter stops due to underflow in the same clock period as the timer is enabled by external input the former has priority so that the counter stops f the counter stops due to underflow in the same clock period as count is enabled by writing to the enable bit the latter has priority so that count is enabled If the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit the latter has priority so that count is disabled Even when the counter overflows due to correction of counts no interrupt is generated for the occurrence of overflow When the counter underflows in the subsequent down count after overflow a false underflow interrupt is generated due to overcounting When you read the counter immediately after reloading it pursuant to underflow the value you get is temporarily H FFFF But this counter value immediately changes to reload value 1 at the next clock edge Reload due to underflow Y Count clock ul f Enable bit Down count starting Reload from reloaded register gt cycle value Counter
189. shown below Completion of one transfer in channel 0 starts DMA transfer in channel 1 Completion of one transfer in channel 1 starts DMA transfer in channel 2 Completion of one transfer in channel 2 starts DMA transfer in channel 0 Completion of one transfer in channel 3 starts DMA transfer in channel 4 Completion of one transfer in channel 5 starts DMA transfer in channel 6 Completion of one transfer in channel 6 starts DMA transfer in channel 7 Completion of one transfer in channel 7 starts DMA transfer in channel 5 Completion of one transfer in channel 8 starts DMA transfer in channel 9 Completion of all DMA transfers in channel 0 transfer count register underflow starts DMA transfer in channel 5 9 2 Ver 0 10 9 1 Outline of the DMAC DMA channel 0 a es yox Source address 4 transfer completed cl register conversion completed Destination address request register MJT TIO8 udf gt selector Transfer count MJT input event bus 2 gt register udf DMA channel Software start DMA Source MJT output event bus 0 request L Destination selector One transfer completed gt Transfer count ud DMA channel 2 Software start Source DMA MJT output event bus 1 gt request Destination MJT
190. signals 50 51 RD BLE WAIT and WR Bus free state internal bus access BCLK 12 A30 Y 7X CS0 CS1 1 RD WR BHW BLW DBO DB15 _ WAIT Note 1 Hi Z denotes a high impedance state Note 2 BCLK is not output Figure 16 3 8 Internal Bus Access during Bus Free State 16 13 Ver 0 10 16 WAIT CONTROLLER 16 3 Typical Operation of the Wait Controller Read Read 2cycles 1 internal Wait cycle x BCLK A12 5 oso osi LLULLA WR pn BLE 7 x KL 2 DBO DB15 WAT H Write i Write 2 cycles gt 1 internal cycle gt i BCLK A12 A30 771 CS0 CS1 2 D 2 RD WR E BLE AL 2 DBO DB15 _ WAT Note 1 Circles above indicate points at which signals are sampled Note 2 BCLK is not output Figure 16 3 9 Read Write Timing for Access with 1 Internal Wait Cycle 16 14 Ver 0 10 WAIT CONTROLLER 16 3 Typical Operation of the Wait Controller Read 3 cycles Read
191. signals from peripheral circuits AD and SIO Figure 10 1 1 Block Diagram of MJT 1 3 10 4 Ver 0 10 MULTIJUNCTION TIMERS 10 1 Outline of Multijunction Timers 10 Clock bus Input event bus Output event bus 3210 3210 12 o IRQ7 O TCLK3S HE 5 ck TMS 0 cap3 cap2 0 Il as S Ze S ji S IRQ7 Note1 Mr 5 ck 5 1 IRQ10 cap3 cap2 0 TIN16 O 1TIN16S S IRO10 TIN17 1 175 5 IRO10 85 5 DROS IRa10 TIN19 0 1 195 x S DRO6 1 2 internal peripheral S clock DRQI2 ck TMLO ati cap3 2 TIN20 O TIN20S H 5 TIN21 OH 215 5 TIN22 225 5 TIN23 1 235 5 NE To A DO converter 1 2 internal peripheral t S TML 1 clock cap3 cap2 0 M S 5 5 t S a
192. start counting down In the example diagram here H 4000 is written to the correction register when the counter has counted down to H 5000 As a result of this correction the count has been increased to H 9000 so that the counter stops after counting a total of H 8000 1 H 4000 1 counts 10 69 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer Enabled by writing to enable bit or by external input Count clock UL VARRONE UUL a aka Ja Disabled by underflow Enable bit Write to correction register Y AHBBBES ater 7 2 H 5000 H 4000 H 8000 Reload register H 8000 Correction register H 4000 F F output Data inverted Data inverted by enable by underflow TOP interrupt 2 due to underflow Note This diagram does not show detail timing information Figure 10 3 12 Example of Counting in TOP Single shot Output Mode When Count is Corrected 10 70 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer 3 Precautions to be observed when using TOP single shot output mode The following describes precautions to be observed when using TOP single shot output mode f the counter stops due to underflow in the same clock period as the timer is enabled by external input the former has priority so that the counter stops
193. test 2 Bypass Register JTAGBPR The Bypass Register is a 1 bit register used to bypass boundary scan passes when the 32171 is not the target of boundary scan test Connected between the JTDI and JTDO pins this register is selected when issuing BYPASS instruction This register when in Capture DR state has b 0 fixed value loaded into it 3 ID Code Register JTAGIDR The ID Code Register is a 32 bit register used to identify the device and manufacturer It holds the following information Version information 4 bits b 0000 Part number 16 bits b 0011 0010 0010 0000 Manufacturer ID 11 bits b 000 0001 1100 This register is connected between the JTDI and JTDO pins and is selected when issuing IDCODE instruction When in Capture DR state this register has the said IDCODE data loaded into it which is output from the JTDO pin in Shift DR state This register is a read only register so that the data written from the JTDI pin during DR pass sequence is ignored Therefore make sure JTDI input low during Shift DR state 0 34 19 20 30 31 Version Part number Manufacturer ID 1 4 bits 16 bits 11 bits Note For details about Capture DR and Shift DR states refer to Section 19 4 19 5 Ver 0 10 1 9 JTAG 19 4 Basic Operation of JTAG 19 4 Basic Operation of JTAG 19 4 1 Outline of JTAG Operation The instruction and data registers basically are accessed in the following th
194. the A DO converter during single mode Setting this bit to 0 selects conversion mode and setting this bit to 1 selects comparator mode 2 ADOSSPD A DO conversion rate selection bit D9 This bit selects an A D conversion rate for the A DO converter during single mode Setting this bit to 0 selects a normal speed and setting this bit to 1 selects a 2 speed two times normal speed 3 ANOSEL analog input pin selection bits 012 015 These bits select analog input pins for the A DO converter during single mode It is the channels selected by these bits that are operated on for A D conversion or comparate operation When you read these bits they show the values written to them 11 20 Ver 0 10 1 1 5 11 2 Converter Related Registers 11 2 3 A D Scan Mode Register 0 A DO Scan Mode Register 0 ADOSCMO Address H 0080 0084 gt DO 1 2 3 4 5 6 D7 ADocMSL ADOCTRG ADOCSEL ADOCREQADOCCMP ADOCSTP ADOCSTT When reset H 04 gt D Bit Name Function R 0 No functions assigned 0 1 ADOCMSL 0 Single shot mode O O A DO scan mode selection 1 Continuous mode 2 ADOCTRG 0 Use inhibited A DO hardware trigger selection 1 Output event bus 3 3 ADOCSEL 0 Software trigger A DO conversion start trigger selection 1 Hardware trigger 4 ADOCREQ 0 Requests A DO interrupt O O Interrupt request DMA request selection 1 Reques
195. the transmit frame receive frame memory space Note indeterminate value is written to this register 13 49 For receive slots if when storing a data frame the data length DLC value 5 an Ver 0 10 13 CANO Message Slot 0 Data 6 COMSLODT6 CANO Message Slot 1 Data 6 COMSL1DT6 CANO Message Slot 2 Data 6 COMSL2DT6 CANO Message Slot 3 Data 6 COMSL3DT6 CANO Message Slot 4 Data 6 COMSLADT6 CANO Message Slot 5 Data 6 COMSL5DT6 CANO Message Slot 6 Data 6 COMSL6DT6 CANO Message Slot 7 Data 6 COMSL7DT6 CANO Message Slot 8 Data 6 COMSL8DT6 CANO Message Slot 9 Data 6 COMSL9DT6 CANO Message Slot 10 Data 6 COMSL10DT6 CANO Message Slot 11 Data 6 COMSL11DT6 CANO Message Slot 12 Data 6 COMSL12DT6 CANO Message Slot 13 Data 6 COMSL13DT6 CANO Message Slot 14 Data 6 COMSL14DT6 CANO Message Slot 15 Data 6 COMSL15DT6 DO 1 2 3 4 CAN MODULE 13 2 CAN Module Related Registers Address H 0080 110C gt Address H 0080 111C gt Address H 0080 112C Address H 0080 113C gt Address H 0080 114C gt Address H 0080 115 gt Address H 0080 116C gt Address H 0080 117C gt Address H 0080 118C gt Address H 0080 119 gt Address H 0080 11 gt Address H 0080 11 gt Address H 0080 11CC gt Address H 0080 11DC gt lt Address H 0080 11 gt Address H 0080 11FC gt 5 6 D7 COMSLnDT6 D Bit Name 0 7 COMSLnDT6
196. tpxz BLWH DZ Data Output Disable Time after Write tpxz BHWH DZ Byte write mode td A WRL Address Delay Time before Write Byte enable mode D Q 2 gah Q e 5 i ES a e 2 i EA Chip Select Delay Time before Write Byte enable mode BS Address d after Write ces Chip Select 27 after Write td BLE WRL Byte enable delay time before write td BHE WRL Byte enable mode e Sim e 2 A e iv e 2 un sei olr 2 e e 2 i L tv WRH BLE Byte enable delay time after write tv WRH BHE Byte enable mode td WRL D Data Output Delay Time after Write Byte enable mode tv WRH D Valid Data Output Time after Write Byte enable mode t Data output disable time after write pxzWRETDZ Byte enable mode Read high level pulse width 5 Bus arbitration E m E o r 2 2 Symbol Parameter Condition Rated Value Rated Value Value HACKL Delay Time after BCLK HACK Delay Time after BCLK Time after BCLK meee mms 21 17 Ver 0 10 21 ELECTRICAL CHARACTERISTICS 21 5 AC Characteristics 21 5 3 AC Characteristics BCLK 0 8VCCE 0 8VCCE Port input O2VCCE 0 2VCCE ta E P Port output 13 Figure 21 5 1 Input Output Port Timing a CSIO mode with internal clock selected CLKour td CLk D th CLK
197. two at a time When as transfer proceeds the six low order bits reach B 111110 they are recycled to B 000000 by the next increment operation thus returning to the start address again When the source address has been set to be incremented it is the source address that recycles to the start address when the destination address has been set to be incremented it is the destination address that recycles to the start address If both source and destination addresses have been set to be incremented both addresses recycle to the start address However the start address on either side must have their five low order bits initially being B 00000 During ring buffer mode the transfer count register is ignored Also once DMA operation starts the counter operates in free run mode and the transfer continues until the transfer enable bit is cleared to to disable transfer When transfer unit 8 bits When transfer unit 16 bits Transfer count Transfer address Transfer count Transfer address 1 H 0080 1000 1 H 0080 1000 2 H 0080 1001 2 H 0080 1002 3 H 0080 1002 3 H 0080 1004 31 H 0080 101E 31 0080 103C 32 H 0080 101F 32 H 0080 103E 1 H 0080 1000 1 H 0080 1000 2 H 0080 1001 2 H 0080 1002 Figure 9 3 4 Example of Address Increment Operation in 32 Channel Ring Buffer Mode 9 36 Ver 0 10 9 9 3 Functional Description of the DMAC 9 3 10 End of DMA and Interrupt In normal mode DMA t
198. value 4 H 0001 X H 0000 x H FFFF X H AAA9 X H AAAS H AAAA 1 2 Reload register H AAAA During reload cycle you always see H FFFF and not the reload register value in this case H AAAA Figure 10 3 19 Counter Value Immediately after Underflow 10 77 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer 10 3 11 Operation in TOP Continuous Output Mode Without Correction Function 1 Outline of TOP continuous output mode In continuous output mode the timer counts down clock pulses starting from the set value of the counter and when the counter underflows reloads it with the reload register value Thereafter this operation is repeated each time the counter underflows thus generating consecutive pulses whose waveform is inverted in width of reload register set value 1 When after setting the counter and reload register the timer is enabled by writing to the enable bit in software or by external input it starts counting down from the counter s set value synchronously with the count clock and when the minimum count is reached generates an underflow This underflow causes the counter to be reloaded with the content of the reload register and start counting over again Thereafter this operation is repeated each time an underflow occurs To stop the counter disable count by writing to the enable bit in software The F F output waveform in continuous output mode
199. value invalid 0 Read always as 0 1 Read always as 1 At write O Write enabled Write enable conditionally include some conditions at write Write disabled Written value invalid Example of representation Registers represented with thick rectangles are accessible only with halfwords or words not accessible with bytes in the shaded portion 0 DO 1 2 3 4 Bbit Cbit 2 at reset H 04 D Bit name Function R 0 Not assigned 0 1 Abit 1 2 Bbit 0 O nsi d 3 Cbit 0 Contents CHAPTER 1 OVERVIEW 1 1 Outline of the 32171 nine dre etc aan resta elect 1 2 1 1 1 M32R Family CPU 1 2 1 1 2 Built in Multiply Accumulate Operation Function 1 3 1 1 3 Built in Flash Memory and RAM seem 1 3 1 1 4 Built in Clock Frequency Multiplier 2 2 44400420 0 1 4 1 1 5 Built in Powerful Peripheral Functions 0 1 4 1 1 6 Built in Full CAN Function 2 1 6 1 1 7 Built in Debug Function 1 6 1 2 Block Diagram eani 1 7 1 3 Pin F nctlon eric ite ternis 1 10 1 4 PIn EayOUl m 1 16
200. 0 0 1 0 Processor mode Start address of External area external area H 0000 0080 H 0000 0000 0 0 1 Extended external mode Start address of Flash area 1 0 1 0 flash memory H 0000 0080 H 0000 0000 1 0 0 1 Single chip mode Start address of Beginning of flash E W enable flash memory internal RAM H 0000 0000 H 0080 4000 1 1 0 0 Boot mode Start address of Flash area boot program area H 0000 0080 H 8000 0000 1 1 0 1 Boot mode Start address of Beginning of flash E W enable boot program area internal RAM H 8000 0000 H 0080 4000 1 0 1 1 Extended external mode Start address of Beginning of flash E W enable flash memory internal RAM H 0000 0000 H 0080 4000 1 1 reserved Note Indicates the FENTRY bit status of Flash Control Register 1 1 The bar denotes Don t Care 1 Flash E W enable mode Flash E W enable mode is a mode in which the internal flash memory can be programmed or erased In flash E W enable mode no programs can be executed in the internal flash memory Therefore before entering flash E W enable mode you need to transfer the necessary program into the internal RAM and run the program in RAM 6 22 Ver 0 10 INTERNAL MEMORY 6 5 Programming of the Internal Flash Memory 2 Entering flash E W enable mode Flash E W enable mode can be entered only when the device is operating in single chip mode or extended external mode Namely you can enter flash E W enable mode on
201. 0 00A0 10 bit A DO Data Register 8 ADODT8 H 0080 00A2 10 bit A DO Data Register 9 ADODT9 H 0080 00A4 10 bit A DO Data Register 10 ADODT10 H 0080 00A6 10 bit A DO Data Register 11 ADODT11 H 0080 00A8 10 bit A DO Data Register 12 ADODT12 H 0080 00AA 10 bit A DO Data Register 13 ADODT13 H 0080 00AC 10 bit A DO Data Register 14 ADODT14 H 0080 O0AE 10 bit A DO Data Register 15 ADODT15 H 0080 00DO 8 bit A DO Data Register 0 ADOBDTO Blank addresses are reserved areas Figure 3 4 4 Register Mapping of the SFR Area 2 3 11 Ver 0 10 ADDRESS SPACE 3 4 Internal ROM SFR Area Address 0 Address 1 Address H 0080 0216 H 0080 0218 TIN Input Processing Control Register TINCR3 H 0080 021A TIN Input Processing Control Register 4 TINCR4 H 0080 021C H 0080 021E H 0080 0220 E F Source Select Register 0 FFSO H 0080 0222 F F Source Select Register 1 FFS1 H 0080 0224 F F Protect Register 0 FFPO H 0080 0226 F F Data Register 0 FFDO H 0080 0228 F F Protect Register 1 FFP1 H 0080 022A F F Data Register 1 FFD1 H 0080 0230 TOP Interrupt Control Register 0 TOPIRO TOP Interrupt Control Register 1 TOPIR1 H 0080 0232 TOP Interrupt Control Register 2 TOPIR2 TOP Interrupt Control Register 3 TOPIR3 H 0080 0234 TIO Interrupt Control Register 0 TIOIRO TIO Interrupt Control Register 1 TIOIR1 H 0080 0236 T
202. 0 Measure 1 Register TMLOMR1H Address H 0080 03 8 gt B TMLO Measure 1 Register TMLOMR1L Address H 0080 gt 0 Measure 0 Register TMLOMROH Address H 0080 03FC gt E TMLO Measure 0 Register TMLOMROL Address H 0080 03FE gt DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 TMLOMR3H TMLOMROH 16 high order bits DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 TMLOMRSL TMLOMROL 16 low order bits When reset Indeterminate gt D Bit Name Function R 0 15 TMLOMR3H 0H 32 bit counter value 16 high order bits TMLOMRS3L OL 32 bit counter value 16 low order bits Note 1 These registers are a read only register Note 2 These registers must always be accessed in words 32 bits beginning with a word boundary The TMLO Measure Registers are used to latch counter contents upon event input The TMLO Measure Registers are configured with 32 bits the TMLOMR3H 0H accommodating the 16 high order bits and the TMLOMR3L 0L accommodating the 16 low order bits The TMLO Measure Registers are a read only register These registers must always be accessed in words 32 bits beginning with a word boundary 10 138 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 6 TML Input related 32 bit Timer E TML1 Measure 3 Register TML1MR3H Address H 0080 OFFO gt TML1 Measure Register TML1MR3L Address H 0080 OFF2 gt E TML1 Measure 2 Register TML1MR2H Address H 0080 OFF4 gt TML1 Measure 2 Register TML1MR2L Addr
203. 0 OFFE TS 000 H 0080 11FE H 0080 3FFE 0 ADDRESS SPACE 3 4 Internal ROM SFR Area 7 8 0 address 1 address Flash control 15 MJT TML1 Note The Real time Debugger RTD is designed to be an independent module operated from an external source and is transparent to the CPU Figure 3 4 2 Outline Address Mapping of the SFR Area 3 9 Multijunction timer MJT Ver 0 10 Address H 0080 0000 H 0080 0002 H 0080 0004 H 0080 0006 H 0080 0060 CANO Transmit Receive amp Error Interrupt Control Register H 0080 0062 H 0080 0064 H 0080 0066 H 0080 0068 H 0080 006A H 0080 006C H 0080 006E H 0080 0070 H 0080 0072 H 0080 0074 0 Address DO ADDRESS SPACE 3 4 Internal ROM SFR Area 1 Address Interrupt Vector Register IVECT Interrupt Mask Register IMASK SBI Control Register SBICR RTD Interrupt Control Register IRTDCR SIO2 3 Transmit Receive Interrupt Control Register ISO23CR DMAS 9 Interrupt Control Register IDMA59CR A DO Conversion Interrupt Control Register ADOCCR SIOO Transmit Interrupt Control Register ISIOOTXCR SIOO Receive Interrupt Control Register ISIOORXCR SIO1 Receive Interrupt Control Register ISIO1 RXCR SIO1 Transmit Interrupt Control Register ISIO1TXCR DMAO 4 Interrupt Control Register IDMA04CR MJT Output Interrupt Control Register 0 IMJTOCRO MJT
204. 0 register value is loaded into the counter causing it to continue counting down and the counter stops when it underflows next time The F F output waveform in delayed single shot output mode is inverted when the counter underflows first time and next generating a single shot pulse waveform in width of reload 0 register set value 1 only once with the output delayed by an amount of time equal to first set value of counter 1 Also an interrupt can be generated when the counter underflows first time and next 10 85 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer 6 Continuous output mode without correction function In continuous output mode the timer counts down clock pulses starting from the set value of the counter and when the counter underflows reloads it with the reload 0 register value Thereafter this operation is repeated each time the counter underflows thus generating consecutive pulses in width of reload 0 register set value 1 When after setting the counter and reload 0 register the timer is enabled by writing to the enable bit in software or by external input it starts counting down from the counter s set value synchronously with the count clock and when the minimum count is reached generates an underflow This underflow causes the counter to be reloaded with the content of reload 0 register and start counting over again Thereafter this operation is repeated each time
205. 00 00C0 H 0000 00C3 H 0000 00C4 H 0000 00C7 H 0000 00C8 H 0000 00CB H 0000 00CC H 0000 00 H 0000 0000 0000 0003 H 0000 00D4 H 0000 0007 H 0000 00D8 H 0000 00DB H 0000 00DC H 0000 00DF H 0000 00E8 H 0000 00 H 0000 00 0000 00 H 0000 00 0 0000 00F3 H 0000 010C H 0000 010F 5 17 Level recognized Level recognized Level recognized Level recognized Level recognized Level recognized Edge recognized Level recognized Level recognized Level recognized Level recognized Level recognized Level recognized Edge recognized Edge recognized Edge recognized Edge recognized Edge recognized Level recognized Level recognized Edge recognized Level recognized Ver 0 10 INTERRUPT CONTROLLER ICU 5 5 Description of Interrupt Operation Table 5 5 2 ILEVEL Settings and Accepted IMASK Values ILEVEL values set IMASK values at which interrupts are accepted 0 ILEVEL 000 Accepted when IMASK is 1 7 1 ILEVEL 001 Accepted when IMASK is 2 7 2 ILEVEL 010 Accepted when IMASK is 3 7 3 ILEVEL 011 Accepted when IMASK is 4 7 4 ILEVEL 100 Accepted when IMASK is 5 7 5 ILEVEL 101 Accepted when IMASK is 6 7 6 ILEVEL 110 Accepted when IMASK is 7 7 ILEVEL 111 Not accepted interrupts disabled 5 18 Ver 0 10 INTERRUPT CONTROLLER ICU 5 5 Description of Interrupt Operation 5 5 2 Processing of Internal Peripheral I O Interrupts by Handlers 1 Branching to the interrupt hand
206. 080 041 DMAS Destination Address Register DM5DA H 0080 041 DMA1 Channel Control DMA1 Transfer Count H 0080 0420 Register DM1CNT Register DM1TCT H 0080 0422 DMA1 Source Address Register DM1SA H 0080 0424 Destination Address Register DM1DA H 0080 0426 DMA6 Channel Control DMA6 Transfer Count 0080 0428 Register DM6CNT Register DM6TCT H 0080 042A DMA6 Source Address Register DM6SA H 0080 042C DMA6 Destination Address Register DM6DA H 0080 042 i DMA2 Channel Control DMA2 Transfer Count BOOED bese Register DM2CNT Register DM2TCT H 0080 0432 DMA2 Source Address Register DM2SA H 0080 0434 DMA2 Destination Address Register DM2DA H 0080 0436 T DMA7 Channel Control DMA7 Transfer Count H 0080 0438 Register DM7CNT Register DM7TCT H 0080 043A DMA7 Source Address Register DM7SA H 0080 043 DMA7 Destination Address Register DM7DA H 0080 043E Blank addresses are reserved Note The registers enclosed in thick frames can only be accessed in halfwords Figure 9 2 1 DMAC Related Register Map 1 2 9 4 Ver 0 10 DMAC 9 2 DMAC Related Registers Address H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080
207. 0CC TOPO Correction Register TOPOCC Address H 0080 0246 gt TOP1 Correction Register TOP1CC Address H 0080 0256 gt TOP2 Correction Register TOP2CC Address H 0080 0266 gt E TOP3 Correction Register TOP3CC Address H 0080 0276 TOP4 Correction Register TOP4CC Address H 0080 0286 gt E TOP5 Correction Register TOP5CC Address H 0080 0296 gt E TOP6 Correction Register TOP6CC Address H 0080 02 6 gt Correction Register TOP7CC Address H 0080 02 6 gt E TOP8 Correction Register TOP8CC Address H 0080 02 6 gt 9 Correction Register TOP9CC Address H 0080 02D6 gt TOP10 Correction Register TOP10CC lt Address H 0080 02E6 gt DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 TOPOCC TOP10CC Acceptable set values 32767 32768 When reset Indeterminate gt D Bit Name Function R 0 15 10 16 bit correction register value Note This register must always accessed halfwords The TOP correction registers are used to correct the TOP counter value by adding or subtracting it in the middle of operation To increase or reduce the counter value write a value to this correction register the value by which you want to be increased or reduced from the initial count set in the counter To add write the value you want to add to the correction register directly as is to subtract write the two s complement of the value you want to subtract to t
208. 1 TSZSL1 SADSL1 DADSL1 When reset 00 gt D Bit Name Function R 0 MDSEL1 0 Normal mode Selects 1 transfer mode 1 Ring buffer mode 1 TREQF1 0 Not requested O A DMA1 transfer request flag 1 Requested 2 3 REQSL1 00 Software start O O Selects cause of DMA1 request 01 MJT output event bus 0 10 Use inhibited 11 One transfer completed 4 TENL1 0 Disables transfer O Enables 1 transfer 1 Enables transfer 5 TSZSL1 0 16 bits Selects DMA1 transfer size 1 8 bits 6 SADSL1 0 Fixed Selects DMA1 source address direction 1 Incremental 7 DADSL1 0 Fixed Selects DMA1 destination 1 Incremental address direction W A Only writing a 0 is effective when you write 1 the previous value is retained 9 7 Ver 0 10 9 DMAC 9 2 DMAC Related Registers E DMA2 Channel Control Register DM2CNT Address 0080 0430 DO 1 3 4 5 6 D7 MDSEL2 TREQF2 TENL2 TSZSL2 SADSL2 DADSL2 When reset 00 gt D Bit Name Function R 0 MDSEL2 0 Normal mode Selects transfer mode 1 Ring buffer mode 1 TREQF2 0 Not requested A DMA2 transfer request flag 1 Requested 2 3 REQSL2 00 Software start Selects cause of DMA2 request 01 MJT output event bus 1 10 MJT TIN18 input signal 11 transfer completed 4 TENL2 0 Disables transfer Ena
209. 1 During measure free run clear input mode even if this bit is set to O external input disabled when a capture signal is entered from an external device the counter value at that point in time is written to the measure register However because in measure clear input mode if this bit 0 external input disabled the counter value is not initialized H FFFF upon capture we recommend that this bit be set to 1 external input enabled when using measure clear input mode Note 2 Always make sure the counter has stopped and is idle before setting or changing operation modes 10 94 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer Clock bus Input event bus 3210 3210 TCLK1 OdTCLK1S tet 5 Ck TIO5 t S TIT TCLK2 OA TCLK2S 4 B en cap TIO6 S TIT Tu S clk enicap 4 5 CK en cap 8 H S TIT 7 2 Ck TIO9 o 4 S 3210 3210 S Selector Note This is an outline diagram shown for the explanation of TIO Control Register Figure 10 4 6 Outline Diagram of
210. 1 7 No functions assigned 0 8 15 SBANKAD A12 A19 of start address of the S bank S bank address to be selected Note This register must always be accessed in halfword 1 MODENS Virtual Flash Emulation Enable bit DO The MODENS bit can be set to 1 after entering virtual flash emulation mode by setting the FEMMOD bit to 1 while the FENTRY bit 0 This causes the virtual flash emulation function to become effective for the S bank area selected by the SBANKAD bits 2 SBANKAD S Bank Address bits D8 D15 The SBANKAD bits are provided for selecting one S bank from a total of 192 S banks separated every 4 KB Use these SBANKAD bits to set the eight bits A12 A19 of the 32 bit start address of the S bank you want to select For details refer to Section 6 7 Virtual Flash Emulation Function 6 15 Ver 0 10 6 INTERNAL MEMORY 6 5 Programming of the Internal Flash Memory 6 5 Programming of the Internal Flash Memory 6 5 1 Outline of Programming Flash Memory When writing to the internal flash memory there are following two methods to use depending on situation 1 When the write program does not exist in the internal flash memory 2 When the write program already exists in the internal flash memory For 1 set the FP pin high MODO high and MOD1 low to enter boot flash E W enable mode In this case the reset vector entry is located at the beginning of the boot program area H 8000 0000 Normal
211. 1 Outline of the Real Time Debugger RTD Item Content Transfer method Clock synchronized serial Generation of transfer clock Generated by external host RAM access area Entire area of internal RAM controlled by A16 A29 Transmit receive data length 32 bits fixed Bit transfer sequence LSB first Maximum transfer rate 2 Mbits second Input output pins 4 lines RTDTXD RTDRXD RTDACK RTDCLK Number of commands Following five functions Monitors continuously Outputs real time RAM contents Forcibly rewrites RAM contents with verify Recovers from runaway Requests RTD interrupt RTD control circuit Entire RAM dc CPU 22 Control circuit RTDCLK cc RTDACK Address Data Address Data Command EE RTDTXD Address T3 O Data Data RTDRXD Bus switching circuit Figure 14 1 1 Block Diagram of the Real Time Debugger RTD 14 2 Ver 0 10 14 REAL TIME DEBUGGER RTD 14 2 Pin Function of the RTD 14 2 Pin Function of the RTD Pin functions of the RTD are shown below Table 14 2 1 Pin Function of the RTD Pin Name Type Function RTDTXD Output RTD serial data output RTDRXD Input RTD serial data input RTDACK Output Outputs a low level pulse synchronously with the beginning clock edge of the output data word The width of the low level pu
212. 11 12 13 14 D15 IEB3S IEB2S IEB1S IEBOS uai CKB2S When reset H 00 gt D Bit Name Function R 8 9 IEB3S OX Selects external input 3 O O input event bus 3 input selection 10 Selects output event bus 2 11 Selects TIO7 output 10 11 1 25 00 Selects external input 0 TINO O O input event bus 2 input selection 01 No selection 1X No selection 12 IEB1S 0 No selection input event bus 1 input selection 1 Selects 6 output 13 IEBOS 0 No selection input event bus 0 input selection 1 Selects 5 output 14 No functions assigned 0 15 CKB2S 0 Selects prescaler 2 Clock Bus 2 input selection 1 Selects external clock 3 TCLK3 The register CKIEBCR is used to select the clock source external input or prescaler supplied to the clock bus and the count enable capture signal external input or output event bus supplied to the input event bus 10 13 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer Output Event Bus Control Register OEBCR Address H 0080 0205 D8 9 10 11 12 13 14 D15 OEB3S 25 15 mar OEBOS When reset 00 gt D Bit Name Function R 8 9 5 00 Selects TOP8 output O output event bus 3 input selection 01 Selects TIO3 output 10 Selects TIO4 output 11 Selects TIO8 output 10 No functions assigned 0 11 OEB2S 0 Selects TOP9 outpu
213. 14 Time Stamp COMSL14TSP Address H 0080 11 gt E CANO Message Slot 15 Time Stamp COMSL15TSP Address H 0080 11FE gt DO 1 2 3 4 5 6 7 8 9 10 1 12 13 14 015 COMSLnTSP When reset Indeterminate gt D Bit Name Function R 0 15 COMSLRnTSP Message slot n time stamp These registers the transmit frame receive frame memory space When the CAN module finishes transmitting or receiving the CANO Time Stamp Count Register value is set in this register 13 52 Ver 0 10 1 3 CAN MODULE 13 3 CAN Protocol 13 3 CAN Protocol 13 3 1 CAN Protocol Frame There are four types of frames which are handled by CAN protocol 1 2 3 4 Data frame Remote frame Error frame Overload frame Frames are separated from each another by an interframe space YS YS WH Data frame Standard format Arbitration field ACK field CRC field Data field Control field Remote frame Standard format Extended format T SOR EOF m Arbitration L ACK field field CRC field Control field Numbers in each field denote the number of bits Figure 13 3 1 CAN Protocol Frames 1 13 53 Ver 0 10 CAN MODULE 1 3 13 3 CAN Protocol Error frame 6 12 8 Error delimiter Interframe space or overload flag Error flag Overload frame space or Overload
214. 18 CHAPTER 22 TYPICAL CHARACTERISTICS 22 1 A D Conversion Characteristics eene 22 2 APPENDIX 1 MECHANICAL SPECIFICATIONS Appendix 1 1 Dimensional Outline Drawing Appendix 1 2 APPENDIX 2 INSTRUCTION PROCESSING TIME Appendix 2 1 32170 Instruction Processing Time Appendix 2 2 12 APPENDIX 3 PRECAUTIONS ABOUT NOISE Appendix 3 1 Precautions about Noise Appendix 3 2 Appendix 3 1 1 Reduction of Wiring Length Appendix 3 2 Appendix 3 1 2 Inserting a Bypass Capacitor between VSS and VCC Lines Appendix 3 4 Appendix 3 1 3 Processing Analog Input Pin Wiring Appendix 3 5 Appendix 3 1 4 Consideration about the Oscillator Appendix 3 6 Appendix 3 1 5 Processing Input Output Ports Appendix 3 8 13 This is a blank page 14 CHAPTER 1 OVERVIEW 1 1 Outline of the 32171 1 2 Block Diagram 1 3 Pin Function 1 4 Pin Layout 1 OVERVIEW 1 1 Outline of the 32171 1 1 Outline of the 32171 1 1 1 M32R Family CPU Core 1 Based on RISC architecture The 32171 is a 32 bit RISC single chip microcomputer which is built around the M32R family CPU core hereafter referred to as the M32R and incorporates flash mem
215. 1SIDO Address H 0080 11102 CANO Message Slot 2 Standard 100 COMSL2SIDO Address H 0080 11202 CANO Message Slot 3 Standard 100 COMSLSSIDO Address H 0080 1130 E CANO Message Slot 4 Standard 100 COMSLASIDO Address H 0080 1140 2 E CANO Message Slot 5 Standard 100 COMSLSSIDO Address H 0080 1150 E CANO Message Slot 6 Standard 100 COMSL6SIDO Address H 0080 1160 CANO Message Slot 7 Standard 100 COMSL7SIDO Address H 0080 11702 E CANO Message Slot 8 Standard 100 COMSL8SIDO Address H 0080 1180 E CANO Message Slot 9 Standard 100 COMSL9SIDO Address H 0080 1190 CANO Message Slot 10 Standard IDO COMSL10SIDO Address H 0080 11A0 gt CANO Message Slot 11 Standard IDO COMSL11SIDO Address H 0080 11 0 gt CANO Message Slot 12 Standard IDO COMSL12SIDO Address H 0080 11C0 gt CANO Message Slot 13 Standard IDO COMSL13SIDO Address H 0080 1100 gt E CANO Message Slot 14 Standard 100 COMSL14SIDO Address H 0080 11 0 gt CANO Message Slot 15 Standard 100 COMSL15SIDO Address H 0080 11 0 gt DO 1 2 3 4 5 6 D7 SIDO SID1 SID2 SID3 SID4 When reset Indeterminate gt D Bit Name Function R 0 2 No functions assigned 0 3 7 SIDO SID4 Standard IDO to standard ID4 Q Q Standard IDO to standard ID4 These registers are the transmit frame receive frame memory space 13 38 Ver 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers E CANO Message
216. 2 Precautions to be observed when using TIO single shot output mode The following describes precautions to be observed when using TIO single shot output mode f the counter stops due to underflow in the same clock period as the timer is enabled by external input the former has priority so that the counter stops f the counter stops due to underflow in the same clock period as count is enabled by writing to the enable bit the latter has priority so that count is enabled f the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit the latter has priority so that count is disabled Because the internal circuit operation is synchronized to the count clock prescaler output a finite time equal to a prescaler delay is included before F F starts operating after the timer is enabled 10 116 Ver 0 10 10 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer TIO interrupt Enabled Disabled by writing to enable bit by underflow or by external input y y Count clock Enable bit NT DR Counts down starting H A000 reload 0 register Counter set value tud Reload 0 register Q Reload 1 register Not used F F output P Data inverted by enable Data inv
217. 2 TIO9ENS 00 No selection TIO9 enable measure 01 External input TIN1 input source selection 10 Input event bus 1 11 Input event bus 3 13 15 TIO9M 000 Single shot output mode Q Q TIO9 operation mode selection 001 Delayed single shot output mode 010 Continuous output mode 011 PWM output mode 100 Measure clear input mode 101 Measure free run input mode 11X Noise processing input mode Note Always make sure the counter has stopped and is idle before setting or changing operation modes 10 100 Ver 0 10 1 0 MULTIJUNCTION 5 10 4 TIO Input Output related 16 bit Timer 10 4 5 TIO Counter TIOOCT TIO9CT TIOO Counter TIOOCT Address H 0080 0300 gt Bi TIO1 Counter TIO1CT Address H 0080 0310 TIO2 Counter 2 Address H 0080 0320 TIO3 Counter Address H 0080 0330 gt E TIO4 Counter TIO4CT lt Address H 0080 0340 E TIO5 Counter 5 Address H 0080 0350 gt E TIO6 Counter 6 Address H 0080 0360 gt TIO7 Counter TIO7CT Address H 0080 0370 TIO8 Counter TIO8CT Address H 0080 0380 gt TIO9 Counter TIO9CT Address H 0080 0390 gt DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 TIOOCT TIO9CT When reset Indeterminate gt D Bit Name Function R 0 15 TIOOCT TIO9CT 16 bit counter value W A Write to this register is not accepted is disabled PWM output mode Note This register must always be accessed
218. 3 Data 1 COMSL3DT1 E CANO Message Slot 4 Data 1 COMSL4DT1 E CANO Message Slot 5 Data 1 COMSL5DT1 E CANO Message Slot 6 Data 1 COMSL6DT1 E CANO Message Slot 7 Data 1 COMSL7DT1 E CANO Message Slot 8 Data 1 COMSL8DT1 CANO Message Slot 9 Data 1 COMSL9DT1 E CANO Message Slot 10 Data 1 COMSL10DT1 E CANO Message Slot 11 Data 1 COMSL11DT1 E CANO Message Slot 12 Data 1 COMSL12DT1 E CANO Message Slot 13 Data 1 COMSL13DT1 E CANO Message Slot 14 Data 1 COMSL14DT1 E CANO Message Slot 15 Data 1 COMSL15DT1 D8 9 10 11 12 CAN MODULE 13 2 CAN Module Related Registers Address H 0080 1107 Address H 0080 1117 Address H 0080 1127 Address H 0080 1137 Address H 0080 1147 Address H 0080 1157 Address H 0080 1167 Address H 0080 1177 Address H 0080 1187 Address H 0080 1197 Address H 0080 11 7 gt Address H 0080 11 7 gt Address H 0080 11 7 gt Address H 0080 11D7 gt Address H 0080 11E7 Address H 0080 11F7 gt 13 14 D15 COMSLnDT1 D Bit Name 8 15 COMSLnDT1 lt reset Indeterminate gt Function R Message slot n data 1 O O These registers are the transmit frame receive frame memory space Note indeterminate value is written to this register 13 45 For receive slots if when storing a data frame the data length DLC value 1 an Ver 0 10 13 CANO Message Slot 0 Data 2 COMSLODT2 CANO Message Slot 1 Data 2
219. 3210 3210 PET Figure 10 1 2 Block Diagram of MJT 2 3 10 5 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 1 Outline of Multijunction Timers Clock bus Input event bus Output event bus 3210 3210 542 apo completed f DMAIRQO 8 pMao 41 5 Note3 TIN18 S DMA2 ui DMAIRQO Note 2 Note 3 SIO0 TXD SIO1 RXD S DMA3 udf DMAIRQO TINO TE end Note 2 ote Note3 siOO BXD g DMA DMAIRQO TIN19 4 Note 2 Note3 SIO2 RXD 7 5 gt 1 20 5 DMAS 10 Note 2 Noreg gt 1 SIot TXD 5 Note3 SIO2 TXD S DMA7 ual DMAIRQ1 S DMAg DMAIRQ1 end 5 DMA 9 udt I DMAIRQ1 3210 3210 5126 Figure 10 1 3 Block Diagram of MJT 3 3 10 6 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer 10 2 Common Units of Multijunction Timer The common units of the multijunction timer include the following Prescaler unit Clock bus input output event bus control unit Input processing control unit Output flip flop control unit Interrupt control unit 10 2 1 Timer Common Register Map Th
220. 32171 Figure 8 2 1 Input Output Ports and Pin Function Assignments 8 5 Ver 0 10 8 PORTS AND FUNCTIONS 8 3 Input Output Port Related Registers 8 3 Input Output Port Related Registers The input output port related registers consist of the Port Data Register Port Direction Register and Port Operation Mode Register Of these the Port Operation Mode Register is available for only 6 22 Ports 4 and P225 have their pin functions determined depending on CPU operation mode selected by FP MODO and MOD1 pins Port P5 is reserved for future use An input output port related register map is shown below Address DO H 0080 070E H 0080 0710 H 0080 0712 H 0080 0714 H 0080 072bE H 0080 0730 H 0080 0732 H 0080 0734 0 Address 0702 gol red biceeo ante 0708 0708 0706 H 0080 0716 P22 Data Register P22DATA H 0080 0736 P22 Direction Register P22DIR 1 Address D7 D8 D15 P15 Data Register P15DATA P15 Direction Register P15DIR TET vv Blank addresses are reserved Note The Data Register Direction Register and Operation Mode Register for P14 P16 and P18 P21 are not included Figure 8 3 1 Input Output Port Related Register Map 1 2 8 6 Ver 0 10 INPUT OUTPUT PORTS AND FUNCTIONS 8 3 Input Output Port Related Registers Address 0 A
221. 4 1 shows a TIO block diagram Table 10 4 1 Specifications of TIO Input Output related 16 bit Timer Item Specification Number of channels 10 channels Counter 16 bit down counter Reload register 16 bit reload register Measure register 16 bit capture register Timer startup Started by writing to enable bit in software or by enabling with external input rising falling edge or both or high low level Mode selection Input mode Measure clear input mode Measure free run input mode Nose processing input mode Output mode without correction function PWM output mode Single shot output mode Delayed single shot output mode Continuous output mode Interrupt generation Can be generated by a counter underflow 10 82 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer
222. 5 H 0080 11DC CANO Message Slot 13 Data 6 COMSL13DT6 CANO Message Slot 13 Data 7 COMSL13DT7 H 0080 11DE CANO Message Slot 13 Ti me Stamp COMSL13TSP H 0080 11 0 CANO Message Slot 14 Standard IDO COMSL14SIDO CANO Message Slot 14 Standard ID1 COMSL14SID1 H 0080 11E2 CANO Message Slot 14 Extended IDO COMSL14EIDO CANO Message Slot 14 Extended ID1 COMSL14EID1 H 0080 11E4 H 0080 11E6 CANO Message Slot 14 Extended ID2 COMSL14EID2 CANO Message Slot 14 Data 0 COMSL14DTO CANO Message Slot 14 Data Length Register COMSL14DLC CANO Message Slot 14 Data 1 COMSL14DT1 H 0080 11E8 CANO Message Slot 14 Data 2 COMSL14DT2 CANO Message Slot 14 Data 3 COMSL14DT3 H 0080 11EA CANO Message Slot 14 Data 4 COMSL14DT4 CANO Message Slot 14 Data 5 COMSL14DT5 H 0080 11EC CANO Message Slot 14 Data 6 COMSL14DT6 CANO Message Slot 14 Data 7 COMSL14DT7 H 0080 11EE CANO Message Slot 14 Ti me Stamp COMSL14TSP H 0080 11F0 CANO Message Slot 15 Standard IDO COMSL15SIDO CANO Message Slot 15 Standard ID1 COMSL15SID1 H 0080 11F2 CANO Message Slot 15 Extended IDO COMSL15EIDO CANO Message Slot 15 Extended ID1 COMSL15EID1 H 0080 11F4 H 0080 11F6 CANO Message Slot 15 Extended ID2 COMSL15EID2 CANO Message Slot 15 Data 0 COMSL15DTO CANO Message Slot 15 Data Length Register COMSL15DLC CANO Message Slot 15 Data 1 COMSL1
223. 5DT1 H 0080 11F8 CANO Message Slot 15 Data 2 COMSL15DT2 CANO Message Slot 15 Data 3 COMSL15DT3 H 0080 11FA CANO Message Slot 15 Data 4 COMSL15DT4 CANO Message Slot 15 Data 5 COMSL15DT5 H 0080 11FC CANO Message Slot 15 Data 6 COMSL15DT6 CANO Message Slot 15 Data 7 COMSL15DT7 H 0080 11FE CANO Message Slot 15 Ti me Stamp COMSL11TSP H 0080 3FFE Blank addresses are reserved areas Figure 3 4 14 Register Mapping of the SFR Area 12 3 21 Ver 0 10 3 ADDRESS SPACE 3 5 EIT Vector Entry 3 5 EIT Vector Entry The EIT vector entry is located at the beginning of the internal ROM extended external areas Instructions for branching to the start addresses of respective EIT event handlers are written here Note that it is branch instructions and not the jump addresses that are written here For details refer to Chapter 4 EIT H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 H 0000 SBI System Break Interrupt RI Reset Interrupt Reserved Instruction Exception RIE AE Address Exception TRAPO TRAP1 TRAP2 TRAP3 TRAP4 TRAPS TRAP6 TRAP7 TRAP8 9 10 TRAP11 TRAP12 T
224. 6 5 Programming of the Internal Flash Memory M32171F4 s Internal Flash Memory Area 512KB H 0000 0000 H 0000 3FFF H 0000 4000 H 0000 5FFF H 0000 6000 H 0000 7FFF H 0000 8000 H 0000 FFFF H 0001 0000 H 0001 FFFF H 0002 0000 H 0002 FFFF H 0003 0000 H 0003 FFFF H 0004 0000 H 0004 FFFF H 0005 0000 H 0005 FFFF Block 0 Block 1 Block 2 Block 3 Block 4 5 7 Block 6 7 Block 8 Uneven blocks Even blocks 6 29 Figure 6 5 8 Block Configuration of the M32171F3 Flash Memory Ver 0 10 INTERNAL MEMORY 6 5 Programming of the Internal Flash Memory 4 Block Erase command The Block Erase command erases the contents of internal flash memory one block at a time For Block Erase write the command data H 2020 to any address of the internal flash memory Next write the Verify command data H DODO to the last even address of the memory block you want to erase see Table 6 5 3 Table 6 5 4 and Table 6 5 5 Target Blocks and Specified Addresses The content of this memory block is erased With the Block Erase command you cannot erase the protected blocks Block Erase is automatically performed by the internal control circuit and the completion of Block Erase can be verified by checking the Flash Status Register 1 FSTAT1 FSTAT bit Refer to Section 6 4 2 Flash Status Registers While the FSTAT bit 1 you cannot
225. 7 10 P132MOD 0 P132 Port P132 operation mode 1 TIN18 11 P133MOD 0 P133 Port P133 operation mode 1 TIN19 12 P134MOD 0 P134 Port P134 operation mode 1 TIN20 13 P135MOD 0 P135 Port P135 operation mode 1 TIN21 14 P136MOD 0 P136 Port P136 operation mode 1 TIN22 15 P137MOD 0 P137 Port P137 operation mode 1 TIN23 8 16 Ver 0 10 8 INPUT OUTPUT PORTS AND FUNCTIONS 8 3 Input Output Port Related Registers E P15 Operation Mode Register P15MOD Address H 0080 074F gt D8 9 10 11 12 13 14 D15 P150MOD P153MOD When reset 00 gt D Bit Name Function R 8 P150MOD 0 P150 150 1 TINO 9 10 No functions assigned 0 11 P153MOD 0 P153 Port P153 operation mode 1 TIN3 12 15 functions assigned 0 Note Ports P151 P152 and 154 157 are nonexistent 8 17 Ver 0 10 8 INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 3 Input Output Port Related Registers E P17 Operation Mode Register P17MOD Address H 0080 0751 D8 9 10 11 12 13 14 D15 P174MOD P175MOD When reset 00 gt D Bit Name Function R 8 11 functions assigned 0 12 P174MOD 0 P174 Port P174 operation mode 1 TXD2 13 P175MOD 0 P175 Port P175 operation mode 1 RXD2 14 15 No functions assigned 0 Note Ports 170 1713 an
226. 70 P86 RXD1 110 JTCK 31 P05 DB5 71 P87 SCLKM SCLKO1 111 JTRST 32 P06 DB6 72 VSS 112 JTDO 33 P07 DB7 73 FVCC 113 JTDI 34 P10 DB8 74 P61 114 P103 TO11 35 P11 DB9 75 P62 115 P104 TO12 36 P12 DB10 76 P63 116 105 13 37 P13 DB11 77 P64 SBI 117 P106 TO14 38 P14 DB12 78 P70 BCLK WR 118 P107 TO15 39 P15 DB13 79 P71 WAIT 119 P124 TCLKO 40 P16 DB14 80 P72 HREQ 120 P125 TCLK1 Ver 0 10 This is a blank page 1 18 Ver 0 10 CHAPTER 2 2 1 CPU Registers 2 2 General purpose Registers 2 3 Control Registers 2 4 Accumulator 2 5 Program Counter 2 6 Data Formats 2 2 1 CPU Registers 2 1 CPU Registers The MS2R has sixteen general purpose registers five control registers an accumulator a program counter The accumulator is a 56 bit configuration and all other registers are a 32 bit configuration 2 2 General purpose Registers General purpose registers are 32 bits in width and there are sixteen of them RO to R15 which are used to hold data and base addresses Especially R14 is used as a link register and R15 is used as a stack pointer The link register is used to store the return address when executing a subroutine call instruction The stack pointer is switched between an interrupt stack pointer SPI and a user stack pointer SPU depending on the value of the Processor Status Word register PSW s stack mode SM bit R8 R9 R10
227. 72 ov 5V RESET EN ov 6 3 3V VDD p 3 3V VCCI 3 3V FVCC ov 3 3V OSC VCC N ov 9 Pull the HREQ pin input low to halt the CPU at end of bus cycle Or disable RAM access software The M32R E allows P72 to be used as HREQ irrespective of its operation mode 2 With the CPU halted pull the RESET pin input low Or while RAM access is disabled pull the RESET pin input low 9 Turn off the 5 V and the 3 3 V power supply after the RESET pin goes low Reduce the VDD voltage from 3 3 V to 2 0 V as necessary Note Power shutdown requirements VDD z VCCI z FVCC OSC VCC gt VCCI Figure 20 3 2 Power Shutdown Sequence When Using RAM Backup 20 6 Ver 0 10 20 POWER UP POWER SHUTDOWN SEQUENCE 20 3 Power Shutdown Sequence M32R E VCCE lt power supply control circuit AVCCO A D converter circuit 3 3V CPU Peripheral circuits RAM Flash OSC VCC rt eg Roe ncaa gt Oscillator and PLL circuits Figure 20 3 3 Microcomputer Ready to Run State VCCE 5 V VCCI system 3 3 V VDD 3 3 V M32R E control circuit OV 5V power supply ATF AVCCO converter circuit 3 3V power supply 3 3V CPU Peripheral circuits RAM Flash Oscillator and PLL circuits Figure 20 3 4
228. 80 11 0 CANO Message Slot 15 Standard IDO COMSL15SIDO CANO Message Slot 15 Standard ID1 COMSL15SID1 H 0080 11F2 CANO Message Slot 15 Extended IDO COMSL15EIDO CANO Message Slot 15 Extended ID1 COMSL15EID1 H 0080 11F4 CANO Message Slot 15 Extended ID2 COMSL15EID2 CANO Message Slot 15 Data Length Register COMSL15DLC H 0080 11F6 CANO Message Slot 15 Data 0 COMSL15DTO CANO Message Slot 15 Data 1 COMSL15DT1 H 0080 11F8 CANO Message Slot 15 Data 2 COMSL15DT2 CANO Message Slot 15 Data 3 COMSL15DT3 H 0080 11FA CANO Message Slot 15 Data 4 COMSL15DT4 CANO Message Slot 15 Data 5 COMSL15DT5 H 0080 11FC CANO Message Slot 15 Data 6 COMSL15DT6 CANO Message Slot 15 Data 7 COMSL15DT7 H 0080 11FE CANO Message Slot 15 Time Stamp COMSL15TSP X Blank addresses reserved H 0080 3FFE Figure 13 2 4 CAN Module Related Register Map 4 4 13 7 Ver 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers 13 2 1 CAN Control Register CANO Control Register CANOCNT Address H 0080 1000 gt DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 RBO TSR TSP FRST BCM LBM RST When 0011 gt D Bit Name Function R 0 3 No functions assigned 0 4 0 Enables normal operation A Return bus off 1 Requests clearing of error counter 5 TSR 0 Enables count operation Q A Time stamp Counter reset 1 Initializes count by setting
229. 85 0 Z amp 285 BC 1 control 0 amp 284 4 P105 observe only X amp 283 1 P105 output3 X 282 0 Z amp 282 BC 1 control 0 amp 281 4 P106 observe only X amp 280 1 P106 output3 X 279 0 2 amp 279 BC 1 control 0 amp 278 4 P107 observe only X amp 277 BC_1 P107 output3 X 276 0 Z amp 276 BC 1 control 0 amp 275 BC 4 P124 observe only amp 274 1 124 output3 X 273 0 2 amp 273 BC 1 control 0 amp 272 4 P125 observe only amp Figure 19 5 8 BSDL Description for the 32171 8 14 19 22 Ver 0 10 1 9 JTAG 19 5 Boundary Scan Description Language 271 1 P125 X 270 0 2 amp 270 BC 1 control 0 amp 269 BC_4 P126 observe_only X amp 268 BC_1 P126 outputs X 267 0 2 amp 267 BC 1 control 0 amp 266 4 P127 observe only X amp 265 1 P127 Output3 X 264 0 2 amp 264 BC 1 control 0 amp 263 4 P130 observe only X amp 262 1 P130 Output3 X 261 0 2 amp 261 1 control 0 amp 260 BC_4 P131 observe_only X amp 259 BC_1 P131 outputs X 258 0 2 amp 258 BC 1 control 0 amp 257 4 P132 observe only X amp 256 1 P132 Output3 X 255 0 2 amp 255 B
230. 97 operation mode 1 20 Note Ports 90 P92 are accommodated 8 12 Ver 0 10 8 INPUT OUTPUT PORTS AND FUNCTIONS 8 3 Input Output Port Related Registers 10 Operation Mode Register P10MOD Address H 0080 074A DO 1 2 3 4 5 6 D7 P100MOD P101MOD P102MOD P103MOD P104MOD P105MOD P106MOD P107MOD When reset 00 gt D Bit Name Function R 0 P100MOD 0 P100 Port P100 operation mode 1 1 P101MOD 0 P101 Port P101 operation mode 1 TO9 2 P102MOD 0 P102 e Port P102 operation mode 1 TO10 3 P103MOD 0 P103 Port P103 operation mode 1 TO11 4 P104MOD 0 P104 Port P104 operation mode 1 TO12 5 P105MOD 0 P105 Port P105 operation mode 1 TO13 6 P106MOD 0 P106 Port P106 operation mode 1 TO14 7 P107MOD 0 P107 Port P107 operation mode 1 TO15 8 13 Ver 0 10 8 INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 3 Input Output Port Related Registers Bi P11 Operation Mode Register P11MOD Address H 0080 074B D8 9 10 11 12 13 14 D15 P110MOD P111MOD P112MOD P113MOD P114MOD P115MOD P116MOD P117MOD When reset 00 gt D Bit Name Function R 8 P110MOD 0 P110 Port P110 operation mode 1 TOO 9 P111MOD 0 P111 Port P111 operation mode 1 TO1 10 P112MOD 0 P112 Port
231. A D CONVERTERS 11 1 Outline of A D nnns 11 2 141 1 1 Conversion MODES i tee hee Eagles 11 5 11 1 2 Operation Modes eet eec dee ens 11 6 11 1 3 Special Operation Modes sse 11 10 11 1 4 Converter Interrupt DMA Transfer Requests 11 13 11 2 Converter Related Registers eene 11 14 11 2 1 Single Mode Register 0 11 16 11 2 2 Single Mode Register 1 11 19 11 2 3 Scan Mode Register 0 11 21 11 2 4 Scan Mode Register 1 11 24 11 2 5 A D Successive Approximation Register 11 26 11 2 6 A DO Comparate Data 11 27 11 2 7 10 bit A D Data Registers 11 28 11 2 8 8 bit A D Data Registers 00 11 29 11 3 Functional Description of A D Converters eene 11 30 11 3 1 How to Find Along Input Voltages 11 30 11 3 2 Conversion by Successive Approximation Method 11 31 11 3 8 Comparator Operation 11 33 11 3
232. A D conversion in scan mode restarts from the canceled channel 11 18 Ver 0 10 1 1 5 11 2 Converter Related Registers 11 2 2 Single Mode Register 1 A DO Single Mode Register 1 ADOSIM1 Address H 0080 0081 gt D8 9 10 11 12 13 14 D15 ADOSMSL ADOSSPD ANOSEL When reset H 00 gt D Bit Name Function R 8 ADOSMSL 0 A DO conversion mode A DO conversion mode selection 1 Comparator mode 9 ADOSSPD 0 Normal rate A DO conversion rate selection 1 Double rate 10 11 No functions assigned 0 12 15 ANOSEL 0000 Selects ADOINO Analog input pin selection 0001 Selects ADOIN1 0010 Selects ADOIN2 0011 Selects ADOIN3 0100 Selects ADOIN4 0101 Selects ADOIN5 0110 Selects ADOIN6 0111 Selects ADOIN7 1000 Selects ADOIN8 1001 Selects ADOIN9 1010 Selects ADOIN10 1011 Selects ADOIN1 1 1100 Selects ADOIN12 1101 Selects ADOIN13 1110 Selects ADOIN14 1111 Selects ADOIN15 W A Only writing a 0 is effective when you write a 1 device operation cannot be guaranteed A DO Single Mode Register 1 is used to control operation of the A DO converter during single mode including special mode Forcible single mode execution during scan mode 11 19 Ver 0 10 1 1 5 11 2 Converter Related Registers 1 ADOSMSL A DO conversion mode selection bit 08 This bit selects A D conversion mode for
233. ADO ADO ADO ADO ADO ADO ADO CMPO CMP1 CMP2 CMP3 CMP4 CMP5 CMP6 CMP7 CMP8 CMP9 10 11 12 13 14 15 When reset Indeterminate gt D Bit Name Function R 0 15 ADOCMPO ADOCMP 15 Note 2 0 Analog input voltage gt comparison voltage A DO comparate result flag 1 Analog input voltage comparison voltage Note 1 This register must always be accessed in halfwords Note 2 During comparator mode each bit corresponds to channels 0 through 15 When comparator mode is selected by setting the A DO Single Mode Register 1 ADOSMSL A DO conversion mode selection bit the selected analog input value is compared with the value written to the A DO Successive Approximation Register with the result stored in the corresponding bit of this comparate data register The bit is 0 when the analog input voltage gt comparison voltage and is 1 when the analog input voltage comparison voltage 11 27 Ver 0 10 11 11 2 7 10 bit A D Data Registers Bi 10 bit Data Register 0 ADODTO E 10 bit A DO Data Register 1 ADODT1 E 10 bit A DO Data Register 2 ADODT2 Bi 10 bit Data Register ADODT3 E 10 bit A DO Data Register 4 ADODT4 Bi 10 bit A DO Data Register 5 ADODT5 Bi 10 bit A DO Data Register 6 ADODT6 E 10 bit A DO Data Register 7 ADODT7 Bi 10 bit Data Register 8 ADODT8 Bi 10 bit A DO Data Register 9 ADODT9 Bi 10 bit A DO Data Regi
234. ADODT12 ADODT13 ADODT14 ADODT15 a Figure 11 2 1 Converter Related Register Map 1 2 11 14 Ver 0 10 11 5 11 2 Converter Related Registers Address H 0080 00DO H 0080 00D2 H 0080 00D4 H 0080 00D6 H 0080 00D8 H 0080 00DA H 0080 OODC H 0080 OODE H 0080 00 0 H 0080 00 2 H 0080 00 4 H 0080 00 6 H 0080 00 8 H 0080 00 H 0080 00 H 0080 OOEE 0 Address DO D7 D8 1 Address D15 8 bit A DO Data Register 0 ADO8DTO 8 bit A DO Data Register 1 ADO8DT1 8 bit A DO Data Register 2 ADO8DT2 8 bit A DO Data Register 3 ADO8DT3 8 bit A DO Data Register 4 ADO8DT4 8 bit A DO Data Register 5 ADO8DT5 8 bit A DO Data Register 6 ADO8DT6 8 bit A DO Data Register 7 ADO8DT7 8 bit A DO Data Register 8 ADO8DT8 8 bit A DO Data Register 9 ADO8DT9 8 bit A DO Data Register 10 ADO8DT10 8 bit A DO Data Register 11 ADO8DT11 8 bit A DO Data Register 12 ADO8DT12 8 bit A DO Data Register 13 ADO8DT13 8 bit A DO Data Register 14 ADO8DT14 8 bit A DO Data Register 15 ADO8DT15 Blank addresses are reserved Figure 11 2 2 A D Converter Related Register Map 2 2 11 15 Ver 0 10 1 1 CONVERTERS 11 2 Converter Related Registers 11 2 1 A D Single Mode Register 0 A DO Single M
235. ADVANCED AND EVER ADVANCING MITSUBISHI ELECTRIC P re n ary MS D m32171 U 0008 Mitsubishi 32 bit RISC Single chip Microcomputers M32R Family M32R E Series 2000 08 04 Ver0 10 NOTE Information in this manual may be changed without prior notice Mitsubishi Electric Corporation Mitsubishi Electric Semiconductor Systems Corporation Keep safety first in your circuit designs e Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable but there is always the possibility that trouble may occur with them Trouble with semiconductors may lead to personal injury fire or property damage Remember to give due consideration to safety when making your circuit designs with appropriate measures such as i placement of substitutive auxiliary circuits ii use of non flammable material or iii prevention against any malfunction or mishap Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer s application they do not convey any license under any intellectual property rights or any other rights belonging to Mitsubishi Electric Corporation or a third party Mitsubishi Electric Corporation assumes no responsibility for any damage or infringement of any third party s rights originating in the use of any product data diagrams charts or circ
236. ANO Message Slot 0 Extended ID1 COMSLOEID1 CANO Message Slot 0 Extended ID2 COMSLOEID2 CANO Message Slot 0 Data Length Register COMSLODLC CANO Message Slot 0 Data 0 0 510070 CANO Message Slot 0 Data 1 COMSLODT1 CANO Message Slot 0 Data 2 COMSLODT2 CANO Message Slot 0 Data 3 COMSLODT3 CANO Message Slot 0 Data 4 COMSLODT4 CANO Message Slot 0 Data 5 COMSLODT5 CANO Message Slot 0 Data 6 COMSLODT6 CANO Message Slot 0 Data 7 COMSLODT7 CANO Message Slot 0 Time Stamp COMSLOTSP CANO Message Slot 1 Standard IDO COMSL1SIDO CANO Message Slot 1 Extended IDO COMSL1EIDO CANO Message Slot 1 Standard ID1 COMSL1SID1 CANO Message Slot 1 Extended ID1 COMSL1EID1 CANO Message Slot 1 Extended ID2 COMSL1EID2 CANO Message Slot 1 Data Length Register COMSL1DLC CANO Message Slot 1 Data 0 COMSL1DTO CANO Message Slot 1 Data 1 COMSL1DT1 CANO Message Slot 1 Data 2 COMSL1DT2 CANO Message Slot 1 Data 4 COMSL1DT4 CANO Message Slot 1 Data 3 COMSL1DT3 CANO Message Slot 1 Data 5 COMSL1DT5 CANO Message Slot 1 Data 6 COMSL1DT6 CANO Message Slot 1 Data 7 COMSL1DT7 CANO Message Slot 1 Time Stamp COMSL1TSP CANO Message Slot 2 Standard IDO 0 51 25100 CANO Message Slot 2 Standard ID1 COMSL2SID1 CANO Message Slot 2 Extended IDO COMSL2EIDO CANO Message Slot 2 Extended ID1 COMSL2EID1 CANO Message Slot 2 Extended ID2 COMSL2EID2
237. ANO Message Slot 10 Data 1 COMSL10DT1 Figure 3 4 13 Register Mapping of the SFR Area 11 3 20 Ver 0 10 ADDRESS SPACE 3 4 Internal ROM SFR Area Address H 0080 11A8 H 0080 11AA 0 Address DO D7 CANO Message Slot 10 Data 2 COMSL10DT2 CANO Message Slot 10 Data 4 COMSL10DT4 1 Address D8 D15 CANO Message Slot 10 Data 3 COMSL10DT3 CANO Message Slot 10 Data 5 COMSL10DT5 H 0080 11AC CANO Message Slot 10 Data 6 COMSL10DT6 CANO Message Slot 10 Data 7 COMSL10DT7 H 0080 11AE CANO Message Slot 10 Ti me Stamp COMSL10TSP H 0080 11 0 CANO Message Slot 11 Standard IDO COMSL11SIDO CANO Message Slot 11 Standard ID1 COMSL11SID1 H 0080 11B2 CANO Message Slot 11 Extended IDO COMSL11EIDO CANO Message Slot 11 Extended ID1 COMSL11EID1 H 0080 11B4 CANO Message Slot 11 Extended ID2 COMSL11EID2 CANO Message Slot 11 Data Length Register COMSL11DLC H 0080 11B6 CANO Message Slot 11 Data 0 COMSL11DTO CANO Message Slot 11 Data 1 COMSL11DT1 H 0080 11B8 CANO Message Slot 11 Data 2 COMSL11DT2 CANO Message Slot 11 Data 3 COMSL11DT3 H 0080 11BA CANO Message Slot 11 Data 4 COMSL11DT4 CANO Message Slot 11 Data 5 COMSL11DT5 H 0080 11 H 0080 11BE CANO Message Slot 11 Data 6 COMSL11DT6 CANO Message Slot 11 Ti CANO Message Slot 11 Data 7 COMSL11DT7 me Stamp COMSL11TSP H 0080 11 0 CANO Mes
238. Bit Status Register 6 37 Ver 0 10 6 INTERNAL MEMORY 6 5 Programming of the Internal Flash Memory 6 5 4 Flash Write Time for Reference The time required for writing to the internal flash memory is shown below for your reference 1 M32171F4 Transfer time by SIO for a transfer data size of 512 KB 1 57600 bps x 1 frame x 11 number of transfer bits x 512 KB 100 1 s Flash write time 512 KB 256 byte block x 8 ms 16 4 s 9 Erase time entire area 50 ms x number of blocks 550 ms 2 Total flash write time entire 512 KB area When communicating at 57600 bps using UART the flash write time can be ignored because it is very short compared to the serial communication time Therefore the flash write time can be calculated using the equation below CD 101 s When writing data to flash memory at high speed by speeding up the serial communication or by other means the fastest write time possible is as follows 0 17 s 2 32171 3 D Transfer time by SIO for a transfer data size of 384 KB 1 57600 bps x 1 frame x 11 number of transfer bits x 384 KB 75 1 s Flash write time 384 KB 256 byte block x 8 ms 12 3 s 3 Erase time entire area 50 ms x number of blocks 450 ms 2 Total flash write time entire 384 KB area When communicating at 57600 bps using UART the flash write time can be ignored because it is very short compared to the serial communi
239. Blank addresses are reserved areas Figure 3 6 2 ICU Vector Table of the 32171 2 2 3 24 Ver 0 10 3 ADDRESS SPACE 3 7 Notes on Address Space 3 7 Note about Address Space Virtual flash emulation function The 32171 can map one 8 Kbyte block of internal RAM beginning with the start address into one of 8 Kbyte areas L banks of the internal flash memory and can map up to two 4 Kbyte blocks of internal RAM beginning with address H 0080 6000 into one of 4 Kbyte areas S banks of the inter nal flash memory This capability is referred to as the pseudo flash emulation function For details about this function refer to Section 6 7 Pseudo Flash Emulation Function 3 25 Ver 0 10 ADDRESS SPACE 3 7 Notes on Address Space This is a blank page 3 26 Ver 0 10 41 42 4 3 4 4 4 5 4 6 4 7 4 8 4 9 CHAPTER 4 Outline of EIT EIT Event EIT Processing Procedure EIT Processing Mechanism Acceptance of EIT Events Saving and Restoring the PC and PSW EIT Vector Entry Exception Processing Interrupt Processing 4 10 Trap Processing 4 11 EIT Priority Levels 4 12 Example of EIT Processing 4 EIT 4 1 Outline of EIT 4 1 Outline of EIT If some event occurs when the CPU is executing an ordinary program it may become necessary to suspend the program being executed and execute another program Events like this one are referred to by a generic name as EIT Exception Interrupt a
240. C 9 2 DMAC Related Registers E Channel Control Register DMACNT Address H 0080 0450 DO 1 3 4 5 6 D7 MDSEL4 TREQF4 bird TENL4 TSZSL4 SADSL4 DADSL4 When reset 00 gt D Bit Name Function R 0 MDSEL4 0 Normal mode Selects DMA4 transfer mode 1 Ring buffer mode 1 TREQF4 0 Not requested A DMA4 transfer request flag 1 Requested 2 3 REQSL4 00 Software start Selects cause of DMA4 request 01 One transfer completed 10 Serial 1 00 reception completed 11 MJT TIN19 input signal 4 TENL4 0 Disables transfer Enables DMA4 transfer 1 Enables transfer 5 TSZSL4 0 16 bits Selects DMA4 transfer size 1 8 bits 6 SADSL4 0 Fixed O Selects DMA4 source address direction 1 Incremental 7 DADSL4 0 Fixed O O Selects DMA4 destination 1 Incremental address direction W A Only writing a 0 is effective when you write a 1 the previous value is retained 9 10 Ver 0 10 9 DMAC 9 2 DMAC Related Registers E DMAS Channel Control Register DM5CNT Address H 0080 0418 DO 1 3 4 5 6 D7 MDSEL5 TREQF5 aa TENL5 TSZSL5 SADSL5 DADSL5 When reset 00 gt D Bit Name Function R 0 MDSEL5 0 Normal mode Selects 5 transfer mode 1 Ring buffer mode 1 TREQF5 0 Not requested O A 5 transfer request fl
241. C 1 control 0 amp 254 4 P133 observe only X amp 253 1 P133 output3 X 252 0 2 amp 252 BC_1 control 0 amp 251 BC_4 P134 observe_only X amp 250 BC_1 P134 outputs X 249 0 Z amp 249 BC_1 control 0 amp 248 BC_4 P135 observe_only X amp 247 BC_1 P135 output3 X 246 0 2 amp 246 BC 1 control 0 amp 245 BC 4 P136 observe only X amp 244 1 P136 X 243 0 2 amp 243 BC 1 control 0 amp 242 BC 4 P137 observe only X amp 241 1 P137 X 240 0 2 amp 240 BC 1 control 0 amp 239 4 P150 observe only X amp 238 1 P150 Output3 X 237 0 2 amp 237 BC 1 control 0 amp 236 4 P153 observe only X amp 235 1 P153 Output3 X 234 0 2 amp 234 BC 1 control 0 amp 233 BC_4 P41 observe_only X amp 232 BC_1 P41 output3 X 231 0 2 amp 231 1 control 0 amp 230 BC 4 P42 observe only X amp 229 BC 1 P42 output3 X 228 0 2 amp 228 BC 1 control 0 amp 227 BC_4 P43 observe_only X amp 226 BC_1 P43 outputs X 225 0 Z amp 225 BC_1 control 0 amp 224 BC_4 P44 observe_only X amp 223 BC_1 P44 outputs X 222 0 2 amp 222 1 control 0 amp 221 4 P45 o
242. CLK2 2 P225 A12 42 VREFO 82 74 RTDTXD 122 127 3 OSC VSS 43 83 75 RTDRXD 123 VCCI 4 XIN 44 ADOINO 84 P76 RTDACK 124 P130 TIN16 5 XOUT 45 ADOIN1 85 P77 RTDCLK 125 P131 TIN17 6 OSC VCC 46 ADOIN2 86 P93 TO16 126 P132 TIN18 7 VONT 47 87 P94 TO17 127 P133 TIN19 8 P30 A15 48 ADOIN4 88 P95 18 128 P134 TIN20 9 P31 A16 49 5 89 96 TO19 129 135 21 10 P32 A17 50 6 90 97 20 130 136 22 11 P33 18 51 ADOIN7 91 RESET 131 P137 TIN23 12 P34 A19 52 ADOIN8 92 MODO 132 VCCE 13 P35 A20 53 9 93 MOD1 133 150 TINO 14 P36 A21 54 ADOIN10 94 FP 134 P153 TIN3 15 P37 A22 55 ADOIN11 95 VCCE 135 P41 BLW BLE 16 P20 A23 56 ADOIN12 96 VSS 136 P42 BHW 17 P21 A24 57 97 110 00 137 18 22 25 58 14 98 111 1 138 VSS 19 P23 26 59 ADOIN15 99 112 2 139 RD 20 VCCE 60 550 100 P113 140 P44 CS0 21 VSS 61 VCCI 101 P114 4 141 P45 CS1 22 P24 A27 62 55 102 115 142 P46 A13 23 25 A28 63 P174 TXD2 103 116 6 143 P47 14 24 P26 A29 64 P175 RXD2 104 P117 TO7 144 P220 CTX 25 P27 A30 65 VCCE 105 P100 TO8 26 DBO 66 P82 TXDO 106 101 TO9 27 P01 DB1 67 P83 RXDO 107 P102 TO10 28 P02 DB2 68 P84 SCLKIO SCLKOO 108 VDD 29 P03 DB3 69 P85 TXD1 109 JTMS 30 P04 DB4
243. CPU Reset State 20 7 Ver 0 10 20 POWER UP POWER SHUTDOWN SEQUENCE 20 3 Power Shutdown Sequence M32R E VCCE 5 gt 5V power supply control circuit H A D converter circuit VCCI OV gt 43 3 power supply e CPU 7777 Peripheral circuits VDD gt RAM Flash OSC VCC Oscillator and PLL circuits Figure 20 3 5 CPU Halt State 2 0 2 5V power supply 7777 control circuit A D converter circuit ov 3 3V power supply CPU ZUM Peripheral circuits VDD 3 3V 2 0V RAM FVCC Flash OSC VCC PRADA Oscillator and PLL circuits Figure 20 3 6 SRAM Data Backup State 20 8 Ver 0 10 CHAPTER 21 ELECTRICAL CHARACTERISTICS 21 1 Absolute Maximum Ratings 21 2 Recommended Operating Conditions 21 3 DC Characteristics 21 4 A D Conversion Characteristics 21 5 AC Characteristics 21 ELECTRICAL CHARACTERISTICS 21 1 Absolute Maximum Ratings 21 1 Absolute Maximum Ratings Absolute Maximum Ratings Guaranteed for Operation at 40 to 125 C Internal Logic Power Supply Voltage VDD2VCCIZFVCC OSC VCC 0 3 to 4 2 RAM Power Supply Voltage VDDZ VCCIZ FVCC OSC VCC 0 3 to 4 2 PLL Powe
244. CSIO Mode 12 5 Precautions on Using CSIO Mode Settings of SIO Transmit Receive Mode Register and SIO Baud Rate Register The SIO Transmit Receive Mode Register and SIO Baud Rate Register and the Transmit Control Register s BRG count source select bit must always be set when not operating When transmitting or receiving data be sure to check that transmission and or reception under way has been completed and clear the transmit and receive enable bits before you set the registers Settings of Baud Rate BRG Register If you selected f BCLK with the BRG clock source select bit make sure the BRG register value you set does not exceed 2 Mbps About successive transmission To transmit multiple data successively set the next transmit data in the SIO Transmit Buffer Register before transmission of the preceding data is completed About reception Because during CSIO mode the receive shift clock is derived from operation of the transmit circuit you need to execute transmit operation by sending dummy data even when you only want to receive data In this case note that if the port function is set for TXD pin by setting the operation mode register to 1 dummy data is actually output from the pin About successive reception To receive multiple data successively set data dummy data in the SIO Transmit Buffer Register before the transmitter starts sending data Transmit receive operations using DMA To transmit receive data in
245. CTION TIMERS 10 4 TIO Input Output related 16 bit Timer Continued from the preceding page D Bit Name 9 11 TIO1M TIO1 operation mode selection Function R 000 Single shot output mode 001 Delayed single shot output mode 010 Continuous output mode 011 PWM output mode 100 Measure clear input mode 101 Measure free run input mode 11X Use inhibited 12 TIOOENS TIOO enable measure input source selection 0 No selection O 1 External input 13 15 TIOO operation mode selection 000 Single shot output mode 001 Delayed single shot output mode 010 Continuous output mode 011 PWM output mode 100 Measure clear input mode 101 Measure free run input mode 11X Noise processing input mode Note 3 This register must always be accessed in halfwords Note 4 Always make sure the counter has stopped and is idle before setting or changing operation modes Clock bus Input event bus 3210 3210 T S 4 7 cik en cap TIO TIN3 5 S 0 l T en cap TIO S 1 f clk en cap TIO S I 2 ii en cap TIO 3 n S Ik M eE y 5 3210 3210 S Selector Note This diagram is shown for the explanation of TIO
246. Conceptual Diagram of A D Conversion Time Table 11 3 1 List of Conversion Clock Periods Unit BCLK Transfer Start dummy A D conversion Comparate execu End Scan to scan rate Note 1 Note2 Note 3 execution cycle tion cycle dummy dummy Note 4 Normal rate 4 4 4 294 42 1 4 Double rate 4 4 4 168 24 1 4 Note 1 This applies to a software triggered case Note 2 This applies to a hardware triggered case Note 3 This applies to a comparator mode case where a value is written to the A D Successive Approximation Register Note 4 This applies to only scan mode and is added to the execution time for each channel 11 35 Ver 0 10 11 Table 11 3 2 Total Conversion Time Conversion started by Conversion rate Conversion mode Note 1 A D CONVERTERS 11 3 Functional Description of A D Converters Conversion time BCLK Software trigger Normal Single mode 299 Note 2 Single shot scan 4 channel scan 1193 Continuous 8 channel scan 2385 16 channel scan 4769 Comparator mode 47 2 Single mode 173 Single shot scan 4 channel scan 689 Continuous 8 channel scan 1377 16 channel scan 2753 Comparator mode 27 Hardware trigger Normal Single mode 299 Note 3 Single shot scan 4 channel scan 1193 Continuous 8 channel scan 2385 16 channel scan 4769 Comparator mode 47 2 Single mode 173 Single shot scan 4 channel scan 689 Continuous 8 channel scan 1377
247. D 0 8VCCE TxD th CLk D gt gt 0 8VCCE 0 8VCCE RxD M 0 2VCCE 02VCCE P b CSIO mode with external clock selected 7 tw CLKH gt CLKin 2 TxD tsu D CLK 0 thicLk D Cee NES 0 8VCCE RxD lt 0 2 0 2 Figure 21 5 2 Serial I O Timing 21 18 Ver 0 10 ELECTRICAL CHARACTERISTICS 21 21 5 AC Characteristics SBI 0 2 0 2 13 tw SBIL Figure 21 5 3 SBI Timing BCLK 15 4 i 0 8VCCE TOi X 02 Figure 21 5 4 TOi Timing 0 8VCCE 0 8VCCE TINI lt 0 2VCCE o2vcce P Figure 21 5 5 TINi Timing 21 19 Ver 0 10 21 ELECTRICAL CHARACTERISTICS 21 5 AC Characteristics tc BCLK tw BCLKH tw BCLKL A 20 0 43VCCE td BCLKH 23 td BCLKH A tv BCLKH A 2 5 12 0 918 50 51 29 ta cs RDL td A RDL CS lt tw RDL RD 0 4 0 4 OXeVCCE tw RDH tsu D RDH 45 th RDH D Data Input JANGCE 0 43VCCE 00 015 0 16VCCE 87 tsu D BCLKH G3 th BCLKH D P td BLWH RDL 5 td BHWH RDL 68 td RDH BLWL E td RDH BHWL La BLW BHW tpzx BCLKL DZ tpxz BCLKH DZ tpzx RDH D
248. D4X D3 X D2X D1 d Attribute of D7 06 DO When it agrees with the selected parity attribute PAR 0 is added 1 When it agrees with the selected parity attribute PAR 0 is added When receiving Received data is checked to see if the number of 1 s included in its data bits and the parity bit agrees with the parity attribute known as parity check MSB LSB ST D7 X DX D5 D4 D3 D2 D DOXPARY SP If the result of D7 D6 DO PAR does not agree with the selected parity attribute a parity error is assumed Note 1 Shown above is an example of data format in 8 bit UART mode Note 2 The data bit numbers Dn above indicate bit numbers in a data list and not the register bit numbers Dn Figure 12 2 5 Data Format when Parity is Enabled 12 17 Ver 0 10 1 2 SERIAL I O 12 2 Serial I O Related Registers 12 2 5 SIO Transmit Buffer Registers E SIOO Transmit Buffer Register SOTXB lt Address H 0080 0112 gt SIO1 Transmit Buffer Register STTXB Address H 0080 0122 E 5102 Transmit Buffer Register S2TXB Address H 0080 0132 DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 TDATA When reset Indeterminate gt D Bit Name Function R 0 6 No functions assigned 7 15 TDATA Sets transmit data Transmit data Indeterminate when read The SIOn Transmit Buffer Register is used to set t
249. D7 DMITST9 DMITST8 DMITST7 DMITST6 DMITST5 When reset 00 gt D Bit Name Function R 0 2 No functions assigned 0 3 DMITST9 DMA9 interrupt request status 0 No interrupt request O A 4 DMITST8 interrupt request status 1 Interrupt requested 5 DMITST7 DMA7 interrupt request status 6 DMITST6 DMA6 interrupt request status 7 DMITST5 DMAS interrupt request status W A Only writing a 0 is effective when you write 1 the previous value is retained The DMA5 9 Interrupt Request Status Register lets you know the status of interrupt requests in channels 5 9 If the DMAn interrupt request status bit n 5 to 9 is set to 1 it means that a DMAn interrupt request in the corresponding channel has been generated DMITSTn DMAn interrupt request status bit n 5 to 9 Setting the DMAn interrupt request status bit This bit can only be set in hardware and cannot be set in software Clearing the DMAn interrupt request status bit This bit is cleared by writing 0 in software Note The DMAn interrupt request status bit cannot be cleared by writing a 0 to the Interrupt cause bit of the DMA Interrupt Control Register that the interrupt controller has When writing to the DMA5 9 Interrupt Request Status Register be sure to set the bits you want to clear to O and all other bits to 1 The bits which are thus set to 1 are unaffected by writing in software
250. DE7 IDE8 IDE9 IDE10 IDE11 IDE12 IDE13 IDE14 IDE15 When reset H 0000 gt D Bit Name Function R 0 IDEO Extended IDO 0 Standard ID format 1 IDE1 Extended ID1 1 Extended ID format 2 IDE2 Extended ID2 3 IDE3 Extended ID3 4 IDE4 Extended ID4 5 IDE5 Extended ID5 6 IDE6 Extended ID6 7 IDE7 Extended 1 7 8 IDE8 Extended ID8 9 IDE9 Extended ID9 10 IDE10 Extended 1010 11 IDE11 Extended ID11 12 IDE12 Extended ID12 13 IDE13 Extended 1013 14 IDE14 Extended ID14 15 IDE15 Extended 1015 This register selects the format of frames handled in message slots corresponding to each bit The standard ID format is selected when a message slot s corresponding bit is set to 0 or the extended ID format is selected when the bit is set to 1 Note Settings of each bit of this register can only be changed when the corresponding slot does not have transmit or receive requests set 13 15 Ver 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers 13 2 4 CAN Configuration Register CANO Configuration Register CANOCONF Address H 0080 1006 gt DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 SIN PH2 1 m SAM When reset H 0000 gt D Bit Name Function R 0 1 SJW Sets reSynchronization Jump Width reSynchronization Jump Width 00 SUW 1
251. DMA request mode enable the DMAC to accept transfer requests by setting the DMA Mode Register before you start serial communication About the receive finished bit If a receive error overrun error occurs the receive finished bit cannot be cleared by reading out the receive buffer register In this case it can only be cleared by clearing the receive enable bit 12 40 Ver 0 10 1 2 SERIAL I O 12 5 Precautions on Using CSIO Mode About overrun error If all bits of the next receive data are received in the SIO Receive Shift Register before you read out the SIO Receive Buffer Register an overrun error occurs the receive data is not stored in the Receive Buffer Register and the Receive Buffer Register retains the previously received data Thereafter although receive operation is continued no receive data is stored in the Receive Buffer Register the receive status bit 1 To restart reception normally you need to temporarily clear the receive enable bit before you restart This is the only way you can clear the overrun error flag About DMA transfer request generation during SIO transmission If the Transmit Buffer Register becomes empty the transmit buffer empty flag 1 while the transmit enable bit is set to 1 transmit enabled an SIO transmit buffer empty DMA transfer request is generated About DMA transfer request generation during SIO reception When the receive finished bit is set to 1 the receive buffer reg
252. DMAC Refer to Chapter 9 DMAC 12 33 Ver 0 10 1 2 SERIAL 12 4 Receive Operation CSIO Mode 8 Selecting pin functions Because the serial I O related pins serve dual purposes shared with input output ports set pin functions Refer to Chapter 8 Input Output Ports and Pin Functions Initial settings for CSIO reception v Set SIO Transmit Receive Mode Register Cale mode Select internal or external clock v Set SIO Transmit Control Register Select clock divider s divide by ratio Serial related registers z Set SIO Baud Rate Register Divide by ratio H 00 to H FF Note 2 v Set SIO Interrupt Mask Register r Enable disable transmit buffer empty interrupt Vv Set SIO Receive Control Register Set receive enable bit v Set the Interrupt Controller When using interrupt Set DMAC When using DMAC v Set input output port Operation Mode Register v Initial settings for CSIO reception finished Note 1 This is necessary when you use the internal clock Note 2 When you selected the internal clock and a divide by ratio 1 you are subject to limitations that the baud rate generator must be set not to exceed 2 Mbps Figure 12 4 1 Procedure for CSIO Receive Initialization 12 34 Ver 0 10 1 2 SERIAL I O 12 4 Receive
253. Data 0 0 51 50 0 CANO Message Slot 5 Data 1 COMSL5DT1 CANO Message Slot 5 Data 2 COMSL5DT2 CANO Message Slot 5 Data 3 COMSL5DT3 CANO Message Slot 5 Data 4 COMSL5DT4 CANO Message Slot 5 Data 5 COMSL5DT5 CANO Message Slot 5 Data 6 COMSL5DT6 CANO Message Slot 5 Data 7 COMSL5DT7 CANO Message Slot 5 Ti me Stamp COMSL5TSP CANO Message Slot 6 Standard IDO COMSL6SIDO CANO Message Slot 6 Standard ID1 COMSL6SID1 CANO Message Slot 6 Extended IDO COMSL6EIDO CANO Message Slot 6 Extended 101 COMSL6EID1 CANO Message Slot 6 Extended ID2 COMSL6EID2 CANO Message Slot 6 Data Length Register COMSL6DLC CANO Message Slot 6 Data 0 COMSL6DTO CANO Message Slot 6 Data 1 COMSL6DT1 CANO Message Slot 6 Data 2 COMSL6DT2 CANO Message Slot 6 Data 3 COMSL6DT3 CANO Message Slot 6 Data 4 COMSL6DT4 CANO Message Slot 6 Data 5 COMSL6DT5 CANO Message Slot 6 Data 6 COMSL6DT6 CANO Message Slot 6 Data 7 COMSL6DT7 CANO Message Slot 6 Ti me Stamp COMSL6TSP CANO Message Slot 7 Standard IDO COMSL7SIDO CANO Message Slot 7 Standard ID1 COMSL7SID1 CANO Message Slot 7 Extended IDO COMSL7EIDO CANO Message Slot 7 Extended ID1 COMSL7EID1 CANO Message Slot 7 Extended ID2 COMSL7EID2 CANO Message Slot 7 Data Length Register COMSL7DLC CANO Message Slot 7 Data 0 COMSL7DTO CANO Message Slot 7 Data 2 COMSL7DT2 CANO Messa
254. E 5 V 10 VCCI 3 3 V 0 8 V Ta 40 to 125 C Unless Otherwise Noted Parameter Condition Rated Value Output High Voltage IOH 2mA Output Low Voltage IOL 2mA RAM Retention Power Supply When operating Voltage When back up IIH High State Input Current VI VCCE uA Low State Input Current 0 EXE I f XIN When ICC 5V 5 power supply Note 1 8 0MHz operating 3 3 V power supply Note 2 f XIN 8 0MHz When operating Ta 25 C retention RAM Retention Power Supply Current power supply Ta 125 C characteristic VT VT Hysteresis Note 3 RTDCLK RTDRXD SCLKIO 1 RXDO 1 2 TCLK3 0 VCCE 5V TINO 3 16 23 RESET FP MODO 1 JTMS JTRST JTDI Note 1 Total current when VCCE AVCC VREF in single chip mode See the next page for the rated values of power supply current on each power supply pin Note 2 Total current when VCCI VDD FVCC OSC VCC in single chip mode See the next page for the rated values of power supply current on each power supply pin Note 3 All these pins except RESET serve dual functions Note 4 The HREQ pin serves dual functions 21 7 Ver 0 10 21 ELECTRICAL CHARACTERISTICS 21 3 DC Characteristics 4 Electrical characteristics of each power supply pin when f XIN 8 MHz Referenced to VCCE 5 V 0 5V VCCI 3 3 V 0 3 V Ta 40 to 125 C Unless Otherwise Noted Symbol Condition Rated Value VCCE power s
255. EID2 CANO Message Slot 11 Data Length Register COMSL11DLC H 0080 11B6 CANO Message Slot 11 Data 0 COMSL11DTO CANO Message Slot 11 Data 1 COMSL11DT1 H 0080 11B8 CANO Message Slot 11 Data 2 COMSL11DT2 CANO Message Slot 11 Data 3 COMSL11DT3 H 0080 11BA CANO Message Slot 11 Data 4 COMSL11DT4 CANO Message Slot 11 Data 5 COMSL11DT5 H 0080 11BC CANO Message Slot 11 Data 6 COMSL11DT6 CANO Message Slot 11 Data 7 COMSL11DT7 H 0080 11 CANO Message Slot 11 Ti me Stamp COMSL11TSP H 0080 11 0 CANO Message Slot 12 Standard IDO COMSL12SIDO CANO Message Slot 12 Standard ID1 COMSL12SID1 H 0080 11C2 CANO Message Slot 12 Extended 100 COMSL12EIDO CANO Message Slot 12 Extended ID1 COMSL12EID1 H 0080 11C4 CANO Message Slot 12 Extended ID2 COMSL12EID2 CANO Message Slot 12 Data Length Register COMSL12DLC H 0080 11C6 CANO Message Slot 12 Data 0 COMSL12DTO CANO Message Slot 12 Data 1 COMSL12DT1 H 0080 11C8 CANO Message Slot 12 Data 2 COMSL12DT2 CANO Message Slot 12 Data 3 COMSL12DT3 H 0080 11CA CANO Message Slot 12 Data 4 COMSL12DT4 CANO Message Slot 12 Data 5 COMSL12DT5 H 0080 11CC CANO Message Slot 12 Data 6 COMSL12DT6 CANO Message Slot 12 Data 7 COMSL12DT7 H 0080 11CE CANO Message Slot 12 Time Stamp COMSL12TSP H 0080 1100 CANO Message Slot 13 Standard IDO COMSL13SIDO CANO
256. EL 00 conversion start trigger select bit D3 This bit selects whether to apply the A D conversion start trigger in software or in hardware during scan mode of the A DO converter When software trigger is selected A D conversion is started by setting the ADOCSTT A DO conversion start bit to 1 When hardware trigger is selected set the ADOCTRG hardware trigger select bit to 1 and specify conversion to be started by MJT output 4 ADOCREQ A DO interrupt DMA transfer request select bit D4 This bit selects whether to generate an A DO conversion interrupt request or a DMA transfer request at completion of one cycle of scan mode operation 5 ADOCCMP A DO conversion complete bit D5 This is a read only bit and is 1 when reset This bit is 0 when scan mode conversion of the A DO converter is in progress and set to 1 when one shot scan mode operation is completed or when continuous scan mode is stopped by setting the ADOCSTT A DO conversion stop bit to 1 11 22 Ver 0 10 1 1 5 11 2 Converter Related Registers 6 ADOCSTP A DO conversion stop bit D6 Scan mode operation of the A DO converter can be stopped by setting this bit to 1 while scan mode A D conversion is under way This bit is effective for only scan mode operation and does not affect single mode operation when both single and scan modes of special operation mode are active Operation is stopped immediately after writing t
257. ERRUPT CONTROLLER ICU 5 1 Outline of the Interrupt Controller ICU Interrupt controller System Break Interrupt request generated SBI Control Register SBICR SBIREQ 5 spi To SBI the CPU core Peripheral circuits ge pep recognized IREQ 2 2 Interrupt Edge ILEVEL Maskable interrupt request eee IREQ request generated Interrupt recognized request ua 2 Els 2 5 Interrupt Vector Register 211 5 5 IMASK El it e 5 3 gt ine Interrupt oie d 5 8 core U recognize mt control circuit gt NEW IMASK L IREQ o S aa evel A d Interrupt recognized i lt l control circuit S Interrupt Mask Register Level IREQ 5119 IMASK Interrupt recognized po 2 control circuit Interrupt Control Register Figure 5 1 1 Block Diagram of the Interrupt Controller 5 3 Ver 0 10 INTERRUPT CONTROLLER ICU 5 2 Interrupt Sources of Internal Peripheral I Os 5 2 Interrupt Sources of Internal Peripheral I Os The interrupt controller receives as its inputs the interrupt requests from MJT multijunction timer serial I O A D converter RTD and CAN For details abou
258. ERTERS 11 1 Outline of Converters 11 2 A D Converter Related Registers 11 3 Functional Description of A D Converters 11 4 Precautions on Using A D Converters 1 1 CONVERTERS 11 1 Outline of Converters 11 1 Outline of A D Converter The 32171 contains a 10 bit resolution A D converter based on successive approximation method A total of 16 analog input pins channels from ADOINO to ADOIN15 are available The A D conversion results can be read out in either 8 bits or 10 bits For A D conversion there are following conversion modes and operation modes 1 Conversion mode A D conversion mode Ordinary mode in which analog input voltages are converted into digital quantities Comparator mode Note A mode in which analog input voltage is compared with a preset comparison voltage to only find the relative magnitude of two quantities Single mode only 2 Operation mode Single mode Analog input voltage in one channel is A D converted once or comparated note with a given quantity Scan mode Analog input voltages in multiple selected channels 4 8 or 16 channels are sequentially A D converted 3 Types of scan modes Single shot scan mode Scan operation is performed for one machine cycle Continuous scan mode Scan operation is performed repeatedly until stopped 4 Special operation mode Forcible single mode execution during scan mode Conversion is forcibl
259. G related registers are shown below Test Logic Reset 0 Capture IR 0 Shift IR D 1 7 1 Exit1 IR 4 Pause IR y 1 Update IR 1 0 LA Note Values 0 and 1 in this diagram denote the state of JTMS input signal Figure 19 4 1 TAP Controller State Transition Shift register stage p To next cell Input multiplexer Data input 0 Shift DR or Shift IR Clock DR or Clock IR Update DR or Update IR Test reset Parallel output stage From preceding cell Note Shown here is the basic configuration and the configuration of DR and IR does not all have to be like this Figure 19 4 2 Basic Configuration of JTAG Related Registers 19 7 Ver 0 10 1 9 JTAG 19 4 Basic Operation of JTAG 19 4 2 IR Path Sequence Instruction code is set in the Instruction Register JTAGIR to select the data register to be accessed in the subsequent DR path sequence The IR path sequence is performed following the procedure described below 1 Enter JTMS high for a period of two JTCK cycles from Run Test Idle state to go to Select IR Scan state 2 Set JTMS low to go to Capture IR state At this time b 110001 fixed value is set in the instruction register s shift register stage 3 Subsequently enter JTMS low to go to Shift IR state In Shift IR stat
260. Generation Register 0 1 Serial 1 01 transmit buffer empty When serial 1 transmit buffer is emptied 1 0 None Use inhibited 1 1 One 5 transfer completed When one DMAS transfer is completed cascade mode Table 9 3 8 Causes of DMA Requests DMA7 and Generation Timings REQSL7 Cause of DMA Request 0 0 Software start DMA Request Generation Timing When any data is written to DMA7 Software Request Generation Register 0 1 Serial 2 transmit buffer empty When serial 1 2 transmit buffer is emptied 1 0 None Use inhibited 1 1 One DMA6 transfer completed When one DMA6 transfer is completed cascade mode 9 29 Ver 0 10 9 DMAC 9 3 Functional Description of the DMAC Table 9 3 9 Causes of DMA Requests in DMA8 and Generation Timings REQSL8 Cause of DMA Request DMA Request Generation Timing 0 0 Software start When any data is written to DMA8 Software Request Generation Register 0 1 input event bus 0 When MJT s input event bus 0 signal is generated 1 0 None Use inhibited 1 1 None Use inhibited Table 9 3 10 Causes of DMA Requests 9 and Generation Timings REQSL9 Cause of DMA Request DMA Request Generation Timing 0 0 Software start When any data is written to DMA9 Software Request Generation Register 0 1 None Use inhibited 1 0 None Use inhibited 1 1 transfer completed When one DMAS8 transfer is
261. H 0080 0364 TIO7 Reload 1 Register TIO7RL1 Address H 0080 0374 TIO8 Reload 1 Register TIO8RL1 Address H 0080 0384 E TIO9 Reload 1 Register TIO9RL1 Address H 0080 0394 gt DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 TIOORL1 TIO9RL1 When reset Indeterminate gt D Bit Name Function R 0 15 TIOORL1 TIO9RL1 16 bit reload register value Q Q Note This register must always be accessed in halfwords The TIO Reload 1 Registers are used to reload the TIO Counter Registers TIOOCT TIO9CT with data It is in the following cases that the content of reload 1 register is loaded into the counter When the count value set by reload 0 register underflowed in PWM output mode Writing data to the reload 1 register does not mean that the data is loaded into the counter simultaneously 10 103 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer 10 4 8 TIO Enable Control Registers TIOO 9 Enable Protect Register TIOPRO lt Address H 0080 03BC gt DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 9 TIO8 TIO7 6 5 TIO4 2 TIO1 TIOO PRO PRO PRO PRO PRO PRO PRO PRO PRO PRO When reset H 0000 gt D Bit Name Function R 0 5 No functions assigned 0 6 TIO9PRO TIO9 Enable Protect 0 Enables rewrite 7 TIO8PRO 8 Enable Protect 1 Disables rewrite 8 TIO7PRO TIO7 Enable Protect 9 TIO6PRO TIO6 En
262. H 0080 11 4 gt CANO Message Slot 12 Extended ID2 COMSL12EID2 Address H 0080 11C4 gt E CANO Message Slot 13 Extended 102 COMSL13EID2 Address H 0080 11D4 gt CANO Message Slot 14 Extended ID2 COMSL14EID2 Address H 0080 11 4 gt E CANO Message Slot 15 Extended 102 COMSL15EID2 Address H 0080 11 4 gt DO 1 2 3 4 5 6 D7 EID12 EID13 EID14 EID15 EID16 EID17 When reset Indeterminate gt D Bit Name Function R W 0 1 No functions assigned 0 2 7 EID12 EID17 Extended ID12 to extended ID17 Extended 1012 to extended 1017 These registers are the transmit frame receive frame memory space Note When set for the receive slot standard ID format values written to EID bits when storing received data in the slot are indeterminate 13 42 Ver 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers CANO Message Slot 0 Data Length Register COMSLODLC Address H 0080 1105 gt E CANO Message Slot 1 Data Length Register COMSL1DLC Address H 0080 1115 E CANO Message Slot 2 Data Length Register COMSL2DLC Address H 0080 1125 E CANO Message Slot Data Length Register COMSL3DLC Address H 0080 1135 E CANO Message Slot 4 Data Length Register COMSL4DLC Address H 0080 1145 gt E CANO Message Slot 5 Data Length Register COMSL5DLC Address H 0080 1155 gt E CANO Message Slot 6 Data Length Register COMSL6DLC Address H 0080 1165 CANO Message Slot 7 Data Length Reg
263. H WAITL 3 tsu WAITL BCLKH 1510 50 pF tpzx BCLKL DZ tsu WAITH BCLKH tpxz BCLKH DZ th BCLKH WAITH Note 1 Stipulated values are guaranteed values when the test pin load capacitance CL Note 2 Input and output signals are determined high or low with respect to TTL level Figure 21 5 7 Write Timing 21 21 Ver 0 10 21 ELECTRICAL CHARACTERISTICS 21 5 AC Characteristics Address A12 A30 0 43VCCE 0 43VCCE CS0 CS1 0 16VCCE 0 16VCCE D td RDH BLEL 6 td BLEH RDL td RDH BHEL td BHEH RDL on 0 43VCCE RD 0 16VCCE 70 td CS WRL tv WRH CS 69 td A WRL tv WRH A tw WRL WR 0 43VCCE WR 0 16VCCE 0 16VCCE td BLEL WRL tv WRH BLEL td BHEL WRL 74 tv WRH BHEL gt 4 BLE 0 16VCCE osevece JA 243 00 2 QT texz wRH bz tv WRH D Data output 00 015 Note 1 Stipulated values guaranteed values when the test pin load capacitance CL 15 to 50 pF Note 2 Input and output signals are determined high or low with respect to TTL level Figure 21 5 8 Write Timing Byte enable mode BCLK 0 16VCCE 55 tsu HREQL BCLKH HREQ 0 16VCCE 0 16VCCE K th BCLKH HREQL tv BCLKL HACKL m 4 gt LS seve 87 td BCLKL HACKL Figure 21 5 9 Bus Arbitration Timing 21 22 Ver 0 10
264. I O channel 2 Real time RTDTXD Transmit data Output Serial data output pin for the real time debugger debugger RTDRXD Receive data Input Serial data input pin for the real time debugger RTDCLK Clock input Input Serial data transmit receive clock input pin for the real time debugger RTDACK Acknowledge Output This pin outputs a low pulse synchronously with the beginning clock of the real time debugger s serial data output word The duration of this low pulse indicates the type of command data that the real time debugger has received Flash FP Flash Protect Input This mode pin has a function to protect the flash only memory against E W in hardware 1 13 Ver 0 10 OVERVIEW 1 3 Pin Function Table 1 3 1 Description of the 32171 Pin Function 4 5 Type Pin Name Signal Name Input Output Function CAN CTX Data output Output This pin outputs data from the CAN module CRX Data input Input This pin is used to input data to the CAN module JTAG JTMS Test mode Input Test mode select input to control state transition of the test circuit JTCK clock Input Clock input for the debug module and test circuit JTRST Test reset Input Test reset input to initialize the test circuit asynchronously JTDI Serial input Input This pin is used to input test instruction code or test data serially JTDO Serial output Output This pin outputs test instruction code or test data serial
265. IMERS 10 2 Common Units of Multijunction Timer E TIN Input Processing Control Register 0 TINCRO Address H 0080 0212 DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 ET ow When reset 0000 gt D Bit Name Function R 0 No functions assigned 0 1 3 45 reserved Set these bits to 000 Note 1 4 No functions assigned 0 5 7 TIN3S 000 Invalidates input input 001 Rising edge processing selection 010 Falling edge 011 Both edges 10X Low level 11X High level 8 9 No functions assigned 0 10 11 TIN2S reserved Set these bits to 00 Note 2 O O 12 13 15 reserved Set these bits to 00 Note 2 O O 14 15 05 00 Invalidates input O O TINO input 01 Rising edge processing selection 10 Falling edge 11 Both edges Note 1 Always set the TIN4S bits to 000 Note 2 Always set the TIN2S bits and TIN1S bits to 00 10 19 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer E TIN Input Processing Control Register TINCR3 Address H 0080 0218 DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D15 When reset 0000 gt D Bit Name Function R 0 1 TIN19S 19 input processing selection 00 Invalidates input O O 2 3 TIN18S TIN18 input processing selection 01 Rising edge 4 5 TIN17S TIN17 input processing selection 10 Falling edge 6 7 TIN16S TIN16 i
266. IN4 ADOINS ADOING ADOIN7 ADOIN8 ADOIN9 ADOIN10 ADOIN11 ADOIN12 ADOIN13 ADOIN14 ADOIN15 AVSS 60 VCCI 61 VSS 62 P174 P175 VCCE 65 P82 P83 P84 P85 P86 P87 VSS 72 FVCC 73 P61 P62 P63 P64 P70 P71 P72 P73 P74 P75 P76 P77 P93 P94 P95 P96 P97 inout inout inout linkage linkage linkage linkage linkage linkage linkage linkage linkage linkage linkage linkage linkage linkage linkage linkage linkage linkage linkage linkage linkage inout inout linkage inout inout inout inout inout inout linkage linkage inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit Figure 19 5 2 BSDL Description for the 32171 2 14 19 16 Ver 0 10 1 9 JTAG 19 5 Boundary Scan Description Language RESET bit MODO bit MOD1 bit FP bit VCCE 95 linkage bit VSS 96 linkage bit P110 sinout bit P111 sinout bit P112 sinout bit P113 inout bit P114 inout bit P115 inout bit
267. IO Interrupt Control Register 2 TIOIR2 TMS Interrupt Control Register TMSIR H 0080 0238 TIN Interrupt Control Register 0 TINIRO TIN Interrupt Control Register 1 TINIR1 H 0080 023A H 0080 023C TIN Interrupt Control Register 4 TINIR4 nterrupt Control Register 5 5 H 0080 023E TIN Interrupt Control Register 6 TINIR6 H 0080 0240 TOPO Counter TOPOCT H 0080 0242 TOPO Reload Register TOPORL H 0080 0244 H 0080 0246 Correction Register TOPOCC H 0080 0250 TOP1 Counter TOP1CT H 0080 0252 TOP1 Reload Register TOP1RL H 0080 0254 H 0080 0256 TOP1 Correction Register TOP1CC H 0080 0260 TOP2 Counter TOP2CT H 0080 0262 TOP2 Reload Register TOP2RL H 0080 0264 H 0080 0266 TOP2 Correction Register TOP2CC H 0080 0270 TOP3 Counter H 0080 0272 TOP3 Reload Register TOP3RL H 0080 0274 H 0080 0276 TOP3 Correction Register H 0080 0280 Counter TOP4CT H 0080 0282 Reload Register TOP4RL H 0080 0284 H 0080 0286 Correction Register TOP4CC H 0080 0290 TOP5 Counter 5 H 0080 0292 TOPS5 Reload Register TOP5RL H 0080 0294 es are reserved area Figure 3 4 5 Register Mapping of the SFR Area 3 3 12 Ver 0 10 3 ADDRESS SPACE 3 4 Internal ROM SFR Area Address 0 Address 1 Address H 0080 0296 TOP5 Correction Register T
268. IRS H 0080 0233 TOP9udf TOPIS9 2 source inputs Data bus b10 F F MJT output 0 interrupt 6 9 Level IRQ6 014 TOP8udf TOPIS8 b11 DS TOPIM8 b15 F F Figure 10 2 8 Block Diagram of MJT Output Interrupt 6 10 35 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer E TIO Interrupt Control Register 0 TIOIRO Address H 0080 0234 gt DO 1 2 3 4 5 6 D7 TIOIS3 TIOIS2 TIOIS1 TIOISO 2 TIOIM1 TIOIMO When reset 00 gt D Bit Name Function R 0 TIOIS3 interrupt status 0 No interrupt request O A 1 TIOIS2 TIO2 interrupt status 1 Interrupt request generated 2 TIOIS1 TIO1 interrupt status 3 TIOISO TIOO interrupt status 4 interrupt mask 0 Enables interrupt request O O 5 TIOIM2 TIO2 interrupt mask 1 Masks disables interrupt request 6 TIOIM1 TIO1 interrupt mask 7 TIOIMO 0 interrupt mask W A Only writing 0 is effective when you write a 1 the previous value is retained TIOIRO lt 0080 0234 gt TlO3udf Data bus TIOIS3 4 source inputs EE MJT output a interrupt 0 d TIOIM3 Level IRQO F F TlO2udf 4 TIOIS2 b1 F F r TIOIM2 b5 F F TlO1udf TIOIS1 b2 F F
269. MAO 4 Interrupt Control Register IDMAO4CR H 0080 0072 MJT Output Interrupt Control Register 0 IMJTOCRO MJT Output Interrupt Control Register 1 IMJTOCR1 H 0080 0074 MJT Output Interrupt Control Register 2 IMJTOCR2 MJT Output Interrupt Control Register 3 IMJTOCR3 H 0080 0076 MJT Output Interrupt Control Register 4 IMJTOCR4 MJT Output Interrupt Control Register 5 IMJTOCR5 H 0080 0078 MJT Output Interrupt Control Register 6 IMJTOCR6 MJT Output Interrupt Control Register 7 IMJTOCR7 H 0080 007 MJT Input Interrupt Control Register 2 IMJTICR2 MJT Input Interrupt Control Register IMJTICR3 H 0080 007E Input Interrupt Control Register 4 IMJTICR4 H 0080 0080 A DO Single Mode Register 0 ADOSIMO A DO Single Mode Register 1 ADOSIM1 H 0080 0082 0080 0084 00 Scan Mode Register 0 ADOSCMO A DO Scan Mode Register 1 ADOSCM1 0080 0086 0080 0088 A DO Successive Approximation Register ADOSAR H 0080 008A H 0080 008C A DO Comparate Data Register ADOCMP H 0080 0090 10 bit A DO Data Register 0 ADODTO H 0080 0092 10 bit A DO Data Register 1 ADODT1 0080 0094 10 bit A DO Data Register 2 ADODT2 0080 0096 10 bit A DO Data Register 3 ADODT3 0080 0098 10 bit A DO Data Register 4 ADODT4 H 0080 009A 10 bit A DO Data Register 5 ADODT5 H 0080 009C 10 bit A DO Data Register 6 ADODT6 H 0080 009E 10 bit A DO Data Register 7 ADODT7 H 008
270. MDM CONTROL amp MDM SETUP amp MTM CONTROL amp MON CODE amp MON DATA amp MON PARAM amp MON ACCESS amp DMA_RADDR amp DMA_RDATA amp DMA_RTYPE amp DMA_ACCESS amp RTDENB 0000 amp 0011001000100000 amp 00000011100 amp 4 attribute SCAN IN of TDI signal is true attribute TAP SCAN MODE of TMS signal is true attribute TAP SCAN OUT of TDO signal is true attribute SCAN CLOCK of TCK signal is 5 0 6 BOTH attribute TAP SCAN RESET of TRST signal is true attribute INSTRUCTION LENGTH of M32171F4VFP entity is 6 attribute INSTRUCTION OPCODE of M32171F4VFP entity is BYPASS 111111 amp SAMPLE 000001 amp EXTEST 000000 amp IDCODE 000010 amp USERCODE 000011 amp MDM SYSTEM 001000 amp MDM CONTROL 001001 amp SETUP 001010 amp MTM CONTROL 001111 amp MON CODE 010000 amp MON DATA 010001 amp MON PARAM 010010 amp MON ACCESS 010011 amp RADDR 011000 amp RDATA _ 011001 amp RTYPE 011010 amp ACCESS 011011 amp RTDENB 100000 attribute INSTRUCTION CAPTURE of M32171F4VFP entity is 110001 attribute INSTRUCTION PRIVATE of M32171F4VFP entity is attribute IDCODE REGISTER of M32171F4VFP entity is version part number manufacturer s identity required by 1149 1
271. Message Slot 2 Data 0 COMSL2DTO Address H 0080 1126 2 E CANO Message Slot 3 Data 0 COMSL3DTO lt Address H 0080 1136 E CANO Message Slot 4 Data 0 COMSLA4DTO Address H 0080 1146 2 E CANO Message Slot 5 Data 0 COMSL5DTO lt Address H 0080 1156 E CANO Message Slot 6 Data 0 COMSL6DTO lt Address H 0080 1166 CANO Message Slot 7 Data 0 COMSL7DTO Address H 0080 1176 2 E CANO Message Slot 8 Data 0 COMSL8DTO lt Address H 0080 1186 CANO Message Slot 9 Data 0 COMSL9DTO lt Address H 0080 1196 CANO Message Slot 10 Data 0 COMSL10DTO lt Address H 0080 11 6 gt CANO Message Slot 11 Data 0 COMSL11DTO lt Address H 0080 11 6 gt CANO Message Slot 12 Data 0 COMSL12DTO Address H 0080 11C6 gt CANO Message Slot 13 Data 0 COMSL13DTO lt Address H 0080 11D6 gt CANO Message Slot 14 Data 0 COMSL14DTO lt Address H 0080 11E6 gt CANO Message Slot 15 Data 0 COMSL15DTO lt Address H 0080 11F6 gt DO 1 2 3 4 5 6 D7 eels lt When reset Indeterminate gt D Bit Name Function R 0 7 COMSLnDTO Message slot n data 0 O O These registers are the transmit frame receive frame memory space Note For receive slots if when storing a data frame the data length DLC value 0 an indeterminate value is written to this register 13 44 Ver 0 10 13 E CANO Message Slot 0 Data 1 COMSLODT1 E CANO Message Slot 1 Data 1 COMSL1DT1 CANO Message Slot 2 Data 1 COMSL2DT1 E CANO Message Slot
272. N Control Register s BCM BasicCAN mode bit is set If BCM 0 normal operation this bit is set to 1 when the message slot is set for remote frame transmission reception If BCM 1 BasicCAN this bit shows which type of frame is received In BasicCAN mode the received data is stored in slots 14 and 15 for both data frame and remote frame If RA 0 it means that the frame stored in the slot is a data frame if RA 1 it means that the frame stored in the slot is a remote frame 13 36 Ver 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers 6 ML Message Lost bit D5 This bit is effective for receive slots It is set to 1 when the message slot contains unread receive data which is overwritten by reception This bit is cleared by writing a 0 in software 7 TRSTAT Transmit Receive Status bit D6 This bit indicates that the CAN module is transmitting or receiving and is accessing the message slot This bit is set to 1 when the CAN module is accessing and set to 0 when not accessing For transmit slots This bit is set to 1 when a transmit request for the message slot is accepted It is cleared to 0 when the CAN module lost bus arbitration when a CAN bus error occurs or when transmission is completed For receive slots This bit is set to 1 when during data reception the received data is being stored in the message slot Note that the value read from message slot while TRSTAT bit remains set is indeterminate
273. NAL BUS INTERFACE 15 2 Read Write Operations 15 2 Read Write Operations 1 When Bus Mode Control Register 0 External read write operations are performed using the address bus data bus and signals CSO CS1 RD BHW BLW WAIT and BCLK In external read cycle the RD signal is low while BHW and BLW both are high reading data from only the valid byte position of the bus In external write cycle BHW or BLW output for the byte position to which to write is pulled low as data is written to the bus When an external bus cycle starts wait cycles are inserted as long as the WAIT signal is low Unless the WAIT signal is needed leave it held high During external bus cycles at least one wait cycle is inserted even for the shortest case access The shortest bus cycle is 2 BCLK periods Bus free state internal bus access f F4 BCLK A12 A30 X7 7 cso 51 RD BHW BLW c TOME es DBO DB15 WAT JN GE Note THi Z denotes a high impedance state Figure 15 2 1 Internal Bus Access during Bus Free State 15 6 Ver 0 10 EXTERNAL BUS INTERFACE 15 2 Read Write Operations 15 Read 2 cycles Read 2 2 B E aa ore dst dor Erden sati a ea Lose D oa cci Ri gt 5 z n a E jen 5 Y o I
274. O Message Slot 0 Data 3 COMSLODT3 E CANO Message Slot 1 Data 3 COMSL1DT3 E CANO Message Slot 2 Data 3 COMSL2DT3 E CANO Message Slot 3 Data COMSL3DT3 E CANO Message Slot 4 Data 3 COMSLADT3 E CANO Message Slot 5 Data 3 COMSL5DT3 E CANO Message Slot 6 Data COMSL6DT3 E CANO Message Slot 7 Data COMSL7DT3 E CANO Message Slot 8 Data 3 COMSL8DT3 E CANO Message Slot 9 Data COMSL9DT3 E CANO Message Slot 10 Data COMSL10DT3 E CANO Message Slot 11 Data 3 COMSL11DT3 E CANO Message Slot 12 Data 3 COMSL12DT3 E CANO Message Slot 13 Data 3 COMSL13DT3 E CANO Message Slot 14 Data 3 COMSL14DT3 E CANO Message Slot 15 Data 3 COMSL15DT3 D8 9 10 11 12 CAN MODULE 13 2 CAN Module Related Registers Address H 0080 1109 Address H 0080 1119 Address H 0080 1129 Address H 0080 1139 Address H 0080 1149 Address H 0080 1159 Address H 0080 1169 Address H 0080 1179 Address H 0080 1189 Address H 0080 1199 Address H 0080 11A9 gt Address H 0080 11 9 gt Address H 0080 11C9 gt Address H 0080 1109 gt Address H 0080 11 9 gt Address H 0080 11 9 gt 13 14 D15 COMSLnDT3 D Bit Name 8 15 COMSLnDT3 When reset Indeterminate gt Function R Ww Message slot n data 3 O O These registers are the transmit frame receive frame memory space Note indeterminate value is written to this register 13 47 For receive slots if when storing a dat
275. OCTH register accommodates the 16 high order bits and the TMLOCTL register accommodates the 16 low order bits of the 32 bit counter The counter can be read on the fly 10 136 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 6 TML Input related 32 bit Timer E TML1 Counter High TML1CTH Address 0080 OFEO gt B TML1 Counter Low TML1CTL Address H 0080 2 gt D 1 2 3 4 5 6 7 8 9 10 1 12 13 14 015 TML1CTH 16 high order bits DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 TML1CTL 16 low order bits When reset Indeterminate gt D Bit Name Function R 0 15 32 bit counter value 16 high order bits Q TML1CTL 32 bit counter value 16 low order bits Note This register must always be accessed in words 32 bits beginning with the address of TML1CTH The TML1 Counter is a 32 bit up counter which starts counting upon deassertion of reset The TML1CTH register accommodates the 16 high order bits and the TML1CTL register accommodates the 16 low order bits of the 32 bit counter The counter can be read on the fly 10 137 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 6 TML Input related 32 bit Timer 10 6 6 TML Measure Registers 0 Measure 3 Register TMLOMR3H Address H 0080 03 gt 0 Measure 3 Register TMLOMR3L Address 0080 03 2 gt B TMLO Measure 2 Register TMLOMR2H Address H 0080 03 4 gt B TMLO Measure 2 Register TMLOMR2L Address H 0080 03F6 gt
276. OMSL8DLC CANO Message Slot 8 Data 0 COMSL8DTO CANO Message Slot 8 Data 1 COMSL8DT1 CANO Message Slot 8 Data 2 COMSL8DT2 CANO Message Slot 8 Data 3 COMSL8DT3 CANO Message Slot 8 Data 4 COMSL8DT4 CANO Message Slot 8 Data 6 COMSL8DT6 CANO Message Slot 8 Data 5 COMSL8DT5 CANO Message Slot 8 Data 7 COMSL8DT7 CANO Message Slot 8 Time Stamp COMSL8TSP CANO Message Slot 9 Standard IDO COMSL9SIDO CANO Message Slot 9 Standard ID1 COMSL9SID1 CANO Message Slot 9 Extended IDO COMSL9EIDO CANO Message Slot 9 Extended ID2 COMSL9EID2 CANO Message Slot 9 Extended ID1 COMSL9EID1 CANO Message Slot 9 Data Length Register COMSL9DLC CANO Message Slot 9 Data 0 COMSL9DTO CANO Message Slot 9 Data 2 COMSL9DT2 CANO Message Slot 9 Data 1 COMSL9DT1 CANO Message Slot 9 Data COMSL9DT3 CANO Message Slot 9 Data 4 COMSL9DT4 CANO Message Slot 9 Data 6 COMSL9DT6 CANO Message Slot 9 Data 5 COMSL9DT5 CANO Message Slot 9 Data 7 COMSL9DT7 CANO Message Slot 9 Time Stamp COMSL9TSP CANO Message Slot 10 Standard IDO COMSL10SIDO CANO Message Slot 10 Standard ID1 COMSL10SID1 CANO Message Slot 10 Extended 100 COMSL10EIDO CANO Message Slot 10 Extended ID1 COMSL10EID1 CANO Message Slot 10 Extended ID2 COMSL10EID2 CANO Message Slot 10 Data Length Register COMSL10DLC CANO Message Slot 10 Data 0 COMSL10DTO Blank addresses are reserved areas C
277. OP Reload Registers TOPORL TOP10RL 10 60 10 3 7 TOP Correction Registers TOPOCC TOP10CC 10 61 10 3 8 TOP Enable Control Register 10 62 10 3 9 Operation in TOP Single shot Output Mode with Correction Function 10 66 10 3 10 Operation in TOP Delayed Single shot Output Mode With Correction Function 10 73 10 3 11 Operation in TOP Continuous Output Mode Without Correction Function 10 78 10 4 TIO Input Output related 16 bit Timer cereos 10 4 1 Outline of TIO 10 82 10 4 2 Outline of Each Mode 2 10 84 10 4 3 TIO Related Register Map 10 87 10 4 4 TIO Control 10 90 10 4 5 TIO Counter 9 10 101 10 4 6 TIO Reload 0 Measure Register TIOORLO TIOQRLO 10 102 10 4 7 TIO Reload 1 Registers TIOORL1 TIOQRL1 10 103 10 4 8 TIO Enable Control Registers 10 104 10 4 9 Operation in TIO Measure Free run Clear Input Modes 10 107 10 4 10 Operation in TIO Noise Processing Input Mode 10 111 10 4 11 Operation in TIO PWM Output 10 112 10 4 12 Operation in TIO Single shot
278. OP5CC H 0080 0298 H 0080 029A TOPO 5 Control Register 0 TOPOSCRO H 0080 029C TOPO 5 Control Register 1 TOPOSCR1 H 0080 029E H 0080 02A0 TOP6 Counter TOP6CT H 0080 02A2 6 Reload Register TOP6RL H 0080 02A4 H 0080 02A6 TOP6 Correction Register 6 H 0080 02A8 H 0080 02AA TOP6 7 Control Register TOP67CR H 0080 02BO TOP7 Counter TOP7CT H 0080 02B2 TOP7 Reload Register TOP7RL H 0080 02B4 H 0080 02B6 Correction Register TOP7CC H 0080 02 0 TOP8Counter TOP8CT H 0080 02C2 TOP8 Reload Register TOP8RL H 0080 02C4 H 0080 02C6 TOP8 Correction Register TOP8CC H 0080 02D0 TOP9 Counter TOP9CT H 0080 0202 TOP9 Reload Register TOP9RL H 0080 0204 H 0080 0206 TOP9 Correction Register TOP9CC H 0080 02 0 TOP10 Counter TOP10CT H 0080 02E2 TOP10 Reload Register TOP10RL H 0080 02E4 H 0080 02E6 TOP10 Correction Register TOP10CC H 0080 02E8 H 0080 02 TOP8 10 Control Register TOP810CR H 0080 02FA 10 External Enable Register TOPEEN H 0080 02FC 10 Enable Protect Register TOPPRO H 0080 02FE TOPO 10 Count Enable Register TOPCEN H 0080 0300 TIOO Counter TIOOCT H 0080 0302 H 0080 0304 TIOO Reload Register TIOORL H 0080 0306 TIOO Reload 0 Measure Register TIOORLO H 0080 0310 TIO1 Counter TIO1CT H
279. OP5RL H 0080 0294 H 0080 0296 TOP5 Correction Register TOP5CC H 0080 0298 H 0080 029A 5 Control Register 0 TOPOSCRO 5 Control Register 1 bL 5 1 H 0080 02A0 TOP6 Counter TOP6CT H 0080 02A2 TOP6 Reload Register TOP6RL H 0080 02A4 H 0080 02A6 TOP6 Correction Register TOP6CC H 0080 02A8 H 0080 02AA 6 7 Control Register TOP67CR 22 22 Blank addresses are reserved Note The registers enclosed in thick frames must always be accessed in halfwords Figure 10 3 3 TOP Related Register Map 2 3 10 50 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer 0 Address 1 Address Address DO i D7D8 D15 H 0080 02E0 10 Counter 10 H 0080 02 2 10 Reload Register TOP10RL H 0080 02 4 H 0080 02 6 TOP10 Correction Register TOP10CC H 0080 02 8 H 0080 02 TOP8 10 Control Register TOP810CR 22 22 H 0080 O2FA TOPO0 10 External Enable Enable Register TOPEEN H 0080 02FC TOP0 10 Enable Protect Register TOPPRO H 0080 02 10 Count Enable Register TOPCEN Blank addresses are reserved Note The registers enclosed in thick frames must always be accessed in halfwords Figure 10 3 4 TOP Related Register Map 3 3 10 51 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer 10 3 4 TOP Control Regi
280. OnRLO PWM mode control Ns x Prescaler output _ 16 bit counter FF L o TO Figure 10 4 12 PWM Circuit Diagram If you want to rewrite reload 0 and reload 1 registers while the timer is operating rewrite reload 1 register first and then reload 0 register In this way reload 0 and reload 1 registers both are updated synchronously with PWM periods from which the timer starts operating again This operation can normally be performed collectively by accessing register addresses wordwise in 32 bits beginning with that of reload 1 register Data are automatically written to reload 1 and then reload 0 registers in succession If you update the reload registers in reverse by updating reload 0 register first and then reload 1 register only reload 0 register is updated when you read reload 0 and reload 1 registers the values you get are always the data written to the registers and not the reload values being actually used Note that when updating the PWM period if the PWM period is terminated before you finished writing to reload 0 the PWM period is not updated in the current period and what you ve set is reflected in the next period 10 114 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer When reload register updates take effect in the current period reflected in the next period Write to reload 0 Write to reload 1 reload 1 data latc
281. Operation in CSIO Mode 12 4 2 Starting CSIO Reception When all of the following receive conditions are met after you finished initialization the serial I O starts receive operation 1 Receive conditions when CSIO mode internal clock is selected The SIO Receive Control Register s receive enable bit is set to 1 Transmit conditions are met Refer to Section 12 3 3 Starting CSIO Transmission 2 Receive conditions when CSIO mode external clock is selected The SIO Receive Control Register s receive enable bit is set to 1 Transmit conditions are met Refer to Section 12 3 3 Starting CSIO Transmission Note The receive status bit is set to 1 at the time dummy data is set in the lower byte of the SIO Transmit Buffer Register When the above conditions are met the serial I O starts receiving 8 bit serial data LSB first synchronously with the receive shift clock 12 4 3 Processing at End of CSIO Reception When data reception is completed the following operation is automatically performed in hardware 1 When reception is completed normally The receive finished receive buffer full bit is set to 1 Note 1 If a receive finished receive buffer full interrupt has been enabled an interrupt request is generated Note 2 A DMA transfer request is generated 2 When error occurs during reception When an error only overrun error in CSIO mode occurs during reception the overrun error bit and receive sum
282. Otherwise Noted M aii peripheral During double 173 clock Speed mode Note 3 Analog Input Leakage Current Note 2 200 Note 1 The nonlinearity error refers to a deviation from ideal conversion characteristics after the offset full scale errors have been adjusted to 0 When AVCC VREF 5 12 V 1 LSB 5 mV Note 2 This refers to input leakage current on ANO AN15 when the A D converter remains idle Input voltage condition 0 lt AVCC Temperature condition 40 to 85 C Note 3 One cycle of the internal peripheral clock is 50 ns Conversion Characteristics Referenced to AVCC VREF VCCE 5 12 V Ta 25 f XIN 8 0 MHz Unless Otherwise Noted T F Duri al Numb peripheral During double 173 clock Speed mode Note 3 Analog Input Leakage Current Note 2 Note 1 The nonlinearity error refers to a deviation from ideal conversion characteristics after the offset full scale errors have been adjusted to 0 When AVCC VREF 5 12 V 1 LSB 5 mV Note 2 This refers to input leakage current on ANO AN15 when the converter remains idle Input voltage condition 0 lt ANi AVCC Temperature condition 40 to 125 C Note 3 One cycle of the internal peripheral clock is 62 5 ns 21 11 Ver 0 10 21 ELECTRICAL CHARACTERISTICS 21 5 AC Characteristics 21 5 AC Characteristics 21 5 1 Timing Re
283. Output Mode without Correction Function 10 116 10 4 13 Operation in TIO Delayed Single shot Output Mode without Correction Function 10 118 10 4 14 Operation in TIO Continuous Output Mode Without Correction Function 10 120 10 5 TMS Input related 16 bit Timer nnnnnnnnnnnn nnna 10 122 10 51 Outline OF 10 122 10 5 2 Outline of TMS Operation 10 122 10 5 3 TMS Related Register 10 124 10 5 4 TMS Control Registers 0 0008 10 125 10 5 5 TMS Counter TMSOCT TMS1CT 10 127 10 5 6 TMS Measure Registers TMSOMR3 0 TMS1MR3 0 10 128 10 5 7 Operation of TMS Measure Input 10 129 10 6 TML Input related 32 bit Timer 2 eere 10 131 10 6 1 Outline of 10 131 10 6 2 Outline of TML Operation 10 132 10 6 3 TML Related Register Map 10 133 10 6 4 TML Control 48 10 134 10 6 5 TML Counters 222004 40 00 10 136 10 6 6 TML Measure Registers 10 138 10 6 7 Operation of TML Measure 10 140 CHAPTER 11
284. P116 inout bit P117 inout bit P100 inout bit P101 sinout bit P102 sinout bit VDD_108 linkage bit TMS bit TCK bit TRST bit TDO out bit TDI bit P103 inout bit P104 sinout bit P105 inout bit P106 inout bit P107 sinout bit P124 sinout bit P125 inout bit P126 sinout bit P127 sinout bit VCCI_123 linkage bit P130 inout bit P131 inout bit P132 inout bit P133 inout bit P134 inout bit P135 inout bit P136 inout bit P137 inout bit VCCE_132 linkage bit P150 inout bit P153 inout bit P41 inout bit P42 inout bit VCCI_137 linkage bit VSS_ 138 linkage bit P43 inout bit P44 inout bit P45 inout bit P46 inout bit Figure 19 5 3 BSDL Description for the 32171 3 14 19 17 Ver 0 10 19 JTAG 19 5 Boundary Scan Description Language P47 inout bit P220 inout bit use STD 1149 1 1994 all attribute COMPONENT CONFORMANCE of M32171F4VFP entity is STD 1149 1 1993 attribute MAP of M32171F4VFP entity is PHYSICAL MAP constant P6Q144 PIN MAP STRING P221 1 225 2 amp OSCVSS 3 3 amp XIN 4 amp XOUT 5 amp OSCVCC 6 6 amp VONT 7 7 P30 8 amp P31 9 amp P32 10 amp P33 11 amp P34 12 amp P35 113 amp P36 14 amp P37 15 amp P20 16 amp P21 17 amp P22 18
285. P175 port 17 P220 P221 Input output nput output Programmable input output port P225 Note2 port 22 However P221 is an input only port Note 1 For the 32171 input output ports 14 16 18 19 20 and 21 are nonexistent Note 2 Use caution when using P225 because they have a debug event function 1 15 Ver 0 10 1 OVERVIEW 1 4 Pin Layout 1 4 Pin Layout Figure 1 4 1 shows pin assignments on the M32171FxVFP Table 1 4 1 lists the pin assignments 39 73 HACK 74 Pey 5 VDD lt gt P102 TO10 lt gt P101 TO9 lt gt P100 TO8 lt gt 117 707 lt gt 97 020 4 9 po6 TO19 gt P95 TO18 lt gt Po4TO17 gt 93 016 4 9 P77 RTDCLK 4 95 76 4 9 P75 RTDRXD lt gt P74RTDTXD 4 9 P72 HREQ 71 WAIT 4 gt P70 BCLK WR FVCC 746 RESET 4 Pe 4 2 4 p61 Or 105 104 91 90 89 87 86 5 84 83 82 1 80 79 78 TE 76 75 74 1 1 7 1106 JTMS vss JTCK P87 SCLKI1 SCLKO1 JTRST P86 RXD1 JTDO P85 TXD1 JTDI P84 SCLKIO SCLKOO P103 TO11 P83 RXDO P104 TO12 P82 TXDO P105 TO13 VCCE 106 014 P175 RXD2 P107 TO15 P174 TXD2 P124 TCLKO vss P125 TCLK1 VCCI P126 TCLK2 AVSSO P127 TCLK3 59 4 ADOIN15 M32171FxVFP 58 4 amp ADOIN14 P130 TIN16 57 4 ADOIN13 P131 TIN17 56
286. P7 H 0000 005C Indeterminate 0 PC of TRAP instruction 4 TRAP8 H 0000 0060 Indeterminate 0 of TRAP instruction 4 TRAP9 H 0000 0064 Indeterminate 0 of TRAP instruction 4 TRAP10 H 0000 0068 Indeterminate 0 PC of TRAP instruction 4 TRAP11 H 0000 006C Indeterminate 0 PC of TRAP instruction 4 TRAP12 H 0000 0070 Indeterminate 0 PC of TRAP instruction 4 TRAP13 H 0000 0074 Indeterminate 0 of TRAP instruction 4 TRAP14 H 0000 0078 Indeterminate 0 PC of TRAP instruction 4 TRAP15 H 0000 007C Indeterminate 0 PC of TRAP instruction 4 External Interrupt El H 0000 0080 Note 2 0 0 PC of the next instruction Note 1 During boot mode this vector address is moved to the beginning of the boot ROM address H 8000 0000 For details refer to Section 6 5 Programming of Internal Flash Memory Note 2 During flash E W enable mode this vector address is moved to the beginning of the internal RAM address H 0080 4000 For details refer to Section 6 5 Programming of Internal Flash Memory 4 10 Ver 0 10 4 EIT 4 8 Exception Processing 4 8 Exception Processing 4 8 14 Reserved Instruction Exception RIE Occurrence Conditions Reserved Instruction Exception RIE is generated when execution of a reserved instruction unimplemented instruction is detected Instruction check is performed on the op code part of the instruction When a reserved instruction exception occurs the instruction which generated it is not execute
287. Port Peripheral Circuits P84 SCLKIO SCLKOO P87 SCLKH SCLKO1 Direction register 1 pd fe Databus _ 4 Port output R DBO DB15 latch gt 21 Operation mode register 4 UART CSIO function select bit Dy rore ccc gt H clock select bit SCLKOi output SCLKII input lt LG Input function enable MODO MODO MOD1 x O MOD1 RESET RESET lt 7 Note denotes pins Figure 8 4 4 Port Peripheral Circuit Diagram 4 8 25 Ver 0 10 INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 4 Port Peripheral Circuits This is a blank page 8 26 Ver 0 10 CHAPTER 9 DMAC 9 1 Outline of the DMAC 9 2 DMAC Related Registers 9 3 Functional Description of the DMAC 9 4 Precautions about the DMAC DMAC 9 1 Outline of the DMAC 9 1 Outline of the DMAC The 32171 contains a 10 channel DMA Direct Memory Access Controller It allows you to transfer data at high speed between internal peripheral I Os between internal RAM and internal peripheral I O and between internal RAMs as requested by a software trigger or from an internal peripheral I O Table 9 1 1 Outline of the DMAC Item Number of channel Description 10
288. RAP13 TRAP14 TRAP15 External Interrupt Note Note When flash entry bit 1 i e flash enable mode the El vector entry is at H 0080 4000 Figure 3 5 1 EIT Vector Entry 3 22 Ver 0 10 3 ADDRESS SPACE 3 6 ICU Vector Table 3 6 ICU Vector Table The ICU vector table is used by the internal interrupt controller The start addresses of interrupt handlers for the interrupt requests from respective internal peripheral I Os are set at the ad dresses shown below For details refer to Chapter 5 Interrupt Controller The 32171 s ICU vector table is shown in Figures 3 6 1 and 3 6 2 Address H 0000 0094 H 0000 0096 H 0000 0098 H 0000 009A H 0000 009C H 0000 009E H 0000 00A0 H 0000 00A2 H 0000 00A4 H 0000 00A6 H 0000 00A8 H 0000 00AA H 0000 00AC H 0000 00AE H 0000 00BO H 0000 00B2 H 0000 00B4 H 0000 00B6 H 0000 00B8 H 0000 00BA H 0000 00BC H 0000 00 H 0000 00CO H 0000 00C2 H 0000 00C4 H 0000 00C6 0 Address 1 Address D15 T Input Interrupt 4 Handler Start Address 0 15 MJ MJ M JT MJT MJT T nput nput nput nput nput nput nterrupt 4 Hand nterrupt 3 Hand nterrupt 3 Hand nterrupt 2 Hand nterrupt 2 Hand nterrupt 1 Hand er Start Address A16 A31 er Start Address A0 A15 er Start Address A16 A31 er Start Address A0 A15 er Start Address A16 A31 er Start Add
289. RT Transmission Successive Transmission with Transmit Interrupt Used 12 51 Ver 0 10 1 2 SERIAL I O 12 7 Receive Operation in UART Mode 12 7 Receive Operation in UART Mode 12 7 1 Initial Settings for UART Reception To receive data in UART mode initialize the serial following the procedure described below 1 Setting SIO Transmit Receive Mode Register Set the register to UART mode Set parity when enabled select odd even Set stop bit length Set character length Note During UART mode settings of the internal external clock select bit have no effect only the internal clock is useful 2 Setting SIO Transmit Control Register Select the clock divider s divide by ratio 3 Setting SIO Baud Rate Register Set a baud rate generator value Refer to Section 12 6 1 Setting the UART Baud Rate 4 Setting SIO interrupt related registers Cause of Receive Interrupt Select Register Select the cause of receive interrupt receive finished receive error Interrupt Mask Register Enable disable receive interrupts 5 Setting the Interrupt Controller When you use interrupts during reception set its priority level 6 Setting DMAC When you issue DMA transfer requests to the internal DMAC when reception is completed set the DMAC Refer to Chapter 9 DMAC 7 Selecting pin functions Because the serial I O related pins serve dual purposes shared with input output ports set pin functions
290. Register TMS1MR3 H 0080 03D4 TMS1 Measure 2 Register TMS1MR2 H 0080 03D6 TMS1 Measure 1 Register TMS1MR1 H 0080 03D8 TMS1 Measure 0 Register 51 0 H 0080 03 0 TMLO Counter High TMLOCTH H 0080 03 2 TMLO Counter Low TMLOCTL H 0080 03EA TMLO Control Register TMLOCR H 0080 03 0 TMLO Measure 3 Register High TMLOMR3H H 0080 03 2 TMLO Measure Register Low TMLOMR3L H 0080 O3F4 TMLO Measure 2 Register High TMLOMR2H H 0080 03 6 TMLO Measure 2 Register Low TMLOMR2L H 0080 O3F8 TMLO Measure 1 Register High TMLOMR1H H 0080 TMLO Measure 1 Register Low TMLOMR1L H 0080 TMLO Measure 0 Register High TMLOMROH H 0080 03 TMLO Measure 0 Register Low TMLOMROL H 0080 0400 DMAO 4 Interrupt Request Status Register DMOAITST DMAO 4 Interrupt Mask Register DMO4ITMK H 0080 0408 DMA65 9 Interrupt Request Status Register DM59ITST DMAS 9 Interrupt Mask Register DM59ITMK H 0080 0410 DMAO Channel Control Register DMOCNT DMAO Transfer Count Register DMOTCT H 0080 0412 DMAO Source Address Register DMOSA H 0080 0414 DMAO Destination Address Register DMODA H 0080 0416 H 0080 0418 DMAS Channel Control Register DM5CNT DMAS Transfer Count Register DM5TCT H 0080 041A DMAS Source Address Register DM5SA H 0080 041C DMAS Destination Address Register DM5DA H 0080 041E
291. Register 2 ERESE Auto Erase operating condition WRERR1 Program operating condition 1 and WRERR2 Program operating condition 2 bits to check for program error Figure 6 5 11 Lock Bit Program 6 34 Ver 0 10 INTERNAL MEMORY 6 5 Programming of the Internal Flash Memory E START Write Erase command H 2020 to any address of internal flash memory Write Verify command H DODO to the last even address of the block you want to erase Flash memory contents erased by Erase program Note 1 1 us wait by hardware timer or software timer Read any address of internal flash memory to check for erase error Note 2 Note 1 When Erase operation starts you have the Read Status Register command automatically entered You do not need to enter the Read Status Register command until you issue another command Note 2 Examine the Flash Status Register 2 ERESE Auto Erase operating condition WRERR1 Program operating condition 1 and WRERR2 Program operating condition 2 bits to check for erase error Forcibly terminated Figure 6 5 12 Block Erase 6 35 Ver 0 10 INTERNAL MEMORY 6 5 Programming of the Internal Flash Memory START Write Erase Unlock Block command H A7A7 to any address of internal flash memory Write Verify command H DODO to address in memory blocks you wa
292. Register 6 ADODT6 10 bit A DO Data Register 7 ADODT7 10 bit Data Register 8 ADODT8 10 bit A DO Data Register 9 ADODT9 10 bit A DO Data Register 10 ADODT10 10 bit A DO Data Register 11 ADODT11 10 bit A DO Data Register 12 ADODT12 10 bit A DO Data Register 13 ADODT13 0080 00AC H 0080 10 bit A DO Data Register 14 ADODT14 10 bit A DO Data Register 15 ADODT15 8 bit A DO Data Register 0 ADO8DTO Blank addresses are reserved areas Figure 3 4 3 Register Mapping of the SFR Area 1 3 10 Ver 0 10 3 ADDRESS SPACE 3 4 Internal ROM SFR Area Address 0 Address 1 Address DO H 0080 0000 Interrupt Vector Register IVECT H 0080 0002 H 0080 0004 Interrupt Mask Register IMASK H 0080 0006 SBI Control Register SBICR H 0080 0060 CANO Transmit Receive amp Error Interrupt Control Register ICANOCR H 0080 0062 H 0080 0064 H 0080 0066 RTD Interrupt Control Register IRTDCR H 0080 0068 5102 3 Transmit Receive Interrupt Control Register ISO23CR DMAS 9 Interrupt Control Register IDMAS9CR H 0080 006A H 0080 006C A DO Conversion Interrupt Control Register IADOCCR SIOO Transmit Interrupt Control Register ISIOOTXCR H 0080 006 5100 Receive Interrupt Control Register ISIOORXCR SIO1 Transmit Interrupt Control Register ISIO1TXCR H 0080 0070 SIO1 Receive Interrupt Control Register ISIO1RXCR D
293. SB 31 LSB PC PC 0 2 6 Ver 0 10 2 CPU 2 6 Data Formats 2 6 Data Formats 2 6 1 Data Types There are several data types that can be handled by the M32R s instruction set These include signed and unsigned 8 16 and 32 bit integers Values of signed integers are represented by 2 s complements Signed byte 8 bit integer Unsigned byte 8 bit integer Signed halfword 16 a integer Unsigned halfword 16 bit integer 0 5 31 LSB integer 0 5 31 LSB integer S Sign bit Figure 2 6 1 Data Types 2 7 Ver 0 10 2 CPU 2 6 Data Formats 2 6 2 Data Formats 1 Data formats in register Data sizes in M32R registers are always words 32 bits When loading byte 8 bit or halfword 16 bit data from memory into a register the data is sign extended LDB LDH instructions or zero extended LDUB LDUH instructions into word 32 bit data before being stored in the register When storing data from M32R register into memory the register data is stored in memory in different sizes depending on the instructions used The ST instruction stores the entire 32 bit data of the register the STH instruction stores the least significant 16 bit data and the STB instruction stores the least significant 8 bit data From memory LDB Sign extended LDB instruction or LDUB instructions O MSB zero extended LDUB instruction n 31 LSB lt When loading gt Rn Byte Sign extend
294. SERIAL I O 12 4 Receive Operation in CSIO Mode 12 4 Receive Operation in CSIO Mode 12 4 1 Initial Settings for CSIO Reception To receive data in CSIO mode initialize the serial I O following the procedure described below Note however that because the receive shift clock is derived from operation of the transmit circuit you need to execute transmit operation even when you only want to receive data 1 Setting SIO Transmit Receive Mode Register Set the register to CSIO mode Select the internal or an external clock 2 Setting SIO Transmit Control Register Select the clock divider s divide by ratio when internal clock selected 3 Setting SIO Baud Rate Register When the internal clock is selected set a baud rate generator value Refer to Section 12 3 1 Setting the CSIO Baud Rate 4 Setting SIO Interrupt Mask Register Enable or disable the transmit buffer empty interrupt SIO Interrupt Mask Register Select the cause of receive interrupt receive finished error Cause of Receive Interrupt Select Register 5 Setting SIO Receive Control Register Set the receive enable bit 6 Setting the Interrupt Controller SIO Transmit Interrupt Control Register When you use a transmit interrupt or receive interrupt during transmission reception set its priority level 7 Setting the DMAC When you generate a DMA transfer request to the internal DMAC when the transmit buffer is empty or transmission is completed set the
295. SK and 6 IMASK H 0080 0004 save it to stack Interrupt generated v pru Read Interrupt Vector Register lt IVECT H 0080 0000 ICU vector 4 Read ICU vector table lt table gc i ae ole Address H 9000 0094 PSW register IE bit 1 Note B i H 0000 010F 6 Branch to interrupt handler CN for each internal peripheral I O J 2 AA Interrupt Interrupt 7 handler handler MN ed Y Y Q Psw register IE bit 0 y 9 Restore Interrupt Mask Register IMASK Y Restore general purpose register 10 His PSW 1 40 Processing of El by interrupt handler Y Restore BPC 6 When enabling multiple MR interrupts x CA Note For operations performed when accepting EIT and returning from handlers also refer to Section 4 3 EIT Processing Procedure Figure 5 5 2 Typical Operation for Interrupts from Internal Peripheral 1 5 20 Ver 0 10 5 INTERRUPT CONTROLLER ICU 5 6 Description of System Break Interrupt SBI Operation 5 6 Description of System Break Interrupt SBI Operation 5 6 1 Acceptance of SBI System Break Interrupt SBI is an emergency interrupt which is used when power failure is detected or a fault condition is notified by an external watchdog timer The system break interrupt is accepted anytime upon detection of a falling edge on the SBI signal regardless of how the PSW register IE bit is set and cannot be masked 5
296. SL6EID2 CANO Message Slot 6 Extended ID1 COMSL6EID1 CANO Message Slot 6 Data Length Register COMSL6DLC CANO Message Slot 6 Data 0 COMSL6DTO CANO Message Slot 6 Data 2 COMSL6DT2 CANO Message Slot 6 Data 1 COMSL6DT1 CANO Message Slot 6 Data COMSL6DT3 CANO Message Slot 6 Data 4 COMSL6DT4 CANO Message Slot 6 Data 6 COMSL6DT6 CANO Message Slot 6 Data 5 COMSL6DT5 CANO Message Slot 6 Data 7 COMSL6DT7 CANO Message Slot 7 Standard 100 COMSL7SIDO CANO Message Slot 6 Time Stamp COMSL6TSP CANO Message Slot 7 Standard 101 COMSL7SID1 CANO Message Slot 7 Extended 100 COMSL7EIDO CANO Message Slot 7 Extended ID1 COMSL7EID1 CANO Message Slot 7 Extended ID2 COMSL7EID2 CANO Message Slot 7 Data Length Register COMSL7DLC CANO Message Slot 7 Data 0 COMSL7DTO CANO Message Slot 7 Data 1 COMSL7DT1 CANO Message Slot 7 Data 2 COMSL7DT2 CANO Message Slot 7 Data 3 COMSL7DT3 CANO Message Slot 7 Data 4 COMSL7DT4 CANO Message Slot 7 Data 5 COMSL7DT5 CANO Message Slot 7 Data 6 COMSL7DT6 CANO Message Slot 7 Data 7 COMSL7DT7 CANO Message Slot 7 Time Stamp COMSL7TSP CANO Message Slot 8 Standard IDO COMSL8SIDO CANO Message Slot 8 Standard ID1 COMSL8SID1 CANO Message Slot 8 Extended IDO COMSL8EIDO CANO Message Slot 8 Extended 102 COMSL8EID2 CANO Message Slot 8 Extended ID1 COMSL8 CANO Message Slot 8 Data Length Register C
297. Slot 6 Control Register COMSL6CNT CANO Message Slot 7 Control Register COMSL7CNT H 0080 1058 CANO Message Slot 8 Control Register COMSL8CNT CANO Message Slot 9 Control Register COMSL9CNT H 0080 105A CANO Message Slot 10 Control Register COMSL10CNT CANO Message Slot 11 Control Register COMSL11CNT H 0080 105C CANO Message Slot 12 Control Register COMSL12CNT CANO Message Slot 13 Control Register COMSL13CNT H 0080 105E Message Slot 14 Control Register COMSL14CNT CANO Message Slot 15 Control Register COMSL15CNT Blank addresses are reserved Figure 13 2 1 CAN Module Related Register Map 1 4 13 4 Ver 0 10 13 CAN MODULE 13 2 CAN Module Related Registers H 0080 1100 H 0080 1102 H 0080 1104 H 0080 1106 H 0080 1108 H 0080 110A H 0080 110C H 0080 110 H 0080 1110 H 0080 1112 H 0080 1114 H 0080 1116 H 0080 1118 H 0080 111A H 0080 111C H 0080 111E H 0080 1120 H 0080 1122 H 0080 1124 H 0080 1126 H 0080 1128 H 0080 112A H 0080 112C H 0080 112 H 0080 1130 H 0080 1132 H 0080 1134 H 0080 1136 H 0080 1138 H 0080 113A H 0080 113C H 0080 113E H 0080 1140 H 0080 1142 H 0080 1144 H 0080 1146 H 0080 1148 H 0080 114A H 0080 114C H 0080 114E H 0080 1150 H 0080 1152 Address 0 Address CANO Message Slot 0 Standard IDO COMSLOSIDO 1 Address D7 D8 D15 CANO Message Slot 0 Standard ID1 COMSLOSID1 CANO Message Slot 0 Extended IDO COMSLOEIDO C
298. Slot 9 Data 3 COMSL9DT3 CANO Message Slot 9 Data 5 COMSL9DT5 CANO Message Slot 9 Data 6 COMSL9DT6 CANO Message Slot 9 Data 7 COMSL9DT7 CANO Message Slot 9 Ti me Stamp COMSL9TSP CANO Message Slot 10 Standard IDO COMSL10SIDO CANO Message Slot 10 Standard ID1 COMSL10SID1 CANO Message Slot 10 Extended IDO COMSL10EIDO CANO Message Slot 10 Extended 102 COMSL10EID2 CANO Message Slot 10 Extended 101 COMSL10EID1 CANO Message Slot 10 Data Length Register COMSL10DLC CANO Message Slot 10 Data 0 COMSL10DTO Blank addresses are reserved CANO Message Slot 10 Data 1 COMSL10DT1 Figure 13 2 3 CAN Module Related Register Map 3 4 13 6 Ver 0 10 13 CAN MODULE 13 2 CAN Module Related Registers Address 0 Address H 0080 11A8 CANO Message Slot 10 Data 2 COMSL10DT2 1 Address CANO Message Slot 10 Data 3 COMSL10DT3 H 0080 11AA CANO Message Slot 10 Data 4 COMSL10DT4 H 0080 11AC CANO Message Slot 10 Data 6 COMSL10DT6 CANO Message Slot 10 Data 5 COMSL10DT5 CANO Message Slot 10 Data 7 COMSL10DT7 H 0080 11 CANO Message Slot 10 Time Stamp COMSL10TSP H 0080 11B0 CANO Message Slot 11 Standard IDO COMSL11SIDO CANO Message Slot 11 Standard 101 COMSL11SID1 H 0080 11 2 CANO Message Slot 11 Extended IDO COMSL11EIDO CANO Message Slot 11 Extended ID1 COMSL11EID1 H 0080 11B4 CANO Message Slot 11 Extended ID2 COMSL11
299. Start address of bank in S bank address SBANKAD bit set value S bank 0 H 0000 0000 H 00 NOTE S bank 1 0000 1000 H 01 S bank 2 H 0000 2000 H 02 1 5 126 H 0007 E000 S bank 127 H 0007 F000 Note Set the eight bits A12 A19 of the start address 32 bit of each S bank of flash memory divided every 4 Kbytes in the Virtual Flash S Bank Register s S bank address SBANKAD bits Figure 6 7 7 Values Set in the M32171F4 s Virtual Flash Bank Register when Divided in Units of 4 Kbytes 6 44 Ver 0 10 INTERNAL MEMORY 6 7 Virtual Flash Emulation Function Start address of bank in flash memory L bank address LBANKAD bit set value L bank 0 H 0000 0000 H 00 NOTE L bank 1 H 0000 2000 H 02 L bank 2 H 0000 4000 H 04 L bank 46 H 0005 C000 L bank 47 H 0005 E000 H 5E Note Set the seven bits A12 A18 of the start address 32 bit of each L bank of flash memory divided every 8 Kbytes in the Virtual Flash L Bank Register s L bank address LBANKAD bits Figure 6 7 8 Values Set in the M32171F3 s Virtual Flash Bank Register when Divided in Units of 8 Kbytes Start address of bank in flash memory S bank address SBANKAD bit set value S bank 0 H 0000 0000 H 00 NOTE S bank 1 H 0000 1000 H 01 S bank 2 H
300. T FP MODO 1 JTMS JTRST JTDI Hysteresis Note 4 VT VT Note 1 Total current when VCCE AVCC VREF in single chip mode See the next page for the rated values of power supply current on each power supply pin Note 2 Total current when VCCI VDD FVCC OSC VCC in single chip mode See the next page for the rated values of power supply current on each power supply pin Note 3 All these pins except RESET serve dual functions Note 4 The HREQ pin serves dual functions 21 5 Ver 0 10 21 2 Electrical characteristics of each power supply when 10 MHz ELECTRICAL CHARACTERISTICS 21 3 DC Characteristics Referenced to VCCE 5 V 0 5V VCCI 3 3 V 0 3 V Ta 40 to 85 Unless Otherwise Noted ICCE ICCI IOSCVCC FICC IDD IAVCC Parameter VCCE power supply current when operating VCCI power supply current when operating OSCVCC power supply current when operating FVCC power supply current when operating Note 1 VDD power supply current when operating Note 2 AVCC power supply current when operating 10 IVREF VREF power supply current f XIN 210 0MHz Note 1 Maximum value including currents during program erase operation Note 2 Maximum value including cases where the program is executed in RAM 21 6 Ver 0 10 21 ELECTRICAL CHARACTERISTICS 21 3 DC Characteristics 3 Electrical characteristics when f XIN 8 MHz Referenced to VCC
301. TAG Instruction List Instruction Code Abbreviation Operation b 000000 EXTEST Tests circuit board level connections outside the chip b 000001 SAMPLE PRELOAD Samples operating circuit status and outputs the sampled status from JTDO pin while at the same time entering the data used for boundary scan test from the JTDI pin and presets it in Boundary Scan Register b 000010 IDCODE Selects ID Code Register and outputs device and manufacturer identification data from JTDO pin b 111111 BYPASS Selects Bypass Register and inspects or sets data Note 1 Do not set any other instruction code Note 2 For details about IR path sequence DR path sequence Test reset Capture IR state Shift IR state Exit1 IR state and Update IR state refer to Section 19 4 19 4 Ver 0 10 1 9 JTAG 19 3 JTAG Registers 19 3 2 Data Registers 1 Boundary Scan Register JTAGBSR The Boundary Scan Register is a 471 bit register used to perform boundary scan test Bits in this register are assigned to each pin on the 32171 Connected between the JTDI and JTDO pins this register is selected when issuing EXTEST or SAMPLE PRELOAD instruction In Capture DR state this register captures the status of input pins or internal logic output values In Shift DR state while outputting the sampled value it is used to set pin functions input output pin and tristate output pin direction and output values by entering data for boundary scan
302. TIO5 9 Clock Enable Inputs 10 95 Ver 0 10 10 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer E TIO5 Control Register TIO5CR D8 9 10 11 lt Address H 0080 034 gt 12 13 14 D15 TIO5CKS TIOSENS 5 When reset H 00 gt D Bit Name Function R 8 10 TIO5CKS External input TCLK1 TIO5 clock source selection 100 Clock bus 0 101 Clock bus 1 110 Clock bus 2 111 Clock bus 3 11 12 5 OX No selection Q 5 enable measure 10 No selection input source selection 11 Input event bus 3 13 15 TIO5M 000 Single shot output mode Q 5 operation mode selection 001 Delayed single shot output mode 010 Continuous output mode 011 PWM output mode 100 Measure clear input mode 101 Measure free run input mode 11X Noise processing input mode Note Always make sure the counter has stopped and is idle before setting or changing operation modes 10 96 Ver 0 10 1 0 MULTIJUNCTION 5 10 4 TIO Input Output related 16 bit Timer TIO6 Control Register TIOGCR Address H 0080 036A DO 1 2 3 4 5 6 D7 6 5 TIOGENS TIO6M When reset H 00 gt D Bit Name Function R 0 2 TIO6CKS External input TCLK2 TIO6 clock source selection 100 Clock bus 0 101 Clock bus 1 110 Clock bus 2 111 Clock bus 3 3 4 TIOGENS 00 No selec
303. This bit is cleared to 0 when transmit is idle no data in the Transmit Shift Register and no data exists in the Transmit Buffer Register This bit also is cleared by clearing the transmit enable bit 3 TBE transmit buffer empty bit D6 Set condition This bit is set to 1 when data is transferred from the Transmit Buffer Register to the Transmit Shift Register and the Transmit Buffer Register becomes empty This bit also is set by clearing the transmit enable bit Clear condition This bit is cleared to 0 by writing data to the lower byte of the Transmit Buffer Register when transmit is enabled TEN 1 4 TEN transmit enable bit 07 Transmit is enabled by setting this bit to 1 and disabled by clearing this bit to O If this bit is cleared to 0 while transmitting data the transmit operation stops 12 14 Ver 0 10 1 2 SERIAL I O 12 2 Serial Related Registers 12 2 4 SIO Transmit Receive Mode Registers 5100 Mode Register SOMOD lt Address H 0080 0111 gt E SIO1 Mode Register S1MOD Address H 0080 0121 E SIO2 Mode Register S2MOD Address H 0080 0131 D8 9 10 11 12 13 14 D15 SMOD CKS STB PSEL PEN SEN When reset 00 gt D Bit Name Function R 8 10 SMOD 000 7 bit UART Serial I O mode select bit 001 8 bit UART Note 1 01X 9 bit UART 1XX 8 bit clock synchronized serial I O 11 CKS 0 Internal clock Internal exte
304. Tq Q Q 01 SJW 2Tq 10 SJW 3 4 11 SJW 4Tq 2 4 PH2 Sets Phase Segment2 Phase Segment2 000 Settings inhibited O O 001 Phase Segment2 2Tq 010 Phase Segment2 3Tq 011 Phase Segment2 4 100 Phase Segment2 5Tq 101 Phase Segment2 6Tq 110 Phase Segment2 7Tq 111 Phase Segment2 8Tq 5 7 PH1 Sets Phase Segment1 Phase Segmenti 000 Phase Segmenti 1Tq O O 001 Phase Segmenti 2Tq 010 Phase Segmenti 3Tq 011 Phase Segmenti 4Tq 100 Phase Segmenti 5Tq 101 Phase Segmenti 6Tq 110 Phase Segmenti 7Tq 111 Phase Segmenti 8Tq 13 16 Ver 0 10 13 CAN MODULE 13 2 CAN Module Related Registers D Bit Name 8 10 PRB Propagation Segment When reset H 0000 gt Function R Sets Propagation Segment 000 Propagation Seqment 1Tq O 001 Propagation Seqment 2Tq 010 Propagation Seqment 3Tq 011 Propagation Seqment 4Tq 100 Propagation Seqment 5Tq 101 Propagation Seqment 6Tq 110 Propagation Seqment 7Tq 111 Propagation Seqment 8Tq 11 SAM Number of times sampled 0 Samples once O O 1 Samples three times 12 15 functions assigned 13 17 Ver 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers 1 SJW bits DO D1 These bits set reSynchronization Jump Width 2 PH2 bits D2 D4 These bits set the width of Phase Segment2 Note The internal CAN module of the M32R E has IPT Information Processing Time 2 Because
305. UNCTION TIMERS 10 5 TMS Input related 16 bit Timer Bi TMS1 Control Register TMS1CR Address H 0080 03CB gt D8 9 10 11 12 13 14 D15 TMS1 TMS1 TMS1 TMS1 sso 851 5852 5853 TMS1CKS TMS1CEN When reset H 00 gt D Bit Name Function R 8 51550 0 External input TIN19 TMS1measure 0 source selection 1 Input event bus 0 9 TMS1SS1 0 External input TIN18 TMS1 measure 1 source selection 1 Input event bus 1 10 TMS1SS2 0 External input TIN17 Q TMS1 measure 2 source selection 1 Input event bus 2 11 TMS1SS3 0 External input TIN16 TMS1 measure 3 source selection 1 Input event bus 3 12 No functions assigned 0 13 TMS1CKS 0 Clock bus 0 O 81 clock source selection 1 Clock bus 3 14 No functions assigned 0 15 TMS1CEN 0 Count stops O O TMS1 count enable 1 Count starts 10 126 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 5 TMS Input related 16 bit Timer 10 5 5 TMS Counter TMSOCT TMS1CT TMSO Counter TMSOCT Address H 0080 03 0 gt E TMS1 Counter TMS1CT Address H 0080 03D0 gt DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 TMSOCT TMS1CT When reset Indeterminate gt D Bit Name Function R 0 15 50 51 16 bit counter value Note This register must always be accessed halfwords The TMS counters are a 16 bit up counter which starts counting when the timer is enabled by wr
306. W field and the general purpose registers to be used in the EIT handler are saved to the stack by the EIT handler you write Remember that these registers must be saved to the stack in a program by the user When processing by the EIT handler is completed restore the saved registers from the stack and finally execute the RTE instruction Control is thereby returned from EIT processing to the program that was being executed when the EIT occurred This does not apply to the System Break Interrupt however In the M32R E s hardware postprocessing the contents of the backup registers BPC register and the BPSW field of the PSW register are moved back to the PC and PSW registers 4 5 Ver 0 10 4 EIT 4 4 EIT Processing Mechanism 4 4 EIT Processing Mechanism The MS2R E s EIT processing mechanism consists of the M32R CPU core and the interrupt controller for internal peripheral I Os It also has the backup registers for the PC and PSW BPC register and the BPSW field of the PSW register The M32R E s internal EIT processing mechanism is shown below M32R E M32R CPU core RI M Internal peripheral o gt Interrupt controller ICU AE RIE TRAP register BPsw PSW PSW register Priority Figure 4 4 1 The M32R E s EIT Processing Mechanism 4 6 Ver 0 10 4 EIT
307. WAIT CONTROLLER 16 3 Typical Operation of the Wait Controller 16 3 Typical Operation of the Wait Controller The following shows a typical operation of the wait controller The wait controller can control bus access in the range of 2 to 5 cycles If more access cycles than that are needed use the WAIT function in combination with the wait controller 1 When Bus Mode Control Register 0 External read write operations are performed using the address bus data bus and signals 50 CS1 RD BHW BLW WAIT and BCLK Bus free state internal bus access f lt lt _ 1 BCLK A12 A30 X7 7 CS0 CS1 RD H BHW BLW E UM o DBO 0815 WAIT Note THi Z denotes a high impedance state Figure 16 3 1 Internal Bus Access during Bus Free State 16 6 Ver 0 10 WAIT CONTROLLER 16 3 Typical Operation of the Wait Controller 16 Read 2 cycles Read 4 soek Gb Oo edes ibs isi da ca Lieu D ots MM gt o 5 o e Y sepe 4 gt T A 0 I 4 a a cs gen tap o 919 m E o z x O I Ao gt og
308. When reset Indeterminate gt Function R Message slot n data 6 O O These registers are the transmit frame receive frame memory space Note For receive slots if when storing a data frame the data length DLC value 6 an indeterminate value is written to this register 13 50 Ver 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers CANO Message Slot 0 Data 7 COMSLODT7 Address H 0080 110D gt CANO Message Slot 1 Data 7 COMSL1DT7 Address H 0080 111D gt CANO Message Slot 2 Data 7 COMSL2DT7 Address H 0080 112D gt CANO Message Slot 3 Data 7 COMSL3DT7 Address H 0080 113D gt CANO Message Slot 4 Data 7 COMSL4DT7 Address H 0080 114D gt CANO Message Slot 5 Data 7 COMSL5DT7 Address H 0080 115D gt CANO Message Slot 6 Data 7 COMSL6DT7 lt Address H 0080 116D gt CANO Message Slot 7 Data 7 COMSL7DT7 lt Address H 0080 117D gt CANO Message Slot 8 Data 7 COMSL8DT7 lt Address H 0080 118D gt CANO Message Slot 9 Data 7 COMSL9DT7 lt Address H 0080 119D gt CANO Message Slot 10 Data 7 COMSL10DT7 lt Address H 0080 11AD gt CANO Message Slot 11 Data 7 COMSL11DT7 lt Address H 0080 11BD gt CANO Message Slot 12 Data 7 COMSL12DT7 lt Address H 0080 11CD gt CANO Message Slot 13 Data 7 COMSL13DT7 lt Address H 0080 11DD gt CANO Message Slot 14 Data 7 COMSL14DT7 lt Address H 0080 11ED gt CANO Message Slot 15 Data 7 COMSL15DT7 lt Address H 0080 11FD
309. Z Data output 0 43VCCE 00 015 0 16VCCE 78 tsu WAITH BCLKH th BCLKH WAITH gt lt 3 tsu WAITL BCLKH th BCLKH WAITL i WAIT 0 43VCCE 0 43VCCE 0 16 Note 1 Stipulated values are guaranteed values when the test load capacitance CL 15 to 50 pF Note 2 Input and output signals are determined high or low with respect to TTL level Figure 21 5 6 Read Timing 21 20 Ver 0 10 21 ELECTRICAL CHARACTERISTICS 21 5 AC Characteristics BCLK Address A12 A30 CS0 CS1 0 43VCCE tc BCLK _ lt lt lt ir QD tw BCLKH tw BCLKL 4 5 4 8 td BCLKH CS tv BCLKH CS td BCLKH A tv BCLKH A pa 0 43VCCE 0 43VCCE 0 16 X 0 16 td RDH BLWL td RDH BHWL e 23 td BCLKL RDL 0 4 td CS BLWL td CS BHWL td A BLWL td A BHWL lt 0 16 tv BCLKL BLWL tv BCLKL BHWL 29 td BLWH RDL td BHWH RDL _ BLW BHW Data Output DO D15 WAIT f td BCLKL BLWL td BCLKL BHWL 2 2 td BCLKL D 0 4 0 4 M tv BLWH CS 59 tv BHWH CS ag MBLWH A tv BHWH A gt tpxz BLWH DZ tpxz BHWH DZ td BLWL D gt td BHWL D tv BLWH D tv BHWH D 0 16 28 tv BCLKH D 0 4 0 16 th BCLK
310. a frame the data length DLC value 3 an Ver 0 10 13 CANO Message Slot 0 Data 4 COMSLODT4 E CANO Message Slot 1 Data 4 0 51 1074 E CANO Message Slot 2 Data 4 0 51 2074 CANO Message Slot 3 Data 4 COMSL3DT4 CANO Message Slot 4 Data 4 COMSL4DT4 E CANO Message Slot 5 Data 4 COMSL5DT4 E CANO Message Slot 6 Data 4 0 51 6074 E CANO Message Slot 7 Data 4 COMSL7DT4 CANO Message Slot 8 Data 4 COMSL8DT4 E CANO Message Slot 9 Data 4 COMSL9DT4 E CANO Message Slot 10 Data 4 COMSL10DT4 E CANO Message Slot 11 Data 4 COMSL11DT4 E CANO Message Slot 12 Data 4 COMSL12DT4 E CANO Message Slot 13 Data 4 COMSL13DT4 E CANO Message Slot 14 Data 4 COMSL14DT4 E CANO Message Slot 15 Data 4 COMSL15DT4 DO 1 2 3 4 CAN MODULE 13 2 CAN Module Related Registers Address H 0080 110A Address H 0080 111A Address H 0080 112A Address H 0080 113A Address H 0080 114A Address H 0080 115A Address H 0080 116A Address H 0080 117A Address H 0080 118A Address H 0080 119A Address H 0080 11 gt Address H 0080 11 gt Address H 0080 11 gt Address H 0080 11DA gt Address H 0080 11 gt Address H 0080 11FA 5 6 D7 COMSLnDT4 D Bit Name 0 7 COMSLnDT4 When reset Indeterminate gt Function R Message slot n data 4 O O These registers are the transmit frame receive frame memory space Note indeterminate value is w
311. able Protect 10 TIO5PRO 5 Enable Protect 11 TIO4PRO 4 Enable Protect 12 TIO3PRO TIO3 Enable Protect 13 TIO2PRO TIO2 Enable Protect 14 TIO1PRO 1 Enable Protect 15 TIOOPRO TIOO Enable Protect Note This register must always be accessed in halfwords The TIOO 9 Enable Protect Register controls rewriting of the TIO count enable bit described in the next page by enabling or disabling rewrite 10 104 Ver 0 10 10 MULTIJUNCTION 5 10 4 TIO Input Output related 16 bit Timer TIOO 9 Count Enable Register TIOCEN DO 1 2 3 4 5 6 7 8 9 10 11 9 TIO8 TIO7 6 5 4 CEN CEN CEN CEN Address H 0080 03 gt 12 13 14 015 TIO2 TIO1 TIOO CEN When reset H 0000 gt D Bit Name Function R 0 5 No functions assigned 0 6 9 9 count enable 0 Stops count O 7 TIO8CEN TIO8 count enable 8 TIO7CEN TIO7 count enable 9 6 TIO6 count enable 10 TIOSCEN 5 count enable 11 TIO4CEN TIO4 count enable 12 TIOSCEN TIO3 count enable 13 TIO2CEN TIO2 count enable 14 TIO1CEN TIO1 count enable 15 TIOOCEN TIOO count enable 1 Enables count Note This register must always be accessed in halfwords The TIOO 9 Count Enable Register controls operation of TIO counters To en
312. able interrupts from internal peripheral 1 which are managed by assigning them one of eight priority levels including an interrupt disabled state When multiple interrupt requests of the same priority level occur simultaneously their priorities are resolved by predetermined hardware priority The source of an interrupt request generated in internal peripheral 1 is identified by reading the relevant interrupt status register provided for internal peripheral I Os On the other hand the system break interrupt SBI is recognized when a low going transition occurs on the SBI signal input pin This interrupt is used for emergency purposes such as when power outage is detected or a fault condition is notified by an external watchdog timer so that it is always accepted irrespective of the PSW register IE bit status When the ICU has finished servicing an SBI terminate or reset the system without returning to the program that was being executed when the interrupt occurred Specifications of the interrupt controller are outlined in the table below Table 5 1 1 Outline of Interrupt Controller ICU Item Specification Interrupt source Maskable interrupt from internal peripheral I O 22 sources System break interrupt 1 source entered from SBI pin Level management Eight levels including an interrupt disabled state However interrupts of the same level have their priorities resolved by fixed hardware priority 5 2 Ver 0 10 INT
313. able the counter in software enable the relevant 0 9 Enable Protect Register for write and set the count enable bit by writing a 1 To stop the counter enable the 0 9 Enable Protect Register for write and reset the count enable bit by writing a O In all but continuous mode when the counter stops due to an occurrence of underflow the count enable bit is automatically reset to 0 Therefore what you get by reading the TIOO 9 Count Enable Register is the status that indicates the counter s operating status active or idle 10 105 Ver 0 10 10 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer TlOm external enable TIOmEEN or TIOmENS F F Edge selection gg Event bus EN ON TlOm enable TIOmCEN TlOm enable protect TlIOmPRO WR F F TIO enable control WR Figure 10 4 7 Configuration of the TIO Enable Circuit 10 106 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer 10 4 9 Operation in TIO Measure Free run Clear Input Modes 1 Outline of TIO measure free run clear input modes In TIO measure free run clear input modes the timer measures a duration of time from when it starts counting till when an external capture signal is entered An interrupt can be generated by a counter underflow or execution of measure operation A
314. access Maximum external input clock frequency 10 MHz CAN Sixteen message slots JTAG Capable of boundary scan 1 9 Ver 0 10 1 3 Pin Function OVERVIEW 1 3 Pin Function Figure 1 3 1 shows pin functions of the M32171FxVFP Table 1 3 1 explains the pin functions Port 22 Port 15 Port 13 Port 12 Port 11 Port 10 Port 9 Figure 1 3 1 Pin Function Diagram of 240QFP XIN XOUT VONT OSC VCC OSC VSS P70 BCLK WR Reset RESET MODO Model MOD1 FP P220 CTX CAN P221 CRX 10 150 153 5 130 137 TIN16 TIN23 Multi junction 4 i timer p124 P127 TCLKO TCLK3 lt gt P93 P97 TO16 TO20 2 P100 P107 TO8 TO15 110 117 TOO TO7 ADOINO ADOIN15 AVCCO 550 VREFO A D converter Pote P6tP63 Interrupt CR controller L VCCE 5V Note 1 M32171FxVFP 45 651 P44 CS0 P43 RD P42 BHW P41 BLW BLE P71 WAIT P72 HREQ P73 HACK P20 P27 23 A30 P30 P37 A15 A22 P46 P47 A13 A14 P225 A12 Note2 P00 P07 DB0 DB7 P10 P17 DB8 DB15 P82 TXDO P83 RXDO P84 SCLKI 0 SCLKO 0 P85 TXD1 P86 RXD1 P87 SCLKI 1 SCLKO 1 P174 TXD2 P175 RXD2 P74 RTDTXD P75 RTDRXD P76 RTDACK P77 RTDCLK Note1 denotes blocks operating with a 3 3 V power supply denotes blocks operating with 5 V power supply Note2 Use caution when us
315. achine cycle by pulling the RESET input signal low The reset interrupt is assigned the highest priority among all EITs EIT Processing 1 Initializing SM IE and C bits The SM IE and C bits of the PSW register are initialized in the manner shown below For the reset interrupt the values of BSM BIE and BC bits are indeterminate SM 0 IE 0 C 0 2 Branching to the EIT vector entry Control branches to the address H 0000 0000 in the user space However when operating in boot mode control goes to the beginning of the boot ROM address H 8000 0000 For details refer to Section 6 5 Programming of Internal Flash Memory 3 Jumping from the EIT vector entry to the user program The M32R E executes the instruction written at address H 0000 0000 of the EIT vector entry by the user In the reset vector entry be sure to initialize the PSW and SPI registers before jumping to the start address of the program you created 4 15 Ver 0 10 4 4 9 Interrupt Processing 4 9 2 System Break Interrupt SBI System Break Interrupt SBI is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer The system break interrupt cannot be masked by the PSW register IE bit Therefore the system break interrupt can only be used when some fatal event has already occurred to the system when the interrupt is detected Also this interrupt must be used
316. ag 1 Requested 2 3 REQSL5 00 Software start or DMA7 transfer completed e Selects cause of DMA5 request 01 All DMAO transfers completed 10 Serial 1 02 reception completed 11 MJT 20 input signal 4 TENL5 0 Disables transfer O Enables DMAS transfer 1 Enables transfer 5 TSZSL5 0 16 bits Selects 5 transfer size 1 8 bits 6 SADSL5 0 Fixed Selects DMAS source address direction 1 Incremental 7 DADSL5 0 Fixed Selects 5 destination 1 Incremental address direction W A Only writing a 0 is effective when you write 1 the previous value is retained 9 11 Ver 0 10 9 DMAC 9 2 DMAC Related Registers E DMA6G Channel Control Register DM6CNT Address H 0080 0428 DO 1 3 4 5 6 D7 MDSEL6 TREQF6 ae TENL6 TSZSL6 SADSL6 DADSL6 When reset 00 gt D Bit Name Function R 0 MDSEL6 0 Normal mode Selects DMA6 transfer mode 1 Ring buffer mode 1 TREQF6 0 Not requested A DMAG6 transfer request flag 1 Requested 2 3 REQSL6 00 Software start Selects cause of DMA6 request 01 Serial 1 01 transmit buffer empty 10 Use inhibited 11 One DMAS transfer completed 4 TENL6 0 Disables transfer Enables DMAG transfer 1 Enables transfer 5 TSZSL6 0 16 bits Selects DMAG transfer size 1 8 bits 6 SADSL6 0 Fixed Selects DMAG source address directi
317. age Slot 3 Standard ID1 COMSL3SID1 CANO Message Slot 3 Extended ID1 COMSL3EID1 CANO Message Slot 3 Extended 102 COMSL3EID2 CANO Message Slot 3 Data Length Register COMSL3DLC CANO Message Slot 3 Data 0 COMSL3DTO CANO Message Slot 3 Data 1 COMSL3DT1 CANO Message Slot 3 Data 2 COMSL3DT2 CANO Message Slot 3 Data 3 COMSL3DT3 CANO Message Slot 3 Data 4 COMSL3DT4 CANO Message Slot 3 Data 6 COMSL3DT6 CANO Message Slot 3 Ti CANO Message Slot 3 Data 5 COMSL3DT5 CANO Message Slot 3 Data 7 COMSL3DT7 ime Stamp COMSL3TSP CANO Message Slot 4 Standard IDO COMSL4SIDO CANO Message Slot 4 Standard ID1 COMSL4SID1 CANO Message Slot 4 Extended IDO COMSLAEIDO CANO Message Slot 4 Extended ID1 COMSL4EID1 CANO Message Slot 4 Extended ID2 COMSL4EID2 CANO Message Slot 4 Data Length Register COMSL4DLC CANO Message Slot 4 Data 0 COMSLADTO CANO Message Slot 4 Data 2 COMSL4DT2 CANO Message Slot 4 Data 4 COMSL4DT4 CANO Message Slot 4 Data 1 COMSL4DT1 CANO Message Slot 4 Data 3 COMSL4DT3 CANO Message Slot 4 Data 5 COMSL4DT5 CANO Message Slot 4 Data 6 COMSL4DT6 CANO Message Slot 4 Data 7 COMSL4DT7 CANO Message Slot 4 Time Stamp COMSL4TSP CANO Message Slot 5 Standard IDO COMSL5SIDO CANO Message Slot 5 Standard ID1 COMSL5SID1 CANO Message Slot 5 Extended IDO COMSL5EIDO Blank addresses are reserved areas CANO Message Slot 5 E
318. al Programmer 6 8 Connecting to A Serial Programmer When you rewrite the internal flash memory using a general purpose serial programmer in Boot Flash E W Enable mode you need to process the pins on the 32171 shown below to make them suitable for the serial programmer Table 6 8 1 Processing the 32171 Pins when Using a Serial Programmer SCLKI1 Need to be pulled high LINE NM MEN NENNEN re Trensmitreceive enable ouput noto be puloatioh x ee CO gt qe e pee oro ume Connect to 3 3 V power supply 108 Connect to 3 3 V power supply VCCI 3 3 V power supply Note All other pins do not need to be processed 6 49 Ver 0 10 INTERNAL MEMORY 6 8 Connecting to A Serial Programmer The diagram below shows an example of user system configuration which has had a serial programmer connected After the user system is powered on the serial programmer writes to the flash memory in clock synchronized serial mode No communication problems associated with the oscillation frequency may occur If the system uses any 32171 pins which will connect to a serial programmer care must be taken to prevent adverse effects on the system when a serial programmer is connected Note that the serial programmer uses the addresses H 0000 0084 through H 0000 0093 as an area to check ID for flash memory protection board Various sig
319. al area internal RAM area and Spe cial Function Register SFR area an area containing a group of internal peripheral I O regis ters Of these the internal ROM and extended external areas are located differently depend ing on mode settings which will be described later 2 Boot program space A 1 Gbyte of address space from H 8000 0000 to H BFFF FFFF is the boot program space This space stores a program boot program which enables on board programming when the internal flash area is blank 3 System space A 1 Gbyte of address space from H C000 0000 to H FFFF FFFF is the system space This space is reserved for use by development tools such as an in circuit emulator or a debug monitor and cannot be used by the user 3 2 Ver 0 10 3 ADDRESS SPACE 3 1 Outline of Address Space Extended external Logical address space of M32171F4 gt area EIT vector ent 4 Mbytes vector entry Logical address H 0000 0000 H 0000 0000 A Internal ROM area 16 Mbytes 1 H 0007 FFFF H 0008 0000 Reserved area 512 Kbytes H O00F FFFF H 0010 0000 CSO area 1 Mbyte meme _ 16 Mbytes H 0020 0000 CS1 area 1 Mbyte User space H 002F FFFF Ghost area in H 0030 0000 CS1 y 1 Mbyte H O03F FFFF HTFFF FFFF ELS H 0040 0000 H 8000 0000 H 8000 0000 BOOT ROM area A 8 Kbytes 8000 1FFF oat Ghost area in Reserved area 8000 2000 4 Mbytes 8
320. always accepted by entering the RESET signal The reset interrupt is assigned the highest priority 2 System Break Interrupt SBI System Break Interrupt SBI is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer This interrupt can only be used in cases when after interrupt processing control will not return to the program that was being executed when the interrupt occurred 3 External Interrupt El External Interrupt El is requested from internal peripheral I Os managed by the interrupt controller The 32171 s internal interrupt controller manages these interrupts by assigning each one of eight priority levels including an interrupt disabled state 4 2 3 Trap Traps are software interrupts which are generated by executing the TRAP instruction Sixteen distinct vector addresses are provided corresponding to TRAP instruction operands 0 15 4 3 Ver 0 10 4 4 3 EIT Processing Procedure 4 3 EIT Processing Procedure EIT processing consists of two parts one in which they are handled automatically by hardware and one in which they are handled by user created programs EIT handlers The procedure for processing EITs when accepted except for a rest interrupt is shown below BN p __ EIT request enerated S 9 Instruction Instruction A B Instruction EIT vector entry Branch
321. an underflow occurs To stop the counter disable count by writing to the enable bit in software The F F output waveform in continuous output mode is inverted at startup and upon underflow generating consecutive pulses until the timer stops counting Also an interrupt can be generated each time the counter underflows 10 86 Ver 0 10 10 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer 10 4 3 TIO Related Register The diagram below shows a TIO related register map Address 0 Address 1 Address DO D7 D8 D15 H 0080 0318 H 0080 031A TIOO 3 Control Register 0 TIOOSCRO 0 3 Control Register 1 M d TIO03CR1 22 H 0080 0320 TIO2 Counter TIO2CT H 0080 0322 H 0080 0324 TIO2 Reload 2 Register TIO2RL H 0080 0326 TIO2 Reload 0 Measure Register TIOORL2 Blank addresses are reserved Note The registers enclosed in thick frames must always be accessed in halfwords Figure 10 4 2 TIO Related Register Map 1 3 10 87 Ver 0 10 10 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer Address H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 0 Address 1 Address 7 D8 0340 4 Counter TIO4CT 0344 4 Reload 1 Reg
322. and bit 15 LSB Therefore the MSB and LSB sides must be reversed when connecting external extension memory 15 14 Ver 0 10 15 2 When Bus Mode Control Register 1 EXTERNAL BUS INTERFACE 15 4 Typical Connection of External Extension Memory A typical connection when using external extension memory is shown in Figure 15 4 2 External extension memory can only be used in external extension mode and processor mode M32171F3 Flash memory a Number of bus wait cycles can be set to 1 4 Y 1 D 1 D D D Y D 2 23 Memory mapping H 0000 0000 Internal flash memory 384 H 0006 0000 H O00F FFFF Hooiooooo 4 O External memory area 1M CSO area H 0020 0000 External memory area 1MB 2M CS1 H 0030 0000 area Ghost area H 0040 0000 i Normally used as port WAIT is used only when four or more wait cycles are needed Figure 15 4 2 Typical Connection of External Extension Memory When BUSMOD 1 Note The 32171 addresses and data are arranged in such way that bit 0 MSB and bit 15 LSB Therefore the MSB and LSB sides must be reversed when connecting external extension memory 15 15 Ver 0 10 1 5 EXTERNAL BUS INTERFACE 15 4 Typical Connection of External Extension Memory 3 Using 8 16 bit data bus memories in combination when Bus Mode Contr
323. are 1 The accepted new IMASK NEW IMASK is set in the IMASK register 2 The accepted interrupt request is cleared not cleared for level recognized interrupt Sources 8 The interrupt request El to the CPU core is cleared 4 The ICU s internal sequencer is activated to start internal processing interrupt priority resolution CAUTION Note that the Interrupt Vector Register IVECT can only be read out by the EIT handler PSW register IE bit being disabled Also make sure that in the EIT handler the Interrupt Mask Register IMASK is read out before reading out the IVECT register 5 6 Ver 0 10 5 INTERRUPT CONTROLLER ICU 5 3 ICU Related Registers 5 3 2 Interrupt Mask Register B Interrupt Mask Register IMASK Address H 0080 0004 gt DO 1 2 3 4 5 6 D7 IMASK lt When reset H 07 gt D Bit Name Function R 0 4 No functions assigned 0 5 7 IMASK Interrupt mask 000 Maskable interrupts are disabled 001 Level 0 interrupts be accepted 010 Level 0 1 interrupts can be accepted 011 Level 0 2 interrupts can be accepted 100 Level 0 3 interrupts can be accepted 101 Level 0 4 interrupts can be accepted 110 Level 0 5 interrupts can be accepted 111 Level 0 6 interrupts can be accepted The Interrupt Mask Register IMASK is used to finally determine whether an interrupt request can be accepted after comparing its priority with the priority le
324. ation Example of Virtual Flash Emulation Mode By locating two RAM areas in the same virtual flash area using the Virtual Flash Emulation Function you can rewrite data in the flash memory successively 1 Operation when reset Bank xx Initial value Replace area RAM block 0 Data write to RAMO RAM block 1 2 Program operation using RAM block 0 Initial value RAM block 0 RAM block 1 8 Program operation changed from RAM block 0 to RAM block 1 Initial value RAM block 0 RAM block 1 Replace RAM block 0 Bank xx specified Bank xx Data write to RAM1 Replace RAM block 0 RAM block 1 Bank xx specified xx specified settings invalid Bank xx Figure 6 7 11 Application Example of Virtual Flash Emulation 1 2 6 47 Ver 0 10 INTERNAL MEMORY 6 7 Virtual Flash Emulation Function 4 Program operation using RAM block 1 Flash Replace Bank xx Initial value RAM block 1 Bank xx specified RAM block 0 Data write to RAMO RAM block 1 5 Program operation changed from RAM block 1 to RAM block 0 Replace Bank xx Initial value RAM block 0 RAM block 1 HS Bank xx specified Bank xx specified RAM block 0 settings invalid RAM block 1 6 Go to item 2 NOTE pem valid area Figure 6 7 12 Application Example of Virtual Flash Emulation 2 2 6 48 Ver 0 10 6 INTERNAL MEMORY 6 8 Connecting to A Seri
325. ation of DMA transfer To ensure the stable operation of DMA transfer never rewrite the DMAC related registers except the DMA Channel Control Register s transfer enable bit unless transfer is disabled One exception is that even when transfer is enabled you can rewrite the DMA Source Address and DMA Destination Address Registers by DMA transfer from one channel to another 9 39 Ver 0 10 DMAC 9 4 Precautions about the DMAC This is a blank page 9 40 Ver 0 10 CHAPTER 10 MULTIJUNCTION TIMERS 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 9 Outline of Multijunction Timers Common Units of Multijunction Timer TOP Output related 16 bit Timer TIO Input Output related 16 bit Timer TMS Input related 16 bit Timer TML Input related 32 bit Timer TID Input related 16 bit Timer TOD Output related 16 bit Timer TOM Output related 16 bit Timer 10 MULTIJUNCTION TIMERS 10 1 Outline of Multijunction Timers 10 1 Outline of Multijunction Timers The multijunction timers abbreviated MJT have input event and output event buses Therefore in addition to being used as a single unit the timers can be internally connected to each other This capability allows for highly flexible timer configuration making it possible to meet various application needs It is because the timers are connected to the internal event bus at multiple points that they are called the multijunction timers The
326. aud rate Tq period x number of Tq s for one bit 1 Mbps BRP 1 255 0 Inhibited Number of Tq s for one bit Synchronization Segment Propagation Segment Phase Segment 1 Phase Segment 2 Progagation Segment 1 8Tq Phase Segment 1 1 8Tq Phase Segment 2 2 8Tq IPT 2 Remote frame automatic response function A slot which received a remote frame automatically sends a data frame Time stamp function Time stamp function implemented by a 16 bit counter Using CAN bus bit period as the fundamental period a count period can be set to 1 1 through 1 4 of it BasicCAN mode BasicCAN function is materialized using two local slots Transmit abort function Transmit request can be canceled Loopback function The data transmitted by CAN module itself is received Return bus off function Forcibly placed into error active mode after clearing error counter 13 2 Ver 0 10 13 Table 13 1 2 CAN Module Interrupt Generation Function CAN module interrupt source CANO transmit complete interrupt ICU interrupt source CANO group interrupt CAN MODULE 13 1 Outline of the CAN Module CANO receive complete interrupt CANO group interrupt CANO bus error interrupt CANO group interrupt CANO error passive interrupt CANO group interrupt CANO bus off interrupt CANO group interrupt Data bus CANO Status Register CANO REC Register
327. avg Noted iic 3 lOL peak Low State Peak Output Current PO P22 Note 3 10 mA Low State Average Output Current PO P22 lOL avg Note 4 ger p mA JTCK JTDI JTMS PF CL Output Load JTDO JTRST Capacitance Note 1 Subject to conditions VCCE gt AVCC VREF Note 2 Subject to conditions VDD VCCI z FVCC OSC VCC Note 3 The total amount of output current peak on ports must satisfy the conditions below Ports PO P1 P2 lt 80 mA Ports P4 P13 P15 P22 lt 80 mA Ports P6 P7 P8 P9 P17 lt 80 mA Ports P10 P11 P12 lt 80 mA Note 4 The average output current is a value averaged during a 100 ms period 21 3 Ver 0 10 21 ELECTRICAL CHARACTERISTICS 21 2 Recommended Operating Conditions Recommended Operating Conditions Referenced to VCCE 5 V 0 5 V VOCI 3 3 V 0 3 V Ta 40 to 125 C Unless Otherwise Noted Symbol Parameter Rated Value Unit MIN Voltage Ports P1 external extension processor mode only WAIT 0 43VCCE VCCE Ports PO P22 RESET 0 2VCCE V Voltage Ports PO P1 external extension 0 16VCCE processor mode only WAIT IOH peak High State Peak Output Current PO P22 Note 3 10 High State Average Output Current 22 E lOL peak Low State Peak Output Current PO P22 Note 3 10 IOL avg Na E Average Output Current PO P22 5 JTCK JTDI JTMS 80 Output Load JTDO JTRST Capacitance Oth
328. bles DMA2 transfer 1 Enables transfer 5 TSZSL2 0 16 bits Selects transfer size 1 8 bits 6 SADSL2 0 Fixed O Selects DMA2 source address direction 1 Incremental 7 DADSL2 0 Fixed O O Selects DMA2 destination 1 Incremental address direction W A Only writing a 0 is effective when you write a 1 the previous value is retained 9 8 Ver 0 10 9 DMAC 9 2 DMAC Related Registers E DMAS3 Channel Control Register DM3CNT Address H 0080 0440 DO 1 3 4 5 6 D7 MDSEL3 REQSLS TENL3 TSZSL3 SADSL3 DADSL3 lt When reset H 00 gt D Bit Name Function R 0 MDSEL3 0 Normal mode Selects transfer mode 1 Ring buffer mode 1 TREQF3 0 Not requested O A transfer request flag 1 Requested 2 3 REQSL3 00 Software start O O Selects cause of DMA3 request 01 Serial 0 transmit buffer empty 10 Serial 1 01 reception completed 11 MJT TINO input signal 4 TENL3 0 Disables transfer O Enables transfer 1 Enables transfer 5 TSZSL3 0 16 bits Selects transfer size 1 8 bits 6 SADSL3 0 Fixed Selects DMA3 source address direction 1 Incremental 7 DADSL3 0 Fixed Selects destination 1 Incremental address direction W A Only writing a 0 is effective when you write 1 the previous value is retained 9 9 Ver 0 10 9 DMA
329. bserve_only X amp 220 BC_1 P45 outputs X 219 0 2 amp Figure 19 5 9 BSDL Description for the 32171 9 14 19 23 Ver 0 10 1 9 E JTAG 19 5 Boundary Scan Description Language 219 BC 1 control 0 amp 218 4 P46 observe only X amp 217 1 P46 outputs X 216 0 2 amp 216 1 control 0 amp 215 4 P47 observe only X amp 214 1 P47 outputs X 213 0 2 amp 213 BC 1 control 0 amp 212 4 P220 observe only X amp 211 1 P220 output3 X 210 0 2 amp 210 BC 1 control 0 amp 209 4 P221 observe only X amp 208 4 P225 observe only X amp 207 1 P225 output3 X 206 0 2 amp 206 BC 1 control 0 amp 205 4 P30 observe only X amp 204 1 P30 output3 X 203 0 Z amp 203 BC_1 control 0 amp 202 BC_4 P31 observe only X amp 201 1 P31 output3 X 200 0 2 amp 200 1 control 0 amp 199 4 P32 observe only X amp 198 1 P32 outputs X 197 0 2 amp 197 1 control 0 amp 196 4 P33 observe only X amp 195 1 P33 output3 X 194 0 2 amp 194 BC 1 control 0 amp 193 4 P34 observe only X amp 192 1 P34 outputs X 191 0 2 amp 191 1 control 0 amp 190 4 5 ob
330. bus error occurs while transmitting the CAN module clears the CAN Message Slot Control Register s TRSTAT Transmit Receive Status bit to 0 If the CAN module requested a transmit abort the transmit abort is accepted and writing to the message slot is enabled 5 Completion of remote frame transmission When remote frame transmission is completed a time stamp count value at the time transmission was completed is written to the CAN Message Slot Time Stamp COMSLnTSP and the CAN Message Slot Control Registers RA Remote Active bit is cleared to 0 Also the CAN Slot Interrupt Status bit is set to 1 by completion of transmission but the CAN Message Slot Control Register s TRFIN Transmit Receive Finished bit is not set to 1 If the CAN slot interrupt has been enabled an interrupt request is generated upon completion of transmission 6 Receiving a data frame When remote frame transmission is completed the slot automatically starts functioning as a data frame receive slot 7 Acceptance filtering When the CAN module finished receiving data it starts searching for the slot that satisfies conditions for receiving the received message sequentially from slot O up to slot 15 13 71 0 10 CAN MODULE 13 13 7 Transmitting Remote Frames The following shows receive conditions for slots that have been set for data frame reception Conditions The receive frame is a data frame The receive ID and the slot ID are iden
331. canceled type generated AE Trap TRAP Instruction processing TRAP instruction 4 completed type 3 System Break Instruction processing PC of the next instruction Interrupt SBI completed type 4 External Interrupt El Instruction processing PC of the next instruction completed type Note that for External Interrupt El the priority levels of interrupt requests from each peripheral I O are set by the 32171 s internal interrupt controller For details refer to Chapter 5 Interrupt Controller 4 22 Ver 0 10 4 EIT 4 12 Example of EIT Processing 4 12 Example of EIT Processing 1 When RIE AE SBI El or TRAP occurs singly BPC register Return address RIE AE SBI El or TRAP occurrs Singly 1 If IE 2 0 no events but reset and SBI are accepted Return address A RTE instruction EIT handler Figure 4 12 1 Processing of Events When RIE AE SBI El or TRAP Occurs Singly 2 When RIE AE or TRAP and El occurs simultaneously RIE AE or TRAP is accepted first BPC register Return address ap RTE instruction RIE AE or TRAP and EI gt 1 occurs simultaneously El is accepted next Return address A TE 7 register Return address instruction EIT handler Figure 4 12 2 Processing of Events when RIE AE or TRAP and Occurs Simultaneously 4 23 Ver 0 10 4 EIT 4 12 Example of EIT Processing EIT vector entry BRA instruction
332. cation time Therefore the flash write time can be calculated using the equation below 76 s When writing data to flash memory at high speed by speeding up the serial communication or by other means the fastest write time possible is as follows Q 13 s 6 38 0 10 6 INTERNAL MEMORY 6 6 Boot ROM 6 6 Boot ROM The table below shows boot memory specifications of the 32171 Table 6 6 1 Boot Memory Specifications Item Capacity Specification 8 Kbytes Location address H 8000 0000 H 8000 1FFF Wait insertion Operates with no wait states with 40 MHz internal CPU memory clock Internal bus connection Connected by 32 bit bus Read Can only be read when FP 1 MODO 1 and MOD1 0 When read in other modes indeterminate values are read out Cannot be accessed for write Other Because the boot ROM area is a reserved area that can only be used in boot mode the program cannot be modified 6 39 Ver 0 10 6 INTERNAL MEMORY 6 7 Virtual Flash Emulation Function 6 7 Pseudo Flash Emulation Function The 32171 can map one 8 Kbyte block of internal RAM beginning with the start address into one of 8 Kbyte areas L banks of the internal flash memory and can map up to two 4 Kbyte blocks of internal RAM beginning with address H 0080 6000 into one of 4 Kbyte areas S banks of the internal flash memory This capability is referred to as the pseudo flash emulation
333. cation with other nodes cannot be performed until the CAN module returns to an error active state 13 55 Ver 0 10 1 3 CAN MODULE 13 4 Initializing the CAN Module 13 4 Initializing the CAN Module 13 4 1 Initialization of the CAN Module Before you perform communication set up the CAN module as described below 1 Selecting pin functions The CAN transmit data output pin CTX and CAN data receive input pin CRX are shared with input output ports so be sure to select the functions of these pins Refer to Chapter 8 Input Output Ports and Pin Functions 2 Setting the interrupt controller ICU When you use CAN module interrupts set the interrupt priority 3 Setting CAN Error Interrupt Mask and CAN Slot Interrupt Mask Registers When you use CAN bus error interrupts CAN error passive interrupts CAN error bus off interrupts or CAN slot interrupts set each corresponding bit to 1 to enable interrupt requests 4 Setting bit timing and the number of times sampled Using the CAN Configuration Register and CAN Baud Rate Prescaler set the bit timing and the number of times the CAN bus is sampled D Setting the bit timing Determine the period Tq that is the base of bit timing the configuration of Propagation Segment Phase Segment1 and Phase Segment2 and reSynchronization Jump Width The equation to calculate Tq is shown below Tq CANBRP 1 CPU clock The baud rate is determined by the number of Tq s that comp
334. ccess external devices The 32171 s 50 and CS1 signals are output corresponding to the address mapping of the ex tended external area CSO signal is output for the CSO area and the CS1 signal is output for the CS1 area Table 3 3 2 Address Mapping of the Extended External Area in Each Operation Mode of the 32171 Operation Mode Address mapping of the extended external area Single chip mode None Extended external mode Addresses H 0010 0000 to H 001F FFFF CSO area 1 Mbytes Addresses H 0020 0000 to H 002F FFFF CS1 area 1 Mbytes Note 1 Processor mode Addresses H 0000 0000 to 000 FFFF CSO area 1 Mbytes Note 2 Addresses H 0020 0000 to 002 FFFF CS1 area 1 Mbytes Note 2 Note 1 During extended external mode a ghost 1 Mbyte of the CS1 area appears in an area of H 0030 0000 through H 003F FFFF Note 2 During processor mode a ghost 1 Mbyte of the 50 area appears an area of H 0010 0000 through H 001F FFFF and a ghost 1 Mbyte of the CS1 area appears an area of H 0030 0000 through H 003F FFFF 3 7 Ver 0 10 3 4 Internal RAM Area and SFR Area 3 4 1 Internal RAM Area 3 4 2 Special Function Register SFR Area H 0080 0000 SFR area 16 Kbytes H 0080 3FFF H 0080 4000 Internal RAM 16 Kbytes H 0080 7FFF 3 8 ADDRESS SPACE 3 4 Internal ROM SFR Area The 8 Mbyte area at addresses H 0080 0000 to H 00FF FFFF in the user space accommodates the internal RAM area a
335. ced in boot mode the reset vector entry address is moved to the start address of the boot program space address H 8000 0000 For details refer to Section 6 5 Programming of Internal Flash Memory 7 2 Ver 0 10 7 RESET 7 3 Internal State Immediately after Reset Release 7 3 Internal State Immediately after Reset Release The table below lists the register state of the device immediately after it has gotten out of reset For details about the initial register state of each internal peripheral I O refer to each section in this manual where the relevant internal peripheral I O is described Table 7 3 1 Internal State Immediately after Reset Register State after Reset Release PSW CRO B 0000 0000 0000 0000 00 000 0000 0000 BSM BIE BC bits indeterminate CBR 1 H 0000 0000 C bit 0 SPI CR2 Indeterminate SPU CR3 Indeterminate BPC CR6 Indeterminate PC H 0000 0000 Executed beginning with address H 0000 0000 Note ACC accumulator Indeterminate Note When in boot mode this changes to the start address of the boot program space H 8000 0000 7 3 0 10 7 RESET 7 4 Things To Be Considered after Reset Release 7 4 Things To Be Considered after Reset Release Input output ports After reset release the 32171 s input output ports are disabled against input in order to prevent current from flowing through the port To use any ports in input mode enable them for i
336. cessed in halfwords Figure 10 4 4 TIO Related Register Map 3 3 10 89 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer 10 4 4 TIO Control Registers The TIO control registers are used to select TIOO 9 operation modes measure input noise processing input PWM output single shot output delayed single shot output or continuous output mode as well as select the counter enable and counter clock sources Following eight TIO control registers are provided for each timer group TIOO 3 Control Register 0 TIOO3CRO TIOO 3 Control Register 1 TIOOSCR1 TIO4 Control Register TIO4CR TIO5 Control Register TIO6 Control Register TIO6CR TIO7 Control Register TIO7CR TIO8 Control Register TIO8CR TIO9 Control Register TIO9CR 10 90 Ver 0 10 10 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer E TIOO 3 Control Register 0 TIO3CRO D 0 1 2 3 4 5 6 7 8 9 10 11 12 2 TIO1 0 TIO2M TIO1M Address H 0080 031A 13 14 015 When reset H 0000 gt D Bit Name Function R 0 external input enable 0 Disables external input 2 Note 2 1 Enables external input 1 3 operation mode selection 000 Single shot output mode 001 Delayed single shot output mode 010 Continuous output mode 011 PWM output mode 100 Meas
337. ch may result in the microcomputer operating erratically or getting out of control High speed serial I O High speed timer input output etc Do not intersect signal lines XIN XOUT VSS O Figure 3 1 7 Wiring of Rapidly Level changing Signal Lines i 0 to 3 Appendix 3 7 Ver 0 10 PRECAUTIONS ABOUT NOISE Appendix 3 1 Precautions about Noise Appendix 3 Appendix 3 1 5 Processing Input Output Ports For input output ports take the appropriate measures in both hardware and software following the procedure described below Hardware measures Insert resistors of 100 O or more in series to input output ports Software measures For input ports read out data in a program two or more times to verify that levels match For output ports rewrite the data register at certain intervals because there is a possibility of the output data being inverted by noise Rewrite the direction register at certain intervals Data bus Direction register 4 Data register Input output port Figure 3 1 8 Processing Input Output Ports Appendix 3 8 Ver 0 10 Mitsubishi 32 bit RISC Single chip Microcomputers M32R Family M32R E Series 32171 Group User s Manual Ver 0 10 August 08 2000 Copyright 2000 MITSUBISHI ELECTRIC CORPORATION Copyright 2000 MITSUBISHI ELECTRIC SEMICONDUCTOR SYSTEMS CORPORATION All Rights Reversed No part of this manual may be repro
338. channels Transfer request Software trigger Request from internal peripheral 1 A D converter multijunction timer or serial reception completed transmit buffer empty Transfer operation can be cascaded between DMA channels Note Maximum number of times transferred 256 times Transferable address space 64 Kbytes address space from H 0080 0000 to H 0080 FFFF Transfers between internal peripheral l Os between internal RAM and internal peripheral I O between internal RAMs are supported Transfer data size 16 or 8 bits Transfer method Single transfer DMA control of the internal bus is relinquished for each transfer performed dual address transfer Transfer mode Single transfer mode Direction of transfer One of three modes can be selected for the source and destination Address fixed Address incremental Ring buffered Channel priority Channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 channel 8 channel 9 Priority is fixed Maximum transfer rate 13 3 Mbytes per second with 20 MHz internal peripheral clock Interrupt request Group interrupt request can be generated when each transfer count register underflows Transfer area 64 Kbytes from H 0080 0000 to H 0080 FFFF Transferable in the entire internal RAM SFR area Note Transfer operation can be cascaded between DMA channels as
339. cleared when restored from the error passive state 13 12 Ver 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers 3 CBS CAN Bus Error bit D3 Set condition This bit is set to 1 when an error on the CAN bus is detected Clear condition This bit is cleared when normally transmitted or received 4 BCS BasicCAN Status bit D4 When BCS bit 1 it means that the CAN module is operating in BasicCAN mode Set condition This bit is set to 1 when operating in BasicCAN mode Conditions for operating in BasicCAN mode The CAN Control Register BCM bit must be set to 1 Slots 14 and 15 both must be set for data frame reception Clear condition This bit is cleared by clearing the BCM bit to 0 5 LBS Loopback Status bit D6 When LBS bit 1 it means that the CAN module is operating in loopback mode Set condition This bit is set to 1 by setting the CAN Control Register LBM loopback mode bit to 1 Clear condition This bit is cleared by clearing the LBM bit to O 6 CRS CAN Reset Status bit D7 When CRS bit 1 it means that the protocol control unit is in a reset state Set condition This bit is set to 1 when the CAN module s protocol control unit is in a reset state Clear condition This bit is cleared by clearing the CAN Control Register RST CAN reset bit to 0 13 13 Ver 0 10 1 3 MODULE 13 2 CAN Module Related Registers 7 RSB Receive Status bit D8 Set cond
340. completed cascade mode 9 30 Ver 0 10 DMAC 9 3 Functional Description of the DMAC 9 3 2 DMA Transfer Processing Procedure Shown below is an example of how to control DMA transfer in cases when performing transfer in DMA channel 0 DMA transfer processing starts Setting interrupt v controller related Set the interrupt controller s DMAO0 4 e Interrupt priority level registers Interrupt Control Register v Set DMAO Channel Control Register e Transfers disabled Set 4 Interrupt Request Status Register Clears interrupt request status bit Set DMAO 4 Interrupt Mask Register e Enables interrupt request v Setting DMAE Set DMAO Source Address Register e Source address of transfer related registers 7 Set DMAO Destination Address Register e Address v Set DMAO Count Register Number of times transfer performed Set DMAO Channel Control Register Transfer mode cause of request transfer size i address direction and y transfer enable Starting DMA DMA transfer starts as requested by transfer internal peripheral I O Y Transfer count register underflows DMA transfer Y completed Interrupt request generated operation completed Figure 9 3 1 Example of a Transfer Processing Procedure 9 31 Ver 0 10 9 9 3 Functional Description of
341. curred H 08 address H 08 H 0C Figure 4 8 1 Example of Return Address for Reserved Instruction Exception RIE 4 Branching to the EIT vector entry Control branches to the address H 0000 0020 in the user space This is the last operation performed in hardware preprocessing by the M32R E 5 Jumping from the EIT vector entry to the user created handler The M32R E executes the BRA instruction written at address H 0000 0020 of the EIT vector entry by the user to jump to the start address of the user created handler At the beginning of the EIT handler you created first save the BPC and PSW registers and the necessary general purpose registers to the stack 6 Returning from the EIT handler Atthe end of the EIT handler restore the general purpose registers and the BPC and PSW registers from the stack and then execute the RTE instruction As you execute the RTE instruction hardware postprocessing is automatically performed by the M32R E 4 12 Ver 0 10 4 EIT 4 8 Exception Processing 4 8 2 Address Exception AE Occurrence Conditions Address Exception AE is generated when an attempt is made to access a misaligned address in Load or Store instructions The following lists the combination of instructions and accessed addresses that may cause address exceptions to occur When the LDH LDUH or STH instruction accessse
342. d 55 B6 b6 F F IRB6 b6 F F Slot 7 transmit receive completed D 55 7 2 F F IRB7 br F F gt To remaining 11 source inputs in the next page Figure 13 2 5 Block Diagram of CANO Group Interrupts 1 3 13 27 Ver 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers CANOSLIST H 0080 100 gt CANOSLIMK H 0080 1010 Slot 8 transmit receive completed Data bus SSB8 19 source inputs F F J 0 To preceding page b8 EE e Level Slot 9 transmit receive completed 55 9 b9 F F D IRB9 5s F F Slot 10 transmit receive completed 55810 F F p IRB10 18 F F Slot 11 transmit receive completed 55 11 b11 F F IRB11 D F F Slot 12 transmit receive completed SSB12 Bie F F Py IRB12 b12 F F Slot 13 transmit receive completed 55 13 b13 F F IRB13 b13 Slot 14 transmit receive completed S B14 pr F F D ENT F F Slot 15 transmit receive completed pig 55815 F F MD IRB15 To remaining 3 source inputs in the next page Figure 13 2 6 Block Diagram of CANO Group Interrupts 2 3 13 28 Ver 0 10
343. d If an external interrupt is requested at the same time a reserved instruction exception is detected itis the reserved instruction exception that is accepted EIT Processing 1 Saving SM IE and C bits The SM IE and C bits of the PSW register are saved to their backup bits the BSM BIE and BC bits BSM lt SM BIE lt IE BC C 2 Updating SM IE and C bits The SM IE and C bits of the PSW register are updated as shown below SM lt Unchanged BIE lt 0 lt 0 3 Saving PC value of the instruction that generated the reserved instruction exception is set in the BPC register For example if the instruction that generated the reserved instruction exception is at address 4 the value 4 is set in the BPC register Similarly if the instruction is at address 6 the value 6 is set in the BPC register In this case the value of the BPC register bit 30 indicates whether the instruction that generated the reserved instruction exception resides on a word boundary BPC 30 0 or not on a word boundary BPC 30 1 However in either case of the above the address to which the RTE instruction returns after completion of processing by the EIT handler is address 4 This is because the two low order bits are cleared to 00 when returning to the PC 4 11 Ver 0 10 EIT 4 8 Exception Processing 0 1 Address 7 Address Boi H 00 H 00 aud ues gt 04 RIE occurred Return H 04 RIE oc
344. d P176 P177 are nonexistent 8 18 Ver 0 10 8 INPUT OUTPUT PORTS AND FUNCTIONS 8 3 Input Output Port Related Registers E P22 Operation Mode Register P22MOD Address H 0080 0756 DO 1 2 3 4 5 6 D7 P220MOD P225MOD When reset 00 gt D Bit Name Function R 0 P220MOD 0 P220 Port P220 operation mode 1 CTX 1 4 No functions assigned 0 5 P225MOD 0 P225 O O Port P225 operation mode 1 Use inhibited 6 7 No functions assigned 0 Note 1 P221 is a CAN input only pin Note 2 The pin function of P225 changes depending on how MODO and MOD pins set Also because it has a debug event function be careful when using this port Note 3 P222 224 P226 and P227 are nonexistent 8 19 Ver 0 10 8 INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 3 Input Output Port Related Registers Bi Port Input Function Enable Register PIEN Address H 0080 0745 gt D8 9 10 11 12 13 14 D15 PIENO When reset 00 gt D Bit Name Function R 8 14 functions assigned 0 15 PIENO 0 Disables input to prevent current from flowing Port input function enable bit 1 Enables input This register is provided to prevent current from flowing into the port input pin Because after reset this register is set to disable input it must be set to 1 before input can be processed During boot mode all pins shared with serial I O function are
345. d Time after Read Ex umm qme ml ERN E mmm ETHIC Se e 21 13 Ver 0 10 21 ELECTRICAL CHARACTERISTICS 21 5 AC Characteristics 6 Bus arbitration timing Symbol Parameter Condition RaedVaue i Figure 7 Input transition time on JTAG pin Rated Value See Symbol Condition Unit Figure 21 5 10 MIN MAX Input Rising Transition Time Input Falling Transition Time Other than JTRST pin is 10 JTCK JTDI JTMS JTDO JTRST pin TAP Other than JTRST pin JTCK JTDI JTMS JTDO cca mcm Co TAP TAP Note Stipulated values are guaranteed values when the test pin load capacitance CL 80pF 8 JTAG interface timing RatedVale Value Symbol Condition NIMM paure 4 9 user moowscaymeme nura 714 w G JTRST Input Low Pulse Width tc JTCK 5 Note Stipulated values are guaranteed values when the test pin load capacitance CL 80pF 21 14 Ver 0 10 21 ELECTRICAL CHARACTERISTICS 21 5 AC Characteristics 21 5 2 Switching Characteristics 1 Input output ports Symbol Parameter Condiion Rated Value Rated Value Value Unit See 2 Serial I O a CSIO mode with internal clock selected ii ae
346. d an address whose two low order bits are 01 or 1 1 When the LD ST LOCK or UNLOCK instruction accessed an address whose two low order bits are 01 10 or 11 When an address exception occurs memory access by the instruction that generated the exception is not performed If an external interrupt is requested at the same time an address exception is detected it is the address exception that is accepted EIT Processing 1 Saving SM IE and C bits The SM IE and C bits of the PSW register are saved to their backup bits the BSM BIE and BC bits BSM lt SM BIE lt IE BC C 2 Updating SM IE and C bits The SM IE and C bits of the PSW register are updated as shown below SM lt Unchanged IE lt 0 lt 0 3 Saving PC The PC value of the instruction that generated the address exception is set in the BPC register For example if the instruction that generated the address exception is at address 4 the value 4 is set in the BPC register Similarly if the instruction is at address 6 the value 6 is set in the BPC register In this case the value of the BPC register bit 30 indicates whether the instruction that generated the address exception resides on a word boundary BPC 30 0 or not on a word boundary BPC 30 1 However in either case of the above the address to which the RTE instruction returns after completion of processing by the EIT handler is address 4 This is because the two
347. ddress 1 Address DO D8 D1 Ptr Eras IE H 0080 074C P13 Operation Mode Register P13MOD H 0080 074E PO P15 Operation Mode Register P15MOD H 0080 0752 H 0080 0744 H 0080 0754 H 0080 0756 Blank addresses are reserved 8 3 2 Input Output Port Related Register Map 2 2 8 7 Ver 0 10 INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 3 Input Output Port Related Registers 8 3 1 Port Data Registers E PO Data Register PODATA Address H 0080 0700 E P1 Data Register P1DATA Address H 0080 0701 E P2 Data Register P2DATA Address H 0080 0702 B Data Register P3DATA Address H 0080 0703 Data Register PADATA Address H 0080 0704 E P6 Data Register P6DATA Address H 0080 0706 B P7 Data Register P7DATA Address H 0080 0707 E P8 Data Register P8DATA Address H 0080 0708 E P9 Data Register PODATA Address H 0080 0709 E P10 Data Register 100 Address H 0080 070A B P11 Data Register P11DATA Address H 0080 070 gt E P12 Data Register P12DATA Address H 0080 070 gt E P13 Data Register P13DATA Address H 0080 070D gt E P15 Data Register P15DATA lt Address H 0080 070F gt E P17 Data Register P17DATA lt Address H 0080 0711 gt E P22 Data Register P22DATA Address H 0080 0716 DO 1 2 3 4 5 6 D7 D8 9 10 11 12 13 14 D15 PnODT PniDT Pn2DT Pn3DT Pn4DT Pn5DT PneDT Pn7DT Note n 0 13 15 17 and 22 not including P5
348. ddresses or between odd addresses data may be transferred from even address to odd address or from odd address to even address When the transfer unit 8 bits the LSB of the address register D15 of the address register is ignored and data are always transferred in two bytes aligned to the 16 bit bus The diagram below shows the valid transfer byte positions When transfer unit 8 bits When transfer unit 2 16 bits v Figure 9 3 3 Transfer Byte Positions 9 35 Ver 0 10 9 3 Functional Description of the DMAC 7 Ring buffer mode When ring buffer mode is selected transfer begins from the transfer start address and after performing transfers 32 times control is recycled back to the transfer start address from which transfer operation is repeated In this case however the five low order bits of the ring buffer start address must always be B 00000 The address increment operation in ring buffer mode is described below CD When the transfer unit 8 bits The 27 high order bits of the transfer start address are fixed and the five low order bits are incremented by one at a time When as transfer proceeds the five low order bits reach B 11111 they are recycled to B 00000 by the next increment operation thus returning to the start address again When the transfer unit 16 bits The 26 high order bits of the transfer start address are fixed and the six low order bits are incremented by
349. de comparator mode Operation mode Single mode scan mode Scan mode Single shot scan mode continuous scan mode Conversion start trigger Software start Started by setting A D converter start bit to 1 Hardware start Starts A DO converter by MJT output event bus 3 Note 2 Conversion rate f BCLK Internal peripheral clock operating frequency During single mode Normal rate 299 X 1 f BCLK Note 3 shortest time Double rate 173 X 1 f BCLK During comparator mode Normal rate 47 X 1 BCLK shortest time Double rate 29 1 f BCLK Interrupt request generation function Generated at completion of A D conversion comparate operation single shot scan operation or one cycle of continuous scan operation DMA transfer request generation function Note 1 errors are adjusted to 0 Note 2 Note 3 Generated at completion of A D conversion comparate operation single shot scan operation or one cycle of continuous scan operation The nonlinearity error is a deviation from ideal conversion characteristics after the offset and full scale Refer to Chapter 10 Multijunction Timers When 20 2 this is 1 f BCLK 50 ns Ver 0 10 1 1 CONVERTERS 11 1 Outline of Converters Internal data bus lt gt
350. ded IDO to extended ID3 Extended IDO to extended 103 These registers are the transmit frame receive frame memory space Note When set for the receive slot standard ID format values written to EID bits when storing received data in the slot are indeterminate 13 40 Ver 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers CANO Message Slot 0 Extended ID1 COMSLOEID1 Address H 0080 1103 E CANO Message Slot 1 Extended ID1 COMSL1EID1 Address H 0080 1113 E CANO Message Slot 2 Extended 101 COMSL2EID1 Address H 0080 1123 CANO Message Slot 3 Extended ID1 COMSL3EID1 Address H 0080 1133 E CANO Message Slot 4 Extended ID1 COMSL4EID1 Address H 0080 1143 CANO Message Slot 5 Extended ID1 COMSL5EID1 Address H 0080 1153 2 E CANO Message Slot 6 Extended ID1 COMSLGEID1 Address H 0080 1163 E CANO Message Slot 7 Extended ID1 COMSL7EID1 Address H 0080 1173 CANO Message Slot 8 Extended ID1 COMSL8EID1 Address H 0080 1183 E CANO Message Slot 9 Extended ID1 COMSL9EID1 Address H 0080 1193 2 E CANO Message Slot 10 Extended ID1 COMSL10EID1 Address H 0080 11 gt CANO Message Slot 11 Extended ID1 COMSL11EID1 Address H 0080 11 3 gt CANO Message Slot 12 Extended ID1 COMSL12EID1 Address H 0080 11C3 gt E CANO Message Slot 13 Extended ID1 COMSL13EID1 Address H 0080 1103 gt CANO Message Slot 14 Extended ID1 COMSL14EID1 Address H 0080 11 gt CANO Message Sl
351. diagram does not show detail timing information Figure 10 4 8 Typical Operation in Measure Free run Input Mode 10 108 Ver 0 10 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer Measure event Enabled capture by writing to enable bit occurs Y Count clock Enable bit ARRE E Indeterminate Value 3555555 nanese Measure register Indeterminate Y H 7000 22 4 TIN interrupt i TIN interrupt by external event input a TIO interrupt n TIO interrupt by underflow Note This diagram does not show detail timing information Figure 10 4 9 Typical Operation in Measure Clear Input Mode 10 109 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer 2 Precautions to be observed when using TIO measure free run clear input modes The following describes precautions to be observed when using TIO measure free run clear input modes f measure event input and write to the counter occur simultaneously in the same clock period the write value is set in the counter while at the same time latched into the measure register 10 110 Ver 0 10 10 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer 10 4 10 Operation in TIO Noise Processing Input Mode In noise processing input mode the timer detects the status of an input signal that it remained in the same state for
352. duced or distributed in any form or by any means without the written permission of Mitsubishi M32R Family M32R E Series 32171 Group User s Manual Preliminary Ver 0 10 gt Mitsubishi Electric Corporation Mitsubishi Electric Semiconductor Systems Corporation MSD M32171 U 0008
353. e 00 conversion start Software trigger Started by setting A DO conversion start bit to 1 Hardware trigger Started by output event bus 3 gt Completed here when operating in single shot scan mode Figure 11 1 5 Operation of A D Conversion in Scan Mode for 8 channel 16 channel Scan Ver 0 10 1 1 CONVERTERS 11 1 Outline of Converters Table 11 1 2 Registers in Which Scan Mode A D Conversion Results Are Stored Scan loop Selected channels Selected channels A D Conversion result selection for single shot scan for continue scan storage Register 4 channel scan ADOINO ADOINO 10 bit A DO Data Register 0 ADOIN1 ADOIN1 10 bit A DO Data Register 1 ADOIN2 ADOIN2 10 bit A DO Data Register 2 ADOIN3 ADOIN3 10 bit A DO Data Register 3 Completed ADOINO 10 bit A DO Data Register 0 Repeated until forcibly halted 8 channel scan ADOINO ADOINO 10 bit A DO Data Register 0 ADOIN1 ADOIN1 10 bit A DO Data Register 1 ADOIN2 ADOIN2 10 bit A DO Data Register 2 ADOIN3 ADOIN3 10 bit A DO Data Register 3 ADOIN4 ADOIN4 10 bit A DO Data Register 4 ADOIN5 ADOIN5 10 bit A DO Data Register 5 ADOIN6 ADOIN6 10 bit A DO Data Register 6 ADOIN7 ADOIN7 10 bit A DO Data Register 7 Completed ADOINO 10 bit A DO Data Register 0 Repeated until forcibly halted 16 channel scan ADOINO ADOINO 10 bit A DO Data Register 0 ADOIN1 ADOIN1 10 b
354. e Figure 17 3 2 shows the normal operating state of the M32R E During normal operation the RAM backup signal output by the external signal is high Also input on the SBI pin or ADnINi i 0 15 pin used for RAM backup signal detection remains high Port X which is the transistor s base connecting pin should output a high This causes the transistor s base voltage IB to go high so that current is fed from the power supply to the VCC pin via the transistor DC IN E Input Regulator Output RAM backup power supply 3 3V system Regulator Output bV system Output Regulator External circuit 3 3V system RAM backup signal Note 1 j 4 69 69 69 69 e Port X VCCI OSC VCC VCCE VREFn AVCCn VDD Note 2 SBI m Notes M32R E Note 1 This signal outputs a low for RAM backup Note 2 This pin outputs a high when the power is on and is set for input mode when RAM backup mode Note 3 These pins are used to detect a RAM backup signal Figure 17 3 2 Normal Operating State 17 6 Ver 0 10 1 7 RAM BACKUP MODE 17 3 Example of RAM Backup for Saving Power Consumption 17 3 2 RAM Backup State Figure 17 3 3 shows the RAM backup state of the M32R E Figure 17 3 4 shows a RAM backup sequence When the external circuit outputs a low input on the SBI or ADnINi pin goes low low on these input pin
355. e Slot Control Register TRSTAT bit 0 Set ID in message slot Set Extended ID Register Set CAN Message Slot Control Register Settings completed Write 00 Verify that transmission is idle Standard ID or extended ID Write H AO transmit request remote Figure 13 7 1 Remote Frame Transmit Procedure 13 70 Ver 0 10 CAN MODULE 13 13 7 Transmitting Remote Frames 13 7 2 Remote Frame Transmit Operation The following describes remote frame transmit operation The operations described below are automatically performed in hardware 1 Setting the RA Remote Active bit At the same time H AO Transmit Request Remote is written to the CAN Message Slot Control Register the RA Remote Active bit is set to 1 indicating that the corresponding slot is to handle remote frames 2 Selecting a transmit frame The CAN module checks slots which have transmit requests including data frame transmit slots every intermission to determine the frame to transmit If there are multiple transmit slots frames are transmitted in order of slot numbers beginning with the smallest 3 Transmitting a remote frame After determining the transmit slot the CAN module sets the corresponding CAN Message Slot Control Register s TRSTAT Transmit Receive Status bit to 1 thereby starting transmission 4 If the CAN module lost bus arbitration or a CAN bus error occurs If the CAN module lost bus arbitration or a CAN
356. e Therefore be sure to set the output high level in the Port X Data Register before you set port X for output mode Unless this method is followed port output may go low at the same time port output is set after the clock oscillation has stabilized causing the device to enter RAM backup mode 17 8 Ver 0 10 1 7 RAM BACKUP MODE 17 4 Exiting RAM Backup Mode Wakeup 17 4 Exiting RAM Backup Mode Wakeup Processing to exit RAM backup mode and return to normal operation is referred to as wakeup processing Figure 17 4 1 shows an example of wakeup processing Wakeup processing is initiated by reset input The following shows how to execute wakeup processing 1 Reset the device D in Figure 17 4 1 For details about reset refer to Chapter 7 Reset 2 Set port X for output mode and output a high from the port in Figure 17 4 1 Note 3 Check the RAM contents against the check data created before entering RAM backup mode in Figure 17 4 1 4 If the RAM contents and check data did not match when checked in 3 initialize the RAM 4 in Figure 17 4 1 If the RAM contents and check data matched use the retained data in the program 5 After initializing each internal circuit in Figure 17 4 1 return the main routine in Figure 17 4 1 Note For wakeup from power outage RAM backup mode settings for port X are unnecessary Example of wakeup processing D Reset Set transistor s base connectin
357. e the value of the shift register stage is shifted right one bit every cycle and the data b 110001 fixed value that was set in 2 is serially output from the JTDO pin At the same time the instruction code serially entered from the JTDI pin is set in the shift register stage bit by bit Because instruction code is set in the instruction register which is comprised of 6 bits the Shift IR state continues for a period of 6 JTCK cycles To stop the shift operation in the middle go to Pause IR state via temporarily Exit1 IR state by setting JTMS input from high to low Also to return from Pause IR state go to Shift IR state via temporarily Exit1 IR state by setting JTMS input from high to low 4 By setting JTMS high go from Shift IR state to Exit1 IR state This completes the shift operation 5 Subsequently enter JTMS high to go to Update IR state In Update IR state the instruction code that was set in the instruction register s shift register stage is transferred to the instruction register s parallel output stage and thus JTAG instruction decoding begins 6 Subsequently enter JTMS high to go to Select DR Scan state JTMS low to go to Run Test ldle state 19 8 Ver 0 10 19 JTAG 19 4 Basic Operation of JTAG of JTCK in Shift IR state JTDI input is sampled at rise Instruction code is set in the parallel output J stage at fall of JTCK in Update IR state
358. e 16 3 5 Read Write Timing for Access with 4 Internal Wait Cycles 16 10 Ver 0 10 16 WAIT CONTROLLER 16 3 Typical Operation of the Wait Controller Read Read 6 cycles 1 external 4 internal wait cycles Wait cycle xu oe BCLK A12 A30 5 cei 74 ZK KL DE EE E SE PHT DBO DB15 B AT 0 XQ OO NN 7 1 1 Don t Care L Write Write 6 cycles 1 external 4 internal wait cycles cycle im gt i 12 A30 oso G8 22 04 0 ww i i1 1 DBO DB15 WAIT a i Don t Care L Note Circles above indicate points at which signals are sampled Figure 16 3 6 Read Write Timing for Access with 4 Internal and 1 External Wait Cycles 16 11 Ver 0 10 WAIT CONTROLLER 16 3 Typical Operation of the Wait Controller Read 3 n cycles Read Don t Care n A a ees ESSI PROS eene A ieee ru Quir
359. e 19 5 13 BSDL Description for the 32171 13 14 19 27 Ver 0 10 19 JTAG 19 5 Boundary Scan Description Language end M32171F4VFP 4 P117 1 117 1 4 100 1 100 1 BC 4 P101 BC 1 P101 BG ds BC 4 P102 BC 1 P102 BG observe only X output3 X 9 0 Z control 0 amp observe only X output3 X 6 0 Z control 0 amp observe only X output3 X 3 0 Z control 0 amp observe only X output3 X 0 0 Z control 0 amp amp amp amp amp amp amp amp Figure 19 5 14 BSDL Description for the 32171 14 14 19 28 Ver 0 10 19 JTAG 19 6 Precautions about Board Design when Connecting JTAG 19 6 Precautions about Board Design when Connecting JTAG To materialize fast and highly reliable communication with JTAG tools the JTAG pins require that wiring lengths be matched during board design M32R E JTDO JTDI JTMS JTCK JTRST VCCE 5V SDI connector JTAG connector User board i Power MA 10KQ rM 332 l A TDO 10KQ Me 332 AM TDI 10KQ 332 l AM TMS 10KQ 332 AM 332 TRST 2KQ T GND P Make sure wiring lengths are the same and avoid bending wires as much as p
360. e 3 1 4 Bypass Capacitor between VSS and VCC Lines Appendix 3 4 Ver 0 10 INSTRUCTION PROCESSING TIME Ap pend IX 3 Appendix 3 1 Precautions about Noise Appendix 3 1 3 Processing Analog Input Pin Wirin Connect a resistor of about 100 to 500 Q in series to the analog signal wire connecting to the analog input pin at a position as close to the microcomputer as possible Also insert a capacitor of about 100 pF between the analog input pin and AVSS pin at a position as close to the AVSS pin as possible lt Reasons gt The signal fed into the analog input pin e g A D converter input pin normally is an output signal from a sensor In many cases a sensor to detect changes of event is located apart from the board on which the microcomputer is mounted so that wiring to the analog input pin inevitably is long Because a long wiring serves as an antenna which draws noise into the microcomputer the signal fed into the analog input pin tends to be noise ridden Furthermore if the capacitor connected between the analog input pin and AVSS pin is grounded at a position apart from the AVSS pin noise ridding on the ground line may penetrate into the microcomputer via the capacitor Noise Sensor Micro computer Analog input pin Figure 3 1 5 Resistor and Capacitor for Analog Signal Line Appendix 3 5 Ver 0 10 PRECAUTIONS ABOUT NOISE Ap pend IX 3 Appendix 3 1 Precautions about Noise Appendix 3 1 4 Con
361. e CAN module finished reading out from the slot normally 13 74 Ver 0 10 13 CAN MODULE 13 7 Transmitting Remote Frames Reading out received data Clear TRFIN bit to 0 Read out from message slot Read CAN Message Slot Control Register Finished reading out received data Figure 13 7 3 Procedure for Reading Out Received Data when Set for Remote Frame Transmission 13 75 Ver 0 10 CAN MODULE 13 13 8 Receiving Remote Frames 13 8 Receiving Remote Frames 13 8 1 Remote Frame Receive Procedure The following describes the procedure for receiving remote frames 1 Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the slot in which you want to receive by writing H OO to the register 2 Confirming that reception is idle Read the CAN Message Slot Control Register after being initialized and check the TRSTAT Transmit Receive Status bit to see that reception has stopped and remains idle If this bit 1 it means that the CAN module is accessing the message slot so you need to wait until the bit is cleared 3 Setting the receive ID Set the ID you want to receive in the message slot 4 Setting the Extended ID Register Set the corresponding bit of the Extended ID Register to 0 when you want to receive a standard frame or 1 when you want to receive an extended frame 5 Setting the CAN Message Slot Control Register D When automat
362. e SIO Receive Control Register s REN receive enable bit However if an overrun error occurs this bit cannot be cleared by reading the lower byte from the Receive Buffer Register In this case clear the REN receive enable bit 6 FLM framing error bit D6 This bit is effective in only UART mode During CSIO mode this bit is fixed to 0 Set condition The FLM framing error bit is set to 1 when the number of received bits does not agree with one that has been selected by the SIO Transmit Receive Mode Register However if an overrun error occurs this bit cannot be cleared by reading the lower byte from the Receive Buffer Register In this case clear the REN receive enable bit Clear condition The FLM bit is cleared by reading the lower byte from the SIO Receive Buffer Register or by clearing the SIO Receive Control Register s REN receive enable bit 7 ERS Error sum bit 07 Set condition This flag is set to 1 when any one of overrun framing or parity errors is detected at completion of reception Clear condition If an overrun has occurred this flag is cleared by clearing the REN receive enable bit Otherwise this flag is cleared by reading the lower byte from the Receive Buffer Register or clearing the SIO Receive Control Register s REN receive enable bit 12 22 Ver 0 10 1 2 SERIAL I O 12 2 Serial Related Registers 12 2 8 SIO Baud Rate Registers E 5100 Baud Rate Register SOBAUR
363. e accessed in halfwords Note 2 Always make sure the counter has stopped and is idle before setting or changing operation modes 10 53 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer TOPO 5 Control Register 1 TOPO5CR1 lt Address H 0080 029D gt D8 9 10 11 12 13 14 D15 5 When reset H 00 gt D Bit Name Function R 8 11 No functions assigned 0 12 13 5 TOP5 operation mode selection 00 Single shot output mode 14 15 operation mode selection 01 Delayed single shot output mode 1X Continuous output mode Note Always make sure the counter has stopped and is idle before setting or changing operation modes Clock bus Input event bus 3210 3210 Te 5 0 Ik te an TOP 1 tO TOP 2 tock TOP 3 tk 4 776 5 TINO O TINOS E en 4 51 4 t S Selector Note This diagram is shown for the explanation of TOP control registers and is partly omitted Figure 10 3 5 Outline Diagram of TOPO 5 Clock Enable Inputs 10 54 Ver 0 10 10 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer TOP6 7 Control Register TOP67CR DO 1 2 3 4 5 6 7 8
364. e data that was set in 2 is serially output from the JTDO in At the same time the setup data serially entered from the JTDI pin is set in the data register s shift register stage bit by bit By continuing the Shift DR state as long as the number of bits of the selected data register by entering JTMS low all bits of data can be set in and read out from the shift register stage To stop the shift operation in the middle go Pause DR state via temporarily Exit1 DR state by setting JTMS input from high to low Also to return from Pause DR state to Shift DR state via temporarily Exit1 DR state by setting JTMS input from high to low 4 Set JTMS high to go from Shift DR state to Exit2 DR state This completes the shift operation 5 Subsequently enter JTMS high to go to Update DR state In Update DR state the data that was set in the data register s shift register stage is transferred to the parallel output stage and thus the setup data becomes ready for use 6 Subsequently enter JTMS high to go to Select DR Scan state or JTMS low to go to Run Test ldle state 19 10 Ver 0 10 19 JTAG 19 4 Basic Operation of JTAG JTDI input is sampled at rise 2 Setup data is set in the parallel output stage of JTCK in Shift DR state at fall of JTCK in Update DR state JTCK JTMS o T 2 2 9 LM Ea state S
365. e diagrams in the next pages show a map of registers in the common units of the multijunction timer 10 7 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer 0 Address 1 Address Address DO D7 D8 Clock Bus amp Input Event Bus H 0080 0200 Control Register CKIEBCH H 0080 0202 Prescaler Register 0 PRSO Prescaler Register 1 PRS1 H 0080 0204 Prescaler Register 2 PRS2 Output Eveni BEBER o Register H 0080 0210 Input Processing Control Register TCLKCR H 0080 0212 TIN Input Processing Control Register O TINCRO H 0080 0216 H 0080 0218 TIN Input Processing Control Register 3 TINCR3 H 0080 021A TIN Input Processing Control Register 4 TINCR4 s F F Source Select Register 0 FFS0 H 0080 0222 F F Source Select Register 1 FFS1 H 0080 0220 TIN Interrupt Control Register 0 TIN Interrupt Control Register 1 H 0080 0238 TINIRO 1 TIN Interrupt Control Register 4 TIN Interrupt Control Register 5 H 0080 023C TINIRA 99 INIR5 99 H 0080 023E TIN Interrupt Control Register 6 TIN Interrupt Control Register 7 INIRG INIR7 Y Blank addresses are reserved Note The registers included in thick frames must always be accessed in halfwords Figure 10 2 1 Timer Common Register Map 10 8 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer 10 2 2 Prescaler Unit The prescalers 50 2 are an 8 bit c
366. e of measuring input pulses in two circuit blocks comprising a total eight channels The table below shows specifications of TMS The diagram in the next page shows a block diagram of TMS Table 10 5 1 Specifications of TMS Input related 16 bit Timer Item Specification Number of channels 8 channels 2 circuit blocks consisting of 4 channels each 8 channels in total Counter 16 bit up counter x 2 Measure register 16 bit measure register x 8 Timer startup Started by writing to enable bit in software Interrupt generation Can be generated by a counter overflow 10 5 2 Outline of TMS Operation In TMS when the timer is started by writing to the enable bit in software the counter starts operating The counter is a 16 bit up counter where when a measure signal is entered from an external device the counter value is latched into each measure register The counter stops counting at the same time count is disabled by writing to the enable bit in software TIN interrupts can be generated by entering an external measurement signal no TIN interrupts available for 50 and TMS interrupts can be generated by an overflow signal from the counter 10 122 Ver 0 10 10 MULTIJUNCTION 5 10 5 TMS Input related 16 bit Timer
367. e program erase operations Flash Status Register 1 FSTAT1 Address H 0080 07 1 gt D8 9 10 11 12 13 14 D15 FSTAT When reset H 01 gt D Bit Name Function R 8 14 functions assigned 0 15 FSTAT 0 Busy Ready Busy status 1 Ready The Flash Status Register 1 FSTAT1 is a read only status register used to know the execution status of whether the flash memory is being programmed or erased When the FSTAT bit 0 it means that the flash memory is being programmed or erased during which time any operation to program the flash memory area is disabled 6 5 Ver 0 10 6 INTERNAL MEMORY 6 4 Registers Associated with the Internal Flash Memory B Flash Status Register 2 FSTAT2 D8 9 10 11 12 13 14 D15 FBUSY ERASE WRERR1 WRERR2 When reset 80 gt D Bit Name Function R 8 FBUSY 0 Program or erase under way e Flash busy 1 Ready state 9 No functions assigned 0 10 ERASE 0 Erase normally operating terminated Auto Erase operating condition 1 Erase error occurred 11 WRERR1 0 Program normally operating terminated e Program operating condition 1 Program error occurred 12 WRERR2 0 Program normally operating terminated Program operating condition 1 Over programming occurred 13 15 No functions assigned 0 The Flash Status Register 2 FSTAT2 consists of the following four read
368. e value in mask registers for the two slots the possibility of a message lost trouble when for example receiving frames which have many IDs can be reduced Procedure for entering BasicCAN mode Follow the procedure below during initialization D Set the IDs for slots 14 and 15 and local mask registers A and B We recommend setting the same value Set the frame types handled by slots 14 and 15 standard or extended in the CAN Extended ID Register We recommend setting the same type 3 Set the Message Slot Control Register for slots 14 and 15 to for data frame reception Setthe BCM bit to 1 Note 1 Do not change settings of BCM bit when CAN is operating CAN Status Register CRS bit 0 Note 2 first slot that is active after clearing the RST bit is slot 14 Note 3 Even during BasicCAN mode slots 0 to 13 can be used as in normal operation 6 LBM Loopback Mode bit D14 When the LBM bit is set to 1 if a receive slot exists whose ID matches that of the frame sent by the CAN module itself then the frame can be received Note 1 No ACK is returned for the transmit frame Note 2 Do not change settings of LBM bit when CAN is operating CAN Status Register CRS bit 0 7 RST CAN Reset bit D15 When the RST bit is cleared to 0 the CAN module is connected to the CAN bus and becomes possible to communicate after detecting 11 consecutive recessive bits Also the CAN Time Stamp Count Register thereby starts c
369. e virtual flash function Virtual flash emulation enable 1 Enable virtual flash function 1 7 No functions assigned 0 8 14 LBANKAD A12 A18 of start address of the L bank O O L bank address to be selected 15 No functions assigned 0 Note This register must always be accessed in halfword 1 MODENL Virtual Flash Emulation Enable bit DO The MODENL bit can be set to 1 after entering virtual flash emulation mode by setting the FEMMOD bit to 1 while the FENTRY bit 0 This causes the virtual flash emulation function to become effective for the L bank area selected by the LBANKAD bits 2 LBANKAD L Bank Address bits D8 D14 The LBANKAD bits are provided for selecting one L bank from a total of 96 L banks separated every 8 KB Use these LBANKAD bits to set the seven bits A12 A18 of the 32 bit start address of the L bank you want to select For details refer to Section 6 7 Virtual Flash Emulation Function 6 14 Ver 0 10 6 INTERNAL MEMORY 6 4 Registers Associated with the Internal Flash Memory 6 4 5 Virtual Flash S Bank Registers E Virtual Flash S Bank Register 0 FESBANKO Address H 0080 07 gt E Virtual Flash S Bank Register 1 FESBANK1 Address H 0080 07 2 gt MOD DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 When reset H 0000 gt D Bit Name Function R 0 MODENS 0 Disable virtual flash function Virtual flash emulation enable 1 Enable virtual flash function
370. ead any address of internal flash memory to check for program error Note 3 Go to next page YES Forcibly terminated Last address Note 1 Start writing from the beginning of a 256 byte boundary of the flash memory lower address H 00 Note 2 When Program operation starts you have the Read Status Register command automatically entered You do not need to enter the Read Status Register command until you issue another command Note 3 Examine the Flash Status Register 2 ERESE Auto Erase operating condition WRERR1 Program operating condition 1 and WRERR2 Program operating condition 2 bits to check for program error Figure 6 5 10 Page Program 6 33 Ver 0 10 INTERNAL MEMORY 6 5 Programming of the Internal Flash Memory C START y Write Lock Bit Program command H 7777 to any address of internal flash memory Write Verify command H DODO to the last even address of the block you want to protect Written to the lock bit by program Note 1 1 us wait by hardware timer or software timer Read any address of internal flash memory to check for program error Note 2 Forcibly terminated Note 1 When Program operation starts you have the Read Status Register command automatically entered You do not need to enter the Read Status Register command until you issue another command Note 2 Examine the Flash Status
371. easure register f the timer operates with any clock other than the 1 2 internal peripheral clock while clock bus 1 is selected for the count clock the counter cannot be written to normally Therefore when operating with any clock other than the 1 2 internal peripheral clock do not write to the counter f the timer operates with any clock other than the 1 2 internal peripheral clock while clock bus 1 is selected for the count clock the captured value is one that leads the actual counter value by one clock period However during the 1 2 internal peripheral clock interval from the count clock this problem does not occur and the counter value is captured at exact timing The diagram below shows the relationship between counter operation and the valid data that can be captured When 1 2 internal peripheral clock is selected 1 2 internal peripheral clock i N 8 When clock bus 1 is selected 1 2 internal _ 21 peripheral clock Count clock Counter A X Capture B Figure 10 6 4 Mistimed Counter Value and Captured Value 10 141 Ver 0 10 10 This is a blank page 10 142 MULTIJUNCTION TIMERS 10 6 TML Input related 32 bit Timer Ver 0 10 CHAPTER 11 CONV
372. eceive error interrupt 6 ISR2 SIO2 receive interrupt 0 Receive finished interrupt O O cause select bit 1 Receive error interrupt 7 No functions assigned 0 This register selects the cause of an interrupt generated at completion of receive operation When set to 0 Receive finished interrupt receive buffer full is selected Receive finished interrupts occur for receive errors except an overrun error as well as for completion of receive operation When set to 1 Receive error interrupt is selected The following lists the types of errors detected for reception errors CSIO mode Overrun error UART mode Overrun error parity error and framing error 12 11 Ver 0 10 12 SERIAL I O 12 2 Serial I O Related Registers RXD2 b6 receive finished RXD2 receive error Data bus ISR2 F F SI23STAT H 0080 0100 gt lt SIO3MASK H 0080 0101 TXD2 us F F 2 5 012 HE 55 ROMASK b13 TEF 4 source inputs 51023 transmit receive Level interrupts Figure 12 2 4 Block Diagram of SIO23 Transmit Interrupts 12 12 Ver 0 10 12 SERIAL I O 12 2 Serial Related Registers 12 2 3 SIO Transmit Control Registers SIOO Transmit Control Register SOTCNT E SIO1 Transmit Control Register STTCNT SIO2 Transmit Control Register
373. ecified address Figure 14 3 7 Operation of the VER Continuous Monitor Command 14 9 Ver 0 10 1 4 REAL TIME DEBUGGER RTD 14 3 Functional Description of the RTD 14 3 5 Operation of Interrupt Request When the VEI interrupt request command is issued the RTD outputs data from the address that has been accessed by the instruction either read or write immediately before receiving the VEI command LSB side MSB side 31 20 19 18 17 16 15 0 RTDRXD X X 0 1 1 0 X X Note Note VEI interrupt request generation command Note X Don t Care However if issued immediately after the RCV command bits 20 31 must all be set to 1 Figure 14 3 8 VEI Interrupt Request Command Data Format 32 clock 32 clock 32 clock 32 clock lt rod x saree eee gt FALL AAEL RTDRXD RDR A X VEI y sate Note 1 EE RTDTXD ee DN C jd RTDACK 2 clock D 1 Read value D 1 Read value periods Note 2 Note 2 RTD interrupt request A RTD interrupt Note 1 WRR command can also be used Note 2 An Specified address D An Data at specified address Figure 14 3 9 Operation of the VEI Inte
374. ed Released bus Y i Y i Y i One DMA transfer One DMA transfer One DMA transfer R Read W Write Figure 9 3 2 Gaining and Releasing Control of the Internal Bus 9 32 Ver 0 10 9 9 3 Functional Description of the DMAC 9 3 6 Transfer Units Use the TSZSL DMA transfer size select bit to set for each channel the number of bits 8 or 16 bits to be transferred in one DMA transfer 9 3 7 Transfer Counts Use the DMA Transfer Count Register to set transfer counts for each channel Transfer can be performed up to 256 times The value of the DMA Transfer Count Register is decremented by one each time one transfer unit is transferred In ring buffer mode the DMA Transfer Count Register operates in free run mode with the value set in it ignored 9 3 8 Address Space The address space in which data can be transferred by DMA is the internal peripheral I O or 64 Kbytes of RAM space H 0080 0000 through H 0080 FFFF for either source or destination To set the source and destination addresses in each channel use the DMA Source Address Register and DMA Destination Address Register 9 3 9 Transfer Operation 1 Dual address transfer Irrespective of the size of transfer unit data is transferred in two bus cycles one for source read access and one for destination write access The transfer data is temporarily taken into the DMA s internal temporary register 2 Bus protocol and bus timing Because the bu
375. ed LDH instruction or zero extended LDUH instruction 0 MSB 16 Rn Halfword From memory LDH LDUH instructions Y 31 LSB From memory LD instructions Y Word When storing 0 MSB Rn Byte To memory STB instruction 31 LSB Halfword To memory STH instruction 31 LSB Word To memory ST instruction Figure 2 6 2 Data Formats in Register 2 8 Ver 0 10 2 6 Data Formats 2 Data formats in memory Data sizes in memory are either byte 8 bits halfword 16 bits or word 32 bits Byte data can be located at any address However halfword data must be located at halfword boundaries where the LSB address bit 0 and word data must be located at word boundaries where two LSB address bits 00 If an attempt is made to access memory data across these halfword or word boundaries an address exception is generated Address 0address 1 address 2 address address Y 15 16 23 24 Halfword Figure 2 6 3 Data Formats in Memory 2 9 Ver 0 10 2 2 6 Data Formats 3 Endian The following shows the generally used endian methods and the M32R family endian Bit endian Byte endian 01 H 01234567 MSB LSB MSB LSB Little endian Note Even for bit big endian H 01 is not B 10000000 Figure 2 6 4 Endian Methods 7700 family Competition M32R family Mennene 16 family M16 family Endian Bit Byte Address Data arra
376. ed MJT output interrupt 5 MJT output interrupt group 5 TOP10 output 1 Edge recognized MJT output interrupt 4 output interrupt group 4 4 TIO7 output 4 Level recognized MJT output interrupt 3 MJT output interrupt group 3 TIO8 TIO9 output 2 Level recognized MJT output interrupt 2 MJT output interrupt group 2 TOPO TOP5 output 6 Level recognized MJT output interrupt 1 MJT output interrupt group 1 TOP6 TOP7 output 2 Level recognized MJT output interrupt 0 output interrupt group 0 TIOO TIO3 output 4 Level recognized MJT input interrupt 4 input interrupt group 4 TINS input 1 Level recognized MJT input interrupt 3 MJT input interrupt group 3 TIN20 TIN23 input 4 Level recognized MJT input interrupt 2 MJT input interrupt group 2 TIN16 TIN19 input 4 Level recognized MJT input interrupt 1 MJT input interrupt group 1 TINO input 1 Level recognized Note ICU type of input source Edge recognized Interrupt requests are generated on a falling edge of the interrupt signal applied to the ICU Level recognized Interrupt requests are generated when the interrupt signal applied to the ICU is held low For these level recognized interrupts the ICU s Interrupt Control Register IRQ bit cannot be set or cleared in software 5 4 Ver 0 10 INTERRUPT CONTROLLER ICU 5 3 ICU Related Registers 5 3 ICU Related Registers The diagram below shows a map of the Interrupt Controller ICU s related regist
377. ed above is enabled 10 28 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer 10 2 6 Interrupt Control Unit The interrupt control unit controls the interrupt signals sent to the interrupt controller by each timer Following 22 timer interrupt control registers are provided for each timer TOPIRO TOPIR1 Interrupt Control Register 0 TOP Interrupt Control Register 1 TOP Interrupt Control Register 2 TOPIR2 Interrupt Control Register 3 TOPIR3 TIO Interrupt Control Register 0 TIOIRO TIO Interrupt Control Register 1 TIOIR1 TIO Interrupt Control Register 2 TIOIR2 TMS Interrupt Control Register TMSIR Interrupt Control Register 0 TINIRO TIN Interrupt Control Register 1 TINIR1 Interrupt Control Register 4 TINIR4 Interrupt Control Register 5 5 Interrupt Control Register 6 TINIR6 For interrupts which have only one source of interrupt in one interrupt table no interrupt control registers are provided in the timer and the interrupt status flags are automatically managed within the interrupt controller For details refer to Chapter 5 Interrupt Controller TOP10 MJT Output Interrupt 5 IRQ5 For interrupts which have two or more sources of interrupt in one interrupt table interrupt control registers are provided with which to control interrupt requests and determine
378. ed for future use Note The registers in the thick frames must always be accessed in halfwords Figure 5 3 1 Interrupt Controller ICU Related Register Map 5 5 Ver 0 10 INTERRUPT CONTROLLER ICU 5 3 ICU Related Registers 5 3 1 Interrupt Vector Register B Interrupt Vector Register IVECT Address H 0080 0000 gt DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 IVECT When reset Indeterminate gt D Bit Name Function R 0 15 16 low order When an interrupt is accepted the 16 low order bits bits of ICU vector in ICU vector table address for the accepted table address interrupt source is stored in this register Note This register must always be accessed in halfwords The Interrupt Vector Register IVECT is used when an interrupt is accepted to store the 16 low order bits of ICU vector table address for the accepted interrupt source Before this function can work the ICU vector table addresses H 0000 0094 through H 0000 must have set in it the start addresses of interrupt handlers for each internal peripheral I O When an interrupt is accepted the 16 low order bits of ICU vector table address for the accepted interrupt source is stored in this IVECT register The EIT handler reads out the content of the IVECT register by the LDH instruction to acquire the ICU vector table address When the IVECT register is read out operations 1 to 4 below are automatically performed in hardw
379. edure described below D The ILEVEL values set by the Interrupt Control Register for each interrupt peripheral I O are compared with each other If the ILEVEL values are the same they are resolved according to the predetermined hardware priority 8 The ILEVEL value is compared with IMASK value When multiple interrupt requests occur simultaneously the interrupt controller first compares their priority levels set by each Interrupt Control Register s ILEVEL bit to select an interrupt request which has the highest priority If the interrupt requests have the same LEVEL value they are resolved according to the hardware fixed priority The interrupt request thus selected has its ILEVEL value compared with IMASK value and if its priority is higher than the IMASK value the interrupt controller sends an El request to the CPU Interrupt requests may be masked by setting the Interrupt Mask Register and the Interrupt Control Register s ILEVEL bit level 7 disabled provided for each internal peripheral I O and the PSW register IE bit Resolve priority ae according to jene Compare with bau eruet if requeste interrupt priority gt gto gt IMASK value 77 SW register IE bit or not levels ILEVEL hardware priority 21 ILEVEL settings i Can be accepted when 9 Level3 ted Level 3 IMASK 4 7 MJT Output Interrupt 4 _ S 14 MJT Output Inte
380. ely changes to reload value 1 at the next clock edge Because the internal circuit operation is synchronized to the count clock prescaler output a finite time equal to a prescaler delay is included before F F starts operating after the timer is enabled 10 120 Ver 0 10 10 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer Enabled Underflow by writing to enable bit first time or by external input Underflow second time Down count starting from reload 0 register set value Y Y Count clock 2 LL IL Enable bit HERRE ete So E ee etus i Down count H A000 starting from Counter counter set value L 0000 Down count starting from reload 0 register set value Reload 0 register 000 Reload 1 register Not used F F output 5 i Data inverted Data inverted by enable by underflow 2 20 TIO interrupt by underflow Note This diagram does not show detail timing information Figure 10 4 16 Typical Operation in TIO Continuous Output Mode without Correction Function 10 121 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 5 TMS Input related 16 bit Timer 10 5 TMS Input related 16 bit Timer 10 5 1 Outline of TMS TMS Timer Measure Small is an input related 16 bit timer capabl
381. emory 6 2 Internal RAM Specifications of the 32171 s internal RAM are shown below Table 6 2 1 Specifications of the Internal RAM Item Specification Capacity 16 Kbytes Location address H 0080 4000 H 0080 7FFF Wait insertion Operates with no wait states when using 40 MHz CPU clock Internal bus connection Connected by 32 bit bus Dual port By using the Real Time Debugger RTD data can be read monitored or written to any area of the internal RAM via serial communication from external devices independently of the CPU Refer to Chapter 14 Real Time Debugger 6 3 Internal Flash Memory Specifications of the 32171 s internal flash memory are shown below Table 6 3 1 Specifications of the Internal Flash Memory Item Specification Capacity M32171F4 512 Kbytes M32171F3 384Kbytes Location address M32171F4 H 0000 0000 H 0007 FFFF M32171F3 H 0000 0000 H 0005 FFFF Wait insertion Operates with no wait states when using 40 MHz CPU clock Durability Can be rewritten 100 times Internal bus connection Connected by 32 bit bus Other Virtual flash emulation function is included Refer to Section 6 7 Virtual Flash Emulation Function 6 2 Ver 0 10 6 INTERNAL MEMORY 6 4 Registers Associated with the Internal Flash Memory 6 4 Registers Associated with the Internal Flash Memory The diagram below shows a register map associated with the internal flash memory Address
382. en it executes the RTE instruction 1 Hardware preprocessing when an EIT is accepted D Save the SM IE and C bits of the PSW register BSM lt SM BIE lt IE BC C Update the SM IE and C bits of the PSW register SM lt Remains unchanged RIE AE TRAP or set to 0 SBI El RI IE lt Setto0 C lt Setto0 9 Save the PC register BPC lt PC 4 Set the vector address in the PC register Branches to the EIT vector and executes the branch instruction BRA instruction written in it thereby transferring control to the user created EIT handler 2 Hardware postprocessing when the RTE instruction is executed Restore the SM IE and C bits of the PSW register from their backup bits SM lt BSM IE lt BIE C lt BC Restore the value of the PC register from the BPC register PC lt BPC Note The value of the BPC register and those of the BSM BIE and BC bits of the PSW register after execution of the RTE instruction are indeterminate 4 8 Ver 0 10 4 4 6 Saving and Restoring the PSW 1 Save SM IE and C bits 8 Save PC BSM lt SM BPC PC BIE lt IE BC 4 Set vector address in PC PC Update SM IE and C bits lt Vector address SM Unchanged 0 E lt 0 lt 0 Restore BSM BIE and BC bits Restore PC value from BPC from backup bits SM lt BSM The value of BPC after IE lt BIE execution of the RTE lt instruc
383. en odd parity select bit SP stop bit Indicates the end of data transmission and is added immediately after characters or if parity enabled immediately after the parity bit The stop bit can be chosen to be one bit or two bits long 12 43 Ver 0 10 12 SERIAL I O 12 6 Transmit Operation in UART Mode LSB MSB ST D7 D6 D5 D4 D3 D2 D1 SP 4 ST D7 D6 D5 D4 D3 D2 D1 SP SP ST 07 06 D5 D4 D2 D1 PAR SP ST D7 D6 D5 D4 D3 D2 D1 PAR SP SP 7 bit characters LSB MSB ST D7 D6 D5 D4 D3 D1 DO SP lt 4 ST D7 D6 D5 D4 D3 D1 DO SP SP ST D7 D6 D5 D4 D3 D2 D1 DO PAR SP ST D7 D6 D5 D4 D3 D2 D1 DO SP SP 8 bit characters LSB MSB ST D8 D7 D6 D5 DO SP ST D8 D7 D6 D5 D4 D3 D1 DO SP SP ST D8 D7 D6 D5 D4 D3 D2 D1 DO PAR SP ST D8 D7 D6 D5 D4 D3 D2 D1 DO PAR SP SP 9 bit characters ST Start bit DO D7 Character data bits PAR Parity bit SIO Transmit Buffer Register SP Stop bit SIO Receive B
384. en you want to transmit the data as an extended frame b Setting the CAN Message Slot Control Register Write H 80 note to the CAN Message Slot Control Register to set the TR Transmit Request bit to 1 Note When you are transmitting a data frame always write H 80 to this register 13 59 Ver 0 10 13 CAN MODULE 13 5 Transmitting Data Frames Data frame transmit procedure Initialize CAN Message Slot Control Register Read CAN Message Slot Control Register TRSTAT bit 2 0 Set ID and data in message slot Set Extended ID Register Set CAN Message Slot Control Register Settings completed Write 00 Verify that transmission is idle Standard ID or extended ID Write H 80 transmit request Figure 13 5 1 Data Frame Transmit Procedure 13 60 Ver 0 10 CAN MODULE 13 13 5 Transmitting Data Frames 13 5 2 Data Frame Transmit Operation The following describes data frame transmit operation The operations described below are automatically performed in hardware 1 Selecting a transmit frame The CAN module checks slots which have transmit requests including remote frame transmit slots every intermission to determine the frame to transmit If there are multiple transmit slots frames are transmitted in order of slot numbers beginning with the smallest 2 Transmitting a data frame After determining the transmit slot the CAN module sets the corresponding CAN Message
385. enabled for input so that when rewriting the flash memory via serial communication you can set this register to 0 to prevent current from flowing in from any pins other than serial I O function The next page lists the pins that can be controlled by the Port Input Function Enable Register in each mode 8 20 Ver 0 10 Table 8 3 1 Controllable Pins by Port Function Enable Bit Mode Name Single chip INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 3 Input Output Port Related Registers Controllable Pins POO 07 P10 P17 P20 P27 P30 P37 P41 P47 P61 P63 P70 P77 P82 P87 P93 P97 P100 P107 P110 P117 P124 P127 P130 P137 P150 P153 P174 P175 P220 P225 Noncontrollable Pins P64 P221 FP Extended external Microprocessor P61 P63 P70 P77 P82 P87 P93 P97 P100 P107 P110 P117 P124 P127 P130 P137 P150 P153 P174 P175 P220 POO P07 P10 P17 P20 P27 P30 P37 P41 P47 64 P221 P225 FP Boot single chip POO P07 P10 P17 20 27 P30 P37 P41 P47 P61 P63 P67 P70 P77 P93 P97 P100 P107 110 117 124 127 P130 P137 P140 P147 P150 P157 P160 P167 P172 P173 P180 P187 P190 P197 P210 P217 P220 P222 P225 8 21 P64 P82 P87 P174 P175 P221 FP Ver 0 10 8 INPUT OUTPUT PORTS AND FUNCTIONS 8 4 Port Peripheral Circuits 8 4 Port Peripheral Circuits Figures 8 4 1 through 8 4 4 sh
386. equest mask 0 Enables interrupt request O O 12 DMITMK8 DMAS8 interrupt request mask 1 Masks disables interrupt request 13 DMITMK7 DMA7 interrupt request mask 14 DMITMK6 DMA6 interrupt request mask 15 DMITMK5 DMAS interrupt request mask The 5 9 Interrupt Mask Register is used to mask interrupt requests DMA channels 5 9 DMITMKn DMAn interrupt request mask bit n z 5 to 9 DMAn interrupt request is masked by setting the DMAn interrupt request mask bit to 1 However when an interrupt request is generated the DMAn interrupt request status bit is always set to 1 irrespective of the contents of this register 9 24 Ver 0 10 9 2 DMAC Related Registers 5 source inputs DMA transfer DMO4ITST H 0080 0400 DMO4ITMK H 0080 0401 DMA4UDF Data bus DMITST4 53 DMITMK4 ep DMA3UDF b4 F F DMITMK3 512 F F DMA2UDF DMITST2 b5 F F DMITMK2 513 DMA1UDF DMITST1 b6 F F a DMITMK1 514 F F DMAOUDF DMITSTO b7 F F 5 DMITMKO EF Level interrupt 0 Figure 9 2 3 Block Diagram of DMA Transfer Interrupt 0 9 25 Ver 0 10 9 2 DMAC Related Registers
387. er 1 Configuration when using BRG 2 clock TXD ST Data SP RXD UARTt it i ransmit receive ST Data SP Clock output to peripheral circuits SCLKO 2 Operation timing Internal BRG output i i i i BRGperod SCLKO output 50 50 Figure 12 8 1 Example of Fixed Period Clock Output 12 58 Ver 0 10 1 2 SERIAL I O 12 9 Precautions on Using UART Mode 12 9 Precautions on Using UART Mode Settings of SIO Transmit Receive Mode Register and SIO Baud Rate Register The SIO Transmit Receive Mode Register and SIO Baud Rate Register and the Transmit Control Register s BRG count source select bit must always be set when not operating When transmitting or receiving data be sure to check that transmission and or reception under way has been completed and clear the transmit and receive enable bits before you set the registers Settings of Baud Rate BRG Register If you selected f BCLK with the BRG clock source select bit make sure the BRG register value you set is equal to or greater than 7 The value written to the SIO Baud Rate Register becomes effective beginning with the next period after the BRG counter finished counting However when transmit and receive operations are disabled the re
388. er on 17 8 17 4 Exiting RAM Backup Mode Wakeup eene 17 9 CHAPTER 18 OSCILLATION CIRCUIT 18 1 Oscillator Circuit euis 18 2 18 1 1 Example of an Oscillator 18 2 18 1 2 System Clock Output Function sssseeee 18 3 18 1 3 Oscillation Stabilization Time at Power on 18 4 18 2 Clock Generator 18 5 CHAPTER 19 JTAG 19 1 Outline OF STAG ecient set cca ces arene cence teret erre guine 19 2 19 2 Configuration of the JTAG Circuit esee 19 3 19 3 JTAG Registers 1 19 4 19 3 1 Instruction Register JTAGIR sse 19 4 19 3 2 Data Registers 00 2 19 5 19 4 Basic Operation of JTAQG 19 6 19 4 1 Outline of JTAG Operation 19 6 19 4 2 IR Path Sequence 2 19 8 19 4 3 DR Path 19 10 19 4 4 Examining and Setting Data Registers 19 12 19 5 Boundary Scan Description 19 14 19 6 Precautions about Board Design when Connecting JTAG 19 29 11 CHAPTER 20
389. er than above f XIN External Clock Input Frequency 5 Note 1 Subject to conditions VCCE gt AVCC gt VREF Note 2 Subject to conditions VDD VCCI FVCC OSC VCC Note 3 The total amount of output current peak on ports must satisfy the conditions below Ports PO P1 P2 80 mA Ports P4 P13 P15 P22 lt 80 mA Ports P6 P7 P8 P9 P17 lt 80 Ports P10 P11 12 lt 80 mA Note 4 The average output current is a value averaged during 100 ms period D H L L C 21 4 Ver 0 10 21 ELECTRICAL CHARACTERISTICS 21 3 DC Characteristics 21 3 DC Characteristics 21 3 1 Electrical Characteristics 1 Electrical characteristics when f XIN 2 10 MHz Referenced to VCCE 5 V 0 5V VCCI 3 3 V 0 3 V Ta 40 to 85 C Unless Otherwise Condon Rated Va Output High Voltage 2mA VCCE 1 RES VCCE RAM Retention Power Supply When operating VCCI Voltage BEC High State Input Current VI VCCE st ts te 10 0 2 When reset 5 5 V power supply Note 1 f XIN 10 0MHz When operating f XIN 10 0M Wh ICCI 3V 3 3 V power supply Note 2 en reset f XIN 10 0MHz When operating Ta 25 C IDDhold RAM Retention Power Supply Current 85 Hysteresis Note 3 Vr VT RTDCLK RTDRXD SCLKIO 1 RXDO 1 2 TCLK3 0 VCCE 5V See RAM retention power supply current cnaracisristie TINO 3 16 23 RESE
390. er underflows the reload register value is loaded into the counter causing it to continue counting down and the counter stops when it underflows next time The F F output waveform in delayed single shot output mode is inverted when the counter underflows first time and next generating a single shot pulse waveform in width of reload register set value 1 only once with the output delayed by an amount of time equal to first set value of counter 1 Also an interrupt can be generated when the counter underflows first time and next 3 Continuous output mode In continuous output mode the timer counts down clock pulses starting from the set value of the counter and when the counter underflows reloads it with the reload register value Thereafter this operation is repeated each time the counter underflows thus generating consecutive pulses whose waveform is inverted in width of reload register set value 1 10 47 Ver 0 10 10 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer When after setting the counter and reload register the timer is enabled by writing to the enable bit in software or by external input it starts counting down from the counter s set value synchronously with the count clock and when the minimum count is reached generates an underflow This underflow causes the counter to be reloaded with the content of the reload register and start counting over again Thereafter this operation is repeated
391. erefore what you get by reading the TOPO 10 Count Enable Register is the status that indicates the counter s operating status active or idle 10 64 Ver 0 10 10 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer TOPm external enable TOPmEEN F F Edge selection p TINnS Event bus TOPm enable protect TOPmPRO WR Dn FF 93 EN ON TOPm enable TOPmCEN F F WR TOP enable control Figure 10 3 8 Configuration of the TOP Enable Circuit 10 65 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer 10 3 9 Operation in TOP Single shot Output Mode with Correction Function 1 Outline of TOP single shot output mode In single shot output mode the timer generates a pulse in width of reload register value 1 only once and stops without performing any operation When after setting the reload register the timer is enabled by writing to the enable bit in software or by external input it loads the content of the reload register into the counter synchronously with the count clock letting the counter start counting The counter counts down clock pulses and stops when it underflows after reaching the minimum count The F F output waveform in single shot output mode is inverted F F output levels change from low to high or vice versa at start
392. ernal devices by RTD s exclusive clock synchronized serial I O 1 3 Ver 0 10 OVERVIEW 1 1 Outline of the 32171 1 1 4 Built in Clock Frequency Multiplier The 32171 internally multiplies the input clock signal frequency by 4 and the internal peripheral clock by 2 If the input clock frequency is 10 0 MHz the CPU clock frequency will be 40 MHz and the internal clock frequency 20 MHz 1 1 5 Built in Powerful Peripheral Functions 1 Built in multijunction timer MJT The multijunction timer is configured with the following 37 channels timers 16 bit output related timer x 11 channels 16 bit input output related timer x 10 channels 16 bit input related timer x 8 channels incorporating three channels of multiply by 4 counter 32 bit input related timer x 8 channels Each timer has multiple modes of operation which can be selected according of the purpose of use The multijunction timer has internal clock bus input event bus and output event bus allowing multiple timers to be combined for use internally This provides a flexible way to make use of timer functions The output related timers TOP have a correction function This function allows the timer s count value in progress to be increased or reduced as desired thus materializing real time output control 2 Built in 10 channel DMA The 10 channel DMA is built in supporting data transfers between internal peripheral I Os or between internal per
393. errupt mask 14 TOPIM1 TOP1 interrupt mask 15 TOPIMO TOPO interrupt mask 10 32 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer TOPIRO H 0080 0230 TOPIR1 H 0080 0231 TOP5udf Data bus TOPIS5 6 source inputs b2 F F MJT output 1 interrupt 2 TOPIM5 Level IRQ2 bi0 p TOP4udf TOPIS4 b3 F F J TOPIM4 511 F F TOP3udf TOPIS b4 F F 7 b12 F F TOP2udf TOPIS2 b5 F F pu TOPIM2 pis F F TOP1udf TOPIS1 b6 F F i 5 TOPIM1 b14 FF TOPOudf TOPISO b7 F F CE TOPIMO b15 FF Figure 10 2 6 Block Diagram of MJT Output Interrupt 2 10 33 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer E TOP Interrupt Control Register 2 TOPIR2 Address H 0080 0232 DO 1 2 3 4 5 6 D7 TOPIS7 56 TOPIM7 6 When reset 00 gt D Bit Name Function R 0 1 No functions assigned 0 2 TOPIS7 interrupt status 0 No interrupt request A 3 TOPIS6 TOP6 interrupt status 1 Interrupt request generated 4 5 No functions assigned 0 6 TOPIM7 TOP7 interrupt mask 0 Enables interrupt request O O 7 6 interrup
394. ers Address 0 Address 1 Address DO D7 D8 D15 H 0080 0000 Interrupt Vector Register IVECT H 0080 0006 SBI Control Register SBICR CANO Transmit Receive amp Error 0080 0060 Interrupt Control Register ICANOCR RTD Interrupt Control Register SIO2 3 Transmit Receive Interrupt 5 9 Interrupt Control Register H 0080 0068 Control Register ISIO23CR IDMA59CR i A DO Conversion Interrupt Control SIOO Transmit Interrupt Control H 0080 006 Register IADOCCR Register ISIOOTXCR H 0080 006 SIOO Receive Interrupt Control SIO1 Transmit Interrupt Control Register ISIOORXCR Register ISIO1TXCR 5101 Receive Interrupt Control DMAO 4 Interrupt Control H 0080 0070 Register ISIO1 RXCR Register IDMA04CR MJT Output Interrupt Control Register O MJT Output Interrupt Control Register H 0080 0072 IMJTOCRO IMJTOCR1 MJT Output Interrupt Control Register 2 MJT Output Interrupt Control Register H 0080 0074 IMJTOCR2 IMJTOCR3 MJT Output Interrupt Control Register 4 MJT Output Interrupt Control Register5 H 0080 0076 IMJTOCR4 5 MJT Output Interrupt Control Register MJT Output Interrupt Control Register7 H 0080 0078 IMJTOCR6 IMJTOCR7 MJT Input Interrupt Control Input Interrupt Control MJT Input Interrupt Control H 0080 007C Register 2 IMJTICR2 Register 3 IMJTICR3 MJT Input Interrupt Control H 0080 007E Register 4 IMJTICR4 Blank addresses are reserv
395. ers COMSL8CNT E CANO Message Slot9 Control Registers COMSL9CNT E CANO Message Slot10 Control Registers COMSL10CNT E CANO Message Slot11 Control Registers COMSL11CNT E CANO Message Slot12 Control Registers COMSL12CNT E CANO Message Slot13 Control Registers COMSL13CNT E CANO Message Slot14 Control Registers COMSL14CNT E CANO Message Slot15 Control Registers COMSL15CNT Address H 0080 1050 gt Address H 0080 1051 2 Address H 0080 1052 Address H 0080 1053 gt Address H 0080 1054 gt Address H 0080 1055 gt Address H 0080 1056 gt Address H 0080 1057 Address H 0080 1058 gt Address H 0080 1059 gt Address H 0080 105 gt Address H 0080 105 gt lt Address H 0080 105 gt Address H 0080 105D gt Address H 0080 105 gt Address H 0080 105F gt DO D8 1 2 3 4 5 6 D7 D15 TR RR RM RL RA ML TRSTAT TRFIN When reset H 00 gt D Bit Name Function R 0 0 Does not use message slot as transmit slot Q Transmit request 1 Uses message slot as transmit slot RR 0 Does not use message slot as receive slot Receive request 1 Uses message slot as receive slot RM 0 Transmits receives data frame Remote 1 Transmits receives remote frame RL 0 Enables automatic response for remote frame Q Automatic response inhibit 1 Disables automatic response for remote frame RA BasicCAN mode Remote active 0 Receives
396. erted by underflow 22 CQ by underflow Note This diagram does not show detail timing information Figure 10 4 14 Typical Operation in TIO Single shot Output Mode without Correction Function 10 117 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer 10 4 13 Operation in TIO Delayed Single shot Output Mode without Correction Function 1 Outline of TIO delayed single shot output mode In delayed single shot output mode the timer generates a pulse in width of reload 0 register set value 1 only once with the output delayed by an amount of time equal to counter set value 1 and then stops without performing any operation When after setting the counter and reload 0 register the timer is enabled by writing to the enable bit in software or by external input it starts counting down from the counter s set value synchronously with the count clock The first time the counter underflows the reload 0 register value is loaded into the counter causing it to continue counting down and the counter stops when it underflows next time The F F output waveform in delayed single shot output mode is inverted F F output levels change from low to high or vice versa when the counter underflows first time and next generating a single shot pulse waveform in width of reload 0 register set value 1 only once with the output delayed by an amount of time equal to first set value of
397. erve_only X amp outputs X 86 0 Z amp control 0 amp observe_only X amp outputs X 83 0 2 amp control 0 amp observe only X amp outputs X 80 0 2 amp control 0 amp observe_only X amp outputs X 77 0 Z amp control 0 amp observe_only X amp observe_only X amp output3 X 73 0 Z amp control 0 amp observe_only X amp output3 X 70 0 2 amp control 0 amp observe only X amp output3 X 67 0 Z amp control 0 amp observe_only X amp output3 X 64 0 Z amp control 0 amp Figure 19 5 12 BSDL Description for the 32171 12 14 19 26 Ver 0 10 1 9 JTAG 19 5 Boundary Scan Description Language 63 BC 4 P74 observe only X amp 62 BC_1 P74 output3 X 61 0 Z amp 61 BC 1 control 0 amp 60 BC 4 P75 observe only X amp 59 BC_1 P75 output3 X 58 0 2 amp 58 BC 1 control 0 amp 57 BC_4 P76 observe_only X amp 56 BC_1 P76 output3 X 55 0 Z amp 55 1 control 0 amp 54 BC 4 P77 observe only X amp 53 BC_1 P77 output3 X 52 0 2 amp 52 BC 1 control 0 amp 51 BC_4 P93 observe_only X amp 50 BC_1 P93 output3 X 49 0 Z amp 49 BC 1 control 0 amp 48 BC 4 P94 observe only X amp 47 BC_1 P94 output3 X 46 0 Z a
398. eserved areas Figure 3 4 11 Register Mapping of the SFR Area 9 3 18 Ver 0 10 ADDRESS SPACE 3 4 Internal ROM SFR Area Address 0080 1100 0080 1102 0080 1104 0080 1106 0080 1108 H 0080 110A H 0080 110C 0080 110E 0080 1110 0080 1112 0080 1114 0080 1116 0080 1118 0080 111A H 0080 111C 0080 111E H 0080 1120 H 0080 1122 H 0080 1124 H 0080 1126 H 0080 1128 H 0080 112A H 0080 112C H 0080 112 H 0080 1130 H 0080 1132 H 0080 1134 H 0080 1136 H 0080 1138 H 0080 113A H 0080 113C H 0080 113E H 0080 1140 H 0080 1142 H 0080 1144 H 0080 1146 H 0080 1148 H 0080 114A H 0080 114C H 0080 114E H 0080 1150 H 0080 1152 0 Address DO D7 CANO Message Slot 0 Standard IDO COMSLOSIDO 1 Address D8 D15 CANO Message Slot 0 Standard ID1 COMSLOSID1 CANO Message Slot 0 Extended 100 COMSLOEIDO CANO Message Slot 0 Extended ID1 COMSLOEID1 CANO Message Slot 0 Extended ID2 COMSLOEID2 CANO Message Slot 0 Data Length Register COMSLODLC CANO Message Slot 0 Data 0 COMSLODTO CANO Message Slot 0 Data 1 COMSLODT1 CANO Message Slot 0 Data 2 COMSLODT2 CANO Message Slot 0 Data 4 COMSLODT4 CANO Message Slot 0 Data 6 COMSLODT6 CANO Message Slot 0 Data 3 COMSLODT3 CANO Message Slot 0 Data 5 0 5100 5 CANO Message Slot 0 Data 7 COMSLODT7 CANO Message Slot 0 Ti me Stamp COMSLOTSP CANO M
399. esponding 10 bit Data Registers 0 15 and convert operations in steps to 2 above are reexecuted for the next channel to be converted In single shot scan mode the convert operation stops when A D conversion for one specified scan loop is completed 3 Continuous scan mode When comparison of the A D Successive Approximation Register s D15 bit in a specified channel is completed the content of the A D Successive Approximation Register is transferred to the corresponding 10 bit A D Data Registers 0 15 and convert operations in steps to above are reexecuted for the next channel to be converted During continuous scan mode the convert operation is executed continuously until scan operation is forcibly halted by setting the conversion stop bit Scan Mode Register 0 s D6 bit to 1 11 32 Ver 0 10 1 1 CONVERTERS 11 3 Functional Description of Converters 11 3 3 Comparator Operation When comparator mode single mode only is selected the A D converter functions as a comparator that compares analog input voltages with a preset comparison voltage When a comparison value is written to the successive approximation register the A D converter starts comparating the analog input voltage selected by the Single Mode Register 1 analog input selection bit with the value written to the successive approximation register Once comparate begins the following operation is automatically executed D The Sing
400. ess H 0080 OFF6 gt B TML1 Measure 1 Register TML1MR1H Address H 0080 OFF8 gt Bi TML1 Measure 1 Register TML1MR1L Address H 0080 gt B TML1 Measure 0 Register TML1MROH Address H 0080 OFFC gt B TML1 Measure 0 Register TML1MROL Address H 0080 gt DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 TML1MR3H TML1MROH 16 high order bits DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 TML1MR3L TML1MROL 16 low order bits When reset Indeterminate gt D Bit Name Function R 0 15 TML1MR3H 0H 32 bit counter value 16 high order bits TML1MR3L 0L 32 bit counter value 16 low order bits Note 1 These registers are a read only register Note 2 These registers must always be accessed in words 32 bits beginning with a word boundary The TML1 Measure Registers are used to latch counter contents upon event input The TML1 Measure Registers are configured with 32 bits the TML1MR3H 0H accommodating the 16 high order bits and the TML1MR3L 0L accommodating the 16 low order bits The TML1 Measure Registers are a read only register These registers must always be accessed in words 32 bits beginning with a word boundary 10 139 Ver 0 10 10 MULTIJUNCTION 5 10 6 TML Input related 32 bit Timer 10 6 7 Operation of TML Measure Input 1 Outline of TML measure input In TML measure input the counter starts counting up clock pulses upon deassertion of reset When event input measure regis
401. ess of transfer in such way that DO corresponds to A16 and D15 corresponds to A31 Because this register is comprised of a current register the value you get by reading this register is always the current value When DMA transfer finishes at which the Transfer Count Register underflows the value in this register if Address fixed is selected is the same source address that was set in it before DMA transfer began if Address incremental is selected the value in this register is the last transfer address 1 for 8 bit transfer or the last transfer address 2 for 16 bit transfer Make sure the DMA Source Address Register is always accessed in halfwords 16 bits beginning with an even address If accessed in bytes the value read from this register is indeterminate DMOSA DMS9SA A16 A31 of the source address By setting this register specify the source address of DMA transfer in internal I O space ranging from H 0080 0000 to H 0080 FFFF or in the RAM space The 16 high order bits of the source address A0 A15 are always fixed to H 0080 Use this register to set the 16 low order bits of the source address with DO corresponding to A16 and D15 corresponding to A31 Ver 0 10 9 2 4 Destination Address Registers DMAO Destination Address Register DMODA E Destination Address Register DM1DA E DMA2 Destination Address Register DM2DA E Destination Address Register DM3DA E DMA4 Dest
402. essage Slot 1 Standard 100 COMSL1SIDO CANO Message Slot 1 Standard 101 COMSL1SID1 CANO Message Slot 1 Extended IDO COMSL1EIDO CANO Message Slot 1 Extended ID1 COMSL1EID1 CANO Message Slot 1 Extended ID2 COMSL1EID2 CANO Message Slot 1 Data 0 COMSL1DTO CANO Message Slot 1 Data 2 COMSL1DT2 CANO Message Slot 1 Data Length Register COMSL1DLC CANO Message Slot 1 Data 1 COMSL1DT1 CANO Message Slot 1 Data 3 COMSL1DT3 CANO Message Slot 1 Data 4 COMSL1DT4 CANO Message Slot 1 Data 5 COMSL1DT5 CANO Message Slot 1 Data 6 COMSL1DT6 CANO Message Slot 1 Data 7 COMSL1DT7 CANO Message Slot 1 Time Stamp COMSL1TSP CANO Message Slot 2 Standard 100 COMSL2SIDO CANO Message Slot 2 Standard ID1 COMSL2SID1 CANO Message Slot 2 Extended IDO COMSL2EIDO CANO Message Slot 2 Extended ID2 COMSL2EID2 CANO Message Slot 2 Extended ID1 COMSL2EID1 CANO Message Slot 2 Data Length Register COMSL2DLC CANO Message Slot 2 Data 0 COMSL2DTO CANO Message Slot 2 Data 2 COMSL2DT2 CANO Message Slot 2 Data 1 COMSL2DT1 CANO Message Slot 2 Data 3 COMSL2DT3 CANO Message Slot 2 Data 4 COMSL2DT4 CANO Message Slot 2 Data 5 COMSL2DT5 CANO Message Slot 2 Data 6 COMSL2DT6 CANO Message Slot 2 Data 7 COMSL2DT7 CANO Message Slot 2 Ti Stamp COMSL2TSP CANO Message Slot Standard IDO COMSL3SIDO CANO Message Slot 3 Extended IDO COMSL3EIDO CANO Mess
403. ests in each channel The generated DMA request is cleared by writing a O to this bit If you write a 1 the value you wrote is ignored and the bit retains its previous value If a new DMA transfer request is generated for a channel whose DMA transfer request flag has already been set to 1 the next DMA transfer request is not accepted until the transfer under way in that channel is completed 3 REQSLn cause of DMAn request select bits D2 D3 These bits select the cause of DMA request in each DMA channel 4 TENLn DMAn transfer enable bit D4 Transfer is enabled by setting this bit to 1 so that the channel is ready for DMA transfer Conversely transfer is disabled by setting this bit to 0 However if a transfer request has already been accepted transfer in that channel is not disabled until after the requested transfer is completed 5 TSZSLn DMAn transfer size select bit D5 This bit selects the number of bits to be transferred in one DMA transfer operation unit of one transfer The unit of one transfer is 16 bits when TSZSL 0 or 8 bits when TSZSL 1 6 SADSLn DMAn source address direction select bit D6 This bit selects the direction in which the source address changes as transfer proceeds This mode can be selected from two choices address fixed or address incremental 7 DADSLn DAMn destination address direction select bit D7 This bit selects the direction in which the destination address changes as transfer
404. execution This special operation mode starts scan operation subsequently after executing conversion in single mode A D conversion or comparate To start this mode in software choose a software trigger using the Scan Mode Register 0 A D conversion start trigger select bit Then set the said register s A D conversion start bit to 1 during single mode conversion operation To start in hardware select hardware trigger using the Scan Mode Register 075 A D conversion start trigger select bit and enter the hardware trigger output event bus 3 specified by the said register while single mode conversion is in operation When a hardware trigger output event bus 3 is entered after selecting hardware trigger with the A D conversion start trigger select bits of both Single Mode Register 0 and Scan Mode Register 0 conversion is first performed in single mode and then after execution of it conversion is performed in scan mode An A D conversion interrupt request or a DMA transfer request can be generated at completion of single mode conversion in the specified channel or at completion of one cycle of scan operation To start 4 channel single shot scan mode subsequently after single mode conversion on ADON5 gt Instructed to start scan mode conversion Single mode ADOIN ADOIN1 ADOIN2 ADOIN gt conversion starts ong 0 0 OINS Completed 10 bit A DO data register ADODT5 ADODTO ADODT1 ADODT2 ADODT3
405. ext conversion result transferred allowing the content to be read out at any time 11 28 Ver 0 10 11 11 2 8 8 bit A D Data Registers E 8 bit A DO Data Register 0 ADOBDTO E 8 bit A DO Data Register 1 ADO8DT1 E 8 bit Data Register 2 ADO8DT2 E 8 bit A DO Data Register ADO8DT3 E 8 bit A DO Data Register 4 ADO8DT4 E 8 bit A DO Data Register 5 ADOBDT5 E 8 bit A DO Data Register 6 ADOBDT6 E 8 bit A DO Data Register 7 ADO8DT7 E 8 bit A DO Data Register 8 ADO8DT8 E 8 bit A DO Data Register 9 ADO8DT9 E 8 bit A DO Data Register 10 0080710 E 8 bit A DO Data Register 11 ADO8DT11 E 8 bit A DO Data Register 12 0080712 E 8 bit A DO Data Register 13 ADO8DT13 E 8 bit A DO Data Register 14 0080714 E 8 bit A DO Data Register 15 0080715 D8 9 10 11 A D CONVERTERS 11 2 A D Converter Related Registers Address H 0080 00D1 gt Address H 0080 0003 gt Address H 0080 0005 gt Address H 0080 00D7 gt Address H 0080 0009 gt Address H 0080 00DB Address H 0080 00DD gt Address H 0080 00DF gt Address H 0080 00 1 gt Address H 0080 00 gt Address H 0080 00 5 gt Address H 0080 00E7 gt Address H 0080 00 9 gt Address H 0080 00 gt Address H 0080 OOED gt Address H 0080 00EF gt 13 14 D15 ADO8DTO ADO8DT15 D Bit Name 8 15 ADOS8DTO ADOSDT15 8 bit A DO data When reset Indeterminate Function R 8 bit
406. f the voltage fed from the D A converter into the comparator is determined according to changes of the content of the A D Successive Approximation Register Shown below are the equations used to calculate the comparison voltage Vref When the content of the A D Successive Approximation Register 0 Vref V 2 0 When the content of the A D Successive Approximation Register 1 to 1 023 Vref V reference voltage VREFO 1 024 x content of the Successive Approximation Register 0 5 11 31 Ver 0 10 1 1 5 11 3 Functional Description of Converters The comparison result is stored in the 10 bit Data Register ADODTn corresponding to each converted channel Also the 8 high order bits of the 10 bit A D conversion result can be read out from the 8 bit Data Register ADO8DTn The following shows the procedure for A D conversion by successive approximation in each operation mode 1 Single mode The convert operation stops when comparison of the A D Successive Approximation Register s D15 bit is completed The content A D conversion result of the A D Successive Approximation Register is transferred to the 10 bit A D Data Registers 0 15 for the converted channel 2 Single shot scan mode When comparison of the A D Successive Approximation Register s D15 bit in a specified channel is completed the content of the A D Successive Approximation Register is transferred to the corr
407. f TOP6 TOP7 Clock Enable Inputs 10 56 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer TOP8 10 Control Register TOP810CR Address H 0080 02 gt 12 13 14 015 DO 1 2 3 4 5 6 7 8 9 10 11 TOP When reset H 0000 gt D Bit Name Function R 0 1 No functions assigned 0 2 3 10 TOP10 operation mode selection 00 Single shot output mode 2 4 5 TOP9M 9 operation mode selection 01 Delayed single shot output mode 6 7 TOP8M TOP8 operation mode selection 1X Continuous output mode 8 10 No functions assigned 0 11 TOP810ENS 0 No selection TOP8 10 enable source selection 1 Input event bus 3 12 13 No functions assigned 0 14 15 810 5 00 Clock bus 0 8 10 clock source selection 01 Clock bus 1 10 Clock bus 2 01 Clock bus 3 Note 1 This register must always be accessed in halfwords Note 2 Always make sure the counter has stopped and is idle before setting or changing operation modes 10 57 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer Clock bus Input event bus 3210 3210 5 4 8 Helk a 9 Ck 10 S Selector Note This diagram is shown for the explanation of TOP control registers and is partly omitted
408. ferred from transmit buffer to transmit shift register transmission starts Cleared D7X D6 DOXPAB ST ST Transmit interrupt 4 v Note 4 v sI SIO transmit interrupt Transmit interrupt Note 5 J u Note 1 Interrupt request accepted Processing by software Note 1 Note 2 When transmit finished interrupt is enabled timing Note interrupt request bit cleared Note 4 Note 5 buffer is thereby emptied Change of the Interrupt Controller SIO Transmit Interrupt Control Register interrupt request bit The Interrupt Controller IVECT register is read or SIO Transmit Interrupt Control Register Transmit interrupt request is generated when transmission is enabled Even after transmit data is written to the transmit buffer a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit Note 2 Note 3 S yt Interrupt generation DMA transfer can also be requested at the same Figure 12 6 5 Example of UART Transmission Transmitted Only Once with Transmit Interrupt Used 12 50 Ver 0 10 1 2 SERIAL I O 12 6 Transmit Operation in UART Mode UART on transmit side UART on receive side TXD i RXD UART on transmit side Set Transmit enable bit ER
409. flag overload flag Overload delimiter Interframe space In an error active state 3 0 ISOF SOF of next frame Bus idle Intermission In an error passive state s 3 8 0 5 SOF SOF of next frame Bus idle Suspend transmission Intermission Numbers in each field denote the number of bits Figure 13 3 2 CAN Protocol Frames 2 13 54 Ver 0 10 1 3 CAN MODULE 13 3 CAN Protocol Initial settings Error active state Transmit error counter 2 128 or Receive error counter 2 128 11 consecutive recessive bits detected on CAN bus 128 times or reset by software Transmit error counter lt 128 and Receive error counter lt 128 Bus off state Error passive state pp Transmit error counter gt 255 Figure 13 3 3 CAN Control Error States The CAN controller assumes one of the following three error states depending on the transmit error and receive error counter values 1 Error active state This is a state where almost no errors have occurred When an error is detected an active error flag is transmitted Immediately after being initialized the CAN controller is in this state 2 Error passive state This is a state where many errors have occurred When an error is detected a passive error flag is transmitted 3 Bus off state This is a state where a large number of errors have occurred CAN communi
410. fter the timer is enabled by writing to the enable bit in software the counter starts counting down synchronously with the count clock When a capture signal is entered from an external device the counter value at that point in time is written to the measure register Especially in measure clear input mode the counter value is initialized to H FFFF upon capture from which the counter starts counting down again When the counter underflows after reaching the minimum count it starts counting down from H FFFF again In measure free run input mode the counter continues counting down even after capture and upon underflow recycles to H FFFF from which it starts counting down again To stop the counter disable count by writing to the enable bit in software 10 107 Ver 0 10 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer Measure event Measure event Enabled writing to enable bit occurs occurs Count clock Enable bit ca M C LC EM D ME CLE CM Mr CM EU MU LEE Indeterminate 22 2 value Counter H 0000 RR A RUE NE IET e Miu Une Measure register Indeterminate x H 7000 X H 9000 gt 22 lt lt TIN interrupt interrupt by external event input 24 external event input TIO interrupt TIO interrupt by underflow Note This
411. g pin port X for high level output mode Note Check RAM contents against backup RAM check data Error a Initialize RAM y Initial each internal circuit y 8 To main routine Note For wakeup from power outage RAM backup mode settings for port X are unnecessary Figure 17 4 1 Wakeup Processing 17 9 Ver 0 10 17 BACKUP MODE 17 4 Exiting RAM Backup Mode Wakeup This is a blank page 17 10 Ver 0 10 CHAPTER 18 OSCILLATION CIRCUIT 18 1 Oscillator Circuit 18 2 Clock Generator Circuit 1 8 OSCILLATION CIRCUIT 18 1 Oscillator Circuit 18 1 Oscillator Circuit The 2 contains an oscillator circuit that supplies operating clocks for the CPU core internal peripheral I O and internal memory The frequency fed to the clock input pin XIN is multiplied by 4 by the internal PLL circuit to produce the CPU clock which is the operating clock for the CPU core and internal memory The frequency of this clock is divided by 2 in the subsequent circuit to produce the internal peripheral clock which is the operating clock for the internal peripheral I O 18 1 1 Example of an Oscillator Circuit A clock generating circuit can be configured by connecting a ceramic or crystal resonator between the XIN and XOUT pins external to the chip Figure 18 1 1 below shows an example of a system clock generating circuit using a resonator connected exte
412. g the TRFIN Transmit Receive Finished bit Write H AE or H 00 to the CAN Message Control Register COMSLnONT to clear the TRFIN bit to 0 After this write the slot operates as follows Value written to Slot operation after write COMSLnCNT H AE Operates as a data frame receive slot Overwrite can be verified by ML bit H 00 The slot stops transmit receive operation Note 1 If message lost check by the ML bit is needed write H AE to the COMSLnONT register as you clear the TRFIN bit Note 2 If you clear the TRFIN bit by writing H AE or H OO it is possible that new data will be stored in the slot while still reading a message from the slot Note 3 The received data frame cannot be read out by writing H AO to the register If you clear the TRFIN bit by writing H AO the slot performs remote frame transmit operation 2 Reading out from the message slot Read out a message from the message slot 3 Checking the TRFIN Transmit Receive Finished bit Read the CAN Message Control Register to check the TRFIN Transmit Receive Finished bit CD When TRFIN Transmit Receive Finished bit 1 It means that new data was stored in the slot while still reading out from the slot in 2 In this case the data read out in 2 may contain an indeterminate value Therefore reexecute beginning with clearing of the TRFIN Transmit Receive Finished bit in 1 2 When TRFIN Transmit Receive Finished bit 0 It means that th
413. gA gt 9 n tc m LI sende 5 E DBO DB15 Ln Don t Care 222222 c onu ee Cee 5 E EEPO EE EE T N gt Y L S at lt o gA El g A PERF TP TA So E pe ay i sea FS DE E reuersi d eror eee ed 3 mme Pg Be s ug s z Write DBO DB15 Don t Care Circles O above indicate points at which signals are sampled Note 2 BCLK is not output Note 1 Figure 16 3 14 Read Write Timing for Access with 2 Internal and n External Wait Cycles Ver 0 10 16 19 16 WAIT CONTROLLER 16 3 Typical Operation of the Wait Controller This is a blank page 16 20 Ver 0 10 CHAPTER 17 BACKUP MODE 17 1 Outline 17 2 Example of RAM Backup when Power is Down 17 3 Example of RAM Backup for Saving Power Consumption 17 4 Exiting RAM Backup Mode Wakeup 1 7 RAM BACKUP MODE 17 1 Outline 17 1 Outline In RAM backup
414. ge Slot 7 Data 1 COMSL7DT1 CANO Message Slot 7 Data 3 COMSL7DT3 CANO Message Slot 7 Data 4 COMSL7DT4 CANO Message Slot 7 Data 5 COMSL7DT5 CANO Message Slot 7 Data 6 COMSL7DT6 CANO Message Slot 7 Data 7 COMSL7DT7 CANO Message Slot 7 Ti me Stamp COMSL7TSP CANO Message Slot 8 Standard IDO COMSL8SIDO CANO Message Slot 8 Standard ID1 COMSL8SID1 CANO Message Slot 8 Extended IDO COMSL8EIDO CANO Message Slot 8 Extended ID1 COMSL8EID1 CANO Message Slot 8 Extended ID2 COMSL8EID2 CANO Message Slot 8 Data Length Register COMSL8DLC CANO Message Slot 8 Data 0 COMSL8DTO CANO Message Slot 8 Data 1 COMSL8DT1 CANO Message Slot 8 Data 2 COMSL8DT2 CANO Message Slot 8 Data 3 COMSL8DT3 CANO Message Slot 8 Data 4 COMSL8DT4 CANO Message Slot 8 Data 5 COMSL8DT5 CANO Message Slot 8 Data 6 COMSL8DT6 CANO Message Slot 8 Data 7 COMSL8DT7 CANO Message Slot 8 Ti CANO Message Slot 9 Standard IDO COMSL9SIDO me Stamp COMSL8TSP CANO Message Slot 9 Standard ID1 COMSL9SID1 CANO Message Slot 9 Extended IDO COMSL9EIDO CANO Message Slot 9 Extended ID1 COMSL9EID1 CANO Message Slot 9 Extended ID2 COMSL9EID2 CANO Message Slot 9 Data Length Register COMSL9DLC CANO Message Slot 9 Data 0 COMSL9DTO CANO Message Slot 9 Data 1 COMSL9DT1 CANO Message Slot 9 Data 2 COMSL9DT2 CANO Message Slot 9 Data 4 COMSL9DT4 CANO Message
415. gister 4 FCNT4 Address H 0080 07E5 gt D8 9 10 11 12 13 14 D15 When reset 00 gt D Bit Name Function R 8 14 functions assigned 0 15 FRESET 0 No operation performed O O Reset flash 1 Reset the flash memory The Flash Control Register 4 FCNT4 controls canceling program erase operation in the middle and initializing each status bit of Flash Status Register 2 FSTAT2 When the FRESET bit is set to 1 program erase operation is canceled in the middle and each status bit of FSTAT2 is initialized H 80 The FRESET bit is effective only when the FENTRY bit 1 Information on FRESET bit is ignored unless the FENTRY bit 1 Make sure that when programming or erasing the flash memory the FRESET bit remains 0 6 12 Ver 0 10 INTERNAL MEMORY 6 4 Registers Associated with the Internal Flash Memory FENTRY 0 FENTRY 1 Y Program erase flash memory 5 Program erase terminated normally FRESET 1 FRESET 0 Program erase flash memory Figure 6 4 3 Example for Using the FCNT4 Register 6 13 Ver 0 10 6 INTERNAL MEMORY 6 4 Registers Associated with the Internal Flash Memory 6 4 4 Virtual Flash L Bank Registers E Virtual Flash L Bank Register 0 FELBANKO Address H 0080 07 8 gt MOD DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 When reset 0000 gt D Bit Name Function R 0 MODENL 0 Disabl
416. gister value can be changed at the same time you write to the register Transmit receive operations using DMA To transmit receive data in DMA request mode enable the DMAC to accept transfer requests by setting the DMA Mode Register before you start serial communication About overrun error If all bits of the next receive data are received in the SIO Receive Shift Register before you read out the SIO Receive Buffer Register an overrun error occurs the receive data is not stored in the Receive Buffer Register and the Receive Buffer Register retains the previously received data Once an overrun error occurs no receive data is stored in the Receive Buffer Register although receive operation is continued To restart reception normally you need to temporarily clear the receive enable bit before you restart This is the only way you can clear the overrun error flag 12 59 Ver 0 10 1 2 SERIAL 12 9 Precautions on Using UART Mode Flags indicating the status of UART receive operation Following flags are available that indicate the status of receive operation during UART mode SIO Receive Control Register receive status bit SIO Receive Control Register receive finished bit SIO Receive Control Register receive error sum bit SIO Receive Control Register overrun error bit SIO Receive Control Register parity error bit SIO Receive Control Register framing error bit The manner in which the receive finished bit a
417. gnals shown below These signals can be used in external extension mode or processor mode 1 Address The 32171 outputs a 19 bit address A12 A30 for addressing any location in 1 Mbytes of space The least significant A31 is not output and in external write cycles the 32171 outputs BHW and BLW signals to indicate the valid byte position at which to write on the 16 bit data bus In read cycles the 32171 reads data always in 16 bits transferring only the data read from the valid byte position of the bus 2 Chip select 50 CS1 These signals are output in external extension mode or processor mode with 50 and CS1 specifying an extended external area of 2 Mbytes each The 50 signal points to a 2 Mbyte area in processor mode or a 1 Mbyte area in external extension mode For details refer to Chapter 3 Address Space 3 Read strobe RD Output during external read cycle this signal indicates the timing at which to read data from the bus This signal is driven high when writing to the bus or accessing the internal function 4 Byte High Write Byte High Enable BHW BHE The pin function changes depending on the Bus Mode Control Register BUSMODC When BUSMOD 0 and this signal is Byte High Write BHW during external write access it indicates that the upper byte DBO DB7 of the data bus is the valid data to transfer During external read and when accessing the internal function it outputs a high When BUSMOD 1 and
418. gt D Bit Name Function R 8 9 No functions assigned 10 15 SID5M SID10M 0 ID not checked O Standard ID5 to standard ID10 1 ID checked 13 30 Ver 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers Three registers are used in acceptance filtering Global Mask Register Local Mask Register A and Local Mask Register B The Global Mask Register is used for message slots 0 13 while Local Mask Registers A and B are used for message slots 14 and 15 respectively When a bit in this register is set to 0 its corresponding ID bit is masked assumed to have matched during acceptance filtering When a bit in this register is set to 1 its corresponding ID bit is compared with the receive ID during acceptance filtering and when it matches the ID set for the message slot the received data is stored in it Note 1 SIDOM corresponds to the MSB of standard ID Note 2 The Global Mask Register can only be changed when none of slots 0 13 have receive requests set Note 3 The Local Mask Register A can only be changed when slot 14 does not have a receive request set Note 4 The Local Mask Register B can only be changed when slot 15 does not have a receive request set 13 31 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers CANO Global Mask Register Extended 100 COGMSKEO lt Address H 0080 102 gt E CANO Local Mask Register A Extended 100 COLMSKAEO lt Address H 0080 1032 E CANO Local Mask Register
419. gt To interrupt Transmit interrupt controller TXD2 SIO2 Transmit Shift Register n Transmit receive Receive interrupt control circuit Transmit DMA transfer request DMAC7 RXD2 gt 5102 Receive Shift Register Receive DMA transfer request To DMACS A Note 1 When BCLK is selected the BRG set value is subject to limitations Note 2 SIO2 does not have the SCLKI SCLKO function Figure 12 1 1 Block Diagram of 5100 5105 12 5 Ver 0 10 12 12 2 Serial Related Registers The diagram below shows a serial I O related register map SERIAL I O 12 2 Serial I O Related Registers H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 H 0080 Address 0100 0102 0110 0112 0114 0116 0120 0122 0124 0126 0130 0132 0134 0136 A 22 C C 0 Address 1 Address DO D7 D8 D15 1023 Interrupt Status Register 51003 Interrupt Mask Register 51235 SIO3MASk 51003 Cause of Receive Interrupt Select Register SIO3SEL C 2 C 5100 Transmit Control Register SOTCNT 5 0 Transmit Receive Mode Register SOMOD SIOO Transmit Buffer Register SOTXB SIOO Receive Buffer Register SORXB 5100 Receive Control Register SORCNT SIO0 Baud Rate Register SOBAUR 27 CC SIO1 Transmit Control Register S1TCNT SIO1 Transmit Receive Mode Register S1MOD
420. h are used in acceptance filtering of received messages 6 Settings when running in BasicCAN mode Setthe CAN Extended ID Register IDE14 and IDE15 bits We recommend setting the same value in these bits Set IDs for message slots 14 and 15 Set the Message Control Registers 14 and 15 for data frame reception H 40 7 Setting CAN module operation mode Using the CAN Control Register CANOCNT select the CAN module s operation mode BasicCAN or loopback mode and the clock source for the time stamp counter 8 Releasing the CAN module from reset After you finished settings 1 through 7 above clear the CAN Control Register CANOCNT s forcible reset bit FRST and reset bit RST to 0 Then after detecting 11 consecutive recessive bits on the CAN bus the CAN module becomes ready to communicate 13 57 Ver 0 10 13 MODULE 13 4 Initializing the CAN Module Initialize CAN module Y Set Input output Port Operation Mode Register Set Interrupt Controller Set CAN Related Interrupt Mask Register uu Set CAN Configuration Register Set ID Mask Register Set CAN operation mode Negate CAN reset CAN module initialization completed e Set interrupt priority Set CAN Error Interrupt Set CAN Slot Interrupt Mask Register Mask Register Enable disable CAN Enable disable interrupt bus error interrupt to be ge
421. he PSW C bit is reflected in this register This register is a read only register writes to this register by MVTC instruction are ignored 0 MSB 31 LSB CBR O00000000000000000000000000000 0 C ee es Le he a 2 3 3 Interrupt Stack Pointer SPI CR2 User Stack Pointer SPU CR3 The Interrupt Stack Pointer SPI and User Stack Pointer SPU hold the current address of the stack pointer These registers can be accessed as general purpose register R15 In this case whether R15 is used as SPI or as SPU depends on the PSW s Stack Mode SM bit SPI SPI 0 MSB 31 LSB SPU SPU 1 1 1 2 3 4 Backup CR6 The Backup PC is a register used to save the value of the Program Counter PC when an EIT occurs Bit 31 is fixed to 0 When an EIT occurs the value held in the PC immediately before the EIT occurred or the value of the next instruction is set in this register When the RTE instruction is executed the saved value is returned from the BPC to the PC However the two low order bits of the PC when thus returned are always fixed to 00 control always returns to word boundaries 0 MSB 31 LSB BPC BPC 0 2 5 Ver 0 10 2 2 4 Accumulator 2 4 Accumulator The accumulator ACC is a 56 bit register used by DSP function instructions When read out or written to it
422. he TOP correction register In this case one down count in the clock period during which the correction was performed is canceled Therefore note that the counter value actually is corrected by correction register value 1 For example if the initial counter value is 7 and you write a value 3 to the correction register when the counter has counted down to 3 then the counter underflows after a total of 12 counts Count value 7 1 3 1 12 1 2 3 4 5 6 7 8 9 10 11 A Count clock 4 f f f t f f f f f Prescaler delay A Enable Counter Reload H FFFF register Correction 3 register Interrupt P Underflow Note 1 What you actually see in the cycle immediately after reload is the previous counter value and not 7 Note 2 This diagram does not show detail timing information Figure 10 3 11 Example of Counting in TOP Single shot Output Mode When Count is Corrected 10 68 Ver 0 10 10 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer When writing to the correction register be careful not to cause the counter to overflow Even when the counter overflows due to correction of counts no interrupt is generated for the occurrence of overflow In the example below the reload register has the initial value H 8000 set in it When the timer starts the reload register value is loaded into the counter causing it to
423. he correction register Correction of the counter is performed synchronously with a clock period next to the one in which the correction value was written to the TOP correction register In this case one down count in the clock period during which the correction was performed is canceled Therefore note that the counter value actually is corrected by correction register value 1 For example if the initial counter value is 10 and you write a value 3 to the correction register when the counter has counted down to 5 then the counter underflows after a total of 15 counts 10 61 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer 10 38 Enable Control Register TOPO 10 External Enable Permit Register TOPEEN Address H 0080 2 gt 12 13 14 015 DO 1 2 3 4 5 6 7 8 9 10 11 10 TOP9 TOP8 TOP6 5 4 TOP3 2 TOP1 TOPO EEN EEN EEN EEN EEN EEN EEN EEN EEN EEN EEN D Bit Name Function R 0 4 No functions assigned 0 5 TOP10EEN TOP10 external enable permit 0 Disables external enable 6 TOP9EEN TOP9 external enable permit 1 Enables external enable 7 TOP8EEN TOP8 external enable permit 8 TOP7EEN TOP7 external enable permit 9 TOP6EEN TOP6 external enable permit 10 TOP5 external enable permit 11 TOP4EEN TOP4 external enable permit 12 ex
424. he flash memory The flash memory protection becomes invalid unlocked by setting the FPROT bit to 1 so that any blocks protected by the lock bit can be erased or programmed To set the FPROT bit to 1 write a 0 and then a 1 to the FPROT bit in succession while the FENTRY bit 1 FPROT bit is cleared to 0 by writing a 0 to the FPROT bit and setting the FP pin low or the FENTRY bit to 0 immediately after reset NO FENTRY 1 YES FENTRY 1 T v FPROT 0 FPROT is not set to 1 if write cycle to any other area occurs during this time Y FPROT 1 2 Figure 6 4 2 Protection Unlocking Flow 6 10 Ver 0 10 INTERNAL MEMORY 6 4 Registers Associated with the Internal Flash Memory Flash Controle Register 3 FCNT3 Address H 0080 07 4 gt DO 1 2 3 4 5 6 D7 FELEVEL When reset 00 gt D Bit Name Function R Ww 0 6 No functions assigned 0 7 FELEVEL 0 Normal level Raise erase margin 1 Raise erase margin The Flash Control Register 3 FCNT3 controls the depth of erase levels when erasing the internal flash memory with one of erase commands By setting the FELEVEL bit to 1 the flash memory erase level can be deepened which will result in an increased reliability margin 6 11 Ver 0 10 6 INTERNAL MEMORY 6 4 Registers Associated with the Internal Flash Memory E Flash Controle Re
425. he status of receive operation in CSIO mode SIO Receive Control Register receive status bit SIO Receive Control Register receive finished bit SIO Receive Control Register receive error bit SIO Receive Control Register overrun error bit After reception is completed you may read out the content of the SIO Receive Buffer Register but if the serial I O finishes receiving the next data before you read an overrun error occurs In this case the data received thereafter is not transferred to the SIO Receive Buffer Register To restart reception temporarily clear the receive enable bit to 0 and initialize the receive control block before you restart The said receive enable bit can be cleared when there are no receive errors note encountered by reading the lower byte from the SIO Receive Buffer Register or clearing the REN receive enable bit If any receive error has occurred it can only be cleared by clearing the REN receive enable bit and cannot be cleared by reading the lower byte from the SIO Receive Buffer Register Note Overrun error is the only error that can be detected during reception in CSIO mode 12 37 Ver 0 10 12 SERIAL 12 4 Receive Operation CSIO Mode 12 4 6 Typical CSIO Receive Operation The following shows a typical receive operation in CSIO mode CSIO on receive side CSIO on transmit side SCLKO gt SCLKI MIT TXD RXD Internal cloc
426. hed Y Reload 0 register H 1000 X e H 8000 Reload 1 register H 2000 H 9000 New PWM Old PWM output period output period gt F F output Operation by new reload value written je Enlarged view gt lt New PWM output period Count clock Counter H 0001 H 0000 H FFFF HTFFF H 7FFE Interrupt F1 by underflow Reload 0 register H1000 X H 8000 Reload 1 register 000 H 9000 Reload 1 buffer H2000 gt X H9000 F F output Timing at which reload 1 Zl and reload 0 registers are updated PWM period latched E Note This diagram does not show detail timing information b When reload register updates take effect in the next period reflected one period later Write to reload 0 Write to reload 1 reload 1 data latched Reload 0 register H 1000 ok H 8000 v Reload 1 register H 2000 X Q H 9000 oro Old PWM Old PWM output period 4 output period F F output 1 Operation by old reload value ET Enlarged view A 2 gt lt Old PWM output period Count clock l Counter 000 H 000 j H H OFFF H OFFE 1 0 Interrupt by underflow Reload 0 register H 1000 ee Reload 1 register H 2000 H 9000 9 Reload 1 buffer H2000 E H 9000 F F output PWM period
427. hen transfer is enabled this register is protected in hardware so that any data you write to this register is ignored Rewriting the DMA source and DMA destination addresses on different channels by DMA transfer In this case you are writing to the DMAC related registers while DMA is enabled but this practically does not present any problem However you cannot DMA transfer to the DMAC related registers on the local channel itself in which you are currently operating 9 38 Ver 0 10 9 9 4 Precautions about the DMAC 9 4 Precautions about the DMAC Manipulating DMAC related registers by DMA transfer When manipulating DMAC related registers by means of DMA transfer e g reloading the DMAC related registers initial values by DMA transfer do not write to the DMAC related registers on the local channel itself through that channel If this precaution is neglected device operation cannot be guaranteed Only if residing on other channels you can write to the DMAC related registers by means of DMA transfer For example you can rewrite the DMAn Source Address and DMAn Destination Address Registers on channel 1 by DMA transfer through channel 0 About the DMA Interrupt Request Status Register When clearing the DMA Interrupt Request Status Register be sure to write 1s to all bits but the one you want to clear The bits to which you wrote 1s retain the previous data they had before the write About the stable oper
428. ic response data frame transmission for remote frame reception is desired Write H 60 to the CAN Message Slot Control Register to set the RR Receive Request and RM Remote bits to 1 When automatic response data frame transmission for remote frame reception is not needed Write H 70 to the CAN Message Slot Control Register to set the RR Receive Request RM Remote and RL Automatic Response Inhibit bits to 1 Note In BasicCAN mode slots 14 and 15 although capable of receiving remote frames cannot automatically respond to remote frame reception 13 76 Ver 0 10 13 CAN MODULE 13 8 Receiving Remote Frames Remote frame reception procedure Initialize CAN Message Slot Control Register Read CAN Message Slot Control Register TRSTAT bit 0 Set ID in message slot Set Extended ID Register Set CAN Message Slot Control Register Settings completed Write H 00 Verify that reception is idle Standard ID or extended ID Write H 60 receive request remote automatic response enable Write H 70 receive request remote automatic response disable Figure 13 8 1 Remote Frame Receive Procedure 13 77 Ver 0 10 1 3 CAN MODULE 13 8 Receiving Remote Frames 13 8 2 Remote Frame Receive Operation The following describes remote frame receive operation The operations described below are automatically performed in hardware 1 Setting the RA Remote Active bit When H 60 T
429. ied turns to an invalid level before the counter underflows the counter temporarily stops counting and when a valid level signal is entered again it is reloaded with the initial count and restarts counting The timer stops at the same time the counter underflows or count is disabled by writing to the enable bit An interrupt can be generated by a counter underflow 3 PWM output mode without correction function In PWM output mode the timer uses two reload registers to generate a waveform with a given duty cycle 10 84 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer When after setting the initial values in reload 0 and reload 1 registers the timer is enabled by writing to the enable bit in software or by external input it loads the reload 0 register value into the counter synchronously with the count clock letting the counter start counting down The first time the counter underflows the reload 1 register value is loaded into the counter letting it continue counting Thereafter the counter is reloaded with the reload 0 and reload 1 register values alternately each time an underflow occurs The F F output waveform in PWM output mode is inverted at count startup and upon each underflow The timer stops at the same time count is disabled by writing to the enable bit and not in synchronism with PWM output period An interrupt can be generated when the counter underflows every other time second time
430. ift Register is transferred to the SIO Receive Buffer Register This register is a read only register For 7 bit data UART mode only data is set in bits D9 D15 with D8 and D7 always set to 0 For 8 bit data data is set in bits D8 D15 with D7 always set to O After reception is completed you may read out the content of the SIO Receive Buffer Register but if the serial I O finishes receiving the next data before you read the previous data an overrun error occurs In this case the data received thereafter is not transferred to the Receive Buffer Register To restart reception normally clear the Receive Control Register s REN receive enable bit to O Note For 7 bit and 8 bit data the register can be accessed bytewise 12 19 Ver 0 10 SERIAL I O 1 2 12 2 Serial Related Registers 12 2 7 SIO Receive Control Registers 5100 Receive Control Register SORCNT 5101 Receive Control Register S1RCNT E 5102 Receive Control Register S2RCNT Address H 0080 0116 Address H 0080 0126 Address H 0080 0136 DO 1 2 3 4 5 6 D7 RSTAT RFIN REN OVR PTY FLM ERS When reset H 00 gt D Bit Name Function R 0 No functions assigned 0 zz 1 RSTAT 0 Reception stopped O Receive status bit 1 Reception in progress 2 RFIN 0 No data in receive buffer register O Receive completed bit 1 Data exists in receive buffer register 3 REN 0 D
431. ime factor necessary to calculate the conversion time D Start dummy time A time from when the CPU executed the A D conversion start instruction to when the A D converter starts A D conversion 2 A D conversion execution cycle time Comparate execution cycle time End dummy time A time from when the A D converter finished A D conversion to when the CPU can stably read out this conversion result from the A D data register Scan to scan dummy time A time during single shot or continuous scan mode from when the A D converter finished A D conversion in a channel to when it starts A D conversion in the next channel The equation to calculate the A D conversion time is as follows A D conversion time Start dummy time Execution cycle time Scan to scan dummy time Execution cycle time Scan to scan dummy time Execution cycle time Scan to scan dummy time Execution cycle time End dummy time Note Shown are the conversion time required for the second and subsequent channels to be converted in scan mode 11 34 Ver 0 10 11 5 11 3 Functional Description of Converters Single mode Scan mode A D conversion Convert operation Transferred to A D start trigger begins data register Completed Channel 0 Channel 1 can to scan Start dummy Execution cycle dummy Executioncycle a Last channel n Execution cycle End dummy Figure 11 3 3
432. in the flash memory or apply reset to enter normal mode Flash Boot ROM memory Flash write Write data data External device M32R E Figure 6 5 4 Procedure for Writing to Internal Flash Memory when the write program already exists in the flash memory 6 20 Ver 0 10 INTERNAL MEMORY 6 5 Programming of the Internal Flash Memory Write to flash memory by flash rewrite program Flash rewrite Flash mode Flash mode starts turned on turned off RESET ort N MODO MOD L Single chip or extended external FP H or L FENTRY lt gt lt gt Flash rewrite program transferred to RAM Figure 6 5 5 Internal Flash Memory Write Timings when the write program already exists in the flash memory 6 21 Ver 0 10 6 INTERNAL MEMORY 6 5 Programming of the Internal Flash Memory 6 5 2 Controlling Operation Mode during Programming Flash The device s operation modes are set by MODO MOD1 and Flash Control Register 1 FCNT1 FENTRY bit The table below lists operation modes that may be set during flash write Table 6 5 1 Operation Modes Set during Flash Write FP MODO MOD1 FENTRY NorE Operation Mode Reset Vector Entry Vector Entry 0 0 0 Single chip mode Start address of Flash area 1 0 0 0 flash memory H 0000 0080 H 0000 000
433. ination Address Register DM4DA DMAS Destination Address Register DM5DA E DMAG Destination Address Register DM6DA DMAT Destination Address Register DM7DA E DMAG Destination Address Register DM8DA E DMAO9 Destination Address Register DM9DA DMAC 9 2 DMAC Related Registers Address H 0080 0414 gt Address H 0080 0424 Address H 0080 0434 gt Address H 0080 0444 gt Address H 0080 0454 gt Address H 0080 041C gt Address H 0080 042 gt Address H 0080 043 gt Address H 0080 044C gt Address H 0080 045 gt 10 11 12 13 14 015 D Bit Name Function When reset Indeterminate gt R Ww 0 15 DMODA DM9DA A16 A31 of the destination address O A0 A15 are fixed to H 0080 Note This register must always be accessed in halfwords The DMA Destination Address Register is used to set the destination address of DMA transfer in such a way that DO corresponds to A16 and D15 corresponds to A31 Because access to this register is comprised of a current register the value you get by reading this register is always the current value When DMA transfer finishes at which the Transfer Count Register underflows the value in this register if Address fixed is selected is the same destination address that was set in it before DMA transfer began if Address incremental is selected the value in this register is the last transfer address 1 for 8 bit transfer or the last transfer address
434. ine of Each Mode of TOP Each mode of TOP is outlined below For each TOP channel only one of the following modes can be selected 1 Single shot output mode In single shot output mode the timer generates a pulse in width of reload register set value 1 only once and then stops without performing any operation When after setting the reload register the timer is enabled by writing to the enable bit in software or by external input the content of the reload register is loaded into the counter synchronously with the count clock letting the counter start counting The counter counts down clock pulses and stops when it underflows after reaching the minimum count The F F output waveform in single shot output mode is inverted at startup and upon underflow generating a single shot pulse waveform in width of reload register set value 1 only once Also an interrupt can be generated when the counter underflows 2 Delayed single shot output mode In delayed single shot output mode the timer generates a pulse in width of reload register set value 1 only once with the output delayed by an amount of time equal to counter set value 1 and then stops without performing any operation When after setting the counter and reload register the timer is enabled by writing to the enable bit in software or by external input it starts counting down from the counter s set value synchronously with the count clock The first time the count
435. ing out received data Figure 13 6 3 Procedure for Reading Out Received Data 13 68 Ver 0 10 CAN MODULE 13 13 7 Transmitting Remote Frames 13 7 Transmitting Remote Frames 13 7 1 Remote Frame Transmit Procedure The following describes the procedure for transmitting remote frames 1 Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the slot in which you want to transmit by writing H OO to the register 2 Confirming that transmission is idle Read the CAN Message Slot Control Register after being initialized and check the TRSTAT Transmit Receive Status bit to see that transmission has stopped and remains idle If this bit 1 it means that the CAN module is accessing the message slot so you need to wait until the bit is cleared 3 Setting transmit ID Set the ID to be transmitted in the message slot 4 Setting the Extended ID Register Set the corresponding bit of the Extended ID Register to 0 when you want to transmit the frame as a standard frame or 1 when you want to transmit the frame as an extended frame 5 Setting the CAN Message Slot Control Register Write H AO to the CAN Message Slot Control Register to set the TR Transmit Request and RM Remote bits to 1 13 69 Ver 0 10 13 CAN MODULE 13 7 Transmitting Remote Frames Remote frame transmit procedure Initialize CAN Message Slot Control Register Read CAN Messag
436. ing this port because it has a debug event function 1 10 3 bus Port 4 Port 22 Port 2 J Port 3 Port 0 Port 1 a Real time Port 7 us JTAG Ver 0 10 OVERVIEW 1 3 Pin Function Table 1 3 1 Description of the 32171 Pin Function 1 5 Type Pin Name Signal Name Input Output Function Power Power supply Power supply to external I O ports 5 V supply Power supply Power supply to internal logic 3 3 V VDD RAM power supply Power supply for internal RAM backup 3 3 V FVCC FLASH power supply Power supply for internal flash memory 3 3 V VSS Ground Connect all VSS to ground GND Clock XIN Clock Input Clock input output pins These pins contains a PLL based XOUT Output frequency multiplier circuit Apply a clock whose frequency is 1 4 the operating frequency When using 40 MHz CPU clock XIN input 10 0 MHz BCLK WR System clock Output This pin outputs a clock whose frequency is twice that of external input clock When using 10 MHz external input clock BCLK output 20 MHz Use this output when external operation needs to be synchronized OSC VCC Power supply Power supply for PLL circuit Connect OSC VCC to the power supply rail OSC VSS Ground Connect OSC VSS to ground VONT PLL control Input This pin controls the PLL circuit Connect a resistor and capacitor to it For external circuits refer
437. interrupt 2 4 IRQ9 TINO input MJT input interrupt 1 1 IRQ7 TMSO TMS1 output MJT output interrupt 7 2 IRQ6 TOP8 TOP9 output MJT output interrupt 6 2 IRQ5 TOP10 output output interrupt 5 1 IRQ4 4 7 output MJT output interrupt 4 4 IRQ3 TIO8 9 output MJT output interrupt 2 IRQ2 TOPO 5 output MJT output interrupt 2 6 IRQ1 TOP6 TOP7 output MJT output interrupt 1 2 IRQO TIOO 3 output MJT output interrupt 0 4 Table 10 1 3 DMA Transfer Request Generation by MJT Signal Name Source of DMA Request Generated DMAC Input Channel DRQO TIO8 underflow Channel 0 DRQ1 Input event bus 2 Channel 0 DRQ2 Output event bus 0 Channel 1 DRQ4 Output event bus 1 Channel 2 DRQ5 TIN18 input Channel 2 DRQ6 TIN19 input Channel 4 DRQ7 TINO input Channel 3 DRQ12 TIN20 input Channel 5 DRQ13 Input event bus 0 Channel 8 Table 10 1 4 A D Conversion Start Request by MJT Signal Name Source of A D Conversion Start Requested A D Converter ADOTRG Output event bus 3 Can be input to A DO conversion start trigger 10 3 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 1 Outline of Multijunction Timers
438. ion R 8 9 No functions assigned 0 10 TMSIS1 51 interrupt status 0 No interrupt request O A 11 TMSISO 50 interrupt status 1 Interrupt request generated 12 13 functions assigned 0 14 TMSIM1 TMS1 interrupt mask 0 Enables interrupt request O O 15 TMSIMO TMSO interrupt mask 1 Masks disables interrupt request W A Only writing a 0 is effective when you write a 1 the previous value is retained TMSIR H 0080 0237 TMS10vf Data bus TMSIS1 2 source inputs b10 F F MJT output r a interrupt 7 TMSIM1 Level IRQ7 014 TMSOovf TMSISO b11 F F RA TMSIMO b15 F F Figure 10 2 12 Block Diagram of MJT Output Interrupt 7 10 39 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer E TIN Interrupt Control Register 0 TINIRO Address H 0080 0238 DO 1 2 3 4 5 6 D7 TINISO TINIM2 TINIM1 TINIMO When reset 00 gt D Bit Name Function R 0 2 No functions assigned 0 3 TINISO TINO interrupt status 0 No interrupt request A 1 Interrupt request generated 4 No functions assigned 0 5 TINIM2 reserved Setting this bit has no effect 6 TINIM1 reserved Setting this bit has no effect O O 7 TINIMO TINO interrupt mask 0 Enables interrupt request O O 1 Masks disables interrupt request W A Only writing a 0 is effective when you write a 1 the previous val
439. ions assigned 0 6 LBS Normal mode Loopback status Loopback mode 7 CRS Operating Q CAN reset status Reset 8 RSB Not receiving Receive status Receiving 9 TSB Not transmitting Transmit status Transmitting 10 RSC Reception not completed yet Receive complete status Reception completed 11 TSC Transmission not completed yet Transmit complete status Transmission completed 13 11 Ver 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers D Bit Name Function R 12 15 MSN Number of message slot which has finished sending or receiving Message slot number 0000 SlotO 0001 Slot1 0010 Slot2 0011 Slot3 0100 Slot4 0101 Slot5 0110 Slot6 0111 Slot7 1000 Slot8 1001 Slot9 1010 Slot10 1011 Slot11 1100 Slot12 1101 Slot13 1110 Slot14 1111 Slot15 1 BOS Bus Status bit 01 When BOS bit 1 it means that the CAN module is in bus off state Set condition This bit is set to 1 when the transmit error counter value exceeded 255 and a bus off state is entered Clear condition This bit is cleared when restored from the bus off state 2 EPS Error Passive Status bit D2 When EPS bit 1 it means that the CAN module is in an error passive state Set condition This bit is set to 1 when the transmit or receive error counter value exceeded 127 and an error passive state is entered Clear condition This bit is
440. ipheral I O and internal RAM Not only can DMA transfer requests be generated in software but can also be triggered by a signal generated by an internal peripheral I O e g A D converter MJT or serial I O Cascaded connection between DMA channels DMA transfer in a channel is started by completion of transfer in another is also supported allowing for high speed transfer processing without imposing any extra load on the CPU 3 Built in 16 channel A D converters 32171 contains one 16 channel A D converters which can convert data 10 bit resolution In addition to single A D conversion in each channel successive A D conversion in four eight or 16 channels combined into one unit is possible In addition to ordinary A D conversion a comparator mode is supported in which the A D conversion result is compared with a given set value to determine the relative magnitudes of two quantities When A D conversion is completed the 32171 can generate not only an interrupt but can also generate a DMA transfer request The 32171 supports two read out modes so that A D conversion results can be read out in 8 bits or 10 bits 1 4 Ver 0 10 OVERVIEW 1 1 Outline of the 32171 4 High speed serial I O 32171 incorporates 3 channels of serial I O which be set for clock synchronized serial I O or UART When set for clock synchronized serial I O the data transfer rate is a high 2 Mbits per second
441. is handled as 64 bit register When reading the value of bit 8 is sign extended When writing bits 0 7 are ignored Also the accumulator is used by the multiplication instruction MUL Note that when executing this instruction the value of the accumulator is destroyed The MVTACHI and MVTACLO instructions are used to write to the accumulator The MVTACHI instruction writes data to the 32 high order bits bits 0 31 and the MVTACLO instruction writes data to the 32 low order bits bits 32 63 The MVFACHI MVFACLO and instructions are used to read data from the accumulator The instruction reads data from the 32 high order bits bits 0 31 the MVFACLO instruction reads data from the 32 low order bits bits 32 63 and the MVFACHI instruction reads data from the 32 middle bits bits 16 47 Range of bits read by instruction 0 MSB 78 15 16 31 32 47 48 63 LSB ACC Range of bits read written to by Range of bits read written to by MVFACHI MVTACHI instructions MVFACLO MVTACLO instructions Note Note Bits 0 7 always show the sign extended value of bit 8 Writes to this bit field are ignored 2 5 Program Counter The Program Counter PC is a 32 bit counter used to hold the address of the currently executed instruction Because M32R instructions each start from an even address the LSB bit 31 is always 0 0 M
442. is inverted F F output levels change from low to high or vice versa at startup and upon underflow generating consecutive pulses until the timer stops counting Also an interrupt can be generated each time the counter underflows 10 78 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer The valid count values are the counter set value 1 and reload register set value 1 The diagram below shows timer operation as an example when the initial counter value 4 and the initial reload register value 5 Count value 5 Count value 26 Count value 26 deg Count clock Prescaler delay i Note 1 4 i 5 5 4 5 Enable _ Counter Reload register F F output e m gt Interrupt A A Underflow Underflow Underflow Note 1 What you actually see in the cycle immediately after enable is the previous counter value and not 4 Note 2 What you actually see in the cycle immediately after reload is H FFFF underflow value and not 5 Note 3 This diagram does not show detail timing information Figure 10 3 20 Example of Counting in TOP Continuous Output Mode 10 79 Ver 0 10 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer In the example below the counter has the initial value 000 set in it and the reload regi
443. is the reference voltage input pin for the A D1 converter Interrupt SBI System break Input System break interrupt SBI input pin for the interrupt controller interrupt controller Serial I O SCLKIO UART transmit Input output When channel 0 is in UART mode SCLKOO receive clock This pin outputs a clock derived from BRG output by halving it output or CSIO transmit receive When channel 0 is in CSIO mode clock input output This pin accepts as its input a transmit receive clock when external clock Source is selected or outputs a transmit receive clock when internal clock Source is selected SCLKH UART transmit Input output When channel 1 is in UART mode SCLKO1 receive clock This pin outputs a clock derived from BRG output by halving it output or CSIO transmit receive When channel 1 is in CSIO mode clock input output This pin accepts as its input a transmit receive clock when external clock Source is selected or outputs a transmit receive clock when internal clock Source is selected TXDO Transmit data output Transmit data output pin for serial channel 0 RXDO Receive data Input Receive data input pin for serial I O channel 0 TXD1 Transmit data Output Transmit data output pin for serial I O channel 1 RXD1 Receive data Input Receive data input pin for serial I O channel 1 TXD2 Transmit data Output Transmit data output pin for serial I O channel 2 RXD2 Receive data Input Receive data input pin for serial
444. isables reception O O Receive enable bit 1 Enables reception 4 OVR 0 No overrun error O Overrun error bit 1 Overrun error occurred 5 PTY 0 No parity error O Parity error bit UART mode only 1 Parity error occurred 6 FLM 0 No framing error Framing error bit UART mode only 1 Framing error occurred 7 ERS 0 No error Error sum bit 1 Error occurred 12 20 Ver 0 10 1 2 SERIAL I O 12 2 Serial Related Registers 1 RSTAT receive status bit D1 Set condition This bit is set to 1 by a start of receive operation When this bit 1 it means that the serial I O is receiving data Clear condition This bit is cleared to 0 upon completion of receive operation or by clearing the REN receive enable bit 2 RFIN receive completed bit D2 Set condition This bit is set to 1 when all data bits have been received in the Receive Shift Register and whose content is transferred to the Receive Buffer Register Clear condition This bit is cleared to 0 by reading the lower byte from the Receive Buffer Register or by clearing the REN receive enable bit However if an overrun error occurs this bit cannot be cleared by reading the lower byte from the Receive Buffer Register In this case clear the REN receive enable bit 3 REN receive enable bit D3 Receive is enabled by setting this bit to 1 and is disabled by clearing this bit to 0 at which time the receive unit is i
445. ister COMSL7DLC Address H 0080 1175 E CANO Message Slot 8 Data Length Register COMSL8DLC Address H 0080 1185 E CANO Message Slot 9 Data Length Register COMSL9DLC Address H 0080 1195 gt CANO Message Slot 10 Data Length Register COMSL10DLC Address H 0080 11 5 gt CANO Message Slot 11 Data Length Register COMSL11DLC Address H 0080 11 5 gt CANO Message Slot 12 Data Length Register COMSL12DLC Address H 0080 11 5 gt CANO Message Slot 13 Data Length Register COMSL13DLC Address H 0080 11D5 gt CANO Message Slot 14 Data Length Register COMSL14DLC Address H 0080 11E5 gt CANO Message Slot 15 Data Length Register COMSL15DLC Address H 0080 11F5 gt D8 9 10 11 12 13 14 D15 DLCO DLC1 DLC2 DLC3 When reset Indeterminate gt D Bit Name Function R 8 11 No functions assigned 0 12 15 DLCO DLC3 0 0 0 byte Sets data length 0 1 1 byte 1 0 2 byte o o o 1 1 3 byte 0 4 byte 1 5 byte 110 6byte Oo o o EN 11 1 7 byte 1XXX 8byte These registers are the transmit frame receive frame memory space When transmitting the register sets the length of transmit data When receiving the register stores the received DLC 13 43 Ver 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers CANO Message Slot 0 Data 0 COMSLODTO lt Address H 0080 1106 CANO Message Slot 1 Data 0 COMSL1DTO Address H 0080 11162 CANO
446. ister TIO4RL 0346 TIO4 Reload 0 Measure Register TIO4RLO 0348 4 Control Register 5 Control Register 034A TIO4CR 5 0350 TIO5 Counter TIO5CT 0352 0354 TIO5 Reload 1 Register TIOBRL 0356 TIO5 Reload 0 Measure Register TIOBRLO 0360 TIO6 Counter TIO6CT 0364 TIO6 Reload 1 Register TIO6RL 0366 TIO6 Reload 0 Measure Register TIOGRLO 0368 036A TIO6 Control Register TIO7 Control Register TIO6CR 7 0370 7 Counter TIO7CT 0372 0374 TIO7 Reload 1 Register TIO7RL 0376 TIO7 Reload 0 Measure Register TIO7RLO Blank addresses are reserved Figure 10 4 3 TIO Related Register Map 2 3 10 88 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer Address 0 Address 1 Address DO D7 D8 D15 H 0080 0380 TIO8 Counter TIO8CT H 0080 0384 TIO8 Reload 1 Register TIO8RL H 0080 0386 TIO8 Reload 0 Measure Register TIOBRLO H 0080 0388 m TIO8 Control Register TIO9 Control Register TIO8CR TIO9CR H 0080 0390 9 Counter TIO9CT H 0080 0392 H 0080 0394 TIO9 Reload 1 Register TIO9RL1 H 0080 0396 TIO9 Reload 0 Measure Register TIO9RLO H 0080 03BC TIOO 9 Enable Protect Register TIOPRO H 0080 0 9 Count Enable Register TIOCEN Blank addresses are reserved Note The registers enclosed in thick frames must always be ac
447. ister 1 FFD1 Timings at which signals are generated to the output flip flop by each timer are shown in Table 10 2 5 below Note that signals are generated at different timings than those fed to the output event bus 10 21 Ver 0 10 10 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer Table 10 2 5 Timings at Which Signals Are Generated to the Output Flip Flop by Each Timer Timer Mode Timings at which signals are generated to the output flip flop TOP Single shot output mode When counter is enabled and when underflows Delayed single shot output mode When counter underflows Continuous output mode When counter is enabled and when underflows TIO Measure clear input mode When counter underflows Measure free run input mode When counter underflows Noise processing input mode When counter underflows PWM output mode When counter is enabled and when underflows Single shot output mode When counter is enabled and when underflows Delayed single shot output mode When counter underflows Continuous output mode When counter is enabled and when underflows TMS 16 bit measure input No signal generation function TML 32 bit measure input No signal generation function Port operation mode OBS elec TEES register PnMOD TIO udi F F metri oo ete sora Output event bus 2 O Output event bus 3 34o WR F F protect FPn Dn FF Output control
448. ister full a receive finished DMA transfer request is generated However if an overrun error has occurred this DMA transfer request is not generated 12 41 Ver 0 10 1 2 SERIAL I O 12 6 Transmit Operation in UART Mode 12 6 Transmit Operation in UART Mode 12 6 1 Setting the UART Baud Rate The baud rate data transfer rate during UART mode is determined by a transmit receive shift clock In UART mode the source for this transmit receive shift clock is always the internal clock regardless of how the internal external clock select bit SIO Transmit Receive Mode Register bit D11 is set 1 Calculating the UART mode baud rate After being divided by the clock divider f BCLK is fed into the Baud Rate Generator BRG after which it is further divided by 16 to produce a transmit receive shift clock The clock divider s divide by value is selected from 1 8 32 or 256 note using the SIO Transmit Control Register s CDIV baud rate generator count source select bits D2 D3 The Baud Rate Generator divides the clock it received from the clock divider by baud rate register set value 1 and further divides the resulting clock by 16 to produce a transmit receive shift clock During UART mode in which the internal clock is always used the baud rate is calculated using the equation below 1 BCLK Baud rate LM bps Clock divider s divide by value x baud rate register set value 1 x 16 Baud rate register set value H 00 t
449. it D13 Figure 12 2 4 shows an example of data format when parity is enabled 6 SEN sleep select bit 015 This bit is effective during UART mode If the sleep function is enabled by setting this bit to 1 data is latched into the UART Receive Buffer Register only when the most significant bit MSB of the received data is 1 12 16 Ver 0 10 12 SERIAL I O 12 2 Serial Related Registers ST Start bit PAR Parity bit D Data bit SP Stop bit gt One frame equivalent lt a Direction of transfer Clock synchronous mode DeX D5 X D4 X DX D2 D1 X a Note 1 Note 2 7 bit UART mode st De bs X D2 D1 X DOXPARY SP gt Note 1 Note 2 8 bit UART mode ST D7 D6 X D5 X DA D3 X D2 X D1 Do XPAR SP CZ ra gt Note 1 Note 2 9 bit UART mode ST D8 D7 X D6 X D5 X D4 X D2X D1 XPARY SP Note 1 Whether or not to add a parity bit is selectable Note 2 The stop bit can be one bit or two bits long as selected When transmitting If the attribute odd even of the number of 1 s included in data bits agrees with the selected parityattribute a 0 is added as parity bit If the attribute odd even of the number of 1 s included in data bits does not agree with the selected parity attribute a 1 is added as parity bit MSB LSB ST D7 X DeX D5X
450. it A DO Data Register 1 ADOIN2 ADOIN2 10 bit A DO Data Register 2 ADOIN3 ADOIN3 10 bit A DO Data Register 3 ADOIN4 ADOIN4 10 bit A DO Data Register 4 ADOIN5 ADOIN5 10 bit A DO Data Register 5 ADOIN6 ADOIN6 10 bit A DO Data Register 6 ADOIN7 ADOIN7 10 bit A DO Data Register 7 ADOIN8 ADOIN8 10 bit A DO Data Register 8 ADOIN9 ADOIN9 10 bit A DO Data Register 9 ADOIN10 ADOIN10 10 bit A DO Data Register 10 ADOIN11 ADOIN11 10 bit A DO Data Register 11 ADOIN12 ADOIN12 10 bit A DO Data Register 12 ADOIN13 ADOIN13 10 bit A DO Data Register 13 ADOIN14 ADOIN14 10 bit A DO Data Register 14 ADOIN15 ADOIN15 10 bit A DO Data Register 15 Completed ADOINO 10 bit A D Data Register 0 Repeated until forcibly halted 11 9 Ver 0 10 1 1 CONVERTERS 11 1 Outline of Converters 11 1 3 Special Operation Modes 1 Forcible single mode execution during scan mode This special operation mode forcibly executes single mode conversion A D conversion or comparate in a specified channel during scan mode operation For conversion mode the conversion result is stored in the 10 bit A D Data Register corresponding to the specified channel For comparate mode the conversion result is stored in the 10 bit A D Comparate Data Register When the A D conversion or comparate operation in the specified channel is completed scan mode A D conversion is restarted from where it was canceled during scan operation To start single mode conversion duri
451. it is cleared to 0 writes to the transmit buffer register are ignored Always be sure to set the transmit enable bit to 1 before you write to the transmit buffer register Note 2 When the internal clock is selected a write to the lower byte of the transmit buffer register in Note 1 above triggers a start of transmission Note 3 The transmit status bit is set to 1 at the time data is set in the lower byte of the SIO Transmit Buffer Register When transmission starts the serial I O transmits data following the procedure below Transfer the content of the SIO Transmit Buffer Register to the SIO Transmit Shift Register Setthe transmit buffer empty bit to 1 Note Start sending data synchronously with the shift clock beginning with the LSB Note A transmit buffer empty interrupt request and or a DMA transfer request can be generated when the transmit buffer is emptied 12 3 4 Successive CSIO Transmission Once data is transferred from the transmit buffer register to the transmit shift register the next data can be written to the transmit buffer register even when transmission of the preceding data is not completed When the next data is written to the transmit buffer before completion of the preceding data transmission the preceding and the next data are successively transmitted To see if data has been transferred from the transmit buffer register to the transmit shift register check the SIO Status Register s transmit buffer emp
452. iting to the enable bit in software The counter can be read on the fly 10 127 Ver 0 10 MULTIJUNCTION TIMERS 10 5 TMS Input related 16 bit Timer 10 10 5 6 TMS Measure Registers TMSOMR3 0 TMS1MR3 0 E TMSO Measure Register TMSOMR3 TMSO Measure 2 Register TMSOMR2 E TMSO Measure 1 Register TMSOMR1 TMSO Measure 0 Register TMSOMRO E TMS1 Measure Register TMS1MR3 Bi TMS1 Measure 2 Register TMS1MR2 E TMS1 Measure 1 Register TMS1MR1 TMS1 Measure 0 Register TMS1MRO DO 1 2 3 4 5 6 7 8 9 Address Address Address Address Address Address Address Address 12 13 H 0080 03 2 gt H 0080 03 4 gt H 0080 03 6 gt H 0080 03 8 gt H 0080 03D2 gt H 0080 03D4 gt H 0080 0306 gt H 0080 03D8 gt 14 015 TMSOMR3 0 TMS1MR3 0 D Bit Name Function 0 15 TMSOMR3 TMSOMRO TMS1MR3 TMS1MRO Note 1 This register is a read only register Note 2 This register can be accessed in either byte or halfword When reset Indeterminate gt 16 bit reload register value R L The TMS measure registers are used to latch counter contents upon event input The TMS measure registers are a read only register 10 128 Ver 0 10 1 0 MULTIJUNCTION 5 10 5 TMS Input related 16 bit Timer 10 5 7 Operation of TMS Measure Input 1 Outline of TMS measure input In TMS measure input the counter starts counting up clock pulse
453. ition This bit is set to 1 when the CAN module is operating as a receive node Clear condition This bit is cleared when the CAN module started operating as a transmit node or entered a bus idle state 8 TSB Transmit Status bit D9 Set condition This bit is set to 1 when the CAN module is operating as a transmit node Clear condition This bit is cleared when the CAN module started operating as a receive node or entered a bus idle state 9 RSC Receive Complete Status bit D10 Set condition This bit is set to 1 when the CAN module finished receiving normally regardless of whether any slot exists that meets receive conditions Clear condition This bit is cleared when the CAN module finished transmitting normally 10 TSC Transmit Complete Status bit D11 Set condition This bit is set to 1 when the CAN module finished transmitting normally Clear condition This bit is cleared when the CAN module finished receiving normally 11 MSN Message Slot Number bits D12 D15 These bits show the relevant slot number when the CAN module finished transmitting or finished storing received data This bit cannot be cleared to 0 in software 13 14 Ver 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers 13 2 3 CAN Extended ID Register CANO Extended ID Register CANOEXTID Address H 0080 1004 DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 IDEO IDE1 IDE2 IDES IDE4 IDES IDE6 I
454. itted twice in succession Note 3 For the RCV command all bits not just bits 16 19 i e bits 0 15 and bits 20 31 must be set to 1 14 4 Ver 0 10 1 4 REAL TIME DEBUGGER RTD 14 3 Functional Description of the RTD 14 3 2 Operation of RDR Real time RAM Content Output When the RDR real time RAM content output command is issued the RTD is made possible to transfer the contents of the internal RAM to external devices without causing the CPU s internal bus to stop Because the RTD reads data from the internal RAM while no transfers are being performed between the CPU and internal RAM no extra load is levied on the CPU The address to be read from the internal RAM can only be specified on 32 bit word boundaries The two low order address bits specified by a command are ignored Note also that data are read out in units of 32 bits as transferred from the internal RAM to an external device LSB side MSB side 31 eseese 9014848 17 1615 AAAS 12 1 0 RTDRXD 4 X 010110 X 29 28 17 16 Command RDR Specified address Note X Don t Care However if issued immediately after the RCV command bits 20 31 must all be set to 1 Figure 14 3 1 RDR Command Data Format lt periods gt lt periods gt K periods gt lt periods gt RTA TUS RTDRXD
455. k Register A Standard ID1 COLMSKAS1 H 0080 1032 Register A Extended IDO COLMSKAEO CANO Local Mask Register A Extended ID1 COLMSKAE1 H 0080 1034 Register A Extended ID2 COLMSKAE2 H 0080 1036 H 0080 1038 Register B Standard IDO COLMSKBSO CANO Local Mask Register B Standard ID1 COLMSKBS1 H 0080 103A Register B Extended IDO COLMSKBEO CANO Local Mask Register B Extended ID1 COLMSKBE1 H 0080 103C Register B Extended ID2 COLMSKBE2 H 0080 1050 CANO Message Slot 0 Control Register COMSLOCNT H 0080 1052 H 0080 1054 H 0080 1056 H 0080 1058 H 0080 105A H 0080 105C H 0080 105E CANO Message Slot 1 Control Register COMSL1CNT CANO Message Slot 2 Control Register COMSL2CNT CANO Message Slot 4 Control Register 0 514 CANO Message Slot 3 Control Register COMSL3CNT CANO Message Slot 5 Control Register COMSL5CNT CANO Message Slot 6 Control Register COMSL6CNT CANO Message Slot 7 Control Register COMSL7CNT CANO Message Slot 8 Control Register COMSL8CNT CANO Message Slot 9 Control Register COMSL9CNT CANO Message Slot 10 Control Register COMSL10CNT CANO Message Slot 12 Control Register COMSL12CNT CANO Message Slot 11 Control Register COMSL11CNT CANO Message Slot 13 Control Register COMSL13CNT CANO Message Slot 14 Control Register COMSL14CNT CANO Message Slot 15 Control Register COMSL15CNT Blank addresses are r
456. k selected External clock selected CSIO on receive side Recei lock SCLKI m 4 4 Clock stopped a Cleared Set 3 Y Receive enable bit RXD D7 D6 D5X D4 D3 X 2 D1X DO Set by a write to transmit buffer Automatically cleared for each receive operation Receive status bit performed Receive finished bit Read from receive buffer AR Receive finished interrupt 7 SIO receive interrupt Note 2 Note 1 M When receive finished interrupt is selected Interrupt request accepted Note 3 When receive error No interrupt request interrupt is selected Processing by software Interrupt generation Note 1 Change of the Interrupt Controller SIO Receive Interrupt Control Register interrupt request bit Note 2 When receive finished interrupt is enabled DMA transfer can also be requested at the same timing Note 3 The Interrupt Controller IVECT register is read or SIO Receive Interrupt Control Register interrupt request bit cleared Figure 12 4 3 Example of CSIO Reception When Received Normally 12 38 Ver 0 10 12 SERIAL I O 12 4 Receive Operation in CSIO Mode Note 1 Note 2 Note 3 Note 4 Note 5 lt CSIO on receive side gt Internal clock selected lt CSIO on receive side gt
457. l purposes as a register for reloading TIO Count Registers TIOOCT TIO9CT with data and as a measure register during measure input mode These registers are disabled against write during measure input mode It is in the following cases that the content of reload 0 register is loaded into the counter When after the counter started counting in noise processing input mode the input signal is inverted and a valid level signal is entered again before the counter underflows When the counter is enabled in single shot mode When the counter underflowed in delayed single shot or continuous mode When the counter is enabled in PWM mode and when the counter value set by reload 1 register underflowed Writing data to the reload 0 register does not mean that the data is loaded into the counter simultaneously When used as a measure register the counter value is latched into the measure register by an event input 10 102 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer 10 4 7 TIO Reload 1 Registers TIOORL1 TIO9RL1 TIOO Reload 1 Register TIOORL1 Address H 0080 0304 Bi TIO1 Reload 1 Register TIO1RL1 Address H 0080 0314 TIO2 Reload 1 Register TIO2RL1 Address H 0080 0324 TIO3 Reload 1 Register TIOSRL1 Address H 0080 0334 E TIO4 Reload 1 Register TIO4RL1 Address H 0080 0344 TIO5 Reload 1 Register TIO5RL1 Address H 0080 0354 E TIO6 Reload 1 Register TIO6RL1 Address
458. l set to 1 Figure 14 3 11 Operation of the RCV Command 14 11 Ver 0 10 1 4 REAL TIME DEBUGGER RTD 14 3 Functional Description of the RTD 14 3 7 Method to Set a Specified Address when Using the RTD When using the Real Time Debugger RTD you can set low order 16 bit addresses of the internal RAM area Because the internal RAM area is located in a 48 KB area ranging from H 0080 4000 to H 0080 FFFF you can set low order 16 bit addresses of that area However access to any locations other than the area where the RAM resides is inhibited Note also that two least significant address bits A31 and A30 are always 0 s because data are read and written to the internal RAM in a fixed length of 32 bits Memory map X A29 A16 H 0080 0000 SFR 16KB H 0080 4000 p H 0080 4000 H 0080 FFFF only can be specified RAM area H 0080 FFFF Figure 14 3 12 Method for Setting Addresses in Real Time Debugger 14 12 Ver 0 10 1 4 REAL TIME DEBUGGER RTD 14 3 Functional Description of the RTD 14 3 8 Resetting the RTD The RTD is reset by applying a system rest i e by entering the RESET signal The status of the RTD related output pins after a system reset are shown below Table 14 3 2 RTD Pin State after System Reset Pin Name State RTDACK High level output RTDTXD High level output The first command transfer to the RTD after it was reset is initiated by transferring
459. lash Emulation Function eere 6 40 6 7 1 Virtual Flash Emulation Area eee 6 41 6 7 2 Entering Virtual Flash Emulation Mode 6 46 6 7 3 Application Example of Virtual Flash Emulation Mode 6 47 6 8 Connecting to A Serial Programmer eese 6 49 6 9 Precautions to Be Taken When Rewriting Flash Memory 6 51 CHAPTER 7 RESET 7 1 Outline Of Heset 7 2 7 2 R set Operation Ele cn 7 2 7 221 Reset at FPOweroN a e 7 2 7 2 2 Reset during 7 2 7 2 3 Reset Vector Relocation during Flash Rewrite 7 2 7 3 Internal State Immediately after Reset Release 7 8 7 4 Things To Be Considered after Reset Release 7 4 CHAPTER 8 INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 1 Outline of Input Output Ports 8 2 8 2 Selecting Pin Functions nennen 8 4 8 3 Input Output Port Related Registers eese 8 6 8 3 1 Port Data Registers eese 8 8 8 3 2 Port Direction
460. latched Timing at which reload 1 V and reload 0 registers are updated Note This diagram does not show detail timing information Figure 10 4 13 Reload 0 and Reload 1 Register Updates in PWM Output Mode 10 115 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer 10 4 12 Operation in TIO Single shot Output Mode without Correction Function 1 Outline of TIO single shot output mode In single shot output mode the timer generates a pulse in width of reload 0 register set value 1 only once and stops without performing any operation When after setting the reload 0 register the timer is enabled by writing to the enable bit in software or by external input it loads the content of reload 0 register into the counter synchronously with the count clock letting the counter start counting The counter counts down clock pulses and stops when it underflows after reaching the minimum count The F F output waveform in single shot output mode is inverted F F output levels change from low to high or vice versa at startup and upon underflow generating a single shot pulse waveform in width of reload 0 register set value 1 only once Also an interrupt can be generated when the counter underflows The count value is reload 0 register set value 1 For details about count operation also refer to Section 10 3 9 Operation in Single shot Output Mode with Correction Function
461. le Mode Register 0 or Scan Mode Register 0 s conversion comparate completion flag is cleared to 0 The comparison voltage Vref note is fed from the D A converter into the comparator 9 The comparison voltage Vref and the analog input voltage VIN are compared with the comparison result stored in the comparate result flag A D Comparate Data Register s D15 If Vref VIN then the comparate result flag 0 If Vref gt VIN then the comparate result flag 1 The comparate operation stops after storing the comparison result The comparison result is stored in the A D Comparate Data Register ADOCMP s corresponding bit Note The comparison voltage Vref the voltage fed from the D A converter into the comparator is determined according to changes of the content of the A D Successive Approximation Register Shown below are the equations used to calculate the comparison voltage Vref When the content of the A D Successive Approximation Register 0 Vref V 2 0 When the content of the A D Successive Approximation Register 1 to 1 023 Vref V reference voltage VREFO 1 024 x content of the A D Successive Approximation Register 0 5 11 33 Ver 0 10 1 1 5 11 3 Functional Description of Converters 11 3 4 Calculation of the A D Conversion Time The A D conversion time is expressed by the sum of dummy cycle time and the actual execution cycle time The following shows each t
462. lected from 7 bits 8 bits and 9 bits Serial I Os 0 2 each have transmit and receive DMA transfer requests Through a combined use with the internal DMAC they allow for fast serial communication and help to reduce the data communication load on the CPU Serial is outlined in the pages to follow 12 2 Ver 0 10 12 SERIAL I O 12 1 Outline of Serial Table 12 1 1 Outline of Serial 1 Item Number of channels Content CSIO UART 2 channels SIOO SIO1 UART only 1 channels SIO2 Clock During CSIO mode Internal clock or external clock as selected Note 1 During UART mode Internal clock only Transfer mode Transmit half duplex receive half duplex transmit receive full duplex BRG count source f BCLK BCLK 6 f BCLK 32 f BCLK 256 when internal peripheral clock selected Note 2 f BCLK Internal peripheral clock operating frequency Data format CSIO mode Data length 8 bits fixed Order of transfer LSB first fixed UART mode Start bit 1 bit Character length 7 8 or 9 bits Parity bit Added or not added when added selectable between odd and even parity Stop bit 1 or 2 bits Order of transfer LSB first fixed Baud rate CSIO mode 152 bits sec to 2M bits sec at BCLK 20 MHz UART mode 19 bits sec to 156K bits sec at f BCLK 20 MHz Error detection CSIO mode Overrun error only UART mode Overrun error parity err
463. ler When the CPU accepts an interrupt control branches to the EIT vector entry after hardware preprocessing as described in Section 4 3 EIT Processing Procedure The EIT vector entry for External Interrupt El is located at address H 0000 0080 This address is where the instruction not the jump address for branching to the beginning of the interrupt processing routine for External Interrupt El is written 2 Processing by interrupt handler In the External Interrupt El handler first save the BPC register PSW register and general purpose registers to the stack Next read out the Interrupt Mask Register IMASK and save the read value to the stack Then read out the Interrupt Vector Register IVECT Always be sure to read out the IMASK before reading the IVECT A read of IMASK and that of IVECT both triggers an operation to clear interrupt requests to the CPU and accept the next interrupt Furthermore a read of IVECT causes NEW_IMASK to be set in the IMASK and the accepted interrupt request to be cleared not cleared in the case of level recognized interrupt sources however The IVECT register has set in it the 16 low order bits of ICU vector table address for the accepted interrupt source Read the IVECT register using a signed halfword load instruction LDH instruction and then the content of the ICU interrupt vector table indicated by the read address Make sure the ICU vector table has the start addresses of interrupt handler
464. lies power to external ports AVCCO Power supply for A D converter VREFO Reference voltage for A D converter 3 3 V system VCCI Supplies power to internal logic FVCC Power supply for internal flash memory VDD Power supply for internal RAM backup OSC VCC Power supply for oscillator and PLL circuits 20 2 Ver 0 10 20 POWER UP POWER SHUTDOWN SEQUENCE 20 2 Power Up Sequence 20 2 Power On Sequence 20 2 1 Power On Sequence When Not Using RAM Backup The diagram below shows a power on sequence 5 0 V 3 3 V power supply of the M32R E when not using RAM backup 5V VCCE ov AVCCO ov 5V VREFO ov A RESET ov g 3 3V VDD ov 3 3V VCCI OV 3 3V FVCC OV 3 3V OSC VCC 0 D Turn on the 3 3 V power supply after turning on the 5 V power supply After turning on all power supplies and holding the RESET pin low for an oscillation stabilization time release the RESET pin input back high to deactivate reset Note Power on limitations VDD OSC VCC 2 VCCI VCCE gt VCCI FVCC OSC VCC Figure 20 2 1 Power On Sequence When Not Using RAM Backup 20 3 Ver 0 10 20 20 2 2 Power On Sequence When Using RAM Backup The diagram below shows a power on sequence 5 0 V 3 3 V power supply of the M32R E when using RAM backup 5V VCCE ov 5V AVCCO ov fi VREF ov i 0 C 5V _ gt 5 ov 3 3V VDD ov 3 3V
465. ll other areas in address space are located the same way The address maps of internal ROM and extended external areas in each mode are shown below For flash rewrite mode FP 2 VCO not listed in the above table refer to Section 6 5 Programming of Internal Flash Memory Non CS0 area H 0000 0000 Internal ROM Internal ROM area area 512 Kbytes 512 Kbytes 50 area H 0007 FFFF 1 Mbytes H 0008 0000 Reserved area 000 FFFF 512 Kbytes H 0010 0000 Ghost area in cso 1 Mbyte CSO area 1 Mbyte d external area H 001F FFFF H 0020 0000 Extendd CS1 area CS1 area 1 Mbytes 1 Mbytes H 002F FFFF H 0020 0000 Extended external area Ghost area in Ghost area in CS1 CS1 1 Mbyte 1 Mbyte H 003F FFFF lt Single chip mode gt lt Extended external mode gt lt Processor mode gt Figure 3 2 1 M32171F4 Operation Mode and Internal ROM Extended External Areas 3 5 Ver 0 10 H 0000 0000 Internal ROM area 384 Kbytes H 0005 FFFF H 0006 0000 H OO0F FFFF H 0010 0000 H 001F FFFF H 0020 0000 H 002F FFFF H 0030 0000 H 003F FFFF Single chip mode gt ADDRESS SPACE 3 2 Operation Modes 50 area Internal ROM area 384 Kbytes Reserved area 640 Kbytes 50 area 1 Mbyte CS1 area 1 Mbytes Ghost area in CS1 1 Mbytes lt Extended external mode gt external area CSO area 1 Mbytes Ghost area in cso 1 Mbytes CS1 area
466. lot 5 interrupt request mask 6 IRB6 Slot 6 interrupt request mask 7 IRB7 Slot 7 interrupt request mask 8 8 Slot 8 interrupt request mask 9 IRB9 Slot 9 interrupt request mask 10 IRB10 Slot 10 interrupt request mask 11 IRB11 Slot 11 interrupt request mask 12 IRB12 Slot 12 interrupt request mask 13 IRB13 Slot 13 interrupt request mask 14 IRB14 Slot 14 interrupt request mask 15 IRB15 Slot 15 interrupt request mask This register controls interrupt requests generated at completion of data transmission or reception in each corresponding slot by enabling or disabling them When IRBn n 0 15 is set to 1 interrupt requests to be generated at completion of transmission or reception in the corresponding slot are enabled The CAN Slot Interrupt Status Register CANOSLIST shows you which slot has requested the interrupt 13 24 Ver 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers CANO Error Interrupt Status Register CANOERIST Address H 0080 1014 DO 1 2 3 4 5 6 D7 EIS PIS ols When 00 gt D Bit Name Function R 0 4 No functions assigned 0 5 EIS 0 No interrupt request bus error interrupt status 1 Interrupt requested 6 PIS Error passive interrupt status 7 OIS Bus off interrupt status W A Only writing a 0 is effective when you write a 1 the previous value is retained When using CAN interrupts and the interrupt
467. lows Value written to Slot operation after write COMSLnCNT H 4E Operates as a data frame receive slot Overwrite can be verified by ML bit H 40 Operates as a data frame receive slot Overwrite cannot be verified by ML bit H 00 The slot stops transmit receive operation Note 1 If message lost check by the ML bit is needed write H AE to the COMSLnONT register as you clear the TRFIN bit Note 2 If you clear the TRFIN bit by writing H AE H 40 or H OO it is possible that new data will be stored in the slot while still reading a message from the slot 2 Reading out from the message slot Read out a message from the message slot 3 Checking the TRFIN Transmit Receive Finished bit Read the CAN Message Control Register to check the TRFIN Transmit Receive Finished bit When TRFIN Transmit Receive Finished bit 1 It means that new data was stored in the slot while still reading out from the slot in 2 In this case the data read out in 2 may contain an indeterminate value Therefore reexecute beginning with clearing of the TRFIN Transmit Receive Finished bit in 1 When TRFIN Transmit Receive Finished bit 0 It means that the CAN module finished reading out from the slot normally 13 67 Ver 0 10 CAN MODULE 1 3 13 6 Receiving Data Frames Reading out received data Clear TRFIN bit to 0 Read out from message slot Read CAN Message Slot Control Register Finished read
468. lse thus output indicates the type of instruction data that the RTD received 1 clock period VER continuous monitor command 1 clock period VEI RTD interrupt request command 2 clock periods RDR real time RAM content output command 3 clock periods WRR RAM content forcible rewrite command or the data to rewrite 4 clock periods or more RCV recover from runaway command RTDCLK Input RTD transfer clock input 14 3 Ver 0 10 14 REAL TIME DEBUGGER RTD 14 3 Functional Description of the RTD 14 3 Functional Description of the RTD 14 3 1 Outline of RTD Operation Operation of the RTD is specified by a command entered from devices external to the chip A command is specified in bits 16 19 note 1 of the RTD receive data Table 14 3 1 RTD Commands RTD Receive Data 519 b18 b17 b16 Command Mnemonic RTD Function 0 0 0 0 VER VERify Continuous monitor 0 1 0 0 0 1 0 1 0 1 il 0 VEI VErify Interrupt request RTD interrupt request 0 0 1 0 RDR ReaD RAM Real time RAM content output 0 0 1 1 WRR WRite RAM RAM content forcibly rewrite with verify 1 1 1 1 RCV ReCoVer Recover from runaway Note 2 Note 3 0 0 0 1 System reserved use inhibited Note 1 Note 1 Bit 19 of RTD receive data is not actually stored in the command register and except for the RCV command is handled as Don t Care bit Bits 16 18 are effective for the command specified Note 2 The RCV command must always be transm
469. ly Input POO PO7 Input output nput ouput Programmable input output port output port 0 port Note 10 17 Input output nput ouput Programmable input output port port 1 20 27 Input output nput ouput Programmable input output port port 2 P30 P37 Input output nput ouput Programmable input output port port 3 P41 P47 Input output nput ouput Programmable input output port port 4 P61 P64 Input output nput output Programmable input output port port 6 However P64 is an input only port P70 P77 Input output nput ouput Programmable input output port port 7 P82 P87 Input output nput ouput Programmable input output port port 8 P93 P97 Input output nput ouput Programmable input output port port 9 P100 Input output nput ouput Programmable input output port P107 port 10 P110 Input output nput ouput Programmable input output port P117 port 11 Note Input output port 5 is reserved for future use 1 14 Ver 0 10 OVERVIEW 1 3 Pin Function Table 1 3 1 Description of the 32171 Pin Function 5 5 Type Input output port Note1 Pin Name Signal Name Input Output Function P124 Input output nput output Programmable input output port P127 port 12 P130 Input output nput output Programmable input output port P137 port 13 P150 Input output nput output Programmable input output port P153 port 15 P174 Input output nput output Programmable input output port
470. ly the reset vector entry is located at the start address of the internal flash memory Transfer the flash write program from the boot area into the internal RAM using a boot program After this transfer jump to the RAM and set the Flash Control Register 1 FENTRY bit to 1 to make the flash memory ready for write You now can write to the internal flash memory using the flash write program that has been transferred into the internal RAM For 2 set the FP pin high MODO low MOD1 low to enter flash E W enable mode in single chip mode Transfer the flash write program from the internal flash memory in which it has been prepared beforehand into the internal RAM After this transfer jump to the RAM and set the Flash Control Register 1 FCNT1 FENTRY bit to 1 using a program in the RAM to make the flash memory ready for write You now can write to the internal flash memory using the flash write program that has been transferred into the internal RAM Or you can set the FP pin high MODO low and MOD1 high to enter flash E W enable mode in extended external mode When in flash E W enable mode FP pin 1 FENTRY bit 1 the EIT vector entry for External Interrupt El is moved to the beginning of the internal RAM H 0080 4000 During normal mode the EIT vector entry exists in the flash area H 0000 0080 6 16 Ver 0 10 INTERNAL MEMORY 6 5 Programming of the Internal Flash Memory Flash E W enable mode Normal m
471. ly when the FP pin high and the Flash Control Register 1 1 FENTRY bit 1 You cannot enter flash E W enable mode when the device is operating in processor mode or the FP pin low 3 Detecting the MODO and pin levels The MODO and MOD pin levels high or low can be verified using the P8 Data Register Port Data Register H 00800 0708 MODODT and MOD1DT bits E P8 Data Register P8DATA Address H 0080 0708 DO 1 2 3 4 5 6 D7 MODODT MOD1DT P82DT P83DT P84DT P85DT P86DT P87DT When reset Indeterminate gt D Bit Name Function R 0 MODODT 0 MODO pin low MODO data 1 MODO pin high 1 MOD1DT 0 MODI pin low MOD 1 data 1 MODI pin high 2 P82DT Depending on how the Port Direction Register is set O Port P82 data When direction bit 0 input mode 3 P83DT 0 Port input pin low Port P83 data 1 Port input pin high 4 P84DT When direction bit 1 output mode O O Port P84 data 0 Port output latch low 5 P85DT 1 Port output latch high O O Port P85 data 6 P86DT 86 7 P87DT Port P87 data 6 23 Ver 0 10 INTERNAL MEMORY 6 5 Programming of the Internal Flash Memory 4 START Enter one of the following modes Single chip mode flash E W enable mode Boot mode flash E W enable mode FMOD H 0080 07 0 Extended
472. me Function R 8 TOMASK 5100 transmit 0 Masks disables interrupt request O interrupt mask bit 1 Enables interrupt request 9 ROMASK 6100 receive 0 Masks disables interrupt request interrupt mask bit 1 Enables interrupt request 10 T1MASK SIO1 transmit 0 Masks disables interrupt request O O interrupt mask bit 1 Enables interrupt request 11 R1MASK SIO1 receive 0 Masks disables interrupt request interrupt mask bit 1 Enables interrupt request 12 T2MASK 5102 transmit 0 Masks disables interrupt request O interrupt mask bit 1 Enables interrupt request 13 R2MASK SIO2 receive 0 Masks disables interrupt request O interrupt mask bit 1 Enables interrupt request 14 15 No functions assigned 0 mE This register enables or disables interrupt requests generated by each SIO Interrupt requests from an SIO are enabled by setting its corresponding interrupt mask bit to 1 12 10 Ver 0 10 1 2 SERIAL I O 12 2 Serial Related Registers SIOO3 Cause of Receive Interrupt Select Register SIO3SEL Address H 0080 0102 gt DO 1 2 3 4 5 6 D7 ISRO ISR1 ISR2 When reset 00 gt D Bit Name Function R 0 3 No functions assigned 0 4 ISRO SIOO receive interrupt 0 Receive finished interrupt O O cause select bit 1 Receive error interrupt 5 ISR1 SIO1 receive interrupt 0 Receive finished interrupt O O cause select bit 1 R
473. me Function R 8 15 Transmit error count value Q Transmit error counter In an error active error passive state a transmit error count is stored in this register When transmitted normally the counter counts down when an error occurs the counter counts up In bus off state an indeterminate value is stored in this register The count is reset to H 00 upon returning to an error active state 13 20 Ver 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers 13 2 7 CAN Baud Rate Prescaler CANO Baud Rate Prescaler CANOBRP Address H 0080 10162 DO 1 2 3 4 5 6 D7 CANBRP When reset H 01 gt D Bit Name Function R 0 7 Selects baud rate prescaler value This register sets the period of The CAN baud rate is determined by period x number of Tq s for 1 bit Tq period CANBRP 1 CPU clock 1 Tq period x number of Tq s for 1 bit CAN transfer baud rate Number of Tq s for 1 bit Synchronization Segment Progagation Segment Phase Segment 1 Phase Segment 2 Note Setting H 00 divided by 1 is inhibited 13 21 Ver 0 10 13 CAN MODULE 13 2 CAN Module Related Registers 13 2 8 CAN Interrupt Related Registers CANO Slot Interrupt Status Register CANOSLIST Address H 0080 100 gt DO 1 2 3 4 5 6 7 8 9 10 11 12
474. me clock period as count is disabled by writing to the enable bit the latter has priority so that count is disabled When you read the counter immediately after reloading it pursuant to underflow the value you get is temporarily H FFFF But this counter value immediately changes to reload value 1 at the next clock edge Because the internal circuit operation is synchronized to the count clock prescaler output a finite time equal to a prescaler delay is included before F F starts operating after the timer is enabled Write to enable bit ME ME Prescaler cycle gt Count clock 2 22 Internal clock Enable Delay till prescaler cycle gt X F F operation Figure 10 3 22 Prescaler Delay 10 81 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer 10 4 TIO Input Output related 16 bit Timer 10 4 4 Outline of TIO TIO Timer Input Output is an input output related 16 bit timer whose operation mode can be selected from the following by mode switching in software Input mode Measure clear input mode Measure free run input mode Nose processing input mode Output mode without correction function PWM output mode Single shot output mode Delayed single shot output mode Continuous output mode The following shows TIO specifications Figure 10
475. mes 1 enne 13 69 13 7 1 Remote Frame Transmit Procedure 13 69 13 7 2 Remote Frame Transmit Operation 13 71 13 7 3 Reading Out Received Data Frames when Set for Remote Frame Transmission 13 74 9 13 8 Receiving Remote Frames nnmnnn nnna 13 76 13 8 4 Remote Frame Receive Procedure 13 76 13 8 2 Remote Frame Receive Operation 13 78 CHAPTER 14 REAL TIME DEBUGGER RTD 14 1 Outline of the Real Time Debugger RTD 14 2 14 2 Pin Function of the RTD nennen nennt 14 3 14 3 Functional Description of the RTD nnmnnn 14 4 14 3 1 Outline of RTD Operation 14 4 14 3 2 Operation of RDR Real time RAM Content Output 14 5 14 3 3 Operation of WRR RAM Content Forcible Rewrite 14 7 14 3 4 Operation of VER Continuous Monitor 14 9 14 3 5 Operation of VEI Interrupt Request 14 10 14 3 6 Operation of RCV Recover from Runaway 14 11 14 3 7 Method to Set a Specified Address when Using the RTD
476. mode In PWM output mode the timer uses two reload registers to generate a waveform with a given duty cycle When after setting the initial values in reload 0 and reload 1 registers the timer is enabled by writing to the enable bit in software or by external input it loads the reload 0 register value into the counter synchronously with the count clock letting the counter start counting down The first time the counter underflows the reload 1 register value is loaded into the counter letting it continue counting Thereafter the counter is reloaded with the reload 0 and reload 1 register values alternately each time an underflow occurs The valid count values are reload 0 register set value 1 and reload 1 register set value 1 The timer stops at the same time count is disabled by writing to the enable bit and not in synchronism with PWM output period The F F output waveform in PWM output mode is inverted F F output levels change from low to high or vice versa at count startup and upon each underflow An interrupt can be generated when the counter underflows every other time second time fourth time and so on after being enabled Note that TIO s PWM output mode does not have the correction function 10 112 Ver 0 10 10 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer Count clock H FFFF Counter L H 0000 Reload 0 register Reload 1 register TIO interrupt by underflow
477. mode the contents of the internal RAM are retained while the power is turned off RAM backup mode is used for the following two purposes Back up the internal RAM data when the power is down Turn off the power to the CPU whenever necessary to save on the system s power consumption The 32R E CPU is placed in RAM backup mode by applying a voltage of 2 0 3 3 V to the VDD pin provided for RAM backup and 0 V to all other pins During RAM backup mode the contents of the internal RAM are retained while the CPU and internal peripheral I O remain idle Also because all pins except VDD are held low during RAM backup mode power consumption in the system can effectively reduced 17 2 Example of RAM Backup when Power is Down A typical circuit for RAM backup at power outage is shown in Figure 17 2 1 The following explains how the RAM can be backed up by using this circuit as an example Regulator Output DC IN Input 5V system 4 Regulator Output 3 3V system Power supply C monitor IC Backup power supply for power outage Note 1 Reference voltage for power outage detection VDD VCCI 5 VCCE VREFn AVCCn t Note 3 Power outage __ 5 vel OUT detection signal SBI Backup battery um 77 77 Note 1 Power outage is detected by the DC IN regulator input voltage Note 2 These pins are used to detect a RAM backup signal Note 3 This pin outputs a high when the power
478. mp 46 BC 1 control 0 amp 45 BC 4 P95 observe only X amp 44 BC_1 P95 output3 X 43 0 Z amp 43 1 control 0 amp 42 BC 4 P96 observe only X amp 41 BC_1 P96 output3 X 40 0 Z amp 40 BC 1 control 0 amp 89 BC 4 P97 observe only X amp 38 BC_1 P97 output3 X 37 0 Z amp 37 1 control 0 amp 96 BC 4 RESET observe only X amp 35 BC 4 MODO observe only X amp 34 4 MODI observe_only X amp 33 BC_4 FP observe_only X amp 32 BC_4 P110 observe_only X amp 31 1 110 output3 X 30 0 2 amp 30 BC 1 control 0 amp 29 4 P111 observe only X amp 28 BC_1 P111 outputs X 27 0 2 amp 27 BC_1 control 0 amp 26 BC_4 P112 observe_only X amp 25 BC_1 P112 outputs X 24 0 Z amp 24 BC_1 control 0 amp 23 BC_4 P113 observe_only X amp 22 BC_1 P113 output X 21 0 Z amp 21 BC 1 control 0 amp 20 BC 4 P114 observe only X amp 19 BC_1 P114 output X 18 0 2 amp 18 1 control 0 amp 17 4 P115 observe only X amp 16 1 115 output3 X 15 0 2 amp 15 BC 1 control 0 amp 14 BC 4 P116 observe only X amp 13 1 116 output3 X 12 0 2 amp 12 1 control 0 amp Figur
479. mp RESET 91 amp MODO 92 amp Figure 19 5 5 BSDL Description for the 32171 5 14 19 19 Ver 0 10 19 JTAG 19 5 Boundary Scan Description Language MOD1 95 VSS 96 P110 P111 P112 py py py py py P4 py P4 13 14 15 16 17 00 01 02 VDD 108 TMS TRST TDO TDI P1 P1 P1 P1 P1 P1 P1 P1 P1 VCCI 123 P1 P1 P1 P1 P1 P1 P1 P1 03 04 05 06 07 24 25 26 27 30 31 32 33 34 35 36 37 VCCE 132 PY P1 50 53 P41 P42 137 VSS 138 P43 P44 P45 P46 P47 P220 93 94 amp 95 amp 96 amp 97 amp 98 amp 99 amp 100 amp 101 amp 102 amp 1103 amp 104 amp 1105 amp 1106 amp 107 amp 108 amp 109 amp 110 amp 411 amp 1112 amp 113 amp 114 amp 115 amp 1116 amp 117 amp 118 amp 119 amp 120 amp 121 amp 122 amp 123 amp 124 amp 125 amp 126 amp 127 amp 128 amp 129 amp 1130 amp 181 amp 132 amp 133 amp 184 amp 1385 amp 136 amp 137 amp 138 amp 1139 amp 140 amp 141 amp 142 amp 143 amp 144 Figure 19 5 6 BSDL Description for the 32171 6 14 19 20 Ver 0 10 19 JTAG 19 5 Boundary Scan Description Language MDM SYSTEM amp
480. mpleted Generation Register software start or one DMA2 transfer is completed cascade mode 0 1 A DO conversion completed When A D0O conversion is completed 1 0 MJT TIO8 udf When MJT 8 underflow occurs 1 1 MJT input event bus 2 When MJT s input event bus 2 signal is generated Table 9 3 2 Causes of DMA Requests in DMA1 and Generation Timings REQSL1 Cause of DMA Request DMA Request Generation Timing 0 0 Software start When any data is written to DMA1 Software Request Generation Register 0 1 MJT output event bus 0 When MJT s output event bus 0 signal is generated 1 0 None Use inhibited 1 1 One DMAO transfer completed When one DMAO transfer is completed cascade mode 9 27 Ver 0 10 DMAC 9 3 Functional Description of the DMAC Table 9 3 3 Causes of DMA Requests in DMA2 and Generation Timings Cause of DMA Request DMA Request Generation Timing Software start When any data is written to DMA2 Software Request Generation Register MJT output event bus 1 When MJT s output event bus 1 signal is generated MJT TIN18 input signal When MJT s TIN18 input signal is generated One DMA 1 transfer completed When transfer is completed cascade mode Causes of DMA Requests in DMA3 and Generation Timings Cause of DMA Request DMA Request Generation Timing Software start When any data is written to DMA3 Software Request Generation Register Serial 1 00 transmit buffer empty
481. n bit Note 1 bits listed below have no functions assigned They show a 0 when read writing to these bits has no effect P40 P60 P65 P67 P90 P92 P120 P123 P151 P152 P154 P157 P170 P173 P176 P177 P222 P224 P226 P227 Note 2 When reset all ports are placed in input mode Note 3 Port P64 is input mode only The register does not have a P64DIR bit Note 4 Port P221 is input mode only The register does not have a P221DIR bit Note 5 Ports P80 and P81 are input mode only The register does not have P80DIR and P81DIR bits Note 6 P14 P16 and P18 P21 do not have data registers 8 9 Ver 0 10 8 INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 3 Input Output Port Related Registers 8 3 3 Port Operation Mode Registers E P7 Operation Mode Register P7MOD Address H 0080 0747 D8 9 10 11 12 13 14 D15 P70MOD P71MOD P72MOD P73MOD P74MOD P75MOD P76MOD P77MOD When reset 00 gt D Bit Name Function R 8 P70MOD 0 P70 O O Port P70 operation mode 1 BCLK WR 9 P71MOD 0 P71 Port P71 operation mode 1 WAIT 10 P72MOD 0 P72 Port P72 operation mode 1 HREQ 11 P73MOD 0 P73 O O Port P73 operation mode 1 HACK 12 P74MOD 0 P74 O O Port P74 operation mode 1 RTDTXD 13 P75MOD 0 P75 Port P75 operation mode 1 RTDRXD 14 P76MOD 0 P76 Port P76 operation mode 1 RTDACK 15 P77MOD 0 P77
482. n outputs a high when the power is on and outputs a low when the power is down Note 4 Determined by the input voltage level on SBI or ADnINI pin Note 5 Adjust this capacitance to provid the RAM backup mode necessary processing time in Figure 17 2 3 RAM Backup State at Power Outage 17 4 Ver 0 10 1 7 RAM BACKUP MODE 17 3 Example of RAM Backup for Saving Power Consumption 17 3 Example of RAM Backup for Saving Power Consumption Figure 17 3 1 shows a typical circuit for RAM backup to save on power consumption The following explains how the RAM is backed up for the purpose of low power operation by using this circuit as an example DC IN p Input Regulator Output RAM backup power supply system x Regulator Output IBA 5V system Regulator Output External circuit 3 3V system RAM backup signal Note 1 Port X VCCI 5 VCCE VREFn AVCCn VDD Note 2 SBI m Notes M32R E Note 1 This signal outputs a low for RAM backup Note 2 This pin outputs a high when the power is on and is set for input mode when in RAM backup mode Note 3 These pins are used to detect a RAM backup signal Figure 17 3 1 Typical Circuit for RAM Backup to Save on Power Consumption 17 5 Ver 0 10 1 7 BACKUP MODE 17 3 Example of RAM Backup for Saving Power Consumption 17 3 1 Normal Operating Stat
483. nals on flash programmer To system circuit Set microcomputer User system circuit Connects to A V power supply n et fo P85 TXD1 P84 SCLKIO SCLKOO esed e mH Ree a iss eer cen ies Connects to 3 3 V power supply Connects to 5 V power supply FVCC VCCI OSC VCC L voo 550 5 55 MOD1 JTRST about 2KQ operating conditions Note 1 Note 2 Note 3 Note 4 Note 5 Note 6 Turn on the power to the user system before you write to the flash memory P64 SBI must be fixed high or low to ensure that interrupts will not be generated The pullup resistances of P84 P86 and P87 must be set to suit system design conditions The typical pullup resistances of P84 P86 and P87 4 7 to 10 All other ports whether high or low do not affect flash memory programming If the system circuit uses P84 P87 consideration must be taken for connection of a serial programmer Figure 6 8 1 Pin Connection Diagram 6 50 Ver 0 10 6 INTERNAL MEMORY 6 9 Precautions to Be Taken When Rewriting Flash Memory 6 9 Precautions to Be Taken When Rewriting Flash Memory The following describes precautions to be taken when you rewrite the flash memory using a general purpose serial programmer in Boot Flash E W Enable mode When you use the pins with the system that are used by a
484. nd Special Function Register SFR area Of this a 128 Kbytes of address space from H 0080 0000 to H 0081 FFFF is the area that the user can actually use All other areas here comprise a ghost area in units of 128 Kbytes When programming do not use this ghost area The internal RAM 16 Kbyte is allocated to the addresses H 0080 4000 through H 0080 SFFF Addresses H 0080 0000 to H 0080 3FFFF are the Special Function Register SFR area This area has registers for internal peripheral I O located in it Pseudo flash emulation areas separated in units of 8 Kbytes or 4 Kbytes can be allocated here For details refer to Section 6 7 Figure 3 4 1 Internal RAM Area and Special Function Register SFR Area Ver 0 10 0 0 address 78 15 1 address H 0080 0000 H 0080 007E Interrupt controller ICU H 0080 0080 A DO converter H 0080 00 gt H 0080 0100 5 H 0080 0146 Serial 1 00 22 ENG H 0080 0180 Wait controller oN nee 0200 H 0080 023E H 0080 0240 5 H 0080 02FE H 0080 0300 H 0080 03 H 0080 03 0 5 H 0080 0308 MJT common part MJT TMS UNA H 0080 03E0 H 0080 OSFE MJT TMLO Multijunction timer MJT H 0080 0400 H 0080 0478 DMAC 2232 TN H 0080 0700 H 0080 0756 Input output port H 0080 0760 7 H 0080 07F2 H 0080 OFEO H 008
485. nd Trap 1 Exception This is an event related to the context being executed It is generated by an error or violation during instruction execution In the M32R E this type of event includes Address Exception AE and Reserved Instruction Exception RIE 2 Interrupt This is an event generated irrespective of the context being executed It is generated in hardware by a signal from an external source In the M32R E this type of event includes External Interrupt El System Break Interrupt SBI and Reset Interrupt RI 3 Trap This refers to a software interrupt generated by executing a TRAP instruction This type of event is intentionally generated in a program as in the OS s system call by the programmer Exception Reserved Instruction Exception RIE Address Exception AE I Interrupt Reset Interrupt RI I System Break Interrupt SBI L External Interrupt El Figure 4 1 1 Classification of EITs 4 2 Ver 0 10 4 EIT 4 2 EIT Event 4 2 EIT Event 4 2 1 Exception 1 Reserved Instruction Exception RIE Reserved Instruction Exception RIE is generated when execution of a reserved instruction unimplemented instruction is detected 2 Address Exception AE Address Exception AE is generated when an attempt is made to access a misaligned address in Load or Store instructions 4 2 2 Interrupt 1 Reset Interrupt RI Reset Interrupt RI is
486. nd those stipulated in IEEE 1149 1 standards 19 14 Ver 0 10 19 JTAG 19 5 Boundary Scan Description Language Boundary Scan Description Language BSDL for M32171F4VFP M32R E M32171 Group Flash 512KB 144P6Q Modification History Date Author Modified Version Created 99 05 07 MITSUBISHI Ver 0 1 entity 32171 is generic PHYSICAL PIN MAP string P6Q144 port P221 P225 OSCVSS 3 XIN XOUT OSCVCC 6 VONT 7 P30 P31 P32 P33 P34 P35 P36 P37 P20 P21 P22 P23 VCCE_20 VSS 21 P24 P25 P26 P27 00 01 P02 P04 05 06 P07 P10 P11 P12 P13 P14 linkage in buffer linkage linkage inout inout inout inout inout inout inout inout inout inout inout inout linkage linkage inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout inout bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit bit Figure 19 5 1 BSDL Description for the 32171 1 14 19 15 Ver 0 10 19 JTAG 19 5 Boundary Scan Description Language P15 P16 P17 VREF 42 AVCC 43 ADOINO ADOIN1 ADOIN2 ADOIN3 ADO
487. nd various error bit flags are cleared varies depending on whether an overrun error has occurred or not as described below When no overrun error has occurred Said bits can be cleared by reading the lower byte from the receive buffer register or clearing the receive enable bit to 0 When an overrun error has occurred Said bits can only be cleared by clearing the receive enable bit to 0 12 60 Ver 0 10 13 1 13 2 13 3 13 4 13 5 13 6 13 7 13 8 CHAPTER 13 CAN MODULE Outline of the CAN Module CAN Module Related Registers CAN Protocol Initializing the CAN Module Transmitting Data Frames Receiving Data Frames Transmitting Remote Frames Receiving Remote Frames 13 CAN MODULE 13 1 Outline of the CAN Module 13 1 Outline of the CAN Module The MS2R E contains CAN Controller Area Network Specification 2 0B compliant Full CAN module This module has 16 message slots and three mask registers effective use of which helps to reduce the CPU load for data processing The following outlines the Full CAN module Table 13 1 1 Outline of the CAN Module Item Protocol Content CAN Specification 2 0B Number of message slots Total 16 slots 14 global slots two local slots Polarity 0 Dominant 1 Recessive Acceptance filter One global mask Two local masks Baud rate 1 Time quantum Tq BRP 1 CPU clock BRP Baud rate prescaler set value 1 B
488. ndary register description Logical port description The logical port description assigns meaningful symbol names to each pin on the chip This determines the logic type of input output input output buffer or link of each pin that defines the logical direction of signal flow Physical pin map The physical pin map correlates the chip s logical ports to the physical pins on each package Use of separate names for each map makes it possible to define multiple physical pin maps in one BSDL description Instruction set statement The instruction set statement writes bit patterns to be shifted in into the chip s instruction register This bit pattern is necessary to place the chip into each test mode defined in standards It is also possible to write instructions exclusive to the chip Boundary register description The boundary register description is a list of boundary register cells or shift stages Each cell is assigned a separate number The cell with number 0 is located closest to the test data output JTDO pin and the cell with the largest number is located closest to the test data input JTDI pin Cells also contain related other information which includes cell type logical port corresponding to cell logical function of cell safety value control cell number disable value and result value The BSDL for the 32171 shown in the pages to follow have been prepared for use in test engineering for the purpose of PCB design a
489. nerated at 4 completion of transmission Enable disable or reception in the slot error passive interrupt Enable disable CAN bus off interrupt Set bit timing baud rate Set the number of times sampled Set ID mask bit Set loopback mode Set BasicCAN mode Set CAN Extended IDRegister Set IDs for message slots 14 and 15 Set Message Slot Control Register RET Release CAN module from reset Figure 13 4 2 Initializing the CAN Module 13 58 Ver 0 10 CAN MODULE 13 13 5 Transmitting Data Frames 13 5 Transmitting Data Frames 13 5 1 Data Frame Transmit Procedure The following describes the procedure for transmitting data frames 1 Initializing the CAN Message Slot Control Register Initialize the CAN Message Slot Control Register for the slot in which you want to transmit by writing H OO to the register 2 Confirming that transmission is idle Read the CAN Message Slot Control Register after being initialized and check the TRSTAT Transmit Receive Status bit to see that transmission has stopped and remains idle If this bit 1 it means that the CAN module is accessing the message slot so you need to wait until the bit is cleared 3 Setting transmit data Set the transmit ID and transmit data in the message slot 4 Setting the Extended ID Register Set the corresponding bit of the Extended ID Register to 0 when you want to transmit the data as a standard frame or 1 wh
490. ng scan mode operation in software select software trigger using the Single Mode Register 075 A D conversion start trigger select bit and for A D conversion set the said register s A D conversion start bit to 1 For comparate mode write the value to be compared into the A D Successive Approximation Register ADOSAR during scan mode operation To start single mode conversion during scan mode operation in hardware select hardware trigger using Single Mode Register 0 5 A D conversion start trigger select bit and enter the hardware trigger output event bus 3 specified by the said register An A D conversion interrupt request or a DMA transfer request can be generated at completion of conversion in the specified channel or at completion of one cycle of scan operation To perform single mode conversion on ADOIN5 during ADOIN2 conversion in 4 channel single shot scan mode Forcible single mode execution starts N ed Scan mode ADOINO ADOIN1 Completed conversion starts 10 bit A DO data register ADODT1 ADODT5 ADODT2 ADODT3 A D conversion interrupt request transfer request Note The canceled convert operation in channel 2 is reexecuted from the beginning Figure 11 1 6 Forcible Single Mode Execution during Scan Mode 11 10 Ver 0 10 1 1 CONVERTERS 11 1 Outline of Converters 2 Scan mode start after single mode
491. ngement Bit number 31 24 23 16 15 8 7 0 31 24 23 16 15 8 7 0 E 5 16 23 24 31 0 01234567 byte 67 45 23 01 byte 01 23 45 67 byte 01 23 45 67 Note The M32R s endian method is big endian for both bit and byte Figure 2 6 5 M32R Family Endian 2 10 Ver 0 10 CPU 2 6 Data Formats 4 Transfer instructions Constant transfer LD24 Rdest imm24 LDI Rdest imm16 LDI Rdest imm8 SETH Rdest imm16 Register to register transfer MV Rdest Rsrc Control register transfer MVFC Rdest CRsrc MVTC Rsrc CRdest LD24 Rdest imm24 0 23 Rdest SETH Rdest imm16 0 Rdest Rsrc MVTC Rsrc CRdest HENENEN 0 31 0 31 Note For the MVTC instruction the condition bit C does not change unless CRdest is CRO PSW Figure 2 6 6 Transfer instructions 241 Ver 0 10 2 2 6 Data Formats 5 Memory signed to register transfer Register Signed 32 bits Rdest LD24 Rsrc label 0 31 Signed 16 bits LD24 Rsrc label LDH Rdest Rsrc XO Fi 12 Check the MSB 0 positive 1 negative Signed 8 bits Rdest LD24 Rsrc label LDB Rdest Rsrc L 00 00 00 0 positive 1 negative Figure 2 6 7 Memory signed register transfer 6 Memory unsigned to register transfer Memory Register Unsigned 32 bits Rdest LD24 Rsrc label 0 31 Unsigned 16 bits LD24 R
492. nitialized Accordingly the receive status flag receive completed flag bit overrun error flag framing error flag parity error flag and error sum flag all are cleared The receive operation stops when the receive enable bit is cleared to 0 while receiving data 4 OVR overrun error bit 04 Set condition This bit is set to 1 when all bits of the next receive data have been received in the Receive Shift Register while the Receive Buffer Register still contains the previous receive data In this case the receive data is not stored in the Receive Buffer Register Although receive operation is continued when the overrun error flag 1 the receive data is not stored in the Receive Buffer Register To start reception normally you need to clear this bit Clear condition This bit is cleared to 0 by only clearing the REN receive enable bit 12 21 Ver 0 10 1 2 SERIAL 12 2 Serial I O Related Registers 5 PTY parity error bit D5 This bit is effective in only UART mode During CSIO mode this bit is fixed to 0 Set condition The PTY parity error bit is set to 1 when the SIO Transmit Receive Mode Register s PEN parity enable disable bit is enabled and the parity even odd of the receive data does not agree with the value that has been set by the said register s PSEL bit parity select bit Clear condition The PTY bit is cleared by reading the lower byte from the SIO Receive Buffer Register or by clearing th
493. nits iet tener otitis 9 33 9 3 7 Transfer 9 33 9 3 8 Address Space date etie eee 9 33 9 3 9 Transfer 9 33 9 3 10 End of DMA and 9 37 9 3 11 Status of Each Register after Completion of DMA Transfer 9 37 9 4 Precautions about the DMAC esses nennen nnn nnne 9 38 CHAPTER 10 MULTIJUNCTION TIMERS 10 1 Outline of Multijunction Timers 10 2 10 2 Common Units of Multijunction Timer eere 10 7 10 2 1 Timer Common Register 10 7 10 2 2 Prescaler Units iit e ee ees 10 9 10 2 3 Clock Bus Input Output Event Bus Control Unit 10 10 10 2 4 Input Processing Control 2 10 15 10 2 5 Output Flip Flop Control 10 21 10 2 6 Interrupt Control Unit 10 29 10 3 TOP Output related 16 bit Timer seen 10 45 10 31 Outline OF iret Bened tdt 10 45 10 3 2 Outline of Each Mode 10 47 10 3 3 TOP Related Register 10 49 10 3 4 TOP Control 10 52 10 3 5 TOP Counters TOPOCT TOP10CT 10 59 10 3 6 T
494. nnel is comparated compared with the Successive Approximation Register value and the result relative magnitude of two values is returned to a flag The channel to be comparated is selected using the Single Mode Register 1 analog input pin select bit The result of comparate operation is flagged 1 or 0 by setting or resetting the A D Comparate Data Register bit that corresponds to the selected channel An A D conversion interrupt request or a DMA transfer request can be generated at completion of comparate operation 11 5 Ver 0 10 1 1 5 11 1 Outline of Converters 11 1 2 Operation Modes The A D converters operate in two modes Single mode and Scan mode 1 Single mode In single mode the analog input voltage in one selected channel is A D converted once or comparated with a given quantity An A D conversion interrupt request or a DMA transfer request can be generated at completion of A D conversion M A D conversion interrupt request or DMA transfer request Conversion A Completed 0 15 starts Note ADODTn 10 bit A Di data register Note 00 conversion start Software trigger Started by setting A DO conversion start bit to 1 Hardware trigger Started by output event bus 3 Figure 11 1 2 Operation in Single Mode A D Conversion A D successive approximation register ADOSAR A D conversion interrupt request
495. nput processing selection 11 Both edges 8 9 TIN15S reserved Set these bits to 00 Note 10 11 145 reserved 12 13 135 reserved 14 15 TIN12S reserved Note Always set the TIN15S bits TIN14S bits TIN13S bits and 125 bits to 00 E TIN Input Processing Control Register 4 TINCR4 Address H 0080 021A DO 1 14 015 2 4 5 6 7 8 9 10 11 12 13 When reset H 0000 gt D Bit Name Function R 0 1 TIN33S reserved Set these bits to 00 Note 2 3 TIN32S reserved 4 5 TIN31S reserved 6 7 TIN30S reserved 8 9 TIN23S TIN23 input processing selection 00 Invalidates input O O 10 11 TIN22S 22 input processing selection 01 Rising edge 12 13 215 TIN21 input processing selection 10 Falling edge 14 15 205 20 input processing selection 11 Both edges Note Always set the TIN33S bits TIN32S bits TIN31S bits and TIN30S bits to 00 10 20 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer 10 2 5 Output Flip Flop Control Unit The output flip flop control unit controls the flip flop F F provided for each timer output Following flip flop control registers are included Source Select Register 0 FFSO F F Source Select Register 1 FFS1 F F Protect Register 0 FFPO F F Protect Register 1 FFP1 F F Data Register 0 FFDO F F Data Reg
496. nput using the Port Input Function Enable Register PIEN PIENO bit For details refer to Section 8 3 Input Output Port Related Registers 7 4 Ver 0 10 Gl BR amp EJ PUT OUTPUT PORTS AND PIN FUNCTIONS 8 1 Outline of Input Output Ports 8 2 Selecting Pin Functions 8 3 Input Output Port Related Registers 8 4 Port Peripheral Circuits 8 INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 1 Outline of Input Output Ports 8 1 Outline of Input Output Ports The 32171 has a total of 97 input output ports consisting of PO P13 P15 P17 and P22 with P5 reserved for future use however These input output ports can be used as input ports or output ports by setting up the direction registers Each input output port serves as a dual function or triple function pin sharing the pin with other internal peripheral I O or extended external bus signal line Pin functions are selected depending on the device s operation mode you choose or by setting the input output port s Operation Mode Register If any internal peripheral I O has still another function you need to set the register provided for that peripheral I O As new function the 32171 internally contains Port Input Function Enable bit that can be used to prevent current from flowing into the input ports This helps to simplify the software and hardware processing to be performed immediately after reset or during flash rewrite To use any
497. nsferred to Set by a write to transmit shift register transmit buffer Cleared by LU completion of transmission D1XD Transmit status bit TXD D7 X D6X D5X DAX D3 X D2 0 Transmit Transmit interrupt interrupt Note 4 Note 5 SIO transmit interrupt Td Note 1 Note 2 Interrupt request accepted Note 3 UM Processing by software v Interrupt generation Note 1 Change of the Interrupt Controller SIO Transmit Interrupt Control Register interrupt request bit Note 2 When transmit interrupt is enabled DMA transfer can also be requested at the same timing Note 3 The Interrupt Controller IVECT register is read or SIO Transmit Interrupt Control Register interrupt request bit cleared Note 4 Transmit interrupt request is generated when transmission is enabled Note 5 Even after transmit data is written to the transmit buffer a transmit interrupt request is generated when the data is transferred from the transmit buffer to the transmit shift register and the transmit buffer is thereby emptied Figure 12 3 3 Example of CSIO Transmission Transmitted Only Once with Transmit Interrupt Used 12 31 Ver 0 10 1 2 SERIAL 12 3 Transmit Operation CSIO Mode CSIO on transmit side CSIO on receive side SCLKO gt SCLKI as RXD Internal clock selected External clock selected
498. nsfers 256 times H FF 9 37 Ver 0 10 9 9 4 Precautions about the DMAC 9 4 Precautions about the DMAC About writing to DMAC related registers Because DMA transfer involves exchanging data via the internal bus basically you only can write to the DMAC related registers immediately after reset or when transfer is disabled transfer enable bit 0 When transfer is enabled do not write to the DMAC related registers because write operation to those registers except the DMA transfer enable bit transfer request flag and the DMA Transfer Count Register which is protected in hardware is instable The table below shows the registers that can or cannot be accessed for write Table 9 4 1 DMAC Related Registers That Can or Cannot Be Accessed for Write Status Transfer enable bit Transfer request flag Other DMAC related registers When transfer is enabled O When transfer is disabled O O Can be accessed X Cannot be accessed For even registers that can exceptionally be written to while transfer is enabled the following requirements must be met DMA Channel Control Register s transfer enable bit and transfer request flag For all other bits of the channel control register be sure to write the same data that those bits had before you wrote to the transfer enable bit or transfer request flag Note that you only can write 0 to the transfer request flag as valid data DMA Transfer Count Register W
499. nt to erase Flash memory contents erased by Erase program Note 1 1 us by hardware timer or software timer Read any address of internal flash memory to check for erase error Note 2 TIME OUT Forcibly terminated 10s YES Note 1 When Erase operation starts you have the Read Status Register command automatically entered You do not need to enter the Read Status Register command until you issue another command Note 2 Examine the Flash Status Register 2 ERESE Auto Erase operating condition WRERR1 Program operating condition 1 and WRERR2 Program operating condition 2 bits to check for erase error Figure 6 5 13 Erase All Unlock Block 6 36 Ver 0 10 INTERNAL MEMORY 6 5 Programming of the Internal Flash Memory C START D __ l Write Read Status command H 7070 to any address of internal flash memory Read any address of internal flash memory END Figure 6 5 14 Read Status Register START Write Clear Status command H 5050 to any address of internal flash memory Figure 6 5 15 Clear Status Register C START CEEE Write Read Lock Bit Status command H 7171 to any address of internal flash memory v Read the last even address of the block whose status you want to read Figure 6 5 16 Read Lock
500. nternal flash memory does not affect the pin functions 8 4 Ver 0 10 INPUT OUTPUT PORTS AND PIN FUNCTIONS 8 2 Selecting Pin Functions DBO DB1 DB2 DB3 DB4 DB5 DB6 DB7 P1 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 Settings of CPU operation mode pp A24 A25 A26 A27 A28 A29 A30 Note 1 P3 A15 A16 A17 A18 A19 A20 A21 A22 P Tr RD cso CS1 A13 A14 Reserved P5 le eee eee Ses ae Ho am P6 ME 61 P62 P63 SBI P7 FEX WAIT HREQ HACK RTDRXD RTDACK RTDCLK P8 16 17 18 019 20 P9 P10 TO8 TO9 TO10 TO11 TO12 TO13 TO14 TO15 P11 TOO TO1 TO2 TOS TO4 TOS TO6 TO7 P12 TCLKO TCLK1 TCLK2 TCLKS P13 TIN20 TIN21 TIN22 TIN23 Settings of input output port Operation Mode 14 Register P15 TINO 16 P17 TXD2 RXD2 P18 P19 P20 P21 A2 22 CTX CRX NOTED i Note 1 Pin functions are switched over by setting MODO and MOD1 pins Note 2 Pin functions are switched over by setting MODO and MOD 1 pins Also use of this pin requires caution because it has a debug event function Note 3 P14 P16 P18 P19 P20 and P21 have no functions assigned in M
501. o H FF Note 2 Set SIO Interrupt Mask Register Enable disable transmit buffer empty interrupt v Set the Interrupt Controller When using interrupt v Set DMAC When using DMAC v Set input output port Operation Mode Register Vv Initial settings for CSIO transmission finished Note 1 This is necessary when you use the internal clock Note 2 When you selected the internal clock and a divide by ratio 1 you are subject to limitations that the baud rate generator must be set not to exceed 2 Mbps Figure 12 3 1 Procedure for CSIO Transmit Initialization 12 27 Ver 0 10 1 2 SERIAL 12 3 Transmit Operation CSIO Mode 12 3 3 Starting CSIO Transmission When all of the following transmit conditions are met after you finished initialization the serial I O starts transmit operation 1 Transmit conditions when CSIO mode internal clock is selected The SIO Control Register s transmit enable bit is set to 1 Transmit data 8 bits is written to the lower byte of the SIO Transmit Buffer Register transmit buffer empty bit 0 2 Transmit conditions when CSIO mode external clock is selected The SIO Control Register 0 s transmit enable bit is set to 1 Transmit data is written to the lower byte of the SIO Transmit Buffer Register transmit buffer empty bit 0 Afalling edge of transmit clock on the SCLKI pin is detected Note 1 While the transmit enable b
502. o H FF Note Clock divider s divide by value 1 8 32 or 256 Note If the divide by value selected for the baud rate generator count source is 1 i e itself make sure the baud rate register value you set is equal to or greater than 7 12 42 Ver 0 10 1 2 SERIAL I O 12 6 Transmit Operation in UART Mode 12 6 2 UART Transmit Receive Data Formats The transmit receive data format during UART mode is determined by setting the SIO Transmit Receive Mode Register Shown below is the transmit receive data format that can be used in UART mode lt Transmit data gt data Data bits 8 bits ___________ LSB MSB ST D7 D6 D5 D4 D3 D2 D1 DO PAR SP SP ST Start bit Parity bit Stop bit Figure 12 6 1 Example of Transmit Receive Data Format in UART Mode Table 12 6 1 Transfer Data in UART Mode Bit Name Content ST start bit Indicates the beginning of data transmission This is a low signal of a one bit duration which is added immediately before the transmit data DO D8 character bits Transmit receive data transferred via serial I O In UART mode data in 7 8 or 9 bits can be transmitted received PAR parity bit Added to the transmit receive characters When parity is enabled parity is automatically set in such a way that the number of 1 s in characters including the parity bit itself is always even or odd as selected by the ev
503. o this bit and A D conversion on the channel which is in the middle of conversion is aborted with no data transferred to the A D Data Register If the A DO conversion start and A DO conversion stop bits are set to 1 simultaneously the A DO conversion stop bit is effective 7 ADOCSTT A DO conversion start bit D7 This bit is used to start scan mode operation of the A DO converter in software Only when software trigger has been selected with the ADOCSEL A DO conversion start trigger select bit A D conversion can be started by setting this bit to 1 If the A DO conversion start and A DO conversion stop bits are set to 1 simultaneously the conversion stop bit is effective When this bit is set to 1 during scan mode conversion again special operation mode Conversion restart is assumed so that scan operation restarts according to the contents set by Scan Mode Register 0 and Scan Mode Register 1 When this bit is set to 1 during A D conversion in single mode special operation mode Start scan mode after executing single mode is assumed so that scan mode operation starts on successive channels after single mode finishes 11 23 Ver 0 10 1 1 CONVERTERS 11 2 Converter Related Registers 11 2 4 A D Scan Mode Register 1 A DO Scan Mode Register 1 ADOSCM1 Address H 0080 0085 D8 9 10 11 12 13 14 D15 ANOSGAN lt When reset H 00 gt D Bit Name Function R 8 No functions
504. ode Select the internal or an external clock 2 Setting SIO Transmit Control Register Select the clock divider s divide by ratio when internal clock selected 3 Setting SIO Baud Rate Register When the internal clock is selected set a baud rate generator value Refer to Section 12 3 1 Setting the CSIO Baud Rate 4 Setting SIO Interrupt Mask Register Enable or disable the transmit buffer empty interrupt SIO Interrupt Mask Register 5 Setting the Interrupt Controller SIO Transmit Interrupt Control Register When you use a transmit buffer empty interrupt during transmission set its priority level 6 Setting DMAC When you issue DMA transfer requests to the internal DMAC when the transmit buffer is empty set the DMAC Refer to Chapter 9 DMAC 7 Selecting pin functions Because the serial I O related pins serve dual purposes shared with input output ports set pin functions Refer to Chapter 8 Input Output Ports and Pin Functions 12 26 Ver 0 10 12 SERIAL I O 12 3 Transmit Operation in CSIO Mode Initial settings for CSIO transmission v Set SIO Transmit Receive Mode Register register to CSIO mode Select internal or external clock v Set SIO Transmit Control Register e Select clock divider s divide by ratio N 1 Serial Notet related v registers Set SIO Baud Rate Register Divide by ratio H 00 t
505. ode FENTRY 1 FENTRY 0 H 0000 0000 H 0000 0000 vector entry H 0000 0080 Internal ROM area Internal ROM area vector entry H 0080 3FFF H 0080 4000 g 65086 4000 H 0080 3FFF H 0080 4000 Internal RAM Internal RAM H OOFF FFFF H OOFF FFFF Figure 6 5 1 El Vector Entry When in Flash E W Enable Mode 6 17 Ver 0 10 INTERNAL MEMORY 6 5 Programming of the Internal Flash Memory 1 When the write program does not exist in the internal flash memory Use a program in the boot ROM located on memory map to write to the flash memory To transfer the write data use serial 1 01 in clock synchronized serial mode Use this serial transfer when writing to the flash memory using a flash programmer RAM RAM Flash memory FP H FP LorH MOD1 L MODO L RESET L RAM Flash memory Step 1 gt Initial state where the write program does not exist in the flash memory SIO1 M32R E T T MOD1 L MODO H RESET H T Flash write program Flash memory CPU SIO1 M32R E FP H MOD1 L T T MOD0 H RESET H T Flash write program Flash write data M32R E Write data External device lt Step 2 gt Set the FP pin high the MODO pin high and the MOD pin low to
506. ode Register 0 ADOSIMO Address H 0080 0080 gt DO 1 2 3 4 5 6 D7 ADOSTRG ADOSSEL ADOSREQ IADOSCMP ADOSSTP ADOSSTT When reset H 04 gt D Bit Name Function R 0 1 No functions assigned 0 2 ADOSTRG 0 Use inhibited O A DO hardware trigger selection 1 Output event bus 3 3 ADOSSEL 0 Software trigger A DO conversion start trigger selection 1 Hardware trigger 4 ADOSREQ 0 A DO interrupt request O O Interrupt request DMA transfer request selection 1 DMA transfer request 5 ADOSCMP 0 A D0 conversion comparate in progress E A DO conversion comparate completed A DO conversion comparate completed 6 ADOSSTP 0 Performs no operation 0 e i A DO conversion stop Stops A DO conversion 7 ADOSSTT 0 Performs no operation 0 E A DO conversion start Starts A DO conversion A DO Single Mode Register 0 is used to control operation of the A DO converter during single mode including special mode Forcible single mode execution during scan mode 11 16 Ver 0 10 1 1 5 11 2 Converter Related Registers 1 ADOSTRG A DO hardware trigger select bit D2 When starting A D conversion of the A DO converter in hardware this bit specifies the conversion to be started by MJT output output event bus 3 If software trigger is selected with the ADOSSEL A DO conversion start trigger select bit the content of this bit
507. ogram must be prepared in the internal RAM before entering flash E W enable mode Once you ve entered flash E W enable mode you cannot use any command except flash commands to access the flash memory To access the internal flash memory in flash memory E W enable mode issue commands for the internal flash memory address to be operated on The table below lists the commands that can be issued in flash memory E W enable mode Note During flash E W enable mode the flash memory cannot be accessed for read or write wordwise Table 6 5 2 Commands in Flash Memory E W Enable Mode Command Name Issued Command Data Read Array command H FFFF Page Program command H 4141 Lock Bit Program command H 7777 Block Erase command H 2020 Erase All Unlock Block command H A7A7 Read Status Register command H 7070 Clear Status Register command H 5050 Read Lock Bit Status command H 7171 Verify command Note H DODO Note This command is used in conjunction with Lock Bit Program Block Erase and Erase All Unlock Block operations 1 Read Array command Read mode is entered by writing command data H FFFF to any address of the internal flash memory Then read the flash memory address you want to read out and the content of that address will be read out Before exiting flash E W enable mode always be sure to execute the Read Array command 6 25 Ver 0 10 INTERNAL MEMORY 6 5 Programming of the Internal Flash Memory
508. ol Register 1 The diagram below shows a typical connection of external extension memory with 8 bit data bus memory located in the CSO area and 16 bit data bus memory located in the CS1 area External extension memory can only be used in external extension mode and processor mode When CL 50 pF memory can be connected with only 2 ns data delay M32171F3 8 bit memory Memory mapping H 0000 0000 1 Internal flash memory 384KB 2 Eod i maxiMB 0000 Unused mod0000 A Di5 External 1 1 50 Zo 8 bit bus area arga H 0020 0000 External memory area 1MB 16 bit bus area 2M CS1 area max1MB R 00 015 00 015 Ghost area c Number of bus wait cycles can be set to 1 4 Normally used as port WAIT is used only when four or more wait cycles are needed Note The QS32X2245 is a product made by IDT Company Figure 15 4 3 Typical Connection of External Extension Memory Using 8 16 bit Mixed Memories when BUSMOD 1 Note The 32171 addresses and data are arranged in such a way that bit 0 MSB and bit 15 LSB Therefore the MSB and LSB sides must be reversed when connecting external extension memory 15 16 Ver 0 10 CHAPTER 16 WAIT CONTROLLER 16 1 Outline of the Wait Controller 16 2 Wait Controller Related Regi
509. old circuit Therefore make sure the analog input levels are fixed during A D conversion A D conversion completion bit readout timing If you want to read the A D conversion completion bit Single Mode Register 05 D5 bit or Scan Mode Register 05 D5 bit immediately after A D conversion has started be sure to adjust the timing one clock cycle by for example inserting a NOP instruction before you read 11 40 Ver 0 10 12 1 12 2 12 3 12 4 12 5 12 6 12 7 12 8 12 9 CHAPTER 12 SERIAL I O Outline of Serial I O Serial I O Related Registers Transmit Operation in CSIO Mode Receive Operation in CSIO Mode Precautions on Using CSIO Mode Transmit Operation in UART Mode Receive Operation in UART Mode Fixed Period Clock Output Function Precautions on Using UART Mode 1 2 SERIAL 12 1 Outline of Serial 12 1 Outline of Serial The 32171 contains a total of three serial I O channels 5100 SIO1 SIO2 Serial channels 5100 and SIO1 can be selected between CSIO mode clock synchronous serial I O and UART mode asynchronous serial I O SIO2 is UART mode only CSIO mode clock synchronous serial Communication is performed synchronously with transfer clock using the same clock on both transmit and receive sides The transfer data is 8 bits long fixed UART mode asynchronous serial Communication is performed asynchronously The transfer data length can be se
510. on 1 Incremental 7 DADSL6 0 Fixed O O Selects DMA6 destination 1 Incremental address direction W A Only writing a 0 is effective when you write 1 the previous value is retained 9 12 Ver 0 10 9 DMAC 9 2 DMAC Related Registers E DMA7 Channel Control Register DM7CNT Address H 0080 0438 DO 1 3 4 5 6 D7 MDSEL7 TREQF7 REQSEZ TENL7 TSZSL7 SADSL7 DADSL7 lt When reset H 00 gt D Bit Name Function R 0 MDSEL7 0 Normal mode Selects DMA7 transfer mode 1 Ring buffer mode 1 TREQF7 0 Not requested O A DMA7 transfer request flag 1 Requested 2 3 REQSL7 00 Software start O O Selects cause of DMA7 request 01 Serial I O2 transmit buffer empty 10 Use inhibited 11 One DMA6 transfer completed 4 TENL7 0 Disables transfer O Enables DMA7 transfer 1 Enables transfer 5 TSZSL7 0 16 bits Selects DMA7 transfer size 1 8 bits 6 SADSL7 0 Fixed Selects DMA7 source address direction 1 Incremental 7 DADSL7 0 Fixed Selects DMA7 destination 1 Incremental address direction W A Only writing a 0 is effective when you write 1 the previous value is retained 9 13 Ver 0 10 9 DMAC 9 2 DMAC Related Registers E DMAS Channel Control Register DM8CNT Address H 0080 0448 DO 1 3 4 5 6 D7 MDSEL8 TREQF8 iar d TENL8 TSZSL8 SADSL8 DADSL8
511. on condition that after processing by the SBI handler control will not return to the program that was being executed when the system break interrupt occurred Occurrence Conditions A system break interrupt is accepted by a falling edge on SBI input pin The system break interrupt cannot be masked by the PSW register IE bit In no case will a system break interrupt be activated immediately after executing a 16 bit instruction that starts from a word boundary For 16 bit branch instructions however the interrupt may be accepted immediately after branching gt Order in which instructions are executed Address 1000 Address 1002 Address 1004 Address 1008 16 bit instruction 16 bit instruction 32 bit instruction A A A x Interrupt may Interrupt Interrupt may Interrupt may be accepted cannot be be accepted be accepted accepted Figure 4 9 1 Timing at Which System Break Interrupt SBI is Accepted 4 16 Ver 0 10 EIT 4 9 Interrupt Processing EIT Processing 1 Saving SM IE and C bits The SM IE and C bits of the PSW register are saved to their backup bits the BSM BIE and BC bits BSM lt SM BIE IE BC C 2 Updating SM IE and C bits The SM IE and C bits of the PSW register are updated as shown below SM 0 IE 0 C 0 8 Saving PC The content always word boundary of the PC register is saved to the BPC register 4 Branching to the EIT vector entry
512. on execution without wasting clock cycles 3 Compact instruction code The MS2R instructions come in two types one consisting of 16 bits in length and the other consisting of 32 bits in length Use of the 16 bit length instruction format especially helps to suppress the program code size Some 32 bit long instructions can branch directly to a location 32 Mbytes forward or backward from the instruction address being executed Compared to architectures where address space is segmented this direct jump allows for easy programming 1 2 Ver 0 10 OVERVIEW 1 1 Outline of the 32171 1 1 2 Built in Multiply Accumulate Operation Function 1 Built in high speed multiplier The M32R incorporates a 32 bit x 16 bit high speed multiplier which enables it to execute a 32 bit x 32 bit integral multiplication instruction in three cycles 1 cycle 25 ns when using a 40 MHz internal CPU clock 2 Supports Multiply Accumulate operation instructions comparable to DSP The 2 supports the following four modes of Multiply Accumulate operation instructions or multiplication instructions using a 56 bit accumulator Any of these operations can be executed in one cycle 16 high order register bits x 16 high order register bits Q 16 low order register bits x 16 low order register bits Entire 32 register bits x 16 high order register bits Entire 32 register bits x 16 low order register bits The 2 has instructions to ro
513. on mode of serial I O 2 CKS internal external clock select bit D11 This bit is effective when CSIO mode is selected Setting this bit has no effect when UART mode is selected in which case the serial I O is clocked by an internal clock 3 STB stop bit length select bit 012 This bit is effective when UART mode is selected Use this bit to select the stop bit length that indicates the end of data to transmit Setting this bit to 0 selects one stop bit and setting this bit to 1 selects two stop bits During clock synchronous mode the content of this bit has no effect 4 PSEL parity odd even select bit D13 This bit is effective during UART mode When parity is enabled D14 1 use this bit to select the parity attribute whether odd or even Setting this bit to 0 selects an odd parity and setting this bit to 1 selects an even parity When parity is disabled D14 0 and during clock synchronous mode the content of this bit has no effect 5 PEN parity enable bit 014 This bit is effective during UART mode When this bit is set to 1 a parity bit is added immediately after the data bits of transmit data and for receive data the parity in it is checked The parity bit added to the transmit data is automatically determined to be a 1 or a 0 in such a way that the attribute odd even of the sum of the number of 1 s in data bits and the content of the parity bit agrees with one selected by the parity odd even select b
514. on to which valid data is transferred write enable when writing to an external device BHW BHE corresponds BLW BLE Byte low Output to the upper address DO D7 is valid BLW BLE write enable corresponds to the lower address D8 D15 is valid WAIT Wait Input When the 2 accesses an external device a low on this WAIT input extends the wait cycle HREQ Hold request Input This pin is used by an external device to request control of the external bus A low on this HREQ input causes the M32R to enter a hold state HACK Hold Output This signal is used to notify that the M32R has entered a acknowledge hold state and relinquished control of the external bus Multi DIN 23 Input Input pins for multijunction timer junction 700 7020 Timer output Output Output pins for the multijunction timer timer TCLK0 TCLK3 Timer clock Input Clock input pins for the multijunction timer A D AVCCO Analog power supply AVCCO is the power supply for the A DO converter converter Connect AVCCO to the power supply rail 550 Analog ground AVSSO is analog ground for the A DO converter Connect AVSSO to the ground 1 12 Ver 0 10 OVERVIEW 1 3 Pin Function Table 1 3 1 Description of the 32171 Pin Function 3 5 Type Pin Name Signal Name Input Output Function A D ADOINO Analog input Input 16 channel analog input pins for the A DO converter converter ADOIN15 VREFO voltage input Input VREFO
515. ons are met after you finished initialization the serial I O starts receive operation The SIO Receive Control Register s receive enable bit is set to 1 Start bit falling edge signal is applied to the RXD pin When the above conditions are met the serial I O enters UART receive operation However if the start bit when checked again at the first rise of the internal receive shift clock is detected high for reason of noise etc the serial stops receive operation and waits for the start bit again 12 7 3 Processing at End of UART Reception When data reception is completed the following operation is automatically performed in hardware 1 When reception is completed normally The receive finished receive buffer full bit is set to 1 Note 1 If a receive finished receive buffer full interrupt has been enabled an interrupt request is generated Note 2 A DMA transfer request is generated 2 When error occurs during reception When an error occurs during reception the corresponding error bit OE FE or PE and the receive sum bit are set to 1 Note 1 If a receive finished interrupt has been selected by SIO Cause of Receive Interrupt Select Register a receive finished interrupt request is generated when interrupt requests are enabled However if an overrun error has occurred this interrupt is not generated Note 2 If a receive error interrupt has been selected by SIO Cause of Receive Interrupt Select Registe
516. operation mode setup pins When connecting operation mode setup pins and the VCC or VSS pin make sure they are connected with the shortest possible wiring lt Reasons gt The levels of operation mode setup pins affect the microcomputer s operation mode When connecting operation mode setup pins and the VCC or VSS pin be careful that no noise induced potential difference will exist between operation mode setup pins and the VCC or VSS pin This is because the presence of such a potential difference makes operation mode instable which may result in the microcomputer operating erratically or getting out of control Noise Operation mode setup pins Operation mode setup pins e Figure 3 1 3 Example for Wiring of MODO and MODI Pins Appendix 3 3 Ver 0 10 3 PRECAUTIONS ABOUT NOISE Appendix 3 1 Precautions about Noise Appendix 3 1 2 Inserting a Bypass Capacitor between VSS and VCC Lines Insert a bypass capacitor of about 0 1 between VSS and VCC lines in such a way as to meet the requirements described below The wiring length between VSS pin and bypass capacitor and that between VCC pin and bypass capacitor are equal The wiring length between VSS pin and bypass capacitor and that between VCC pin and bypass capacitor are the shortest possible The VSS and VCC lines are comprised of wiring in greater width than that of other signal lines Figur
517. or framing error Occurrence of any of these errors is indicated by an error sum bit Fixed period clock function When using SIOO and SIO1 as UART this function outputs a divided by 2 BRG clock from the SCLK pin Note 1 The maximum input frequency of external clock during CSIO mode is 1 16 of f BCLK Note 2 When f BCLK is selected as the BRG count source the BRG set value is subject to limitations 12 3 Ver 0 10 12 SERIAL I O 12 1 Outline of Serial Table 12 1 2 Serial I O Interrupt Request Generation Function Serial I O Interrupt Request SIOO transmit buffer empty interrupt ICU Interrupt Cause SIOO transmit interrupt SIOO receive finished or receive error interrupt selectable SIOO receive interrupt SIO1 transmit buffer empty interrupt SIO1 transmit interrupt SIO1 receive finished or receive error interrupt selectable SIO1 receive interrupt SIO2 transmit buffer empty interrupt SIO2 3 transmit receive interrupt group interrupt SIO2 receive finished or receive error interrupt selectable SIO2 3 transmit receive interrupt group interrupt Table 12 1 3 Serial DMA Transfer Request Generation Function Serial I O DMA Transfer Request DMAC Input Channel SIOO transmit buffer empty Channel 3 SIOO receive finished Channel 4 SIO1 transmit buffer empty Channel 6 5101 receive finished Channel 3 SIO2 transmit buffer empty Channel 7 5102
518. or TOP10 there are no interrupt status and mask bits in MJT interrupt control register because it only has one source of interrupt in the group It is controlled directly by the interrupt controller 10 31 Ver 0 10 10 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer TOP Interrupt Control Register 0 TOPIRO DO 1 2 Address H 0080 0230 3 4 5 6 D7 TOPIS5 TOPIS4 TOPIS3 TOPIS2 TOPIS1 TOPISO When reset 00 gt D Bit Name Function R 0 1 No functions assigned 0 2 TOPIS5 5 interrupt status 0 No interrupt request A 3 TOPIS4 interrupt status 4 TOPIS3 interrupt status 5 TOPIS2 TOP2 interrupt status 6 TOPIS1 TOP1 interrupt status 7 TOPISO TOPO interrupt status 1 Interrupt request generated W A Only writing a 0 is effective when you write a 1 the previous value is retained E TOP Interrupt Control Register 1 TOPIR1 lt Address H 0080 0231 gt D8 9 10 11 12 13 14 D15 5 TOPIM4 2 TOPIM1 TOPIMO When reset 00 gt D Bit Name Function R 8 9 No functions assigned 0 10 5 TOP5 interrupt mask 0 Enables interrupt request O O 11 TOPIM4 TOP4 interrupt mask 1 Masks disables interrupt request 12 interrupt mask 13 TOPIM2 TOP2 int
519. ore stipulated as part of timing requirements If noise in pulse width shorter than the stipulated duration is applied to the RESET pin reset will be negated before the internal logic of the microcomputer is fully initialized causing the program to go wild Noise Reset circuit Reset circuit VSS VSS Figure 3 1 1 Wiring of the RESET Pin Appendix 3 2 Ver 0 10 INSTRUCTION PROCESSING TIME Ap pend IX 3 Appendix 3 1 Precautions about Noise 2 Wiring of clock input output pins Reduce the length of wiring connecting to the clock input output pins When connecting a capacitor to the oscillator make sure its ground lead wire and the VSS pin on the microcomputer are connected with the shortest possible wiring within 20 mm Also make sure the VSS pattern for clock oscillation is used for only the oscillator circuit and is separated from other VSS patterns lt Reasons gt The microcomputer operates synchronously with the clock generated by the oscillator circuit Inclusion of noise on clock input output pins causes the clock waveform to become distorted which may result in the microcomputer operating erratically or getting out of control Also if a noise induced potential difference exists between the microcomputer s VSS level and the oscillator s VSS level the clock fed into the microcomputer may not be an exact clock Noise Figure 3 1 2 Wiring of Clock Input Output Pins 3 Wiring of
520. ory RAM and various other peripheral functions all integrated into a single chip The M32R is based on RISC architecture Memory access is performed using load and store instructions and various arithmetic operations are executed using register to register operation instructions The 2 internally contains sixteen 32 bit general purpose registers and has 83 distinct instructions The M32R supports compound instructions such as Load amp Address Update and Store amp Address Update in addition to ordinary load and store instructions These compound instructions help to speed up data transfers 2 5 stage pipelined processing The MS32R uses 5 stage pipelined instruction processing consisting of Instruction Fetch Decode Execute Memory Access and Write Back Not just load and store instructions or register to register operation instructions compound instructions such as Load amp Address Update and Store amp Address Update also are executed in one cycle Instructions are entered into the execution stage in the order they are fetched but this does not always mean that the first instruction entered is executed first If the execution of a load or store instruction entered earlier is delayed by one or more wait cycles inserted in memory access a register to register operation instruction entered later may be executed before said load or store instruction By using out of order completion like this the M32R controls instructi
521. ossible Also do not use through holes within wiring JTAG tool Figure 19 6 1 Precautions to Be Observed when Connecting JTAG Tool when Using the 240QFP 19 29 Ver 0 10 19 JTAG 19 6 Precautions about Board Design when Connecting JTAG This is a blank page 19 30 Ver 0 10 CHAPTER 20 POWER UP POWER SHUTDOWN SEQUENCE 20 1 Configuration of the Power Supply Circuit 20 2 Power Up Sequence 20 3 Power Shutdown Sequence 20 POWER UP POWER SHUTDOWN SEQUENCE 20 1 Configuration of the Power Supply Circuit 20 1 Configuration of the Power Supply Circuit To materialize high speed operation at low power the M32R E is designed in such a way that its external interface circuits operate at 5 V power supply and all other circuits operate at 3 3 V This requires that control timing of both 5 V and 3 3 V power supplies be considered when designing your circuit 5 V power supply 3 3 V power supply 2 VCCE control circuit _ VCCI VDD FVCC A D converter circuit CPU Peripheral circuit RAM Flash OSC VCC Oscillator and PLL circuits Figure 20 1 1 Configuration of the Power Supply Circuit Table 20 1 1 List of Power Supply Functions Type of Power Supply Pin Name Function 5 0 V system VCCE Supp
522. ot 15 Extended ID1 COMSL15EID1 Address H 0080 11F3 gt D8 9 10 11 12 13 14 D15 EID4 EID5 EID6 EID7 EID8 EID9 EID10 EID11 When reset Indeterminate gt D Bit Name Function R 8 15 EID4 EID11 Extended ID4 to extended ID11 Extended ID4 to extended ID1 1 These registers are the transmit frame receive frame memory space Note When set for the receive slot standard ID format values written to EID bits when storing received data in the slot are indeterminate 13 41 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers CANO Message Slot 0 Extended ID2 COMSLOEID2 Address H 0080 1104 gt CANO Message Slot 1 Extended ID2 COMSL1EID2 Address H 0080 1114 2 CANO Message Slot 2 Extended ID2 COMSL2EID2 Address H 0080 1124 gt CANO Message Slot 3 Extended ID2 COMSL3EID2 Address H 0080 1134 gt CANO Message Slot 4 Extended ID2 COMSL4EID2 Address H 0080 1144 gt E CANO Message Slot 5 Extended 102 COMSL5EID2 Address H 0080 1154 E CANO Message Slot 6 Extended 102 COMSLGEID2 Address H 0080 1164 gt CANO Message Slot 7 Extended ID2 COMSL7EID2 Address H 0080 1174 gt E CANO Message Slot 8 Extended 102 COMSL8EID2 Address H 0080 1184 gt CANO Message Slot 9 Extended ID2 COMSL9EID2 Address H 0080 1194 gt E CANO Message Slot 10 Extended 102 COMSL10EID2 Address H 0080 11 4 gt CANO Message Slot 11 Extended ID2 COMSL11EID2 Address
523. ounted down to H FFFO As a result of this correction the count overflows to H 0004 and fails to count correctly Also an interrupt is generated for an erroneous overcount 10 71 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer Enabled by writing to enable bit or by external input Disabled by underflow Y Y Count clock Enable bit Write to E correction register Overflow occurs H FFF0 0014 200 Indeterminate Counter Actual count after overflow L 2 4 ose De Reload register H FFF8 Correction register Indeterminate Y H 0014 F F output ay Data inverted Data inverted by enable by underflow P CC TOP interrupt due to underflow Note This diagram does not show detail timing information Figure 10 3 14 Example of Operation in TOP Single shot Output Mode Where Count Overflows due to Correction 10 72 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer 10 3 10 Operation in TOP Delayed Single shot Output Mode With Correction Function 1 Outline of TOP delayed single shot output mode In delayed single shot output mode the timer generates a pulse in width of reload register set value 1 only once with the output delayed by an amount of time equal to counter set
524. ounter Low TML1CTL TML1 Control Register TML1CR TML1 Measure 3 Register High TML1MR3H TML1 Measure 3 Register Low TML1MR3L Blank addresses are reserved areas Figure 3 4 10 Register Mapping of the SFR Area 8 3 17 Ver 0 10 3 ADDRESS SPACE 3 4 Internal ROM SFR Area Address Bd 0 Address 1 Address H 0080 OFF4 TML1 Measure 2 Register High TML1MR2H H 0080 OFF6 TML1 Measure 2 Register Low TML1MR2L H 0080 OFF8 TML1 Measure 1 Register High TML1MR1H H 0080 OFFA TML1 Measure 1 Register Low TML1MR1L H 0080 OFFC TML1 Measure 0 Register High TML1MROH H 0080 OFFE TML1 Measure 0 Register Low TML1MROL i i H 0080 100 Receive Error Count Register CANOREC CANO Transmit Error Count Register CANOTEC H 0080 100C CANO Slot Interrupt Status Register CANOSLIST H 0080 100E H 0080 1010 CANO Slot Interrupt Mask Register CANOSLIMK H 0080 1012 H 0080 1014 CANO Error Interrupt Status Register CANOERIST CANO Error Interrupt Mask Register CANOERIMK H 0080 1016 CANO Baut Rate Prescaler CANOBRP H 0080 1028 CANO Global Mask Register Standard IDO COGMSKSO CANO Global Mask Register Standard ID1 COGMSKS1 H 0080 102A CANO Global Mask Register Extended IDO COGMSKEO CANO Global Mask Register Extended ID1 COGMSKE 1 H 0080 102C CANO Global Mask Register Extended ID2 COGMSKE2 H 0080 102 H 0080 1030 Register A Standard IDO COLMSKASO CANO Local Mas
525. ounter which generates clocks supplied to each timer TOP TIO TMS and TML from the divide by 2 frequency of the internal peripheral clock 10 0 MHz when the internal peripheral clock 20 MHz The values of prescaler registers are initialized to H 00 when reset Also when you rewrite the set value of any prescaler register the device starts operating with the new value simultaneously when the prescaler underflows Values H 00 to H FF can be set in the counter registers of prescalers The prescalers divide by ratios are given by the equation below 1 Prescaler divide by ratio Prescaler set value 1 Bi Prescaler Register 0 PRSO Address H 0080 0202 Bi Prescaler Register 1 PRS1 Address H 0080 0203 Bi Prescaler Register 2 PRS2 Address H 0080 0204 DO 1 2 3 4 5 6 D7 D8 9 10 11 12 13 14 D15 PRSO PRS5 When reset 00 gt D Bit Name Function R 0 7 50 2 Sets the prescaler s divide by value O O 8 15 PRS1 Prescaler Registers 0 2 start counting after reset removal 10 9 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer 10 2 3 Clock Bus Input Output Event Bus Control Unit 1 Clock bus The clock bus is provided for supplying clock to each timer and is comprised of four lines of clock bus 0 3 Each timer can use this clock bus signal as clock input signal The table below lists the
526. ounter causing it to start counting Thereafter it continues counting down clock pulses until it underflows after reaching the minimum count Enabled by writing to enable bit or by external input Disabled by underflow M Count clock HUUL EEE EEDS EEE Enable bit ene xc ees Starts counting down from the reload register set value H A000 gt Counter eh Sete bep Reload register HA000 G Correction register Not used F F output Data inverted Data inverted by enable by underflow TOP interrupt 0 2 due to underflow Note This diagram does not show detail timing information Figure 10 3 10 Typical Operation in TOP Single shot Output Mode 10 67 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer 2 Correction function of TOP single shot output mode If you want to change the counter value during operation write a value to the TOP correction register the value by which you want to be increased or reduced from the initial count set in the counter To add write the value you want to add to the correction register directly as is to subtract write the two s complement of the value you want to subtract to the correction register Correction of the counter is performed synchronously with a clock period next to the one in which the correction value was written to t
527. ounting When the RST bit is set to 1 the CAN module is reset so that after sending a frame from the slot which has had a transmit request set the protocol control unit is reset and the CAN module is disconnected from the CAN bus Frames received during this time are processed normally Note 1 11 is inhibited to set a new transmit request for a while from when the CAN Status Register CRS bit is set to 1 after setting the RST bit to 1 till when the protocol control unit is reset Note 2 When the protocol control unit is reset by setting the RST bit to 1 the CAN Time Stamp Count Register and CAN Transmit Receive Error Count Registers initialized to 0 Note 3 To restart CAN communication the FRST and RST bits must be cleared to 0 13 10 Ver 0 10 13 13 2 2 Status Register CANO Status Register CANOSTAT CAN MODULE 13 2 CAN Module Related Registers Address H 0080 1002 7 DO 1 2 3 4 6 7 8 9 10 11 12 13 14 015 BOS EPS CBS BCS LBS CRS RSB TSB RSC TSC oe lt When reset H 0100 gt D Bit Name Function R 0 No functions assigned 0 1 BOS Not Bus off Bus off status Bus off state 2 EPS Not error passive Error passive status Error passive state 3 CBS No error occurred CAN bus error Error occurred 4 BCS Normal mode BasicCAN status BasicCAN mode 5 No funct
528. over a predetermined time In noise processing input mode the counter is started by entering a high or low level signal from an external device and if the signal remains in the same state for over a predetermined time before the counter underflows the counter stops after generating an interrupt If the valid level signal being applied turns to an invalid level before the counter underflows the counter temporarily stops counting and when a valid level signal is entered again it is reloaded with the initial count and restarts counting The valid count value is reload 0 register set value 1 The timer stops at the same time the counter underflows or count is disabled by writing to the enable bit An interrupt can be generated by a counter underflow Enabled by writing to enable bit or by external input Count clock Disabled Enable bit y by underflow External input noise processing lt Invalid lt gt Invalid Counter Valid signal width Reload 0 register TIO interrupt H A000 gt CC TIO interrupt by Note This diagram does not show detail timing information underflow Figure 10 4 10 Typical Operation in Noise Processing Input Mode 10 111 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer 10 4 11 Operation in TIO PWM Output Mode 1 Outline of TIO PWM output
529. ow the peripheral circuit diagrams of the input output ports described in the preceding pages P00 P07 DBO DB7 P10 P17 DB8 DB15 P20 P27 A23 A30 P30 P37 A15 A22 P41 BLW BLE P42 BHW BHE P43 RD P44 50 P45 CST P46 P47 A13 A14 P61 P63 P225 A12 Data bus 4 DBO DB15 Direction register DEREN m DHe Port output 4 latch 24 He Zu 1 Iu Input function Note 1 Although P00 07 P10 17 P20 27 P30 37 P41 47 and P225 serve as external bus interface control signal pins during extended external mode and processor mode functional description is eliminated in this block diagram enable P75 RTDRXD P77 RTDCLK ee e P83 RXDO egiste EA a gt P86 RXD1 Data bus Port output 5 tt O P124 P127 TCLKO TCLK3 DBO DB15 latch Ly 130 137 16 23 P150 P153 TINO TIN3 P175 RXD2 t 1 A Operation i mode register Peripheral function input c 2 Input function enable Note 2 O denotes pins Figure 8 4 1 Port Peripheral Circuit Diagram 1 8 22 Ver 0 10 INPUT OUTPUT PORTS AND FUNCTIONS 8 4 Port Peripheral Circuits
530. p Prescaler bits D6 D7 These bits select the count clock source for the time stamp counter Note Do not change settings of TSP bits while CAN is operating CAN Status Register CRS bit 0 4 FRST Forcible Reset bit D11 When the FRST bit is set to 1 the CAN module is separated from the CAN bus regardless of whether or not the CAN module is communicating and the protocol control unit is reset Note 1 To restart CAN communication the FRST and RST bits must be cleared to 0 Note 2 If the FRST bit is set to 1 during communication the CTX pin output goes high immediately after that Therefore setting the FRST bit to 1 while transmitting CAN frame may cause a CAN bus error 5 BCM BasicCAN Mode bit D12 By setting this bit to 1 the CAN module can be operated in BasicCAN mode Operation during BasicCAN mode In BasicCAN mode two local slots slots 14 and 15 are used as double buffers and receive frames that are found matching to the ID by acceptance filtering are stored alternately in slots 14 and 15 Used for this acceptance filtering when slot 14 is active next receive frame to be stored in slot 14 are the ID set for slot 14 and local mask A and those used when slot 15 is active are the ID set for slot 15 and local mask B Two types of frames data frame and remote frame can be received in this mode 13 9 Ver 0 10 1 3 MODULE 13 2 CAN Module Related Registers By using the same ID and setting the sam
531. ped and remains idle If this bit 1 it means that the CAN module is accessing the message slot so you need to wait until the bit is cleared 3 Setting the receive ID Set the ID you want to receive in the message slot 4 Setting the Extended ID Register Set the corresponding bit of the Extended ID Register to 0 when you want to receive a standard frame or 1 when you want to receive an extended frame b Setting the CAN Message Slot Control Register Write H 40 to the CAN Message Slot Control Register to set the RR Receive Request bit to 1 13 63 Ver 0 10 13 CAN MODULE 13 6 Receiving Data Frames Data frame receive procedure Initialize CAN Message Slot Control Register Read CAN Message Slot Control Register TRSTAT bit 0 Set ID in message slot Set Extended ID Register Set CAN Message Slot Control Register Settings completed Write 00 Verify that reception is idle Standard ID or extended ID Write H 40 receive request Figure 13 6 1 Data Frame Receive Procedure 13 64 Ver 0 10 CAN MODULE 13 13 6 Receiving Data Frames 13 6 2 Data Frame Receive Operation The following describes data frame receive operation The operations described below are automatically performed in hardware 1 Acceptance filtering When the CAN module finished receiving data it starts searching for the slot that satisfies conditions for receiving the received message
532. pin beginning with the LSB The JTDO pin outputs valid data in only Shift IR state of IR path sequence and Shift DR state of DR path sequence In all other states the JTDO pin is tristated high impedance Note 3 Data can only be read out from the data register which is selected by the instruction that was set in the immediately preceding IR path sequence Output in the selected data register s shift register stage is the value that was sampled during Capture DR state Figure 19 4 5 Continuous JTAG Access 19 13 Ver 0 10 1 9 JTAG 19 5 Boundary Scan Description Language 19 5 Boundary Scan Description Language The Boundary Scan Description Language abbreviated BSDL is stipulated in supplements to Standard Test Access Port and Boundary Scan Architecture of IEEE 1149 1 1990 and IEEE 1149 1a 1993 BSDL is a subset of IEEE 1076 1993 Standard VHSIC Hardware Description Language VHDL BSDL helps to precisely describe the functions of standard compliant components to be tested For package connection test this language is used by Automated Test Pattern Generation tools and for synthesized test logic and verification it is used by Electronic Design Automation tools BSDL provides powerful extended functions usable in internal test generation and necessary to write hardware debug and diagnostics software The primary section of BSDL contains statements of logical port description physical pin map instruction set and bou
533. pled Note 2 BCLK is not output Figure 16 3 12 Read Write Timing for Access with 4 Internal Wait Cycles 16 17 Ver 0 10 1 6 WAIT CONTROLLER 16 3 Typical Operation of the Wait Controller Read d Read 6 cycles E 1 external 4 internal wait cycles wait cycle a gt a gt BCLK i A12 A30 77 50 CS1 LK X 2 55 WR Wn BHE BLE 77 7 77 DBO 0815 _ o T o Don t Care TE Write 6 Write ta rite 6 cycles S 1 external 4 internal wait cycles cycle EX BCLK i 12 3077 RD wR mA BLE I 17 DBO DB15 Ween 2 27 Don t Care L Note 1 Circles above indicate points at which signals are sampled Note 2 BCLK is not output Figure 16 3 13 Read Write Timing for Access with 4 Internal and 1 External Wait Cycles 16 18 Ver 0 10 WAIT CONTROLLER 16 3 Typical Operation of the Wait Controller 16 Read o gt T _ 5 WAH gt Y c
534. ports in input mode you need to set the Port Input Function Enable bit accordingly The input output ports are outlined in the next pages 8 2 Ver 0 10 INPUT OUTPUT PORTS AND FUNCTIONS Table 8 1 1 Outline of Input Output Ports 8 1 Outline of Input Output Ports Item Specification Number of ports Total 97 lines PO POO P07 8 lines P1 P10 P17 8 lines P2 P20 P27 8 lines P3 P30 P37 8 lines P4 P41 P47 7 lines P6 P61 P64 4 lines P7 P70 P77 8 lines P8 P82 P87 6 lines 9 P93 P97 5 lines P10 100 107 8lines P11 P110 P117 8 lines P12 P124 P127 4lines P13 P130 P137 8 lines P15 P150 P153 2 lines P17 P174 P175 2 lines P22 P220 P221 P225 3 lines Port function The input output ports can individually be set for input or output mode using the Direction Control Register provided for each input output port However P64 is an SBI input only port and P221 is a CAN input only port Pin function Shared with peripheral I O or extended external signals to serve dual functions with two or more peripheral I O functions to serve multiple functions Pin function switchover PO P4 P225 P6 P22 Depends on CPU operation mode determined by setting MODO and MOD pins As set by each input output port s Operation Mode Note P14 16 and 18 21 are nonexistent Register However peripheral I O pin functions are selected by periphe
535. power is on and for backup RAM is set for input mode when in RAM backup mode Note 3 These pins are used to detect a RAM backup Set transistor s base connecting pin port X for signal input mode Note 5 Note 4 Determined by the input voltage level on SBI pin or ADnINi pin RAM backup mode Note 5 Base voltage IB 0 causes the current fed to the VCC pin to stop Explained in A to D above Figure 17 3 3 RAM Backup State for Low Power Operation 17 7 Ver 0 10 1 7 RAM BACKUP MODE 17 3 Example of RAM Backup for Saving Power Consumption Power on RAM backup 4 5 0V period VREFn AVCCn Lu hv VCCI 3 3 5 lt v ov VDD i 1 Port output setting Portinput Port output setting High level mode High level Port X External input External input 2 23 signal goes low ona goes high SBI i ADnINi f XIN Oscillation 12 Oscillation stabilization time Stabilization time RESET Figure 17 3 4 Example of RAM Backup Sequence for Low Power Operation 17 3 3 Precautions to Be Observed at Power on When changing port X from input mode to output mode after power on pay attention to the following If port X is set for output mode while no data is set in the Port X Data Register the port s initial output level is indeterminat
536. pt Enable IE and Condition bit C The BPSW field consists of backup bits of the foregoing i e Backup SM bit BSM Backup IE bit BIE and Backup C bit BC BPSW field PSW field 0 MSB 7 8 15 16 17 2L 25 31 LSB PSW 00000000 00000000 00000 00000 5 BIE BC SM IE C Note 1 D Bit Name Function Initial R Ww 16 BSM Backup SM Holds the value of SM bit when EIT Indeterminate is accepted 17 BIE Backup IE Holds the value of IE bit when EIT Indeterminate is accepted 23 BC Backup C Holds the value of C bit when EIT Indeterminate O is accepted 24 SM Stack Mode 0 Interrupt stack pointer is used 0 oO 1 User stack pointer is used 25 IE Interrupt Enable 0 No interrupt is accepted 0 oO 1 Interrupt is accepted 31 Condition bit Depending on instruction execution it indicates 0 whether operation resulted carry borrow or overflow Notes 1 Initial shows the state immediately after reset R means the register is readable W means the register is writable 2 For changes of the state of each bit when an EIT event occurs refer to Chapter 4 EIT 2 4 Ver 0 10 2 2 3 Control Registers 2 3 2 Condition Bit Register CBR CR1 The Condition Bit Register CBR is created as a separate register from the PSW by extracting the Condition bit C from it The value written to t
537. quirements Unless otherwise noted timing conditions are VOCE 5 V 0 5 V VCCI 3 3 V 0 3 V 40 to 125 C The characteristic values apply to the case of concentrated capacitance with an output load capacitance of 15 to 50 pF however 80 pF for JTAG related In cases where the output load capacitance varies they may deviate from the rated switching characteristics 1 Input output ports Symbol Parameter ReedVaue Value iui See 2 Serial I O a CSIO mode with internal clock selected Symbol Parameter Condition Rated Value i Figure MAX b CSIO mode with external clock selected Symbol Parameter Condition Rated Value i Figure MN O MAX 21 5 2 ees 1 6 ees moms _ 3 SBI Symbol Parameter Condition Rated Value Unit See Figure 21 12 Ver 0 10 21 ELECTRICAL CHARACTERISTICS 21 5 AC Characteristics 4 TINI i20 3 16 23 Symbol Parameter Condition Rated Value Rated Value Value Figure 21 5 5 5 Read and write timing eus pesseesen 3 218 o 5 esee r eme _ wem heH Data Input Hold Time after Read Hol
538. r a receive error interrupt request is generated when interrupt requests are enabled Note 3 No DMA transfer requests are generated 12 54 Ver 0 10 12 SERIAL I O 12 7 Receive Operation in UART Mode The following processing is automatically executed in hardware UART receive operation starts Transmit conditions met Start bit detected ormally Y Vv Set receive status bit to 1 Vv Receive data Overrun error iN Transfer data from SIO Receive Shift Register to SIO Receive Buffer Register Set SIO Receive Control Register s overrun error bit and error sum bit to 1 Parity error or framing error N Set SIO Receive Control Register s corresponding error bit and receive error sum bit to 1 Set SIO Receive Control Register s receive finished bit to 1 UART reception completed Figure 12 7 2 Receive Operation during UART Mode Hardware Processing 12 55 Ver 0 10 1 2 SERIAL I O 12 7 Receive Operation in UART Mode 12 7 4 Typical UART Receive Operation The following shows a typical receive operation in UART mode UART on receive side lt UART on transmit side TXD RXD gare Ug Internal clock selected UART on receive side Set
539. r ADODTO ADODT1 ADODTO ADODT1 ADODT2 ADODT3 27 conversion interrupt request or transfer request Figure 11 1 9 Restarting Conversion during Scan Operation 11 12 Ver 0 10 1 1 CONVERTERS 11 1 Outline of Converters 11 1 4 A D Converter Interrupt and DMA Transfer Requests The A D converter can generate an A D conversion interrupt request or DMA transfer request at completion of A D conversion comparate operation or one shot scan or when each cycle of continuous scan mode is completed To select between A D conversion interrupt or DMA transfer requests to generate use Single Mode Register 0 and Scan Mode Register 0 A DO Scan Mode Register 0 interrupt request DMA transfer request select bit Y Scan mode when one cycle of scan completed A DO conversion interrupt request To the interrupt controller DMA transfer request To the DMAC Single mode when A D conversion or comparate operation completed A DO Single Mode Register 0 interrupt request DMA transfer request select bit Figure 11 1 10 Selecting between Interrupt Request and DMA Transfer Request 11 13 Ver 0 10 11 11 2 CONVERTERS Converter Related Registers 11 2 A D Converter Related Registers The diagrams below show an A D converter related register map Address H 0080 H 0080 H 0080 H 0080 H 0080
540. r Supply Voltage VDD2VCCIZFVCC OSC VCC 0 3 to 4 2 Flash Power Supply Voltage VDD2VCCIZ2FVCC OSC VCC 0 3 to 4 2 External I O Buffer Voltage VCCE2 AVCC VREF 0 3 to 6 5 Analog Power Supply Voltage VCCE2AVCC VREF 0 3 to 6 5 Analog Reference Voltage VCCEZ 2 VREF 0 3 to 6 5 Xin VONT 0 3 to OSC VCC 0 3 Other 0 3 to VCCE 0 3 Xout 0 3 to OSC VCC 0 3 Other 0 3 to VCCE 0 3 Power Dissipation Ta 40 to 85 C 600 Ta 40 to 125 C 500 Operating Ambient Temperature Note 40 to 125 Storage Temperature 65 to 150 Note This does not guarantee that the device can operate continuously at 125 C If you are considering the use of this product in 125 C application please consult Mitsubishi 21 2 Ver 0 10 21 ELECTRICAL CHARACTERISTICS 21 2 Recommended Operating Conditions 21 2 Recommended Operating Conditions Recommended Operating Conditions Referenced to VOCE 5 V 0 5 V VCCI 3 3 V 0 3 V Ta 40 to 85 Unless Otherwise Noted Symbol Parameter Rated Value Unit Ports PO P22 RESET VIH Input High Voltage Ports PO P1 external extension processor Gide only WAIT 0 43VCCE VCCE V Ports 22 RESET VIL nput Low Voltage 0 16VCCE V Ports PO P1 external extension processor Bs only WAIT High State Peak Output Current PO P22 High State Average Output Current PO P22 E IOH
541. r external access with one wait cycle When the 32171 accesses external circuits it requires at least one wait cycle inserted Appendix 2 3 Ver 0 10 INSTRUCTION PROCESSING TIME Appendix 2 1 32171 Instruction Processing Time Appendix 2 This is a blank page Appendix 2 4 Ver 0 10 APPENDIX 9 PRECAUTIONS ABOUT NOISE Appendix 3 1 Precautions about Noise PRECAUTIONS ABOUT NOISE Ap pend IX 3 Appendix 3 1 Precautions about Noise Appendix 3 1 Precautions about Noise The following describes precautions to be taken about noise and corrective measures against noise The corrective measures described here are theoretically effective for noise but require that the application system with these measures incorporated be fully evaluated before it can actually be put to use Appendix 3 1 1 Reduction of Wiring Length Wiring on the board may serve as an antenna to draws noise into the microcomputer Shorter the total wiring length the smaller the possibility of drawing noise into the microcomputer 1 Wiring of the RESET pin Reduce the length of wiring connecting to the RESET pin Especially when connecting a capacitor between the RESET and VSS pins make sure it is connected to each pin with the shortest possible wiring within 20 mm lt Reasons gt Reset is a function to initialize the internal logic of the microcomputer The pulse width applied to the RESET pin is important and is theref
542. r ome 2 ee NS NE SIE HZ 31 gt Note 1 Circles O above indicate points at which signals are sampled Note 2 Hi z indicate the high impedance state Note 3 Idle cycles are inserted only when the hold state is assumed after external lead access Figure 15 3 2 Bus Arbitration Timing 15 1 3 Ver 0 10 15 EXTERNAL BUS INTERFACE 15 4 Typical Connection of External Extension Memory 15 4 Typical Connection of External Extension Memory 1 When Bus Mode Control Register 0 A typical connection when using external extension memory is shown in Figure 15 4 1 External extension memory can only be used in external extension mode and processor mode M32171F3 Flash memory Memory mapping 1 H 0000 0000 i Internal flash memory 384KB H 0006 0000 Unused max1MB H 000F FFFF H 0010 0000 External memory area 1 FFF H 0020 0000 External memory area 1MB 015 max512MB 2 i total 1MB i H 0030 0000 i Ghost area WR 00 7 i WR D8 D15 RD 00 015 1 H 0040 0000 CS Number of bus wait cycles can be set to 1 4 Normally used as port WAIT is used only when four or more wait cycles are needed Figure 15 4 1 Typical Connection of External Extension Memory When BUSMOD 0 Note The 32171 addresses and data are arranged in such a way that bit 0 MSB
543. ral I O registers 8 3 Ver 0 10 8 PORTS AND FUNCTIONS 8 2 Selecting Pin Functions 8 2 Selecting Pin Functions Each input output port serves dual purposes along with other internal peripheral l Os or extended external bus signal lines or triple purposes along with multiple functions of peripheral I O Pin functions are selected according to the operation modes set or using the input output port operation mode registers When the selected CPU operation mode is extended external mode or processor mode 4 and P225 all are switched to signal pins for external access The operation mode is determined depending on how MODO and MOD pins are set See the table below Table 8 2 1 CPU Operation Modes and 4 and P225 Pin Functions MODO MOD1 Operation Mode Pin Functions of PO P4 P225 VSS VSS Single chip mode input output port pin VSS VCC Extended external mode Extended external signal pin VCC VSS Processor mode VCC VCC Reserved Use inhibited Note VCC 5 V and VSS GND Ports 6 13 P15 P17 and P22 except for P64 P221 P225 have their pin functions switched between input output ports and internal peripheral I Os by setting up the input output port operation mode registers If any internal peripheral has multiple functions select the desired pin function using the relevant internal peripheral I O register Operation on FP and MOD 1 pins during write to the i
544. rame receive frame memory space 13 39 Ver 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers CANO Message Slot 0 Extended IDO COMSLOEIDO Address H 0080 1102 CANO Message Slot 1 Extended IDO COMSL1EIDO Address H 0080 1112 2 CANO Message Slot 2 Extended IDO COMSL2EIDO Address H 0080 1122 gt CANO Message Slot 3 Extended 0 COMSLSEIDO Address H 0080 1132 E CANO Message Slot 4 Extended 100 COMSL4EIDO Address H 0080 1142 E CANO Message Slot 5 Extended 100 COMSLSEIDO Address H 0080 1152 E CANO Message Slot 6 Extended 100 COMSL6EIDO Address H 0080 1162 CANO Message Slot 7 Extended IDO COMSL7EIDO Address H 0080 1172 gt E CANO Message Slot 8 Extended 100 COMSLSEIDO Address H 0080 1182 E CANO Message Slot 9 Extended 100 COMSL9EIDO Address H 0080 1192 E CANO Message Slot 10 Extended IDO COMSL10EIDO Address H 0080 11 2 gt E CANO Message Slot 11 Extended IDO COMSL11EIDO Address H 0080 11B2 E CANO Message Slot 12 Extended IDO COMSL12EIDO Address H 0080 11C2 gt E CANO Message Slot 13 Extended IDO COMSL13EIDO Address H 0080 11D2 gt CANO Message Slot 14 Extended IDO COMSL14EIDO Address H 0080 11 2 gt E CANO Message Slot 15 Extended IDO COMSL15EIDO Address H 0080 11 2 gt DO 1 2 3 4 5 6 D7 EIDO EID1 EID2 EID3 When reset Indeterminate gt D Bit Name Function R 0 3 No functions assigned 0 4 7 EIDO EID3 Exten
545. ransfer is terminated when the transfer count register underflows When transfer finishes the transfer enable bit is cleared to 0 and transfers are thereby disabled Also an interrupt request is generated at completion of transfer However this interrupt is not generated for channels where interrupt requests have been masked by the DMA Interrupt Mask Register During ring buffer mode the transfer count register operates in free run mode and transfer continues until the transfer enable bit is cleared to 0 to disable transfer In this case therefore the DMA transfer completed interrupt request is not generated Nor is this interrupt request generated even when transfer in ring buffer mode is terminated by clearing the transfer enable bit 9 3 11 Status of Each Register after Completion of DMA Transfer When DMA transfer is completed the status of the source address and destination address registers becomes as follows 1 Address fixed The value set in the address register before DMA transfer started remains intact fixed 2 Address incremental For 8 bit transfer the value of the address register is the last transfer address 1 For 16 bit transfer the value of the address register is the last transfer address 2 The transfer count register when DMA transfer completed is in an underflow state H FF Therefore to perform another DMA transfer set the transfer count register newly again except when you are performing tra
546. ransmit Request Remote or H 70 Transmit Request Remote Automatic Response Disable is written to the CAN Message Slot Control Register the RA Remote Active bit is set to 1 indicating that the corresponding slot is to handle remote frames 2 Acceptance filtering When the CAN module finished receiving data it starts searching for the slot that satisfies conditions for receiving the received message sequentially from slot O up to slot 15 The following shows receive conditions for slots that have been set for data frame reception Conditions The receive frame is a remote frame The receive ID and the slot ID are identical assuming the ID Mask Register bits set to 0 are Don t care bit The standard and extended frame types are the same 3 When receive conditions are met When receive conditions in 2 above are met the CAN module sets the CAN Message Slot Control Register s TRSTAT Transmit Receive Status and TRFIN Transmit Receive Finished bits to 1 while at the same time writing the received data to the message slot Furthermore a time stamp count value at the time the message was received is written to the CAN Message Slot Time Stamp COMSLnTSP along with the received data When the CAN module finished writing to the message slot it sets the CAN Slot Interrupt Status bit to 1 If the interrupt for the slot has been enabled an interrupt request is generated Note 1 The ID field and DLC value are written to the
547. ransmit data This register is a write only register so you cannot read out the content of this register Set data L SB aligned and write transmit data to bits D9 D15 for 7 bit data UART mode only D8 D15 for 8 bit data or D7 D15 for 9 bit data UART mode only Before you set data in this register enable the Transmit Control Register TEN transmit enable bit by setting it to 1 Writing data to this register while the TEN bit is disabled cleared to 0 has no effect When data is written to the Transmit Buffer Register while transmit is enabled the data is transferred from the SIO Transmit Buffer Register to the SIO Transmit Shift Register upon which the serial I O starts transmitting the data Note For 7 bit and 8 bit data the register can be accessed bytewise 12 18 Ver 0 10 1 2 SERIAL I O 12 2 Serial Related Registers 12 2 6 SIO Receive Buffer Registers E 5100 Receive Buffer Register SORXB Address H 0080 0114 SIO1 Receive Buffer Register S1RXB Address H 0080 0124 gt SIO2 Receive Buffer Register S2RXB Address H 0080 0134 gt DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 RDATA When reset Indeterminate gt D Bit Name Function R 0 6 No functions assigned 0 8 15 Stores receive data Receive data The SIOn Receive Buffer Register is used to store the receive data When the serial I O finishes receiving data the content of the SIO Receive Sh
548. ransmit slot the CAN module sets the corresponding CAN Message Slot Control Register s TRSTAT Transmit Receive Status bit to 1 thereby starting transmission e Ifthe CAN module lost bus arbitation or a CAN bus error occurs If the CAN module lost bus arbitation or a CAN bus error occurs while transmitting the CAN module clears the CAN Message Slot Control Register s TRSTAT Transmit Receive Status bit to 0 If the CAN module requested a transmit abort the transmit abort is accepted and writing to the message slot is enabled Completion of data frame transmission When data frame transmission is completed the CAN Message Slot Control Register s TRFIN Transmit Receive Finished bit and the CAN Slot Interrupt Status Register are set to 1 Also a time stamp count value at the time transmission was completed is written to the CAN Message Slot Time Stamp COMSLnTSP and the transmit operation is thereby completed If the CAN slot interrupt has been enabled an interrupt request is generated at completion of transmit operation The slot which has had transmission completed goes to an inactive state and remains inactive neither transmit nor receive until it is newly set in software 13 79 Ver 0 10 13 CAN MODULE 13 8 Receiving Remote Frames B 0000 0000 Write H 60 automatic response enable Wait for Clear receive request B 0110 1000 receive data Store received data Store Store B 0000 0000 B 0110 0000
549. re any number of External extension mode wait cycles entered from WAIT pin and processor mode Note 2 However wait cycles set by software have priority Note 1 During processor mode a ghost 1 Mbyte of the CSO area appears in an area of H 0010 0000 through H 001F FFFF Note 2 A ghost 1 Mbyte of the CS1 area appears an area of H 0030 0000 through H 003F FFFF 16 3 Ver 0 10 1 6 WAIT CONTROLLER 16 2 Wait Controller Related Registers 16 2 Wait Controller Related Registers The following shows a wait controller related register map A 0 Add 1 Address ddress DO ress D7 De 015 Wait Cycles Control Register H 0080 0180 WTCCR Blank addresses are reserved area Figure 16 2 1 Wait Controller Related Register Map 16 4 Ver 0 10 1 6 WAIT CONTROLLER 16 2 Wait Controller Related Registers 16 2 1 Wait Cycles Control Register E Wait Cycles Control Register WTCCR Address H 0080 0180 DO 1 2 3 4 5 6 D7 CSOWTC CS1WTC When reset 00 gt D Bit Name Function R 0 1 No functions assigned 0 2 3 CSOWTC 00 4 wait cycles when reset CSO wait cycles control 01 3 wait cycles 10 2 wait cycles 11 1 wait cycle 4 5 No functions assigned 0 6 7 CSIWTC 00 4 wait cycles when reset O O CS1 wait cycles control 01 3 wait cycles 10 2 wait cycles 11 1 wait cycle 16 5 Ver 0 10 1 6
550. re the minimum number of cycles required for memory access Therefore these values do not always reflect the number of cycles required for actual memory or bus access In write access for example although the CPU finishes the MEM stage by only writing to the write buffer this operation actually is followed by a write to memory Depending on the memory or bus state before or after the CPU requested a memory access the instruction processing may take more time than the calculated value R read cycle Cycles When existing in instruction menm 1 When reading internal resource ROM 1 When reading internal resource SFR byte 2 When reading internal resource SFR word eee 4 When reading external memory byte 5 Note When reading external memory 9 Note When successively fetching instructions from external memory 8 Note E W write cycle Cycles When writing to internal resource RAM sesese ee 1 When writing to internal resource SFR byte halfword 2 When writing to internal resource 4 When writing to external memory byte 4 Note When writing to external memory word Note This applies fo
551. receive finished Channel 5 12 4 Ver 0 10 12 SERIAL I O 12 1 Outline of Serial I O 5100 Va SIO0 Transmit Buffer Register y Transmit interrupt S gt To interrupt TXDO SIOO Transmit Shift Register Receive interrupt controller Transmit receive control circuit K Transmit DMA transfer request RXDO 5100 Receive Shift Register DMACS ves Receive DMA transfer request 4 gt To DMAC4 100 Receive Buffer Register UART CSIO d mode Mo Y When external clock selected Ub internal clock selected BCLK 1 16 O BCLK 8 BCLK 32 1 1 2 pee SCLKIO SCLKOO BCLK 256 Set value 1 z Baud rate Slo mode s BCLK Clock divider When internal clock selected generator BRG When UART mode selected SIO1 TXD1 SIO1 Transmit Shift Register 4 dransmitinterrupt gt To interrupt Transmit receive Receive interrupt controller control circuit Transmit transfer request gt To 6 RXD1 gt 5101 Receive Shift Register gt Receive DMA transfer request gt To DMAC4 D SCLKI1 SCLKO1 5 2 C
552. rection Register P16DIR P13 Direction Register P13DIR P15 Direction Register P15DIR P17 Direction Register P17DIR P18 Direction Register P18DIR P20 Direction Register P20DIR P19 Direction Register P19DIR P21 Direction Register P21DIR P22 Direction Register P22DIR Port Input Function Enable Register PIEN P6 Operation Mode Register PBMOD P7 Operation Mode Register P7MOD P8 Operation Mode Register P8MOD P9 Operation Mode Register POMOD P10 Operation Mode Register P10MOD P11 Operation Mode Register P11MOD P12 Operation Mode Register P12MOD P14 Operation Mode Register P14MOD P16 Operation Mode Register P16MOD P13 Operation Mode Register P13MOD P15 Operation Mode Register P15MOD P17 Operation Mode Register P17MOD P18 Operation Mode Register P18MOD P19 Operation Mode Register P19MOD P20 Operation Mode Register P20MOD P21 Operation Mode Register P21MOD P22 Operation Mode Register P22MOD Bus Mode Control Register BUSMODC Flash Mode Register FMOD Flash Status Register 1 FSTAT1 Flash Control Register 1 FCNT1 Flash Control Register 2 FCNT2 Flash Control Register 3 FCNT3 Flash Control Register 4 FCNT4 Pseudo flash L Bank Register 0 FELBANKO Pseudo flash S Bank Register 0 FESBANKO Pseudo flash S Bank Register 1 FESBANK1 TML1 Counter High TML1CTH TML1 C
553. ree operations which are performed based on state transitions of the TAP controller The TAP controller changes state according to JTMS input and generates control signals required for operation in each state Capture operation The result of boundary scan test or the fixed data defined for each register is sampled As register operation the input data is loaded into the shift register stage Shift operation The register is accessed from outside through the boundary scan path The sampled value is output to an external device at the same time data is set from outside As register operation bits are shifted right between each shift register stage Update operation The data set from outside during shift is driven As register operation the value set in the shift register stage is transferred to the parallel output stage The JTAG interface undergoes transitions of internal state depending on JTMS input as it performs the following two operations In either case the operation basically is performed in order of Capture Shift Update path sequence Instruction code is set in the instruction register to select the data register to be operated on in the subsequent DR path sequence DR path sequence The selected data register is operated on to inspect or set data 19 6 Ver 0 10 1 9 19 4 Basic Operation of JTAG The state transitions of the TAP controller and the basic configuration of the 32171 s JTA
554. ress A0 A15 MJT Input Interrupt 1 Handler Start Address A16 A31 MJT Output Interrupt 7 Handler Start Address A0 A15 MJT Output Interrupt 7 Handler Start Address A16 A31 MJT Output Interrupt 6 Handler Start Address A0 A15 MJT Output Interrupt 6 Handler Start Address A16 A31 T Output Interrupt 5 Handler Start Address A0 A15 M MJT Output Interrupt 5 Handler Start Address A16 A31 M T Output Interrupt 4 Handler Start Address A0 A15 T Output Interrupt 4 Handler Start Address A16 A31 M MJT Output Interrupt 2 Handler Start Address A0 A15 M T Output Interrupt 2 Handler Start Address A16 A31 T Output Interrupt 1 Handler Start Address A0 A15 M MJT Output Interrupt 1 Handler Start Address A16 A31 MJT Output Interrupt O Handler Start Address A0 A15 MJT Output Interrupt O Handler Start Address A16 A31 Blank addresses are reserved areas Figure 3 6 1 ICU Vector Table of the 32171 1 2 MJ MJT Output Interrupt 3 Handler Start Address A0 A15 JT Output Interrupt 3 Handler Start Address A16 A31 3 23 Ver 0 10 3 ADDRESS SPACE 3 6 ICU Vector Table 0 Address 1 Address DO D15 0000 00 6 H 0000 00E8 DMAS5 9 Interrupt Handler Start Address A0 A15 H 0000 00 4 poe e T 0000 010 H 0000 010C CANO Transmit Receive amp Error Interrupt Handler Start Address A0 A15 H 0000 010E CANO Transmit Receive amp Error Interrupt Handler Start Address A16 A31
555. rflow Note This diagram does not show detail timing information Figure 10 3 16 Typical Operation in TOP Delayed Single shot Output 10 74 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer 2 Correction function of TOP delayed single shot output mode If you want to change the counter value during operation write a value to the TOP correction register the value by which you want to be increased or reduced from the initial count set in the counter To add write the value you want to add to the correction register directly as is to subtract write the two s complement of the value you want to subtract to the correction register Correction of the counter is performed synchronously with a clock period next to the one in which the correction value was written to the TOP correction register In this case one down count in the clock period during which the correction was performed is canceled Therefore note that the counter value actually is corrected by correction register value 1 For example if the initial counter value is 7 and you write a value 3 to the correction register when the counter has counted down to 3 then the counter underflows after a total of 12 counts after reload Count value after reload 7 1 3 1 12 5 1 2 3 4 5 6 7 8 9 10 11 2 ji 4 4 f 5 f f t f f Enable H
556. rise one bit The equation to calculate the baud rate is shown below 1 Tq period x number of Tq s for 1 bit Baud rate bps Number of Tq s for 1 bit Synchronization Segment Propagation Segment Phase Segment 1 Phase Segment 2 13 56 Ver 0 10 13 CAN MODULE 13 4 Initializing the CAN Module 1 Bit Time Synchronization Segment Propagation Segment Phase Segment Phase Segment2 1Tq 3 2 1 Sampling Point Shown in this diagram is the bit timing for cases where one bit consists of 8 Tq s When one time sampling is selected the value sampled at Sampling Point 1 is assumed to be the value of the bit When three time sampling is selected the value of the bit is determined by majority from CAN bus values sampled at Sampling Points 1 2 and 3 Figure 13 4 1 Example of Bit Timing 2 Setting the number of times sampled Select the number of times the CAN bus is sampled from one time and three times When you select one time sampling the value sampled at the end of Phase Segment1 is assumed to be the value of the bit When you select three time sampling the value of the bit is determined by majority from values sampled at three points i e the value sampled at the first point and those sampled one Tq before and two Tq s before that b Setting ID Mask Registers Set the values of ID Mask Registers Global Mask Register Local Mask Register A and Local Mask Register B whic
557. rite WR during external write access it indicates the valid data on the data bus to transfer During external read cycle and when accessing the internal function it outputs a high 8 Wait WAIT When the 32171 started an external bus cycle it automatically inserts wait cycles while the WAIT signal is asserted For details refer to Chapter 16 Wait Controller When not using the WAIT function this pin can be used as P71 by setting the P7 Operation Mode Register P71MOD bit to 0 Note that the 32171 always inserts one or more wait cycles for external access Therefore the shortest time in which an external device can be accessed is one wait cycle 2 BCLK periods 9 Hold control HREQ HACK The hold state refers to a state in which the 32171 has stopped bus access and bus interface related pins are tristated high impedance While the 32171 is in a hold state any bus master external to the chip can use the system bus to transfer data The 32171 is placed in a hold state by pulling the HREQ pin input low While the 32171 remains in a hold state after accepting the hold request and during a transition to the hold state the HACK pin outputs a low level signal To exit from the hold state and return to normal operating state release the HREQ signal back high When not using the HREQ and HACK functions these pins can be used as P72 and P7 by setting the P73 Operation Mode Register P72MOD and P73MOD bits to 0 The status of each 32171 pin
558. ritten to this register 13 48 For receive slots if when storing a data frame the data length DLC value 4 an Ver 0 10 13 CANO Message Slot 0 Data 5 COMSLODT5 E CANO Message Slot 1 Data 5 COMSL1DT5 CANO Message Slot 2 Data 5 COMSL2DT5 E CANO Message Slot 3 Data 5 COMSL3DT5 E CANO Message Slot 4 Data 5 COMSL4DT5 E CANO Message Slot 5 Data 5 COMSL5DT5 E CANO Message Slot 6 Data 5 COMSL6DT5 CANO Message Slot 7 Data 5 COMSL7DT5 CANO Message Slot 8 Data 5 COMSL8DT5 E CANO Message Slot 9 Data 5 COMSL9DT5 E CANO Message Slot 10 Data 5 COMSL10DT5 E CANO Message Slot 11 Data 5 COMSL11DT5 E CANO Message Slot 12 Data 5 COMSL12DT5 E CANO Message Slot 13 Data 5 COMSL13DT5 E CANO Message Slot 14 Data 5 COMSL14DT5 E CANO Message Slot 15 Data 5 COMSL15DT5 D8 9 10 11 12 CAN MODULE 13 2 CAN Module Related Registers Address H 0080 110 gt Address H 0080 111B Address H 0080 112B Address H 0080 113B Address H 0080 114 gt Address H 0080 115 gt Address H 0080 116 gt Address H 0080 117B Address H 0080 118B Address H 0080 119 gt Address H 0080 11AB Address H 0080 11 gt Address H 0080 11CB gt Address H 0080 11DB gt Address H 0080 11 gt Address H 0080 11FB 13 14 D15 COMSLnDT5 D Bit Name 8 15 COMSLnDT5 When reset Indeterminate gt Function R Ww Message slot n data 5 O O These registers are
559. rnal DMAC when the transmit buffer is empty set the DMAC Refer to Chapter 9 DMAC 7 Selecting pin functions Because the serial I O related pins serve dual purposes shared with input output ports set pin functions Refer to Chapter 8 Input Output Ports and Pin Functions 12 45 Ver 0 10 12 SERIAL I O 12 6 Transmit Operation in UART Mode Initial settings for UART transmission Set register to UART mode x Set parity when enabled Set SIO Transmit Receive Mode Register select odd even Set stop bit length Set character length v Set SIO Transmit Control Register Select clock divider s divide by ratio Serial related Set SIO Baud Rate Register Divide by ratio H 00 to H FF Note registers v Set SIO Interrupt Related Registers v Set the Interrupt Controller Enable disable transmit interrupt When using interrupt v Set DMAC related registers When using DMAC v Set input output port Operation Mode Register Vv Initial settings for UART transmission finished Note When you selected f BCLK for the BRG count source CDVI you are subject to limitations that the baud rate register value you set must be equal to or greater than 7 Figure 12 6 3 Procedure for UART Transmit Initialization 12 46 Ver 0 10 1 2 SERIAL I O 12 6 Transmit Operation in UART Mode
560. rnal clock select bit 1 External clock Note 2 12 STB Stop bit length select bit 0 One stop bit O O UART mode only 1 Two stop bits Note 3 13 PSEL Parity odd even select bit 0 Odd parity UART mode only 1 Even parity Note 3 14 PEN Parity enable bit 0 Disables parity UART mode only 1 Enables parity Note 3 15 SEN Sleep select bit 0 Disables sleep function UART mode only 1 Enables sleep function Note 3 Note 1 For SIO2 the D8 bit is fixed to 0 in hardware You cannot set the D8 bit to 1 to choose clock synchronous serial I O Note 2 Has no effect when UART mode is selected Note 3 D12 to D15 have no effect during clock synchronous mode 12 15 Ver 0 10 1 2 SERIAL I O 12 2 Serial Related Registers The SIO Mode Register consists of bits to set the serial I O operation mode data format and the functions used during communication The SIO Transmit Receive Mode Register must always be set before serial I O starts operating If you want to change settings of this register after the serial I O started transmitting or receiving data be sure to confirm that transmit and receive operations have been completed and disable transmit receive operations by clearing the SIO Transmit Control Register transmit enable bit and SIO Receive Control Register receive enable bit to 0 before you change 1 SMOD serial I O mode select bits 08 to 010 These bits select the operati
561. rnal to the chip and an RC network connected to the PLL circuit control pin VONT For constants Rf CIN COUT and Rd consult your resonator manufacturer to determine the appropriate values When you use an externally sourced clock signal without using the internal oscillator circuit connect the external clock signal to the XIN pin and leave the XOUT pin open M32R E Oscillator module B CPU clock PLL circuit 1 2 gt To internal circuit ji clock OSCVSS OSCVCC XIN Rf XOUT VONT BCLK P70 Rd M UT 4 Cour 0 1uF OSCVCC 3 3 V power supply Figure 18 1 1 Example of a System Clock Generating Circuit 18 2 Ver 0 10 1 8 OSCILLATION CIRCUIT 18 1 Oscillator Circuit 18 1 2 System Clock Output Function A clock whose frequency is twice the input frequency can be output from the BCLK pin The BCLK pin is shared with port P70 When you use this pin to output the system clock set the P7 Operation Mode Register P7MOD s D8 bit to 1 Configuration of the P7 Operation Mode Register is shown below E P7 Operation Mode Register P7MOD Address H 0080 0747 D8 9 10 11 12 13 14 D15 P70MOD P71MOD P72MOD P73MOD P74MOD P75MOD P76MOD
562. rrupt 3 Leye Requested MJT Output Interrupt 2 Levels Requested priority MJT Output Interrupt 1 scii Requested sae DMAO 4 Interrupt Leeli Not requested A DO Converter Interrupt pail Requested gt Figure 5 5 1 Example of Priority Resolution When Accepting Interrupt 5 16 Ver 0 10 INTERRUPT CONTROLLER ICU 5 5 Description of Interrupt Operation Table 5 5 1 Hardware fixed Priority Levels ICU Vector Table Address Type of Input Source Priority High Low CANO Transmit Receive amp Error Interrupt Interrupt Source MJT Input Interrupt 4 IRQ12 MJT Input Interrupt 3 IRQ11 MJT Input Interrupt 2 IRQ10 Input Interrupt 1 IRQ9 MJT Output Interrupt 7 IRQ7 MJT Output Interrupt 6 IRQ6 MJT Output Interrupt 5 IRQ5 MJT Output Interrupt 4 IRQ4 MJT Output Interrupt 3 IRQ3 MJT Output Interrupt 2 IRQ2 MJT Output Interrupt 1 IRQ1 MJT Output Interrupt 0 IRQO DMAO 4 Interrupt SIO1 Receive Interrupt SIO1 Transmit Interrupt SIOO Receive Interrupt SIOO Transmit Interrupt A DO Converter Interrupt DMAS5 9 Interrupt 5102 3 Transmit Receive Interrupt RTD Interrupt H 0000 0094 H 0000 0097 H 0000 0098 H 0000 009B H 0000 009C H 0000 009F H 0000 00A0 H 0000 00 H 0000 00A8 H 0000 00AB H 0000 00AC H 0000 00AF H 0000 00B0 H 0000 00B3 H 0000 00B4 H 0000 00B7 H 0000 00B8 H 0000 00BB H 0000 00BC H 0000 00 H 00
563. rrupt Request Command 14 10 Ver 0 10 14 REAL TIME DEBUGGER RTD 14 3 Functional Description of the RTD 14 3 6 Operation of RCV Recover from Runaway When the RTD runs out of control the RCV recover from runway command can be issued to forcibly recover from the runaway condition without having to reset the system The RCV command must always be issued twice in succession Also any command issued subsequently after the RCV command must have its bits 20 31 all set to 1 LSB side MSB side 31 20 19 18 17 16 15 0 RTDRXD lt 1 1 1 1 1 1 1 1 Note Command RCV Note All of 32 data bits are 1 s The RCV command must always be issued twice in succession Figure 14 3 10 RCV Command Data Format 32 clock 32 clock 32 clock 32 clock lt periods gt lt periods gt lt periods gt lt periods gt lt 4 L L RA Bits 20 31 RTDRXD RCV RCV Y 14 1 RDR A1 X eee Next command following the RCV command RTDTXD Indeterminate data during runway condition W D A1 RTDACK A lt gt lt gt Indeterminate value 2 clock 2 clock during runway condition RCV command stored here periods periods Note The next command following the RCV command must have its bits 20 31 al
564. s esee M LII Enable bit E ITM s Ug ieee H F000 Down count starting H A i Down count starting from reload 0 register 000 from counter set value Counter set value BI00005 56 75 D Sete e Reload 0 register H F000 Reload 1 register Not used F F output Data inverted Data inverted by underflow by underflow CC TIO interrupt by underflow Note This diagram does not show detail timing information Figure 10 4 15 Typical Operation in TIO Deleted Single shot Output Mode without Correction Function 10 119 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer 10 4 14 Operation in TIO Continuous Output Mode Without Correction Function 1 Outline of TIO continuous output mode In continuous output mode the timer counts down clock pulses starting from the set value of the counter and when the counter underflows reloads it with reload 0 register value Thereafter this operation is repeated each time the counter underflows thus generating consecutive pulses whose waveform is inverted in width of reload 0 register set value 1 When after setting the counter and reload 0 register the timer is enabled by writing to
565. s for each internal peripheral I O written in it beforehand so that control will branch to the address read from this table to execute processing by each handler When returning from the handler clear the PSW register IE bit to 0 to disable interrupts and then restore the IMASK value from the stack 3 Identifying the source of interrupt generated If any internal peripheral I O has multiple interrupt sources check the Interrupt Status Register for each internal peripheral I O to identify the source of interrupt generated 4 Enabling multiple interrupts To enable another interrupt in an interrupt handler set the PSW register s IE Interrupt Enable bit to 1 to enable interrupts so that they will be accepted However before writing a 1 to the IE bit always be sure to save each register BPC PSW general purpose register and IMASK to the stack 5 19 Ver 0 10 INTERRUPT CONTROLLER ICU 5 5 Description of Interrupt Operation EI External Interrupt vector entry Ay H 0000 0080 BRA instruction P Elsa A handler A Y Save BPC to stack AA Note 1 Save PSW to stack Y Program Save general purpose being executed register to stack d Read Interrupt Mask 2 Register IMA
566. s generates a RAM backup signal A and D in Figure 17 3 3 To enable RAM backup mode make the following settings 1 Create check data to verify after returning from RAM backup to normal mode whether the RAM data has been retained normally in Figure 17 3 3 2 To materialize low power operation set all programmable input output pins except port X for input mode or for output mode with pins outputting a low in Figure 17 3 3 3 Set port X for input mode B and in Figure 17 3 3 This causes the transistor s base voltage IB to go low so that no current flows from the power supply to the VCC pin via the transistor C in Figure 17 3 3 Consequently the power to the pin is shut off D in Figure 17 3 3 Due to settings in 1 to 3 the voltage applied to the VDD pin becomes 3 3 V 10 and voltages applied to all other pins drop to 0 V thus placing the M32R E in RAM backup mode in Figure 17 2 3 DC IN Input Regulator Outpu Power supply for RAM 3 3V system Regulator Outpu X 5V system Regulator Outpu External circuit 3 3V system RAM backup signal Note 1 B l Port X VCCI OSC VCC VCCE VREFn AVCCn VDD Note 2 SBI aie M32R E Example of RAM backup processing Generate RAM backup signal Note 4 Note 1 This signal outputs a low for RAM backup Create check data Note 2 This pin outputs a high when the
567. s interface is shared with the CPU the same applies to both bus protocol and bus timing as in peripheral module access from the CPU 3 Transfer rate The maximum transfer rate is calculated using the equation below 1 Maximum transfer rate bytes second 2 bytes x 1 f BCLK x 3 cycles 9 33 Ver 0 10 9 DMAC 9 3 Functional Description of the DMAC 4 Address count direction and address changes The direction in which the source and destination addresses are counted as transfer proceeds Address fixed or Address incremental is set for each channel using the SADSL source address direction select and DADSL destination address select bits When the transfer size is 16 bits the address is incremented by two for each DMA transfer performed when the transfer size is 8 bits the address is incremented by one Table 9 3 11 Address Count Direction and Address Changes Address Count Direction Transfer Unit Address Change for One DMA Address fixed 8 bits 0 16 bits 0 Address incremental 8 bits 16 bits 2 5 Transfer count value The transfer count value is decremented by one at a time irrespective of the size of transfer unit 8 or 16 bits 9 34 Ver 0 10 DMAC 9 3 Functional Description of the DMAC 6 Transfer byte positions When the transfer unit 8 bits the LSB of the address register is effective for both source and destination Therefore in addition to data transfers between even a
568. s precautions to be observed when using TMS measure input If measure event input and write to the counter occur simultaneously in the same clock period the write value is set in the counter while at the same time latched to the measure register 10 130 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 6 TML Input related 32 bit Timer 10 6 TML Input related 32 bit Timer 10 6 1 Outline of TML TML Timer Measure Large is an input related 32 bit timer capable of measuring input pulses in two circuit blocks comprising a total of eight channels The table below shows specifications of TML The diagram in the next page shows a block diagram of TML Table 10 6 1 Specifications of TML Input related 32 bit Timer Item Specification Number of channels 8 channels 2 circuit blocks consisting of 4 channels each 8 channels in total Input clock Divided by 2 frequency of the internal peripheral operating clock e g 10 0 MHz when using 20 MHz internal peripheral operating clock or clock bus 1 input Counter 32 bit up counter x 2 Measure register 32 bit measure register x 8 Timer startup Starts counting after leaving reset 10 131 Ver 0 10 1 0 MULTIJUNCTION 5 10 6 TML Input related 32 bit Timer
569. s selected from 1 8 32 or 256 by using the CDIV baud rate generator count source select bits Transmit Control Register D2 D3 bits The baud rate generator divides the clock divider output by baud rate register set value 1 and then by 2 which results in generating a transmit receive shift clock When the internal clock is selected in CSIO mode the baud rate is calculated using the equation below 1 BCLK Baud rate bps Clock divider s divide by value x baud rate register set value 1 x 2 Baud rate register set value H 00 to H FF Note Clock divider s divide by value 1 8 32 or 256 Note If the divide by value selected for the baud rate generator count source is 1 i e itself make sure the baud rate register value you set does not exceed 2 Mbps 2 When external clock is selected in CSIO mode In this case the baud rate generator is not used instead the input clock from the SCLKI pin serves directly as CSIO transmit receive shift clock The maximum frequency of the SCLKI pin input clock is 1 16 of f BCLK Baud rate SCLKI pin input clock bps 12 25 Ver 0 10 SERIAL I O 12 3 Transmit Operation in CSIO Mode 1 2 SERIAL I O 12 3 Transmit Operation in CSIO Mode 12 3 2 Initial Settings for CSIO Transmission To transmit data CSIO mode initialize the serial I O following the procedure described below 1 Setting SIO Transmit Receive Mode Register Set the register to CSIO m
570. s when the timer is actuated by writing to the enable bit in software When event input is entered to TMS while the timer is operating the counter value is latched into measure registers 0 3 The timer stops at the same time count is disabled by writing to the enable bit A TIN interrupt can be generated by entering a measure signal from an external device for TMS1 only no TIN interrupts available for TMSO Also when the counter overflows a TMS interrupt can be generated Enabled Measure Measure Measure Measure by writing to eventO event1 Overflow event0O event 1 enable bit occurs occurs occurs occurs occurs Count clock 00 AN SLA Enable bit A H D000 H C000 Counter Een H 6000 Indeterminate H 6000 value 4 MS Re Measure 0 register Indeterminate K H 8000 X H 6000 CC C TIN15 interrupt Measure 1 register Indeterminate 000 Ba Pa TIN14 interrupt TMS interrupt by overflow Note This diagram does not show detail timing information Figure 10 5 3 Typical Operation in TMS Measure Input 10 129 Ver 0 10 1 0 TIMERS 10 5 TMS Input related 16 bit Timer 2 Precautions to be observed when using TMS measure input The following describe
571. sabling rewrite 10 63 Ver 0 10 10 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer B TOPO 10 Count Enable Register TOPCEN lt Address H 0080 02FE gt DO 1 2 3 4 5 6 7 8 9 10 11 10 TOP9 TOP8 TOP6 5 TOP4 CEN CEN CEN CEN CEN CEN CEN 12 13 14 015 2 1 When reset H 0000 gt D Bit Name Function R 0 4 No functions assigned 0 5 10 TOP10 count enable 0 Stops count Q Q 6 TOP9CEN TOP9 count enable 7 TOP8CEN TOP8 count enable 8 TOP7CEN TOP7 count enable 9 TOP6CEN TOP6 count enable 10 TOP5CEN TOP5 count enable 11 TOP4CEN count enable 12 TOP3CEN TOP3 count enable 13 TOP2CEN count enable 14 TOP1CEN TOP1 count enable 15 TOPOCEN TOPO count enable 1 Enables count Note This register must always be accessed in halfwords TOPO0 10 Count Enable Register controls the operation of TOP counter To enable the counter in software enable the relevant TOPO 10 Enable Protect Register for write and set the count enable bit by writing a 1 To stop the counter enable the TOPO 10 Enable Protect Register for write and reset the count enable bit by writing a 0 In all but continuous mode when the counter stops due to an occurrence of underflow the count enable bit is automatically reset to 0 Th
572. sage Slot 12 Standard IDO COMSL12SIDO CANO Message Slot 12 Standard ID1 COMSL12SID1 H 0080 11C2 CANO Message Slot 12 Extended IDO COMSL12EIDO CANO Message Slot 12 Extended ID1 COMSL12EID1 H 0080 11C4 H 0080 11C6 CANO Message Slot 12 Extended ID2 COMSL12EID2 CANO Message Slot 12 Data 0 COMSL12DTO CANO Message Slot 12 Data Length Register COMSL12DLC CANO Message Slot 12 Data 1 COMSL12DT1 H 0080 11C8 CANO Message Slot 12 Data 2 COMSL12DT2 CANO Message Slot 12 Data 3 COMSL12DT3 H 0080 11CA H 0080 11CC CANO Message Slot 12 Data 4 COMSL12DT4 CANO Message Slot 12 Data 6 COMSL12DT6 CANO Message Slot 12 Data 5 COMSL12DT5 CANO Message Slot 12 Data 7 COMSL12DT7 H 0080 11CE CANO Message Slot 12 Ti me Stamp COMSL12TSP H 0080 1100 CANO Message Slot 13 Standard IDO COMSL13SIDO CANO Message Slot 13 Standard ID1 COMSL13SID1 H 0080 11D2 CANO Message Slot 13 Extended IDO COMSL13EIDO CANO Message Slot 13 Extended ID1 COMSL13EID1 H 0080 11D4 CANO Message Slot 13 Extended ID2 COMSL13EID2 CANO Message Slot 13 Data Length Register COMSL13DLC H 0080 11D6 CANO Message Slot 13 Data 0 COMSL13DTO CANO Message Slot 13 Data 1 COMSL13DT1 H 0080 11D8 CANO Message Slot 13 Data 2 COMSL13DT2 CANO Message Slot 13 Data 3 COMSL13DT3 H 0080 11DA CANO Message Slot 13 Data 4 COMSL13DT4 CANO Message Slot 13 Data 5 COMSL13DT
573. sed in halfwords 10 23 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer E F F Source Select Register 1 FFS1 Address H 0080 0223 When reset 00 gt D Bit Name Function R 8 9 FF19 F F19 source selection OX TIO8 output O 10 Output event bus 0 11 Output event bus 1 10 11 18 F F18 source selection 0X TIO7 output O O 10 Output event bus 0 11 Output event bus 1 12 13 FF17 F F17 source selection OX TIO6 output O 10 Output event bus 0 11 Output event bus 1 14 15 FF16 F F16 source selection 00 TIO5 output O O 01 Output event bus 0 10 Output event bus 1 11 Output event bus 3 The registers FFSO and FFS1 are used to select the signal sources fed to each output F F flip flop For these signal sources you can choose signals from the internal output bus or underflow output from each timer 10 24 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer B F F Protect Register 0 FFPO Address H 0080 0224 DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 When reset 0000 gt D Bit Name Function R 0 FP15 F F15 protect 0 Enables write to F F output bit 1 FP14 F F14 protect 1 Disables write to F F output bit 2 FP13 F F13 protect 3 FP12 F F12 protect 4 FP11 F F11 protect 5 FP10 F F10 protect 6 FP9 F F9 protect 7 FP8 F F8 protect
574. sequentially from slot O up to slot 15 The following shows receive conditions for slots that have been set for data frame reception Conditions The receive frame is a data frame The receive ID and the slot ID are identical assuming the ID Mask Register bits set to 0 are Don t care bits The standard and extended frame types are the same Note In BasicCAN mode slots 14 and 15 while being set for data frame reception can also receive remote frames 2 When receive conditions are met When receive conditions in 1 above are met the CAN module sets the CAN Message Slot Control Register s TRSTAT Transmit Receive Status and TRFIN Transmit Receive Finished bits to 1 while at the same time writing the received data to the message slot If the TRFIN Transmit Receive Finished bit is already 1 the CAN module also sets the ML Message Lost bit to 1 indicating that the message slot has been overwritten The message slot has its ID field and DLC field both overwritten and an indeterminate value written in its unused area e g extended ID field for standard frame reception and an unused data field Furthermore a time stamp count value at the time the message was received is written to the CAN Message Slot Time Stamp COMSLnTSP along with the received data When the CAN module finished writing to the message slot it sets the CAN Slot Interrupt Status bit to 1 If the interrupt for the slot has been enabled an interrupt reques
575. serve only X amp 189 1 P35 output3 X 188 0 2 amp 188 BC 1 control 0 amp 187 4 P36 observe only X amp 186 1 P36 output3 X 185 0 2 amp 185 1 control 0 amp 184 4 P37 observe only X amp 183 1 P37 outputs X 182 0 2 amp 182 1 control 0 amp 181 4 P20 observe only X amp 180 1 P20 output3 X 179 0 2 amp 179 1 control 0 amp 178 4 21 observe only X amp 177 1 21 outputs X 176 0 2 amp 176 1 control 0 amp 175 4 P22 observe only X amp 174 1 P22 outputs X 173 0 2 amp 173 1 control 0 amp 172 4 P23 observe only X amp 171 BC_1 P23 outputs X 170 0 2 amp 170 1 control 0 amp 169 4 P24 observe only X amp 168 1 P24 outputs X 167 0 2 amp Figure 19 5 10 BSDL Description for the 32171 10 14 19 24 Ver 0 10 19 JTAG 19 5 Boundary Scan Description Language UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UJ UB P25 P25 P26 P26 P27 P27 POO POO 2 2 POS P04 P04 P05
576. sideration about the Oscillator The oscillator that generates the fundamental clock for microcomputer operation requires consideration to make it less susceptible to influences from other signals 1 Avoidance from large current signal lines Signal lines in which a large current flows exceeding the range of current values that the microcomputer can handle must be routed as far away from the microcomputer especially the oscillator as possible lt Reasons gt Systems using the microcomputer contain signal lines to control for example a motor LED and thermal head When a large current flows in these signal lines it generates noise due to mutual inductance Mutual inductance ff 00 Large current Microcomputer Figure 3 1 6 Wiring of Large current Signal Lines Appendix 3 6 Ver 0 10 Appendix 3 2 Avoiding effects of rapidly level changing signal lines INSTRUCTION PROCESSING TIME Appendix 3 1 Precautions about Noise Locate signal lines whose levels change rapidly as far away from the oscillator as possible Also make sure rapidly level changing signal lines will not intersect clock related signal lines and other noise sensitive signal lines Reasons Rapidly level changing signal lines tend to affect other signal lines as their voltage level frequently rises and falls Especially if they intersect clock related signal lines they will cause the clock waveform to become distorted whi
577. signals that can be fed to the clock bus Table 10 2 1 Signals That Can Be Fed to Each Clock Bus Line Clock Bus Acceptable Signal 3 TCLKO input 2 Internal prescaler PSC2 or TCLK3 input 1 Internal prescaler PSC1 0 Internal prescaler PSCO 2 Input event bus The input event bus is provided for supplying a count enable signal or measure capture signal to each timer and is comprised of four lines of input event bus 0 3 Each timer can use this input event bus signal as enable or capture signal input The table below lists the signals that can be fed to the input event bus Table 10 2 2 Signals That Can Be Fed to Each Input Event Bus Line Input Event Bus Acceptable Signal 3 TIN3 input output event bus 2 or TIO7 underflow signal 2 TINO input 1 TIO6 underflow signal 0 TIO5 underflow signal 10 10 Ver 0 10 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer 10 3 Output event bus The output event bus has the underflow signal from each timer connected to it and is comprised of four lines of output event bus 0 3 Output event bus signals are connected to output flip flops and can also be connected to other peripheral circuits output event bus 3 to A DO converter output event bus 0 to DMA channel 1 and output event bus 1 to DMA channel 2 Furthermore output event bus 2 can be connected to input event bus 3 The table below lists the signals that can be connected to the output event bus
578. sion ADOINO ADOIN1 ADOIN2 Completed here when starts operating in single shot Note scan mode 10 bit A DO data register ADODTO ADODT1 ADODT2 ADODT3 zT A D conversion interrupt request or DMA transfer request Note 00 conversion start Software trigger Started by setting A DO conversion start bit to 1 Hardware trigger Started by output event bus 3 Figure 11 1 4 Operation of A D Conversion in Scan Mode for 4 channel Scan 11 7 Ver 0 10 11 5 11 1 Outline of Converters 8 channel scan During continuous scan mode Conversion DOINO starts Note ADOIN1 158 10 bit A Di data register ADODTO ADODT1 ADODT2 ADODT3 DOIN4 DOIN5 292 ADODT4 ADODT5 ADODT6 ADODT7 lt 16 channel scan gt During continuous scan mode Conversion DOINO ADOIN1 ADOIN2 DOIN3 starts Note 10 bit A Di data register ADODTO ADODT1 ADODT2 ADODT3 DOIN4 DOIN5 DOING ADOIN7 ADODT4 ADODT5 ADODT6 ADODT7 2 ADODT8 ADODT9 ADODT1d ADODT11 Completed here when operating in single shot scan mode CBO ADODT12 ADODT13 ADODT14 ADODT15 mM A D conversion interrupt request or DMA transfer request Not
579. sk Register A and Local Mask Register B The Global Mask Register is used for message slots 0 13 while Local Mask Registers A and B are used for message slots 14 and 15 respectively When a bit in this register is set to 0 its corresponding ID bit is masked assumed to have matched during acceptance filtering When a bit in this register is set to 1 its corresponding ID bit is compared with the receive ID during acceptance filtering and when it matches the ID set for the message slot the received data is stored in it Note 1 EIDOM corresponds to the MSB of extended ID Note 2 The Global Mask Register can only be changed when none of slots 0 13 have receive requests set Note 3 The Local Mask Register A can only be changed when slot 14 does not have a receive request set Note 4 The Local Mask Register B can only be changed when slot 15 does not have a receive request set 13 33 Ver 0 10 CAN MODULE 13 2 CAN Module Related Registers 13 13 2 10 CAN Message Slot Control Registers E CANO Message Slot0 Control Registers COMSLOCNT E CANO Message Slot1 Control Registers COMSL1CNT E CANO Message Slot2 Control Registers COMSL2CNT E CANO Message Slot3 Control Registers COMSL3CNT CANO Message Slot4 Control Registers COMSL4CNT E CANO Message Slot5 Control Registers COMSL5CNT E CANO Message Slot6 Control Registers COMSL6CNT CANO Message Slot7 Control Registers COMSL7CNT E CANO Message Slot8 Control Regist
580. sources are associated with errors this register lets you know which source generated the interrupt 1 EIS CAN Bus Error Interrupt Status bit D5 This bit is set to 1 when a communication error is detected This bit is cleared by writing a 0 in software 2 PIS Error Passive Interrupt Status bit D6 This bit is set to 1 when the CAN module goes to an error passive state This bit is cleared by writing a 0 in software 3 OIS Bus Off Interrupt Status bit D7 This bit is set to 1 when the CAN module goes to a bus off state This bit is cleared by writing a 0 in software When writing to the CAN error interrupt status make sure the bits you want to clear are set to 0 and all other bits are set to 1 The bits thus set to 1 are unaffected by writing in software and retain the value they had before you write 13 25 Ver 0 10 13 CANO Error Interrupt Mask Register CANOERIMK CAN MODULE 13 2 CAN Module Related Registers Address H 0080 1015 2 D8 9 10 11 12 13 14 D15 EIM PIM OIM When reset H00 gt D Bit Name Function R 8 12 No functions assigned 0 13 0 Masks disables interrupt request CAN bus error interrupt mask 1 Enables interrupt request 14 PIM Error passive interrupt mask 15 OIM Bus off interrupt mask 1 EIM CAN Bus Error Interrupt Mask bit D5 This bit controls interrupt requests generated for occurrence of CAN bus errors by enabling or
581. src label LDUH Rdest Rsrc Unsigned 8 bits LD24 Rsrc label LDUB Rdest Rsrc Figure 2 6 8 Memory unsigned to register transfer 2 12 Ver 0 10 2 2 6 Data Formats 7 Things to be noted for data transfer Note that in data transfer data arrangements in registers and those in memory are different Data in register Data in memory 1 2 Word data 32 bits Half word data 16 bits Byte data 8 bits MSB LSB Figure 2 6 9 Difference in Data Arrangements 2 13 Ver 0 10 This is a blank page 2 14 Ver 0 10 CHAPTER S ADDRESS SPACE 3 1 Outline of Address Space 3 2 Operation Modes 3 3 Internal ROM Area and Extended External Area 3 4 Internal RAM Area and SFR Area 3 5 EIT Vector Entry 3 6 ICU Vector Table 3 7 Note about Address Space 3 ADDRESS SPACE 3 1 Outline of Address Space 3 1 Outline of Address Space The M32R s logical addresses are always handled in 32 bits providing 4 Gbytes of linear ad dress space The M32R E s address space consists of the following 1 User space Internal ROM area Extended external area Internal RAM area Special Function Register SFR area 2 Boot program space 3 System space areas not open to the user 1 User space A 2 Gbytes of address space from H 0000 0000 to H 7FFF FFFF is the user space Located in this space are the internal ROM area extended extern
582. ss in the first frame and then the write data in the second frame The timing at which the RTD writes to the internal RAM occurs in the third frame after receiving the write data a First frame LSB side MSB side 31 esie 20 19 18 17 16 15 434 13402 m 1 0 RTDRXD X 8625662 0101111 29 28 6 17 16 Command WRR Specified address b Second frame LSB side MSB side 31 30 CO 1 0 RTDRXD 031 030 D1 Write data Note Note 1 X Don t Care However if issued immediately after the RCV command bits 20 31 must all be set to 1 Note 2 The specified address and write data are transferred LSB first Figure 14 3 4 WRR Command Data Format 14 7 Ver 0 10 1 4 REAL TIME DEBUGGER RTD 14 3 Functional Description of the RTD The RTD reads out data from the specified address before writing to the internal RAM and again reads out from the same address immediately after writing to the internal RAM this helps to verify the data written to the internal RAM The read data is output at the timing shown below 32 clock 32 clock 32 clock 32 clock lt AS a Brod zS RTDCLK y ty 72 12 L v RTDRXD X WRR A1 X 1 4
583. status Interrupt status flag b4 5 6 b7 Initial state 9 request b6 event occurred 0 0 1 0 q b4 event occurred 1 0 1 0 Write to the interrupt status b4 5 6 b7 1 1 0 1 gt 1 0 0 0 o Only b6 cleared b4 data retained Figure 10 2 5 Example for Clearing the Interrupt Status 10 30 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer The table below shows the relationship between the interrupt signals generated by multijunction timers and the interrupt sources input to the interrupt controller Table 10 2 6 Interrupt Signals Generated by MJT Signal Name Source of Interrupt Generated Interrupt Sources Input to ICU Note 1 Number of Input Sources IRQO TIOO TIO1 TIO2 TIO3 MJT output interrupt 0 4 IRQ1 TOP6 TOP7 MJT output interrupt 1 2 IRQ2 TOPO TOP1 TOP2 TOP3 TOP4 TOP5 MJT output interrupt 2 6 IRQ3 TIO8 TIO9 output interrupt 3 2 IRQ4 4 TIO5 6 TIO7 MJT output interrupt 4 4 IRQ6 TOP8 TOP9 output interrupt 6 2 IRQ7 TMSO TMS1 MJT output interrupt 7 2 IRQ9 TINO MJT input interrupt 1 1 IRQ10 TIN16 TIN17 TIN18 TIN19 MJT input interrupt 2 4 IRQ11 TIN20 TIN21 TIN22 TIN23 input interrupt 3 4 IRQ12 input interrupt 4 1 Note 1 Refer to Chapter 5 Interrupt Controller ICU Note 2 F
584. ster CANOCNT s RST bit 0 Note 1 The protocol control unit is reset and the counter is initialized to H 0000 by setting the CAN Control Register CANOCNT s RST CAN Reset bit to 1 Also the counter can be initialized to H 0000 while the CAN module is operating by setting TSR Time Stamp Counter Reset bit to 1 Note 2 During loopback mode if an ID matching slot exists the CAN module stores the time stamp value in the corresponding slot when it finished receiving No time stamp value is stored this way when the CAN module finished transmitting 13 19 Ver 0 10 1 3 CAN MODULE 13 2 CAN Module Related Registers 13 2 6 CAN Error Count Registers CANO Receive Error Count Register CANOREC Address H 0080 100 gt DO 1 2 3 4 5 6 D7 When reset H 00 gt D Bit Name Function R 0 7 Receive error count value Receive error counter In an error active error passive state a receive error count is stored in this register When received normally the counter counts down when an error occurs the counter counts up When received normally while REC 2 gt 128 error passive REC is set to 127 In bus off state an indeterminate value is stored in this register The count is reset to H 00 upon returning to an error active state E CANO Transmit Error Count Register CANOTEC Address H 0080 100 gt D8 9 10 11 12 13 14 D15 When reset H 00 gt D Bit Na
585. ster 10 ADODT10 E 10 bit A DO Data Register 11 ADODT11 Bi 10 bit A DO Data Register 12 ADODT12 Bi 10 bit A DO Data Register 13 ADODT13 Bi 10 bit A DO Data Register 14 ADODT14 Bi 10 bit A DO Data Register 15 ADODT15 DO 1 2 3 4 5 6 7 5 11 2 Converter Related Registers Address H 0080 0090 Address H 0080 0092 Address H 0080 0094 gt Address H 0080 0096 Address H 0080 0098 Address H 0080 009A Address H 0080 009 gt Address H 0080 009 gt Address H 0080 00 0 gt Address H 0080 00A2 gt Address H 0080 00 4 gt Address H 0080 00 6 gt Address H 0080 00 8 gt Address H 0080 gt Address H 0080 00 gt Address H 0080 00AE 8 9 10 11 12 13 14 015 When reset Indeterminate D Bit Name Function R 0 5 No functions assigned 0 6 15 ADODTO ADODT15 A D conversion result 10 bit A DO data Note This register must always be accessed in halfwords In single mode of the A DO converter the result of A D conversion is stored in the 10 bit A DO Data Register for each corresponding channel In single shot and continuous scan modes the content of the A DO Successive Approximation Register is transferred to the 10 bit A D Data Register for the corresponding channel every time the A D conversion in each channel is completed Each 10 bit A D Data Register retains the last conversion result until they receive the n
586. ster has the initial value 000 set in it When the timer starts the counter starts counting down clock pulses and when it underflows after reaching the minimum count the counter is reloaded with the content of the reload register and continues counting down Enabled by writing to enable bit Underflow Underflow or by external input first time second time Countclock LUL Enable bit HFFFF H FFFF C H EEFE inet eee deles 000 V H E000 1 4 H E000 1 i Down count 7 Down count 5 Down count H AO00 Starting from starting from starting from counter s reload register reload register Counter set value set value set value EXE E M E Reload register HE000 Q Correction register Not used F F output Data inverted by Data inverted by Data inverted by enable underflow underflow 22 TOP interrupt due to underflow Note This diagram does not show detail timing information Figure 10 3 21 Typical Operation in TOP Continuous Output Mode 10 80 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer 2 Precautions to be observed when using TOP continuous output mode The following describes precautions to be observed when using TOP continuous output mode If the timer is enabled by external input in the sa
587. sters TOP control registers are used to select operation modes of TOPO 10 single shot delayed single shot or continuous mode as well as select the counter enable and counter clock sources Following four TOP control registers are provided for each timer group TOPO 5 Control Register 0 5 TOPO 5 Control Register 1 TOPO5CR1 TOP6 7 Control Register TOP67CR TOP8 10 Control Register TOP810CR 10 52 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer TOPO 5 Control Register 0 TOPOBCRO Address H 0080 029 gt 14 015 DO 1 2 3 4 5 6 7 8 9 10 11 12 13 2 1 5 5 2 TOPOSCKS When reset H 0000 gt D Bit Name Function R 0 1 TOP3 operation mode selection 00 Single shot output mode 2 3 2 2 operation mode selection 01 Delayed single shot output mode 4 5 TOP1M TOP1 operation mode selection 1X Continuous output mode 6 7 TOPOM TOPO operation mode selection 8 No functions assigned 0 9 10 TOPO5ENS OXX External TINO input TOPO 5 enable source selection 100 Input event bus 0 101 Input event bus 1 110 Input event bus 2 111 Input event bus 3 12 13 functions assigned 0 14 15 TOPO5CKS 00 Clock bus 0 O O TOPO 5 clock source selection 01 Clock bus 1 10 Clock bus 2 11 Clock bus 3 Note 1 This register must always b
588. sters 16 3 Typical Operation of the Wait Controller 1 6 WAIT CONTROLLER 16 1 Outline of the Wait Controller 16 1 Outline of the Wait Controller The wait controller controls the number of wait cycles inserted in bus cycles during access to an extended external area The following outlines the wait controller Table 16 1 1 Outline of the Wait Controller Item Specification Target space Wait cycles in following memory spaces are controlled depending on operation mode Single chip mode No target space Wait controller settings have no effect External extension mode CSO area 1 Mbytes CS1 area 1 Mbytes Processor mode CSO area 1 Mbytes CS1 area 1 Mbytes Number of wait cycles 1 to 4 wait cycles inserted by software any number of wait cycles inserted from that can be inserted WAIT pin Bus cycles with 1 wait cycle are the shortest bus cycle for external access In external extension mode and processor mode two chip select signals CSO CS1 are output to an extended external area Two areas in it corresponding to CSO CS1 signals are called the 50 and the CS1 areas respectively Non CSO0 area Internal ROM access area H 0000 0000 Ceu a P Internal ROM area 50 area 1 Mbytes H OOOF FFFF Reserved area H 0010 0000 50 area 5 Ghost of 1 Mbytes T CS0 area D 1 Mbytes H 001F FFFF g H 0020 0000 g 3 CS1 area g CS1 area 3 1 Mbytes
589. supply and ground AVCCO AVSSO are separated from those of the digital circuit with sufficient noise prevention measures incorporated For details about the conversion accuracy refer to Section 11 3 5 Accuracy of A D Conversion 10 bit A DO data register ADODTO 15 00 comparate data register ADOCMP AVCCO Li 10 bit A DO successive approximation register 4 AVSS0 ADISAR A D control circuit VREFo L 10 bit D A converter ADOINO ADOIN1 ADOIN2 ADOINS ADOIN4 ADOINS ADOIN6 ADOIN7 ADOIN8 ADOIN9 ADOIN10 ADOIN1 1 ADOIN12 ADOIN13 ADOIN14 ADOIN15 Selector Successive approximation type A D converter unit Figure 11 3 1 Outline Block Diagram of the Successive Approximation type Converter Unit 11 30 Ver 0 10 1 1 CONVERTERS 11 3 Functional Description of Converters 11 3 2 A D Conversion by Successive Approximation Method The A D converter has A D convert operation started by an A D conversion start trigger in software or hardware Once A D conversion begins the following operation is automatically executed D During single mode Single Mode Register 0 s conversion comparate completion bit is cleared to 0 During scan mode Can
590. t O output event bus 2 input selection 1 Selects TIO2 output 12 No functions assigned 0 13 15 0 Selects output O output event bus 1 input selection 1 Selects TIO1 output 14 No functions assigned 0 15 05 0 Selects TOP6 output O O output event bus 0 input selection 1 Selects 0 output The register OEBCR is used to select the timer TOP or TIO whose underflow signal is supplied to the output event bus 10 14 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer 10 2 4 Input Processing Control Unit The input processing control unit processes the TCLK and TIN signals fed into the MJT In the TCLK input processing unit selection is made of the source of TCLK signal or for external input the active edge rising or falling or both or level high or low of the signal with or at which to generate the clock signal fed to the clock bus In the TIN input processing unit selection is made of the active edge rising or falling or both or level high or low of the signal at which to generate the enable measure or count source signal for each timer or the signal fed to each event bus Following input processing control registers are included TCLK Input Processing Control Register TCLKCR Input Processing Control Register 0 TINCRO TIN Input Processing Control Register 3 TINCR3 Input Processing Control Register 4 TINCR4
591. t buffer register to the transmit shift register check the SIO Transmit Control Register s transmit buffer empty flag 12 47 Ver 0 10 1 2 SERIAL I O 12 6 Transmit Operation in UART Mode 12 6 6 Processing at End of UART Transmission When data transmission is completed the following operation is automatically performed in hardware 1 When not transmitting successively The transmit status bit is set to O 2 When transmitting successively When transmission of the last data in a consecutive data train is completed the transmit status bit is set to O 12 6 7 Transmit Interrupt If a transmit buffer empty interrupt has been enabled by the SIO Interrupt Mask Register a transmit buffer empty interrupt is generated at the time data is transferred from the transmit buffer register to the transmit shift register Also a transmit buffer empty interrupt is generated when the TEN transmit enable bit is set to 1 enabled after being disabled while a transmit buffer empty interrupt has been enabled You must set the Interrupt Controller ICU before you can use transmit interrupts 12 6 8 Transmit DMA Transfer Request When data has been transferred from the transmit buffer register to the transmit shift register a transmit DMA transfer request for the corresponding SIO channel is ouput to the DMAC This transfer request is also output when the TEN transmit enable bit is set to 1 enabled after being disabled You must se
592. t is generated and the slot goes to a wait state for the next reception 3 When receive conditions are not met The received frame is discarded and the CAN module goes to the next transmit receive operation without writing to the message slot 13 65 Ver 0 10 CAN MODULE 13 13 6 Receiving Data Frames B 0000 0000 Receive request set Clear receive request Wait for receive data B 0100 0000 Store received data Clear receive request B 0000 0011 B 0100 0011 CPU read Finished storing Finished storing 1 received data received data B 0100 0001 B 0000 0001 Store received data B 0000 0111 B 0100 0111 CPU read e gh eU pu Finished storing oO Finished storing received data received data Store received data Comes i Wait for oe Clear receive receive data request B 0000 0101 B 0100 0101 Figure 13 6 2 Operation of the CAN Message Slot Control Register when Receiving Data Frames 13 66 Ver 0 10 1 3 CAN MODULE 13 6 Receiving Data Frames 13 6 3 Reading Out Received Data Frames The following describes the procedure for reading out received data frames from the slot 1 Clearing the TRFIN Transmit Receive Finished bit Write H 40 or H 00 to the CAN Message Control Register COMSLnONT to clear the TRFIN bit to O After this write the slot operates as fol
593. t mask 1 Masks disables interrupt request W A Only writing a 0 is effective when you write 1 the previous value is retained TOPIR2 H 0080 0232 TOP7udf Data bus 2 source inputs 2 MJT output o interrupt 1 TOPIM7 Level IRQ1 06 TOP6udf TOPIS6 F F 6 07 Figure 10 2 7 Block Diagram of MJT Output Interrupt 1 10 34 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer E TOP Interrupt Control Register TOPIR3 Address H 0080 0233 2 D8 9 10 11 12 13 14 D15 TOPIS9 TOPIS8 9 TOPIM8 When reset 00 gt D Bit Name Function R W 8 9 No functions assigned 0 10 TOPIS9 interrupt status 0 No interrupt request O A 11 TOPIS8 TOP8 interrupt status Interrupt request generated 12 13 No functions assigned 0 14 9 interrupt mask 0 Enables interrupt request O O 15 TOPIM8 TOP8 interrupt mask 1 Masks disables interrupt request W A Only writing a 0 is effective when you write a 1 the previous value is retained Note For TOP10 there are no interrupt status and mask bits in MJT interrupt control registers because it only has one source of interrupt in the group It is controlled directly by the interrupt controller TOP
594. t the Interrupt Controller ICU before you can transmit data using DMA transfers 12 48 Ver 0 10 12 SERIAL I O 12 6 Transmit Operation in UART Mode The following processing is automatically executed in hardware UART transmit operation starts Transmit conditions met n Note Transmit interrupt Transfer content of transmit buffer to request transmit shift register AM Transmit Set transmit buffer empty bit to 1 transfer request Transmit data Y Successive Transmit conditions transmission met j Clear transmit status bit to 0 UART transmit operation completed Note This applies when transmit interrupt has been enabled by SIO Interrupt Mask Register Figure 12 6 4 Transmit Operation during UART Mode Hardware Processing 12 49 Ver 0 10 12 SERIAL I O 12 6 Transmit Operation in UART Mode 12 6 9 Typical UART Transmit Operation The following shows a typical transmit operation in CSIO mode UART on transmit side d UART on transmit side TXD UART on receive side RXD Set Transmit enable bit 4 Transmit status bit TXD BN ST Write to transmit buffer register Cleared Transmit buffer Y empty bit Trans
595. t these interrupts refer to each section in which the relevant internal peripheral I O is described Table 5 2 1 Interrupt Sources of Internal Peripheral I Os 1 2 Interrupt Cause Contents Number of Input ICU Type of Input Sources Source Note 00 conversion interrupt Single shot conversion in 00 converter scan mode completed 1 Edge recognized single mode completed or comparator mode completed 5100 transmit interrupt SIOO transmit buffer empty interrupt 1 Edge recognized SIOO receive interrupt 5100 reception completed or receive error interrupt 1 Edge recognized lO1transmit interrupt SIO1 transmit buffer empty interrupt 1 Edge recognized SIO1 receive interrupt SIO1 reception completed or receive error interrupt 1 Edge recognized 5102 3 transmit receive 65102 reception completed or receive error interrupt 2 Level recognized interrupt Transmit buffer empty interrupt RTD interrupt RTD interrupt generation command 1 Edge recognized DMA transfer interrupt 0 DMAO 4 transfer completed 5 Level recognized DMA transfer interrupt 1 DMA5 9 transfer completed Level recognized CANO transmit receive transmission completed CANO reception completed 19 Level recognized amp error interrupt CANO error passive CANO error bus off CANO bus error MJT output interrupt 7 output interrupt group 7 TMSO TMS1 output 2 Level recognized MJT output interrupt 6 output interrupt group 6 TOP8 TOP9 output 2 Level recogniz
596. ta 0 0 514070 CANO Message Slot 4 Data 1 COMSL4DT1 CANO Message Slot 4 Data 2 COMSL4DT2 CANO Message Slot 4 Data 3 COMSL4DT3 CANO Message Slot 4 Data 4 COMSL4DT4 CANO Message Slot 4 Data 6 COMSL4DT6 CANO Message Slot 4 Data 5 COMSL4DT5 CANO Message Slot 4 Data 7 COMSL4DT7 CANO Message Slot 4 Time Stamp COMSL4TSP CANO Message Slot 5 Standard IDO COMSL5SIDO CANO Message Slot 5 Standard 101 COMSL5SID1 CANO Message Slot 5 Extended IDO COMSLSEIDO Blank addresses are reserved CANO Message Slot 5 Extended ID1 COMSLSEID1 Figure 13 2 2 CAN Module Related Register Map 2 4 13 5 Ver 0 10 13 MODULE 13 2 CAN Module Related Registers Address H 0080 1154 H 0080 1156 H 0080 1158 H 0080 115A H 0080 115C H 0080 115E H 0080 1160 H 0080 1162 H 0080 1164 H 0080 1166 H 0080 1168 H 0080 116A H 0080 116 H 0080 116E H 0080 1170 H 0080 1172 H 0080 1174 H 0080 1176 H 0080 1178 H 0080 117A H 0080 117C H 0080 117E H 0080 1180 H 0080 1182 H 0080 1184 H 0080 1186 H 0080 1188 H 0080 118A H 0080 118C H 0080 118E H 0080 1190 H 0080 1192 H 0080 1194 H 0080 1196 H 0080 1198 H 0080 119A H 0080 119C H 0080 119E H 0080 11A0 H 0080 11A2 H 0080 11A4 H 0080 11 6 DO 0 Address D7 CANO Message Slot 5 Extended ID2 COMSL5EID2 41 Address D8 D15 CANO Message Slot 5 Data Length Register COMSL5DLC CANO Message Slot 5
597. ted 1 Measure clear free run input modes In measure clear free run input modes the timer measures a duration of time from when it starts counting till when an external capture signal is entered After the timer is enabled by writing to the enable bit in software the counter starts counting down synchronously with the count clock When a capture signal is entered from an external device the counter value at that point in time is written to a register called the measure register Especially in measure clear input mode the counter value is initialized to H FFFF upon capture from which the counter starts counting down again In measure free run mode the counter continues counting down even after capture and upon underflow recycles to H FFFF from which it starts counting down again To stop the counter disable count by writing to the enable bit in software Note that an interrupt can be generated by a counter underflow or execution of measure operation 2 Noise processing input mode In noise processing input mode the timer detects the status of an input signal that it remained in the same state for over a predetermined time In noise processing input mode the counter is started by entering a high or low level signal from an external device and if the signal remains in the same state for over a predetermined time before the counter underflows the counter stops after generating an interrupt If the valid level signal being appl
598. ter PBDATA P9 Data Register H 0080 070A P10 Data Register P10DATA P11Data Register P11DATA H 0080 070C P12 Data Register P12DATA P13 Data Register P13DATA H 0080 070E P15 Data Register P15DATA H 0080 0710 P17 Data Register P17DATA H 0080 0712 H 0080 0714 Blank addresses are reserved areas Figure 3 4 9 Register Mapping of the SFR Area 7 3 16 Ver 0 10 Address H 0080 0716 H 0080 0720 H 0080 0722 H 0080 0724 H 0080 0726 H 0080 0728 H 0080 072A H 0080 072C H 0080 072 H 0080 0730 H 0080 0732 H 0080 0734 H 0080 0736 H 0080 0744 H 0080 0746 H 0080 0748 H 0080 074A H 0080 074C H 0080 074E H 0080 0750 H 0080 0752 H 0080 0754 H 0080 0756 H 0080 077E H 0080 07EO H 0080 07E2 H 0080 07E4 H 0080 07 6 H 0080 07E8 H 0080 07 0 H 0080 07F2 H 0080 OFEO H 0080 OFE2 H 0080 OFEA H 0080 OFFO H 0080 OFF2 0 Address P22 Data Register P22DATA ADDRESS SPACE 3 4 Internal ROM SFR Area 1Address PO Direction Register PODIR P1 Direction Register P1DIR P2 Direction Register P2DIR P3 Direction Register P3DIR P4 Direction Register P4DIR P6 Direction Register PEDIR P7 Direction Register P7DIR P8 Direction Register P8DIR P9 Direction Register P9DIR P10 Direction Register P10DIR P11 Direction Register P11DIR P12 Direction Register P12DIR P14 Direction Register P14DIR P16 Di
599. ternal RAM address H 0080 4000 For details refer to Section 6 5 Writing to Internal Flash Memory This is the last operation performed in hardware preprocessing by the M32R E 5 Jumping from the EIT vector entry to the user created handler The M32R E executes the BRA instruction written at address H 0000 0080 of the EIT vector entry by the user to jump to the start address of the user created handler At the beginning of the EIT handler you created first save the BPC and PSW registers and the necessary general purpose registers to the stack 6 Returning from the EIT handler Atthe end of the EIT handler restore the general purpose registers and the BPC and PSW registers from the stack and then execute the RTE instruction As you execute the RTE instruction hardware postprocessing is automatically performed by the M32R E 4 19 Ver 0 10 4 4 10 Trap Processing 4 10 Trap Processing 4 10 1 Trap TRAP Occurrence Conditions Traps refer to software interrupts which are generated by executing the TRAP instruction Sixteen distinct traps are generated each corresponding to one of TRAP instruction operands 0 15 Accordingly sixteen vector entries are provided EIT Processing 1 Saving SM IE and C bits The SM IE and C bits of the PSW register are saved to their backup bits the BSM BIE and BC bits BSM lt SM BIE lt IE BC C 2 Updating SM IE and C bits The SM IE and C bits
600. ternal enable permit 13 TOP2EEN TOP2 external enable permit 14 TOP1EEN TOP1 external enable permit 15 TOPOEEN TOPO external enable permit Note This register must always be accessed in halfwords The TOPO 10 External Enable Permit Register controls enable operation from sources external to the TOP counter by enabling or disabling it 10 62 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer TOPO 10 Enable Protect Register TOPPRO lt Address H 0080 02FC gt DO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 015 1 9 TOP8 6 5 4 TOP3 TOP2 TOP1 TOPO PRO PRO PRO PRO PRO PRO PRO PRO PRO PRO PRO When reset H 0000 gt D Bit Name Function R 0 4 No functions assigned 0 5 TOP10PRO 10 enable protect 0 Enables rewrite 6 TOP9PRO 9 enable protect 1 Disables rewrite 7 TOP8PRO TOP8 enable protect 8 TOP7PRO TOP7 enable protect 9 TOP6PRO TOP6 enable protect 10 TOP5PRO TOP5 enable protect 11 TOP4PRO TOPA enable protect 12 TOP3PRO TOP3 enable protect 13 TOP2PRO enable protect 14 TOP1PRO TOP1 enable protect 15 TOPOPRO TOPO enable protect Note This register must always be accessed in halfwords The TOPO 10 Enable Protect Register controls rewriting of the TOPO 10 count enable bits shown in the next page by enabling or di
601. ters is entered to measure registers 0 3 the counter value is latched into the A TIN interrupt can be generated by entering an external measure signal No TML counter overflow interrupts are available Counter 32 bits value H 0000 0000 Measure 0 register TIN23 interrupt Measure 1 register TIN22 interrupt Enabled Measure Measure Measure Measure by deassertion event 0 event 1 Overflow event 0 event 1 of Ei ee E ua oh ms Count clock TAM JL des n A Reset EU BEFFF EEFE cat ed eie due Mae Indeterminate H C000 0000 H D000 0000 1572254 Z H8000 0000 H 6000 0000 Indeterminate Y H 8000 0000 6000 0000 m Gi Indeterminate K H C000 0000 Y H D000 0000 E Note This diagram does not show detail timing information Figure 10 6 3 Typical Operation in TML Measure Input 10 140 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 6 TML Input related 32 bit Timer 2 Precautions to be observed when using TML measure input The following describes precautions to be observed when using TML measure input f measure event input and write to the counter occur simultaneously in the same clock period the write value is set in the counter whereas the up count value before being rewritten is latched to the m
602. th sequence is completed you want to proceed and perform IR path sequence or DR path sequence enter JTMS high to return to Select DR Scan state If after a series of IR and DR path sequence processing is completed you want to wait for the next processing enter JTMS low to go to Run Test ldle state and retain the state 19 12 Ver 0 10 1 9 JTAG 19 4 Basic Operation of JTAG TAP Test Logic Run Test IR path DR path Run Test IR path DR path states Reset state Idle state sequence sequence Idle state sequence sequence JTDI Instruction Setup data Instruction Setup data Note 1 code 0 0 code 1 1 JTDO Note 2 Specify the data register Setup data is entered serially from JTDI you want to inspect or set Reference data is serially output from JTDO 1 Basic access TAP Test Logic Run Test IR path DR path Run Test IR path DR path states Reset state Idle state sequence sequence Idle state sequence sequence JTDI Instruction Setup data Setup data Setup data Note 1 code 0 0 1 2 JTDO Note 2 C Specify the data register Same data register uel you want to inspect or set on to inspect or set data continuously 2 Continuous access to the same data register Note 1 The setup value for each register must be entered from the JTDI pin beginning with the LSB Note 2 The value of each register is output from the JTDO
603. the DMAC 9 3 3 Starting DMA Use the REQSL cause of DMA request select bit to set the cause of DMA request To enable DMA set the TENL DMA transfer enable bit to 1 DMA transfer begins when the specified cause of DMA request becomes effective after setting the TENL DMA transfer enable bit to 1 9 3 4 Channel Priority Channel 0 has the highest priority The priority of this and other channels is shown below Channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 channel 8 channel 9 This order of priority is fixed and cannot be changed Among channels for which DMA transfers are requested the channel that has the highest priority is selected Channel selection is made every transfer cycle one DMA bus cycle consisting of three machine cycles 9 3 5 Gaining and Releasing Control of the Internal Bus For any channel control of the internal bus is gained and released in single transfer DMA mode In single transfer DMA the DMA gains control of the internal bus when DMA transfer request is accepted and after executing one transfer consisting of one read cycle one write cycle of internal peripheral clock returns bus control to the CPU The diagram below shows DMA operation in single transfer DMA Requested Gained Requested Gained Requested Gained Internal bus arbitration control requested by DMAC A A Internal Released Releas
604. the enable bit in software or by external input it starts counting down from the counter s set value synchronously with the count clock and when the minimum count is reached generates an underflow This underflow causes the counter to be reloaded with the content of reload 0 register and start counting over again Thereafter this operation is repeated each time an underflow occurs To stop the counter disable count by writing to the enable bit in software The F F output waveform in continuous output mode is inverted F F output levels change from low to high or vice versa at startup and upon underflow generating consecutive pulses until the timer stops counting Also an interrupt can be generated each time the counter underflows The valid count values are the counter set value 1 and reload 0 register set value 1 For details about count operation also see Section 10 3 11 Operation in TOP Continuous Output M10 4 TIO Input Output related 16 bit Timer 2 Precautions to be observed when using TIO continuous output mode The following describes precautions to be observed when using TIO continuous output mode f the timer is enabled by external input in the same clock period as count is disabled by writing to the enable bit the latter has priority so that count is disabled When you read the counter immediately after reloading it pursuant to underflow the value you get is temporarily H FFFF But this counter value immediat
605. this signal is Byte High Enable during external access it indicates that the upper byte DBO DB7 of the data bus is the valid data to transfer When accessing the internal function it outputs a high 5 Byte Low Write Byte Low Enable BLW BLE The pin function changes depending on the Bus Mode Control Register BUSMODC When BUSMOD 0 and this signal is Byte Low Write BLW during external write access it indicates that the lower byte DB8 DB15 of the data bus is the valid data to transfer During external read cycle it outputs a high When BUSMOD 1 and this signal is Byte Low Enable BLE during external access it indicates that the lower byte DB8 DB15 of the data bus is the valid data to transfer When accessing the internal function it outputs a high 15 2 Ver 0 10 1 EXTERNAL BUS INTERFACE 15 1 External Bus Interface Related Signals 6 Data bus DBO DB15 This is the 16 bit data bus used to access external devices 7 System clock write BCLK WR The pin function changes depending on the Bus Mode Control Register BUSMODC When BUSMOD 0 and this signal is System Clock BCLK it outputs the system clock necessary to synchronize operations an external system When the CPU clock 40 MHz a 20 MHz clock is output from BCLK When not using the BCLK WR function this pin can be used as P70 by setting the P7 Operation Mode Register 7 bit to 0 When BUSMOD 1 and this signal is W
606. tical assuming the ID Mask Register bits set to 0 are Don t care bit The standard and extended frame types are the same Note In BasicCAN mode slots 14 and 15 cannot be used as transmit slots 8 When receive conditions are met When receive conditions in 7 above are met the CAN module sets the CAN Message Slot Control Register s TRSTAT Transmit Receive Status and TRFIN Transmit Receive Finished bits to 1 while at the same time writing the received data to the message slot If the TRFIN Transmit Receive Finished bit is already 1 the CAN module also sets the ML Message Lost bit to 1 indicating that the message slot has been overwritten The message slot has its ID field and DLC field both overwritten and an indeterminate value written in its unused area e g extended ID field for standard frame reception and an unused data field Furthermore a time stamp count value at the time the message was received is written to the CAN Message Slot Time Stamp COMSLnTSP along with the received data When the CAN module finished writing to the message slot it sets the CAN Slot Interrupt Status bit to 1 If the interrupt for the slot has been enabled an interrupt request is generated and the slot goes toa wait state for the next reception Note If the CAN module received a data frame before transmitting a remote frame it stores the data frame in the slot and does not transmit the data frame 9 When receive conditions are not met
607. tion 6 enable measure 01 External input TIN8 input source selection 10 Input event bus 2 11 Input event bus 3 5 7 TIO6M 000 Single shot output mode 6 operation mode selection 001 Delayed single shot output mode 010 Continuous output mode 011 PWM output mode 100 Measure clear input mode 101 Measure free run input mode 11X Noise processing input mode Note Always make sure the counter has stopped and is idle before setting or changing operation modes 10 97 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 4 TIO Input Output related 16 bit Timer E TIO7 Control Register TIO7CR Address H 0080 036 gt D8 9 10 11 12 13 14 D15 TIO7CKS TIO7ENS TIO7M When reset H 00 gt D Bit Name Function R 8 No functions assigned 0 9 10 TIO7CKS 00 Clock bus 0 TIO7 clock source selection 01 Clock bus 1 10 Clock bus 2 11 Clock bus 3 11 12 TIO7ENS 00 No selection TIO7 enable measure 01 External input TIN9 input source selection 10 Input event bus 0 11 Input event bus 3 13 15 TIO7M 000 Single shot output mode Q Q TIO7 operation mode selection 001 Delayed single shot output mode 010 Continuous output mode 011 PWM output mode 100 Measure clear input mode 101 Measure free run input mode 11X Noise processing input mode Note Always make sure the counter has stopped and is idle before setting or changing operation modes
608. tion is indeterminate The values of BSM BIE and BC bits after execution of the RTE instruction are indeterminate When EIT is accepted When instruction is executed BPSW field PSW field 0 MSB 78 15 23 24 25 31 LSB 0 000000000000000 BSM Figure 4 6 1 Saving and Restoring the PC and PSW 4 9 Ver 0 10 4 EIT 4 7 EIT Vector Entry 4 7 EIT Vector Entry The EIT vector entry is located in the user space starting from address H 0000 0000 The table below lists the EIT vector entry Table 4 7 1 EIT Vector Entry Name Abbreviation Vector Address SM IE BPC Reset Interrupt RI H 0000 0000 Note 1 0 0 Indeterminate System Break Interrupt SBI H 0000 0010 0 0 PC of the next instruction Reserved Instruction RIE H 0000 0020 Indeterminate 0 PC of the instruction that Exception generated EIT Address Exception AE H 0000 0030 Indeterminate 0 PC of the instruction that generated RIE Trap TRAPO H 0000 0040 Indeterminate 0 of TRAP instruction 4 TRAP1 H 0000 0044 Indeterminate 0 PC of TRAP instruction 4 TRAP2 H 0000 0048 Indeterminate 0 PC of TRAP instruction 4 TRAP3 H 0000 004C Indeterminate 0 PC of TRAP instruction 4 TRAP4 H 0000 0050 Indeterminate 0 PC of TRAP instruction 4 TRAP5 H 0000 0054 Indeterminate 0 PC of TRAP instruction 4 TRAP6 H 0000 0058 Indeterminate 0 of TRAP instruction 4 TRA
609. to Section 18 1 1 Example of an Oscillator Circuit Reset RESET Reset Input This pin resets the internal circuit Mode MODO Mode Input These pins set operation mode MOD1 MODO MOD1 Mode 0 0 Single chip mode 0 1 Extended external mode 1 0 Processor mode Boot mode Note 1 1 Reserved Address 12 A30 Address Output The device has 19 address lines A12 A30 to allow two Bus Bus channels of up to 1 MB of memory space to be added external to the chip A31 is not output Note For boot mode refer to Chapter 6 Internal Memory 1 11 Ver 0 10 OVERVIEW 1 3 Pin Function Table 1 3 1 Description of the 32171 Pin Function 2 5 Type Pin Name Signal Name Input Output Function Data DBO DB15 Data bus Input output These pins comprise 16 bit data bus to connect external devices In write bus cycles the valid byte positions to be written on the 16 bit data bus are output as BHW BHE and BLW BLE In read cycles data is always read from the 16 bit data bus However when transferring to the internal circuit of the M32R only data at the valid byte positions are transferred Bus 50 Chip select Output These pins comprise external device chip select signal For control CS1 areas for which a chip select signal is output refer to Chapter 3 Address Space RD Read Output This signal is output when reading an external device BHW BHE Byte high Output Indicates the byte positi
610. to enable interrupts 3 About DMA transfer requests from SIO Each SIO can generate a transmit DMA transfer and a receive finished DMA transfer request These DMA transfer requests can be generated by enabling each SIO s corresponding TEN transmit enable bit or REN receive enable bit When using DMA transfers to communicate with external devices be sure to set the DMAC before enabling the TEN or REN bits When a receive error occurs no receive finished DMA transfer requests are generated Transmit DMA transfer request Generated when the transmit buffer is empty and the TEN bit is enabled TEN transmit enable bit TBE transmit buffer empty bit Transmit DMA transfer request B Figure 12 2 2 Transmit Transfer Request 12 7 Ver 0 10 1 2 SERIAL I O 12 2 Serial I O Related Registers Receive finished DMA transfer request DMA transfer request is generated when the receive buffer is filled RFIN receive completed bit Receive DMA transfer request Note When a receive error occurs no receive finished DMA transfer requests are generated Figure 12 2 3 Receive finished DMA Transfer Request 12 8 Ver 0 10 1 2 SERIAL I O 12 2 Serial Related Registers 12 2 2 SIO Interrupt Control Registers E 51023 Interrupt Status Register 51235 lt Address H 0080 0100 gt DO 1 2 3 4 5 6 D7 IRQT2 IRQR2
611. trary to the export control laws and regulations of Japan and or the country of destination is prohibited e Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein PREFACE This manual describes the hardware specifica tions of Mitsubishi s 32171 group of 32 bit CMOS microcomputers This manual was created to help you under stand the hardware specifications of the 32171 group microcomputers so you can take full advantage of the versatile performance ca pabilities of these microcomputers The CPU features and the functionality of each internal peripheral circuit are described in detail which we hope will prove useful for your circuit de sign For details about the M32R family software products and development support tools please refer to the user s manuals and related other documentation included with your prod ucts and tools How to read internal 1 register tables Bit Numbers Each register is connected with an internal bus of 16 bit wide so the bit numbers of the registers located at even addresses 00 07 and those at odd addresses are D8 D15 State of Register at Reset Represents the initial state of each register immediately after reset with hexadecimal numbers undefined bits after reset are indicated each in column At read O read enabled read disabled read
612. ts DMA transfer 5 ADOCCMP 0 A DO conversion in progress Q A DO conversion completed 1 A DO conversion completed 6 ADOCSTP 0 Performs no operation 0 Q A DO conversion stop 1 Stops A DO conversion 7 ADOCSTT 0 Performs no operation 0 A DO conversion start 1 Starts A DO conversion A DO Scan Mode Register 0 is used to control operation of the A DO converter during scan mode 11 21 Ver 0 10 1 1 5 11 2 Converter Related Registers 1 ADOCMSL 0 scan mode select bit D1 This bit selects the A DO converter scan mode between one shot scan and continuous scan modes Setting this bit to 0 selects one shot scan mode so that A D conversion of channels selected with the ANOSCAN scan loop select bit are performed sequentially When A D conversion on all selected channels is completed the convert operation stops Setting this bit to 1 selects continuous scan mode so that when operation in one shot mode finishes A D conversion is performed from the first channel again This is repeated until stopped by setting the ADOCSTP A DO conversion stop bit to 1 2 ADOCTRG A DO hardware trigger select bit D2 When starting A D conversion of the A DO converter in hardware this bit specifies the conversion to be started by MJT output output event bus 3 If software trigger is selected with the ADOSSEL A D conversion start trigger select bit the content of this bit is ignored 3 ADOCS
613. ty flag 12 28 Ver 0 10 1 2 SERIAL I O 12 3 Transmit Operation in CSIO Mode 12 3 5 Processing at End of CSIO Transmission When data transmission is completed the following operation is automatically performed in hardware 1 When not transmitting successively The transmit status bit is set to 0 2 When transmitting successively When transmission of the last data in a consecutive data train is completed the transmit status bit is set to O 12 3 6 Transmit Interrupt If a transmit buffer empty interrupt has been enabled by the SIO Interrupt Mask Register a transmit buffer empty interrupt is generated at the time data is transferred from the transmit buffer register to the transmit shift register Also a transmit buffer empty interrupt is generated when the TEN transmit enable bit is set to 1 enabled after being disabled while a transmit buffer empty interrupt has been enabled You must set the Interrupt Controller ICU before you can use transmit interrupts 12 3 7 Transmit DMA Transfer Request When data has been transferred from the transmit buffer register to the transmit shift register a transmit DMA transfer request for the corresponding SIO channel is ouput to the DMAC This transfer request is also output when the TEN transmit enable bit is set to 1 enabled after being disabled You must set the Interrupt Controller ICU before you can transmit data using DMA transfers 12 29 Ver 0 10 12
614. uctions residing on word boundaries and when an interrupt request is detected and the PSW register IE flag 1 accepts it as an external interrupt In no case will an external interrupt be activated immediately after executing a 16 bit instruction that starts from a word boundary For 16 bit branch instructions however the interrupt may be accepted immediately after branching Address 1000 2 Order in which instructions are executed Address 1002 Address 1004 Address 1008 16 bit instruction 16 bit instruction 32 bit instruction A Interrupt may be accepted A Interrupt cannot be accepted A Interrupt may be accepted Figure 4 9 2 Timing at Which External Interrupt El is Accepted Interrupt may be accepted 4 18 Ver 0 10 4 EIT 4 9 Interrupt Processing EIT Processing 1 Saving SM IE and C bits The SM IE and C bits of the PSW register are saved to their backup bits the BSM BIE and BC bits BSM lt SM BIE IE BC C 2 Updating SM IE and C bits The SM IE and C bits of the PSW register are updated as shown below SM 0 IE 0 C 0 8 Saving PC The content always word boundary of the PC register is saved to the BPC register 4 Branching to the EIT vector entry Control branches to the address H 0000 0080 in the user space However when operating in flash E W enable mode control goes to the beginning of the in
615. ue is retained TINIRO lt H 0080 0238 gt Data bus TINO edge MJT input interrupt 1 TINIMO Level IRQ9 b7 F F Figure 10 2 13 Block Diagram of MJT Input Interrupt 1 10 40 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer E TIN Interrupt Control Register 1 TINIR1 Address H 0080 0239 gt D8 9 10 11 12 13 14 D15 TINIS3 6 5 TINIM4 TINIM3 When reset 00 gt D Bit Name Function R 8 10 No functions assigned 0 11 5 interrupt status 0 No interrupt request O A 1 Interrupt request generated 12 6 reserved Setting this bit has no effect 13 TINIM5 reserved 14 TINIM4 reserved 15 interrupt mask 0 Enables interrupt request 1 Masks disables interrupt request W A Only writing a 0 is effective when you write 1 the previous value is retained TINIR1 lt H 0080 0239 gt Data bus TINSedge PNSS F F MJT input interrupt 4 Leve IRQ12 015 Figure 10 2 14 Block Diagram of MJT Input Interrupt 4 10 41 Ver 0 10 10 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer E TIN Interrupt Control Register 4 TINIR4 Address H 0080 023C
616. uffer Register DO D7 D8 D15 1 l 7 bit characters 8 bit characters gt 9 bit characters Note 1 The high order bits of the SIO Receive Buffer Register s selected character bits are fixed to 0 Note 2 The data bit numbers Dn above indicate bit numbers in a data list and not the register bit numbers Dn Figure 12 6 2 Selectable Data Formats during UART Mode 12 44 Ver 0 10 1 2 SERIAL I O 12 6 Transmit Operation in UART Mode 12 6 3 Initial Settings for UART Transmission To transmit data in UART mode initialize the serial following the procedure described below 1 Setting SIO Transmit Receive Mode Register Set the register to UART mode Set parity when enabled select odd even Set stop bit length Set character length Note During UART mode settings of the internal external clock select bit have no effect only the internal clock is useful 2 Setting SIO Transmit Control Register Select the clock divider s divide by ratio 3 Setting SIO Baud Rate Register Set a baud rate generator value Refer to Section 12 6 1 Setting the UART Baud Rate 4 Setting SIO Interrupt Mask Register Enable or disable SIO transmit interrupt 5 Setting the Interrupt Controller SIO Transmit Interrupt Control Register When you use a transmit interrupt set its priority level 6 Setting DMAC When you issue DMA transfer requests to the inte
617. uit application examples contained in these materials All information contained in these materials including product data diagrams and charts represent information on products at the time of publication of these materials and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes such as apparatus or systems for transportation vehicular medical aerospace nuclear or undersea repeater use e The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials e these products or technologies are subject to the Japanese export control restrictions they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination Any diversion or reexport con
618. ultifunction timer Contains output related timer x 11 channels input output related timer x 10 channels 16 bit input related timer x 8 channels and 32 bit input related timer x 8 channels Capable of flexible timer configuration by mutual connection between each channel A D converter 16 channel 10 bit resolution converter Incorporates comparator mode Can generate interrupt or start DMA transfer upon completion of conversion Can read out conversion results in 8 or 10 bits Serial 3 channel serial I O be set for clock synchronized serial I O or UART Capable of high speed data transfer at 2 Mbits per second when clock synchronized or 156 Kbits per second during UART Real time debugger rewrite or monitor the internal RAM independently of the CPU by command input from an external source Has its exclusive clock synchronized serial port Interrupt controller Accepts and manages interrupt requests from internal peripheral I O Resolves interrupt priority in 8 levels including interrupt disabled state Wait controller Controls wait state for access to extended external areas Can insert 1 to 4 wait cycles by setting in software and extend wait period by external WAIT signal Clock PLL Multiply by 4 clock generator circuit Maximum 40 MHz of CPU clock CPU internal ROM internal RAM access Maximum 20 MHz of internal peripheral clock peripheral module
619. und off the value stored in the accumulator to 16 or 32 bits as well as instructions to shift the accumulator value to adjust digits and store the digit adjusted value in a register These instructions also can be executed in one cycle so that when combined with high speed data transfer instructions such as Load amp Address Update and Store amp Address Update they enable the M32R to exhibit high data processing capability comparable to that of DSP 1 1 3 Built in Flash Memory and RAM The 32171 contains flash memory and RAM which can be accessed with no wait states allowing you to build a high speed embedded system The internal flash memory allows for on board programming you can write to it while being mounted on the printed circuit board Use of flash memory means the chip engineered at the development phase can be used directly in mass production so that you can smoothly migrate from prototype to mass production without changing the printed circuit board The internal flash memory can be rewritten 100 times The internal flash memory has a pseudo flash emulation function allowing the internal RAM to be artificially mapped into part of the internal flash memory This function when combined with the internal Real Time Debugger RTD facilitates data tuning on ROM tables The internal RAM can be accessed for read or rewrite from an external device independently of the M32R by using RTD real time debugger It is communicated with ext
620. up and upon underflow generating a single shot pulse waveform in width of reload register set value 1 only once Also an interrupt can be generated when the counter underflows The count value is reload register set value 1 In the case shown below for example if the reload register value 7 then the count value 8 Because all internal circuits operate synchronously with the count clock a finite time equal to a prescaler delay is included before F F output changes state after the timer is enabled Count value 8 1 2 3 4 5 6 7 dl Count clock i f 1 f 1 f 1 TL fi Enable Note 1 Counter Reload aris E register 2 H FFFF F F output2 Interrupt i A finite time equal to a prescaler delay is Underflow included before F F output changes state after the timer is enabled Note 1 What you actually see in the cycle immediately after reload is the previous counter value and not 7 Note 2 This diagram does not show detail timing information Figure 10 3 9 Example of Counting in TOP Single shot Output Mode 10 66 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer In the example below the reload register has the initial value 000 set in it The initial value of the counter can be indeterminate and does not have to be specific When the timer starts the reload register value is loaded into the c
621. upply current when operating 8 0 2 10 VCCI power supply current when operating f XIN 8 0MH 2 105 OSCVCC power supply current FVCC power supply ae VDD power meen mm IAVCC AVCC power at 22 f XIN 8 0MH 2 when operating IVREF VREF power supply current f XIN 28 0MH 2 Note 1 Maximum value including currents during program erase operation Note 2 Maximum value including cases where the program is executed in RAM 21 8 Ver 0 10 21 ELECTRICAL CHARACTERISTICS 21 3 DC Characteristics RAM retention power supply current in a standard sample reference value 1000 100 VDD V 21 9 Ver 0 10 21 ELECTRICAL CHARACTERISTICS 21 3 DC Characteristics 21 3 2 Flash Related Electrical Characteristics Flash Related Electrical Characteristics Referenced to VOCE 5 V 0 5 V VCCI 3 3 V 0 3 V Unless Otherwise Noted Symbol Condition Rated Value Value Power Supply Current when Programming Ifvcc2 FVCC Power Supply Current m Temperature we 0 Poonam m om mec 5 m 21 10 Ver 0 10 21 ELECTRICAL CHARACTERISTICS 21 4 A D Conversion Characteristics 21 4 A D Conversion Characteristics Conversion Characteristics Referenced to AVCC VREF VCCE 5 12 V Ta 25 f XIN 10 0 MHz Unless
622. upts available for TML1 However the TML does not have counter overflow interrupts 10 132 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 6 TML Input related 32 bit Timer 10 6 3 TML Related Register Map The diagram below shows a TML related register map Address Do 0 Address D7 D8 1 Address D15 H 0080 TMLO Counter High TMLOCTH 0080 03E2 TMLO Counter Low TMLOCTL TMLO Control Register TMLOCR 0080 0080 0080 OS3F2 0080 O3F4 0080 O3F6 0080 O3F8 0080 0080 0080 O3FE 0080 0080 OFE2 TML1 Counter Low TML1CTL TML1 Control Register E TML1CR H OOSO Measure Register High TML1MR3H 0080 OFF2 Measure 3 Register Low TML1MR3L 8 OFF4 Measure 2 Register High TML1MR2H 0080 OFF6 Measure 2 Register Low TML1MR2L 0080 Measure 1 Register High TML1MR1H 0080 OFFA Measure 1 Register Low TML1MR1L H OOSO OFEC Measure 0 Register High TML1MROH H OO80 OFF El Measure Register Low TML1MROL Blank addresses are reserved Note The registers enclosed in thick frames must always be accessed in halfwords Figure 10 6 2 TML Related Register Map 10 133 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 6 TML Input related 32 bit Timer 10 6 4 TML Control Registers E TMLO Control Register
623. ure clear input mode 101 Measure free run input mode 11X Noise processing input mode 4 TIO2ENS reserved Setting this bit has no effect 5 7 TIO2M 000 Single shot output mode 2 operation mode selection 001 Delayed single shot output mode Note 3 010 Continuous output mode 011 PWM output mode 100 Measure clear input mode 101 Measure free run input mode 11X Use inhibited 8 TIO1ENS reserved Setting this bit has no effect O O Continues to the next page Note 1 select enable measurement input source use the TIO4 Control Register TIO34ENS 4 enable measurement input source select bits Note 2 During measurement free run clear input mode the TIO1 and TIO2 timers do not have the capture function Note 3 Even when this bit is 0 external input disabled during measurement free run clear input mode if a capture signal is entered from an external device the counter value at that point in time is written to the measurement register However because if this bit is 0 external input disabled during measurement clear input mode the counter value may not be initialized H FFFF upon capturing make sure this bit 1 external input enabled before using the measurement clear function Note 4 This register must always be accessed in half word Note 5 Before setting or changing operation mode always be sure to stop the counter 10 91 Ver 0 10 10 MULTIJUN
624. urrent from the backup battery to the M32R E Also the power supply monitor IC s power outage detection pin outputs a low causing the SBI pin or ADnINi pin input to go low which generates a RAM backup signal D in Figure 17 2 3 Whether the power is down or not must be determined with respect to the DC IN regulator input voltage in order to allow for a software processing time at power outage To enable RAM backup mode make the following settings 1 Create check data to verify after returning from RAM backup to normal mode whether the RAM data has been retained normally in Figure 17 2 3 When the power supply to VCC goes down after settings in 1 the voltage applied to the VDD pin becomes 2 0 3 3 V and voltages applied to all other pins drop to 0 V and the 2 thereby enters RAM backup mode in Figure 17 2 3 DC IN X gt Input Regulator Output bV system Regulator Output 3 3V system xt Power supply c monitor IC Note 5 Backup power supply 77 for power outage Note 1 2 0V 3 8V Reference voltage for power outage detection Note 3 VDD VCCI OSC VCC VCCE VREFn ote Power outage ___ detection signal SBI Note 4 m 2 Backup battery M32R E 77 77 Note 1 Power outage is detected by the DC IN Example of RAM backup processing regulator input voltage Note 2 These pins are used to detect a RAM backup signal Note 3 This pi
625. us Mode Control Register BUSMODC The 32171 contains a function to switch between two external bus modes Bus Mode Control Register BUSMODC Address H 0080 077F D8 9 10 11 12 13 14 D15 BUSMOD When reset 00 gt D Bit Name Function R 8 15 functions assigned 0 15 BUSMOD 0 WR signal separate mode Bus mode control 1 Byte enable separate mode This register is used to facilitate memory connection in processor mode and external extension mode When Bus Mode Control Register BUSMOD 0 the WR signal is output separately for each byte area Signals RD BHW BLW BCLK and WAIT can be used For memory connection in boot mode the Bus Mode Control Register has no effect and the interface operates under conditions where Bus Mode Control Register BUSMOD 0 When Bus Mode Control Register BUSMOD 1 the byte enable signal is output separately for each byte area Signals RD BHW BLE WR and WAIT can be used For WAIT control circuit configuration because BCLK is not output external timing control is required BUSMOD 0 BUSMOD 1 12 0 gt A12 A30 CS0 CS1 gt 50 CS1 gt BCLK gt RD WR BHW BLW BLE DBO DB15 DBO DB15 M WAIT WAIT 4 Figure 15 1 1 Pin Function when Bus Modes are Changed 15 5 Ver 0 10 1 5 EXTER
626. using the clock divider Next it divides the resulting clock by BRG set value 1 according to the BRG set value and then by 16 which results in generating a transmit receive shift clock When using SIOO or SIO1 in UART mode you can choose the relevant port P84 or P87 to function as the SCLKO pin so that a divided by 2 BRG output clock can be output from the SCLKO pin When using the internal clock internally clocked CSIO or UART mode with f BCLK selected as the BRG count source make sure that during CSIO mode the transfer rate does not exceed 2 Mbits per second and that during UART mode BRG is equal to or greater than 7 12 24 Ver 0 10 12 12 3 Transmit Operation CSIO Mode 12 3 1 Setting the CSIO Baud Rate The baud rate data transfer rate in CSIO mode is determined by a transmit receive shift clock The clock source from which to generate the transmit receive shift clock is selected from the internal clock f BCLK or external clock The CKS internal external clock select bit SIO Transmit Receive Mode Register D11 bit is used to select the clock source The equation by which to calculate the transmit receive baud rate values differs with the selected clock source whether internal or external 1 When internal clock is selected in CSIO mode When the internal clock is selected f BCLK is divided by the clock divider before being fed into the baud rate generator BRG The clock divider s divide by value i
627. ut data 6 FD9 F F9 output data 7 FD8 F F8 output data 8 FD7 F F7 output data 9 FD6 F F6 output data 10 FD5 F F5 output data 11 FD4 F F4 output data 12 FD3 output data 13 FD2 F F2 output data 14 FD1 F F1 output data 15 FDO F FO output data Note This register must always be accessed in halfwords This register is used to set data in each output F F flip flop Normally the data output from F F changes with timer output but by setting data 0 or 1 in this register you can produce the desired output from any F F The F F Data Register can only be accessed for write when the F F Protect Register described above is enabled for write 10 27 Ver 0 10 1 0 MULTIJUNCTION TIMERS 10 2 Common Units of Multijunction Timer B F F Data Register 1 FFD1 Address H 0080 022 gt D8 9 10 11 12 13 14 D15 When reset 00 gt D Bit Name Function R W 8 10 No functions assigned 0 E 11 FD20 F F20 output data 0 F F output data 0 12 FD19 F F19 output data 1 F F output data 1 13 FD18 F F18 output data 14 FD17 F F17 output data 15 FD16 F F16 output data This register sets output of each output F F flip flop F F outputs normally vary with timer output but can forcibly be set to either 0 or 1 as desired by manipulating this register The F F Data Register can be operated on only when the F F Protect Register describ
628. uts lower than the gt lt fullscale l scale error Ideal conversion line Conversion line where the output code does not reach the full scale even for full scale equivalent analog inputs Full scale gt Along input level Figure 11 3 7 A D Converter s Full scale Error 11 39 Ver 0 10 1 1 5 11 4 Precautions on Using Converters 11 4 Precautions on Using A D Converters Forcible termination during scan operation If A D conversion is halted by setting the A D conversion stop bit ADOCSTP to 1 during scan mode operation and you read the content of the A D data register for the channel in which conversion was in progress it shows the last conversion result that had been transferred to the A D data register before the conversion was forcibly terminated Modification of A D converter related registers If you want to change the contents of the A D Conversion Interrupt Control Register each Single and Scan Mode Register or A D Successive Approximation Register except for the A D conversion stop bit do your change while A D conversion is inactive or be sure to restart A D conversion after you changed the register contents If the contents of these registers are changed in the middle of A D conversion the conversion results cannot be guaranteed Handling of analog input signals The A D converters included in the 32171 do not have a sample and h
629. value 1 and then stops without performing any operation When after setting the counter and reload register the timer is enabled by writing to the enable bit in software or by external input it starts counting down from the counter s set value synchronously with the count clock The first time the counter underflows the reload register value is loaded into the counter causing it to continue counting down and the counter stops when it underflows next time The F F output waveform in delayed single shot output mode is inverted F F output levels change from low to high or vice versa when the counter underflows first time and next generating a single shot pulse waveform in width of reload register set value 1 only once with the output delayed by an amount of time equal to first set value of counter 1 Also an interrupt can be generated when the counter underflows first time and next The valid count values are the counter set value 1 and reload register set value 1 The diagram below shows timer operation as an example when the initial counter value 4 and the initial reload register value 5 Count value 4 1 5 1 11 1 2 3 4 5 6 7 8 9 1 1 Count clock Prescaler delay Enable _ Note 1 Note 2 Counter register gt 7 F F output 22 Interrupt Underflow Underflo
630. vels that have been set for each interrupt source by setting the Interrupt Control Register ILEVEL bits When the Interrupt Vector Register IVECT described above is read out a new mask value NEW IMASK is set in this IMASK register When any value is written to the IMASK register operations 1 to 2 below are automatically performed in hardware 1 The interrupt request El to the CPU core is cleared 2 The ICU s internal sequencer is activated to start internal processing interrupt priority resolution CAUTION Note that the Interrupt Mask Register IMASK can only be read out by the EIT handler PSW register IE bit being disabled 5 7 Ver 0 10 INTERRUPT CONTROLLER ICU 5 3 ICU Related Registers 5 3 3 SBI System Break Interrupt Control Register SBI System Break Interrupt Control Register Address H 0080 0006 gt DO 1 2 3 4 5 6 D7 SBIREQ When reset 00 gt D Bit Name Function R 0 6 No functions assigned 0 7 SBI REQ SBI request 0 SBI is not requested O A 1 SBI is requested W A Writable for only clearing operation see the description below The SBI System Break Interrupt is an interrupt generated by a falling edge on SBI signal input pin When an SBI occurs the SBI Control Register s SBIREQ SBI request bit is set to 1 The SBIREQ bit cannot be set in software To clear the SBIREQ bit after being set perform the operation described below
631. vides 4 Mbytes of space 1 5 Ver 0 10 OVERVIEW 1 1 Outline of the 32171 1 1 6 Built in Full CAN Function The 32171 contains CAN Specification V2 0B compliant CAN module thereby providing 16 message slots 1 1 7 Built in Debug Function The 32171 supports JTAG interface Boundary scan test can be performed using this JTAG interface 1 6 Ver 0 10 1 OVERVIEW 1 2 Block Diagram 1 2 Block Diagram Figure 1 2 1 shows a block diagram of the 32171 Features of each block are shown in Tables 1 2 1 through 1 2 3 32171 M32R CPU core Internal bus interface max 40 MHz DMAC Multiplier 10 channels accumulator 82 X 16 56 Multijunction timer MJT 37 channels A D converter Internal flash memor T 10 bit resolution 16 channels M32171F4 512KB M32171F3 384KB Internal 32 bit bus Serial 8 channels Interrupt controller 22 sources 8 levels 5 5 2 c E 9 E Internal RAM 16KB Wait controller Full CAN 1 channel Real time debugger RTD External bus interface PLL clock generator circuit Data TEN Address Input output port JTAG 97 lines Figure 1 2 1 Block Diagram of the 32171 1 7 Ver 0 10 OVERVIEW 1 2 Block Diagram Table 1 2 1 Features of the M32R Family CPU Core Functional Block M32R family CPU core Features Bus specifications Basic bus cycle 25 ns when operating with 40 MHz CPU
632. voltage 5 12 x N 1024 V 22 2 Ver 0 10 APPENDIX 1 MECHANICAL SPECIFICATIONS Appendix 1 1 Dimensional Outline Drawing Appendix 1 Appendix 1 1 Dimensional Outline Drawing 1 144 pin QFP MECHANICAL SPECIFICATIONS Appendix 1 1 Dimensional Outline Drawing 144P6Q A Plastic 144pin 20X20mm body LQFP EIAJ Package Code JEDEC Code Weight g Lead Material LQFP144 P 2020 0 50 MD 9 HD c 1 D e Lj 92 O e UZ Recommended Mount Pad Dimension in Millimeters Symbol Min Nom Max A 1 7 0 05 0 125 02 A2 1 4 b 017 022 0 27 0 105 0 125 0 175 3 D 199 200 201 E 199 200 20 1 6 Z 0 5 11 218 22 0 222 218 220 222 L 0 35 05 0 65 Sl Li 1 0 L n 9 0 1 I tj I ui 0 0 Z 8 d b2 0225 b Tal y L l2 1 0 m Detail F Mb 204 20 4 Appendix 1 2 Ver 0 10 A A D
633. w Note 1 What you actually see in the cycle immediately after enable is the previous counter value and not 4 Note 2 What you actually see in the cycle immediately after reload is H FFFF underflow value and not 5 Note 3 This diagram does not show detail timing information Figure 10 3 15 Example of Counting in TOP Delayed Single shot Output Mode 10 73 Ver 0 10 10 MULTIJUNCTION TIMERS 10 3 TOP Output related 16 bit Timer In the example below the counter has the initial value 000 set in it and the reload register has the initial value 000 set in it When the timer starts the counter starts counting down clock pulses and when it underflows after reaching the minimum count the counter is reloaded with the content of the reload register Then when the counter underflows next time while continuing down count it stops Enabled i Underflow Underflow by writing to enable bit first time second time or by external input Y Y Count clock UUL UL WUL Enable bit v BEREBR 2 eee d H F000 Down count starting Down count starting H A000 from counter s from reload register s set value set value Counter EN d gest Ne Reload register H F000 Correction register used F F output Data inverted by Data inverted by underflow underflow TOP interrupt due to unde
634. ximation method is used to perform A D conversion With this method the reference voltage VREFO and analog input voltages are sequentially compared bitwise beginning with the high order side and the comparison result is set in the A DO Successive Approximation Register ADOSAR bits D6 D15 After the A D conversion is completed the value of this register is transferred to the 10 bit A DO Data Register ADODTn corresponding to the converted channel When you read this register in the middle of A D conversion you see the result in the middle of conversion In comparator mode write a comparison value the value to be compared in comparate operation to this register Simultaneously with a write to this register comparate operation with the analog input pin that has been set by Single Mode Register 1 starts After comparate operation the result is stored in the A DO Comparate Data Register ADOCMP Use the calculation formula shown below to find the comparison value to be written to the A DO Successive Approximation Register ADOSAR during comparator mode Comparate comparison voltage V VREFO input voltage V Comparison value H 3FF x 11 26 Ver 0 10 1 1 5 11 2 Converter Related Registers 11 2 6 A D Comparate Data Register A DO Comparate Data Register ADOCMP Address H 0080 008 gt 12 13 14 D15 0 DO 1 2 3 4 5 6 7 8 9 10 11 ADO ADO ADO ADO ADO ADO ADO ADO ADO
635. xtended ID1 COMSL5SEID1 3 19 Figure 3 4 12 Register Mapping of the SFR Area 10 Ver 0 10 ADDRESS SPACE 3 4 Internal ROM SFR Area Address H 0080 1154 H 0080 1156 0080 1158 H 0080 115A H 0080 115C H 0080 115E H 0080 1160 H 0080 1162 H 0080 1164 H 0080 1166 0080 1168 H 0080 116A H 0080 116C 0080 116E H 0080 1170 H 0080 1172 H 0080 1174 H 0080 1176 H 0080 1178 H 0080 117A 0080 117C H 0080 117E 0080 1180 H 0080 1182 H 0080 1184 H 0080 1186 H 0080 1188 H 0080 118A 0080 118C H 0080 118E 0080 1190 H 0080 1192 H 0080 1194 0080 1196 H 0080 1198 H 0080 119A 0080 119C 0080 119E H 0080 11A0 H 0080 11A2 0080 11 4 0080 11 6 0 Address DO CANO Message Slot 5 Extended 102 COMSL5EID2 1 Address D7 D8 D15 CANO Message Slot 5 Data Length Register COMSL5DLC CANO Message Slot 5 Data 0 COMSL5DTO CANO Message Slot 5 Data 1 COMSL5DT1 CANO Message Slot 5 Data 2 COMSL5DT2 CANO Message Slot 5 Data 3 COMSL5DT3 CANO Message Slot 5 Data 4 COMSL5DT4 CANO Message Slot 5 Data 5 COMSL5DT5 CANO Message Slot 5 Data 6 COMSL5DT6 CANO Message Slot 5 Data 7 COMSL5DT7 CANO Message Slot 6 Standard IDO COMSL6SIDO CANO Message Slot 5 Time Stamp COMSL5TSP CANO Message Slot 6 Standard 101 COMSL6SID1 CANO Message Slot 6 Extended IDO COMSL6EIDO CANO Message Slot 6 Extended ID2 COM
636. y executed in single mode during scan operation Scan mode start after single mode execution Scan operation is started subsequently after executing conversion in single mode Conversion restart A D conversion being executed in single or scan mode is restarted The A D conversion and comparate rates can be selected between normal and double rate An A D conversion interrupt request or a DMA transfer request can be generated at completion of A D conversion comparate operation single shot scan operation or one cycle of continuous scan operation Note To discriminate between the comparison operation performed internally by the successive approximation type A D converter and the operation in comparator mode performed using the A D converter as a comparator the comparison operation in comparator mode in this manual is referred to as comparate 11 2 Ver 0 10 11 CONVERTERS 11 1 Outline of Converters Table 11 1 1 outlines the A D converter Figure 11 1 1 shows a block diagram of the A D converter Table 11 1 1 Outline of A D Converters Item Analog input Content 16 channels A D conversion method Successive approximation method Resolution 10 bits Conversion results can be read out in either 8 bits or 10 bits Nonlinearity error Note1 Conditions 25 C AVCC0 1 VREFO0 1 5 12V Normal rate mode 2LSB Double rate mode 2LSB Conversion mode A D conversion mo
637. ystem Break Interrupt SBI Operation 5 21 5 6 1 Acceptance Of 5 21 5 6 2 SBI Processing by 5 21 CHAPTER 6 INTERNAL MEMORY 6 1 Outline of the Internal Memory 6 2 6 2 Internal 6 2 6 3 Internal Flash Memory 6 2 6 4 Registers Associated with the Internal Flash Memory 6 3 6 4 1 Flash Mode 6 4 6 4 2 Flash Status 6 5 6 4 3 Flash Controle Registers 6 8 6 4 4 Virtual Flash L Bank Registers 6 14 6 4 5 Virtual Flash S Bank Registers 6 15 6 5 Programming of the Internal Flash 6 16 3 6 5 1 Outline of Programming Flash Memory 6 16 6 5 2 Controlling Operation Mode during Programming Flash 6 22 6 5 3 Programming Procedure to the Internal Flash Memory 6 25 6 5 4 Flash Write Time for Reference 6 38 6 6 ci koci SG eae 6 39 6 7 Virtual F

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