ComSync/PCI-104 User Manual
Contents
1. 18 Connecting Serial Devices ERR 19 V 28 COMMECTIONS 19 RS 422 N Connections 19 ComSync PCI 104 Synchronous Clocking 20 Iph Wonder 20 Connector PINOUTS TT 21 PCT IOA Headet PI e TO ra DESI He ERES 21 PPCM Ke ve M EET 22 ComSync PCT 104 Specifications eese essent sere tette tret tana tette nnam etta tenet oth ntt theo oin 22 Operating Enyvirontuent eld tee ert re 22 OMT TI CATIONS s T 22 ESD Protection oer etc eve OUR 22 E m En 22 Connectors 22 22 Cable 22 VO Connect Pin Assignments 3 eig estre np eite aeree 23 Multi drop communications using V 11 RS 422 485 line modes esee 24 Asynchronous Communications 1 24 Serial Line Interface Tutorial e reete ee E Eee ERREUR ERE tue Ee HERE Hee FREE DEUS 25 RS 232 Lime oerte rre exuere tre E deterior rete vete Ea Eee bee uie orbis 25 Differential Lane Interface nie recti tiere reete rire 25 Multi drop 4 Wire Full Duplex Communications eese nennen nennen 26 Basic 2 Wire Half Duplex Multi drop Connection 27 Termination Resistors in Di2. signaling ComSync PCI 104 RS 422 V 11 Device 2 TX Data RX 14 TX pata RX 16 RX tI pata TX 3 _ ooo pata TX 7 SR SR Figure 9 Basic RS 422 V 11 Asynchronous Connections 19 www connecttech com CTIM 00048 0 00 10 31 2008 800 426 8979 519 836 1291 Connect Tech Inc ComSync PCI 104 User Manual Industrial Strength Communications ComSync PCI 104 RS 422 V 11 Device 2 TX Data RX 14 TX Data RX 16 RX MH Data TX 3 RX Data TX 9 RxC3 Clk TX 17 RxCQ 12 Clk RX 15 TxC RX 7 SR Figure 10 Basic RS 422 V 11 Synchronous Connections NOTE ComSync PCI 104 synchronous clock signals are bidirectional See below ComSync PCI 104 Synchronous Clocking The clocking circuits on the ComSync PCI 104 are very flexible The ComSync PCI 104 DB 25 clock pins are bi directional This means that the TXC or RXC pins can be inputs receiving a clock or outputs driving a clock Functionally the two pins are equal For example the following clocking combinations are possible RXC as clock input and TXC as clock input RXC as clock output and TXC as clock output RXC as clock input and TXC as clock output RXC as clock output and TXC as clock input The ComSync PCI 104 receivers and transmitters can be clocked independently from any combination of the above or from internal clock sources Loopbac
3. SRAM LEN PCIBAR3 512 KByte 0x0007 FFFF PCI Base Address Register 2 PCIBAR2 As previously stated the ComSync PCI 104 s IUSC serial controllers the FPGA control registers and the FPGA status registers are mapped to the PCIBAR2 memory region Table 4 below presents the Offset Address of the internal registers of both IUSCS relative to PCIBAR2 Detailed information about how to configure and control the IUSCs can be found in the Zilog Z16C32 Integrated Universal Serial Controller User s Manual seen at http www zilog com docs serial um0140 pdf Table 4 Memory Map of PCIBAR2 IUSC Registers IUSC Area IUSC 1 JSC 1 Sreg SC 1 Sreg SC 1 Sreg SC 1 Sreg IUSC 1 Sreg SC 1 Sreg IUSC 1 Sreg SC 1 Sreg 136 1 Sreg USC 1 Sreg SC 1 Sreg USC 1 Sreg sc 1 Sreg USC 1 Sreg IUSC 1 Sreg SC 1 Sreg IUSC 1 Sreg R TDR 8 16 bit serial data byte word Writes go to the Transmitter FIFO Reads come from the Receiver FIFO Q ezlgzaazuzossmxmzooog i Ax e ii DR ISR a G G G gt NN E IUSC 1 Sreg 7 www connecttech com CTIM 00048 0 00 10 31 2008 800 426 8979 519 836 1291 ComSync PCI 104 User Manual Ea I I I I I I 0034 0036 0038 003A 003C I U U U U U U U U U U U U U U 003E 00400078 0080 gt 009 IUSC Data FIFOs 32 bytes 0100 SC 1 Sreg S
4. 519 836 1291 Connect Tech Inc ComSync PCI 104 User Manual Industrial Strength Communications Table 6 FPGA Register Detailed Description LEDC Control Bits Read Write only as a 16 Bit word Auto Flash Mode Direct Mode LED 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Control X X X X X X X X X X X X X X X AFM Register NOTE Auto Flash Mode AFM 0 LED automatically flashes every 2 second a system heart beat 1 LED off X Reserved for future use Set to zero for Writes Returns zero on Reads 1004 LIFC 1 Control Bits Read Write only as a 16 Bit word 0007 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Pane X X X X X X X X X X 42W DM SPT SP2 SPI SPO Interface TUSC l Control Basic Line Mode Control bits Register SP 2 0 SP508 Line Mode setting bits See Table 10 for Line Interface Mode settings Power up state 111 SPT SP508 Terminator Enable 0 disable terminator 1 enable terminator Power up State 0 Duplex Control and RTS Pin Control bits DM Duplex Mode selection 0 Full 1 Duplex 42W 4 2 Wire mode selection 022wire Duplex 1 4wire or Multi Drop Slave NOTE See Duplex Modes for complete information on implementation For Future Use X Reserved for future use Set to zero for Writes Returns z
5. SC 1 Dreg z lalag M 9 SC 1 Dreg 2 2 C SC 1 Dreg 2 SC 1 Dreg RENE Connect Tech Inc Industrial Strength Communications 01A0 01A9 IUSC 1 Dreg IUSC 1 Dreg IUSC 1 Dreg 01B001B9 IUSC 1 Dreg IUSC 1 Dreg 01 IUSC 1 Dreg 01C0 01FF 0200 IUSC 1 0202 03FF IUSC 1 IUSC 2 IUSC 2 0400 05FF 0600 IUSC 2 0602 07FF IUSC 2 FPGA Register Descriptions As Above ComSync PCI 104 User Manual Reserved do not access Reserved do not access Reserved do not access Interrupt Acknowledge read only Reserved do not access Same registers as addresses 000 1FF Interrupt Acknowledge read only Reserved do not access Again the ComSync PCI 104 s FPGA control and status registers are mapped to the PCIBAR2 memory region Table 5 below shows the Offset Address of the FPGA registers relative to PCIBAR2 The details of the operation of each bit in the registers is also outlined in the description below FPGA Area 1000 LEDC 1002 1004 LIFC1 1006 pO 1008 LIFC2 104 1012 10141FFF Table 5 Memory Map of PCIBAR FPGA Register Summary E www connecttech com See FPGA Registers for details Alias of 1000 Serial Port 1 Line I F control 16 Bit Read Write Alias of 1004 Serial Port 2 Line I F control 16 Bit Alias of 1010 CTIM 00048 0 00 10 31 2008 800 426 8979
6. The clock structure diagram below must be followed precisely CTIM 00048 0 00 10 31 2008 www connecttech com 16 800 426 8979 519 836 1291 Connect Tech Inc Industrial Strength Communications ComSync PCI 104 User Manual IUSC Device Receiver Logic TXCD Transmitter Logic TxCLK Figure 6 ComSync PCI 104 Diagram of the Clock Integration with the IUSC 17 www connecttech com CTIM 00048 0 00 10 31 2008 800 426 8979 519 836 1291 Connect Tech Inc ComSync PCI 104 User Manual Industrial Strength Communications Software Selectable Line Interface Modes The Serial Line Interface utilizes Sipex devices SP508 Refer to the data sheet seen at http www exar com Common Content ProductDetails aspx ID SP5068 for all electrical characteristics of the interface The Line Interface Mode is software selectable for each channel The following modes are available Table 10 Line Interface Mode Settings Signal Name Pin Line Interface Mode Settings binary values LIFC1 2 SP2 0 EIA EIA X21 RS diss ts 26Pin 25pin 530A 530 Mode 449 yog Shutdown Mode Mode V 11 V 36 i 001 010 011 100 101 110 111 TX 2 14 V 11 11 V 357 v 11 High Z MHigh Z TX TX 3 2 Vl V 11 11 V35P vil v 28 High Z RX 6 16 35 v 11 High Z
7. RTS CTS GND SR EN 4 26 pin header EN NN NN EN M NM NM NN Printed circuit board Top view of DB 25 cable lt 26 pin cable header Arrow pin 1 Red stripe pin 1 Ribbon Cable Female DB 25 Connector NOTE ComSync PCI 104 does not include this cable CBG001 unless it is ordered as part of the SKU ComSync PCI 104 model numbers using a 01 suffix include the CBGO001 cable 23 www connecttech com 800 426 8979 519 836 1291 CTIM 00048 0 00 10 31 2008 Connect Tech Inc ComSync PCI 104 User Manual Industrial Strength Communications Multi drop communications using V 11 RS 422 485 line modes When wiring multi drop RS 485 networks it is necessary to wire the devices in a daisy chain they must not be wired with a star topology see diagram Daisy Chain Topology Correct v i Blue Heat Net 8 485 Device 1 RS 485 Device Star Topology Incorrect X Twisted Pair Cabling p Twisted Pair Cabling x Blue Heat Net RS485 Device 1 RS 485 Device Figure 13 Wiring Diagram for V 11 RS 422 RS 485 Line Modes Asynchronous Communications Tutorial The ComSync PCI 104 features two asynchronous serial communication ports Asynchronous communications is a simple cost effective means of terminal serial communication For this reason it is widely used for communications on personal computers bar c
8. enable the interrupts from the IUSC devices through the FPGA through the PCI Bridge to the PCI bus If the MIE bit is turned OFF MIE 0 the interrupt signals from the IUSC are disabled but the Interrupts Status bits continue to show correct status of the IUSC interrupt bits The power default state of MIE is 0 MIE is disabled IABT IUSC DMA operation Abort Setting this bit will abort any DMA transfer underway and is mainly used to abruptly stop autonomous IUSC Power up default of IABT is 0 IABT not active Interrupt Information Both the IUSC interrupts are logically combined together and are presented to the PCI Bridge to the Local Bus Interrupt pin For Future Use X Reserved for future use Set to zero for Writes Returns zero on Reads 1010 FPGA Read D15 0 Control Bits Read only as a 16 bit word STATUS Only 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X Rev 2 Rev 1 Rev 0 ID 2 ID 1 ID 0 X X X X X X IS 1 IS 0 Status Bits IS 1 0 Interrupt Status IS 0 Port1 IS 1 Port2 ID 3 0 FPGA ID Begins at 1 and increments 3 0 FPGA Revision Begins at 1 and increments For Future Use X Reserved for future use Set to zero for Writes Returns zero on Reads 11 www connecttech com CTIM 00048 0 00 10 31 2008 800 426 8979 519 836 1291 Connect Tech Inc ComSync PCI 104 User Manual Industrial St
9. protocols supported HDLC SDLC MonoSync BiSync Transparent BiSync Async external character sync and others Supports data encoding methods NRZI NRZB NRZI Mark NRZI Space Biphase Space Biphase Mark FM1 Biphase Level Manchester Differential Biphase Baud rates up to 20 Mbps synchronous using special build options 10 Mbps synchronous standard model 230 4 Kbps asynchronous Software selectable internal and external clocking modes External clocking is provided on TxC and RxC pins Operating temperature range of 0 C to 70 RoHS compliant www connecttech com CTIM 00048 0 00 10 31 2008 800 426 8979 519 836 1291 Connect Tech Inc ComSync PCI 104 User Manual Industrial Strength Communications System Overview Based on the PCI bus and a compact form factor ComsSync PCI 104 provides maximum flexibility The ComSync PCI 104 enables users to choose from multiple electrical interfaces protocols and encoding schemes to provide a hardware solution that is ideally suited to each specific application 104 is PCI 104 1 0 compliant Lifetime warranty and free technical support are included The following conceptual block diagram provides a high level overview of the ComSync PCI 104 and illustrates the general interconnection between components and connectors System Control FPGA Figure 1 ComSync PCI 104 Block Diagram CTIM 00048 0 00 10 31 2008
10. www connecttech com 4 800 426 8979 519 836 1291 Connect Tech Inc Industrial Strength Communications ComSync PCI 104 User Manual Rot SW PCI Bus Connector Connector 9 OQ Figure 2 ComSync PCI 104 Board Layout Hardware Installation The following section describes the function of the PCI slot selection rotary dip switch Be sure to establish settings prior to the physical installation of the ComSync PCI 104 adapter in your PCI 104 stack Slot Selection Rotary Switch RSW1 This rotary switch selects a slot position in the PCI 104 stack When installing ComSync PCI 104 in a stack ensure that the rotary switch matches the card position in the stack Table 1 Slot Selection RWSI 5 www connecttech com CTIM 00048 0 00 10 31 2008 800 426 8979 519 836 1291 Connect Tech Inc ComSync PCI 104 User Manual Industrial Strength Communications Software Development Hardware Information This section offers information about how the ComSync PCI 104 on board functions can be accessed through the PCI bus Below are details about the PCI Bridge Configuration Space the PCI Base Address Registers and detailed Memory Maps for each of the decoded Base Address Register regions that allow access to the on board SRAM FPGA control and status registers as well as two Zilog Z16C32 Integrated Universal Serial Controllers IUSCs This information is the framework for software developm
11. C 1 Sreg SC 1 Sreg IUSC 1 Sreg COR I SC 1 Sreg TDR RDR 8 16 bit serial data byte word Writes go to the Transmitter FIFO Reads come from the Receiver 0032 SC 1 Sreg MR 00A0 gt 00FE TUSC 1 Dreg 2 Connect Tech Inc Industrial Strength Communications SC 1 Sreg SC 1 Sreg Aliases of addresses 00 gt 3F 16 bit serial data transfers ONLY Writes go to the Transmitter FIFO Reads come from the Receiver FIFO useful for block data movements Aliases of 080 gt 9F CAR 0102 JSC 1 Dreg DMR 0104 0106 SC 1 Dreg Reserved do not access 0108 SC 1Dreg par 4 0112 0114 SC 1 Dreg 0116 I I I I I I I 011A IUSC 1 Dreg 011C IUSC 1 Dreg I I I I I I I I U U U U U U U U U USC 1 Dreg U U U U U U U U 012A 012C SC 1 Dreg 012 JSC 1 Dreg 013020133 013A 013C JSC 1 Dreg 013E SC 1 Dreg 014020181 0182 0184 gt 019D 019 IUSC 1 Dreg CTIM 00048 0 00 10 31 2008 oon 0118 JSC 1 Dreg 0120250120 5 pg fT Reserved do not access Reserved do not access Reserved do not access Reserved do not access Reserved do not access www connecttech com 800 426 8979 519 836 1291 SC 1 Dreg AO Zw ZZ dl AA 217 2 2 ua Siola EE EE 858 j Jj i Alo Z wn 4 z
12. Connect Tech Inc Industrial Strength Communications USER MANUAL ComSync PCI 104 CTIM 00048 0 00 October 31 2008 Connect Tech Inc 800 426 8979 519 836 1291 ComSync PCI 104 User Manual Industrial Strength Communications Table of Contents EE XO CRT 2 Hoineet itor REC D c E 3 tnc me 3 SYSTEM OVERVIEW e HER 4 Hardware Installations RES 5 Slot Selection Rotary Switch nne en nennen en nnne tentent nennen nne 5 Software ER TER ET 6 Hardware IntormatiOn RH 6 PCI Configuration 5 P 6 Decoded Address 7 PCI Base Address Register 2 2 7 FPGA Register Descriptions cererii acean 9 PCI Base Address Register 3 12 Sp d E E A E E E 12 IntetTUDIs 12 System Block de 13 D plex 15 TUSC CONTO liee neee e 16 Software Selectable Line Interface 4
13. High Z RX RX 5 3 v i v 35 v 11 v 28 High Z DTR 20 23 High Z 1 High Z High Z High Z DTR DTR 14 20 V 10 V 11 V 11 v 28 V ll V 28 High Z RTS 12 19 VAI V 11 V 11 High Z High Z High Z RTS RTS 7 4 V 11 V 11 VAI 28 V 11 V28 High Z CTS 25 13 VAI Vl 1 High Z V 11 High Z High Z CTS CTS 9 5 V 11 V 11 VAI 28 V ll V28 High Z DSR 18 DD High Z V 11 VI High Z V 11 High Z High Z DSR DSR 11 6 V 10 V 11 VAI 28 11 V28 High Z DCD 19 10 11 Vl 1 High Z V 11 High Z High Z CD 15 8 V 11 V 11 11 28 V 11 V28 High Z 17 9 v 35 v 11 High Z High Z RxC RxC 8 17 v i v 35 v11 v 28 High Z RXSYNCO 21 11 V 11 V 11 1 High Z V 11 High Z High Z RXSYNCO 22 24 11 Vl V 11 28 V 28 High Z 23 12 V 11 V 11 1 V 35P 9 V 11 High Z High Z TxC TxC 4 15 V 11 11 1 352 v 11 v 28 High Z RI RXREQ 24 25 V 10 v 10 High 2 V28 10 V28 High Z GND 1 13 1 7 GND GND GND GND GND GND GND Pl 35 Termination Network is applied between the d signals Notes 3 anid signals When signal is an input V 10 RS 423 single ended 5 0V max 9450 Q 11 RS 422 differential 1 5 to 4 5 max 100 Q 28 RS 232 single ended 12 0V max 35 35 differential 550 mV R network Gr
14. Industrial Strength Communications TX ENA I 0 Data and Clock Enables ENA I 0 From FPGA 7 TxC ENA I 0 IUSC Z16C32 RxC ENA I 0 x2 T TX 2 TX L 0 2 2 TX 2 RX 1 0 NE T RX E s 2 TxC I1 0 aa TxC Bi directional Clocks L 2 RxC 1 0 2 Hy nc TO DB25 x2 2 CTS 2 CTS CTS Fist Setup Port3 N C Port6 Fsyne N C 2 2 IDCD DCD DCD pee NC DCD TxTSA RTS Port4 N C 2 TxComp Port7 Zep 2 MODE From FPGA LIFC Registers lt lt Latch 2 2 RURXREQ RXREQ 2 DSR TxReqt 2 xReq TXREQ DSR TxReq 2 gt DTR 2 d ros EE Porto 2 18 432MHz 2 Figure 4 ComSync PCI 104 IUSC to Line Driver Connection Diagram SP508 x 2 CTIM 00048 0 00 10 31 2008 www connecttech com 800 426 8979 519 836 1291 14 Connect Tech Inc Industrial Strength Communications ComSync PCI 104 User Manual Duplex Modes ComSync PCI 104 gives the user the ability to enable or disable the transmission and reception of data The data transmission and reception enable is controlled through an interaction between the function of each IUSC Port 7 pin and register assignments in the FPGA Both IUSC Port 7 pins are connected to the SP508 line driver of each channel through logic on the FPGA The Port 7 pin is one of eight pins on each IUSC which can be assigned to perform a specific function or become a gen
15. abelled with a The differential communication refers to the as Tx and the as Tx Any noise injected into the wires is cancelled at the receiver leaving only the original undistorted data signal Twisted pair cables are always used in RS 485 this ensures that the communications are robust and as error free as possible RS 485 signal levels are between 0 and 5 Volts the differential voltage can be as little as 200mV Differential can operate in three different modes a 4 wire full duplex interface 4 wire multi drop full duplex interface and a 2 wire half duplex interface A full duplex bi directional differential communication interface requires at least four wires two for transmit and two for receive A half duplex interface only requires two wires this provides a cost effective cabling solution Multi drop is a great feature of RS 485 Multiple RS 485 devices can be bussed together in a daisy chain type fashion to create a network Up to 32 devices may be connected together on the same network In multi drop networks one of the devices usually the computer is designated as the master and all other devices are designated as slaves All communication is initiated by the master The master and slave designations are established by your communications application 25 www connecttech com CTIM 00048 0 00 10 31 2008 800 426 8979 519 836 1291 Connect Tech Inc Industrial Strength Communications ComSync PCI 104 U
16. ansmitting This feature is managed by the ComSync PCI 104 and is fully transparent to your application For example in a multi drop network the differential transmitter is enabled prior to the master initiating transmission When transmission is complete the transmitter is placed in high impedance mode Each slave will receive that transmission from the master A protocol must be in place to address or select the desired slave device however that discussion is beyond the scope of this tutorial and is entirely application dependent When the slave device has received the data it will respond by enabling its transmitter and transmitting data onto the bus and then placing its transmitter into high impedance mode just as the master did 27 www connecttech com CTIM 00048 0 00 10 31 2008 800 426 8979 519 836 1291 Connect Tech Inc ComSync PCI 104 User Manual Industrial Strength Communications Termination Resistors in Differential Networks Differential networks often benefit from the installation of termination resistors Termination is rarely required for lower baud rates for example 9 6 Kbps or less However differential networks are transmission lines and can suffer from the electrical effects of ringing or undershoot and overshoot all of which can cause data errors especially at higher baud rates like 115 2 Kbps Termination resistors should always be installed at the extreme ends of the network as close to the differential trans
17. ceiver circuits as possible as outlined in the diagram below ComSync PCI 104 Master RS 485 Slave Device 1 Termination Resistor sf RXD lt amp TXD cH De Enable e Enable HN TXD gt RXD gt es e e e RS 485 Slave Devicen A e TXD E Enable 1 d Figure 18 Termination Resistors in Differential Networks NOTE The ComSync PCI 104 features software selectable termination CTIM 00048 0 00 10 31 2008 www connecttech com 28 800 426 8979 519 836 1291 Connect Tech Inc Industrial Strength Communications ComSync PCI 104 User Manual Limited Lifetime Warranty Connect Tech Inc provides a Lifetime Warranty for all Connect Tech Inc products Should this product in Connect Tech Inc s opinion fail to be in good working order during the warranty period Connect Tech Inc will at its option repair or replace this product at no charge provided that the product has not been subjected to abuse misuse accident disaster or non Connect Tech Inc authorized modification or repair You may obtain warranty service by delivering this product to an authorized Connect Tech Inc business partner or to Connect Tech Inc along with proof of purchase Product returned to Connect Tech Inc must be pre authorized by Connect Tech Inc with an RMA Return Material Authorization number marked on the outside of the packa
18. day to Friday Facsimile 519 836 4878 online 24 hours Email Internet You may contact us through the Internet Our email and URL addresses are sales connecttech com support connecttech com www connecttech com Mail Courier You may contact us by letter and our mailing address for correspondence is Connect Tech Inc Technical Support 42 Arrow Road Guelph Ontario Canada N1K 1S6 Note Please go to the Download Zone or the Knowledge Database in the Support Center on the Connect Tech website for product manuals installation guides device driver software and technical tips Submit your technical support questions to our customer support engineers via the Support Center on the Connect Tech website CTIM 00048 0 00 10 31 2008 www connecttech com 30 800 426 8979 519 836 1291
19. e SRAM Please contact Connect Tech Inc at support connecttech com for more information on available resources example code and configuration files for ComSync PCI 104 Interrupts The two IUSC interrupt outputs are connected to the FPGA Inside the FPGA the interrupts are logically combined controlled by an MIE register control bit Master Interrupt Enable routed through to the PCI Bridge local bus interrupt input and appear a single PCI Interrupt on the INTA signal of the PCI Bus The FPGA CONTROL register MIE bit can mask the interrupts it may enable these IUSC interrupts to be passed through the FPGA to the host The host will then read the status registers of the IUSC to determine the source of the interrupt CTIM 00048 0 00 10 31 2008 www connecttech com 12 800 426 8979 519 836 1291 Connect Tech Inc Industrial Strength Communications ComSync PCI 104 User Manual Table 8 ComSync PCI 104 Interrupts Interrupt request output of the IUSCs combined and connected to ComSync PCI 104 PCI Interrupt Clock Buffer System Block Diagrams OSC 33 33 Mhz ComSync PCI 104 Local Bus ZILOG Z16C32 FPGA REGISTERS and CONTROL LOGIC X16 I O 15 0 ADI7 0 WE CE BHE BLE OE SRAM 256K x 16 Figure 3 ComSync PCI 104 FPGA Connection Diagram 13 www connecttech com CTIM 00048 0 00 10 31 2008 800 426 8979 519 836 1291 Connect Tech Inc ComSync PCI 104 User Manual
20. eater than 100 Q termination resistor is applied between the and signals CTIM 00048 0 00 10 31 2008 www connecttech com 18 800 426 8979 519 836 1291 Connect Tech Inc Industrial Strength Communications ComSync PCI 104 User Manual Table 11 Signal Description RS 423 Single ended 5VDC RS 422 RS485 Differential 1 5VDC to 4 5VDC RS 232 Single ended 12VDC V 35 Differential 550mVDC Connecting Serial Devices V 28 Connections V 28 has signaling levels compatible with EIA RS 232 The Signal Reference SR pin must always be connected This pin provides the ground return path for all signaling Basic Asynchronous V 28 RS 232 The figure below illustrates the typical way to connect the ComSync PCI 104 to a serial device ComSync PCI 104 RS 232 Device 2 TX M 3 RX S 7 SR mn Figure 7 Basic V 28 Asynchronous Connections ComSync PCI 104 RS 232 Device 2 TX 3 RX 6__ _ TX Txe RC 17 RxC TxC 7 SR SR Figure 8 Basic V 28 Synchronous Connections RS 422 V 11 Connections The following basic connections are achieved when the I O levels are in V 11 RS 422 mode V 11 mode signaling can be enabled with 530 RS 449 or X 21 modes on your ComSync PCI 104 The Signal Reference SR pin should always be connected This pin provides the ground return path for all
21. ent PCI Configuration Space Accessibility to the on board functions of the ComSync PCI 104 is available via the PLX 9054 PCI Bridge This PCI Bridge accesses the on board functions by mapping them to different PCI Base Address Registers PCIBARn The contents of the PCI Bridge s 256 Byte PCI Configuration Space and the location of the on board functions as decoded by the PCI Base Address registers is illustrated in Table 2 The SRAM is accessible to both the host through the PCI Bridge and the two IUSCs This accessibility is the mechanism for running the two IUSCs in DMA mode The details of the operation of each of the registers are listed below Table 2 PCI Bridge Configuration Space Description I O Mapped Configuration Register IUSC and FPGA Register Access SRAM Access PCI Base Address Space 5 PCIBARS Cardbus CIS Pointer INE mum CTIM 00048 0 00 10 31 2008 www connecttech com 6 800 426 8979 519 836 1291 Connect Tech Inc Industrial Strength Communications ComSync PCI 104 User Manual The ComSync PCI 104 has both IUSCs and FPGA control and status registers all mapped into the PCIBAR2 memory region The on board SRAM is mapped into PCIBAR3 Table 3 below indicates the size and function of the memory regions decoded by the different PCI Base Address Registers Decoded Address Map Table 3 PCI Bridge Base Address Registers Bi IUSC and FPGA PCIBAR2 8Kbye Kbyte 0x0000 1FFF internal registers
22. eral purpose input output general discussion of the implementation of all the port pins can be found in Zilog Z16C32 Integrated Universal Serial Controller User s Manual section 4 12 seen at http www zilog com docs serial um0140 pdf Port 7 s specific function is the Tx Complete signal which is suitable for controlling the enable of a line driver More information about this function can be found in Zilog Z16C32 Integrated Universal Serial Controller User s Manual section 4 10 The ComSync PCI 104 has adopted the IUSC Port 7 pin to act as the RTS signal which can be manipulated directly by software or autonomously by the IUSC In conjunction with several control bits in the FPGA LIFCx bits 4 and 5 several different duplex modes can be implemented Figure 5 and Table 9 below describe the interaction of the IUSC Port 7and the logic within the FPGA that controls the SP508 TX and RX enable RTS TxCOMP PORT7 2 RTS TxComp PORT7 T IUSC Z16C32 1 0 x2 Header 1 T 1 r 1 1 1 Eza 4Wire 2Wire Duplex HALF Full LIFC 5 LIFC 4 FPGA Registers Figure 5 ComSync PCI 104 SP508 TX RX Driver Enable Diagram SIPEX SP508 X 15 www connecttech com CTIM 00048 0 00 10 31 2008 800 426 8979 519 836 1291 Connect Tech Inc ComSync PCI 104 User Manual Industrial Strength Communications Table 9 ComSync PCI 104 SP508 TX RX Driver Enable MODE spur RD _ 7 po
23. eros on Reads 1008 LIFC 2 Control Bits Read Write only as a 16 Bit word 15 14 13 12 11 10 9 8 7 6 3 4 3 2 1 0 Line 0007 Interface X X X X X X X X X X 42W DM SPT SP2 SPI SPO IUSC Basic Line Mode Control bits SP 2 0 SP508 Line Mode setting bits See Table 10 for Line Interface Mode settings Power up state 111 SPT SP508 Terminator Enable 0 disable terminator 1 enable terminator Power up State 0 Duplex Control and RTS Pin Control bits DM Duplex Mode selection 0 Full 1 Duplex 42W 4 2 Wire mode selection 022wire Duplex 1 4wire or Multi Drop Slave NOTE See Duplex Modes for complete information on implementation Duplex Modes For Future Use X Reserved for future use Set to zero for Writes Returns zero on Reads CTIM 00048 0 00 10 31 2008 www connecttech com 10 800 426 8979 519 836 1291 Connect Tech Inc Industrial Strength Communications ComSync PCI 104 User Manual 100C FPGA R W D15 0 Control Bits Read Write only as a 16 Bit word CNTRL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000 X X X X X X X X X X IABT MIE X X SR 1 SR 0 Control Bits SR 1 0 TUSC Software Reset SR 0 Port1 SR 1 Port2 Reset of the respective IUSC is asserted while bit is set to 1 Also the Line Interface Control bits for the given Port are set back to their power up state Power up default of SR 1 0 is 0 MIE Master Interrupt Enable This bit will
24. fferential Networks eee ener enne nennen enne nennen 28 Limited AVEC N 29 ev pirhidicc a 29 Trademark Acknowledgement sisisi sresti doreir sin sees 29 Customer Support iuil c PH 30 Contact Information 4 ee ree entes mereri cetero De EROR REOR 30 CTIM 00048 0 00 10 31 2008 www connecttech com 2 Connect Tech Inc Industrial Strength Communications ComSync PCI 104 User Manual Introduction Connect Tech s ComSync PCI 104 is a two channel synchronous asynchronous serial adapter card designed for PCI 104 bus systems Multi protocol ComSync PCI 104 offers high performance and reliable communications for industrial and embedded applications ComSync PCI 104 utilizes the features and functionality of the Zilog Z16C32 Integrated Universal Serial Controller along with a simple register structure to provide users with full featured synchronous asynchronous communications Features PCI 104 form factor Universal PCI 2 2 bus 33MHz 32 bit PCI interface Two software selectable synchronous asynchronous serial ports Supports two software programmable PCI Bus DMA Direct Memory Access channels to on board 512KB SRAM Seven software selectable electrical interfaces RS 232 V 28 RS 422 485 RS 449 V 36 EIA 530 EIA 530 A V 35 and X 21 V 11 Multiple communication
25. ge and sent prepaid insured and packaged for safe shipment Connect Tech Inc will return this product by prepaid shipment service The Connect Tech Inc lifetime warranty is defined as the serviceable life of the product This is defined as the period during which all components are available Should the product prove to be irreparable Connect Tech Inc reserves the right to substitute an equivalent product if available or to retract lifetime warranty if no replacement is available The above warranty is the only warranty authorized by Connect Tech Inc Under no circumstances will Connect Tech Inc be liable in any way for any damages including any lost profits lost savings or other incidental or consequential damages arising out of the use of or inability to use such product Copyright Notice The information contained in this document is subject to change without notice Connect Tech Inc shall not be liable for errors contained herein or for incidental consequential damages in connection with the furnishing performance or use of this material This document contains proprietary information that is protected by copyright rights are reserved No part of this document may be photocopied reproduced or translated to another language without the prior written consent of Connect Tech Inc Copyright O 2008 by Connect Tech Inc Trademark Acknowledgement Connect Tech Inc acknowledges all trademarks registered trademarks and or copyri
26. ghts referred to in this document as the property of their respective owners Not listing all possible trademarks or copyright acknowledgments does not constitute a lack of acknowledgment to the rightful owners of the trademarks and copyrights mentioned in this document 29 www connecttech com CTIM 00048 0 00 10 31 2008 800 426 8979 519 836 1291 Connect Tech Inc ComSync PCI 104 User Manual Industrial Strength Communications Customer Support Overview If you experience difficulties after reading the manual and or using the product contact the Connect Tech reseller from which you purchased the product In most cases the reseller can help you with product installation and difficulties In the event that the reseller is unable to resolve your problem our highly qualified support staff can assist you Our support section is available 24 hours a day seven days a week on our website at www connecttech com sub support support asp See the contact information section below for more information on how to contact us directly Our technical support is always free Contact Information We offer three ways for you to contact us Telephone Facsimile Technical Support representatives are ready to answer your call Monday through Friday from 8 30 a m to 5 00 p m Eastern Standard Time Our numbers for calls are Telephone 800 426 8979 North America only Telephone 519 836 1291 Live assistance available 8 30 a m to 5 00 p m EST Mon
27. k Connectors Loopback connectors are useful for performing diagnostics Figure 11 and Figure 12 illustrate the recommended pinouts for creating loopback connectors for ComSync PCI 104 DB 25 Male 2 TX 3 RX 4 RTS 5 CTS 6 DSR 8 DCD 20 DTR 17 RXC Figure 11 Recommended Pinouts for V 28 RS 232 Loopback Connector CTIM 00048 0 00 10 31 2008 www connecttech com 20 800 426 8979 519 836 1291 Connect Tech Inc Industrial Strength Communications ComSync PCI 104 User Manual DB 25 Male 2 TX 14 16 RX 3 RX 9 RXC 17 RXC 12 TXC 15 TXC 7 SR Figure 12 Recommended Pinouts for a V 11 RS 422 Loopback Connector NOTES 1 For an asynchronous loopback omit the TXC and RXC pins 2 When using clock signals one signal must be configured as an input while the other must be configured as an output 3 When using a DB 25 female loopback connector solder cup DB 25 connectors and 24 AWG solid core wire such as wire from a CATS cable is recommended Connector Pinouts 21 PCI 104 Header P1 Refer to PCI 104 specifications at http www pc104 org NOTE P1 must be connected to a PCI 104 stack supplying 5V only or both 5V and 3 3V The ComSync PCI 104 is not able to operate in a 3 3V only PCI 104 stack www connecttech com CTIM 00048 0 00 10 31 2008 800 426 8979 519 836 1291 Connect Tech Inc ComSync PCI 104 User Manual Industrial Strength Communication
28. mSync PCI 104 has RS 232 signal levels with a typical range of 8 Volts The maximum cable length you can use with RS 232 is dependant on a number of factors including Baud Rate The faster the baud rate the shorter the cable length must be Cable Quality Quality refers to the capacitance of the cable A higher capacitance usually specified as pF or pico Farads per foot dictates a lower baud rate and a shorter maximum length Low capacitance computer cables for RS 232 applications are available from all wire and cable suppliers Operation is usually possible with cable lengths of up to 100 feet 30 m at baud rates up to 115 2 Kbps using low capacitance cable For higher baud rates such as 230 4 Kbps and up we recommend keeping the cable lengths to within 25 feet 7 6 m The TIA EIA232 specification specifies a DB 25 connectors This connector has a standardized pinout as seen in Table 12 Differential Line Interface RS 485 or 4 85 is a differential line interface standard capable of high baud rates over long cables RS 485 is fully compatible with RS 422 which is considered a subset of RS 485 The use of differential transmitters and receivers ensures RS 485 communications are reliable and robust This means two wires are used to transmit or receive a signal One wire carries the true or non inverted signal the other wire carries the inverted signal The non inverted signal is labelled with a and the inverted is l
29. odes readers printers terminals and much more In asynchronous serial communication the electrical interface is held in the idle position between characters also referred to as mark A change in signal level known as space level indicates the start of transmission of a character The receiver recognizes this change as a start bit Once the start bit has been sent the transmitter sends the actual data bits In typical asynchronous communications there may be 5 6 7 or 8 data bits depending on the application Both the receiver and the transmitter must be set to the same number of data bits baud rate and stop bits Stop bits can be 1 1 5 or 2 bit periods in length When the transmitter has sent all the data bits it sends a stop bit This stop bit signals to the receiver that the data has finished transmission The stop bit is the same state as the idle or mark state O111213 1415 16 17 Start Bit Data Bits Stop Bit Figure 14 Typical Asynchronous Date Frame CTIM 00048 0 00 10 31 2008 www connecttech com 24 800 426 8979 519 836 1291 Connect Tech Inc Industrial Strength Communications ComSync PCI 104 User Manual Serial Line Interface Tutorial RS 232 Line Interface RS 232 is the simplest least expensive line interface standard It is also referred to as EIA232 and TIA EIA 232 The RS 232 specification signals levels of 3V to 15V for a logic 0 or Space and 3V to 15V fora logic 1 or Mark The Co
30. rength Communications PCI Base Address Register 3 PCIBAR3 The ComSync PCI 104 has mapped the on board SRAM to the PCIBAR3 memory region Table 7 below presents the locations in PCI memory at which the on board SRAM appears The SRAM is used when the IUSCs run in DMA mode The SRAM can be accessed by 8 16 or 32 bit read or write operations Table 7 Memory Map of PCIBAR3 SRAM Memory SRAM Area 512 Kbyte 0 0000 SRAM data 0 0001 0 0002 0 0004 0 0005 0 0006 0 0007 SRAM data 0 0003 E 7 FFFF SRAM dua DMA Support To allow for fast continuous data reception and transmission the ComSync PCI 104 supports four DMA channels where each of the two IUSCs has a Transmit and a Receive channel By writing configuration data to the IUSC registers listed in Table 4 and by carefully following the Zilog Z16C32 Integrated Universal Serial Controller User s Manual seen at http www zilog com docs serial um0140 pdf both IUSCs can be set up to perform automated data transmission and reception using DMA through ComSync PCI 104 s on board SRAM The host can configure the IUSCS to run in one of four DMA modes Single Buffer Pipelined Array or Linked List Once the IUSCs are setup and started data can be placed into the assigned area in SRAM memory to be transmitted or received data can be removed from the SRAM by the host software The host must respond to interrupts or poll the IUSCS to detect when data has been received to th
31. rt uro uc s 0 o f 1 1 0 Disabled 1 3 0 dme ctive Active 12 Duplex ee 1 1 1 IUSC Clock Control The ComSync PCI 104 s implementation of the Zilog Z16C32 clocking system is extremely flexible This flexibility adds complexity to the set up of the clocking system A diagram of the ComSync PCI 104 s clock system and how it is integrated with the IUSC is displayed below The user has the option of receiving a system clock on RxC or TxC or driving out a system clock on TxC or RxC By writing the appropriate register in the IUSC the line driver SP508 clock direction selection is automatically controlled by the FPGA The user has the option of using the on board 18 432MHz clock as the source or the externally received clock to drive the IUSC data structure The user also has the option of dividing the clock frequency down using the features of the IUSC Users are strongly advised to refer to the Z16C32 Integrated Universal Serial Controller User s Manual seen at http www zilog com docs serial um0140 pdf section 4 3 Transmit and Receive Clocking Users must correctly configure the following IUSC registers CMCR CCSR HCR TCOR TCIR and IOCR to configure the clock Great care must be used when assigning values to these registers or unexpected operation may be the result
32. s Appendix ComSync PCI 104 Specifications Operating Environment 0 C to 70 C 32 F to 158 F Communications Synchronous Up to 18 432 Mbps with internal clock reference up to 20Mbps with external clock reference Asynchronous 230 4 Kbps Custom baud rates are also available Please contact sales connecttech com for more information ESD Protection 15kV Power 5V 1 0 A maximum V 35 530 or 530A synchronous mode at maximum clock rate 5V 700 mA or less typical X 21 V 28 Connectors Two 26 pin dual row headers 0 100 pitch Cables for serial I O DB 25 Female Dimensions Compliant with PCI 104 specification 1 0 Cable Options If required cabling options are available for the ComSync PCI 104 CB001 1 26 pin Header 1 x DB 25 Female NOTE One CBG001 is required per port on the ComSync PCI 104 As model options for the ComSync PCI 104 continue to grow cabling options may grow as well Please contact sales 9 connnecttech com for the most recent list of cables CTIM 00048 0 00 10 31 2008 www connecttech com 22 800 426 8979 519 836 1291 Connect Tech Inc Industrial Strength Communications I O Connect Pin Assignments DA GND SR TX TXC RX RTS RXC Table 12 Pin Assignments for Cable Part Number CBG001 ComSync PCI 104 User Manual DTR DCD RxSYNC IN RXC DSR DCD RxS YNC_IN DTR RxSYNC_OUT CTS RxSYNC OUT TXC DSR RI
33. ser Manual ComSync PCI 104 RS 485 Device E 4 RXD TXD a K TXD RXD sale Figure 15 Basic 4 Wire Full Duplex Communications Signal Ground In a 4 wire RS 485 network two devices are connected together For example a ComSync PCI 104 RS 485 port and an RS 485 device may be connected Multi drop 4 Wire Full Duplex Communications In a multi drop 4 wire differential network two to 32 devices are connected together Note that each RS 485 receiver counts as a device or load In this multi drop mode of communication a master slave protocol must be enforced that is all communication is initiated by the master in this case a ComSync PCI 104 The communication is full duplex meaning that receive and transmit traffic occur on different pairs of wires The ComSync PCI 104 can receive and transmit data from to a device at the same time ComSync PCI 104 Master RS 485 Slave Device 1 RXD TXD z Enable Enable TXD RXD e e RS 485 Slave Device n TXD Enable T RXD Figure 16 Multi drop 4 Wire Full Duplex Communications CTIM 00048 0 00 10 31 2008 www connecttech com 26 800 426 8979 519 836 1291 Connect Tech Inc Industrial Strength Communications ComSync PCI 104 User Manual Basic 2 Wire Half Duplex Multi drop Connection In a 2 wire differential net
34. work two to 32 devices are connected together Note that each receiver counts as a device or load In this multi drop mode of communication a master slave protocol must be enforced that is all communication is initiated by the master in this case a ComSync PCI 104 The communication is half duplex meaning that receive and transmit traffic occur on the same wire The ComSync PCI 104 and devices cannot receive and transmit data at the same time Note that the Receiver and the Transmitter signals are connected together This is performed at the DB 9 connectors All communication between devices occurs over a single pair of wires this can lower the cost of wiring your network ComSync PCI 104 RS 485 Device 1 A 4 RXD TXD O 1 Enable o Enable A A TXD E gt RAD LO j e e e RS 485 Devicen Figure 17 Bus Contention on Differential Multi drop Networks Bus contention occurs when two or more devices enabled on a bus attempt to run the bus to opposite logic values From the diagram above we can see that there are multiple differential transmitters TXD on the bus To avoid the bus contention problem the differential transmitter features a tri state or high impedance mode controlled by an input pin enable Software and hardware in the ComSync PCI 104 and the differential devices will always place the transmitter into high impedance mode when not tr
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