Creating AXI-LITE `Custom IP` in Vivado
Contents
1. set_property IOSTANDARD LVCMOS33 get_ports sw_in 0O set_property PACKAGE _PIN M15 get_ports sw_in 7 set_property PACKAGE _PIN H17 get_ports sw_in 6 set_property PACKAGE _PIN H18 get_ports sw_in 5 set_property PACKAGE_PIN H19 get_ports sw_in 4 set_property PACKAGE_PIN F21 get_ports sw_in 3 set_property PACKAGE _PIN H22 get_ports sw_in 2 set_property PACKAGE_PIN G22 get_ports sw_in 1 set_property PACKAGE_PIN F22 get_ports sw_in O 322. 131 latehed raddr lt axi araddr Figure 4 5 Exposing the written values and latched addresses within labO_ip_v1_O_SO0O_AXI vhd To ensure that the Toplevel can access the signals introduced above the port definition of the Slave_AXI component needs to be modified as shown in Figure 4 6 14 HERE oe 5 AXI RVALID out std logic 1 c b Read ready This signal indicates that the master can accept the read data and response information DEE i S AXI RREADY in std logic 4 DATA WIDTH 1 downto 0 5 _DATA WIDTH 1 downto 0 Co co Gi ADDR WIDTH 1 downto 1 6 oo co Figure 4 6 Required signal additions to the Slave _AXI entity declaration 4 b ii Changes to Toplevel There are two ways that one can utilise the values from the processor e The first approach is to use registers which will be accessed independently by both the AXI bus and the underlying peripheral The peripheral need not know exactly when a read or write operation has taken place e The second approach is to handle AXI communication in real time One can effectively snoop the AXI bus lines and be reactive to communication from the master as it occurs An example would be an address which always reads O but when written with any value a state transition occurs within the peripheral The data in either case has no tangible value We ll come back to these ideas in the Section 6 but for now we ll stick to some s
3. Processor 12 4 b Customising the Custom IP Based on the tutorial on the AXI protocol in the previous subsection it should be clear that AXI signals can be used by the hardware designer to determine whether or not a read or write has been requested by the Master There are a few files and naming conventions to take note of before we begin to modify the IP e Slave_AXI labO_ip v1 0 SOO AXI vhd a generated file which implements the AXI LITE handshaking process and stores all writes to local registers These same registers are currently configured to also be used for read values e Toplevel labO_ip v1 _0 vhd refers to the VHDL file that encapsulates the Slave _AXI file described above You ll notice that it is largely empty This is where we will be focussing our implementation efforts When coding your own designs it is recommended that you use this file only as a connection point between your VHDL components Given that this is a relatively short lab we will code entirely within this file for convenience Figure 4 3 below shows the overall organization of our design The high level project encapsulates the Zynq the AXI Interconnect and your Custom IP block The source for your custom IP block resides in an independent project and contains the files mentioned above The green arrows in Figure 4 3 denotes the changes we will be making to expose some of the internal signals of the Slave_AxXI file into the Toplevel where we can then des
4. addr is 363 J EE when b 00 gt ee reg data out lt datainO slv_reg0d ee when b 01 gt eS reg data out dataini slv_ regi a when b 10 gt J i reg data out lt datain slv_ reg Be ee when b 11 gt SIO f i ee eb reg data out datain3 slyv_ regs SE when others gt ee reg data out lt others gt O se end case ee end if 375 end process Figure 4 4 Changes to AXI read data within labO_ip_v1_0_S00_AXI vhd Now that we have taken care of the output values we next need to expose the data that the master writes to this Slave so that their values can be used by the Toplevel In this case instead of modifying the Slave logic we simply map the local signals named s v_reg to external signals named dataout Recall from the timing figures in Sections 4 a i and 4 a ii that the address bus value is only valid for a very short amount of time The axi_awaddr and axi_araddr registers are used in the generated code as latches to ensure that their values are persistent for the duration of a transaction These signals will also need to be made available to the Toplevel The changes that need to be made are shown in Figure 4 5 174 begin 125 I O Connections assignments 126 o dateaoutd lt sly regoO 127 dataoutl lt sly regi 128 o dataout2 lt sly reg2 129 o dataout3 lt sly reg3 130 latched waddr lt axi awaddr
5. on the request When connection automation was run on your Custom AXI IP Vivado inserted a Xilinx AXI Interconnect between the Master and your Slave IP See the Xilinx AXI Interconnect documentation 3 The Interconnect provides a layer of abstraction that prevents a Slave from receiving any signal unless the significant bits of the address match the assigned address range of the Slave This is achieved by multiplexers and internally embedded routing data and explains why the observable address width of your Slave IP may not match the width of the bus The downside of this abstraction layer is the introduction of some delay which will be seen in the timing diagrams in the following subsections 10 4 a 1 AXI Writes SSS ee Name Value u M system _i timer 31 0 MA system _i processing_system _0_ayi_periph MOO_AXI_WDATA 31 0 o system_i processing_system _0_axi_periph_MOO_AXI_WVALID lh system i processing system _0_axi_periph MOO AXT_AWVALID lh system _i processing system7_0 axi_periph MOO_AXI AWREADY lik system_i processing system _0_axi_periph MOO _AXI_WREADY Figure 4 1 Debug output for AXI write transactions The waveforms in Figure 4 1 show the Master writing OxFFFFFFFF BASE_ADDR 0x0 then 0x00000001 BASE_ADDR 0x0 and finally OxOO00000a BASE _ADDR 4 0x4 Note that the signals are prefixed with MOO_AXI Master AXI instead of SOO AXI Slave AXI This is because the net was assigned a label by arb
6. possible Section 5 Shows you how to package and upgrade your IP Sample software will be presented in order to test the modifications that were made to your hardware Section6 The penultimate section of this documentation consists of a series of implementation exercises These exercises are designed to get you comfortable with developing custom IP and to familiarise you with alternative ways of interfacing via the AXI bus Section 7 Concludes this lab by listing methods of going forward and developing your own hardware based solutions By the end of this lab you should be able to generate your own IP quickly implement hardware solutions and effectively utilise the AXI bus to transfer data between the PS and the PL You ll also become proficient in the hardware design flow within the Vivado framework and learn methods of debugging for producing hardware solutions as effortlessly as possible Assumed knowledge precursors for this tutorial include e VHDL coding ability e Read through Zedboard Getting Started Guide e Completed the Advanced Embedded Design courses to familiarise yourself with Vivado minimum lab 1 and 2 2 High level design configuration The first step in this lab is to use Vivado to configure a high level design that features a ZynQ7 processing core For detailed instructions on the Vivado design flow please refer to Lab1 of the Xilinx Advanced Embedded Design course As we progress through this lab we will create c
7. your IP by dicking the button at the bottom of this pane This panel provides you with an overview and status of your IP and suggests possible missing information b F Summary of your IP E IP root directory c Users Shivam Desktop comp4601 lab0_ip_1 0 labO_ip_1 0 xilinx com user labO_ip 1 0 __ C for starting lab a 3 4 visible parameters for customization edit 4 21 ports on your IP 3 3 interfaces on your IP settings After Packaging Cay TF will be made available in the catalog using the repository c Users Shivam Desktop comp4601 lab0_ip_1 0 ay IP Packager window will dose upon successful completion a An archive will not be generated Use the settings link above to change your preference Figure 5 6 Step 5 6 finalising the packaging process 19 Screens that were skipped e IP compatibility is used to list the valid target boards for the IP It should always include the ZYNQ board for our designs e IP Customisation Parameters should be used if the customisation parameters generic parameters for the IP have been changed e IP interfaces This screen is used to match or create a standardised interface port by grouping signals e g a FIFO_WRITE port for interfacing with a Xilinx FIFO instance e IP Addressing and Memory Informational only e IP Licencing and Security Informational only 5 b IP upgrade in high level design Within the high level Vivado project 5 7 Reopen th
8. 7 Opening the Slave AXI file Now that we have a suitable development environment now in place we can begin to develop our AXI peripheral In the following sections of this manual we will extend the operation of our new IP and repackage it so that we can upgrade the instantiated component in the high level module 4 Customising the Custom IP This section provides an AXI LITE interface tutorial and will walk you through customising the Slave AXI file that was generated in Section 3 You will modify the Custom IP component to set the stage for extending the generated skeleton implementation 4 a AXI Tutorial The Advanced extensible Interface AXI bus protocol was developed by ARM to control access to a shared bus Some of the key features of this protocol are as follows e Independent address control and data lines e Simple handshaking due to the independent control lines e Burst mode transfer support with the provision of only a starting address e Uses a Master Slave model with the Master being solely responsible for the arbitration of the bus directing writes and requesting reads from the Slave This section is limited to an overview of the AXI protocol For more information see the AXI Reference Guide 2 The Master accesses a connected Slave by first applying an appropriate address on the address bus Each Slave then determines if the provided address lies within its assigned addressable range before either ignoring or acting
9. Creating AXI LITE Custom IP in Vivado Lab for COMP4601 Developed by Shivam Garg Alexander Kroh 1 2 3 4 7 Contents ITO UN as cate E E E swede ee et E E saa shee anesteaee scan napeteeessesaceeterscess 2 High level design configuration ccecccccssseccccesscccceesececauseceeceeeceeeuececeuneceeeuaeeessenecesseneceesanaeeetas 3 Crearno CUSTOM Pronn E T Aenea ot aeneelolees 4 3 a Generating a CUSTOM IP COMPONENL ccscccseccseccseeceeceeceecoesceusceusceusceuscesscesscessceseceseenaes 4 3 b Creating a Project file for the CUSTOM IP ccccceesecccesseccceesecceceesececsesecesseneceeseusecessuecesseneess 7 US EOI SINS Ere Cis GO UP area aa cers raceet obaeetocunenscasonce E E 10 4 a ATUTO Ier E A A S 10 Aar AANO a E E E ree eee ene eee eer ree 11 Aa PUN EAS sepe E A E 12 4 b Customising the Custom IP ssrin casein asaenaamecatesesosssanseececectnasseiecies 13 Apa CE TO NE N eea E E E E E EN ENAT 14 ANON Changes to Topleve lesnir EEE EAE EEEE act 15 Packaging and testing your IP serranas e 17 5 a IP Packager Within the Custom IP S Vivado project essesssssssesessrrreesrrereesrrrrressrrrresseeere 17 5 6 IP upgrade in high level design Within the high level Vivado project ccccceeeesseeeeeees 20 5 C interfacing with the Custom IP sccnccsedancnadansnosodssaainstes use osiedieinnabadediasaiiecesoslenliocsratiedeeuncbetanetotecesins 21 Hapene ion EXET E ee EA 23 6 a Pe A E a CON E E E eate
10. HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH set_property IOSTANDARD LVCMOS33 get_ports led_out 7 set_property IOSTANDARD LVCMOS33 get_ports led_out 6 set_property IOSTANDARD LVCMOS33 get_ports led_out 5 set_property IOSTANDARD LVCMOS33 get_ports led_out 4 set_property IOSTANDARD LVCMOS33 get_ports led_out 3 set_property IOSTANDARD LVCMOS33 get_ports led_out 2 set_property IOSTANDARD LVCMOS33 get_ports led_out 1 set_property IOSTANDARD LVCMOS33 get_ports led_out 0 set_property PACKAGE _PIN U14 get_ports led_out 7 set_property PACKAGE _PIN U19 get_ports led_out 6 set_property PACKAGE PIN W22 get_ports led_out 5 set_property PACKAGE PIN V22 get_ports led_out 4 set_property PACKAGE _PIN U21 get_ports led_out 3 set_property PACKAGE _PIN U22 get_ports led_out 2 set_property PACKAGE PIN T21 get_ports led_out 1 set_property PACKAGE PIN T22 get_ports led_out 0 HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH Switch constraints HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH set_property IOSTANDARD LVCMOS33 get_ports sw_in 7 set_property IOSTANDARD LVCMOS33 get_ports sw_in 6 set_property IOSTANDARD LVCMOS33 get_ports sw_in 5 set_property IOSTANDARD LVCMOS33 get_ports sw_in 4 set_property IOSTANDARD LVCMOS33 get_ports sw_in 3 set_property IOSTANDARD LVCMOS33 get_ports sw_in 2 set_property IOSTANDARD LVCMOS33 get_ports sw_in 1
11. P 0 500 AXI BASEADDR OxC 316 readData 816 ORFFFF amp read return readData Figure 6 5 C functions to interface with the BRAM within the Custom IP 28 7 Conclusion Now that you are comfortable with utilising Vivado s built in tools to generate and modify Custom IP and the design flow related to the process it s time to go out and design full fledged hardware solutions While designing your own solutions we have a few recommendations e Simulation In terms of compilation time and quality of debugging output Simulation provides the fastest way to test your design You should first make sure that your individual components are flawless before attempting to integrate them with the AXI bus This will save a substantial amount of time when diagnosing faults One important point to keep in mind of while when simulating on an FPGA with clock speeds in the MegaHertz range is that the number of clock cycles that occur within a second is more than what you could possibly view within a simulation frame Consequently ensure that your FSMs within the custom IP are initiated by an AXI transaction and STOP when the transaction has completed Your FSMs should wait for a second AXI transaction before continuing the data processing This is particularly evident if you decide to print characters to the console between reading and writing data from the Custom IP A large amount of clock cycles will be used up writing out to the UART t
12. XI transaction This is particularly important for a read operation where the data read will be unpredictable if the data on the data bus does not remain stable S AXI Write occurs Insert AXI Increment FIFO WDATA into insertion HiO pointer AXI read occurs Increment FIFO read position valid for next read Read RDATA from FIFO Figure 6 2 FIFO Finite State Machine FSM Implementing a FIFO will be more challenging than the timer since we now need to consider peripheral state and state transitions State transitions are triggered by AXI communication as follows e Write When a write is taking place we should read the data bus WDATA and set this as the FIFO data input We should also enable a FIFO write signal for exactly one clock cycle such that the FIFO knows to push the current data to its tail Referring back to Section 4 a i and the original source code for Slave _AXI it should be noted that the S_AXI_WREADY is asserted by the Slave for exactly one clock cycle once the write was successful We can probe this signal as high and once so enable a write to the FIFO For example we will be performing our FIFO insertion operation at the start of the 14 clock cycle in Figure 4 1 on page 11 24 e Read From the timing diagrams in Section 4 a ii on pages 11 and 12 it should be apparent that the Slave has only a couple of clock cycles to correctly set the data to be read onto the data bus Instead of trying to p
13. _ip update the display name and provide a description of the peripheral Li st a Create And Package New IP Specify VLMV information and other details for the Peripheral av Vendor xilinx com Library user Name labo_ip Version 1 0 Display Name iabo ipv 1_0 Description AXI IP demo i Vendor Display Name Company URL Figure 3 3 Step 3 5 naming the new IP 3 6 In the next menu keep the default options selected as shown in Figure 3 4 gt Interface Type LITE Full and Steam AXI allows for burst transfers 4 packets at a time and continuous data transfers respectively When coupled with other peripherals such as DMA controllers these AXI protocols can be essential for meeting throughput requirements AXI LITE on the other hand is a simpler protocol that satisfies the minimum hardware requirements of the AXI bus This means that there will be fewer signals and state to worry about when designing your custom IP Interface Mode SLAVE Since this IP is going to be issued commands by the processor this IP will act as a Slave Data Width 32 For simplicity we will keep the bus at the default width Number of registers 4 This option will affect the generated Slave AXI code With four registers the data transferred from Master to Slave will be stored in 4 unique registers The 4 least significant address bits are used to multiplex between these registers b0000 first register b0100 second regist
14. cate that the current read is invalid DE DE oo os Write ptr Read ptr Read ptr Write ptr 3 After 4 more values have been written by 4 More values written note the write ptr has the user note read ptr is now valid moved beyond read ptr Undefined behaviour Figure 6 3 Run through of FIFO behaviour The FIFO diagrams in Figure 6 3 denote the functioning of the FIFO they should all be fairly easy to follow The one which causes some concern is the 4 diagram where the user has written over data that has not yet been read by the user It is up to you to decide how to respond in this case Just ignore the transaction and assume the user knows not to overfill the FIFO Store the current size of the FIFO by counting writes and decrement with reads If the FIFO is full the request should be ignored Note that it will not be possible to provide the client with immediate feedback when this occurs as this information is only reported by a read transaction 25 The specification for the FIFO that you will design is as follows e FIFO data width of 16 bits and a capacity of 1024 words This should be implemented as block ram in the Toplevel The BRAM should have both an address and a data width of 16 If you need a refresher on the use of BRAM refer to the Distributed and Block ram on Xilinx FPGA s guide 5 e f we reach the end of FIFO addressing reads and writes should wrap around the BRAM This can trivially be achieved by ign
15. ction 4 b of this lab correctly include lt stdio h gt Folattorm h define TIMER STOP 0 define TIMER START 1 define TIMER RESET 2 int main init platform Xil Outs2 PAR LABO IP 0 500 AXI BASEADDR 0x1 Xil Out32 APAR LABO IP 0 500 AXI BASEADDR 0x4 0x2 All Outs32 APAR LABO IP 0 500 AXI BASEADDRtOxd 08x990 All Outs2 APAR LABO IP 0 500 AXI BASEADDRt OxC 0x100 u32 r0 0 ri r2 r3 rO Xil In32 XPAR LABO IP 0 500 AXI BASEADDR ri Xil In32 XPAR LAPO IF 0 500 AXI BASEADDR 024 r2 Xil In32 XPAR LAPO IF 0 500 AXI BASEADDR 028 r3 Xil In32 XPAR LAPO IP 0 500 AXI BASEADDR 0xC xil printf Values read 40K 0X 0X 20 r n r0 ri rz rsi Figure 5 9 C code which is used to test our Custom IP 21 If you were to write to the address XPAR_LABO_IP_O SOO AXI_BASEADDR 0x10 it would mimic the effect of writing to XPAR_LABO_IP_O SOO AXI_BASEADDR Ox0 since the Slave only sees the least significant 4 bits of the address The xil_io h file contains definitions for IO functions of various widths such as Xil_in8 Xil_ out16 You may have considered using these functions given that we are reading and writing such small data sizes A problem with this approach lies in our AXI bus abstraction layer where we have chosen not to expose the signals required for detecting these access widths It is common to find that AXI devices will only support 32 bit IO You will also find definitions for fixed size da
16. e Fabiana aceasta Copy To Add File Group Remove File Group Refresh Table Export to Spreadsheet lt Figure 5 3 Step 5 3 Add VHDL files to the IP definition if needed 5 4 Ifthe ports to the Toplevel have been changed then use the IP Ports page by clicking on the Port import dialog and following the prompts E Project Summary X W PP Identification veces J The top evel ports of your IP that were found during analysis are listed refuting port properties in the table 4 To use ports from a different module entity or a different HDL file use the WV IP File Groups A Name Direction Driver Value SizeLeft Size Left Dependency Size Right Size Right Dependency Type Name WV IP Customization Parameters D gt s00_axi_awaddr in 3 C_S00_AXI_ADDR_WIDTH 1 0 wire D s00_axi_awprot in 2 0 wire meos l D sooaxiawaid in 0 0 wire I s00_axi_awready out 0 0 wire Y Pieters D s00_axiwdata in 31 C_S00_AXI_DATA_WIDTH 1 0 wire W IP Addressing and Memory D s00_axi_wstrb in 3 C_S00_AXI_DATA_WIDTH 8 1 0 wire D gt s00_axi_wvalid in 0 0 wire W IP GUI Customization Layout lt s00_axi_wready out 0 0 wire J s00_axi_bresp out 1 0 wire IP Licensing and Security lt 500_axi_bvalid out 0 0 wire D s00_axi_bready in 0 0 wire Review and Package D s00_axi_araddr in 3 C_S00_AXI_ADDR_WIDTH 1 0 wire D s00_axi_arprot in 2 0 wire D s00_axi_arvalid in 0 0 wire J s00_axi_arready out 0 0 wire lt s00_axi_rdata out 31 C_S00_AXI_DATA_WIDTH 1 0 w
17. e high level design Vivado file and open the Block Design 5 8 Select the TCL console window and run the following commands a update ip catalog rebuild This refreshes the IP repositories specified in Project Settings gt IP gt IP Repositories you can do this manually if you wish b report ip status name ip status 1 This generates an IP report which shows whether or not the IP in your design are up to date You should see that labO_ ip Ohas a Major Version Change as shown in Figure 5 7 1MajorChange 3 Up to dates Hide All A vit S0UrCE File m IP Status Recommendation ChangeLog UpgradeLog IF Name Current Version Recommended Version License E gh a system bd 4 Open Block Design p2 0 Rev 0 Rev N A fprocessing_system7_0_axi_periph p T Gate lo changes required More info EATE ETE PRE T NJA i rst_processing_system _0_50M No changes required More info Processor System Reset 5 0 Rev 3 5 0 Rev 3 N A JF jprocessing_system7_0 at No changes required More info ZYNQ Processing System 5 3 Rev 1 5 3 Rev 1 lt ip_status_1 x d gt a Figure 5 7 Step 5 9 Vivado reporting changes to the IP in your high level design 5 9 Tick the checkbox associated with our IP and click the upgrade selected button Vivado will now upgrade the instantiated IP while retaining all existing connections 5 10 Regenerate the HDL wrapper for your high level design and save your project file 5 11 Generate a b
18. er b1000 third register and b1100 fourth register The last two bits are always b00 due to 32 bit width alignment Add Interfaces Add AXI4 interfaces supported by your peripheral S00_AXI Interface Type Interface Mode Slave Data Width Bits y oIZe OYtes Number of Registers Select a property above to see the description of it Figure 3 4 Step 3 6 configuring AXI protocol for IP 3 7 When you are happy with the configuration click Next 3 8 On the Generation Options screen leave the options unchecked and click next 3 9 Finally select Add IP to catalog and hit finish Begin Peripheral Creation Output Products 1 IP xilinx com user lab0_ip 1 0 with following interfaces a lite slave Interface Data Width 32 Number of registers 4 IP Created will be available in the catalog with repository C Users Shivam Desktop comp4601 After Creation Add IP to catalog Add IP to catalog and open IP in editing session VIVADO Click Finish to begin peripheral creation Figure 3 5 Step 3 9 Finishing off the creation of Custom IP You have now generated your own Custom IP component In the next section we will create a Vivado project file for the Custom IP so that we can independently modify the Custom IP abstracting it from the high level design Vivado block diagram 3 b Creating a Project file for the Custom IP 3 10 Inthe block diagram view with only the ZynQ7 IP i
19. erilog_version Verilog 2001 a Run Simulation Implementation Generics Parameters b 4 RTL Analysis EA Mae library Figure 3 1 Step 3 1 Project target language 3 2 Go to the tools menu gt Create and Package IP 3 3 On the introductory screen select the next option 3 4 Select Create new AXI4 peripheral and then in the IP location go up one level in the directory hierarchy from where the high level project file is located The high level project directory and the IP that will be created should be located in the same directory e g C XX high level amp C XX IP Choose Create Peripheral or Package IP Package your project Use the project as the source for creating a new IP Definition Note All sources to be packaged must be located at or below the specified directory Package generated files Package already generated HDL for IP in the project Package a specified directory Choose a directory as the source for creating a new IP Definition Package as a library core Library cores are available for reference by other IP Note Library cores do not appear in the IP Catalog Creates AXI4 IP Driver TestApp and the AXI4 BFM example design C Users Shivam Desktop comp460 1 Figure 3 2 Step 3 4 selecting IP type and location Project device dBoard Zyng Evaluation and Development Kit xc7z020cdg484 1 F 3 5 Name the IP as labO
20. fied Once packaged it can be instantiated in the high level design as an independent IP block in the same way that we instantiate any other IP block Then all that remains is to write some C driver like code to interact with the IP and ensure that the changes that we have made are correct This process will need to be repeated every time you change the implementation of the IP however a lot of the steps below are conditional 5 a IP Packager Within the Custom IP s Vivado project 5 1 Select Package IP in the project manager section in the left hand pane Xm Gt Be 4 Project Manager Gl Design Sources 2 g Project Settings E se labO_ip_v1_0 arch_imp lat at Add Sources _ dt labO_ip_v1_0_500_AXI_inst lal B A IP XACT 1 F IP Catalog H Constraints E Simulation Sources 1 d IP Integrator Pas Create Block Design gs Open Block Design Figure 5 1 Step 5 1 starting the packaging process 5 2 At the start screen leave all the options the same except for the version number ensure that you INCREASE the version number e g 1 0 gt 2 0 The reason for this is so that Vivado will detect the version change and prompt you for an upgrade You should also alter the display name to reflect the version number change E Project Summary x Package I W IP Compatibility TF Identification SL appear in the IP Catalog by modifying the Taxonomy IP File Groups Kd p T W IP Customization Parame
21. h has a reset signal controlled by bit 1 of dataout0 and an enable counter signal controlled by bit O of dataoutd In this case the counter is counting rising edges in the FCLK_CLKO signal number of FCLK_CLKO periods elapsed The implementation of the timer will be quite simple since AXI writes from the Master to the Slave are stored in the Slave registers which we have piped out to the Toplevel After implementing the timer control logic all that remains is to get the value of the timer back to the Master PS Since the selected AXI data bus width was 32 bits we will implement a 32 bit timer The timer value will need to be provided every time the user reads from OxYYO where YY is any 23 number To achieve this we simply need to set the datainO signal to be the current value of the timer The final step for this exercise is to export the design to the SDK and modify the IP test code to exercise the timer and ensure that it operates correctly An example solution can be found in Appendix A in case you wish to verify your IP implementation 6 b FIFO implementation A FIFO is acommon design element that is used to queue a transmitted data stream until the receiver is ready to collect it A FIFO is particularly important when transferring data between two clock domains subsystems that are clocked at different rates Figure 6 2 details the FSM that you will be implementing It should be noted that state transitions must not occur during an A
22. h set the read value of register O BASE_ADDR 0x0 Similarly writes to register O set the read value of register 1 Meanwhile for the reads from register 2 BASE ADDR 0x8 and register 3 BASE ADDR OxC the constant values of 3 and 4 will be read respectively and writes to these registers will be ignored Anid user logic here datainoO lt dataoutil 144 datainl lt dataoutod datain s X 00000003 datains3s X 00000004 Da Lai Pj Figure 4 8 Simple IP logic to test the changes that we have made Within the IP project file check for compilation errors by clicking on the Synthesise button in the left hand pane Once you have corrected any outstanding errors all that remains is to save these changes within the IP In the next section of this manual you will update the instantiated component within your high level design and test the implementation of your updated IP via the PS The importance of the steps outlined in this section is that you no longer have to worry about the Slave _AXI implementation file because you have exposed all of the signals that will be useful for your implementation From now on you are free to modify only the Toplevel file when changing the behaviour of your custom IP or to instantiate additional components 16 5 Packaging and testing your IP In this Section we will package the Custom IP Toplevel and Slave _AXI files that we have generated and modi
23. h_MOO_AXI RVALID Uk system_i processing system7_0 axi_periph MOO AXI WREADY Uk system_i processing system7_0 axi_periph MOO _AXI_ WVALID Figure 4 2 Debug output for AXI read transactions The waveforms in Figure 4 2 show the processor reads via AXI LITE from a FIFO at address BASEADDR 4 0x4 The FIFO contains the data Ox0a OxOb OxOc The Master initiates an AXI read as follows where numbers refer to the labelled signals between the clock cycles 175 177 1 For AXI LITE the Master generally always has the signal RREADY asserted signalling that it is able to receive data from the Slave 2 The Master then places the requested address 0x4 onto the ARADDR bus and asserts ARVALID The Slave then performs the following where numbers refer to the labelled signals between the clock cycles 177 180 3 The Slave asserts ARREADY to signal that the address has been accepted by the Slave 4 The Slave then sets RDATA to reflect the appropriate data 0x0000000a and asserts RVALID and de asserts ARREADY At this point the 178 clock cycle the correct data has been placed onto the bus and the Master has just one clock cycle to read it before RVALID is de asserted Since the Master AXI Interconnect and the Slave are clocked at the same rate FCLK_CLKO the RVALID signal can be viewed as a latch signal for the AXI Interconnect to store this data into its own internal register and later forward it to the up stream Master the Zyng
24. hus distorting your perception of time elapsed between the two AXI transactions e Debug If your hardware is not working the way you envisioned despite simulations telling you otherwise one method of identifying the problem is to set all relevant signals as outputs to the Toplevel of the Custom IP Then utilising the knowledge gained in lab2 of Advanced Embedded Design set all of these ports as debug Once you have assigned the debug cores set the waveform to trigger on a change in one of the AXI signals and run through your software Finally analyse the waveform to work out where the issue lies This approach has been tried and found to be much faster at identifying problems than trying to simulate your Toplevel Custom IP individually since that approach involves having to simulate Master AXI behaviour e Advanced users If you can churn out perfect syntax error free VHDL every time then potentially you may wish to skip the IP synthesis amp repackaging every time and instead modify the files within C XX HIGH LEVEL HIGH LEVEL srcs sources 1 bd system ip system labO ip O O hdl vhd The obvious traps with this method include a much longer time for the compilation to fail on syntax errors and the fact that you can only modify the logic of the IP and not add extra VHDL files and ports to the definition of the IP For most users it is recommended that you repackage and upgrade the IP every time as the extra minute or two added v
25. ia this process allows for faster identification and fix up of errors amp warnings should they occur 29 References 1 Xilinx Custom IP guide slightly outdated but quite comprehensive guide to Custom IP http www xilinx com support documentation application notes xapp1168 axi ip integrator pdf 2 AXI reference guide http www xilinx com support documentation io documentation ug761 axi reference 3 Xillinx AXI Interconnect http www xilinx com support documentation ip documentation axi interconnect v2 1 axi interconnect pdf 4 Zedboard user manual http www zedboard org sites default files ZedBoard HW UG v1 1 pdf 5 Block and distributed RAM s on Xilinx http vhdiguru blogspot com au 2011 01 block and distributed rams on xilinx html uide pdf 059 30 Appendix Appendix A Timer Solution Timer implementation uses the dataoutO signal to represent the current value which has been written to the timer s control register And datainO signal to output the timer value process clk dataout0 begin if dataoutO 1 1 then asynchronous reset timer32 lt others gt 0 else if rising edge clk then if dataout0O 0 1 then timer32 lt timer32 X 00000001 end if end if end if end process datainO lt timer3 7 Appendix B GPIO constraints HHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH LED constraints H HHHHHHHHHHHHHHHHH
26. ign the peripheral directly or instantiate other components The reason for this is so that we preserve the protocol implemented by the Slave AXI file and concentrate our efforts on the implementation of the device logic shown in orange High Level Design LabO_ip Toplevel AXI Data in Interconnect Implementation Data_out Latched_addr Processing Programmable System Logic Select signals Figure 4 3 System diagram denoting the changes we are about to make green arrows and a high level overview of how all the components are connected 13 4 b 1 Changes to Slave_AXI Figure 4 4 presents a subset of the Slave _AXI design file You should note that the RDATA bus for AXI reads is driven by reg_data_out The generated Slave implementation drives this signal from the local signals named slv_reg The first modification will be to introduce four externally visible signals to take the place of these signals during a read operation We will call these signals datain as shown in Figure 4 4 353 process si reg axi araddr S AXI ARESETN 354 slv_reg_rden datain0 datainl datain2 datain3 355 variable loc addr std_logic vector OPT MEM ADDR BITS downto 0 356 begin SES if 5S AXT ARESETN 0 then a58 i reg data out lt others gt 1 eee else 360 Address decoding for reading registers Ee loc addr axi araddr ADDR _ LSB OPT MEM ADDR BITS downto ADDR LSB SE ease loc
27. imple modifications so that we can determine if the changes that we have made to the IP source have carried through to our high level design Your next task is to modify the Toplevel source file to reflect the port changes that were made to the Slave_AXI component in Section 4 b i as shown in Figure 4 7 You will also need to declare these signals within the Toplevel lab0 ip vi 0 500 AXI inst labO ip vi 500 AXI Generic map om tn H ti Ee C 5 AXI DATA WIDTH gt C 500 AXI DATA WIDTH OUZO SPA C 5 AXI ADDR WIDTH gt C_ 500 AXI ADDR WIDTH 10 108 port map COUSO S 5 AXI ACLE gt s300 axi acik gt Mees S AAT RREADY gt s300 axi rready CEU SE dataindg gt dataing ef dataint gt dataintl is SAST gdatminz Oatain T33 ti datain3 gt datains isa i dataautd dataouto a dataouti gt dataoutl a GQabeoquiz datacout tS dataouts3 gt dataout3 tS latched waddr lwaddr LSS KER latched raddr gt lraddr 140 1 Figure 4 7 Signal additions to the port map of the Slave_AXI Lines 110 129 require no changes 15 We will now implement some trivial logic shown in Figure 4 8 for the purposes of testing the changes that we have made Notice that the registers which store the data written by the Master dataout0 dataout1 are routed to the AXI read registers datain1 datainO Writes to register 1 BASE ADDR 0x4 whic
28. ire c s00_axi_rresp out 1 0 wire lt s00_axi_rvalid out 0 0 wire D s00_axi_rready in 0 0 wire D s00_axi_ack in 0 0 wire D s00_axi_aresetn in 0 0 wire Figure 5 4 Step 5 4 Modifying IP ports if needed 5 5 If you used the IP ports page to add remove ports you should now go to the IP GUI Customization Layout and use the IP GUI customization layout wizard to regenerate the 18 image of the IP component Simply follow the run the wizard link to regenerate the diagram of the IP E Project Summary x W IP Identification W IP Compatibility WV IP File Groups W IP Customization Parameters W IP Ports W IP Interfaces W IP Addressing and Memory IP Licensing and Security Review and Package 5 6 screen CE Project Summary x WZ IP Identification W IP Compatibility f IP Customization Parameters W IP Ports W IP Interfaces W IP Addressing and Memory W IP GUI Customization Layout TF Licensing and Security IP GUI Customization Layout o configure the parameters that appear on each page of the IP Customization GUI When you finish the w Component Name lab0_ip_0 4S00_AxI 500 axi_aclk s00 axi aresetn Figure 5 5 Step 5 5 Regenerating the IP GUI Complete the process by clicking on the Re Package IP button in the Review and package Review and Package When all information is properly induded you will be able to package
29. irst thing to do is close it so that a permanent project file will form This will make it easier to edit the IP in future without the need to generate and regenerate temporary project files also protecting against data loss if Vivado crashes You should now have two project files as shown in Figure 3 9 One is the high level module labO and the second contains the IP labO_ip 1 0 p t comp4601 w Name Date modal ed Type PT labO_ip_1 0 21 07 2014 12 12 File folder dd 21 07 2014 12 11 File folder wt 21 07 2014 12 11 File folder labO 20 07 2014 amp 10PM File folder 12 06 2014 amp 03 PM File folder t comp4601 labOQ_ip_ 1 0 labO_ip_v1_0_ project Mame Date modified id ta pe labO_ip_v1_0_project xpr 21 07 2014 12 12 21 07 2014 12 12 bO_ip_v1_0_project data di t comp4601 lab v G Name dJi labO0 cache Ji labO data dJi labO hw ult labO runs J labO sdk labO sres Figure 3 9 Step 3 15 Expected directory structure 3 16 Now we will reopen the Vivado project file for the Custom IP Navigate to the lab0O_ip 1 0 labO_ip_v1_0_project folder and open the xpr file shown above 3 17 Open the VHDL file named labO_ip v_1 0 SOO AXI vhd from the project manager view Project Manager lab0_ip_ vi_0_project Sources m E 4 a h o B fe oo i asle Gla Design Sources 2 wis i eS IP KACT 1 H Constraints H Simulation Sources 1 Figure 3 10 Step 3 1
30. itrarily choosing the name of just one of the ports that it connects in this case the Master AXI port The AXI writes are initiated by the Master as follows where the numbers refer to the labelled signals between clock cycles 10 12 1 The Master sets up WDATA with OxFFFFFFFF and asserts WVALID write data is valid 2 The Master sets up AWADDR with 0x0 and asserts AWVALID address valid Master strictly speaking it is the AXI interconnect which acts as the Master for this Slave AXI component not the PS The Slave then responds as follows where the numbers refer to the labelled signals between clock cycles 13 15 3 The Slave asserts AWREADY write address can be accepted by the Slave determined by WVALID amp amp AWVALID 4 The Slave asserts WREADY write data can be accepted by the Slave determined by WVALID amp amp AWVALID at this point AWADDR is also latched to free the bus for another operation Once WVALID amp AWVALID amp AWREADY amp WREADY are all asserted o Slave register write is enabled o Onthe next clock cycle the 14 clock cycle in the figure marked with a yellow line WDATA is written to the appropriate Slave register in your custom IP 11 4 a ii AXI Reads Name Uk system_i processing_system 7_0_axi_periph_MO0_AXI RREADY Uk system_i processing system7_0 axi_periph_MOO_AXI_ARVALID Ug system_i processing system7_0_axi_periph_MOO_AXI_ARREADY Ug system_i processing system 7_0_axi_perip
31. itstream for the project 5 12 Once generated open the Implemented Design and export it to the SDK so that we can begin the development of driver software for interfacing with our custom IP 20 5 c Interfacing with the Custom IP In this section you will write C code to integrate and test our new IP with the CPU When creating the application project it is best to use the Hello World example project as a template because one of the first steps that the application performs is to initialize the UART You will need to include xparameters h to import the definitions shown in Figure 5 8 These addresses should correspond to those listed in Vivado s Address Editor Since the generated IP has a 4 register implementation only the bottom 4 bits of the address will be seen at the Slave byte addressing 32 bit data bus You should also include lt xil_io h gt to get the Xil_ Out32 Xil_ in32 function definitions Definitions for peripheral LABO IP 0 Rf define XFAR LABO IF 0 500 AXI BASEADDR 0x43C00000 define APAR LABO IP 0 500 AXI HIGHADDR Ox4SCOOFFF Figure 5 8 AXI address range of the AXI peripheral inside xparameters h Once you ve verified this go back to helloworld c and add the code shown in Figure 5 9 below This code writes 4 values and reads 4 values back from the IP The expected output should be Values read 00000002 00000001 00000003 00000004 if you followed the steps in Se
32. n 23 6 b FIFO IDEME a O ee E E 24 6 c PO WA MEn O e nan teewseaeebuanneeasaneceaaepncsetaneuasttecaces 26 6 d BIOCK RAM IMPlOMENtatiOn wicsseicscsssaiveccasvdccceveardoesvavdcessvendessnsendessavens souscevdsnapweedvencaseduncaueeuaes 27 CONCOS ON r E E EEE E E E E 29 1 Introduction The aim of this lab is to introduce a design flow that will allow you to create your own Custom Intellectual Property Custom IP targeted at a Zynq device using Xilinx s Vivado 2013 4 The lab has been created for senior undergraduates using the ZedBoard We assume the reader is familiar with the use of VHDL for specifying hardware The lab explains how to modify the generated component by focusing on how the AXI LITE protocol works and how it can be utilised to establish a two way data flow between the Processing System PS and the hardware component implemented in programmable logic PL This lab concludes on methods for maintaining and integrating this IP as part of a larger design As a high level overview this document will cover the following Section 2 Setting up your Vivado high level design focussing on the configuration of the Processing System Section 3 Using Vivado s built in tools to generate your own Custom IP and modifying this IP Section 4 Provides a tutorial on the AXI protocol that explains the critical modifications that allow the Slave AXI implementation to be abstracted thereby making the AXI communication logic as simple as
33. nstantiated select Add IP and find the labO_ip that you just created 3 11 Select the Run connection automation to the sOO_AXI of the Custom IP that we just created The end result should resemble that shown in Figure 3 6 processing_system7_0 DDR DDR F FIXED_IO F Maea ZYN aeo FIXED_IO s00_axi_aresetn bus_struct_reset 0 0 aux_reset_in peripheral_reset 0 0 b_debug_sys_rst interconnect_aresetn 0 0 dem locked peripheral_aresetn 0 0 Processor System Reset Figure 3 6 Step 3 11 Adding Custom IP to your high level design 3 12 Save the block design and project file 3 13 Right click the lab0_ip_v1_0 Custom IP in your design and select Edit in IP Packager E Block Properties Ctrl E Delete Delete Copy Ctrl C asl Ctrl V Search Ctrl F Select All Ctrl A Add IP Ctri am Ry ig A i iF I Customize Block oe Orientation Validate Design Figure 3 7 Step 3 13 opening the IP packager 3 14 Select Ok in the project location screen pes Choose project name and location for un packaging IP for editing labO_ip_v1_0_project Project location C Users Shivam Deskton comp4601 lab0_ip_1 0 Edit IP project will be created at C comp4601 lab0_ip 1 0 lab0_ip v1_0 project Bo Caneel Figure 3 8 Step 3 14 selecting the project name and location 3 15 When the new instance of Vivado shows up the f
34. oring underflows and overflows in FIFO position e Reading from an empty FIFO should not affect the FIFO position If the user tries to read from an empty FIFO bit 31 Most Significant Bit should be set to indicate that the data is invalid It is expected that the user checks this bit for data validity Table 6 2 FIFO register interface 31_ 30 a5 1 0 Read Invalid n a Data out wa oa Datain At this stage you should be able to verify your design by writing C code on the PS to sequentially push 1023 values onto the HW FIFO and then read them back in the same order 6 c GPIO implementation The GPIO implementation will mimic that of the Xilinx GPIO IP as seen in the Advanced Embedded design AED Lab 1 however it will be implemented entirely within our Custom IP component This exercise will involve adding ports to our IP as well as external pins and constraints to our high level design in order to extend the connectivity of our IP beyond the AXI bus We will implement two registers e LED The value of this register can be assigned directly from the most recent AXI write transaction dataout2 The output of this register should be directly connected to the LED pins e Switch The value of this register is associated with the logical state of the SWITCH pins and should be reported on the data bus during AXI read transactions from datain2 Once you have implemented this very simple hardware solution y
35. ou will need to repackage the IP Since you have added two ports to the IP you ll need to run the IP ports and GUI customisation of the IP packager as described in Section 5 a on page 17 Finally within the high level design you need to declare the LED s and SW s and connect them to external pins see AED lab1 for pin assignments within the xdc file and refer to the Zedboard user manual 4 for the IO pin numbers A sample constraints file for both the LED s and Switches has been provided in Appendix B if you are stuck at this stage 26 Figure 6 4 shows what your high level design should resemble For testing your IP through the PS it is recommended that you write an infinite loop that reads the switch values and writes this pattern back out to the LED register labO_ip_0 4400_AXI D i led_out 7 0 _ outf led_out 7 0 processing_system _0 processing_system7_0_axi_periph s00_axi_aresetn E j J lab0_ip_v13_0 Pre Producti bag POR i ab0_ip_v13_0 Pre Production PS FIXED 10 ZYNQ7 Processing System PEREA Figure 6 4 High Level Vivado project file denoting the relevant pin to port connections to be made 6 d Block RAM implementation Block RAM plays an important role in peripheral local storage for PL IP components As an example you may wish to perform a DSP operation on an image This image may need to be uploaded from the CPU into the IP for efficient random data acce
36. rovide a read result at the exact instance it is required we shall set up the next read value as soon as any read transaction has completed Referring back to Section 4 a ii on page 12 and the original source code it should be noted that when S_AXI_RVALID is asserted the Slave has updated the data bus with valid read data Furthermore this signal is asserted for exactly 1 clock cycle If we were to wait for this signal to be asserted on the rising edge of a clock pulse which would mean the falling edge of the signal S_AXI_RVALID we know that the data datain1 has been accepted by the Master and we can safely replace the value of datain1 with the next value in the FIFO The position in time at which this happens is denoted by the start of the 179 clock cycle in Figure 4 2 on page 12 The last point to note is that you also have to check the address of the write read operation to ensure that it is a FIFO operation denoted by the addressing corresponding to OxYY4 However if you refer back to the timing diagrams in Figure 4 1 and Figure 4 2 you ll notice that the read write address is only valid for a very small amount of time Therefore we will need to make use of the latched write and read addresses and check that the 3 downto 2 bits are equal to 01 i Read ptr Write ptr Write ptr 1 Initial FIFO after 3 values have been 2 After 3 values read by user note that the written next read should not move read ptr Set bit 31 to indi
37. ss The image may also need to be downloaded again later such that the processed result can be forwarded to the next process block For this exercise it is assumed that you are now familiar with the design flow We provide you with only the register API and leave the implementation details entirely to you API Assumptions e 16 bit BRAM data width e 16 bit BRAM address width e The Master can read and write to any address within the BRAM Table 6 3 Block RAM register interface Aoa n a n a Data at active address A D n a If bit 31 0 Active address select select If bit 31 1 Data to write to active address Bit 31 selects the context for an AXI write transaction If this bit is not set the data should be interpreted as a BRAM address selection When this bit is set the AXI data represents the 16bit value which should be written to the current active BRAM address During a read request bit 31 is always ignored and data should always be read from the active BRAM address For example to perform a read or write transaction at a particular address you would need to write a driver which executes the functions shown in Figure 6 5 27 Wold writeToBRAM ul6 addr 316 data t Xil Out32 XPAR LABO IP 0 500 AXI BASEADDR OxC addr Xil Out32 XPAR LABO IP 0 500 AXI BASEADDR OxC lu lt lt 31 data 7s16 readFromBRaAM ulsb addr Xil Outs2 XFAR LABO IP 0 500 AXI BASEADDR OxC addr u32 read Xil In32 XPAR LABRO I
38. ta types such as u32 unsigned 32 bit within xil_io h As you may already be aware the size of an int data type is not well defined For this reason it is good practice to use fixed size data types when accessing fixed size peripheral registers 22 6 Implementation Exercises By now you should be familiar with the process of modifying a Custom IP component repackaging the IP and integrating it back into your high level design In this section we will extend the custom IP design to produce a useful AXI peripheral The peripheral will be split into 4 functions a timer a FIFO a GPIO controller and CPU accessible BRAM All exercises are intended to be implemented in the Toplevel file of the Custom IP The AXI register layout for this lab is shown in Figure 6 1 Writes via AXI Reads via AXI Address OxYYO OxYY4 OxYY8 OxYYB NS ad Figure 6 1 AXI Protocol for the Implementations to follow 6 a Timer implementation The first task will be to implement a simple AXI accessible 32 bit timer within the FPGA The timer will run at FCLK_CLKO and counts the number of clock cycles elapsed since the timer was last reset by the user CPU AXI Master The register interface for the timer is shown in Error Reference source not found 31 30 nm af 0 o a n a m u Reset Enable Timervalue Timer value Table 6 1 Timer register interface The timer can be considered to be a counter whic
39. ters Vendor yilinx com TF Ports v Library user W IF Interfaces Name labO_ip W IP Addressing and Memory Version W IP GUI Customization Layout sete ete ab ip TF Licensing and Security Description IP for lab Review and Package Vendor display name Company url Categories AXI_Peripheral Root directory c Users Shivam Desktop comp4601 labproduction labO0 ip 1 0 Xml file name c Users Shivam Desktop comp4601 labproduction lab0_ip_1 0 component xml Advanced Figure 5 2 Step 5 2 altering the version number for your IP 17 5 3 Ifthe changes to the file involved adding new VHDL files they must be added in the IP File Groups to both the VHDL synthesis and VHDL Simulation folders as shown in Figure 5 3 E Project Summary X Package IP labO_ip x IP File Groups W IP Identification Linfo message W IP Compatibility When the file group list below is expanded the individual files within each group will be displayed You can select and use the W IP Customization Parameters A f Name oe ol fe W IP Ports ia ii Standard Te aeii Se VDE Syne A WV IP Interfaces hdlflabO_ip_v1_0_S00_AXI vhd e hdlflabO_ip_v1_0 vhd Add Fil j W IP Addressing and Memory G2 VHDL Simulation 2 By Advanced W IP GUI Customization Layout a H 6 UI Layout 1 5 6 Block Diagram 1 IP Licensing and Security i B bd bd td Add Sub Core Reference Review and Packag
40. ustom AXI based IP components that provide fundamental hardware implementations such as a timer a FIFO and GPIO The starting point for this lab is the following high level configuration e Instantiate a Zynq7 processing system with UART1 enabled e Apply block automation without board pre sets applied to connect DDR and FIXED_IO to external pins e Check that your bock diagram matches the diagram shown in Figure 2 1 processing_system _0 DoR DOR FIXED 104 _ gt FIXED_IO M_AXI_GPO_ACLK ZYNQ M_AXI_GPO E FCLK_CLEO FCLK_RESETO_N ZYNQ Processing System Figure 2 1 Initial design 3 Creating Custom IP In this section you will be creating your own Custom IP which features an AXI LITE interface for communication between the Processing System PS and the Programmable Logic PL We will then connect this IP to the PS and prepare a project file so that you can readily modify the design later 3 a Generating a Custom IP component 3 1 Open the project created in Section 2 Click on Project Settings then ensure that the Target Language is set to VHDL else the generated IP will be in Verilog Click OK when done General Name labo GBF Create Block Design es Open Block Design Fa Generate Block Design Top module name system_wrapper Synthesis Language Options 4 Simulation 5 Simulation Settings gt Verilog options v
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