Home

MPC8280 PowerQUICC II™ Specification

1. Mode PC Clock 3 CPM Clock CPU Clock Bus Clock 6 MHz CPM MHz CPU MHz Bus MHz Multiplication Multiplication Division MODCKIT SI low high Factor ow nigh Factor tow nign Factor tow high 0010_011 26 0 50 0 6 156 3 300 0 4 250 0 480 0 2 5 62 5 120 0 0010_100 25 0 50 0 6 150 0 300 0 4 5 270 0 540 0 2 5 60 0 120 0 0011 000 Reserved 0011 001 31 3 50 0 4 125 0 200 0 2 5 125 0 200 0 3 41 7 66 7 0011_010 Reserved 0011_011 46 9 50 0 4 187 5 200 0 4 250 0 266 7 3 62 5 66 7 0011_100 41 7 50 0 4 166 7 200 0 4 5 250 0 300 0 3 55 6 66 7 0100 000 Reserved 0100 001 25 0 50 0 6 150 0 300 0 3 150 0 300 0 3 50 0 100 0 0100 010 35 7 50 0 6 214 3 300 0 3 5 250 0 350 0 3 71 4 100 0 0100_011 31 3 50 0 6 187 5 300 0 4 250 0 400 0 3 62 5 100 0 0100_100 27 8 50 0 6 166 7 300 0 4 5 250 0 450 0 3 55 6 100 0 0101_000 25 0 50 0 5 125 0 250 0 2 5 125 0 250 0 2 5 50 0 100 0 0101_001 25 0 50 0 5 300 0 2 5 50 0 100 0 0101_010 35 7 50 0 5 350 0 2 5 71 4 100 0 0101_011 31 3 50 0 5 400 0 2 5 62 5 100 0 0101_100 27 8 50 0 5 450 0 2 5 55 6 100 0 0101_101 25 0 50 0 5 500 0 2 5 50 0 100 0 0101_110 25 0 50 0 5 550 0 2 5 50 0 100 0 0110 000 Reserved 0110_001 25 0 50 0 8 200 0
2. Mode2 PCI Clock 3 CPM Clock CPU Clock Bus Clock 6 MHz CPM MHz CPU MHz Bus MHz Multiplication Multiplication Division MODCK TS low high Factor iow nign Factor tow high Factor tow high 0101_000 50 0 66 7 5 250 0 333 3 2 5 250 0 333 3 2 5 100 0 133 3 0101_001 50 0 66 7 5 250 0 333 3 3 300 0 400 0 2 5 100 0 133 3 0101_010 50 0 66 7 5 250 0 333 3 3 5 350 0 466 6 2 5 100 0 133 3 0101_011 50 0 66 7 5 250 0 333 3 4 400 0 533 3 2 5 100 0 133 3 0101_100 50 0 66 7 5 250 0 333 3 4 5 450 0 599 9 2 5 100 0 133 3 0101_101 50 0 66 7 5 250 0 333 3 5 500 0 666 6 2 5 100 0 133 3 0101_110 50 0 66 7 5 250 0 333 3 5 5 550 0 733 3 2 5 100 0 133 3 0110 000 Reserved 0110_001 50 0 66 7 4 200 0 266 6 3 200 0 266 6 3 66 7 88 9 0110_010 53 6 66 7 4 214 3 266 6 3 5 250 0 311 1 3 71 4 88 9 0110_011 50 0 66 7 4 200 0 266 6 4 266 7 355 5 3 66 7 88 9 0110_100 50 0 66 7 4 200 0 266 6 4 5 300 0 400 0 3 66 7 88 9 0111_000 50 0 66 7 3 150 0 200 0 2 150 0 200 0 2 75 0 100 0 0111_001 50 0 66 7 3 150 0 200 0 2 5 187 5 250 0 2 75 0 100 0 0111_010 50 0 66 7 3 150 0 200 0 3 225 0 300 0 2 75 0 100 0 0111_011 50 0 66 7 3 150 0 200 0 3 5 262 5 350 0 2 75 0 100 0 1000 000 Reserved 1000
3. Tx data FIFO 16 byte Mode register Command register Tx data FIFO Rx FIFO EPO 16 byte Port configuration Address unction USB Host state machine registr State machine End point registers Transmitter Receiver DPLL Bus Interface External transceiver Figure 7 4 USB Controller Block Diagram 7 5 1 USB Host Controller Transmit Receive The USB host controller initiates all USB transactions in the system After the reset condition the HOST bit in USB mode register should be set refer to Section 7 5 7 1 USB Mode Register USMOD to enable host operation Setting USMOD TEST enables the loopback operation where 3 of the endpoints are function end points The USB controller supports four independent end points Each endpoint can be configured to support either control interrupt bulk or isochronous transfers modes This is done by programming the end point registers refer to Section 7 5 7 3 USB End Point Registers USEP1 USEP4 End point 1 must be used for host transactions think exactly how it should be programmed and its limitations After reset the host should enumerate the functions in the system The enumeration process is done by software Once enabled the USB host controller waits for a packet in its fifo When FIFO i
4. Channel Opcode SMC SMC FCC USB SCC UART GCI SPI IDMA Special Transparent 0000 RX AND INIT RX AND INIT RKAND INITRX INIT RX INIT RX TX PARAMS TX PARAMS TX PARAMS AND TX AND TX AND TX AND TX PARAMS PARAMS PARAMS PARAMS 0001 INIT RX INIT RX INIT RX INIT RX INIT RX INIT RX PARAMS PARAMS PARAMS PARAMS PARAMS PARAMS 0010 INIT TX INIT TX INIT TX INIT TX INIT TX INIT TX PARAMS PARAMS PARAMS PARAMS PARAMS PARAMS 0011 ENTER ENTER ENTER INITMCC HUNT MODE HUNT MODE HUNT MODE RXAND TX PARAMS ONE CHANNEL 0100 STOPTX STOP TX STOP MCCSTOP TX 0101 GRACEFUL GRACEFUL IINITMCC STOP TX STOP TX TX PARAMS ONE CHANNEL 0110 RESTART RESTART RESTART IINITMCC TX TX TX RX PARAMS ONE CHANNEL 0111 1000 SET GROUP SET GROUP SET ADDRESS ADDRESS TIMER 1001 GCI START MCCSTOP TIMEOUT IDMA RX 1010 ATM USB STOP TX RESET BCS GCI TRANSMIT ENDPOINT ABORT COMMAND REQUEST MOTOROLA Chapter 5 Internal Multiported RAM DPRAM 5 11 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Command Set Fr
5. MOTOROLA Chapter 4 PLL and Clock Generator 4 11 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Configuration Modes Table 4 6 Local Bus Clock Modes continued 2 3 3 3 Bus ee CPU MHz Multiplication MHz Multiplication MHz 4 5 MODCK H MODCK 1 3 tow Factor Factor 0000_110 50 0 160 0 2 5 0000_111 41 7 160 0 2 3 5 Full Configuration Modes 2 0001_000 62 5 167 0 125 0 334 0 4 250 0 668 0 0001_001 50 0 167 0 2 100 0 334 0 5 250 0 835 0 0001_010 50 0 167 0 2 100 0 334 0 6 300 0 1002 0 0001 011 Reserved 0001_100 Reserved 0001 101 62 5 133 3 3 187 5 400 0 4 250 0 533 3 0001_110 50 0 133 3 3 150 0 400 0 5 250 0 666 7 1000_111 45 5 133 3 3 136 4 400 0 5 5 250 0 733 3 0001 111 417 133 3 3 125 0 400 0 6 250 0 800 0 0010 000 Reserved 0010 001 Reserved 0010 010 62 5 100 0 4 250 0 400 0 4 250 0 400 0 0010 011 50 0 100 0 4 200 0 400 0 5 250 0 500 0 0010 100 41 7 100 0 4 166 7 400 0 6 250 0 600 0 0010 101 35 7 100 0 4 142 9 400 0 7 250 0 700 0 0010 110 31 3 100 0 4 125 0 400 0 8 250 0 800 0 0010 111 Reserved 0011 000 50 0 80 0 5 250 0 400 0 5 250 0 400 0 0011 001 41
6. 4 6 4 6 System Clock Control Register 22 2 2 2 4 9 4 7 system Clock Mode Register SCMB cero 4 10 5 1 Internal RAM Block DIBSPAHE eta P ibi tolam eain edhe 5 2 5 2 Instruction RAM Partitioning dot oett dut ade etnia 5 3 5 3 Internal Data RAM Memory Map rennes eio te Paene eia ok ed eamus ees ene bdo leo e 5 4 5 4 RISC Controller Configuration Register RCCR eere 5 7 5 5 CP Command Register CPCR des RATER YE 5 9 6 1 CPM Low Interrupt Priority Register SCPRR L eee 6 2 6 2 SIU Interrupt Pending Register 5 1 22 6 3 6 3 SIU Interrupt Mask Register SIM B canes 6 4 6 4 Bus Configuration Register 2 6 5 7 1 USB Ote de 7 3 7 2 USB Function Block Diagratn 7 5 7 3 USB Controller Operating Modes no feo 7 6 7 4 USB Controller Block Diagram ashe A Hae 7 9 7 5 USB Controller Operating Modes essen 7 10 7 6 External Request OBHegPALIGEL eei o es e etl ot ee 7 12 7 7 Endpoint Pointer Registers
7. 4 18 4 9 Clock Configurations for PCI Agent Mode PCI 0 4 22 4 10 Clock Configurations for PCI Agent Mode PCI 1 4 25 5 1 Parameter RAM cack ci tents cot erat oL dn LE aa 5 6 5 2 RISC Controller Configuration Register Field Descriptions esses 5 7 5 3 CP Command Register Field Descriptions 41 04 41121 020 4 0 3 4 0 3 4 5 10 5 4 CPCommand GOpeoues sies acento eee 5 11 5 5 Command Description T M 5 12 6 1 Interrupt Source Priority Devels Eo deo 6 1 6 2 Encoding the Interrupt VeGtor 6 2 6 3 SC PR RTs Descriptions d onere 6 3 6 4 BCR Eield DOsCEIUGOHS o era necs ee 6 5 7 1 USB Pins 7 4 7 2 USB TOKens ueni obeunt Ld A act deer 7 7 7 3 USB TOKENS adage 7 11 7 4 USB Parameter RA MENG ad ed ie 7 13 7 5 Parameter BICK let at p E amete eade pner 7 14 7 6 FRAME N Field Descri pions oae dieti beo edet aues apice leds 7 15 7 7 FRAME_N Field DESCripti Ons
8. Bits Name Description 21 EXDD External master delay disable Generally the MPC8280 adds one clock cycle delay for each external master access to a region controlled by the memory controller This occurs because the external master drives the address on the external pins compared to internal master like MPC8280 s DMA which drives the address on an internal bus in the chip Thus it is assumed that an additional cycle is needed for the memory controllers banks to complete the address match However in some cases when the bus is operated in low frequency this extra cycle is not needed The user can disable the extra cycle by setting EXDD This bit is similar to BCR DAM but with opposite polarity 0 The memory controller inserts one wait state between the assertion of TS and the assertion of CS when external master accesses an address space controlled by the memory controller 1 The memory controller asserts CS on the cycle following the assertion of TS by external master accessing an address space controlled by the memory controller 22 LPLDP Local bus pipeline maximum depth See Section 8 4 5 Pipeline Control of the MPC8260 PowerQUICC II User s Manual 0 The local bus pipeline maximum depth is one 1 The local bus pipeline maximum depth is zero 23 25 Reserved should be cleared 26 SPAR Slave parity check If set enables parity check on 60x bus transactions to the MPC8280 s internal memory space
9. MOTOROLA Chapter 9 Parallel I O Ports PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com MPHY address pins 3 and 4 master mode can come from FCC2 depending on CMXUAR programming See MPC8260 PowerQUICC II User s Manual Section 15 4 1 CMX UTOPIA Address Register MPHY address pins 0 4 slave mode can come from FCC2 depending on CMXUAR programming See MPC8260 PowerQUICC II User s Manual Section 15 4 1 CMX UTOPIA Address Register Available only when the primary option for this function is not used 9 14 Freescale Semiconductor Inc MPC8280 PowerQUICC II Specification PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com MOTOROLA
10. eere 6 2 SIU Interrupt Pending Register SIPNR D eoo odes egt 6 3 SIU Interrupt Mask Register SIM 6 4 Bus Configuration lt lt aa Eve AHS 6 4 Chapter 7 Universal Serial Bus Controller USB Inteeration um the 6280 3 asper vede darter on et pow edes 7 1 Overview ntum nx ont Nt I te II E 7 1 USB Controller Features sees eee enne i 7 2 Host Controller 8 221 2 41 000 000000000000 0 7 2 USB Controller Pin Functions and Clocking eese 7 3 USB P ncuon 8 1 eee 7 4 USB Function Controller Transmit Receive 00 0 7 5 USE Hest DOSCEIDEDD A tede ease een eet 7 8 USB Host Controller 2000 0 1 7 9 SOF Transmission for USB Host Controller 0000000 1 7 12 USB Function and Host Parameter RAM Memory 7 13 End Point Parameters Block Pointer 7 13 Frame Number BERAMIE IN iio eee exi oett poet cose dc a Ee 7 15 USB Function Code Registers RFCR and 2 2 2 7 16 USB Function Programming Model essere 7 17 USB
11. Offset Bit Name Description 2 W Wrap Final BD in Table 0 This is not the last BD in the Rx BD table 1 This is the last BD in the Rx BD table After this buffer has been used the CP will receive incoming data into the first BD in the table the BD pointed to by RBASE The number of Rx BDs in this table is programmable and is determined only by the W bit and the overall space constraints of the dual port RAM 3 Interrupt 0 No interrupt is generated after this buffer has been filled 1 The RXB bit in the USB event register will be set when this buffer has been completely filled by the CP indicating the need for the CPU core to process the buffer The RXB bit can cause an interrupt if it is enabled 4 L Last This bit is set by the USB controller when the buffer is closed due to detection of end of packet condition on the bus or as a result of error Written by the USB controller after the received data has been placed into the associated data buffer 0 Buffer does not contain the last byte of the message 1 Buffer contains the last byte of the message 5 F First This bit is set by the USB controller when the buffer contains the first byte of a packet Written by the USB controller after the received data has been placed into the associated data buffer 0 Buffer does not contain the first byte of the message 1 Buffer contains the first byte of the message 6 7 Reserved should be cleared 8 9 Packet ID Th
12. aet es 7 16 7 8 RPCR and TECR Fields ied i eget to ee t peii he ett Do epit ee eie ugs 7 16 7 9 USMOD Rie sk 7 18 7 10 US ADR Biells 5 M 7 18 7 11 Uic urs I LEE 7 19 7 12 NISC OM Fieldsi pato i estote Samoa ia tad fo 7 20 7 13 HSBER Fields a cua dI eiui Me 7 21 MOTOROLA Tables vii PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Table Number 7 14 7 15 7 16 7 17 7 18 7 19 8 1 8 2 8 3 8 4 8 5 8 6 8 7 9 1 9 2 9 3 9 4 viii Freescale Semiconductor Inc Tables Page Title Number USBS M aatia ecg ates ease ous re is 7 22 USB RXBD Fields m 7 24 USB F nction TA iot iiie peat 7 26 USB Host Tx BD Fields iactat ei EU MERIT R SENE 7 28 USB Controller Transmission tne Peor ent Pub Riv etn edes ents 7 30 USB Controller Reception Errors eds 7 31 GPEMRx Field DeSCPIDLUODS 8 2 FPSMR Ethernet Field Descriptions ca ae 8 3 FIRPERx Field Descriptions TIREM 1 8 7 FIRERx Field Des
13. Freescale Semiconductor Inc SIU Interrupt Mask Register SIMR L 6 5 SIU Interrupt Mask Register SIMR L NOTE Reference Documentation This section replaces the description of SIMR L in Section 4 3 1 5 SIU Interrupt Mask Registers of the 8260 PowerQUICC User s Manual Note the addition of SIMR L TC Figure 6 3 shows SIMR L fields 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 Reset 0000 0000 0000 0000 R W R W Addr 0x10C20 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 el ac ser er p oca ome ow ona owe soma vse ess were Tres Reset 0000 0000 0000 0000 R W R W Addr 0x10C22 Figure 6 3 SIU Interrupt Mask Register SIMR_L 6 6 Bus Configuration Register BCR NOTE Reference Documentation This section replaces the description of BCR in Section 4 3 2 1 Bus Configuration Register in the MPC8260 PowerQUICC II User s Manual Note the addition of BCR 9 10 and 22 The bus configuration register BCR shown in Figure 6 4 contains configuration bits for various features and wait states on the 60x bus 6 4 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Configuration Register BCR 0 1 3 4 5 7 8 9 10 11 12 13 14 15 Field APD L2C L2D PLDP DREF DAM EAV
14. The USB peripheral and SCC4 are mutually exclusive it is not legal to enable both peripherals at the same time The USB controller pins are multiplexed with SCC4 pins in the parallel IO Refer to Chapter 9 Parallel I O Ports The user programs the parallel I O registers as if SCC4 was being used If the USB controller is enabled the signals are automatically routed to the USB controller instead of SCC4 The USB controller uses the transmit clock of SCC4 as its clock The user must program CMXSCR TS4CS refer to Section 15 4 5 in the MPC8260 PowerQUICC II User s Manual to the desired source for USB when the USB controller is enabled The user must clear CMXSCR SCA refer to Section 15 4 5 in the MPC6260 PowerQUICC II User s Manual when the USB controller is enabled 7 2 Overview The universal serial bus USB is an industry standard extension to the PC architecture The USB controller on the MPC8280 supports data exchange between a wide range of simultaneously accessible peripherals Attached peripherals share USB bandwidth through a host scheduled token based protocol The USB physical interconnect is a tiered star topology and the center of each star is a hub Each wire segment is a point to point connection between the host and a hub or function or a hub connected to another hub or a function The USB transfers signal and power over a four wire cable and the signalling occurs over two wires and point to point
15. Addition of two breakpoint control registers DBCR and IBCR For more information on the execution units refer to the G2 Core User s Manual G2CORE D MOTOROLA Chapter 2 Embedded MPC603e Core 2 3 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com 2 4 Freescale Semiconductor Inc MPC8280 PowerQUICC II Specification PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Chapter 3 Memory Map The MPC8280 s internal address space is mapped within a contiguous block of memory This 256 Kbyte block on the MPC8260 this block is 128 Kbytes within the global 4 Gbyte real memory can be mapped on 256 Kbytes resolution through an implementation specific special register the internal memory map register IMMR Refer to Section 3 1 Internal Memory Map Register IMMR Table 3 1 lists only registers new on the MPC8280 NOTE Reference Documentation The following table supplements Table 3 1 Internal Memory Map in the MPC6260 PowerQUICC II User s Manual Table 3 1 Internal Memory Map Additional Registers Internal Address Abbreviation Name Size Section CPM Dual Port RAM DPRAM 00000 03FFF DPRAM1 Dual port data BD RAM 16 Kbytes Chapter 5 04000 07FFF Reserved
16. PowerQUICC II User s Manual 6 3 CPM Low Interrupt Priority Register SCPRR L NOTE Reference Documentation This section replaces the description of SCPRR_L in Section 4 3 1 3 CPM Interrupt Priority Registers of the 8260 PowerQUICC II User s Manual Note the change in the description of SCPRR_L YC1P 100 the status of all other bits is unchanged SCPRR_L register shown in Figure 6 1 defines prioritization of SCCs and the TC layer 0 2 3 5 6 8 9 11 12 15 Field YCAP YC2P YC4P Reset 000 001 010 011 0000 R W R W Addr 0 10 18 16 18 19 21 22 24 25 27 28 31 Field YC5P YC6P YC7P YC8P Reset 100 101 110 111 0000 R W R W Addr 0x10C20 Figure 6 1 CPM Low Interrupt Priority Register SCPRR L Table 6 3 describes SCPRR_L fields 6 2 MPC8280 PowerQUICC II Specification PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc IU Interrupt Pending Register SIPNR L Table 6 3 SCPRR L Field Descriptions Bits Name Description YC1P YCC1 Priority order Defines which SCC asserts its request in the YCC1 priority position Do not program the same SCC to multiple priority positions This field can be changed dynamically 000 001 010 011 100 SCC1 asserts its request in the YCC1 position SCC2 asserts its reques
17. Underrun Indicates that the USB encountered a transmitter underrun condition while sending the buffer Reserved should be cleared 0x02 0x04 0 31 Data length Tx data buffer pointer The data length is the number of octets that the CP should transmit from this BD s data buffer It is never modified by the CP This value should normally be greater than zero The transmit buffer pointer which always points to the first location of the associated data buffer may be even or odd The buffer may reside in either internal or external memory Data length the second half word of a TxBD is the number of octets the CP should send from this BD s data buffer It is never modified by the CP MOTOROLA Chapter 7 Universal Serial Bus Controller 7 27 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com l _ Freescale Semiconductor Inc USB Buffer Descriptor Ring Tx buffer pointer the third and fourth half words of a TxBD always points to the first location of the buffer in internal or external memory The pointer may be even or odd 7 6 3 USB Transmit Buffer Descriptor Tx BD for Host Data to be transmitted with the USB to the CP by is arranged in buffers referenced by the Tx BD ring The first word of the Tx BD contains status and control bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
18. 7 14 7 8 Frame Number FRAME N in Function Mode seen 7 15 7 9 Frame Number FRAME N in Function Mode sse 7 16 7 10 USB Function Code Registers RFCR and TFCR eee 7 16 7 11 USB Mode Register CUSMOB HE belg Bit us 7 17 7 12 USB Slave Address Register USADR 7 18 7 13 USB End Point Registers USEPI USEPA eese 7 19 7 14 USB Command Register USCONMD ie atiende 7 20 7 15 USB Event Register USBER cu tiec a Bl Bless 7 21 7 16 USB Status Register USES chs 7 22 7 17 USB Memory SUUCITe siae trap i EY near 7 23 MOTOROLA Figures ix PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Figure Number 7 18 7 19 7 20 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 Freescale Semiconductor Inc Figures Page Title Number USB Receive Buffer Descriptor Rx BD ee e dn 7 24 USB Transmit Buffer Descriptor Tx See eee Cae 7 26 USB Transmit Buffer Descriptor TX BD eese 7 28 General FCC Expansion Mode Register 8 1 FCC Ethernet Mode 8 2 Connecting the MPC8280 to Ethernet RMIT eene 8 4 FCC T
19. 8 11 Internal Rate Programming Model eee 8 11 Chapter 9 Parallel I O Ports Table of Contents PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Paragraph Number vi Freescale Semiconductor Inc Contents Title MPC8280 PowerQUICC II Specification PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Page Number MOTOROLA Freescale Semiconductor Inc Tables Table Page Number Title Number 1 1 HiP7 PowerQUICC II Device Packages uccisi aeneae tes tuae xn eee ee 1 1 3 1 Internal Memory Map Additional Registers eee 3 1 3 2 IMME Field DescEIDEOBS ett oce ead dels 3 3 4 1 Dedicated PIER 4 5 4 2 Hard Reset Configuration Word Field Descriptions 4 6 4 3 SCCR Field Descriptions esa ite e s essaie 4 9 4 4 SCMR Field DesctipHODS xs ree tS Des 4 10 4 5 MPC8280 Clocking Modes entr neta eX e aaa 4 11 4 6 local Bus Clock Modes obe ates ok ave ee uides 4 1 4 7 Clock Configurations for PCI Host Mode PCI 0 4 15 4 8 Clock Configurations for PCI Host Mode PCI 1
20. DEM12 DEM34 DR4QP Reset 0000 0000 0000 0000 R W R W Addr 0X119C6 Figure 5 4 RISC Controller Configuration Register RCCR RCCR bit fields are described in Table 5 2 Note that unless otherwise stated all cross references are to the 8260 PowerQUICC II User s Manual Table 5 2 RISC Controller Configuration Register Field Descriptions Bits Name Description 0 TIME Timer enable Enables the CP internal timer that generates a tick to the CP based on the value programmed into the TIMEP field TIME can be modified at any time to start or stop the scanning of the RISC timer tables 1 MCCPR MCC request priority Controls the priority of the MCCs in relation to the other communication peripherals See Table13 2 Peripheral Prioritization for more information 0 Original CPM priority scheme MCCx priority behaves according to Table 13 2 1 MCC priority remains at emergency level priority level 4 2 7 TIMEP Timer period controls the CP timer tick The RISC timer tables are scanned on each timer tick and the input to the timer tick generator is the general system clock 133 166MHZ divided by 1 024 The formula is TIMEP 1 x 1 024 general system clock period Thus a value of 0 stored in these bits gives a timer tick of 1 x 1 024 1 024 general system clocks and a value of 63 decimal gives a timer tick of 64 x 1 024 65 536 general system clocks MOTOROLA Chapter 5 Internal M
21. FTIRR1 GRPO 0 11310 FTIRR1_GRP1 0x1131E FTIRR1_GRP2 0x1131F FTIRR1_GRP3 0x1133C FTIRR2 0x1133D FTIRR2 GRP1 0x1133E FTIRR2 GRP2 0x1133F FTIRR2 GRP3 Figure 8 8 FCC Transmit Internal Rate Register FTIRR Table 8 7 describes FTIRRx fields 8 10 MPC8280 PowerQUICC II Specification PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc ATM Registers Table 8 7 FTIRRx Field Descriptions Bit Name Description 0 TRM PHY transmit mode 0 0 External rate mode 1 Internal rate mode TRM Group transmit mode 1 0 Group rate timer x disabled 1 Internal rate timer for Group x is enabled and division factor is set by Initial Value field 1 7 Initial Value The initial value of the internal rate timer A value of Ox7F produces the minimum clock rate BRG CLK divided by 128 0x00 produces the maximum clock rate BRG CLK divided by 1 Figure 8 9 shows how transmit clocks are determined PHY O0 Int rate timer L PHY 0 or GRP 0 Tx Rate L PHY 1 Int rate timer L PHY 1 or GRP 1Tx Rate BRG 1 PHY 2 Int rate timer PHY 2 or GRP 2 Tx Rate L PHY 83 Int rate timer LL PHYS or GRP 3 Tx Rate Figure 8 9 FCC Transmit Internal Rate Clockin
22. MOTOROLA Chapter 7 Universal Serial Bus Controller 7 33 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Programming the USB Host Controller e For low speed transactions with an external hub set TxBD LSP in the token s BD This causes the USB host controller to generate a preamble PRE token at full speed before changing the transmit rate to low speed and sending the data packet After completion of the transaction the host returns to full speed operation Note that LSP should be set only for token BDs 7 10 1 USB Host Controller Initialization Example The following is a local loopback example initialization sequence for the USB controller operating as a host It can be used to set up endpoints 0 and 1 to fill up transmit FIFOs to demonstrate an IN token transaction Program CMXSCR to provide a 48 MHz clock to the USB controller Clear PDIRD 22 and set PPARD 22 to select USBRXD Clear PDIRC 8 9 and set PPARC 8 9 to select USBRXP and USBRXN Set PDIRD 20 21 and PPARD 20 21 to select USBTXP and USBTXN Set PDIRC 20 and PPARC 20 to select USBOE Write DPRAM 0x500 to EPOPTR DPRAM 0x520 to EPIPTR to set up the endpoint pointers 7 Write 0 000 0000 to DPRAM 0x00 to set up the RxBD Status and Control Data Length fields of endpoint 0 8 Write DPRAM 0x100 to DPRAM 0x04 to set up the RxBD Buffer Pointer field
23. SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 USB Function Controller Initialization Example Table 7 19 USB Controller Reception Errors Error Description Overrun Error If the 16 byte receive FIFO overruns the previously received byte is overwritten The controller closes the buffer and sets both RxBD OV and USBER RXB For USB function mode the NAK handshake is sent after the end of the received packet if the packet was received error free Busy Error A frame was received and discarded due to lack of buffers The controller sets USBER BSY Non Octet Aligned If this error occurs the controller writes the received data to the buffer closes the buffer and sets Packet both RxBD NO and USBER RXB CRC Error When a CRC error occurs the controller closes the buffer and sets both RxBD CR and an error occurs USBER RXB In isochronous mode USEPn TM 0611 the USB controller reports a CRC error however there are no handshake packets ACK and the transfer continues normally when 7 9 USB Function Controller Initialization Example The following is an example initialization sequence for the USB controller operating in function mode It can be used to set up four function endpoints 0 3 to fill transmit FIFOs so that data is ready for transmission when an IN token is received from the USB The token can be generat
24. 0 Exceptions are vectored to the physical address 0x000n nnnn 7 ISPS Internal space port size Defines the initial value of BCR ISPS Setting ISPS configures the MPC8260 to respond to accesses from a 32 bit external master to its internal space See Section 4 3 2 1 Bus Configuration Register in the MPC8260 PowerQUICC User s Manual 8 9 2 12 cache pins configuration Defines the initial value of SIUMCR L2CPC See Section 4 3 2 6 SIU Module Configuration Register SIUMCR in the MPC8260 PowerQUICC User s Manual 10 11 DPPC Data parity pin configuration Defines the initial value of SIUMCR DPPC For more details refer to Section 4 3 2 6 SIU Module Configuration Register SIUMCR in the MPC8260 PowerQUICC II User s Manual 12 PLLBP bypass 0 Normal operation 1 Bypass CPM PLL 13 15 ISB Initial internal space base select Defines the initial value of IMMR 0 14 and determines the base address of the internal memory space 000 0x0000_0000 001 0 00 0 0000 010 0 0 00 0000 011 OxOFFO 0000 100 0 000 0000 101 OxFOFO 0000 110 OxFFOO 0000 111 OxFFFO 0000 See Section 4 3 2 7 Internal Memory Map Register IMMR in the MPC8260 PowerQUICC II User s Manual 16 BMS Boot memory space Defines the initial value for BRO BA There are two possible boot memory regions HIMEM and LOMEM 0 0 00 0000 0xFFFF FFFF 1 0x0000 0000 0x01FF FFFF See Section 10 3 1 Base Registers BRx 17 B
25. 400 0 400 0 533 3 0101_000 0101_001 0101_010 PCI host mode PCI_MODCK 1 only refer to Table 4 8 0101 011 2 125 0 133 3 4 250 0 266 6 0101 100 2 111 1 133 3 4 5 250 0 300 0 0110 000 0110 001 0110 010 0110 011 0110 100 0110 101 0110 110 0111 000 Reserved 0111 001 3 150 0 200 0 3 150 0 200 0 0111 010 PCI host mode PCI_MODCK 1 only refer to Table 4 8 0111 011 3 187 5 200 0 4 250 0 266 6 0111 100 3 166 7 200 0 4 5 250 0 300 0 1000_000 Reserved 1000_001 3 3 4 1000_010 3 3 5 4 1000_011 3 4 4 1000_100 3 4 5 4 1000_101 3 6 4 1000_110 66 7 88 9 3 200 0 266 6 6 5 433 3 577 7 4 50 0 66 7 1001_000 57 1 76 2 3 5 200 0 266 6 2 5 142 9 190 5 4 50 0 66 7 1001_001 57 1 76 2 3 5 200 0 266 6 3 171 4 228 5 4 50 0 66 7 1001_010 71 4 76 2 3 5 250 0 266 6 3 5 250 0 266 6 4 62 5 66 7 4 16 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Configuration Modes Table 4 7 Clock Configurations for PCI Host Mode PCI MODCK O 1 continued MODCK H MODCK 1 3 Bus Clock 4 MHz CPM Multiplication Facto
26. 611 1 3 83 3 111 1 4 24 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Configuration Modes Table 4 9 Clock Configurations for PCI Agent Mode PCI 0 continued Mode2 PCI Clock 3 CPM Clock CPU Clock Bus Clock 6 MHz CPM MHz CPU MHz Bus MHz t Multiplication Multiplication Division MODCK_H Factor Factor 5 Factor MODCK 1 3 low high low high low high low high 1100_000 50 0 66 7 2 100 0 133 3 Bypass 50 0 66 7 2 50 0 66 7 1100_001 50 0 66 7 3 150 0 200 0 Bypass 60 0 80 0 2 5 60 0 80 0 1100_010 50 0 66 7 3 150 0 200 0 Bypass 50 0 66 7 3 50 0 66 7 As shown in Table 4 5 PCI MODCK determines the PCI clock frequency range Refer to Table 4 10 for lower range configurations MODCK hard reset configuration word 28 31 Refer to Section 5 4 in the MPC8260 User s Manual MODOCK 1 3 three hardware configuration pins High and low indicate frequency limits for a given configuration CPM multiplication factor CPM clock bus clock CPU multiplication factor Core PLL multiplication factor 60x and local bus frequency Identical to CLKIN oun Table 4 10 Clock Configurations for PCI Agent Mode PCI 1 1
27. Addr 0x119D0 Figure 5 5 CP Command Register CPCR Table 5 3 describes CPCR fields MOTOROLA Chapter 5 Internal Multiported RAM DPRAM 5 9 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Command Set Freescale Semiconductor Inc Table 5 3 CP Command Register Field Descriptions Bit Name Description 0 RST Software reset command Set by the core and cleared by the CP When this command is executed RST and FLG bit are cleared within two general system clocks The CP reset routine is approximately 60 clocks long but the user can begin initialization of the CP immediately after this command is issued RST is useful when the core wants to reset the registers and parameters for all the channels FCCs SCCs SMCs SPI 2 MCC as well as the CP and RISC timer tables However this command does not affect the serial interface SI or parallel I O registers 1 5 PAGE Indicates the parameter RAM page number associated with the sub block being served See the SBC description for page numbers 6 10 5 Subblock code Set by the core to specify the subblock on which the command is to operate Subblock Code Page Subblock Code Page FCC1 01110 ATM transmit 00100 SPI 01010 01001 OPCODE 1010 10000 all other commands FCC2 01110 ATM transmit 00101 2 01011 01010 OPCODE 1010 10001 all
28. Data Length fields of endpoint 3 15 Write DPRAM 0x230 to DPRAM 0x3C to set up the TxBD Buffer Pointer field of endpoint 3 16 Write OXCAFE CAFE to DPRAM 0x200 to set up the endpoint 0 Tx data pattern 17 Write FACE to DPRAM 0x210 to set up the endpoint 1 Tx data pattern 18 Write to DPRAM 0x220 to set up the endpoint 2 Tx data pattern 19 Write CACE to DPRAM 0x230 to set up the endpoint 3 Tx data pattern 20 Write 0x2000 2020 to 0 500 to set up the RBASE and TBASE fields of the endpoint 0 parameter RAM 21 Write 0 1818 0100 to DPRAM 0x504 to set up the RFCR TFCR and MRBLR fields of the endpoint 0 parameter RAM 22 Write 0x2000 2020 to DPRAM 4 0x508 to set up the RBPTR and TBPTR fields of the endpoint 0 parameter RAM 23 Clear the TSTATE field of the endpoint 0 parameter RAM 24 Write 0x2008 2028 to DPRAM 0x520 to set up the RBASE and TBASE fields of the endpoint 1 parameter RAM 25 Write 0 1818 0100 to 0 524 to set up the RFCR TFCR and MRBLR fields of the endpoint 1 parameter RAM 26 Write 0 2008 2028 to DPRAM 0x528 to set up the RBPTR and TBPTR fields of the endpoint 1 parameter RAM 27 Clear the TSTATE field of the endpoint 1 parameter RAM 28 Write 0 2010 2030 to DPRAM 0x540 to set up RBASE and TBASE fields of the endpoint 2 parameter RAM 29 Write 0 1818 0100 to DPRAM 0x544 to set up the RFCR TFCR and MRBLR fields of the endp
29. In case of a parity error a core machine check is asserted and the error is reported in TESCR1 ISBE PAR and TESCR2 REGS DPR PCIO PCI 27 ISPS Internal space port size Defines the port size of MPC8280 s internal space region as seen to external masters Setting ISPS enables a 32 bit master to access MPC8280 internal space 0 MPC8280 acts as a 64 bit slave to external masters accesses to its internal space 1 MPC8280 acts as a 32 bit slave to external masters accesses to its internal space 28 31 Reserved should be cleared MOTOROLA Chapter 6 System Interface Unit 6 7 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Bus Configuration Register BCR 6 8 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 7 Universal Serial Bus Controller The universal serial bus USB controller allows the MPC8280 to communicate with other devices via a USB connection This chapter describes the MPC8280 s USB controller including basic operation the parameter RAM and registers It also provides programming examples for initializing host mode and function mode of the USB controller 71 USB Integration in the MPC8280 The following restrictions apply when enabling the USB controller in the MPC8280
30. LETM EPAR LEPAR Reset Depends on reset configuration sequence Refer to Section 4 3 1 1 Hard Reset Configuration Word R W R W 16 18 19 20 21 22 25 26 27 28 31 Field NPQM EXDD LPLDP SPAR ISPS Reset Depends on reset configuration sequence Refer to Section 4 3 1 1 Hard Reset Configuration Word R W R W Addr 0x10024 Figure 6 4 Bus Configuration Register BCR Table 6 4 describes BCR fields Table 6 4 BCR Field Descriptions Bits Name Description 0 EBM External bus mode 0 Single MPC8280 bus mode is assumed 1 60x compatible bus mode For more information refer to Section 8 2 Bus Configuration of the 8260 PowerQUICC II User s Manual 1 3 APD Address phase delay Specifies the minimum number of address tenure wait states for address operations initiated by a 60x bus master BCR APD specifies the minimum number of address tenure wait states for address operations initiated by 60x bus devices APD indicates how many cycles the MPC8280 should wait for ARTRY but because it is assumed that ARTRY can be asserted by other masters only on cacheable address spaces APD is considered only on transactions that hit one of the 60x assigned memory controller banks and have the GBL signal asserted during address phase 4 L2C Secondary cache controller See Chapter 11 Secondary L2 Cache Support of the MPC8260 PowerQUICC II User s Manual 0 No secondary cache controller is
31. N N ENDPOINT 1 X RX BUFFER DESCRIPTORS RX BD TABLE E N FRAME STATUS DATA LENGTH Y ENDPOINT4RXBD TABLE WE e VO RX BUFFER DESCRIPTORS EP1 RX BD ee TABLE POINTER TX BD TABLE POINTER FRAME STATUS DATA LENGTH RX DATA BUFFER EP4 RX BD DATA POINTER 1 5 TABLE POINTER EP4 TX BD TABLE POINTER Figure 7 17 USB Memory Structure MOTOROLA 7 Universal Serial Bus Controller 7 23 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com l _ Freescale Semiconductor Inc USB Buffer Descriptor Ring 7 6 1 USB Receive Buffer Descriptor Rx BD for Host and Function The CP reports information about each buffer of received data using Rx BDs The CP closes the current buffer generates a maskable interrupt and starts receiving data in the next buffer when the current buffer is full Additionally it closes the buffer on the following conditions e End of packet detected e Overrun error occurred Bit stuff violation detected As shown in Figure 7 18 the first word of the Rx BD contains status and control bits These bits are prepared by the user before reception and are set by the CP after the buffer has been closed The second word contains the data length in bytes that was received The third and fourth words contain a pointer that always points to the beginning of the received data buffer The Rx
32. PowerQUICC II User s Manual 2 CDIS Core disable Defines the initial value for the SIUMCR CDIS 0 The core is active See Section 4 3 2 6 SIU Module Configuration Register SIUMCR in the MPC8260 PowerQUICC II User s Manual 1 The core is disabled In this mode the MPC8280 functions as a slave 4 6 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PLL Pins Table 4 2 Hard Reset Configuration Word Field Descriptions continued Bits Name Description 3 EBM External bus mode Defines the initial value of BCR EBM See Section 4 3 2 1 Bus Configuration Register in the MPC8260 PowerQUICC II User s Manual 4 5 BPS Boot port size Defines the initial value of BRO PS the port size for memory controller bank 0 00 64 bit port size 01 8 bit port size 10 16 bit port size 11 32 bit port size See Section 10 3 1 Base Registers BRx in the MPC8260 PowerQUICC II User s Manual 6 Core initial prefix Defines the initial value of MSR IP Exception prefix The setting of this bit specifies whether an exception vector offset is prepended with Fs or Os In the following description nnnnn is the offset of the exception vector 0 MSR IP 1 default Exceptions are vectored to the physical address OXFFFn nnnn 1 MSR IP
33. for IDMA S 4 See Section 18 7 2 DONEx in the MPC8260 PowerQUICC II User s Manual DONE 3 4 asserts as follows 0 High to low change 1 Low to high change MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Command Set 5 3 Command Set NOTE Reference Documentation This section replaces Section 13 4 in the 8260 PowerQUICC II User s Manual It includes additional commands for the universal serial bus USB The core issues commands to the CP by writing to the CP command register CPCR The CPCR rarely needs to be accessed For example to terminate the transmission of an SCC s frame without waiting until the end a STOP TX command must be issued through the CP command register CPCR 5 3 1 CP Command Register CPCR When the core issues a command and the CP clears CPCR FLG after completing the command thus indicating to the core that it is ready for the next command the core should set CPCR FLG Subsequent commands to the CPCR can be given only after FLG is cleared However the software reset command issued by setting CPCR RST does not depend on the state of CPCR FLG but the core should still set FLG when setting RST 0 1 5 6 10 11 14 15 Reset 0000 0000 0000 0000 R W R W Addr 0x119CE 16 17 18 25 26 27 28 31 Field MCN OPCODE Reset 0000 0000 0000 0000 R W R W
34. 0x113AA FIRSR2 HI 0x113CA FIRSR3_HI Figure 8 6 FCC Internal Rate Selection Register HI FIRSRx HI Table 8 5 describes FIRSRx HI fields Table 8 5 IRSRx HI Field Descriptions TIREM 1 Bit Name Description 0 31 GSy Group select for PHY y 00 transmit internal rate for PHY address y is controlled by FTIRRx GRPO 01The transmit internal rate for PHY address y is controlled by FTIRRx GRP1 10The transmit internal rate for PHY address y is controlled by FTIRRx GRP2 11The transmit internal rate for PHY address y is controlled by FTIRRx GRP3 Field Reset R W Addr Field Reset R W Addr Table 8 MOTOROLA 18 19 20 21 22 23 24 25 26 27 28 29 30 GS24 GS25 GS26 GS27 GS28 GS29 GS30 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000_0000_0000_0000 R W 0x1138C FIRSR1_HI 0x113AC FIRSR2 HI 0x113CC FIRSR3_HI 16 1 81 0000 0000 0000 0000 R W 0x1138E FIRSR1 HI 0x113AE FIRSR2 HI 0x113CE FIRSR3_HI Figure 8 7 FCC Internal Rate Selection Register LO FIRSRx LO 6 describes FIRSRx LO fields Chapter 8 Fast Communication Controller FCC PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com ATM Registers Freescale Semiconductor Inc Table 8 6 FIRSRx_LO Field Descriptions TIREM 1 Bit Name Description 0 29 GSy Group select for PHY y OOThe transmit internal rate for PHY address y
35. 16 Kbytes 08000 0BFFF DPRAM2 Dual port data BD RAM 16 Kbytes Chapter 5 OCOO0O OFFFF Reserved 16 Kbytes 20000 27FFF DPRAM3 Dual port instructionRAM 32 Kbytes Chapter 5 Registers 1131 11 1 FTIRRx FCC transmit internal rate register 8 bits 8 6 5 11380 FIRPER1 internal rate port enable register 32 bits 8 6 2 11384 FIRER1 internal rate event register 32 bits 8 6 3 11388 FIRSR1 HI FCC1 internal rate selection register HI part 32 bits 8 6 4 1138C FIRSR1 LO FCC 1 internal rate selection register LO part 32 bits 8 6 4 11390 GFEMR1 General FCC1 expansion mode register 8 bits 8 2 FCC2 Registers 1133 1133 FTIRRx FCC transmit internal rate register 8 bits 8 6 5 113A0 FIRPER2 FCC2 internal rate port enable register 32 bits 8 6 2 MOTOROLA Chapter 3 Memory Map 3 1 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Internal Memory Map Register IMMR Table 3 1 Internal Memory Map Additional Registers continued Internal Address Abbreviation Name Size Section 113A4 FIRER2 FCC2 internal rate event register 32 bits 8 6 3 113A8 FIRSR2 HI FCC2 internal rate selection register HI part 32 bits 8 6 4 113AC FIRSR2 LO FCC2 internal rate selection register LO part 32 bits 8 6 4 113B0 GFEMR2 General FCC2 expansion mode register 8 bits 8 2 FCC3 Registers 113DO GFEMR3 General FCC3 expansion mode register 3
36. 2 5 156 3 400 0 4 250 0 640 0 0111_000 55 6 160 0 2 5 138 9 400 0 4 5 250 0 720 0 0111 001 Reserved 0111 010 Reserved 0111_011 41 7 133 3 3 125 0 400 0 3 125 0 400 0 0111_100 71 4 133 3 3 214 3 400 0 3 5 250 0 466 7 0111 101 62 5 133 3 3 187 5 400 0 4 250 0 533 3 0111 110 55 6 133 3 3 166 7 400 0 4 5 250 0 600 0 0111 111 Reserved 1000 000 Reserved 1000 001 Reserved 1000 010 71 4 114 3 3 5 250 0 400 0 3 5 250 0 400 0 1000 011 62 5 114 3 3 5 218 8 400 0 4 250 0 457 1 1000 100 55 6 114 3 3 5 194 4 400 0 4 5 250 0 514 3 1000 101 50 0 114 3 3 5 175 0 400 0 5 250 0 571 4 1000 110 45 5 114 3 3 5 159 1 400 0 5 5 250 0 628 6 1100 000 50 0 167 0 2 100 0 334 0 Bypass 50 0 167 0 MOTOROLA Chapter 4 PLL and Clock Generator 4 13 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Configuration Modes Table 4 6 Local Bus Clock Modes continued 2 3 3 3 Bus oe CPM iine CPU icis MHz Multiplication MHz Multiplication MHz 4 5 H MODCK 1 3 tow high Factor Factor 1100 001 Bypass 1100 010 33 3 133 3 3 100 0 400 0 Bypass 33 3 133 3 1101 000 Reserved E MODCK hard reset configuration word 28 31 Refer to Section 5 4 in the MPC8260 User s Manual MODCK 1 3 three hardware configuration pins 60x and local bus frequency
37. 400 0 3 200 0 400 0 3 66 7 133 3 0110_010 26 8 50 0 8 214 3 400 0 3 5 250 0 466 7 3 71 4 133 3 0110 011 25 0 50 0 8 200 0 400 0 4 266 7 533 3 3 66 7 133 3 0110_100 25 0 50 0 8 200 0 400 0 4 5 300 0 600 0 3 66 7 133 3 0111_000 25 0 50 0 6 150 0 300 0 2 150 0 300 0 2 75 0 150 0 0111_001 25 0 50 0 6 150 0 300 0 2 5 187 5 375 0 2 75 0 150 0 0111_010 25 0 50 0 6 150 0 300 0 3 225 0 450 0 2 75 0 150 0 0111_011 25 0 50 0 6 150 0 300 0 3 5 262 5 525 0 2 75 0 150 0 4 26 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Configuration Modes Table 4 10 Clock Configurations for PCI Agent Mode PCI MODCK 1 1 continued Mode PC Clock 3 CPM Clock CPU Clock Bus Clock 6 MHz CPM MHz CPU MHz Bus MHz Multiplication Multiplication Division MODCK_H Factor 4 Factor 5 2 Factor 2 MODCK 1 3 low high low high low high low high 1000 000 Reserved 1000 001 25 0 50 0 6 150 0 300 0 2 5 150 0 300 0 2 5 60 0 120 0 1000_010 25 0 50 0 6 150 0 300 0 3 180 0 360 0 2 5
38. 60 0 120 0 1000_011 29 8 50 0 6 178 6 300 0 3 5 250 0 420 0 2 5 71 4 120 0 1000 100 26 0 50 0 6 156 3 300 0 4 250 0 480 0 2 5 62 5 120 0 1000_101 25 0 50 0 6 150 0 300 0 4 5 270 0 540 0 2 5 60 0 120 0 1001 000 Reserved 1001 001 Reserved 1001 010 Reserved 1001_011 31 3 50 0 8 250 0 400 0 4 250 0 400 0 62 5 100 0 1001 100 27 8 50 0 8 222 2 400 0 4 5 250 0 450 0 4 55 6 100 0 1010 000 Reserved 1010 001 25 0 50 0 8 200 0 400 0 3 200 0 400 0 3 66 7 133 3 1010 010 26 8 50 0 8 214 3 400 0 3 5 250 0 466 7 3 71 4 133 3 1010 011 25 0 50 0 8 200 0 400 0 4 266 7 533 3 3 66 7 133 3 1010 100 25 0 50 0 8 200 0 400 0 4 5 300 0 600 0 3 66 7 133 3 1011 000 Reserved 1011_001 25 0 50 0 8 200 0 400 0 2 5 200 0 400 0 2 5 80 0 160 0 1011_010 25 0 50 0 8 200 0 400 0 3 240 0 480 0 2 5 80 0 160 0 1011 011 25 0 50 0 8 200 0 400 0 3 5 280 0 560 0 2 5 80 0 160 0 1011_100 25 0 50 0 8 200 0 400 0 4 320 0 640 0 2 5 80 0 160 0 1100 101 31 3 50 0 6 187 5 300 0 4 250 0 400 0 3 62 5 100 0 1100 110 27 8 50 0 6 166 7 300 0 4 5 250 0 450 0 3 55 6 100 0 1100 111 25 0 50 0 6 150 0 300 0 5 250 0 500 0 3 50 0 100 0 1101_000 25 0 50 0 6 150 0 300 0 5 5 275 0 550 0 3 50 0 100 0 1101_001 29 8 50 0 6 178 6 300 0 3 5 250 0 420 0 2 5 71 4 120 0 1101 010 26 0 50 0 6 156 3 300 0 4 250 0 480 0 2 5 62 5 120 0 MOTOROLA Chapter 4 PLL and Clo
39. 66 7 2 0000_010 50 0 66 7 3 0000_011 62 5 66 7 3 0000_100 50 0 66 7 3 0000 101 3 0000 110 53 6 66 7 4 0000 111 50 0 66 7 4 0001 001 Reserved 0001 010 Reserved 0001 011 Reserved 0001_100 62 5 66 7 2 125 0 133 3 8 250 0 266 6 4 31 3 33 3 0010_001 50 0 66 7 3 150 0 200 0 3 180 0 240 0 2 5 60 0 80 0 0010 010 59 5 66 7 3 178 6 200 0 3 5 250 0 280 0 2 5 71 4 80 0 0010_011 52 1 66 7 3 156 3 200 0 4 250 0 320 0 2 5 62 5 80 0 0010_100 50 0 66 7 3 150 0 200 0 4 5 270 0 360 0 2 5 60 0 80 0 0011 000 Reserved 0011 001 Reserved 0011 010 Reserved 0011 011 Reserved 0011 100 Reserved 0100 000 Reserved 0100_001 50 0 66 7 3 150 0 200 0 3 150 0 200 0 3 50 0 66 7 0100 010 Reserved 0100_011 62 5 66 7 3 187 5 200 0 4 250 0 266 6 3 62 5 66 7 0100_100 55 6 66 7 3 166 7 200 0 4 5 250 0 300 0 3 55 6 66 7 4 22 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Configuration Modes Table 4 9 Clock Configurations for PCI Agent Mode PCI 0 continued
40. 7 80 0 5 208 3 400 0 6 250 0 480 0 0011 010 35 7 80 0 5 178 6 400 0 7 250 0 560 0 0011 011 31 3 80 0 5 156 3 400 0 8 250 0 640 0 0011 100 Reserved 0011 101 Reserved 0011 110 41 7 66 7 6 250 0 400 0 6 250 0 400 0 0011 111 35 7 66 7 6 214 3 400 0 7 250 0 466 7 0100 000 31 3 66 7 6 187 5 400 0 8 250 0 533 3 4 12 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Configuration Modes Table 4 6 Local Bus Clock Modes continued 2 3 3 3 Bus CPU ie MHz Multiplication MHz Multiplication MHz 4 5 0101_101 62 5 167 0 2 125 0 334 0 2 125 0 334 0 0101_110 50 0 167 0 2 100 0 334 0 2 5 125 0 417 5 0101_111 50 0 167 0 2 100 0 334 0 3 150 0 501 0 0110_000 71 4 167 0 2 142 9 334 0 3 5 250 0 584 5 0110_001 62 5 167 0 2 125 0 334 0 4 250 0 668 0 0110_010 55 6 167 0 2 111 1 334 0 4 5 250 0 751 5 0110 011 Reserved 0110_100 50 0 160 0 2 5 125 0 400 0 2 5 125 0 400 0 0110 101 417 160 0 2 5 104 2 400 0 3 125 0 480 0 0110_110 71 4 160 0 2 5 178 6 400 0 3 5 250 0 560 0 0110_111 62 5 160 0
41. A2 L1RXD 0 Input nibble secondary option PD20 SCC4 RTS FCC1 RxD 2 A2 L1RSYNC SCC4 TENA UTOPIA 16 secondary option Ethernet USB TP MOTOROLA Chapter 9 Parallel I O Ports 9 11 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 9 4 Port D Dedicated Pin Assignment PPARD 1 continued Pin Function PSORD 0 PSORD 1 Pin _ _ Default x PDIRD 0 Input or Default PDIRD 1 Output PDIRD 0 Input Input PDIRD 1 Output Inout if Specified Input PD19 FCC1 TxAddr 4 1 FCC1 TxAddr 4 GND BRG1 BRGO SPI SPISEL PC1 MPHY master MPHY slave primary option multiplexed polling multiplexed polling FCC2 TxAddr 3 FCC1 32 MPHY master MPHY master direct multiplexed polling polling FCC2 TxAddr 0 MPHY slave multiplexed polling PD18 FCC1 RxAddr 4 FCC1 RxAddr 4 GND SPI SPICLK PC19 MPHY master MPHY slave Inout multiplexed polling multiplexed polling primary option FCC2 RxAddr 3 FCC1 RxClav32 MPHY master MPHY master direct multiplexed polling polling FCC2 RxAddr 0 MPHY slave multiplexed polling PD17 BRG2 BRGO FCC1 RxPrty PA5 SPI SPIMOSI UTOPIA Inout primary option PD16 FCC1 TxPrty 1 GND SPI SPIMISO SPIMO UTOPIA L1TSYNC GRANT Inout SI secondary option PD15 TDM C2 L1RQ
42. External Filter Capacitor XPC needed ct ec ide a rites System Clock Control Register 0 System Clock Mode Register SCMR seen Clock Configuration MOdes once edidi Local Bus Mode certon n pev Oo snares aban E ada rona tet tees Tableof Contents PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Page Number Paragraph Number 4 6 2 1 4 6 2 2 5 1 5 2 5 3 5 3 1 5 3 1 1 6 1 6 2 6 3 6 4 6 5 6 6 74 722 7 2 1 7 3 7 3 1 7 4 7 4 1 7 5 7 5 1 2 5 2 7 5 3 7 5 4 7 5 5 7 5 6 7 5 1 7 5 7 1 7 5 7 2 Freescale Semiconductor Inc Contents Page Title Number PChHosSCMOde oer tovc 4 14 PELA gent C36 at tu E ne ED 4 21 Chapter 5 Internal Multiported RAM DPRAM Parameter RAM e sere eve Per eo d oa Beak 5 5 RISC Controller Configuration Register esee 5 7 Command Sets ead ON OR S 5 9 CP Command R sister CPG RB 5 9 CP Commands ew nen sea BR I eh SS 5 11 Chapter 6 System Interface Unit USB Interrupt Priority sui aic esperes es cortan a 6 1 Interrupt Vector Generation and Calculation eene 6 1 CPM Low Interrupt Priority Register SCPRR L
43. FCC1 RxD 1 GND 12C I2ZCSDA Vpp UTOPIA 16 Inout PD14 TDM C2 L1CLKO FCC1 RxD 0 GND 12C I2CSCL GND UTOPIA 16 Inout PD13 SH L1ST1 B1 L1TXD GND Inout PD12 11 L1ST2 TDM B1 L1RXD GND Inout PD11 TDMB2 L1RQ FCC2 RxD 0 GND TDM B1 L1TSYNC GND UTOPIA 8 GRANT secondary option 10 TDMB2 L1CLKO FCC2 0 1 3 GND BRG4 BRGO B1 L1RSYNC GND UTOPIA 8 secondary option PD9 SMC1 SMTXD BRG3 BRGO FCC2 RxPrty GND UTOPIA 9 12 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 9 4 Port D Dedicated Pin Assignment PPARD 1 continued Pin Function PSORD 0 PSORD 1 Pin _ a PDIRD 0 Input or Default PDIRD 1 Output PDIRD 0 Input PDIRD 1 Output Inout if Specified Input PD8 FCC2 TxPrty SMC1 SMRXD BRG5 BRGO UTOPIA PD7 SMC1 SMSYN FCC1 TxAddr 3 FCC1 TxAddr 3 2 GND MPHY master MPHY slave multiplexed polling multiplexed polling FCC2 TxAddr 4 FCC1 22 MPHY master MPHY master direct multiplexed polling polling FCC2 TxAddr 1 MPHY slave multiplexed polling PD6 FCC1 TxD 4 IDMA1 DACK UTOPIA 16 PD5 FCC1 TxD 3 IDMA1 Vpp UTOPIA 16 Inout secondary option PD4 BRG8 BRGO TDM_D1 FCC3 RTS SMC2 SMRXD GND L1TSYNC GRANT secondary option secondary option 1
44. MODCK_H 0000 0000 000 100 0 133 3 2 5 125 0 0000 001 100 0 133 3 3 150 0 0000 010 150 0 200 0 3 180 0 0000 011 178 6 200 0 3 5 250 0 0000 100 0000 101 156 3 150 0 200 0 4 200 0 3 250 0 150 0 200 0 0000 110 PCI host mode PCI MODCK 1 only refer to Table 4 8 0000 111 3 187 5 200 0 4 250 0 266 6 Full Configuration Modes 0001_000 150 0 200 0 5 0001_001 0001_010 150 0 200 0 0001_011 0010_000 0010_001 0010_010 0010_011 0010_100 0010_101 0010_110 0011_000 0011_001 0011_010 0011_011 0100_000 0100_001 Reserved 0100_010 MOTOROLA Chapter 4 PLL and Clock Generator PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com 4 15 Freescale Semiconductor Inc Clock Configuration Modes Table 4 7 Clock Configurations for PCI Host Mode PCI MODCK O0 1 continued Bus Clock 4 CPM Clock CPU Clock PCI Clock MHz CPM MHz CPU MHz PCI MHz Multiplication Multiplication Division MODCK H Factor 5 MODCK 1 3 Factor 6 Factor low high low high 0100_011 300 0
45. NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 2 Embedded MPC603e Core The MPC8280 contains an embedded version of the MPC603e processor the G2 core This processor is backward compatible with the CPU core in previous devices in the PowerQUICC II family The G2 core s major features are the same throughout the PowerQUICC II family and are listed below enhancements to the G2 core specific to the MPC8280 follow High performance superscalar microprocessor core Up to three instructions issued and retired per clock Up to five instructions in execution per clock Single cycle execution for most instructions Pipelined FPU for all single precision and most double precision operations Five independent execution units and two register files BPU featuring static branch prediction 32 bit IU Fully IEEE 754 compliant FPU for both single and double precision operations LSU for data transfer between data cache and GPRs and FPRs SRU that executes condition register CR special purpose register SPR and integer add compare instructions Thirty two 32 bit GPRs for integer operands Thirty two 64 bit FPRs for single or double precision operands High instruction and data throughput Zero cycle branch capability branch folding Programmable static branch prediction on unresolved conditional branches Instruction fetch
46. OFFSET 0 R W 1 L TC LSP PID NAK STAL TO UN OFFSET 2 DATA LENGTH OFFSET 4 TX DATA BUFFER POINTER OFFSET 6 Figure 7 20 USB Transmit Buffer Descriptor Tx BD 2 Entries in boldface must be initialized by the user 2 All fields should be prepared by the user before transmission Table 7 16 describes USB TxBD fields Table 7 17 USB Host Tx BD Fields Offset Bit Name Description 0x00 0 R Ready bit after the buffer has been transmitted or after an error condition is encountered written by the user once this bit is set 0 The data buffer associated with this BD is not ready for transmission The user is free to manipulate this BD or its associated data buffer The CP clears this 1 The data buffer which has been prepared for transmission by the user has not been transmitted or is currently being transmitted No fields of this BD may be 1 Reserved should be cleared 2 W Wrap Final BD in Table 0 This is not the last BD in the Tx BD table 1 This is the last BD in the Tx BD table After this buffer has been used the CP will send data using the first BD in the table the BD pointed to by TBASEx The number of Tx BDs in this table is programmable and is determined only by the Tx BD W and the overall space constraints of the dual port RAM 3 l Interrupt 0 No interrupt is generated after this buffer has been serviced and TXE can cause interrupts if they are e
47. Supports both 12 and 1 5 Mbps data rates automatic generation of preamble token and data rate configuration Note that low speed operation requires an external hub Flexible data buffers with multiple buffers per frame Supports local loopback mode for diagnostics 12 Mbps only Supports USB slave mode e CPU Four independent endpoints support control bulk interrupt and isochronous data transfers CRC16 generation and checking 5 checking NRZI encoding decoding with bit stuffing 12 or 1 5 Mbps data rate Flexible data buffers with multiple buffers per frame Automatic retransmission upon transmit error Enhanced MMU with eight entry data and instruction BAT arrays providing 128 Kbyte to 256 Mbyte blocks Enhanced cache control 1 2 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor 8280 Architecture Overview 1 2 MPC8280 Architecture Overview NOTE Reference Documentation The following figure replaces Figure 1 1 the 8260 PowerQUICC II User s Manual Figure 1 1 shows the block diagram for the MPC8280 Shaded portions are device or package specific refer to the notes that follow 16 Kbytes I MMU System Interface Unit SIU lt lt 60x Bus G2 Core Bus Interface Unit 60x to PCI Bridge 6
48. clock multiplier ratios Three power saving modes doze nap and sleep Automatic dynamic power reduction when internal functional units are idle n system testability and debugging features through JTAG boundary scan capability Features specific to the G2 core on the MPC8280 are as follows Enhancements to the G2 core register set Additional HIDO bits Address bus enable ABE HIDO 28 Allows the G2 core to broadcast dcbf and dcbst onto the 60x bus Instruction fetch enable M IFEM HIDO 24 Allows the G2 core to reflect the value of the M bit during instruction translation onto the 60x bus HID2 register Enables true little endian mode the new additional BAT registers and cache way locking for the G2 core 2 2 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System version register SVR Identifies the specific version and revision level of the system on a chip integration Processor version register PVR Updated with a new value to identify the version and revision level of the processor Enhancements to cache implementation Instruction cache is blocked only until the critical load completes hit under reloads allowed Minimized stalls due to load delays The critical double word is simultaneously written to the cache and fo
49. following transaction is with the host or a full speed device 1 The following transaction is with a low speed device Required only for tokens Note that LSP should always be cleared in slave mode 8 9 Packet ID This bit field is valid for the first BD of a packet otherwise it is ignored 0X Do not append PID to the data 10 Transmit DATAO PID before sending the data 11 Transmit DATA1 PID before sending the data 10 Reserved should be cleared 11 received Indicates that the endpoint has responded with handshake The packet was received error free however the endpoint could not accept it 12 STAL STALL received Indicates that the endpoint has responded with a STALL handshake The endpoint needs attention through the control pipe 13 TO Time out Indicates that the endpoint failed to acknowledge the packet 14 UN Underrun Indicates that the USB encountered a transmitter underrun condition while sending the buffer 15 Reserved should be cleared 0x02 0 15 Data length The data length is the number of octets that the CP should transmit from this BD s data buffer It is never modified by the CP This value should normally be greater than zero 0x04 0 31 Tx data buffer The transmit buffer pointer which always points to the first location of the pointer associated data buffer may be even or odd The buffer may reside in either internal or external memory 1 Written b
50. function TIMEOUT RESET BCS Reset block check sequence Used BISYNC mode to reset the block check sequence calculation STOP See Section 24 9 MCC Commands the MPC8260 PowerQUICC User s Manual TRANSMIT MCC STOP See Section 24 9 MCC Commands the MPC8260 PowerQUICC User s Manual RECEIVE ATM See Section 29 14 ATM Transmit Command in the MPC8260 PowerQUICC User s Manual TRANSMIT RANDOM Generate a random number and put it in dual port RAM see RAND in Table 11 9 in the MPC8260 NUMBER PowerQUICC II User s Manual MOTOROLA Chapter 5 Internal Multiported RAM DPRAM 5 13 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Command Set 5 14 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 6 System Interface Unit This chapter describes changes related to interrupt support for the USB interface and the transmission convergence TC layer 6 1 USB Interrupt Priority NOTE Reference Documentation The following section supplements Table 4 2 in Section 4 2 2 Interrupt Source Priorities of the MPC8260 PowerQUICC II User s Manual Priority of an USB interrupt is between SDMA bus error and IDMA1 interrupts As shown in the following ta
51. of endpoint 0 9 Write 0 800 0003 to DPRAM 0x20 to set up the TxBD Status and Control Data Length fields of endpoint 0 10 Write DPRAM 0x200 to 0 24 to set up the TxBD Buffer Pointer field of endpoint 0 11 Write OXBC80 0003 to DPRAM 0x28 to set up the TxBD Status and Control Data Length fields of endpoint 1 12 Write DPRAM 0x210 to DPRAM 0x2C to set up the TXBD Buffer Pointer field of endpoint 1 13 Write 0x698560 to DPRAM 0x200 to set up the endpoint 0 Tx data pattern This pattern consists of the IN token and the 5 14 Write OXABCD 1234 DPRAM 0x210 to set up the endpoint 1 Tx data pattern 15 Write 0x2000 2020 to DPRAM 0x500 to set up the RBASE and TBASE fields of the endpoint 0 parameter RAM 16 Write 0 1818 0100 to DPRAM 0x504 to set up the TFCR and MRBLR fields of the endpoint 0 parameter RAM amp 7 34 8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor the USB Host Controller 17 Write 0x2000_2020 to DPRAM 0x508 to set up the RBPTR and TBPTR fields of the endpoint 0 parameter RAM 18 Clear the TSTATE field of the endpoint 0 parameter RAM 19 Write 0x2008_2028 to DPRAM 0x520 to set up RBASE and TBASE fields of the endpoint 1 parameter RAM 20 Write 0x1818_0100 to DPRAM 4 0x524 to set up the
52. on the MPC8280 ISB is 14 bits on the MPC8260 it is 15 bits 14 15 Reserved should be cleared 16 23 PARTNUM Part number This read only field is mask programmed with a code corresponding to the part number of the part on which the SIU is located It is intended to help factory test and user code which is sensitive to part changes This changes when the part number changes For example it would change if any new module is added or if the size of any memory module is changed It would not change if the part is changed to fix a bug in an existing module The part number for the MPC8280 is 24 31 MASKNUM Mask number This read only field is mask programmed with a code corresponding to the mask number of the part on which the SIU is located It is intended to help factory test and user code which is sensitive to part changes It is programmed in a commonly changed layer and should be changed for all mask set changes The first revision of the MPC8280 has 0x00 in this field The value of this field is changed every revision of the device MOTOROLA Chapter 3 Memory Map 3 3 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Internal Memory Map Register IMMR 3 4 MPC8280 PowerQUICC II Specification PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale co
53. option FCC3 TXD 2 FCC2 RxD 1 TDM A2 by PC9 MII HDLC nibble UTOPIA 8 PD10 L1TSYNC GRANT primary option primary option PB4 FCC3 TXD 3 FCC2 RxD 0 by FCC3 RTS A2 L1RSYNC by MII HDLC nibble UTOPIA 8 PD11 primary option PD20 primary option Table 9 3 shows the port C pin assignments Table 9 3 Port C Dedicated Pin Assignment PPARC 1 Pin Function PIN PSORC 0 PSORC 1 Default A PDIRC 0 Input or Default PDIRC 1 Output PDIRC 0 Input PDIRC 1 Output Inout if Specified Input 1 BRG1 BRGO CLK1 CLK5 MOTOROLA Chapter 9 Parallel I O Ports 9 7 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 9 3 Port C Dedicated Pin Assignment PPARC 1 continued Pin Function PIN PSORC 0 PSORC 1 _ _ Default _ PDIRC 0 Input or Default PDIRC 1 Output PDIRC 0 Input Input PDIRC 1 Output Inout if Specified Input PC30 FCC2 TxD 3 CLK2 CLK6 Timer1 TOUT UTOPIA 8 PC29 BRG2 BRGO CLK3 TIN2 CLK7 SCC1 CTS GND SCC1 CLSN Ethernet secondary option PC28 Timer2 TOUT CLK4 TIN1 CLK8 FCC2 RxAddr 4 SCC2 CTS GND SCC2 CLSN Ethernet secondary option PC27 FCC3 TxD CLK5 GND BRG3 BRGO HDLC transp serial FCC3 TxD 0 MII HDLC nibble FCC3 TXD 0 RMII dibit PC26 Timer3 TOUT CLK6 GND T
54. packet is received the USB controller issues a SOF maskable interrupt and the frame Frame number entry in the parameter RAM is updated SOF Preamble The PRE token signals the hub that a low speed transaction is about to occur The PRE token is read only PRE by the hub The USB controller ignores the PRE token function in function mode 7 5 USB Host Description When programmed as a host the USB controller supports a limited host functionality The following sections describe the available host functionality its limitations and the programming model Figure 7 4 illustrates the functionality of the USB controller in host mode The USB controller consists of transmitter and receiver sections host control unit and a function control unit which is used for testing purposes The USB transmitter contains four independent FIFOs each containing 16 bytes End point 1 is dedicated for host transactions end points 2 4 are for function transactions in test mode There is a dedicated FIFO for each of the four supported end points end point 1 FIFO is for host transactions The USB receiver has a single 16 byte FIFO 7 8 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 USB Host Description Peripheral bus U bus E MEME Port control
55. proceeds when the RESTART command is issued GRACEFUL Graceful stop transmission Stops the transmission from this channel as soon as the current frame has STOP TX been fully transmitted from the transmit FIFO Transmission proceeds when the RESTART command is issued and the R bit is set in the next TxBD RESTART TX Restart transmission Once the STOP TX command has been issued this command is used to restart transmission at the current BD USB STOP See Section 7 7 USB CP Commands TX ENDPOINT USB See Section 7 7 USB CP Commands RESTART TX ENDPOINT START IDMA See Section 14 4 8 8 IDMA Commands in the MPC8260 PowerQUICC II User s Manual STOP IDMA 5 Section 14 4 8 8 IDMA Commands in the MPC8260 PowerQUICC II User s Manual SET TIMER Settimer Activates deactivates or reconfigures one of the 16 timers in the RISC timer table SET GROUP Set group address Sets a bit in the hash table for the Ethernet logical group address recognition ADDRESS function 5 12 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Command Set Table 5 5 Command Descriptions continued Command Description GCI ABORT abort request The receiver sends an abort request on the E bit REQUEST GCI GCI time out The GCI performs the timeout
56. than the least significant byte of the same buffer word 5 TC2 Transfer code Contains the transfer code value of TC 2 used during this SDMA channel memory access TC 0 1 is driven with a 0b11 to identify this SDMA channel access as a DMA type access 6 DTB Data bus Indicator 0 Use 60x bus for SDMA operation 1 Use Local bus for SDMA operation 7 Reserved should be cleared 7 5 7 USB Function Programming Model The following sections describe USB controller registers 7 5 7 4 USB Mode Register USMOD USMOD controls the USB controller operation mode 0 1 2 3 4 5 6 7 Field LSS RESUME TEST HOST EN Reset 0000 0000 R W R W Addr 0x11B60 Figure 7 11 USB Mode Register USMOD Table 7 9 describes USMOD fields MOTOROLA Chapier 7 Universal Serial Bus Controller 7 17 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc USB Host Description Table 7 9 USMOD Fields Bits Name Description 0 LSS Low speed signaling Selects the signaling speed The actual bit rate depends on the USB clock source 0 Full speed 12 Mbps signaling Normal operation 1 Low speed 1 5 Mbps signaling For a point to point connection with a low speed device or for local loopback testing 1 RESUME Generate resume condition When set this bit generates a resume condition on the U
57. x 92 UJ Address 1 Peripheral SCC1 SCC2 SCC3 SCC4 2 MCC1 Reserved SMC1 base IDMA1 base MCC2 Reserved SMC2 base IDMA2 base Reserved SPI base IDMA3 base Reserved TIMERS REV_NUM Reserved Reserved RAND 2 base IDMA4 base USB Reserved e e Offset from RAM Base 5 6 MPC8280 PowerQUICC II Specification PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Size Bytes 256 256 256 256 256 256 256 128 124 224 A MNI N A AJ N N 256 1224 MOTOROLA Freescale Semiconductor Inc RISC Controller Configuration Register 5 2 RISC Controller Configuration Register NOTE Reference Documentation This section supplements Section 13 3 6 the MPC8260 PowerQUICC II User s Manual Note the change in the description of RCCR ERAM in Table 5 2 all other bits are unchanged The RISC controller configuration register RCCR configures the CP to run microcode from ROM or RAM and controls the CP s internal timer This register is cleared at reset 0 1 2 7 8 9 10 11 12 13 14 15 Field TIME MCCPR TIMEP brim DR2M DR1QP EIE SCD DR2QP Reset 0000_0000_0000_0000 R W R W Addr 11904 16 19 20 21 22 23 24 25 26 27 28 29 30 31 Field ERAM EDM1 EDM2 EDM3 EDM4 DRAM
58. 0 0110_101 60 0 120 0 2 5 150 0 300 0 5 300 0 600 0 6 25 0 50 0 0110 110 60 0 120 0 2 5 150 0 300 0 6 360 0 720 0 6 25 0 50 0 0111 000 Reserved 0111 001 50 0 100 0 3 150 0 300 0 3 150 0 300 0 6 25 0 50 0 MOTOROLA Chapter 4 PLL and Clock Generator 4 19 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Configuration Modes Table 4 8 Clock Configurations for PCI Host Mode PCI MODCK 1 1 continued Mode Bus Clock 4 CPM Clock CPU Clock PCI Clock MHz CPM MHz CPU MHz PCI MHz Multiplication Multiplication Division MODERA low high Factor low high Factor low high Factor high 0111_010 71 4 100 0 3 214 3 300 0 3 5 250 0 350 0 6 35 7 50 0 0111_011 62 5 100 0 3 187 5 300 0 4 250 0 400 0 6 31 3 50 0 0111_100 55 6 100 0 3 166 7 300 0 4 5 250 0 450 0 6 27 8 50 0 1000_000 Reserved 1000_001 66 7 133 3 3 200 0 400 0 3 200 0 400 0 8 25 0 50 0 1000 010 71 4 133 3 3 214 3 400 0 3 5 250 0 466 7 8 26 8 50 0 1000_011 66 7 133 3 3 200 0 400 0 4 266 7 533 3 8 25 0 50 0 1000 100 66 7 133 3 3 200 0 400 0 4 5 300 0 600 0 8 25 0 50 0 1000_101 66 7 133 3 3 200 0 400 0 6 400 0 800 0 8 25 0 50 0 1000_110 66 7 133 3 3 200 0 4
59. 00 0 266 6 2 5 200 0 266 6 2 5 80 0 106 7 1011_010 50 0 66 7 4 200 0 266 6 3 240 0 320 0 2 5 80 0 106 7 1011_011 50 0 66 7 4 200 0 266 6 3 5 280 0 373 3 2 5 80 0 106 7 1011_100 50 0 66 7 4 200 0 266 6 4 320 0 426 6 2 5 80 0 106 7 1100 101 50 0 66 7 6 300 0 400 0 4 400 0 533 3 3 100 0 133 3 1100_110 50 0 66 7 6 300 0 400 0 4 5 450 0 599 9 3 100 0 133 3 1100_111 50 0 66 7 6 300 0 400 0 5 500 0 666 6 3 100 0 133 3 1101_000 50 0 66 7 6 300 0 400 0 5 5 550 0 733 3 3 100 0 133 3 1101_001 50 0 66 7 6 300 0 400 0 3 5 420 0 559 9 2 5 120 0 160 0 1101 010 50 0 66 7 6 300 0 400 0 4 480 0 639 9 2 5 120 0 160 0 1101 011 50 0 66 7 6 300 0 400 0 4 5 540 0 719 9 2 5 120 0 160 0 1101 100 50 0 66 7 6 300 0 400 0 5 600 0 799 9 2 5 120 0 160 0 1110 000 50 0 66 7 5 250 0 333 3 2 5 312 5 416 6 2 125 0 166 7 1110 001 50 0 66 7 5 250 0 333 3 3 375 0 500 0 2 125 0 166 7 1110 010 50 0 66 7 5 250 0 333 3 3 5 437 5 583 3 2 125 0 166 7 1110 011 50 0 66 7 5 250 0 333 3 4 500 0 666 6 2 125 0 166 7 1110_100 50 0 66 7 5 250 0 333 3 4 333 3 444 4 3 83 3 111 1 1110 101 50 0 66 7 5 250 0 333 3 4 5 375 0 500 0 3 83 3 111 1 1110 110 50 0 66 7 5 250 0 333 3 5 416 7 555 5 3 83 3 111 1 1110_111 50 0 66 7 5 250 0 333 3 5 5 458 3
60. 00 0 6 5 433 3 866 7 8 25 0 50 0 1001_000 Reserved 1001_001 Reserved 1001_010 71 4 114 3 3 5 250 0 400 0 3 5 250 0 400 0 8 31 3 50 0 1001_011 62 5 114 3 3 5 218 8 400 0 4 250 0 457 1 8 27 3 50 0 1001_100 57 1 114 3 3 5 200 0 400 0 4 5 257 1 514 3 8 25 0 50 0 1001 101 50 0 85 7 3 5 175 0 300 0 5 250 0 428 6 6 29 2 50 0 1001_110 45 5 85 7 3 5 159 1 300 0 5 5 250 0 471 4 6 26 5 50 0 1001_111 42 9 85 7 3 5 150 0 300 0 6 257 1 514 3 6 25 0 50 0 1010_000 75 0 150 0 2 150 0 300 0 2 150 0 300 0 6 25 0 50 0 1010_001 75 0 150 0 2 150 0 300 0 2 5 187 5 375 0 6 25 0 50 0 1010_010 75 0 150 0 2 150 0 300 0 3 225 0 450 0 6 25 0 50 0 1010_011 75 0 150 0 2 150 0 300 0 3 5 262 5 525 0 6 25 0 50 0 1010_100 75 0 150 0 2 150 0 300 0 4 300 0 600 0 6 25 0 50 0 1011 000 Reserved 1011_001 80 0 160 0 2 5 200 0 400 0 2 5 200 0 400 0 8 25 0 50 0 1011_010 80 0 160 0 2 5 200 0 400 0 3 240 0 480 0 8 25 0 50 0 1011_011 80 0 160 0 2 5 200 0 400 0 3 5 280 0 560 0 8 25 0 50 0 1011_100 80 0 160 0 2 5 200 0 400 0 4 320 0 640 0 8 25 0 50 0 4 20 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock
61. 0x to Local Bridge Memory Controller Clock Counter System Functions PCI Bus 32 bits up to 66 MHz Local Bus 32 bits up to 100 MHz Communication Processor Module CPM y 32 KB Timers Interrupt Instruction Serial Controller RAM DMAs Parallel I O 32 bit RISC Microcontroller 4 Virtual Baud Rate and Program ROM EE IDMAs Generators Microcode 2 2 FCC3 SCC1 SCC2 SCC3 SPI Layer Hardware Time Slot Assigner Serial Interface ty yy 3 MII 2 UTOPIA Non Multiplexed Ports Ports 8 TDM Ports Notes 1 MPC8280 only not on MPC8270 nor the VR package MPC8270VR and MPC8275VR 2 MPC8280 only 4 TDMs 8270 and the VR package MPC8270VR and MPC8275VR 3 MPC8280 and MPC8275VR only not on MPC8270 nor MPC8270VR 4 No local bus on the VR package MPC8270VR and MPC8275VR Figure 1 1 MPC8280 Block Diagram MOTOROLA Chapter 1 Overview 1 3 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc MPC8280 Architecture Overview 1 4 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT
62. 0x11386 FIRER1 0x113A6 FIRER2 0x113C6 FIRER3 Figure 8 5 FCC Internal Rate Event Register FIRER Table 8 4 describes FIRERx fields Table 8 4 FIRERx Field Descriptions TIREM 1 Bit Name Description 0 30 TIRUy Transmit internal rate underrun 0 There is no transmission underrun for this PHY 1 Transmit internal rate underrun or PHY address y has occurred Bit is cleared by writing 1 to it Writing 0 has no effect on value 31 Reserved should be cleared 8 6 4 FCC Internal Rate Selection Registers FIRSR FIRSR LO If TIREM 1 each PHY can be assigned one of four rates as configured by the four FCC transmit internal rate timers The FCC internal rate selection registers FIRSRx HI FIRSRx LO shown in Figure 8 6 and Figure 8 7 assign rate group to each of the PHYs 8 8 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Field Reset R W Addr Field Reset R W Addr Freescale Semiconductor Inc ATM Registers 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GSO GS1 GS2 GS3 GS4 GS5 GS6 GS7 0000 0000 0000 0000 R W 0x11388 FIRSR1_Hl 0x113A8 FIRSR2 0x113C8 FIRSR3_HI 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 GS8 GS9 GS10 GS11 GS12 GS13 GS14 GS15 0000_0000_0000_0000 R W 0x1138A FIRSR1 HI
63. 1100_010 50 0 100 0 3 150 0 300 0 Bypass 50 0 100 0 6 25 0 50 0 As shown Table 4 5 PCI MODCK determines the PCI clock frequency range Refer to Table 4 7 for higher range configurations MODCK hard reset configuration word 28 31 Refer to Section 5 4 in the MPC8260 User s Manual MODOCK 1 3 three hardware configuration pins 60x and local bus frequency Identical to CLKIN High and low indicate frequency limits for a given configuration CPM multiplication factor CPM clock bus clock CPU multiplication factor Core PLL multiplication factor 4 6 2 2 Agent Mode Table 4 9 and Table 4 10 show configurations for PCI agent mode Note that the range of the PCI clock frequency is determined by PCI MODCK MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Chapter 4 PLL and Clock Generator For More Information On This Product Go to www freescale com 4 21 Freescale Semiconductor Inc Clock Configuration Modes Table 4 9 Clock Configurations for PCI Agent Mode PCI 0 Mode 2 MODCK H MODCK 1 3 PCI Clock 3 MHz ow high CPM Multiplication Factor 4 D CPM Clock MHz CPU Multiplication Factor gt efault Modes MODCK 0000 CPU Clock MHz low high Bus Division Factor Bus Clock amp MHz low high 0000_000 2 0000_001 50 0
64. 12 PE13 PE14 PE15 Reset 0000_0000_0000_0000 R W R W Addr 0x11380 FIRPER1 0x113A0 FIRPER2 0 113 0 FIRPERS 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field 16 PE17 PE18 PE19 PE20 21 22 PE23 24 PE25 26 27 28 29 Reset 0000_0000_0000_0000 R W R W Addr 0x11382 FIRPER1 0x113A2 FIRPER2 0x113C2 FIRPERS Figure 8 4 FCC Transmit Internal Rate Port Enable Register FIRPER Table 8 3 describes FIRPERx fields Table 8 3 FIRPERx Field Descriptions TIREM 1 Bit Name Description 0 15 PEy Port enable 0 Transmit internal rate for PHY address y is disabled TxClav from this PHY is masked 1 Transmit Internal rate for PHY address y is enabled rate assigned for PHY y is selected by register FIRSR_HI refer to Section 8 6 4 FCC Internal Rate Selection Registers FIRSR_HI FIRSR LO 16 30 PEy Port enable 0 Transmit internal rate for PHY address y is disabled TxClav from this PHY is masked 1 Transmit Internal rate for PHY address y is enabled The rate assigned for PHY y is selected by register FIRSR LO refer to Section 8 6 4 FCC Internal Rate Selection Registers FIRSR HI FIRSR_LO 31 Reserved should be cleared 8 6 3 FCC Internal Rate Event Register FIRER Transmit internal rate underrun TIRU errors are reported for any PHY that has a transmission deficiency of 8 cells Under this con
65. 15 USB Rx BD Fields continued Offset Bit Name Description buffer It is written once by the CP as the BD is closed than or equal to the contents of the MRBLR 0x02 0 15 Data length Data length is the number of octets that the CP has written into this BD s data Note The actual amount of memory allocated for this buffer should be greater 0x04 0 31 Rx data buffer The receive buffer pointer which always points to the first location of the internal or external memory pointer associated data buffer must be divisible by 4 The buffer may reside in either Data length represents the number of octets that the CP has written into this BD s buffer It is written once by the CP as the BD is closed The receive buffer pointer always points to the first location of the associated buffer The pointer must be divisible by 4 The buffer may reside in either internal or external memory 7 6 2 USB Transmit Buffer Descriptor Tx BD for Function Data that the USB function wishes to transmit to the host is arranged in buffers referenced by the Tx BD ring The first word of the Tx BD contains the status and control bits 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 OFFSET 0 R W 1 L TC CNF PID TO UN OFFSET 2 DATA LENGTH OFFSET 4 TX DATA BUFFER POINTER OFFSET 6 Figure 7 19 USB Transmit Buffer Descriptor Tx BD 1 2 Entries in boldfa
66. 150 0 300 0 Bypass 50 0 100 0 3 50 0 100 0 1 As shown in Table 4 5 PCI MODCK determines the PCI clock frequency range Refer to Table 4 9 for higher range configurations MODCK H hard reset configuration word 28 31 Refer to Section 5 4 in the MPC8260 User s Manual MODCK 1 3 three hardware configuration pins 4 28 High and low indicate frequency limits for a given configuration CPM multiplication factor CPM clock bus clock CPU multiplication factor Core PLL multiplication factor 60x and local bus frequency Identical to CLKIN MPC8280 PowerQUICC II Specification PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc Chapter 5 Internal Multiported RAM DPRAM NOTE Reference Documentation This section replaces the introduction to Section 13 5 Dual Port RAM in the 8260 PowerQUICC II User s Manual Subsection 13 5 1 in the manual is valid for the MPC8280 The CPM has 64 Kbytes of static RAM This RAM is divided into two 32 Kbyte blocks of RAM 32 Kbytes CPM RISC instructions RAM This RAM is used to store a microcode package of up to 8 K instructions e 32 Kbytes of CPM RISC data RAM This RAM is used to store CPM RISC parameter RAM and data structures as defined in the MPC6260 PowerQUICC User s Manual Figure 5 1 shows a block diagram of the interna
67. 2 bits 8 2 11B60 USMOD USB mode register 8 bits 7 5 7 1 11B61 USADR USB address register 8 bits 7 5 7 2 11B62 USCOM USB command register 8 bits 7 5 7 4 11B64 USEP1 USB end point 1 register 16 bits 7 5 7 3 11B66 USEP2 USB end point 2 register 16 bits 7 5 7 3 11B68 USEP3 USB end point 3 register 16 bits 7 5 7 3 11B6A USEP4 USB end point 4 register 16 bits 7 5 7 3 11B6C 11B6F Reserved 32 bits m 11B70 USBER USB event register 16 bits 7 5 7 5 11B72 Reserved 16 bits 11B74 USBMR USB mask register 16 7 5 7 6 11B77 USBS USB status register 8 bits 7 5 7 7 11B79 11B7F Reserved 56 bits 3 1 Internal Memory Map Register IMMR NOTE Reference Documentation This section replaces Section 4 3 2 7 Internal Memory Map Register in the MPC8260 PowerQUICC II User s Manual The internal memory map register IMMR shown in Figure 3 1 contains both identification of a specific device and the base address for the internal memory map Software can deduce availability and location of on chip system resources from the values in IMMR Note that PARTNUM and MASKNUM are mask programmed and cannot be changed for any particular device 3 2 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Internal Memory Map Register IMMR 0 13 14 15 Field ISB
68. 5 0 4 200 0 300 0 5 250 0 375 0 6 33 3 50 0 0010 101 45 5 75 0 181 8 300 0 5 5 250 0 412 5 6 30 3 50 0 0010_110 41 7 75 0 4 166 7 300 0 6 250 0 450 0 6 27 8 50 0 0011_000 50 0 50 0 5 250 0 250 0 5 250 0 250 0 5 50 0 50 0 0011_001 41 7 50 0 5 208 3 250 0 6 250 0 300 0 5 41 7 50 0 0011_010 35 7 50 0 5 178 6 250 0 7 250 0 350 0 5 35 7 50 0 0011_011 31 3 50 0 5 156 3 250 0 8 250 0 400 0 5 31 3 50 0 0100_000 Reserved 0100_001 41 7 50 0 6 250 0 300 0 6 250 0 300 0 6 41 7 50 0 0100_010 35 7 50 0 6 214 3 300 0 7 250 0 350 0 6 35 7 50 0 0100 011 31 3 50 0 6 187 5 300 0 8 250 0 400 0 6 31 3 50 0 0101_000 50 0 100 0 2 100 0 200 0 2 5 125 0 250 0 4 25 0 50 0 0101_001 50 0 100 0 2 100 0 200 0 3 150 0 300 0 4 25 0 50 0 0101_010 71 4 100 0 2 142 9 200 0 3 5 250 0 350 0 4 35 7 50 0 0101_011 62 5 100 0 2 125 0 200 0 4 250 0 400 0 4 31 3 50 0 0101 100 55 6 100 0 2 111 1 200 0 4 5 250 0 450 0 4 27 8 50 0 0110_000 60 0 120 0 2 5 150 0 300 0 2 5 150 0 300 0 6 25 0 50 0 0110_001 60 0 120 0 2 5 150 0 300 0 3 180 0 360 0 6 25 0 50 0 0110 010 71 4 120 0 2 5 178 6 300 0 3 5 250 0 420 0 6 29 8 50 0 0110 011 62 5 120 0 2 5 156 3 300 0 4 250 0 480 0 6 26 0 50 0 0110_100 60 0 120 0 2 5 150 0 300 0 4 5 270 0 540 0 6 25 0 50
69. 6 PB11 FCC2 TxD 0 FCC3 RxD 3 GND TDM D1 L1TXD by UTOPIA 8 MII HDLC nibble Inout PD25 primary option 9 6 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 9 2 Port B Dedicated Pin Assignment PPARB 1 continued Pin Function PSORB 0 PSORB 1 Pin _ _ Default _ PDIRB 0 Input or Default PDIRB 1 Output PDIRB 0 Input Input PDIRB 1 Output Inout if Specified Input FCC2 TxD 1 FCC3 RxD 2 TDM D1 L1RXD UTOPIA 8 MII HDLC nibble Inout PD24 primary option PB9 FCC2 TxD 2 FCC3 RxD 1 GND TDM A2 L1TXD 2 by PD4 UTOPIA 8 MII HDLC nibble Nibble L1TSYNC GRANT FCC3 RxD 1 primary option RMII dibit PB8 FCC2 TxD 3 FCC3 RxD 0 GND SCC3 TXD TDM D1 L1RSYNC by UTOPIA 8 MII HDLC nibble primary option PD23 FCC3 RxD 0 RMII dibit FCC3 RxD HDLC transp serial PB7 FCC3 TXD 0 FCC2 RxD 3 by A2 L1TXD 0 A2 L1TXD by MII HDLC nibble UTOPIA 8 PC10 Output nibble Inout serial PD22 FCC3 TXD 0 primary option primary option RMII dibit FCC3 TXD HDLC transp serial PB6 FCC3 TXD 1 FCC2 RxD 2 by TDM A2 L1RXD by MII HDLC nibble UTOPIA 8 PC11 Inout serial PD21 FCC3 TXD 1 primary option A2 L1RXD 0 RMII dibit Input nibble primary
70. 6 7 8 9 10 11 12 13 14 15 Field HBC FC SBT LPB LCW FDE MON PRO FCE RSH RMII Reset 0000_0000_0000_0000 R W R W Addr 0x11304 FPSMR1 0x11324 FPSMR2 0x11344 FPSMR3 16 20 21 22 23 24 25 26 31 Field CRC Reset 0000 0000 0000 0000 R W R W Addr 0x11306 FPSMR1 0x11326 FPSMR2 0x11346 FPSMR3 Figure 8 2 FCC Ethernet Mode Register FPSMRx 8 2 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Fast Ethernet Controller Table 8 2 describes FPSMR fields Table 8 2 FPSMR Ethernet Field Descriptions Bits Name Description 0 HBC Heartbeat checking 0 No heartbeat checking is performed Do not wait for a collision after transmission 1 Wait 40 transmit serial clocks for a collision asserted by the transceiver after transmission TxBD HB is set if the heartbeat is not heard within 40 transmit serial clocks 1 FC Force collision 0 Normal operation 1 The channel forces a collision on transmission of every transmit frame The MPC8280 should be configured in loopback operation when using this feature which allows the user to test the MPC8280 collision logic It causes the retry limit to be exceeded for each transmit frame 2 SBT Stop backoff timer 0 The backoff timer functions normally 1 The backoff timer for the random
71. 6 bits 16 bits 16 bits 32 bits Rx Tx function code Controls the value to appear on AT 1 3 when the associated SDMA channel accesses memory and the byte ordering convention Maximum receive buffer length Defines the maximum number of bytes the MPC8280 writes to the USB receive buffer before moving to the next buffer MRBLR must be divisible by 4 The MPC8280 can write fewer data bytes to the buffer than the MRBLR value if a condition such as an error or end of packet occurs but it never exceeds MRBLR Therefore user supplied buffers should never be smaller than MRBLR MRBLR is not designed to be changed dynamically for the currently active RXBD during USB operation however MRBLR can be modified safely for the next and subsequent RxBDs using a single bus cycle with one 16 bit move not two 8 bit bus cycles back to back Transmit buffers for the USB controller are not affected by the MRBLR value Transmit buffer lengths can vary individually as needed The number of bytes to be sent is chosen by programming TxBD Data Length RxBD pointer Points to the next BD the receiver will transfer data to when it is in an idle state or to the current BD while processing a frame Software should initialize RBPTR after reset When the end of the BD table is reached the CP initializes this pointer to the value programmed in RBASE Although the user does not need to write RBPTR in most applications except initialization it can be changed when
72. 7 3 and Table 7 2 describe the behavior of the USB controller for each token Tokens that are not valid i e PID check fails or CRC check fails or packet length is not 3 bytes are ignored by the USB function controller unenumerated Enumeration process IDLE setup start of frame transmit receive Figure 7 3 USB Controller Operating Modes 7 6 MPC8280 PowerQUICC II Specification PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com MOTOROLA Freescale Semiconductor Inc mu USB Function Description Table 7 2 USB Tokens Token Description OUT Reception begins when an OUT token is received The USB controller fetches the next BD associated with the endpoint if the BD is empty the controller starts sending the incoming packet to the buffer After the buffer is full the USB controller clears RxBD E and generates an interrupt if 1 If the incoming packet is larger than the buffer the USB controller fetches the next BD and if it is empty sends the rest of the packet to its buffer The entire packet including the DATAO DATA1 PID are written to the receive buffers Software must check data packet synchronization by monitoring the DATAO DATA1 PID sequence toggle If the packet reception has no CRC or bit stuff errors the USB receiver sen
73. 8 50 0 0000_100 62 5 120 0 2 5 156 3 300 0 4 250 0 480 0 6 26 0 50 0 0000_101 50 0 100 0 3 150 0 300 0 3 150 0 300 0 6 25 0 50 0 0000_110 71 4 100 0 3 214 3 300 0 3 5 250 0 350 0 6 35 7 50 0 0000_111 62 5 100 0 3 187 5 300 0 4 250 0 400 0 6 31 3 50 0 Full Configuration Modes 0001 000 50 0 100 0 3 150 0 300 0 5 250 0 500 0 6 25 0 50 0 0001_ 001 50 0 100 0 3 150 0 300 0 6 300 0 600 0 6 25 0 50 0 0001 010 50 0 100 0 3 150 0 300 0 7 350 0 700 0 6 25 0 50 0 0001 011 50 0 100 0 3 150 0 300 0 8 400 0 800 0 6 25 0 50 0 0010_000 50 0 100 0 4 200 0 400 0 5 250 0 500 0 8 25 0 50 0 0010_001 50 0 100 0 200 0 400 0 6 300 0 600 0 8 25 0 50 0 4 18 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Configuration Modes Table 4 8 Clock Configurations for PCI Host Mode PCI MODCK 1 1 continued Mode Bus Clock 4 CPM Clock CPU Clock PCI Clock MHz CPM MHz CPU MHz PCI MHz Multiplication Multiplication Division MODCK H Factor 5 Factor 6 Factor MODCK 1 3 low high low high low high low high 0010 010 50 0 100 0 200 0 400 0 7 350 0 700 0 8 25 0 50 0 0010 011 50 0 100 0 4 200 0 400 0 8 400 0 800 0 8 25 0 50 0 0010 100 50 0 7
74. ATA 2K Bank 15 BD DATA 2K 0X3800 0XB800 Bank 8 BD DATA 2K Bank 16 BD DATA 2K Figure 5 3 Internal Data RAM Memory Map The internal data RAM data bus is 64 bits wide The RAM is used for six possible tasks e To store parameters associated with the FCCs SCCs SMCs SPI PC and IDMAs in the 2 048 byte parameter RAM To store the BDs that describe where data is to be received and transmitted from e store data from the serial channels optional because data can also be stored externally in the system memory Temporary storage between FCC FIFO and external memory for FCC data that is moved by BTM from to FCC FIFO and SDMA to from external memory 5 4 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Parameter RAM e For additional RAM space for user software The data RAM is designed to serve multiple requests as long as the requests are not in the same bank at the same cycle Only the parameters in the parameter RAM require fixed addresses The BDs buffer data and scratched RAM can be located in the internal system RAM or in any unused parameter RAM such as the area made available when a serial channel or sub block is not being used Microcode can be executed from the 32 Kbyte instruction RAM 5 1 Parameter RAM NOTE Reference Documentatio
75. BD Bus busy disable Defines the initial value of SIUMCR BBD See Section 4 3 2 6 SIU Module Configuration Register SIUMCR in the MPC8260 PowerQUICC User s Manual 18 19 MMR Mask masters requests Defines the initial value of SIUMCR MMR See Section 4 3 2 6 SIU Module Configuration Register SIUMCR in the MPC8260 PowerQUICC User s Manual MOTOROLA Chapter 4 PLL and Clock Generator 4 7 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc PLL Pins Table 4 2 Hard Reset Configuration Word Field Descriptions continued Bits Name Description 20 21 LBPC Local bus pin configuration Defines the value of SIUMCR LBPC See Section 4 3 2 6 SIU Module Configuration Register SIUMCR 00 Local bus pins function as local bus 01 Local bus pins function as PCI bus 10 Local bus pins function as core pins 11 Reserved 22 23 APPC Address parity pin configuration Defines the initial value of SIUMCR APPC See Section 4 3 2 6 SIU Module Configuration Register SIUMCR in the MPC8260 PowerQUICC User s Manual 24 25 CS10PC CS10pin configuration Defines the initial value of SIUMCR CS10PC See Section 4 3 2 6 SIU Module Configuration Register SIUMCR in the MPC8260 PowerQUICC User s Manual 26 ALD EN CP auto load enable Allows the CP to automatically load the essential PCI configura
76. BD is identical for both the host mode and the function mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 OFFSET 0 E w 1 L F PID NO AB CR OV OFFSET 2 DATA LENGTH OFFSET 4 RX DATA BUFFER POINTER OFFSET 6 Figure 7 18 USB Receive Buffer Descriptor Rx BD 1 2 1 Entries in boldface must be initialized by the user 2 All fields should be written by the CPU core before enabling the USB Table 7 15 describes USB receive buffer descriptor fields Table 7 15 USB Rx BD Fields Offset Bit Name Description 0x00 0 E Empty 0 The data buffer associated with this Rx BD has been filled with received data or data reception has been aborted due to an error condition The CPU core is free to examine or write to any fields of this Rx BD The CP will not use this BD again while the E bit remains zero 1 The data buffer associated with this BD is empty or reception is currently in progress This Rx BD and its associated receive buffer are owned by the CP Once the E bit is set the CPU core should not write any fields of this Rx BD Reserved should be cleared 7 24 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor In Buffer Descriptor Ring Table 7 15 USB Rx BD Fields continued
77. Bank 5 CPM Instruction 2K Bank 6 CPM Instruction 2K Bank 7 CPM Instruction 2K Bank 8 CPM Instruction 2K Figure 5 3 shows a memory map of the internal data RAM The addresses refer to CPU address space MOTOROLA Freescale Semiconductor Inc 0X24000 Bank 9 CPM Instruction 2K 0X24800 Bank 10 CPM Instruction 0X25000 Bank 11 CPM Instruction 2K 0X25800 Bank 12 CPM Instruction 2K 0X26000 Bank 13 CPM Instruction Trace Buffer 2K 0X26800 Bank 14 CPM Instruction Trace Buffer 15 CPM Instruction Trace Buffer 0 27800 Bank 16 CPM Instruction Trace Buffer 2K Chapier 5 Internal Multiported RAM DPRAM PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Reserved Figure 5 2 Instruction RAM Partitioning Go to www freescale com Reserved Freescale Semiconductor Inc 0X0000 0X4000 0X8000 0 000 Bank 9 Parameter RAM 2K Bank 1 BD DATA 2K 0X0800 0X8800 Bank 10 Bank 2 Parameter RAM BD DATA 2K Partly reserved for future serials 0X1000 0X9000 Bank 3 BD DATA 2K Bank 11 BD DATA 2K 0X1800 0X9800 Bank 4 Bank 12 BD DATA Reserved BD DATA Reserved 2K 2K 0 500 0 000 Bank 13 BD DATA 2K Bank 5 BD DATA 2K 0 2800 0 800 Bank 6 BD DATA 2K Bank 14 BD DATA 2K 0X3000 Bank 47 0XB000 BD D
78. C2 RENA MPHY master MPHY slave Ethernet FCC2 RxAddi 3 MPHY slave PC11 TDM_D1 L1CLKO SCC3 CTS TDM A2 L1TXD 3 2 RxD 2 GND SCC3 CLSN Nibble UTOPIA 8 Ethernet secondary option primary option PC10 FCC1 TxD 2 SCC3 CD Sli L1STA 2 RxD 3 GND UTOPIA 16 SCC3 RENA strobe UTOPIA Ethernet secondary option PC9 FCC1 TxD 1 SCC4 CTS SI2 L1ST1 TDM A2 GND UTOPIA 16 SCC4 CLSN strobe L1TSYNC GRANT USB RP secondary option Ethernet primary option PC8 FCC1 TxD 0 SCC4 CD GND SI2 L1ST2 SCC3 CTS GND UTOPIA 16 SCC4 RENA Strobe secondary option USB RN Ethernet PC7 TDM C1 L1RQ FCC1 CTS GND FCC1 TxAddr 2 FCC1 TxAddi 2 GND MPHY master MPHY slave multiplexed polling multiplexed polling FCC1 TxClav1 MPHY master direct polling FCC2 TxAddr 2 MPHY slave multiplexed polling MOTOROLA Chapter 9 Parallel I O Ports 9 9 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 9 3 Port C Dedicated Pin Assignment PPARC 1 continued Pin Function PIN PSORC 0 PSORC 1 Default PDIRC 0 Input or Default PDIRC 1 Output PDIRC 0 Input Input PDIRC 1 Output Inout if PARU Input PC6 C1 L1CLKO FCC1 CD FCC1 RxAddi 2 FCC1 RxAddr 2 GND MPHY master MPHY slave multiplexed polling multiplexed polling RxClav1 MPHY master direc
79. COM is used to start USB transmit operation 0 1 2 5 6 7 Field STR FLUSH EP Reset 0000_0000 R W R W Addr 0x11B62 Figure 7 14 USB Command Register USCOM Table 7 12 describes USCOM fields Table 7 12 USCOM Fields Bits Name Description 0 STR Start FIFO fill Setting the STR bit to one causes the USB controller to start the filling the corresponding end point transmit FIFO with data Transmission will begin once the IN token for this end point is received The STR bit is read always as a zero 1 FLUSH Flush FIFO Setting the FLUSH bit to one causes the USB controller to flush the corresponding end point transmit FIFO Before flushing the FIFO the user should issue the Stop_Tx command After flushing the FIFO the user should issue the Restart_Tx command Refer to Section 7 7 USB CP Commands FLUSH is always read as a zero 2 5 Reserved should be cleared 6 7 EP End point Selects one of the four supported end points 7 20 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc USB Host Description 7 5 7 5 USB Event Register USBER The USBER reports events recognized by the USB channel and generates interrupts Upon recognition of an event the USB sets its corresponding bit in the USBER Interrupts generated by this re
80. Configuration Modes Table 4 8 Clock Configurations for PCI Host Mode PCI MODCK 1 1 continued Mode Bus Clock 4 CPM Clock CPU Clock PCI Clock MHz CPM MHz CPU MHz PCI MHz Multiplication Multiplication Division MODCK H Factor 5 Factor 6 Factor MODCK 1 3 low high low high low high low high 1011 101 80 0 160 0 2 5 200 0 400 0 4 5 360 0 720 0 8 25 0 50 0 1101_000 50 0 100 0 2 5 125 0 250 0 3 150 0 300 0 5 25 0 50 0 1101_001 71 4 100 0 2 5 178 6 250 0 3 5 250 0 350 0 5 35 7 50 0 1101 010 62 5 100 0 2 5 156 3 250 0 4 250 0 400 0 5 31 3 50 0 1101 011 55 6 100 0 2 5 138 9 250 0 4 5 250 0 450 0 5 27 8 50 0 1101 100 50 0 100 0 2 5 125 0 250 0 5 250 0 500 0 5 25 0 50 0 1101 101 62 5 125 0 2 125 0 250 0 3 187 5 375 0 5 25 0 50 0 1101_110 62 5 125 0 2 125 0 250 0 4 250 0 500 0 5 25 0 50 0 1110_000 71 4 100 0 3 214 3 300 0 3 5 250 0 350 0 6 35 7 50 0 1110_001 62 5 100 0 3 187 5 300 0 4 250 0 400 0 6 31 3 50 0 1110_010 55 6 100 0 3 166 7 300 0 4 5 250 0 450 0 6 27 8 50 0 1110_011 50 0 100 0 3 150 0 300 0 5 250 0 500 0 6 25 0 50 0 1110_100 50 0 100 0 3 150 0 300 0 5 5 275 0 550 0 6 25 0 50 0 1100_000 50 0 100 0 2 100 0 200 0 Bypass 50 0 100 0 4 25 0 50 0 1100_001 60 0 120 0 2 5 150 0 300 0 Bypass 60 0 120 0 6 25 0 50 0
81. Division Factor PCI Clock MHz 1110_100 300 0 400 0 5 5 550 0 733 3 1100_000 Bypass 1100_001 Bypass 1100 010 50 0 66 7 3 150 0 200 0 Bypass 50 0 66 7 3 50 0 66 7 1 As shown in Table 4 5 PCI MODCK determines the PCI clock frequency range Refer to Table 4 8 for lower range configurations 2 MODCK hard reset configuration word 28 31 Refer to Section 5 4 in the MPC8260 User s Manual MODCK 1 3 three hardware configuration pins 3 and local bus frequency Identical to CLKIN High and low indicate frequency limits for a given configuration 5 CPM multiplication factor CPM clock bus clock 8 CPU multiplication factor Core PLL multiplication factor Table 4 8 Clock Configurations for PCI Host Mode 1 Mode BUS Clock 3 4 CPM Clock CPU Clock PCI Clock MHz CPM MHz CPU MHz PCI MHz Multiplication Multiplication Division MODCK H Factor 5 Factor 6 Factor MODCK 1 3 low high low high low high low high Default Modes MODCK_H 0000 0000_000 50 0 100 0 100 0 200 0 2 5 125 0 250 0 4 25 0 50 0 0000_001 50 0 100 0 100 0 200 0 3 150 0 300 0 4 25 0 50 0 0000_010 60 0 120 0 2 5 150 0 300 0 3 180 0 360 0 6 25 0 50 0 0000_011 71 4 120 0 2 5 178 6 300 0 3 5 250 0 420 0 6 29
82. FO if L 0 last bit or after the last character was transmitted on the line if L 1 15 RXB Rx buffer A buffer has been received This bit is set after the last character has been written to the receive buffer and the Rx BD is closed 7 5 7 6 USB Mask Register USBMR The USBMR is a 16 bit read write register 0 1 1B74 that has the same bit formats as the USB event register If a bit in the USBMR is one the corresponding interrupt in the USBER is enabled If the bit is zero the corresponding interrupt in the USBER will be masked This register is cleared at reset MOTOROLA Chapier 7 Universal Serial Bus Controller 7 21 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com l Freescale Semiconductor Inc USB Buffer Descriptor Ring 7 5 7 7 USB Status Register USBS The USB status register described in Figure 7 16 and Table 7 14 is a read only register that allows the user to monitor real time status condition on the USB lines Field 0 1 2 3 4 5 6 7 eT Figure 7 16 USB Status Register USBS Table 7 14 describes USBS fields Table 7 14 USBS Fields Bit Name Description 0 6 Reserved 7 IDLE Idle status IDLE is set when an idle condition is detected on the USB lines it is cleared when the bus is not idle 7 6 USB Buffer Descriptor Ring The data associated with the USB channel is stored in buffers that are referenced
83. Freescale Semiconductor Inc ef 2 digital dna intelligence everywhere MPC8280UMAD D 10 2002 Rev 0 1 MPC8280 PowerQUICC II Specification Addendum to the MPC8260 PowerQUICC User s Manual For More Information On This Product Go to www freescale com Freescale Semiconductor Inc HOW TO REACH US USA EUROPE LOCATIONS NOT LISTED Motorola Literature Distribution P O Box 5405 Denver Colorado 80217 1 303 675 2140 or 1 800 441 2447 JAPAN Motorola Japan Ltd SPS Technical Information Center 3 20 1 Minami Azabu Minato ku Tokyo 106 8573 Japan 81 3 3440 3569 ASIA PACIFIC Motorola Semiconductors H K Ltd Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 852 26668334 TECHNICAL INFORMATION CENTER 1 800 521 6274 HOME PAGE http www motorola com semiconductors Information in this document is provided solely to enable system and software implementers to use There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the appl
84. IFO 16 byte Port configuration Address USB function lt gt register state machine End point registers Receiver Transmitter DPLL Bus Interface External transceiver Figure 7 2 USB Function Block Diagram 7 4 4 USB Function Controller Transmit Receive After reset condition the USB function is addressable at the default address 0x00 During the enumeration process the USB function is assigned by the host with a unique address The USB slave address register refer to Section 7 5 7 2 USB Slave Address Register USADR should be programmed with the assigned address The USB function controller supports four independent end points Each endpoint can be configured to support either control interrupt bulk or isochronous transfers modes This is done by programming the end point registers refer to Section 7 5 7 3 USB End Point Registers USEPI USEP4 NOTE It is mandatory that end point O be configured as a control transfer type This endpoint is used by the USB system software as a control pipe Additional control pipes may be provided by other end points MOTOROLA Chapter 7 Universal Serial Bus Controller 7 5 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc USB Function Description Once enabled the USB function controller looks for valid token packets Figure
85. Identical to CLKIN High and low indicate frequency limits for a given configuration CPM multiplication factor CPM clock bus clock CPU multiplication factor Core PLL multiplication factor a fk 4 6 2 PCI Mode The following tables show the possible clock configurations for the MPC8280 in both PCI host and PCI agent modes In addition note the following NOTE In PCI mode only PCI MODCK comes from the LGPLS5 pin and MODCK H 0 3 comes from LGPLO LGPL1 LGPL2 LGPL3 NOTE The minimum 2 when PCI MODCK 1 and minimum 1 when PCI MODCK 0 therefore board designers should use clock configurations that fit this condition to achieve PCI compliant AC timing 4 6 2 1 PCI Host Mode Table 4 7 and Table 4 8 show configurations for PCI host mode Note that the range of the PCI clock frequency is determined by PCI MODCK 4 14 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Configuration Modes Table 4 7 Clock Configurations for PCI Host Mode PCI MODCK 0 MODCK H MODCK 1 3 Bus Clock 4 MHz low high CPM Multiplication Factor gt Clock MHz CPU Multiplication 6 low high Factor CPU Clock MHz PCI Division low high Factor PCI Clock MHz Default Modes
86. LK fixed 2 BUS_CLK CLKIN SCMR BUSDF BUSDF 1 General Purpose Divider SCC CLK 2 SCMR CPMDF x 4 SCCR DFBRG o2 DFBRG 1 BRG PCI_CLK TENDRE si IPSIDE 41 Note Used in PCI modes only CORE PLL BUS_CLK vco CORE_CLK PLL c SCMR CORECNF divider gt VCO_DF Notes PCI agent mode CLKIN is the PCI clock input to 8280 SCMR register is read only register Its value is determined during Poweron Reset Refer to Section 4 5 System Clock Mode Register SCMR Figure 4 1 MPC8280 System Clock Architecture MOTOROLA Chapter 4 PLL and Clock Generator 4 3 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com _ Freescale Semiconductor Inc MPC8280 Clock Block Diagram 4 1 6 PCI Bridge as an Agent Operating from the PCI System Clock If the MPC8280 is connected to a system which generates the PCI clock the PCI clock should be fed to the CLKINI pin The PCI clock is internally multiplied by the PLL to generate the chip s internal high speed clock This clock is used to generate the 60x bus clock refer to Table 4 9 and Table 4 10 The 60x bus clock is then driven by a DLL circuit to the DLLOUT pin which has a feedback path from the board to the CLKIN2 pin This feedback clock signal is used by the DLL logic to minimize clock skew between the internal and extern
87. MCLK BRGO1 real time counter PC25 FCC2 TxD 2 CLK7 GND BRG4 BRGO UTOPIA 8 PC24 FCC2 TxD 3 CLK8 GND Timer4 TOUT UTOPIA 8 PC23 BRG5 BRGO CLK9 IDMA1 DACK PC22 FCC1 TxPrty CLK10 IDMA1 DONE by PD5 UTOPIA Inout primary option PC21 BRG6 BRGO CLK11 PC20 USB OE CLK12 timer1 2 TGATE1 GND PC19 BRG7 BRGO CLK13 SPI SPICLK GND Inout secondary option PC18 CLK14 GND timer3 4 TGATE2 GND PC17 BRG8 BRGO CLK15 TIN3 GND PC16 CLK16 TIN4 GND 9 8 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 9 3 Port C Dedicated Pin Assignment PPARC 1 continued Pin Function PIN PSORC 0 PSORC 1 _ _ Default _ PDIRC 0 Input Default PDIRC 1 Output PDIRC 0 Input Input PDIRC 1 Output Inout if Specified Input PC15 SMC2 SMTXD SCC1 CTS by PC5 FCC1 TxAddr 0 FCC1 TxAddr 0 GND SCC1 CLSN MPHY master MPHY slave Ethernet FCC2 TxAddr 4 primary option MPHY slave PC14 SCC1 CD GND FCC1 RxAddr 0 FCC1 RxAddr 0 GND SCC1 RENA MPHY master MPHY slave Ethernet FCC2 RxAddr 4 MPHY slave PC13 TDM_D1 L1RQ SCC2 CTS by PC4 FCC1 TxAddi 1 FCC1 TxAddi 1 GND SCC2 CLSN MPHY master MPHY slave Ethernet FCC2 TxAddr 3 primary option MPHY slave PC12 SH L1ST3 SCC2 CD GND FCC1 RxAddi 1 FCC1 RxAddr 1 GND SC
88. MPC8280 bus mode the bank select signals for SDRAM accesses are multiplexed on the 60x bus address lines So for SDRAM accesses the internal address is not visible for debug purposes However the bank select signals can also be driven on dedicated pins see SIUMCR APPC In this case EAV can be used to force address visibility 0 Bank select signals are driven on 60x bus address lines There is no full address visibility 1 Bank select signals are not driven on address bus During READ and WRITE commands to SDRAM devices the full address is driven on 60x bus address lines 12 Compatibility mode enable See Section 8 4 3 8 Extended Transfer Mode of the MPC8260 PowerQUICC II User s Manual 0 Strict 60x bus mode Extended transfer mode is disabled 1 Extended transfer mode is enabled 13 Local bus compatibility mode enable See Section 8 4 3 8 Extended Transfer Mode of the MPC8260 PowerQUICC User s Manual 0 Extended transfer mode is disabled on the local bus 1 Extended transfer mode is enable on the local bus Note that if the local bus memory controller is configured to work with read modify write parity LETM must be cleared 14 EPAR Even parity Determines odd or even parity on the 60x bus 0 Odd parity 1 Even parity Writing the memory with EPAR 1 and reading the memory with EPAR 0 generates parity errors for testing 15 LEPAR Local bus even parity Determines odd or even parity on the local bus 0 O
89. Mode Clock 3 CPM Clock CPU Clock Bus Clock 6 MHz CPM MHz CPU MHz Bus MHz Multiplication _ _j Multiplication Division MODCK H Factor 4 s Factor 5 Factor MODCK 1 3 low high low high low high MODCK_H 0000 fault Modes 0000_000 2 0000_001 25 0 50 0 300 0 2 50 0 100 0 0000_010 25 0 50 0 300 0 3 50 0 100 0 0000_011 31 3 50 0 400 0 3 62 5 100 0 0000_100 0000_101 0000_110 26 8 50 0 0000_111 25 0 50 0 178 6 214 3 200 0 300 0 400 0 400 0 466 7 3 71 4 133 3 480 0 2 5 80 0 160 0 Full Configuration Modes 0001_001 50 0 50 0 4 200 0 200 0 5 250 0 250 0 4 50 0 50 0 0001 010 41 7 50 0 4 166 7 200 0 6 250 0 300 0 4 41 7 50 0 0001 011 35 7 50 0 4 142 9 200 0 7 250 0 350 0 4 35 7 50 0 0001 100 31 3 50 0 4 125 0 200 0 8 250 0 400 0 4 31 3 50 0 0010_001 25 0 50 0 6 150 0 300 0 3 180 0 360 0 2 5 60 0 120 0 0010_010 29 8 50 0 6 178 6 300 0 3 5 250 0 420 0 2 5 71 4 120 0 MOTOROLA Chapter 4 PLL and Clock Generator 4 25 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Configuration Modes Table 4 10 Clock Configurations for PCI Agent Mode PCI MODCK 1 continued
90. Mode Register U SMOD eee ecsid esee n pev rta Mo shed 7 17 USB Slave Address Register USADR 7 18 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Paragraph Number 7 5 7 3 7 5 7 4 7 5 7 5 7 5 7 6 7 5 7 7 7 6 7 6 1 7 6 2 7 6 3 7 1 7 7 1 7 7 2 7 8 7 9 7 10 7 10 1 8 1 8 2 8 3 8 3 1 8 3 2 8 4 8 5 8 5 1 8 6 8 6 1 8 6 2 8 6 3 8 6 4 8 6 5 8 6 5 1 8 6 6 MOTOROLA Freescale Semiconductor Inc Contents Page Title Number USB End Point Registers 08 7 18 USB Command Register acetate 7 20 USB Event Register QUSBER 54s ie cri de 7 21 USB Mask Register USBMEB 7 21 USB Stat s Register USBS auae eee Rete ce tiep osse ert Posh id 7 22 USB Butter Descriptor Kine poete emu es 7 22 USB Receive Buffer Descriptor Rx BD for Host and Function 7 24 USB Transmit Buffer Descriptor Tx BD for Function 7 26 USB Transmit Buffer Descriptor Tx BD for Host sess 7 28 ESBACP OMI ANON scito 7 30 STOP Tx Command sacri HO va Un ure bui DRM 7 30 RESTART Tx Comi
91. Ox1C TXUSBU 16 bits Tx microcode return address temp _PTR Ox1E 16bits Reserved 1 Offset from endpoint parameter block base Note that the items in boldface should be initialized by the user 3 These parameters need not be accessed in normal operation but may be helpful for debugging 7 5 5 Frame Number FRAME This entry is used for frame number updates both in function mode and in host mode In function mode it is updated by the USB controller in host mode it is updated by the application software This entry is updated by the USB controller in function mode whenever a SOF start of frame token is received The entry contains 11 bits that represent the frame number An SOF interrupt is issued upon an update of this entry 0 1 4 5 15 Field V FRAME NUMBER Reset 0000_0000_0000_0000 R W R W Addr USB base 0x10 Figure 7 8 Frame Number FRAME_N in Function Mode 1 This bit is set if the SOF token was received error free Table 7 6 describes FRAME_N fields Table 7 6 FRAME_N Field Descriptions Bits Name Description 0 V The valid bit is set if the SOF token is received without error 1 4 Reserved should be cleared 5 15 FRAME The frame number is loaded with the value received in the SOF packet Be sure the frame NUMBER number is cleared before beginning USB operation The entry is updated by the application software wh
92. P7 devices are available in two packages the standard ZU package and an alternate VR package as shown in Table 1 1 For information on VR packages refer to the MPC8280 Hardware Specification Note that in this document references to the MPC8280 are inclusive of the VR devices unless otherwise specified Table 1 1 HiP7 PowerQUICC II Device Packages ZU VR 480 TBGA 516 PBGA MPC8280 MPC8275VR MPC8270 MPC8270VR 1 11 Features NOTE Reference Documentation This sections supplements Section 1 1 the 8260 PowerQUICC II User s Manual The MPC8280 s enhancements are summarized below e Clock frequencies CPU Up to 450Mhz MOTOROLA Chapter 1 Overview 1 1 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Features Freescale Semiconductor Inc CPM Up to 300Mhz Bus Up to 100Mhz Communication interfaces ATM Extended number of phys for FCC2 MPC8280 only Internal Rate Scheduling for 31 PHYs 802 3x through RMII interface USBI 1 CPM RISC engine Internal multiport RAM 32 Kbytes CPM RISC Data RAM for storage of protocol parameters 32 Kbytes CPM RISC Instruction RAM for storage of CPM microcode e Universal serial bus USB controller USB host mode Supports control bulk interrupt and isochronous data transfers CRC16 generation and checking NRZI encoding decoding with bit stuffing
93. Patent and Trademark Office digital dna is a trademark of Motorola Inc All other product or service names are the property of their respective owners Motorola Inc is an Equal Opportunity Affirmative Action Employer Motorola Inc 2002 For More Information On This Product Go to www freescale com Paragraph Number 1 1 1 2 3 1 4 1 4 1 1 4 1 2 4 1 3 4 1 4 4 1 5 4 1 6 4 1 7 4 2 4 3 4 31 4 3 1 1 4 3 1 2 4 3 1 3 4 4 4 5 4 6 4 6 1 4 6 2 MOTOROLA Freescale Semiconductor Inc Contents Title Chapter 1 Overview CALITO S 8280 Architecture 0002040 enne Chapter 2 Embedded MPC603e Core Chapter 3 Memory Map Internal Memory Map Register IMMR eee Chapter 4 PLL and Clock Generator MPC8280 Clock Block erre REN UR Mami PEL ME Core PLI eit dan TEES Skew d MD IVISOTS di ici septa deo aR Internal Clock Signals cs iu aei PCI Bridge as an Agent Operating from the PCI System Clock PCI Bridge as a Host Generating the PCI System Clock External C lock Inpuls cadet ad LU Wee EP Important Differences MPC8280 vs 26 Hard Reset Configuration Word sese
94. RFCR TFCR and MRBLR fields of the endpoint 1 parameter RAM 21 Write 0 2008 2028 to DPRAM 0x528 to set up the RBPTR and TBPTR fields of the endpoint 1 parameter RAM 22 Clear TSTATE field of the endpoint 1 parameter RAM 23 Write 0x0020 to USEPO for the host control transfer multi packet 24 Write 0x1100 to USEPI for endpoint 1 interrupt transfer one packet only 25 Write 0x06 to USMOD for full speed 12 Mbps signaling local loopback configuration test and host modes set and disable the USB 26 Write 0x05 to the USAD for slave address 5 27 Set USMOD EN to enable the USB controller 28 Write 0x81 to the USCOM to start filling the Tx FIFO with endpoint 1 data ready for transmission when an IN token is received 29 Write 0x80 to the USCOM to start filling the Tx FIFO with endpoint 0 data ready for transmission The expected results are as follows e TxBD Status and Control of endpoint 0 should contain 0x3800 e TxBD Data Length of endpoint 0 should contain 0x0003 e TxBD Status and Control of endpoint 1 should contain 0x3C80 e TxBD Data Length of endpoint 1 should contain 0x0003 e RxBD Status and Control of endpoint 0 should contain 0x3C00 e RxBD Data Length of endpoint 0 should contain 0x0005 The receive buffer of endpoint 0 should contain OXABCD 122 0 42 MOTOROLA Chapter 7 Universal Serial Bus Controller 7 35 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More In
95. Reset Depends on reset configuration sequence Refer to Section 4 3 1 1 Hard Reset Configuration Word R W R W Addr 0x101A8 16 23 24 31 Field PARTNUM MASKNUM Reset R W R Addr 0x101AA Figure 3 1 Internal Memory Map Register IMMR Table 3 2 describes IMMR fields Table 3 2 IMMR Field Descriptions Bits Name Description 0 13 ISB Internal space base Defines the base address of the internal memory space The value of ISB be configured at reset to one of 8 addresses it can then be changed to any value by the software The default is 0 which maps to address 0x0000_0000 ISB defines the 14 msbs of the memory map register base address IMMR itself is mapped in the internal memory space region As soon as the ISB is written with a new base address the IMMR base address is relocated according to the ISB ISB can be configured to one of 8 possible addresses at reset to enable the configuration of multiple MPC8280 systems The number of programmable bits in this field and hence the resolution of the location of internal space depends on the internal memory space of a specific implementation In the MPC8280 all 14 bits can be programmed See the MP8260 PowerQUICC User s Manual Chapter 3 Memory Map for details on the device s internal memory map and to Chapter 5 Reset for the available default initial values Note The MPC8280 s internal address space is 256 Kbytes on the MPC8260 it is 128 Kbytes Also
96. SB This bit should be used if the function wants to exit the suspend state 2 4 Reserved should be cleared 5 TEST USB controller test loopback mode 0 Test mode is disabled 1 Test mode is enabled Note This bit may be set only when HOST is set USB host mode 6 HOST USB host mode 0 USB host disabled 1 USB host is enabled 7 EN Enable USB When the EN bit is cleared the USB is in a reset state 0 USB is disabled 1 USB is enabled Note Setting this bit automatically disables SCC4 Note Other bits of the USMOD should not be modified by the user while EN is set 7 5 7 2 USB Slave Address Register USADR The USB address register is an 8 bit memory mapped register It holds the address for this USB port when operating as function 0 1 7 Field d SADx Reset 0000 0000 R W R W Addr 0x11B61 Figure 7 12 USB Slave Address Register USADR Table 7 10 describes USADR fields Table 7 10 USADR Fields Bits Name Description 0 Reserved should be cleared 1 7 SADx Slave address 0 6 Holds the slave address for the USB port when configured as function 7 5 7 3 USB End Point Registers USEP1 USEP4 There are four memory mapped end point configuration registers 7 18 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2
97. TFCR Fields Bits Name Description 0 1 Reserved should be cleared 2 GBL Global 0 Snooping disabled 1 Snooping enabled 7 16 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 2 USB Host Description Table 7 8 RFCR and TFCR Fields continued Bits Name Description 3 4 Byte ordering This bit field should be set by the user to select the required byte ordering for the data buffer If this bit field is modified on the fly it will take effect at the beginning of the next frame 00 DEC and Intel convention is used for byte ordering swapped operation It is also called little endian byte ordering The transmission order of bytes within a buffer word is reversed as compared to the Motorola mode This mode is supported only for 32 bit port size memory 01 PowerPC little endian byte ordering As data is transmitted onto the serial line from the data buffer the least significant byte of the buffer double word contains data to be transmitted earlier than the most significant byte of the same buffer double word 1X Motorola byte ordering normal operation It is also called big endian byte ordering As data is transmitted onto the serial line from the data buffer the most significant byte of the buffer word contains data to be transmitted earlier
98. This Product Go to www freescale com Freescale Semiconductor Inc ae USB Host Description Table 7 3 USB Tokens Token Description OUT Transmission begins when The USB host controller fetches a TxBD containing OUT token and a data TxBD and loads them to the host FIFO The token and data are transmitted and a handshake is expected If a handshake is not received within the expected time interval the USB controller clears TxBD E of data BD sets the TxBD TO indication and generates an interrupt if TXBD I 1 When STALL or is received within the expected time interval the USB controller clears TXBD E of data BD sets the TxBD STALL or TXBD NAK indication and generates an interrupt if TXBD I 1 When ack received within the expected time interval the USB controller clears TxBD E of data BD generates an interrupt if TXBD I 1 No indication is set The token TxBD R is cleared right after the OUT token transmission USB Out Transaction Handshake Generated by Token Data Function Indication on TxBD OUT Sent by host None Data Discarded TO ACK None NAK NAK STALL STALL Transmission begins when the USB host controller fetches a TxBD containing an IN token and loads the token to FIFO After the IN token is transmitted the USB host controller waits for reception of data within expected time interval On reception of a correct DATA PID an RxBD is fetched The received data
99. USB Host Description 0 3 4 5 6 7 8 9 10 11 12 13 14 15 Field EPN TM MF RTE THS RHS Reset 0000_0000_0000_0000 R W R W Addr 0x11B64 USEP1 0x11B66 USEP2 0x11B68 USEP3 0x11B6A USEP4 Figure 7 13 USB End Point Registers USEP1 USEP4 Table 7 11 describes the fields of USEP1 USEP4 The setting for USB host controller should be set only in USEP1 when USMOD HOST is set Table 7 11 USEPx Fields Bits Name USB Function Mode Description USB Host Mode Description 0 3 EPN point number For USB function controller For USB host controller should be cleared defines the supported end point number 4 5 Reserved should be cleared Reserved should be cleared 6 7 ITM Transfer mode for USB function controller Transfer mode for USB host controller 00 Control 00 Control interrupt bulk 01 Interrupt 11 Isochronous 10 Bulk 11 Isochronous 8 9 Reserved should be cleared Reserved should be cleared 10 MF Enable multi frame For USB function controller Enable multi frame for USB host controller Should allows loading of the next transmit packet into the be always set FIFO before transmission completion of the previous packet 0 Transmit FIFO may hold only one packet 1 Transmit FIFO may hold more than one packet Note For USB function configuration Should be cleared unless the endpoint is configured for ISO transfer mode 11 RTE Retransm
100. _001 50 0 66 7 3 150 0 200 0 2 5 150 0 200 0 2 5 60 0 80 0 1000 010 50 0 66 7 3 150 0 200 0 3 180 0 240 0 2 5 60 0 80 0 1000 011 59 5 66 7 3 178 6 200 0 3 5 250 0 280 0 2 5 71 4 80 0 1000_100 52 1 66 7 3 156 3 200 0 4 250 0 320 0 2 5 62 5 80 0 1000_101 50 0 66 7 3 150 0 200 0 4 5 270 0 360 0 2 5 60 0 80 0 1001 000 Reserved 1001 001 Reserved 1001 010 Reserved 1001_011 62 5 66 7 4 250 0 266 6 4 250 0 266 6 4 62 5 66 7 1001_100 55 6 66 7 4 222 2 266 6 4 5 250 0 300 0 4 55 6 66 7 1010 000 Reserved MOTOROLA Chapter 4 PLL and Clock Generator 4 23 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Configuration Modes Table 4 9 Clock Configurations for PCI Agent Mode PCI MODCK O continued Mode2 PCI Clock 3 CPM Clock CPU Clock Bus Clock 6 MHz CPM MHz CPU MHz Bus MHz Multiplication Multiplication Division MODCK_H Factor 4 2 Factor 5 Factor MODCK 1 3 low high low high low high low high 1010 001 50 0 66 7 4 200 0 266 6 3 200 0 266 6 3 66 7 88 9 1010 010 53 6 66 7 4 214 3 266 6 3 5 250 0 311 1 3 71 4 88 9 1010 011 50 0 66 7 4 200 0 266 6 4 266 7 355 5 3 66 7 88 9 1010 100 50 0 66 7 4 200 0 266 6 4 5 300 0 400 0 3 66 7 88 9 1011 000 Reserved 1011 001 50 0 66 7 4 2
101. al clocks NOTE All PCI timings are measured relative to CLKINI all 60x bus timings are measured relative to CLKIN2 MPC8280 CPM CLK PCI Interface rx 96 Dividers BUS_CLK dilout PCI Circuit 60x Circuit Bus Clock PCI Clock Figure 4 2 PCI Bridge as an Agent Operating from the PCI System Clock 4 1 7 PCI Bridge as a Host Generating the PCI System Clock In a system where the MPC8280 is the host that generates the PCI clock the 60x bus clock should be driven to the CLKIN1 pin The 60x bus clock is internally multiplied by the PLL to generate the CPM high speed clock and then internally divided to generate the PCI bus clock The PCI bus clock is then driven by the DLL circuit to the DLLOUT pin which has a feedback path from the board to the CLKIN2 pin This feedback controls clock skew by ensuring the same internal and external clock timing NOTE All PCI timings are measured relative to CLKIN2 and all 60x bus timings are measured relative to CLKINI 4 4 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc External Clock Inputs CPM CLK MPC8280 PCI Interface dllout 60x Circuit PLL PCI Circuit PCI CLK clkin2 clkin1 PCI Clock 60x Bus Clock F
102. and DATA PID are stored in receive FIFO If RXBD E is set PID and data will be moved to the buffer While receiving the data the USB host controller calculates CRC16 performs bit un stuffing On end of reception calculated CRC is compared to received and octet alignment is checked RxBD E is cleared RxBD PID is set according to received DATA PID and error indications are set if required RXBD CR for failed CRC check RxBD NO for non octet sized data RxBD AB if bit stuffing error occurred If no correct DATA PID or no data at all received during the expected time interval a TO indication in the token TxBD is set USB In Transaction Data Transmitted by Handshake Generated by Token Function Host Indication on BD IN Received correctly ACK RxBD E is cleared Received corrupted None RxBD CR or RxBD AB or RxBD NO None None TxBD TO SETUP The format of setup transactions is similar to OUT but uses a SETUP rather than an OUT PID A SETUP token is recognized only by a control endpoint and cannot be answered with NAK or STALL there for host expects either ack or no handshake at all MOTOROLA Chapter 7 Universal Serial Bus Controller 7 11 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc USB Host Description Table 7 3 USB Tokens continued Token Description Start of SOF is
103. ardware independent 7 39 1 USB Controller Pin Functions and Clocking The USB controller interfaces to the USB bus through a differential line driver and differential line receiver The OE output enable signal enables the line driver when the USB controller transmits on the bus MPC8280 USB transceiver USBOE USBTXP D USBTXN D USBRXD USBRXP lt USBRXN 4 Figure 7 1 USB Interface The reference clock for the USB controller USBCLK is used by the DPLL circuitry to recover the bit rate clock The source for USBCLK is selected in CMXSCR TSACS refer to Section 15 4 5 in the MPC8260 PowerQUICC II User s Manual The MPC8280 run at different frequencies but the USB reference clock must be four times the USB bit rate Thus USBCLK must be 48 MHz for a 12 Mbps full speed transfer or 6 MHz for a 1 5 Mbps low speed transfer MOTOROLA Chapier 7 Universal Serial Bus Controller 7 3 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc USB Function Description There are six I O pins associated with the USB port Their functionality is described in Table 7 1 Additional control lines that might be needed by some transceivers e g speed select low power control may be supported by general purpose output lines Table 7 1 USB Pin
104. assumed 1 An external secondary cache controller is assumed 5 7 L2D 12 cache hit delay Controls the number of clock cycles from the assertion of TS until HIT is valid 8 PLDP Pipeline maximum depth See Section 8 4 5 Pipeline Control of the MPC8260 PowerQUICC II User s Manual 0 The pipeline maximum depth is one 1 The pipeline maximum depth is zero 9 DREF Disable reflection Disables reflection of system bus reflection on external pins of internal transfers on 60x bus For 8101 0 Enable reflection 1 Disable reflection 10 DAM Delay all masters Applies to all the masters on the bus CPU EXT CPM This bit is similar to BCR EXDD but with opposite polarity 0 The memory controller asserts CS on the cycle following the assertion of TS by a master accessing an address space controlled by the memory controller 1 The memory controller inserts one wait state between the assertion of TS and the assertion of CS when a master accesses an address space controlled by the memory controller MOTOROLA Chapter 6 System Interface Unit 6 5 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Bus Configuration Register BCR Table 6 4 BCR Field Descriptions continued Bits Name Description 11 Enable address visibility Normally when the MPC8280 is single
105. ble an interrupt from the SDMA bus error event is higher priority than an USB interrupt and an interrupt from IDMA1 is lower priority than an interrupt from USB All other interrupts do not change relative priorities Table 6 1 Interrupt Source Priority Levels Priority Level Interrupt Source Description Multiple Events 1 33 same as MPC8260 PowerQUICC II User s Manual 34 SDMA Bus Error Yes 35 USB Yes 36 IDMA1 Yes 37 74 same as in MPC8260 PowerQUICC II User s Manual 6 2 Interrupt Vector Generation and Calculation NOTE Reference Documentation The following table supplements Table 4 3 in Section 4 2 4 Interrupt Vector Generation and Calculation of the 8260 PowerQUICC II User s Manual MOTOROLA Chapter 6 System Interface Unit 6 1 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com L T Freescale Semiconductor Inc CPM Low Interrupt Priority Register SCPRR Changes to the interrupt vector table appear in boldface Table 6 2 Encoding the Interrupt Vector Interrupt Number Interrupt Source Description Interrupt Vector 0 10 same as in MPC8260 0200 0000 0b00 1010 PowerQUICC II User s Manual 11 USB ObOO 1011 12 43 same as in MPC8260 ObOO 1100 0010 1011 PowerQUICC II User s Manual 44 TC layer 0b10 1100 45 47 Reserved 0b10 1101 10 1111 48 63 same as in MPC8260 0011 0000 0011 1111
106. by 32 11 Divide by 128 MOTOROLA Chapter 4 PLL and Clock Generator 4 9 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc System Clock Mode Register 5 4 5 System Clock Mode Register SCMR The PLL low power and reset control register SCMR shown in Figure 4 7 hold the parameters necessary for determining the output clock frequencies To understand how the interaction of these values refer to Section 4 1 8280 Clock Block Diagram 0 2 3 7 8 11 12 15 Field CORECNF BUSDF CPMDF Reset 000 Refer to Table 4 4 R W R Addr 0x10C88 16 27 28 31 Field PLLMF Reset 0000_0000_0000 Refer to Table 4 4 R W R Addr 0x10C8A Figure 4 7 System Clock Mode Register SCMR Table 4 4 describes SCMR fields Table 4 4 SCMR Field Descriptions Defaults Bits Name Description POR Hard Reset 0 2 Reserved 3 7 CORECNF Config pins Unaffected Core PLL configuration 8 11 BUSDF Config pins Unaffected 60x bus division factor 12 15 CPMDF Config pins Unaffected CPM division factor This value is always 1 16 27 Reserved 28 31 PLLMF Config pins Unaffected PLLMF control the value of the divider in the PLL feedback loop 4 10 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Produ
107. by BDs organized in BD rings located in the dual port RAM refer to Figure 7 17 These rings have the same basic configuration as those used by the SCCs and SMCs There are four separate transmit BD rings and four separate receive BD rings one for each endpoint The BD ring allows the user to define buffers for transmission and buffers for reception Each BD ring forms a circular queue The CP confirms reception and transmission or indicates error conditions using the BDs to inform the processor that the buffers have been serviced 7 22 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc USB Buffer Descriptor Ring The buffers may reside in either external or internal memory DUAL PORT RAM TX BUFFER DESCRIPTORS EXTERNAL MEMORY gt L gt FRAME STATUS ENDPOINT 1 DATA LENGTH TX BD TABLE DATA POINTER p TX DATA BUFFER u e TX BUFFER DESCRIPTORS N ENDPOINT 4 x TX BD TABLE FRAME STATUS N DATA LENGTH DATA POINTER p DATA BUFFER N r
108. ce must be initialized by the user 2 All fields should be prepared by the user before transmission Table 7 16 describes USB TxBD fields Table 7 16 USB Function Tx BD Fields Offset Bit Name Description 0x00 0 R Ready bit after the buffer has been transmitted or after an error condition is encountered written by the user once this bit is set 0 The data buffer associated with this BD is not ready for transmission The user is free to manipulate this BD or its associated data buffer The CP clears this 1 The data buffer which has been prepared for transmission by the user has not been transmitted or is currently being transmitted No fields of this BD may be 1 Reserved should be cleared 7 26 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Offset Bit Freescale Semiconductor In Table 7 16 Name Buffer Descriptor Ring USB Function Tx BD Fields continued Description Wrap Final BD in Table 0 This is not the last BD in the Tx BD table 1 This is the last BD in the Tx BD table After this buffer has been used the CP will send data using the first BD in the table the BD pointed to by TBASEx The number of Tx BDs in this table is programmable and is determined only by the Tx BD W and the overall space constraints of the dual port RAM Interrup
109. ck Generator 4 27 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Configuration Modes Table 4 10 Clock Configurations for PCI Agent Mode PCI MODCK 1 continued Mode PC Clock 3 CPM Clock CPU Clock Bus Clock 6 MHz CPM MHz CPU MHz Bus MHz Multiplication Multiplication Division MODCK H Factor 4 Factor 5 2 Factor MODCK 1 3 low high low high low high low high 1101 011 25 0 50 0 6 150 0 300 0 4 5 270 0 540 0 2 5 60 0 120 0 1101 100 25 0 50 0 6 150 0 300 0 5 300 0 600 0 2 5 60 0 120 0 1110 000 25 0 50 0 5 125 0 250 0 2 5 156 3 1312 5 2 62 5 125 0 1110 001 25 0 50 0 5 125 0 250 0 3 187 5 375 0 2 62 5 125 0 1110_010 28 6 50 0 5 142 9 250 0 3 5 250 0 437 5 2 71 4 125 0 1110 011 25 0 50 0 5 125 0 250 0 4 250 0 500 0 2 62 5 125 0 1110 100 37 5 50 0 5 187 5 250 0 4 250 0 333 3 3 62 5 83 3 1110_101 33 3 50 0 5 166 7 250 0 4 5 250 0 375 0 3 55 6 83 3 1110_110 30 0 50 0 5 150 0 250 0 5 250 0 416 7 3 50 0 83 3 1110 111 27 3 50 0 5 136 4 250 0 5 5 250 0 458 3 3 45 5 83 3 1100 000 25 0 50 0 4 100 0 200 0 Bypass 50 0 100 0 2 50 0 100 0 1100 001 25 0 50 0 6 150 0 300 0 Bypass 60 0 120 0 2 5 60 0 120 0 1100 010 25 0 50 0 6
110. criptions 22244 4 20 8 8 IRSRx HI Field Descriptions TIREM 1 cece eee eeseceseceseeesnceceaecneenseeesneeenaeenes 8 9 FIRSRx_LO Field Descriptions TIREM 1 4 4 2 11121 2 445 4 100 8 10 PRR Field a o teta Ie 8 11 Port A Dedicated Pin Assignment 1 2 4 4 101 9 1 Port Dedicated Pin Assignment PPARB 1 9 5 Port Dedicated Pin Assignment PPARC 1 0000001 9 7 Port D Dedicated Pin Assignment 1 9 10 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Figures Figure Page Number Title Number 1 1 MPC38280 Block Di agtatnb oeste es e SAIS vn acy a Sae Tee RENE IAS EN HERES 1 3 3 1 Internal Memory Map Register 3 3 4 1 MPC8280 System Clock Architecture 4 3 4 2 PCI Bridge as an Agent Operating from the PCI System Clock 4 4 4 3 PCI Bridge as a Host Generating the PCI System Clock 4 5 4 4 Filtering Circuit M 4 6 4 5 Hard Reset Configuration WOI
111. ct Go to www freescale com Freescale Semiconductor Inc Clock Configuration Modes 4 6 Clock Configuration Modes The MPC8280 has three clocking modes local PCI host and PCI agent The clocking mode is set according to three input pins PCI_MODE PCI_CFG 0 PCILMODCK as shown in Table 4 5 Table 4 5 MPC8280 Clocking Modes Pins PCI Clock Clocking Mode Frequency Range Reference PCI MODE PCI CFG 0 PCI MODCK MHZ 1 Local bus Table 4 6 0 0 0 PCI host 50 66 Table 4 7 0 0 1 25 50 Table 4 8 0 1 0 PCI agent 50 66 Table 4 9 0 1 1 25 50 Table 4 10 1 Determines PCI clock frequency range Refer to Section 4 6 2 PCI Mode In each clocking mode the configuration of bus core PCI and CPM frequencies is determined by seven bits during the power up reset three hardware configuration pins MODCK 1 3 and four bits from hardware configuration word 28 31 MODCK Both the PLLs and the dividers are set according to the selected MPC8280 clock operation mode as described in the following sections 4 6 1 Local Bus Mode Table 4 6 lists default and full configurations for the MPC8280 in local bus mode NOTE Clock configuration is set while POR is asserted Table 4 6 Local Bus Clock Modes 2 3 3 3 Bus MES CPM peas CPU ee MHz Multiplication MHz Multiplication MHz 4 250 0 533 3 250 0 666 7 250 0 400 0 250 0 500 0 125 0 417 5
112. d per PHY is configured by registers FTIRR 0 3 In internal rate expanded mode GFEMR TIREM 1 registers FTIRR 0 3 control the available rates but the PHY settings are configured in registers FIRPER FIRSR_HI and FIRSR_LO In TIREM 0 mode internal rate can only be used for PHYs 0 3 whereas in TIREM 1 mode up to 31 PHYs are supported If TIREM 1 mode is selected the transmit internal rate underrun TIRU status per PHY may be read at any time in register FIRER 8 6 2 FCC Transmit Internal Rate Port Enable Register FIRPER This register enables internal rate transmission for PHYs 0 30 It is valid only if GFEMR TIREM 1 If a PHY is not enabled in FIRPER all TxClav indications from that PHY will be masked The user should configure FIRPER according to the PHY addresses which are being used on the UTOPIA bus and should not enable PHYs with addresses larger then the last PHY address set by FPSMR Last PHY PHYs can be enabled or disabled at any time for example if a TIRU event has occurred 8 6 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ATM Registers 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field PEO 1 PE2 PE4 PES PE6 PE7 PE8 9 10 PE11
113. dd parity 1 Even parity Writing the memory with LEPAR 1 and reading the memory with LEPAR 0 generates parity errors for testing 16 18 NPQM Non PowerQUICC II master Identifies the type of bus masters which are connected to the arbitration lines when the MPC8280 is in internal arbiter mode Possible types are PowerQUICC II master and non PowerQUICC II master This field is related to the data pipelining bits BRx DR in the memory controller Because an external bus master that is not a MPC8280 cannot use the data pipelining feature the MPC8280 which controls the memory needs to know when a non PowerQUICC II master is accessing the memory and handle the transaction differently NPQM 0 designates the type of master connected to the set of pins BR BG and NPQM 1 designates the type of master connected to the set of pins EXT BR2 EXT BG2 and EXT DBGa2 NPQM 2 designates the type of master which is connected to the set of pins EXT EXT and EXT DBGS3 0 The bus master connected to the arbitration lines is a MPC8280 1 The bus master connected to the arbitration lines is not a MPC8280 19 20 Reserved should be cleared 6 6 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Configuration Register BCR Table 6 4 BCR Field Descriptions continued
114. dition and in internal rate mode only FCCE TIRU is set and if the corresponding bit in the FCC mask register FCCM TIRU is set an interrupt is generated If TIREM 1 the TIRU status per PHY can be read at any time in the FCC internal rate event register FIRER Once FIRER TIRUy error status 15 set it can be cleared only by writing 1 to it To prevent an underrun PHY from continuously reporting errors it can be disabled by FIRPER The sequence of disabling a PHY is as follows e Disable PHY y by clearing FIRPER y Clear event FIRER y by writing 1 to it Clear event FCCE TIRU by writing 1 to it MOTOROLA Chapter 8 Fast Communication Controller FCC 8 7 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ATM Registers 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Field TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Reset 0000_0000_0000_0000 R W R W Addr 0x11384 FIRER1 0x113A4 FIRER2 0 113 4 FIRERS 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU TIRU 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Reset 0000_0000_0000_0000 R W R W Addr
115. ds the handshake selected in the endpoint configuration register USEPn RHS see table below to the host If an error occurs no handshake packet is returned and error status bits are set in the last RxBD associated with this packet USB Out Token Reception Data Packet USEPn RHS Corrupted Handshake Sent to Host XX Yes None Data Discarded 00 Normal No ACK 01 Ignore No None 10 No NAK 11 STALL No STALL To guarantee a transfer the control software must preload the endpoint FIFO with a data packet before receiving an IN token Software should set up the endpoint TxBD table and set USCOM STR The USB controller fills the transmit FIFO and waits for the IN token Once the token is received and the FIFO has been loaded with the last data byte or with at least four bytes transmission begins The four byte minimum is a threshold to prevent underruns in the FIFO If data is not ready in the transmit FIFO or if USEPn THS is set to respond with handshake is returned If USEPn THS was set to respond with STALL a STALL handshake is returned See table below When the end of the last buffer is reached TxBD L is set the CRC is appended After the frame is sent the USB controller waits for a handshake packet If the host fails to acknowledge the packet the timeout status bit TXBD TO is set Software must set the proper DATAO DATA1 PID in the transmitted packet USB In Tok
116. e USB Base 04 EP2PTR Half Word Figure 7 7 The map of the endpoint parameter block is shown in Table 7 5 Note When USB host mode is set EPOPTR must be used for the host end USB Base 06 EPAPTR Half Word point USB Base 08 RSTATE Word Receive internal state Reserved for CP use only Should be cleared before enabling the USB controller USB Base 0 RPTR Word Receive internal data pointer Updated by the SDMA channels to show the next address in the buffer to be accessed USB Base 10 FRAME N Half Word Frame number See Figure 7 8 Note The definition of this parameter is different for host mode and function mode USB Base 12 RBONT Half Word Receive internal byte count A down count value that is initialized with the MRBLR value and decremented with every byte written by the SDMA channels USB Base 14 RTEMP Word Receive temp Reserved for CP use only USB Base 18 RXUSB Word Rx Data temp Data USB Base 1C RXUPTR Half Word Rx microcode return address temp Theitems in boldface should be initialized by the user before the USB controller is enabled other values are initialized by the CP Once initialized the parameter RAM values do not normally need to be accessed by user software They should only be modified when no USB activity is in progress 7 5 4 End Point Parameters Block Pointer EPXPTR The endpoint parameter block pointers EPXPTR are DPRAM in indices to an
117. e the fast PHYs should be assigned consecutive addresses starting at 0 and fixed priority mode should be chosen 8 12 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Chapter 9 Freescale Semiconductor Inc Parallel I O Ports NOTE Reference Documentation The following tables replace those in Chapter 35 Parallel I O Ports in the MPC8260 PowerQUICC II User s Manual MPC8280 parallel I O ports are backward compatible to previous PowerQUICC II devices Additional pin multilexing options were added in order to support e USB 1 1 in place of TDMAI SMC2 TDMD2 no clks SCC1 FCC2 Master Mphy 32 MultiPHY for each FCC in place of TDMA1 SMC2 Additions appear in red boldface Table 9 1 shows the port A pin assignments Table 9 1 Port A Dedicated Pin Assignment PPARA 1 Pin Function PSORA 0 PSORA 1 Pin _ Default _ PDIRA 0 Input or Default PDIRA 1 Output PDIRA 0 Input Input PDIRA 1 Output Inout if Specified Input PA31 FCC1 TxEnb FCC1 TxEnb FCC1 COL GND UTOPIA master UTOPIA slave MII PA30 FCC1 TxClav FCC1 TxClav FCC1 RTS FCC1 CRS GND UTOPIA slave UTOPIA master MII FCC1 TxClavO MPHY master direct polling PA29 FCC1 TxSOC 1 ER UTOPIA MII PA28 FCC1 RxEnb FCC1 RxEnb GND FCC1 TX EN UTOPIA master UTOPIA sla
118. ed using a USB traffic generator 1 Clear PDIRD 22 and set PPARD 22 to select USBRXD Clear PDIRC 8 9 and set PPARC 8 9 to select USBRXP and USBRXN Set PDIRD 20 21 and PPARD 20 21 to select USBTXP and USBTXN Set PDIRC 20 and PPARC 20 to select USBOE Clear FRAME N M oO ta BOO D Program CMXSCR to provide a 48 MHz clock to the USB controller Write DPRAM 0x500 to EPOPTR DPRAM 0x520 to EPIPTR DPRAM 0x540 to EP2PTR and DPRAM 0x560 to EP3PTR to set up the endpoint pointers Write OXBC80 0004 to DPRAM 0x20 to set up the TxBD Status and Control Data Length fields of endpoint 0 Write DPRAM 0x200 to DPRAM 0x24 to set up the TxBD Buffer Pointer field of endpoint 0 10 Write 0004 to DPRAM 0x28 to set up the TxBD Status and Control Data Length fields of endpoint 1 11 Write DPRAM 0x210 to DPRAM 0x2C to set up the TxBD Buffer Pointer field of endpoint 1 12 Write OxBC80_0004 to DPRAM 0x30 to set up the TxBD Status and Control Data Length fields of endpoint 2 MOTOROLA Chapter 7 Universal Serial Bus Controller 7 31 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc USB Function Controller Initialization Example 13 Write DPRAM 0x220 to DPRAM 0x34 to set up the TxBD Buffer Pointer field of endpoint 2 14 Write OxBCCO_0004 to DPRAM 0x38 to set up the TxBD Status and Control
119. eescale Semiconductor Inc Table 5 4 CP Command Opcodes continued Channel Opcode SMC SMC FCC USB SCC UART GCI SPI IDMA Special Transparent 1011 USB STOP RESTART TX IDMA ENDPOINT 1100 ar um NE HER RANDOM NUMBER 11xx Undefined Reserved for use by Motorola supplied RAM microcodes The commands in Table 5 4 are described in Table 5 5 Table 5 5 Command Descriptions Command Description INIT TX AND Initialize transmit and receive parameters Initializes the transmit and receive parameters in the RX PARAMS parameter RAM to the values that they had after the last reset of the CP This command is especially useful when switching protocols on a given serial channel INIT RX Initialize receive parameters Initializes the receive parameters of the serial channel PARAMS INIT TX Initialize transmit parameters Initializes the transmit parameters of the serial channel PARAMS ENTER Enter hunt mode Causes the receiver to stop receiving and begin looking for a new frame The exact HUNT MODE operation of this command may vary depending on the protocol used STOP TX Stop transmission Aborts the transmission from this channel as soon as the transmit FIFO has been emptied It should be used in cases where transmission needs to be stopped as quickly as possible Transmission
120. en Reception USEPn THS FIFO Loaded Handshake Sent to Host 00 Normal No NAK Yes Data packet is sent 01 Ignore 10 NAK 11 STALL STALL MOTOROLA Chapter 7 Universal Serial Bus Controller 7 7 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc USB Host Description Table 7 2 USB Tokens continued Token Description SETUP The format of setup transactions is similar to OUT but uses a SETUP rather than an OUT PID A SETUP token is recognized only by a control endpoint When a SETUP token is received setup reception begins The USB controller fetches the next BD associated with the endpoint if it is empty the controller starts transferring the incoming packet to the buffer When the buffer is full the USB controller clears RxBD E and generates an interrupt if RxBD I 1 If the incoming packet is larger than the buffer the USB controller fetches the next BD and if it is empty continues transferring the rest of the packet to this buffer The entire data packet including the DATAO PID is written to the receive buffers If the packet was received without CRC or bit stuff errors an ACK handshake is sent to the host If an error occurs no handshake packet is returned and error status bits are set in the last RxBD associated with this packet Start of When an SOF
121. endpoint s parameter block The parameter block can be allocated to any address that is divisible by 32 The format of the endpoint pointer registers EPxPTR is shown in Figure 7 7 MOTOROLA Chapter 7 Universal Serial Bus Controller 7 13 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com USB Host Description Field R W Reset Addr Freescale Semiconductor Inc 10 11 15 Endpoint Index Pointer zm R W 0000_0000_0000_0000 USB base 0x00 EPOPTR 0x02 EP1PTR 0x04 EP2PTR 0x06 EP3PTR Figure 7 7 Endpoint Pointer Registers EPxPTR The map of the endpoint parameter block is shown in Table 7 5 Table 7 5 Endpoint Parameter Block Offset Name 2 Width Description 0x00 RBASE 16 bits 0x02 TBASE 16 bits RxBD TxBD base addresses Define the starting location in dual port RAM for the USB controller s TxBDs and RxBDs This provides flexibility in how BDs are partitioned Setting W in the last BD in each list determines how many BDs to allocate for the controller s send and receive sides These entries must be initialized before the controller is enabled Overlapping USB BD tables with another serial controllers BDs causes erratic operation RBASE and TBASE values should be divisible by 8 0x04 RFCR 8 bits 0x05 0x06 0x08 OX0A OX0C TFCR MRBLR RBPTR TBPTR TSTATE 8 bits 1
122. enever a SOF start of frame token should be received The software should prepare the frame number and the CRC and place itin FRAME N field MOTOROLA Chapter 7 Universal Serial Bus Controller 7 15 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc USB Host Description 0 1 4 5 6 7 8 9 10 11 12 13 14 15 Field CRC5 FRAME NUMBER Reset 0000_0000_0000_0000 R W R W Addr USB base 0x10 Figure 7 9 Frame Number FRAME_N in Function Mode Table 7 6 describes FRAME_N fields Table 7 7 FRAME_N Field Descriptions Bits Name Description 0 4 CRC5 CRC5 calculated on frame number 5 11 FRAME The frame number is inserted by the application software NUMBER NOTE The FRAME NUMBER field is also updated by the USB controller when the USB controller is configured as the host thus indicating that SOF was transmitted Therefore the FRAME NUMBER field should always be regenerated and rewritten to the entry before SOF is issued 7 5 6 USB Function Code Registers RFCR and TFCR and TFCR control the value that the user would like to appear on the Address Type pins AT1 AT3 when the associated SDMA channel accesses memory 0 1 2 3 4 5 6 7 Field GBL BO TC2 DTB Figure 7 10 USB Function Code Registers RFCR and TFCR Table 7 8 describes RFCR and TFCR fields Table 7 8 RFCR and
123. er 8 Fast Communication Controller FCC 8 5 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ATM Registers Internal rate expanded mode The total transmission rate is determined by the FCC internal rate timers and by the assignment of rate per PHY In this mode the FCC does not insert idle unassign cells The internal rate expanded mode differs from the internal rate mode in that the internal rate mechanism is extended for 31 PHY devices PHY addresses 0 30 and there cannot be a mix of external and internal rate PHYs Expanded internal rate is configured by registers GFEMRx FIRPERx FIRSRx_HI FIRSRx_LO and by FTIRRx Another feature of internal rate expanded mode is an indication of transmit underrun error status per PHY When using internal rate expanded mode the user assigns one of the baud rate generators BRGs to clock the four internal rate timers and any timer can trigger any PHY 8 6 ATM Registers NOTE This section applies to the MPC8280 only The MPC8270 does not support ATM The following sections describe the configuration of the registers in ATM internal rate mode 8 6 1 FCC Transmit Internal Rate Mode In internal rate mode the total transmission rate is the sum of the rates assigned for all PHYs This register controls how internal rate is configured In internal rate mode GFEMR TIREM 0 the internal rate assigne
124. et Controller Table 8 1 GFEMRx Field Descriptions Bit Name Description 0 TIREM Transmit internal rate expanded mode ATM mode 0 Internal rate mode Internal rate for PHYs 0 3 is controlled only by FTIRR 0 3 FIRPER FIRSR FIRSR LO FITER are unused 1 Internal rate expanded mode PHYs 0 31 are controlled by FTIRR 0 3 FIRPER FIRSR and FIRSR LO Underrun status for PHYs 0 31 is available by FIRER This bit should be set only in transmit master multi PHY mode In this mode mixing of internal rate and external rate is not enabled 1 LPB RMII Loopback diagnostic mode Ethernet mode 0 Normal mode 1 Loopback mode 2 CLK RMII reference clock rate for 50 Mhz input clock from external oscillator Ethernet mode 0 50 Mhz for Fast Ethernet 1 5 Mhz for 10BaseT 3 7 Reserved should be cleared 8 3 Fast Ethernet Controller 8 3 1 FCC Ethernet Mode Register FSPMR NOTE Reference Documentation This section replaces Section 30 18 1 in the MPC8 amp 260 PowerQUICC II User s Manual The MPC2880 supports 10 100 Mbps Ethernet through a RMII interface according to RMII Specification March 20 1998 The RMII use a single reference clock 50 MHz and seven pins which are a proper subset of the MII interface pins Ethernet features are unchanged in RMII mode To select RMII PHY interface a mode bit in the Ethernet mode register FPSMR has been added as shown in Figure 8 2 0 1 2 3 4 5
125. formation On This Product Go to www freescale com Freescale Semiconductor Inc Programming the USB Host Controller 7 36 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 8 Fast Communication Controller FCC NOTE Reference Documentation This chapter is an addendum to the MPC8260 PowerQUICC II User s Manual it supplements Chapters 28 30 8 1 FCC Enhancements Overview The MPC8280 FCC has the following enhanced features this list supplements the list on page 28 1 of the MPC8260 PowerQUICC II User s Manual 10 100 Mbps Ethernet through RMII interface e ATM internal rate mode for 31 PHYs e ATM 31 PHY addresses for both FCC1 and FCC2 8 2 General FCC Expansion Mode Register GFEMR The general FCC expansion mode register GFEMR defines the expansion modes It should be programmed according to the protocol used 0 1 2 3 7 Field TIREM LPB CLK m Reset 0000 0000 R W R W Addr 0x11390 GFEMR1 0x113B0 GFEMR2 0x113D0 GFEMR3 Figure 8 1 General FCC Expansion Mode Register GFEMR Table 8 1 describes fields MOTOROLA Chapter 8 Fast Communication Controller FCC 8 1 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Fast Ethern
126. frames 12 13 Reserved should be zero 14 RMII RMII interface mode 0 MII interface 1 interface RMII to from MII conversion logic is enabled MOTOROLA Chapter 8 Fast Communication Controller FCC 8 3 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Fast Ethernet Controller Table 8 2 FPSMR Ethernet Field Descriptions continued Bits Name Description 15 20 Reserved should be zero 21 CAM CAM address matching 0 Normal operation 1 Use the CAM for address matching CAM result 16 bits is added at the end of the frame 22 BRO Broadcast address 0 Receive all frames containing the broadcast address 1 Reject all frames containing the broadcast address unless FSMR PRO 1 23 Reserved should be zero 24 25 CRC CRC selection Ox Reserved 10 32 bit CCITT CRC Ethernet X32 X26 X23 X22 X16 X12 X11 X10 X8 X7 X5 X4 X2 X1 1 Select this to comply with Ethernet specifications 11 Reserved 26 31 Reserved should be zero 8 3 2 Connecting the MPC8280 to Ethernet RMIl NOTE Reference Documentation This section is an addition to Chapter 30 Fast Ethernet Controller in the 8260 PowerQUICC II User s Manual Figure 8 3 shows the basic components of the reduced media independent interface RMIT and the signals requi
127. g 8 6 5 1 Example If the MPC8280 is connected to four 155 Mbps PHY devices and the maximum transmission rate is 155 Mbps for the first PHY and 10 Mbps for the rest of the PHYs the BRG CLK should be set according to the highest rate If the system clock is 133 MHz the BRG should be programmed to divide the system clock by 362 to generate cell transmit requests every 362 system clocks 133MHz x 53 x 8 155 52Mbps For the 155 Mbps PHY the FTIRR divider should be programmed to zero the BRG CLK is divided by one for the rest of the 10 Mbps PHYs the FTIRR divider should be programmed to 14 the BRG CLK is divided by 15 362 8 6 6 Internal Rate Programming Model The programming sequence in TIREM 0 mode is as follows 1 Clear GFEMRx TIREM 2 Program FTIRRx MOTOROLA Chapter 8 Fast Communication Controller FCC 8 11 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com ATM Registers Freescale Semiconductor Inc The programming sequence in TIREM 1 mode is as follows Clear FTIRRx TRM Set GFEMRx TIREM Program FIRSRx HI and FIRSRx LO Program FTIRRx 5 Program FIRPERx BR U N If FTIRRx are set to generate same order of magnitude rates setting round robin polling mode is more adequate than fixed priority mode To reduce the risk of transmit underrun if there are a few PHYs with high internal rate and a number of PHYs with a low internal rat
128. generated every 1 ms The timing must be exact and is controlled by a CPM timer programed by Frame the user From the host state machine point of view it is a packet to transmit placed in its FIFO SOF transmitted as is Preamble The PRE token signals the hub that a low speed transaction is about to occur The PRE token is read PRE only by the hub The USB host controller generates a full speed PRE token before sending a packet to a low speed peripheral 7 5 2 SOF Transmission for USB Host Controller SOF packets should be transmitted every 1115 The following section describes the mechanism that supports it Because the precision of the time interval between two SOF packets is strict a CPM timer or BRG may be used to assert an external interrupt to the CP The user should program the CPM timer or the BRG to a value that is equal to 1 ms time interval Before each expiration the software should prepare a value for the frame number and crc5 to be transmitted in SOF token and place it in the parameter RAM for further details please refer to Section 7 5 5 Frame Number FRAME On timer expiration or on BRG clock phase change the external interrupt is asserted When the external interrupt is serviced by the CP a microcode routine prepares a SOF token and loads it to the host endpoint Once it is loaded to FIFO it is transmitted as any other token The application software should guarantee that the USB host has completed all
129. gister may be masked in the USB mask register The USBER may be read at any time A bit is cleared by writing a one writing a zero does not affect a bit s value More than one bit may be cleared at a time All unmasked bits must be cleared before the CP will clear the internal interrupt request This register is cleared at reset 0 5 6 7 8 9 10 11 12 13 14 15 Field RESET IDLE TXE4 TXE3 2 TXE1 SOF BSY TXB RXB Reset 0000_0000_0000_0000 R W R W Addr 0x11B70 Figure 7 15 USB Event Register USBER Table 7 13 describes USBER fields Table 7 13 USBER Fields Bit Name Description Reserved should be cleared Reset condition detected USB reset condition was detected asserted IDLE status changed A change in the status of the serial line was detected The real time suspend status is reflected in the USB status register Tx error An error occurred during transmission for End Point x packet not acknowledged or underrun Start of frame A start of frame packet was received The packet is stored in the FRAME_N parameter ram entry Busy condition Received data has been discarded due to a lack of buffers This bit is set after the first character is received for which there is no receive buffer available Tx buffer A buffer has been transmitted This bit is set once the transmit data of the last character in the buffer was written to the transmit FI
130. h FCC1 and FCC2 To utilize this feature do the following Program CMXUAR MAD4 1 Program CMXUAR MAD3 1 Select dedicated UTOPIA address lines for FCC2 in the parallel I O TxADDR 4 3 RxADDR 4 3 Refer to Chapter 9 Parallel I O Ports of this document and Section 15 4 1 CMX UTOPIA Address Register CMXUAR in the MPC8260 PowerQUICC II User s Manual 8 5 ATM Expanded Internal Rate NOTE This section applies to the MPC8280 only The MPC8270 does not support ATM 8 5 1 Transmit External Rate and Internal Rate Modes The ATM controller supports the following three rate modes e External rate mode The total transmission rate is determined by the PHY transmission rate The FCC sends cells to keep the PHY FIFOs full the FCC inserts idle unassign cells to maintain the transmission rate Internal rate mode The total transmission rate is determined by the FCC internal rate timers In this mode the FCC does not insert idle unassign cells The internal rate mechanism is supported for the first four PHY devices PHY address 0 3 Each PHY has its own FTIRR described in Section 8 6 5 FCC Transmit Internal Rate Register FTIRRx The FTIRR includes the initial value of the internal rate timer A cell transmit request is sent when an internal rate timer expires When using internal rate mode the user assigns one of the baud rate generators BRGs to clock the four internal rate timers MOTOROLA Chapt
131. his Product Go to www freescale com Freescale Semiconductor Inc PLL Pins 100hm von VCCSYN 10uF 0 1uF Figure 4 4 PLL Filtering Circuit 4 3 14 Important Differences MPC8280 vs MPC826x A 4 3 1 1 Hard Reset Configuration Word NOTE Reference Documentation This section replaces Section 5 4 1 Hard Reset Configuration Word in MPC6260 PowerQUICC II User s Manual Note the addition of bit 12 PLLBP this is the only change The contents of the hard reset configuration word are shown in Figure 4 5 1 2 3 4 5 6 7 8 9 10 11 12 13 15 EXMC CDIS ISPS L2CPC DPPC PLLBP 0000 0000 0000 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 31 BMS LBPC APPC CS10PC ALD EN MODCK 0000 0000 0000 0000 Field EARB Reset Field Reset Figure 4 5 Hard Reset Configuration Word Table 4 2 describes hard reset configuration word fields Table 4 2 Hard Reset Configuration Word Field Descriptions Bits Name Description 0 EARB External arbitration Defines the initial value for ACR EARB If EARB 1 external arbitration is assumed See Section 4 3 2 2 60x Bus Arbiter Configuration Register PPC_ACR in the 8260 PowerQUICC II User s Manual 1 EXMC External MEMC Defines the initial value of BRO EMEMC If EXMC 1 an external memory controller is assumed See Section 10 3 1 Base Registers BRx in the MPC8260
132. ication or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and the Stylized M Logo are registered in the U S
133. igure 4 3 Bridge as a Host Generating the PCI System Clock 4 2 External Clock Inputs The input clock source to the PLL is an external clock oscillator at the bus frequency The PLL skew elimination between the CLOCKIN pin and the internal bus clock is guaranteed 4 3 PLL Pins Table 4 1 shows the dedicated PLL pins Table 4 1 Dedicated PLL Pins Signal Description VCCSYN1 Drain Voltage Analog VDD dedicated to core analog PLL circuits To ensure core clock stability filter the power to the VCCSYN1 input with a circuit similar to the one in PLL Filtering Curcuit Figure To filter as much noise as possible place the circuit as close as possible to VCCSYN1 The 0 1 pF capacitor should be closest to VCCSYN1 followed by the 10 uF capacitor and finally the 10 0 resistor to Vdd These traces should be kept short and direct VCCSYN Drain Voltage Analog VDD dedicated to analog main PLL circuits To ensure internal clock stability filter the power to the VCCSYN input with a circuit similar to the one in PLL Filtering Curcuit Figure To filter as much noise as possible place the circuit should as close as possible to VCCSYN The 0 1 capacitor should be closest to VCCSYN followed by the 10 uF capacitor and finally the 10 Q resistor to Vdd These traces should be kept short and direct MOTOROLA Chapter 4 PLL and Clock Generator 4 5 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On T
134. ill interrupt the CP Note If EIE 1 DR1M must be reset No external interrupt occurs otherwise Note External CPM RISC interrupt must be connected to DREQ1 and DREQ4 13 SCD Scheduler configuration Configure as instructed in the download process of a Motorola supplied RAM microcode package 0 Normal operation 1 Alternate configuration of the scheduler according to bit 19 in the ERAM field If RCCR 19 0 the jump table starts at dual port RAM address 0x0000 If RCCR 19 1 the jump table starts at dual port RAM address 0x4000 16 19 ERAM Enable RAM microcode Configure this field as instructed during the downloading process of a Motorola supplied RAM microcode package Otherwise it should not be used 0000 Disable microcode program execution from the internal RAM 0100 Microcode is executed from the Instruction RAM Other combinations of these bits are not valid and must not be used 20 21 22 23 EDMx Edge detect mode DREQx asserts as follows 0 Low to high change 1 High to low change Note When DRxM is set to level mode 0 DRxM is active high 1 DRxM is active low 28 DEM12 Edge detect mode for DONE 1 2 for IDMA 1 2 See Section 18 7 2 DONEx in the MPC8260 PowerQUICC II User s Manual DONE 1 2 7 the MPC8260 PowerQUICC II User s Manual asserts as follows 0 High to low change 1 Low to high change 29 5 8 DEM34 Edge detect mode for DONE 3 4
135. is bit field is set by the USB controller to indicate the type of the packet This bit is valid only if the USB RXBDI F is set Written by the USB controller after the received data has been placed into the associated data buffer 00 Buffer contains DATAO packet 01 Buffer contains DATA1 packet 10 Buffer contains SETUP packet This option can never be set on host RxBD 10 Reserved should be cleared 11 NO Rx non octet aligned packet A packet that contained a number of bits not exactly divisible by eight was received Written by the USB controller after the received data has been placed into the associated data buffer 12 AB Frame aborted Bit stuff error occurred during reception Written by the USB controller after the received data has been placed into the associated data buffer 13 CR CRC error This frame contains a CRC error The received CRC bytes are always written to the receive buffer Written by the USB controller after the received data has been placed into the associated data buffer 14 OV Overrun A receiver overrun occurred during reception Written by the USB controller after the received data has been placed into the associated data buffer 15 Reserved should be cleared MOTOROLA Chapier 7 Universal Serial Bus Controller 7 25 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com l _ Freescale Semiconductor Inc USB Buffer Descriptor Ring Table 7
136. is controlled by FTIRRx GRPO 01The transmit internal rate for PHY address y is controlled by FTIRRx GRP1 10The transmit internal rate for PHY address y is controlled by FTIRRx GRP2 11The transmit internal rate for PHY address y is controlled by FTIRRx GRP3 30 31 Reserved should be cleared 8 6 5 FCC Transmit Internal Rate Register FTIRRx If GFEMR TIREM 0 PHYs at addresses 0 3 have their own FCC transmit internal rate registers FTIRRx PHYO FTIRRx PHY3 for use in transmit internal rate mode If TIREM 1 FTIRRx are used as group timers and PHYs at addresses 0 30 are assigned to a rate group by FIRSRx HI FIRSRx LO FTIRR shown in Figure 8 8 includes the initial value of the internal rate timer The clock to the internal rate timers is supplied by one of four baud rate generators selected in CMXUAR refer to Section 15 4 1 UTOPIA Address Register CMXUAR in the MPC8260 PowerQUICC II User s Manual Note that in slave mode FTIRRO is used regardless of the slave PHY address Field Reset R W Address TRM Initial Value 0000_0000 R W GFEMR TIREM 0 FCC1 0x1131C FTIRR1_PHY0 FCC1 FCC1 0x1131D FTIRR1 PHY1 FCC1 FCC1 0x1131E FTIRR1_PHY2 FCC1 0x1131F FTIRR1_PHY3 2 0x1133C FTIRR2 FCC2 FCC2 0x1133D FTIRR2 1 FCC2 FCC2 0x1133E FTIRR2 PHY2 FCC2 FCC2 0x1133F FTIRR2 PHY3 FCC2 GFEMR TIREM 1 0 1131
137. it enable for USB function controller For USB host controller should be cleared 0 No retransmission 1 Automatic frame retransmission is enabled The frame will be retransmitted if transmit error occurred time out Note May be set only if the transmit packet is contained in a single buffer If it is not retransmission should be handled by software intervention Note Should be set to zero for endpoint which is configured for ISO transfer mode MOTOROLA Chapter 7 Universal Serial Bus Controller 7 19 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com USB Host Description Bits Name Freescale Semiconductor Inc Table 7 11 USEPx Fields continued USB Function Mode Description USB Host Mode Description 12 13 5 Transmit hand shake for USB function controller Transmit hand shake for USB host controller 00 Normal handshake 00 Normal handshake 01 Ignore IN token 10 Force NACK handshake Not allowed for control end point 11 Force STALL handshake Not allowed for control end point 14 15 RHS Receive hand shake for USB function controller Receive hand shake for USB host controller 00 Normal handshake 00 Normal handshake 01 Ignore OUT token 10 Force NACK handshake Not allowed for control end point 11 Force STALL handshake Not allowed for control end point 7 5 7 4 USB Command Register USCOM US
138. l RAM modules MOTOROLA Chapter 5 Internal Multiported RAM DPRAM 5 1 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Internal Instruction RAM Slave address Slave data gt lt gt RISC Instruction address 2 RISC instruction RISC trace buffer address Trace buffer data T 32K bytes lE Internal Data RAM Slave address Slave data gt lt lt gt RISC data address RISC data 32K bytes fe DMA PPC address DMA PPC data gt lt DMA local address DMA local data gt lt BTM address BTM data gt lt gt Figure 5 1 Internal RAM Block Diagram The internal instruction RAM can be accessed by the following e CP instruction fetcher in case of microcode from RAM e PPC 60x slave The internal data RAM can be accessed by the following e CP load store machine e CP block transfer module BTM e PPC 60x slave e SDMA 60x bus e SDMA Local bus Figure 5 2 shows a memory map of the internal instruction RAM Note that the addresses refer to CPU address space 5 2 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Bank 1 CPM Instruction 2K Bank 2 CPM Instruction 2K Bank 3 CPM Instruction 2K Bank 4 CPM Instruction 2K
139. le Semiconductor Inc System Clock Control Register SCCR 4 4 System Clock Control Register SCCR The system clock control register SCCR shown in Figure 4 6 is memory mapped into the MPC8280 s internal space 0 22 23 24 25 28 29 30 81 Field PCI MODE PCI MODCK PCIDF CLPD DFBRG Reset 0 Refer to Table 4 3 0 01 R W R Addr 0x10C80 Figure 4 6 System Clock Control Register SCCR Table 4 3 SCCR Field Descriptions describes SCCR fields Table 4 3 SCCR Field Descriptions Defaults Bits Name Description POR Hard Reset 0 22 0 Unaffected Reserved 23 PCI MODE Mode Unaffected PCI Mode 0 Disabled 1 Enabled Reflects the inverted value of the PCI Mode pin 24 PCI MODCK PCI MODCK Unaffected Reflects the value of the PCI MODCK pin 25 28 PCIDF Config pins Unaffected division factor 29 CLPD 0 Unaffected CPM low power disable 0 Default CPM does not enter low power mode when the core enters low power mode 1 and SIU enter low power mode when the core does This may be useful for debug tools that use the assertion of QREQ as an indication of breakpoint in the core 30 31 DFBRG 01 Unaffected Division factor of BRGCLK Defines the BRGCLK frequency Changing the value does not result in a loss of lock condition The is divided from the CPM clock 00 Divide by 2 01 Divide by 8 normal operation 10 Divide
140. ll MPC8280 internal clocks by synchronously dividing MAIN_CLK These clocks are then output from the clock block to the entire MPC8280 4 1 4 Main PLL The main PLL performs frequency multiplication and skew elimination It allows the CPM to operate at a high internal clock frequency while using a low frequency clock input This has two immediate benefits MOTOROLA Chapter 4 PLL and Clock Generator 4 1 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com _ Freescale Semiconductor Inc MPC8280 Clock Block Diagram A lower clock input frequency reduces overall electromagnetic interference generated by the system e Oscillating at different frequencies eliminates the need for another oscillator 4 1 2 Core PLL The core PLL has the same advantages as the main PLL it performs frequency multiplication and skew elimination for the core blocks The core PLL input clock is synchronous with the 60x bus clock Its configuration word CORE_PLL_CFG 0 4 is determined by the MPC8280 clock configuration mode setting refer to CPU Multiplication Factor in Table 4 6 through Table 4 10 According to the setting the core PLL multiplies the internal bus clock and synchronously provides the core clocks 4 1 3 Skew Elimination The PLL can tighten synchronous timings by eliminating skew between phases of the internal clock and the external clock entering the chip CLKIN Skew eliminati
141. m MOTOROLA Freescale Semiconductor Inc Chapter 4 PLL and Clock Generator NOTE Reference Documentation This chapter replaces Chapter 9 Clocks and Power Control in the MPC8260 PowerQUICC User s Manual and Section 1 3 Clocking in the PCI Bridge Functional Specification Addendum 8260 PowerQUICC II User s Manual The MPC8280 s clocking architecture includes two PLLs the main PLL and the core PLL The main PLL together with the divisors provides the internal 60x bus clock and internal clocks for all blocks in the chip except core blocks The core PLL provides the internal core clocks The MPC8280 s clocking is a configurable system supporting three clock configuration modes The clock configuration mode is set during the power on reset Refer to Table 4 5 CLKIN is the primary timing reference for the MPC8280 The frequency of CLKIN equals 60x and local bus frequencies The main PLL multiplies the frequency of the input clock to the final CPM frequency Clock ratios for the various clock configuration modes are presented in Section 4 6 Clock Configuration Modes 41 8280 Clock Block Diagram The MPC8280 clocking system shown in Figure 4 1 is designed around two PLLs the main PLL and the core PLL The main PLL receives CLKIN as its input clock and multiplies it to provide MAIN_CLK which is twice the CPM clock to the clock block divisors The divisors shown in Figure 4 1 generate a
142. n This section replaces Section 13 5 2 Parameter RAM in the MPC8260 PowerQUICC II User s Manual Note the addition of USB The CPM maintains a section of RAM called the parameter RAM which contains many parameters for the operation of the FCCs SCCs SMCs SPI PC USB and IDMA channels An overview of the parameter RAM structure is shown in Table 5 1 The exact definition of the parameter RAM is contained in each protocol subsection describing a device that uses a parameter RAM For example the Ethernet parameter RAM is defined differently in some locations from the HDLC specific parameter RAM MOTOROLA Chapter 5 Internal Multiported RAM DPRAM 5 5 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Parameter RAM Freescale Semiconductor Inc Table 5 1 Parameter RAM N a AJ Ww o 9 9 9 9 OF 9 9 9 9 909 o ol ol ojl ojlo x xj x x x KT x KT x x KT x KT KT x x KT x KT KT x x x x x rir rl rl Sr Sr Se Se ojl ol NI NI NIN a gt 12 mimi mimi mio TIT So Ty TI S Ty o o 2 9 ey 9 Q ol lalrml olo l oOo mj a oC mm alo SO mia eo el ey ey ey ey ey oye 12 13 16 Page
143. n Assignment PPARA 1 continued Freescale Semiconductor Inc Pin Function Pin PSORA 0 PSORA 1 PDIRA 1 Output PA18 FCC1 TxD 7 UTOPIA 8 FCC1 TxD 15 UTOPIA 16 FCC1 TxD 0 MII HDLC nibble FCC1 TxD 0 RMII dibit FCC1 TxD HDLC transp PDIRA 0 Input Default Input PDIRA 1 Output PDIRA 0 Input or Inout if Specified Default Input PA17 FCC1 RxD 7 UTOPIA 8 FCC1 RxD 15 UTOPIA 16 FCC1 RxD 0 MII HDLC nibble FCC1 RxD 0 RMII dibit FCC1 RxD 0 HDLC transp PA16 FCC1 RxD 6 UTOPIA 8 RxD 14 UTOPIA 16 RxD 1 MII HDLC nibble RxD 1 RMII dibit PA15 FCC1 RxD 5 UTOPIA 8 FCC1 RxD 13 UTOPIA 16 RxD 2 MII HDLC nibble PA14 PA13 RxD 4 UTOPIA 8 RxD 12 UTOPIA 16 FCC1 RxD 3 MII HDLC nibble FCC1 RxD 3 UTOPIA 8 FCC1 RxD 11 UTOPIA 16 GND MSNUM 2 MOTOROLA Chapter 9 Parallel I O Ports PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com 9 3 Table 9 1 Port A Dedicated Pin Assignment PPARA 1 continued Freescale Semiconductor Inc Pin Function PSORA 0 PSORA 1 D Default PDIRA 0 Input or Default PDIRA 1 Output PDIRA 0 Input Input PDIRA 1 Output Inout if Specified I
144. nabled 1The TXB or TXE bit in the event register is set when this buffer is serviced TXB 4 L Last 0 Buffer does not contain the last byte of the message 1 Buffer contains the last byte of the message 7 28 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor In Buffer Descriptor Ring Table 7 17 USB Host Tx BD Fields continued Offset Bit Name Description 5 TC Transmit CRC Valid only when the L bit is set otherwise it is ignored Prepare TC before sending data 0 Transmit end of packet after the last data byte This setting can be used for testing purposes to send a bad CRC after the data 1 Transmit the CRC sequence after the last data byte 6 CNF Transmit confirmation Valid only when the L bit is set otherwise it is ignored Applies to multi frame enabled endpoints USEPn MF 1 see Section 7 5 7 3 USB End Point Registers USEP1 USEP4 0 Continue to load the transmit FIFO with the next packet No handshake or response is expected from the function for this packet 1 Wait for handshake or response from the function before starting the next packet or this is the last packet Do not clear CNF for a token preceding a data packet unless the data packet s BD is ready 7 LSP Low speed transaction Use for tokens only 0 The
145. niand a eec tnde te eiae 7 30 USB Controller BEEOES it eae Doi Mai tio ie bebe tS 7 30 USB Function Controller Initialization Example esee 7 31 Programming the USB Host Controller 2 7 33 USB Host Controller Initialization Example eene 7 34 Chapter 8 Fast Communication Controller FCC FCC Enhancements 1 Ae 8 1 General FCC Expansion Mode Register 2 4 4 021 8 1 Fast Ethernet Controller eee te ie eid osa et eade 8 2 FCC Ethernet Mode Register FSPMR 8 2 Connecting the MPC8280 to Ethernet eene 8 4 ATM Extended Number of PHY nm anina a 8 5 ATM Expanded Internal Rate usos cuero 8 5 Transmit External Rate and Internal Rate 2 242 22 8 5 ATM ROSISIBIS I ies aet tes 8 6 FCC Transmit Internal Rate Mode 5 eder etti 8 6 FCC Transmit Internal Rate Port Enable Register FIRPER 8 6 FCC Internal Rate Event Register 2 2 22 2 2 8 7 FCC Internal Rate Selection Registers FIRSR HI FIRSR LO 8 8 FCC Transmit Internal Rate Register FTIRRx eere 8 10 1 T
146. nput PA12 FCC1 RxD 2 MSNUN 3 UTOPIA 8 FCC1 RxD 10 UTOPIA 16 PA11 FCC1 RxD 1 MSNUMI 4J UTOPIA 8 FCC1 RxD 9 FCC1 UTOPIA 16 PA10 FCC1 RxD 0 MSNUM 5 UTOPIA 8 FCC1 RxD 8 UTOPIA 16 PA9 SMC2 SMTXD TDM A1 L1TXD 0 GND Output PA8 FCC2 TxAddr 4 SMC2 SMRXD TDM A1 L1RXD 0 GND primary option Input nibble TDM A1 L1RXD Inout serial PA7 FCC2 TxAddr 3 SMC2 SMSYN 1 L1TSYNC GND primary option GRANT PA6 FCC2 RxAddr 3 TDM A1 L1RSYNC GND PA5 SCC2 RSTRT FCC1 RxPrty FCC2 RxAddr 2 IDMA4 DREQ GND UTOPIA MPHY master secondary option PA4 FCC2 RxAddr 1 SCC2 REJECT IDMA4 DONE VDD MPHY master Inout 2 RxAddr 0 19 GND IDMA4 DACK TDM_A2 L1RXD 1 GND MPHY master Nibble PA2 FCC2 TxAddr 0 CLK20 GND IDMA3 DACK MPHY master PA1 FCC2 TxAddi 1 SCC1 REJECT VDD IDMA3 DONE VDD MPHY master Inout PAO SCC1 RSTRT FCC2 TxAddr 2 IDMA3 DREQ GND MPHY master 1 MSNUM 0 4 is the sub block code of the peripheral controller using SDMA MSNUM 5 indicates which section transmit or receive is active during the transfer See MPC8260 User s Manual Section 18 2 4 SDMA Transfer Error MSNUM Registers PDTEM and LDTEM 2 Available only when the primary option for this function is not used MPC8280 PowerQUICC II Specification PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com MOTOROLA Free
147. oding decoding with bit stuffing Supports both 12 and 1 5 Mbps data rates automatic generation of preamble token and data rate configuration Note that low speed operation requires an external hub e Flexible data buffers with multiple buffers per frame Supports local loopback mode for diagnostics 12 Mbps only T 3 Host Controller Limitations The following tasks are not supported by the hardware and must be implemented in software e CRCS5 generation for tokens Because 5 is calculated on 11 bits this task should not impose much software overhead e Retransmission after an error and error recovery Generation and transmission of an SOF start of frame token every 1 ms 7 2 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ae Host Controller Limitations Scheduling the various transfers within and between frames Because the MPC8280 USB host controller does not integrate the root hub an external hub is required when more than one device is connected to the host An external hub is also required for low speed operation Also note that the host controller programming model is similar to the function endpoint programming model but does not conform to the open host controller interface OHCI or universal host controller interface UHCI standards in which software drivers are h
148. oint 2 parameter RAM 30 Write 0 2010 2030 to 0 548 to set up the RBPTR and TBPTR fields of the endpoint 2 parameter RAM 31 Clear the TSTATE field of the endpoint 2 parameter RAM 32 Write 0x2018 2038 to DPRAM 0x560 to set up the RBASE and TBASE fields of the endpoint 3 parameter RAM 33 Write 0 1818 0100 to 0 564 to set up the RFCR TFCR and MRBLR fields of the endpoint 3 parameter RAM 34 Write 0 2018 2038 to 0 568 to set up the RBPTR and TBPTR fields of the endpoint 3 parameter RAM 7 32 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Programming the USB Host Controller 35 Clear the TSTATE field of the endpoint 3 parameter RAM 36 Write 0x0000 to USEPO for control transfer one packet only and manual handshake 37 Write 0x1200 to USEPI for bulk transfer one packet only and manual handshake 38 Write 0x2200 to USEP2 for bulk transfer one packet only and manual handshake 39 Write 0x3200 to USEP3 for bulk transfer one packet only and manual handshake 40 Write 0x00 to the USMOD for full speed 12 Mbps function endpoint mode and disable the USB 41 Write 0x05 to the USAD for slave address 5 42 Set USMOD EN to enable the USB controller 43 Write 0x80 to USCOM to start filling the Tx FIFO with endpoint 0 data ready for t
149. on is always active when the PLL is enabled Disabling the PLL PLL bypass can greatly increase clock skew 4 1 4 Divisors The PLL output clock MAIN_CLK is twice the CPM clock MAIN_CLK applies to general purpose dividers Each MPC8280 internal clock is generated by a dedicated divisor which is a programmable number between 1 and 16 Divisors are determined by the clock modes presented in Section 4 6 Clock Configuration Modes Note that all divisors output clocks will have identical skew in relation to the input clock because the delay through the divisors for all clocks is identical independent of how it s divisors have been programmed 4 1 5 Internal Clock Signals The internal logic of the MPC8280 generates the next internal clock lines general system clocks CPM_CLK e 60x bus and local bus BUS_CLK Identical to CLKIN SCC clocks e Baud rate generator clock e PCI clock PCI DLL clocks The PLL synchronizes these clock signals to each other 4 2 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 8280 Clock Block Diagram MAIN PLL for CPM Clocks VCO MAIN CLK CLKIN SCMR PLLMF CLKIN gt divider gt Main PLL MF SCMR PLLMF PLL gt SCMR CPMDF CPMDF 1 CEM C
150. other commands FCC3 10010 00110 Timer 01111 01010 SCC1 00100 00000 MCC1 11100 00111 5 2 00101 00001 2 11101 01000 SCC3 00110 00010 IDMA1 10100 00111 SCC4 00111 00011 IDMA2 10101 01000 SMC1 01000 00111 IDMA3 10110 01001 SMC2 01001 01000 IDMA4 10111 01010 RAND 01110 01010 USB 10011 01011 11 14 Reserved should be cleared 15 FLG Command semaphore flag Set by the core and cleared by the CP 0 The CP is ready to receive a new command 1 The CPCR contains a command that the CP is currently processing The CP clears this bit at the end of command execution or after reset 16 17 EP Endpoint Logical pipe number only in USB 00 ENDPOINT 0 01 ENDPOINT 1 10 ENDPOINT 2 11 ENDPOINT 3 18 25 MCC channel number Specifies the channel number the case of an MCC command In FCC protocols this field contains the protocol code as follows 0x00 HDLC ATM OxOC Ethernet OxOF Transparent 5 10 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Command Set Table 5 3 CP Command Register Field Descriptions continued Bit Name Description 26 27 Reserved should be cleared 28 31 OPCODE Operation code Settings are listed in Table 5 4 5 3 1 1 Commands The CP command opcodes are shown in Table 5 4 Table 5 4 CP Command Opcodes
151. pending transactions prior to the 1 ms tick TOUT1 or BRGO1 TIMER1 or BRG1 DREQ1 PORT DREQn n 2 3 4 Figure 7 6 External Request Configuration Due to system limitations two external requests should be connected to the output of BRG CPM timer DREQI is configured as external interrupt and the other DREQn are configured as an external request When there are no hardware originated requests to the CP it enters the stall state Only hardware requests can wake it up this is guaranteed by the connectivity to the DREQ configured as an external request 7 12 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc T USB Host Description 7 5 3 USB Function and Host Parameter RAM Memory Map The USB controller parameter RAM area shown in Table 7 4 begins at the USB base address Ox8BOO offset from RAM Base Note that the user must initialize certain parameter RAM values before the USB controller is enabled Table 7 4 USB Parameter RAM Memory Map Address Name Width Description USB Base 00 EPOPTR Half Word Endpoint pointer registers 0 3 The endpoint parameter block pointers are index pointers to each endpoint s parameter block Parameter blocks can USB Base 02 EPIPTR Half Word allocated to any address divisible by 32 in the dual port RAM Se
152. r Inc Table 9 4 Port D Dedicated Pin Assignment PPARD 1 continued Pin Function PSORD 0 PSORD 1 Pin _ Default _ PDIRD 0 Input or Default PDIRD 1 Output PDIRD 0 Input Input PDIRD 1 Output Inout if Specified Input SCC1 RTS FCC1 RxAddr 3 FCC1 RxAddr 3 2 SCC1 TENA MPHY master MPHY slave Ethernet multiplexed polling multiplexed polling FCC2 RxAddr 4 FCC1 RxClav2 2 MPHY master MPHY master direct multiplexed polling polling FCC2 RxAddr 1 MPHY slave multiplexed polling PD28 FCC1 TxD 7 SCC2 RXD GND C1 L1TXD GND UTOPIA 16 bit secondary option Inout secondary option PD27 SCC2 TXD FCC1 RxD 7 C1 L1RXD UTOPIA 16 Inout secondary option PD26 SCC2 RTS FCC1 RxD 6 C1 LIRSYNC SCC2 TENA UTOPIA 16 secondary option Ethernet PD25 FCC1 TxD 6 SCC3 RXD D1 L1TXD UTOPIA 16 secondary option Inout secondary option PD24 SCC3 TXD FCC1 RxD 5 D1 L1RXD UTOPIA 16 Inout secondary option PD23 SCC3 RTS FCC1 RxD 4 D1 L1RSYNC SCC3 TENA UTOPIA 16 secondary option Ethernet PD22 FCC1 TxD 5 SCC4 RXD GND A2 L1TXD 0 A2 L1TXD UTOPIA 16 USB Rxd Output nibble Inout serial secondary option secondary option PD21 SCC4 TXD FCC1 RxD 3 A2 L1RXD USB TN UTOPIA 16 Inout serial
153. r 5 CPM Clock MHz low high CPU Multiplication Factor 6 CPU Clock MHz low high PCI Division Factor PCI Clock MHz 1001_011 3 5 218 8 266 6 250 0 304 7 1001_ 100 3 5 200 0 266 6 257 1 342 8 1001 101 1001 110 1001 111 1010 000 1010 001 1010 010 1010 011 1010 100 1011 000 Reserved 1011_001 2 5 1011_010 1011_011 3 1011_100 1011_101 1101_000 1101_001 1101_010 1101_011 1101 100 1101 101 1101 110 1110 000 100 0 133 3 3 300 0 400 0 3 5 350 0 466 6 6 50 0 66 7 1110 001 100 0 133 3 3 300 0 400 0 4 400 0 533 3 6 50 0 66 7 1110 010 100 0 133 3 3 300 0 400 0 4 5 450 0 599 9 6 50 0 66 7 1110 011 100 0 133 3 3 300 0 400 0 5 500 0 666 6 6 50 0 66 7 MOTOROLA Chapter 4 PLL and Clock Generator 4 17 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Clock Configuration Modes Table 4 7 Clock Configurations for PCI Host Mode PCI MODCK O0 1 continued MODCK H MODCK 1 3 Bus Clock 4 MHz CPM Multiplication Factor gt CPM Clock MHz low high CPU Multiplication Factor 6 CPU Clock MHz low high PCI
154. r More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 9 2 Port B Dedicated Pin Assignment PPARB 1 continued Pin Function PSORB 0 PSORB 1 Pin _ Default _ PDIRB 0 Input or Default PDIRB 1 Output PDIRB 0 Input Input PDIRB 1 Output Inout if Specified Input PB21 FCC2 RxD 7 GND TDM A1 L1TXD 2 TDM D2 GND UTOPIA 8 Nibble L1TSYNC GRANT FCC2 RxD 0 MII HDLC nibble FCC2 RxD 0 RMII dibit FCC2 RxD HDLC transp serial PB20 FCC2 RxD 6 GND A1 L1TXD 1 TDM D2 L1RSYNC GND UTOPIA 8 Nibble FCC2 RxD 1 MII HDLC nibble FCC2 RxD 1 RMII dibit PB19 FCC2 RxD 5 GND TDM D2 L1RQ A2 L1RXD 3 GND UTOPIA 8 Nibble FCC2 RxD 2 MII HDLC nibble PB18 FCC2 RxD 4 GND TDM D2 L1CLKO TDM A2 L1RXD 2 GND UTOPIA 8 Nibble FCC2 RxD 3 MII HDLC nibble TDM A1 L1RQ FCC3 RX DV GND CLK17 GND MII FCC3 CRS DV RMII 16 1 L1CLKO GND CLK18 GND MII RMII PB15 FCC3 TX ER SCC2 RXD by TDM C1 L1TXD by MII primary option PD28 Inout PD28 primary option PB14 FCC3 TX EN SCC3 RXD by TDM C1 L1RXD by MII RMII primary option PD25 Inout PD27 primary option PB13 TDM B1 L1RQ FCC3 COL GND TDM A2 L1TXD 1 C1 by MII Nibble L1TSYNC GRANT PD16 primary option PB12 TDM B1 L1CLKO FCC3 CRS GND SCC2 TXD TDM C1 L1RSYNC by MII primary option PD2
155. ransmission when an IN token is received 44 Write 0x81 to USCOM to start filling the Tx FIFO with endpoint 1 data ready for transmission when an IN token is received 45 Write 0x82 to USCOM to start filling the Tx FIFO with endpoint 2 data ready for transmission when an IN token is received 46 Write 0x83 to USCOM to start filling the Tx FIFO with endpoint 3 data ready for transmission when an IN token is received 7 10 Programming the USB Host Controller The MPC8280 implementation of a USB host uses endpoint 0 to control the host transmission and reception The other endpoints are typically not used unless for testing purposes loop back Programming the USB controller to act as host is similar to configuring an endpoint for function operation A general outline of how to program the host controller follows A more detailed example can be found in Section 7 10 1 USB Host Controller Initialization Example e Set the host bit in the mode register USBMOD HOST 1 to configure the controller as a host e Set the multi frame bit in the endpoint 0 configuration register USEPO MF 1 to allow SETUP OUT tokens packets to be sent back to back Prepare tokens in separate BDs Using software append the 5 as part of the transmitted data because the CPM does not support automatic CRC5 generation Clock the USB host controller as a high speed function 48 MHz reference clock
156. ransmit Internal Rate Port Enable Register 8 7 FCC Internal Rate Event Register FIRER eene 8 8 FCC Internal Rate Selection Register HI FIRSRx 4 2 22 2 8 9 FCC Internal Rate Selection Register LO FIRSRx LO eere 8 9 FCC Transmit Internal Rate Register 8 10 FCC Transmit Internal Rate Clocking eae eoe ee 8 11 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Chapter 1 Overview This document supports 13um HiP7 devices in the PowerQUICC family of integrated communications processors and supplements the MPC8260 PowerQUICC User s Manual Reference Documentation notes indicate whether the information in this document supplements or replaces information presented in the manual The MPC8280 and MPC8270 collectively referred to throughout this document as the MPC8280 are pin compatible with previous PowerQUICC devices the 29um HiP3 MPC8260 and the 25um HiP4 MPC826xA and include a number of enhancements that do not affect software drivers written for previous PowerQUICC II devices The MPC8280 s primary enhancements include the 64 Kbyte internal multiport RAM DPRAM and increased clock frequencies The 13um Hi
157. red for the fast Ethernet connection between the MPC8280 and a PHY The MDC MDIO management interface is the same as in MII The RMII reference clock REF_CLK is distributed over the FCC transmit clock In RMII mode receive clock is not used RMII Transmit di bit Data TXD 1 0 x Transmit Enable TX EN Reference Clock REF CLK ag MPC8280 Receive di bit Data RXD 1 0 Fast Ethernet Receive Error RX ER RMII PHY mM Receive CRS DV CRS DV Management Data Clock MDC Management Data I O MDIO 1 management signals MDC and MDIO can be common to all of the fast Ethernet connec tions in the system assuming that each PHY has a different management address Use parallel I O port pins to implement MDC and MDIO The 2 controller cannot be used for this function Figure 8 3 Connecting the MPC8280 to Ethernet RMII 8 4 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc ATM Extended Number of PHYs 8 4 ATM Extended Number of PHYs NOTE This section applies to the MPC8280 only The MPC8270 does not support ATM NOTE Reference Documentation This section is an addition to Chapter 29 ATM Controller in the MPC8260 PowerQUICC II User s Manual The MPC8280 has additional pin muxing to support 31 PHYs on bot
158. rwarded to the requesting unit HID2 register enables instruction and data cache way locking Optional data cache operation broadcast feature Allows for correct system management using an external copy back L2 cache Enabled by HIDO ABE Cache control instructions HIDO A BE must be enabled to execute all cache control instructions icbi dcbi dcbf and dcbst excluding dcbz Exceptions Hardware support for misaligned little endian LE accesses LE load store accesses that are not on a word boundary with the exception of strings and multiples generate exceptions under the same circumstances as big endian BE accesses Graphics instructions cause an alignment exception if the access is not on a word boundary The G2 core does not have misalignment support for eciwx and ecowx Critical interrupt exception that has higher priority than the system management interrupt e Busclock New bus multipliers are selected by the encodings of core pll cfg 0 4 Instruction timing Integer divide instructions divwu o and divw o execute in 20 clock cycles Execution in the original MPC603e PID6 603e takes 37 clock cycles Support for single cycle store Adder comparator added to system register unit Allows dispatch and execution of multiple integer add and compare instructions on each cycle Enhanced debug features Addition of three breakpoint registers IABR2 DABR and DABR2
159. s Functions Signal 1 0 Function USBTXN O Outputs from the USB transmitter inputs to the differential driver USBTXP XU ee TP Result 0 0 single ended 0 0 1 logic 0 1 0 logic 1 1 1 USBOE Output enable Enables the transceiver to send data on the bus USBRXD Receive data Input to the USB receiver from the differential line receiver USBRXP Gated version of D D Used to detect single ended zeros and the interconnect speed USBRXN RP RN Result 0 0 single ended 0 1 0 full speed 0 1 low speed 1 1 7 4 USB Function Description As shown in Figure 7 2 the USB function consists of transmitter and receiver sections and a control unit The USB transmitter contains four independent FIFOs each containing 16 bytes There is a dedicated FIFO for each of the four supported end points The USB receiver has a single 16 byte FIFO 7 4 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc uu USB Function Description Peripheral bus U bus Port control Tx data FIFO Mode register Command register 16 byte Rx F
160. s filled with packet the host transaction starts Figure 7 3 and Table 7 2 describe the behavior of MOTOROLA Chapter 7 Universal Serial Bus Controller 7 9 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc USB Host Description the USB host controller for each token Tokens are not checked for validity and transmitted as is The user is responsible for token validity as well as 5 generation Low speed transactions start with a preamble which is generated by the USB host controller state machine when LSP bit in token TxBD is set The signalling on the USB lines is controlled by USMODILSS Low Speed PREAMBLE transmit receive Figure 7 5 USB Controller Operating Modes The SOF transaction is initiated and generated using a CPM timer and a microcode routine Once the SOF token is loaded to host FIFO it is transmitted refer to Section 7 5 2 SOF Transmission for USB Host Controller When USMOD TEST is programmed both the host state machine and function state machine are active End points 2 4 receive transmit data according to tokens received from host The programming model and functional description are described in Section 7 5 7 USB Function Programming Model 7 10 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On
161. scale Semiconductor Inc Table 9 2 shows the port B pin assignments Table 9 2 Port B Dedicated Pin Assignment PPARB 1 Pin Function PSORB 0 PSORB 1 Pin B Default PDIRB 0 Input or Default PDIRB 1 Output PDIRB 0 Input Input PDIRB 1 Output Inout if Specified Input 1 2 ER 2 RxSOC GND TDM B2 L1TXD GND MII UTOPIA Inout PB30 FCC2 TxSOC FCC2 RX_DV GND TDM_B2 L1RXD GND UTOPIA MII Inout FCC2 CRS_DV RMII PB29 FCC2 RxClav FCC2 RxClav GND 2 TDM_B2 L1RSYNC GND UTOPIA slave UTOPIA master MII RMII PB28 FCC2 RTS FCC2 RX ER GND SCC1 TXD TDM B2 GND MII RMII L1TSYNC GRANT PB27 FCC2 TxD 0 FCC2 COL GND TDM C2 L1TXD GND UTOPIA 8 MII Inout PB26 FCC2 TxD 1 FCC2 CRS GND C2 L1RXD GND UTOPIA 8 MII Inout PB25 FCC2 TxD 4 A1 L1TXD 3 TDM C2 GND UTOPIA 8 Nibble L1TSYNC GRANT FCC2 TxD 3 MII HDLC nibble PB24 FCC2 TxD 5 A1 L1RXD 3 GND TDM C2 L1RSYNC GND UTOPIA 8 Nibble FCC2 TxD 2 MII HDLC nibble PB23 FCC2 TxD 6 TDM A1 L1RXD 2 GND TDM D2 L1TXD GND UTOPIA Nibble Inout FCC2 TxD 1 MII HDLC nibble FCC2 TxD 1 RMII dibit PB22 FCC2 TxD 7 TDM A1 L1RXD 1 GND TDM D2 L1RXD GND UTOPIA Nibble Inout FCC2 TxD 0 MII HDLC nibble FCC2 TxD 0 RMII dibit FCC2 TxD HDLC transp serial MOTOROLA Chapter 9 Parallel I O Ports 9 5 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE Fo
162. segments MOTOROLA Chapier 7 Universal Serial Bus Controller 7 1 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com _ Freescale Semiconductor Inc Host Controller Limitations The USB full speed signalling bit rate is 12 Mbps Also a limited capability low speed signalling mode is defined at 1 5 Mbps Refer to the USB Specification Revision 1 1 for further details It can be downloaded from http www usb org The MPC8280 USB controller consists of a transmitter module receiver module and two protocol state machines The protocol state machines control the receiver and transmitter modules One state machine implements the function state diagram and the other implements the host state diagram The USB controller can implement a USB function endpoint a USB host or both for testing purposes loop back diagnostics 7 21 USB Controller Features The USB function mode features are as follows Four independent endpoints support control bulk interrupt and isochronous data transfers e CRCIO6 generation and checking CRC5 checking e NRZI encoding decoding with bit stuffing e 2 or 1 5 Mbps data rate e Flexible data buffers with multiple buffers per frame e Automatic retransmission upon transmit error The USB host controller features are as follows Supports control bulk interrupt and isochronous data transfers e CRCIO6 generation and checking e NRZI enc
163. shown in Table 7 18 Errors which exist exclusively in host mode or function mode are marked as such Table 7 18 USB Controller Transmission Errors Error Description Transmit If an underrun occurs the transmitter forces a bit stuffing violation terminates buffer transmission Underrun closes the buffer sets TxBD UN and the corresponding USBER TXEn The endpoint resumes transmission after the RESTART TX ENDPOINT command is received Transmit Transmit packet not acknowledged If a timeout occurs the controller tries to retransmit if Timeout USEPn RTE 1 If RTE 0 or the second attempt fails the controller closes the buffer and sets TxBD TO and USBER TXEn The endpoint resumes transmission after receiving a RESTART TX ENDPOINT command Tx Data For USB function mode only Not Ready This error occurs if an IN token is received but the corresponding endpoint s transmit FIFO is empty or if the target endpoint is configured to NAK or STALL The controller sets USBER TXEn Reception For USB host mode only of or If this error occurs the channel closes the buffer sets the corresponding status bit in the Tx BD STALL or STAL and sets the TXE bit in the USB event register The host will resume transmission after hand reception of the RESTART TRANSMIT command shake Table 7 19 describes the USB controller reception errors 7 30 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY
164. t polling FCC2 RxAddr 2 MPHY slave multiplexed polling PC5 FCC2 TxClav FCC2 TxClav SI2 L1ST3 FCC2 CTS GND UTOPIA slave UTOPIA master Strobe PC4 FCC2 RxEnb FCC2 RxEnb 612 L1ST4 FCC2 CD GND UTOPIA master UTOPIA slave Strobe PC3 FCC2 TxD 2 FCC3 CTS IDMA2 DACK 5 4 CTS GND UTOPIA 8 secondary option PC2 FCC2 TxD 3 FCC3 CD IDMA2 DONE Vpp UTOPIA 8 Inout PC1 BRG6 BRGO IDMA2 DREQ TDM A2 L1RQ SPI SPISEL Vpp secondary option PCO BRG7 BRGO IDMA1 DREQ A2 L1TCLKO SMC2 SMSYN GND secondary option Available only when the primary option for this function is not used MPHY Address pins 3 4 master mode can come from FCC2 depending on CMXUAR programming See MPC8260 PowerQUICC II User s Manual Section 15 4 1 CMX UTOPIA Address Register CMXUAR Table 9 4 shows the port D pin assignments Table 9 4 Port D Dedicated Pin Assignment PPARD 1 Pin Function i PSORD 0 PSORD 1 Pin Default PDIRD 0 Input or Default PDIRD 1 Output PDIRD 0 Input input PDIRD 1 Output hout if Specified Input PD31 SCC1 RXD GND PD30 FCC2 TxEnb FCC2 TxEnb GND SCC1 TXD UTOPIA master UTOPIA slave 9 10 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconducto
165. t 0 No interrupt is generated after this buffer has been serviced 1The TXB or TXE bit in the event register is set when this buffer is serviced TXB and TXE can cause interrupts if they are enabled 8 9 TC CNF PID Last 0 Buffer does not contain the last byte of the message 1 Buffer contains the last byte of the message Transmit CRC Valid only when the L bit is set otherwise it is ignored Prepare TC before sending data 0 Transmit end of packet after the last data byte This setting can be used for testing purposes to send a bad CRC after the data 1 Transmit the CRC sequence after the last data byte Transmit confirmation Valid only when the L bit is set otherwise it is ignored Applies to multi frame enabled endpoints USEPn MF 1 refer to Section 7 5 7 3 USB End Point Registers USEP1 USEP4 0 Continue to load the transmit FIFO with the next packet Several packets may be loaded to the FIFO 1 Last packet that is loaded to FIFO No more packets will be loaded to fifo after a packet marked CNF till it transmitted Reserved should be cleared Packet ID This bit field is valid for the first BD of a packet otherwise it is ignored 0X Do not append PID to the data 10 Transmit DATAO PID before sending the data 11 Transmit DATA1 PID before sending the data 10 12 Reserved should be cleared 13 TO Time out Indicates that the host failed to acknowledge the packet 14 UN
166. t in the YCC1 position SCC3 asserts its request in the YCC1 position SCCA asserts its request in the YCC1 position TC layer assert interrupt to YCC1 position Other combinations YCC1 position is not active 3 11 YC2P YC8P Same as YC1P but for YOC2 YCC8 12 15 Reserved should be cleared 6 4 SIU Interrupt Pending Register SIPNR L NOTE Reference Documentation This section replaces the description of SIPNR L in Section 4 3 1 4 SIU Interrupt Pending Registers of the MPC8260 PowerQUICC User s Manual Note the addition of SIPNR L TC Figure 6 2 shows SIPNR L fields 1 2 3 4 5 8 9 10 Field FCC1 FCC2 FCC3 MCC1 MCC2 SCC1 SCC2 SCC3 SCC4 TC Reset 0000 0000 0000 0000 R W R W Addr 0x10C0C 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Field 12C SPI SMC1 SMC2 IDMA1 IDMA2 IDMA3 IDMA4 SDMA USB 1 2 4 Reset 0000_0000_0000_000 0 R W R W Addr Ox10COE These fields are zero after reset because their corresponding mask register bits SCCM are cleared disabled MOTOROLA Figure 6 2 SIU Interrupt Pending Register SIPNR L Chapter 6 System Interface Unit PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com 6 3
167. the receiver is disabled or when no receive buffer is being used TxBD pointer Points to the next BD that the transmitter will transfer data from when it is in an idle state or to the current BD during frame transmission TBPTR should be initialized by the software after reset When the end of BD table is reached the CP initializes this pointer to the value programmed in the TBASEn entry Although the user never needs to write TBPTR in most applications except initialization it can be changed when the transmitter is disabled or when no transmit buffer is being used Transmit internal state Reserved for CP use only Should be cleared before enabling the USB controller 0x10 32 bits Transmit internal data pointer Updated by the SDMA channels to show the next address in the buffer to be accessed 0x14 TCRC3 16 bits Transmit temp CRC Reserved for CP use only 7 14 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc pe USB Host Description Table 7 5 Endpoint Parameter Block continued Offset Name Width Description 0x16 TBCNT 16 bits Transmit internal byte count A down count value that is initialized with the TxBD data length and decremented with every byte read by the SDMA channels 0x18 TTEMP 32bits Tx temp
168. tion registers from the EEPROM during reset O CP auto load is disabled 1 CP auto load is enabled 27 Reserved should be cleared 28 31 MODCK H High order bits of the MODCK bus which determine the clock reset configuration If the device is configured to PCI mode PCI MODE is driven low this field has no effect and the value for MODCK_H is loaded directly from the MODCK H pins Note The value of the MODCK bits are derived from the dedicated PCI MODCK H 0 3 pins when operating in PCI mode This bit cannot be changed after reset 4 3 1 2 External Filter Capacitor XFC The XFC pin that is used in the MPC826x A is not used in the MPC8280 There is no need for external capacitor to operate the PLL New designs should connect AB2 XFC pin to GND Old designs when the MPC8280 is used as a drop in replacement can leave the pin connected to the current capacitor 4 3 1 3 GNDSYN GNDSYN exists on the MPC826x A but does not exist as a separate ground signal in the MPC8280 New designs must connect pin to GND and follow layout practices suggested in the MPC6280 Hardware Specifications Old designs when the MPC8280 is used as a drop in replacement can leave the pin connected to GND with the noise filtering capacitors 4 8 MPC8280 PowerQUICC II Specification MOTOROLA PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freesca
169. ultiported RAM DPRAM 5 7 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc RISC Controller Configuration Register Table 5 2 RISC Controller Configuration Register Field Descriptions continued Bits Name Description 8 9 24 25 DRxM IDMAx request mode Controls the IDMA request x DREQx sensitivity mode DREQx is used to activate IDMA channel x See Section 18 7 IDMA Interface Signals 0 DREQx is edge sensitive according to EDMx 1 DREQxis level sensitive Note When DRxM is set to level mode EDMx determines if IDMA request is active high or active low Refer to description of RCCR 20 24 Note If RCCR EIE 1 RCCR DR1M must be reset No external interrupt occurs otherwise 10 11 14 15 26 27 30 31 DRxQP IDMAx request priority Controls the priority of DREQx relative to the communications controllers See Section 18 7 IDMA Interface Signals 00 DREQx has more priority than the communications controllers default 01 DREQx has less priority than the communications controllers option 2 10 DREQx has the lowest priority option 3 11 Reserved 12 EIE External interrupt enable When EIE is set DREQ acts as an external interrupt to the CP Configure as instructed in the download process of a Motorola supplied RAM microcode package 0 DREQ1 cannot interrupt the CP 1 DREG w
170. unit capable of fetching two instructions per clock from the instruction cache Six entry instruction queue IQ that provides lookahead capability Independent pipelines with feed forwarding that reduces data dependencies in hardware MOTOROLA Chapter 2 Embedded MPC603e Core 2 1 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc 16 Kbyte data cache and 16 Kbyte instruction cache Four way set associative Physically addressed LRU replacement algorithm Cache write back or write through operation programmable on a per page or per block basis BPU that performs CR lookahead operations Address translation facilities for 4 Kbyte page size variable block size and 256 Mbyte segment size 64 entry two way set associative ITLB and DTLB Eight entry data and instruction BAT arrays providing 128 Kbyte to 256 Mbyte blocks Software table search operations and updates supported through fast trap mechanism 52 bit virtual address 32 bit physical address Facilities for enhanced system performance 32 or 64 bit split transaction data bus interface 60x bus with burst transfers Support for one level address pipelining and out of order bus transactions on the 60x interface Hardware support for misaligned little endian accesses Integrated power management Internal processor bus
171. ve MII RMII PA27 FCC1 RxSOC GND FCC1 RX DV GND UTOPIA MII FCC1 CRS DV RMII MOTOROLA Chapter 9 Parallel I O Ports 9 1 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc Table 9 1 Port A Dedicated Pin Assignment PPARA 1 continued Pin Function Pin PA26 PSORA 0 PSORA 1 PDIRA 1 Output FCC1 RxClav UTOPIA slave PDIRA 0 Input FCC1 RxClav UTOPIA master FCC1 RxClavO MPHY master direct polling PDIRA 1 Output PDIRA 0 Input or Inout if Specified FCC1 RX_ER MII RMII Default Input GND PA25 FCC1 TxD 0 UTOPIA 8 FCC1 TxD 8 UTOPIA 16 MSNUM O PA24 FCC1 TxD 1 UTOPIA 8 FCC1 TxD 9 UTOPIA 16 MSNUM 1 PA23 FCC1 TxD 2 UTOPIA 8 FCC1 TxD 10 UTOPIA 16 PA22 FCC1 TxD 3 UTOPIA 8 FCC1 TxD 11 UTOPIA 16 PA21 FCC1 TxD 4 UTOPIA 8 FCC1 TxD 12 UTOPIA 16 FCC1 TxD 3 MII HDLC nibble PA20 FCC1 TxD 5 UTOPIA 8 FCC1 TxD 13 UTOPIA 16 FCC1 TxD 2 MII HDLC nibble PA19 FCC1 TxD 6 UTOPIA 8 TxD 14 UTOPIA 16 FCC1 TxD 1 MII HDLC nibble FCC1 TxD 1 RMII dibit 9 2 MPC8280 PowerQUICC II Specification PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com MOTOROLA Table 9 1 Port A Dedicated Pi
172. wait after a collision is stopped whenever carrier sense is active In this method the retransmission is less aggressive than the maximum allowed in the IEEE 802 3 standard The persistence P PER feature in the parameter RAM can be used in combination with the SBT bit or in place of the SBT bit 3 LPB Loopback operation 0 Normal operation receiver does not receive when transmitter sends 1 The channel is configured for internal or external loopback operation as determined by GFMR DIAG For external loopback configure DIAG for normal operation for internal loopback configure DIAG for loopback operation 4 LCW Late collision window 0 A late collision is any collision that occurs at least 64 bytes from the preamble 1 A late collision is any collision that occurs at least 56 bytes from the preamble 5 FDE Full duplex Ethernet 0 Disable full duplex 1 Enable full duplex Must be set if FSMR LPB is set or external loopback is performed 6 MON RMON mode 0 Disable RMON mode 1 Enable RMON mode 7 8 Reserved should be zero 9 PRO Promiscuous 0 Check the destination address of incoming frames 1 Receive the frame regardless of its address A CAM can be used for address filtering when FSMR CAM is set 10 FCE Flow control enable O Flow control is not enabled 1 Flow control is enabled 11 RSH Receive short frames 0 Discard short frames frames smaller than the value specified in MINFLR 1 Receive short
173. y the USB controller after it finishes sending the associated data buffer Data length the second half word of a TxBD is the number of octets the CP should send from this BD s data buffer It is never modified by the CP Tx buffer pointer the third and fourth half words of a TxBD always points to the first location of the buffer in internal or external memory The pointer may be even or odd MOTOROLA Chapier 7 Universal Serial Bus Controller 7 29 PRELIMINARY SUBJECT TO CHANGE WITHOUT NOTICE For More Information On This Product Go to www freescale com Freescale Semiconductor Inc USB CP Commands 7 7 USB CP Commands The following transmit commands are issued to the CP command register CPCR Refer to Section 5 3 1 CP Command Register CPCR 7 7 1 STOP Tx Command This command disables the transmission of data on the selected endpoint After issuing the command the corresponding End Point FIFO should be flushed No further transmissions will take place until the Restart Tx Command is issued 7 7 2 RESTART Tx Command This command enables the transmission of data from the corresponding endpoint on the USB This command is expected by the USB controller after a STOP Tx Command or after transmission error underrun or time out 7 8 USB Controller Errors The USB controller reports frame reception and transmission error conditions using the BDs and the USB event register USBER Transmission errors are

MPC8280 PowerQUICC II™ Specification

Contents

Download Pdf Manuals

Related Search

Related Contents

MPC8280 PowerQUICC II&trade; Specification

Contents

Download Pdf Manuals

Related Search

Related Contents

MPC8280 PowerQUICC II™ Specification