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1. Mnemonic Byte Operation data3 0000h data3 00h data3 data4 0000h data4 OOh data4 data16 data16 data16 OFFh data8 0000h data8 data8 mask OO00h mask mask Immediate constants are always signified by a leading number sign 6 2 5 Branch Target Addressing Modes Different addressing modes are provided to specify the target address and segment of jump or call instructions Relative absolute and indirect modes can be used to update the Instruction Pointer IP register while the Code Segment Pointer CSP register can be updated only with an absolute value A special mode is provided to address the interrupt and trap jump vector table which is allocated to the lowest portion of code segment 0 Table 6 5 Branch Target Addressing Modes Target Address Target Segment Mnemonic Valid Address Range IP caddr caddr O FFFEh IP 2 IP 2 el rel QOh 7Fh IP IP 2 Crel 1 rel 80h FFh Rw IP CP 2Rw Rw 0 15 seg CSP seg seg 0 3 trap7 IP 0000h 4 trap7 CSP 0000h trap7 0 7Fh Siemens Aktiengesellschaft 6 9 Instruction Set Overview In the following the branch target addressing modes are described in more detail caddr Specifies an absolute 16 bit code address within the current segment Bran ches MAY NOT be taken to odd code addresses Therefore the least signifi cant bit of caddr must always contain a 0
2. 0000 ee eue D 4 Selection of Bus Modes and ROM Mapping D 5 Change of the READY Function 0 000 e eee eee D 8 Implementation of an additional Bus Configuration Register D 9 Switching between the Bus Modes 0 0c eee eens D 11 Implementation of ALE Lengthening 2000 ee eee D 11 Automatic Continuation of Reset Sequence 04 D 12 Implementation of HOLD HLDA BREO Bus Arbitration D 12 Top Tech Semiconductors Worldwide Siemens Aktiengesellschaft 5 Introduction 1 Introduction The rapidly growing area of embedded control applications is representing one of the most time critical operating environments for today s microcontrollers Complex control aigorithms must be processed based on a large number of digital as well as analog input signals and the appropriate output signals must be generated within a defined minimum response time Embedded control applications are often confronted with restrictions con cerning board space power consumption and overall system cost Therefore embedded control applications require microcontrollers which provide a high level of system integra tion to eliminate the need for additionai peripheral devices and the associated software overhead High system security and fail safe mechanisms are also a fundamental neces sity in embedded control systems With the incre
3. 8 3 A D Converter ADC 0 cc eee ees 8 3 1 Conversion Modes and Operation 8 3 1 1 Single Channel Converion Mode 8 3 1 2 Single Channel Continuous Conversion 8 3 1 3 Auto Scan Conversion Mode 8 3 1 4 Auto Scan Continuous Conversion l l 8 3 2 A D Converter interrupt Control llle 8 4 Serial Channels 0 cee eee eee eee 8 4 1 Modes of Operation 0 ccc cee eee ees 8 4 1 1 Asynchronous Operation llle 8 4 1 1 1 8 Bit Data Mode ce ee eee ee 8 4 1 1 2 7 Bit Data Parity Bit Mode 8 4 1 1 3 9 Bit Data Mode llle E 8 4 1 1 4 8 Bit Data Wake Up Bit Mode 8 4 1 1 5 8 Bit Data Parity Bit Mode 8 4 1 2 Synchronous Operation lllllln 8 4 1 2 1 Synchronous Data Transmission 8 4 1 2 2 Synchronous Data Reception lsuu 8 4 1 3 Loop Back Mode suede IAIR PAROS Rp 8 4 2 Baud Hdles cc ect yx e E ox dese eee eee Sees Ss 8 4 2 1 Asynchronous Mode Baud Rates 8 4 2 2 Synchronous Mode Baud Rates 406 8 4 3 Serial Channels Interrupt Control 05 8 5 Watchdog Timer WDT 9 External Bus Interface 9 1 External Bus Configuration During Reset 9 2 Single Chip Mo
4. 16 bit 18 bit Addresses 16 bit Data Multiplexed 16 bit 18 bit Addresses 8 bit Data Multiplexed In the non multiplexed bus mode Port 1 is used as an output for addresses and Port 0 is used as an input output for data In the multiplexed bus modes just one of the two 16 bit ports Port 0 is used as an input output for both addresses and data Important timing characteristics of the external bus interface Memory Cycle Time Memory Tri State Time and Read Write Delay have been made programmable to allow the user the adaption of a wide range of different types of memories Access to very slow memories is supported via a particular Ready function Semiconductor Group 3 2 SIEMENS System Description For applications which require less than 64 Kbytes of memory space a non segmented memory model can be selected In this case all memory locations can be addressed by 16 bits and thus Port 4 is not needed as an output for the two most significant address bits A17 and A16 as is the case when using the segmented memory model 3 3 Central Processing Unit CPU The main core of the CPU consists of a 4 stage instruction pipeline a 16 bit arithmetic and logic unit ALU and dedicated SFRs Additional hardware has been spent fora separate multiply and divide unit a bit mask generator and a barrel shifter Based on these hardware provisions most of the SAB 80C166 s instructions can be exected in just one machine cycle which req
5. 7 2 1 1 Interrupt Control Registers All interrupt control registers are organized identically An interrupt control register is 8 bits wide and contains the complete interrupt status information of the associated source which is required during one round of prioritization All interrupt control registers are bit addressable and all bits can be read or written by software This allows each interrupt source to be programmed or modified with just one instruction When accessing interrupt control registers through instructions which operate on word data types bits 8 through 15 will be read as zeros while the written value is insignificant In figure 7 1 an example of the SAB 80C166 s Interrupt Control registers xxlC is shown where xx replaces the mnemonic for the specific source Each interrupt control register with its name and address will be shown in the specific section on the peripheral it is associated with see chapter 8 The function of each single or multiple bit field of an interrupt control register is described in more detail in the following paragraphs Siemens Aktiengesellschaft 7 5 Interrupt and Trap Functions Figure 7 1 Interrupt Control Register for Source xx xxiC Reset Value 0000h Position Function Interrupt Group Priority GLVL 3 Highest group priority GLVL 0 Lowest group priority Interrupt Priority Level ILVL Fh Highest priority level ILVL 0 Request will not be serviced Interrupt Enable Contr
6. In order to use pin P2 x CCxlO as compare signal output pin in the double register mode P2 x must be configured as output i e the corresponding direction control bit DP2 x in register DP2 must be set to 1 With this configuration P2 x has the same characteristics as in compare mode 1 Figure 8 1 16 shows a functional diagram of a register pair configured for the double register compare mode In this configuration example the same timer allocation was chosen for both compare registers but each register may also be individually allocated to either timer TO or T1 Figure 8 1 17 shows a timing example for this compare mode In this example the compare values in registers CCx and CCz are not modified Semiconductor Group 8 21 SIEMENS Compare Reg CCx CAPCOM Timer Ty Compare Reg CCz Figure 8 1 16 Peripherals Interrupt CCMODx Bequest Mode 1 Interrupt Request Mode 0 CCMODz Interrupt Request Double Register Compare Mode Block Diagram Interrupt Requests E ocan eaan ices ccart State of CCxIO Figure 8 1 17 FFFFh Compare Value in CCz Compare Value in CCx Timing Example for the Double Register Compare Mode Semiconductor Group 8 22 SIEMENS Peripherals 8 1 2 3 Capture Compare Interrupts Upon a capture or compare event the interrupt request flag CCxIR for the respective capture compare register CCx is set to 1 This flag can be used to generate an interrupt or tri
7. C Application Examples This portion of the appendix is subdivided into two sections Section C 1 shows examples for the use of different types of memories connected to the SAB 80C166 in different external bus configurations Section C 2 contains formulas tables and examples for programming the SAB 80C166 wait states described in detail in section 9 7 C 1 External Bus and Memory Configurations A description of the possible SAB 80C166 external bus configuration modes which are determined by the state of the EBC1 and EBCO input pins during reset can be found in chapter 9 0 Note that the following examples refer to the non segmented memory model which supports only 64 Kbytes of memory space Thus port pins P4 1 and P4 0 are not required as an output of additional segment address bits A17 and A16 1 16 bit Addresses 8 bit Data Multiplexed Bus External RAM ROM Byte Organized Memories This configuration is shown in figure C 1 An external byte organized memory is implemented by a 32K 8 EPROM and an 8K 8 RAM The connected external bus is used for both 16 bit addresses and 8 bit data Because of time multiplexing an external address latch is required for the lower byte of the address 2 6 bit Addresses 16 bit Data Multiplexed Bus External RAM ROM Byte Organized Memories This configuration is shown in figure C 2 The external memory is implemented by two 16K 8 EPROMs and by two 2K 8 RAMs The connected external bus is us
8. SAB 80C166 83C166 SIEMENS Note The new scheme of selecting a bus mode during reset is fully upward compatible to the existing AB step of the SAB 80C166 when external start of execution is selected For this selection the BUSACT pin is tied to 0 which corresponds to the level at pin 7 of the AB step which is a GND pin There is only a difference for the ROM version the SAB 83C166 Since currently no mask ROM programmed components are delivered and used no board design change is necessary in order to use the BA step in already existing boards The external pins BUSACT EBCO and EBC1 are used to specify from where the first instruction after a reset should be fetched by the SAB 80C166 During the initialization routine however the user has the option to change any configuration which was selected during reset Other than in the AB step where the ROMEN bit was a read only bit if the single chip mode was selected during reset the new BUSACT bit which replaces the ROMEN bit is always read and writeable Also the BTYP bits which were read only bits if an external bus mode was selected during reset are now always read and writeable regardless whether execution begins with single chip mode or external bus mode This feature of the BTYP field is already implemented in the AB step see Errata Sheet SAB 80C166 S Release 1 3 page 6 Thus one has full control over these bits and can reprogram the bus configuration after reset In addi
9. Siemens Aktiengesellschaft 9 9 External Bus Interface Figure 9 7 Multiplexed External Bus Accesses ALE WR A memory access is initiated by the controller by placing an address on the bus and then generating the Address Latch Enable signal ALE This signal triggers an external latch to capture the address After a period of time during which the address must have been latched externally the address is removed from the bus Note that in the 16 18 bit Address 8 bit Data Multiplexed bus mode only the lower eight bits of Port 0 are muitiplexed on the external bus between address output and data input output while the upper eight bits of Port O continue to output address bits A15 to A8 throughout the entire memory access cycle Note also that Port 4 is never time multiplexed and continues to output the two most significant segment address bits A17 and A16 9 6 1 1 Multiplexed Bus Memory Reads At the same time when the address is removed from the bus which is then tri stated again the active low memory read signal RD is applied to the memory This enables the memory to drive data onto the bus After a period of time which is determined by the access time of the memory data become valid on the bus Then the controller latches the valid data from the bus and removes its memory read signal This causes the memory to remove its data from the bus which is then tri stated again Siemens Aktiengesellschaft 9 10 E
10. Table 6 2 Long Addressing Mode Physical Address Long Address Range Allows Access On DPPO mem A 3FFFh 0000 3FFFh Any Byte or Word DPP1 mem A 3FFFh 4000 7FFFh DPP2 mem A 3FFFh 8000 BFFFh mem A 3FFFh FFFFh Mnemonic 6 2 3 Indirect Addressing Modes These addressing modes can be regarded as a mixture of short and long addressing mo des This means that long 16 bit addresses are specified indirectly by the contents of a word GPR which is specified directly by a short 4 bit address Rw 0 to 15 Note that for some instructions only the lowest four word GPRs RO to R3 can be used as indirect address pointers which are specified via short 2 bit address in that case There are indi rect addressing modes where the GPR contents are modified by a constant addition be fore the long 16 bit address is calculated Moreover there are addressing modes which allow decrementing or incrementing the indirect address pointers bya data type depen dent value In each case one of the four DPP registers isusedto specify physical 18 bitaddresses Any word or byte data within the entire memory space can be addressed indirectly Word ac cesses may not be performed on odd byte addresses Otherwise a hardware trap would occur After reset the DPP registers are initialized in a way that all indirectly generated long addresses are directly mapped onto the identical physical addresses The following algorithm
11. arsi Eoo EUR RR RO ALBIS IARE 7 29 Stack Underflow Trap cule v ERR EEG ERR VERRE EEE 7 29 Undefined Opco de Trap sivo ae RE arbe wate YER ER 7 30 Protection Fault Trap sso x xU ae reen EO e Baws wee 7 30 Illegal Word Operand Access Trap leleleess 7 30 Illegal Instruction Access Trap eee 7 30 Illegal External Bus Access Trap leeren 7 30 Peripherals oesie tu doie diaii PES de wid 8 1 Capture Compare CAPCOM Unit sese 8 2 Timers TO and Ti sario Abu Sarees Rv yore arenes 8 5 Timer Mode uu eio euo uk sv E Eu MeV qe ERES 8 6 Counter ModE iua codo eae eX VAT A dac v UA US ea a 8 7 Reload 2 52 22 hii ga Seid aoa ata Se PII E MEE eters 8 8 Timer TO and T1 Interrupt 4 voee MA wee haere dae eae de See 8 8 Block Diagrami sa keke sk ante tien es bee eye ae eee see Rae OX 8 8 Capture Compare Registers 0 eee ee eee ees 8 9 Capture Mode 32 eds Seats ES ACE a Aarne N08 nd PRA E 8 13 Compare Modes i 2g pegar wa vae RUE a a RAT oes 8 14 Compare Moda O secc 605 sce rer demas EA y or 9 4 8 14 Compare ModB 1 obi Lil Rae ee REG mee dore Vrat wee 8 16 Compare Moda 2 seven sean et an oe i A M etos 8 17 Compare Mode 3 04 0240 xao S064 nx CR ge wA heen ewes 8 18 Double Register Compare Mode ee eee eens 8 19 Capture Compare Interrupts 0 ee eee ee ee tees 8 22 General Purpose Timers GPT 2 0 2 2 eee eee 8 22 GPTEBIGSR ona Cate e
12. 4 etc This results in periodic interrupt requests from timer Ty and in interrupt requests from register CCx which occur at the time specified by the user through cv1 and cv2 Interrupt Compare Reg CCx Request Interrupt CAPCOM Timer Ty Request Figure 8 1 10 Compare Mode 0 and 1 Block Diagram Contents of Ty FFFFh Compare Value cv2 Compare Value cv1 Reload Value lt TyREL gt 0000h Interrupt Requests TyIR CCxIR CCxIR TyIR CCxIR COxIR TyIR gt Event 1 Event 2 Event 3 Event 4 t CCx cv2 CCx cv1 CCx cv2 CCx cv1 Figure 8 1 11 Timing Example for Compare Mode 0 Semiconductor Group 8 16 SIEMENS Peripherals 8 1 2 2 2 Compare Mode 1 Compare mode 1 is selected for register CCx by setting bit field CCMODx of the corresponding mode control register to 101b When a match between the contents of the allocated timer and the compare value in register CCx is detected in this mode interrupt request flag CCxIR is set to 1 but also the corresponding pin CCxIO alternate output function of Port 2 pin P2 x is toggled For this purpose the state of Port 2 output latch P2 x not the pin is read inverted and then written back to the output latch Compare mode 1 allows several compare events within a single timer period An overflow of the timer to which compare register CCx is allocated has no effect on pin P2 x nor does it disable or enable further compare events In order to use pin P2 x CCxlO as
13. FOh FFh CP 1 reg A OFh reg FOh FFh reg bitoff OFDOOh 2 bitoff bitoff OOh RAM Bit Word Offset OFFOOh 2 bitoffA OFFh bitoff 80h EFh SFR Bit Word Offset CP 2 bitoff A OFh bitoff FOh FFh GPR Bit Word Offset bitaddr Word offset see bitoff bitoff z Any Single Bit Immediate Bit Position bitpos In the following the short addressing modes which are shown in table 6 1 are described in more detail Rw Rb Specifies direct access to any GPR inthe currently active context register bank Both Rw and Rb require four bits in the instruction format The base address is determined by the contents of the CP register Rw specifies a 4 bit word GPR address relative to the base address CP while Rb specifies a4 bit byte GPR address relative to the base address CP reg Specifies direct access to any SFR or GPR in the currently active context regis ter bank reg requires eight bits in the instruction format Short reg addres ses from OOh to EFh always specify SFRs In that case the base address is OFEOOh and the factor A equates 2 Depending on the opcode of an instruction either the total word for word operations or the low byte for byte operations of an SFR can be addressed via reg Note that the high byte of an SFR can not be accessed via the reg addressing mode Short reg addresses from FOh to FFh always specify GPRs In that
14. Function i Enable Read Buffer Alternate Write Port P3 12 Data Output Output Buffer P3 12 BHE Buffer Figure 10 11 Block Diagram of Port 3 Pin BHE Semiconductor Group 10 13 SIEMENS Parallel Ports 10 1 3 4 Port 3 Pins RXDO and RXD1 The configuration of the two pins RXDO and RXD1 with both an alternate input and an alternate output function is shown in figure 10 12 The Alternate Data Output line again is ANDed with the port output latch line In the asynchronous modes of the Serial Channels pins RXDO and RXD1 are always used as data inputs The direction of these pins must be set to input by the user DP3 y 0 The Serial Channels read the state of pins RXDO and RXD1 via the line Alternate Data Input In the half duplex synchronous mode pins RXDO and RXD1 are used as either data inputs or outputs For transmission the user first must set the direction to output DP3 y 1 and must write a 1 into the port output latch For reception the user must set the direction to input before starting the reception When the alternate output function on these pins is not used the Alternate Data Output line is in its inactive state which is a high level 1 Write DP3 y Direction Latch DP3 y Read DP3 y Read Alternate Buffer Data Output Write Port P3 y Output Latch P3 9 RXD1 P3 11 RXDO Read Port P3 y Read l Buffer Alternate Data Input Figure 10 12 Block Diagram of Port 3 Pins R
15. The internal system stack can also be used to temporarily store data between subrou tines or tasks Instructions are provided to push or pop registers on from the system stack However in most cases the register banking scheme provides the best perfor mance for saving state between multiple tasks Note THE SYSTEM STACK PERMITS STORAGE OF WORDS ONLY Bytes can be stored on the system stack but must be extended to words first One must also con sider that only even byte addresses can be stored in the SP register LSB of SP is always 0 Detection of stack overflow underflow is supported by two registers STKOV Stack Overflow Pointer and STKUN Stack Underflow Pointer Specific system traps Stack Overflow trap Stack Underflow trap will be entered whenever the SP reaches either boundary specified in these pointer registers The contents of the Stack Pointer are always compared to the contents of the Overflow register whenever the SP is DECREMENTED either by a Call Push or Subtract instruction An Overflow Trap will be entered when the SP value is less than the value in the Stack Overflow register The Stack Pointer value is compared to the contents of the Underflow register whenever the SP is INCREMENTED either by a Return Pop or Addinstruction An Under flow Trap will be entered when the SP value is greater than the value in the Stack Underflow register When a value is MOVED into the Stack Pointer NO check against the
16. The overflow flag V is set if the resuit can not be represented in a word data type One must first copy the high portion of the MD register result into the register file or memory to ensure that the MDRIU flag is set correctly but one may write to either half of the MD register to set the MDRIU flag The following instruction sequence performs a 32 by 16 bit division MOV MDH RI1 Move dividend to MD register Sets MDRIV MOV MDL R2 Move low portion to MD DIV R3 Divide 32 16 signed R3 holds the divisor JB V ERROR Test for divide overflow MOV R3 MDH Move remainder to R3 MOM R4 MDL Move integer result to R4 Clears MDRIV Whenever a multiply or divide instruction is interrupted while in progress the MULIP flag in the PSW of the interrupting routine is set When the interrupt routine is exited with the RETI instruction this bit is implicitly tested before the old PSW is popped from the stack If MULIP 1 the interrupted multiply divide instruction will then be completed after the RETI instruction has been executed Interrupt routines which require the use of the multiply divide hardware MUST first push and then clear the MDC register before starting a multiply divide operation if a multiply divide instruction was in progress in the interrupted routine MULIP 1 The MDC register holds state of the interrupted multiply divide instruction which is necessary in order to complete the instruction properly after the RETI ins
17. This modular family concept allows an easy and quick implemen tation of new family members with different internal memory sizes and technologies different sets of on chip peripherals and or different numbers of O pins As programs for embedded control applications become larger high level languages are favoured by programmers because high level language programs are easier to write and debug For its SAB 80C166 family of microcontrollers Siemens offers a complete set of software and hardware development tools including C compiler assembler linker lo cater librarian object to hex converter simulator and in circuit emulator Siemens Aktiengesellschaft 1 1 Introduction In the following the features of the SAB 80C166 family members will be discussed in detail The SAB 80C166 family currently includes SAB 80C166 S ROM less Version SAB 83C166 3S mask programmable ROM Version Note In this document any reference to the SAB 80C166 also applies tothe SAB 83C166 unless otherwise noted All time specifications are referredto a CPU clockof 20 MHz which means an oscillator frequency fosc of 40 MHz 1 2 Features of the SAB 80C166 and the SAB 83C166 The SAB 80C166 and the SAB 83C166 are the first representatives of the new Siemens SAB 80C166 family of fuil featured single chip CMOS microcontrollers They combine high CPU performance up to 10 millions of instructions per second with high peripheral functionality A summar
18. When BUSACT is high at the end of reset the SAB 80C166 fetches the first instruction from the internal ROM space regardless of the state of the pins EBCO and EBC1 However to avoid unintentional effects caused by read modify write operations on the SYSCON register it is recommended to select the Single Chip Mode only with the EBC pins tied low When BUSACTH is low at the end of reset the SAB 80C166 fetches the first instruction from external memory with a bus configuration specified through EBCO and EBC1 Note that for all members of the SAB 80C166 family without internal program memory e g the ROM less SAB 80C166 BUSACT must be tied low The following table illustrates all possible options BUSACT EBC 1 EBCO Bus Mode 1 0 0 Single Chip Mode 1 0 1 reserved but currently the Single Chip Mode will be entered 1 1 0 reserved but currently the Single Chip Mode will be entered 1 1 1 reserved but currently the Singel Chip Mode will be entered 0 0 0 8 Bit data non multiplexed bus 0 0 1 8 Bit data multiplexed bus 0 1 0 16 Bit data multiplexed bus 0 1 1 16 Bit data non multiplexed bus With the end of reset the inverted value of the pin BUSACT is copied into bit 10 BUSACT of register SYSCON this bit used to be the ROM enable bit ROMEN The value of the pins EBCO and EBC1 are copied into the BTYP field of the SYSCON register Figure 5 1 shows the new organisation of register SYSCON Semiconductor Group D 5
19. XXXXh read only SORIC b FF6Eh B7h Serial Channel 0 Receive Interrupt Control 0000h SOTBUF FEBOh 58h Serial Channel 0 Transmit Buffer Register 0000h write only SOTIC b FF6Ch B6h Serial Channel 0 Transmit Interrupt Control 0000h Semiconductor Group B 15 SIEMENS SAB 80C166 Registers Name Physical 8 Bit Description Reset Address Address Value S1G FEBCh 5Eh Serial Channel 1 Baud Rade Generator 0000h Reload Register S1CON b FFB8h DCh Serial Channel 1 Control Register 0000h S1EIC b FF76h BBh Serial Channel 1 Error Interrupt control 0000h S1RBUF FEBAh 5Dh Serial Channel 1 Receive Buffer Register XXXXh read only S1RIC b FF74h BAh Serial Channel 1 Receive Interrupt Control 0000h S1TBUF FEB8h 5Ch Serial Channel 1 Transmit Buffer Register 0000h write only S1TIC b FF72h B9h Serial Channel 1 Transmit Interrupt Control 0000h SP FE12h 09h CPU System Stack Pointer Register FCOOh STKOV FE14h OAh CPU Stack Overflow Pointer Register FAOOh STKUN FE16h OBh CPU Stack Underflow Pointer Register FCOOh SYSCON b FFOCh 86h CPU System Configuration Register OXXOh system configuration selected during reset TO FE50h 28h CAPCOM Timer 0 Register 0000h TO1CON b FF50h A8h CAPCOM Timer 0 and Timer 1 Control 0000h TOIC b FF9Ch CEh CAPCOM Timer 0 Interrupt Control 0000h Register TOREL FE54h 2Ah CAPCOM Timer 0 Reload Register 0000h T1 FE52h 29h CAPCOM Timer 1 Reload
20. bus modes One can also disable the ROM if only test and initialization routines were stored in ROM Remap the internal ROM to segment one This allows to have the interrupt vector table internal or external Notes Although the combinations 001 010 and 011 which are marked as reserved would also select the internal ROM in segment 0 it is strongly recommended not to use these combinations since unexpected results may occur when changing SYSCON parameters One must be very careful when changing the SYSCON parameters during the initialisation routine One must not execute instructions from a resource external bus or internal ROM which is to be switched e g disabling the external bus when executing from external memory Example Consider the case where an application requires to have an external 16 bit non multiplexed data bus and the internal ROM mapped to segment 1 After reset the execution should start from external memory For this purpose pin BUSACT is tied to 0 and pins EBC1 and EBCO are tied to 1 After the reset is performed the chip starts fetching instructions from the external memory In the initialisation routine software changes the bits in the SYSCON register such that BUSACT 0 and the BTYP field is 01 This enables the internal ROM in segment 1 The configuration of the external bus however is not changed via this modification The external bus is only changed when BUSACT 1 After execution of the
21. depending on the selected range size only a part of this bit field is relevant for specification of the start address This is shown in the following table x don t care R relevant bit Range Size Selected Address Range Relevant Bits of RGSZ Range Start Address 000 2 KByte RRRRRRR 001 16 KByte RRRRxxx 010 32 KByte RRRxxxx 011 64 KByte RRXxxxx 100 128 KByte RXXXXXX 101 reserved 110 reserved 111 reserved After reset all bits of the BUSCON1 register are cleared to 0 Other than for the SYSCON register the state of the external bus control pins EBCO EBC1 and BUSACTZ are not copied into the BUSCON 1 register after reset After reset the BUSCON1 register is disabled and all bus characteristics are controlled by register SYSCON To enable the BUSCON1 register one should first specify an address range and start address of this range through register ADDRSEL1 then program the BUSCON1 register to the desired bus configuration and set the BUSACT control bit The BUSCON1 register will then take control of the external bus when an access to the specified address range is made During accesses to all other addresses outside the address range specified through register ADDRSEL1 the SYSCON parameters control the external bus characteristics Figure 7 3 illustrates an example how to partition the address space into a range controlled through the new BUSCON1 register and into ranges controlled through the SYSC
22. lt T1REL gt 2 T P PTo 7 pri fosc fosc The timer input frequencies resolution and periods which result from the selected prescaler option in TOI or T11 when using a 40 MHz oscillator are listed in table 8 1 1 The numbers for the timer periods are based on a reload value of 0000h Note that some numbers may be rounded to 3 significant digits Table 8 1 1 CAPCOM Timers TO and T1 Input Frequencies Resolution and Periods fosc 40MHz Timer Input Selection TOI T1I 000b 001b 010b 011b 100b 101b 110b 111b Prescaler for fosc 16 32 64 128 256 512 1024 2048 Input Frequency 2 5 1 25 625 312 5 156 25 78 125 39 06 19 53 MHz MHz kHz kHz kHz kHz kHz kHz Resolution 400 ns 800 ns 1 6us 3 2us 6 4us 12 8 us 25 6 us 51 2 us Period 26 ms 52 5ms 105 ms 210 ms 420 ms 840 ms 1 68s 3 36 s After a timer has been started by setting its run flag TOR or T1R to 1 the first increment will occur within the time interval which is defined by the selected timer resolution All further increments occur exactly after the time defined by the timer resolution When both timers are to be incremented or reloaded at the same time TO is always serviced one state before T1 Semiconductor Group SIEMENS Peripherals 8 1 1 2 Counter Mode Counter mode is selected for timer TO or T1 by setting the appropriate mode selection bit TOM or T1M in register TO1CON to 1
23. otherwise a hardware trap would occur rel This mnemonic represents an 8 bit signed word offset address relative to the current Instruction Pointer contents which represent the address of the instruc tion after the branch instruction Depending on the offset address range either forward rel 00h to 7F or backward rel 80h to FFh branches are possi ble According to an either word or double word sized branch instruction a rel value of 1 FFh or 2 FEh leads to a repeated execution of the branch instruction itself Rw In this case the 16 bit branch target instruction address is determined indirec tly by the contents of a word GPR In contrast to indirect data addresses indirec tly specified code addresses are NOT caiculated via additional pointer registers e g DPP registers Note that branches MAY NOT betaken to odd code addres ses Therefore the least significant bit of the address pointer GPR mustalways contain a 0 otherwise a hardware trap would occur seg Specifies an absolute code segment number Currently the SAB 80C166 sup ports four different code segments and thus only the two least significant bits of the seg operand value are used for updating the CSP register trap7 Specifies a particular interrupt or trap number for branching to the correspon ding interrupt or trap service routine via a jump vector table According to the maximum number of interrupt sources which are provided for th
24. the controller latches the valid data from the data bus and removes its memory read signal This causes the memory to remove its data from the data bus which is then tri stated again Simultaneously with the removal of the RD signal the controller puts the address for the next memory access on the address bus if a subsequent external memory access is required 9 6 2 2 Non Multiplexed Bus Memory Writes A memory write access is initiated by the controller by placing an address on the address bus This address stays valid on the bus until the next memory access cycle is started After a fixed period of time the controller drives its data onto the data bus and applies the active low memory write signal WR to the memory This enables the memory to store the data from the data bus onto the addressed location After a period of time which is determined by the access time of the memory the data become valid in the addressed memory location Then the controller removes its memory write signal and puts the address for the next memory access on the address bus if a subsequent exter nal memory access is required The data remain valid on the data bus until the next memory access cycle is started 9 7 User Selectable Bus Characteristics Important timing characteristics of the external bus interface including the Memory Cycle Time the Memory Tri State Time and the Read Write Delay Time have been made user programmable to allow adapting a wide range
25. the minimum time Timin ext to process an external instruction additionally depends on the instruction length Timin ext is either 1 ALE Cycle Time for most of the 2 byte instructions or 2 ALE Cycle Times for most of the 4 byte instructions The following formula represents the minimum execution time of in structions fetched from an external memory via a 16 bit wide data bus Siemens Aktiengesellschaft 5 9 Central Processing Unit CPU For 2 byte instructions Timn ext TACT Timin ROM 2 States For 4 byte instructions Tima ext 2 ACTs Timin ROM 2 States For instructions fetched from an external memory via an 8 bit wide data bus the mini mum number of required ALE Cycle Times is twice the number for a 16 bit wide bus 5 2 3 Additional State Times As described in the following some operand accesses can extend the execution time of an instruction Tin Since the additional time Tiag is mostly caused by internal instruction pipelining it often will be possible to evade these timing effects in time critical program modules by means of a suitable rearrangement of the corresponding instruction sequen ces The SAB 80C166 simulator and emulator offer a lot of facilities which support the user in optimizing his program whenever required 1 Internal ROM operand reads Tas 2 States Both byte and word operand reads always require 2 additional state times 2 Internal RAM operand reads via indirect addre
26. timers T2 or T4 its corresponding interrupt request flag T2IR or T4IR will be set This flag may cause an interrupt to the specific auxiliary timer s interrupt vector T2INT or T4INT or initiate a PEC transfer when the request is enabled Each of the auxiliary timers T2 and T4 has its own interrupt control register T21C T4IC as shown in figure 8 2 18 Refer to chapter 7 for further details on interrupts T2IC FF60h BOh Reset Value 0000h 7 6 5 4 3 2 1 0 T4IC FF64h B2h Reset Value 0000h 7 6 5 4 3 2 1 0 Figure 8 2 18 GPT1 Auxiliary Timer Interrupt Control Registers T2IC and T4IC 8 2 2 GPT2 Block Block GPT2 supports high precision event control with a maximum resolution of 200 ns 40 MHz oscillator frequency It includes the two timers T5 and T6 and the 16 bit capture reload register CAPREL Timer T6 is referred to as the core timer and T5 is referred to as the auxiliary timer of GPT2 An overflow underflow of T6 which can only operate in timer mode is indicated by a toggle bit T6OTL whose state may be output on an alternate function port pin In addition T6 may be reloaded with the contents of CAPREL The toggle bit also supports concatenation of T6 with auxiliary timer T5 while concatenation of T6 with CAPCOM timers TO and T1 is provided through a direct connection Based on an external signal the contents of T5 can be captured into register CAPREL and T5 may optionally be cleared Both timer T6 and T5 can cou
27. 1 is used as a word wide address output and Port 0 is used as separated word wide data output The least significant address bit AO is normally not used when accessing word organized memories Since two independent buses are used no time multiplexing and no additional address latch is required in this case As long as memory segmentation is not disabled Port 4 is additionally used as an output for the two most significant bits of the required 18 bit addresses Compared with the other external bus configuration modes the 16 18 bit Address 16 bit Data Non Muitiplexed Bus mode provides the highest level of performance It is faster than other modes because it doesn t have to access the memory twice in order to fetch a word wide value and it also saves the additional time delay caused by address and data multiplexing If the 16 18 bit Address 16 bit Data Non Multiplexed Bus mode has been selected once during reset internal ROM accesses are globally disabled and no other external bus configuration can be selected later Figure 9 5 16 18 Bit Address 16 Bit Data Non Multiplexed Bus Word Wide Memories Porta WR RO ADDR OE WR Port 1 16 Bit SAB 80C166 Ext Memory INSTR DATA A0 not used As shown in figure 9 6 this external bus configuration mode can also be selected if the word organized external memory is implemented by two separate 8 bit wide memory devices These two memories can be accessed both wordwise coupled toget
28. 3 5 shows the interrupt control registers which are associated with the A D converter For more details on interrupts refer to chapter 7 ADCIC FF98h CCh Reset Value 0000h 7 6 5 4 3 2 1 0 ADCIR ADCIE ILVL GLVL ADEIC FF9Ah CDh Reset Value 0000h Figure 8 3 5 Interrupt Control Registers ADCIC and ADEIC Semiconductor Group 8 60 SIEMENS Peripherals 8 4 Serial Channels For serial communication with other microcontrollers microprocessors and external peripherals the SAB 80C166 has two identical serial interfaces on chip Serial Channel 0 ASCO and Serial Channel 1 ASC1 They support full duplex asynchronous communication up to 625 KBaud and half duplex synchronous communication up to 2 5 MBaud In the synchronous mode data are transmitted or received synchronous to a shift clock which is generated by the SAB 80C166 In the asynchronous mode 8 or 9 bit data transfer parity generation and the number of stop bits can be selected The reception of data is double buffered Parity framing and overrun error detection is provided to increase the reliability of data transfers For multiprocessor communication a mechanism to distinguish address from data bytes is included and a loop back option is available for testing purposes Each serial channel has separate interrupt vectors for receive transmit and error and each channel has its own dedicated baud rate generator This is a 13 bit timer with a 13 bit reload registe
29. 4 1 SFRs and Port Pins Associated with the Serial Channels 8 4 1 Modes of Operation The operation of the serial channels ASCO and ASC1 is controlled by the bit addressable control registers SOCON and S1CON which are shown in figure 8 4 2 They contain control bits for mode and error check selection and status flags for error identification Semiconductor Group 8 62 SIEMENS Peripherals SOCON FFBOh D8h Reset Value 0000h 13 12 11 10 9 8 15 14 ee Ee pee ees 7 6 5 4 3 2 1 0 EE psema ae S1CON FFB8h DCh Reset Value 0000h 15 14 13 12 11 10 9 8 ERED pope pes wenns Figure 8 4 2 Serial Channels Control Registers SOCON and S1CON Symbol Position Function SxM SxCON 2 0 ASCx Mode Control see table 8 4 1 SxSTP SxCON 3 Number of Stop Bits Selection SxSTP 0 One Stop Bit SxSTP 1 Two Stop Bits SxREN SxCON 4 Receiver Enable Bit Used to Initiate Reception Reset by hardware after a byte in synchronous mode has been received SxREN 0 Receiver Disabled SxREN 1 Receiver Enabled SxPEN SxCON 5 Parity Check Enable Bit SxPEN 0 Parity Check Disabled SxPEN 1 Parity Check Enabled SxFEN SxCON 6 Framing Check Enable Bit SxFEN 0 Framing Check Disabled SxFEN 1 Framing Check Enabled SxOEN SxCON 7 Overrun Check Enable Bit SxOEN 0 Overrun Check Disabled SxOEN 1 Overrun Check Enabled SxPE SxCON 8 Parity Error Flag Set by hardware when a parity error occurs and SxPEN 1 Mu
30. 7 21 Interrupt and Trap Functions In general all delays with respect to the standard instruction execution time which may occur during execution of instructions in the pipeline may result in a longer interrupt res ponse time When internal hold conditions between instruction pairs N 2 N 1 or N 1 N occur or instruction N explicitly writes to the PSW the minimum interrupt response time may be extended by 1 state time for each of these conditions When instruction N reads an operand from the internal ROM or when N is a call return trap or MOV Rn Rm data16 instruction the minimum interrupt response time may additionally be extended by 2 state times during internal ROM program execution In case instruction N reads the PSW and instruction N 1 has an effect on the condition flags the interrupt response time may additionally be extended by 2 state times The worst case interrupt response time during internal ROM program execution is 12 state times 500 ns 40 MHz See section 5 2 for more details on instruction timing The absolute worst case interrupt response time will occur when instructions N through N 2 are executed out of an external memory instructions N and N 1 require external operand read accesses instructions N 3 through N write back external operands and the interrupt vector location is also in the external memory In this case the interrupt respon se time is the time to perform 9 word bus accesses because instruction
31. 80C166 83C166 SIEMENS ee a ee EEEE N EN qt Mies Sei Ic o m Lll r IL IpIl l 0 e i c NE EDS ol A s MS inl FTO cof 3 E ce E pm nad nii od d mi i i m M rd ecg PENER f 4 EERE pein 3k 3t a 2 a tc T tc 3 oc oc T c Xo 2 Q Q E E x x ui ui READY Line is Checked Using READY and Wait States Figure 6 1 D 18 Semiconductor Group SIEMENS SAB 80C166 83C166 BUSCON1 FF14h 8Ah Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BTYP MTTC1 RWDC1 MCTC Figure 7 1 Bus Configuration Register BUSCON1 Symbol Position Function MCTC BUSCON1 8 0 Memory Cycle Time Control RWDC BUSCON1 4 Read Write Delay Control MTTC1 BUSCON 1 5 Memory Tri state Time Control BTYP BUSCON 7 6 External Bus Configuration Control See description for details BUSCON1 8 reserved ALECTL1 BUSCON1 9 ALE Lengthening Control Bit BUSACT1 BUSCON 1 10 Bus Active Control Bit See description for details BUSCON1 11 reserved RDYEN1 BUSCON1 12 READY Input Enabled control bit RDYEN1 0 READY function disabled for BUSCON1 accesses RDYEN1 1 READY function enabled for BUSCON1 accesses BUSCON 15 13 reserved Semiconductor Group D 19 SIEMENS SAB 80C166 83C166 ADDRSEL1 FE18h 0Ch Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
32. 80C166 also contains two blocks of general purpose timers acapture compare unit two serial interface channels an A D converter a watchdog timer six I O ports with a total of 76 I O lines Each peripheral also contains a set of SFRs which control the functionality of the peripheral and temporarily store intermediate data results Each peripheral has an associated set of status flags Individually selected clock signals are generated for each peripheral from binary multiples of the system clock Semiconductor Group 2 7 SIEMENS System Description 3 System Description In this chapter a summary of the SAB 80C166 is presented The following block diagram gives an overview of the different on chip components and of the advanced high bandwidth internal bus structure of the SAB 80C166 Internal Internal ROM SAB 80C166 32 RAM ER 8 KBytes 2 1K SAB 83C16 CEUS GARE Bytes 16 AN AN AN 10 bit USART USART CAPCOM ADC ASCO ASC1 1 0 Figure 3 1 Block Diagram Semiconductor Group 3 1 SIEMENS System Description 3 1 Memory Organization The memory space of the SAB 80C166 is configured in a Von Neumann architecture which means that code memory data memory registers and I O ports are organized within the same linear address space which currently includes 256 Kbytes Address space expansion to 16 Mbytes is provided for future versions The entire memory space ca
33. Both timers can operate in counter mode by counting the overflows underflows of timer T6 in block GPT2 see section 8 2 2 for details on GPT2 In addition timer TO offers the capability of being clocked by external events Either a positive a negative or both a positive and a negative transition at pin TOIN alternate input function of port pin P3 0 can be selected to cause an increment of TO When T1 is programmed to run in counter mode T1M 1 bit field T11 is used to enable the overflows underflows of timer T6 as the count source for T1 This is the only option for T1 and it is selected by the combination T1l2X00b When bit field T1l is programmed to other combinations timer T1 stops When TO is programmed to run in counter mode TOM 1 bit field TOI is used to select the count source and transition which should cause a count trigger for TO Table 8 1 2 shows the possible selections for the counter mode of timers TO and T1 Table 8 1 2 Input Selection for TO and T1 in Counter Mode Counter TO is Incremented on TOI T1I Counter T1 is incremented on 2 1 0 Overflow or Underflow of GPT2 Timer T6 Positive External Transition at Pin TOIN Negative External Transition at Pin TOIN Positive and Negative Transition at TOIN Overflow or Underflow of GPT2 Timer T6 Counter T1 stops Counter T1 stops Counter T1 stops X Xxx olo a o A o In order to use pin P3 0 TOIN as external count inp
34. Code Segment Pointer CSP registers are both cleared and thus program execution begins at the internal ROM location 00000h As shown in figure 9 1 Port 0 Port 1 and Port 4 A17 and A16 can be used as general purpose O registers Note that any intended access to a location within the external memory space will cause a hardware trap to occur if the controller is in the single chip mode For applications where the on chip program memory is not sufficient the single chip mode can be left by simply modifying the BTYP bit field in the SYSCON register see section 5 3 1 1 In this case an external memory can be accessed and the entire on chip memory stays accessible Siemens Aktiengesellschaft 9 3 External Bus Interface Figure 9 1 Single Chip Mode Port 4 SAB 83C166 Port 0 4 1 0 9 3 16 18 Bit Address 8 Bit Data Multiplexed Bus This external bus mode must be selected if a byte wide external memory shall be con nected to the SAB 80C166 As shown in figure 9 2 the lower address byte and the data byte are time multiplexed on the lower portion of the word wide external bus Therefore an external byte wide address latch is required for the eight least significant address bits An Address Latch Enable ALE signal is generated by the on chip External Bus Controller EBC to signify a valid address being available on Port 0 As long as memory segmentation is not disabled Port 4 is additionally used as an output for th
35. Control 0000h CC13 FE9Ah 4Dh CAPCOM Register 13 0000h CC13lC b FF92h C9h CAPCOM Register 13 Interrupt Control 0000h Semiconductor Group B 13 SIEMENS SAB 80C166 Registers Name Physical 8 Bit Description Reset Address Address Value CC14 FE9Ch 4Eh CAPCOM Register 14 0000h CC14IC b FF94h CAh CAPCOM Register 14 Interrupt Control 0000h CC15 FE9Eh 4Fh CAPCOM Register 15 0000h CC15IC b FF96h CBh CAPCOM Register 15 Interrupt Control 0000h CCMO b FF52h A9h CAPCOM Mode Control Register 0 0000h CCM1 b FF54h AAh CAPCOM Mode Control Register 1 0000h CCM2 b FF56h ABh CAPCOM Mode Control Register 2 0000h CCM3 b FF58h ACh CAPCOM Mode Control Register 3 0000h CP FE10h 08h CPU Context Pointer Register FCOOh CRIC b FF6Ah B5h GPT2 CAPREL Interrupt Control Register 0000h CSP FEO8h 04h CPU Code Segment Pointer Register 0000h 2 Bits read only DPO b FFO2h 81h Port 0 Direction Control Register 0000h DP1 b FFO6h 83h Port 1 Direction Control Register 0000h DP2 b FFC2h Eth Port 2 Direction Control Register 0000h DP3 b FFC6h E3h Port 3 Direction Control Register 0000h DP4 b FFOAh 85h Port 4 Direction Control Register 2 Bits 0000h DPPO FEOOh 00h CPU Data Page Pointer 0 Register 4 Bits 0000h DPP1 FEO2h 01h CPU Data Page Pointer 1 Register 4 Bits 0001h DPP2 FEO4h 02h CPU Data Page Pointer 2 Register 4 Bits 0002h DPP3 FEO6h 03h CPU Data Page Pointe
36. Diagram for Interrupt Response Time DECODE EXECUTE WRITEBACK IR Flag interrupt Response Time Whenever the pipeline is advanced and a new instruction cycle is started all sources whose interrupt request flags have been set during the previous cycle compete for ser vice in a round of prioritization In the next cycle a TRAP is performed to the vector loca tion of the winning source and the source s interrupt request flag is reset to 0 Fetching of the instruction 1 at the vector loacation is started in the following cycle All instructions that are in the pipeline at the time the interrupt request flag is set will be completed be fore the interrupt service routine while the following instruction N 1 will be executed after return from the interrupt service routine As can be seen from figure 7 10 the TRAP instruction requires two cycles to push the PSW generated by instruction N and the IP and in segmentation mode the CSP of instruction N 1 The minimum interrupt response time is 5 states 250 ns 40 MHz This applies to pro gram execution from the internal ROM when no external operand read requests are per formed and when the interrupt request flag is set during the last state of an instruction cycle When the interrupt request flag is set during the first state of an instruction cycle the minimum interrupt response time under these conditions is 6 state times 300 ns 40 MHz Siemens Aktiengesellschaft
37. EINIT instruction modifications of the internal ROM address space are no more possible It is possible however to change the external bus configuration under the precautions mentioned in the note above or via the new BUSCON1 register see Chapter 7 Semiconductor Group D 7 SIEMENS SAB 80C166 83C166 6 Change of the READY Function When the READY function is enabled through bit RDYEN the selection between synchronous or asynchronous operation of READY is performed in the AB step via bit 0 of register SYSCON LSB of field MCTC In the BA step this selection is performed through bit 3 of register SYSCON which is the MSB of the MCTC Memory Cycle Time Control bit field This change frees bit positions 0 to 2 of this field These 3 bits will now be used to offer the possibility to program up to 7 Memory Cycle Time Wait States in addition to the READY function When the READY function is enabled the operation will be as follows f 0 wait states are programmed in bits 0 to 2 of the MCTC field the READY function will operate fully compatible to the specification of the AB step f between 1 and 7 wait states are programmed in bits 0 to 2 of the MCTC field the CPU will first insert the programmed number of wait states into the memory cycle Cycle Time Wait States regardless of the state of the READY line After the wait state time has expired the CPU will check the READY line and delay the memory access depending on the state of
38. For an overview of the resulting input frequencies resolution and periods when using a 40 MHz oscillator refer to table 8 2 3 in section 8 2 1 1 1 The block diagram of an auxiliary timer in timer mode is shown in the following figure 8 2 10 p i Interrupt Auxiliary Timer Tx Request Figure 8 2 10 Block Diagram of an Auxiliary Timer in Timer Mode Semiconductor Group 8 35 SIEMENS Peripherals 8 2 1 2 2 Gated Timer Mode The gated timer mode for the auxiliary timers functions as described for the core timer For the auxiliary timers an active low level for the gate is selected by setting the mode control fields T2M or TAM to 010b and an active high level is selected by the bit combination 011b The gate for timer T2 is the external input pin T2IN and T4IN is the gate for timer T4 T2IN is an alternate function of P3 7 while T4IN is an alternate function of P3 5 In order to use these alternate functions the corresponding direction control bits DP3 7 and DP3 5 must be set to 0 Figure 8 2 11 shows a block diagram of an auxiliary timer in gated timer mode pi Interrupt TxIN Auxiliary Timer Tx Request P3 7 P3 5 TxR x 2 4 Figure 8 2 11 Block Diagram of an Auxiliary Timer in Gated Timer Mode 8 2 1 2 3 Counter Mode Basically the counter mode for the auxiliary timers functions as described for the core timer In addition however timers T2 and T4 offer the possibility of selecting between two count sources Th
39. Maximum System Stack Size Selection via STKSZ PSW Processor Status Word 00 00 eeee ALU Status N C V Z E MULIP veu eee oad ie os CPU Interrupt Status IEN ILVL 2 0 ee eae IP Instruction Pointer llle CSP Code Segment Pointer 244 254 curse ce RR n DPPO DPP1 DPP2 DPP3 Data Page Pointers CP Context Pointer i2 5024 onde vee be ea EX Ra rmn Implicit CP Use with Short 4 Bit GPR Addresses Implicit CP Use with Short 8 Bit Register Addresses SP Stack Pointer 2 ee ex aeg RE doa zara Te A Oe a STKOV Stack Overflow Pointer lees STKUN Stack Underflow Pointer 2 55 MDH Multiply Divide Register High Portion MDL Multiply Divide Register Low Portion MDC Multiply Divide Control Register ONES Constant Ones Register lesus ZEROS Constant Zeros Register else Instruction Set Overview Summary of Instruction Classes Arithmetic Instructions eee Siemens Aktiengesellschaft 2 Contents Contents 6 1 2 6 1 3 6 1 4 6 1 5 6 1 6 6 1 7 6 1 8 6 1 9 6 1 10 6 1 11 6 1 12 6 2 6 2 1 6 2 2 6 2 3 6 2 4 6 2 5 6 3 7 1 7 2 7 2 1 7 2 1 1 7 2 1 2 7 2 2 7 2 2 1 7 2 2 2 7 2 3 7 2 3 1 7 2 3 2 7 2 3 3 7 2 4 7 2 4 1 7 2 4 2 7 2 4 3 7 2 5 7 2 6 7 2 7 7 3 7 3 1 Page Logical NStRIC
40. Must be reset by software Stack Overflow Trap request flag Set when the stack pointer value is less than the contents of the Stack Overflow STKOV register Must be reset by software Stack Underflow Trap request flag Set when the stack pointer value is greater than the contents of the Stack Underflow STKUV register Must be reset by software UNDOPC Undefined Opcode Trap request flag Set when the opcode of the instruction currently in decode is not a valid SAB 80C166 opcode Must be reset by software PRTFLT Protection Fault Trap request flag Set when an illegal format of a protected instruction is detected Must be reset by software ILLOPA Illegal Word Operand Access Trap request flag Set when a word operand read or write access is made to an odd byte address Must be reset by software ILLINA Illegal Instruction Access Trap request flag Set when a branch is made to an odd byte address Must be reset by software ILLBUS Illegal External Bus Access Trap request flag Set when an external access is requested and no external bus is configured Must be reset by software reserved A class A trap occurring during the execution of a class B trap service routine will be ser viced immediately During the execution of a class A trap service routine however any class B trap occurring will not be serviced until the class A trap service routine has finis hed Thus in this case the occurrence of the class B trap is stored i
41. Name Physical 8 Bit Description Reset Address Address Value ADDAT FEAOh 50h A D converter Result Register 0000h FEA2h 51h reserved e e e e e e FEACh 56h reserved WDT FEAEh 57h Watchdog Timer Register read only 0000h SOTBUF FEBOh 58h Serial Channel 0 Transmit Buffer Register 0000h write only SORBUF FEB2h 59h Serial Channel 0 Receive Buffer Register XXXXh read only SOBG FEB4h 5Ah Serial Channel 0 Baud Rate Generator 0000h Reload Register FEB6h 5Bh reserved S1TBUF FEB8h 5Ch Serial Channel 1 Transmit Buffer Register 0000h S1RBUF FEBAh 5Dh Serial Channel 1 Receive Buffer Register XXXXh read only S1BG FEBCh 5Eh Serial Channel 1 Baud Rate Generator 0000h Reload Register FEBEh 5Fh reserved PECCO FECOh 60h PEC Channel 0 Control Register 0000h PECC1 FEC2h 61h PEC Channel 1 Control Register 0000h PECC2 FEC4h 62h PEC Channel 2 Control Register 0000h PECC3 FEC6h 63h PEC Channel 3 Control Register 0000h PECC4 FEC8h 64h PEC Channel 4 Control Register 0000h PECC5 FECAh 65h PEC Channel 5 Control Register 0000h PECC6 FECCh 66h PEC Channel 6 Control Register 0000h PECC7 FECEh 67h PEC Channel 7 Control Register 0000h FEDOh 68h reserved e e e e e e FEFEh 7Fh reserved Semiconductor Group B 6 SIEMENS SAB 80C166 Registers B 2 2 Bit Addressable Special Function Registers Name Physical 8 Bit Description Reset Address Address Value PO FFOOh 80h
42. Outputs external bus enabled L L L RD H H Porto 7 0 DATA FLOAT DATA FLOAT 15 8 DATA last ADDR H 16 8 DATA last ADDR H 16 8 FLOAT otherwise FLOAT otherwise Porti DATA last ADDR 16 16 DATA last ADDR 16 16 DATA otherwise DATA otherwise Port2 DATA AF DATA AF DATA AF DATA last AF Port3 DATA AF DATA AF DATA AF DATA last AF BHE P3 12 DATA LorH DATA L or H WR P3 13 DATA H DATA H CLKOUT P3 15 active active L if enabled Port4 DATA DATA non segm DATA non segm A16 A17 last ADDR otherwise last ADDR otherwise RSTOUT 1 1 1 1 L if IDLE or PWRON executed before EINIT otherwise H Siemens Aktiengesellschaft 12 4 System Programming 13 System Programming To aid in software development a number of features has been incorporated into the instruction set of the SAB 80C166 These include constructs for modularity loops and context switching In many cases commonly used instruction sequences have been simpli fied while providing greater flexibility The following sections cover programming features and implementations to fully utilize this instruction set 13 1 Instructions Provided as Subsets of Instructions In many cases instructions found in other microcontrollers are provided as subsets of more powerful instructions in the SAB 80C166 This allows the same functionality to be provided while decreasing the hardware
43. P3 0 within a port there is a direction control bit e g DP3 0 within the associated port direction control register e g DP3 In this figure those portions of port and direction registers which are not used by the CAPCOM unit for alternate functions are not shaded Semiconductor Group 8 3 SIEMENS Peripherals Ports amp Direction Control Data Registers Control Registers Interrupt Control Alternate Functions T Ts uM TOIN P3 0 CCOIO P2 15 P2 0 Port 3 Direction Control Register Port 3 Data RegisterDP2Port 2 Direction Control Register Port 2 Data Register CAPCOM Timer 0 Register CAPCOM Timer 0 Reload Register CAPCOM Timer 1 Register CAPCOM Timer 1 Reload Register CAPCOM Registers O 15 CAPCOM Timer 0 and Timer 1 Control Register CCMO CCM3 CAPCOM Mode Control Registers 0 3 TOIC CAPCOM Timer 0 Interrupt Control Register T1IC CAPCOM Timer 1 Interrupt Control Register CCOIC CC15IC CAPCOM Register 0 15 Interrupt Control Registers Figure 8 1 2 SFRs and Port Pins Associated with the CAPCOM Unit Semiconductor Group 8 4 SIEMENS Peripherals 8 1 1 Timers TO an
44. P3 7 T2IN Buffer P3 14 READY Alternate Data Input Synchronous READY Input y 0 2 4 5 6 7 14 Note This line only exists for Pin P3 14 READY Figure 10 9 Block Diagram of a Port 3 Pin with an Alternate Input Function Semiconductor Group 10 11 SIEMENS Parallel Ports When the on chip peripheral associated with such a pin is configured to use the alternate input function it reads the input latch which represents the state of the pin via the line labeled Alternate Data Input If an external device is driving the pin the direction of the pin must be set to input When no external device is connected to the pin one can set the direction to output and write to the port output latch to trigger the Alternate Data Input line 10 1 3 2 Port 3 Pins T3OUT TeOUT TXDO TXD1 WR CLKOUT These six of the seven Port 3 pins which have only an alternate output function associated also have an identical structure shown in figure 10 10 The Alternate Data Output line which is controlled by the respective peripheral unit is ANDed with the port output latch line When using these alternate functions the user must set the direction of the port line to output DP3 y 1 and must write a 1 into the port output latch Otherwise the pin is in its high impedance state when configured as input or the pin is stuck at 0 when writing a O into the port output latch When the alternate output functions are not used the Altern
45. Port 0 Register 0000h DPO FFO2h 81h Port 0 Direction Control Register 0000h P1 FFO4h 82h Port 1 Register 0000h DP1 FFO6h 83h Port 1 Direction Control Register 0000h P4 FFO8h 84h Port 4 Register 2 Bits 0000h DP4 FFOAh 85h Port 4 Direktion Control Register 2 Bits 0000h SYSCON FFOCh 86h CPU System Configuration Register OXXOh system configuration selected during reset MDC FFOEh 87h CPU Multiply Divide Control Register 0000h PSW FF10h 88h CPU Program Status Word 0000h FF12h 89h reserved e e e e e e FF1Ah 8Dh reserved ZERO FF1Ch 8Eh Constant Value 0 s Register read only 0000h ONES FF1Eh 8Fh Constant Value 1 s Register read only FFFFh FF20h 90h reserved e e e e e e FF3Eh 9Fh reserved Semiconductor Group SIEMENS SAB 80C166 Registers Name Physical 8 Bit Description Reset Address Address Value T2CON FF40h AOh GPT1 Timer 2 Control Register 0000h T3CON FF42h Ath GPT1 Timer 3 Control Register 0000h T4CON FF44h A2h GPT1 Timer 4 Control Register 0000h T5CON FF46h A3h GPT2 Timer 5 Control Register 0000h T6CON FF48h A4h GPT2 Timer 6 Control Register 0000h FF4Ah A5h reserved FF4Ch A6h reserved FF4Eh A7h reserved TO1CON FF50h A8h CAPCOM Timer 0 and Timer 1 Control 0000h CCMO FF52h A9h CAPCOM Mode Control Register 0 0000h CCM1 FF54h AAh CAPCOM Mode Control Register 1 0000h CCM2 FF56h ABh CAPCOM Mode Contr
46. ROM accesses stay globally disabled The ROMEN bit is modifiable only via hardware during reset For software it is always only readable If the SAB 80C166 is initialized to an external bus configuration mode other than the single chip mode Port 4 pins are used as an output for the most significant address pins A17 and A16 This aiternate function of Port 4 stays enabled until the SGTDIS bit in the SYSCON register is set to 1 If one of the two 16 bit Data Bus modes is selected during reset the function of the Byte High Enable pin BHE becomes also enabled and stays enabled until the BYTDIS bit in the SYSCON register is set to 1 This ensures that the External Bus Controller can properly access the initialization code in any case Many of the external bus transfer characteristics are controlled via the SYSCON register too Software programming of the SYSCON register allows the user to vary particular timing parameters in a wide range During reset all of the external bus timing parameters are initialized in a way that even very slow external memories can be accessed properly For more details on the programmable external bus timing parameters see section 9 6 9 2 Single Chip Mode The single chip mode must be selected whenever program execution shail start from the on chip program memory ROM If this mode has been selected once during reset inter nal ROM accesses stay globally enabled During reset the Instruction Pointer IP and the
47. Register CRIC Semiconductor Group 8 53 SIEMENS Peripherals 8 2 2 3 4 Using the Capture and Reload Mode Since the reload and the capture mode of register CAPREL can be configured individually by bits T5SC and T6SR one can set both bits to use the two modes of register CAPREL simultaneously This feature can be used to build a digital PLL configuration which generates an output frequency that is a multiple of the input frequency as described in the following Figure 8 2 31 shows a block diagram of this configuration The operation in this mode will be explained with an example T5UD Input 7 3 Interrupt Clock Auxiliary Timer T5 T5IR Request T5CLR Edge T5SC Select Request CAPREL Register aH 7 reour aA D31 T6OE Input Interrupt Clock Core Timer T6 T6IR Request Timers TO T1 Figure 8 2 31 Register CAPREL in Capture and Reload Mode Consider the case where one has to detect consecutive external events which may occur aperiodically but needs a finer resolution that means more ticks within the time between two external events For this purpose one measures the time between the external events using timer T5 and the CAPREL register Timer T5 runs in timer mode counting up TS5UD 0 with a frequency of for example fosc 64 The external events are applied to pin CAPIN When an external event occurs the timer T5 contents are latched into register CAPREL and timer T5 is cleared Semiconductor Group 8 54 SI
48. an overflow underflow of timer T6 in module GPT2 Semiconductor Group 3 5 SIEMENS System Description This provides a wide range of variation for the timer period and resolution and allows precise adjustment to the application specific requirements In addition an external count input for CAPCOM timer TO allows event scheduling for the capture compare registers relative to external events The capture compare register array contains 16 dual purpose capture compare registers each of which may be individually allocated to either CAPCOM timer TO or T1 and programmed for capture or compare function Each register has one port pin associated with it which serves as an input pin for triggering the capture function or as an output pin to indicate the occurrence of a compare event When a capture compare register has been selected for capture mode the current contents of the allocated timer will be latched captured into the capture compare register in response to an external event at the port pin which is associated with this register In addition a specific interrupt request for this capture compare register is generated Either a positive a negative or both a positive and a negative external signal transition at the pin can be selected as the triggering event The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers When a match occurs bet
49. and N 1 are indirect MOV instructions between two external memory locations When instructions N and N 1 are executed out of an external memory but all operands for instructions N 3 through N 1 are in internal memory then the PEC response time is the time to perform 1 word bus access plus 2 state times Once a request for PEC service has been acknowledged by the CPU the execution of the next instruction is delayed by 2 state times plus the additional time it might take to fetch the source operand from internal ROM or external memory and to write the desti nation operand over the external bus in an external program environment 7 2 7 External Interrupts Nineteen of the SAB 80C166 s port pins may be used as universal external interrupt input pins if their alternate function is not required in conjunction with an on chip peripheral These pins are listed in table 7 5 Table 7 5 Port Pins Configurable as External Interrupt Input Pins Port Pin Alternate Symbol Alternate Function P2 0 CCOIO CAPCOM Register 0 Capture Input Compare Output P2 15 CC15IO CAPCOM Register 15 Capture Input Compare Output P3 2 CAPIN CAPREL Register Capture Input P3 5 TAIN Timer 4 Count Gate Reload Capture Input P3 7 T21IN Timer 2 Count Gate Reload Capture Input For each of these pins either a positive a negative or both a positive and a negative external transition can be selected to cause an interrupt or PEC service request The edge selection is perfo
50. and PEC requests is completely programmable Each Source request can be assigned to a specific priority Once per instruction cycle all sour ces which require PEC or interrupt processing will contend for servicing Every requesting Source will try to exert its priority on the interrupt system A special mechanism called group priority has been implemented that allows the specification of the order of ser vice for simultaneous requests from a group of different sources on the same priority level At the end of the instruction cycle only one source with the highest priority will be left with control of the interrupt system This source will then be enabled for servicing if the priority of the request is higher than the current CPU priority in the PSW This arbitra tion which occurs once every instruction cycle is called a round of prioritization 7 2 1 interrupt System Register Description Interrupt processing is controlled globally by the PSW through a general interrupt enable bit IEN and the CPU priority field ILVL Additionaily the different interrupt sources are controlled individually by their specific interrupt control registers Thus the acceptance of requests by the CPU is determined by both the individual interrupt control registers and the PSW For PEC service one additional dedicated register and 2 pointers must be program med in order to specify the task which is to be performed by the respective PEC service channel
51. case only the lower four bits of reg are significant for physical address generation and thus it can be regarded as being identical to the address generation described for the Rb and Rw addressing modes bitoff Specifies direct access to any word in the bit addressable memory space bit off requires eight bits in the instruction format Depending on the specified bitoff range different base addresses are used to generate physical addres ses Short bitoff addresses from 00h to 7Fh use OFDOOh as a base address and thus they specify the 128 highest internal RAM word locations OFDOOh to OFDFEh Short bitoff addresses from80h to EFhuse OFFOOh as a base address and thus they specify the highest internal SFR word locations OFFOOh to OFFDEh Siemens Aktiengeselischaft 6 5 instruction Set Overview bitoff Short bitoff addresses from 80h to EFh use OFFOOh as a base address and thus they specify the highest internal SFR word locations OFFOOh to OFFDEh For short bitoff addresses from FOh to FFh only the lowest four bits and the contents of the CP register are used to generate the physical address of the selected word GPR bitaddr Any bit address is specified by a word address within the bit addressable me mory space see bitoff and by a bit position bitpos within that word Thus bitaddr requires twelve bits in the instruction format 6 2 22 Long Addressing Mode This addressing mode uses one of th
52. commonly used baud rates together with the required reload value The maximum baud rate that can be achieved for the asynchronous modes when using a 40 MHz oscillator is 625 KBaud Table 8 4 2 Asynchronous Modes Baud Rates Baud Rate fosc Reload Value 625 KBaud 40 MHz 0000h 19 2 KBaud 39 3216 MHz 001Fh 9600 Baud 39 3216 MHz 003Fh 4800 Baud 39 3216 MHz 007Fh 2400 Baud 39 3216 MHz OOFFh 1200 Baud 39 3216 MHz 01FFh 600 Baud 39 3216 MHz O3FFh 75 Baud 39 3216 MHz 1FFh Semiconductor Group 8 75 SIEMENS Peripherals 8 4 2 2 Synchronous Mode Baud Rates In the synchronous mode the baud rate generators provide 4 times the rate of the desired baud rate Therefore the underflow rate coming from the baud rate timers is additionally divided by four The maximum baud rate that can be achieved in synchronous operation when using a 40 MHz oscillator is 2 5 MBaud Generally the baud rates BsyncO and Bsync1 for the serial channels in synchronous operation are determined as follows T fosc fosc Bsyne m Fe ESOBRLSE i Bsynel 46 lt S1BRL gt 1 8 4 3 Serial Channels Interrupt Control Three bit addressable interrupt control registers are provided for each serial channel Registers SOTIC and S1TIC control the transmit interrupt registers SORIC and S1RIC control the receive interrupt and registers SOEIC and S1EIC control the error interrupt of serial channel ASCO and ASC1 respectively Each interrupt sourc
53. compare instructions embedded in loops One simply places the lowest negative number at the end of the specific table and specifies branching if neither this value nor the compared value have been found Otherwise the loop is terminated if either condition has been met One can then test which condition has occurred This method is described in detail in section 13 7 The third loop enhancement provides a more flexible solution than the Decrement and Skip on Zero instruction which is found in many other microcontrollers Through the use of Compare and Increment or Decrement instructions the user can make comparisons to any value This allows loop counters to cover any range This is particularly advantageous in table searching Saving of system state is automatically performed on the internal system stack avoiding the use of instructions to preserve state upon entry and exit of interrupt or trap routines Call instructions push the value of the IP on the system stack and require the same execution time as branch instructions Instructions have also been provided to support indirect branch and call instructions This supports implementation of multiple CASE statement branching in assembler macros and high level languages 2 1 5 Consistent and Optimized Instruction Formats To obtain optimum performance in a pipelined design an instruction set has been designed which incorporates concepts from Reduced Instruction Set Computers RISC These conc
54. converter ADST ADCH ADM ADBSY Conversion Interrupt Control Requests 10 Bit Result Reg ADDAT Converter Figure 8 3 1 A D Converter Block Diagram In the following figure 8 3 2 all SFRs and port pins are listed which are associated with the A D converter Semiconductor Group 8 55 SIEMENS Peripherals Data Control Interrupt Registers Registers Control mE Ee AN9 ANO P5 9 P5 0 P5 Port 5 Data Register ADDAT A D Converter Result Register ADCON A D Converter Control Register ADCIC A D Converter End of Conversion Interrupt Control Register ADEIC A D Converter Overrun Error Interrupt Control Register Figure 8 3 2 SFRs and Port Pins Associated with the A D Converter 8 3 1 Conversion Modes and Operation The analog input channels ANO through AN9 are alternate functions of port 5 which is a 10 bit input only port The port 5 lines may either be used as analog or digital inputs No special action is required by the user software to configure the port 5 lines as analog inputs The functions of the A D converter are controlled by the A D Converter Control Register ADCON shown in figure 8 3 3 This bit addressable register holds the bits which specify the analog channel the conversion mode and the status of the converter Bit ADST is used to start or stop the A D converter The busy flag ADBSY is a read only flag which indicates whether a conversion is in progress or not Bit field ADM determines the mode of
55. counter mode allowing it to be clocked by an external event Each capture compare register may be programmed individually for capture or compare function and each register may be allocated to either timer TO or T1 Each capture compare register has one pin of port 2 associated with it which serves as an input pin for the capture function or as an output pin for the compare function The capture function causes the current timer contents to be latched into the capture compare register based on an external event on its associated port 2 pin The compare function may cause an output signal transition on that port 2 pin whose associated capture compare register matches the current timer contents Specific interrupt requests are generated up on each capture compare event or upon timer overflow Figure 8 1 1 shows a block diagram of the CAPCOM unit Semiconductor Group 8 2 SIEMENS Peripherals Reload Reg System Clock E iaai APCOM Timer Toir H terrupt GPT2 Timer T6 16 Port 2 16 Bit iB Alternate Capture Capture Compare C151O P2 15 System Clock terrupt APCOM Timer i i GPT2 Timer T6 N Reload Reg Figure 8 1 1 CAPCOM Unit Block Diagram Register Overview From the programmer s point of view the term CAPCOM unit refers to a set of SFRs which are associated with this peripheral including the port pins which may be used for alternate input output functions As can be seen from figure 8 1 2 for each pin e g
56. data output by setting both P3 11 1 and DP3 11 1 or P3 9 1 and DP3 9 1 respectively 8 4 1 2 2 Synchronous Data Reception Data reception is initiated by setting bit SOREN 1 S1REN 1 If bit SOR 1 S1R 1 the data applied at pin RXDO RXD1 are clocked into the receive shift register synchronous to the clock which is output at pin TXDO TXD1 After the 8th bit has been shifted in the contents of the receive shift register are transferred to the receive data buffer SORBUF S1RBUF the receive interrupt request flag SORIR S1RIR is set the receiver enable bit SOREN S1REN is reset and serial data reception stops RXDO P3 11 or RXD1 P3 9 are configured as receive data input by setting DP3 11 0 or DP3 9 0 Once a reception is in progress on a serial channel resetting its receiver enable bit SOREN or S1REN to 0 by software has no effect Writing to its transmit buffer register while a reception is in progress has no effect on reception nor will it ever start a transmission In synchronous operation the low byte of the receive buffer register represents the received data while the high byte is always zero after synchronous reception If a previously received byte has not been read out of the receive buffer register at the time reception of the next byte is complete both the error interrupt request flag SOEIR or S1EIR and the overrun error status flag SOOE or S10OE will be set provided the overrun check has been enabled by bit SOOEN or S1O
57. describes how physical addresses are generated via indirect address pointers 1 Determination of the physical address of the word GPR which is used as indirect address pointer This address is calculated via the register bank base address specified by the CP register contents plus two times the specified short address Rw GPR Address CP 2 Short Address 2 In case of pre decrement signified by a leading minus sign the indirect address pointer is decremented by a data type dependent value A 1 for byte operations A 2 for word operations before the long 16 bit address is generated GPR Address GPR Address A optional step Siemens Aktiengeselischaft 6 7 3 4 Instruction Set Overview Then the long 16 bit address is determined by the contents of the indirect address pointer plus a selectable constant value in some cases Long Address GPR Address Constant Afterwards the physical 18 bit address is determined via the resulting long address and the corresponding DPP register contents as already described for the long mem addressing modes For more details about data paging see section 5 3 5 Long Address Long Address Bits 15 14 Bits 13 0 specifies x Physical Address DPP Number Page Offset Address x 0 3 In case of Post Increment signified by a subsequent plus sign the indirect address pointer value is additionally incremented by a data type dependent v
58. disabled which is signified by a 0 in the read only ROMEN bit This means that all memory accesses at addresses from 00000h to 01FFFh are made externaily If no external bus has been configured during reset internal ROM accesses are globally enabled which is signified by a 1 in the ROMEN bit In this so called Single Chip Mode the BTYP bit field stays modifiable to be capable of reconfiguring an external bus by software later If the ROMEN bit contains a 1 all memory accesses at addresses from 00000h to 01FFFh are made internally Note that the selection of a multiplexed external bus configuration automatically extends the Memory Tri State Time by one state time 1 state time 2 1 fosc For further information and for examples about the Single Chip Mode and the external bus configuration modes see section 9 1 Siemens Aktiengesellschaft 5 13 Central Processing Unit CPU Figure 5 4 System Configuration Register SYSCON FFOCh 86h Reset Values 0400h 0040h 0080h or 00COh 15 14 13 12 11 10 9 8 NE STKSZ RDYEN SGTDIS ROMEN BYTDIS CLKEN 7 5 4 3 2 1 0 6 zc Symbol Poston Function Cd MCTC SYSCON 3 0 Memory Cycle Time Control See Subsection 5 3 1 2 for details FRwoC SYSCON 4 Read Write Delay Control See Subsection 5 3 1 2 for details MTTC SYSCON 5 Memory Tri state Time Control See Subsection 5 3 1 2 for details BTYP SYSCON 7 6 External Bus Configuration Control r
59. does not have to develop write and test on his own in the on chip ROM Chapter 5 describes how the ROM mapping is selected Semiconductor Group D 4 SIEMENS SAB 80C166 83C166 Note Due to instruction pipelining any new ROM mapping will at the earliest become valid for the second instruction after the instruction which has changed the ROM mapping This always applies to data accesses For code accesses in particular any new ROM mapping will not become valid until the first absolute branch to the newly selected ROM area is actually performed When mapping the ROM however normally no instruction or data accesses should be made to the internal ROM otherwise unpredictable results may occur In order to avoid this problem one could either execute the instructions to map the ROM from external memory or from the internal RAM When mapping the ROM to segment 1 the address space of the 8 Kbyte ROM in the SAB 83C166 is 10000h to 11FFFh 64K to 72K 5 Selection of Bus Modes and ROM Mapping Since an additional fourth bus mode is implemented in the SAB 80C166 family two external bus control pins EBCO and EBC1 are not enough to select all the options after reset Thus an additional external pin is required For this purpose pin 7 which used to be an extra V pin will be assigned to this function This pin is named BUSACT Bus Active and specifies whether the SAB 80C166 is starting execution after reset from internal or external memory
60. double register compare mode for registers CC8 through CC15 1 0 1 Compare Mode 1 Pin toggles on each match several compare events per timer period registers CCO through CC7 have to be in this mode for double register compare operation 1 1 O0 Compare Mode 2 Interrupt only only one interrupt per timer period 1 1 1 Compare Mode 3 Pin set on match pin reset on timer overflow only one compare event per timer period As each of the 16 capture compare registers CCO through CC15 can be programmed to any of the available capture or compare modes these modes will be described in detail in the following only for one representative capture compare register which is referred to as CCx The index x may be substituted by any of the indices 0 through 15 Identically the Port 2 pin which is associated with register CCx will be referred to as CCxIO where CCxIO is the alternate function of P2 x The interrupt request flag which is associated with capture compare register CCx is referred to as CCxIR and the allocation and mode control bits for CCx are referred to as ACCx and CCMODx respectively Semiconductor Group 8 13 SIEMENS Peripherals 8 1 2 1 Capture Mode The contents of the timer TO or T1 according to the state of the allocation control bit ACCx are latched into the allocated capture register CCx in response to an external event The external event causing a capture can be programmed to be either a positive a ne
61. eae wha eta EA 14 3 Simulator Packages lt nodus uet edna eu bee SE ee ee bb ST 14 3 HOSS 052 cada E hie exit e dua rdiet oe Pita iM do 14 3 Appendix A Removed Siemens Aktiengesellschaft 4 Contents B 1 B 1 1 B 1 2 B 2 B 2 1 B 2 2 B 3 C C 1 C 1 D D 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D 9 D 10 D 11 Page SAB 80C166 Register 0 0 ccc cc eens B 1 CPU General Purpose Registers GPRs 0 0000 e eee B 2 Word Registers erreca tent cag wexreteed ered RAS MEER Deni epa B 2 Byte Hegistets 2 oes eRe eha wend Seaw biagheU eee Re eee OES B 3 Special Function Registers Ordered by Address B 4 Non Bit Addressable Special Function Registers 2000ee0e eee B 4 Bit Addressable Special Function Registers 00200c eee eens B 7 Special Function Registers Alphabetical Order B 12 Application Examples 0 0 ccc cee eee C 1 External Bus and Memory Configurations 2 055 C 1 Calculation of the user Selectable Bus Timing Parameters C 9 Addendum to User s Manual 09 90 D 1 GPT2 Timer T5 Clear Function 0 00 e eee eee D 3 Serial Port Baud Rates 00 0060 ee D 3 Implementation of a 16 18 Bit Address 8 Bit Data Non Multiplexed Bus Mode 0 000 D 4 Mapping the internal ROM address space
62. enabled state of the timers i e when both TOR and T1R are set to 1 In all modes both timer TO and timer T1 are always counting upward The current timer values are accessible by the CPU in timer registers TO and T1 which are both non bit addressable SFRs When TO or T1 are written by the CPU in the state immediately before a timer increment or reload is to be performed the CPU write operation has priority and the increment or reload is disabled to guarantee correct timer operation Semiconductor Group 8 6 Peripherals SIEMENS 8 1 1 1 Timer Mode Bits TOM and T1M in SFR TO1CON select between timer or counter mode for TO or T1 respectively In timer mode TOM 0 or T1M 0 the input clock for a timer is derived from the internal system clock divided by a programmable prescaler The different options for the prescaler are selected separately for TO and T1 by the bit fields TOI and T11 The input frequencies frg and fr4 for TO and T1 are determined as a function of the oscillator frequency as follows where TOI and lt T1I gt represent the contents of the bit fields TOI and Til fosc 1 6 o lt T1 I gt fosc Iis 1 6 3 9 lt T0l gt Tp When a timer overflows from FFFFh to 0000h it is reloaded with the value stored in its respective reload register TOREL or T1REL The reload values determine the periods pro and Pt between two consecutive overflows of TO and T1 as follows 16 216 lt TOREL gt 2 70 16 216
63. etu leq uM oio d fiera p ped 10 8 FOIT Se ood uet wiser cee s eU n e CoU uoa oaa ead anu durior t ii e ep uid 10 10 Port 3 Pins TOIN T2IN T3IN T4IN T3EUD CAPIN and READY 10 11 Port 3 Pins T3OUT TeOUT TXDO TXD1 WR CLKOUT 10 12 Pont 3 Pin BHE S ios dove ates ERA Bu ads e 10 13 Port 3 Pins RXDO and BXDT 4s see V RESRERLIW ER GU AUR x aoe 10 14 dre MC cr 10 15 POMS Coco coe Rl ssi uc Row e o dese Rs 10 16 System Reset o xus ores REA RU eases ease 11 1 RSTIN and RSTOUT Pins 2 0 20 2 eee essen 11 1 Reset Values for SAB 80C166 Registers 11 3 Watchdog Timer Operation after Reset 11 3 Ports and External Bus Configuration during Reset 11 4 Initialization Software Routine lleesss 11 4 Power Reduction Modes 0 00 0 cece enue 12 1 Power Down Mode 6 3 lues Gb pega eee tke x AR Eu RE 12 1 Ile MOGG sitet eaa Ser ate eae RARE A Erates irse eed 12 2 Status of Output Pins during Idle and Power Down Mode 12 3 Siemens Aktiengesellschaft 6 Contents 13 13 1 13 1 1 13 1 2 13 1 3 13 2 13 3 13 4 13 4 1 13 4 1 1 13 4 2 13 5 13 6 13 6 1 13 6 2 13 6 3 13 7 13 8 13 9 13 10 14 14 1 14 2 14 2 1 14 2 2 14 2 3 14 3 Appendix Page System Programming naaa aaae 13 1 Instructions Provided as Subsets of Instructions 13 1 Directly Substitutable Instruct
64. external fetch to location zero is made Siemens Aktiengesellschaft 11 4 System Reset When internal ROM access is enabled after resetin singie chip mode where bit ROMEN 1 in register SYSCON one can reconfigure the external bus options in the first instructions of the software initialization routine This is normally required whenever an external memory is used because the SYSCON register is initialized during reset to the slowest possible memory configuration To select the desired memory configuration and the re quired access parameters one simply moves a constant to the SYSCON register thus en suring that proper synchronization between the external memory and the SAB 80C166 is achieved The external bus configuration options are described in detail in section 9 1 To decrease the number of instructions required to initialize the SAB 80C166 each peri pheral is programmed to a default configuration upon reset but is disabled from opera tion These default configurations can be found in the descriptions of the individual peri pherals in chapter 8 During the software design phase portions of the internal memory space must be assi gned to register banks and system stack When selecting initialization values for the SP Stack Pointer and CP Context Pointer registers one must ensure that these registers are initialized before any GPR or stack operation is performed This includes interrupt processing which is disabled upon completi
65. from the new top of stack into GPR 0 External Memory Access Sequences The effect described here will only become noticeable if one looks at the external memory access sequences on the external bus i e by means of a Logic Analyzer Dif ferent pipeline stages can simultaneously put a request on the External Bus Controller EBC Since the predefined priority of external memory accesses is as follows 1st Write Data 2nd Fetch Code 3rd Read Data the sequence of instructions processed by the CPU may diverge from the sequence of the corresponding external memory accesses performed by the EBC Siemens Aktiengeseilschaft 5 6 Central Processing Unit CPU e Timing As already described instruction pipelining reduces the average instruction processing time in a wide scale from four to one machine cycles mostly However there are some rare cases where a particular pipeline situation causes a single instruction processing time to be extended either by a half or by one machine cycle Although this additional time represents only a tiny part of the total program execution time it might be of interest to avoid these pipeline caused time delays in time critical program modules Besides a general execution time description section 5 2 provides some hints how one can optimize time critical program parts with regard to such pipeline caused timing particularities 5 2 Instruction State Times Basically the time to execute an instruction d
66. it reads an operand in the internal ROM or if it is executed out of the internal RAM Similar to the interrupt response time the response time for a PEC data transfer request can be defined as the time required from the moment an interrupt request flag has been set until the PEC data transfer is started In general the PEC response time in the SAB 80C166 is 2 instruction cycles It depends on the instructions N 3 through N which are in the pipeline at the moment the request flag is set and on the following instruction N 1 This is explained by the pipeline diagram in figure 7 11 Siemens Aktiengesellschaft 7 22 Interrupt and Trap Functions Figure 7 11 Pipeline Diagram for PEC Response Time PEC Response Time PEC is equivalent to MOV B DSTPx SRCPx or MOV B DSTPx SRCPx or MOV B DSTPx SRCPx Once per instruction cycle ail enabled interrupt sources whose interrupt request flags have been set during the previous cycle compete for service in a round of prioritization In the next cycle the PEC data transfer is started when the winning source was programmed for PEC service and the source s interrupt request flag is reset to 0 Note that when instruction N reads any of the PEC control registers PECCO through PECC7 while a PEC request wins the current round of prioritization this round is repeated and the PEC data transfer is started one cycle later The minimum PEC response time is 3 states 150 ns 40 MHz T
67. location FAOOh the data actually is pushed at the top of the allocated stack space e g location FBFEh where 256 words have been allocated for the stack Thus the internal access pointer wraps around the internal stack as specified by the stack size in the SYSCON register The stack pointer always points to the virtual location in the ex ternal memory The boundary pointers STKOV and STKUN also point to the external virtual stack locations Siemens Aktiengesellschaft 13 5 System Programming The following procedure is required upon initialization of the controller 1 Specify in the SYSCON register the size of the internal RAM to be dedicated to the system stack 2 Initialize two pointers in the internal data memory which specify the upper and lower boundary of the external stack These values are then tested in the stack underflow and overflow trap routines 3 Initialize the stack underflow pointer to the bottom of the external stack and the overflow pointer to the value of the underflow pointer minus the size of the internal stack pius six words for the reserved space Following this procedure the internal stack will fill until the overflow pointer is reached After entry to the overflow trap procedure the top of the stack will be copied out to the external RAM The internal pointers will then be modified to reflect the newly allocated space After exiting from the trap procedure the internal stack will wrap around to the
68. mode is provided for accesses to a byte organized external memory The eight least significant bits of the address and the data byte are time multiplexed on the lower portion of the word wide external bus For this mode Port 0 is used as interface to the multi plexed external address data bus As long as memory segmentation is not disabled Port 4 is additionally used as an output for the two most significant bits of the required 18 bit addresses 16 18 Bit Address 16 Bit Data Multiplexed Bus This mode is provided for accesses to a word organized external memory The sixteen least significant address bits and the data word are time multiplexed on the word wide external bus For this mode Port 0 is used as interface to the multiplexed external address data bus As long as memory segmentation is not disabled Port 4 is additionally used as an output for the two most significant bits of the required 18 bit addresses 16 18 Bit Address 16 Bit Data Non Multipiexed Bus This mode is also provided for accesses to a word organized external memory However two separate buses are used for the sixteen least significant address bits and the data word Thus addresses and data do not have to be time multiplexed For this mode Port O is used as an interface to the external data bus and Port 1 is used as an interface to the external address bus As long as memory segmentation is not disabled Port 4 is additionally used as an output for the two most signif
69. muitiply or divide instruction was interrupted BSET SAVED Save indication of stored state PUSH MDH Save previous MD contents PUSH MDL on system stack Note The above save sequence and the restore sequence after COPYL are only required if the current routine could have interrupted a previous routine which contained a MUL or DIV instruction The MDC register is also saved because it is possible that a previous routine s Multiply or Divide instruction was interrupted while in progress In this case the information about how to restart the instruction is contained in this register The MDC register must be cleared to be correctly initialized for a subsequent multiplication or division Siemens Aktiengesellschaft 13 2 System Programming START MULUR 1 R2 Multiply 16 16 unsigned Sets MDRIV JNB V COPYL Test for only 16 bit result MOV R3 MDH Move high portion of MD COPYL MOV R4 MDL Move low portion of MD Clears MDRIV RESTORE JNB SAVED DONE Test if MD registers were saved POP MDL Restore registers POP MDH POP MDC DONE any instruction To perform division the user must first move the dividend into the MD register If a 16 16 bit division is specified only the low portion of the MD register must be loaded The result is also stored in the MD register The low portion of the MD register MDL contains the integer result of the division while the high portion of the MD register MDH contains the remainder
70. of a machine cycle 25 ns at fose 40 MHz Siemens Aktiengesellschaft 9 18 External Bus Interface Table 9 5 RWDC Encoding of the Read Write Signal Delay ALE RD WR Delays Enabled Disabled These programmable Read Write Signal Delays can be specified for ail of the external bus configuration modes 9 8 External Memory Access via the Data Ready Signal An optional Data Ready function can be used to allow an external device to determine the duration of an external memory access If the Data Ready function is enabled the duration of all external accesses is not determined by the contents of the MCTC bit field in the SYSCON register as described in section 9 7 1 but by the state of the READY input pin Note that the READY input pin must be correctly activated for every external memory access if the Data Ready function has been enabled Otherwise the CPU would be halted until a reset occurs No time out protection other than a Watchdog Timer overflow is provided The Data Ready function can be enabled by setting the RDYEN bit in the SYSCON register to 1 see section 5 3 1 4 Siemens Aktiengesellschaft 9 19 SIEMENS Parallel Ports 10 Parallel Ports The SAB 80C166 provides 76 parallel I O lines organized into four 16 bit I O ports Port 0 through 3 one 2 bit I O port Port 4 and one 10 bit input port Port 5 All port lines are bit addressable and all lines of Port 0 through 4 are individually bit wise progr
71. of different external bus and memory con figurations with different types of memories Note that internal memory access time are not extended by external waitstates Examples tables and formulas showing the calculation of the user selectable bus characteristics can be found in the appendix section C 2 Siemens Aktiengesellschaft 9 12 External Bus Interface 9 7 31 Programmable Memory Cycle Time The SAB 80C166 allows the user to adjust the controller s Memory Access Cycle Time to the Memory Cycle Time of the external memory being used The Memory Cycle Time is the total time required to perform a memory access It represents the period of time from the moment when the controller puts an address on the bus for the first time until the next external memory access can be started at the earliest As shown in figure 9 9 the Memory Cycle Time determines how fast the memory can be accessed in general Figure 9 9 Memory Cycle Time ___ Memory Cycle Time ALE N WR If an external memory is too slow the controller must slow down in order to allow the memory to keep pace The SAB 80C166 can be slowed down for external memory accesses by introducing wait states during the access During these Memory Cycle Time wait states the CPU is idle Figure 9 10 shows when Memory Cycle Time wait states are introduced during the memory access Siemens Aktiengesellschaft 9 13 External Bus In
72. of the same or lower classes Siemens Aktiengeselischaft 7 16 interrupt and Trap Functions 7 24 interrupt Procedure Once an interrupt has been selected for servicing the state of the task currently being executed by the CPU is saved on the system stack To ensure correct return to the loca tion where the task had been interrupted the information stored on the stack also depends on whether segmentation is currently enabled as indicated by the SGTDIS bit in the SYSCON register 7 2 4 1 Interrupt Procedure with Segmentation Disabled If segmentation is disabled the contents of the PSW and the contents of the IP are pushed on the system stack The interrupt source s priority level is then copied into the CPU Priority field of the PSW If a multiply or divide operation was in progress when the interrupt was acknowledged the MULIP bit in the PSW of the interrupt service routine is set to 1 The Interrupt Request Flag of the source that caused the interrupt is cleared The CPU then passes control to the source s interrupt vector The pushed IP contains the address of the instruction to which execution will return after the interrupt service routine is completed Upon execution of the RETI instruction Return from Interrupt the information that was pushed on the stack is popped in reverse order In this way the status of the interrupted routine is restored Figure 7 7 shows how the system stack is affected when an interrupt is ackno
73. programmed in register WDTCON The period pWDT between servicing the Watchdog Timer and the next overflow can be determined as follows 22 WDTIN 6 516 lt WDTREL gt 28 Pwot fosc Table 8 5 1 shows the possible ranges for the watchdog time which can be achieved using a 40 MHz oscillator Note that some numbers are rounded to 3 significant digits For safety reasons the user is advised to rewrite WDTREL each time before the Watchdog Timer is serviced Table 8 5 1 Watchdog Time Ranges WDTREL Prescaler for fosc 4 WDTIN 0 256 WDTIN 1 FFh 25 6 us 1 6 ms 00h 6 55 ms 419 ms Semiconductor Group 8 80 External Bus Interface 9 External Bus Interface The SAB 80C166 has been architected to be placed in a number of different applications and system designs In order to meet the needs of designs where more memory is re quired than is provided on the chip a number of external bus configuration modes are supported These are listed below Single Chip Mode No external bus is configured in this mode Selecting this mode during reset implies that program execution starts from the internal ROM No external memory can be accessed as long as the SAB 80C166 is in this mode However the single chip mode can be left to enter any of the following external bus configuration modes by simply reprogramming the System Configuration SYSCON register 16 18 Bit Address 8 Bit Data Multiplexed Bus This
74. set to FFh the continuous transfer mode is selec ted for the respective PEC channel In this mode the COUNT value is not decremented which means that an unlimited number of transfers will be performed by this PEC chan nel The operation of a PEC Service Channel programmed for continuous transfer can only be terminated either by disabling PEC service or by reprogramming its PEC Chan nel Counter Control register For the different possibilities of disabling interrupt sources see section 7 2 3 1 7 2 2 2 PEC Source and Destination Pointers Eight pairs of word wide pointers are associated with the 8 PEC Service Channels Each pair is directly assigned to one specific PEC channel Each of these pairs of pointers con sists of a Source Pointer which contains the source address of the PEC data transfer and a Destination Pointer which contains the respective destination address These pointers share the top 16 word locations byte addresses FDEOh through FDFFh in the internal RAM If no PEC service is required for a specific PEC channel the loca tions of its pointers can be used for general data storage Siemens Aktiengesellschaft 7 12 interrupt and Trap Functions Note If word data transfer is selected for a specific PEC channel i e bit BWT 0 the respective Source and Destination Pointers must both contain a valid word address which points to an even byte boundary Otherwise the Illegal Word Access trap will be invoked when this ch
75. state through an internal reset procedure When a reset is initiated pending inter nal hold states are cancelled and external memory access cycles are aborted regardless of an unreturned READY signal Write operations to the internal RAM however are completed before the internal reset procedure begins After this internal reset has been completed in case of a software or watchdog timer triggered reset or after deassertion of the signal at pin RSTIN in case of a hardware reset the microcontroller will start program execution from memory location 0000h in code segment zero Here one would normaily place a branch instruction to the start of a software initialization routine for the application specific configuration of peripherals and CPU Special Function Registers 11 1 RSTIN and RSTOUT Pins Two pins RSTIN Reset In and RSTOUT Reset Out are dedicated to the system re set function of the SAB 80C166 The RSTIN pin is used for resetting the microcontroller through an external hardware reset signal Whenever a logical low level is asserted on this pin for a specified period of time an internal reset is performed In order to obtain an automatic power on reset the RSTIN pin can be connected to an external capacitor since this pin already has an internal pullup resistor connected to Vcc see figure 11 1a The reset signal on RSTIN first passes a Schmitt Trigger in order to obtain a fast transition The minimum duration of the power
76. the in ternal instruction pipeline a new CP value is not yet usable for GPR address calculations of the instruction immediately following the instruction updating the CP register Note that bit 10 is always forced to the inverse state of bit 9 by hardware For soft ware bit 10 can only be read but not directly be written Siemens Aktiengesellschaft 5 27 Central Processing Unit CPU The Switch Context SCXT instruction allows saving the contents of the CP register on the stack and updating the CP with a new vaiue in just one machine cycle The organiza tion of the GPRs within the internal RAM is described in section 4 3 2 For detailed infor mation about the different addressing modes mentioned in the following see section 6 2 Figure 5 12 Register Bank Selection via the CP register Internal RAM CP 30 CP 28 Context Pointer XJ eo BIS R4 O O RIS R2 O RI RIO INN MD R8 MES RENE R6 p R5 ERE RENI R a i a a a RO The CP register is implicitly used for address calculations by different addressing modes as follows 5 3 6 1 Implicit CP Use with Short 4 Bit GPR Addresses When a short 4 bit GPR address mnemonic Rw or Rb is used the four bits specify an address relative to the memory location specified by the contents of the CP register Siemens Aktiengesellschaft 5 28 Central Processing Unit CPU Depending on whether a relative word Rw or by
77. top of the internal stack and continue to grow until the new value of the stack overflow pointer is reached 13 4 2 User Stacks User stacks provide the ability to create task specific data stacks and to off load data from the system stack The user may push both bytes and words onto a user stack but is responsible for using the appropriate instructions when popping data from the specific user stack No hardware detection of overflow or underflow of a user stack is provided The following addressing modes allow implementation of user stacks Rb Rw or Rw Rw Post increment Indirect Addressing Used to pop one byte or word from a user stack This mode is only available for MOV instructions and can specify any GPR as the user stack pointer Rw Rb or Rw Rw Pre decrement Indirect Addressing Used to push one byte or word onto a user stack This mode is only available for MOV instructions and can specify any GPR as the user stack pointer Rb Rw or Rw Rw Post increment Index Register Indirect Addressing Used to pop one byte or word from a user stack This mode is available to most instructions but only GPRs RO R3 can be specified as the user stack pointer Siemens Aktiengesellschaft 13 6 System Programming 13 5 Register Banking Register banking provides the user with an extremely fast method of switching user context A single machine cycle instruction saves the old bank and enters a new register ban
78. unpredictable results may occur When the external bus modes are again disabled the contents of the direction register last written by the user become active 10 1 2 Port 2 All of the 16 pins of Port 2 P2 may be used for the alternate input output functions of the CAPCOM unit They serve as an input line for the capture function or as an output line for the compare functions The alternate symbols CCOIO through CC15IO have been assigned to Port 2 in addition to the standard symbols P2 0 through P2 15 in order to reflect its alternate functions Figure 10 8 shows a block diagram of a Port 2 pin When a Port 2 line is used as a capture input the state of the input latch which represents the state of the port pin is directed to the CAPCOM unit via the line Alternate Pin Data Input The user software must set the direction of the pin to input if an external capture Semiconductor Group 10 8 SIEMENS Parallel Ports Write DP2 y Direction Latch DP2 y Read DP2 y Alternate Data Output Write Port P2 y Compare Trigger Alternate Latch Data Input Alternate Pin Data Input Figure 10 8 Block Diagram of a Port 2 Pin trigger signal is used If the direction is set to output the state of the port output latch will be read since the pin represents the state of the output latch This can be used to trigger a capture event through software by setting or clearing the port latch Note thatinthe output configuration no external dev
79. which is predeter mined by hardware This allows direct identification of the source that caused the re quest The only exceptions are the class B hardware traps which ail share the same vector address The status flags in the Trap Flag Register TFR can then be used to determine the type of the trap see section 7 3 for more details For the special software TRAP in struction the vector address is specified by the operand field of the instruction which is a seven bit trap number The reserved vector locations of the SAB 80C166 s memory space form a jump table Here one can place the appropriate jump instructions to the memory locations where the interrupt or trap service routines will actually start The entries to the jump table are lo cated at the lowest addresses in code segment zero of the memory space Jump table entries have a distance of 4 bytes between consecutive entries except for the reset vec tor and the hardware trap vectors where the distance is 8 or 16 bytes The following table 7 1 contains all sources that are capable of requesting interrupt or PEC service in the SAB 80C166 including the associated interrupt vectors and trap num bers Also listed are the mnemonics of the affected Interrupt Request flags and their corresponding Interrupt Enable flags The mnemonics are composed of apartthat specifies the respective source followed by a part that specifies their function IR Interrupt Re quest flag IE Interrupt Enable
80. 0 Figure 7 2 Address Select Register ADDRSEL1 Symbol Position Function RGSZ ADDRSEL1 2 0 BUSCON1 Address Range Selection See description for details RGSAD ADDRSEL1 9 3 BUSCON1 Address Range Start Address Selection See description for details ADDRSEL1 reserved 15 10 Segment 0 FFF External Memory Accessed via SYSCON Parameters C000 Ext Memory Peripheral 16 K Range Accessed via BUSCON1 Start Address Parameters e g 8000H 32 K 8 Bit Data Multiplexed Bus 2 8000 Wait States READY enabled External Memory Accessed via SYSCON Parameters 4000 e g 16 Bit Data Non Multiplexed Bus No Wait States 0000 Figure 7 3 Example for Partitioning of the External Address Range via SYSCON and BUSCON1 Non Segmented Mode Semiconductor Group D 20 SIEMENS SAB 80C166 83C166 _ A DATA OUT ADDRESS i f ADDRESS 4 1 LI Non Multiplexed Bus Access 1 State Hold Multiplexed Bus Access Figure 8 1 Switching from Non Multiplexed Bus to Multiplexed Bus Semiconductor Group D 21 DATA OUT ADDRESS ADDRESS SIEMENS SAB 80C166 83C166 CLKOUT ALE Port 0 RD WR 1 Normal Memory Cycle Lengthened Memory Cycle Multiplexed Bus Multiplexed Bus Figure 9 1 Timing with ALE Lengthening Multiplexed Bus Semiconductor Group D 22 SIEMENS SAB 80C166 83C166 PSW FF10h 88h Reset Value 0000h 15 14 13 12 1
81. 1 10 9 8 7 6 5 4 3 2 1 0 Figure 11 1 Processor Status Word Register PSW Symbol Position Function N PSW 0 This bit represents a negative result from the ALU C PSW 1 This bit represents a carry result from the ALU V PSW 2 This bit represents an overflow result from the ALU Z PSW 3 This bit represents a zero result from the ALU E PSW 4 This bit supports table search operation by signifying the end of a table MULIP PSW 5 This bit specifies that a multiply divide operation was interrupted before completion MULIP 0 No multiply divide operation in progress MULIP 1 Multiply divide operation in progress USRO PSW 6 This bit is provided as the user s general purpose flag HLDEN PSW 10 Bus Arbitration HOLD HLDA BREQ Enable Bit See description chapter 11 for details HLDEN 0 HOLD HLDA BREQ desabled HLDEN 1 HOLD HLDA BREQ enabled Pins P2 13 P2 15 used for these functions IEN PSW 11 This bit globally enables or disables acceptance of interrupts IEN 20 CPU Interrupts disabled IEN 1 CPU Interrupts enabled ILVL PSW 15 12 This field represents the current interrupt level being serviced by the CPU Upon entry into an interrupt routine the four bits of the priority level of the acknowledged interrupt are copied into this field By modifying this field the priority level of the current CPU task can be programmed reserved Semiconductor Group D 23 S
82. 11 can not be fetched over the external bus until all write fetch and read requests of preceding instruc tions in the pipeline are terminated Under the same conditions but with the interrupt vector location in the internal ROM the interrupt response time is 7 word bus accesses plus 2 states because fetching of 1 from the internal ROM can start earlier Note that these worst case situations are rather untypical and occur only when instructions N and N 1 are indirect MOV instructions between two external memory locations When instruc tions N through N 2 are executed out of an external memory and the interrupt vector location is also in external memory but all operands for instructions N 3 through N are in internal memory then the interrupt response time is the time to perform 3 word bus accesses Under the same conditions but with the interrupt vector location in the internal ROM the interrupt response time is 1 word bus access plus 4 states After an interrupt service routine has been terminated through execution of the RETI instruction and if further interrupts are pending the next interrupt service routine will not be entered until at least two instruction cycles have been executed in the program sec tion returned to In most cases two instructions will be executed during this time Only one instruction will typically be executed if the first instruction following the RETI instruc tion is a branch instruction without cache hit or if
83. 21 Timer Counter x counts down TxCON 15 8 reserved x 2 4 The operating modes for the auxiliary timers T2 and T4 are independently selectable by bit fields T2M and T4M The available options for both timers are listed in table 8 2 5 and will be discussed in detail in the following subsections Semiconductor Group 8 34 SIEMENS Peripherals Table 8 2 5 GPT1 Auxiliary Timer T2 and T4 Mode Control T2M T4M Mode 2 1 0 0 0 0 Timer 0 0 1 Counter 0 1 0 Gated Timer gate is active low 0 1 1 Gated Timer gate is active high 1 0 0 Reload 1 0 1 Capture 1 1 X reserved no function selected In all of the counting modes of operation the auxiliary timers can count up or down depending on the state of their control bits T2UD and T4UD They can be started or stopped through their run bits T2R and T4R In gated timer mode the respective timer will only run if T2R 1 or T4R 1 and the gate is active 8 2 1 2 1 Timer Mode The operation of the auxiliary timers in this mode is identical to that of the core timer T3 Timer mode is selected for the auxiliary timers T2 or T4 by setting the mode control field T2M or TAM in the respective control register T2CON or T4CON to 000b The input frequencies fr and fr to T2 and T4 are determined by the contents of the timer input selection fields T2l and T4I as follows f f Byz 22990 fi OSC 16 o T2l 16 o lt T4l gt
84. 3 Internal RAM A dual port 512 by 16 bit internal RAM provides fast access to General Purpose Registers GPRs user data and system stack A unique decoding scheme provides flexible user register banks in the internal memory while optimizing the remaining RAM for user data Hardware detection of the selected memory space is placed at the internal memory decoders and allows the user to specify any address directly or indirectly and obtain the desired data without using temporary registers or special instructions 2 2 4 Internal ROM An optional large internal ROM of 8 Kbytes is provided for both code and constant data storage This memory area is connected to the CPU via a 32 bit wide bus Thus an entire double word instruction can be fetched in just one machine cycle Program execution from the on chip ROM is the fastest of all possible alternatives Semiconductor Group 2 6 SIEMENS Architectural Overview 2 2 5 Clock Generator The on chip clock generator contains a prescaler which divides the external clock frequency by 2 Thus the internal clock frequency is half the external clock frequency i e fosc 40 MHz internal clock frequency 20 MHz Two separated clocks are generated for the CPU and the peripheral part of the chip While the CPU clock is stopped during waitstates or during the idle mode the peripheral clock keeps running Both clocks are switched off when the power down mode is entered 2 2 6 Peripherals and Ports The SAB
85. 3IN shows a low level A high level at this pins tops the timer If T3M 0 1 pin T3IN must have a high level in order to enable the timertorun In addition the timer can be turned on or off by software using bit T3R The timer will only run if T3R 1 and the gate is active it will stop if either T3R 0 orthe gate isin active Note that a transition of the gate signal at pin T3IN does not cause an interrupt request Semiconductor Group 8 31 SIEMENS Peripherals Interrupt Request Figure 8 2 6 Block Diagram of Core Timer T3 in Gated Timer Mode 8 2 1 1 3 Counter Mode Counter mode is selected for T3 by programming bit field T3M in register T3CON to 01b In counter mode timer T3 is clocked by a transition at the external input pin T3IN which is an alternate function of P3 6 The event causing an increment or decrement of the timer can be a positive a negative or both a positive and a negative transition at this pin The options are selected by bit field T3l in control register T3CON as shown in table 8 2 4 For counter operation pin T3IN P3 6 must be configured as input by setting direction control bit DP3 6 to 0 The maximum input frequency which is allowed in counter mode is fosc 16 1 25 MHz fosc 40 MHz To ensure that a transition of the count input signal which is applied to T3IN is correctly recognized its level should be held for at least 8 state times before it changes Figure 8 2 7 shows a block diagram of the core ti
86. 4 Double Register Mode Compare Register Pairs Register Pair Associated Pin Bank 1 Bank 2 CCO CC8 CCOIO CC1 CC9 CC1IO CC2 CC10 CC2lO CC3 CC11 CC3IO CC4 CC12 CC4IO CC5 CC13 CC4IO0 CC6 CC14 CC6lO CC7 CC15 CC7IO The double register mode can be programmed individually for each register pair In order to enable the double register mode a bank 1 register CCO through CC7 must be programmed for compare mode 1 and the corresponding bank 2 register CC8 through CC15 must be programmed for compare mode O If the corresponding bank 1 compare register is disabled or programmed for a mode other than mode 1 the bank 2 register will operate in compare mode 0 interrupt only mode as described in section 8 1 2 2 1 In the following a bank 2 register programmed to compare mode 0 will be referred to as CCz while the corresponding bank 1 register programmed to compare mode 1 will be referred to as CCx When a match is detected for one of the two registers in a register pair CCx or CCz the associated interrupt request flag CCxIR or CCzIR is set to 1 and pin CCxlO corresponding to bank 1 register CCx is toggled The interrupt generated always corresponds to the register that caused the match NOTE If a match occurs simultaneously for both register CCx and register CCz of the register pair pin CCxIO will be toggled only once but two separate compare interrupt requests will be generated one for vector CCxINT and one for vector CCzINT
87. 8 2 1 Block Diagram of GPT1 System mae Interrupt Requests mods Interrupt and CAPREL Register and ale nut Output utput Control Control External To Capture CAPCOM input Timers TO T1 Core Timer T6 Figure 8 2 2 Block Diagram of GPT2 Semiconductor Group 8 25 SIEMENS Peripherals System Auxiliary Timer T5 uo Interrupt Requests MoR Interrupt and CAPREL Register and di PUE Output utpu Control Control External To Capture CAPCOM mee Timers TO T1 Core Timer T6 Figure 8 2 2 Block Diagram of GPT2 8 2 1 GPT1 Block All three timers T2 T3 T4 of block GPT1 can run in 3 basic modes which are timer gated timer and counter mode and all timers can either count up or down Each timer has an alternate input function pin on port 3 associated with it which serves as the gate control in gated timer mode or as the count input in counter mode As a specific feature of the core timer T3 its count direction may be dynamically altered by a signal at an external input pin and each overflow underflow may be indicated on an alternate output function pin The auxiliary timers T2 and T4 may additionally be concatenated with the core timer or used as capture or reload registers for the core timer The current contents of each timer can be read or modified by the CPU by accessing the corresponding timer registers T2 T3 or T4 which are located in the non bit addressable SFR space When any of the timer registers is written by the
88. 82h Cih CAPCOM Register 5 Interrupt Control Register 0000h CC6IC FF84h C2h CAPCOM Register 6 Interrupt Control Register 0000h CC7IC FF86h C3h CAPCOM Register 7 Interrupt Control Register 0000h CC8IC FF88h C4h CAPCOM Register 8 Interrupt Control Register 0000h CC9IC FF8Ah C5h CAPCOM Register 9 Interrupt Control Register 0000h CC10IC FF8Ch C6h CAPCOM Register 10 Interrupt Control 0000h Register CC11IC FF8Eh C7h CAPCOM Register 11 Interrupt Control 0000h Register CC12IC FF90h C8h CAPCOM Register 12 Interrupt Control 0000h Register CC13IC FF92h C9h CAPCOM Register 13 Interrupt Control 0000h Register CC14IC FF94h CAh CAPCOM Register 14 Interrupt Control 0000h Register CC15IC FF96h CBh CAPCOM Register 15 Interrupt Control 0000h Register Semiconductor Group B 9 SIEMENS SAB 80C166 Registers Name Physical 8 Bit Description Reset Address Address Value ADCIC FF98h CCh A D Converter End of Conversion Interrupt 0000h Control Register ADEIC FF9Ah CDh A D Converter Overrun Error Interrupt Control 0000h TOIC FF9Ch CEh CAPCOM Timer 0 Interrupt Control Register 0000h T1IC FF9Eh CFh CAPCOM Timer 1 Interrupt Control Register 0000h ADCON FFAOh DOh A D Converter Control Register 0000h P5 FFA2h D1h Port 5 Register 10 Bits read only XXXXh FFA4h D2h reserved e e e e e e FFAAh D5h reserved TFR FFACh D6h Trap Flag Register 0000h WDTCON FFAEh D7h Watchdog Timer Control Regis
89. A detailed description of each single instruction including its operand data type condition flag settings addressing modes length number of bytes and object code format can be found in appendix A 6 1 Summary of Instruction Classes This section contains a summary of the SAB 80C166 s instruction set subdivided in instruc tion classes Mnemonic instruction names refer to the corresponding description in appen dix A where one can gain more detailed information 6 1 1 Arithmetic Instructions Addition of two words or bytes ADO ADDB Addition with Carry of two words or bytes ADDC ADDCB Subtraction of two words or bytes SUB SUBB Subtraction with Carry of two words or bytes SUBC SUBCB 16 16 bit signed or unsigned multiplication MUL MULU 16 16 bit signed or unsigned division DIV DIVU e 32 16 bit signed or unsigned division DIVL DIVLU e 1 s complement of a word or byte CPL CPLB 2 s complement negation of a word or byte NEG NEGB 6 1 2 Logical Instructions Bitwise ANDing of two words or bytes AND ANDB Bitwise ORing of two words or bytes OR ORB Bitwise XORing of two words or bytes XOR XORB Siemens Aktiengesellschaft 6 1 6 1 3 6 1 4 6 1 5 6 1 6 Siemens Aktiengesellschaft Boolean Bit Manipulation instructions Manipulation of a maskable bit field in either the high or the low byte of a word Setting of a bit Clearing of a bit Movement of a bit Movement of a negat
90. Addresses 16 bit Data Multiplexed Bus External RAM ROM Byte Organized Memories Semiconductor Group C 4 SIEMENS Application Examples 800166 P115 P4 0 A16 P43 A17 RD P3 12 BHE Fe MCS 00289 EPROM 16K 16 Oh 7FFFh 8000h 9FFFh Figure C 3 16 bit Addresses 16 bit Data Multiplexed Bus External RAM ROM Word Organized Memories Semiconductor Group C 5 SIEMENS Application Examples P4 0 A16 P41 A17 RO P312 BHE P3 13 WR P314 READY P315 CLKOUT Address Range Oh 7FFFh 8000h 9FFFh MCS00290 Memory Config Figure C 4 16 bit Addresses 16 bit Data Non Multiplexed Buses External RAM ROM Byte Organized Memories Semiconductor Group C 6 SIEMENS Application Examples P07 P0 8 SAB 800166 PL 0 A16 PLALATI 7 P312 BHE P3 13 WR P314 READY 82 P315 CLKOUT MCS00291 EPROM 16K 16 Oh 7FFFh 8000h 9FFFh Figure C 5 16 bit Addresses 16 bit Data Non Multiplexed Buses External RAM ROM Word Organized Memories Semiconductor Group C 7 SIEMENS Application Examples EBCO EBC ALEHO P0 0 I poa 33 08 SAB 80C166 1 2 4 s OOD MCS00292 EPROM 16K 16 Oh 7FFFh RAM 8000h 9FFFh Figure C 6 16 bit Addresses 16 bit Data Non Multiplexed Buses External RAM ROM Word and Byte Organized Memories Semiconductor Group C 8 SIEMENS Application Examples C 2 Calculation of the User Selectable Bus Tim
91. Auxiliary Timer in Reload Mode Triggered by T3OTL Note Although it is possible the user should not program both of the auxiliary timers to reload the core timer on the same trigger event since in this case both of the reload registers would try to reload the core timer at the same time In this case the contents of T4 are loaded into the core timer T3 The reload mode triggered by T3OTL can be used in a number of different configurations Depending on the selection of the active transition the following functions can be performed If both a positive and a negative transition of TSOTL is selected to trigger a reload the core timer will be reloaded with the contents of the auxiliary timer each time it overflows or underflows This is the hnormal reload mode reload on overflow underflow If either a positive or a negative transition of T3OTL is selected to trigger a reload the core timer T3 will be reloaded with the contents of the auxiliary timer on every second overflow or underflow Using the latter configuration for both auxiliary timers one can perform very flexible pulse width modulation PWM One of the auxiliary timers is programmed to reload the core timer on a positive transition of T3OTL the other is programmed for a reload on a negative transition of T3OTL Thus the core timer is alternately reloaded by each of the auxiliary timers Semiconductor Group 8 40 SIEMENS Peripherals Figure 8 2 16 shows such a configuratio
92. BC places any byte value to be written to the external memory on both the upper byte portion and the lower byte portion of the 16 bit external data bus However the byte will only be stored in that byte memory which is specified by AO and BHE Table 9 2 Word or Byte Access to Two Coupled Byte Wide Memories BHE Type of Access 0 Both byte memories are accessed together for word transfers 0 Only the high byte memory is accessed for byte transfers 1 Only the low byte memory is accessed for byte transfers 1 Not used To be correctly used as just described the BHE output pin must be connected to the chip select input CS of the memory at the high byte location and the AO address output pin must be connected to the chip select input of the memory at the low byte location as shown in figure 9 4 Detailed application examples for the just mentioned external bus and memory configurations are shown in appendix C Figure 9 4 16 18 Bit Address 16 Bit Data Muitiplexed Bus Byte Wide Memories Segment Addr Pons WR RD BHE ALE SAB 80C166 Porto ADDR CS OE wR4 ADDR CS OE WR Port 1 8 Bit 8 Bit Ext Memory Ext Memory INSTR DATA INSTR DATA Siemens Aktiengesellschaft 9 7 External Bus Interface 9 5 16 18 Bit Address 16 Bit Data Non Multiplexed Bus This external bus mode can be selected if the SAB 80C166 is to be used in collaboration with a word wide external memory As shown in figure 9 5 Port
93. CAPCOM Register 0 0000h CCOIC b FF78h BCh CAPCOM Register 0 Interrupt Control 0000h CC1 FE82h 41h CAPCOM Register 1 0000h CC1IC b FF7Ah BDh CAPCOM Register 1 Interrupt Control 0000h CC2 FE84h 42h CAPCOM Register 2 0000h CC2lC b FF7Ch BEh CAPCOM Register 2 Interrupt Control 0000h CC3 FE86h 43h CAPCOM Register 3 0000h CC3IC b FF7Eh BFh CAPCOM Register 3 Interrupt Control 0000h CC4 FE88h 44h CAPCOM Register 4 0000h CCAIC b FF80h COh CAPCOM Register 4 Interrupt Control 0000h Semiconductor Group B 12 SIEMENS SAB 80C166 Registers Name Physical 8 Bit Description Reset Address Address Value CC5 FE8Ah 45h CAPCOM Register 5 0000h CCB5IC b FF82h Cih CAPCOM Register 5 Interrupt Control 0000h CC6 FE8Ch 46h CAPCOM Register 6 0000h CC6IC b FF84h C2h CAPCOM Register 6 Interrupt Control 0000h CC7 FE8Eh 47h CAPCOM Register 7 0000h CC7IC b FF86h C3h CAPCOM Register 7 Interrupt Control 0000h CC8 FE90h 48h CAPCOM Register 8 0000h CC8lC b FF88h C4h CAPCOM Register 8 Interrupt Control 0000h CC9 FE92h 49h CAPCOM Register 9 0000h CC9IC b FF8Ah C5h CAPCOM Register 9 Interrupt Control 0000h CC10 FE94h 4Ah CAPCOM Register 10 0000h CC10IC b FF8Ch C6h CAPCOM Register 10 Interrupt Control 0000h CC11 FE96h 4Bh CAPCOM Register 11 0000h CC11IC b FF8bEh C7h CAPCOM Register 11 Interrupt Control 0000h CC12 FE98h 4Ch CAPCOM Register 12 0000h CC12IC b FF90h C8h CAPCOM Register 12 Interrupt
94. CE will provide the capability of setting breakpoints based on a series of events conditional arming Tracing Having a history of operations which proceed a breakisuseful infinding bugs in hardware and software A trace buffer for capturing important trace information in real time will be supported This trace information includes IP addresses opcode va lues operand addresses operation results and data values In addition it will provide trace on and trace off capability to allow tracing of only selected portions of code exe cuted during emulation f Siemens Aktiengesellschaft 14 1 Support Tools Single Step The ability to single step the target through the execution of a single instruction or HLL High Level Language statement will be provided Counter Vaiue A counter will be provided which can be used in conjunction with the triggering conditions to count events The counter will also have the ability to trigger a trace or a break after a specified count has been reached Symbolic debugging The ability to reference alphanumeric symbols instead of ab solute addresses will be provided This increases programming efficiency by allowing the programmer to refer to names instead of physical addresses To aid in producing an emulator that supports the above set of functions a bond out version of the SAB 80C166 will be provided To further enhance emulation and testing the majority of the internal system state has been
95. CPU in the state immedeately before a timer increment reload or capture is to be performed the CPU write operation has priority in order to guarantee correct results From a programmer s point of view the GPT1 block is composed of a set of SFRs as shown in figure 8 2 3 Those portions of port and direction registers which are not used for alternate functions by the GPT1 block are not shaded Semiconductor Group 8 26 SIEMENS Peripherals Ports amp Direction Control Data Registers Control Registers Alternate Functions DP3 T2 T2CON T2IC T2IN P3 7 T3IN P3 6 T3 T3CON T3IC T4IN P3 5 T3EUD P3 4 T3OUT T4 T4CON T4IC P3 3 Interrupt Control Port 3 Direction Control Register Port 3 Data Register GPT1 Timer 2 Register GPT1 Timer 3 Register GPT1 Timer 4 Register GPT1 Timer 2 Control Register GPT1 Timer 3 Control Register GPT1 Timer 4 Control Register GPT1 Timer 2 Interrupt Control Register GPT1 Timer 3 Interrupt Control Register GPT1 Timer 4 Interrupt Control Register Figure 8 2 3 SFRs and Port Pins Associated with the GPT1 Block In the following the individual features of each timer in block GPT1 will be discussed separately Semiconductor Group 8 27 SIEMENS Peripherals 8 2 1 1 GPT1 Core Timer T3 The configuration of the core timer T3 is determined by its bit addressable control register T3CON which is shown in the following figure 8 2 4 T3CON FF42h A1h Reset
96. Compare Register CC2 Allocation Bit ACC2 20 CC2 allocated to Timer 0 ACC2 21 CC2 allocated to Timer 1 CCMOD3 CCMO 14 12 Capture Compare Register CC3 Mode Selection see table 8 1 3 ACC3 CCM0 15 Capture Compare Register CC3 Allocation Bit ACC3 0 CC3 allocated to Timer 0 ACC3 1 CC3 allocated to Timer 1 Semiconductor Group 8 11 SIEMENS Peripherals CCM1 FF54h AAh Reset Value 0000h 15 14 13 11 10 9 8 6 5 4 3 ACC5 CCMOD5 CCMOD4 CCM2 FF56h ABh Reset Value 0000h 14 13 12 11 10 9 8 ACC11 CCMOD11 ACC10 CCMOD10 6 5 4 3 ACC9 CCMOD9 CCMOD8 CCM3 FF58h ABh Reset Value 0000h 14 13 12 11 10 9 8 ACC15 CCMOD15 ACC14 CCMOD14 6 5 4 3 ACC13 CCMOD13 ACC12 CCMOD12 Figure 8 1 8 CAPCOM Mode Control Registers CCM1 CCM2 CCM3 Semiconductor Group 8 12 SIEMENS Peripherals Table 8 1 3 lists the possible capture and compare modes which can be programmed for each capture compare register The different modes are discussed in detail in the following subsections Table 8 1 3 Capture Compare Register Mode Selection x 0 15 CCMODx Function 2 1 0 0 0 0 Capture Compare Disabled 0 0 1 Capture on Positive External Transition at Pin CCxlO 0 1 O Capture on Negative External Transition at Pin CCxlO 0 1 1 Capture on Positive and Negative External Transition at Pin CCxlO 1 0 0 Compare Mode 0 Interrupt only several interrupts per timer period enables
97. E Alternate Output Function Enable in register T3CON enables the state of T3OTL to be an alternate function of the external output pin TSOUT P3 3 For that purpose a 1 must be written into port data latch P3 3 and pin T3OUT P3 3 must be configured as output by setting direction control bit DP3 3 to 1 If T30E 1 pin TSOUT then outputs the state of T3OTL If T3OE 0 pin T3OUT can be used as a general purpose O pin In addition TSOTL can be used in conjunction with the timer over underflows as a trigger source for the counter or reload functions of the auxiliary timers For this purpose the state of T3OTL does not have to be available at pin T3OUT because an internal connection is provided for this option This feature is described in detail in section 8 2 1 2 3 and 8 2 1 2 4 about the auxiliary timers 8 2 1 1 1 Timer Mode Timer mode is selected for the core timer T3 by setting bit field T3M in register T3CON to 00b In this mode T3 is clocked with the internal system clock divided by a programmable prescaler which is selected by bit field T3l The input frequency fr for timer T3 is scaled linearly with slower oscillator frequencies fosc as can be seen from the following formula fra B 16 F o lt T3l gt The timer input frequencies resolution and periods which result from the selected prescaler option when using a 40 MHz oscillator are listed in table 8 2 3 This table also applies to the gated timer mode of T3 and to the auxili
98. E44h 22h GPT1 Timer 4 Register 0000h T5 FE46h 23h GPT2 Timer 5 Register 0000h T6 FE48h 24h GPT2 Timer 6 Register 0000h CAPREL FE4Ah 25h GPT2 Capture Reload Register 0000h FE4Ch 26h reserved FE4Eh 27h reserved Semiconductor Group B 4 SIEMENS SAB 80C166 Registers Name Physical 8 Bit Description Reset Address Address Value TO FE50h 28h CAPCOM Timer 0 Register 0000h T1 FE52h 29h CAPCOM Timer 1 Register 0000h TOREL FE54h 2Ah CAPCOM Timer 0 Reload Register 0000h T1REL FE56h 2Bh CAPCOM Timer 1 Reload Regiser 0000h FE58h 2Ch reserved e e e e e e FE7Eh 3Fh reserved CCO FE80h 40h CAPCOM Register 0 0000h CC1 FE82h 41h CAPCOM Register 1 0000h CC2 FE84h 42h CAPCOM Register 2 0000h CC3 FE86h 43h CAPCOM Register 3 0000h CC4 FE88h 44h CAPCOM Register 4 0000h CC5 FE8Ah 45h CAPCOM Register 5 0000h CC6 FE8Ch 46h CAPCOM Register 6 0000h CC7 FE8Eh 47h CAPCOM Register 7 0000h CC8 FE90h 48h CAPCOM Register 8 0000h CC9 FE92h 49h CAPCOM Register 9 0000h CC10 FE94h 4Ah CAPCOM Register 10 0000h CC11 FE96h 4Bh CAPCOM Register 11 0000h CC12 FE98h 4Ch CAPCOM Register 12 0000h CC13 FE9Ah 4Dh CAPCOM Register 13 0000h CC14 FE9Ch 4Eh CAPCOM Register 14 0000h CC15 FE9Eh 4Fh CAPCOM Register 15 0000h Semiconductor Group B 5 SIEMENS SAB 80C166 Registers
99. EMENS Peripherals T5CLR 1 Thus register CAPREL always contains the correct time between two events measured in timer T5 increments Timer T6 which runs in timer mode counting down T6UD 1 with a frequency of for example fosc 8 uses the value in register CAPREL to perform a reload on underflow This means the value in register CAPREL represents the time between two underflows of timer T6 now measured in timer T6 increments Since timer T6 runs 8 times faster than timer T5 it will underflow 8 times within the time between two external events Thus the underflow signal of timer T6 generates 8 ticks Upon each underflow interrupt request flag T6IR will be set and bit T6OTL will be toggled The state of TEOTL may be output on pin T6OUT This signal has 8 times more transitions than the signal which is applied to pin CAPIN The underflow signal of timer T6 can furthermore be used to clock the CAPCOM timers TO and or T1 which gives the user the possibility to set compare events based on a finer resolution than that of the external events 8 3 A D Converter ADC The SAB 80C166 provides a 10 bit A D converter with 10 multiplexed analog input channels and a sample amp hold circuit on chip It supports 4 different conversion modes including single channel single channel continuous auto scan and auto scan continuous conversion The external analog reference voltages Varer and Vacnp are fixed Figure 8 3 1 shows a block diagram of the A D
100. EN Semiconductor Group 8 73 SIEMENS Peripherals 8 4 1 3 Loop Back Mode For testing purposes a special loop back mode is provided which allows testing of each serial channel without using the alternate functions of the port pins associated with this channel While in loop back mode instead of receiving data from the RXDO or RXD1 pin the data which are transmitted are simultaneously clocked into the receive shift register A transmission in loop back mode is initiated for channel ASCO by a write operation to SOTBUF when SOLB 1 SOREN 1 and SOR 1 and for ASC1 by writing to S1TBUF with S1LB 1 S1REN 1 and S1R 1 This feature is available for all operating modes asynchronous and synchronous of the serial channels 8 4 2 Baud Rates Each of the serial channels of the SAB 80C166 has its own dedicated 13 bit baud rate generator with 13 bit reload capability allowing independent baud rate selection for each channel Both baud rate generators are 13 bit timers clocked with the internal system clock divided by 2 10 MHz 40 MHz oscillator frequency The timers are counting downwards and can be started or stopped through the Baud Rate Generator Run Bits SOR or S1R in register SOCON or S1CON Each underflow of a timer provides one clock pulse to a serial channel The timers are reloaded with the value stored in their 13 bit reload register each time they underflow Thus the baud rate of a serial channel is determined by the oscillator frequ
101. FAh CPU General Purpose Register RL5 XXh RH5 CP 11 FBh CPU General Purpose Register RH5 XXh RL6 CP 12 FCh CPU General Purpose Register RL6 XXh RH6 CP 13 FDh CPU General Purpose Register RH6 XXh RL7 CP 14 FEh CPU General Purpose Register RL7 XXh RH7 CP 15 FFh CPU General Purpose Register RH7 XXh Semiconductor Group B 3 SIEMENS SAB 80C166 Registers B 2 Special Function Registers Ordered by Address B 2 1 Non Bit Addressable Special Function Registers Name Physical 8 Bit Description Reset Address Address Value DPPO FEOOh 00h CPU Data Page Pointer 0 Register 4 bits 0000h DPP1 REO2h Oth CPU Data Page Pointer 1 Register 4 bits 0001h DPP2 FEO4h 02h CPU Data Page Pointer 2 Register 4 bits 0002h DPP3 FEO6h O3h CPU Data Page Pointer 3 Register 4 bits 0003h CSP FEO8h 04h CPU Code Segment Pointer Register 0000h 2 bits read only FEOAh 05h reserved MDH FEOCh 06h CPU Multiply Divide Register High Word 0000h MDL FEOEh 07h CPU Multiply Divide Regiser Low Word 0000h CP FE10h 08h CPU Context Pointer Register FCOOh SP FE12h 09h CPU System Stack Pointer Register FCOOh STKOV FE14h OAh CPU Stack Overflow Pointer Register FAOOh STKUN FE16h OBh CPU Stack underflow Pointer Register FCOOh FE18h OCh reserved e e e e e e FESEh 1Fh reserved T2 FE40h 20h GPT1 Timer 2 Register 0000h T3 FE42h 21h GPT1 Timer 3 Register 0000h T4 F
102. FC2h E1h Reset Value 0000h 15 14 13 12 11 10 9 8 Ed za s BR Bia a ac Dee 7 6 5 4 3 2 1 0 EE Ec i an REIR c DP3 FFC6h E3h Reset Value 0000h 15 14 13 12 11 10 9 8 gerais ua ai Boa Ea EE BC ia 7 6 5 4 3 2 1 0 er a RSEN ae eaea ERR Figure 10 2 Ports 0 through 3 Direction Control Registers DPO DP1 DP2 DP3 Symbol Position Function DPx y DPx y Port Px Direction Control x20 through 3 y 0 through 15 DPx y 0 Port Line Px y is Input high impecance DPx y 1 Port Line Px y is Output Semiconductor Group 10 3 Parallel Ports SIEMENS P4 FF08h 84h Reset Value 0000h 7 6 5 4 3 2 1 0 Figure 10 3 Port 4 Data Register P4 Symbol Position Function P4 y P4 y Port P4 Data Register y 0 through 1 PA 7 2 reserved DPA FFOAh 85h Reset Value 0000h 7 6 5 4 3 2 1 0 pepe qe s e Figure 10 4 Port 4 Direction Control Register DPA Symbol Position Function DP4 y DP4 y Port P4 Direction Control y 0 through 1 DP4 y 0 Port Line P4 y is Input high impedance DP4 y 1 Port Line P4 y is Output DP4 7 2 reserved Using PO through P4 as General Purpose I O Ports When the alternate input or output function associated with a port pin is not enabled the pin can be used as a general purpose l O pin Each port pin consists of a port output latch an output buffer an input latch an input read buffer and a direction control latch Each port pin can
103. General Purpose Registers GPRs andthe PEC source and destina tion pointers are situated within the internal RAM space Additionally the internal RAM can be used for both code and data storage The SAB 80C166 assembler supports the re servation of the required internal RAM areas according to the just mentioned particular uses Code accesses are always made on even byte addresses Provided that the PEC source and destination pointers are not required the highest possible code storage location in the internal RAM is either OFDFEh for single word instructions or OFDFCh for double word instructions If used for code storage the corresponding location must contain a branch instruction to a memory location other than in the SFR space because this space is not provided for code execution Any word and byte data in the internal RAM can be accessed via indirect or long 16 bit addressing modes if the selected DPP register points to data page 3 Any word data access is made on an even byte address Provided that the PEC source and destination pointers are not required the highest possible word data storage location in the internal RAM is address OFDFEh For PEC data transfers the internal RAM canbeaccessedinde pendent of the contents of the DPP registers via the PEC source and destination poin ters Siemens Aktiengesellschaft 4 8 Memory Organization All system stack operations are implicitly performed by means of the Stack Pointer SP regist
104. HONS oto ce aa a ae eb aS a ise need 6 1 Boolean Bit Manipulation Instructions lees 6 2 Compare and Loop Control Instructions lee 6 2 Shift and Rotate Instructions llle 6 2 Prioritize Instruction soe Ese aoa os eee Saas RES ES 6 2 Data Movement Instructions 2 0 0 6 eee eee eee 6 3 System Stack Instructions 4 04 65 eh Radek RE Eee eps 6 3 Jump and Call Instructions llle 6 3 Return Instruction soegin 64 ed od y IRR rere Ris Ree 6 4 System Control Instructions lee 6 4 Miscellaneous 453154 xe me TRUE Ro bore ERAT COR LC S T RU ROS AUR 6 4 Addressing Modes ccc cee cee ce ne 6 4 Short Addressing Modes sene 6 4 Long Addressing Mode o sialecee yr mer e ROC E S ples 6 6 Indirect Addressing Modes llle 6 7 Gonstans sus C ETECPP 6 9 Branch Target Addressing Modes lees 6 9 Condition Code Specification 0 cee eee 6 10 interrupt and Trap Functions 04 7 1 Interrupt System Structure eee eee ees 7 2 Normal Interrupt Processing and PEC Service 7 5 Interrupt System Register Description lees 7 5 Interrupt Control Registers lecce al e IAS xn 7 5 Interrupt Control Functions in the PSW ww ec ees 7 9 PEC Service Channels Register Description se 7 10 PEC Channel Counter Control Registers eee ee eee 7 10 PEC Source and Des
105. I 85 lt 135 2 gt 175 lt 225 3 gt 135 lt 185 3 gt 225 lt 275 4 2 185 lt 235 4 gt 2 5 lt 325 5 J 235 lt 285 5 Semiconductor Group C 11 SIEMENS Table C 2a Multiplexed Memory Write with Read Write Delay Application Examples Symbol Meaning 40 MHz Clock Variable Timing but Write Pulse Low Time twres to nt 50 ty lt s 2TCL 10 n1 2TCL n1 gt ty 50 0 8 n1 gt ty 10 2TCL 1 tow Data Valid to WR tjw b2 N2 50 fg 2 217CL 15 n2 2TCL n22214 50 0 7 n22z tyy 15 2TCL 1 tah Data Hold after WR tih b3 tn 2TCL 15 has Adress Setup tas lg lg tas 2TCL 25 Lo 529 t ALE Cycle Time t 150 n 50 t 6TCL n 2TCL Note TCL 1 fosc 25 ns at 40 MHz ALE Cycle Time Memory Cycle Time 26TCL 150 ns at 40 MHz for 0 wait state operation toa An address float time of 5 ns must be permissible la tg to too 154 See Device Specification Section D 5 3 Take care of fy and ts These times cannot be proglonged by wait states Table C 2b Multiplexed Memory Write with Read With Delay Quick Table fwr ni law n2 lt 40 0 lt 35 0 2 40 lt 90 1 2 gt 35 lt 85 1 gt 90 lt 140 2 285 lt 135 2 gt 140 lt 190 3 J 135 lt 185 3 gt 190 lt 240 4 2 185 lt 235 4 gt 240 lt 290 5 2 235 lt 285 5 Semiconduc
106. IEMENS SAB 80C166 83C166 a a ae oe oe oe olg CLKOUT ry moe Nou Hema Oe c cd i Internal Weak Pull Down ALE LUTTE ME ea oot reo l f l i LELALLL LAL i 4 Sur AAAA Porto DATAOUT TTT Figure 11 2 Timing for Entry into Hold Non Multiplexed Bus Semiconductor Group D 24 SAB 80C166 83C166 SIEMENS e ae E a a eee a a A aa a c ce i 00 d a a T a a a a O Vc E or coe Tur Lcd decns ec 7p a nm Lo ees o l eps LLL O e N T prg ER Fe 4 g c z o ke mM kai Lon P ee ME INNER eS MN D g g o Q rue ss mer 8 ums sien oe Dee ee eB 5 g gt cm Sas I ES QD uci qe cos I E bd i L Lu z E lea or eed m pe H l D 2 Lu o t Q lt f Q c c or zi O d E e E 2 z E Oo r o ei TO r D J DE LL Fr D 25 Semiconductor Group
107. Implicitly incrementing or decrementing the SP register immediately after an instruction which explicitly writes to the SP register as shown in the following example I MOV SP Z0FBOOh explicit update of the stack pointer ner SCXT R1 1000h implicit decrement of the stack pointer Tid 2 States In these cases the extra state times can be avoided by putting other suitable instructions before the instruction 1 reading the SFR 4 External operand reads Tiagg 1 ACT Any external operand reading via a 16 bit wide data bus requires one additional ALE Cycle Time Reading word operands via an 8 bit wide data bus takes twice as much time 2 ALE Cycle Times as the reading of byte operands 5 External operand writes Tiag 0 State 1 ACT Writing of an external operand via a 16 bit wide data bus takes one additional ALE Cycle Time For timing calculations of external program parts this extra time must always be considered The value of Tiagg which must be considered for timing evaluations of internal program parts may fluctuate between 0 state times and 1 ALE Cycle Time This is because external writes are normally performed in paraileito other CPU operations Thus Tiaga could already have been considered in the standard processing time of another instruction Writing a word operand via an 8 bit wide data bus requires twice as much time 2 ALE Cycle Times as the writing of a byte operand 6 Testing Branch Condit
108. ON register Note that the new BUSCON1 register is only capable of controlling the external bus It is not possible to control or modify the on chip ROM space through the BUSCON 1 register This can only be done with register SYSCON Semiconductor Group D 10 SIEMENS SAB 80C166 83C166 8 Switching between the Bus Modes With the new features of the BA step of the SAB 80C166 the additional bus mode and the new BUSCON 1 register it is possible to switch the bus characteristics on the fly One can change the number of wait states switch from a multiplexed bus to a non multiplexed bus or vice versa or can use the READY function in a certain address range while operating without READY in the remaining address range This can either be done by using the SYSCON and BUSCON 1 registers with different parameters in certain address ranges or by reprogramming the SYSCON or BUSCON1 register prior to an access which should be performed with different bus characteristics However it is not recommended or very useful to modify the SYSCON or BUSCON1 register which is currently being used for instruction fetches since pipeline effects can make it very difficult to determine which of the following accesses will be made with the new configuration Thus it is recommended to modify bus configuration registers used for instruction fetches while executing instructions from either internal ROM RAM or from a different SYSCON or BUSCON1 address range For exa
109. Overflow Underflow registers is performed l Siemens Aktiengesellschaft 13 4 System Programming 13 4 1 1 Use of Stack Underflow Overflow Registers In many cases the user will place a Software Reset SRST instruction in the stack under flow and overflow trap service routines indicating a fatal error However it is also possible to use the stack underflow and stack overflow registers to cache portions of a larger ex ternal stack This technique places only the portion of the system stack currently being used in the internal memory thus allowing a greater portion of the internal RAM to be used for program data or register banking This basic technique allows data to be pushed until the overflow boundary of the internal stack is reached At this point a portion of the stacked data must be saved in the external memory to create space for further stack pushes Thisis called stack flushing When execu ting a number of return or pop instructions the upper boundary since the stack empties upward to higher memory locations is reached The entries that have been previously saved on the external memory must now be restored This is called stack filling Because procedure call instructions do not continue to nest indefinitely and return instructions are interspersed with cails flushing and filling normally occur very infrequently If this is not true for a given program environment this technique should not be used because of the overhead of flus
110. Register 0000h T1IC b FF9Eh CFh CAPCOM Timer 1 Interrupt Control 0000h Register T1REL FE56h 2Bh CAPCOM Timer 1 Reload Register 0000h Semiconductor Group B 16 SIEMENS SAB 80C166 Registers Name Physical 8 Bit Description Reset Address Address Value T2 FE40h 20h GPT1 Timer 2 Register 0000h T2CON b FF40h AOh GPT1 Timer 2 Control Register 0000h T2IC b FF60h Boh GPT1 Timer 2 Interrupt Control Register 0000h T3 FE42h 21h GPT1 Timer 3 Register 0000h T3CON b FF42h Ath GPT1 Timer 3 Control Register 0000h T3IC b FF62h Bih GPT1 Timer 3 Interrupt Control Register 0000h T4 FE44h 22h GPT1 Timer 4 Register 0000h TACON b FF44h A2h GPT1 Timer 4 Control Register 0000h T4IC b FF64h B2h GPT1 Timer 4 Interrupt Control Register 0000h T5 FE46h 23h GPT2 Timer 5 Register 0000h T5CON b FF46h A3h GPT2 Timer 5 Control Register 0000h T5IC b FF66h B3h GPT2 Timer 5 Interrupt Control Register 0000h T6 FE48h 24h GPT2 Timer 6 Register 0000h TeCON b FF48h A4h GPT2 Timer 6 Control Register 0000h T6IC b FF68h B4h GPT2 Timer 6 Interrupt Control Register 0000h TFR b FFACh D6h Trap Flag Register 0000h WDT FEAEh 57h Watchdog Timer Register read only 0000h WDTCON b FFAEh D7h Watchdog Timer Control Register 0000h for Watchdog Timer overflow 0002h ZEROS b FF1Ch 8Eh Constant Value 0 s Register read only 0000h Semiconductor Group B 17 SIEMENS Application Examples
111. Request CAPREL Register Figure 8 2 28 Register CAPREL in Capture Mode 8 2 2 3 2 Reload Mode This mode is selected by setting bit T SR 1 in register TECON The event causing a reload in this mode is an overflow or underflow of the core timer T6 Semiconductor Group 8 52 SIEMENS Peripherals If T6SR 1 when timer T6 overflows from FFFFh to 0000h when counting up or when it underflows from 0000h to FFFFh when counting down the value stored in register CAPREL is loaded into timer T6 This will not set the interrupt request flag CRIR associated with the CAPREL register However interrupt request flag T6IR will be set indicating the overflow underflow of T6 Figure 8 2 29 shows a block diagram of the reload mode of register CAPREL CAPREL Register Interrupt Request To CAPCOM Timers TO T1 Figure 8 2 29 Register CAPREL in Reload Mode 8 2 2 3 3 CAPREL Register Interrupt Control Whenever a transition according to the selection in bit field Cl is detected at pin CAPIN P3 2 interrupt request flag CRIR in register CRIC is set This will cause an interrupt to the CAPREL register interrupt vector CRINT or will trigger a PEC service if the interrupt enable bit CRIE in register CRIC is set Figure 8 2 30 shows the organization of register CRIC Refer to chapter 7 for more details on interrupts CRIC FF6Ah B5h Reset Value 0000h 7 6 5 4 3 2 1 0 CRIR CRIE ILVL GLVL Figure 8 2 30 CAPREL Register Interrupt Control
112. SIEMENS Microcomputer Components SAB 80C166 83C166 16 Bit CM OS Single Chip M icrocontrollers for Embedded Control Applications SAB 80C166 83C166 Revision History Current Version 06 90 08 97 Previous Releases Original version 6 90 Page Subjects major changes since last revision A Instruction Set removed See separate Instruction Set Manual B158 H6772 G1 X 7600 D Device Specifications removed Please refer to actual data sheet Addendum to User s Manual 9 90 included Now both documents are combined to one single book Note The contents of the combined documents is identical with the respective original version 6 90 or 9 90 Edition 06 90 08 97 Published by Siemens AG Bereich Halbleiter Marketing Kommunikation BalanstraBe 73 81541 M nchen Siemens AG 1997 All Rights Reserved Attention please As far as patents or other rights of third parties are concerned liability is only assumed for components not for applications processes and circuits implemented within components or assemblies The information describes the type of component and shall not be considered as assured characteristics Terms of delivery and rights to change design reserved For questions on technology delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide see address list Due to technical r
113. SIEMENS SYSCON FFOCh 86h Reset Values 0400h 0040h 0080h or 00COh 15 14 1 3 12 11 10 9 8 m STKSZ RDYEN SGTDIS BUSACT BYTDIS CLKEN 2 1 0 7 6 5 4 3 BTYP MTTC RWDC MCTC Figure 5 1 System Configuration Register Symbol Position Function MCTC SYSCON 3 0 Memory Cycle Time Control See description chapter 6 for details RWDC SYSCON 4 Read Write Delay Control MTTC SYSCON 5 Memory Tri state Time Control BTYP SYSCON 7 6 External Bus Configuration Control See description chapter 5 for details CLKWN SYSCON 8 System Clock Output CLKOUT Enable bit CLKEN 0 CLKOUT disabled pin can be used for normal I O CLKEN 21 CLKOUT enabled pin used for system clock output BYTDIS SYSCON 9 Byte High Enable BHE pin control bit BYTDIS 20 BHE enabled BYTDIS 21 BHE disabled pin can be used for normal I O BUSACT SYSCON 10 Bus Active Control Bit See description chapter 5 for details SGTDIS SYSCON 11 Segmentation Disable control bit SGTDIS 20 A16 and A17 enabled Port 4 used for segment address SGTDIS 21 A16 and A17 disabled Port 4 can be used for normal I O RDYEN SYSCON 12 READY Input Enabled control bit RDYEN 2 20 READY function disabled for SYSCON accesses RDYEN 1 READY function enabled for SYSCON accesses STKSZ SYSCON 14 13 Maximum System Stack Size Selection of between 32 and 256 words SYSCON 15 reserved Semiconductor Group D 17 SAB
114. Semiconductor Group 3 4 SIEMENS System Description In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed just one cycle is stolen from the current CPU activity to perform a PEC service A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer An individual PEC transfer counter is implicitly decremented for each PEC service except when performing in the continuous transfer mode When this counter reaches zero a standard interrupt is performed to the corresponding source related vector location PEC services are very well suited for example for supporting the transmission or reception of blocks of data or for transferring A D converted results to a memory table The SAB 80C166 has 8 PEC channels each of which offers such fast interrupt driven data transfer capabilities A separate control register which contains an interrupt request flag an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources Via its related register each source can be programmed to one of sixteen interrupt priority levels Once having been accepted by the CPU an interrupt service can only be interrupted by a higher prioritized service request For the standard interrupt processing each of the possible interrupt so
115. T4IN the core timer T3 is reloaded with the contents of the auxiliary timer and the interrupt request flag T2IR or T4IR of the auxiliary timer is set The direction control bits DP3 7 for T2IN or DP3 5 for TAIN must be set to 0 and the input signal should hold its level for at least 8 states to ensure correct recognition of the triggering edge Figure 8 2 14 shows a block diagram of this external reload mode Reload Register Tx Txl Input Clock Figure 8 2 14 GPT1 Auxiliary Timer in External Reload Mode When bit T21 2 1 or bit T41 2 1 a transition of the toggle bit TSOTL which is caused by an overflow underflow of T3 is the trigger for a reload Note that software modifications of TSOTL will NOT trigger the reload function Again one can select either a positive a negative or both a positive and a negative transition of T3OTL to cause a reload When a selected transition of T3OTL is detected the core timer T3 is reloaded with the contents of the auxiliary timer and the interrupt request flag T2IR or T4IR of the respective auxiliary timer is set Note that the interrupt request flag T3IR of the core timer T3 will also be set indicating the overflow underflow of T3 Figure 8 2 15 shows a block diagram of this reload mode Semiconductor Group 8 39 SIEMENS Peripherals Reload Register Tx Interrupt Note Line only affected by over underflows of T3 but NOT by software modifications of T3OTL Figure 8 2 15 GPT1
116. TXD1 P3 8 are used by ASC1 Figure 8 4 3 shows a block diagram of a serial channel in the asynchronous mode of operation Semiconductor Group 8 65 SIEMENS Peripherals Reload Register Baud Rate Timer V SxST SxFEASxOE SxRIR Receive Int Clock Request RXDO P3 11 Serial Port Control SxTIR QUod Int RXD1 P3 9 Nl Samp Receive Shift Register Transmit Buffer Reg ling SxTBUF m 10 TXD1 P3 8 Receive Buffer Reg SxRBUF Figure 8 4 3 Serial Channel Asynchronous Mode Block Diagram Information Frames in Asynchronous Operation Each information frame that can be transmitted or received by the serial channels in asynchronous operation consists of the following elements One start bit An 8 bit or 9 bit data frame selected by bit fields SOM S1M One or two stop bits selected by bits SOSTP S1STP in control registers SOCON S1CON Semiconductor Group 8 66 SIEMENS Peripherals Figure 8 4 4 shows an information frame with an 8 bit data frame DO to D6 are data bits D7 can be configured as the 8th data bit 8 bit data mode or as the parity bit 7 bit data parity bit mode 1 st 2 nd Start DO D1 D2 D3 D4 D5 D7 Stop Stop Bit LSB Bit Bit Figure 8 4 4 8 Bit Data Frame Figure 8 4 5 shows an information frame with a 9 bit data frame DO to D7 are data bits D8 can be configured to either be the 9th data bit 9 bit data mode the parity bit 8 bit data parity bit mode or the special w
117. The function of the BHE pin is enabled if the BYTDIS bit contains a 0 Otherwise it is disabled and the pin can be used as standard 1 O pin The BHE pin is implicitly used by the External Bus Controller to select one of two byte organized memory chips which are connected with the SAB 80C166 via a word wide external data bus After reset BYTDIS is initialized to zero For further information about the use of the BHE pin see section 9 1 3 5 3 1 4 Ready Pin Control via RDYEN The RDYEN bit provides an optional Data Ready function via the active low READY in put pin to allow an external memory controller or peripherals to determine the duration of an external memory access The Data Ready function is enabled by setting the RDYEN bit to 1 In this case port pin P3 14 takes on its alternate function as active low READY input pin An active low signal on the READY input pin signifies that data is available and must be latched by the on chip External Bus Controller Note that it is the user s respon sibility to set the direction of the READY pin to input before using this function In the case that the Data Ready function is enabled the contents of the MCTC bit field are not significant This means that the external bus timing is only determined by the READY pin the MTTC bit the RWDC bit and by the selected external bus mode Warning If the Data Ready function is enabled the READY input pin must be activated for every externa
118. Value 0000h ii c Ra nov Ter ie Figure 8 2 4 GPT1 Core Timer T3 Control Register T2CON Symbol Position Function TSI T3CON 2 0 Timer 3 Input Selection For Timer and Gated Timer mode see table 8 2 3 For Counter mode see table 8 2 4 T3M T3CON 4 3 Timer 3 Mode control see table 8 2 1 T3R T3CON 6 Timer 3 Run Bit T3R 20 Timer Counter 3 stops T3R 21 Timer Counter 3 runs T3UD T3CON 7 Timer 3 Up Down Control see table 8 2 2 T3UDE T3CON 8 Timer 3 External Up Down Control Enable Bit see table 8 2 2 Alternate Output Function Enable TSOE T3CON 9 T30E 0 Alternate Output Function Disabled TSOE 1 Alternate Output Function Enabled Semiconductor Group 8 28 SIEMENS Peripherals Timer 3 Mode Selection Bit field T3M Timer 3 Mode Control selects the basic operating mode for timer T3 The available options are listed in table 8 2 1 and will be discussed in detail in the following subsections Table 8 2 1 Core Timer T3 Mode Control T3M Mode 1 0 0 0 Timer 0 1 Counter 1 0 Gated Timer gate is active low 1 1 Gated Timer gate is active high Timer 3 Run Bit The timer can be started or stopped by software through bit T3R Timer T3 Run Bit If T3R 0 the timer stops Setting T3R to 1 will start the timer In gated timer mode the timer will only run if T3R 1 and the gate is active Count Direction Control The count direction of the core timer can
119. XDO and RXD1 Semiconductor Group 10 14 Parallel Ports SIEMENS 10 1 4 Port 4 The alternate functions on the two pins of Port 4 P4 are the two segment address lines A16 and A17 shown in table 10 2 As for Port 0 Port 1 and the BHE signal the alternate function of Port 4 might be required directly after reset Thus the alternate function of Port 4 will be switched automatically Table 10 2 Port 4 Alternate Output Functions Symbol Alternate Symbol __ Input Output Function P4 0 A16 O Lower Address Line of Segment Address P4 1 A17 O Higher Address Line of Segment Address Figure 10 13 shows a block diagram of a Port 4 pin which is the same as for a Port 1 pin When an external bus is selected AND segmentation is enabled through bit SGTDIS 0 in register SYSCON default after reset the input to the port output latch is switched via a Write DP4 y Direction Latch DP4 y Alternate Function Enable Read Direction Read Buffer Alternate Function Enable Write Port P4 y Alternate Data Output Output Buffer Read Port P4 y Read Buffer Figure 10 13 Block Diagram of a Port 4 Pin Semiconductor Group 10 15 SIEMENS Parallel Ports multiplexer from the internal bus to the Alternate Data Output line which supplies the segment address Via a second multiplexer the output buffer is enabled to drive the segment address If segmentation is not required in an application th
120. XXXh H3 CP 6 F3h CPU General Purpose Register R3 XXXXh R4 CP 8 F4h CPU General Purpose Register R4 XXXXh R5 CP 10 F5h CPU General Purpose Register R5 XXXXh R6 CP 12 F6h CPU General Purpose Register R6 XXXXh H7 CP 14 F7h CPU General Purpose Register R7 XXXXh H8 CP 16 F8h CPU General Purpose Register R8 XXXXh H9 CP 18 F9h CPU General Purpose Register R9 XXXXh R10 CP 20 FAh CPU General Purpose Register R10 XXXXh R11 CP 22 FBh CPU General Purpose Register R11 XXXXh R12 CP 24 FCh CPU General Purpose Register R12 XXXXh R13 CP 26 FDh CPU General Purpose Register R13 XXXXh R14 CP 28 FEh CPU General Purpose Register R14 XXXXh R15 CP 30 FFh CPU General Purpose Register R15 XXXXh Semiconductor Group B 2 SIEMENS SAB 80C166 Registers B 1 2 Byte Registers Name Physical 8 Bit Description Reset Address X Address Value RLO CP 0 FOh CPU General Purpose Register RLO XXh RHO CP 1 F1ih CPU General Purpose Register RHO XXh RL1 CP 2 F2h CPU General Purpose Register RL1 XXh RH1 CP 3 F3h CPU General Purpose Register RH1 XXh RL2 CP 4 F4h CPU General Purpose Register RL2 XXh RH2 CP 5 F5h CPU General Purpose Register RH2 XXh RL3 CP 6 F6h CPU General Purpose Register RL3 XXh RH3 CP 7 F7h CPU General Purpose Register RH3 _ XXh RL4 CP 8 F8h CPU General Purpose Register RL4 XXh RH4 CP 9 F9h CPU General Purpose Register RH4 XXh RL5 CP 10
121. a Booth algorithm Each instruction implicitly uses the 32 bit MD register MDL low 16 bits MDH high 16 bits Whenever either half of this register is writ ten into the MDRIU flag Multiply or Divide Register In Use in the MDC register is set It is cleared whenever the MDL register is read Because an interrupt can be acknowled ged before the MD register contents are saved this flag is required to alert interrupt routines which require the use of the multiply divide hardware of state preserved in the MD register This register however must only be saved when an interrupt routine re quires use of the MD register and a previous task has not saved the current result This flag is easily tested by the Jump on Bit instructions Multiplication is simply performed by specifying the correct signed or unsigned version of the instruction The result is then stored in the MD register The overflow flag V is set if the resuit from a multiply or divide instruction is greater than 16 bits This flag can then be used to determine whether both word halves of the MD register must be transferred from the MD register One must first move the high portion of the MD register into the register file or memory to ensure that the MDRIU flag reflects the correct state The following instruction sequence performs an unsigned 16 by 16 bit multiplication SAVE JNB MDRIU START Test if MD was in use SCXT MDC 0 Save and clear control register only required if
122. a Page Pointer Updating An instruction which calculates a physical operand address via a particular DPPn n 0to3 register is mostly not capable of using a new DPPn register value which is to be updated by an immediately preceding instruction Thus if one surely wants the new DPPn register value to be used one must put at least one instruction between a DPPn changing instruc tion and a subsequent instruction which implicitly uses DPPn via a long or indirect addres sing mode as shown in the following example In MOV OPPO 4 select data page 4 via DPPO lied io must not be an instruction using DPPO for long or in direct addresses from 0000h to 3FFFh Iln 2 MOV 0000h R1 move contents of GPR 1 to address location 10000h in data page 4 supposed that segmentation is not disabled Explicit Stack Pointer Updating Any of the RET RETI RETS RETP or POP instructions is not capable of correctly using a new SP register value which is to be updated by an immediately preceding instruction Thus if one wants the new SP register value to be used without erroneously performed stack accesses one must put at least one instruction between an explicitly SP writing and any subsequent of the just mentioned implicitly SP using instructions as shown in the following example In MOV SP 0FA40h select a new top of stack ined o must not be an instruction popping operands from the system stack ln 2 POP RO pop the word value
123. able register is used to point to the top of the internal system stack TOS The SP register is pre decremented whenever data is to be pushed onto the stack and it is post incremented whenever data is to be popped from the stack Thus the system stack grows from higher toward lower memory locations Siemens Aktiengesellschaft 5 29 Central Processing Unit CPU Figure 5 14 Implicit CP Use by Short 8 Bit Addressing Specified by reg or bitoff Internal RAM Must be situated in the internal RAM area A 1 for byte GPR accesses A 2 for word GPR accesses Figure 5 15 Stack Pointer Register SP FE12h 09h Reset Value FCOOh sp continuation ee eee Bit tied to 0 by hardware because only even SP contents are allo isp SP 10 1 Modifiable portion of the SP register SP 15 11 Bits tied to 1 by hardware This allows possible conterits from F800h through FFFEh Note however that the physical system Stack is forced to internal RAM addresses by hardware as shown in table 5 7 Siemens Aktiengesellschaft 5 30 Central Processing Unit CPU Since the least significant bit of the SP register is tied to 0 and bits 11 to 15 are tied to 1 by hardware the SP register can only point to even word addresses from OF800h to OFFFEh After reset the SP register is initialized to FCOOh The SP register can be updated via any instruction which is capable of modifying an SFR Based on the internal instructi
124. ake up bit used in multiprocessor communication 8 bit data wake up bit mode D8 wet 2 nd Stat DO D1 D2 D3 D4 D5 D7 Parity Stop Stop Bit LSB wae Bit Bit Figure 8 4 5 9 Bit Data Frame Asynchronous Transmission A transmission is initiated by writing the data to be transmitted into the transmit data buffer register SOTBUF or S1TBUF respectively However a transmission will only be performed if the corresponding baud rate generator run bit SOR 1 or S1R 1 at the time the write operation to the transmit buffer occurs Transmission then starts at the next overflow of the divide by 16 counter see figure 8 4 3 First the start bit will be output on the associated transmit data output pin TXDO or TXD1 followed by the selected number of data bits LSB first In the two modes with parity bit generation the parity bit will automatically be generated by hardware and inserted at the MSB position of the data frame during transmission When one stop bit has been selected for the data frame SOSTP 0 or S1STP 0 the corresponding transmit interrupt request flag SOTIR or S1TIR will be set after the last bit of the data frame including the parity or wake up bit has been sent out otherwise it will be set after the first stop bit has been sent out Semiconductor Group 8 67 SIEMENS Peripherals When a write operation to the transmit data buffer is performed while a transmission on the respective channel is in progress th
125. alue A 1 for byte operations A 2 for word operations GPR Address GPR Address A optional step The following table 6 3 gives an overview of the particular indirect addressing modes of the SAB 80C166 Table 6 3 Indirect Addressing Modes Mnemonic Particularity Rw Normally any word GPR can be used as indirect address pointer For some instructions however only the first four word GPRs can be used as indirect address pointers Rw The specified indirect address pointer is automatically post incremen ted by either 1 for byte data operations or 2 for word data opera tions Rw The specified indirect address pointer is automatically pre decremented by either 1 for byte data operations or 2 for word data operations Rw data16 A 16 bit constant and the contents of the indirect address pointer are added before the long 16 bit address is calculated Siemens Aktiengesellschaft 6 8 Instruction Set Overview 6 2 4 Constants The SAB 80C166 instruction set also supports the use of wordwide or bytewide immediate constants For an optimum utilization of the available code storage these constants are represented in the instruction formats by either 3 4 8 or 16 bits Thus short constants are always zero extended while long constants are truncated if necessary to match the data format required for the particular operation Table 6 4 Data Type Adaption of Immediate Constants Word Operation
126. alues the corresponding external bus configuration modes and the ports used as interface to the external address and or data bus es Table 9 1 Initial External Bus Configuration During Reset Ports used for Singie Chip Mode No External Bus Internal ROM enabled 18 Bit Address 8 Bit Data Time Muitiplexed internal ROM disabled 18 Bit Address 16 Bit Data Time Multiplexed Internal ROM disabled 18 Bit Address 16 Bit Data Non Muitipiexed Internai ROM disabled Siemens Aktiengesellschaft 9 2 Externai Bus Interface As just mentioned the BTYP field in the SYSCON register is initialized during reset After reset the values on the EBC pins stay non significant until the next system reset occurs In the meantime the SAB 80C166 s external bus configuration is determined only by the contents of the BTYP bit field If the controller has been initialized to the single chip mode once an external bus can be reconfigured later because the BTYP bit field stays modi fiable for the software Any other initial external bus configuration can not be changed via software because the BTYP bit field has a read only access state in those cases When the single chip mode is selected during reset the ROM Enable Bit ROMEN in the SYSCON register is set to 1 signifying that internal ROM accesses are globally enabled In any other initial external bus configuration the ROMEN bit is cleared and therefore internal
127. ammable as inputs or outputs via direction registers Each port line has one programmable alternate input or output function associated with it Port 0 and Port 1 may be used as the address and data lines when accessing external memory Port 4 outputs the additional segment address bits A16 and A17 when segmentation is enabled The pins of Port 2 serve as capture inputs or compare outputs for the CAPCOM unit Port 3 includes alternate input output functions of CAPCOM timer TO the general purpose timer blocks GPT1 2 and the serial channels ASCO 1 In addition Port 3 provides the bus interface control signals WR BHE READY and the system clock CLKOUT Port 5 is used for the analog input channels to the A D converter All ports have Schmitt Trigger input characteristics except when used as external data bus and as analog inputs to the A D converter The following subsections first give a general description of Ports 0 through 4 then each of these ports is described in detail Port 5 will be discussed separately in section 10 2 10 1 Ports 0 through 4 Each of the Ports 0 through 4 has its own port data register PO through P4 and direction register DPO through DP4 Figure 10 1 shows the 16 bit data registers PO through P3 for Ports 0 through 3 and figure 10 2 shows the corresponding Port Direction control registers DPO through DP3 Figure 10 3 shows the 8 bit data register P4 for Port 4 Port 4 is actually a 2 bit port but the data a
128. ammed to different group priorities Otherwise undetermined results may occur for the interrupt vector Using the group priorities 0 through 3 up to 4 sources can be programmed to the same priority level The advantage of this priority scheme is that the order for servicing of simultaneous re quests from different sources on the same priority level is not fixed by the system but can be assigned via software In all cases the source on the highest priority level which also has the highest group prio rity wins the current round of prioritization Whether the request of this source will be accepted by the CPU or not depends on the current CPU priority If the priority of the re questing source is higher the request is acknowledged and the CPU passes control to the source s interrupt vector Siemens Aktiengesellschaft 7 14 interrupt and Trap Functions The interrupt system supports 16 different priority levels Only 15 of those levels are actually effective priority levels because requests on level 0 are not capable of interrup ting the CPU Therefore up to 15 interrupt service routines on different priority levels can be nested In the following section a method will be described which allows the limitation of nested interrupt leveis to a number less than 15 This may be desirable for reasons of stack efficiency Normally the 2 highest priority levels level 15 and 14 are used by PEC requests Those levels can also be used to process a
129. anch to the appropriate trap interrupt vector is made This sequence is described in detail in chapter 7 All trap and interrupt routines require use of the RETI return from interrupt instruction to exit from the called routine This instruction restores the system state from the system stack and then branches to the location where the trap or interrupt occurred Siemens Aktiengesellschaft 13 10 Support Tools 14 Support Tools A majority of the application areas where the SAB 80C166 will be used is in embedded systems where one has little external control over the internal working of the product The debugging and testing of the software and hardware in this type of system is normally a difficult and time consuming process Thorough testing is essential to ensure that the end product performs to the required specifications To provide an effective debugging environment the hardware and software development tools should be easy to use and provide maximum flexibility The following sections will cover the hardware and software development tools provided with the SAB 80C166 14 1 Hardware Support In order to determine that both the hardware and software components of the target system are working the internal state of the microcontroller must be accessible Aspecial tool is therefore required to provide the capability of monitoring and controlling the be havior of the microcontroller in a target system This device known as an In Cir
130. annel is used see section 7 3 2 6 In the following a Source Pointer will be referred to as SRCPx and a Destination Pointer will be referred to as DSTPx where x indicates the number oftheassociated PEC Service Channel x 2 0 through 7 Figure 7 6 shows the mapping ofthe PEC Source and Destina tion Pointers into the internal RAM Note that for all PEC data transfers the data page pointers DPPO through DPP3 are NOT used The addresses contained in the PEC source and destination pointers are interpreted as direct 16 bit memory addresses in segment 0 so that data transferscan be performed between any two memory locations within the first four data pages pages 0 through 3 Figure 7 6 Mapping of PEC Source and Destination Pointers into the Internal RAM 15 15 0 M Ml PEC Source and Destination Pointers Internal RAM DSTPO SRCPO External Memory PEC RAM Location PEC RAM Location Source Pointer Word Address Destination Pointer Word Address Siemens Aktiengesellschaft 7 13 Interrupt and Trap Functions 7 2 8 Prioritization of Interrupt and PEC Service Requests Interrupt and PEC service requests from all sources that are enabled compete for service in the prioritization process The prioritization sequence is repeated every instruction _ cycle 7 2 3 1 Enabling and Disabling of Interrupt Sources Enabling and disabling of interru
131. anual When SxBRS 1 the baud rate of the respective serial interface x is determined by the formulas Basyncx 2 3 fosc 64 lt SxBRL gt 1 and Bsyncx 2 3 fosc 16 lt SxBRL gt 1 Thus when bit SxBRS is set the current baud rate formulas are multiplied with 2 3 Figure 2 1 shows the new extended functionality of the serial channels control registers SOCON and S1CON Semiconductor Group D 3 SIEMENS SAB 80C166 83C166 3 Implementation of a 16 18 Bit Address 8 Bit Data Non Multiplexed Bus Mode Besides the three bus modes currently implemented in the SAB 80C166 a fourth bus mode 8 bit data 16 18 bit address non multiplexed will be implemented Thus all possible combinations of data bus width 8 bit 16 bit and multiplexed non multiplexed operation are available In the new bus mode Port 1 is used as a word wide address output while the lower half of Port 0 is used as the byte wide data bus Since two independent buses are used to access external memory or peripherals no time multiplexing and no additional address latch is required when operating in this bus mode If segmentation is enabled Port 4 is additionally used to output the two most significant bits of the required 18 bit address For selecting this new bus mode during reset and normal operation see Chapter 5 of this specification Note The upper half of Port 0 can not be used for general purpose I O 4 Mapping the internal ROM address space Beg
132. any instruction which is capable of addressing an SFR Siemens Aktiengesellschaft 5 36 Central Processing Unit CPU Figure 5 21 Constant Ones Register ONES FE1Eh 8Fh Reset Value FFFFh 15 14 13 12 11 10 9 8 pa p agorcEa pop pp 7 6 5 4 3 2 1 0 Ls el oru ee ee Bod ONES 15 0 All of the bits are tied to 1 by hardware The entire ONES register is read only 5 3 14 ZEROS Constant Zeros Register All bits of this bit addressable register are tied to 0 by hardware This register is read only The ZEROS register can be used as a register addressable constant of all zeros i e for bit manipulation or mask generation It can be accessed via any instruction which is capable of addressing an SFR Figure 5 22 Constant Zeros Register ZEROS FF1Ch 8Eh Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol Position Function y O 0 ZEROS 15 0 All of the bits are tied to 0 by hardware The entire ZEROS register is read only Siemens Aktiengesellschaft 5 37 instruction Set Overview 6 Instruction Set Overview This chapter describes the SAB 80C166 s instruction set In the first section a short over view of all available instructions ordered by particular instruction classes is given The se cond section describes which addressing modes can basically be used Section 6 3 contains a description of the condition codes available for conditional branch instructions
133. ary timers T2 and T4 in timer and gated timer mode Note that some numbers may be rounded to 3 significant digits Figure 8 2 5 shows a block diagram of timer T3 in timer mode Semiconductor Group 8 30 SIEMENS Peripherals Table 8 2 3 GPT1 Timer Input Frequencies Resolution and Periods fosc 40MHz Timer Input Selection T2I TSI TAI 000b 001b 010b 011b 100b 101b 110b 111b Prescaler for fosc 16 32 64 128 256 512 1024 2048 Input Frequency 2 5 1 25 625 312 5 156 25 78 125 39 06 19 53 MHz MHz kHz kHz kHz kHz kHz kHz Resolution 400ns 800ns 1 6us 3 2us 6 4us 12 8 us 25 6 us 51 2 us Period 26 ms 52 5ms 105 ms 210 ms 420 ms 840 ms 1 68s 3 36 s Interrupt Request Figure 8 2 5 Block Diagram of Core Timer T3 in Timer Mode 8 2 1 1 2 Gated Timer Mode In the gated timer mode the same options for the input frequency as for the timer mode are available see table 8 2 3 However the input clock to the timer in this mode is gated by the external input pin T3IN Timer T3 External Input which is an alternate function of P3 6 Figure 8 2 6 shows a block diagram of the core timer in this mode The gated timer mode is selected by setting bit T3M 1 T3CON 4 to 1 Bit T3M 0 T3CON 3 selects the active level of the gate Pin T3IN P3 6 must be configured as input i e direction control bit DP3 6 must contain O If T3M 0 0 the timer is enabled when T
134. as transmit data input or receive data output Channel ASC1 uses pins RXD1 P3 9 and TXD1 P3 8 for these purposes Semiconductor Group 8 72 SIEMENS Peripherals 8 4 1 2 1 Synchronous Data Transmission For data transmission the transmit data buffer register SOTBUF S1TBUF is loaded with the byte to be transmitted If bit SOR 1 and SOREN 0 in register SOCON S1R 1 and S1REN 0 in S1CON at that time the LSB of the transmit buffer register will appear at pin RXDO RXD1 within 4 state times after this write operation has been executed Subsequently the contents of the transmit buffer register are shifted out synchronous with the clock at the corresponding shift clock output pin TXDO TXD1 After the bit time for the 8th bit both pins TXDO and RXDO TXD1 and RXD1 will go high the transmit interrupt request flag SOTIR S1TIR is set and serial data transmission stops While a synchronous data transmission is in progress any write operation to the transmit buffer register of this serial channel will abort the current transmission and start a new transmit process When the receiver enable bit SOREN or S1REN is set to 1 during a transmission unpredictable results may occur on the affected channel In order to configure TXDO P3 10 or TXD1 P3 8 as shift clock output both the corresponding port output bit latch P3 10 or P3 8 and the direction control bit DP3 10 or DP3 8 must be set to 1 Pin RXDO P3 11 or RXD1 P3 9 is each configured as transmit
135. asing complexity of embedded control applications a significant increase in CPU performance and peripheral functionality over conventional 8 bit controllers is requi red of microcontrollers for high end embedded control systems n order to achieve this high performance goal Siemens has decided to develop its new SAB 80C166 family of 16 bit CMOS microcontrollers without the constraints of backward compatibility However hardware and software concepts which have successfully been established in Siemens s popular SAB 8051x family of 8 bit controllers have been integrated into the new Siemens SAB 80C166 family 1 4 The SAB 80C166 Family of Microcontrollers The microcontrollers of the new Siemens SAB 80C166 family have been designed to meet the high performance requirements of real time embedded control applications The architecture of the SAB 80C166 family has been optimized for high instruction throughput and minimum response time to external stimuli Intelligent peripheral subsystems have been integrated to reduce the need for CPU intervention to a minimum extent The high flexibility of this architecture allows to serve the diverse and varying needs of different application areas such as automotive industrial control or data communications The core of the SAB 80C166 family has been developped with a family concept in mind All family members will utilize the same efficient control optimized instruction set and soft ware development tools
136. ate Data Output line is in its inactive state which is a high level 1 Write Direction Direction Latch DP3 y Read DP3 y Read Alternate Buffer Data Output Write Port P3 1 TEOUT P3 3 T3OUT Read Port P3 y P3 8 TXD1 P3 10 TXDO P3 13 WR P3 15 CLKOUT y 1 3 8 10 13 15 Figure 10 10 Block Diagram of a Port 3 Pin with an Alternate Output Function Semiconductor Group 10 12 SIEMENS Parallel Ports 10 1 3 3 Port 3 Pin BHE Figure 10 11 shows the block diagram of pin P3 12 BHE which is the seventh Port 3 pin with only an alternate output function Since the BHE signal might be required directly after reset when an external 16 bit data bus mode multiplexed or non multiplexed is selected through pins EBC1 and EBCO there is no way the user can configure the BHE pin Thus it will be switched automatically to the alternate function When an external 16 bit data bus mode is selected AND the BHE function is enabled through bit BYTDIS 0 in register SYSCON default after reset the two multiplexers in the port data output line and the port direction control line are switched The direction is set to 1 output and the pin is controlled by the Alternate Data Output line If the BHE pin is not required in an application the user can disable the function by setting bit BYTDIS to 1 The pin can then be used for general purpose I O Write DP3 12 Direction Latch DP3 12 Read DP3 12 Alternate
137. ation of Core Timer T3 and an Auxiliary Timer 8 2 1 2 4 Reload Mode Reload mode is selected by programming the mode control fields T2M or T4M to 100b In reload mode the core timer T3 is reloaded with the contents of an auxiliary timer register Two different sources can be selected to cause a reload of the core timer The options are programmed by the input selection bits of bit fields T2l and T4l in registers T2CON or TACON as shown in table 8 2 7 When programmed for reload mode the respective auxiliary timer T2 or T4 stops independent of its run flag T2R or T4R Table 8 2 7 GPT1 Auxiliary Timers Reload Trigger Selection xz 2 4 T21 T4l Reload on 2 1 0 0 0 0 No Transition Selected Tx Disabled 0 0 1 Positive External Transition on TxIN 0 1 0 Negative External Transition on TxIN 0 1 1 Positive and Negative External Transition on TxIN 1 0 0 No Transition Selected Tx Disabled 1 0 1 Positive Transition of T3OTL 1 1 0 Negative Transition of T3OTL 1 1 1 Positive and Negative Transition of T3OTL Semiconductor Group 8 38 SIEMENS Peripherals When bit T21 2 0 or bit T41 220 the source which can cause a reload is the external input pin T2IN for timer register T2 or pin TAIN for timer register T4 One can select either a positive a negative or both a positive and a negative transition at these input pins to cause a reload When a selected transition is detected at the input pin T2IN or
138. ator is illustrated in table 8 2 9 This table also applies to GPT2 auxiliary timer T5 Note that the numbers may be rounded to 3 significant digits Table 8 2 9 GPT2 Timer Input Frequencies Resolution and Periods fosc 40MHz Timer Input Selection T5I T6l 000b 001b 010b 011b 100b 101b 110b 111b Prescaler for fosc 8 16 32 64 128 256 512 1024 Input Frequency 5 2 5 1 25 625 312 5 156 25 78 125 39 06 MHz MHz kHz kHz kHz kHz kHz kHz Resolution 200ns 400 ns 800 ns 1 6us 3 2 us 6 4 us 12 8 us 25 6 us Period 13ms 26ms 52 5ms 105 ms 210 ms 420 ms 840 ms 1 68 s An overflow or underflow of timer T6 will clock the toggle bit T6OTL in control register T6CON T6OTL can also be set or reset by software Bit TGOE Alternate Output Function Enable in register T6CON enables the state of TGOTL to be an alternate function of the external output pin TGOUT P3 1 For that purpose a 1 must be written into port data latch P3 1 and pin T6OUT P3 1 must be configured as output by setting direction control bit DP3 1 to 1 If T6OE 1 pin TOUT then outputs the state of T6OTL If TEOEZO0 pin TOUT can be used as a general purpose O pin In addition T6OTL can be used as the trigger source for the counter function of auxiliary timer T5 For this purpose the state of TEOTL does not have to be available at pin TGOUT because an internal connection is provided for this option This feat
139. be individually programmed for input or output via the respective direction control bit DPx y Figure 10 5 shows a general block diagram of a port pin as it is configured when used as a general purpose l O port Port pins selected as inputs DPx y 0 are placed into a high impedance state since the output buffer is disabled This is the default configuration after reset During reset all port pins are configured for input When exiting reset while no external bus function is selected all port pins remain in input mode unless configured otherwise by the user When an external bus is selected the corresponding port pins are switched to the direction required by the selected bus type This is explained in detail in the following sections Semiconductor Group 10 4 SIEMENS Parallel Ports Write DPx y Direction Latch DPx y Read DPx y Read Buffer Write Port Px y Output Latch Output Buffer Read Port Px y 4 0 4 Read 5 for x 0 3 1 Buffer for x 4 Figure 10 5 Block Diagram of a Port 0 through 4 General Purpose I O Port The logic level of a pin is clocked into the input latch once per state time regardless whether the port is configured for input or output A write operation to a port pin configured as an input causes the value to be written into the port output latch while a read operation returns the latched state of the pin itself A read modify write operation reads the value of the pin modifies it and wr
140. be specified either by software or by the external input pin T3EUD Timer T3 External Up Down Control Input which is the alternate input function of port pin P3 4 These options are selected by bits T3UD and T3UDE in control register T3CON When the up down control is done by software bit T3UDE 0 the count direction can be altered by setting or clearing bit T3UD When T3UDE 1 pin T3EUD is selected to be the controlling source of the count direction However bit T3UD can still be used to reverse the actual count direction as listed in table 8 2 2 If T3UD 0 and pin T3EUD shows a low level the timer is counting up With a high level at T3EUD the timer is counting down If T3UD 1 a high level at pin T3EUD specifies counting up and a low level specifies counting down The count direction can be changed regardless of whether the timer is running or not When pin T3EUD P3 4 is used as external count direction control input its corresponding direction control bit DP3 4 must be set to O Semiconductor Group 8 29 SIEMENS Peripherals Table 8 2 2 GPT1 Core Timer T3 Count Direction Control Pin T3EUD Bit TSUDE Bit TSUD Count Direction X 0 0 Count Up X 0 1 Count Down 0 1 0 Count Up 1 1 0 Count Down 0 1 1 Count Down 1 1 1 Count Up Timer 3 Output Toggle Latch An overflow or underflow of timer T3 will clock the toggle bit T3OTL in control register T3CON T3OTL can also be set or reset by software Bit TSO
141. ble by changing the CSP register contents by means of the parti cular branch instructions JMPS and CALLS Siemens Aktiengesellschaft 4 7 Memory Organization External word and byte data can only be accessed via indirect or long 16 bit addressing modes in collaboration with the DPP registers There is no short addressing mode for ex ternal operands Any word data access is made to an evenbyte address Thus the highest possible word data storage locations in the external memory are address OF9FEh in seg ment 0 and addresses xFFFEh in all other segments x 1 2 3 For PEC datatransfers the external memory in segment 0 can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers The external memory is not provided for single bit storage and thus it is not bit addres sable Whenever a reset a hardware trap or an interrupt occurs or whenever a software TRAP instruction is executed and provided that internal ROM accesses are disabled program execution branches to an implicit external memory address independent of the current CSP register contents expecting a jump vector being situated there For detailed infor mation about the trap and interrupt jump vector table see section 7 1 Interrupt System Structure 4 3 Internal RAM The SAB 80C166 contains 1 Kbyte of on chip dual port RAM which is organized in 512 16 bytes Internal RAM accesses are always enabied The system stack the
142. by bit field T5l in control register T5CON as shown in table 8 2 10 Figure 8 2 25 shows a block diagram of timer T5 in this mode Table 8 2 10 Auxiliary Timer T5 Counter Mode Input Selection T5I Counter T5 is Incremented Decremented on 2 1 0 0 X X No Transition Selected T5 Disabled 1 0 0 No Transition Selected T5 Disabled 1 0 1 Positive Transition of TEOTL 1 1 0 Negative Transition of T6OTL 1 1 1 Positive and Negative Transition of T6OTL Semiconductor Group 8 49 SIEMENS Peripherals Interrupt Request Figure 8 2 25 Block Diagram of GPT2 Auxiliary Timer T5 in Counter Mode This mode can be used to concatenate the core timer T6 and the auxiliary timer T5 to form a 32 bit or a 33 bit timer 16 bit timer T6 T6OTL 16 bit timer T5 see also section 8 2 1 2 3 The count directions of the two timers are not required to be the same which offers a wide variety of different configurations Figure 8 2 26 shows a block diagram for the concatenation of timers T5 and T6 Interrupt Request Interrupt Request T5UD Note Line only affected by over underflows of T6 but NOT by software modifications of TGOTL Figure 8 2 26 Concatenation of Timers T5 and T6 Semiconductor Group 8 50 SIEMENS Peripherals 8 2 2 2 3 Timer T5 Interrupt Control When timer T5 overflows from FFFFh to 0000h when counting up or when it underflows from 0000h to FFFFh when counting down the inter
143. ce amagna ieorr Target ee DECODE 1st loop iteration Repeated loop iteration 5 1 4 Particular Pipeline Effects Since up to four different instructions are processed simultaneously additional hardware has been spent in the SAB 80C166 to consider all causal dependencies which may exist on instructions in different pipeline stages without a loss of performance This extra hardware i e for forwarding operand read and write values avoids thatthe pipeline becomes noticeable for the user in most of the cases However there are some very rare cases where one must pay attention to the circums tance that the SAB 80C165 is a pipelined machine Intelligent SAB 80C166 tools like the simulator and the emulator support the user by easing the association with the following particular pipeline effects Context Pointer Updating An instruction which calculates a physical GPR operand address via the CP register is mostly not capable of using a new CP value which is to be updated by an immediately preceding instruction Thus if one surely wants the new CP value to be used one must put at least one instruction between a CP changing and a subsequent GPR using instruc tion as shown in the following example Siemens Aktiengesellschaft 5 5 Central Processing Unit CPU In SCXT CP 0FCOOh select a new context Ine i e must not be an instruction using a GPR In 2 MOV RO dataX write to GPR O in the new context Dat
144. cification of an instruction al ways refers to the average execution time due to pipelined parallel instruction processing Figure 5 1 Sequential Instruction Pipelining 1 Machine Cycle at Siemens Aktiengesellschaft 5 3 Central Processing Unit CPU 5 1 2 Standard Branch instruction Processing Instruction pipelining helps to speed sequential program processing In the case that a branch is taken the instruction which has already been fetched providently is mostly not the instruction which must be decoded next Thus at least one additional machine cycle is normally required to fetch the branch target instruction This extra machine cycle is provided by means of an injected instruction as shown in figure 5 2 Figure 5 2 Standard Branch Instruction Pipelining 1 Machine ici Ld FETCH a langer tarncer 1 tancet 2 TARGET 3 lrancet raRGET 1 WRITE BACK ae ai If a conditional branch is not taken there is no deviation from the sequential program flow and thus no extra time is required In this case the instruction after the branch in struction will enter the decode stage of the pipeline at the beginning of the next machine cycle after decode of the conditional branch instruction 5 1 3 Cache Jump Instruction Processing A jump cache has been incorporated in the SAB 80C166 as an optimization of conditional jumps which are processed repeatedly within a loop Whenever a jump on cache istaken the e
145. compare signal output pin for compare register CCx in compare mode 1 P2 x must be configured as output i e the corresponding direction control bit DP2 x in register DP2 must be set to 1 With this configuration the initial state of the output signal can be programmed or its state can be modified at any time by writing to bit latch P2 x However if P2 x is written to by software at the same time it would be altered by a compare event the software write will have priority In this case the hardware triggered change will not become effective For operation in the double register compare mode compare mode 1 must be selected for the registers CCO to CC7 see section 8 1 2 2 5 for details on the double register mode Figure 8 1 12 shows the timing example from the previous section now for compare mode 1 The functional block diagram of a compare register in compare mode 1 is included in figure 8 1 10 of the previous section Note that in compare mode 1 the port latch is toggled upon each compare event Contents of Ty FFFFh Compare Value cv2 Compare Value cv1 0000h Interrupt moauesisy Reload Value lt TyREL gt TyIR CCxIR COXIB TyIR COxIR CCxIR TyIR State of COxlO Event 1 Event 42 Event 3 Event 4 t CCx cv2 CCx cv1 CCx cv2 CCx cv1 Figure 8 1 12 Timing Example for Compare Mode 1 Semiconductor Group 8 17 SIEMENS Peripherals 8 1 2 2 3 Compare Mode 2 Compare mode 2 is an in
146. conversion mode the analog level on a specified channel is once sampled and converted into a digital result In the Single Channel Continous mode the analog level is repeatedly sampled and converted without software intervention In the Auto Scan mode the analog levels on a prespecified number of channels are sequentially sampled and converted In the Auto Scan Continuous mode the number of prespecified channels is repeatedly sampled and converted The Peripheral Event Controller PEC may be used to automatically store the conversion results into a table in memory for later evaluation without requiring the overhead of ertering and exiting interrupt routines for each data transfer 3 8 Serial Channels Serial communication with other microcontrollers processors terminals or external peripheral components is provided by two serial interfaces with identical functionality Serial Channel 0 ASCO and Serial Channel 1 ASC1 Semiconductor Group 3 7 SIEMENS System Description They are upward compatible with the serial ports of the Siemens SAB 8051x microcontroller family and support full duplex asynchronous communication up to 625 Kbaud and half duplex synchronous communication up to 2 5 Mbaud Two dedicated baud rate generators allow to set up all standard baud rates without oscillator tuning For transmission reception and erroneous reception 3 separate interrupt vectors are provided for each serial channel In the synchronous mod
147. cuit Emul ator ICE has the function of emulating in real time the execution of an application pro gram and to provide the hardware stimuli characteristics of the microcontroller In order for an ICE to be an effective debugging tool it has useful functions for both hard ware and software development These functions include the following Real Time In order to test under real conditions the emulator executes the applica tion program in the target system The operation will be done in real time with the target systems original clock without adding wait states due to emulator functions Memory The full compliment of 256 Kbytes of ICE memory will be supported Host Link Since the software will change many times during the program develop ment phase an efficient means of downloading and uploading from to the host will be supported This provides the ability of changing program or data memory to accom modate specific test situations Trigger Conditions in order to allow the user to control the execution of the target system a flexible means of specifying the trace and breakpointtriggers will be provided Trigger conditions for both tracing and halting execution will include IP addresses IP ranges opcode values operation results and operand addresses Because the system hardware signals may be asynchronous to the execution of software some problems may occur as a result of a complicated series of events Asaresult the I
148. d T1 The primary use of the timers TO and T1 is to provide two independent time bases 400 ns maximum resolution for the capture compare registers but they may also be used independent of the capture compare registers The functions of the timers TO and T1 are controlled by the bit addressable 16 bit control register TO1CON shown in figure 8 1 3 T1 is controlled by the upper byte and TO is controlled by the lower byte of TO1CON TO1CON FF50h A8h l PES Value eee Figure 8 1 3 CAPCOM Timer 0 and 1 Control Register T01CON Semiconductor Group 8 5 SIEMENS Peripherals Symbol Position Function TOl TO1CON 2 0 Timer Counter 0 Input Selection For Timer mode see table 8 1 1 For Counter mode see table 8 1 2 TOM T01CON 3 Timer Counter 0 Mode Selection TOM 20 Timer Mode TOM 2 1 Counter Mode TOR T01CON 6 Timer Counter 0 Run Bit TOR 20 Timer Counter 0 disabled TOR 1 Timer Counter 0 enabled T1I TO1CON 10 8 Timer Counter 1 Input Selection For Timer mode see table 8 1 1 For Counter mode see table 8 1 2 T1M T01CON 1 1 Timer Counter 1 Mode Selection TiM 20 Timer Mode TiM 21 Counter Mode TA1R T01CON 14 Timer Counter 1 Run Bit TIR 20 Timer Counter 1 disabled TIR 21 Timer Counter 1 enebled reserved TOR and T1R are the run flags of TO and T1 respectively They allow for enabling and disabling the timers The following description of the timer modes and operation always applies to the
149. de eee eee 9 3 16 18 Bit Address 8 Bit Data Multiplexed Bus 9 4 16 18 Bit Address 16 Bit Data Multiplexed Bus Siemens Aktiengesellschaft 5 Contents 9 5 9 6 9 6 1 9 6 1 1 9 6 1 2 9 6 2 9 6 2 1 9 6 2 2 9 7 9 7 1 9 7 2 9 7 3 9 8 10 10 1 10 1 1 10 1 2 10 1 3 10 1 3 1 10 1 3 2 10 1 3 3 10 1 3 4 10 1 4 10 2 11 11 1 11 2 11 3 11 4 11 5 12 12 1 12 2 12 3 Contents Page 16 18 Bit Address 16 Bit Data Non Multiplexed Bus 9 8 External Bus Transfer Characteristics 9 9 Muitiplexed Bus Transfer Characteristics lll 9 9 Multiplexed Bus Memory Reads llle 9 10 Multiplexed Bus Memory Writes lese een 9 11 Non Multiplexed Bus Transfer Characteristics Len 9 11 Non Multiplexed Bus Memory Reads sells 9 12 Non Multiplexed Bus Memory Writes 000 e eee eee 9 12 User Selectable Bus Characteristics 0005 9 12 Programmable Memory Cycle Time eee 9 13 Programmable Memory Tri State Time 0 0 eee eee 9 16 Read Write Signal Delay 0 cee cece e eee 9 18 External Memory Access via the Data Rea y Signal 9 19 Parallel Ports oca eR AS s OPERE 10 1 Ports 0 through 4 uude PX vas E RARE SES 10 1 Pot O and POT a beo rape Ga dA DE ae erence etaed ho avs 10 6 POM 2 1o ufo cta htt cup vk oe Ud o pru
150. de the clocks to the CPU and to the peripherals are turned off In the SAB 80C166 the oscillator is completely switched off Like in Idle mode ail port pins which are configured as general purpose output pins output the last data value which was written to their port output latches When the alternate output function of a port pin is used by a peripheral the state of this pin is determined by the last action of the peripheral before the clocks were switched off In particular if CLKOUT the alternate output function of P3 15 had been enabled it is not active during Power Down mode All external bus actions are completed before Idle or Power Down mode is entered However Idle or Power Down modes can NOT be entered if READY is enabled but has not been deasserted during the last bus access The following table 12 1 presents a summary of the state of all SAB 80C166 output pins during idle and Power Down modes Siemens Aktiengesellschaft 12 3 Power Reduction Modes Abbreviations used AF State determined by last activity of Alternate Output Function ADDR_H Address High Byte DATA Data in Port Output Latch 16 8 16 18 bit Address 8 bit Data Multiplexed Bus 16 16 16 18 bit Address 16 bit Data Non Multiplexed Bus non segm Segmentation Disabled Table 12 1 Output Pins Status during Idle and Power Down Mode Power Down Mode NO external bus enabled idle Mode NO external external bus bus enabled enabled
151. digital result while the upper four bits ADDAT 15 12 represent the number of the channel which was converted Register ADDAT is not bit addressable The data remains in ADDAT until it is overwritten by the data of the next conversion Semiconductor Group 8 57 SIEMENS Peripherals Table 8 3 2 Analog Input Channel Selection ADCH Selected Channel 3 2 1 0 0 0 0 0 ANO Analog Input Channel 0 0 0 0 1 AN1 Analog Input Channel 1 0 0 1 0 AN2 Analog Input Channel 2 0 0 1 1 AN3 Analog Input Channel 3 0 1 0 0 AN4 Analog Input Channel 4 0 1 0 1 AN5 Analog Input Channel 5 0 1 1 0 AN6 Analog Input Channel 6 0 1 1 1 AN7 Analog Input Channel 7 1 0 0 0 AN8 Analog Input Channel 8 1 0 0 1 AN9 Analog Input Channel 9 1 0 1 X reserved no channel selected 1 1 X X reserved no channel selected ADDAT FEAO0h 50h Reset Value 0000h 15 14 13 12 11 10 9 8 CHNR ADRES p 7 6 5 4 3 2 1 0 ADRES 7 0 Figure 8 3 4 A D Converter Result Register ADDAT Symbol Position Function ADRES ADDAT 9 10 10 bit Result of the A D Conversion CHNR ADDAT 15 12 4 bit Channel Number reserved Semiconductor Group 8 58 SIEMENS Peripherals In all 4 conversion modes a conversion is started by setting bit ADST 1 This will also set the busy flag ADBSY The converter then selects and samples the input channelspecified by the channel
152. ds and the remaining operands within the internal RAM space are written back A particularity of the SAB 80C166 are the so called injected instructions These injected instructions are internally generated by the machine to provide the time needed 9 pro cess instructions which cannot be processed within one machine cycle They are utomati cally injected into the decode stage of the pipeline and then they pass through the re maining stages as every standard instruction Program interrupts are performed by means of injected instructions too Although one will not notice these internally injected instruc tions in reality they are introduced here to ease the explanation of the pipeline in the following 5 1 1 Sequential Instruction Processing Each single instruction has to pass through each of the four pipeline stages regardless of whether all possible stage operations are really performed or not Since passing through one pipeline stage takes at least one machine cycle any single instruction takes at least four machine cycles to be completed Pipelining however allows parallel this means simultaneous processing of up to four instructions Thus most of the instructions seem to be processed during one machine cycle as soon as the pipeline has been filled once after reset see figure 5 1 Instruction pipelining increases the average instruction throughput considered over a cer tain period of time In the following any execution time spe
153. e one data byte is transmitted or received synchronously to a shift clock which is generated by the SAB 80C166 In the asynchronous mode an 8 or 9 bit data frame is transmitted or received preceded by a start bit and terminated by one or two stop bits For multiprocessor communication a mechanism to distinguish address from data bytes has been included 8 bit data wake up bit mode and a loop back option is available for testing purposes A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers A parity bit can automatically be generated on transmission or be checked on reception Framing error detection allows to recognize data frames with missing stop bits An overrun error will be generated if the last character received has not been read out of the receive buffer register at the time reception of a new character is complete 3 9 Watchdog Timer The Watchdog Timer of the SAB 80C166 represents one of the fail safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time The Watchdog Timer of the SAB 80C166 is always enabled after a reset of the chip and can only be disabled in the time interval until the EINIT end of initialization instruction has been executed Thus the chip s start up procedure is always monitored The Watchdog Timer of the SAB 80C166 is always enabled after a reset of the chip and can only be di
154. e IDLE instruction The Idle mode can also be terminated by a Non Maskable Interrupt through a high to low transition on the NMI pin After the idle mode has been terminated by an interrupt or NMI request the interrupt system performs a round of prioritization to determine the highest priority request In the case of an NMI request the NMI trap will always be entered Any interrupt request whose individual Interrupt Enable flag was set before the Idle mode was entered will terminate the Idle mode regardless of the current CPU priority The CPU will NOT go back into Idle mode when a CPU interrupt request is detected even when the interrupt was not serviced because of a higher CPU priority or a globally disabled interrupt system IEN 0 The CPU will ONLY go back into Idle mode when the interrupt system is globally enabled IEN 1 AND a PEC service on a priority level higher than the current CPU level is requested and executed The Watchdog Timer may be used for monitoring the Idle mode an internal reset will be generated if no interrupt or NMI request occurs before the Watchdog Timer overflows To prevent the Watchdog Timer from overflowing during Idle mode it must be programmed to a reasonable time interval before the Idle mode is entered Siemens Aktiengesellschaft 12 2 Power Reduction Modes 12 3 Status of Output Pins during Idle and Power Down Mode During Idle mode the CPU clocks are turned off while all peripherals continue t
155. e also has its own dedicated interrupt vector SOTINT is the transmit interrupt vector SORINT is the receive interrupt vector and SOEINT is the error interrupt vector for channel ASCO while S1TINT S1RINT and S1EINT are the corresponding interrupt vectors for ASC1 The cause of an error interrupt request framing parity overrun error can be identified by the error status flags in control registers SOCON and S1CON Note that unlike the error interrupt request flags SOEIR or S1EIR the error status flags SOFE SOPE SOOE or S1FE S1PE S10E are not reset automatically upon entry into the error interrupt service routine but must be cleared by software Figure 8 4 7 shows the organization of the interrupt control registers associated with the serial channels For more details on interrupts refer to chapter 7 Semiconductor Group 8 76 SIEMENS Peripherals SOTIC FF6Ch B6h Reset Value 0000h 6 5 4 3 2 SOTIR SOTIE ILVL SORIC FF6Eh B7h SOEIC FF70h B8h 7 6 5 S1TIC FF72h B9h 6 5 4 3 2 S1TIR S1TIE ILVL S1RIC FF74h BAh S1EIC FF76h BBh 7 6 5 Figure 8 4 7 Serial Channel Interrupt Control Registers Semiconductor Group 8 77 SIEMENS Peripherals 8 5 Watchdog Timer WDT To allow recovery from software or hardware failure a Watchdog Timer has been provided in the SAB 80C166 If the software fails to service this timer before an overflow occurs an internal hardware reset will be initiated Thi
156. e current transmission willbe aborted the associated output pin TXDO or TXD1 will go high and a new character frame will be sent with the data written to SOTBUF or S1TBUF at the next overflow of the divide by 16 counter Continuous data transfer can be achieved by using the transmit interrupt request to reload the transmit data buffer in the interrupt service routine or by PEC data transfer In order to use pin TXDO P3 10 or TXD1 P3 8 as transmit data output the corresponding port data output latch P3 10 or P3 8 must be set to 1 and the pin must be configured as output by setting its direction control bit DP3 10 or DP3 8 to 1 Asynchronous Reception Reception is initiated on channel ASCO by a detected 1 to 0 transition on pin RXDO if bit SOR 1 and SOREN 1 and on ASC1 by a 1 to 0 transition on RXD1 if S1R21 and S1REN 1 The receive data input pins RXDO and RXD1 are sampled at 16 times the rate of the selected baud rate The 7th 8th and 9th sample are examined by the internal bit detectors The effective bit value is determined by a majority decision in order to avoid erroneous results that may be caused by noise If the detected value is not a 0 when the start bit is sampled the receive circuit is reset and waits for the next 1 to 0 transition at pin RXDO or RXD1 respectively If the start bit proves valid the receive circuit continues sampling and shifts the incoming data frame into the receive shift register When the last stop bi
157. e eii Ere Rea een Whereas d vr med 8 25 GPU Cord Timer ls vss or udo PR esa do xA wees 8 27 Timer Mode iur ee erae ree Rb e EGAN E RR EROR 8 29 Gated Timer Mode oi sia xd xe ERRARE SIT ETE eerie 8 30 Co nter M de reu Sok i nea NUR Re Belge E RR CR 8 31 Interrupt Control for Core Timer T3 2 2 cee ee ee ee eee 8 32 GPT1 Auxiliary Timers T2 and T4 2 Le eee 8 32 Timer Mode 43 5 sso ga wat ee ed ewe ON aaa ere SR eee 8 34 Gated Timer Mode iussu uu een steerer UR R3 RE Oe ea 8 35 Gounter MOde 5 22 tesis dec eie Un UE eere DR Any Rl RET 8 35 Reload Mode i sw IRURE cde enu Bowie UR ee 8 37 Capture Mode 23 0 dig iia OR m RA od ieee wanna C 8 40 Inter pt Control ure chara and ee exe ERE E e 8 42 GPI2 Block iom ora annt agate eaMbe eed deu qr te 8 42 Siemens Aktiengesellschaft 4 8 2 2 1 GPT2 Core Timer T6 0 ee ee eee 8 2 2 1t Timer MOOG 2o y Rod ICE EEG RASS RE S 8 2 2 4 2 Timer T6 Interrupt Control llle 8 2 2 2 GPT2 Auxiliary Timer T5 0 0 ccc eee eee 8 22 21 Timer Mode ie eee eS ace 64 has aes ale ee wa 8 2 2 2 2 Counter Mode sisse se Guten wae PACS BS ROCA ORLRUR 8 2 2 2 3 Timer T5 Interrupt Control llle 8 2 2 3 GPT2 Capture Reload Register CAPREL 8 2 2 3 1 Capture Mode 654666 sh ox Ka be eG whee Shee S EE es 9 22 92 Haload Moda nue uie E Y ets eo eee ee 8 2 2 3 3 CAPREL Register Interrupt Control 0 8 2 2 8 4 Using the Capture and Reload Mode
158. e first source is an external input pin T2IN for timer T2 and T4IN for timer T4 One can select either a positive a negative or both a positive and a negative transition to cause an increment or decrement The direction control bits DP3 7 for T2IN or DP3 5 for T4IN must be set to 0 and the input signal should be held at least 8 states for correct edge detection which results in a maximum allowed frequency for the count input signal of 1 25 MHz 9 fosc 40 MHz The second count source is the toggle bit T3OTL of the core timer T3 One can also select either a positive a negative or both a positive and a negative transition of T3OTL to cause an increment or decrement Note that only state transitions of T3OTL which are caused by the overflows underflows of T3 will trigger the counter function of T2 T4 Modifications of T3OTL by software will NOT trigger the counter function of T2 T4 Table 8 2 6 summarizes the different counter modes of the auxiliary timers A block diagram of an auxiliary timer in counter mode is shown in figure 8 2 12 Semiconductor Group 8 36 SIEMENS Peripherals Table 8 2 6 GPT1 Auxiliary Timers Counter Mode Input Selection x 2 4 T21 T4l Counter T2 T4 is Incremented Decremented on 2 1 0 0 0 0 No Transition Selected Tx Disabled 0 0 1 Positive External Transition on TxIN 0 1 0 Negative External Transition on TxIN 0 1 1 Postive and Negative External Transition on TxIN 1 0 0 No Transit
159. e four DPP registers to specify a physical 18 bit ad dress Any word or byte data within the entire memory space can be accessed in such a manner Word accesses may not be performed on odd byte addresses Otherwise ahard ware trap would occur After reset the DPP registers are initialized in a way that all long addresses are directly mapped onto the identical physical addresses Any long 16 bit address consists of two portions which are interpreted in different ways Bits 0 to 13 specify a 14 bit data page offset address while bits 14 to 15 specify that of the four Data Page Pointer registers which is to be used to generate the physical 18 bit address as follows Long Address Long Address Bits 15 14 Bits 13 0 specifies x Physical Address Contents of DPPx Page Offset Address x 0 3 At present the SAB 80C166 supports 256 Kbytes of address space and thus only the low est four bits of the selected DPP register contents are added to the 14 bit data page offset address In case of segmentation being disabled all data accesses are restricted on segment 0 and thus only the lowest two bits of the selected DPP register are signi ficant at all For more details about data paging see section 5 3 5 The long addressing mode is represented by the mnemonic mem Table 6 2 shows the association between long 16 bit addresses and the corresponding Data Page Pointer registers Siemens Aktiengeseilschaft 6 6 Instruction Set Overview
160. e future only trap numbers from 00h to 7Fh can be specified Any double word code loca tion in the address range from 00000h to 001FCh in code segment 0 can be accessed by the trap addressing mode The association between trap num bers and the corresponding interrupt or trap sources is specified in table 7 1 6 3 Condition Code Specification 16 possible condition codes can be used to determine whether a conditional branch shail be taken or not Table 6 6 gives an overview of which mnemonic abbreviations are avail able for that It also describes which kinds of tests are performed due to the selected con dition code and it shows the association between the condition codes and their internal representation by a four bit number Siemens Aktiengesellschaft 6 10 Instruction Set Overview Table 6 6 Condition Codes Condition Code Test Description cc Mnemonics Number b DL cc UC Unconditional Oh co 2n e NZ on NT sh NE on oc NN N 0 Nenegawe TA CN in e NC z0 ch TN zt Rua 2 cc NE Not equal 3h UE Fh cc_UGE o cc UGT ZvC 2 0 Unsigned greater than Eh eS on Siemens Aktiengesellschaft 6 11 Interrupt and Trap Functions 7 interrupt and Trap Functions The architecture of the SAB 80C166 supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or ex ternal to the microcontroller These mechanisms include Normal Interrupt Proce
161. e of this feature see the following description of the STKOV and STKUN stack boundary registers 5 3 8 STKOV Stack Overfiow Pointer This non bit addressable register is compared against the SP register after each opera tion which pushes data onto the system stack e g PUSH and CALL instructions or inter rupts and after each subtraction from the SP register If the contents of the SP register are less than the the contents of the STKOV register a stack overflow hardware trap will occur Stack Overflow Condition SP lt STKOV Figure 5 16 Stack Overflow Pointer Register STKOV FE14h 0Ah Reset Value FAO00h 15 14 13 12 11 10 9 8 2 1 0 7 6 5 4 3 Stkov continuation Symbol Position Function STKOV 0 Bit tied to 0 by hardware because only even STKOV contents are compared against the SP register STKOV Modifiable portion of the STKOV register 10 1 STKOV Bits tied to 1 by hardware This restricts contents to values from 15 11 F800h to FFFEh Siemens Aktiengesellschaft 5 32 Central Processing Unit CPU Since the least significant bit of the STKOV register is tied to 0 and bits 11 to 15 are tied to 1 by hardware the STKOV register can only point to even word addresses from OF800h to OFFFEh After reset the STKOV register is initialized to FAOOh The default initialization allows treating a stack overflow as a fatal error in the corresponding
162. e trap The IP value pushed onto the system stack is the address of the instruction that caused the trap This can be used to emulate unimplemented instructions The trap service routine can examine the faulting instruction to decode operands for unimplemented opcodes based on the stacked IP In order to resume processing the stacked IP value mustbe incremen ted by the size of the undefined instruction which is determined by the user before a RETI instruction is executed 7 3 2 5 Protection Fault Trap Whenever one of the special protected instructions is executed where the opcode of that instruction is not repeated twice in the second word of the instruction and the byte follo wing the opcode is not the complement of the opcode the PRTFLT flaginthe TFRregister is set and the Protection Fault Trap is entered The protectedinstructions include DISWDT EINIT IDLE PWRDN SRST and SRVWDT The IP value pushed ontothe system stack for the protection fauit trap is the address of the instruction that caused the trap 7 3 2 8 Illegal Word Operand Access Trap Whenever a word operand read or write access is made to an odd byte address the ILLOPA flag is set and the Illegal Word Operand Access trap is entered The IP value pushed onto the system stack is the address of the instruction following the one which caused the trap 7 3 2 7 legal Instruction Access Trap Whenever a branch is made to an odd byte address the ILLINA flag is set in the TFR reg
163. e two most significant bits of the required 18 bit addresses Port 1 can be used for general purpose I O functions Whenever a word is to be accessed externally in this mode the EBC generates two consecutive addresses and adjusts incoming bytes into words or outgoing words into bytes The low byte of a word is accessed first then the high byte access is performed The process of transferring two bytes sequentially over the externai bus for any word access causes the operation of the processor to slow down In fact this mode is not as fast as the other external memory access modes However there is a cost advantage since inexpensive byte wide memories can be used If this mode has been selected once during reset internal ROM accesses stay globally disabled and no other external bus configuration can be selected later A detailed application example for this external bus configuration mode is shown in appendix C Siemens Aktiengesellschaft 9 4 External Bus Interface Figure 9 2 16 18 Bit Address 8 Bit Data Multiplexed Bus Segment Addr Low Byte Porta WR RD ALE SAB 80C166 Port 0 High Byte ADDR OE WR 8 Bit Ext Memory Port 1 INSTR DATA 9 4 16 18 Bit Address 16 Bit Data Multiplexed Bus This external bus mode can be selected if a word wide external memory shail be con nected to the SAB 80C166 i As shown in figure 9 3 Port 0 is used as a word wide output for both the address and data which are time m
164. e user can disable segmentation by setting bit SGTDIS to 1 The pins of Port 4 can then be used for general purpose I O 10 2 Port 5 Port 5 P5 differs from Ports 0 through 4 since it is a 10 bit input only port Besides being used as a digital input port all lines of Port 5 may be used as the analog input channels to the A D converter The input buffers to P5 have Schmitt Trigger characteristics in order to achieve logic levels from the analog inputs Figure 10 14 illustrates the structure of a Port 5 pin Channel Select Analog Switch to Sample Hold Circuit n t e r n a l nc UJ Figure 10 14 Block Diagram of a Port 5 Pin Since Port 5 is an input only port it has no port output latches and no direction register However an address in the bit addressable register address space is provided in order to be able to read Port 5 by software Figure 10 15 shows the format of the result when reading Port 5 Port 5 is actually a 10 bit port but the port register P5 is realized as a word register Positions P5 10 through P5 15 are reserved and will be read as zeros A write operation to P5 has no effect The value written to it is lost No special distinction has to be made between Port 5 lines being used as analog inputs and Port 5 lines being used as digital inputs A read operation on Port 5 may be performed on any of the 10 bits The bits corresponding to lines being used as analog inputs are don t care bits An A D co
165. e will be implemented in the BA step of the SAB 80C166 Three new signals are required for this feature HOLD Input Only When brought to low active state this signals to the SAB 80C166 that another master wants to perform one or several bus accesses on the external bus of the SAB 80C166 After internal synchronisation of this signal and after complete termination of the current external bus cycle if any the SAB 80C166 backs off its external bus and activates signal HLDA to flag the second master that the bus is now free This condition will be held until the HOLD line goes back to high inactive state After an internal synchronisation phase the SAB 80C166 deactivates signal HLDA and takes over the control of the external bus again if required During the HOLD phase the SAB 80C166 can still operate and fetch instruction or data when executing out of internal ROM or RAM The CPU really only stops execution if external data or instruction fetches are required HLDA Hold Acknowledge Output Only Semiconductor Group D 12 SIEMENS SAB 80C166 83C166 When brought to low active state through the SAB 80C166 this signal tells the second master that the bus is now free for use BREQ Bus Request Output Only This signal is intended to give the SAB 80C166 a chance to flag an own external bus request to the second master The second master can then decide whether or not to grant the SAB 80C166 the external bus for one or more ex
166. ead only for ROMIess parts See Subsection 5 3 1 1 for details CLKEN SYSCON 8 System Clock Output CLKOUT Enable bit CLKEN 0 CLKOUT disabled pin can be used for normal O CLKEN 1 CLKOUT enabled pin used for system clock output See Subsection 5 3 1 5 for details BYTDIS SYSCON 3 xii ni vO SGTDIS SYSCON 11 See Subsection 5 3 1 6 for details RDYEN SYSCON 12 READY Input Enable control bit RDYEN 0 READY disabled pin can be used for normal O RDYEN 1 READY enabled pin used for READY input See Subsection 5 3 1 4 for details STKSZ SYSCON Maximum System Stack Size Selection of between 32 and 256 words 14 13 See Subsection 5 3 1 7 for details Byte High Enable BHE pin control bit BYTDIS 0 BHE enabled BYTDIS 1 BHE disabled pin can be used for normal I O See Subsection 5 3 1 3 for details Internal ROM Access Enable Read Only ROMEN 0 ROM Accesses disabled ROMEN 1 ROM Accesses enabled See Subsection 5 3 1 1 for details Segmentation Disable control bit SGTDIS 0 A16 and A17 enabled Port 4 used for segment address SGTDIS t A16 and A17 disabled Port 4 can be used for normal Siemens Aktiengesellschaft 5 14 Central Processing Unit CPU 5 3 1 2 External Bus Timing Control via MCTC MTTC RWDC The MCTC bit field and the MTTC and RWDC bits in the SYSCON register are provided for varying external bus timing parameters as f
167. ecome globally enabled or disabled during reset by means of the external bus configuration pins EBC1 and EBCO as shown in table 4 2 The selected internal ROM access state is stored in the read only ROMEN bit in the SYSCON register Table 4 2 Internal ROM Access State Selection during Reset EBC1 Pin Internal ROM Access enabled disabled disabled disabled The internal ROM can be used for both code and data constants tables etc storage Code accesses are always made on even byte addresses Thus the highest possible code storage location in the internal ROM is either 01FFEh for single word instructions or01FFCh for double word instructions If used for code storage the corresponding location must con tain a branch instruction because sequential boundary crossing from the internal ROM to the external memory is not provided and would cause erroneous results Word and byte data within in the internal ROM can only be accessed via indirect or long 16 bit addressing modes provided that the selected DPP register points to data page 0 There is no short addressing mode for internal ROM operands Any word data access is made to an even byte address Thus the highest possible word data storage location in the internal ROM is address 01FFEh For PEC data transfers the internal ROM canbe ac cessed independent of the contents of the DPP registers via the PEC source and destina tion pointers The internal ROM is not provided for
168. ed target instruction within any code segment Conditional jumping to a relatively addressed target instruction within the current code segment depending on the state of a selectable bit e Conditional jumping to a relatively addressed target instruction within the current code segment depending on the state of a selectable bit with a post inversion of the tested bit in case of jump taken semaphore support e Conditional calling of an either absolutly or indirectly addressed subroutine within the current code segment e Unconditional calling of a relatively addressed subroutine within the current code segment e Unconditional calling of an absolutely addressed subroutine within any code segment Unconditional calling of an absolutely addressed subroutine within the current code segment plus an additional pushing of a selectable register onto the system stack Unconditional branching to the interrupt or trap vector jump table in code segment 0 Siemens Aktiengesellschaft 6 3 MOV MOVBS PUSH POP SCXT JMPA JMPS JB JBC CALLA CALLR CALLS PCALL TRAP MOVB MOVBZ JMPI JMPR JNB JNBS CALLI Instruction Set Overview 6 1 10 Return Instruction e Returning from a subroutine within the current code segment RET e Returning from a subroutine within any code segment RETS e Returning from a subroutine within the current code segment plus an additional popping of a selectable r
169. ed bit ANDing of two bits ORing of two bits XORing of two bits Comparison of two bits Compare and Loop Control Instructions Comparison of two words or bytes Comparison of two words with post increment by either 1 or 2 Comparison of two words with post decrement by either 1 or 2 Shift and Rotate Instructions Shifting right of a word Shifting left of a word Rotating right of a word Rotating left of a word Arithmetic shifting right of a word sign bit shifting Prioritize Instruction Determination of the number of shift cycles required to normalize a word operand floating point support Instruction Set Overview BFLDH BSET BCLR BMOV BMOVN BAND BOR BXOR BCMP BFLDL CMP CMPB CMPI1 CMPI2 CMPD1 CMPD2 SHR SHL ROR ROL ASHR PRIOR Instruction Set Overview 6 1 7 Data Movement Instructions e Standard data movement of a word or byte e Data movement of a byte to a word location with either sign or zero byte extension 6 1 8 System Stack Instructions Pushing of a word onto the system stack e Popping of a word from the system stack e Saving of a word on the system stack and then updating the old word with a new value provided for register bank switching 6 14 9 Jump and Call Instructions e Conditional jumping to an either absolutely indirectly or relatively addressed target instruction within the current code segment e Unconditional jumping to an absolutely address
170. ed for both 16 bit addresses and 16 bit data Because of time multiplexing two external address latches are required The EPROMs can only be accessed wordwise while the RAMs can also be accessed bytewise provided that the function of the BHE output pin is not disabled In this case the address signal AO selects the lower byte memory and the active low BHE signal selects the upper byte memory Semiconductor Group C 1 SIEMENS Application Examples 3 4 5 6 16 bit Addresses 16 bit Data Multiplexed Bus External RAM ROM Word Organized Memories This configuration is shown in figure C 3 Except that the available RAM space is doubled and that two byte organized memories are replaced by one word organized memory this configuration is identical to the example shown in figure C 2 16 bit Addresses 16 bit Data Non Multiplexed Buses External RAM ROM Byte Organized Memories This configuration is shown in figure C 4 The external memory is implemented by two 16K 8 EPROMs and by two 2K 8 RAMs Because two separate 16 bit data and 16 bit address buses are used no external address latch is required The EPROMs can only be accessed wordwise while the RAMs can also be accessed bytewise provided that the function of the BHE output pin is not disabled In this case the address signal AO selects the lower byte memory and the active low BHE signal selects the upper byte memory 16 bit Addresses 16 bit Data Non Multiple
171. ed in the following because any explicit write to the PSW register supersedes the condition flag values which are implicitly generated by the CPU Explicitly reading the PSW register supplies a read value which represents the state of the PSW register after execution of the immediately preceding instruction E Flag The E flag can be altered by instructions which perform ALU or data movement operations The E flag is cleared by those instructions which can not be reasonably used for table search operations In all other cases the E flag is set depending on the value of the source operand to signify whether the end of a search table is reached or not If the value of the source operand of an instruction equals the lowest negative number which is representable by the data format of the corresponding instruction 8000h for the word data type or 80h for the byte data type the E Flag is set to 1 otherwise it is cleared 2 Flag The Z Flag is normally set to 1 if the result of an ALU operation equals zero otherwise it is cleared For the addition and subtraction with carry the Z flag is only set to 1 if the Z flag already contains a 1 and if the result of the current ALU operation additionally equals zero This mechanism is provided for the support of multiple precision calculations For Boolean bit operations with only one operand the Z flag represents the logical negation of the previous state of the specified bit For Boolean bi
172. ed to X11b both a positive and a negative transition will set the request flag In ail three cases the contents of the core timer T3 will be captured into the auxiliary timer registers T2 or T4 based on the transition at pins T2IN or T4IN When the interrupt enable bits T2IE or T4IE are set a PEC request or an interrupt request for vector T2INT or T4INT will be generated For further details on the GPT1 block see section 8 2 1 Pin CAPIN P3 2 differs slightly from the other pins described before in that it can be used as external interrupt input pin without affecting peripheral functions When the capture mode enable bit T5SC in register T5CON is set to 0 signal transitions on pin CAPIN P3 2 wiil only set the interrupt request flag CRIR in register CRIC and the capture function of register CAPREL is not activated This means that register CAPREL can still be used as re load register for GPT2 timer T5 while pin CAPIN P3 2 is used as external interrupt input Siemens Aktiengesellschaft 7 25 interrupt and Trap Functions Through bit field Ci in register T5CON the effective transition of the external interrupt input signal can be selected When Cl is programmed to 01b a positive external transition will set the interrupt request flag CI 10b selects a negative transition to set the interrupt request flag and with CI 11b both a positive and a negative transition will set the request flag When the interrupt enable bit CRIE is set an i
173. ee eee eee ee 4 10 4 3 3 PEC Source and Destination Pointers 000 ce eee 4 11 4 4 Internal Special Function Registers 4 12 Siemens Aktiengesellschaft 1 5 1 5 1 1 5 1 2 5 1 3 5 1 4 5 2 5 2 1 5 2 2 5 2 3 5 3 5 3 1 5 3 1 1 5 3 1 2 5 3 1 3 5 3 1 4 5 3 1 5 5 3 1 6 5 3 1 7 5 3 2 5 3 2 1 5 3 2 2 5 3 3 5 3 4 5 3 5 5 3 6 5 3 6 1 5 3 6 2 5 3 7 5 3 8 5 3 9 5 3 10 5 3 11 5 3 12 5 3 13 5 3 14 6 1 6 1 1 Central Processing Unit CPU Instruction Pipelining 0 00 0 eee eee eee Sequential Instruction Processing eese Standard Branch Instruction Processing Cache Jump Instruction Processing sess Particular Pipeline Effects 0 0 00 eee eee Instruction State Times Time Unit Definitions 2 2 0 0 000000 ee eens Minimum State Times 0 000 cc cee eee Additional State Times ee ee ees CPU Special Function Registers SYSCON System Configuration Register Internal ROM External Memory Access Mode Selection via ROMEN BTYP o oo aaao naan ns External Bus Timing Control via MCTC MTTC RWDC Byte High Enable Pin Control via BYTDIS Ready Pin Control via RDYEN 00 6 Clock Output Pin Control via CLKEN 00 Non Segmented Memory Mode Selection via SGTDIS
174. egister from the system stack RETP e Returning from an interrupt service routine RETI 6 1 11 System Control Instructions e Resetting the SAB 80C166 by software SRST e Entering the Idle mode IDLE e Entering the Power Down mode PWRDN e Servicing the Watchdog Timer SRVWDT e Disabling the Watchdog Timer DISWDT e Signifying the end of the initialization routine pulls RSTOUT pin high and disables the effect of any later execution of a DISWDT instruction EINIT 6 1 12 Miscellaneous e Nuil operation which requires 2 bytes of storage and the minimum time for execution NOP 6 2 Addressing Modes The SAB 80C166 provides a lot of powerful addressing modes for access on word byte and bit data or to specify the target address of a branch instruction The addressing modes are subdivided in different categories as follows 6 2 4 Short Addressing Modes All of these addressing modes use an implicit base offset address to specify a physical 18 bit address By these addressing modes data can be specified within the GPR SFR or bit addressable memory space Physical Address Base Address A Short Address Siemens Aktiengeseilschaft 6 4 instruction Set Overview Table 6 1 Short Addressing Modes Mnemonic Allows Access On GPRs Word GPRs Byte SFRs Word Low Byte GPRs Word GPRs Byte Physical Address Short Address Range CP Bw CP RB OFEO0h 2 reg reg 2 00h EFh CP 2 reg OFh reg
175. ely following the SCXT instruction see also section 5 1 4 Before executing the RETI instruction at the end of an interrupt service routine the pre vious Context Pointer must be popped from the system stack to ensure correct return to the previous context 7 25 Interrupt Processing via the Peripheral Event Controller PEC As an alternative to software oriented interrupt processing the PEC provides a way to minimize interrupt latency and software overhead in cases where only a single data transfer operation is required to service a peripheral device As ail the SAB 80C166 s peripheral functions are controlled by Special Function Registers SFRs it is sufficient for many applications to simply transfer data to or from the Special Function Registers and a data memory location to handle service requests Examples would be storing of results from the A D converter or data from a serial channel With the SAB 80C166 s PEC data transfers between two memory locations in segment 0 data page 0 through 3 are possible The PEC data transfer itself does not affect the IP or the flags in the PSW Therefore no program status information needs to be saved when the PEC performs a data transfer This improves the overall system throughput and speeds up the servicing of peripheral requests The priority level structure of the SAB 80C166 s interrupt system has been designed such that requests for PEC service have priority over requests for CPU interrupt se
176. en incorporated to allow four bits to be multiplied and two bits to be divided per machine cycle Thus these operations require four and nine machine cycles respectively to perform a 16 bit by 16 bit or 32 bit by 16 bit calculation plus one machine cycle to setup and adjust the operands and the result Even these longer multiply and divide instructions can be interrupted during their execution to allow for very fast interrupt response Instructions have also been provided to allow byte packing in memory while providing sign extension of bytes for word wide arithmetic operations The internal bus structure also allows transfers of bytes or words to or from peripherals based on the peripheral requirements A set of consistent flags is automatically updated in the PSW after each arithmetic logical shift or movement operation These flags allow branching on specific conditions Support for both signed and unsigned arithmetic is provided through user specifiable branch tests These flags are also preserved automatically by the CPU upon entry to an interrupt or trap routine 2 1 3 Extended Bit Processing and Peripheral Control A large number of instructions has been dedicated to bit processing These instructions provide efficient control and testing of peripherals while enhancing data manipulation Unlike many current microcontrollers these instructions provide direct access to two operands in the bit addressable space without requiring movement int
177. enabled or not through bit T5SC The external input pin CAPIN P3 2 can be used to clear timer T5 to 0000h Either a positive a negative or both a positive and a negative transition at this pin can be selected to trigger the clear function The active edge is controlled by bit field Cl in register T5CON according to Table 8 2 11 see User s Manual For triggering the clear function of T5 pin CAPIN must be configured as input by setting its direction control bit DP3 2 to 0 To ensure that a transition of the clear trigger signal is correctly recognized its level should be held for at least 4 state times When the clear function is enabled and a selected transition at the external input pin CAPIN is detected timer T5 is cleared to 0000h and the interrupt request flag CRIR in register CRIC is set Note The timer T5 clear function and the capture function are always triggered by the same transition at pin CAPIN Figures 1 1 and 1 2 are the corrected figures of the User s Manual showing the changed functionality of the timer T5 clear function 2 Serial Port Baud Rates To increase the range of programmable baud rates for the two serial interfaces an additional control bit will be implemented in the control registers SOCON and S1CON This bit SxBRS Serial Port x Baud Rate Selection will be located at bit position 13 in each of the two control registers When SxBRS 0 the baud rate is determined by the formula described in the User s M
178. ency the reload value and the mode asynchronous or synchronous of the serial channel Registers SOBG and S1BG are the dual function Baud Rate Generator Reload registers Reading SOBG or S1BG returns the contents of the timer while writing to SOBG or S1BG always updates the reload register When writing to SOBG or S1BG i e to the reload registers the 3 upper bits 13 through 15 are insignificant while reading SOBG or S1BG i e the timer registers always returns zero in bits 13 through 15 An auto reload of the timer with the contents of the reload register is performed each time SOBG or S1BG is written to However if SOR 0 or S1R 0 at the time the write operation to SOBG or S1BG is performed the timer will not be reloaded until the first instruction cycle after SOR 1 or S1R 1 Semiconductor Group 8 74 SIEMENS Peripherals 8 4 2 1 Asynchronous Mode Baud Rates In asynchronous operation the baud rate generators provide a clock with 16 times the rate of the established baud rate The reason for this is that on reception every bit frame is sampled 16 times Thus the baud rates BasyncO and Basync1 for the serial channels ASCO and ASC1 in asynchronous operation are determined by the following formulas fosc 64 lt S1BRL gt 1 f OSC async eq lt S0BRI gt 1 Basync1 lt SOBRL gt and lt S1BRL gt represent the contents of the reload registers taken as unsigned 13 bit integers Table 8 4 2 lists various
179. ens Aktiengesellschaft 4 11 Memory Organization As shown in figure 4 5 a pair of source and destination pointers is stored in two subse quently following word memory locations with the source pointer SRCPx on the lower and with the destination pointer DSTPx on the higher word address x 7 0 to 7 Provi ded that the intended use of a PEC channel is passed to the SAB 80C166 assembler the required memory space reservation for the pair of pointers is supported by PES166 the software tool package for the SAB 80C166 Whenever a PEC data transfer is performed the pair of source and destination pointers which is selected by the specified PEC channel number is accessed independent of the current DPP register contents If a PEC channel is not used the corresponding pointer locations can be used for word byte or single bit data storage For more details about the use of the source and destination pointers for PEC data transfers see section 7 2 2 4 4 Internal Special Function Registers The SAB 80C166 provides 512 bytes of on chip Special Function Register SFR space The SFRs are mapped into the address space from OFEOOh to OFFFFh The SFRs are not provided for general code or data storage but for data storage dedica ted to very particular uses mainly for controlling CPU Peripheral and 1 O functions Accor ding to the just mentioned control functions the SFRs are described in detail inoneofthe chapters 5 0 CPU 8 0 Peripherais o
180. epends on where the instruction is fetched from and where possible operands are read from or written to The fastest processing mode of the SAB 80C166 is to execute a program fetched from the internal ROM In that case most of the instructions can be processed within just one machine cycle which also represents the general minimum execution time All of the external memory accesses are performed by the SAB 80C166 on chip External Bus Controller EBC which works in parallel with the CPU Mostly instructions from the external memory can not be processed as fast as instructions from the internal ROM because some data transfers which internally can be performed in parallel have to be performed sequentially via the external interface In contrast to internal ROM program execution the time required to process an external program additionally depends on the length of the instructions and operands on the selected bus mode and on the duration of an external memory cycle which is partly selectabie by the user Processing a program from the internal RAM space is not as fast as execution from the internal ROM area but it offers a lot of flexibility i e for end of line programming where a program could be loaded into the internal RAM via the chip s serial interface The following description allows evaluating the minimum and maximum program exe cution times This will be sufficient for most of the requirements For an exact determi nation of the in
181. epts primarily allow fast decoding of the instructions and operands while reducing pipeline holds These concepts however do not preclude the use of complex instructions which are required by microcontroller users The following goals were used to design the instruction set 1 Provide powerful instructions to perform operations which currently require sequences of instructions and are frequently used Avoid transfer into and out of temporary registers such as accumulators and carry bits Perform tasks in parallel such as saving state upon entry to interrupt routines or subroutines 2 Avoid complex encoding schemes by placing operands in consistent fields for each instruction Also avoid complex addressing modes which are not frequently used This decreases the instruction decode time while also simplifying the development of compilers and assemblers 3 Provide most frequently used instructions with one word instruction formats All other instructions are placed into two word formats This allows all instructions to be placed on word boundaries which alleviates the need for complex alignment hardware It also has the benefit of increasing the range for relative branching instructions Semiconductor Group 2 3 SIEMENS Architectural Overview 2 1 6 Programmable Multiple Priority Interrupt Structure A number of enhancements have been included to allow processing of a large number of interrupt sources These are presented below 1 Periphera
182. equirements components may contain dangerous substances For information on the types in question please contact your nearest Siemens Office Semiconductor Group Siemens AG is an approved CECC manufacturer Packing Please use the recycling operators known to you We can also help you get in touch with your nearest sales office By agreement we will take packing material back if it is sorted You must bear the costs of transport For packing material that is returned to us unsorted or which we are not obliged to accept we shall have to invoice you for any costs in curred Components used in life support devices or systems must be expressly authorized for such purpose Critical components of the Semiconductor Group of Siemens AG may only be used in life support devices or systems with the express written approval of the Semiconductor Group of Siemens AG 1 Acritical component is a component used in a life support device or system whose failure can reasonably be expected to cause the failure of that life support device or system or to affect its safety or effectiveness of that device or system 2 Life support devices or systems are intended a to be implanted in the human body or b to support and or maintain and sustain hu man life If they fail it is reasonable to assume that the health of the user may be endangered SIEMENS Microcomputer Components SAB 80C166 83C 166 16 Bit CMOS Single Chip Microcontrollers for Embedded Cont
183. er The GPRs are accessed via short 2 4 or 8 bit addressing modes in collabora tion with a particular Context Pointer CP register The channel number of a PEC data transfer to be performed determines which PEC source or destination pointers will be implicitly accessed All of the just mentioned implicit internal RAM accesses are made independent of the current DPP register contents The upper portion of the internal RAM addresses from OFDOOh to OFDFFh and the cur rently active GPRs are provided for single bit storage and thus they are bit addressable The following subsections 4 3 1 through 4 3 3 describe in more detail the organization of the system stack of the GPRs and of the PEC source and destination pointers 4 3 1 System Stack The internal RAM address space from OFBFFh downward to OFAOOh is basically provided for the SAB 80C166 s system stack implementation The default maximum stack size of 256 words can easily be reduced by changing the stack size STKSZ bit field in the SYSCON register as shown in table 4 4 Table 4 4 Maximum System Stack Size Selection STKSZ Stack Size Internal RAM Addresses words in descending order 00b 256 OFBFFh OFAO0h defauit 01b 128 OFBFFh OFBOOh 10b 64 OFBFFh OFB80h 11b 32 OFBFFh OFBCOh For all system stack operations the on chip RAM is accessed via the Stack Pointer SP register The stack grows downward from higher towards lower RAM address locations Only word accesse
184. eset SRST instruction is executed or a watchdog timer reset occurs internal circuitry provides for the correct number of state times of the reset sequence Now in the BA step this is also true when an external reset signal is applied to pin RSTIN The external reset signal has to be held at a logic low level for a duration of at least 2 state times for internal latching purposes The internal circuitry will then perform the complete reset sequence regardless whether the external reset signal stays at a low level or turns back to a logic high level If the external reset signal is still low by the time the internal reset sequence is completed the sequence will start again This procedure continues until a high level is found at the RSTIN pin at the end of a reset sequence This new feature helps to avoid unexpected results due to noise on the RSTIN line Noise pulses longer than 2 state times will always initiate a complete reset of the SAB 80C166 Shorter noise pulses have to be avoided or suppressed by external circuitry Note that holding the reset pin RSTIN low for a minimum of 2 state times is only sufficient for a warm reset For a power up reset the RSTIN pin has to be held low at minimum for the duration of the oscillator start up time about 50 ms for a quartz crystal 11 Implementation of HOLD HLDA BREQ Bus Arbitration In order to support multi master systems and communication with external DMA functions a bus arbitration featur
185. esses For the non segmented memory mode or the Single Chip Mode the contents of this re gister are not significant because all code acccesses are automatically restricted to seg ment 0 Note that the CSP register can only be read but not written for data operations It is how ever modified either directly by means of the JMPS and CALLS instructions or indirectly via the stack by means of the RETS and RETlinstructions Upon the acceptance of an inter rupt or the execution of a software TRAP instruction the CSP register is automatically set to zero After reset the CSP register is initialized to 0000h 5 3 5 DPPO DPP1 DPP2 DPP3 Data Page Pointers These four non bit addressable registers select up to four different data pages being ac tive at run time Currently only the four least significant bits of each DPP register are im plemented while the bits 4 to 15 are reserved for future use The DPP registers allow ac cessing the entire memory space in currently 16 pages of 16 Kbytes each The DPP registers are implicitly used whenever data accesses to any memory space are made via indirect or direct long 16 bit addressing modes except for PEC data transfers After reset the Data Page Pointers are initialized in a way that all indirect or direct long 16 bit addresses result in identical 18 bit addresses This allows accessing data pages 0 to 3 in segment 0 as shown in figure 5 9 If the user does not want to use any data paging
186. esses have been disabled during reset the lowest 8 Kbytes of segment 0 also specify an external memory area Siemens Aktiengesellschaft 4 2 Memory Organization Table 4 1 Memory Address Space Mapping Address Space Memory Range Size Bytes 00000h O1FFFh Internal ROM or 8K External Memory 02000h OF9FFh External Memory 54 5 K OFAO00h OFDFFh Internal RAM 1K OFEO0h OFFFFh Internal SFRs 512 10000h 3FFFFh External Memory 192 K The internal ROM the internal RAM and the external memory space can be used for ge neral code and data storage The internal SFR space is provided for control data but not for code storage Note that byte units forming a single word or a double word must always be stored within the same physical and organizational memory area page segment A particular use is provided for some memory areas as follows Addresses from 00000h to OOOBFh in code segment zero are reserved for the hardware trap and interrupt vector jump table The active General Purpose Register Bank which is selected by the Context Pointer CP Register can be situated anywhere in the internal RAM area addresses from OFAOQh to OFDFFh Word addresses from OFAO0h to OFBFEh in the internal RAM can basi cally be used for the system stack implementation The highest 32 bytes of the internal RAM addresses from OFDEOh to OFDFFh are provided for the Peripheral Event Control ler PEC source and destination pointers Three memory s
187. essing Unit CPU 5 Central Processing Unit CPU Basic tasks of the CPU are to fetch and decode instructions to supply operands for the arithmetic and logic unit ALU to perform operations on these operands in the ALU and to store the previously calculated results Since a four stage pipeline is implemented in the SAB 80C166 up to four instructions can be processed in parallel Section 5 1 describes how the pipeline works for sequential and branch instructions in general and which hardware provisions have been made to speed the execution of jump instructions in particular With reference to instruction pipelining most of the SAB 80C166 instructions can be regarded as being executed during one machine cycle 100 ns at 40 MHz oscillator frequency Section 5 2 describes the general instruction timing including standard and exceptional timing While internal memory accesses are normally performed by the CPU itself all of the ex ternal memory accesses are performed by a particular on chip External Bus Controller EBC which is automatically invoked by the CPU whenever a code or data address be longs to the external memory space If possible the CPU continues operating while an external memory access is in progress If external data are required but are not yet avail able or if a new external memory access is requested by the CPU before aprovious ac cess has been completed the CPU will be held by the EBC until the request can be sati
188. events with minimum software overhead In all compare modes the 16 bit value stored in compare register CCx in the following also referred to as compare value is continuously compared with the contents of the timer TO or T1 to which the register is allocated If the current timer contents match the compare value an appropriate output signal which is based on the selected compare mode can be generated at the corresponding Port 2 pin and an interrupt request is generated by setting the associated interrupt request flag CCxIR As for the capture mode the compare registers are also processed sequentially during compare mode When any two compare registers are programmed to the same compare value their corresponding interrupt request flags will be set to 1 and the selected output signals will be generated within 8 state times after the allocated timer is incremented to the compare value Further compare events on the same compare value are disabled until the timer is incremented or written to by software After a reset compare events for register CCx will only become enabled if the allocated timer has been incremented or written to by software and one of the compare modes described in the following has been selected for this register The different compare modes which can be programmed for a given compare register CCx are selected by the mode control field CCMODx in the associated capture compare mode control register see table 8 1 3 In the
189. f the group were on the same priority level For example an application may have 24 interrupt sources where these sources must be organized in 3 priority classes with 8 10 and 6 sources per class In the priority scheme of the SAB 80C166 the 24 sources could be organized and configured as follows Siemens Aktiengesellschaft 7 15 Interrupt and Trap Functions Table 7 4 Example of 24 interrupt Organization in 3 Classes ILVL Organization ee aes p 29 Fh Eh 1l PEC Service 8 Channels Dh Eae RES ER Class A 8 Interrupts Class B 10 Interrupts In this example the 3 user defined priority levels are called classes Each of the three classes A through C includes interrupt sources on 2 or 3 priority levels of the interrupt system The 2 highest priority levels of the interrupt system are used by the PEC service functions Priority level O does not provide interrupt service With the organization shown in table 7 4 any acknowledged interrupt from the sources within a class e g A must set the CPU Priority field of the PSW to the highest priority level contained in its class e g 8 for class B at the beginning of its interrupt service routine eo Using this technique interrupts generated by the lowest class i e C can be interrupted by a request from higher classes i e B or A However an interrupt service routine of a source that belongs to the highest class i e A can not be interrupted by requests
190. f the microcontroller to external hardware Siemens Aktiengesellschaft 11 5 Power Reduction Modes 12 Power Reduction Modes Two different power reduction modes with different leveis of power reduction have been implemented in the SAB 80C166 which may be entered under software control In Idle mode the CPU is stopped while the peripherals continue their operation In Power Down mode both the CPU and the peripherals are stopped Idle mode can be terminated by any reset or interrupt request while Power Down mode can only be terminated by a hardware reset 12 1 Power Down Mode To save power in a system the microcontroiler can be placed in Power Down mode All clocking of internal blocks is stopped but the contents of the internal RAM are preserved through the voltage supplied by the Vec pins The Watchdog Timer is stopped in Power Down mode One can only exit this mode through an external hardware reset by asserting a low level on the RSTIN pin for a specified period of time 1040 state times This reset will initialize all SFRs and ports to their default state but will not change the contents of the internal RAM There are two levels of protection against unintentionally entering the Power Down mode First the PWRDN Power Down instruction which is used to enter this mode has been implemented as a protected instruction Second this instruction is effective ONLY if the NMI Non Maskable Interrupt pin is externally pulled low while t
191. ffer register SOTBUF or S1TBUF In general any instruction or PEC data transfer operation which uses these registers as destination will initiate a transmission Note that SOTBUF and S1TBUF are non bit addressable WRITE ONLY registers and that only the number of data bits which is determined by the selected operating mode will actually be transmitted This means that the bits written to positions 9 through 15 of registers SOTBUF and S1TBUF are always insignificant After a transmission has been completed the transmit buffer registers are cleared to 0000h Semiconductor Group 8 64 SIEMENS Peripherals Table 8 4 1 Serial Channel Modes of Operation SOM S1M Mode 2 1 0 0 0 1 8 bit data asynchronous operation 0 1 1 7 bit data parity bit asynchronous operation 1 0 0 9 bit data asynchronous operation 1 0 1 8 bit data wake up bit asynchronous operation 1 1 1 8 bit data parity bit asynchronous operation 0 0 0 8 bit data synchronous operation X 1 0 reserved Data reception is enabled by the Receiver Enable Bits SOREN and S1REN respectively After reception of a character has been completed the received data and if provided by the selected operating mode the received parity bit can be read from the Receive Buffer registers SORBUF or S1RBUF of the associated serial channel These registers are non bit addressable READ ONLY registers Bits in the upper half of SORBUF and S1RBUF which are not signi
192. ficant for the selected operating mode will be read as zeros Data reception is double buffered so that reception of a second character may already begin before the previously received character has been read out of the receive buffer register In all modes receive buffer overrun error detection can be selected through bits SOOEN and S1OEN When enabled the overrun error status flag SOOE or S1OE and the error interrupt request flag SOEIR or S1EIR for the respective channel will be set when the receive buffer register has not been read by the time reception of a second character is complete The previously received character in the receive buffer is overwritten In each of the operating modes provided by the serial channels of the SAB 80C166 a loop back option can be selected through bits SOLB or S1LB This option allows to simultaneously receive the data which are being transmitted by the SAB 80C166 All operating modes of the serial channels will be described in detail in the following subsections 8 4 1 1 Asynchronous Operation In asynchronous operation full duplex communication is supported The same operating mode and baud rate is used for both transmission and reception Each serial channel of the SAB 80C166 has two pins associated with it which are alternate functions of port 3 pins RXDO P3 11 and TXDO P3 10 are used by ASCO in asynchronous operation as receive data input and transmit data output pins respectively while RXD1 P3 9 and
193. flag Siemens Aktiengesellschaft 7 2 Table 7 1 Interrupt and Trap Functions Interrupt Sources and Associated Interrupt Vectors Source of Interrupt or PEC Service Request CAPCOM Register 0 CAPCOM Register 1 CAPCOM Register 2 CAPCOM Register 3 CAPCOM Register 4 CAPCOM Register 5 CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM Register 9 CAPCOM Register 10 CAPCOM Register 11 CAPCOM Register 12 CAPCOM Register 13 CAPCOM Register 14 CAPCOM Register 15 CAPCOM Timer 0 CAPCOM Timer 1 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5 GPT2 Timer 6 GPT2 CAPREL Register A D Conversion Complete A D Overrun Error Seriai Channel 0 Transmit Seriai Channel 0 Receive Serial Channel 0 Error Serial Channel 1 Transmit Serial Channel 1 Receive Serial Channel 1 Error Siemens Aktiengesellschaft Flag Flag Vector Location Number CC3IR 13h 14h scn t7h CC8IR 60h 18h 68h 1Ah 1Ch 1h Eh 1Fh To Toe TONT aon 2oh SORIR SORIE SORINT ACh 2Bh soen soe SOEINT Goh 2Ch 2Eh 7 3 Interrupt and Trap Functions The vector locations for hardware traps and the corresponding status flags in register TFR are listed in table 7 2 Also listed are the priorities of trap service in case simulta neous trap conditions might be detected within the same instruction After any reset hardware reset software reset instruction SRST or reset by watchdog timer overflow program exec
194. following each of the compare modes including the special double register mode is discussed in detail 8 1 2 2 1 Compare Mode 0 This is an interrupt only mode which can be used for software timing purposes Compare mode 0 is selected for a given compare register CCx by setting bit field CCMODx of the corresponding mode control register to 100b In this mode interrupt request flag CCxIR is set each time a match is detected between the contents of compare register CCx and the allocated timer Several of these compare events are possible within a single timer period when the compare value in register CCx is updated during the timer period The corresponding Port 2 pin P2 x is not affected by compare events in this mode and can be used as a normal I O pin If compare mode 0 is programmed for one of the registers CC8 to CC15 the double register compare mode becomes enabled for this register if the corresponding bank 1 register is programmed to compare mode 1 see section 8 1 2 2 5 for details on the double register mode Semiconductor Group 8 15 SIEMENS Peripherals Figure 8 1 10 shows a functional diagram of a compare register CCx configured for compare mode 0 Note that the port latch and pin remain unaffected in compare mode 0 Figure 8 1 11 shows a simple timing example for this mode In this example the compare value in register CCx is modified from cv1 to cv2 after compare events 1 and 3 and from cv2 to cv1 after events 2 and
195. gative or both a positive and a negative transition at the respective external input pin CCxlO The active transition is selected by the mode bits CCMODx in the respective CAPCOM mode control register In any case the event causing a capture will also set the respective interrupt request flag CCxIR which can cause an interrupt or a PEC service request when enabled Figure 8 1 9 shows a block diagram for one capture compare register in capture mode Capture Reg CCx Interrupt Request CAPCOM Timer Ty decus Figure 8 1 9 Capture Mode Block Diagram In order to use pin P2 xX CCxIO as external capture input pin for capture register CCx P2 x must be configured as input i e the corresponding direction control bit DP2 x in register DP2 must be set to 0 To ensure that a signal transition is properly recognized an external capture input signal should be held for at least 8 state times before it changes its level During these 8 states the capture input signals are scanned sequentially When a timer is modified or incremented during this process the new timer contents will already be captured for the remaining capture registers within the scanning sequence If P2 xX CCxIO is configured as output the capture function may be performed by modifying port data register bit P2 x through software e g for testing purposes Semiconductor Group 8 14 SIEMENS Peripherals 8 1 2 2 Compare Modes The compare modes allow triggering of
196. gger a PEC service request when enabled by the interrupt enable bit CCxIE Capture interrupts can be regarded as external interrupt requests with the additional feature of recording the time at which the triggering event occurred see also section 7 2 7 Each of the 16 capture compare registers CCO through CC15 has its own bit addressable interrupt control register CCOIC through CC151C and its own interrupt vector CCOINT through CC15INT Figure 8 1 18 shows the organization of the interrupt control registers CCOIC through CC151C Refer to chapter 7 for more details on the interrupt control registers 8 2 General Purpose Timers GPT The GPT unit represents a very flexible multifunctional timer structure which may be used for timing event counting pulse width measurement pulse generation frequency multiplication and other purposes It incorporates five 16 bit timers that have been divided into two blocks GPT1 and GPT2 Block GPT1 contains 3 timers counters while block GPT2 contains 2 timers counters and a 16 bit Capture Reload register CAPREL The GPT2 timers have a maximum resolution of 200 ns 40 MHz oscillator frequency the resolution of the GPT1 timers is 400 ns Each timer in each block may operate independently in a number of different modes such as gated timer or counter mode or may be concatenated with another timer of the same block The auxiliary timers of GPT1 may optionally be configured as reload or capture register
197. gh order 16 bits of the 32 bit Multiply and Divide Register MO Whenever this register is updated via software the Multiply Divide Register In Use MDRIUJ flag in the Multiply Divide Control register MDC is set to 1 When a multiplication or division is interrupted before its completion and when a new multiply or divide operation is to be performed in the interrupt service routine the MDH register must be saved along with the MDL and MDC registers to avoid erroneous results After reset this register is initialized to O000h A detailed description of how to use the MDH register for programming multiply and divide algorithms can be found in section 13 2 Siemens Aktiengesellschaft 5 34 Central Processing Unit CPU 5 3 11 MDL Multtiply Divide Register Low Portion This register is implicitly used by the CPU when it performs a multiplication or a division After a multiplication this non bit addressable register represents the low order 16 bits of the 32 bit result For long divisions MDL must be loaded with the low order 16 bits of the 32 bit dividend before the division is started After any division the MDL register represents the 16 bit quotient Figure 5 19 Muitiply Divide Register Low Portion MDL FEOEh 07h Reset Value 0000h MOL 15 0 Specifies the low order 16 bits of the 32 bit Multiply and Divide Register MD Whenever this register is updated via software the Multiply Divide Registe
198. h the contents of the stacked MULIP flag when the return from interrupt instruction RETI is executed This normally means that the MULIP flag is cleared again after that After reset all of the ALU status bits are cleared 3 2 2 CPU Interrupt Status IEN ILVL The Interrupt Enable bit allows to globally enable IEN 1 or disable IEN 0 interrupts The four bit Interrupt Level field ILVL specifies the priority of the current CPU activity The interrupt level is updated by hardware upon the entry into an interrupt service routine but it can also be modified by software to prevent other interrupts from being acknow ledged In the case that an interrupt level 15 has been assigned to the CPU it has the highest possible priority and thus the current CPU operation can not be interrupted ex cept by hardware traps or external non maskable interrupts For details about the SAB 80C166 interrupt system see chapter 7 0 After reset all interrupts are globally disabled and the lowest priority ILVL 0 is assigned to the inititial CPU activity 5 3 3 IP Instruction Pointer This register determines the 16 bit intra segment address of the instruction which is cur rently fetched within the code segment selected by the CSP register The IP register is not mapped into the SAB 80C166 s address space and thus it is not directly accessable by the programmer The IP can however be modified indirectly via the stack by means of a return ins
199. he PWRDN instruction is executed The microcontroller will then enter the Power Down mode after the PWRDN instruction has completed This feature can be used in conjunction with an external power failure signal which pulls the NMI pin low when a power failure is imminent The microcontroller will enter the NMI trap routine which can perform saving of the internal state into RAM After the internal state has been saved the trap routine may set a flag or write a certain bit pattern into specific RAM locations and then execute the PWRDN instruction If the NMI pin is still low at this time the Power Down mode will be entered otherwise program execution continues During power down the voltage at the Vcc pins can be lowered to 2 5 V and the contents of the internal RAM will be preserved Later when a reset occurs the initialization routine can check the identification flag or bit pattern in RAM to determine whether the controller was initially switched on or whether it was properly restarted from Power Down mode Siemens Aktiengesellschaft 12 1 Power Reduction Modes 12 2 Idie Mode One can decrease the power consumption of the SAB 80C166 microcontroller by entering Idle mode If enabled all peripherals INCLUDING the Watchdog Timer continue to func tion normally only the CPU operation is halted The Idle mode is entered after the IDLE instruction has been executed and the instruction before the IDLE instruction has completed To p
200. heir operation in the normal way Therefore all ports pins which are configured as general purpose output pins output the last data value which was written to their port output latches If the alternate output function of a port pin is used by a peripheral the state of the pin is determined by the operation of the peripheral Port 2 Port 3 In particular if CLKOUT the alternate output function of P3 15 has been enabled it is also active during Idle mode Port pins which are used for bus control functions go into that state which represents the inactive state of the respective function WR or to a defined state which is based on the last bus access BHE Pins which are dedicated for bus control functions are also held in the inactive state ALE RD Port pins which are used as external address data bus hold the address data which was output during the last external memory access before entry into Idle mode under the following conditions On PO0 15 8 Port O outputs the high byte of the last transferred address if the 16 18 bit address 8 bit data multiplexed bus mode is used otherwise all pins of Port 0 are floating Pins PO 7 0 are always floating in Idle mode Port 1 floates if the non multiplexed bus mode is used otherwise Port 1 acts as a general purpose 1 O port Port 4 outputs the segment address for the last access if segmentation is enabled otherwise Port 4 acts as a general purpose 1 O port During Power Down mo
201. hening The SAB 80C166 currently provides two methods to lengthen an access to external memories or peripherals One is the Memory Cycle Time Wait State which is used to lengthen the middle of a bus cycle the other is the Memory Tri State Time Wait State which lengthens the end of a bus cycle Now in the BA step it is possible to also lengthen the beginning of a bus cycle For this purpose an new bit ALECTL1 ALE Control Bit is implemented in the new BUSCON1 register Since in most cases a longer ALE pulse and longer address setup and hold times are only required by special peripheral components it is no restriction to offer this possibility only in the address range provided for the BUSCON1 register After reset the ALECTL1 bit is cleared to 0 and the bus cycle will be performed as specified for the AB step of the SAB 80C166 When ALECTL1 is set to 1 any access within the address Semiconductor Group D 11 SIEMENS SAB 80C166 83C166 range specified by the ADDRSEL1 register is lengthened by one machine state 50 ns 20 MHz CPU clock The ALE signal is lengthened by one TCL TCL 1 2 machine state 25 ns 20 MHz CPU clock and the address hold time after ALE is also lengthened by one TCL Figure 9 1 illustrates the bus cycle timing when ALECTL1 is set 10 Automatic Continuation of Reset Sequence The SAB 80C166 requires 1040 state times 52 us 20 MHz CPU clock in order to perform a complete reset sequence When a software r
202. her as one word wide memory and individually as two independent byte memories Siemens Aktiengesellschaft 9 8 External Bus Interface For the case where the two memories are accessed coupled together as one word wide memory the addressing scheme is the same as if only one 16 bit wide memory was used For the case where the memories are also accessed as independently suitable byte wide memories the External Bus Controller EBC must be enabled to use the function of the Byte High Enable pin BHE as described in the previous section 9 4 Figure 9 6 16 18 Bit Address 16 Bit Data Non Multiplexed Bus Byte Wide Memories Segment Addr Porta WR RD BHE Port 1 SAB 800166 ADDR CS OE WR l ADDR CS OE WR 8 Bit 8 Bit me Ext Memory Ext Memory INSTR DATA INSTR DATA Detailed application examples for the just mentioned external bus and memory configuration are shown in appendix C 9 6 External Bus Transfer Characteristics With regard to timing characteristics there are basicaily two types of external buses which can be configured These are multiplexed and non muitiplexed buses Transfer characteristics for these two types are described in detail in the following 9 6 1 Multiplexed Bus Transfer Characteristics In both Multiplexed Bus modes the resource External Bus is time shared between addresses and data Figure 9 7 shows the timing sequence of a memory read and memory write access via a multiplexed bus
203. high priority CPU interrupt if the COUNT field of the selected PEC channel contains 0 at the time this channel is invoked see section 7 2 2 1 7 2 3 3 Example for the Use of the CPU Priority The priority level of the routine currently being serviced by the CPU is indicated in the CPU Priority field ILVL of the PSW Modifying the CPU Priority field of the PSW by soft ware adds additional flexibility to the interrupt system of the SAB 80C166 For example it provides the user with a means of reducing the implemented number of 16 priority levels to any smaller integer number This may be desirable to preventa group of several different tasks with similar importance from interrupting each other It also reduces the stack depth For up to 4 tasks per group this can simply be done by assigning the associated interrupt sources to the same priority level in their ILVL field but to different group priorities in their GLVL field To prevent a group of more than 4 tasks with similar importance from interrupting each other the first action within an interrupt service routine of each of these tasks could be to set the CPU Priority field to the priority level ILVL of the source with the highest priority within this group In this way interrupt or PEC service requests of higher priority other than in this group are still accepted All interrupt requests of lower or equal priority become pending Thus the interrupt System operates as if ail tasks o
204. hing and filling To avoid movement of data that remains internally on the stack during flushing and filling a circular stack mechanism has been implemented by masking off the higher bits of the stack pointer Thus only portions of the internal RAM that are flushed or filled need to be moved Without this circular stacking the user would have to move each entry that re mained on the stack by the distance of the space being flushed or filled The circular stack technique requires that the internal stack be one of the following sizes 32 64 128 or 256 words When a boundary is reached the stack underflow or overflow trap is entered where the user moves a predetermined portion of the internal stack to or from the external stack The amount of data transferred is determined by the average stack space required by routines and the frequency of calls traps interrupts and returns In most cases this will be approximately one quarter to one tenth the size of the internal stack Once the transfer is complete the boundary pointers are updated to reflect the newly allocated space on the internal stack Thus the user is free to write code without concern for the internal stack limits Only the execution time required by the trap routines is seen by user pro grams Because of circular stacking data accessed at the boundary limits of the internal stack is accessed as if no boundary existed When data is pushed beyond the bottom of the internal memory
205. his applies to program execution from the internal ROM when no external operand read requests are performed and when the interrupt request flag is set during the last state of an instruction cycle When the request flag was set during the first state of an instruction cycle the PEC response time is 4 state times When internal hold conditions between instruction pairs N 2 N 1 or N 1 N occur the nini mum PEC response time may be extended by 1 state time for each hoid condition When instruction N reads an operand from the internal ROM or when N is a call return trap or MOV Rn Rm data16 instruction the minimum PEC response time may additionally be extended by 2 state times during internal ROM program execution In case instruction N reads the PSW and instruction N 1 has an effect on the condition flags the PECresponse time may additionally be extended by 2 state times The worst case PEC response time during internal ROM program execution is 9 state times 350 ns 2 40 MHz Siemens Aktiengesellschaft 7 23 Interrupt and Trap Functions The absoiute worst case PEC response time will occur when instructions N and N 1 are executed out of an external memory and both require external operand read accesses and instructions N 3 through N 1 write back external operands In this case the PEC res ponse time is the time to perform 7 word bus accesses Note that this worst case situa tion is rather untypical and occurs only when instructions N
206. hmetic and Logic Unit ios eo ok elo RERRaC SES oo eee 2 6 2 2 1 3 Barrel Shifter rie rateau Soe acexa s P a p RE RA RUR a 2 6 2 2 2 Peripheral Event Controller PEC and Interrupt Control 2 6 2 2 3 Internal BAM 12e ere orte aca eae vC ET RR wR LS 2 6 2 2 4 internal ROM 5 zd eser week eee vwd sau See atone tees 2 6 2 2 5 Clock Generator oair re Er CIR PAS ed Hass ware DON PE ES 2 7 2 2 6 Peripherals and Port llli 2 7 3 System Description useseses 3 1 3 1 Memory Organization 0 0 0 cece eee eee 3 2 3 2 External Bus Controller 2 0 cee eee ees 3 2 3 3 Central Processing Unit CPU 0 cee eee 3 3 3 4 Interrupt System lt 6 wees er erre Ses woe ee Rd Gory RR AS 3 4 3 5 Capture Compare CAPCOM Unit lesse 3 5 3 6 General Purpose Timer GPT Unit 2 00 00 eee 3 6 3 7 AID COMVOMON cos Ge ei ht Sieh Y ea Med Rondo ES OES 3 7 3 8 Serial Channels 1i ecd kr ieee pea ee ORI VC Da wt 3 8 3 9 Watchdog Tlmet erm oe ete 0 ba Gee PE CREER EY 3 8 3 10 Parallel POrtS 5 cede nee e EXER AM wee Rea RR RUE 3 9 4 Memory Organization ssess 4 1 4 1 Internal ROM 2d se ete dt Soe OR OUTRE ORO Ug RS 4 6 4 2 External Memory ico sux en axe qma hae US tns 4 7 4 3 Internal BAM 2 444 IER Xe IDE RIPEA E REESE ERE 4 8 4 3 1 System Stack tals E eco ee Sige ae ide AVR nk aoe 4 9 4 3 2 General Purpose Registers 0 e
207. icant bits of the required 18 bit addresses Basically the SAB 80C166 supports an 18 bit address space The 16 bit address mode refers to the case of segmentation being disabled Siemens Aktiengesellschaft 9 1 External Bus Interface Regardless of which external bus mode is selected accesses to addresses from OFAOOh through OFFFFh are performed internally In case of initializing the SAB 83C166 to the single chip mode internal ROM accesses become basically enabled and thus accesses to addresses from 00000h through 01FFFh are performed internally too Otherwise any access to addresses within the first 8 Kbytes would be performed externally In any case accesses to addresses from 02000h through OF9FFh or in any segment other than zero would be tried to be made externally Note however that external memory locations higher than OFFFFh cannot be accessed if the non segmented memory mode or the single chip mode is selected For more details about the SAB 80C166 s memory organization see chapter 4 0 9 1 External Bus Configuration During Reset Any of the initial external bus configuration modes is selected by means of two External Bus Configuration pins EBCO and EBC1 For that the input values on these dedicated pins are sampled during reset and copied into the BTYP bit field of the SYSCON register as follows SYSCON 7 EBC1 SYSCON 6 EBCO Table 9 1 shows the association between the initial EBCO and EBC1 input pin v
208. ice may drive the pin otherwise conflicts would occur When a Port 2 line is used as a compare output compare modes 1 and 3 refer to chapter 8 1 the compare event or the timer overflow in compare mode 3 directly affects the port output latch In compare mode 1 when a valid compare match occurs the state of the port output latch is read by the CAPCOM control hardware via the line Alternate Latch Data Input inverted and written back to the latch via the line Alternate Data Output The port output latch is clocked by the signal Compare Trigger which is generated by the CAPCOM unit In compare mode 3 when a match occurs the value 1 is written to the port output latch via the line Alternate Data Output When an overflow of the corresponding timer occurs a 0 is written to the port output latch In both cases the output latch is clocked by the signal Compare Trigger The direction of Semiconductor Group 10 9 SIEMENS Parallel Ports the pin should be set to output by the user otherwise the pin will be in the high impedance state and will not reflect the state of the output latch As can be seen from the block diagram the user software always has free access to the port pin even when it is used as a compare output This is useful for setting up the initial level of the pin when using compare mode 1 or the double register mode In these modes unlike in compare mode 3 the pin is not set to a specific value when a compare match occurs Ins
209. ich occur during their operation For interfacing with external hardware specific pins of ports P2 P3 or P5 are used when an input or output function has been selected for a peripheral During this time the port pins are controlled by the peripheral when used as outputs or by the external hardware which controls the peripheral when used as inputs This is called the alternate input or output function of a port pin in contrast to its function as a general purpose I O pin Each port consists of a port data register and a direction control register except for port 5 which is an input only port The name Px x 0 5 of a port data register is generally used to refer to the whole port Px For reference to a port pin the notation Px y y 0 15 for the associated bit in the port data register is used as well as the symbol for the alternate function of a port pin This chapter about the peripherals will provide all information which is necessary to use the alternate functions of a port in conjunction with a peripheral A detailed description of the internal port structure will be given in chapter 10 Parallel Ports Peripheral Timing Internal operation of CPU and peripherals is based on the oscillator frequency fosc divided by 2 The resulting frequency is referred to as system clock The basic time unit for internal operation of a chip is commonly called state time For the SAB 80C166 one state is defined as 2 periods of the o
210. idered Then the SYSCON register has to be programmed as follows MTTC 1 n3 MCTC 15 max n1 n2 Note For some memories the Chip Select Time ts may be as long as the Address to Valid Data In Time tage Formulas within this document do not consider any signal delay caused by the chip selecting logic All times are specified in nanoseconds ns unless noted otherwise Semiconductor Group C 10 SIEMENS Table C 1a Multiplexed Memory Read with Read Write Delay Application Examples Symbol Meaning 40 MHz Clock Variable Timing Dec Address to Valid Data In tece 2 7 4 n1 50 tees 2 ATCL 25 n1 2TCL ni22144 50 1 5 ini 2 tag 25 2TCL 2 be RD to Valid Data In be S ta n2 50 h_s 2TCL 15 n2 2TCL n22 50 0 7 n22 fo 15 2TCL 1 tut Data Float after RD typS tgtn3 50 tyes 2TCL 15 n3 2TCL n3 2 fy 50 0 7 n3 2 ty 15 2TCL 1 t ALE Cycle Time t 150 n 50 t 6TCL n 2TCL Note TCL 1 sc 25 ns at 40 MHz ALE Cycle Time Memory Cycle Time 26TCL 150 ns at 40 MHz for 0 wait state operation An address float time of 5 ns must be permissible l4 47 yg See Device Specification Section D 5 3 Table C 1b Multiplexed Memory Read with Read With Delay Quick Table lacc ni be n2 lat n3 lt 75 0 lt 35 0 lt 35 0 gt V5 ae SS 125 1 2 35 lt 85 1 35 lt 85 1 gt 125 lt 175 2
211. ill be requested after exiting the service routine Setting a trap request flag by software causes the same effects as if it had been set by hardware After the reset functions which have highest system priority trap priority IIl the traps of class A have the second highest priority trap priority il A class A trap can interrupt a class B trap but not another class A trap If more than oneof the class A traps occurs at a time an internal hardware prioritization takes place The NMI trap has the highest the stack underflow trap the lowest priority The traps of class B all have the same trap priority trap priority which is lower than the priority of class A traps Thus class B traps can never interrupt class A traps but pending class B traps will be executed after all class A traps are finished In the case ofsimultane ously occurring class B traps the corresponding flags in the TFR register are set and the trap service routine is entered Since ail class B traps have the same vector the priority of service of simultaneously occurring class B traps is determined by software in the trap service routine Siemens Aktiengesellschaft 7 27 interrupt and Trap Functions Figure 7 12 Trap Flag Register TFR TFR FFACh D6h Reset Vaiue 0000h 15 14 13 12 14 10 9 8 7 6 5 4 3 2 1 0 Symboi Position Funotion O External Non Maskable interrupt Trap request flag Set when a negative transition is detected at the NMI pin
212. imulation of the CPU and the on chip peripherals Real Time In Circuit Emulator Evaluation Board with monitor program Siemens Aktiengeseilschaft 1 4 SIEMENS Architectural Overview 2 Architectural Overview This chapter contains an overview of the SAB 80C166 s architecture with combines advantages of both RISC and CISC processors in a very well balanced way It introduces the features which do in sum result in a high performance microcontroller which is the right choice not only for today s applications but also for future engineering challenges 2 1 Basic CPU concepts and optimizations To meet the demand for greater performance and flexibility a number of areas has been optimized in the processor core These are summarized below and described in detail in the following sections 1 High Instruction Bandwidth Fast Execution 2 High Function 8 bit and 16 bit Arithmetic and Logic Unit Co Extended Bit Processing and Peripheral Control o A High Performance Branch Call and Loop Processing Consistent and Optimized Instruction Formats O Programmable Multiple Priority Interrupt Structure 2 1 1 High Instruction Bandwidth Fast Execution To achieve the desired performance a goal of approximately one instruction executed during each machine cycle was set for the core CPU Primarily this goal has been reached except for branch multiply or divide instructions These instructions however have also been optimi
213. ing Parameters This section provides tables which ease the calculation of the number of the SAB 80C166 s wait states which must be programmed into the MCTC bit field and or MTTC bit of the SYSCON register to match the external memory timing specifications The following particular memory accesses are considered in this section 1 Memory Read via a Multiplexed Bus with Read Write Delay 2 Memory Write via a Multiplexed Bus with Read Write Delay 3 Memory Read via a Non Multiplexed Bus with Read Write Delay 4 Memory Write via a Non Multiplexed Bus with Read Write Delay Two types of tables exist for each of these memory accesses The tables signified by an extension a contain formulas for the determination of both the maximum values of particular timing parameters at given numbers of wait states and of the numbers of required wait states at given timing parameter values These tables consist of columns as follows Symbol Specifies commonly used symbols of the particular timing parameters Meaning Provides a short explanation of the symbolic timing parameters 40 MHz Clock Specifies formulas to be used at a fixed oscillator frequency of 40 MHz Variable Timing Specifies formulas to be used at a variable oscillator frequency Other so called Quick Tables signified by an extension b contain results calculated by inserting typical values into the formulas represented in the corresponding table a The required nu
214. ing the READY line to a one But if the READY line is still low with the falling edge of the ALE signal the CPU interprets this as external device is ready and inserts no wait states during the following bus cycle A possible workaround for the AB step of the SAB 80C166 is to use external glue logic to hold the READY line high until the peripheral device is ready to correctly control the READY line This problem will be eliminated with the BA step since the CPU will first insert the programmed wait states before checking the READY line Semiconductor Group D 8 SIEMENS SAB 80C166 83C166 Figure 6 1 a and b illustrate this new feature In this example three wait states have been programmed in field MCTC of register SYSCON in addition to the READY function In Figure 6 1a the READY line goes to zero prior to the execution of the wait states but the chip continues to hold the memory access cycle until all wait states are performed This example could be the case when accessing a memory which just requires three wait states and where the READY line is brought to low with the Chip Select signal for the memory In Figure 6 1b after insertion of all three wait states the READY line is checked and found to be high The chip now continues to hold the memory access cycle until the READY line goes to low Then the bus cycle is terminated This example could be the case when accessing a slow peripheral device which in this case is slower tha
215. inning with the BA step of the SAB 80C166 the option to remap the address space of the on chip ROM or Flash EPROM for the SAB 80C166 from segment 0 to segment 1 will be implemented This feature will be implemented due to the following reasons If a customer is using the SAB 80C166 in several varying applications it is most likely that all applications share a common set of basic software functions for instance converting characters operating with floating point numbers etc Often only the real time control the interrupt procedures differ from application to application Since the interrupt vector table resides in the address space occupied by the on chip ROM this would either mean using different ROM masks for each application or using a ROMless chip with external memory With the new ROM mapping feature however the customer can benefit from the ROM chip in programming the common software routines into the on chip ROM using the fast execution speed and mapping it to segment 1 thus freeing the interrupt vector table space for the different interrupt routines now stored in smaller external memories Another possibility exists in that Siemens itself can program standard routines into the on chip ROM and sell this version as preprogrammed SAB 83C166 The user can map the on chip ROM to segment 1 use the segment 0 address space and the interrupt vector table space for his own routines and has access to standard software routines which he
216. inuous Conversion This mode is selected by setting field ADM in register ADCON to 11b The auto scan continuous mode differs from the auto scan mode described in the previous section only in that the converter does not stop after the conversion of channel ANO is completed The internal channel number counter is reloaded with the channel number which is specified in register ADCON and the conversion round is started again This procedure is repeated until the converter is stopped by software When bit ADST is reset by software the converter will continue until the conversion of channel ANO is complete It will then stop and reset bit ADBSY 8 3 2 A D Converter Interrupt Control At the end of each conversion interrupt request flag ADCIR in interrupt control register ADCIC is set This end of conversion interrupt request may cause an interrupt to vector ADCINT or it may trigger a PEC data transfer which stores the conversion result from register ADDAT e g into a table in the internal RAM for later evaluation Note that the number of the converted channel is contained in the four most significant bits in register ADDAT When the conversion result has not been read out of register ADDAT at the time the next conversion is complete the previous result will be overwritten and interrupt request flag ADEIR in register ADEIC will be set This overrun error interrupt request of the A D converter may be used to cause an interrupt to vector ADEINT Figure 8
217. ion Selected Tx Disabled 1 0 1 Positive Transition of T3OTL Source Edge T3OTL Select Interrupt Request P3 7 P3 5 Figure 8 2 12 Block Diagram of an Auxiliary Timer in Counter Mode Using the toggle bit T3OTL as a clock source for an auxiliary timer in counter mode offers the feature of concatenating the core timer T3 and an auxiliary timer Depending on which transition of T3OTL is selected to clock the auxiliary timer one can form a 32 bit or 33 bit timer This is explained in the following If both a positive and a negative transition of T3OTL is used to clock the auxiliary timer this timer is clocked one very overflow underflow of the core timer T3 Thus the two timers form a 32 bit timer If either a positive or a negative transition of TSOTL is selected to clock the auxiliary timer this timer is clocked on every second overflow underflow of the core timer This configuration forms a 33 bit timer 16 bit core timer T3OTL 16 bit auxiliary timer The count directions of the two concatenated timers are not required to be the same This offers a wide variety of different configurations A block diagram showing the concatenation of a core timer and an auxiliary timer is shown in figure 8 2 13 Semiconductor Group 8 37 SIEMENS Peripherals Interrupt Auxiliary Timer Tx D x 2 4 Note Line only affected by over underflows of T3 but NOT by software modifications of T3OTL Figure 8 2 13 Conncaten
218. ions llle 13 1 Modification of System Flags wc sse e m eR ee EE ERE ADR 13 1 External Memory Data AcceSS 0 00 cc eee eee 13 2 Multiplication and Division 00000 13 2 BCD Calculations 2 3926 pei Gee ue Sube ad Shae a MEO 13 4 Stack Operations ratio Dept citer Dutton fesses aident Pd acne a dU 13 4 Internal System tdeo oec s E ere oe 8 hes Dae Be RIDE e ac etc 13 4 Use of Stack Underflow Overflow Registers llli else 13 5 User Stacks 4 send nter dup oe qp e ERA UR E aea ra Rf N 13 6 Register Banking 5 soko RR EREGRTRUR ARGEATSLEREDI EC EA RYE 13 7 Procedure Call Entry and Exit laaa aaua 13 7 Passing Parameters on the System Stack 000 0c e eee eee 13 7 Gross Segment Subroutine Calls Goce dese nh ELI cle eee e dus 13 7 Providing Local Registers for SubroutineS 00000 cece eee 13 8 Table Searching es 6 2 6 426228 4024 REI ARE DORMIRE IRE Kad IR REO ex 13 9 Peripheral Control and Interface 00 00 c cee eee 13 9 Floating Point Support oorr per mex prem ee RR A 13 10 Trap Interrupt Entry and Exit aaua aaa 13 10 Support TOOIS s 10 uortaerre bale i hr ee eats godes abe aa ae a d 14 1 Hardware Support cunccesoUpREVpe pepe eee id rs Mex prex AREE 14 1 Software SUDDOI c eret Rd ur eR X RrEURE PE ACRES d e dee Nt 14 2 Assembler Package cei c oes sheep het ek 68S See OSLER ESE eee S 14 2 C COMPE ses a Ne gee e Sack eee teeta hate
219. ions Tiagqg 0 or 1 States Mostly NO extra time is required for conditional branch instructions to decide whether a branch condition is met or not However an additional state time will be caused if the preceding instruction writes to the PSW register as shown in the following example l BSET USRO write to PSW l JMPR cc Z label test condition flag in PSW Ti 1 State In this case the extra state time can simply be intercepted by putting another suitable instruction before the conditional branch instruction Siemens Aktiengesellschaft 5 11 Central Processing Unit CPU 7 Jumps into the internal ROM space T4 0 or 2 States As already described standard jumps into the internal ROM space require 4 state times to be executed This minimum time will be extended by 2 additional state times if the branch target instruction is a double word instruction at a non aligned double word location xxx2h xxx6h xxxAh xxxEh as shown in the following example label any non aligned double word instruction i e at location OFFEh l JMPA cc UC label if a standard branch is taken Tagg 2 States T 6 States A cache jump which normally requires just 2 state times will be extended by 2 additional state times if both the cached jump target instruction and its successor instruction are non aligned double word instructions as shown in the following example label any non aligned d
220. is shown in figure 7 4 Figure 7 4 Interrupt Control Functions in the PSW PSW FF10h 88h Reset Value 0000h 7 6 5 4 3 2 1 0 Lo we fw e z v J e vi ILVL CPU Priority Field PSW 15 12 These four bits represent the priority level of the routine that is currently being executed by the CPU During reset the CPU Priority field is initialized to the lowest priority level i e level 0 Upon entry to an interrupt service routine the four bits from the interrupt source s Priority Level field ILVL are copied into these four bits of the PSW after the previous contents of the PSW have been pushed onto the system stack To determine which interrupt will be serviced the interrupt system continuously compares the current CPU priority to the priority levels of all pending interrupts Modifying the ILVL field of the PSW offers the capability of programming the priority level below which the CPU can not be interrupted Because a PEC data transfer takes only one instruction cycle and is never interrupted the CPU priority field remains unaffected by a PEC service For hardware traps the CPU priority is set to the highest priority level i e 15 in the ILVL field of the PSW Therefore no interrupt or PEC request can be serviced while an exception trap service routine is in progress The software TRAP instruction however does not change the CPU priority in the ILVL field of the PSW thus it can be interrupted by higher level
221. isabled 0 1 Positive External Transition on CAPIN 1 0 Negative External Transition on CAPIN 1 1 Positive and Negative Transition External on CAPIN Semiconductor Group 8 51 SIEMENS Peripherals For triggering a capture operation on register CAPREL pin CAPIN P3 2 must be configured as input by setting its direction control bit DP3 2 to 0 The maximum input frequency for the capture trigger signal at pin CAPIN is f537 8 2 5 MHz fogc 40 MHz To ensure that a transition of the capture trigger signal is correctly recognized its level should be held for at least 4 state times before it changes When a selected transition at the external input pin CAPIN is detected the contents of the auxiliary timer T5 are latched into register CAPREL and interrupt request flag CRIR is set With the same event timer T5 can be cleared to 0000h This option is controlled by bit T5CLR in register T5CON If T5CLR 0 the contents of timer T5 are not affected by a capture If T5CLR 1 timer T5 is cleared after the current timer value has been latched into register CAPREL Figure 8 2 28 shows a block diagram of register CAPREL in capture mode Note that bit T5SC only controls whether a capture is performed or not If T5SC 0 the input pin CAPIN can still be used as an external interrupt input see also section 7 2 7 This interrupt is controlled by the CAPREL interrupt control register CRIC described in section 8 2 2 3 3 Interrupt Request Interrupt
222. ister and the Illegal Instruction Access trap is entered The IP value pushed onto the system stack is the illegal odd target address of the branch instruction 7 3 2 8 lllegal External Bus Access Trap Whenever the CPU requests an external instruction or data fetch and no external bus configuration has been specified in the BTYP field of the SYSCON register the ILLBUS flag in the TFR register is set and the Illegal Bus Access trap is entered The IP value pushed onto the system stack is the address of the instruction following the one which caused the trap Siemens Aktiengesellschaft 7 30 SIEMENS Peripherals 8 Peripherals This chapter provides a description of the functionality and programming of the peripherals incorporated in the SAB 80C166 Each of the peripheral units is discussed in a separate section the CAPCOM unit in section 8 1 the General Purpose Timers GPT in section 8 2 the A D Converter in section 8 3 the Serial Channels in section 8 4 and the Watchdog Timer in section 8 5 Peripheral Interfaces The peripherals generally have two different types of interfaces an interface to the CPU and an interface to external hardware Communication between CPU and peripherals is performed through Special Function Registers SFRs and interrupts The SFRs serve as control status and data registers for the peripherals Interrupt requests are generated by the peripherals based on specific events e g operation complete error wh
223. it States Introduce One Wait State Introduce No Wait States These programmable Memory Tri State Time wait states can be specified for all of the external bus configuration modes Note however that one implicit Memory Tri State wait state is automatically added for both multiplexed external bus configuration modes Siemens Aktiengesellschaft 9 17 External Bus Interface 9 7 3 Read Write Signal Delay The SAB 80C166 allows the user to adjust the timing of the data read and write output signals to account for timing requirements of external peripherals As shown in l figure 9 13 the Read Write Delay represents the period of time between the falling edge of the Address Latch Enable ALE signal and the falling edge of the read RD or write WR signal If no additional Read Write Delay is programmed the falling edges of the ALE WR and RD signals are coincident With the delay programmed the falling edge of the ALE signal leads the falling edges of the RD or WR signal by a quarter of a machine cycle An additional Read Write Delay does not extend the Memory Cycle Time and thus it does not slow down the controiler in general Figure 9 13 Memory Read Write Signal Delay Read Write Delay ALE The SAB 80C166 allows the user to disable or enable default after reset Memory Read Write Signal Delays by means of the RWDC bit in the SYSCON register as shown in table 9 5 One Read Write Signal Delay requires a quarter
224. ites it back to the output latch Writing to a pin configured as an output DPx y 1 causes the output latch and the pin to have the written value since the output buffer is enabled Reading this pin returns the value of the output latch A read modify write operation reads the value of the output latch modifies it and writes it back to the output latch thus also modifying the level at the pin Alternate Input and Output Functions of PO through P4 Each of the 76 port lines of the SAB 80C166 has an alternate input or output function associated with it 34 port lines have both an alternate input and output function the other 42 lines have either an alternate input or an alternate output function Semiconductor Group 10 5 SIEMENS Parallel Ports If an alternate output function of a pin is to be used the direction of this pin must be programmed for output DPx y 1 Otherwise the pin remains in the high impedance state and is not affected by the alternate output function If an alternate input function of a pin is used the direction of the pin must be programmed for input DPx y 0 if an external device is driving the pin The input direction is the default after reset If no external device is connected to the pin however one can also set the direction for this pin to output In this case the pin reflects the state of the port output latch Thus the alternate input function reads the value stored in the port output latch This can be u
225. k Each register bank may assign up to 16 registers Each register bank should be allocated during coding based on the needs of each task Once the internal memory has been partitioned into a register bank space internal stack space and a global internal memory area each bank pointer is then assigned Thus upon entry to a new task the appropriate bank pointer is used as the operand of the SCXT switch context instruction Upon exit from a task a simple POP instruction to the context pointer CP restores the previous task s register bank 13 6 Procedure Cail Entry and Exit To support modular coding a procedure mechanism is provided to allow coding of fre quently used portions of code into subroutines The CALL and RET instructions store and restore the value of the Instruction Pointer IP on the system stack before and after a subroutine is executed One must also ensure that any data pushed onto the system stack during execution of the subroutine is popped before the RET instruction is executed 13 6 1 Passing Parameters on the System Stack Parameters may be passed on the system stack through PUSH instructions before the subroutine is called and POP instructions during execution of the subroutine Base plus offset indirect addressing also permits access to parameters without popping these parameters from the stack during execution of the subroutine Indirect addressing pro vides a mechanism of accessing data referenced by data pointer
226. l Event Controller PEC This processor is used to off load many interrupt requests from the CPU It avoids the overhead of entering and exiting interrupt or trap routines by performing single cycle interrupt driven byte or word data transfers 2 Multiple Priority Interrupt Controller This controller allows all interrupts to be placed at any specified priority Interrupts may also be grouped which provides the user with the ability to prevent similar priority tasks from interrupting each other 3 Multiple Register Banks This feature allows the user to specify up to sixteen general purpose registers located anywhere in the internal RAM A single one machine cycle instruction is used to switch register banks from one task to another 4 Interruptable Multiple Cycle Instructions Reduced interrupt latency is provided by allowing multiple cycle instructions multiply divide to be interruptable 2 2 Functional Blocks The SAB 80C166 family clearly separates peripherals from the core This structure permits the maximum number of operations to be performed in parallel and allows peripherals to be added or deleted from family members without modifications to the core Each functional block processes data independently and communicates information over common buses Functional blocks in the CPU core are controlled by signals from the instruction decode logic Peripherals are controlled by data written to the Special Function Registers SFRs The f
227. l bus mode T ACT 2 15 MCTC 1 MTTC States 100 ns 900 ns for fosc 40 MHz In the case of the multiplexed external bus modes ACT 3 15 MCTC 1 MTTC States 150 ns 950 ns for fosc 40 MHz The total time Ti which a particular part of a program takes to be processed can be calculated by the sum of the single instruction processing times Tin of the considered instructions plus an offset value of 6 state times which considers the solitary filling of the pipeline as follows Trot Ty Ti Ti 6 States The time Tn which a single instruction takes to be processed consists of a minimum number Timin plus an additional number Tiasa of instruction state times and or ALE Cycle Times as follows Tin Timin Tadd 5 2 2 Minimum State Times The following table 5 1 shows the minimum number of state times required to process a SAB 80C166 instruction fetched from the internal ROM Timin ROM The minimum num ber of state times for instructions fetched from the internal RAM Timin RAM or of ALE Cycle Times for instructions fetched from the external memory Timin ext can also be easily calculated by means of table 5 1 Siemens Aktiengesellschaft 5 8 Central Processing Unit CPU Most of the SAB 80C166 instructions except some of the branches the multiplication the division and a special move instruction require a minimum of two state times In the case of internal ROM
228. l memory access Otherwise the system would be halted until a reset occurs No time out protection other than a Watchdog Timer overflow is provided for that case In order to allow one to interface to a variety of peripherals support for both asynchro nous and synchronous modes of operation is provided If the Data Ready function is en abled bit O in the SYSCON register the low bit of the MCTC bit field determines whether the READY input pin is to be used in asynchronous or synchronous mode SYSCON 0 1 Asynchronous READY input SYSCON 0 0 Synchronous READY input In the asynchronous mode of operation the READY input signal is internally synchroni zed to the microcontroller s operation In this case an additional delay of up to two state times may be required in order to internally synchronize the signal In the synchronous mode of operation it is the user s responsibility to ensure that the READY input signal meets the specified setup and hold times In order to obtain the necessary timing information and to perform external synchronization the Clock Output function can be used After reset the Data Ready function is disabled Siemens Aktiengesellschaft 5 16 Central Processing Unit CPU 5 3 1 5 Clock Output Pin Control via CLKEN The Clock Output function is enabled by setting the CLKEN bit of the SYSCON register to 1 If enabled port pin P3 15 takes on its alternate function as CLKOUT output pin The Clock Out
229. le Watchdog Timer Control Register WDTCON shown in figure 8 5 3 WDTCON FFAEh D7h Reset Value 0000h or 0002h 15 14 13 12 11 10 9 8 WDTREL 7 6 5 4 3 2 1 0 Epp pee rs qe m Figure 8 5 3 Watchdog Timer Control Register WDTCON Symbol Position Function WDTIN WDTCON O Watchdog Timer Input Frequency Selection WDTIN 0 fosc 4 WDTIN 1 fosc 256 WDTR WDTCON 1 Watchdog Timer Reset Indication Flag read only Set by Watchdog Timer overflow Cleared by hardware reset or by the SRVWDT instruction WDTREL WDTCON Reload Value for the high byte of the Watchdog Timer 15 8 reserved After any software external hardware or Watchdog Timer reset the Watchdog Timer is enabled and starts counting up from 0000h with the frequency fosc 4 The Watchdog Timer can be disabled via the instruction DISWDT Disable Watchdog Timer Instruction DISWDT is a protected 32 bit instruction which will ONLY be executed during the time between a reset and execution of either the EINIT End of Initialization or the SRVWDT Service Watchdog Timer instruction Either one of these instructions disables the execution of DISWDT Semiconductor Group 8 79 SIEMENS Peripherals When the Watchdog Timer is not disabled via instruction DISWDT it will continue counting up even during Idle Mode If it is not serviced via the instruction SRVWDT by the time the count reaches FFFFh the Watchdog Timer will overflow and cause an internal
230. led SxPEN 1 Parity Check Enabled SxFEN SxCON 6 Framing Check Enable Bit SxFEN 20 Framing Check Disabled SxFEN 1 Framing Check Enabled SxOEN SxCON 7 Overrun Check Enable Bit SxOEN 0 Overrun Check Disabled SxOEN 2 1 Overrun Check Enabled SxPE SxCON 8 Parity Error Flag Set by hardware when a parity error occurs and SxPEN 1 Mustbe reset by software SxFE SxCON 9 Framing Error Flag Set by hardware when a framing error occurs and SxFEN 1 Mustbe reset by software Overrun Error Flag Set by hardware when an overrun error occurs and SxOE SxCON 10 SxOEN 1 Must be reset by software Semiconductor Group D 15 SIEMENS SAB 80C166 83C166 SOCON FFBOh D8h Reset Value 0000h 15 14 13 12 11 10 9 8 som sue wee ee ore sore 7 6 5 4 3 2 1 0 pee eC eae ws c1 S1CON FFB8h DCh Reset Value 0000h 15 14 13 12 11 10 9 8 eS eo eel Eee CL 3 ELE 7 6 5 4 3 2 1 0 BE BE Eos ee ud Figure 2 1 cont d Serial Channels Control Registers SOCON and S1CON Symbol Position Function SxCON 12 reserved SxBRS SxCON 13 Baud Rate Selection Bit See description chapter 2 for more details SxLB SxCON 14 Loop Back Mode Enable Bit SxLB 0 Loop Back Mode Disabled SxLB 1 Loop Back Mode Enabled SxR SxCON 15 ASCx Baud Rate Generator Run Bit SxR 0 Baud Rate Generator Disabled SxR 1 Baud Rate Generator Enabled reserved X 0 1 Semiconductor Group D 16 SAB 80C166 83C166
231. lue cv1 0000h Reload Value lt lyREL gt Interrupt Requests i fr s Is lesus X M Event 1 Event 2 y 0 1 CCx cv2 CCx cv1 0 15 Figure 8 1 14 Timing Example for Compare Mode 2 8 1 2 2 4 Compare Mode 3 Compare mode 3 is selected for register CCx by setting bit field CCMODx of the corresponding mode control register to 111b In compare mode 3 only one compare event will be generated per timer period When the first match within the timer period is detected interrupt request flag CCxIR is set to 1 and pin COxIO alternate function of Port 2 pin P2 x will be set to 1 The pin will be reset to 0 when the allocated timer overflows If a match was found for register CCx in this mode all further compare events during the current timer period are disabled for CCx until the corresponding timer overflows If after a match was detected the compare register is reloaded with a new value this value will not become effective until the next timer period In order to use pin P2 x CCxlO as compare signal output pin for compare register CCx P2 x must be configured as output i e the corresponding direction control bit DP2 x in register DP2 must be set to 1 With this configuration the initial state of the output signal can be programmed or its state can be modified at any time by writing to bit latch P2 x Figure 8 1 15 shows the timing example from the previous section now for compare mode 3 The f
232. m Description to the high impedance state when configured as inputs During the internal reset all port pins are configured as inputs Each port line has one programmable alternate input or output function associated with it Ports 0 and 1 may be used as address and data lines when accessing external memory while Port 4 outputs the additional segment address bits A16 and A17 in systems where segmentation is enabled to access more than 64 Kbytes of memory Port 2 is associated with the capture inputs compare outputs of the CAPCOM unit and Port 3 includes alternate functions of timers serial interfaces optional bus control signals WR BHE READY and the system clock output CLKOUT Port 5 is used for the analog input channels to the A D converter When anyone of these alternate functions is not used the respective port line may be used as general purpose O line Semiconductor Group 3 9 Memory Organization 4 Memory Organization The SAB 80C166 family s memory space is configured in a Von Neumann architecture This means that code and data are accessed within the same linear address space All of the physically separated memory areas including the internal ROM forthe SAB 83C 166 internal RAM internal Special Function Registers SFRs and external memory are map ped into a common address space The SAB 80C166 provides a total addressable memory space of 256 Kbytes This address space is arranged in four segments of 64 Kb
233. mbers of wait states are specified in all subsequent tables by symbols as follows For memory read accesses n1 Number of wait states required to match Address to Valid Data In Time 0 lt n1 lt 15 n1 integer n2 Number of wait states required to match RD to Valid Data In Time 0 lt n2 lt 15 n2 integer n3 Number of wait states required to match Data Float After RD Time 0 lt n3 lt 1 n3 integer n Total number of resulting waitstates n max n1 n2 n3 Semiconductor Group C 9 SIEMENS Application Examples For memory write accesses nd Number of wait states required to match Write Pulse Low Time 0 lt n1 lt 15 n1 integer n2 Number of wait states required to match Data Valid to WR Time 0 lt n2 lt 15 n2 integer n Total number of resulting wait states required n max n1 n2 Note The SAB 80C166 s wait states can be programmed in increments of one To get the number of required wait states to be programmed any value n1 n2 n3 calculated by means of the formulas in tables a must be rounded up to the next integer value e g 1 2 2 2 If acalculation already supplies an integer result e g 1 0 one has to perform a worst case evaluation of the selected application signal delays etc to decide whether an additional waitstate must be considered or not If wait state calculations supply different values for the same programmable parameter the worst case maximum value must always be cons
234. me required by the memory to release the bus once the memory read RD signal has been deasserted As shown in figure 9 11 the Memory Tri State Time determines how quickly one memory access can follow another Figure 9 11 Memory Tri State Time a Memory Cycle Time De ALE N RO Memory Tri state Time If an external memory is too slow in releasing the bus after a memory read access the controller must wait for putting the next address on the bus until the bus is tri stated again Therefore an additional Memory Tri State Time wait state must be introduced before the next memory access The CPU is not idle during a Memory Tri State Time wait state Thus CPU operations will only be slowed down if a subsequent external instruction or data fetch operation is required during the next instruction cycle Figure 9 12 shows when a Memory Tri State Time wait state is introduced during the external memory accesses Siemens Aktiengeselischaft 9 16 External Bus Interface Figure 9 12 Memory Tri State Time Wait States Segment Address ALE BUS RD Wait State The SAB 80C166 allows the user to program O or 1 default after reset Memory Tri State Time wait state by means of the MTTC bit in the SYSCON register as shown in table 9 4 One Memory Tri State Time Wait State requires half a machine cycle 50 ns at fosc 40 MHz Table 9 4 MCTC Encoding of the Memory Tri State Time Wait State Wa
235. mer in this mode Table 8 2 4 GPT1 Core Timer T3 Counter Mode Input Selection TSI Counter T3 in Incremented Decremented on 2 1 0 0 0 0 No Transition Selected T3 Disabled 0 0 1 Positive External Transition at Pin T3IN 0 1 0 Negative External Transition at Pin T3IN 0 1 1 Positive and Negative Ext Transtion at T3IN 1 X X reseved Semiconductor Group 8 32 SIEMENS Peripherals Interrupt Request Figure 8 2 7 Block Diagram of Core Timer T3 in Counter Mode 8 2 1 1 4 Interrupt Control for Core Timer T3 When the timer T3 overflows from FFFFh to 0000h when counting up or when it underflows from 0000h to FFFFh when counting down interrupt request flag T3IR in register T3IC will be set This will cause an interrupt to the timer T3 interrupt vector T3INT or trigger a PEC service if the interrupt enable bit TSIE in register T3IC is set Figure 8 2 8 shows the organization of register T3IC Refer to chapter 7 for more details on interrupts T3IC FF62h B1h Reset Value 0000h 7 6 5 4 3 2 1 0 T3IR T3IE ILVL GLVL Figure 8 2 8 GPT1 Core Timer T3 Interrupt Control Register T3IC 8 2 1 2 GPT1 Auxiliary Timers T2 and T4 Both auxiliary timers T2 and T4 have exactly the same functionality They can be configured for timer gated timer or counter mode with the same options for the timer frequencies and the count signal as the core timer T3 In addition to these 3 counting modes the a
236. mory accesses are en abled during reset the BTYP bit field gets a read only access state and thus the external memory access mode selected once can not be changed later For further details about the external bus configuration and control see chapter 9 0 External Bus Interface Table 4 3 External Memory Access State Selection during Reset EBCO Pin External Memory Access disabled can be enabled via software EBC1 Pin enabled enabled enabled The external memory can be used for both code and data storage If the SAB 80C166 Segmentation mode is disabled SGTDIS bit in the SYSCON register contains a 1 all external memory accesses are restricted to segment 0 only Code accesses are always made on even byte addresses Thus the highest possible external code storage location in segment 0 is either OF9FEh for single word instructions or OF9FCh for double word instructions If used for code storage the corresponding location must contain a branch instruction because sequential boundary crossing from the external memory to the inter nal RAM space is not provided and would cause erroneous results In any segment other than 0 the highest code storage location is either xFFFEh for single word instructions or xFFFCh for double word instructions x 1 2 3 If used for code storage the correspon ding location must contain a branch instruction because segment crossing for program execution is only possi
237. mple if one wants to reprogram the BUSCON 1 register one should execute the instructions to modify the register from an address space which is currently controlled by the SYSCON register As mentioned before it is possible to switch from an 8 bit data bus to a 16 bit data bus and vice versa and to switch between a multiplexed and a non multiplexed bus There exists one condition however which presents a special case When switching from a non multiplexed bus to a multiplexed bus an extra hold state is required due to timing constraints In addition Port 1 which is used for the address bus continues to output the address although the address will also appear at Port 0 time multiplexed with the data This has the advantage that the chip select logic which is tied to the address bus does not have to either be switched from Port 1 to Port O or vice versa Figure 8 1 shows a timing diagram for switching from a non multiplexed bus to a multiplexed bus Note As long as any SYSCON or BUSCON1 selects a non multiplexed bus Port 1 is dedicated for the address bus function and can not be used as general purpose I O port In order to use Port 1 for general purpose I O both the SYSCON and the BUSCON1 register must select one of the multiplexed bus modes This is also true for the READY function In order to use the READY pin for general purpose I O RDYEN in register SYSCON and RDYEN1 in register BUSCON1 must be 0 9 Implementation of ALE Lengt
238. muitiply and divide operations internally Thus they should never be modified by the user except after having saved the previous MDC contents or by restoring the MDC register t jwenss When a division or multiplication was interrupted before its completion the MDC register must first be saved along with the MDH and MDL registers to be able to restart the inter rupted operation later and then it must be cleared to be prepared for the new calcula tion After completion of the new division or multiplication the state of the interrupted multiply or divide operation must be restored The MDRIU flag is the only portion of the MDC register which might be of interest for the user The remaining portions of the MDC register are reserved for a dedicated use by the hardware and thus they should never be modified by the user other than as described in the preceding paragraph Otherwise a correct continuation of an interrupted multiply or divide operation can not be guaranteed After reset this register is initialized to 0000h A detailed description of how to use the MDC register for programming multiply and divide algorithms can be found in section 13 2 5 3 13 ONES Constant Ones Register All bits of this bit addressable register are tied to 1 by hardware This register is read only The ONES register can be used as a register addressable constant of all ones i e for bit manipulation or mask generation It can be accessed via
239. n a normal bus cycle with three wait states 7 Implementation of an additional Bus Configuration Register In the current AB step the external bus configuration can only be changed via the SYSCON register This means that in order to access an external device with a different number of wait states a different bus width etc one has to reprogram the SYSCON register wait for the change to become active perform the access and then reprogram the SYSCON register to the former configuration Due to the pipeline this was a rather complicated process and several critical conditions had to be taken into account Now in the BA step a different bus configuration can be selected automatically within a user programmable address range For this purpose two new registers will be implemented The first register BUSCON1 Bus Configuration Register 1 is used to specify the desired configuration of the bus such as number of wait states data width etc while the second one ADDRSEL1 Address Select Register 1 specifies the address space in which these bus characteristics should become active In the BUSCON1 register all control bits of the SYSCON register relevant for configuring the external bus can also be found here Figure 7 1 shows the organization of register BUSCON1 With the Address Select Register ADDRSEL1 an address range is specified When an external access is made to this address range then instead of the SYSCON parameters the con
240. n be accessed bytewise or wordwise Particular portions of the on chip memory have additionally been made directly bit addressable The SAB 83C166 contains 8 Kbytes of a mask programmable on chip ROM for code or constant data A large dual port RAM of 1Kbyte is contained on both the SAB 80C 166 and the SAB 83C166 This internal RAM is provided as a storage for user defined variables for the system stack general purpose register banks and even for code A register bank can consist of up to 16 wordwide RO to R15 and or bytewide RLO RHO RL7 RH7 so called General Purpose Registers GPRs 512 bytes of the address space are reserved for the Special Function Register SFR area SFRs are wordwide registers which are used for controlling and monitoring functions of the different on chip units 98 SFRs are currently implemented Unused SFR addresses are reserved for future members of the SAB 80C166 family In order to meet the needs of designs where more memory is required than is provided on chip up to 256 Kbytes of external RAM and or ROM can be connected to the microcontroller 3 2 External Bus Controller All of the external memory accesses are performed by a particular on chip External Bus Controller EBC It can be programmed to either the Single Chip Mode when no external memory is required or to one of three different external memory access modes which are as follows 16 bit 18 bit Addresses 16 bit Data Non Multiplexed
241. n each stack access for the detection of a stack overflow or underflow The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly functional SAB 80C166 instruction set which includes the following instruction classes Arithmetic Instructions Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneous Instructions The basic instruction lenght is either 2 or 4 bytes Possible operand types are bits bytes and words A variety of direct indirect or immediate addressing modes are provided to specify the required operands 3 4 Interrupt System With an interrupt response time within a range from just 250 ns to 500 ns in case of internal program execution the SAB 80C166 is capable of reacting very fast to the occurence of non deterministic events The architecture of the SAB 80C166 supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller PEC
242. n is enabled and a trap is executed the CSP for the trap service routine is set to code segment 0 However the CPU Priority field of the PSW is not modified and the trap service routine is executed on the priority level from which it was invoked Therefore the service routine entered by the TRAP instruction can be interrupted by other traps or higher priority interrupts No Interrupt Request flags are affected by the TRAP instruction The interrupt service routine called by a TRAP instruction must be terminated with a RETI return from interrupt instruction to ensure correct return 7 3 2 Hardware Traps Hardware traps are used to identify faults or specific system states at runtime which cannot be identified at assembly time Eight different hardware trap functions are sup ported by the SAB 80C166 When a hardware trap condition has been detected the CPU branches to the trap vector location for the respective trap condition Depending on the trap condition the instruction which caused the trap is either compieted or cancelled i e it has no effect on the system state before the trap handling routine is entered Siemens Aktiengeselischaft 7 26 Interrupt and Trap Functions Hardware traps are non maskable and always have priority over every other CPU activity If several hardware trap conditions are detected within the same instruction cycle the highest priority trap is selected for servicing according to table 7 2 in section 7 1 Whe
243. n of the GPT1 timers for flexible PWM T2 is programmed to reload T3 on a positive transition of T3OTL while T4 will reload T3 on a negative transition of T3OTL The alternate output function for T3OTL is enabled T3OE 1 and the PWM output signal will be available at pin T3OUT with the configuration DP3 3 1 and P3 3 1 for port pin P3 3 as explained in section 8 2 1 1 The auxiliary timer T2 holds the value of the high time of the output signal while T4 is used to reload T3 with the value of the low time With this method the low and high time of the PWM signal can be varied in a wide range Note that T3OTL is implemented as a bit in SFR T3CON so that it can be altered by software if required to modify the PWM signal Reload Reg T2 Reload Reg T4 Note Lines only affected by over underflows of T3 but NOT by software modifications of T3OTL Figure 8 2 16 GPT1 Timer Configuration for PWM Generation 8 2 1 2 5 Capture Mode Capture mode is selected by programming the mode control fields T2M or TAM to 101b In capture mode the contents of the core timer are latched into an auxiliary timer register in response to a signal transition at the respective auxiliary timer s external input pin which is T21N P3 7 for timer register T2 or T4IN P3 5 for timer register T4 The capture trigger signal can be a positive a negative or both a positive and a negative transition Semiconductor Group 8 41 SIEMENS Peripherals The two least
244. n the TFR register but the IP value of the instruction which caused this trap is lost Siemens Aktiengesellschaft 7 28 interrupt and Trap Functions In the case where e g an Undefined Opcode trap occurs simultaneously with an NMItrap both the NMI and the UNDOPC flag is set the IP of the instruction with the undefined op code is pushed onto the system stack but the NMI trap is executed After return from the NMI service routine the IP is popped from the stack and immediately pushed again be cause of the pending UNDOPC trap 7 3 2 1 External NMI Trap Whenever a high to low transition on the dedicated external NMI pin Non Maskable Interrupt is detected the NMI flag in register TFR is set and the CPU will enter the Exter nal NMI trap routine The IP value pushed on the system stackisthe address ofthe instruc tion following the one after which normal processing was interrupted by the NMI trap 7 3 2 2 Stack Overflow Trap Whenever the Stack Pointer value is decremented to a value which is less than the value in the Stack Overflow register STKOV the STKOF flag is set in the TFR register and the Stack Overflow trap is entered Which IP value will be pushed onto the system stack de pends on which operation caused the decrement of the SP When an implicit decrement of the SP is made through a Push or Call instruction or upon interrupt or trap entry the IP value pushed is the address of the following instruction When the SP is decremen
245. nd AND the end of table has not been reached Note The last entry in the table must be equal to the lowest signed integer 8000h 13 8 Peripheral Control and Interface All communication between peripherals and the CPU is performed either by PEC trans fers to an from the internal memory or by explicitly addressing the SFRs associated with the specific peripherals After resetting the SAB 80C166 all peripherals except Watchdog Timer are disabled and initialized to default values To program a desired configuration of a specific peripheral one uses MOV instructions of either constants or memory values to specific SFRs One can also aiter specific control flags through bit instructions Siemens Aktiengesellschaft 13 9 System Programming Once in operation the peripheral operates autonomously until an end condition is reached at which time it requests a PEC transfer or requests CPU servicing through an interrupt routine One can also poll information from peripherals through read accesses of SFRs or bit operations including branch tests on specific control bits in SFRs To ensure proper allocation of peripherals among multiple tasks a portion of the internal memory has been made bit addressable to allow user semaphores Instructions have also been provided to lock out tasks through software by setting or clearing of user specific bits and conditionally branching based on these specific bits It is recommended that fields of bits in con
246. nd BFLDH to write to any number of bits in either byte of an SFR without disturbing the non addressed byte and the unselected bits 3 Some of the bits which are contained in the 80C166 s SFRs are marked as reserved User software should never write 1 s to reserved bits These bits are currently not implemented and may be used in future SAB 80C166 family products to invoke new functions In this case the active state for these functions will be 1 and the inactive state will be 0 In the SAB 80C166 the value read from reserved bits is O 8 1 Capture Compare CAPCOM Unit The CAPCOM unit supports generation and control of timing sequences on upto 16 channels with a minimum of software intervention The CAPCOM unit is typically used to handle high speed I O tasks such as pulse and waveform generation pulse width modulation or recording of the time at which specific events occur and it also allows the implemenation of up to 16 software timers The maximum resolution of the CAPROM unit is 400 ns 40 MHz oscillatorn frequency CAPCOM Block Diagram The CAPCOM unit consists of two 16 bit timers TO and T1 each with its own reload register TOREL and T1REL and a bank of sixteen dual purpose 16 bit capture compare registers CCO through CC15 The input clock for TO or T1 is programmable to several prescaled values of the system clock or it can be derived from an overflow underflow of timer T6 in block GPT2 TO may also operate in
247. nd direction registers of Port 4 are realized as byte wide registers Bits 2 through 7 are reserved bits while bits 8 through 15 are unimplemented Writing to the unimplemented bits has no effect while reading always returns zero In the following the symbol Px x 0 through 4 for a port data register is also used to refer to the whole Port x Semiconductor Group 10 1 SIEMENS Parallel Ports PO FFO0h 80h Reset Value 0000h 15 14 13 12 11 10 9 8 poss poss Pons Ponz post Poto roo Pos 7 6 5 4 3 2 1 0 Por ros ros Poa ros Poz ro Poo P1 FF04h 82h Reset Value 0000h 15 14 13 12 11 10 9 8 Pis piss prts Piae ern Prio mo rie 7 6 5 4 3 2 1 0 ez Pie Pis Pra pis Prz ma pio P2 FFCOh EOh Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LET ess esp esse eg me P3 FFC4h E2h Reset Value 0000h 0 acc e Figure 10 1 Ports 0 through 3 Data Registers PO P1 P2 P3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Symbol Position Function Px y Px y Port Px Data Register x 0 through 3 y 0 through 15 Semiconductor Group 10 2 SIEMENS Parallel Ports DPO FF02h 81h Reset Value 0000h 15 14 13 12 11 10 9 8 oes prora onse pren oro prono ro oros 7 6 5 4 3 2 1 0 ores eras oros ores oros oroz ors oroo DP1 FF06h 83h Reset Value 0000h ELO ER E2423 E5723 ERN EET a ICE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DP2 F
248. nd exceptions that arise during the execution of an instruction Hardware traps always have highest priority and cause immediate system reaction The software trap function is invoked by the TRAP instruction which generates a software interrupt for a specified interrupt vector For all types of traps the current program status is saved on the system stack Siemens Aktiengesellschaft 7 1 Interrupt and Trap Functions 7 1 interrupt System Structure In order to support modular and consistent software design techniques each source of an interrupt or PEC request is supplied with a separate interrupt control register and interrupt vector The controi register contains the interrupt request flag the interrupt enable bit and the interrupt priority of the associated source Each source request is activated by one specific event depending on the selected operating mode of the respec tive device The only exceptions are the two serial channels of the SAB 80C166 where an error interrupt request can be generated by a parity framing or overrun error How ever specific status flags which identify the type of error are implemented in the serial channels control registers see section 8 5 for details The SAB 80C166 provides a vectored interrupt system In this system certain vector loca tions in the memory space are reserved for the reset trap and interrupt service functions Whenever a request occurs the CPU branches to one ofthese locations
249. never a trap occurs the PSW the IP and in segmentation mode also the CSP are pushed on the system stack The CPU priority field of the PSW of the trap service routine is set to the highest possible priority level i e level 15 thus disabling all interrupts The CSP is set to code segment zero if segmentation is enabled The trap service routine must be terminated with the RETI instruction The eight hardware trap functions of the SAB 80C166 are divided into two classes class A and B The traps of class A are the external Non Maskable Interrupt NMI the Stack Overflow and the Stack Underflow trap All of these traps have the same trap priority but each of them has a separate vector address The traps of class B are the following Undetined Opcode Trap Protection Fault Trap Illegal Word Operand Access Trap Illegal Instruction Access Trap illegal External Bus Access Trap These trap functions all share the same trap priority and vector address In order to allow a trap service routine to identify the kind of trap which caused the ex ception a bit addressable Special Function Register the Trap Flag Register TFR is pro vided Figure 7 12 shows the configuration of this register For each trap function a separate request flag is implemented When a hardware trap occurs the corresponding request flag in the TFR register is set to 1 It must be reset by software in the trap service routine otherwise a new trap w
250. ng after the internal reset has completed its default clock frequency will be the internal system clock 2 10 MHz fosc 40 MHz and its de fault reload value is 00h such that a watchdog timer overflow will occur 131072 states 6 55 ms fosc 40 MHz after completion of the internal reset When the system reset was caused by a Watchdog Timer overflow the WDTR Watchdog Timer Reset Indica tion flag in register WOTCON will be set to 1 This indicates the cause of the internal reset to the software initialization routine WDTR is reset to 0 by an external hardware reset or by servicing the watchdog timer After the internal reset has completed the operation of the Watchdog Timer can be dis abled by the DISWDT Disable Watchdog Timer instruction This instruction has been im plemented as a protected instruction For further security its execution is only enabled in the time period after a reset until either the SRVWDT Service Watchdog Timer or the EINIT instruction has occurred Otherwise execution of the DISWDT instruction will have no effect More details about Watchdog Timer operation can be found in section 8 5 Siemens Aktiengesellschaft 11 3 System Reset 11 4 Ports and External Bus Configuration during Reset During the internal reset all of the SAB 80C166 s port pins are configured as inputs through their direction registers and are switched to the high impedance state see chap ter 10 for details about the internal po
251. nication are described in more detail Semiconductor Group 8 69 SIEMENS Peripherals 8 4 1 1 1 8 Bit Data Mode This mode is selected by programming the mode selection field SOM or S1M in register SOCON or S1CON to 001b The data frame which will be transmitted and or received consists of 8 data bits After a reception the upper byte of the receive buffer register contains zero The parity checking function upon reception is disabled in this mode independent of the state of SOPEN and S1PEN The overrun and framing checks however can be enabled 8 4 1 1 2 7 Bit Data Parity Bit Mode This mode is selected by programming the respective mode selection field SOM or S1M to 011b The data frame which will be transmitted and or received consists of 7 data bits and a parity bit All error checks may be enabled in this mode On transmission the parity bit is automatically generated by hardware and inserted at the MSB position of the data frame The parity bit is set to 1 if the modulo 2 sum of the 7 data bits is 1 otherwise it is cleared even parity On reception the parity on the 7 data bits received is generated by hardware The result is then compared to the 8th bit received which is the parity bit If the comparison proves false both the parity error flag and the error interrupt request flag for the respective serial channel are set provided the parity check has been enabled in the serial channel s control register The actual
252. njunction with the V flag the C flag allows evaiuating the rounding error with a finer resolution as shown in table 5 6 Table 5 6 Shift Right Rounding Error Evaluation Rounding Error Quantity No Rounding Error 0 lt Rounding Error lt 1 2 LSB Rounding Error 1 2 LSB Rounding Error 1 2 LSB For Boolean bit operations with only one operand the V flag is always cleared For Boolean bit operations with two operands the V flag represents the logical O Ring of the two specified bits C Flag After an addition the C flag indicates that a carry from the most significant bit of the specified word or byte data type has been generated After a subtraction or a comparison the C flag indicates a borrow which represents the logical negation of a carry for the addition This means that the C flag is set to 1 if no carry from the most significant bit of the specified word or byte data type has been generated during a subtraction which is performed internally by the ALU as a 2 s complement addition and the C flag is cleared when this complement addition caused a Carry The C flag is always cleared for logical multiply and divide ALU operations because these operations can not cause a carry anyhow For the shift and rotate operations the C flag represents the value of the bit shifted out last If a shift count of zero is specified the C flag will be cleared The C flag is also cleared for a prioritize ALU operation becau
253. no external program and or data memory is connected to the chip Port 0 PO and Port 1 P1 can be used as general purpose l O ports As described in Chapter 9 ports PO and P1 are used as the address and data lines in the various bus configurations which can be selected for connecting external memory to the chip Port 0 is used in all 3 external bus configurations while P1 is only used as the address bus A15 A0 in the 16 18 bit Address 16 bit Data Non Multiplexed Bus mode Port 1 can be used as a general purpose l O port in the multiplexed external bus configuration modes When a multiplexed bus configuration is selected and the CPU accesses external memory Port O first outputs the 16 bit intra segment address information as an alternate output function Port O is then switched to the high impedance input mode to read the incoming instruction or data In the 16 18 bit Address 8 bit Data Bus mode two memory cycles are required for word accesses the first for the low byte and the second for the high byte of the word When data is written to an external memory Port 0 outputs the data byte or word after outputting the address Semiconductor Group 10 6 SIEMENS Parallel Ports In the non multiplexed bus configuration Port 1 outputs the 16 bit intra segment address while Port 0 reads the incoming instruction or data word or writes the data to the external memory Therefore Port 0 has both alternate input and alternate output functions
254. no further action is required The following figure 5 8 shows the organization of the DPP registers Siemens Aktiengesellschaft 5 23 Central Processing Unit CPU Figure 5 8 Data Page Pointer Registers DPPO FE00h 00h Reset Value 0000h 15 14 13 12 11 10 3 8 7 6 5 4 3 2 1 0 DPP1 FEO2h 01h Reset Value 0001h 15 DPP2 FE04h 02h 15 14 DPP3PN DPPx 3 0 Specifies the data page number selected by DPPx In the case that segmentation is disabled only the two least significant bits of DPPxPN are significant DPPx 15 4 reserved Siemens Aktiengesellschaft 5 24 Central Processing Unit CPU Figure 5 9 Default Configuration of the Data Page Pointers Sixteen 16 KByte Pages Note that all of the internal memory is accessible via 16 bit addresses after reset 16 Bit Data Address orbs i DPP Registers specify 4 Bit Page Address Bit 3 2 Page DPP3 11b DPP2 4 10b 14 Bit Intra Page DPP1 4 01b Address DPPO 00b is concatenated to the DPP contents Data paging is performed by extending the lower 14 bits of indirect or direct long 16 bit addresses by the contents of a DDP register as shown in figure 5 10 The two MSBs of the 16 bit address are interpreted as the number of the OPP register which is to be used for the address extension The contents of the selected DPP register specify one of cur rently sixteen possible data pages This 4 bit data page number in additi
255. nous Mode P3 10 TXDO O Serial Channel 0 Data Output in Asynchronous Mode Clock Output in Synchronous Mode P3 11 RXDO O Serial Channel 0 Data Input in Asynchronous Mode Data Input Output in Synchronous Mode P3 12 BHE O Byte High Enable Control Signal for External Memory P3 13 WR O Write Strobe for External Data Memory P3 14 READY Ready Input P3 15 CLKOUT O System Clock Output Semiconductor Group 10 10 SIEMENS Parallel Ports on the operating mode of the serial channel they are associated with The alternate functions of Port 3 are listed in table 10 1 When the alternate input or output function of a Port 3 pin is not used this pin can be used as a general purpose I O pin When an alternate function is used on a Port 3 pin the configuration of this pin depends on the type of the alternate function There are four different configurations described in the following paragraphs 10 1 3 1 Port 3 Pins TOIN T2IN T3IN T4IN T3bEUD CAPIN and READY The basic structure of these seven Port 3 pins which only have an associated alternate input function is identical as shown in figure 10 9 Note that the READY pin has an additional alternate input line which is tied directly to the pin This line is used for the synchronous Ready function Write DP3 y Direction Latch DP3 y Read DP3 y Read Buffer Write Port P3 y Output Buffer P3 0 TOIN P3 2 CAPIN Clock P3 4 T3EUD P3 5 TAIN P3 6 T3IN
256. ns of the 16 capture compare registers are controlled by 4 bit addressable 16 bit mode control registers named CCMO CCM1 CCM2 and CCMB8 which are all organized identically Each register contains bits for the mode selection and timer allocation of four capture compare registers Figure 8 1 7 shows the organization of CAPCOM mode control register CCMO while figure 8 1 8 shows the organization of CAPCOM mode control registers CCM1 CCM2 and CCMS As the selection of the individual operating mode is identical for each of the capture compare registers only a detailed description of register CCMO is included in figure 8 1 7 The description for registers CCM1 through CCMS is identical except for the indices of the respective capture compare registers CCMO FF52h A9h Reset Value 0000h 1D 14 R z 9 8 7 6 5 4 3 2 1 0 ACC1 CMOD1 ACCO CMODO Figure 8 1 7 CAPCOM Mode Control Register CCMO Symbol Position Function CCMODO CCMO 2 0 Capture Compare Register CCO Mode Selection see table 8 1 3 ACCO CCMO 3 Capture Compare Register CCO Allocation Bit ACCO 20 COO allocated to Timer 0 ACCO 21 COO allocated to Timer 1 CCMOD1 CCMO 6 4 Capture Compare Register CC1 Mode Selection see table 8 1 3 ACC1 CCMO 7 Capture Compare Register CC1 Allocation Bit ACC1 20 CC1 allocated to Timer 0 ACC1 21 CC1 allocated to Timer 1 CCMOD2 CCMO 10 8 Capture Compare Register CC2 Mode Selection see table 8 1 3 ACC2 CCMO 11 Capture
257. nt up or down and the current timer value can be read or modified by the CPU in the non bit addressable SFRs T5 and T6 Each of the above features will be described in detail in the following subsections From a programmer s point of view the GPT2 block is represented by a set of SFRs as shown in figure 8 2 19 Those portions of port and direction registers which are not used for alternate functions by the GPT2 block are not shaded Semiconductor Group 8 43 SIEMENS Peripherals Ports amp Direction Control Data Control Interrupt Alternate Functions Registers Registers Control T6OUT P3 1 CAPIN P3 2 Port 3 Direction Control Register Port 3 Data Register GPT2 Timer 5 Register GPT2 Timer 6 Register GPT2 Capture Reload Register GPT2 Timer 5 Control Register GPT2 Timer 6 Control Register GPT2 Timer 5 Interrupt Control Register GPT2 Timer 6 Interrupt Control Register GPT2 CAPREL Interrupt Control Register Figure 8 2 19 SFRs and Port Pins Associated with the GPT2 Block 8 2 2 1 GPT2 Core Timer T6 The operation of the core timer T6 is controlled by the bit addressable control register TECON which is shown in figure 8 2 20 Semiconductor Group 8 44 SIEMENS Peripherals T6CON FF48h A4h Reset Value 0000h 15 14 13 12 11 10 9 8 CGS EG RC S aod i ED 7 6 5 4 3 2 1 0 acd adi adl Rc E MM AN Figure 8 2 20 GPT2 Core Timer T6 Contr
258. nterrupt request for vector CRINT or a PEC request will be generated See section 8 2 2 for further details on the GPT2 block The non maskable interrupt input pin NMI provides another possibility to obtain CPU reaction on an external input signal The NMI pin is a dedicated input pin which causes a hardware trap when a negative transition is detected on this pin The NMI trap function is discussed in detail in the following section 7 3 Trap Functions The SAB 80C166 provides two different kinds of trapping mechanisms These are software traps and hardware traps Trap functions offer the possibility to bypass the interrupt system s prioritization process in cases where immediate system reaction is required Trap functions are not maskable and always have priority over interrupt requests on any priority level 7 3 1 Software Traps The TRAP instruction is used to cause a software call to an interrupt service routine Associated with the trap instruction is a trap number that can be specified in the operand field of the instruction This trap number determines which vector location in the memory space from Oh through 1FCh will be branched to see also table 7 2 in section 7 1 Executing a TRAP instruction causes a similar effect as if an interrupt at the same vector had occured The IP and PSW and in segmentation mode also the CSP are pushed on the internal system stack and a jump is taken to the specified vector location When segmentatio
259. nversion on a line being used as a digital input will convert the logic level applied to the pin Table 10 3 illustrates the Port 5 lines and the corresponding analog input channels Semiconductor Group 10 16 SIEMENS Parallel Ports P5 FFA2h D1h Reset Value XXXXh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Lern BE a ee Figure 10 15 Port 5 Register P5 Symbol Position Function P5 y P5 y Port 5 Data Register READ ONLY y 0 through 9 P5 10 15 reserved Table 10 3 Alternate Functions of Port 5 Symbol Alternate Description Symbol P5 0 ANO Analog Input Channel 0 P5 1 AN1 Analog Input Channel 1 P5 2 AN2 Analog Input Channel 2 P5 3 AN3 Analog Input Channel 3 P5 4 AN4 Analog Input Channel 4 P5 5 AN5 Analog Input Channel 5 P5 6 ANG Analog Input Channel 6 P5 7 AN7 Analog Input Channel 7 P5 8 AN8 Analog Input Channel 8 P5 9 AN9 Analog Input Channel 9 Semiconductor Group 10 17 System Reset 11 System Reset The internal system reset function provides initialization of the SAB 80C166 into a defined default state This internal reset function is invoked by any of the following conditions 1 By asserting a hardware reset signal on the RSTIN Hardware Reset Input pin 2 Upon the execution of the SRST Software Reset instruction 3 By an overflow of the Watchdog Timer Whenever one of these conditions occurs the microcontroller is reset into its predefined default
260. o improve the safety of asynchronous data exchange the serial channels of the SAB 80C166 provide selectable hardware error detection capabilities For each channel three error status flags in the channel s control register SOCON or S1CON indicate whether an error has been detected during reception Upon completion of a reception the error interrupt request flag SOEIR or S1EIR will be set simultaneously with the receive interrupt request flag SORIR or S1RIR if one or more of the following conditions are met Ifthe framing error detection enable bit SOFEN or S1FEN is set and any of the expected stop bits is not high the framing error flag SOFE or S1FE is set indicating that the error interrupt request is due to a framing error Ifthe parity error detection enable bit SOPEN or S1PEN is set in the modes where a parity bit is received and the parity check on the received data bits proves false the parity error flag SOPE or S1PE is set indicating that the error interrupt request is due to a parity error If the overrun error detection enable bit SOOEN or S1OEN is set and the last character received was not read out of the receive buffer by software or PEC transfer at the time reception of a new frame is complete the overrun error flag SOOE or S1OE is set indicating that the error interrupt request is due to an overrun error In the following subsections specific characteristics of the individual operating modes for the asynchronous commu
261. o temporary flags The same logical instructions available for words and bytes are also supported for bits This allows the user to compare and modify a control bit for a peripheral in one instruction Multiple bit shift instructions have been included to avoid long instruction streams of single bit shift operations These are also performed in a single machine cycle In addition bit field instructions have been provided which allow the modification of multiple bits from one operand in a single instruction 2 1 4 High Performance Branch Call and Loop Processing Due to the high percentage of branching in controller applications branch instructions have been optimized to require one extra machine cycle only when a branch is taken This is implemented by precalculating the target address while decoding the instruction To decrease loop execution overhead three enhancements have been provided The first solution provides single cycle branch execution after the first iteration of a loop Thus only one machine cycle is lost during the execution of the entire loop In loops which fall through upon completion no machine cycles are lost when exiting the loop No special instructions are required to perform loops and loops are automatically detected during execution of branch instructions Semiconductor Group 2 2 SIEMENS Architectural Overview The second loop enhancement allows the detection of the ends of tables and avoids the use of two
262. of the 2 pointers either the Source or the Destination Pointer may be incremented it is not possible to increment both pointers after a transfer When the function increment no pointer is selected INC 00b the transfer is always performed between the same two memory locations Note When software tries to program the INC field to 11b this value is modified by hardware to 10b This will cause the Source Pointer to be incremented after a PEC data transfer BWT Byte Word Transfer Selection Bit This bit selects the data type to be transferred upon a PEC service request When the BWT bit is set to 1 the BYTE data type is selected for a PEC transfer When BWT is clea red the selected data type for a PEC transfer is WORD For byte transfers the optional increment value of the source or destination pointer is 1 For word transfers the optional increment value of the source or destination pointer is 2 Siemens Aktiengesellschaft 7 11 Interrupt and Trap Functions COUNT PEC Transfer Counter Field This 8 bit field is used to specify the number of data transfers to be performed by the respective PEC channel Either an unlimited or a limited number of transfers 0 through 254 can be programmed The Transfer Counter field operates as an 8 bit down counter Values from 0 through FFh can be specified in this field where 0 and FFh have a special meaning If the COUNT value is between FEh and 2 at the time the PEC service reques
263. of the corresponding capture compare register CCx must be configured for capture mode When CCMODx is programmed to 001b the interrupt request flag CCxIR in register CCxIC will be set on a positive external transition at pin CCxIO P2 x When CCMODx is programmed to 010b a negative external transition will set the interrupt request flag When CCMODXx 011b both a positive and a negative transition will set the request flag In all three cases the contents of the allocated CAPCOM timer TO or T1 will be latched into capture register CCx independent whether the timer is running or not When the interrupt enable bit COxIE is set a PEC request or an interrupt request for vector CCxINT will be generated For further details on the CAPCOM unit see section 8 1 Pins T2IN P3 7 or T4IN P3 5 can be used as external interrupt input pins when the associated auxiliary timer T2 or T4 in block GPT1 is configured for capture mode This mode is selected by programming the mode control fields T2M or T4M in control registers T2CON or TACON to 101b The active edge of the external input signal is determined by bit fields T2I or T4l When these fields are programmed to X01b interrupt request flags T21R or T4IR in registers T21C or T4IC will be set on a positive external transition at pins T2IN P3 7 or T4IN P3 5 respectively When T21 or T4l are programmed to X10b then a negative external transition will set the corresponding request flag When T2 or T4I are programm
264. of the timers is supported via the output toggle latch of timer T6 which changes its state on each timer overflow underflow The state of this latch may be used to clock timer T5 or it may be output on a port pin The overflows underflows of timer T6 can additionally be used to clock the CAPCOM timers TO or T1 and to cause a reload from the CAPREL register The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin and timer T5 may optionally be cleared after the capture procedure This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead 3 7 A D Converter For analog signal measurement a 10 bit A D converter with 10 multiplexed input channels and a sample and hold circuit has been integrated on chip It uses the method of successive approximation which returns the conversion result for an analog channel within 9 75 us fosc 40 MHz Overrun error detection capability is provided for the conversion result register an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete For applications which require less than 10 analog input channels the remaining channels can be used as digital input port pins The A D converter of the SAB 80C166 supports four different conversion modes In the standard Single Channel
265. oftware through the use of triggering conditions These triggering conditions are the same as those provided for the ICE In fact in order to provide a smooth transition from the simulator to the ICE environment the same user interface will also be provided with the ICE 14 3 Hosts All tools will initially be supported on standard PCs under DOS Future versions will be supported and on the VAX computer under VMS except ICE Siemens Aktiengeseilschatt 14 3 SAB 80C166 Registers SIEMENS B SAB 80C166 Registers This part of the Appendix contains a summary of all registers incorporated in the SAB 80C166 Section B 1 lists all CPU General Purpose Registers In Section B 2 all SAB 80C166 Specific Special Function Registers are summarized and ordered by address while Section B 3 lists all Special Function Registers in alphabetical order Semiconductor Group B 1 SIEMENS SAB 80C166 Registers B 1 CPU General Purpose Registers GPRs CPU General Purpose Registers are accessed via the Context Pointer CP The Context Pointer must be programmed such that the accessed GPRs are always located in the internal RAM space All GPRs are bit addressable B 1 1 Word Registers Name Physical 8 Bit Description Reset Address X Address Value RO CP 0 FOh CPU General Purpose Register RO XXXXh H1 CP 2 Fih CPU General Purpose Register R1 XXXXh R2 CP 4 F2h CPU General Purpose Register R2 X
266. oi Bit xxiE Interrupt disabled xxlE 1 Interrupt enabled Interrupt Request Flag xxIR 0 No interrupt request xxIR 1 Interrupt request xxIR Interrupt Request Flag This bit is set by hardware whenever a service request from source xx occurs The Interrupt Request flag is automatically cleared upon entry to the interrupt service routine or upon service of the request by the PEC In the case of PEC service the Interrupt Request flag remains set if the COUNT field of the selected PEC channel goes to zero see section 7 2 2 1 for details This allows a normal CPU interrupt to respond to a completed PEC block transfer Modifying the interrupt Request flag by software causes the same effects as if it had been set or cleared by hardware xxlE Interrupt Enable Flag This bit is used to individually enable or disable the acceptance of a service request ILVL Interrupt Priority Level Field xxIC 5 2 These four bits specify the priority level of a service request Values from Oh through Fh can be specified in this field where Fh represents the highest priority level Interrupt requests that are programmed to priority levels 15 or 14 i e ILVL 111Xb will be serviced by the PEC unless the COUNT field of the associated PEC channel contains zero In this case the request will be serviced by normal interrupt processing Interrupt requests that are programmed to priority levels 13 through 1 will always be serviced by normal inter
267. ol Register 2 0000h CCM3 FF58h ACh CAPCOM Mode Control Register 3 0000h FF5Ah ADh reserved FF5Ch AEh reserved FF5Eh AFh reserved T2IC FF60h BOh GPT1 Timer 2 Interrupt Control Register 0000h T3IC FF62h Bih GPT1 Timer 3 Interrupt Control Register 0000h T4IC FF64h B2h GPT1 Timer 4 Interrupt Control Register 0000h T5IC FF66h B3h GPT2 Timer 5 Interrupt Control Register 0000h T6IC FF68h B4h GPT2 Timer 6 Interrupt Control Register 0000h CRIC FF6Ah B5h GPT2 CAPREL Interrupt Control Register 0000h Semiconductor Group B 8 SIEMENS SAB 80C166 Registers Name Physical 8 Bit Description Reset Address Address Value SOTIC FF6Ch B6h Serial Channel 0 Transmit Interrupt Control 0000h SORIC FF6Eh B7h Serial Channel 0 Receive Interrupt Control 0000h SOEIC FF70h B8h Serial Channel 0 Error Interrupt Control 0000h Register S1TIC FF72h B9h Serial Channel 1 Transmit Interrupt Control 0000h S1RIC FF74h BAh Serial Channel 1 Receive Interrupt Control 0000h S1EIC FF76h BBh Serial Channel 1 Error Interrupt Control 0000h Register CCOIC FF78h BCh CAPCOM Register 0 Interrupt Control Register 0000h CC1IC FF7Ah BDh CAPCOM Register 1 Interrupt Control Register 0000h CC2IC FF7Ch BEh CAPCOM Register 2 Interrupt Control Register 0000h CC3IC FF7Eh BFh CAPCOM Register 3 Interrupt Control Register 0000h CC4IC FF80h Coh CAPCOM Register 4 Interrupt Control Register 0000h CC5IC FF
268. ol Register TOECON Symbol Position Function Tel T6CON 2 0 Timer 6 Input Selection see table 8 2 9 T6R T6CON 6 Timer 6 Run Bit T6R 20 Timer 6 stops T6R 1 Timer 6 runs T6UD T6CON 7 Timer 6 Up Down Control T6UD 0 Timer 6 is counting up T6UD 21 Timer 6 is counting down T6OE T6CON 9 Alternate Output Function Enable T6OE 0 Alternate output function disabled T6OE 1 Alternate output function enabled T6OTL T6CON 10 Timer 6 Output Toggle Latch Toggles on each overflow underflow of T6 Can be set or reset by software T6SR TCON 15 Timer 6 Reload Mode Enable Bit T6SR 20 Reload from register CAPREL disabled T6SR 21 Reload from register CAPREL enabled reserved The core timer T6 can only run in timer mode It is started or stopped by software through bit T6R Timer T6 Run Bit If T6R 0 the timer stops Setting T6R to 1 will start the timer The count direction can be controlled by software through bit T6UD Semiconductor Group 8 45 Peripherals SIEMENS 8 2 2 1 1 Timer T6 is clocked with the internal system clock divided by a programmable prescaler Eight different prescaler options can be selected by bit field T6l in control register T6CON The input frequency frs to timer T6 is scaled linearly with slower oscillator frequencies and is determined as follows Timer Mode fosc Ree 399 0 8 k o lt T6l gt The resulting input frequency resolution and timer period when using a 40 MHz oscill
269. ollowing sections describe the functional blocks of the SAB 80C166 and interactions between these blocks 2 2 1 16 Bit CPU 2 2 1 1 Instruction Decoding Instruction decoding is primarily generated from PLA outputs based on the selected opcode No microcode is used and eachpipeline stage receives control signals staged in control registers from the decode stage PLAs Pipeline holds are primarily caused by wait states for external memory accesses and cause the holding of signals in the control registers Multiple cycle instructions are performed through instruction injection and simple internal state machines which modify required control signals Semiconductor Group 2 4 SIEMENS Clock Generator Watchdog Timer 16 Bit Timer TO 16 Channel Capture Compare Unit 16 Bit Timer T1 External Bus Controller Architectural Overview ROM 8 KBytes SAB 83C166 16 Bit CPU Interrupt amp PEC Control General Purpose General Purpose Timer Unit Timer Unit GPT2 GPT2 16 Bit Timer T2 16 Bit Timer T3 16 Bit Timer T4 16 Bit Timer T5 16 Bit Timer T6 I O Ports Functional Block Diagram Semiconductor Group 10 Channel 10 Bit A D Converter Serial Channel ASCO Serial Channel ASC1 SIEMENS Architectural Overview 2 2 1 2 Arithmetic and Logic Unit All standard arithmetic and logical operations are performed in a 16 bit ALU In addition for byte operations signals are provided from bits six and
270. ollows The Memory Cycle Time can be ex tended within a range from 0 to 15 state times by means of the MCTC bit field 1 state time 2 1 fogc By means of the MTTC bit the Memory Tri State time can be exten ded by either 1 or 0 additional state time The Memory Tri State Time is additionally ex tended by one state time whenever a multiplexed external bus configuration is selected The RWDC bit allows programming a time delay of either 0 or 0 5 state times between the falling edges of the ALE and the Read Write signals This read write delay does not extend the general memory access time Note that additional external waitstates do not slow down internal memory accesses Table 5 3 summarizes the SYSCON control func tions for the external bus timing Table 5 3 SYSCON External Bus Timing Control Functions Control Value Number of Additional Affected Time Parameter State Times Memory Cycle Time 9 8 7 6 5 4 3 2 1 0 MTTC 1 Memory Tri State Time 0 RWDC 0 Read Write Signal Delay 0 BTYP Memory Tri State Time implicit implicit for multiplexed implicit bus configurations o 7 1 After reset the MCTC MTTC and RWDC are all initialized to zero Thus even very slow memories will be accessed correctly Siemens Aktiengesellschaft 5 15 Central Processing Unit CPU 5 3 1 3 Byte High Enable Pin Control via BYTDIS The BYTDIS bit is provided for controlling the active low Byte High Enable BHE pin
271. on of the internal reset and should remain disabled until the SP is initialized In addition the stack overflow STKOV and the stack underflow STKUN registers should be initialized After reset the CP SP and STKUN registers all contain the same reset value FCOOh while the STKOV register contains FAOOh With the default reset initialization 256 words of system stack are available where the system stack selected by the SP grows downwards from FBFEh while the register bank selected by the CP grows upwards from FCOOh Based on the application the user may wish to initialize portions of the internal memory before normal program operation Once the register bank has been selected through programming of the CP register one can easily perform memory zeroing through indirect addressing of the desired portions of the internal memory At the end of the initialization the interrupt system may be globally enabled by moving the appropriate constant to the PSW register One must be careful not to enable the interrupt system before initialization is complete The software initialization routine should be terminated with the EINIT instruction This instruction has been implemented as a protected instruction Execution of the EINIT in struction disables the action of the DISWDT instruction and causes the RSTOUT pin to go high see also figure 11 2 This signal can be used to indicate the end of the initializa tion routine and the proper operation o
272. on pipeline a POP or RETURN instruction must not imme diatly follow an instruction updating the SP register The maximum system stack size is programmable via the STKSZ bit field in the SYSCON register The address space which can be addressed via the SP register addresses from OF800h to OFFFEh can be regarded as virtual stack range while the physical system stack range is forced by the hardware to be situated within the internal RAM with its upper boundary at address OFBFEh and with its lower boundary at the memory location which is specified by the selected maximum stack size shown in table 5 7 Depending onthe selec ted maximum stack size different numbers of significant SP bits are used for the physical address calculation while the remaining bits are masked off Table 5 7 Selectable Physical System Stack Ranges Physical Stack Space FAOOh FBFFh puri LIN Fason rarm 9 Facon cram After reset the SP register is initialized in a way that the system stack can be accessed as usual as long as the dynamic stack boundaries do not exceed the selected maximum stack size This means that the virtual SP contents are directly mapped onto identical physical system stack addresses SYSCON STKSZ 00b Significant SP Bits O through 8 0 through 7 O through 6 0 through 5 The virtual stack address space is subdivided in portions whose size is identical to the maxi mum size of the selected physical stack
273. on reset signal mustbe 50 ms because the oscillator needs a start up time The internal pullup resistor may vary between 50 kQ and 150 kQ see aiso Appendix D 3 therefore the minimum power on reset time must be determined by the lowest value of this pullupresistor One may also use an additio nal external resistor In the reset circuit shown in figure 11 1b reset source 1 may be used e g for power on reset and reset source 2 for warm reset In the case of a warm reset where the oscillator is already stabilized the minimum low time of the reset signal at pin RSTIN is only 1040 state times 52 us 9 fosc 40 MHz The RSTOUT pin will be pulled low after a hardware reset signal has been asserted on the RSTIN pin It is also pulled low whenever the SRST instructionis executed or a Watch dog Timer overflow has occurred The signal on the RSTOUT pin can be used to simul taneously reset external hardware whenever the SAB 80C166 is reset The RSTOUT pin stays low until the protected EINIT End of Initialization instruction is executed Figure 11 2 shows the relation between the RSTIN and the RSTOUT signal Siemens Aktiengesellschaft 11 1 System Reset Figure 11 1 Reset Circuits a SAB 80C166 External HW Reset SAB 800166 Reset Source 1 Figure 11 2 Reset Function RSTIN won VC 7 f Watchdog Timer Overflow or SRST Instruction Executed EINIT Instruction Executed Siemens Aktiengesellschaft 11 2 S
274. on to the remai ning 14 bit page offset address forms the physical 18 bit address Siemens Aktiengesellschaft 5 25 Central Processing Unit CPU Figure 5 10 Addressing via the Data Page Pointers Sixteen 16 KByte in the case that segmentation is disabled only the two least significant bits of the DPPs are used and thus only pages 0 to 3 can be specified 16 Bit Data Address 15 14 DPP Registers specity 4 Bit Page Address DPP3 4 11b DPP2 10b n ntra Page DPPO 00b is concatenated to the DPP contents In the case of the non segmented memory mode only the two least significant bits of the implicitly selected DPP register are used forthe physical address generation just described Thus extreme care should be taken when changing a DPP register contents if a non segmented memory model is selected because otherwise unexpected results could occur In the case of the segmented memory mode bits 3 and 2 of the implicitly selected DPP register are output on the segment address pins A17 and A16 of Port 4 for all external data accesses A DPP register can be updated via any instruction which is capable of modifying an SFR Due to the internal instruction pipeline a new DPP value is not yet usable for the operand address calculation of the instruction immediately following the instruction updating the DPP register l Siemens Aktiengesellschaft 5 26 Central Processing Unit CPU 3 6 CP Context Poin
275. operation of the A D converter as illustrated in table 8 3 1 These modes will be discussed in detail in the following subsections Bit field ADCH in register ADCON specifies the analog input channel which is to be converted in the single channel conversion modes or the channel with which a conversion sequence of different channels will be started in the auto scan modes Table 8 3 2 shows the reference between the ADCH field and the selected input channels Programming ADCH to one of the reserved combinations will produce invalid results Semiconductor Group 8 56 SIEMENS Peripherals ADCON FFAOh DOh Reset Value 0000h 15 1 4 13 12 11 10 9 8 peg os s qp p OE 7 6 5 4 3 2 1 0 Figure 8 3 3 A D Converter Control Register ADCON Symbol Position Function ADCH ADCON 3 0 ADC Analog Input Channel Selection see table 8 3 2 ADM ADCON 5 4 ADC Mode Selection see table 8 3 1 ADST ADCON 7 ADC Start Bit ADBSY ADCON 8 ADC Busy Flag read only ADBSY 0 No conversions in progress ADBSY 1 Conversions in progress reserved Table 8 3 1 Conversion Mode Selection ADM Conversion Mode 1 0 0 0 Single Channel Conversion 0 1 Single Channel Continuous Conversion 1 0 Auto Scan Conversion 1 1 Auto Scan Continuous Conversion The A D Converter Result Register ADDAT shown in figure 8 3 4 holds the result of a conversion The low order 10 bits ADDAT 9 0 contain the converted
276. other on chip peripherals there is a closer conjunction between the Watch dog Timer and the CPU if enabled the Watchdog Timer expects to be serviced by the CPU within a programmable period of time otherwise it will reset the chip Thus the Watchdog Timer is able to prevent the CPU from going totally astray when executing er roneous code After reset the Watchdog Timer starts counting automatically but it can be disabled via software if desired By any reset the CPU is forced into a predefined active state Further particular CPU states are The IDLE state where the CPU clock is switched off and the peripheral clocks keep running and the POWER DOWN state where ail of the on chip clocks are switched off A transition into an active CPU state is forced by an interrupt if being IDLE or by a reset if being in POWER DOWN mode respectively The IDLE POWER DOWN and RESET states can be entered by particular SAB 80C166 system control instructions For more in formation on these states see chapter 11 0 Section 5 3 describes the Special Function Registers situated within the CPU core which are all dedicated to particular uses as follows General System Configuration SYSCON e CPU Status Indication and Control PSW e Code Access Control IP CSP e Data Paging Control DPPO DPP1 DPP2 DPP3 e GPRs Access Control CP e System Stack Access Control SP STKUN STKOV Multiply and Divide Support MDL MDH MDC ALU Constants Sup
277. ouble word instruction i e at location 12FAh hei 0 any non aligned double word instruction i e at location 12FEh Ine JMPR cc UC label provided that a cache jump is taken Trad 2 States Ti 4 States If required these extra state times can be avoided by allocating double word jump target instructions to aligned double word addresses xxxOh xxx4h xxx8h xxxCh 5 3 CPU Special Function Registers The core CPU requires a set of Special Function Registers SFRs to maintain the system state information to supply the ALU with register addressable constants and to control system configuration multiply and divide ALU operations code memory segmentation data memory paging and accesses onto the General Purpose Registers and the System Stack The access mechanism for these SFRs in the CPU core is identical to the access mecha nism for any other SFR Since all SFRs can simply be controlled by means of any instruc tion which is capable of addressing the SFR memory space a lot of flexibility has been gained and the need to create a set of system specific instructions was avoided Note however that there are user access restrictions for some of the CPU core SFRs to en Sure proper processor operations Siemens Aktiengesellschaft 5 12 Central Processing Unit CPU The PSW SP and MDC registers can be modified not only explicitly by the programmer but also implicitly by the CPU during normal instruction proce
278. paces fromOFFOO0h to OFFDFh in the internal SFR area from OFDOOh to OFDFFh in the internal RAM area and the ad dress space occupied by the currently selected register bank are basically provided for single bit accesses Figure 4 3a and 4 3b give an overview of the memory organization of the SAB 80C166 For more details about the different memory areas see the corresponding subsections in this chapter The principles of the physical address generation are describedin section 6 2 Addressing Modes Chapter 9 0 is dedicated to the External Bus Controller which is res ponsible for all of the memory accesses made externally Siemens Aktiengesellschaft 4 3 Figure 4 3a External Memory Organization Internal Memory see figure 64 KBytes External Memory 54 5 KBytes External Memory 02000h 8 KBytes Internal ROM or External Memory 00000h Siemens Aktiengesellschaft 4 4 Memory Organization 3FFFFh 2FFFFh 64 KBytes 1FFFFh External Memory 64 KBytes External Memory 30000h 20000h 10000h Memory Organization Figure 4 3b Internal Memory Organization 512 Bytes Internal SFRs Context see figure 4 3a Pointer Stack Pointer Y System Stack 1 KByte Internal RAM Bit Addressable Space Siemens Aktiengesellschaft 4 5 Memory Organization 4 1 Internal ROM The SAB 80C166 contains 8 Kbytes of on chip mask programmable ROM which is organi zed in 2K 32 bytes Internal ROM accesses b
279. parity bit received is placed in the 8th bit of the receive data buffer register The upper byte of the receive buffer register is always zero in this mode 8 4 1 1 3 9 Bit Data Mode This mode is selected by programming the respective mode selection field SOM or S1M to 100b The data frame which will be transmitted consists of the lower 9 bits of the transmit buffer register On reception all 9 data bits received are transferred from the receive shift register to the receive buffer register and the remaining 7 bits 9 through 15 of the receive buffer register are cleared to zero The parity checking function upon reception is disabled in this mode independent of the state of SOPEN and S1PEN The overrun and framing checks however can be enabled Semiconductor Group 8 70 SIEMENS Peripherals 8 4 1 1 4 8 Bit Data Wake Up Bit Mode This is a special mode provided to facilitate multiprocessor communication and it is selected by programming the mode selection field SOM or S1M to 101b The data frame which will be transmitted includes the lower 9 bits of the transmit buffer register The operation in this mode is basically the same as in the 9 bit data mode However on reception if the 9th data bit received is a 0 the received data are not transferred into the receive buffer registers SORBUF S1RBUF and no receive interrupt request will be generated A way to use this feature in multiprocessor systems is as follows When the maste
280. pective channel con tains 1 In the case of simultaneous requests where the COUNT field contains a value greater than 1 at the time the PEC channel is invoked only one PEC data transfer will be performed for ail of the simultaneous requests When the COUNT field contains 1 and simultaneous PEC requests for this channel are generated one PEC data transfer is performed and an interrupt to an un determined vector address may occur Figure 7 9 PEC Service Procedure SAB 80C166 Memory Space Segment 0 PEC Service Control wee ee HH Destination Pointer DSTP Byte Word Source Pointer SRCPy Data Decrement bit T URA Transfer 8 bit Transfer Counter zero Detect Increment I 1 1 1 1 i 1 PEC Service PEC Complete Service Generates Request CPU Interrupt Request Siemens Aktiengesellschaft 7 20 Interrupt and Trap Functions 7 2 6 Interrupt and PEC Response Times Interrupt response time is defined as the time required from the moment an interrupt request flag of an enabled interrupt source is set until fetching of the first instruction 11 at the interrupt vector location can begin In general the interrupt response time in the SAB 80C166 is 3 instruction cycles It depends on the instructions N through N 3which are in the pipeline at the time the request flag is set and on the following two instructions N 1 and N 2 This is explained by the pipeline diagram in figure 7 10 Figure 7 10 Pipeline
281. placed in special function registers which are visible to the debugging tools 14 2 Software Support Initially three major software tools will be offered to support the SAB 80C166 These are the assembler package the C compiler and the simulator package All software tools are written in standard C so they can be easily ported to a variety of hosts 14 2 1 Assembler Package The assembler package includes a macro assembler a linker a locator alibrary manager and an object to hex converter The macro assembler is a full featured assembler which contains features such as generating relocatable code supporting macros with optional parameters supporting conditional assembly supporting program moduies and data clas ses generating optional listing cross reference and symbol table outputs generating ob ject file with all information for use by other tools i e symbology with typing data clas ses modules etc The Linker will allow relocatable object modules to be connected together into a larger relocatable module In addition it will resolve any external references between the smal ler modules as far as possible Any unresolved references will be searched for in aspeci fied library Multiple or nested linking operations will be possible The Locator will allow a relocatable code to be given absolute addresses This allows the user to then load absolute code into the simulator or emulator environments The Locator can op
282. port ZEROS ONES 5 1 Instruction Pipelining As mentioned in the introductional part of this chapter a four stage instruction pipeline is implemented in the SAB 80C166 This means that instruction processing is partitioned in four stages of which each one has its individual task as follows 1st gt FETCH In this stage the instruction selected by the Instruction Pointer and the Code Segment Pointer is fetched from either the internal ROM internal RAM or externai memory 2nd gt DECODE In this stage the instructions are decoded and if required the operand addresses are calculated and the resulting operands are fetched For ail instructions which implicitly access the system stack the SP register is either decremented or incre mented as specified For branch instructions the Instruction Pointer and the Code Seg ment Pointer are updated with the desired branch target addresses provided that the branch is taken Siemens Aktiengesellschaft 5 2 Central Processing Unit CPU 3rd gt EXECUTE in this stage an operation is performed on the previously fetched ope rands in the ALU Additionally the condition flags in the PSW register are updated as specified by an instruction All explicit writes to the SFR memory space and all auto incre ment or auto decrement writes to GPRs used as indirect address pointers are performed during the execute stage of an instruction too 4th gt WRITE BACK In this stage all external operan
283. program execution there is no execution time dependency on the instruction length except for some special branch situations The injected target instruc tion of a cache jump instruction can be considered for timing evaluations as if being exe cuted from the internal ROM regardless of which memory range the rest of the current program is really fetched from For some of the branch instructions table 5 1 represents both the standard number of state times which means that the corresponding branch is taken and an additional Timin value in parentheses which refers to the case that either the branch condition is not met or that a cache jump is taken Table 5 1 Minimum Instruction State Times Instruction Timin ROM Timin ROM Unit i States at 20 MHz CPU clock Any except the following 2 100 ns CALLI CALLA 4 2 200 100 ns CALLS CALLR PCALL 4 200 ns JB JBC JNB JNBS 4 2 200 100 ns JMPS 4 200 ns JMPA JMPI JMPR 4 2 200 100 ns MUL MULU 10 500 ns DIV DIVL DIVU DIVLU 20 1000 ns MOV B Rn Rm data16 4 200 ns RET RETI RETP RETS 4 200 ns TRAP 4 200 ns Instructions executed from the internal RAM require the same minimum time as if being fetched from the internal ROM plus an instruction length dependent number of state times as follows For 2 byte instructions Ti RAM Timin ROM 4 States For 4 byte instructions Ti RAM Timin ROM 6 States In contrast to the internal ROM program execution
284. pt source through the ILVL and GLVL field in the interrupt control register of the res pective source see figure 7 2 Table 7 3 lists all PEC channel counter control registers while their organization is shown in figure 7 5 In the following their function will be discussed in detail Table 7 3 PEC Channel Counter Control Registers Summary Address Address Mandat COME FECOh 6h PECC4 FECB recon en Pecos recm reca em Pecce ren recm eon we rm 8 Bit Address Control Register PECCO Siemens Aktiengesellschaft 7 10 Interrupt and Trap Functions Figure 7 5 PEC Channel Counter Control Registers Organization y 0 through 7 PECCy Reset Value 0000h 15 14 13 12 11 10 9 8 a ee es ee ee x 7 6 5 4 3 2 1 0 COUNT Symbol PECCy 7 0 PEC Transfer Counter field COUNT FFh Continuous transfer mode COUNT value not decremented FEh gt COUNT 2 1 COUNT value decremented after each transfer COUNT 0 CPU interrupt is generated PECCy 8 Byte Word Transfer Select bit BWT 0 Word Transfer BWT t Byte Transfer PECCy 10 9 increment Control field INC 00b Increment no pointer INC 01b Increment destination pointer INC 10b increment source pointer INC 11b reserved INC Increment Control Field This 2 bit field specifies whether the Source Pointer or the Destination Pointer of the associated PEC channel shail be incremented after a PEC data transfer Only one
285. pt sources can be performed in several ways 1 Each interrupt source can be individually enabled or disabled by setting or clearing its Interrupt Enable flag in the interrupt control register that is associated with this source However as long as the global Interrupt Enable control bit IEN in the PSW has not been set all interrupt sources remain globally disabled and no interrupt requests will be acknowledged by the CPU 2 When the IEN bit in the PSW is set to 1 all interrupt sources that have been individu ally enabled become globally enabled Interrupt requests which are generated by these sources can then participate in the prioritization process The requests will be acknowledged by the CPU according to their priority 3 By programming the ILVL field of an Interrupt Control register to level 0 the associated source can never interrupt the CPU 4 Programming the CPU priority in the PSW to a certain level prevents the CPU from being interrupted by requests on the same or any lower level With this method all interrupts below a certain level can be disabled with one instruction e g the Bit Field BFLDH instruction 7 2 3 2 Priority Level Structure In the SAB 80C166 s interrupt system the priority of a request for interrupt or PEC ser vice is completely programmable All enabled source requests must be programmed to different priorities which means that sources which are programmed to the same priority level must be progr
286. put is a 50 duty cycle clock whose frequency is half the oscillator frequency four fosc 2 For a 40 MHz clock oscillator the CLKOUT frequency is 20 MHz Note that it is the user s responsibility to set the direction of the CLKOUT pin to output and to write a 1 into port latch P3 15 before using this function After reset the Clock Output function is disabled 5 3 1 6 Non Segmented Memory Mode Selection via SGTDIS The SGTDIS bit allows selecting either the segmented or non segmented memory mode In the case of the non segmented memory mode SGTDIS 1 the entire address space is restricted to 64 Kbytes segment 0 and thus ail addresses can be represented by 16bits Thus the contents of the CSP register are totally ignored and only the two least significant bits of the DPP registers are used for physical address generation This means also that the pins of Port 4 can be used as standard I O pins In the case of the segmented memory mode SGTDIS 0 the CSP and DPP registers are used for the generation of physical 18 bit addresses as described in sections 5 3 4 and 5 3 5 The pins of Port 4 are used as address pins A17 and A16 provided that an external bus has been configured Whenever the segmented memory mode is selected the CSP register is pushed onto the system stack in addition to the IP register before an interrupt service routine is entered and it is repopped when the interrupt service routine is left again Afte
287. r 10 0 Parallel Ports Atable containing a short des cription symbolic addresses physical 18 bit and short 8 bit addresses ofthe SFRs can be found in appendix B Most commonly an SFR can be accessed wordwise via an implicit base address plus a short 8 bit offset address independent of the current DPP register contents The low byte portion of an SFR but not its high byte portion can be accessed via these short 8 bit addressing modes However provided that the selected DPP register points to data page 3 any high byte low byte or any word in the SFR memory space can be accessed via an indirect or long 16 bit addressing mode The upper portion of the SFR memory space addresses from OFFOOh to OFFDFh con tains SFRs with many single flag control functions Thus this memory area is directly bit addressable Some bits in already existing SFRs and some word locations in the SFR address space have been reserved for a future implementation of additional on chip peripherals Any intended write access to such a reserved SFR memory space would be ignored by the machine and any intended read would supply a read result of 0 Note that any byte write to an existing SFR causes the non addressed complementary byte to be cleared Some SFRs or parts of them have a restricted access type such as read only or write only For more details see the functional description of the corresponding SFRs Siemens Aktiengesellschaft 4 12 Central Proc
288. r 3 Register 4 Bits 0003h MDC b FEOEh 87h CPU Multiply Divide Control Register 0000h MDH FEOCh 06h CPU Multiply Divide Register High Word 0000h MDL FEOEh 07h CPU Multiply Divide Register Low Word 0000h ONES b FF1Eh 8Fh Constant Value 1 s Register read only FFFFh Semiconductor Group B 14 SIEMENS SAB 80C166 Registers Name Physical 8 Bit Description Reset Address Address Value PO b FFOOh 80h Port 0 Register 0000h P1 b FF04h 82h Port 1 Register 0000h P2 b FFCOh EOh Port 2 Register 0000h P3 b FFC4h E2h Port 3 Register 0000h P4 b FFO8h 84h Port 4 Register 2 Bits 0000h P5 b FFA2h D1h Port 5 Register 10 Bits read only XXXXh PECCO FECOh 60h PEC Channel 0 Control Register 0000h PECC1 FEC2h 61h PEC Channel 1 Control Register 0000h PECC2 FEC4h 62h PEC Channel 2 Control Register 0000h PECC3 FEC6h 63h PEC Channel 3 Control Register 0000h PECC4 FEC8h 64h PEC Channel 4 Control Register 0000h PECC5 FECAh 65h PEC Channel 5 Control Register 0000h PECC6 FECCh 66h PEC Channel 6 Control Register 0000h PECC7 FECEh 67h PEC Channel 7 Control Register 0000h PSW b FF10h 88h CPU Program Status Word 0000h SOBG FEB4h 5Ah Serial Channel 0 Baud Rate Generator 0000h Reload Register SOCON b FFBOh D8h Serial Channel 0 Control Register 0000h SOEIC b FF70h B8h Serial Channel 0 Error Interrupt Control 0000h SORBUF FEB2h 59 Serial Channel 0 Receive Buffer Register
289. r In Use MDRIU flag in the Multiply Divide Control register MDC is set to 1 The MDRIU flag is cleared whenever the MDL register is read via software When a multiplication or division is interrupted before its completion and when a new multiply or divide operation is to be performed in the interrupt service routine the MDL register must be saved along with the MDH and MDC registers to avoid erroneous results After reset this register is initialized to 0000h A detailed description of how to use the MDL register for programming multiply and divide algorithms can be found in section 13 2 5 3 1 2 MDC Multiply Divide Contro Register This bit addressable 16 bit register is implicitly used by the CPU when it performs a multiplication or a division It is used to store the required control information for the corresponding multiply or divide operation The MDC register is updated by hardware during each single cycle of a multiply or divide instruction Siemens Aktiengesellschaft 5 35 Central Processing Unit CPU Figure 5 20 Muitiply Divide Control Register MDC FEOEh 87h Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EUNT set to 1 when the MDL or MDH register is written by software or when a divide or multiply instruction is executed This MD Register in Use Flag is cleared when the MDL register is read by software These bit portions are used by the machine for controlling
290. r processor wants to transmit a block of data to one of several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the additional 9th bit is a 1 for an address byte and a 0 for a data byte Operating in the 8 bit data wake up bit mode no slave will be interrupted by a data byte An address byte however will interrupt all slaves so that each slave can examine the 8 LSBs of the received character and see if itis being addressed The addressed slave will switch its operating mode to the 9 bit data mode e g by clearing bit SxM 0 see table 8 4 1 and prepare to receive the data bytes that will be coming The slaves that were not being addressed remain in the 8 bit data wake up bit mode ignoring the incoming data bytes 8 4 1 1 5 8 Bit Data Parity Bit Mode This mode is selected by programming the respective mode selection field SOM or S1M to 111b The data frame which will be transmitted and or received consists of 8 data bits and a parity bit All error checks may be enabled in this mode On transmission the parity bit even parity is automatically generated based on the 8 data bits and inserted at the MSB position of the data frame On reception the parity on the 8 data bits received is generated and the result is compared to the 9th bit received which is the parity bit If the compared bits are different both the parity error flag and the error interrup
291. r reset the segmented memory mode is selected by default 5 3 1 7 Maximum System Stack Size Selection via STKSZ The maximum size of the system stack is directly determined by the two bit field STKSZ as shown in table 5 4 Table 5 4 Maximum System Stack Size Selection Maximum System Stack Size Note that the contents of the STKSZ bit field immediately affect the physical stack address generation via the SP register described in section 5 3 6 After reset the maximum stack size of 256 word locations is selected by default Siemens Aktiengesellschaft 5 17 Central Processing Unit CPU 5 3 2 PSW Processor Status Word This bit addressable register reflects the current state of the microcontroller It is subdi vided into two parts of which the first one contains bits which represent the current ALU status and the second bits which determine the current CPU interrupt status A separate bit USRO within the PSW register is provided for use as general purpose flag Figure 5 5 Processor Status Word Register PSW FF10h 88h Reset Value 0000h 15 14 13 12 11 10 9 8 un pee e 7 6 5 4 3 2 1 0 Position Function PSW 0 This bit represents a negative result from the ALU See subsection 5 3 2 1 for details PSW 1 This bit represents a carry result from the ALU See subsection 5 3 2 1 for details V PSW 2 This bit represents an overflow result from the ALU See subsection 5 3 2 1 for detaiis PSW 3 This bit represents a ze
292. r which supports a wide range of baud rates without oscillator tuning Figure 8 4 1 gives an overview of the SFRs and port pins which are associated with the serial channels Those portions of Port 3 and its direction control register DP3 which are not used for alternate functions by the serial channels are not shaded Semiconductor Group 8 61 SIEMENS Peripherals Ports amp Direction Control Data Registers Control Registers Interrupt Control Alternate Functions RXDO P3 11 TXDO P3 10 RXD1 P3 9 TXD1 P3 8 DP3 Port 3 Direction Control Register P3 Port 3 Data Register SOBG Serial Channel 0 Baud Rate Generator Reload Register SOTBUF Serial Channel 0 Transmit Buffer Register write only SORBUF Serial Channel 0 Receive Buffer Register read only S1BG Serial Channel 1 Baud Rate Generator Reload Register S1TBUF Serial Channel 1 Transmit Buffer Register write only S1RBUF Serial Channel 1 Receive Buffer Register read only SOCON Serial Channel 0 Control Register S1CON Serial Channel 1 Control Register SOTIC Serial Channel 0 Transmit Interrupt Control Register SORIC Serial Channel 0 Receive Interrupt Control Register SOEIC Serial Channel 0 Error Interrupt Control Register S1TIC Serial Channel 1 Transmit Interrupt Control Register S1RIC Serial Channel 1 Receive Interrupt Control Register S1EIC Serial Channel 1 Error Interrupt Control Register Figure 8
293. ransfer count option CPU interrupt generation after a programmable number of PEC transfers e Eliminates overhead of saving and restoring system state for interrupt requests Intelligent Peripheral Subsystems 10 Channel 10 bit A D Converter 9 75 ps conversion time auto scan modes 16 Channel Capture Compare Unit with 2 independent time bases very flexible PWM unit event recording unit with 5 different operating modes includes two 16 bit timers counters with 400 ns maximum resolution e 2 Multifunctional General Purpose Timer Units GPT1 three 16 bit timers counters 400 ns maximum resolution GPT2 two 16 bit timers counters 200 ns maximum resolution e 2 Serial Channels USART with independent baud rate generators provide parity framing and overrun error detection e Watchdog Timer with programmable time intervals 76 VO Lines With Individual Bit Addressability Tri stated in input mode Schmitt Trigger characteristics Different Temperature Ranges e Oto 70 C 40 to 85 C 40 to 110 C 1 2 micron Siemens CMOS Process Low Power CMOS Technology including power saving Idle and Power Down modes Siemens Aktiengesellschaft 1 3 Introduction 100 Pin Plastic Quad Fiat Pack PQFP Package e JEDEC standard 25 mil 0 635 mm lead spacing surface mount technology Complete Development Support C Compiler Macro Assembler Linker Locater Library Manager Object to Hex Converter Simulator for the complete s
294. requests Siemens Aktiengesellschait 7 9 interrupt and Trap Functions IEN Interrupt Enable Control Bit PSW 11 This bit globally enables or disables PEC operation and the acceptance of interrupts by the CPU When IEN is cleared no interrupt requests are accepted by the CPU When IEN is set to 1 all interrupt sources which have been individually enabled by the Inter rupt Enable bits in their associated control registers are globally enabled Note Traps are non maskable and are therefore not affected by the IEN bit 7 22 PEC Service Channels Register Description The SAB 80C166 s Peripheral Event Controller PEC provides 8 PEC Service Channels Upon an interrupt request a PEC channel is capable of performing a single byte or word data transfer between any two memory locations in segment 0 data pages 0 through 3 Each channel consists of a dedicated PEC Channel Counter Control register and a pair of pointers for source and destination of the data transfer 7 2 2 1 PEC Channel Counter Controi Registers Each of the 8 PEC service channels implemented in the SAB 80C166 is supplied with a separate PEC Channel Counter Control register Note that these registers are NOT bit addressable They will be referred to as PECCy where y represents the number of the associated PEC channel y 2 0 through 7 Each register specifies the task which is to be performed by the associated PEC channel A specific PEC channel is selectedbyaninter ru
295. required and decreasing decode complexity In order to aid assembly programming these instructions familiar from other micrccontrol lers can be built in macros The following subsections describe methods of providing the function of these common instructions 13 1 1 Directly Substitutable Instructions Instructions known from other microcontrollers can be replaced by the following instructions on the SAB 80C166 Table 13 1 Instruction Equivalents Other uC Function CLR Rn AND Rn 0h Clear Register CPLB Bit Complerhent Bit DEC Rn SUB Rn 1h Decrement Register INC Rn ADD Rn 1h Increment Register SWAPB Rn ROR Rn 8h Swap Bytes in Word 13 1 2 Modification of System Flags All bit and word instructions can access the PSW register Thus to set or clear PSW flags no CLEAR CARRY or ENABLE INTERRUPTS instruction isrequired These functions are performed using bit set or clear BSET BCLR instructions Siemens Aktiengesellschaft 13 1 System Programming 13 1 3 External Memory Data Access By providing a Von Neumann memory architecture and by providing hardware to detect access to internal RAM GPRs and SFRs specialinstructions are notrequired to load data pointers or explicitly load and store external data See chapter 6 for a detailed description of data addressing modes 13 2 Multiplication and Division Multiplication and division of words and double words is provided through multiple cycle instructions implementing
296. reset This reset will pull the external reset indication pin RSTOUT low It differs from a software or external hardware reset in that bit WDTR Watchdog Timer Reset Indication flag of register WOTCON will be set A hardware reset or the SRVWDT instruction will clear this bit Bit WDTR can then be examined by software in order to determine the cause of the reset To prevent the Watchdog Timer from overflowing it must be serviced periodically by the user software The Watchdog Timer is serviced with the instruction SRVWDT which is a protected 32 bit instruction Servicing the Watchdog Timer clears the low byte and reloads the high byte of the Watchdog Timer Register WDT with the preset value in bit field WDTREL which is the high byte of register WDTCON Servicing the Watchdog Timer will also reset bit WDTR After being serviced the Watchdog Timer continues counting up from lt WDTREL gt 28 Instruction SRVWDT has been encoded in such a way that the chance of unintentionally servicing the Watchdog Timer is minimized When instruction SRVWDT does not match the format for protected instructions the Protection Fault trap will be entered see section 7 3 2 5 The time period for an overflow of the Watchdog Timer is programmable in two ways First there are two options for the input frequency to the Watchdog Timer Either fosc 4 or fosc 256 can be selected by bit WDTIN in register WDTCON Second the reload value WDTREL for the high byte of WDT can be
297. revent unintentional entry into Idle mode the IDLE instruction has been implemented as a protected instruction The Idle mode is terminated by interrupt requests from any enabled interrupt source whose individual Interrupt Enable flag was set before the Idle mode was entered For a request which was selected for CPU interrupt service the associated interrupt ser vice routine is entered if the priority level of the requesting source is higher than the cur rent CPU priority and the interrupt system is globally enabled After the RETI Return from Interrupt instruction of the interrupt service routine is executed the CPU continues nor mal program execution with the instruction following the IDLE instruction Otherwise if the interrupt request can not be serviced because of a too low priority or a globaily disabled interrupt system the CPU immediately resumes normal program execution with the in struction following the IDLE instruction For a request which was programmed for PEC service a PEC data transfer is performed if the priority level of this request is higher than the current CPU priority and the interrupt system is globally enabled After the PEC data transfer has been completed the CPU re turns into Idle mode Otherwise if the PEC request can not be serviced because of a too low priority or a globally disabled interrupt system the CPU does not return to Idle mode but restarts normal program execution with the instruction following th
298. rmed in the control register of the peripheral device associated with the respective port pin The peripheral must be programmed to a specific operating mode to allow generation of an interrupt by the external signal The priority of the inter rupt request is determined by the interrupt control register of the respective peripheral interrupt source and the interrupt vector of this source will be used in case an interrupt is acknowledged Siemens Aktiengesellschaft 7 24 Interrupt and Trap Functions For each of these pins either a positive a negative or both a positive and a negative external transition can be selected to cause an interrupt or PEC service request The edge selection is performed in the control register of the peripheral device associated with the respective port pin The peripheral must be programmed to a specific operating mode to allow generation of an interrupt by the external signal The priority of the interrupt request is determined by the interrupt control register of the respective peripheral interrupt source and the interrupt vector of this source will be used in case an interrupt is acknowledged In order to use any of the pins listed in table 7 5 as external interrupt inputs its direction control bit DPx y in the corresponding port direction control register DPx must be 0 When port pins CCxIO P2 x x 2 0 through 15 are to be used as external interrupt input pins bit field CCMODx in the control register
299. ro result from the ALU See subsection 5 3 2 1 for details PSW 4 This bit supports table search operation by signifying the end of a table See subsection 5 3 2 1 for details MULIP PSW 5 This bit specifies that a muitiply divide operation was interrupted before completion See subsection 5 3 2 1 for details MULIP 0 No multiply divide operation in progress MULIP 1 Multiply divide operation in progress USRO o PSW 6 This bit is provided as the user s general purpose flag PSW 11 This bit globally enables or disables acceptance of interrupts IEN 0 CPU Interrupts disabled IEN 1 CPU Interrupts enabled This field represents the current interrupt level being serviced by the CPU Upon entry into an interrupt routine the four bits of the priority level of the acknowledged interrupt are copied into this field By modifying this field the priority level of the current CPU task can be programmed See Subsection 5 3 2 2 for details Siemens Aktiengesellschaft 5 18 Central Processing Unit CPU 5 3 2 1 ALU Status N C V Z E MULIP The condition flags of the PSW N C V Z E indicate the ALU status due to the last recently performed ALU operation They are set by most of the instructions due to specific rules which depend on the ALU or data movement operation performed by an instruction After execution of an instruction which explicitly updates the PSW register the condition flags can not be interpreted as describ
300. rol Applications User s Manual 06 90 08 97 Note The User s Manual describes the SAB 80C166 up to the AB step The Addendum to the User s Manual describes the improvements and features implemented in the SAB 80C166 from the BA step There is no explicit notice which parts of the User s Manual are to be replaced by the addendum Please be aware that reading the addendum is essential for the correct programming of the SAB 80C166 devices available today Contents Page 1 Introduction sooo eligi aede raa FRAME RES 1 1 1 1 The SAB 80C166 Family of Microcontrollers 1 1 1 2 Features of the SAB 80C166 and the SAB 83C166 1 2 2 Architectural Overview 0 0 00 cece cence 2 1 2 1 Basic CPU concepts and optimizations 2 1 2 1 1 High Instruction Bandwidth Fast Execution llle 2 1 2 1 2 High Function 8 bit and 16 bit Arithmetic and Logic Unit 2 2 2 1 3 Extended Bit Processing and Peripheral Control 2 2 2 1 4 High Performance Branch Call and Loop Processing 2 2 2 1 5 Consistent and Optimized Instruction Formats 2 3 2 1 6 Programmable Multiple Priority Interrupt Structure 2 4 2 2 Functional Block sura ne Ev eric e RUNI ROS ACERO RR fe 2 4 2 2 1 TIG BID PU tes race cee ee E ERR EON AINSI NUS EIER 2 4 2 2 1 1 Instruction Decoding ies dex ques V ope BTA CRI RERO SINCE YOR 2 4 2 2 1 2 Arit
301. rol registers TOIC and T1IC Refer to chapter 7 for more details on the interrupt control registers TOIC FF9Ch CEh Reset Value 0000h Lp T11C FF9Eh CFhReset Value 0000h Lp cm Figure 8 1 4 CAPCOM Timer TO and T1 Interrupt Control Registers TOIC and T1IC 8 1 1 5 Block Diagram The following block diagrams illustrate the selection of the available functions for timer TO and timer T1 Figure 8 1 5 shows a block diagram of timer TO while figure 8 1 6 shows a block diagram of timer T1 Semiconductor Group 8 9 SIEMENS Peripherals Reload Reg TORE System C Interrupt PT2 Timer T6 APCOM Timer Request Figure 8 1 5 CAPCOM Timer To Block Diagram Figure 8 1 6 CAPCOM Timer T1 Block Diagram 8 1 2 Capture Compare Registers The sixteen 16 bit capture compare registers CCO through CC15 are used as data registers for capture or compare operations with respect to timer TO and T1 The capture compare registers are not bit addressable Each of the registers CCO through CC15 may be individually programmed for capture or one of 4 different compare modes and may be allocated individually to one of the timers TO or T1 A special combination of compare modes additionally allows the implementation of a double register compare mode When capture or compare operation is disabled for one of the registers it may be used for general purpose variable storage Semiconductor Group 8 10 SIEMENS Peripherals The functio
302. rrupt service routines of different priority levels Note that an interrupt source which is programmed to priority level O will never be serviced by the CPU because its priority level can never be higher than the CPU priority GLVL Interrupt Group Priority Field xxIC 1 0 These two bits are interpreted as the relative priority of an interrupt service request within a group of simultaneous requests from different sources on the same priority level For Sources which are programmed for PEC service in their ILVL fields the 2 bits of GLVL re present the 2 LSBs of the associated PEC channel number See also figure 7 2 The group priority field is particularly relevant for resolving simultaneous interrupt requests from se verai sources on the same priority level Up to 4 sources can be programmed tothe same priority level They are prioritized according to their group priority where 3 is highest Siemens Aktiengesellschaft 7 7 interrupt and Trap Functions group priority This also means that simultaneous requests for PEC service are prioritized according to their PEC channel number the PEC channel with the highest number has the highest priority Note All interrupt sources that are enabled and programmed to the same priority level must always be programmed to different group priorities Otherwise an incorrect interrupt vector will be generated Figure 7 3 exemplifies the possible configurations which can be programmed in the inter r
303. rt 1 Ext Memory INSTR DATA A0 not used This external bus configuration mode can also be selected if the word organized external memory is implemented by two separate 8 bit wide memories These two memories can be accessed both wordwise coupled together as one word wide memory and individual ly as two independent byte memories For the case where the two byte wide memories are to be accessed only wordwise the addressing scheme is the same as if only one 16 bit wide memorywas used For the case where the two memories are also to be accessed as independently suitable byte wide memories the External Bus Controller EBC must be enabled to use the function of the Byte High Enable pin as described in the following Firstly the Byte Disable bit BYTDIS in the SYSCON register must contain a O this is the default after system reset and secondly a 16 bit Data Bus mode must have been configured if these presuppositions are fulfilled the Byte High Enable BHE function which is an alternate active low output function of Port 3 Pin 12 P3 12 becomes en abled and will be implicitly used by the External Bus Controller EBC whenever an ex ternal memory access is performed Table 9 2 shows which BHE output is generated by the EBC dependent on the least significant address bit AQ and the type of access desired for the two coupled extemal byte memories Siemens Aktiengesellschaft 9 6 External Bus Interface Note that the E
304. rt structure This ensures that the SAB 80C166 and external devices will not try to drive the same pin to different levels Pin ALE is floating to low through a weak internal pulldown and pin RD is floating to high The BTYP Bus Type field of the SYSCON register is initialized to the bus configuration that is determined by the state of pins EBCO and EBC1 External Bus Configuration at the end of the internal system reset The ROM enable bit ROMEN will be set to 1 if single chip mode has been selected EBC1 0 00b otherwise it is set to 0 The other bits of the SYSCON register are forced to zero This default initialization of the SYSCON register has been selected such that external memories are accessed with the slowest possible configuration for the respective bus type The Ready function is disabled When the internal reset has completed the configuration of Ports 0 1 4 and of the BHE signal High Byte Enable aiternate function of P3 12 depends on the bus type which was selected during reset via the EBCO and EBC1 pins All other pins remain in the high impedance state until they are changed by software or peripheral operation When single chip mode was selected Ports 0 1 and 4 andP3 12 BHE also remain in the high impedance state until modified by software or through bus type reconfiguration in register SYSCON When any of the external bus modes was selected during reset Port 0 and or Port 1 will operate in the selected b
305. rupt processing Siemens Aktiengesellschaft 7 6 Interrupt and Trap Functions For interrupt requests which are selected for PEC service by the method described above the LSB of ILVL represents the MSB of the associated PEC channel number In other words by programming a source on priority level 15 ILVL 2 11115 PEC channels 7 through 4 can be selected By programming a source on priority level 14 ILVL 1110b PEC channeis 3 through 0 can be selected The actual PEC channel numberis then deter mined by the Group Priority field GLVL which is described in the following paragraph Figure 7 2 shows the mapping of the ILVL and GLVL fields and their interpretation during a round of prioritization Figure 7 2 Mapping of ILVL and GLVL Fields for the Interrupt Control Registers Interrupt Control Register ARRAS PE hannel Prioritization Priority Level During the prioritization process the ILVL fields of all interrupt requesting sources are compared to the current CPU priority level which is contained in the ILVL field of the PSW An interrupt request of higher priority than the current CPU priority can interrupt the executing routine Upon entry into an interrupt service routine the priority level of the source that won the arbitration is copied into the ILVL field of the PSW after pushing the old PSW contents on the stack The interrupt system of the SAB 80C166 allows nesting of up to 15 inte
306. rupt request flag T5IR in register T5IC will be set This will cause an interrupt to the timer T5 interrupt vector T5INT or will trigger a PEC transfer if the interrupt enable bit T5IE in register T5IC is set Figure 8 2 27 shows the organization of interrupt control register T5IC Refer to Chapter 7 for more details on interrupts T5IC FF66h B3h Reset Value 0000h 7 6 5 4 3 2 1 0 T5IR T5IE ILVL GLVL Figure 8 2 27 GPT2 Timer T5 Interrupt Control Register T5IC 8 2 2 3 GPT2 Capture Reload Register CAPREL This 16 bit register can be used as a capture register for the auxiliary timer T5 or as a reload register for the core timer T6 or as both These functions are controlled separately by bits in the two timer control registers T5CON and T6CON In the following the use of register CAPREL in capture and reload mode is described in detail 8 2 2 3 1 Capture Mode This mode is selected by setting bit T5SC 21 in control register T5CON The source for a capture trigger is the external input pin CAPIN which is an alternate input function of port pin P3 2 Either a positive a negative or both a positive and a negative transition at this pin can be selected to trigger the capture function The active edge is controlled by bit field Cl in register T5CON according to table 8 2 11 Table 8 2 11 Register CAPREL Capture Trigger Selection Cl Contents of T5 Captured into CAPREL on 1 0 0 0 No Transition Selected Capture D
307. rvice Exceptions to this are when the CPU is executing a routine on CPU priority level 15 or 14 While the CPU is executing a routine on CPU priority level 14 only PEC data transfers through service channels 4 through 7 can be processed While the CPU is executing a routine on CPU priority level 15 no PEC data transfers can be processed When an interrupt request that has been programmed for PEC service is selected for servicing by the prioritization circuit the PEC performs one data transfer operation The data type byte or word for this transfer is determined by bit BWT in the PEC channel control register PECCy of the respective PEC channel The source and the destination of this data transfer are pointed to by source pointer SRCPy and destination pointer DSTPy Siemens Aktiengesellschaft 7 19 Interrupt and Trap Functions After completion of the transfer operation one of the 2 pointers can optionaily be incre mented and the channel s transfer counter COUNT can be decremented When the trans fer counter reaches 0 a normal CPU interrupt request is generated and the associated interrupt service routine can be used to reprogram the affected PEC channel A functional diagram of the basic PEC service procedure is shown in figure 7 9 Note All sources which are requesting PEC service should be programmed to the same PEC service channel ONLY if it is ensured that they do not generate simultaneous requests while the COUNT field of the res
308. s fied Chapter 9 0 is dedicated to a description of the external bus interface being serviced by the EBC The SAB 80C166 peripherals work nearly independent of the CPU with a separate clock generator An interchange of data and control information between the CPU and the peripherals is done via Special Function Registers SFRs Whenever peripherals non de terministically need a CPU action an on chip Interrupt Controller compares all pending peripheral service requests against each other and prioritizes one of them If the priority of the current CPU operation is less than the priority of the selected peripheral request an interrupt will occur Basically there are two types of interrupt processing One type the so called standard interrupt processing forces the CPU to save the current program status and the return address on the stack before branching to the interrupt vector jump table The second type the so called PEC interrupt processing steals just one machine cycle from the cur rent CPU activity to perform a single data transfer via the on chip Peripheral Event Con troller PEC System errors detected during program execution so called hardware traps or an external non maskable interrupt are also processed as standard interrupts with a very high priority For more information about interrupts PEC data transfers and hardware traps see chapter 7 0 Siemens Aktiengesellschaft 5 1 Central Processing Unit CPU In contrast to
309. s are permitted to the system stack A stack overflow STKOV and a stack underflow STKUN register are provided to control when the selected stack area is left These two stack boundary registers can be used not only for protection against data destruction but also to implement a circular stack with hardware supported system stack flushing and filling For further details about system stack addressing via the SP register and the use of the STKOV and STKUN registers see section 5 3 CPU Special Function Registers Siemens Aktiengesellschaft 4 9 Memory Organization 4 3 2 General Purpose Registers The SAB 80C166 s GPRs can basically be situated anywhere within the internal RAM address space addresses from OFAOOh to OFDFFh A particular Context Pointer CP register determines the base address of the currently active register bank This register bank may consist of up to 16 word GPRs RO R1 R15 and or of up to 16 byte GPRs RLO RHO RL7 RH7 The sixteen byte GPRs are mapped onto the first eight word GPRs as shown in figure 4 4 Figure 4 4 Word and Byte GPR Organization WORD Register R7 Re R5 Ra R3 Re R1 In contrast to the system stack a register bank grows from lower towards higher address locations and occupies a maximum space of 32 bytes Short 4 and 8 bit addressing modes in collaboration with the CP register support word or byte GPR accesses regard less of the current OPP register contents Additionall
310. s for the core timer In the GPT2 block the additional CAPREL register supports capture and reload operation with extended functionality and its core timer T6 may be concatenated with CAPCOM timers TO and T1 Each block has alternate input output functions and specific interrupts associated with it Figures 8 2 1 and 8 2 2 show block diagrams of GPT1 and GPT2 In the following the GPT1 and GPT2 blocks will be described separately Semiconductor Group 8 23 SIEMENS Peripherals 5 4 7 6 CCOIC FF78h BCh ILVL CC1IC FF7Ah BDh cciiR CCIE CC2IC FF7Ch BEh cc2iR CC2IE CC3IC FF7Eh BFh CC3IR CC3IE CCAIC FF80h COh CCAIR CC4IE CC5IC FF82h Cth CC5IR CCSIE CC6IC FF84h C2h CC6IR cceiE CC7IC FF86h C3h CC7IR CC7IE CC8IC FF88h C4h CC9IC FF8Ah C5h CC101C FF8Ch C6h c10IR CC10IE CC11IC FF8Eh C7h C11IR CC111E CC121C FF90h C8h C12IR CC121E CC13IC FF92h C9h c13IR CC13IE CC14IC FF94h CAh C14IR CC14IE CC15IC FF96h CBh C15IR CC15IE Reset Value for all of the above registers 0000h Figure 8 1 18 CAPCOM Registers Interrupt Control Registers CColC through CC151C Semiconductor Group 8 24 SIEMENS Peripherals Auxiliary Timer T2 Interrupt External Requests a Mode Interrupt Capture 4 f Reload Core Timer T3 an Inputs Input Output Control Control External External Output Up Down Control Input Auxiliary Timer T4 Figure
311. s internal reset will also pull the RSTOUT pin low see chapter 11 When the software has been designed to service the Watchdog Timer before it overflows the Watchdog Timer times out if the program does not progress properly The Watchdog Timer will also time out if a software error was due to hardware related failures This prevents the controller from malfunctioning for longer than a user specified time The Watchdog Timer is a 16 bit up counter which can be clocked with either the oscillator frequency fosc divided by 4 or with fosc 256 The upper 8 bits of the Watchdog Timer can be preset to a user programmable value in order to vary the watchdog time Figure 8 5 1 shows a block diagram of the Watchdog Timer while figure 8 5 2 shows the SFRs and the reset indication pin RSTOUT which are associated with the Watchdog Timer WDT Low Byte WDT High Byte N WDT Control WDTREL Figure 8 5 1 Watchdog Timer Block Diagram Reset Indication Pin Data Registers Control Registers g WDT Watchdog Timer Register read only RSTOUT WDTCON Watchdog Timer Control Register Figure 8 5 2 SFRs and Reset Indication Pin Associated with the Watchdog Timer Semiconductor Group 8 78 SIEMENS Peripherals Watchdog Operation The current count value of the Watchdog Timer is contained in the Watchdog Timer Register WDT which is a non bit addressable READ ONLY register The operation of the Watchdog Timer is controlled by the bit addressab
312. s which are passed to the subroutine In addition two instructions have been implemented to allow one parameter to be passed on the system stack without additional software overhead The PCALL push and call instruction first pushes the reg operand and the IP contents on the system stack and then passes control to the subroutine specified by the caddr operand When exiting from the subroutine the RETP return and pop instruction first pops the IP and then the reg operand from the system stack and returns to the calling program 13 6 2 Cross Segment Subroutine Calls Calls to subroutines in different segments require use of the CALLS call inter segment subroutine instruction This instruction preserves both the CSP code segment pointer and IP on the system stack Siemens Aktiengesellschaft 13 7 System Programming Upon return from the subroutine a RETS return from inter segment subroutine instruc tion must be used to restore both the CSP and IP This ensures that the next instruction after the CALLS instruction is fetched from the correct segment It is possible to use CALLS within the same segment but two words of the stack are still used to store both the IP and CSP i 13 6 3 Providing Local Registers for Subroutines For subroutines which require local storage the following methods are provided Alternate Bank of Registers Upon entry to a subroutine it is possible to specify a new set of local registers by e
313. sabled in the time interval until the EINIT end of initialization instruction has been executed Thus the chip s start up procedure is always monitored When the software has been designed to service the Watchdog Timer before it overflows the Watchdog Timer times out if the program does not progress properly due to hardware or software related failures When the Watchdog Timer overflows it generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to reset The Watchdog Timer of the SAB 80C166 is a 16 bit timer which can either be clocked with fosc 4 or fosc 256 The high byte of the Watchdog Timer register can be set to a prespecified reload value in order to allow further variation of the monimored time interval Each time it is serviced by the application software the high byte of the Watchdog Timer is reloaded Thus time intervals between 25 us and 420 ms can be monitored fosc 40 MHz The default Watchdog Timer interval after reset is 6 55 ms 3 10 Parallel Ports The SAB 80C166 provides 76 I O lines which are organized into four 16 bit I O ports Port 0 through 3 one 2 bit I O port Port 4 and one 10 bit input port Port 5 All port lines are bit addressable and all lines of Port 0 through 4 are individually bit wise programmable as inputs or outputs via direction registers The I O ports are true bidirectional ports which are switched Semiconductor Group 3 8 SIEMENS Syste
314. scillator frequency When a 40 MHz oscillator is used the internal system clock is 20 MHz and 1 state lasts for 50 ns The clock which is gated to the peripherals is independent from the CPU clock During Idle mode the CPU clock is stopped while the peripherals continue their operation Peripheral SFRs may be accessed by the CPU on ceper state When an SFR is written to by software in the same state where it is also to be modified by the peripheral the software write operation has priority Further details on peripheral timing are included in the specific sections about each peripheral Semiconductor Group 8 1 SIEMENS Peripherals Programming Hints 1 All SFRs reside in data page 3 of the memory space Whenever SFRs are to be accessed through indirect or direct addressing with 16 bit mem addresses it must be guaranteed that data page 3 is selected by one of the data page pointer registers DPPO through DPP3 This is not required for accessing SFRs via short 8 bit reg addressing or via the Peripheral Event Controller PEC because in these cases the data page pointers are not used Y Byte write operations to word wide SFRs via indirect or direct 16 bit mem addressing or byte transfers via the PEC force zeros in the non addressed byte Byte write operations via short 8 bit reg addressing can only access the low byte of an SFR and force zeros in the high byte It is therefore recommended to use the bit field instructions BFLDL a
315. se a 1 is never shifted out of the MSB during the normalization of an operand For Boolean bit operations with only one operand the C flag is always cleared For Boolean bit operations with two operands the C flag represents the logical ANDing of the two specified bits N Flag For most of the ALU operations the N flag is set to 1 if the most significant bit of the result contains a 1 otherwise it is cleared In the case of integer operations the N flag can be interpreted as the sign bit of the result negative N 7 1 positive N 2 0 Negative numbers are always represented as the 2 s complementofthe corres ponding positive number The range of signed numbers extends from 8000h to 7FFFh for the word data type or from 80h to 7Fh for the byte data type Siemens Aktiengesellschaft 5 20 Central Processing Unit CPU For Boolean bit operations with oniy one operand the N flag represents the previous state of the specified bit For Boolean bit operations with two operands the N flag represents the logical XORing of the two specified bits MULIP Flag The MULIP flag will be set to 1 by hardware upon the entrance into an interrupt service routine when a multiply or divide ALU operation was interrupted before completion Depending on the state of the MULIP bit the hardware decides whether a multiplication or division must be continued or not at the end of an interrupt service The MULIP bit is overwritten wit
316. sed for testing purposes to allow a software trigger of an alternate input function by writing to the port output latch On most of the port lines the user software is responsible for setting the proper direction when using an alternate input or output function of a pin This is done by setting or clearing the direction control bit DPx y of the pin before enabling the alternate function There are port lines however where the direction of the port line is switched automatically For instance in the multiplexed external bus modes of Port 0 the direction must be switched several times for an instruction fetch in order to output the addresses and to input the data Obviously this can not be done through instructions In these cases the direction of the port line is switched automatically by hardware if the alternate function of such a pin is enabled There is one basic structure for all port lines with only an alternate input function Port lines with only an alternate output function however have different structures due to the way the direction of the pin is switched and depending on whether the pin is accessible by the user software or not in the alternate function mode The following sections describe in detail each of the ports and its alternate input and output functions 10 1 1 Port 0 and Port 1 Port 0 and Port 1 are two 16 bit I O ports They are bit addressable and each line can be programmed individually for input or output When
317. selection field ADCH in register ADCON This will take 1 575 us 40 MHz oscillator frequency The sampled level will then be held internally for the rest of the conversion which will require another 8 175 us 40 MHz When the conversion of this channel is complete the 10 bit result together with the number of the converted channel is transferred into the result register ADDAT and the interrupt request flag ADCIR will be set If a previous conversion result was not read out of register ADDAT by the time a new conversion is complete then the A D overrun error interrupt request flag ADEIR will also be set The previous result in register ADDAT is lost because it is overwritten by the new value If bit ADST is reset and then set again while a conversion is in progress this conversion will be aborted and the converter will start again When setting bit ADST a different conversion mode and channel number may be specified While a conversion is in progress modifications to the mode selection field ADM will not become effective until the next conversion Modifications to the channel selection field ADCH will not become effective until the next conversion in the single channel conversion modes or the next conversion round in the auto scan modes 8 3 1 1 Single Channel Conversion Mode This mode is selected by programming the mode selection field ADM in register ADCON to O0b After starting the converter through bit ADST the channel specified in bi
318. seven of the ALU result to correctly set the condition flags Multiple precision arithmetic is provided through a CARRY IN signal to the ALU from previously calculated portions of the desired operation Booth multiplication and division are supported by an extended ALU and a bit shifter placed on two coupled 16 bit registers MDL and MDH All targets for branch calculations are also computed in the central ALU 2 2 1 3 Barrel Shifter A 16 bit barrel shifter provides multiple bit shifts in a single cycle Rotates and arithmetic shifts are also supported 2 2 2 Peripheral Event Controller PEC and Interrupt Control Each interrupt source is prioritized every machine cycle in the interrupt control block If PEC service is selected a PEC transfer is started If CPU interrupt service is requested the current CPU priority level stored in the PSW register is tested to determine whether a higher priority interrupt is currently being serviced When an interrupt is acknowledged the current state of the machine is saved on the internal system stack and the CPU branches to the system specific vector for the peripheral The PEC contains a set of SFRs which store the count value and control bits for eight data transfer channels In addition the PEC uses a dedicated area of RAM which contains the source and destination addresses The PEC is controlled similar to any other peripheral through SFRs containing the desired configuration of each channel 2 2
319. significant bits of bit fields T2l or T4l are used to select the active transition see table 8 2 8 while the most significant bits T21 2 or T41 2 are irrelevant for the capture mode When programmed for capture mode the respective auxiliary timer T2 or T4 stops independent of its run flag T2R or T4R Table 8 2 8 GPT1 Auxiliary Timers Capture Trigger Selection x 2 4 T21 T4l Contents of T3 Captured into T2 T4 on 2 1 0 X 0 0 No Transition Selected Tx Disabled X 0 1 Positive External Transition on TxIN X 1 0 Negative External Transition on TxIN X 1 1 Positive and Negative External Transition on TxIN If a selected transition at the corresponding input pin T2IN or T4IN is detected then the contents of the core timer are loaded into the auxiliary timer register and the associated interrupt request flag T2IR for timer T2 or T4IR for timer T4 will be set Note that the direction control bits DP3 7 for T2IN and DP3 5 for T4IN must be set to 0 and that the level of the capture trigger signal should be held for at least 8 states to ensure correct edge detection Figure 8 2 17 shows a block diagram of an auxiliary timer in capture mode apture Reg Tx Interrupt Interrupt Figure 8 2 17 GPT1 Auxiliary Timer in Capture Mode Semiconductor Group 8 42 SIEMENS Peripherals 8 2 1 2 6 Interrupt Control Upon each overflow underflow or upon each capture or reload trigger of one of the auxiliary
320. single bit storage and thus it is not bit addressable Whenever a reset hardware trap or interrupt occurs or whenever a software TRAP instruction is executed and provided that internal ROM accesses are enabled program execution branches to an implicit internal ROM address independent of the current Code Segment Pointer CSP register contents expecting a jump vector being situated there For detailed information about the trap and interrupt jump vector table see section 7 1 Interrupt System Structure Siemens Aktiengesellschaft 4 6 Memory Organization 4 2 External Memory Basically the SAB 80C166 provides for up to 4 64 Kbytes of external ROM and or RAM which may be organized in either 8 or 16 bits Since a part of the first 64 Kbytes address space is already occupied by the on chip memory areas only 62 5 Kbytes 54 5 Kbytes for the SAB 83C166 with internal ROM enabled of external memory are really available in segment 0 The bus mode for external memory accesses is selected during reset by means of the ex ternal bus configuration pins EBC1 and EBCO According to there logic levels external me mory accesses are either enabled or disabled during reset as shown in table 4 3 The selec ted external bus configuration is saved in the BTYP bit field in the SYSCON register In case of external memory accesses being disabled during reset they can be enabledlater by simply modifying the BTYP bit field via software If external me
321. space All of these virtual stack portions are map ped onto the available physical stack area by means of an address calculation shown in the following A number of significant bits of the inverted SP contents is subtracted from the upper stack base address OFBFEh An AND mask being changed depending on the STKSZ bit field determines which of the bits are significant Physical Stack Address FBFEh C SP A 1FEh for 256 words stack size FBFEh SP A FEh for 128 words stack size FBFEh SP 7Eh for 64 words stack size FBFEh 2 SP 3Eh for 32 words stack size Siemens Aktiengesellschaft 5 31 Central Processing Unit CPU The following example demonstrates the circular stack mechanism which is also an effect of this virtual stack mapping First register R1 is pushed onto the lowest physical stack location according to the selected maximum stack size With the following instruction re gister R2 will be pushed onto the highest physical stack location although the SP is decre mented by 2 as for the previous push operation Assumed stack size is 64 Assumed SP content is x SP FC82h Physical stack address FB82h PUSHR 1 SP FC80h Physical stack address FB80h PUSHR2 SP FC7Eh Physical stack address FBFEh Upon each stack access the SP register is compared against two stack boundary registers This may cause a stack overflow or stack underflow hardware trap to occur For more details about the us
322. ssing The CPU temporarily suspends the current program execution and branches to an inter rupt service routine in order to service an interrupt requesting device The current pro gram status IP PSW in segmentation mode also CSP is saved on the internal system stack A prioritization scheme with 16 priority levels allows the user to specify the order in which multiple interrupt requests are to be handled Interrupt Processing via the Peripheral Event Controller PEC As a faster alternative to normal software oriented interrupt processing any interrupt requesting source can also be serviced by the SAB 80C166 s integrated Peripheral Event Controller Upon an interrupt request the PEC has the capability of performing a single word or byte data transfer between any two memory locations in segment 0 data pages 0 through 3 through one of eight programmable PEC Service Channels During a PEC transfer the normal program execution of the CPU is halted for 1 instruction cycle No in ternal program status information needs to be saved For PEC service the same prioriti zation scheme is applied which is used for normal interrupt processing PEC transfers share the 2 highest priority levels Trap Functions In response to the execution of certain instructions trap functions are activated A trap can also be caused externally by the Non Maskable interrupt pin NMI Several hardware trap functions are provided for handling erroneous conditions a
323. ssing Note that any explicit programmer s write request to an SFR supersedes a simultaneous modification by hard ware of the same register Note furthermore that any byte write operation to an SFR clears the non addressed com plementary byte within the specified SFR Note also that non implemented reserved SFR bits can not be modified and will always supply a read value of 0 5 3 1 SYSCON System Configuration Register This bit addressable register provides general system configuration and control functions There are four different reset values for the SYSCON register because the BTYP bit field and the ROMEN bit are initialized during reset dependent on the state of the EBCO and EBC1 input pins 5 3 1 1 Internal ROM External Memory Access Mode Selection via ROMEN BTYP A two bit field BTYP reflects the selected external bus configuration as shown in table 5 2 Table 5 2 External Bus Configuration via the BTYP bit field External Bus Configuration No external bus configured 16 18 Bit Address 8 Bit Data Multiplexed 16 18 Bit Address 16 Bit Data Multiplexed 16 18 Bit Address 16 Bit Data Non Muitiplexed 01b 10b The BTYP bit field is initialized to the state of the EBC1 and EBCO pins duringreset When an external bus is configured there BTYP getsaread only access state and thus the exter nal bus configuration selected once during reset can not be changed later In this case internal ROM accesses are globally
324. ssing modes Tiaa O or 1 State Reading a GPR or any other directly addressed operand within the internal RAM space does NOT cause additional state times However reading an indirectly addressed internal RAM operand will extend the processing time by 1 state time if the preceding instruction auto increments or auto decrements a GPR as shown in the following example I MOV R1 RO auto increment RO inex MOV R3 R2 if R2 points into the internal RAM space Tiada 1 State In this case the additional time can simply be avoided by putting another suitable instruc tion before the instruction indirectly reading the internal RAM 3 Internal SFR operand reads Tia 0 1 State or 2 States Mostly SFR read accesses do NOT require additional processing time In some rare cases however either one or two additional state times will be caused by particular SFR operations as follows Reading an SFR immediately after an instruction which writes to the internal SFR space as shown in the following example In MOV TO 1000h write to Timer 0 h ADD RZ T1 read from Timer 1 Tiag 1 State Siemens Aktiengesellschaft 5 10 Central Processing Unit CPU Reading the PSW register immediately after an instruction which implicitly updates the condition flags as shown in the following example I ADD RO 1000h implicit modification of PSW flags Ineo BAND C Z read from PSW Ty 2 States
325. st be reset by software SxFE SxCON 9 Framing Error Flag Set by hardware when a framing error occurs and SxFEN 1 Must be reset by software SxOE SxCON 10 Overrun Error Flag Set by hardware when an overrun error occurs and SxOEN 1 Must be reset by software Semiconductor Group 8 63 SIEMENS Peripherals SOCON FFBOh D8h Reset Value 0000h 14 13 12 11 10 9 8 15 fo Ed a ERR ESAE ER 7 6 5 4 3 2 1 0 aes aa ea ue 3 S1CON FFB8h DCh Reset Value 0000h 13 12 11 10 9 8 15 14 MEE RESTE E ERREUR 7 6 5 4 3 2 1 0 Ez Eod IS EL EG EL NN Figure 8 4 2 cont d Serial Channels Control Registers SOCON and S1CON Symbol Position Function SxLB SxCON 14 Loop Back Mode Enable Bit SxLB 20 Loop Back Mode Disabled SxLB 21 Loop Back Mode Enabled SxR SxCON 15 ASCx Baud Rate Generator Run Bit SxRH 20 Baud Rate Generator Disabled SxR 21 Baud Rate Generator Enabled reserved x 0 1 Serial data transmission or reception is only possible when the Baud Rate Generator Run Bit SOR or S1R for the respective channel is set to 1 The individual operating mode for each channel is determined by the mode control fields SOM and S1M in registers SOCON and S1CON as shown in table 8 4 1 These fields may not be programmed to one of the reserved combinations otherwise unpredictable results may occur A transmission will be performed by writing the data to be transmitted into the associated Transmit Bu
326. structions state times it is recommended to use the facilities provided by the simulator SIM166 or the emulator ETA166 This section is arranged in subsections of which the first one defines the subsequently used time units the second contains an overview about the minimum standard state times of the SAB 80C166 instructions and the third describes the exceptions from that standard timing Siemens Aktiengesellschaft 5 7 Central Processing Unit CPU 5 21 Time Unit Definitions The following time units are used to describe the instructions processing times fosc Oscillator frequency may be variable from 2 MHz to 40 MHz State One state time is specified by two times an oscillator period Henceforth one State is used as the basic time unit because it represents the shortest period of time which has to be considered for instruction timing evaluations 1 State 2 l fosc s for fosc 7 variable 50 ns forfosc 40 MHz ACT This ALE Address Latch Enable Cycle Time specifies the time required to perform one external memory access One ALE Cycle Time consists of either two for a non multiplexed external bus mode or three for a multiplexed external bus mode state times plus a number of state times which is determined by the number of waitstates programmed in the MCTC Memory Cycle Time Control and MTTC Memory Tristate Time Control bit fields of the SYSCON register In the case of the non muitiplexed externa
327. t field ADCH will be converted After the conversion is complete interrupt request flag ADCIR will be set and the converter will automatically stop and reset bits ADBSY and ADST Resetting bit ADST while a conversion is in progress has no effect 8 3 1 2 Single Channel Continuous Conversion This mode is selected by bit combination 01b in bit field ADM After starting the converter the specified channel will be converted repeatedly until the converter is stopped by software Interrupt request flag ADCIR is set at the end of each single conversion When bit ADST is reset by software the converter will complete the current conversion and then stop and reset bit ADBSY 8 3 1 3 Auto Scan Conversion Mode With this mode a set of different analog input channels can be converted without requiring software to change the channel number The channels are converted consecutively starting with channel ANn which is specified in bit field ADCH down to and including channel ANO The auto scan conversion mode is selected by 10b in bit field ADM After conversion of channel ANn has been completed interrupt request flag ADCIR is set and the converter starts to convert channel ANn 1 This procedure is repeated until conversion of channel ANO is complete The A D converter then stops and resets bits ADST and ADBSY Resetting bit ADST while a conversion is in progress has no effect Semiconductor Group 8 59 SIEMENS Peripherals 8 3 1 4 Auto Scan Cont
328. t has been received the contents of the receive shift register are transferred to the receive data buffer register Simultaneously the receive interrupt request flag SORIR or S1RIR is set after the 9th sample in the first stop bit time slot when one stopbit has been programmed or in the second stop bit time slot when two stop bits are programmed regardless whether valid stop bits have been received or not The receive circuit then waits for the next start bit 1 to 0 transition at its receive data input pin Note that in the 8 bit data wake up bit mode the data from receive shift register will only be transferred into SORBUF S1RBUF and the receive interrupt request flag will only be set if the 9th data bit received was a 1 Semiconductor Group 8 68 SIEMENS Peripherals When the receiver enable bit SOREN or S1REN of a serial channel in asynchronous operation is reset to 0 while a reception is in progress the current reception will be completed including generation of the receive interrupt request and in case of errors generation of the error interrupt request and setting of the error status flags which are described in the following Reception then stops for the affected channel and further start bits at the receive data input pin will be ignored In order to use pin RXDO P3 11 or RXD1 P3 9 as receive data input the corresponding direction control bit DP3 11 or DP3 9 must be set to 0 Hardware Error Detection Capabilities T
329. t is genera ted the value is decremented after each PEC data transfer Also the Interrupt Request flag of the source which generated the PEC service request is cleared If the COUNT value equals 1 at the time the PEC service request is generated the value is decremented to zero after the PEC data transfer but the Interrupt Request flag of the source which generated the request remains set This will cause another request from the associated source If the COUNT value equals 0 at the time the request is generated no PEC data transfer will be performed Instead a CPU interrupt request is generated on the same priority level 15 or 14 as the original PEC request The CPU branches to the interrupt service routine of the source that generated the request This interrupt service routine can be used to reprogram the associated PEC service channel Note This feature can be used to specifically generate CPU interrupt requests on the 2 highest priority levels level 15 or 14 For any source request on priority level 15 or 14 whose COUNT field of the associated PEC channel contains 0 a CPU interrupt request with the vector of that source is generated Note that no PEC data transfer operation can be performed while the CPU is executing a routine on CPU priority level 15 While the CPU is executing a routine on CPU priority level 14 only PEC data transfers through ser vice channels 4 through 7 can be processed If the Transfer Counter field has been
330. t operations with two operands the Z flag represents the logical NORing of the two specified bits For the prioritize ALU operation the Z flag allows a differentiation of the two cases which cause a result of zero V Flag For the addition subtraction and 2 s complementation the V flag is always set to 1 if the result overflows the maximum range of signed numbers which are repre sentable by either 16 bits for word operations 8000h to 7FFFh or by 8bits for byte operations 80h to 7Fh otherwise the V flag is cleared Note that the result of an integer addition integer subtraction or 2 s complement is not valid if the V flag signifies an arithmetic overflow For the multiplication and division the V flag is set to 1 if the result can not be repre sented in a word data type otherwise it is cleared Note that a division by zero will al ways cause an overflow In contrast to the result of a division the result of a multipli cation is valid regardless of whether the V flag is set to 1 or not Since logical ALU operations can not produce an invalid resuit the V flag is cleared by these operations Siemens Aktiengesellschaft 5 19 Central Processing Unit CPU The V flag is also used as Sticky Bit for rotate right and shift right operations With only using the C flag a rounding error caused by a shift right operation can be estima ted up to a quantity of one half of the LSB of the result In co
331. t request flag are set provided the parity check has been enabled The actual parity bit received is placed in the 9th bit of the receive data buffer register and the remaining 7 bits 9 through 15 of the receive buffer register are cleared to zero 8 4 1 2 Synchronous Operation This operating mode of the serial channels ASCO and ASC1 allows half duplex communication and is mainly provided for simple I O expansion via shift registers 8 data bits are transmitted or received synchronous to a shift clock generated by the internal baud rate generator The shift clock is only active as long as data bits are transmitted or received Synchronous operation is selected by programming the mode control field SOM or S1M of a serial channel to 000b Figure 8 4 6 shows a block diagram of a serial channel in synchronous mode Semiconductor Group 8 71 SIEMENS Peripherals Reload Register SxR Ww System E 2 Baud Rate Timer 4 Clock E EA SxM 000b Receive Int SxREN Clock SxRIR Request TXDO P3 10 SxTIR Transmit Int TXD1 P3 8 SxOEN Serial Port Control STIR Request SxLB Error Int Shift Clock SxEIR Request Nl Receive sg Receive Shift Register Transmit Buffer Reg RXDO SxTBUF P3 11 l Transmit Receive Buffer Reg SxRBUF Internal Bus Figure 8 4 6 Serial Channel Synchronous Mode Block Diagram In synchronous operation pin TXDO P3 10 is used by ASCO to output the shift clock while RXDO P3 11 either serves
332. te Rb GPR address is specified the short 4 bit GPR address is multiplied either by two or by one before it is added to the contents of the CP register as shown in figure 5 13 Thus both byte and word GPR accesses are possible in this way Figure 5 13 implicit CP Use by Short 4 Bit GPR Addressing Modes Specified by or Rb Internal RAM Control Must be situated in the internal RAM area A 1 for byte GPR accesses A 2 for word GPR accesses GPRs used as indirect address pointers are always accessed wordwise For some instructions only the first four GPRs can be used as indirect address pointers These GPRs are specified via short 2 bit GPR addresses The respective physical address calculation is identical to that for the short 4 bit GPR addresses 5 3 5 2 Implicit CP Use with Short 8 Bit Register Addresses When a short 8 bit address mnemonic reg or bitoff is used and supposed that the re spective value is within a range from FOh to FFh the four least significant bits are inter preted as short 4 bit GPR address while the four most significant bits are ignored As shown in figure 5 14 the respective physical GPR address caiculation is identical to that for the short 4 bit GPR addresses For single bit accesses on a GPR the GPR s word ad dress is calculated as just described but the position of the bit within the word is speci fied by a separate additional 4 bit value 5 3 7 SP Stack Pointer This non bit address
333. tead it is toggled When the user wants to write to the port pin at the same time a compare trigger tries to clock the output latch the write operation of the user software has priority Each time a CPU write access to the port output latch occurs the input multiplexer of the port output latch is switched to the line connected to the internal bus The port output latch will receive the value from the internal bus The hardware triggered change will be lost 10 1 3 Port 3 Each of the 16 pins of Port 3 P3 has an alternate input or output function associated with it Seven pins have an alternate input function seven pins have an alternate output function and two pins RXDO and RXD1 have an alternate input or output function depending Table 10 1 Port 3 Alternate Input Output Functions Symbol Alternate Symbol Input Output Function P3 0 TOIN Timer 0 Count Input P3 1 T6OUT O Timer 6 Toggle Latch Output P3 2 CAPIN CAPREL Register Capture Input P3 3 T3OUT O Timer 3 Toggle Latch Output P3 4 T3EUD Timer 3 External Up Down Control Input P3 5 TAIN Timer 4 Count Gate Reload Capture Input P3 6 T3IN Timer 3 Count Gate Input P3 7 T2IN Timer 2 Count Gate Reload Capture Input P3 8 TXD1 O Serial Channel 1 Data Output in Asynchronous Mode Clock Output in Synchronous Mode P3 9 RXD1 1 0 Serial Channel 1 Data Input in Asynchronous Mode Data Input Output in Synchro
334. ted by a Subtract instruction the IP value pushed represents the address of the instruction after the instruction following the Subtract instruction For recovery from stack overflow it must be ensured that there is enough excess space on the stack for twice saving the current system state PSW IP in segmented mode also CSP Otherwise a system reset should be generated See chapter 13 for more details on stack usage 7 3 2 3 Stack Underflow Trap Whenever the Stack Pointer is incremented to a value which is greater than the value in the Stack Underflow register STKUN the STKUF flag is set in the TFR register and the Stack Underflow trap is entered Again which IP value will be pushed onto the system stack depends on which operation caused the increment of the SP When an implicit in crement of the SP is made through a Pop or Return instruction the IP value pushed is the address of the following instruction When the SP is incremented by an Add instruc tion the IP value pushed represents the address of the instruction after the instruction following the Add instruction See chapter 13 for more details on stack usage Siemens Aktiengesellschaft 7 29 Interrupt and Trap Functions 7 3 2 4 Undefined Opcode Trap Whenever the opcode of an instruction currently decoded by the CPU is not the opcode of a valid instruction in the SAB 80C166 s instruction set the UNDOPC flag is set in the TFR register and the CPU enters the Undefined Opcod
335. ted or stopped through its run bit T5R Timer T5 Run Bit If T5R 0 the timer stops Setting T5R 1 will start the timer Semiconductor Group 8 48 SIEMENS Peripherals 8 2 2 2 1 Timer Mode In this mode selected in register TSCON by setting bit T5M 0 the auxiliary timer T5 operates exactly as described for the core timer T6 It has the same 8 prescaler options which are selected by bit field T5l in control register T5CON The input frequency frs to timer T5 is determined as follows f OSC frs 8 Fe 9 lt l5l gt The resulting input frequency resolution and timer period when using a 40 MHz oscillator is the same as for T6 see table 8 2 9 Figure 8 2 24 shows a block diagram of T5 in timer mode Interrupt Auxiliary Timer T5 Request Figure 8 2 24 Block Diagram of GPT2 Auxiliary Timer T5 in Timer Mode 8 2 2 2 2 Counter Mode The counter mode of timer T5 selected by T5M 1 can only be used in conjunction with the toggle bit TEOTL of the core timer T6 since timer T5 has no external input pin In this mode timer T5 is clocked by a transition of T6OTL Note that only state transitions of T6OTL which are caused by overflows underflows of T6 will trigger the counter function of T5 Modifications of T6OTL by software will NOT trigger the counter function of T5 Either a positive a negative or both a positive and a negative transition of T6OTL can be selected to cause an increment or decrement of T5 The options are selected
336. ter This non bit addressable register is used to select the currentregister context This means that the CP register value determines the address of the first GPR within a register bank of up to 16 wordwide and or bytewide GPRs Figure 5 11 Context Pointer Register CP FE10h 08h Reset Value FCOOh 15 14 13 12 11 10 9 8 7 6 5 4 2 1 0 3 cp continuation Symboi Position Function Bit tied to 0 by hardware since only even CP contents are allowed CP 10 1 Modifiable portion of the CP register CP 15 11 Bits tied to 1 by hardware This allows possible contents from FAQ0h to FDFEh Note however that valid GPR addresses must be situated within the internal RAM space Since the least significant bit of the CP register is tied to 0 and bit 10 is tiedtothe nega ted state of bit 9 and bits 11 to 15 are tied to 1 by hardware the CP register can only point to even word addresses from OFAQOh to ODFFEh Note however that it is the user s responsibility that the physical GPR address specified via the CP register in addition with the short GPR address must always be an internal RAM location If this condition is not met unexpected results may occur After reset the CP register is initialized to FCOOh Figure 5 12 shows how the CP register is used to select a register bank The CP register can be updated via any instruction which is capable of modifying an SFR Due to
337. ter 0000h for Watchdog Timer overflow 0002h Semiconductor Group B 10 SIEMENS SAB 80C166 Registers Name Physical 8 Bit Description Reset Address Address Value SOCON FFBOh D8h Serial Channel 0 Control Register 0000h FFB2h D9h reserved FFB4h DAh reserved FFB6h DBh reserved S1CON FFB8h DCh Serial Channel 1 Control Register 0000h FFBAh DDh reserved FFBCh DEh reserved FFBEh DFh reserved P2 FFCOh EOh Port 2 Register 0000h DP2 FFC2h E1h Port 2 Direction Control Register 0000h P3 FFC4h E2h Port 3 Register 0000h DP3 FFC6h E3h Port 3 Direction Control Register 0000h FFC8h E4h reserved e e e e e e FFDEh EFh reserved Semiconductor Group B 11 SIEMENS SAB 80C166 Registers B 3 Special Function Registers Alphabetical Order The following table lists all SFRs which are implemented in the SAB 80C166 in alphabetical order Bit addressable SFRs are marked with the letter b in column Name Name Physical 8 Bit Description Reset Address Address Value ADCIC b FF98h CCh A D Converter End of Conversion 0000h Interrupt Control Register ADCON b FFAOh DOh A D Converter Control Register 0000h ADDAT FEAOh 50h A D Converter Result Register 0000h ADEIC b FF9Ah CDh A D Converter Overrun Error Interrupt 0000h Control Register CAPREL FE4Ah 25h GPT2 Capture Reload Register 0000h CCO FE80h 40h
338. terface Figure 9 10 Memory Cycle Time Wait States Wait States Segment Address ALE i d m WR I The SAB 80C166 allows the user to program Memory Cycle Time wait states in increments of half a machine cycle within a range from 0 to 15 default after reset The Memory Cycle Time wait states can be configured via software by modifying the MCTC field of the SYSCON register as shown in table 9 3 One Memory Cycle Time Wait State requires half a machine cycle 50 ns at fosc 40 MHz Siemens Aktiengesellschaft 9 14 External Bus Interface Table 9 3 MCTC Encoding of the Memory Cycle Time Wait States MCTC Number of Additional Delay Bit 3 Bit2 sti Bit 0 Wait States at fosc 40 MHz ns Bp 5 p o 9 o9 18 7 750 14 700 8 rs e om n mu 350 o ojojo jo oI lo a 200 C e By means of the Memory Cycle Time Wait States the Memory Cycle Time can be varied as follows Multiplexed Bus Modes 150 ns 900 ns at fosc 40 MHz Non Multiplexed Bus Mode 100 ns 850 ns at fosc 40 MHz These programmable Memory Cycle Time wait states can be specified for all of the external bus configuration modes Siemens Aktiengesellschaft 9 15 External Bus Interface 9 7 2 Programmable Memory Tri State Time The SAB 80C166 allows the user to adjust the time between two subsequent memory accesses to account for the Tri State Time of the external memory being used The Tri State time is the ti
339. ternal bus accesses These three signals will be implemented as second alternate functions at pins P2 15 HOLD P2 14 HLDA and P2 13 BREQ A new control bit HLDEN Hold Function Enable will be implemented in the PSW see Figure 11 1 After reset this bit is O If this bit is once set to 1 the 3 pins of port 2 can no longer be used for general purpose l O or for the CAPCOM unit If bit HLDEN is cleared after once being set this will disable the bus arbitration function of these pins but will not turn them back to I O or CAPCOM mode Clearing of HLDEN is used to disable the HOLD input while executing some critical real time routines which are not allowed to be interrupted or delayed through external HOLD requests If an external HOLD request is acknowledged the SAB 80C166 will bring the external address data and control bus to the following states Port 0 Tri State if an external bus is enable Port 1 Tri State if a non multiplexed bus mode is selected Port 4 Tri State if an external bus and segmentation are enabled ALE Float to 0 through high impedance pull down RD Float to 1 through high impedance pull down WR Tri State even when used as general purpose O pin BHE Tri State if BHE function enabled READY Nochange since this is an input only signal Figures 11 2 and 11 3 illustrate the timings for entry into and exit from HOLD mode timings shown for a non multiplexed bus mode The timing for b
340. terrupt only mode similar to compare mode 0 but only one interrupt request per timer period will be generated Compare mode 2 is selected for register CCx by setting bit field CCMODx of the corresponding mode control register to 110b When a match is detected in compare mode 2 for the first time within a timer period interrupt request flag CCxIR is set to 1 The corresponding Port 2 pin P2 x is not affected and can be used as a normal I O pin However after the first match has been detected in this mode all further compare events within the same timer period are disabled for compare register CCx until the allocated timer overflows This means that after the first match even when the compare register is reloaded with a value higher than the current timer value no compare event will occur until the next timer period Figure 8 1 13 shows a functional diagram of a compare register configured for compare mode 2 Note that the port latch and pin remain unaffected in compare mode 2 Figure 8 1 14 shows a simple timing example for this compare mode In this example the compare value in register CCx is modified from cv1 to cv2 after compare event 1 However compare event 2 will not occur until the next period of timer Ty Interrupt Compare Reg CCx Request CAPCOM Timer Ty dune Figure 8 1 13 Compare Mode 2 and 3 Block Diagram Semiconductor Group 8 18 SIEMENS Peripherals Contents of Ty FFFFh Compare Value cv2 Compare Va
341. the SP into CP see example in figure 13 1 Each local register is then accessed as if it was a normal register Note that the system stack is growing downwards while the register bank is growing upwards Upon exit from the subroutine one first restores the old CP by popping it from the stack and then simply adds the number of local registers used to the SP to restore the allocated local space back to the system stack 13 7 Table Searching A number of features have been included to decrease the execution time required to search tables First branch delays are eliminated after the first iteration of the loop Second in non sequentially searched tables the enhanced performance of the ALU allows more complicated hash algorithms to be processed to obtain better tabie distri bution For sequentially searched tables the auto increment indirect addressing mode and the E end of table flag stored in the PSW decrease the number of overhead in structions executed in the loop Below two examples illustrate searching ordered tables and non ordered tables respectively MOV RO BASE Move table base into RO LOOP CMP R1 RO Compare target to table entry JMPA cc_SGT LOOP Test whether target has not been found Note The last entry in the table must be greater than the largest possible target MOV RO 4BASE Move table base into RO LOOP CMP Ri1 RO Compare target to table entry JMPA CC NET LOOP Test whether target is not fou
342. the READY line This new feature has the following advantages for the user 1 Onecan connect memory operating with or without wait states and peripherals operating with READY to the external bus of the SAB 80C166 and use wait states together with the READY function If the memory is accessed the chip select logic is used to bring the READY line to a LOW state The CPU will insert the programmed number of wait states if any into the memory cycle then check the READY line find that the external device is ready READY 0 and terminate the memory cycle If the peripheral device is accessed first the programmed wait states are inserted and then the READY line is checked For READY 0 the bus cycle will be terminated For READY 1 the CPU will hold the bus cycle until READY goes to 0 and then terminate the cycle Since normally peripherals operating with a READY function are much slower than memories even memories requiring wait states this will have no impact on the access time to the peripheral 2 When using the asynchronous READY function the first time the READY line is checked is near the falling edge of the ALE signal Thus in order to guarantee a correct bus cycle the READY line has to present a valid logic level at this time point Some peripherals however hold the READY line at a low state when they are not accessed and require some time after being addressed by the CPU to signal their not ready state i e br
343. tice which parts of the User s Manual are to be replaced by the addendum Please be aware that reading the addendum is essential for the correct programming of the SAB 80C166 devices available today SIEMENS SAB 80C166 83C166 Table of Contents Page 1 GPT2 Timer T5 Clear Function 2 ia orem yee cree aia Reo o One ec wa D 3 2 Serial T ort Baud ales 3a Eod d tede S iet Rt t Rte Calend UR Sie Rates D 3 3 Implementation of a 16 18 Bit Address 8 Bit Data Non Multiplexed Bus Mode 1v rare que dos ur a reg E og woe er E HRS D 4 4 Mapping the internal ROM address space 000 cece eee eee ees D 4 5 Selection of Bus Modes and ROM Mapping 2000e eee eee eee D 5 6 Change of the READY Function 0 00 2 cece eee D 8 7 Implementation of an additional Bus Configuration Register D 9 8 Switching between the Bus Modes 0 00 cece eee eee eee D 11 9 Implementation of ALE Lengthening 20 00 cee eee eee D 11 10 Automatic Continuation of Reset Sequence 0 00 ee eee eee D 12 11 Implementation of HOLD HLDA BREQ Bus Arbitration D 12 Semiconductor Group D 2 SIEMENS SAB 80C166 83C166 1 GPT2 Timer T5 Clear Function In the BA Step of the SAB 80C166 the capture function and the clear function of timer T5 are no more tied together The timer T5 clear function can be selected through bit T5CLR regardless whether the capture function is
344. tination Pointers lesse 7 12 Prioritization of Interrupt and PEC Service Requests 7 14 Enabling and Disabling of Interrupt Sources sse 7 14 Priority Level SUuCture suivent ita wena ae ERA VE ES 7 14 Example for the Use of the CPU Priority lese 7 15 interrupt Procedure sci sciocvs oa ERES ENE CER ER OO Rae ee 7 17 Interrupt Procedure with Segmentation Disable 7 17 Interrupt Procedure with Segmentation Enabled 7 18 Context Switching for Interrupt Service Routines LL 7 19 Interrupt Processing via the Peripheral Event Controller PEC 7 19 Interrupt and PEC Response Times DT 7 21 External Interrupt 22223 xo RC ornare os bees Gale dees 7 24 Trap Functions 26 cue eee rds ee eee ea A A RUANDA dos 7 26 Software Traps Xaeseev4 pi da P d mex EAR E SA dus Du eee esa 7 26 Siemens Aktiengesellschaft 3 7 3 2 7 3 2 1 7 3 2 2 7 3 2 3 7 3 2 4 7 3 2 5 7 3 2 6 7 3 2 7 7 3 2 8 8 8 1 8 1 1 8 1 1 1 8 1 1 2 8 1 1 3 8 1 1 4 8 1 1 5 8 1 2 8 1 2 1 8 1 2 2 8 1 2 2 1 8 1 2 2 2 8 1 2 2 3 8 1 2 2 4 8 1 2 2 5 8 1 2 3 8 2 8 2 1 8 2 1 1 8 2 1 1 1 8 2 1 1 2 8 2 1 1 3 8 2 1 1 4 8 2 1 2 8 2 1 2 1 8 2 1 2 2 8 2 1 2 3 8 2 1 2 4 8 2 1 2 5 8 2 1 2 6 8 2 2 Contents Page Hardware Traps ipe de ox aree bra a dr eke eee oars 7 26 External NMI Trap xui psa uubneepPbety X Pd eu AS ee 7 29 Stack Overflow Trap
345. tion the mapping of the ROM to segment 1 can be performed see Chapter 4 Any changes of the configuration which affect the on chip ROM however can only be made until the end of initialization instruction EINIT is executed After the EINIT instruction only the external bus configuration can be changed at any time The following table illustrates the possible selections during reset during the initialization phase and after the EINIT instruction Note that directly after reset the bit BUSACT represents the inverted value of the pin BUSACT and BTYP represents the values of the pins EBC1 and EBCO Action Function Selected at BUSACT BTYP Reset During Init After Init 0 00 ROM enable ROM enable No action Segment 0 Segment 0 No ext Bus 0 01 reserved ROM enable No action Segment 1 0 10 reserved Disable ROM No action 0 11 reserved Disable ext Bus No action 1 00 8 Bit Non Mux 8 Bit Non Mux 8 Bit Non Mux No ROM 1 01 8 Bit Mux 8 Bit Mux 8 Bit Mux No ROM 1 10 16 Bit Mux 16 Bit Mux 16 Bit Mux No ROM 1 11 16 Bit Non Mux 16 Bit Non Mux 16 Bit Non Mux No ROM Semiconductor Group SIEMENS SAB 80C166 83C166 This table of functions allows the user to choose between the following options Start execution from any of the four external bus modes including the new 8 bit non multiplexed mode Start execution from the internal ROM or Flash EPROM and later program any of the four
346. tionally be directed to place classes of data in specified areas of memory n this way the Locator can help with the ordering of individual data segments in memory The Library Manager allows one to build and maintain libraries of relocatable object modules Siemens Aktiengesellschaft 14 2 Support Tools 14 2 2 C Compiler The C compiler will implement the standard C language with additional support for certain specific internal features of the SAB 80C166 It will allow for different configura tions of memory usage including single chip applications In addition the output will be assembler code with symbols line numbers and module names included for symbolic and high level language debugging This assembler output can then be translated to a relocatable object code which can then be linked and located by the tools provided with the assembler package In addition the object code can be linked together with the object modules generated by the assembler Optional optimizers can be invoked to provide either code density or execution speed optimization 14 2 3 Simulator Package A software simulator will also be provided for users who would like to develop and debug software for the SAB 80C166 before their hardware is developed This allows one to not oniy debug software but to determine the amount of time required for a piece of code to execute The simulator will provide the ability to control and monitor the execution of the s
347. tor Group C 12 SIEMENS Table C 3a Non Multiplexed Memory Read with Read Write Delay Application Examples Symbol Meaning 40 MHz Clock Variable Timing Dec Address to Valid Data In tecc lt 7 n1 50 tees 2 ATCL 25 n1 2TCL ni2214 50 1 5 nl tacc 25 2TCL 2 be RD to Valid Data In be S ta n2 50 h_es 2TCL 15 n2 2TCL n22215 50 0 7 n22 fb 15 2TCL 1 far Data Float after RD fS top N3 50 fg 2TCL 15 n3 2TCL n3 gt ty 50 0 7 n3 2 fy 15 2TCL 1 t ALE Cycle Time t 100 n 50 t ATCL n 2TCL Note If the external memory is only used for code storage fj may be longer than specified here In this case n max n1 n2 because n3 0 ALE Cycle Time Memory Cycle Time 4TCL 100 ns at 40 MHz l4 47 bg See Device Specification Section D 5 5 Table C 3b Non Multiplexed Memory Read with Read With Delay Quick Table lacc n1 be n2 lgt n3 lt 75 0 lt 35 0 lt 35 0 gt 75 lt 125 1 5 lt 85 1 2 35 lt 85 1 gt 125 lt 175 2 2 85 lt 135 2 gt 175 lt 225 3 2 135 lt 185 3 gt 225 lt 275 4 2 185 lt 235 4 gt 275 lt 325 5 gt 235 lt 285 5 Semiconductor Group C 13 SIEMENS Table C 4a Non Multiplexed Memory Write with Read Write Delay Application Examples Symbol Meaning 40 MHz Clock Variable Timing b
348. trap service routine Note however that data in the bottom of the stack may have been overwritten by the status information stacked upon servicing the stack overflow trap The stack overflow trap could also be used for automatic system stack flushing when the system stack is used as a Stack Cache for an external user stack In this case the STKOV register should be initialized to a value which represents the desired lowest Top of Stack address plus 12 according to the selected maximum stack size This considers the worst case that will occur when a stack overflow condition is detected just during entry into an interrupt service routine Then six additional stack word locations are required for pus hing the IP PSW and CSP registers for both the interrupt service and the hardware trap service For more details about the implementation of a stack overflow trap service rou tine see section 13 4 1 5 3 9 STKUN Stack Underflow Pointer This non bit addressable register is compared against the SP register after each data pop operation from the system stack i e for POP and RETURN instructions and after each addition to the SP register If the contents of the SP register are greater than the contents of the STKUN register a stack overflow hardware trap will occur Stack Underflow Condition SP STKUN Figure 5 17 Stack Underflow Pointer Register STKUN FE16h 0Bh Reset Value FCOOh Stkun continuation Bit tied to 0 by hard
349. trol SFRs are updated using the BFLDH and BFLDL instructions to avoid undesired intermediate modes of operation which can occur when AND OR instruction sequences are used 13 9 Floating Point Support All floating point operations are performed using software Standard multiple precision instructions are used to perform calculations on data types that exceed the size of the ALU Multiple bit rotate and logic instructions allow easy masking and extracting of portions of floating point numbers To decrease the time required to perform floating point operations two hardware features have been implemented in the core CPU The first aids in normalizing floating point num bers by indicating the position of the first set bit in a GPR One can then use this result to rotate the floating point result accordingly The second feature aids in properly rounding the result of normalized floating point numbers through the overflow V flag in the PSW This flag is set when a one is shifted out of the carry bit The overflow flag and the carry flag are then used to round the floating point result based on the desired rounding algorithm 13 10 Trap interrupt Entry and Exit Interrupt routines are entered when a requesting interrupt has a priority higher than the current CPU priority level Traps are entered regardless of the current CPU priority When either a trap or interrupt routine is entered the state of the machine is preserved on the system stack and a br
350. trol bits of the BUSCON1 register specify the configuration of the external bus for this access The ADDRSEL1 register is shown in Figure 7 2 One can see that the ADDRSEL1 register is divided into three parts Bits 0 to 2 RGSZ Range Size Selection bit field specify the address range according to the following table Range Size Selected Address Range RGSZ 000 2 KByte 001 16 KByte 010 32 KByte 011 64 KByte 100 128 KByte 101 reserved 110 reserved 111 reserved Semiconductor Group D 9 SIEMENS SAB 80C166 83C166 The next bit field bits 3 to 9 Range Start Address specifies the start address of the address range The third field of register ADDRSEL1 bits 10 to 15 is reserved for future expansion There is a fixed relationship between the range size and the range start address The range start address can only be specified in boundaries determined by the selected range size That is for a range size of 16 Kbyte the start address of this range can only be programmed to 16 Kbyte boundaries For a range size of 2 Kbyte the start address can be programmed to any 2 Kbyte address boundary If the range size is 128 Kbyte then for the SAB 80C166 the start address can only be 0 Kbyte or 128 Kbyte since the total address range is 256 Kbyte two blocks of 128 Kbyte Bits 3 to 9 the Address Start Location bit field of register ADDRSEL1 can be regarded as the most significant address bits of the selected address range Thus
351. truction The IP register is implicitly updated by the CPU for branch instructions and after instruc tion fetch operations 5 3 4 CSP Code Segment Pointer This non bit addressable register selscts the code segment being used at run time to access instructions Currently only two bits of the CSP register are implemented while bits 2 to 15 are reserved for future use The CSP register ailows accessing the entire memory space in currently four segments of 64 Kbytes each Siemens Aktiengesellschaft 5 21 Central Processing Unit CPU Figure 5 6 Code Segment Pointer Register CSP a l Reset Value 0000 H be fetched Will be ignored in the case of segmentation being CSP 1 0 disabled Code memory addresses are generated by directly extending the 16 bit contents of the IP register by the contents of the CSP register as shown in figure 5 7 Specifies the code segment number where the current instruction is to Figure 5 7 Addressing via the Code Segment Pointer Code segment SFFFF CSP Register IP Register 15 T 0 16 16i inra Segment adaress Intra 16i inra Segment adaress Address pH pH 17 16 71 18 Bit ee Address 00000 18 Bit Address Space Siemens Aktiengesellschaft 5 22 Central Processing Unit CPU In the case of the segmented memory mode bit 1 and bit 0 of the CSP register are out put on the segment address pins A17 and A16 of Port 4 for all external code acc
352. truction The old MDC contents must be popped from the stack before the RETI instruction is executed Siemens Aktiengesellschaft 13 3 System Programming 13 3 BCD Calculations No direct support for BCD calculations is provided in the SAB 80C166 BCD calculations are performed by converting between BCD data types and binary data types performing the desired calculations using standard data types Due to the enhanced performance of division instructions one can quickly convert from binary to BCD through divisions by 10 of binary data types Conversion from BCD to binary is enhanced by multiple bit shift in structions Thus similar performance is achieved in comparison to instructions which would support BCD data types while no additional hardware is required 13 4 Stack Operations Two types of stacks are provided in the SAB 80C166 The first type is used implicitly by the system and is contained in the internal RAM The second type provides stack access to the user in either the internal or external memory Both stack types grow from high memory addresses to low memory addresses and are described in the following subsections 13 4 1 Internal System Stack A system stack is provided to store return vectors segment pointers and processor sta tus for procedures and interrupt routines A system register SP points to the top of the stack This pointer is decremented when data is pushed onto the stack and incremented when data is popped
353. uction Return from Interrupt the information that was pushed on the stack is popped in reverse order to restore the previous status Figure 7 8 shows how the system stack is affected by an interrupt that is acknowledged when segmentation is enabled Figure 7 8 Interrupt Procedure with Segmentation Enabled High High Addresses Addresses sP gt P WMA PSW State of interrupted NEW SP gt CSP task saved on Low l Low Addresses Addresses a System Stack before b System Stack after interrupt Entry Interrupt Entry Siemens Aktiengesellschaft 7 18 interrupt and Trap Functions 7 2 4 3 Context Switching for Interrupt Service Routines Context switching in conjunction with processing an interrupt service routine allows establishing a new context within the interrupt service routine Thus a completely new set of General Purpose Registers GPRs can be provided for the interrupt service routine without the need of explicitly saving and restoring registers Context switching can be performed by executing the Switch Context instruction SCXT within the interrupt service routine before any GPR is accessed For example the instruc tion SCXT CP New Bank is used to push the previous value of the Context Pointer CP on the system stack and set the CP to the value New Bank which is specified as an immediate operand in the SCXT instruction Note that GPRs in the new register bank should not be accessed by the instruction immediat
354. uires 100 ns at 20 MHz CPU clock For example shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted All multiple cycle instructions have been optimized so that they can be executed very fast as well A 32 bit 16 bit division in 1us a 16 bit 16 bit multiplication in 0 5 us and branches in 200 ns Another pipeline optimization the so called Jump Cache allows reducing the execution time of repeatedly performed jumps in a loop from 200 ns to100 ns Mul Div HW Bit Mask Gen General Nu Purpose 4 Stage 16 bit S PSW SYSCON Data Page Ptr Code Seg Ptr Figure 3 2 CPU Block Diagram Semiconductor Group 3 3 SIEMENS System Description The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are physically allocated within the on chip RAM area A Context Pointer CP register determines the base address of the active register bank to be accessed by the CPU at the time The number of register banks is only restricted by the available internal RAM space For easy parameter passing register banks can also be organized overlappingly A system stack of up to 512 bytes is provided as a storage for temporary data The system stack is allocated in the on chip RAM area and it is accessed by the CPU via the stack pointer SP register Two separate SFRs STKOV and STKUN are implicitly compared against the stack pointer value upo
355. uitiplexed on the word wide external bus Therefore an external word wide address latch is required The least significant address bit AO is normally not significant when accessing word organized memories An Address Latch Enable ALE signal is generated by the on chip External Bus Controller EBC to signify a valid ad dress being available on Port 0 As long as memory segmentation is not disabled Port 4 is additionally used as an output for the two most significant bits of the required 18 bit addresses Port 1 can be used for general purpose I O functions Compared with the other external bus configuration modes the 16 18 bit Address 16 bit Data Muitiplexed Bus mode provides a middle level of performance It is faster than the 8 bit data bus mode because a memory doesn t have to be accessed twice in order to fetch a word wide value This advantage however is not totally utilized since addresses and data are time multiplexed on the external bus This time multiplexing reduces the overall possible bandwidth of the bus Siemens Aktiengesellschaft 9 5 External Bus Interface If the 16 18 bit Address 16 bit Data Mutiplexed Bus mode has been selected once during reset internal ROM accesses stay globally disabled and no other external bus configuration can be selected later Figure 9 3 16 18 Bit Address 16 Bit Data Multiplexed Bus Word Wide Memories Segment Addr Porta WR RD ALE SAB 80C166 Poro ADDR OE amp WA 8 Bit Po
356. unctional block diagram of a compare register in compare mode 3 is included in figure 8 1 13 of the previous section Note that in compare mode 3 the port latch is set by the compare event and reset by the next timer overflow Semiconductor Group 8 19 SIEMENS Peripherals Contents of Ty FFFFh Compare Value cv2 Compare Value cv1 Reload Value lt TyREL gt Interrupt 0000h Requests m CCxIR m cour TyIR State of COxIlO gt Event 1 Event 2 t CCx cv2 CCx cv1 Figure 8 1 15 Timing Example for Compare Mode 3 8 1 2 2 5 Double Register Compare Mode In the double register compare mode two compare registers work together to control one pin This mode is selected by a special combination of modes for the two registers For the double register mode the 16 capture compare registers are regarded as two banks of 8 registers each Registers CCO through CC7 form bank 1 while registers CC8 through CC15 form bank 2 For the double register mode a bank 1 register and a bank 2 register form a register pair Both registers of the register pair operate on the pin associated with the bank 1 register pins CCOIO through CC7IO which are the alternate functions of Port 2 pins P2 0 through P2 7 Table 8 1 4 shows the relationship between the bank 1 and 2 register pairs and the affected pins for the double register mode Semiconductor Group 8 20 SIEMENS Peripherals Table 8 1
357. up 8 47 SIEMENS Peripherals 8 2 2 2 GPT2 Auxiliary Timer T5 The auxiliary timer T5 can operate in timer or counter mode These two modes are described below Unlike the core timer T6 the auxiliary timer T5 has no toggle bit and no alternate output function The operation of T5 is controlled by register T5CON which is shown in the following figure 8 2 23 T5CON FF46h A3h Reset Value 0000h 15 14 13 ET T iik T I I I I Figure 8 2 23 GPT2 Auxiliary Timer T5 Control Register T5CON Symbol Position Function T5l T5CON 2 0 Timer 5 Input Selection For Timer mode see table 8 2 9 For Counter mode see table 8 2 10 T5M T5CON 3 Timer 5 Mode Control T5M 0 Timer Mode T5M 1 Counter Mode T5R T5CON 6 Timer 5 Run Bit T5R 20 Timer Counter 5 stops T5R lt 1 Timer Counter 5 runs T5UD T5CON 7 Timer 5 Up Down Control Bit T5UD 20 Timer Counter 5 counts up T5UD 21 Timer Counter 5 counts down Cl T5CON 13 12 Register CAPREL Input Selection see table 8 2 11 T5CLR T5CON 14 Timer 5 Clear Bit T5CLR 0 Timer 5 is not cleared on a capture T5CLR 1 Timer 5 is cleared on a capture T5SC T5CON 15 Timer 5 Capture Mode Enable Bit T5SC 20 Capture into register CAPREL disabled T5SC 1 Capture into register CAPREL enabled z reserved In both timer and counter mode of operation the auxiliary timer T5 can count up or down de pending on the control bit T5UD and it can be star
358. upt control registers Figure 7 3 Examples of Possible Configurations in the Interrupt Control Registers Field Type of Service COUNT PEC Transfer Counter field of selected PEC channel if COUNT 0 PEC Service Channel 7 If COUNT 0 CPU Interrupt Priority Level 15 Group Priority 3 If COUNT 0 PEC Service Channel 6 If COUNT 0 CPU Interrupt Priority Level 15 Group Priority 2 if COUNT 0 PEC Service Channel 3 If COUNT 0 CPU Interrupt Priority Level 14 Group Priority 3 If COUNT z 0 PEC Service Channel 0 If COUNT 0 CPU Interrupt Priority Level 14 Group Priority 0 E 441 1 CPU Interrupt Priority Level 13 Group Priority 3 10 CPU Interrupt Priority Levei 13 Group Priority 2 oo CPU Interrupt Priority Level 13 Group Priority 1 00 CPU Interrupt Priority Level 13 Group Priority 0 00 CPU Interrupt Priority Level 1 Group Priority 0 NRIEN No Service 10 No Service 01 No Service 00 No Service Siemens Aktiengeselischaft 7 8 interrupt and Trap Functions 7 2 12 Interrupt Control Functions in the PSW The Processor Status Word PSW is functionally divided into 2 parts the lower byte of the PSW basically represents the arithmetic status of the CPU the upper byte of the PSW controls the interrupt system of the SAB 80C166 This section specificaily refers only to those fields of the PSW that globally control interrupt and PEC service functions The organization of the PSW
359. urces has a dedicated vector location Software interrupts are supported by means of the TRAP instruction in combination with an individual trap interrupt number The SAB 80C166 also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run time so called Hardware Traps Hardware traps cause immediate non maskable system reaction which is similiarto a standard interrupt service branching to a dedicated vector table location The occurence of a hardware trap is additionally signified by a individual bit in the trap flag register TFR Except another higher prioritized trap service being in progress a hardware trap will interrupt any actual program execution In turn hardware trap services can normally not be interrupted by standard or PEC interrupts 3 5 Capture Compare CAPCOM Unit The CAPCOM unit supports generation and control of timing sequences on upto 16 channels with a maximum resolution of 400 ns The CAPCOM unit is typically used to handle high speed I O tasks such as pulse and waveform generation pulse width modulation PWM Digital to Analog D A conversion software timing or time recording relative to external events Two 16 bit timers TO T1 with reload registers provide two independent time bases for the capture compare register array The input clock for the timers is programmable to several prescaled values of the internal system clock or may be derived from
360. ure is described in detail in section 8 2 2 2 about auxiliary timer T5 Semiconductor Group SIEMENS Peripherals A reload of timer T6 on overflow underflow with the contents of register CAPREL can be selected through bit T6SR in register TECON A detailed description of this option can be found in section 8 2 2 3 about the CAPREL register An overflow or underflow of timer T6 can also be used to clock timers TO or T1 in the CAPCOM unit For this purpose a direct internal connection between timer T6 and timers TO and T1 exists Refer to section 8 1 CAPCOM Unit for more details Figure 8 2 21 shows a block diagram of T6 in timer mode To CAPCOM Timers TO T1 To GPT2 CAPREL Register Interrupt 6UD To GPT2 Timer T5 Figure 8 2 21 Block Diagram of GPT2 Core Timer T6 in Timer Mode 8 2 2 1 2 Timer T6 Interrupt Control When timer T6 overflows from FFFFh to 0000h when counting up or when it underflows from 0000h to FFFFh when counting down the interrupt request flag T6IR in register T6IC will be set This will cause an interrupt to the timer T6 interrupt vector T6INT or will trigger a PEC transfer if the interrupt enable bit T6IE in register T6IC is set Figure 8 2 22 shows the organization of interrupt control register T6IC Refer to chapter 7 for more details on interrupts T6IC FF68h B4h Reset Value 0000h 7 6 1 0 T6IR T6IE GLVL Figure 8 2 22 GPT2 Timer T6 Interrupt Control Register T6IC Semiconductor Gro
361. us mode The two pins of Port 4 will output the segment address since bit SGTDIS in register SYSCON is 0 default after reset The code segment pointer CSP is initialized to zero and all bits of the data page pointers except for the two LSBs are also initialized to zero during reset Therefore Port 4 will always output 00b after reset When no memory accesses above 64 K are to be performed segmentation may be globally disabled by setting bit SGTDIS to 1 When an external 16 bit data bus mode 16 18 bit address multiplexed or non multi plexed is selected the BHE pin will be active after a reset It can be disabled by setting the BYTDIS bit in the SYSCON register to 1 11 5 Initialization Software Routine To ensure proper entry into the initialization software routine a hardware branch to location zero segment zero is made immediately following completion of the internal system reset or deassertion of a correct reset signal on pin RSTIN respectively Since location 0000h is the first vector in the trap interrupt vector table it is the responsibility of the user to place a branch instruction at location zero which branches to the first instruc tion of the initialization routine Note that 8 bytes locations 0000h through 0007h are provided in this table for the reset function If single chip mode is selected through pins EBCO and EBC1 the internal ROM is accessed when the initial branch is madetolocation zero Otherwise an
362. us request BREQ will be detailed in the next revision of this paper Semiconductor Group D 13 SIEMENS SAB 80C166 83C166 Auxiliary Timer T5 TSIR ee Edge Select _ CAPIN i P3 2 off aed Wi cniR Interrupt Request l CAPREL Register MCS02925 Figure 1 1 Register CAPREL in Capture Mode T5UD Input m Interrupt Clock Auxiliary Timer T5 TSIR Request t TSCLR Edge Select CAPIN P3 2 fji N Iv Interrupt gt CRIR Request Y Pe seb easel uw T6SR T60E Input Interrupt Close Core Timer T6 T6IR Request T To CAPCOM T6UD Timers TO T1 MCS02926 Figure 1 2 Register CAPREL in Capture and Reload Mode Semiconductor Group D 14 SIEMENS SAB 80C166 83C166 SOCON FFBOh D8h Reset Value 0000h 15 14 13 12 11 10 9 7 6 5 4 3 2 1 S1CON FFB8h DCh Reset Value 0000h 1 pi 15 14 13 12 11 10 9 8 ps pee e aee ae 7 6 5 4 3 2 1 0 EE eS a usd MUST NN Figure 2 1 Serial Channels Control Registers SOCON and S1CON Symbol Position Function SxM SxCON 2 0 ASCx Mode Control see table 8 4 1 SxSTP SxCON 3 Number of Stop Bits Selection SxSTP 20 One Stop Bit SxSTP 1 Two Stop Bits SxREN SxCON 4 Receiver Enable Bit Used to Initiate Reception Reset by hardware after a byte in synchronous mode has been received SxREN 0 Receiver Disabled SxREN 1 Receiver Enabled SxPEN SxCON 5 Parity Check Enable Bit SxPEN 0 Parity Check Disab
363. ut Write Pulse Low Time twres to nt 50 f x z2TCL 10 n1 2TCL ni gt twr 50 0 8 ni gt hy 10 2TCL 1 tow Data Valid to WR tjw lt b2 N2 50 fg 2 2017CL 15 n2 2TCL n22214 50 0 7 n2 gt tw 15 2TCL 1 tah Data Hold after WR tih bog tn 2TCL 10 has Adress Setup tas lt lg lg tas 2TCL 25 Ls lt 25 t ALE Cycle Time t 100 n 50 t2 4ATCL n 2TCL Note ALE Cycle Time Memory Cycle Time 4TCL 100 ns at 40 MHz for 0 wait state operation PME la lg tyo too t24 See Device Specification Section D 5 5 Take care of ty and fas These times cannot be proglonged by wait states Table C 4b Non Multiplexed Memory Write with Read With Delay Quick Table lacc ni be n2 lt 40 0 lt 35 0 2 40 lt 90 1 25295 2 SS BS 1 gt 90 lt 140 2 I 60 lt 135 2 gt 140 lt 190 3 gt 135 lt 185 3 gt 190 lt 240 4 185 lt 235 4 gt 240 lt 290 5 J 235 lt 285 5 Semiconductor Group C 14 SIEMENS Microcomputer Components SAB 800166 83C166 16 Bit CMOS Single Chip Microcontrollers for Embedded Control Applications Addendum to User s Manual 9 90 Note The User s Manual describes the SAB 80C166 up to the AB step The Addendum to the User s Manual describes the improvements and features implemented in the SAB 80C166 from the BA step There is no explicit no
364. ut pin for TO P3 0 must be configured as input i e the corresponding direction control bit DP3 0 in register DP3 must be set to O If P3 0 TOIN is configured as output timer TO may be clocked by modifying port data register bit P3 0 through software e g for testing purposes The maximum external input frequency to TO in counter mode is fosc 16 1 25 MHz 40 MHz fosc To ensure that a signal transition is properly recognized an external count input signal should be held for at least 8 state times before it changes its level again The incremented count value appears in SFR TO within 8 state times after the signal transition at pin TOIN 8 1 1 3 Reload A reload of a timer with the 16 bit value stored in its associated reload register is performed in timer mode as well as in counter mode each time a timer overflows from FFFFh to 0000h The reload registers TOREL and T1REL are not bit addressable Semiconductor Group 8 8 SIEMENS Peripherals 8 1 1 4 Timer TO and T1 Interrupts Upon timer overflow the corresponding timer interrupt request flag TOIR or T1lIR for the respective timer will be set This flag can be used to generate an interrupt or trigger a PEC service request when enabled by the interrupt enable bits TOIE or T1IE Each of the two timers TO or T1 has its own bit addressable interrupt control register TOIC or T1IC and its own interrupt vector TOINT or T1INT Figure 8 1 4 shows the organization of the interrupt cont
365. ution starts from location 0000h Reset conditions have priority over every other system activity and therefore have the highest priority trap priority IIl For more details on reset refer to chapter 11 Software traps may be performed to any vector location between Oh and 1FCh A routine entered by a software TRAP instruction is always executed on the current CPU priority level which is indicated in the ILVL field in the PSW This means that routines entered via the software TRAP instruction can be interrupted by all hardware traps or higher level interrupt requests Table 7 2 Reset and Trap Vector Locations Exception Condition Reset Functions Hardware Reset Software Reset Watchdog Timer Overflow Class A Hardware Traps Non Maskable interrupt Stack Overflow Stack Underflow Class B Hardware Traps Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Reserved Software Traps TRAP instruction Siemens Aktiengesellschaft Trap Trap Vector Trap Flag Vector Location Number Oh Oh Oh Oh Oh Oh NMITRAP STOTRAP STUTRAP UNDOPC Ah PRTFLT Ah ILLOPA Ah ILLINA Ah ILLBUS A h LL jeesacu iens Any Any Oh 1FCh Oh 7Fh in steps of 4H Trap Priority Current CPU Priority Interrupt and Trap Functions 7 2 Normal Interrupt Processing and PEC Service The priority of service for interrupts
366. uxiliary timers can be concatenated with the core timer or they may be used as reload or capture registers in conjunction with the core timer Unlike the core timer the auxiliary timers can not be controlled for up or down count by an external signal nor do they have a toggle bit or an alternate output function Semiconductor Group 8 33 SIEMENS Peripherals The individual configuration for timers T2 and T4 is determined by their bit addressable control registers T2CON and T4CON which are both organized identically Note that functions which are present in all 3 timers of block GPT1 are controlled in the same bit positions and in the same manner in each of the specific control registers Figure 8 2 9 shows the control registers for the auxiliary timers T2CON FF40h A0h Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T4CON FF44h A2h Reset Value 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Figure 8 2 9 GPT1 Auxiliary Timers T2 and T4 control Registers T2CON and T4CON Symbol Position Function Txl TxCON 2 0 Timer x Input Selection For Timer and Gated Timer mode see table 8 2 3 For Counter Mode see table 8 2 6 For Reload Mode see table 8 2 7 For Capture Mode see talbe 8 2 8 TxM TxCON 5 3 Timer x Mode Control see table 8 2 5 TxR TxCON 6 Timer x Run Bit TxR 20 Timer Counter x stops TxR 21 Timer Counter x runs TxUD TxCON 7 Up Down Control Bit TxUD 20 Timer Counter x counts up TxUD
367. ware For timer T3 the count direction may additionally be altered dynamically by an external signal on a port pin to facilitate e g position tracking Timer T3 has an output toggle latch which changes its state on each timer oveflow underflow The state of this latch may be output on a port pin e g for time out monitoring of external hardware components or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution In addition to their basic operating modes timers T2 and T4 may be configured as reload or capture registers for timer T3 When used as capture or reload registers timers T2 and T4 are Semiconductor Group 3 6 SIEMENS System Description stopped The contents of timer T3 are captured into T2 or T4 in response to a signal at their associated input pins Timer T3 is reloaded with the contents of T2 or T4 either by an external signal or by a selectable state transition of its toggle latch When both T2 and T4 are configured to alternately reload T3 with the low and high times of a PWM signal this signal can be constantly generated without software intervention With its maximum resolution of 200 ns fosc 40 MHz the GPT2 module provides precise event control and time measurement It includes two timers T5 T6 anda capture reload register CAPREL Both timers can independently count up or down clocked with an input clock which is derived from a programmable prescaler Concatenation
368. ware because only even STKUN contents are compared against the SP register Modifiable portion of the STKUN register Bits tied to 1 by hardware This restricts contents to values from F800h to FFFEh Siemens Aktiengesellschaft 5 33 Central Processing Unit CPU Since the least significant bit of the STKUN register is tied to 0 and bits 11 to 15 are tied to 1 by hardware the STKUN register can only point to even word addresses from OF800h through OFFFEh After reset the STKUN register is initialized to FCOOh A stack underflow trap can be used for an automatic filling of the system stack for example when an external user stack is used as a storage extension of the internal system stack For more details about the implementation of a stack underflow trap service routine see chapter 13 4 1 5 3 10 MDH Multiply Divide Register High Portion This register is implicitly used by the CPU when it performs a multiplication or a division After a multiplication this non bit addressable register represents the high order 16 bits of the 32 bit result For long divisions the MDH register must be loaded with the high order 16 bits of the 32 bit dividend before the division is started After any division the MDH register represents the 16 bit remainder Figure 5 18 Multiply Divide Register High Portion MDH FE0Ch 06h Reset Value 0000h Symbol Position Funcion S O MDH 15 0 Specifies the hi
369. ween the timer value and the value in a capture compare register specific actions will be taken based on the selected compare mode 3 6 General Purpose Timer GPT Unit The GPT unit represents a very flexible multifunctional timer counter structure which may be used for many different time related tasks such as event timing and counting pulse width and duty cycle measurement pulse generation or pulse multiplication The GPT unit incorporates five 16 bit timers which are organized in two separate modules GPT1 and GPT2 Each timer in each module may operate independently in a number of different modes or may be concatenated with another timer of the same module Each of the three timers T2 T3 T4 of the GPT1 module can be configured individually for one of three basic modes of operation which are Timer Gated Timer and Counter Mode In Timer Mode the input clock for a timer is derived from the internal system clock divided by a programmable prescaler while Counter Mode allows a timer to be clocked in reference to external events Pulse width or duty cycle measurement is supported in Gated Timer Mode where the operation of a timer is controlled by the gate level on an external input pin For these purposes each timer has one associated port pin which serves as gate or clock input The maximum resolution of the timers in the GPT1 module is 400 ns fogc 40 MHz The count direction up down for each timer is programmable by soft
370. while Port 1 has only an alternate output function Figure 10 6 shows the structure of a Port 0 pin and figure 10 7 shows the structure of a Port 1 pin Alternate Direction Direction Latch DPO y Write DPO y Alternate Function Enable Read DPO y Read Buffer Alternate Function Enable Write Port PO y Alternate Data Read Port PO y Read l Buffer Buffer Alternate Data Input Figure 10 6 Block Diagram of a Port 0 Pin When an external bus mode is enabled the direction of the port pin and the data input to the port output latch are controlled by the bus controller hardware The input to the port output latch is disconnected from the internal bus and is switched via a multiplexer to the line labeled Alternate Data Output On Port 0 the alternate data can be the 16 bit intrasegment address Semiconductor Group 10 7 SIEMENS Parallel Ports Write DP1 y Direction Latch DP1 y Alternate Function Enable Read Alternate Buffer Function Enable Read DP1 y Write Port P1 y Alternate Data Output Read Port P1 y Read l Buffer Figure 10 7 Block Diagram of a Port 1 Pin or the 8 16 bit data information On Port 1 the alternate data is the 16 bit intra segment address in the non multiplexed bus mode The incoming data on Port 0 is read on the line Alternate Data Input While an external bus mode is enabled the user software should not write to the port output latch otherwise
371. wledged while segmentation is disabled Figure 7 7 interrupt Procedure with Segmentation Disabled High High Addresses Addresses SP YY ML as Psw State of interrupted task saved on system stack Low Addresses Addresses a System Stack before b System Stack after Interrupt Entry Interrupt Entry Siemens Aktiengesellschaft 7 17 Interrupt and Trap Functions 7 2 4 2 Interrupt Procedure with Segmentation Enabled The procedure that will be performed by the SAB 80C166 s interrupt system when segmentation is enabled is independent of the code segment that the CPU is currently executing from If segmentation is used when an interrupt request is acknowledged the Code Segment Pointer CSP must also be pushed on the system stack to ensure correct return to the previous segment after completion of the interrupt service routine The contents of the PSW are pushed first then the contents of the CSP and IP are pushed on the system stack The CSP for the interrupt service routine is set to segment zero As with segmentation disabled the interrupt source s priority level is copied into the CPU Priority field of the PSW and the Interrupt Request flag of the source that caused the interrupt is cleared If a multiply or divide operation was in progress when the interrupt was acknowledged the MULIP bit in the PSW of the interrupt service routine is set to 1 No data page pointer is affected Upon execution of the RETI instr
372. xecuting a SCXT switch context instruction This mechanism does not provide a method to recursively call a subroutine Saving and Restoring of Registers To provide local registers one can push the contents of the registers which are required for use by the subroutine and pop the previous values before returning to the calling routine This is the most common technique used today and it does provide a mechanism to support recursive proce dures This method however requires two machine cycles per register stored on the system stack one cycle to PUSH the register and one to POP the register Use of the System Stack for Local Registers Itis possible to use the SP and CP to set up local subroutine register frames This allows subroutines to dynamically allocate local variables as needed in two machine cycles To allocate a local frame one simply subtracts the number of required local registers from the SP and then moves the Figure 13 1 Local Registers Old Stack Example After subroutine entry SUB SP 10 5 Words SCXT CP SP Newly Allocated Register Bank Before exiting subroutine POP CP ADO SP 410 5 Words Siemens Aktiengesellschaft 13 8 System Programming value of the new SP to the CP This operation is supported through the SCXT switch context instruction with the addressing mode reg mem Using this instruction one can save the old contents of the CP on the system stack and move the value of
373. xed Buses External RAM ROM Word Organized Memories This configuration is shown in figure C 5 Except that the available RAM space is doubled and that two byte organized memories are replaced by one word organized memory this configuration is identical to the example shown in figure C 4 16 bit Addresses 16 bit Data Non Multiplexed Buses External RAM ROM Both Word and Byte Organized Memories This configuration is shown in figure C 6 The external memory is implemented by one 16K 16 EPROM and by two 8K 8 RAMs Because two separate 16 bit data and 16 bit address buses are used no external address latch is required The EPROM can only be accessed wordwise while the RAMs can also be accessed bytewise provided that the function of the BHE output pin is not disabled In this case the address signal AO selects the lower byte memory and the active low BHE signal selects the upper byte memory Semiconductor Group C 2 SIEMENS Application Examples AD0 AD7 EBCO EBC ALE P00 P0 7 P0 8 SAB 80C166 MCS00287 EPROM 32K 8 Oh 7FFFh RAM 8K 8 8000h 9FFFh Figure C 1 16 bit Addresses 8 bit Data Multiplexed Bus External RAM ROM Byte Organized Memories Semiconductor Group C 3 SIEMENS Application Examples P40 A16 E P41 A17 P312 BHE 13 WR fg P314 READY Fe P315 CLKOUT c LL LL LL 9 E oO Address Range Oh 7FFFh MCS00288 Memory Config Figure C 2 16 bit
374. xternal Bus Interface 9 6 1 2 Multiplexed Bus Memory Writes After the address has been stored externally and removed from the bus again data are driven onto the bus and the active low memory write signal WR is applied to the memory This enables the memory to store the data from the bus onto the addressed location After a period of time which is determined by the access time of the memory the data become valid in the addressed memory location Then the controller removes its memory write signal The data remain valid on the bus until the next memory access cycle is started 9 6 2 Non Multiplexed Bus Transfer Characteristics In the Non Muitiplexed Bus mode there are separate buses for both the address and the data Figure 9 8 shows the timing sequence of a memory read and memory write access via a non multiplexed bus Figure 9 8 Non Multiplexed External Bus Access ALE N N WR Siemens Aktiengeseilschaft 9 11 External Bus Interface 9 6 2 1 Non Multiplexed Bus Memory Reads A memory read access is initiated by the controller by placing an address on the address bus This address stays valid on the bus until the next memory access cycle is started After a fixed period of time the active low memory read signal RD is applied to the memory This enables the memory to drive data onto the data bus After a period of time which is determined by the access time of the memory data become valid on the data bus Then
375. xtra time to fetch the branch target instruction can be saved andthusthe correspon ding cache jump instruction in most cases takes only one machine cycle to beperformed This performance is achieved by the following mechanism Whenever a cache jump in struction passes through the decode stage of the pipeline for the first time and provided that the jump condition is met the jump target instruction is fetched as usual causing a time delay of one machine cycle In contrast to standard branch instructions however the target instruction of a cache jump instruction JMPA JMPR JB JBC JNB JNBS is additio nally stored in a cache after having been fetched After each repeatedly following execution of the same cache jump instruction the jump target instruction is not fetched but taken from the cache and immediatly injected into the decode stage of the pipeline see figure 5 3 Siemens Aktiengesellschaft 5 4 Central Processing Unit CPU A time saving jump on cache is always taken after the second and any further occurence of the same cache jump instruction unless an instruction whichhas the fundamental capa bility of changing the CSP register contents JMPS CALLS RETS TRAP RETI or any stan dard interrupt has been processed during the period of time between two following occurences of the same cache jump instruction Figure 5 3 Cache Jump Instruction Pipelining Injection Injection of cached 1 Machine Cycle FETCH Fen
376. y each bit in the currently active register bank can be accessed individually Siemens Aktiengesellschaft 4 10 Memory Organization The SAB 80C166 supports fast register bank context switching Based on that multipie register banks can physically exist in the internal RAM at the same time However only the register bank selected by the CP register is active and the remaining register banks are inactive at that time Selecting a new active register bank is simply done by updating the CP register A particular Switch Context SCXT instruction performs register bank swit ching and an automatic saving of the previous context Any number of variously sized re gister banks only limited by the available internal RAM size can be implemented simul taneously For more details about GPR addressing via the CP register see the corresponding section 5 3 3 Advanced programming methods for an optimum utilization of the GPRs features such as Context Switching Context Packing Overlapping Register Banks Local GPRs on the system stack and so on are described in chapter 12 0 System Programming 4 3 3 PEC Source and Destination Pointers The upper 16 word locations in the internal RAM addresses from OFDEOh to OFDFEh are provided as source and destination address pointers for PEC data transfers Figure 4 5 PEC Source and Destination Pointer Word Organization Source ana Internal Destination RAM Pointers DSTPO SRCPO Siem
377. y of key features which contribute to the high performance of the SAB 80C166 is listed below High Performance 16 Bit CPU With Four Stage Pipeline 100 ns minimum instruction cycle time with most instructions executed in 1 cycle 500 ns multiplication 16 bit 16 bit 1 us division 32 bit 16 bit High bandwidth internal data buses Register based design with multiple variable register banks Single cycle context switching support 256 Kbytes linear address space for code and data von Neumann architecture System stack cache support with automatic stack overflow underflow detection Control Oriented Instruction Set with High Efficiency Bit byte and word data types Flexible and efficient addressing modes for high code density e Enhanced boolean bit manipulation with direct addressability of 4 Kbits for peripheral control and user defined flags e Hardware traps to identify exception conditions during runtime Integrated On chip Memory 1 Kbyte internal RAM 8 Kbytes internal ROM SAB 83C166 Siemens Aktiengesellschaft 1 2 Introduction External Memory Expansion Interface e Supports 3 different bus configurations plus segmentation capability 16 Priority Level Interrupt System e 32 interrupt sources with separate interrupt vectors e 300 500 ns typical maximum interrupt latency in case of internal program execution 8 Channel Peripheral Event Controller PEC Interrupt driven single cycle data transfer T
378. ystem Reset 11 2 Reset Values for SAB 80C166 Registers Most SFRs including system registers and peripheral control and data registers are forced to zero once the internal reset has completed This defauit configuration has been selected such that all peripherals and the interrupt system are disabled from operation Only data page pointers DPP1 through DPP3 the CP SP STKOV STKUN SYSCON WDTCON and specific read only registers may contain default values other than zero after a system reset A complete summary of all SAB 80C166 registers and their reset values is contained in Appendix B Note that the contents of the internal RAM are not affected by a system reset After a power on reset the contents of the internal RAM are undefined This implies that the GPRs and the PEC source and destination pointers SRCPy DSTPy y 0 7 which are map ped into the internal RAM are also undefined after a power on reset After a warm reset or a reset which is caused by an overflow of the Watchdog Timer or by execution of the SRST instruction the previous contents of the internal RAM remain unaffected The four Data Page Pointers DPPO through DPP4 are initialized during a system reset such that they are pointing to the lowest four consecutive 16 K data pages DPPO points to data page 0 DPP1 points to data page 1 DPP2 points to data page 2 and DPP3 points to data page 3 11 3 Watchdog Timer Operation after Reset The Watchdog Timer starts runni
379. ytes each and each segment is again subdi vided in four pages of 16 Kbytes each The total addressable memory space can be ex panded up to 16 Mbytes for future members of the SAB 80C166 family Figure 4 1 Memory Segment and Page Arrangement Data Code Address Page Segment 3FFFFh 30000h 1FFFFh 10000h OFFFFh 00000h 256 KByte Total Address Space Siemens Aktiengesellschaft 4 1 Memory Organization Bytes are stored at even or odd byte addresses Words are stored in ascending memory locations with the low byte at an even byte address being followed by the high byte at the next odd byte address Double words code only are stored in ascending memory loca tions as two subsequently following words Single bits are always stored in the specified bit position at a word address Bit position O is the least significant bit of the byte at an even byte address and bit position 15 is the most significant bit of the byte at the next odd byte address Figure 4 2 Word Byte and Bit Storage in a Byte Organized Memory Example plc CORES eo m fo Byte Word High Byte Word Low Byte Table 4 1 shows how the different memory areas are mapped into the physical 256 Kbyte address space Basically all of the internal memory areas ROM RAM SFRs are mapped into parts of memory segment 0 The external memory is mapped into the remaining parts of memory segment 0 and into memory segments 1 through 3 Whenever internal ROM acc
380. zed For example branch instructions only require an additional machine cycle when a branch is taken and most branches taken in loops require no additional machine cycles The instruction cycle time has been dramatically reduced through the use of instruction pipelining This technique allows the core CPU to process portions of multiple sequential instruction stages in parallel The following four stage pipeline provides the optimum balancing for the SAB 80C166 family s CPU core FETCH In this stage an instruction is fetched from the internal ROM or RAM or from the external memory based on the current IP value DECODE In this stage the previously fetched instruction is decoded and the required operands are fetched EXECUTE In this stage the specified operation is performed on the previously fetched operands WRITE BACK In this stage the result is written to the specified location If this technique were not used each instruction would require four machine cycles This increased performance allows a greater number of tasks and interrupts to be processed Semiconductor Group 2 1 SIEMENS Architectural Overview 2 1 2 High Function 8 bit and 16 bit Arithmetic and Logic Unit Most internal execution blocks have been optimized to perform operations on either 8 bit or 16 bit quantities Once the pipeline has been filled one instruction is completed per machine cycle except for multiply and divide An advanced Booth algorithm has be

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