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QorIQ Configuration Suite Tool Introduction

1. d Ly WMA Betar Pores Lonin bP rejrct P 125 bot Properties Alt enm Ew Bask Confgur asti n Zz type f er test Import configoraien fron am axmting PEL fhe E lise ACW Marnd coded configuration COR A Tutoriats v v Prout Pet pass PPSN Deiro OxIO 139 nes heohict Broe HOD Object Dump v Only select the PBL tool for now Select rat Me to te used for importing an existing POL configuration and choose the appropriate fie Format oi O TM o fr e est a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 47 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HH E ZR Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and i i Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Import rew 0x10 Ss Component Inspector Properties Import Decode Input File Input File Docs FrFipaoBO ds R PPSXM Oxi rcw Ox10 5g rev2 low bin txt Input Format XXD Object Dump Input data DODODOD aa55 aa55 010e 0100 4c
2. gt Be HA Rae ime 00 Sauter 4 E Pues Q cesse EL e 4 oe Lp C TM Dl m p r e es a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 8 8 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HR E ZR Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Properties Panel Graphing Panel Graphing Palette Zanta m E E Basic Advanced Expert I moe FMan Port BMan Qu Frame Manager Port ngi PCD E F aT Rx Port z Port Id rx Port EEX yl M Fort name ea Error FQ Id ast Fal ra m e a n ag e r MAC address Do 1 Default FQId p P O rt S ESSE LIODN Offset ts B pow Tx Port Loopback TxPort C use RQ EmoFOld C Reset on init Defsutrold Frame Maagaer Buffer Pools Selecting an item on the graphing panel and double a ee click gets you the Force Buffer Pool Id properties for that objec
3. lt protoacols gt lt protocolret name lan lt protocols gt z distribution zdistrihbution name bistrihution2 Queue count 2 2 bases D 2 gt lt key gt lt fieldref name ethernet srco Iieldrerz name 11c snap type lt key gt lt protoacols gt lt protocolret name lan lt proatocols gt z distribution Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc import XMLs Feature he xmls can be imported at project creation time or later after the project is created Processor Expert Eclipse Platform New QorIQ Configuration Project DPAA Configuration 3 File or Folder not specified Vosa e e 5 ea agate oe ee e imparte hex Ahead Export 0 SS epot te E i Document ain E Generated Code i gt Sources ProcessorE pert pe b Configurations
4. 05500 power ms dea io asco past drsi 29 qonc hmant portas Asi Gore gran i portis cts Q densn port obB 1 DIOT node ts defined im eds cts rm 63 aon boni terials ds re 74 Fite tes ds ine 57 j te Gone rece dei reyes des grinari des qure ek Dx qon eadrec 0 as gonq uc des qoral l c qorerdomt 0 des Qo duet 1 9 regen des Qqor rusb notri raud d Dd bea Sw tries compatible teg 221cO00D interrupts lt 119 Deal Delt Ly i i bmmn portma1829000 cell index tcapetiznie dei reg 0 interrupts sl brann DOCO Dr4000 Dr 10900 mrsa desi ee s2 1 de3 greit D0 ud ree des gore mano ds tyan ogeman t ides gorrbment des qon man dcs aromen O La 0 tes ewe ibm d bmun paortalR24000 celi index n gt compatibie te in 9 compatible property ts defined in anaimani prts dts ne 94 buffer cocl80 Devens tree Include tree e Po ejfe Z freescale TRER t2l tean portel p Ttml1 21 be9n portal include declaration node reference 23 Hyperlink detection for include declarations and device tree references Ctrl left click DT rwDme Tree che HGA os includse fsl nS502021 pre dts1 model fs1 F5020DP8 compatible 251 PS020D3 faddress cells size celis tnterrupt parent _ lt smpic gt senetu wtherneti
5. 57249 gt 4 we A os gy at e s vtt DR DOR Complex DORCLK Ratio 41 420 000 MHz e p Lo PSL A TM ar fr e e S C a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC ins 63 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t m E ZR Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and il Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Properties cfg sys pll 0 2 b010 6 1 Pins LA 29 31 Changing the 400 Mhz gt 600 Mhz EVICE i Li Cored 900 000 MHz Corel 900 00 a Power On Configuration ratios to desired cfg core pll 0 2 ObO11 3 2 1 5 1 Pins LBCTL LALE LGPL2 LOE B L Pins LWEO_B UART SOUTI READ CCB and Core efgcorelpli t2 0b011 32 1 5 1 clocking 1600 Mhz gt 900 Mhz cfg_ddr_pll 0 2 ObOO1 4 1 AUT TSEC_ 4 e500 Core CCB Clock R Corel 4 1 Corel 4 1 Cored 1 600 GHz Corel 1 600 GHz I O Port Selection cfg coreO pll 0 2 QbO00
6. Reset Configuration Word RCW reg isters Memo ry 00000000 105a0000 00000000 1e1e181e 0000cccc 00000010 40464000 3c3c2000 fe800000 61000000 browser expo rt function 00000020 00000000 00000000 00000000 008b6000 00000030 00000000 00000000 00000000 00000000 SERDES Reference Clocks Bank1 125MHz Bank2 125MHz Bank3 125MHz I2C ready DRAM Initializing using SPD Detected UDIMM s Detected UDIMM s 2 GiB left unmapped DDR 4 GiB DDR3 64 bit CL 9 ECC on Testing 0x00000000 Ox7fffffff Testing 0x80000000 Oxffffffff Remap DDR 2 GiB left unmapped 4 N 7 freescale ge E BELTS A DDR Step 2 Import DDR1 and DDR2 Registers Dump Under QCS Processor Expert p4080 core0 Source main c CodeWarrior Development Studio File Edit Source Refactor Navigate Search Project Run Profiler Processor Expert Window Help E37 HG m OU im TQ im we i Ate gl eee 25 Project Panel 3 E amp amp o S component Inspector 53 Basic Advanced Expert lig B a eee A i us 2020rdb cored S pr TEE Import Sl p4080 gt Documentation Memory Dump File H Generated Code Input File DADebianshare GorIQsDK z 03 O08 DDR hweonfig noneyddr1 _OxFFeOO8000_O FreOoerfF bin E id 5 EE ProcessorExpert pe gt Configurations Access Size dP pane v2 0 Cnf Operating System Addressable Size byte Ill Be e Endian made Default Big Endian
7. jormmu 20000 E a rmu rmu d3000 General information Documentation Properties mpic pic 40000 This section describes general information about the selected node Direct Memory Access c 4 timer 41100 Press F1 for more detai m 1 address cells 4 msiO msi 41600 Name dmaQ dmaf100300 4 msil msi 41800 Parent soc socliffe000000 f msi2 msi 41a00 lines 1547 1582 Required yes 2 4 timer 42100 Value type CELLLIST 3 4 guts global utilitiesieQ000 Constraints not defined 4 pins global utilities e0e00 Properties Description This property may be used in any clockgen global utilities e1000 This section describes information about the selected node s properties device node that has children in the device tree repm global utilties e2000 p x hierarchy and describes how child device nodes S edis oio should be addressed It defines the number of posts ol 000 4j dmaU ama Hsec aedi l to Meet E a 4 dmat dma 101300 child node s reg property If missing a client 4 sdhc sdhe 114000 program should assume a default value of 2 2c 116000 4 i2c 119000 size cells or anges Oo 100100 200 20 119100 senan SAE TEO pragai cele leaden Reguired yes sien gps pd Type U32 Value type CELLLIST Serial2 seria 4 bd Mire Constraints not defined cm Description allg T gpio0 gpio 130000 J The cel index property is the hardware index
8. 2013 Freescale Semiconductor Inc New Age Sht N Bh Power Aate fopa Open Path Ciri Sia Qon to Tuext Fie Uie 23187 T em pwm Oe MITER O MLA 5 pen Fe T Makefile Prouect with Extstieg Code teat low wie r Proet ikea Af iri ita Wi Sec to be utet amp Sere foide type Iher test iet Cii 1 C3 ird de lose amp d ewe Fe PI Sese Ai Cit Stems Weeder fus Kun mt ehom Temple PALA Cet Fesarme r r Own Ctrl N Keehi n 9 el Comvert Line Detereters To a Puri Creates propect for PAND dewetive Santech Wortmece n 4 V What s New Product Releg kx Import at us r i Web Resources Service Pi emen de yeu monto configure Properties Ati mtm tot Conpenents to be sefectert fepe iter feet hs Compinerts c y POOTEOM Corfiguratian DDS Lernory Conteotes Configuration sh Project Importer Device Tree Edhar Go Select th elec e K010 The BOOTROM cerfiguraben toal provide tupper fot of boot am m MOM data rinatu and power on reset conmtiguration of PLPG Qot dex o PS PDP TM 2 fr e est a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 62 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet exis Layerscape MagniV
9. Configure LAW 11 for DDR ff7 00D70 80F0001LD 4 Configuration Words data structure definition Version specific item Settings supported only for Boot ROM Data Configuration present in QorlQ devices ey Lpy TM T o r Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Nus 6 8 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t A ZR Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc BOOTROM Step 5 Usage of configuration data file with external booting utility application Use a booting utility boot format from a BSP package Control for P2020RDB P102RDB Words Once you have installed BSP and let configured Itib to build root file system rootfs tar gz uboot for Linux boot Boot the board using this root file system and boot_format utility can be located under root P1020RDB amp cd boot format root P1020RDB boot format Is I Configurati rwxr xr x 1 root root 10400 Apr 7 20
10. freescale CHER LI QorlQ Configura ation S Tool Introduction APF ENT T0579 April 2013 Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc lt gt Promise Before you leave today you will Understand why configuration tools will help you Have a basic understanding of what will be available Have undergone a basic walkthrough of the tools Used actual configurations and modified them based on customer requests to configure RCW pre boot loader settings DDR memory controller settings Device Trees Linuxe hardware device tree settings Data Path graphs configuring the DPAA Know where to get more information 4 N CREM 9 9 TM m e p re esca e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire Col
11. amp init qcs c 11KB C Source File v Receive output L main c 2KB C Source File v Ep integrations QCS Dbg QCS Dbg launch 51KB v gt Referenced Projects 1 E SaAnalysispointsManager apconfig 1 KE v o 6 9 m z freescale JOD Prossime co uina Soa Son and Vote sre toda ofa Soon c Reg US Pad m OF Aras Beek och Ct CHER joa ero these saison s Majin cies a A Hine irre eddie d i ME DPAA Hands on Usecase Output Report Use a serial terminal to receive usecase output Input frames Frames transmitted by usecase on FMAN port2 5 frames on FMO Port IPV4 IPVA UDP VLAN ARP IPV4 TCP Output report Frames received are enqueued according to PCD FMO Port1 FQID 45 0x2D FQID 46 0x2E FQID 32 0x20 FQID 32 0x20 FQID 46 0x2E e Peo freescale YEA HHHH HHHHHHHHHH HetComm Device Drivers THEE AT Version 4 5 HHHH built on Hay 28 2012 Usage gt lt command options argi argH Type For help HCS W gt gt Executing Test DPAA Basic 1 DPAA QCS use case gt INFO FH CPUBB E Freescale NetComm Software 4 5 58 5 HetCommSu zPeripheral Code FHan Controller code uer 186 2 2 loaded to IRAH Sending 5 frames on Port 165 fmi_p2tx from FQR Frame received on x 2d From FOR FOR1 Frame received on x2e From FOR FOR1 Frame received on x2H From FOR F RT1 Frame received on x2H From FOR FOQR1 Frame received on Bx2e From FOR FOR1 A 2 2
12. iwe rot pee Y SOS LPO imen M D Lae rot pomir Y wo 150 B1 Lane E 156 D Lane rot pesce Y su LPO 41 Lane 157 Lame powered m T S05 120 Bi lanet 1158 0 Lave ni powe Y SOS 0196 Bl Lene 1599 D Lane rmt eem SRDS PO 81 Lanel 160 0 Lane not pose SOSON laned PAg 0 Lane not pomes B ie Ov tena Peche ns s i Pergherd Svtishente 50150000 RASS AASE CAGE 0100 GAOZ 20060 2050 0008 DOR QodQ Pewphens 00190010 3919 0000 0090 0000 0040 2209 0000 1609 Pi ME Pepher 90100020 0000 0000 0000 0000 0000 DODD 0000 0000 50150030 SPOS O90 0000 0020 0000 8006 0000 0000 001200040 09000 0900 09000 0000 02313 8660 9A F SSSA 1E LLLLAA ST Component name PBL1 G PLL Configuration 0 3 System PLL T SvY5 PLL CFG bits 0 1 00 Platform freq system 00101 5 1 SYS_PLL_RAT bits 2 Memory Controller Comp MEM_PLL_CFG bits 8 5 OU Lower frequency refe MEM PLL RAT bis 10 00001 1 1 syne made eU Core Clusters PLL OOO CC1_PLL_CFG 00 Core cluster PLL 1 ou CC1 PLL RAT 01000 8 1 Async LE2 FLL CFG 00 Core cluster PLL 2 au LCS PLL RAT 1000 8 1 Async Lore Complexes PLL CO PLL SEL L1 FLL SEL Ce PLL SEL L3 PLL SEL SERDES PLL and Protoco El 0 m cm L O00 CET PLL 1 O00 CC1 PLL 1 O00 CET PLL 1 O00 CC1 PLL 1 c El E Z freescale CHER 10 Freescale the Freescale logo AltiVec C 5
13. Platform in a Package QorlQ Qonverge ngine Ready Play SafeAssure the SafeAssure logo Tower TurboLink Vybrid an Flexis L MagniV MXC Platform in a Package QorlQ Q QUICC Engine Ready Play SafeA he SafeA SMARTMOS T TurboLink Vybrid and i Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc a E E oon ee i Pre ws 4 wh e a Y ie i Tote te ul Poe perew a dd 1 a nad Ad Paar aiaia Wwe ref Ye a ote wr ove Ua ttt yee t pa Te iu z M S aa m SE Project Paned E amp 0 42T44f754 Loyan 44 00000000 Documentation 48 000800006 2 eran gp 8 amp 4 CCB Ciock FLL Betis settings fer 4c 00000000 D BOOTROMI Power s SB Clook SYSCLE Ratio 0120001200 il Procemobyet Setngsami 54100000000 IJ Precenortopert SIGNALS e 52 00 58 11000006 Paapua 5e 00000000 iu Generated Code d D BOOTROML Beet Config WY escono 8 IPM 0 90111072090 aureas 64 90000000 e i rfg sys pti 0 3 68100002010 Qy Processoctipert pe m p Coefgurnbons C um Stern Use PUN Comtiguration F o det i Opereting System i cig sys pii ti cec 4 43000000 E Precenun tt ofg_eye_pli i 650 f f1702000 EAR Tener cf Sci 702980 Embedde
14. Use BOOTROM tool to review amp change settings Details e Change CCB and core clocking 600 900 MHz e I O port configuration required interfaces PCle SRIO and eTSEC boot location set to boot from SD MMC card Step 3 Observe Power on Reset overview details Generated overview report txt HTML e Step 4 Use BOOTROM tool to prepare configuration data file for boot Image processing e Generated configuration file dat support of booting from on chip ROM e g eSDHC or eSPl base data file for boot image processing using external booting utility application Step 5 Usage of configuration data file with external booting utility appl ication using boot_format this application is a part of BSP release N 9 9 TM NR p re esca e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HR F IN Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and i Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners
15. Window Help imo i m OG i ge ia E 8 gt s rem Ta Project Panel Zi H T amp H X Component Inspector 23 H S 2020rdb cored Properties Import ES p4080 Documentation neme Value Details E Generated Cade Component name DDR mcl ddrCtrl 1 cfg 2 Device DDR Controller 1 DDR Controller 1 E ddrCtrl z cfg Memory type DDR 3 Warning DDR3 must use 4 beat burs c InitbdrRegisters 1 c DDR Data Rate 1333 MHz DDR Bus Clock 667 MHz c InitbdrRegisters 2 c Type of DIMM Unbuffered DIMMs le pano v2 Dds ddr c Bus made 64 bit bus Warning DDR3 must use 4 beat burs PBLI pbl m SDRAM Control Confiquratic Sources Control Configuration 1 gs mr Il SDRAM self refresh durir Enabled Gl Canfi Mew ECC Error Checking anc Disabled F P Open Dynamic power manager Disabled gt Oper Open With p Beat burst mode amp beat burst Warning DORS must use 4 beat burs E E cpus Timing mode 1T Timing Fs 4p 5 Copy Ctrl C I O Driver Impedance Full Strength TE Embel E Pa trl Concurent auto prechar Enabled ig PI 3 Delete Delete i E D Miei 5 Le InitDdrRegisters_t c e main c dp Rename F2 ii ee gg Import UBHHEHHHSHHSHEHSSHHSSSDBHSSESSSESSSSSSSHSSSESSSHZSH s Components Libra AE t SorExpert DDR Tool memory initialization gy Export BSHSHHSSHHHSSHHHSHSHHHHHSHHHHSHHSHHSSSSHSSSSHESHH Refresh F5 Oller 1 Registers Component Shaw in Remake Systems view
16. 037 Desenphae for the current value P1101 POs 101 Sorbus tere 0 SHO 1 hx gt Series lana 1 SOME eT 5 C2 Gxt gt SerDes lave 2 SOME eTSEC3 OL gt SesDes lene 3 061101 POe 1 0D SesDes lene SAID 1 10 gt SesDes Une 1 SOE STECH pd gt SerDar lana SOME eTSECS 31 gt SarDwn lane 3 t General Purpose POR Configur t Engineering Use POR Configuri 4 Pin Multiplexing Configuration 4 eTSECI Configuration cfg tsec reduce cfg tsecl prtcl 0 1 4 eTSEC2 Confiquration ia Independent Interface MIT TSEC Configuration Serial Gigabit MI SGMII E Kd IE in andani wi 5 unie aisi Fi ObOl eTSEC in MI c cfg sgmiiz Serial Gigabit MI SGMIT PL 1 Serial Gigabit MIL 3 cfg tsec reduce MM MDC Serial Gi duced G i ga Reviewi ng ie pds e A C2 TXD0 TSEC2_TXD7 cfg sgmii2 ObO eTSEC in 5j a Reduced J en Bit Interface RTBI Blac Configuration TSEC3 ration Serial Gigabit MI m cfg Hm re in 5A CUES EC cfg sgmii3 Media Ifidependent Interface MI C 1588 ALARM OUT2 I i cfg tsec reduce Gigabij Media Independent Interface GMI MDC Miscellaneous Configuration on j Co pile uration cfg_tsec3_prtcl 0 1 LTen B t Interface TBI RT RTSO B UART_RTS1_B 4 Boot ROM Data Configuration PPS FI PPS PS TS Serial Gigabit MII e Po efe TM ar fr e est a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the
17. 4 gman qmani 318000 ranges 0 0 es00000 4 bman bman 31a000 compatible fsl p4080 elb OxF F420 0000 4 rio rapidio ffe0cO000 interrupts 25200 OxF F400 0000 E a Ibe localbus ffe124000 address cells 2 OxF F3FF FFFF E a pci pcie amp fFe200000 Bsire ceils 1 OxF F000 0000 peil pci OxF EFFF FFFF A BG PORTRE LAUD Ibe localbus ffe124000 Ha pci2 pcie fFe202000 OxF E800 0000 4 fsl dpaa 3 xF E7FF FFFF v OxF OL eFs000 Device tree Include tree lt gt per 0100 7FFF REX ULL L p OxF 0000 0000 3 DT1HWDeviceTree dts 23 H OxEFFFFFFFF 1812 DE zs OxC 6000 0000 1813 OxC 5FFF FFFF lbc localbusBffeiz4000 Oxc 4000 0000 reg Oxf Oxfeiz24000 0 Ox1000 OxC SFFF FFFF ranges lt 0 0 Oxf Oxes8000000 Ox8000000 3 O Oxf OxffdfOOO00 Oxso000 xC 2000 0000 compatible fsl p4080 elbc fsl elbc simple bus OxC 1FFF FFFF interrupts lt 25 2 0 0 pci pcie fFeZ200000 FUR we E 3 OxC 0000 0000 address cells lt 2 gt lt gt SH Loe oe TM Cu f Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC e re esca e 26 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HR zk Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engi
18. 77 W000 44 Pm LEO E UART SOUT FREAD values for POR configuration signals iiS bot Confayoratwin and generates overview report tt nt cfg rem ioc j gt ELI Locs iun GPCM 1S be A Pin TSEC TIADIEMS TSEC TX ER including POR value required for ruri rig cpu boot onl PU showed te boot idetewt fine LAI each POR configuration pin device EE t OP desde bet ln Pow LASG specific ce oo e Helps in building a configuration file m s to be used in a boot image creation imt s process boot format for various ipata memory interfaces Rn C 5 TM 7 Pw P d fr e es C a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 59 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet E BH X iR Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and j i A Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc BOOTROM Configuration tool e Power on Reset POR configuration signal value binary value obo represents a signa
19. 99e2 a c If sLeUbuntu 32bit mnt hgfs DebianShare QorIQSDK 02 03 00B images boot p4080ds R RRRSS 0x16 Ir of Z freescale sz E ants vn src otto vanes teareisttscone oruere ts tes rk Tok omues Em KA Ge ee qu Ge ee E nM freescale BOOTROM Configuration Lab 3 Custom Hardware Config 1 Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor LI Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are b trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc P Cormgonemt inagector Base Asvanced ixper ie LI Overview n wre vaut ant De BOOTROM BOOTROAM Powe On Reset Confugut ation PLL Configuration s COB Oock SYSOK Ration 670 000 Mee c g rs ph 1 2 HD 41 Pore LALO 21 e Helps in Power on Reset POR oe EE nn eeu ipti for the rreri vakse OOTD 4 1 000 44 device configuration by definition of Er E mm ssc ct ttg_corel_ph 2
20. A E E Configuratio Clean Selected File s E DER Build Selected Filets 18 PEL CFG OxFEOOS110 Ox47040000 1 BND3 p N Generate Processor Expert Cade Run s k em l xFEJOO0S8O000 Ox3aF Debug s Profile 45 ENDS k Tem em l xFEDDSO0DS Ox0040007F Compare With k Replace with CONFIG Properties Alt Enter em l OxFEQOSO80 xs 04242 0z CONF IG Jjsassembli em l xFEUQ0S80843 xe 0 04z 0z Make Targets CONFIG z Show In Windows Explorer xFEnBnancu Dx n Plo l 4 oie TM m fr e e S C a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 7 4 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet EL HR X iR Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and j A Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc DDR Step 5 Adapt CW Config File e Open the CW config file you want to adapt D Program Files Freescale CW PA v10 1 PA PA_Support Initialization_Files QorlQ P4 P4080DS init core0 tcl Replac
21. A fo gt Test DPAA Basic 1 Passed lt lt lt All tests passed successfully gt gt gt System is terminating Farewell Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 1 03 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc DPAA Hands on Output Analysis Output analysis e FManO Framel1 IPV4 Frame IP src 16 16 16 16 IP frame gt IP miss gt MAC match gt Enqueued FQID 45 0x2D Frame2 IPVA UDP Frame MAC dst 0a 7a 76 5b 67 e9 IP frame gt IP miss gt MAC match gt Enqueued FQID 46 0x2E Frame3 VLAN non IPV4 Frame non IP frame gt Enqueued FQID 32 0x20 Frame4 AHP non IPV4 Frame non IP frame gt Enqueued FQID 32 0x20 Frame2 IPVA TCP Frame MAC dst 0a 7a 76 5b 67 e9 IP frame gt IP miss gt MAC match gt Enqueued FQID 46 0x2E N PO 5 TM T Pe rees e Frees
22. BARCO N V CANOGA PERKINS CEAC INT L CES CREATIVE ELECTRONIC CHANGWON UNIV CISCO CISCO SYSTEMS CONTINOUS COMPUTING CRYPTO AG CYAN INC DIALOGIC INC DSPACE GMBH EDIXIA EMBEDDED SOLUTIONS EMCOSYS FUTURE ELECT INC GAMMA SP Z O O GE INTELLEGENT PLATFORMS LTD GIGAMON SYSTEMS GUODIAN NANJING AUTOMATION HEIDENHAIN GMBH IEP GMBH INTERFACE CONCEPT IPWIRELESS ISKRATEL ELECTRONICS ITEC CONSULTING AS JUNIPER NETWORKS JUNIPER NETWORKS INDIA KDS K N ILOU Gero Contigdration Suite A R COMPUTER SYSTEMS MIRANDA TECHNOLOGIES MOTOROLA MOBILITY INC MYSTICAL ROSE TECHNOLOGIES NARI NETWORKS NKB VS PURESILICON INC REDCOM LABORATORIES INC ROHDE amp SCHWARZ ROHDESCHWARZ GMBHCO KG ROSS VIDEO SASET CHENGDU SERVERGY SERVERGY INC SIMENA SOUTHERN FEDERAL UNIVERSITY SUSQUEHANNA INTERNATIONAL GROUP LLP TECHNOLOGY OF INFINITY THERMO FISHER SCIENTIFIC WB eae S A WINDRIVER WT MICROELECTRONICS CO ZODIAC N Z freescale Gro i C Ware gy Efficient Solutions logo Kinetis mobileG T PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HR F zk 42 Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssur e the SafeAssur elogo SMARTMOS Tower TurboLink Vybrid and i Xtrinsic are trademarks of Freescale Semiconductor Inc All other
23. CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Pre boot Loader standard component interface e Chip version and errata information Device PBL PBL Chip version P4080 v2 0 Erratum information 1 re Description Settings of RCW fields TUM PLL Configuration a SerDes PLL and Protocol Configurats Po Misc PLL Related Configuration Boot Configuration Clocking Configuration Memory and High Speed 1 0 Configur OOOO ed oT OOOO e Input Output format selection General Purpose Information MEER d _ fee E Pin Multiplexing Configuration Possibility to add PBI data Group A Pin Configuration Group B Pin Configuration e Possibility to import RCW PBL Data Offset settings PBI Data Output Format Input Format Input Data X ig Pe PO 5 TM Tr o r Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWar
24. Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC i 6 4 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HH E ZR Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and i Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc oot 1 n J Properties Mame Value Device BOOTROM 4 Power On Reset Configuration 4 PLL Configuration 4 CCB Clock SYSCLK Ratio 6 1 cfg sys pll 0 2 b010 6 4 DDR Complex DDRCLK Ratio 4 1 cfg_ddr_pll 0 2 ObO01 4 e500 Core CCB Clock Ratio Corel cfg core pll 0 2 b011 cfg corel pll 0 2 b011 3 5 Device Status 4 SerDes Configuration 4 SerDes Reference Clock cfg srds refclk 4 SerDes PLL Time out cfg srds pll toe 4 VO Port Selection cfg io ports 0 3 4 Boot Configuration 4 Boot ROM Location cfg rom loc 0 3 4 Boot Sequencer Configuration cfg boot seq 0 1 4 CPU Boot Configuration cfg cpu boot cfg cpul boot t High Speed I O Configurati 5 General Purpose POR b Engineering Use POR 4 Pin Multiplexing Configuration 4 eTSECI Configuration cfg tsec reduce cfg tsecl prtcl 0 1 Qb1111 Local
25. Gbps Enable Loopback and Heset on Init Enable Rx port Error FQld 20 Default FQld 20 Enable Tx port Error FQla 40 Default FQld o Add and use BufferPool0 Number of buffers 100 Buffer pool Id 0 Buffer Size 51200 7 FMan 1 Tx configuration 1 Channel for FM1 Port 1 1 Add a FQIDs range FQR2 used to transmit frames on FM1 and configure FQId 201 and count 1 2 Add FM1 porti channel 3 Link FQIDs2 to FM1 port1 channel WQO c1 A O N 4 N Z freescale CHER DPAA Hands on Generated Code Usage C CodeWarrior Projects 25 e HW configuration EP 5 DpaaQcsUseCases OCS Dbg P4080 v2 0 pads Loopback on FM ports used in Indudes El Gp NetCommsw e SW configuration E accport icf SKB CodeWarrior Lin Y libs CodeWarrior PA 10 1 2 El gp user NetCommSw v4 5 E e r inc Usecase running E a ketas B El Ep common Import DpaaQcsUseCases El x controller NetCommSw and UserEnv for El p DPAA P4080 Gq common inc Replace generated code files Miss ra t d yl luser envibare UseCases comm gan 4 AK pc cormg RD leader Fil on controller DPAA QCS ER pases fmc config c Hg dpc_defaults h 3KB CHeader File v ih dpc_structh 8KB C Header File v dpc str uct h laj fmc config c 6KB C Source File i fmc_config h 1KB C Header File v Clean amp build project Le fmc exec c 26 KB C Source File y Runon tar i fmc h 7KB C Header File v un on ta get
26. Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc freescale Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Pre boot Loader RCW Configuration See Ie 7 ze Vs Progect Pare t2 2 9 e mt Rm Hk Y sos e 1798 ACS TCL 123 133 ROG _MATIO_BL 130 130 e 2 pus SNS RATIO B2 19415 000 1 1 sos OW m2 M7 0 Dide by 1aff ol E 3 foCc Pa v2 D g 5 SADERATID B3 348 150 008 aft 89 mais Unpenere GOS DIv 83 i51 0 Qvide by 10 PR LPR QIQ SaM PD m 152 141 SRDS LPD 92 162 165 SRDS LPO 83 170 173 Qw Berk L A 0x San Ouen paties Wi Y Sosopi lanea 1M Lae tart pen Y OELLO lanen 153 0 ure rot pewer Y Rt LPO Bi Lle 1154
27. Latency ECL 9 clocks Quad Ranked DIMM tRP tRCD ECC Enabled Presets Save S Save Open Presets Folder configuration C Load Elpida DDR3 PC10600 26B 9 7 7 20 as a reusable Select 1st DDR Controller al f OresSe amp e Po ejfe z freescale CHER Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc DR Auto configuration mode e Po Z freescale CHER Nizard Basic Configuration ode Presets New QorlQ Configuration Project ESEESE DDR Configuration Configured device P5020 Configure 1st DDR Controller Configuration mode Auto configuration O Import from memory file DDR Controller DRAM Settings Type DDR3 DRAM Configuration 1Gb 256Mb x4 Data Rate 1333 MT s Speed Rating 1333 MT s Ranks 1 Registered DIM
28. SafeAssure logo SMARTMOS Tower TurboLink Vybrid and i Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc freescale Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc E Summary You should now Be familiar with the QorlQ Configuration Suite basics v1 supports PBL amp DDR configuration available now v2 adds Device Tree and DPAA Graphing tools preview in July Solution Strategy Extensible suite of tools to solve these problems Consolidate into a common tools framework Processor Expert Provide new device support aligned with silicon roadmap Add more configuration tools over time Allow customers to add their own configuration tools to extend
29. amp Tm Off Airfast BeeKit BeeStack CoreNet t HR X iR Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and T Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc import XMLs Feature Imports DPAA configuration from Freescale extensions to NetPDL xml based files DPAA objects Connections between them DPAA objects configuration Automatic update of the objects and links after import is done The xml files can be generated using the QCS solution or can be created by hand DPC Configuration PCD Configuration this is the file that has to be imported eee lz xml wersion 1 0 encoding 2 utr a amp 2 dpc xmlns xi 2 http immr w3 o0rg 7001 xInclude zxi include href config guest xml zxi include hret ped guest 0 xml zbman name pman master gt lt poartals gt lt hbmportal id O irg false gt lt portals gt lt liodn gt 20 lt liodn gt lt irngq gt Ealse lt irqg gt lt rman lt hutferpool name bpool 1 gt zxhuffers 1U0 c buffers xsize 512 00c size z hufferpool o oe Z freescale CHER 29 znetpnccd zxdistrributrion name bistributionl lt Quevue count 2 1 bhase On1 gt action type classification name Classificationl
30. amp beat burst 1T Timing Full Strength Enabled ria Use differential DoS signals Basic Advanced Expert ih E Details EAS DDR Controller 1 Warning DDR3 must use 4 beat burs DDR Bus Clock 667 MHz il Warning DDR3 must use 4 beat burs Warning DDR3 must use 4 beat burs DDR 5DRAM CF 7 provides more control configuration For the DDR controller Assert ODT to internal ICs only durin Don t use nao Disabled Disabled Enabled yes Clock will be launched 7 8 applied cycl Enabled 64 clocks 256 clocks 96 ns 383 8 ns Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 7 3 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc DDR Step 4 Generate DDR Config File Processor Expert p4080 Generated_Code ddrCtrl_1 cfg CodeWarrior Development Studio File Edit Navigate Search Project Run Profiler Processor Expert
31. anm 6oocTDeerme m I is to opal Coen e mec Cat arbeto 8 TIER ELT 21111 1 Nee pat Pemer l atic Temm Tree Cre bo ferri PS nes wen certae 0 000 Fewer mus ge 4 Um P Beret 7 TJA t one oor T m ig Urs msssst pul 2 reversion 9 Lat udine ee ow oai uique muet erm foe e gt aem Car gos ALB Qon t bopt dro r 9 mes tab nepa z Mtt z m M iium ran m 0 cw n Posee sap i man mre roger time eer V nyer Eppe A DNO mama d oom h an en J ow pem vere WN una rae o noe v oe Tht Garter decies efoovamon Met Te m y e y ame i dde Ric gt ib Gee gt ce ower MEI EC gt LE E qe Poet dpt 7 ere her asters Se Se C led MEE Pte ncm ho mom soc Pli 4 9 a C manor wb Od gt x Sad Ld ome 3 v 1p UNIUS L gt fr eslims cong eturds m Feet gn t pordo han tuso wna Phe oum OI FN ote Vue em T 9 Se e 9 d bearna wrat Or deterd a ardeo bea i t wwe ort GOMO gun orl dun cox amp x wo error who cpeodprtece oo freescale TRER i he Ade d da ae n a go se Bunt hoe oor We MON eme m4 i hoffe qoid iae teehee peng tent hehe oot hart hfn m pm muitaj etes Be ae te ee pte he o fe scm enste Peter tm Cm MET mrn 1 earra MIL Ier yee O irs Seve gt nest ieee gt lw OU etd eed mist en 7 16cm et ate O afri thereon brett tet te verte tee m s sere eeu oaa o het meos ead wr F
32. clock 600 MHz DDR clock 650MHz clock 1 3GHz Step 3 Use PBL tool to generate new RCW and compare outcomes with rcw 0x10 5g rev2 high bin txt Step 4 Change Serdes Config to support 8 Gbe compare result with rcw 0x16 all rev2 high bin ogo Kinetis mobileGT PEG PowerQUICC i 2 freescale Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWar peal ciate een die ergy Efficient Solution 46 A ANAKA UAn Qr Crna Sara iPad phony and Vo nia arks of Freescale n onductor s Reg U Tm Off ir a st Be idi BeeStack CoreNet Flexis Layerscape MagniV MXC duis a Package Qo bd s UOCE ngine ene eady Pla i p feAss Fun Sa id 090 Vise alas Tower Tu in nk m rid and t HR F IN Xtrinsic are trademarks of Freescale Sem Bod ctor Inc All other ctor service names are the property o ofthe espective 2013F re cale Semiconductor Inc go Pre Boot Loader Step 1 Create a New Project New Gor ll Confirewration Prorect m E Devices Select the Sec you mould Mike to use Creete s Geri Configure et n Propet Deme tere ee fe he rm ree Soc bo be used type Faites best 2 2 TUMULI tudm hat Same Betas Magie Tamad Pract Hah Puer Proc ia d JO Powe Arrthtactre Propart Wendie ap Oper Pwi Crit Oper Fi rt Pidtette Prot et fono Cade Prit mane Phir Fotis Tof Hapi tm Pie tres Tanp eee G Gees Othe Cheah wives Lee Deters Te bd Til Otu i
33. instant access to configuration settings e by displaying relevant summary of current configuration by immediate code generation at request in any stage of your work ogo Kinetis mobileGT PEG PowerQUICC 2 freescale Lisa the Freescale logo Pelr C 5 CodeTEST CodeWar ii iis ata Sae as aa ergy Efficient Solution 105 Pro r Expr ot Cor Sr Sympa and Vora arks of Fre secon onductor s c Reg US Tm Oft Airiast Be ii eStack CoreNet Flexis Layers cape die ad 9 nc Pla a Package Qo bd QUOC Enge Ra eady Pla i See Fun ree 090 Vise eae te r Tu in ms p and t HR F IN Xtrinsic are tradem cale Sem Bod ctor Inc All other ctor service names are the property o ofthe espective 2013F re cale Semiconductor Inc go el gt freescale CHER
34. janati ethernets aniti artberbetj etbhernet4 etherners ehy ramii O ibhv Learet S nets sanecs roii Qj v 5 Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Interrupts tree The Interrupts tree represents the hierarchy and routing of interrupts in the platform hardware The left side displays the actual representation of the Interrupt tree starting from the root interrupt controller The right side displays the interrupts sources for the selected device tree node Devre Tree Properties Interrupts nterrupt tree e Properties Qmarr portakpcnfF4 204000 interructs gnar port almo I2 Interrupt number Ykerruct level cense qmarcport simos Ir 00000 za Low to high qmareport skposft42 10000 l3 Low bo Hayh gqnacc port al qox f 4214008 25
35. 00 M H Z DRAM LAT 230 231 ObO1 8 8 8 9 9 9 10 10 10 11 11 DDR RATE 232 O60 Refer to hardware specification o oe oe TM ar r e esc a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 5 9 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HH E ZR Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and i i Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Pre boot Loader Step 7 Generate Upgraded RCW TS Project Panel 3 E tS panends n lL Documentation Generated Cade Sources S E Configurat F P4nan Operating Cpus m E48 soc Sh Embedded dij por_ 3 28 PL Sa amp nalvsispoir E E Es 4 Generate Processor Expert Code New Open Open With Copy Delete Move Rename Import Export Refresh Show in Remote Systems view Clean Selected File s Build Selected File s Ege 2 PBL1 pbl 2 oocoooda 00000010 n 00000020 m 00000030 00000040 Fz FS 4455 455 010E O
36. 00 matches Case senative x seriall eseria a pon EP l 2 38 seris Oconee Ja a vo wea v ir Select zero one of more options O 35 senab sorlakpt i cso S Low devte type seris voco iii venait 10600 4 SA WORD T We device type pera Wording set p Po efe freescale CHER define working set 21 Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Device Tree Bindings e Each node has a binding representing its schema It describes what properties are optional or required and what each means SoS E gt rep 2 3 a 1 9 a eS as uc Oc BE IF Device tree paries Interrupts EA Contents Search E Related Topics ET Bookmarks Device Tree Nodes DT dma0 E Index 07 corenet cf 18000
37. 040 Cond P2020 2041 Low End Quad Ce Cummurecabons Processars wm Data P atn P2041 Gonna P3041 Quad Core Communications Processors with Data Fam P4040 Gand P4040 Quad Core Commumcationz Processors with Data Pam Featured Documentation GORIGOCSPROCENUG Processor Expert Users Guide QORIOCSGETST RTEDUG Configuradon Sulle Users Guide QORIDCSINSTALLUG Instarahion Users Guide Current Updates and Reeases OomoCemigSuite_3 5 4_Gaikeo Contouahbon Sule mstater tor Eclipse J 5 Galileo OortQConfigSute_2 6 s_Heliog Configuration Sate Installer tor Eclipse 3 6 x tHeling Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 4 1 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Supporting the Most Sophisticated Customers FUIURE ELECTRONICS CO LTD ADVA OPTICAL NETWORK AEONIUM SERVICES LTD ALCATEL LUCENT ALCATEL LUCENT AG ALVARION ARROW ELECTRONICS ASB AVNET ELECTRONICS
38. 10 boot format on Words qa I OOL POOL 090 Apr 7 2010 Contig Sram dar The utility shows how to use it when typing boot_format Usage boot format config file image sd dev o out config spi spiimage config file includes boot signature and config words image the U Boot image for booting from eSDHC eSPI dev SDCard s device node e g dev sdb dev mmcb1k0 Spiimage boot image for SPI mode out config modified config file for SD mode e41 2 7 xm BOOTROM tool generated config file can be used together with U 9 Boot image and put on an SD MMC card using command line calatetezes e g for dev mmcblk0 boot format BOOTROMI Boot Contig dat u boot brin sd dev mmcblLlkO Rc oe TM m freescale Freescale the Freescale logo pn C 5 CodeTEST CodeWarrior ColdFire ColdFire C War iis ie ue ent Solutions logo Kinetis mobileGT PEG PowerQUICC 69 Processor Expert Qor orlQ Qorivva StarCore Symphony and Vort Qaa re tradema rks of Freescale n RC aes Off Airfa st BeeKit BeeStack CoreNet t HR iR Flexis Layerscape MagriV MXC deeb in a Package QorlQ Qon a e QUICC En idi iie eady Pla p fe ne id SafeAssure logo Pide To ower ee p d i Ai rida nd 1 Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service na re the property o ofthe espective owners 2013 Freescale Semiconduc freescale DDR Configuratio Lab 4 Changing s 29 Freescale t
39. 100 1054 0000 0000 0000 TELE 1E 0000 CCCC 4046 4000 scac 2000 FESO OOOO 6100 OOOO OOOO OOOL oodd OOOO 008E B000 0000 0000 0000 0000 ddd OOOO OOOO OOOO 061s s 040 Dees Bese t Generating the PBL provides the same RCW as the high speed RCW seen in the SDK i fsl Ubuntu 32bit mnt hgfs DebianShare QorlQSDK_02 03 00B images boot p4080ds R_PPSXN_0x10 amp x File Edit View Terminal Help fsleUbuntu 32bit mnt hgfs DebianShare QorIQSDK 02 03 O00B images boot p4080ds R PPSXN Ox10 ls rcw 0x10 13g rev2 low bin hv lp lnx dtb hv 2p lnx lwe dtb hv 4p lnx lnx lwe lwe dtb rcw 0x18 13g rev2 high bin rew 0x10 13g rev2 high bin txt rcw 0x10 13g rev2 low bin txt rcw 0x10 13g sbenO rev2 low bin rcw 0x10 13g sben rev2 low bin txt rcw 0x10 5g rev2 low bin rcw 0x10 13g sbenl rev2 low bin fsl Ubuntu 32bit mnt hgfs DebianShare QorIQSDK 02 03 ayuden ALLE PPSXN _0x10 xxd rew 0x10 5g rev2 high bin 0000000 aa55 aa55 010e 0100 105a 0000 0000 0000 0000010 lele 18le 0000 cccc 4046 4000 3c3c 2000 0000020 fe80 0000 6100 0000 0000 0000 0000 0000 0000030 0000 0000 008b 6000 0000 0000 0000 0000 0000040 0000 0000 0000 0000 0813 8040 d223 b25c fsleUbuntu 32bit mnt hgfs DebianShare QorIQSDK 02 03 00B images boot p4080ds R PPSXN 0x10 Z freescale CHER o4 rcw 0x18 13g sbenl rev2 low bin txt rcw 0x10 5g rev2 high bin rcw 0x10 5g rev2 high bin txt rcw 0x10 5g rev2 low bin txt Freesca
40. 2 me 717 Search Ctrl Alt H a p 4 cpe l3 g e This section describes information about the selected node s properties l hana 3 Refresh F5 Other operations 4 jommu ig Expand x z mpic pic j Collapse Name Value m Import device tree 4 msiQ ms address cells 3 X msil ms Device tree settings size cells 1 A 2 Include device msi msi 41a device type soc tr ee 3 4 guts global utilities e0000 comnatibie R 4 pins global utilities e0e00 0 f fe0DOD00 1000000 4 clockgen global utilities e1000 n Val idate device 0 04 repm global utilities e2000 peg SEER Rae tree 4 sfp sfp es000 4 serdes serdes ea000 _ Search in device 4 dmad dma 100300 fle 4 dmal dma 101300 n tree EE 4 Device tree Include tree ii gt P Se Ireescaie op a E Re S PA A B Bei Co t HR X EIN Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and J Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc pup PowerPC esoomcgo pul FowerPCeSoDmcept 12 pt Cade que PowerPC eScO0mcOQo 4 coud PowerPC eSa a cout PowerPC nS00mci pu5 PowerPC eS00mogs chub PowerPC csoOmchs U cpu Pona PCene test des
41. 23 E E testi E E Documentation B e Generated Code BI ddrCtrl 1 cfo B ddrCtrl 2 cfg 8 InitDdrRegisters 1 c be 8 InitDdrRegisters 2 c A p4080 v2 Ods ddr c ias PBL 1 phl m E Sources Ry ProcessorExpert pe add Configurations f pao80 v2 0 Cnf a Operating System ee amp Processors mH S0c P4080_v2_0 i Ehe Components d PBL1 PEL z i DDR mci DbR Ai DDR mcz DDR E SerDes PLL and Protocol Configuration SerDes Reference Clocks SD REF CLK1 MHz SD REF CLK2 MHz SD REF CLK3 MHz 5 SRDS EN 178 SRDS PRTCL 128 133 SRDS RATIO B1 136 138 SerDes PLL 1 Clock SRDS DIV B1 139 143 SRDS DIV Bi Lanes A B 139 SRDS DIV Bi Lanes C D 140 SRDS DIV B1 LanesE F 141 SRDS DIV B1 LanesG H 142 SRDS DIV Bi LanesI 143 SRDS RATIO B2 144 146 SerDes PLL 2 Clock SRDS DIV B2 147 SRD5 RATIO B3 148 150 Baki Bak2 Baka la S c p E r c wu r is a sicipiaT s c p Debug 5 2 5G pe oes NEM NNNM ees EE ea 2x SGMII pem i FM2 dTSEC 3 4 1 5 2 5G 2x SGMII Debug FM dTSEC 3 4 1 5 2 5G 4x SGMII Debug s Reserved 1 FM2 dTSEC 1 4 1 5 2 5G 4x SGMII Debug md Reserved 1 FM2 dTSEC 1 4 1 5 2 5G RIOD Debug XAu xa Bits 128 133 For additional information see description of the SRDS_PRTCL field in device documentation This item Em SRDS PRTCL5 SRDS5 PRTCLO bits in the RCWSR5 regis
42. 4 1 Pins LBCTL LALE LGPL2 LOE B L R m cfg_io_ports 0 3 pM eTSEC3 x1 gt SerDes lane 3 cfg_corel_pll 0 2 ObOOO 4 1 Pins LWEO B UART SOUTI READ b Device Status 4 SerDes Configuration 4 SerDes Reference Clock cfg srds refclk 4 SerDes PLL Time out Enable 4 CCB Clock SYSCLK Ratio cfg sys pll 0 2 4 DDR Complex DDRCLK Ratio hns TSECL_ TAD 3 1 TSEC2 TX ER fg io pom p d Changing l O Port Selection Ob cfq srds pll toe Disable P 4 ioe to have PCle cfg io ports 0 3 0b1111 PCle 1 SRIO and ra i 4 Boot ROM Location mei O AOGAS Gs SOL RAIS Gope SOME TSEC 64 1 25 Gepa 1 SSME eTSECI cfg rom loc 0 3 b1111 Local bus GPCM It a 2S Gp SAUDE Is 25 Giga SGMETSEC Ht 025 Gepa L SGME eT SECI C Boot Sequencer Configuration 1 Hai mr ML Re cfg boot seq 0 1 0bll Boot sequencer disabled Pins LGPL3 LFWP B LGPL5j KI l l eFSEC2 bd 1 25 Gapi 11 SME ATSECI 4 CPU Boot Configuration 1 Port cig sqm must alo be loge D n adilibum for ETEC te cpeune ia SOME nude cfg cpu boot Obl CPU allowed to boot default Pins LA27 2 Wort cig gm must she be logic 0 n additum tor ISEC te cperete n SOME mode cfg cpul boot Obl CPU allowed to boot default Pins LA16 MM OMM t High Speed I O Configuration SesDes lO Por Selection power on reset comfiguumtion tgnalis cy ports
43. 58 0000 0000 0000 LI LI LX 0000010 1818 5218 0000 ccce 4046 4000 3c3c 2000 R BF cc 0000020 fe80 0000 6100 0000 0000 0000 0000 0000 a 0000040 0000 0000 0000 0000 0813 040 758b 7272 a Bue The content of the file to be imported is displayed e y 2 fr e esc a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 4 8 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and t HH E ZR Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Pre boot Loader Step 2b See Differences Highlighted Processor Expert 94000d O Generated Code PBL1ob odceWarttor Development Studi Pie Edt Nevigste Search Protect Run Profle Processor Expert Window Help Ci x al 29 0 4 Q Tr uo je Pome Penal URN AA amp 8 D gt ccomporent inspector Bask Advaned Ewet A 7 CO 9 u paid 0 Procertw noort v Documentsiion mim gt Generated Co
44. Ban SRDS RATIO BS 148 150 DbODD 10 1 SerDes PLL 3 Clock 1 250 GHz SRDS DIV BS 151 ObO Divide by 1 off OR Bank 3 PLL E SRDS LPD B1 152 151 Set SRDS LPD B1 Lane A 152 O60 Lane not powered do SRDS LPO B1 LaneB 153 Ob0 Lane not powered down S RDS RATIO B2 to 10 1 PBLi pbl 23 DOOOODOOUO A455 455 010E O100 1054 0000 ddid iEIE 181E OOOO ce 5840 OOOO 3C3C 2000 00000020 FESO 0000 6100 0000 occo 0000 oooo ooon SGMII requires 1 250 GHz OOOOOOSO OOOO OOOO agSB B000 OOOO DOOO 00000040 0000 0000 ODDO 0000 0813 8040 Bi63 SSE2 on Bank2 and Bank3 e Po p r e e S a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 56 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HR X iR Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and j i A Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc PBL Step 9 Generate Pre boot Loader and Compare with the RCW Provided in the SDK TS Project Panel 3 Ee E W
45. Cor AEE etra demarks of Fre secon on a coe i Flexi siam ape Magi MXC Palm ea vere QUICC Erg Fen Sable birds dip Vise eae te er TurboLink Vybridan and t HR X zk Xtrinsic are tradem cale Semiconductor Inc All other ctor service nam e the property of their respective owners 2013 Freescale Semiconductor Inc ogo Kinetis mobileGT PEG PowerQUICC at amp Tm Off Airfa st Be ue eStack CoreNet Configure the ethernet dst Entries 1 Link Pass through distribution to FQIDs1 2 Draw 2 links from ethernet dst classification to FQIDs1 3 Configure ethernet dst classification Entries to FQIDs1 1 Data 0a7a76000000 Mask FFFFFF000000 Queue base 0000002bE 2 Data 555555000000 Mask FFFFFF000000 Queue base 0000002F Channel 0x5 SW Portal 5 Pass hroug pes of TM 2 freescale dbase the Freescale logo a C 5 CodeTEST CodeWarrior ColdFire ColdFire C War EN eg Ele ent Solutions logo Kinetis mobileGT PEG PowerQUICC 100 Proc Ee ot Qi a StarCor of mphony an nd VoriiQa a re trademarks of Fre ccu s ids ced iesu m Of Aifast Be diu eStack CoreNet ESER dis siam ape Magi MXC Pato dior pe e e de sei irm ned Heo MARTON TO er TurboLink Vybridand Xtri radem cale Sem od Inc All other ervi names are the property o of their respective s 2013 Freescale Semiconductor Inc Configure the FMan Port 6 FMan 1 Port 1 configuration 1 Port name fmOport01 MAC address 00 04 9f 00 02 66 Interface RGMII Speed 1
46. GE soc Panen v2 n lL Embedded Components Address Information y PEL1 PBL Beginning memory address FeQoso000 Uh DDR mci DDR L 2 DDR mc2 DDR DOR Controller memory address e005000 Use default Ej SadmalysispointsManager apconfig E T __ B p4080 cored Ce CFG H Debug Settings gt Hardware Debug core H E LCF Ld v 8s ERE Library x E T 3 zj Categories Component Component B Configuration Tools GP DOR Peripheral Ini i d PBL Peripheral Ini C d f Ly TM I i 25 es p r e e S fi a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 7 2 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HR X iR Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and j b Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc DDR Step 3 Review Decoded Configurations Processor Expert p4080 core0 Source main c CodeWarrior Development Studio File Edit Source Refactor Navigate Search Project
47. Low bo High anarcoortalqoff42 18000 236 Low bo High j qmance portakpost 4210000 za Properties qmaceportaliposff4220000 Aah Interrupts qarr portalpos ft 4224000 b Ics soc gr am emonpast en00000 adp Interrupt number ee evel sense merry Com olen iO f feN0SO0L 16 Active High memory contr oen pos fte 0wCfCc 3 cacle cortrolerigos eot DOCK coremek porc e ano crest SO sf heOZ00060 meee el4 1609 meedcicfFel4 800 Domain map mssbOon fi edA tao messager tO ed 00 Dev 0 sE e0100 2139 35 i vts re Parent interupts lt j Child interrupts Int 1 Int 2 Int 3 Int 40 rapidio Oxffe0cO000 INTA Disabled Disabled v Disabled xi v localbus Oxffe 124000 INTB SEWELEWN v Disabled Disabled v Disabled Y pcie Oxffe200000 INTC Disabled vi v Disabled v Disabled pcie OxFfe201000 INTO Disabled we Disabled AS eve L v pcie 0xffe202000 Dod pcie OxFF8000000 pcie OxfF8010000 pcie OxfF8020000 re 1 High to Low gt o oe eo o TM 7 nu m fre escale Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HR X iR 24 Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the
48. M Data Bus width 32 bits C Mirrored DIMM CASH Latency tCL 9 clocks C Quad Ranked DIMM tRP ERCD 35ns ECC Enabled Presets P Save Elpida DDR3 PC10600 2GB 9 7 7 20 usa opp c Samsung DDR3 PCI0600 2GB 9 9 9 24 lect 1st DDR c amsung select 1st DDR Ce ix DDR3 PC10600 2GB 9 9 9 24 Elixir DDR3 PC10600 2GB 9 9 9 24 Nanya DDR3 PC10600 2GB 9 9 9 24 Micron DDR3 PC10600 2GB 9 9 9 24 Load Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc 15 DDR Wizard Import Memory Dump Mode f Nen Qoid Conetnqurction Propet DDR Configuration Configured device P5020 Configure 1st DDR Controller Configuration mode O Auto configuration Import from memory file Import from memory dump va ri ous Inpu
49. Run Profiler Processor Expert Window Help E37 Rl E Ws Project Panel 5 5 ASB v7o SS Component Inspector 4 2020rdb cored cues aims i p4 80 Mame ith Documentation H Generated Code E Sources Device ES gs PracessorExpert pe Memory Cy pe EE Configurations DDR Data Rate 48 P4080 v2 0 Cnf Type of DIMM Component name gt Operating System Bus mode Gf Cpus E SDRAM Control Configuratic E 4 SOCiP40BD v2 D E Control Configuration 1 El Embedded Components SDRAM self refresh durir d PBLL PBL ECC Error Checking anc E DDR mci DDR Dynamic power manager E DDR mcz DDR Beat burst made SaAnalvsispointsManager apcanfig Timing mode ES p4080 core0 TO Driver Impedance B E CFG Concurent auto prechar G E Debug Settings E Control Configuration 2 H Hardware Debug care e z x onFiguration Z sd i M ODT Configuration gy Components Library 2 p g c F Number of posted refres Use quad ranked DIMM Categories Alphabetical Assistant CPUs Address Parity Register Control Word Component Component Corrupted data feature B Configuration Tools Use mirrored DIMMs DDR Peripheral Ini B Clock Control 9 PBL Peripheral Ini Clock adjust E 0 Calibration Normal Operation Short Normal Operation Full Cz freescale CHER Fre ee ee a a ie gt Sle Value DDR mci DDR Controller 1 DDR 3 1333 MHz Unbuffered DIMMs 64 bit bus Enabled Disabled Disabled
50. S LPD B1 152 151 SRD5 LPD B1 Lane 4 152 SRD3 LPD B1 Lahe B 153 mL SRDS PRICL 128 133 ISRDS PRTCL a Bic Dooz x z aria 512 56 2x SGMII FM2 dTSEC 3 4 C1 Debug 5 2 56 e x SGMII FM2 dTSEC 3 4 1 Debug fz 4x SGMII FMZ dTSEC 1 4 1 4x SGMII FM dTSEC 1 4 1 Debug 572 56 Debug 5j2 5a sRIO 1 Debug 5 2 56 3 1250 sRIC 1 3 125 Debug SRIO z 3 1256 sRIC 1 3 125 5 2 5G Debug Bank3 A B C D ALI FM 10SEC 4x SGMII FM2 dTSEC 1 4 5j2 5G ALI FM 10SEC SALI FM1 10SEC ALI FM1 10SEC SALI FMi l GEC Reserved 1 Reserved 1 MOLI FM 10SEC 4 x SaM FMidTSECU4 4 x SGMII FM1 dTSEC 1 4 SerDes Protocol Select Bits 126 133 For additional information see description of the SROS PRTCL Field in device documentation Dan rinbian Fae Fha an asabaal ede Rank 1 n r cD 6 73 1e0r i FH cDT Od 63 19507 TOT Mekhi 73 130 Bank AD ds SPAT freescale CHER 55 SRDS PRTCL 2 0x10 to 0x16 P4080DS slots as per user manual Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Free
51. SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Memory Map view Sy Memory Map 23 ENTIRE ADDRESS SPACE localbus ffe 124000 e Any hw device tree can be seen as seo OxF FFDE FFFF a representation of different Local s EN Access Windows LAW eee n Each LAW maps to a specified a target interface such as DDR DoF Form FFF Controller Localbus PCI Express oraso etc aon OxF F800 0000 e Each device tree node having reg merer and ranges properties defines a Bc memory range inside outside E ATIS Configuration Control and Status Qd xF FOOO 0000 Register CCS R Space area E id localbus ffe124000 The Memory Map view popS Up senose automatically when a device tree oe component is selected inside nas gman portals fF4200000 desr desr FO0o000000 OxC 6000 0000 omponent INSPeEClOFr VIEW OxC 7FFF FFFF OxC 6000 0000 OxC SFFF FFFF OxC 4000 0000 OxC 3FFF FFFF M pcil pcie tre201000 OxC 2000 0000 OxC 1FFF FFFF F p pciO pcie ttez00000 Le oe Ly TM P Nes e ae TTC me p p l eest a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 25 Processor Expert QorlQ Qorivva StarCore Symp
52. Solutions logo Kinetis mobileGT PEG PowerQUICC 3 2 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HR zk Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc QCS DPAA Component Features 3 my Component Inspector 5 e Instant display of relevant configurati Policy 1 LEG B e m on summary H for each DPAA element g 3E amp C49 T ead e c freescale CHER an miss Distribution FMan service Queue range 39 39 Extracted protocols ip4 Extracted Fields None Combined Fields Mane an miss FOIDs 1 1 200 bh d Zoom 100 Selection 323 35 Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qo
53. U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Conclusions he sequence of steps for modifying hardware device trees has been presented The benefits of using Hardware Device Tree tool are First device tree editor including two modes for editing GUI and text Easy to understand device trees structure due to the visual representation eupports device tree bindings and validation Allows users to add their own device trees Provides features for all the main aspects of hardware device trees It is an editor and a validation tool for creating valid and well formed device trees Works on Linux and Windows hosts 4 N LGP TM l l l l x l Be p re esti a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC t HR F IN 84 Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and P Xtrinsic are trademarks of Freescale Semiconductor Inc All othe
54. amp P4080 v2 D dts 53 ELI Midi HWDeviceTree Prop rties 96 O Workspace Setected resources J gt Q2 okspec ESIC Q3 c H 13 T Teu vals 3 cpus Working set amp device tree 98 address cells lt 0xi IE 7 ibi Mame cpud PowerPC 40806 99 size cells 0x0 i Parent cpus cpus gP ti 3 100 z ij Properties T orm cpu0 PowerPC 40800 E Property ini cpuD PowerPC 408080 iv ers L20 l2 cache Name device type 102 HevIUB Lgpe sees Eo Wy coat nce c me WI cpul PowerPC 408061 Value cpu 103 reg 0x0 a Prablens Console Wo Progress 0 Sew i E cpu2 PowerPC 4080 2 Property 104 next level cache lt L2Z 0 tpus 12 matches m workspace B a J E cpu3 PowerPC 4080 3 Name reg 105 gt ee m c Oausvertatin memory Value lt 0x0 gt 10 6 w L2 0 a 12 cache 9 QR Generated Code ie bman portals FF4000000 Property 107 next level cache lt cpe gt 0905204 s gman portals Ff4200000 Name next level cache 108 r H soc soc Ffe000000 Value M ge 109 T D gt Wwported Ties rapidioO rapidio FfetcO000 110 i localbus te124000 1119 cpui PowerPC 408081 0 pciO pcie ffe200000 119 Vis H pcil pcie FFe201000 x eL pci2 pcie Ffe202000 ra x amp B fsl dpaa 121 cpu2 PowerPC 408082 i 129 Faf 130 1318 cpu3 PowerPC 408083 139 aie 140 141 be 122 M x lt l d a oe NT d TM 7 2 fr e e S C a e Freescale the Freescale lo
55. are the property of their respective owners 2013 Freescale Semiconductor Inc re boot Lo x Sb Component Inspector 29 Properties Import Name Value Memory Controller Complex MEM PLL CFG 8 9 ObO1 Higher Frequency reference cl MEM PLL RAT 10 14 DbO1101 13 1 async mode only DDR PLL Output Clock 650 000 MHz 3 P B L R AT Core Clusters PLL DERE CC1 PLL CFG 64 65 ObO0 Core cluster PLL 1 output Freq CC1 PLL RAT 66 70 ObO1111 15 1 Async tO 1 2 1 tO set Core Cluster 1 PLL Clock 1 500 GHz CO PLL CFG 72 73 ObOO Core cluster PLL 2 output freq F M CC PLL RAT 74 78 DbO1111 15 1 Async ral e a n ag e r Core Cluster 2 PLL Clock 1 500 GHz CC3 PLL CFG 80 81 ObOO Core cluster PLL 3 output freq C ere ks CC3 PLL RAT 82 86 Dbo1100 12 1 Async Core Cluster 3PLLClock 1200GHz 0000000000 CcC4 PLL CFG 88 89 ObO0 Core cluster PLL 4 output Freq CC4 PLL RAT 90 94 Ob01111 15 1 Async Core Cluster 4 PLL Clock 1 500 GHz Core Complexes PLL Other PLL LBC Clack 50 000 MHz PME Clock 400 000 MHz SerDes PLL SerDes PLL and Protocol Config 3j Misc PLL Related Configuratior DDR S YMC 184 Ob0 Both DDRs in asynchronous mode Boot Configuration Clocking Configuration PME CLK SEL 224 ObO Platform Clock t2 FM1 CLK SEL 225 Ob1 Core Cluster PLL 3 2 FM CLK SEL 226 Obi Core Cluster PLL 3 2 4 5O M H Z gt 6
56. at the import time ini xj Processor Expert Eclipse Platform Import demo File Edit Wavigste Search Project Bun Processor Expert Window Help ENIMS g Tam x i Hav 2 Using the xmls rh Gh Je eo zi y roce t fi generated by P gt nulla Inspector pi Advanced Expert lp eo the hands on scenario presented in the upper slides Device Flowchi Policy m Engine Ports gt BMan Buffer F 3 Policer Distrib Classifii Protoct DPAA c SH an F R s SEC Poli US Iud L5 ai alley 1 pu 39 39 T i Mn E l ee a wu ENS z D mm M z ra I M 22 32 Jof rriss mm mi 2 P ethemat 5 2 i 1 es IR a 3 I Pa b a 4 Pag by art ough ie Bie F n Fa Li FGID3 202202 Channal Or i fz porti Eg d C15 EI es Ready Poom 100 Selection n e Po Ly C IM M KOENE p r e e S a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC ji 3 7 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HR X iR Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the
57. b 4 eTSEC2 Configuration Serial Gigabit MI SGMII cfg sgmii2 b0 eTSEC in SGMII mode 4 eTSEC3 Configuration Serial Gigabit MI SGMIT cfg sgmii3 0b0 eTSEC in SGMII made Z freescale CHER Ob1101 PCle 1 x1 gt SerDes lan Media Independent Interface MIT Obl eTSEC in standard width mode Pins EC MDC ObO1 eTSEC in MI or RAMI mode Details BOOTROM Changing boot location to starts booting from SD card Ob SerDes reference clock 125 M Pins TSEC 1588 ALARM OUTL Obl Disable PLL lock time out co Pins TRIG OUT 0b1111 gt 0b0111 4 Boot Configuration 4 Boot ROM Location cfg rom loc 0 3 4 Boot Sequencer Configuration Pins TSEC3 TXD bus GPCM 16 bit R 0b1111 Loca cfg boot seq 0 1 Obli Boot sequencer disabled Pins LGPLS LFWI 4 CPU Boot Configuration cfg cpu boot Obl CPU allowed to boot default Pins LAZ cfg cpul boot ObO CPU boot holdoff Pins LA16 Pins TSEC1_ TXD 3 1 TSEC2 TX ER Changing boot configuration to allow booting on cpu0 Pins TSECI TXDO TSECI TXD7 Pins LGPL1 Pins TSEC 1588 ALARM OUT2 65 ObO Ob1 4 Boot Configuration 4 Boot ROM Location cfg rom loc 0 3 4 Boot Sequencer Configuratig cfg boot seq 0 1 4 CPU Boot Configuration 0b1111 Local bus GPCM 16 bit KR Pins TSECS TXD Ob11 Boot sequencer disabled Pins LGPL3 LFWI cfg cpu boot Obl CPU allojved to boo
58. cale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HR F IN Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and we d Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc DPAA Hands on Conclusions Outcome generated code for DPAA Hands on In order to accomplish DPAA hands on requirements the following initialization code must be written 220 lines of XML code 750 lines of C code Benefits of using QCS DPAA By using QCS DPAA tool the same result can be accomplished as follows Requested configuration accomplished in approximately ten minutes Configuration done by using a few mouse clicks and visual parameters settings Provides an easy to understand overview of the entire DPAA hands on architecture DPAA tool helps accomplish your desired configuration by highlighting valid choices and prevent you making invalid selections by performing automatic constraints checking by providing
59. conductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet E BH X EIN Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and j A Xtrinsic are trademarks of Freescale Semiconduc uct or names are th perty of their respective owners 2013 Freescale Semiconductor Inc Sore DHIESETI TEDI E Wor wete Unded Sons UE ORR BESO We ion Vy Prem zy l Carmact Us ue Keywos 5 repere reeece s tog Arno sn Pug Brower motor Me Aecormenditons BE Poeeecae Pruciseest Expert and rbatditas Corgonania gt calle Crbsdies Compenetis gt PE CORK SUITE Processor Expert for QoriQ Configuration Suite Cocumertahan The Gan Corfguraten Sutlu ts Gesepred to sunpity the conkguration of ur most complex and powerful deaces The configuration sulle ta 2 set of tots for configuring me Qata Qeces 30 known wong etate from slican reget tp avon me typical board Oring up issues that exst in most complex applicatons wth custom hartwars designa This soto cf tools ts imciamantec az a cet of components each of wich mmows Te details of the silicon control egisters configuration spectes Irun rules and the Necessary value ranges for afl the configuration properties Leveraging Frocessor Expert technology as a hamewor fol these embedded Components makes F easy t align tools w
60. d Comnponerits Output Configuration 90 80014202 fj BOOTROMLEDOTROM Control Words tt TR Complex Clock FLL Ratio setting 4 ff702100 User s Code Length DDR Comples fORCIK Retio 98 90030900 VES i ciffT02104 Components Ubtery 25 A R1 80155770802 Categenes Axphabetca Aasntant Precemors oe a 5f599543 E Component n o VOPI S o i n n n n a o o a 4A ol 019 AO 1 E OORO ac ff70210c BOOTROM Device Co etg sir pii 0 21 bo 9fa0 4di DOR Device Ce SE cu 2 oco O HADeviceTree Device Ca EATETEEHLEEEEEEEEEEAEELEEEERELEUHTEEEETAEELEEEEHELEEEEEEEETEEEETEAERHEH QOL sue iin iene be 24401000 Power On Reser Target Configuration Overview for P2020 t cfg dir pll T ceo bc ff702118 te etg esr pii 1j e Cet e0 00049852 Fiter nn fer P2000 proyect n HL doo et E c4 702124 i Pblems 2 m aE s sno MEA cB 0a280100 s aper for PMN E 3 BOOTROML Power nienst Raportit P Fapertizr PiS T daCi tats ARRAS cor1ff702130 am MI Ner User 2317 Freescale QCS TESTEUILD BL3IONZ2 Inip workspace PR Deunen on FOGTA PowerOsReset Report htm d ar03000090 Descnpton d4 40000001 as j 0c ats d8 00000100 PEE CCB Clock PLL Ratio settings for information only dciff102128 gs B cfg sys pil 0 2 M ILES e412f 702110 m T pil 0 2 eE 23000000 z1 ec f f100C0S f 0 90000000 f4A 700D7D fTB BOFD001D fciefefeter
61. dFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC i 2 Processor Expert QorlQ Qorivva StarCore Symphony VortiQ t arks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform ne Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconduc e names are the property of their respective owners 2013 Freescale Semiconductor Inc Agenda Explore why a configuration suite is important Describe how people get the tools Who is using QCS Review each tool Pre boot loader RCW configuration DDR configuration Device Tree Editor Data Path graphs and configuring the DPAA Summary Where to get more information Walkthrough Labs backup slides Lab1 Pre boot loader RCW Configuration Lab2 DDH configuration Lab3 Device Tree Editor Lab4 Data Path graphs and configuring the DPAA 4 N Z freescale Freescale the Freescale logo AltiVec C 5 CodeTEST Co or ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 3 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC En
62. data storage buffer pools Is a shared resource among cores network interfaces and HW accelerators FM supports in line off line packet parsing and initial classification It enables policing and flow and QoS based packet distribution to the cores QM Manages the queuing of data between cores network interfaces and HW accelerators SEC provides cryptographic acceleration PME high performance hardware pattern matching functionality Accelerators e Po j eo 9 TM m reesca e Fre cale the Fre cale logo o Atec C 5 CodeTEST CodeWar Colin Corin C Wan e the Ene a ent Solutions logo Kinetis mobileGT PEG PowerQUICC 28 ine rer Qr d a StarCor sem phony an nd VoriiQa a s of Fre ccu Reg US PaL Tm m Of Aifast Be iei eStack CoreNet ETSER Flex san cone ag MXC Patom a Package QorlQ Qonv GUC Eng e p bhe Seen dr is eue Tubal uin Xtrinsic onduc udi ctor Inc All other produc ervice names are the property of their respective s 2013 Freescale Sem QCS DPAA Component Overview Flowchart representation of DPAA component is a software solution intended to ease creation of complex DPAA configurations Have an intuitive graphical representation Easy to understand the overall architecture as well as individual DPAA components e QCS integrated component designed to ease DPAA configuration for QorlQ devices e Interactive and user friendly interface in order to provide the best user
63. de c Sources System Ood OO 600 MH omm 5 System PUL V Confgur skions Sp reco v2 0 Cl dh iN DOR Reference Clack 0 000 MH all pus Memery Controller Comghes s di Soh P00 v2 0 MEM Ri OG 8 9 bai frequency reference dock gt Embedded Components DOR _ sec 1 DOR PEL 1 PEL Lore Chesters PLL 5 whossipoant sPManager aptori Care Comgplewes PLL CO Pi SEL 96 99 Ob0O00 CC P fI C FULL SEL 100 103 Obooo0 OCI PEL f i C2 PU SEL 104 107 060000 CC PLL fi C3 PL SEL 108 111 ab00600 CCI P fl C4 PLL SEL 112 115 Ob1100 CC4 PU f1 CS FL SEL 116 119 Ob1100 CC4 Pu fl _ J C PLL SEL 120 123 0b1100 CC4 Pu ft D gt Components tray 7 X 3l C7 PAL SEL 124 127 0b1100 CC4 PU fi e oeme eee Categores Alphabetical Assata CPUS Other PLL m Qvi 2 gt P2 gt PS E P Pex v1 O AIL PRO v2 0 P4000 v1 0 PBL pbl 73 n Pogo 2 O a Gers Changed 00000000 AASS AASS O10K 0100 4C 5 0000 0000 0000 onoD0010 1219 Bie ocoo cccc 4046 4000 scac 2000 EH J J val u es are 00000020 FESO ODOO 6100 0000 0005 0000 0000 09000 00000030 0000 ODOD OCSE 000 DODO goaa 0000 DOOQ h o h o hted 00000040 0000 0000 0000 0000 0613 8040 7565 7A7A ey ze fr e esc a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 49 Processor Expert QorlQ Qorivva StarCo
64. dy Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are b trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc P Device Tree Hands on What we will do Define hardware device tree for P4040 starting from P4080 device tree Import the P4080 which has 8 cores Configure to P4040 which has 4 cores Note P4080 and P4040 are same SOC otherwise Walk through the next slides using QCS Hardware Device Tree editor to solve this scenario pes os 2 freescale Fre SIE cale logo pe Verc rie neon ak sen tele ergy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 77 ine or Ex a Sta ymphony and Vort s of uctor s ER t amp Tm Off Airfast Beekit T d Gor Q Qor rCor a h t BeeKit BeeStack CoreNet EXER Flex siam pe igi C Pom a Package QWQ Con vere QUICC Erg Ready suena bids ipd 5 SARTMOS o er TurboLink Vybridan and Xtrinsi radem cale Sem inn r Inc All o mes are the pr operty of their respective o s 2013 Freescale Semiconductor Inc Device Tree Step 1 Create New Project Creste a Quril Confer stin Pepe t How Gorll Confiner ation Project im E Cem te reyo w he eee rapt Sebect the Sec pou modd Mike to use Sox to be used type fitter best 72 v3 P4 A vl 0 7 gt per Pw Or PADAQ w2 0 oper F gt Pomo vl n nee w P
65. e DDH1 config section with the one from DAProfilesib08844 Workspace p4080 Generated Code ddrCtrl 1 tcl Use the new config file with your stationary project 4 N Ss 9 9 TM NR p re esca e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 7 5 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet z aN Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and t F 5 T Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc freescale Device Tree Edito Lab 5 Changing the Hard C d Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Rea
66. e ito0000000 bman portalsgi f4000000 qman portsisto 4200000 soc sociw000000 t apiciogpefeocoono localbussp fet 24000 pc pis e 200000 pdt poegpifae201 000 pelt paediffezocpoo memory flipa o on M aliases General information This section describes general information about the selected nade Nama allases Farent device rree Lees 23 101 Properties This sechon describes information about the selected node s properties gt x Name ccar deer ethernet ethernecl athernec ethernet ethernec4 ethetnecs ethernet soc dear enecod enecl enetz e x A Dee o DTIHWDevice Tree dis aliases X UTiHWDevieTme dts 4 Aanterrupr parenrt mpic z E cOST amp 20C En dcsr dcsr ectherneto 17 ethernetl 26 ethernetz 29 ethernet3 ID ethernert4 ethernet5 M ethernet 6 ethernet 14 ertherneta e ethernet3 1f serialo 37 seriall T seriall amp epeto seneci amp enetz gepet amp enect amp enec5 4 net amp enet7 amp enecbr amp enetc9 s erialo serial serial cmerials 40 pciO amp pc108 1 poil amp pcil gt pci2 amp pci2 E uabO usbO w Device tree Indude tree Protiens E Console R Wea bend un um oh sena 20 matches n working set orf dis dra Opbors S OritWDevicetree dts
67. ee component is updating with the imported data 3 Expand ProcessorExpert pe gt Embedded Components gt click on DT1 HWDevice I ree component 4 The imported dts file is added under Imported Files folder 5 Open generated device tree file Generated Code P4080 v2 O dts At this moment the imported dts and the generated one are identical ogo Kinetis mobileGT PEG PowerQUICC 7 TM 2 freescale Fre SIE cale logo pe C 5 CodeTEST CodeWarrior ColdFire ColdFire C War tele ery Eile ent Solutions lo 79 ine Expert ot Cor a StarCor on mphony an nd VoriiQa a re trademarks of Fre ccu e c Reg U E m Off Aifast Be ies eStack CoreNet fe 8 EAR ER Flex siam ape Magi MXC Pato ea yaar als shale pride paai iea a er TurboLink Vybridan and Xtrinsic radem cale Sem andu ctor Inc All other ervice names are the property of their respective s 2013 Freescale Semiconductor Inc Device Tree Step 2 Remove Unnecessary Nodes 6 Search for CPU nodes in the tree view you should see 8 cores with 3 properties each 7 Delete cpu4 cpu you have two options Using graphical editor OR gt Component Inspector 3 HwWDeviceTree o c u iz device tree aliases cpus E cpu PowerPC 4080 0 E cpul PowerPC 408061 i cpuz PowerPC 4080 2 H cpu3 PowerPC 4080 3 E cpu P ep Insert node E cpu P Delete node OREORE Rename node bman porta qman porta S Refresh soc soc ff rap
68. eescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Changing the CC1 CC4 PLL RAT for cores to 15 1 sets core clocks to 1 5 Ghz 1 2 Ghz gt 1 5 Ghz CC1 clocks core 0 3 CC4 clocks core 4 7 Note Please change CC2 also even if unused to reach exact high rcw Pre boot Loader x i U Properties Mame MEM PLL CFG 8 9 MEM_PLLRAT 10 14 Core Clusters PLL CC1 PLL CFG 64 65 CC1 PLL RAT 66 70 Core Cluster 1 PLL Clock CCZ PLL CFaG 72 73 CCe PLL RAT 74 78 Core Cluster 2 PLL Clock CC3 PLL CFG 80 81 CC3 PLL RAT 82 86 Core Cluster 3 PLL Clock CC4 PLL CFG 88 89 CC4 PLL RAT 90 94 Core Cluster 4 PLL Clock E Core Complexes PLL CU PLL SEL 96 99 Core O PLL Clock C1 PLL SEL 100 103 Core 1 PLL Clock C2 PLL SEL 104 107 Core 2 PLL Clock C3 PLL SEL 108 111 Core 3 PLL Clock C4 PLL SEL 112 115 Core 4 PLL Clack C5 PLL SEL 116 119 Core 5 PLL Clock C6 PLL SEL 120 123 Core 6 PLL Clock C PLL SEL 124 127 Core 7 PLL Clock Z freescale CHER Memory Cont
69. emiconductor Inc Add a Classification and Extract ethernet dst and remove ethernet type Main h Entries Mame Classification Extract 1 Protocol header fields O Non header field Available protocol fields 3 ethernet E E Dj 4 rw F es FM 1 mt lc snap mpls ipv4 PO an be ipv amp 20 udp a a 1 I 5 aod Po Po Lp C TM 7 mme p r e e S a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 9 Y Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HR X iR Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and j A Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Establish 3 Classification Paths 1 Link ipv4 src classification to ethernet dst classification 2 Draw 3 links from ipv4 src classification to FQIDs1 a a Channel 0x5 SW Portal 5 Po Ly IM p r Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energ
70. experience Allows customers to easily translate their own data flow into a valid driver configuration Designed to deal with complex DPAA user scenarios e yo4 Z freescale CHER to ANS LI fio P Em ne wx wee 9 L Qenan Ls LI fue oes ue wo ima ant Lowe Amt Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWar neon ak sen the Ene ergy Efficient Solution Sympa and Vora arks of Fre iun m eee ot QUOC Enge 6 Rea adela Saone E Safe S logo Kinetis mobileGT PEG PowerQUICC P X prd ic ies S is a Tm Off pa st Be idi BeeStack CoreNet Flexis Layerscape MagniV MXC duis a Packa iia logo Vise alas Tower Tu in nk m rid and Xtrinsic are trademarks of Freescale Sem Bod ctor Inc All other the property of their respective 3 0 2013 Fre ms nductor Inc uml versions LO encodings utf 2 ilpc ximinsxie htp www w3 0ng 2001 XIndude cfadata canfur pine nares hen gt port Types 1G nmumbere 0 policy L2TPv3 portide DwC port type LG numbers 3 policy UDe portide Qe0 enin engine names Ten 1 jconf cfgdata lt bean name bran _master gt portale lt binportal id 0 irg false tenportal id 3 vg Talse diode 20 fod lt qman name gman maste portals gm portal id 0 ing false Godn 1 gmportal id 3 ig false Bodn 1 lt por
71. g address 05001010R K01010 Address in DDR or SRAM memory in which a booting image and RAM based U Boot code is copied to 0x11000000 Execution starting address this is the first instruction of the U Boot to be executed 0x1107F000 sti eal cale logo pn C 5 CodeTEST CodeWarl pads ColdFire iridis Mte ol ent Solu rer Qr d a StarCor Symphony and Vora e tra demarks of Fre cen s c Reg Pro 67 Flo siam cape Magi MXC Pa sa orm in a Package QorlQ Qon e oe Re E ed cue Sa Xtrinsic are tradem cale Semiconductor Inc All other product or service nam e the property of their respective owners 2013 Freescale Sem tions lo U is fe ogo Kinetis mobileGT PEG PowerQUICC s t amp Tm Off Airfa st BeeKit BeeStack CoreNet ASS eee ote uaa aue TurboLnk Vida and onduc Basic Advanced Expert t To B Data Structure Data Structure CCSR Data 4 byte Address Ox ff7o0p70 Data Ox 30F0001D Sample DDR configwration if 1702110 43000000 Addi ng Configure P2020RDB Board ff702000 0000003f lt or 0000001f for P1020RDE Board configuration pairs 102080 80014202 address data eE ee I I 11702108 515993543 to be included into ee a i 702114 24401000 o data 702118 00040852 lle Delay ff702124 03280100 ff702130 03000000 Sample D D a 40000001 00000100 702128 deadbeef configuration data 702110 3000000 fFT00CO8 00000000 structure
72. g four configuration tools all designed to collaborate on consistent configuration PBL tool to define the Reset Control Word bit values and PBI data for the pre boot BOOTROM generator for those QorlQ without RCW functionality DDR configuration supports setting the controller to a working state for any DDR Data path graphical view helps to define data path configuration for the DPAA Hardware Device Tree editor supports references synchronous GUI and XML editing node validation based on specification bindings Packaged as a separate product with installer and wizard functionality Must be a QorlQ customer or under QorlQ NDA for download permission Actual URL is http www freescale com webapp sps site prod summary jsp code PE QORIQ SUITE amp tid PEH 4 ns logo Kinetis mobileGT PEG PowerQUICC dct Oft Aifast Be diu eStack CoreNet 2 freescale Fre E the Freescale logo Pelr C 5 CodeTEST CodeWarrior ColdFire ColdFire C War rae s Fieri ent Solution 5 Ro ii rn rlQ Qori arCor iPad phony an and VortiQa re trademarks of Freescale n s c Reg U S Flo siam cape Mog AG Patom a Package eae beide e Rea E m ed ues rae logo o Tor P da SAEN nk Wybridan and E BH X iR Xtrinsic radem cale Sem Edi ctor Inc All other ervice names are the property of their respective 3 6 2013 Fre cale Semi onductor Inc File Edit Navigate Search Project Run Processor Expert Window Help F3 Bim io we r nz f Project Panel
73. gine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and E BH zk Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc z S Why QorlQ Configuration Suite Configuration of QorlQ processors is increasing in complexity Even more complexity is around the corner We support many many configuration settings Reference manuals are huge and intimidating to new customers e Configuration problems during board bring up are HARD and COSTLY Learning command line tools requires more training etc e Solution Strategy to solve these problems Extensible suite of tools with a common user interface Consolidate into a common tools framework Processor Expert Provide new device support aligned with silicon roadmap Add more configuration tools over time Allow customers to add their own configuration tools to extend what we offer 4 N Z freescale CHER QoriQ Configuration Suite Now Available e QorlQ Configuration Suite v2 2 is NOW AVAILABLE Supports all QorlQ and Qorivva devices Works with Eclipse 3 5 Eclipse 3 6 Eclipse 3 7 development tools Pure Java solution for maximum choice of host system support Add in to CodeWarrior Development Studio for PA v10 1 or later Available from www freescale com QCS FREE DOWNLOAD Includes the followin
74. go AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 8 2 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HR X iR Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and amp FI Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc processor cpu clock revision bogomips processor cpu clock revision bogomips processor cpu clock revision bogomips processor cpu clock revision bogomips processor cpu clock revision bogomips processor cpu clock revision bogomips processor cpu clock revision bogomips processor cpu clock revision bogomips 0 e500mc 1489 985000MHz 2 0 pvr 8023 0020 99 99 4 e50 0mc 1489 985000MHz 2 0 pvr 8023 0020 99 99 02 e500mc 1489 385000MHz 2 0 pvr 8023 0020 99 99 r3 e500mc 1489 985000MHz 2 0 pvr 8023 0020 99 99 4 e500mt 1489 985000MHz 2 0 pvr 8023 0020 99 99 dc e500mc 1489 985000MHz 2 0 pvr 8023 0020 99 99 B e500mc 1489 385000MHz 2 0
75. he Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are b trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc P DDR Step 1 Dump u boot DDR Registers U Boot 2010 12 00001 g612800e Jan 28 2011 22 20 46 Deploy SDK2 3 u boot CPUO P4080E Version 2 0 0x82080020 Core E500MC Version 2 0 080230020 Clock Configuration CPU0 1499 985 MHz CPU1 1499 985 MHz CPU2 1499 985 MHz CPU3 1499 985 MHz CPU4 1499 985 MHz CPU5 1499 985 MHz CPU6 1499 985 MHz e No interleavl NQ CPU7 1499 985 MHz T CCB 799 992 MHz fs dd r cti ntlv null DDR 649 994 MHz 1299 987 MT s data rate Asynchronous LBC 99 999 MHz FMAN1 599 994 MHz FMAN 2 599 994 MHz PME 399 996 MHz e Use CW tO connect and Li D cache 32 kB enabled l cache 32 kB enabled a U Im D R 1 and R Board P4080DS Sys ID 0x17 Sys Ver 0x01 FPGA Ver OxOc vBank 4 36 bit Addressing
76. hony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HR F IN Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and I Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Device tree views synchronization Device tree views GUI lt gt text editor symmetry Memory map view GUI editor symmetry Modifications are reflected in all editors SS Component Inspector 25 U DS Memory Map 23 aa 3 s Ww o EB Jj Device Tree Properties Interrupts ENTIRE ADDRESS SPACE Device Tree Nodes DTI Ibc OxF FFDF 0000 Ibe localbus amp ffe124000 i2c 118000 2 OxF FFDE FFFF j2c 119000 l iu xF FFOO 0000 j2c 119100 gt General information OxF FEFF FFFF serial seriali11c500 D mE F T OxF FEOO 0000 4 seriall serial 11c600 Properties BRP EOTC TTE 4 serial2 serial 11d500 OxF F803 0000 4_ serial3 serial 11d600 This section describes information about the selected node s OxF F802 0000 gpio0 gpio 130000 Ax OxF F801 0000 4 crypto crypto 300000 OxF F800 aono 4 sec mon sec_mon 314000 Name value OxF F7FF FFFF 1 pme pme 316000 red f fel24000 0 xF F440 0000
77. hte b i rt 6 ae m tgm swe st IO Wee ammo remm 008 SAP C 1 L SIE US n A M Lr c a DIO nmm Foe e Am omar 4 shee m LLL ain DORI DORI eee nipis rud m ER DDR Type DDR 3 Bus made 32 bit bus DDR Data Rate Hz 1066000 D DOA Data Rate is E S s Re E SDRAM Control Configuration eee MEE apr te tate on tare i DDR SDRAM Control Confi Hu pen SDRAM self refresh is enabl TRUE mh mv s FRY Enable ECC Error Checking FALSE oe ca Pg v Type of DIMM Registered DIMMs IND ed a _ Enable dynamic power mane FALSE ar ORC HERR Beat burst made 4 beat burst Timing made 1T Timing ree Bank interleaving contral Mo external memory banks are TOR We Pede 505 hme PE He DON 0 E mm A M oi emanita npa s rene LO Driver Impedance Full Strength POR Ub fete l omstew QA FIAT HE P Medias iuit 6 EDNA SER OOA Support concurent auta prec TRUE am maae rue inerte ca mam c yt rj DDR SDRAM Control Confi DLL Reset TRUE DOS Configuration Use true DOS signals ODT Configuration Never assert ODT to internal IU s Number of posted refreshes 1 refresh is issued at a time Use auad ranked DIM TRUE lr DON pene Eclipse based GUI tool which performs configuration of DDR for QorlQ devices The configurable parameters are consistent with the JEDEC standard and also with vendor specific information GUI configuration is validated for consistency and meaningful error
78. idioD ra Expand localbus ff Collapse pciO pcie r pcil pcie ffe201000 pci2 pcie ffe202000 fsl dpaa Delete one node at a time After each deletion dts file is automatically generated e Po ejfe freescale CHER Using text editor LAA NAE E _ Select all 4 nodes and press delete To reflect the modifications in the graphical editor too save the file Ctrl S Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Device Tree Step 3 Solve Validation Errors 8 Look in the Properties view There are 8 errors 9 Click on each error and go to the corresponding line in the device tree file 10 here are undefined references in some nodes pointing to the removed cpus bman portal 10000 bman portal 14000 bman portal 18000 bman portal 1c000 qportal4 qportal5 qp
79. ie tres troio iy Ose VE ids New QorlQ Configuration Project wien i ele KC TUXOTUIUmo CANC AN tih Weekes F Mew QoriO Coaffeuration Project Hardware Device Tree antet eun Toolset sedesc tion sb Cer je Choose shat do you want to configure Properties den Input File Files b05648 Desktop PEx Device Tree dts p4080ds dts Ew pamu Select the device tree file to be imported A Tutorials Project im Goto Wo e oe oe TM lt i fr e est a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 7 8 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet E HR X I Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and JM Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Device Tree Step 1 Create New Project cont 1 File gt New QorlQ Configuration Project enter Project name Next select SoC p4080 v2 0 Next select Device Trees component gt Next browse to an existing p4080ds dts file gt Finish 2 Wait while the device tr
80. it BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Hardware Device Tree Workflow Configure Component Generate Code Qum mhi mpm Create Project ro tree Lond per ater ew LLLI Pf Devices Tree i Tess Cmn Tne rmt IPSI d ds device vn t NORMAI t m e CM cmt ratge trr oso ano cam deca Tee fe an ak drato o a fare Piaty oho ere Gui Po IK Dele node t Han kenere noce bx bom rs oc E Cu Po guste eum amp Qu Po Cp Refresh Wet ut aa mt c dod tore bree fhe Mr Hm hmm n qus o crust Fo Exoend onthe Cw md irent je sth omn n c ae4t lewel ceche feet CPV Ore 201 E LUN amp qu Pu 1 Coloss Modet 5 verry pudr Pree hc 41 beeeportsiestt4o00000 e rye gna portasg 00000 ges soc 0 000000 pest em sw prSo0 rapidioget e0c0000 m Bet Peer endi be eee a dide s Ta V Select Component WwW validate Component Compile DTS tenapi fbi n bash Mete dtc f b 0 p OxB8000 8 8 I dts o dtb 1 dts hee gt D rorem ritos I Pes tion Decem dh avons tw w y Cpu Poem e Sh Tw seton cete peve qor orma ten
81. ks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HR zk Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Add a Set of Frame Queues 1 QMan configuration 1 Add a FQIDs range FQR1 for enqueued frames and configure FQld 1 and count 200 2 Switch to QMan tab and make the following settings Total FQIDs 150000 Fqd Pfdr mem partition Primary DDR non cacheable betel aM EM or wm _ 2 end r PryyessonEspert c liae 3 0 fot lage Seach Project Run PracemerEmet woe rep h bal i 0 29 q iz C Lp TM 7 mme p r Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 9 1 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HR X iR Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and j A Xtrinsic are trademarks of Freescale Semiconduc
82. l pulled down to GND and a value 0b1 represents a signal pulled up to Vdd regardless of the sense of the functional signal name on the signal Configur ation file data structure including control and configuration words two parts that needs to be put together with user s code typically u boot image to create booting image for a device Address Reserved Ox40 Ox43 BOOT signature Control Words structure 0x44 0x47 Reserved Ox4C Ox4F Reserved 0x50 0x53 Source Address Ox80 0x83 Config Address 1 x84 x87 Config Data 1 Ox88 Ox8B Config Address 2 Ox8C Ox8F Config Data 2 0x54 0x57 Reserved MOSQ Target Address E Contig Daa N 0x60 0x63 Execution Starting Address mE Configuration Words structure Reserved Config 0x68 0x6B Number of Address Data pairs Existing U Boot image Reser 4 N oS gt freescale CHER Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC e ert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp T i Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the Safe Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service n BOOTROM Hands on otep 1 Create configuration project for the P2020 device otep 2
83. le the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Pre boot Loader Step 8 Change Serdes for 2 x 4 SGMII e Starting from previous rcw Ox10 d c protocol configuration to allow 2x4 Sy Component Inspector x GMII Basic Advanced Expert hh E rev2_high bin txt config lets adapt Serdes Properties Import Mame Description RCW Source PLL Configuration E SerBbes PLL and Protocol Configuration SerDes Reference Clocks E SRDS_EN 178 SRDS PRTCL 128 133 SRDS RATIO Bl 136 138 SerDes PLL 1 Clock SRDS DIV B1 139 143 SRDS DIV B1 Lanes A B 139 SRDS DIV B1 LanesC D 140 SRDS DIV Bi LanesE F 141 SRDS DIV Bl Lanes G H 142 SRDS DIV Bl Lanes 1 143 SRDS RATIO B 144 146 SerDes PLL 2 Clock SRDS DIv B2 147 SRDS RATIO B3 148 150 SerDes PLL 3 Clock SRDS DIV B3 151 E SRD
84. mphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HR zk Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Link IPv4 Distribution to ipv4 src Classification i Main Entries A n Name Classification 1 Extract Protocol heade CO Non header fie Available protocol fields Policy1 E E Boe lc FM 1 k EM xz 20 Po Po Lp C TM 7 Pw p r e e S a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HR X iR 96 Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and j A Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale S
85. nce cpu handle P4080 v2 prj Generated_ line 318 Device Tree Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 8 1 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Device Tree Step 4 P4040 Device Tree 13 Goto Search menu select Device Tree Search tab gt enter cous text gt press Search 14 n Search view select the found matches associated with the generated file New device tree has 4 cores and looks as follows P Devin Tres Seach O va Search T Pug Search Jm n p Pm Soot v Teer Search E CiC Search Cortera best cpud w l lcan sensitive ary string aw arata escape for Rerate 9 l Reguie expression Mh name patterns v Choose Patterns ore seperabed ty o comme any string 7 ary weracter Leser ove SS Component Inspector 23 Basic Advanced Expert lg E Q
86. ne Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and i Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc freescale Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc DPAA Overview DPAA Data Path Acceleration Architecture provides the infrastructure to pass packets Network to from cores hardware accelerators and network Interfaces interfaces he architecture contains several hardware components Frame Manager FM Buffer Manager BM Queue Manager QM HW accelerators Security SEC Pattern Matching Engine PME Each hardware component is performing specific operations on the incoming outgoing frames BM Manages
87. nfigure QBase 32 2 Link Policy1 to IPv4 distribution and then to Pass through in this order j Ly IM p r Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC i 9 4 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HR zk Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Add a Classification Add a classification for IP source and extract ipv4 src and remove ethernet type Main Entries Name Classification 1 Extract Protocol header fields CO Non header field Available protocol fields faffset tti nextp hchecksum i Extract fied E ipv Ge top E udp i gre pppoe Extracted protocol fields j Ly IM p r Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC i 9 5 Processor Expert QorlQ Qorivva StarCore Sy
88. nverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc QCS DPAA Component Features 4 Immediate code generation at user request in any stage of configuration ps Panel T esis 77 DA Inspech neg Generating code j o x E n Documentatii Generate me Expert Project j B gt Generated Code E Sources B BS ProcessorExperF pe EL Configurations BP P4080 v2 0 cf gt Operating System im Cpus GD SoC P4080 v2 n Embedded Components z oY DPAATDPAA QorIQ 20 n i Generating cade FTF dema usecase ProcessorExpert pe HB Always run in background arene rae Run in Background Cancel Details gt gt LIB BEBO Sr I 1 rJ Immediate notification for all errors occurred during the code generation process error O warnings O others Description S errors 1 item ERROR Incorrect size for queue distribution id 2 ty 9 TM m fre est ale Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 3 4 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat
89. o Expert ot Cor a StarCore Symphony and Vo nia e trademarks of Freesc con n Reg US Pa l reNet n rm SMARTMOS Tow Toi Vb an and R EAR ER 8 Flex siam ape Magi MXC Palm a Package rpm rae QUICC Ere Fen Sable Fun afe Xtrinsic are tradem cale Semiconductor Inc All other ctor service nam e the property of their respective owners 2013 Freescale Semiconductor Inc Lab 4 DPAA Hands on 1 Create a new QCS project called Lab4 1 Choose P4080 rev2 0 2 Choose a DPAA component and select empty component 2 Maximize the DPAA Component Inspector 257 occu ELLE E31 rs Fe Edi Nyipati Seach Fest Wn Proce2es Expert Widow Heb ebd i LJ q ev 11 4 vacas Er Ic Project Pace EL Qcureseximenm o0 Soc Aderat tert a 707 4 rus mamm M g 1 5 2 S HMM NN OO UB wou te i By Peis Sort Mer P r ue ue 8 i r frans anre Dort ttm HC A 2aLre ton n t fri i oe ct vel Code c T p Pot it 2 ier Souctes 5 ja Port z H Py are erar PQ M 9 o up Contgrevens Mac actress Daimi Pte m S 9 2 0 c 9 z amp Opening Ssstev Ei ites a LIQON Qs i gt Cpus b crm a Ji ges a ferst iE Erbedaec Components Leeobao a Ta Port d cea coraa z r Ll mG Em Poig C Reset an et Defa Pie Free Meaga Bulle Foou fe Por Parameters m rare of butters a FS p Efim Poet Lei t Buffe pre i a Mreta sus gt Suffer z K Ea ea Cene re o x i trom
90. of the Description This prope m be used mm 4 sec mon sec_mon 314000 hierarchy and describes how child device nodes pme pme 316000 should be addressed It defines the number of 4 gman qman 318000 v u327 cells used to encode the size field in a child T node s reg property If missing a client program Device tree Include tree x3 ili should assume a default value of 1 o Peo fr e esc a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 2 2 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HR X iR Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and i A Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Device trees inclusion The Include tree allows easy navigation among device tree fragments dts dtsi Hovering support for properties and nodes a tool tip appears displaying their initial locations pAOCCde undees s 13 p5o204s des DTH wDewoeT ree des M bmen portmi819000 gt xD pre dii
91. oldFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 6 6 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc BOOTROM Step 4 Prepare configuration data file gt Component Inspector 8C Properties Mame Device Power On Reset Configuration PLL Configuration Device Status SerDes Configuration Boot Configuration High Speed 1 0 Configuration General Purpose POR Configure Engineering Use POR Configura Pin Multiplexing Configuration Miscellaneous Configuration Boot ROM Data Configuration Offset Output Configuration Control Words Users Code Length Source Address Target Address Execution Start Address Data Structure e Z freescale CHER Configuration Words Value BOOTROM 00001000 11000000 1107F000 Booting image code length in bytes e g RAM based special U Boot image NO 0000010 tarting address O the special U Boot code as an offset from the SD MMC card startin
92. olicy1 to split IP frames traffic and then a link from port FM1 P2 to receive incoming frames e Add a distribution for IP frames and extract IPv4 protocol then configure QBase 39 S Component Inspector x Basic Adve ae It Distribution A Available protocols Distribution name Distribution 1 ethernet tl vlan llc snap E mpls ip CPeration H td E ut gre pppoe minencap sctp dccp ipsec_ah ipsec_esp E EB Ej rm EE es mt Extract protocol Queue base Queue count e o Pal OT C TM M m ps rees a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 9 3 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HR zk Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and T Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Link the Distributions to the Policy 1 Add a Pass through distribution for other non IP frames and co
93. on b O1000 8 1 E emor Controller Complex PLL settings 100 000 MHz Ob01 Higher Frequency reference clock 0601100 12 1 async mode only 80 6 MHz cutoff 600 000 MHz ObO000 CC1 PLL 71 1 200 GHz ObOOOO Cc1 PLL 71 1 200 GHz ObOO00 Cei PLL 71 1 200 GHz oboo CC1 PLL I 1 200 GHz 061100 C4 PLL 71 1 200 GHz 061100 C4 PLL 1 1 200 GHz 061100 CC4 PLL it 1 200 GHz 061100 C4 PLL 71 1 200 Hz And also changes the LBC and PME clocks 450 000 MHz 450 000 MHz Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc 50 a So Component Inspector x ir DACH ates x ADIRE a og UA DE RUE m Say a Properties Mame Memory Controller Complex MEM PLL CF 8 9 MEM PLL RAT 10 14 DDR PLL Output Clock Core Clus
94. or Ex t Qor a Sta Symphony and Varia are ade arks of Fre e i prei eg US Pat Tn Of Aes n A f Ss t go Kinetis mobileGT PEG PowerQUICC T Q Qor Pid c Reg EH ER Flexi san cape Magi MXC Pa i eie ackage Qo c e beide o Rea ea Ply SASS D ga 090 5 SMARTHOS To r Tu iot Pk Wybridan and Xtrinsi radem cale Sem Minn r Inc All o mes are the pr operty of their respective own 3 6 2013 Fre cale Semiconductor Inc freescale Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Pre boot Loader Hands on Step 1 Import and decode low speed config rew 0x10 5g rev2 low bin txt Platform clock 600MHz Core clock 1 2GHz FMAN1 2 clock 450 MHz DDR clock 600MHz 1 2GHz Step 2 Use PBL tool to increase clock speed up to Platform clock 800MHz Core clock 1 5GHz FMAN1 2
95. ortal6 qportal7 11 Remove the above nodes in a similar manner 12 Save your changes e Po freescale CHER 4 P4080 v2 D dts 3 185 bman portal8iO0O000 P 186 cell index 0x4 87 compatible fsi p4060 bman portali fsi bman portal 188 reg lt 0x10000 Ox4000 0x104000 0Ox1000 gt ip c O00 QI 1 cpu handle 1 interrupts lt Ox71 0x2 OxO Ox0O gt 191 i 192 193 bman portal 1i4000 194 cell index 0x5 195 compatible fsi p4060 bman portai fsl bman portal 196 reg lt 0x14000 Ox4000 OxiO05000 0x1000 gt 127 cpu handle c amp cpu5 4 mo owed vaa Mae ID Mae Mise Marin laiton E Console S3 Progress SIDE 8 errors 0 warnings 0 others l l Description Resource Path Locat Type Errors 8 items amp Undefined reference cpu handle P4080 v2 pri Generated line 189 Device Tree Undefined reference cpu handle P4080 v2 j pri Generated_ line 197 Device Tree 9 Undefined reference cpu handle P4080 v2 jprjlGenerated line 205 Device Tree Undefined reference cpu handle P4080 v2 j pri Generated_ line 213 Device Tree Undefined reference cpu handle P4080 v2 JjprjjGenerated line 288 Device Tree 3 Undefined reference cpu handle P4080 v2 JjprjjGenerated line298 Device Tree 3 Undefined reference cpu handle P4080 v2 pri Generated_ line 308 Device Tree Undefined refere
96. p re es a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 86 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HR F IN Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and P A Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc DPAA Hands on QCS Solution Build PCD configuration according to hands on requirements Additional 1 FQ ranges and 1 FMan port channel to be used for transmission 4 3 44 IDs 1 2 an miss FMan1 PCD flow Traffic received by FM1 port1 is split in IP frames and other FM 1 frames by Policy1 ipv4 distribution FOIDs 2 201 201 IP frames classified in one of the 3 defined ranges of IP source are directed into FQIDs 43 45 All other IP frames are classified by MAC destination and are directed into FQIDs 46 amp 47 All other non IP frames are directed in FQID 32 e poss TM 2 freescale Fre et the Freescale logo pe C 5 CodeTEST CodeWar neon ak C War Mise ay ie ent Solution Pr
97. paced v2 0 OF ic Operaing Sysen elect the DPAA dpc xml File to be imported Hu Cpa 4 d socipece v2 0 Ll Erbedded Components Ph Anaad uA AA Look in G3 Generated Code Ei m hy Recent Documents Input File wow o8 o ow oc wx a fmc config xml He i 2 Back eae y ee Bin 100 Sedecbun 6 0 Desktop n rr 2 9 ameen shishar sau My Documents E File name imo_dpc xml Open Files of type ml Cancel eS EZ T d o 9 9 TM m P d r e es C a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 3 6 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet A E R Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and i i A Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Import XMLs Feature Demo Importing files previously generated by the QCS tool won t produce the same output e The objects coordinates are not saved in the xmls and are calculated using a placement algorithm
98. panends n LS Documentation H Generated Cade S j PBL1 pbl 55 M EQ Configurat New i coooodoo AASS AA 55 O10F 0100 1054 0000 noo0 ooga M dins adm 00000010 1E1E 181E 0000 cece 5840 0000 3C3C 2000 perating Seas n Ee 00000020 FESO oo00 6100 0000 noO00 noon0 OOOO ongo ES ta ri misce ji 00000030 0000 oo00 nosB 6000 0000 noon noon ongo oe Bo X du Sus 00000040 0000 0000 0000 0000 0813 5040 B163 SSEZ dd PBLLR Move B SaAnalysispoir Rename F2 Ee eec fut ee ee rc Top cse g Import gy Export t Refresh F5 show n Remote Systems vien Generating the PBL now provides us the Clean Selected File s ild Selected Fil i EET same RCW than the RCW seen in the oDK2 3 4 fsl Ubuntu 32bit mnt hgfs DebianShare QorIQSDK 02 03 00B images boot p4080ds R RRRSS O0x16 ls hv 1lp lnx agent dtb hv 1p lnx host dtb rcw 6x16 all rev2 high bin rcw 0x16 all rev2 low bin hv lp lnx dtb hv 4p lnx lnx lwe lwe dtb rcw 0x16 all rev2 high bin txt rcw 0x16 all rev2 low bin txt fsleUbuntu 32bit mnt hgfs DebianShare QorIQSDK 02 03 00B images boot p4080ds R RRRSS 0x16 xxd rcw 0x16 all rev2 high bin 0000000 aa55 aa55 010e 0100 105a 0000 0000 0000 U U MP 0000010 lele 18le 0000 cccc 5840 0000 3c3c 2000 X lt lt 0000020 fTe80 0000 6100 0000 0000 0000 0000 0000 a 0000030 0000 0000 008b 6000 0000 0000 0000 0000 ore 0000040 0000 0000 0000 0000 0813 8040 bl63
99. product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc freescale ab 1 Installinc A ay Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are b trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc P Installing QCS Download QCS2 1Training zip Skip if you already have QCS v2 1 installed Setup for labs Create a directory where you have read write permissions Eg C QCS21 from now on we ll call this directory lt qcs gt If you already have QCS installed use that directory as lt qcs gt Copy the QCS2 1Training zip labs directory into lt qcs gt Follow the instructions in lt qcs gt labs QORIQCSINS I ALLUG pdf 2 frees ale Fre c the Freescale logo pe C 5 CodeTEST CodeWarrior ColdFire ColdFire en w i ergy Efficient Solutions lo 44 ine
100. pvr 8023 0020 99 99 ne e500mc 1489 3985000MHz 2 0 pvr 8023 0020 99 99 total bogomips 799 99 timebase platform model Memory 49999500 P4080 DS fs P4080058 4096 MB Z freescale TRER processor cpu clock revision bogomips processor cpu clock revision bogomips processor cpu clock revision bogomips processor cpu clock revision bogomips 0 e500mc 1439 385000MHz 2 0 pyr 8023 0020 99 99 1 i e500mc 14993 385000MHz 2 0 pyr 8023 0020 99 99 x e500mc 1489 385000MHz 2 0 pyr 8023 0020 99 99 RE e500mc 1439 385000MHz 2 0 pyr 8023 0020 99 99 total bogomips 399 99 timebase platform model Memory 49999500 P4080 DS fs P4080D5 4086 MB 83 Device Tree Step 5 Apply and Test Changes Ona Linux machine create the device tree binaries before and after changes Boot the Linux kernel on a p4080DS board Check the number of CPUS that Linux kernel sees before and after changes use proc cpuinfo command e You should obtain the results from left side only 4 cores are in use with the new device tree Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg
101. r product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc freescale DPAA Configuration Lab 6 Using Data Path Gi Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are b trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc P DPAA Hands on Problem Statement Receive 1GE traffic on first FMAN e Split incoming traffic in IP frames and others Frames with specified IP source are directed in specified FQIDs and then in SW Portal 0 IPv4 frames IP src 32 xx xx 32 EN FQID 0x2B IP src 48 48 48 48 mE FQID 0x2C IP src 16 16 16 16 FQID 0x2D Other IPs MAC dst 0a 7a 76 xxoo xx FQID 0x2E 0x2E FQID 0x2F Ox2F FQID 0x20 MAC dst 55 55 55 xx xx xx Other frames e Po Is 5 C TM nw
102. re Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HH E ZR Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Gi f a on Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc 3 Increas Basic Advanced Expert I lE hanging the Froperties Import Mame System Clack System PLL SYS PLL CFG 0 1 SVS PLL RAT 2 6 Platform Clock DDR Reference Clock Memory Controller Complex MEM PLL CFG 8 9 MEM PLL RAT 10 14 DDR PLL Output Clock Core Clusters PLL Core Complexes PLL CO PLL SEL 96 99 Core 0 PLL Clock C1 PLL SEL 100 103 Core 1 PLL Clock C2 PLL SEL 104 107 Core 2 PLL Clock C3 PLL SEL 108 111 Core 3 PLL Clock C4 PLL SEL 112 115 Core 4 PLL Clock C5 PLL 5EL 116 119 Core 5 PLL Clock C amp PLL SEL 120 123 Core 6 PLL Clock C PLL SEL 124 127 Core 7 PLL Clock E Other PLL FM1 Clock FMz Clock RU te z freescale TRER ratio to 8 1 makes platform clock 800 MHz 600 Mhz gt 800 Mhz Value Details 100 000 MHz Ob00 Platform Fregfsystem PLL targeting 667 MHz and above operati
103. reescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 19 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Explorer Tree View Operations on nodes SS component Inspector 50 eo Go back forward Device Tree MR 5 Ss J i2 device tree Expand collapse Want in A di d 4 cpus General information Documentation 7 d SCE nal ng escen desr desr FO0000000 This section describes general information about the selected node This node is used to repres bman portals fF4000000 present if the processor is Ing sort H 4 gman portals FF4200000 Mame soc socBf fe000000 Press F1 for more details Insert node 4 di Tenet node F3 PARIS device tree eet XX Delete node Delete Heo Akan Delete node 4 pil Ki Rename node F2 p E Sow 5 Properties E He namen od e ddr
104. rior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 1 1 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HH E ZR Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and j Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc freescale Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc DDR Configuration alej A eee Re o s te oe la T e te LI Q twe
105. roller Complex Value 0601 Higher Frequency reference cl 0601101 13 1 async mode only Ob00 Core cluster PLL 1 output freg O bO1111 15 1 Asvnc 1 500 GHz 0600 Core cluster PLL 2 output Freq DbO1111 15 1 Async 1 500 GHz 0601 Core cluster PLL 3 output Freq ObO1001 9 1 Async 900 000 MHz Ob00 Core cluster PLL 4 output Freq 0601111 15 1 Async 1 500 GHz ObOO00 CCl PLL 71 1 500 Hz ObO000 CC1 PLL j1 1 500 GHz ObO000 CC1 PLL j1 1 500 GHz ObOO00 CC1 PLL j1 1 500 GHz 061100 C4 PLL fl 1 500 Hz 061100 CC4 PLL 1 1 500 Hz 061100 CC4 PLL 1 1 500 GHz 061100 CC4 PLL j1 1 500 GHz Details 650 MHz gt 1 38 GHz o2 Increase DDR Output Clock Basic Advanced Expert Ig E Set MEM PLL RAT to 13 1 Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names
106. s warnings are displayed Tool s output is C file containing memory registers values CodeWarrior TCL initialization file uBoot initialization file tis integrated into the configuration suite for QorlQ devices e Po Ly C TM 7 mme p r e e S a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC ji 1 3 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HR X EIN Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and j A Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc DDR Wizard Basic Configuration Mode Custom Configuration SS New QorlQ Configuration Project ce kE DDR Confiquration Configured device P5020 Configure 1st DDR Controller n Confiquration mode Auto configuration Auto 2 O Import from memory file configuration TUE mE DDR Controller DRAM Settings m od e Type DDR3 DRAM Configuration 1Gb 256Mb x4 Data Rate 1333 MT s Speed Rating 1333 MT s Y Ranks 1 Registered DIMM J Data Bus width Mirrored DIMM CAS
107. scale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Pre boot Loader Step 9 Adapt Serdes Clocks S Component Inspector 3 Properties Import Name Value Detail Description SERDES 8 please refer to the P4080 RCW Source LEC FCM NAND Flash S R O req u res PLL Configuration 3 SerDes PLL and Protocol Configuration 3 1 25 G h Z O nN Ba nN k1 lan e SerDes Reference Clocks SROS EM 178 Ubi SerDes enabled E F G H Set to Divide by 1 SRDS PRTCL 128 133 xf amp Bank f A O eO PS TES SRDS RATIO Bi 136 138 DbD10 25 1 SerDes PLL 1 Clock 3 125 GHz SRD amp 5 DIV B1 139 143 SRDS DIV B1 Lanes AJB 139 ObO Divide by 1 off of Bank 1 PLL SRDS DIV Bi Lanes C D 140 Ob0 Divide by 1 off of Bank 1 PLL SRDS DIV B1 LanesE F 141 Ob0 Divide by 1 off of Bank 1 PLL SRDS DIV Bi Lanes G H 142 b Divide by 1 off of Bank 1 PLL SRDS DIV Bl Lanes I 143 O60 Divide by 1 off of Bank 1 PLL SRDS RATIO B2 144 146 ObOOO 10 1 SerDes PLL 2 Clock 1 250 GHz SROS DIY B2 147 Obo Divide By 1 aff of
108. sors uses Processor Expert to generate configuration files used in the creation of a bootstrap typically to either Linux or another OS Installs as an Eclipse update package under 20MB eupports configuration complexity without altering OS Application software 3 Z freescale CHER gt gt Installing Processor Expert for QoriQ You need either CodeWarrior for PA 10 1 or later OR you download an Eclipse version for free OR you use an existing Eclipse workbench you have installed Wind River QNX GNU etc Processor Expert for QorlQ Configuration Suite installs using the Eclipse updater s Add new software capability The Configuration Suite is 100 pure Java so it should run on any Eclipse 3 5 1 or later host environment Windows Linux Solaris Mac OS 32 bit 64 bit 3 9 9 TM E mW ps re esca e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 8 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet aN Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and E BH A Xtrinsic are trademarks of Freescale Semiconductor
109. specified notifications Input file File format Endian mode Default Big Endian Beginning memory address read from memory dump file 1st DDR Controller memory address FE008000 Use default Import from a memory dump file the register values for the ddr controller Import configuration should be done individual for each DDR controller ey ep TM T o r Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 1 7 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HH E ZR Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and i J Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc freescale Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeK
110. sys pil 0 2 POR Signa ctg sys pit o eng sys pu etg sys pit 2 DOR Complex DORCLK Ratio ObOO1 41 etg ddr pi 0 2 POR Signa cfg ddr pil O ctg dar pu 1 cfg ddr piq2 Je500 Core CCB Clock Ratio Z freescale CHER Power On Reset Configuration settings PLL Configuration settings CCB Clock PLL Ratio settings for information only 61 600 000 MHz cfg_sys_pll cfg_sys_pll 9 cfg_sys_pll cfg sys pll ea DOR Complex Clock PLL Ratio settings for informstion only et DOR Complex O0RCLK Ratio et es 4 1 cig ddr pil 0 2 400 000 Petz doom ee ee ee ee mm pinpdb ean aem qaippe emp ee me cual dpdi quen sm 0b001 4 1 SIT Valve Pin location na cfg ddr 11 0 2 obo TSEC 1688 CLK OUT ee 8 Ob Dl 4 1 wee TEC M PLN GUT e weit we jN amp NMBKME cfg_ddr_p Y CLK TN AE na ee cfg ddr pli 1 tbe TSEC 1588 PULSE OUTI ee cfg dd pli 2 bi TSEC 1588 PULSE OUT2 e500 Core Clock PLL Ratio settings for information only UN uo ove o MEC REEL ornnes c RR Core0 32 Core 32 Core 900 DOO MHz Core1 900 000 1 rr 500 Core Clock PLL Ratio settings for information only 6500 Core CCB Clock Ratio a Coreb 3 2 Corel 5 2 a Coret 999 000 Mtz Corel 900 000 nz Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior C
111. t default Pins LA27 cfg cpul boot UDU LFU boot holdoff Pins LA16 Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc BOOTROM Step 3 Observe Power on reset overview details 83 Power On Reset Target Configuration Overview for P2020 3 z3 M e Ni BO TROMI PowerOnReset Repon te D Report sor PID d GaCpLL S gt 3 Copyright 1997 2012 Freescale Semiconductor Inc All Rights Reserved E fiber C Usar 23137 Freencete QCS_TESTELALD 120522 1 ndiae werkapece 2000 Decumanmaten BOOTHOME _Powerln emt Raport hirri z3 3 http www freescale com Power On Reset Target Configuration Overview for P2020 3 Copyright 1997 2013 Preescale Semiconductor Ino All Rights Reserved 2 http wwu freescale com j zail t support fzeescale cocs OCE Cicek SYSCLK Rano ctg
112. t os Buffer 3 Resizable a scrollable view ees 1 Zoom 100 Selection 644 547 E y certe E gt ex E S S S m PO 9 f TM ar r e est a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t m E ZR 89 Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc The Graphing Palette Policy establishes the order of distribution Distribution sorts incoming frames Classification defines the classification and software portal Policer allows enforcement Frame Queue s Software Portals amp Channels Link between objects j Ly IM 7 p r Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 9 0 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademar
113. t file CUserskcionesclsDesktopxddr mem dump txt txt formats File format Endian mode Default Big Endian Beginning memory address mport from file read from memory dump file 1st DDR Controller memory address FE008000 Use default Import from a memory dump file the register values for the ddr controller Import configuration should be done individual for each DDR controller e Po ejfe freescale CHER Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc DDR Wizard import Memory Dump Mode Mew QorlQ Configuration Project DDR Configuration amp 3 File or folder not specified Configure 1st DDR Controller Configuration mode O Auto configuration Import from memory file Error File or folder not
114. tals gt Total gids 150000 lt totalfgidts gt fodenemornypartition e MEM IST DDR NON CACHEABLE c ftadmemorypartition lt piarmemerypanitions e MEM IST DOR NON CACHEABLE of d reoeenorvpartition xir tases Aeg efase 1 T Base lt rthramesdegth gt 30000 rf ea mes depth pl rteeshold ox pfartreshold gt st ntreshold O sfdrmeshold lt qean gt trepart name tmOportOl type IG number 1 engine neon import name fm OportO3 type 1G number 3 engine hmo T n me tmOpont sm xerrFald 1 erfald QCS DPAA Component Features 1 e Default values capability Easy access to configuration settings for each DPAA element Ss Component Inspector 0 I I 110 e Peo freescale CHER Basic Advanced Expert I mss FOR Man E lea wi Mame Liadn i Total number of Fgids 150000 Fod memory partition Primary DDR non cacheable PFdr memory partition Primary DDR non cacheable Exceptions Callback MULL Use error IRG Partition number of Foids jos Runtime Frames depth ap Pfdr threshold jos Sfdr reservation threshold D Instant display of relevant description for each configuration parameter Queue base Queue count This attribute is only relevant when used in a queue elements inside of the distribution element It defines the number of permitted sequential values Valid
115. ter SerDes PII 3 Clark A Nanninin far Ra meront rabe Mw Bonk 1 A D D Tad GID Er E LP OTe FGI Eit TT Dahi OSD Er Barked 00000000 0000 00000010 11z 0000 OH0000020 j 0000 OO000030 0000 oonogooosdo 0000 00000050 i 0000 OO000060 n 5 0000 a Se D items Description Resource Path Locat Type a Writable Insert 1 1 9 y4 Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc z freescale CHER AA What s Different About QoriQ Processor Expert MCUs use Processor Expert to generate source code that is code size optimized and only includes the minimal functions and operations to support initialization and peripheral drivers Previously Processor Expert was included in CodeWarrior only Now Processor Expert plug ins can be installed into any Eclipse Proces
116. ters PLL CC1 PLL CFG 64 65 CCl PLL RAT 66 70 Core Cluster 1 PLL Clock Cc PLL CFG 72 73 CC2 PLL RAT 74 78 Core Cluster 2 PLL Clock CC3 PLL CFG 80 81 CC3 PLL RAT 82 86 Core Cluster 3 PLL Clock CC4 PLL CFG 88 89 CC4 PLL RAT 90 94 Core Complexes PLL CD PLL SEL 96 99 Core O PLL Clock C1 PLL SEL 100 103 Core 1 PLL Clock C2 PLL SEL 104 107 Core 2 PLL Clock C3 PLL SEL 108 111 Core 3 PLL Clock C4 PLL SEL 112 115 C5 PLL SEL 116 119 C6 PLL SEL 120 123 C PLL SEL 124 127 freescale CHER Value Details Ob01 Higher Frequency reference cl Ob01100 12 1 async made only 600 000 MHz p Ob00 Core cluster PLL 1 autpu DbO1111 15 1 Async 1 500 GHz Ob00 Core cluster PLL 2 autput freq ObO1111 15 1 Async 1 500 GHz Ob01 Core cluster PLL 3 output Freq Ob01001 9 1 Async 900 000 MHz Ob00 Core cluster PLL 4 output freq Ob01111 15 1 Async ObOOOO Cci PLL ft 1 500 Hz ObOOO0 CC1 PLL ft 1 500 GHz ObOOO00 CC PLL fl 1 500 GHz OboO00 Ci PLL fl 1 500 GHz 061100 CC4 PLL fl 061100 CC4 PLL fl 061100 CC4 PLL 1 061100 CC4 PLL ft Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 5 1 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Fr
117. th new slc n producis and sapped upgraded modsis Processor Expert echnolegy and therefore t e Configurabon Sutin zz designed az a set of plugens that tundan within a standard EGipse envronmert such as Code Vramor D evescoment Stucho sarg will creste a Qord Configuration Project thet defines al imported and generated configurate n fies iandor source codes 30 Ihat 3 version conii system can be used 4 ampie wizard is used in zgiact basic configuraton values and to define detautt setings The Component Inspector wrsdow 15 used 12 modify each property Each property is automagcals evaluated In ensure Ima the values are Correct and consistent wih each other Each tool has 3 set of amena matis applied to ensure tme conbguration Set ss propeny definac including Checks with me ome tools for consistant conhigurabon of the entire QoriQ aibcan product Each component generatus output m the form necessary for configuration PRL data in fies lomat DOR c nfiguraton source code for w boot fme emi Gata Device Tree source fies for dis and oo form Every tool and property has tool 9p phie docurnentabon shored wih the product manuals Z freescale CHER Ectpee Compabblty Eqlipss Galteo 53 5 x Edinse Halios 3 5 6 CodgeWamor Deveopment Studio Proce2sor Eeport Onertatan Freescale Technology Forum 7 unc Software Moets Si amp con Blog by Freescalez software expert e tE Fecit Mime seen a Supported Devices P2
118. tor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc 1 Add SW PortalO channel 2 Link FQIDs1 to WQO of SW PortalO L aPrucessoaniExpert bcne Fie Edt Newgaie Sendi Proet u Processor Expert Widow Hep uude 9 Q oF ES Processor ex scc Adverced Expert p E Lr a n id MO i 6 ARE 18 TW Port thea forme Meneger Port non PCE Port Ia Port reme MAC address Interface Speed D jL oopbect 3 J x Suffer Poo Pr vetet timoer of buffers z C J s s te Buffer Pos id Bw wee Buffe Cache ine signent PO Lpy TM 7 ue o r ees a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC I 9 2 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t A ZR Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Define the Parse Classify Distribute Configuration Add a P
119. values for count are powers of 2 When Automatic input validation configuration constraints checking and instant display of relevant conflict messages TT FMan Pork s Bman Frame Manager Port non PCD Port Id T Fort name MAC address InterFace Rami Speed 1 Gbps Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC 3 1 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc QCS DPAA Component Features 2 e On the fly SS Component Inspector 53 hy fo configuration i gt validation by highlighting correct choices and graying out the invalid ones Policy 1 nn miss H E e e m Policy2 n miss eadv Foam 100 Basic link 546 248 e Po Ly C IM 7 p re es a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient
120. what we offer 2 freesi ale Fre E the Freescale logo Pelr C 5 CodeTEST CodeWarrior ColdFire ColdFire C War Ai du nt Solutions logo Kinetis mobileGT PEG PowerQUICC 39 Ro peat Qo rlQ Qori arCor iPad phony an sd Voir rcemafa f Freescale Sem S Reg US Pai t amp Tm UE t BeeKit BeeStack CoreNet ETSER rex sun cp igi D Pom Visa sa rud Varese RU ea Se e the SafeAssure logo an mes cu mede Xtri radem cale Sem Minn r Inc All o e the property of the di ed E Freescale Semiconductor Inc Processor Expert for QoriQ For More Info Processor Expert for QorlQ Configuration Suite htto www freescale com webapp sps site orod summary jsp code PE QORIQ SUITE amp tid PEH Freescale s Processor Expert landing page http www freescale com webapp sps site prod summary sp code PROCESSOR EXPEHT amp tidZPEH http www processorexpert com Freescale Software amp Tools website http www freescale com webapp sps site homepage jisp code DEVELOPER HOME Freescale Component Store purchasing embedded software http www freescale com webapp sps site homepaae jsp code BEAN STORE MAIN amp tidZSWnT 4 N 9 9 C TM mr p r e es a e Freescale the Freescale logo AltiVec C 5 CodeTEST CodeWarrior ColdFire ColdFire C Ware the Energy Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC ji 40 Processor Expert QorlQ Qorivva StarCore Symphon y and VortiQa are trademarks of Freescale Semi
121. y Efficient Solutions logo Kinetis mobileGT PEG PowerQUICC i 9 8 Processor Expert QorlQ Qorivva StarCore Symphony and VortiQa are trademarks of Freescale Semiconductor Inc Reg U S Pat amp Tm Off Airfast BeeKit BeeStack CoreNet t HR zk Flexis Layerscape MagniV MXC Platform in a Package QorlQ Qonverge QUICC Engine Ready Play SafeAssure the SafeAssure logo SMARTMOS Tower TurboLink Vybrid and Xtrinsic are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners 2013 Freescale Semiconductor Inc Configure ipv4 src Classification Entries 1 Select the ipv4 src classification 2 Qo to the Entries tab in Property Panel 3 Set ethernet dst Classification2 on miss entry Properties Classification Classification Entries IP Fragmentation Entries Destination Type Mame Condition Action IP Fragmentation OManiFQR 1 on hik Enqueue Mane OManiFOR 1 on hit Enqueue Mone OManiFOR 1 on hit Enqueue Mone Classification Classification an miss Goto Classificationz OMan an miss Add drop entry 4 To FQIDs1 1 Data Ox20EEEE20 Mask FFOOOOFF Queue base 0000002B 2 Dataz0x30303030 Mask FFFFFFFF Queue basez0000002C 3 Dataz0x10101010 Mask FFFFFFFF Queue basez0000002D e poss 2 freescale Fre Bak the Freescale logo Pelr C 5 CodeTEST CodeWar pecus ColdFire een rae s Fieri ent Solutions lo 99 Proc Expert ot Cor a Star

QorIQ Configuration Suite Tool Introduction

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