EDOSK2674 User Manual - Digi-Key
Contents
1. 55 19 conduire 20 6 1 FEASA PROGRAMMING itai centi te t tecta ra iet t t HE arant tatao irc e 20 6 2 TES MENU ette teta tene tetuer e t e dtd e rt 20 6 3 HBEEMONITOR tte eo t eite tete e e od e tabe redi Det 20 IE DR D 21 fA EDOSK2674 MEMORY MAP nenne rte t tee e rte 21 7 2 8 2674 REGISTER CONFIGURATION eee 23 8 e PVT T MET TALL 33 9 DESIGNING AN EXPANSION CARD vese sess sese ss eves vese nennen ente ennenen tette nsn so sa sensn nnn nnn 34 9 1 RE eee aidera te RT nad 34 9 2 FUNCTIONAL 10 ADDITIONAL 1 1 INTRODUCTION EDOSK2674 is an Evaluation Development Operating System Kit designed around the Hitachi H8 2674R microcomputer MCU The EDOSK2674 operates from a single 5V supply Only two modes of operation Boot mode and Normal mode 33MHz bus clock speed The EDOSK2674 card provides the following interfaces e serial communication interface up to 115200kbs with no errors e A standard RJ45 Ethernet interface provides connection to2. CKS1 CKSO Initial Value 0 0 0 0 0 0 0 0 Asynchronous 8 bit No Parity 1 Stop bit Clock source 2 Bit Rate Register_2 2 H FFFF89 H FF Bit No 7 6 5 4 3 2 1 0 Bit Name 7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRRO Initial Value 1 1 1 1 1 1 1 1 This register is not used Serial Control Register 2 SCR 2 H FFFF8A H 32 Bit No 7 6 5 4 3 2 1 0 Bit Name TIE RIE TE RE MPIE TEIE CKE1 CKEO Initial Value 0 0 1 1 0 0 1 0 Interrupt settings depend on SW External Clock input 16 times bit rate Smart Card Mode Register_2 SCMR 2 H FFFF8E H F2 Bit No 7 6 5 4 3 2 1 0 Bit Name Reserved Reserved Reserved Reserved SDIR SINV Reserved SMIF Initial Value 1 1 1 1 0 0 1 0 Smart Interface mode not used 28 7 2 4 WATCHDOG TIMER Timer Control Status Register TCSR H FFFFBC 18 Bit No 7 6 5 4 3 2 1 0 Bit Name OVF WT IT TME Reserved Reserved CKS2 CKS1 CKSO Initial Value 0 0 0 1 1 0 0 0 Timer Counter TCNT H FFFFBC write H FFFFBD read H 00 is an 8 bit readable writable up counter TCNT is initialized to H 00 when the TME bit in TCSR is cleared to 0 Reset Control Status Register RSTCSR H FFFFBE HF Bit No 7 6 5 4 3 2 1 0 Bit Name WOVF RSTE Reserved Reserved Reserved Reserved Reserved Reserved Initial Value 0 0 0 1 1 1 1 1
3. To prevent accidental overwriting access of WDT registers is different from other registers The WDT may be used to drive the TIMER LED when the counter overflows This however is a very short period and in order to see the LED with the naked eye the WDT must be forced to overflow repeatedly Example to keep LED on TCSR 7 0xA500 clear lower byte TCSR 0xA578 setup amp Enable the watchdog timer while 1 RSTCSR amp 0x0080 detect overflow and reset WDT RSTCSR 7 0xA500 clear watchdog overflow bit TCSR 0 578 clear overflow bit and enable WDT 7 2 5 O PoRT Port Function Control Register 0 PFCRO H FFFE32 H FF Bit No 7 6 5 4 3 2 1 0 Bit Name 7 56 5 CS4E CS3E 52 1 50 Initial Value 1 1 1 1 1 1 1 1 Enable all CS signals 29 Port Function Control Register 1 PFCR1 H FFFE33 H FF Bit No 7 6 5 4 3 2 1 0 Bit Name A23E 22 A21E 20 19 A18E A17E A16E Initial Value 1 1 1 1 1 1 1 1 Enable all Address lines A21 and A23 used for SDRAM bank select Port Function Control Register 2 PFCR2 H FFFE34 H 0D Bit No 7 6 5 4 3 2 1 0 Bit Name Reserved Reserved Reserved Reserved ASOE LWROE 0 5 Initial Value 0 0 0 0 1 1 0 1 PF6 is designated as AS output pin PF3 is des
4. For information about the H8 series microcomputers refer to the H8 Series Hardware Manual For information about the assembly language refer to the H8 Series Programming Manual Further information available for this product can be found on the HMSE web site at http Avww hmse com products edosk General information on Hitachi microcomputers can be found at the following URL Global http www hitachisemiconductor com 38
5. In Normal mode the Main Flash pages 0 and 1 are mapped to areas 0 and 1 respectively Port pin 33 is not used The Boot Flash may only be accessed in area 7 In Boot mode the Main Flash is mapped to area 1 only and driving Port 33 Low or High selects page 0 or 1 The Boot Flash is duplicated in areas 0 and 7 22 7 2 H8 2674R REGISTER CONFIGURATION 7 2 1 BUS CONTROLLER Bus Width Control Register ABWCR H FFFECO H 81 BOOT or H 80 NORMAL Bit No 7 6 5 4 3 2 1 0 Bit Name ABWT ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABWO Initial Value 1 0 1 0 1 0 1 0 1 0 0 0 1 Note In BOOT mode MCU mode 2 ABWCR is initialized to 1 In NORMAL mode MCU mode 1 ABWCR is initialized to 0 In BOOT mode area 7 and 0 are mapped as 8 bit areas In NORMAL mode only area 7 is mapped as 8 bit area The SDRAM ABW2 is always mapped as 16 bit area Access State Control Registers ASTCR H FFFEC1 H FF Bit No 7 6 5 4 3 2 1 0 Bit Name AST AST6 AST5 AST4 AST3 AST2 AST1 ASTO Initial Value 1 1 1 1 1 1 1 1 areas are designated as 3 state access space Wait Control Registers WTCRAH H FFFEC2 H 27 Bit No 15 14 13 12 11 10 9 8 Bit Name Reserved W72 71 W70 Reserved W62 61 W60 Initial Value 0 0 1 0 0 1 1 1 Area 7 has 2 program wait states inserted Area 6 has 7 program wait s
6. 2MB MODE NORMAL amp BOOT H 400000 H BFFFFF 52 53 54 655 SDRAM 8MB 16 H C00000 H DFFFFF CS6 Expansion board 2MB 8 16 H E00000 H EFFFFF CS7 Boot FLASH note 1 512KB x2 8 H F00000 H F7FFFF CS7 TBD 0 5MB H F80000 H FBFFFF CS7 LAN CHIP note 2 256 H FC0000 H FF3FFF CS7 TBD 208KB H FF4000 H FFBFFF CS7 On Chip RAM note 3 32KB H FFC000 H FFFBFF CS7 External address space 15 KB H FFFCO0 H FFFEFF CS7 Internal I O registers 768B H FFFF00 H FFFF1F CS7 External address space 32B H FFFF20 H FFFFFF CS7 Internal I O registers 224B TABLE 7 1 MEMORY MAP Note 1 The same 512K of Boot FLASH is mapped 4 times over the 2MB area of CSO in Boot mode only and 2 times over the 1MB area Note 2 LAN only occupies 16 bytes 0x0 to but is repeated throughout the 256KB mapped area Note 3 Only if internal RAM is enabled 21 00 20 40 5F 60 7E 80 OF CU DF 0 0000h FEFEh 0000h 0000h 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh Area 0 CS0n Area 1 CS1n Area 2 CS2n Area 3 CS3n Area 4 CS4n Area 5 55 6 CS6n Area 7 57 MAIN Flash page 0 BOOT Flash MAINFash X Portpin Portpin page 1 MAIN Flash MAIN Flash page 0 page 1 x NORMAL amp BOOT FIGURE 7 1 MEMORY MAP
7. H FFFF52 Bit No 7 6 5 4 3 2 1 0 Bit Name Reserved Reserved P35 P34 P33 P32 P31 P30 Initial Value 0 0 X X X X X X Read only value determined by the states of pins P35 to P30 Port 3 Open Drain Control Register P3ODR H FFFE3C H 06 Bit No 7 6 5 4 3 2 1 0 Bit Name Reserved Reserved P350DR P340DR P330DR P320DR P310DR P300DR Initial Value 0 0 0 0 0 1 1 0 126 signals are NMOS open drain Port A Data Direction Register PADDR H FFFE29 H FF Bit No 7 6 5 4 2 2 1 0 Bit Name PADDR PADDR PADDR PADDR PADDR PADDR PADDR Initial Value 1 1 1 1 1 1 1 1 The individual bits of PADDR specify input or output for the pins of port A 0 input 1 output Port F Data Direction Register PFDDR H FFFE2E Bit No 7 6 5 4 3 2 1 0 Bit Name PFDDR PFDDR PFDDR PFDDR PFDDR PFDDR PFDDR PFDDR Initial Value 1 1 1 1 1 1 1 0 The individual bits of PFDDR specify input or output for the pins of port F 0 input 1 output Set all as outputs except PFO WAITn Port G Data Direction Register PGDDR H FFFE2F H OF Bit No 7 6 5 4 3 2 1 0 Bit Name Reserved PGDDR PGDDR PGDDR PGDDR PGDDR PGDDR PGDDR Initial Value 0 0 0 0 1 1 1 1 The individual bits of PGDDR specify input or output for the pins of port 0 input 1 output 31 Port H Data Direction Register PHDDR H F
8. a Local Area Network includes Link and Activity indicators e A140 way high density connector for interface to a bus expansion card e Position for a 50 way Auxiliary I O header to allow connection to all unused MCU I O pins and power The EDOSK2674 card is provided with the following memory types and densities e 512KBytes 8 bit x 512 Boot Flash memory e 4MBytes 16 bit x 2M Main Flash memory e 8MBytes 16 bit x 4bank x 1M SDRAM memory A Real time clock RTC is fitted to the EDOSK2674 to provide current date and time information to the MCU EDOSK2674 GENERAL BOARD LAYOUT The general board layout shows the position of all major parts of the board 100 00mm Auxiliary I O NOT FITTED 5 Input E Main RTC Xtal FLASH POWER E TIMER LAN Rj45 SDRAM xl BOOT 8MB H8S 2674R LAN Controller Xtal 74 Jumpers 02 616 74 Serial Port 259 125 Boot FLASH 74 J8 S nin OO RTC_BATTERY 512KB 14 NMI Battery 140 Expansion Connector Reset j e RESET 160 00mm Figure 1 1 EDOSK General Board Layout 1 2 EDOSK2674 AcTUAL BOARD LAYOUT The actual board
9. at present SW has not been developed to enable a HDI monitor for the EDOSK2674 However _ monitor enable jumper has been provided for this future feature This jumper drives MCU port pin 30 Low when fitted and High when not fitted HDI Monitor code may be integrated with the user code and read the monitor enable jumper setting to enable or disable the feature 20 7 SOFTWARE The following map and register settings are for the H8 2674R fitted to the EDOSK2674 as standard i e with a system clock frequency of 33MHz Registers are subject to change depending on the software requirements 7 1 EDOSK2674 Memory The addressable memory address space is split into eight areas each capable of addressing 2Mbytes Each area has a dedicated chip select signal CSOn CS7n Note that these signals are only enabled when PFCRO register bits are set Mode of the system determines which memory resides in areas 0 and 1 The following table shows the EDOSK2674 memory map and bus width FROM TO External Area Description Size Bus Width MODE BOOT H 000000 H FFFFF 50 Boot FLASH note 1 512 4 8 H 200000 H 3FFFFF CS1 Port pin Low Main FLASH page 0 2MB 16 H 200000 H 3FFFFF CS1 Port pin High Main FLASH page 1 2MB MODE NORMAL H 000000 H FFFFF CS0 Main FLASH page 0 2MB 16 H 200000 H 3FFFFF 1 Main FLASH page 1
10. be used 16MB maximum A24 and A25 are not connected Data Bus There are 32 Data lines dedicated to the Expansion connector DO to D31 This allows data to be accessed as Byte 8 bit Word 16 bit or long 32 bit EDOSK2674 Limitations DO to D15 may be used Byte or Word access D16 to D31 are not connected Note For an 8 bit mapped area D8 to D15 must be used Read Write Strobe The Expansion connector has a dedicated Read Write signal RWn High indicates a read cycle and Low indicates a write cycle EDOSK2674 Limitations RWn signal is not connected 35 Read Strobe The Expansion connector has a dedicated active low Read strobe RDn EDOSK2674 Limitations RDn signal may be used Write Strobe There are 4 active low Write Enable signals dedicated to the Expansion connector WEOn to WE3n A 32 bit data bus may be separated into 4 bytes the Write Enable signals are used to determine which of those bytes are to be written EDOSK2674 Limitations WEOn may be used to enable write data on DO to D7 WE1n be used to enable write data D8 to D15 WE2n and WE3n are not connected Note For 8 bit mapped area WE1n must be used Bus Strobe The Expansion connector has a dedicated active low Bus strobe BSn When low this signifies the beginning of a bus cycle or it may be used for latching the address while in MPX mode EDOSK2674 Limitations BSn signal may be used Note 852674 does
11. but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers office equipment communicat
12. have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics To all our customers Regarding the change of names mentioned in the document such as Hitachi Electric and Hitachi XX to Renesas Technology Corp The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003 These operations include microcomputer logic analog and discrete devices and memory chips other than DRAMs flash memory SRAMs etc Accordingly although Hitachi Hitachi Ltd Hitachi Semiconductors and other Hitachi brand names are mentioned in the document these names have in fact all been changed to Renesas Technology Corp Thank you for your understanding Except for our corporate trademark logo and corporate statement no changes whatsoever have been made to the contents of the document and these changes do not constitute any alteration to the contents of the document itself Renesas Technology Home Page http www renesas com Renesas Technology Corp Customer Support Dept April 1 2003 24 N SAS Renesas Technology Corp EDOSK2674 USER MANUAL FoR H8 2674R MICROCOMPUTER Preface Cautions 1 This document may be wholly or p
13. layout shows the real position of all components the reference numbers and silk screen labelling FRONT SER m PORT 1 0 SERIAL NUMBER ME 40 an 26 5 52724 S I
14. not support MPX mode Wait There are 4 active low WAIT signals dedicated to the Expansion connector WAITOn to WAIT3n These are used to hold off the bus cycle until the device being accessed is ready To avoid contention the plug in hardware should have the facility to select which of these is to be used EDOSK2674 Limitations WAITOn may be used WAIT1n to WAIT3n is not connected Interrupts There are 8 Interrupt Request signals dedicated to the Expansion connector IRQ1n to IRQ8n These are used to interrupt the main board processor Depending upon the MCU IRQ may be level and or edge triggered To avoid contention the plug in hardware should have the facility to select which of these is to be used EDOSK2674 Limitations IRQ1n to IRQ4n may be used IRQ5n may be used but is also used by the Main Flash IRQ6n to IRQ8n are not connected Direct Memory Access 36 There are 2 request and 2 acknowledge all active low signals dedicated to the Expansion connector DREQOn DREQ1n DACKOn and DACK1n These are used by the plug in hardware to request and acknowledge a faster memory access To avoid contention the plug in hardware should have the facility to select which of these is to be used EDOSK2674 Limitations All DMA signals may be used 37 10 ADDITIONAL INFORMATION For details on how to use Hitachi Embedded Workshop HEW refer to the HEW manual available on the CD or from the web site
15. p e V F 5 z 2 J 4 z ned N ae E ENT SED L 12 E 49v 29 19 9 22 RZ R3 S 215 Z k POWER 3 EP a xs X 512 RT 5 tor m 4 M C8 S Ho o 21154 4 I Ie JL R27 RIS gt Rie R20 RIT c R28 cis 300 7 lE R29 15 5 5 R37 z PZ 544 la s R41 842 24 8 1 2 gt c17 ete R38 M SL N A IS S X Ely 52 R30 II Sm 5 WF R47 _ lL N 35 55 lt s Rta L c27 629 2101 Jis C26 E cp mn R55 R56 i LO R49 15 A C R50 c34 857 U4 U7 C37 o R6 5 R60 6 45 8 di 2 gt u10 R67 1 2 3 4 5 6 7 8 9 X 0 BOOT amp s 99 MON_EN Res 0003681 L NE WEN A D L ISS fe WEN lt 64 C47 E eee R70 16 EDOSK 2674 BATTERY 02002 U PRODUCT LABEL DI EDI Aur _ U12 411 um eese gs C53 L E SIS 219 Sex 12 12 C55 U J7 TEES K C56 k E C57 19 SW2 RESET EXPANSION Europe Ltd ems cro Syst lt 2002 Hitach 05681 01 VERSION 2 Figure 1 2 EDOSK Actual Board Layout 2 EDOSK2674 BLock DIAGRAM The EDOSK2674 is designed around 8 2674 MCU and includes FLASH memory SDRAM real time clock an interface to
16. the user will wish to select the connector type Through holes and surface mount pads allow for a number of connector options e SM pins fitted on top or under the PCB Samtec TSM 125 0X X DV e 5 sockets on top or under the PCB Samtec SSM 125 X DV e Any through hole 50 way connector at 0 1 pitch Conn MCU Pin Symbol Conn MCU Pin Symbol 1 N A No Connect 2 N A 5V 3 131 AVSS 4 N A GND 5 84 P65 6 83 P64 7 82 P63 8 81 P62 9 110 P53 10 113 PG4 11 114 5 12 115 PG6 13 121 VREF 14 122 AVCC 15 117 P40 16 118 P41 17 119 P42 18 120 P43 19 123 P44 20 124 P45 21 125 P46 22 126 P47 23 127 P54 24 93 STBYn 25 129 P56 26 128 P55 27 61 P61 28 130 P57 29 59 P27 30 60 P60 31 57 P25 32 58 P26 33 55 P23 34 56 P24 35 53 P21 36 54 P22 37 51 P17 38 52 P20 39 49 P15 40 50 P16 41 46 P13 42 48 P14 14 Conn MCU Pin Symbol Conn MCU Pin Symbol 43 44 P11 44 45 P12 45 40 P73 46 43 P10 47 36 P72 48 NIA GND 49 50 3V3 TABLE 3 4 AUXILIARY I O CONNECTIONS 15 4 BOARD OPTIONS 4 1 JUMPER LINKS The EDOSK has a two row 8 pin header for selecting operation modes 0 7 MON EN MF WEN wwe 2707 FIGURE 4 1 JUMPER CONFIGURATION As default jumpers for BOOT and MF WEN are fited BOOT Boot Normal Mode Fitted to link pin
17. timekeeping even when power to the board is removed Battery Reference BR1216 CR1216 BR1220 CL1220 CR1220 and BR1225 2 10 SwiTCHES The EDOSK provides two buttons for influencing the operation of the board The purpose of each button is clearly marked next to it Refer to the board layout for positions Section 1 e Reset Switch This button provides the MCU with a timed reset pulse of at least 250mS s NMI Switch The NMI button on this EDOSK provides the MCU with a positive pulse to generate a non maskable interrupt 2 11 INDICATORS Three red LEDs are fitted to the PCB The function of each red LED is clearly marked on the silk screen of the PCB Please refer to the board layout diagram for position information Section 1 POWER When the board is connected to a power source this led will illuminate BOOT When the EDOSK has been placed into Boot mode this LED will illuminate TIMER Dedicated for user control and is driven by the MCU Watchdog Timer Overflow pin 3 EXTERNAL INTERFACES Connector locations and pin orientation for Expansion and Auxiliary IO right angled 50 way IDC is shown below P Ss gt gt Note Auxiliary connector not fitted as standard 3 1 SERIAL INTERFACE The Serial Communication Interface SCI 3 on the MCU directly supports three wire serial interfaces The EDOSK provides the MCU with an external clock source at 1 8432MHz This prov
18. 12 11 10 9 8 Bit Name DRMI Reserved TPC1 TPCO SDWCD Reserved RCD1 RCDO Initial Value 0 0 0 0 0 0 0 0 Bit No 7 6 5 4 3 2 1 0 Bit Name Reserved Reserved Reserved Reserved CKSPE Reserved RDXC1 RDXCO Initial Value 0 0 0 0 0 0 0 0 Idle cycle not inserted 1 State Pre charge CAS latency enabled No wait between RAS and CAS cycles No clock suspend 1 State read data extension cycle Refresh Control Register REFCR H FFFED4 H 0188 Bit No 15 14 13 12 11 10 9 8 Bit Name CMF CMIE RCW1 RCWO Reserved RTCK2 RTCK1 RTCKO Initial Value 0 0 0 0 0 0 0 1 Bit No 7 6 5 4 2 2 1 0 Bit Name RFSHE CBRM RLW1 RLWO SLFRF TPCS2 TPCS1 TPCSO Initial Value 1 0 0 0 1 0 0 0 No wait states between CAS and RAS REF count on 2 2 Enable refresh control No waits for CAS before RAS refresh cycle Self refresh enabled zero states in the precharge cycle immediately after self refreshing 26 Refresh Timer Counter RTCNT H FFFED6 H FF Bit No 7 6 5 4 3 2 1 0 Bit Name RTCNT7 RTCNT6 5 4 RTCNT3 RTCNT2 RTCNT1 RTCNTO Initial Value 1 1 1 1 1 1 1 1 Refresh Time Constant Register RTCOR H FFFED7 H FF Bit No 7 6 5 4 3 2 1 0 Bit Name RTCOR7 RTCOR6 RTCORS RTCOR4 R
19. 2 1 0 OUT HWR 53 WE2 0 OUT No Connect 53 0 OUT No Connect 54 GND GND 54 GND GND 55 WAITO P UP IN WAIT 55 WAIT1 P UP N No Connect 56 WAIT2 P UP IN No Connect 56 WAIT3 P UP N No Connect 57 GND GND 57 GND GND 58 IRQ1 P UP JIN IIRQ1 58 2 P UP N IIRQ2 59 IRQ3 P UP IIRQ3 59 IRQ4 P UP N IIRQ4 60 IRQ5 P UP IIRQ5 60 IRQ6 P UP N No Connect 61 IRQ7 P UP JIN No Connect 61 IRQ8 P UP N No Connect 62 5V 5V 62 5 5V 63 5 5V 63 5 5V 64 NC1 Option Option No Connect 64 5V 5V 65 RES 0 OUT IRESET 65 5V 66 A 5V 5V 66 5 5V 67 At 5V 5V 67 NC2 Option Option No Connect 68 NC3 Option Option No Connect 68 NC4 Option Option No Connect 69 5 Option Option No Connect 69 NC6 Option Option No Connect 70 NC7 Option Option No Connect 70 NC8 Option Option No Connect TABLE 3 3 EXPANSION BUS CONNECTIONS Not buffered output Not buffered input P UP Pull up resistor Expansion cards to be fitted to the EDOSK should use JAE connector KX15 140K2D and should only have discrete components fitted to the under side with a maximum height of 2mm 3 4 AUXILIARY I O HEADER Position for 50 way Auxiliary I O header is provided on the EDOSK to allow connection to all unused MCU I O pins and power This part has not been fitted as standard because it has been recognised that
20. FFF74 H 0F Bit No 7 6 5 4 3 2 1 0 Bit Name Reserved Reserved Reserved Reserved PHDDR PHDDR PHDDR PHDDR Initial Value 0 0 0 0 1 1 1 1 The individual bits of PHDDR specify input or output for the pins of port H 0 input 1 output 32 8 MECHANICAL DRAWING The mechanical drawing has been included here for the user to develop add on boards and face plates 007721 NOIIO NIS3M wwz 5 55 88 90 100 00 7mm HEIGHT RESTRICTION 2 o m M gt m m 2 f 7 gt E m I m 33 9 2 DESIGNING AN EXPANSION CARD MECHANICAL The Expansion Card should be designed using the following dimensions viewed from the top looking through the board at the connector 4 OFF 2 7mm DIAMETER NON PLATED HOLES The JAE connector KX15 140K2D shown is fitted to the under side of the Expansion Card to mate with KX14 140K5D of the main board in this case the EDOSK2674 with board to board space of 7mm Components fitted to the under side of the Expansion Card must have a maximum height of 2mm Both connectors are surface mounted and therefore another KX14 140K5D may be fitted to the top side of the Expansion Card to allow stacking The 4 off 2 7mm holes in the corners are for stand off fixi
21. N FLASH MEMORY circi eee ed e rede des 9 26 RAM icit intesa tice Ple de neca tied copa erede retento in e ede ed ovp enel 9 2 7 SDRAM E 9 2 8 LAN CONTROLLER re itr tr e e fb t iren ret tc 9 2 9 REAL TIME GLOGK tre tet ede de fene 10 2 10 SWITCHE S Reate deter eie tdt bein dert dia nde 10 2 T1 INDIGATORS c c n Bat ducts cet A NE a te 10 3 EXTERNAL INTERFACES 11 34 SERIAL IN TERRACE meten tee ten ac een an te Dci be nde Pi oar 11 3 2 inte iet eee ee te 12 9 3 EXPANSION CONNECTOR eere edere ner ret P a beide nee dene 13 34 AUXILIARY VO HEADER iaasa aiat eaan a i eti ee iet ie c cete nt duet 14 4 LUDERE 16 4 7 ree trc Gr tate te eno ee ee t ts 16 42 RIG BACKUP SUPPLY ttn oet e tenete eie et rh rae nente dites 16 4 3 REMOTE SWITOH accidet tette ed eo tte d edite Dn ed En Direct cl bd 17 44 CRYSTAL CHOIGE iint ttt ted ee rhe fate av dria foin 17 4 5 REMOVABLE COMPONENT 2 0 0 18 4 6 ADDITIONAL COMPONENT INFORMATION 202 18 5 lt
22. OSK is set to either Boot or Normal mode In Normal mode the BOOT Flash is designed to reside in area 7 only The BOOT Flash may be removed from its socket to be programmed by a dedicated programmer or alternately it may be programmed in system when the Boot write enable jumper is fitted Details of BSC register settings for the AMD Flash boot memory can be found in section 7 2 Boot Flash access Bus Width 8 bit Access States 3 Wait States 3 Cycle Burst 6 area 0 only Extended CS period and T area 7 only 2 5 MAIN FLASH MEMORY The MAIN Flash memory is a 4MByte device INTEL 28F320J3A and is word accessed The MCU interfaces with the MAIN Flash on reset in area 0 only when the EDOSK is set to Normal mode In Normal mode the MAIN Flash is designed to reside in area 0 and area 1 In Boot mode the MAIN Flash is designed to reside in area 1 only and is paged by driving port pin 33 The Main Flash may be programmed in system when write enable jumper is fitted Details of BSC register settings for the Intel Flash memory can be found in section 7 2 Main Flash access Bus Width 16 bit Access States 3 Wait States 2 Cycle burst 6 2 6 RAM The H8 2674R has 32KB of RAM available on chip This RAM can be enabled or disabled by means of the RAME bit in the system control register SYSCR Initially this RAM is enabled 2 7 SDRAM The H8 2674R external address space areas 2 to 5 has been designated as continuou
23. SK NORMAL mode Mode 2 02 0 MD1 1 00 0 Advanced External Data Bus initial Width is 8 bits EDOSK BOOT mode The H8 2674R has no internal Flash memory On power up the EDOSK mode Boot or Normal selects the Flash memory from which the H8 2674R first accesses 2 3 H8 2674R MICROCOMPUTER The MCU is an H8 2674R derivative of the H8 2600 series microprocessor with an internal 16 bit architecture sixteen 16 bit general registers and 69 basic instructions The MCU contains a number of on chip facilities including 33MHz maximum operating frequency Voltage 3 3V 24 hit external address bus 16 bit external data bus 33MHz max external bus frequency 7 areas of external address space each 2MBytes Supports direct SDRAM interface Various peripheral functions DMA controller DMAC EXDMA controller EXDMAC Data transfer controller DTC 16 bit timer pulse unit TPU Programmable pulse generator PPG 8 bit timer TMR Watchdog timer WDT Asynchronous serial communication interface SCI 10 bit A D converter 8 bit D A converter Clock pulse generator On chip memory 32Kbytes RAM General 1 0 ports I O pins 103 Input only pins 12 2 4 BOOT FLASH MEMORY The BOOT Flash memory is a 512K x 8bit PLCC device AMD 29LV040B and is fitted to a socket on the EDOSK2674 The MCU interfaces with the BOOT Flash on reset in area 0 only when the EDOSK is set to Boot mode The same BOOT Flash is also accessible in area 7 when the ED
24. TCOR3 RTCOR2 RTCOR1 RTCORO Initial Value 1 1 1 1 1 1 1 1 Compare refresh count with OXFF 7 2 2 INTERRUPT CONTROLLER The EDOSK2674 only uses the following interrupts e RQ5n Main Flash IRQ0n LAN Controller e RQ1n IRQ5n Expansion connector e NM Switch Interrupt Control Register INTCR H FFFF31 H 08 Bit No 7 6 5 4 9 2 1 0 Bit Name Reserved Reserved 1 INTMO NMIEG Reserved Reserved Reserved Initial Value 0 0 0 0 1 0 0 0 NMI is rising edge triggered Interrupt Control mode 0 IRQ Pin Select Register ITSR H FFFE16 H FF3F Bit No 15 14 13 12 11 10 9 8 Bit Name 11515 11514 11513 11512 17511 11510 1159 1758 Initial Value 1 1 1 1 1 1 1 1 Bit No H 6 5 4 3 2 1 0 Bit Name ITS7 ITS6 ITS5 ITS4 ITS3 ITS2 ITS1 ITSO Initial Value 0 0 1 1 1 1 1 1 IRQ15 IRQ8 Port 2 IRQ7 6 Port 57 56 IRQ5 IRQO Port 8 27 7 2 3 SERIAL COMMUNICATION INTERFACE 2 Serial Extension Mode Register SEMR H FFFDA8 H 00 Bit No 6 5 4 3 2 1 0 Bit Name Reserved Reserved Reserved Reserved ABCS ACS2 1 50 Initial Value 0 0 0 0 0 0 0 0 Basic Clock is External this register is not used Serial Mode Register 2 SMR 2 H FFFF88 H 00 Bit No 7 6 5 4 2 2 1 0 Bit Name C A CHR PE
25. To our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry 2 NE S AS 8 10 11 12 Notice information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is
26. a local expansion card an interface for IO connections a serial port and a LAN port The figure below shows the block diagram of the EDOSK2674 board Boot DB9 FLASH Female 512KByte H8S 2674R LQFP144 Auxiliary Connector Peripherals Expansion Connector Memory Mapped Peripherals FIGURE 2 1 EDOSK BLOCK DIAGRAM 2 14 POWER SUPPLY The EDOSK hardware requires a power supply of 5V Since total power consumption can vary widely due to external connections port states and memory configuration use a power supply capable of providing at least 500mA at 5V DC 5 The design is specified for evaluation the MCU and so does not include circuitry for supply filtering noise reduction under voltage protection over current protection or reversed polarity protection Caution should be used when selecting and using a power supply The power connector on the EDOSK is a 2 5mm Barrel connector The center pin is the positive connection 0 V 5 FIGURE 2 2 POWER SUPPLY CONNECTION Caution Existing customers using E6000 products note that the polarity of this board is opposite to that for the E6000 Use of the E6000 power supply with this board will damage both board and power supply 2 2 OPERATING MODES The H8 2674R has only two modes of operation set by jumper configuration Mode 1 MD2 0 MD1 0 00 1 Advanced External Data Bus initial Width is 16 bits EDO
27. ace mounted AT cut crystal with another of similar type within the operating frequency of the MCU device Please refer to the hardware manual for the MCU for the valid operating range Another crystal is provided at 16 x 115200 1 8432MHz This crystal output is fed directly into the SCK2 pin of the MCU allowing with correct register settings a fixed serial baud rate of 115200bps with zero errors The user may wish to ignore the serial clock oscillator input and use the system clock for baud rate generation register settings will need to be amended as per the following example Example The following table shows the baud rates and Baud Rate Register BRR setting required for each communication rate using the operating speed of 33 0000MHz default Note that there are no zero error percentages Baud Rate Register Settings for Serial Communication Rates using 33 0000MHz system clock SMR Setting 0 1 2 3 Comm BRR ERR 95 BRR ERR 96 BRR ERR 96 BRR ERR 96 Baud setting setting setting setting 110 145 0 33 300 214 0 07 53 0 54 1200 214 0 07 53 0 54 2400 106 0 39 26 0 54 4800 214 0 07 53 0 54 9600 106 0 39 26 0 54 19200 53 0 54 38400 26 0 54 57600 17 0 54 115200 8 0 54 TABLE 4 1 CRYSTAL FREQUENCIES FOR RS232 COMMUNICATION 4 5 REMOVABLE COMPONENT INFORMATION Analogue and reference voltages to the MCU are as default isolated from the Auxiliary con
28. artially subject to change without notice 2 All rights reserved No one is permitted to reproduce or duplicate in any form a part or this entire document without Hitachi Micro Systems Europe Limited s written permission Trademarks General All brand or product names used in this manual are trademarks or registered trademarks of their respective companies or organisations Specific Microsoft MS and MS DOS are registered trademarks and Windows and Windows NT are trademarks of Microsoft Corporation Document Information Product Code 0003680_11 Version 01 1 Date 21 11 2002 Copyright O Hitachi Micro Systems Europe Ltd 1995 2002 All rights reserved Table Contents TABLE eant 3 EE 5 1 1 EDOSK2674 GENERAL BOARD tentent tente trente treten tenis 5 1 2 EDOSK2674 ACTUAL BOARD LAYOUT enesenn 6 2 EDOSK2674 BLOCK 7 242 POWER SUPP Y dede fate tad reete iata 7 2 2 OPERATING MODES testate treated eet uten e 7 2 3 H8 26 4R MICROGOMPUTER regi e e ce nd e nella 8 224 BOOTFEASHMEMORY ria e indeed A atre ted o diee ed reda ebd ces 8 2 9 MAI
29. cess the CSn and address assertion period Th is extended CSACRL H FFFEC9 H 80 Bit No 7 6 5 4 3 2 1 0 Bit Name CSXT7 CSXT6 CSXT5 CSXT4 CSXT3 CSXT2 CSXT1 CSXTO Initial Value 1 0 0 0 0 0 0 0 In area 7 basic bus interface access the CSn and address assertion period Ti is extended 24 Burst Interface Control Register BROMCRH H FFFECA H D3 BOOT or H A3 NORMAL Bit No 7 6 5 4 3 2 1 0 Bit Name BSRMn BSTSn2 BSTSn1 BSTSnO Reserved Reserved BSWDn1 BSWDnO Initial Value 1 1or0 0 or 1 1 or 0 0 0 0 0 Area 0 burst ROM enabled with maximum of 4 words In BOOT mode 6 cycle burst states are used In NORMAL mode 3 cycle burst states are used BROMCRL H FFFECB H A3 Bit No 7 6 5 4 3 2 1 0 Bit Name BSRMn BSTSn2 BSTSn1 BSTSnO Reserved Reserved BSWDn1 BSWDnO Initial Value 1 0 1 0 0 0 0 0 Area 1 burst ROM enabled with maximum of 4 words 3 cycle burst states are used Bus Control Register BCR H FFFECC H 0100 Bit No 15 14 13 12 11 10 9 8 Bit Name BRLE BREQOE Reserved IDLC ICIS1 ICISO WDBE WAITE Initial Value 0 0 0 0 0 0 0 1 Bit No 7 6 5 4 3 2 1 0 Bit Name Reserved Reserved Reserved Reserved Reserved ICIS2 Reserved Reserved Initial Value 0 0 0 0 0 0 0 0 Externa
30. granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this document
31. ides a fixed baud rate of 11520kbps for the serial port with zero errors irrespective of the operating crystal frequency A hyper terminal link between the EDOSK and a PC will enable the user interface e Link to a Hyper Terminal e Connect at baud rate 115200 8 bits no parity 1 stop bit The EDOSK RS232 interface conforms to Data Communication Equipment DCE format allowing the use of 1 1 cables when connected to Data Terminal Equipment DTE such as an IBM PC Handshaking is not supported as standard on the MCU so for normal use a minimal three wire cable can be used The minimum connections are not shaded in the following table EDOSK DB9 Signal Host DB9 Connector Pin Connector Pin No Connection EDOSK Tx Host Rx EDOSK Rx Host Tx No Connection Ground No Connection No Connection No Connection No Connection Qo a rp lt CO ojo 2 TABLE 3 1 RS232 INTERFACE CONNECTIONS 3 2 LAN INTERFACE Figure 3 1 EDOSK Serial Port Pin Numbering A 10MHz LAN connection is provided through a standard RJ45 interface Two LEDs are integrated into the Ethernet connector and give the following indication Green Link Indicator Reflects the integrity status Yellow Activity Indicator Activated by Transmit or Receive activity Pin Name Direction Description RJ1 TxD Output from the EDOSK Transmit Data Positive RJ2 TxD O
32. ignated as LWR output pin P35 is designated as SDRAM CKE output pin PF75 to PF70 are designated as DMAC control pins MCU Port3 Signal Name Function 30 MON ENn Monitor Enable Active Low Enables monitor functions embedded in software 31 I2C_SCL 2 bus serial clock for RTC 32 I2C_SDA 12C bus serial data signal to from RTC 33 MFLASH_PAGE Main Flash page select Used in Boot mode only Low selects page 0 High selects page 1 34 SDRAM_CSn SDRAM chip select Active Low Enables the SDRAM device 35 SDRAM_CKE SDRAM clock enable Active Low Enables the SDRAM clock input Port 3 Data Direction Register P3DDR H FFFE22 H 3A Bit No 7 6 5 4 9 2 1 0 Bit Name Reserved Reserved P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial Value 0 0 1 1 1 0 1 0 The individual bits of P3DDR specify input or output for pins of port 3 0 input 1 output Port 3 Data Register P3DR H FFFF62 H 00 Bit No 7 6 5 4 3 2 1 0 Bit Name Reserved Reserved P35DR P34DR P33DR P32DR P31DR P30DR Initial Value 0 0 0 0 0 0 0 0 P3DR stores output data for the port 3 pins 30 Enable SDRAM CS Port 3 Register PORT3
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34. l bus release and bus request disabled no idle cycles inserted WAIT pin enabled DRAM control register DRAMCR H FFFEDO H 84B4 Bit No 15 14 13 12 11 10 9 8 Bit Name OEE RAST Reserved CAST Reserved RMTS2 RMTS1 RMTSO Initial Value 1 0 0 0 0 1 0 0 Bit No 7 6 5 4 3 2 1 0 Bit Name BE RCDM DDS EDDS Reserved MXC2 MXC1 MXCO Initial Value 1 0 1 1 0 1 0 0 OE CKE signal output enabled RAS is asserted from falling edge in cycle 2 state column address cycle Continuous synchronous DRAM space Access in fast page mode 8 Bit shift Row address bits A23 to A12 used for comparison The precharge sel is A15 to A12 of the column address 25 SDRAM Notes Prior to using the SDRAM the mode must be set in the SMR SDRAM Mode Register The SMR should be set to the value B 0000 0010 0000 CAS latency 2 Burst 1 This is achieved by a write cycle to the SDRAM at an address equal to the required SMR value when in configuration mode The address to set the SMR should be 400040 SDRAM starts at area 400000 and the SMR value must be shifted to compensate for word access Example 1 Configure all other SDRAM Registers 0x85B4 SMR configuration mode SDRAM CONTROL 0 where SDRAM CONTROL is 400040 DRAMCR 0x84B4 Return to SDRAM operating mode DRAM Access Control Register DRACCR H FFFED2 H 0000 Bit No 15 14 13
35. ly from powering all of the board when powered down D2 provides protection for the cell battery or auxiliary supply against accidental charging R when fitted allows charge current to be selected or charging by the RTC device The following options are available Backup power option Component configuration Comments No cell battery No auxiliary supply D1 and D2 fitted Default configuration aestas spp sanet Rr UN Rechargeable cell battery D1 and D2 fitted Default configuration Recnat arable Banz R not fitted No method of recharging cell or auxiliary supply D1 fitted Backup supply is charged through D1 D2 optional RTC trickle charge is not used R 3 3 lcharge D1 not Fitted Backup supply is charged through D2 optional RTC trickle charge network R 0 ohms EDOSK will not operate if backup supply fails 4 3 REMOTE SWITCH Both Reset and NMI switches may be activated remotely By attaching 2 pin headers to J10 and J9 normally open switches can be attached via flying leads J10 NMI J9 RESET The NMI switch signal is de bounced on the EDOSK board with a time constant Trc 0 47 seconds The RESET switch signal is de bounced on the EDOSK board with time constants Tre o 0 03 seconds Tre on 0 22 seconds 4 4 CRYSTAL CHOICE The MCU crystal frequency has been chosen to support the fastest operation The value of the crystal is 33 0000MHz The user may replace the HC49 U surf
36. nector by not fitted 0805 resistors To make this connection the following resistors must be removed and re soldered or replaced in the alternative positions detailed below H8 2674R pin Remove Fit Resistor Value AVCC pin 122 R25 R9 00 0805 AVSS pin 131 7 R8 00 0805 VREF pin 121 R11 R10 00 0805 Care must be taken not to damage the tracking around these components Only use soldering equipment designed for surface mount assembly and rework 4 6 ADDITIONAL COMPONENT INFORMATION The addition of a 00 resistor fitted in position R37 will permanently deactivate the Main Flash This is to be used when 50 and or CS1n are to be used by an Expansion Board 5 START UP INSTRUCTIONS 1 Connect the EDOSK to a PC or notebook computer equipped with a nine pin D connector using a direct 1 1 cable supplied HOST PC EDOSK kn FIGURE 5 1 SERIAL CONNECTION TO PC NOTEBOOK WITH DB 9 CONNECTOR SUPPLIED Open a Hyper terminal set to a baud rate of 115200 8 bits no parity and 1 stop bit Connect a power supply of 5V capable of providing at least 500mA supplied Center ve Check Boot Flash Write Enable setting No jumper fitted to J5 pins 1 2 Check Main Flash Write Enable setting Jumper is fitted to J5 pins 3 4 Check Monitor Enable setting No jumper fitted to J5 pins 5 6 Check Boot Mode set
37. ngs FUNCTIONAL Consideration must be given to the following connecting signals Reset Signal The Expansion connector has a dedicated active low Reset signal RESn When low all devices fitted to the plug in board should be reset EDOSK2674 Limitations RESn signal may be used System Clock The Expansion connector has a dedicated System Clock signal CKIO 34 This clock may be used for bus cycle timing but may vary frequency depending upon the main board used It is recommended that this clock is correctly terminated and or buffered if being used EDOSK2674 Limitations CKIO signal may be used but is not buffered Chip Select There are 7 active low chip select signals dedicated to the Expansion connector 0 to CS6n Theses are used to select 7 areas of external memory To avoid contention the plug in hardware should have the facility to select which of these is to be used EDOSK2674 Limitations BOOT mode H8 mode 2 8 bit 50 may be used if the AMD Boot Flash is removed CS1n may be used if R37 00 resistor is fitted NORMAL mode H8 mode 1 16 bit 50 and CS1n be used if R37 00 resistor is fitted Note that in this mode areas 0 and 1 can not be isolated CS2n to CS5n are not connected CS6n may be used Address Bus There are 26 Address lines dedicated to the Expansion connector A0 to A25 This allows for address mapping of 2 26 Bytes 64MB EDOSK2674 Limitations 0 to A23 may
38. nnect 21 028 T UO Connect 21 29 O No Connect 22 030 No Connect 22 031 T 23 33V 3 3V 23 3 3 3 3V 24 33V 3 3V 24 3 33V 3 3V 25 0 Option Option No Connect 25 33V 3 3V 26 0 0 OUT 0 26 M 0 OUT A1 27 2 0 OUT 2 27 0 OUT A3 28 4 0 OUT A4 28 5 0 OUT 5 29 6 0 OUT 29 0 OUT 30 GND 30 GND GND 31 8 0 OUT AB 31 9 0 OUT A9 32 A10 0 OUT 10 32 11 0 OUT A11 33 A12 0 OUT A12 33 1 0 OUT A13 34 A14 0 OUT 14 34 15 0 OUT A15 35 GND GND 35 GND GND 36 A16 0 OUT 16 36 A17 0 OUT A17 37 A18 0 OUT 18 37 19 0 OUT A19 38 20 0 OUT A20 38 21 0 OUT A21 39 A22 0 OUT A22 39 23 0 OUT A23 40 A24 No Connect 40 25 0 OUT No Connect 41 GND GND 41 GND 42 DACKO 0 OUT IDACKO 42 DACK1 0 OUT IDACK1 43 DREQO 1 P UP JIN IDREQO 43 DREQ1 P UP IN IDREQ1 44 GND GND 44 GND GND 45 50 O P UP OUT 50 45 51 P UP OUT ICS1 46 52 0 OUT No Connect 46 53 0 OUT No Connect 47 CS4 0 OUT No Connect 47 CS5 0 OUT No Connect 48 56 O P UP OUT 56 48 RIW 0 OUT No Connect 49 GND GND 49 GND GND 50 RD 0 OUT IRD 50 BS 0 OUT IAS 13 Col A Assignment Type UO 852674 Col Assignment Type 1 0 852674 51 GND GND 51 GND GND 52 WEO 0 OUT IL WR 5
39. s 8 7 Boot Mode MCU initialises in 8 bit mode and boots from the 512KB Boot FLASH Not fitted Normal Mode Micon initialises in 16 bit mode and boots from the 4MB Main FLASH MON EN Monitor Enable Fitted to link pins 6 5 Enables the Hitachi monitor when included in user code Not fitted Program code runs with no monitor MF WEN Main FLASH Write Enable Fitted to link pins 4 3 Allows the Main FLASH to be written to by the MCU Not fitted Main FLASH is write protected BF WEN Boot FLASH Write Enable Fitted to link pins 2 1 Allows the Boot FLASH to be written to by the MCU Not fitted Boot FLASH is write protected 4 2 Backup SUPPLY Without a backup supply to the RTC time and date information is lost when the board is powered down Two options are available on the EDOSK 1 battery may be fitted 2 Anauxiliary supply of 1 3V to 3 6V may be provided to J8 a 2 pin through hole header not fitted Each of these options may or may not be rechargeable If however neither option is used or the backup supply falls below 1 3V then the EDOSK board will cease to function when powered up unless a supply from Vcc is provided By default design this supply from Vcc is provided The Following diagram shows the circuit used for the RTC backup supply RTC Backup Cell Battery J8 D1 provides the Vcc supply and prevents the cell battery or auxiliary supp
40. s Synchronous DRAM space An 8MB external SDRAM interfaces directly to the MCU The SDRAM used is a MICRON MT48LC4M16A2 Row addressing 4K A0 A11 Bank addressing 4 BAO 1 Column addressing 512 A0 A8 MCU port pin 34 is used to drive the SDRAM CS pin Details of BSC and DRAM register settings for the SDRAM can be found in section 7 2 SDRAM access Bus Width 16 bit 2 8 LAN CONTROLLER The LAN controller IC is a SMSC LAN91C96 device The base address of this device defaults to 300h however the EDOSK re maps this to F80000h The MAC address is contained within a removable EEPROM connected to the Controller This is programmed during production testing and should not be altered Details of BSC register settings for the LAN controller can be found in section 7 2 LAN Controller access Bus Width 8 bit Access States 3 Wait States 3 Extended CS period and 2 9 REAL CLOCK EDOSK is supplied with Real Time Clock and battery backup when fitted for current date and time information A cell retainer J11 is used to hold a cell battery to keep time data correct when system supply is removed The RTC is a Dallas Maxim 0516721 device that interfaces to the H8 2674R via 12 bus SCL Serial Clock MCU port pin 31 SDA Serial Data MCU port pin 32 coin cell battery between 1 3V and 3 6V of 12mm diameter and 3 175mm maximum height may be inserted into the EDOSK to allow
41. tates inserted WTCRAL H FFFEC3 H 77 Bit No 7 6 5 4 3 2 1 0 Bit Name Reserved W52 W51 W50 Reserved W42 W41 W40 Initial Value 0 1 1 1 0 1 1 1 Area 5 has 7 program wait states inserted Area 4 has 7 program wait states inserted 23 WTCRBH H FFFEC4 H 71 Bit No 15 14 13 12 11 10 9 8 Bit Name Reserved W32 W31 W30 Reserved W22 21 W20 Initial Value 0 1 1 1 0 0 0 1 Area 3 has 7 program wait states inserted SDRAM has a CAS Latency of 2 WTCRBL H FFFEC5 H 23 BOOT or H 22 NORMAL Bit No 7 6 5 4 3 2 1 0 Bit Name Reserved W12 11 W10 Reserved W12 11 10 Initial Value 0 0 1 0 0 0 1 1or0 Area 1 has 2 program wait states inserted In BOOT mode area 0 has 3 program wait states inserted In NORMAL mode area 0 has 2 program wait states inserted Read Strobe Timing Control Register RDNCR H FFFEC6 H 00 Bit No 7 6 5 4 3 2 1 0 Bit Name RDN7 RDN RDN RDN RDN RDN RDN RDN Initial Value 0 0 0 0 0 0 0 0 In all areas the RD signal is negated at the end of the read cycle CS assertion Period Control Registers CSACRH H FFFEC8 H 80 Bit No 7 6 5 4 3 2 1 0 Bit Name CSXH7 CSXH6 CSXH5 CSXH4 CSXH3 CSXH2 CSXH1 CSXHO Initial Value 1 0 0 0 0 0 0 0 In area 7 basic bus interface ac
42. ting Jumper is fitted to J5 pins 7 8 Cor XU DUO Lene day Switch Power on 6 CODE DEVELOPMENT Incorporated into the mot file that is programmed into the Boot Flash device is the option to run the Embedded Test Suite software ETS This software is available to the user via a hyper terminal link and contains a number of functions including the choice of testing the major functions of the EDOSK and the option of downloading user software to both the AMD and INTEL Flash devices 6 1 FLASH PROGRAMMING EDOSK hardware allows both Boot and Main Flash memory to be programmed in system when the appropriate write enable jumpers are fitted When the EDOSK is first powered up in Boot mode and a serial connection has been made to a hyper terminal the user will be given the option to re program Flash devices The user may specify any valid S Record file to be programmed 6 2 TEsT MENU The tests incorporated in the Boot Flash allow for a majority of the EDOSK to be verified for production and for prototype debugging Three main menu options are given to Program Flash Testing and Diagnosis These lead to further menu options as shown below PROGRAM TESTING DIAGNOSIS FLASH Boot Flash Main Flash P SDRAM Ethernet loop back Local loop back p Connector loop back Configure MAC RTC Timer LED amp NMI 6 3 HDI MoNITOR The H8 2674R has no dedicated debug port and
43. urther Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products or if you
44. utput from the EDOSK Transmit Data Negative RJ3 RxD Input from the LAN Receive Data Positive RJ4 N C Not Connected RJ5 N C Not Connected RJ 6 RxD Input from the LAN Receive Data Negative RJ7 N C Not Connected RJ8 N C Not Connected SS Figure 3 2 EDOSK LAN Port Pin Numbering TABLE 3 2 LAN INTERFACE CONNECTIONS 12 3 3 EXPANSION CONNECTOR The EDOSK expansion bus connector is a 140 way JAE KX14 140K5D and has the following pin connections Col A Assignment Type UO 852674 Col Assignment Type 1 0 852674 1 GND GND 1 GND GND 2 0 OUT 2 GND GND 3 GND GND 3 GND GND 4 100 1 0 00 4 101 T 1 0 D1 5 102 1 0 D2 5 03 T 1 0 D3 6 104 1 0 D4 6 105 T 05 06 T 1 0 D6 7 07 T 1 0 D7 8 GND 8 GND GND 9 108 T 1 0 D8 9 109 T 09 10 010 1 0 D10 10 011 O D11 11 1012 1 0 D12 11 1013 O D13 12 014 1 0 D14 12 015 T O D15 13 GND GND 13 GND GND 14 016 1 0 No Connect 14 017 T O No Connect 15 1018 T No Connect 15 019 T O No Connect 16 1020 T UO No Connect 16 021 T O No Connect 17 1022 T UO Connect 17 023 O No Connect 18 GND 18 GND GND 19 1024 1 0 No Connect 19 025 T O No Connect 20 026 1 0 No Connect 20 D27 T O No Co
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