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AnadigmVortex FPAA Family User Manual

1. CFGFLGb OUTCLK e ee DIN Figure 12 SPI EPROM Initial Timing Sequence ERRb is an open drain bi directional pin driven active low during reset On the 8th rising ACLK edge the FPAA releases ERRb and then monitors the state of the pin as an input CFGFLGb is asserted one ACLK after detection of a valid logic high on ERRb In the timing example shown above ERRb pulls up to a valid logic high in time to be detected as a logic high by the 9th rising ACLK edge accordingly the FPAA asserts CFGFLGb low on the 10th rising ACLK edge A high frequency ACLK or any combination of high load capacitance or weak pull up on the ERRb node may cause the node to pull high more slowly than shown in this example In such situations it is still the case that CFGFLGb will not assert low until one ACLK after a valid logic high is detected on ERRb As th e s ystem s power supply first beg ins to ramp up the ACL K CF GFLGb an d O UTCLK signals are unknown The device s internal Power On Reset circuitry asserts and gets everything into a known state The FPAASs oscillator has a typical start up time of less then 10 mS and the POR circuitry will conclude within 30 mS Note This diagram is not to scale At an ACLK rate of 2 MHz the entire Primary Configuration occurs within 3 mS of the internal PORb de assertion Serial data is sourced by the SP EPROM on the falling edge of ACLK Setup time of DIN to A
2. yy Master Clock Select Figure 22 System Clocks as Directed by MODE Pin DCLK is the digital clock input A crystal attached to this input will be detected automatically and used as the tuning element of the on chip oscillator otherwise it may be driven directly The DCLK is signal is used to drive the configuration logic and may also be used as the master clock source for the analog clocks in MODE 0 ACLK SPIP is an optional clock in put that can be us ed to serve as the master clock for the analog clock domains within the device In MODE 1 ACLK SPIP is an output which is a divided down version of the DCLK input T he intended connection is to a serial memory device s clock input Regardless of MODE setting at the b eginning of c onfiguration O UTCLK SPIMEM s ources a s erial da ta bitstream designed to setup a 25 series SPI EPROM for read The intended connection is to the MOSI Master Out Slave In pin ofa S PI EP ROM Once configuration completes O UTCLK SPIMEM reverts to serving as an analog clock or comparator output port DOUTCLK is a buffered version of DCLK SPI EPROM AN12x AN22x AN12x AN22x MISO Y DIN ACTIVATE L_4 DIN ACTIVATE SCLK K _q ERRb ERRb a Po MOSI k PORb CFGFLGb PORb CFGFLGb csbk CS2b CS2b EXECUTE EXECUTE CS1b 3 CS1b E LCCb LCCb __ ACLK DOUTCLKL_ _ ________J acLk DOUTCLK lt 16 MHz LU
3. A iit Oily Andog Sich Fabre na Ae signal paths ensure high fidelity operation The Connects any CAB to any Output Cell i 3 f Ep7 second ge neration An adigmVortex ar chitecture o at oe SE L EP 2 pvop provides a significantly improved signal to noise a 38 HE hgn ratio as well as higher bandwidth a Es El CAB1 CAB2 E opts 102P E Bl 8 ERRb 1 3 R n N E y H emet Thesede vicesa ccommodatenon linear El s ey ec functions such as sensor response linearization or 7 SS ale i 3 O giz and arbitrary waveform synthesis i ale x gt E E E cstb 104PA dy P n CABEN osa The A Nx27 S onicMaster se ries i s specially IO4NA a P 2 ts A ors Ja E ass optimized for op timal p erformance thr ough th e en audio ban d pr oviding ne ver bef ore possible 104PC iL a qe Look Up Table audio system design options 104ND BVSS 1 Open Drain Output 2 Programmable Internal Pull Up 3 10KQ External Pull Up Recommended VREFPC VMRC VREFNC Some of the notable features of the Anadigmvortex solution include e Analog design time reduction from months to minutes Faster time to solution compared to discretes or ASIC e High precision operation despite system degradation and aging e Eliminating the need to source and maintain multiple inventories of product Ability to implement multiple chip configurations in a single device and to adapt functionality in the field
4. BANK ADDRESS BYTE Bit Number 76543210 BANK ADDRESS Starting bank address of Shadow SRAM to be loaded The BYTE and BANK Address bytes taken together form the starting Shadow SRAM or LUT SRAM load address for the subsequent block of configuration data The memory within the device is organized as 18 rows banks by 32 columns bytes No special handling is required to cross bank or byte boundaries this is auto matic The address allocation of the device s Shadow and LUT SRAM is shown in the figure below BANK BYTE ADDRESS ADDRESS 1p1p1p1p1 1 1 1 1 1 1 1 1 1 1 1 0 0O JO0O OJO OJOJOJOJOJOJOJOJOJOJO FJEJ D C B JA 9 8 7 6 5 4 3 2 1 O F E D C B A 9 8 7 6 5 4 3 2 1 0 00 Lower Auxiliary Shadow SRAM Bank 01 Upper Auxiliary Shadow SRAM Bank 02 CAB 1 Lower Shadow SRAM Bank 03 CAB 1 Upper Shadow SRAM Bank 04 CAB 2 Lower Shadow SRAM Bank 05 CAB 2 Upper Shadow SRAM Bank 06 CAB 3 Lower Shadow SRAM Bank 07 CAB 3 Upper Shadow SRAM Bank 08 CAB 4 Lower Shadow SRAM Bank 09 CAB 4 Upper Shadow SRAM Bank 0A 0F 10 Look Up Table SRAM Bank 0 11 Look Up Table SRAM Bank 1 12 Look Up Table SRAM Bank 2 13 Look Up Table SRAM Bank 3 14 Look Up Table SRAM Bank 4 15 Look Up Table SRAM Bank 5 16 Look Up Table SRAM Bank 6 17 Look Up Table SRAM Bank 7 18 FF Figure 18 AN12x and AN22x Memory Allocation Table Copyright O 2004 Anadigm Inc All Ri
5. NULL postfix NULL prefix NULL postfix Figure 15 Multi Device SPI EPROM Boot Handoff Figure 14 shows just two FPAA s in the configuration chain The common wired AND ACTIVATE signal pulls high only when the second device completes its configuration and releases it The initial sequence is the same as shown in Figure 12 During a multi device configuration the first several clocks of the configuration sequence for the second device provide the edges needed for the first device to complete its configuration The first device therefore does not require a NULL postfix byte but itis part of a standard configuration data set The clocks associated with a NULL post fix byte are however required at the end of the con figuration load for the sec ond device AnadigmDesigner2 provides these extra for clocking only prefix and postfix NULL bytes In Figure 14 the first device generates the analog clock DCLK 16 which is used by both devices Note the different settings of the mode pins to achieve this Please reference Figure 22 for further detail 3 2 3 Special Considerations for Use of Pull Ups There are several pins on the F PAA s configuration interface which have programmable internal p ull ups available The ACTIVATE and CFGFLGb internal pull ups are programmed as a pair The DIN pull up is sepa rately programmable In small systems one to three FPAAs the internal pull ups are sufficiently strong for proper operation unde
6. A single ended signal can be used as an input to the cell If a single ended source is attached an internal switch will connect the negative side of the internal differential signal pair to Voltage Main Reference VMR is the reference point for all internal signal processing and is set at 2 0 V above AVSS From 7 Array y ct im DE ble f E 2 Programmable Gain nabo le From PINS Amplifi Arra pie 2 gt To PINS i O Zy Array 101P r Array IO1N gt L 0 ae i IO1N OS i VMR i Chopper Stabilized Amp with Gain 2 n 4 5 6 7 Single Ended Input The output path is not available on the ANx20 devices Figure 2 Fully Featured Input Cell for ANx20 amp ANx21 and Simplified ANx22 amp ANx27 As with any sampled data system it may sometimes be necessary to ow pass filter the incoming signal to prevent al iasing artifacts The input p ath of the A Nx20 an d A Nx21 In put Cell contains a second order programmable anti aliasing filter The filter may be bypassed or set to selected corner frequencies When using the anti aliasing filter Anadigm recommends that the ratio of filter corner frequency to maximum signal frequency should be at least 30 These filters are a useful integrated feature for low frequency signals signals with frequency up to 15kHz only and if high order anti alia
7. Device has completed Primary Configuration LCCb Output 0 Local configuration complete 1 Local configuration is not complete Once configuration is completed it is a delayed version 8 clock cycles of CS1b or if the device is addressed for read it serves as serial data read output port CFGFLGb Input In multi device systems 0 Ignore incoming data unless currently addressed 1 Pay attention to incoming data watching for address O D Output 0 Device is being reconfigured Z Device is not being reconfigured DIN Input Serial Configuration Data Input CS1b Input Prior to completion of a Primary Configuration 0 Allow configuration to proceed 1 Hold off configuration Input After completion of a Primary Configuration Data input pin serves as a serial data pass through port for a multi device chain CS2b Input 0 Chip is selected 1 Chip is not selected EXECUTE Input 0 No Action This pin should normally be tied low 1 Transfer Shadow SRAM into Configuration SRAM depending on configuration settings Figure 20 Pins Associated with Device Configuration Copyright 2004 Anadigm Inc All Rights Reserved 25 UM000221 U001b AN12x AN22x AnadigmVortex FPAA Family User Manual 3 5 1 DOUTCLK When enabled by configuration data the DOUTCLK output provides a buffered version ofDCLK This is useful when using the oscillator fe ature of DC LK in the master d evice of am ulti device system In th is scenario a
8. Figure 12 SPI EPROM Initial Timing Sequence ociccocccnnnocccccnnonononcnnnnnnnnnnnn nono nnnrnnnnnn nn ar nnnn rca rr nn nr narran 13 Figure 13 SPI EPROM Completion Sequence occccccccccccononoononncnncnnnnonnnnnnnnnnnnonnnnnnnnnnnnnnnnnnnnnnnnnnnnrrnnnnannnnnes 14 Figure 14 SPI Master Multi Device Boot ooooonocccccnnnnococccononcccncnnnononnnnn non cnn nro nn nn nr rn nn rra r nn nn rra r rr rra 14 Figure 15 Multi Device SPI EPROM Boot Handoff concccccnnincccccnnccococcnononcnnnnnonono nano nonnn ocn nrnnnnn rca rr nnnn rra 15 Figure 16 Primary Configuration Data Stream Structure ooccccnnnncccccnncocconcnnnonncnnnnnnnnnnn nono naar rra nr rra 17 Figure 17 Device IDs for the AnadigmVortex Family c oooconnnccnnnnnnncocccnnoncncnnonononcnnnnnnnnnnn rra n rca rr nnnn rra rra 18 Figure 18 AN12x and AN22x Memory Allocation Table o ooooconnnnnnccninnnocccccnnnnonancnnnoncna nar nnnnn nana r narrar 20 Figure 19 Update Data Stream Structure srren renanipun eeit ar aae anno nn nr rn AA REAREA EEREN ERRA 22 Figure 20 Pins Associated with Device Configuration ooo noccccnnnnnniccnnnnacccccnnncnrcccnnnnrrc cnn nn 25 Figure 21 Known Compatible Crystals oooooonnnnccconinnccccconononacnno conan o nanonnn cnn nn nnno nn nr nono rra rnnn rra 26 Figure 22 System Clocks as Directed by MODE Pin c ooconncccccnnncoccinoninnnccnno nar ncn nana r cc cnn nn c cnn anar cri 27 Figure 23 Using DOUTCLK in a Multi Device Sy
9. 13 lt 3 gs o io D 1021 k 8 k 2 amp LJ activate 12 D gt c g5 E S kJ EXECUTE e 3 0 pas 103P L n ES a A PORb D gt tc 1 2 an Pi la 5 Sle Ss amp AL crcricp E g l le lt s Oo a 3 E E CS1b Ps 5S CAB3 CAB4 S15 OMe a 3 8 sls als k csab I104NA Ky Sek ole Elo 935 8 DVSS o4PB _ ky Bkysoky 104NB gt 104PC H o Z 272 7 o4nc ky VREF VMR VREF ET loapv p Voltage Refrences OO CSP Table O4ND De gi 00000 l n n Q Oo O Oo 0 1 Open Drain Output 2 2 a a a Z 2 2 Programmable Internal Pull Up TI 0 a a w m 3 10KQ External Pull Up Recommended gt gt Figure 1 Chip Overview for a Typical Four CAB AnadigmVortex FPAA Copyright 2004 Anadigm Inc All Rights Reserved 1 UM000221 U001b AN12x AN22x AnadigmVortex FPAA Family User Manual Analog inputs signals are routed into the FPAA core via any of the four Input Cells The Input Cells can accept either differential pair or single ended signals The fourth Input Cell has a special front end multiplexer which allows for the connection of up to fo ur differential pairs or eight single ended signals ANx20 and ANx21 devices provide optional active signal processing elements in the In put Cells which provide programmable gain and anti aliasing filtering All the Input Cells also provide a direct input path to the FPAA core The ANx20 Input Cell provides only an input path all other family members also provide
10. LTL ADCLK Mope OUTCLK DCLK ope OUTCLK Figure 23 Using DOUTCLK in a Multi Device System Copyright 2004 Anadigm Inc All Rights Reserved 27 UM000221 U001b AN12x AN22x AnadigmVortex FPAA Family User Manual 3 5 6 PORb Power On Reset When PORb is asserted low the device s internal power on reset circuitry is re activated as if the device were being powered up for the first time When utilized as a control signal PORb is normally just pulsed low but it can be held low for an indefinitely long period of time Once PORb is released high the POR circuit completes a normal power on reset sequence and control is handed over to the configuration state machine 3 5 7 ERRb Error This is an open drain input output pin An external pull up resistor should be attached to this pin typically 10 kQ In large multi device systems this pull up may be reduced to 5K to overcome loading effects Initially during po wer up this pin serves as an o utput and is asserted low by the d evice As the power on reset sequence progresses the ERRb pin is released and is pulled up by the external resistor allowing the configu ration sequence to commence If there is more than one FPAA in a system then the ERRb pins should be tied together This forces power up to be de layed until ERRb has been released in all devices Different device types will take different times to powe r up The rising ed ge of ERRb is the refore us ed
11. Output gt gt or Factory Test Input DCLK Chopper Clock lt _ Chopper Config Crystal External Clock lt 40 MHz Clock Logic Oscillator lt or Divider Crystal lt 20 MHz oo ACLK SPIP Analog Clocks 3 0 ae Dividers lt Optional Analog Clock Input lt 40 MHz Configuration OUTCLK SPIMEM gt Analog Clock Output sometimes SAR bit clock Figure 7 Clock Features and Clock Domains The analog clock do mains are all sourced from a single master clock either ACLK or DCLK The device configuration determines which clock input will be used as the master clock This master clock is divided into 5 unique domains The first domain sources only the ch opper stabilized amplifiers within the Input Output Cells The other four domains are sourced by a u ser programmable prescaler fe eding four user program mable dividers Each of these domains can be used to drive either the SAR logic of a CAB or the switched capacitor circuitry within the CAB itself The clock generation circuitry ensures that all clocks derived from a single master cl ock signal will synchronize th eir rising ed ges so that there is never any skew between 2 clocks of the same frequency Importantly this holds true for all clocks in a multi device system as well 2 9 Unique CAM Library Features There are some unique CAM Library elements in support
12. PORb CFGFLGb PORb CFGFLGb CSb CS2b CS2b EXECUTE EXECUTE CS1b gt CS1b L LCCb Lech ACLK DOUTCLK E ACLK DOUTCLK ULL lt 16 MHz JDCLK ope OUTCLK ADCLK mope OUTCLK Figure 14 SPI Master Multi Device Boot Tying all the open drain ERRb bi directional pins together ensures that if any one of the devices in the config uration chain detects an error and fails to configure then all of the devices in the chain will be reset and Primary Configuration will start again Likewise all of the devices in the configuration chain also have their open drain ACTIVATE bi directional pins tied together As each device completes it s configuration it ceases to drive the ACTIVATE line low As the last device in the chain completes its configuration it too will cease to drive ACTIVATE low In this manner all the analog circuitry will become active on the next configuration clock after the ACTIVATE line pulls high Copyright 2004 Anadigm Inc All Rights Reserved 14 UM000221 U001b ACLK ACTIVATE wired AND LCCb device1 LCCb device2 DIN OO OOOO OOOO SOOO OOOO nion z k device1_byteN device2_byte0 k device2_byteN 1 k device2_byteN
13. a direct output path Analog output signals are routed out of the FPAA core via either of the two Output Cells or through the Input Cells direct output option ANx20 and ANx21 devices provide optional active signal processing elements in the Output Cells which provide programmable gain and reconstruction filtering The Output Cells also provide a digital output path used for comparator and SAR results data The FPAA can accept either an external clock or generate its own clock using an on chip oscillator and an external crystal Detection of the crystal is automatic The resulting internal clock frequency can be di vided down into fo ur synchronized internal s witched capacitor clocks of different frequencies b y programmable dividers The clock circuitry can also source any of these four clocks as a chip output The behavior of the CABs clocks signal routing Input Cells and Output Cells is controlled by the contents of Configuration SRAM Behind every Configuration SRAM bit is a Shadow SRAM bit The Shadow SRAM of the AN22x devices may be updated without disturbing the currently active analog processing This allows for on the fly modification of one or more analog functions This dynamic reconfiguration is not possible with the AN12x devices The a rchitecture includes a hig hly fl exible digital c onfiguration i nterface T he c onfiguration i nterface is designed to wo rk in stand alone mode by connecting to ei thera common SP ty pe serial
14. by groups Logical Addressing of Multiple FPAAs AN22x Only ADDR1 the primary logical address is established for each device during its Primary Configuration The configuration data itself establishes ADDR2 the alternate logical address for the device Once the Primary Configuration is complete a device will respond to an y Update format configuration data stream which contains either a matching A DDR1 value a matching A DDR2 value or Ox FF inthe TARGET ID byte field The hex address of OxFF serves as a global ID all devices respond to this ID SPI Port Micro GPIO GPIO MOSI GPIO SCLK Clock Source Figure 9 Configuring Multiple Devices from a Host Processor Load Order AN22x AN22x AN22x gt DIN ACTIVATE DIN ACTIVATE DIN ACTIVATE pe ERRb ERRb ERRb PORb CFGFLGb PORb CFGFLGb PORb CFGFLGb CS2b CS2b CS2b EXECUTE EXECUTE i EXECUTE ADDR1 1 ADDR1 2 Jl ADDR1 3 csip ADDR2 X csip ADDR2 X Z Josip ADDR2 Y Foal la LCCb LCCb LCCb ACLK DOUTCLK ACLK DOUTCLK m ACLK DOUTCLKL m DCLK mope OUTCLK DCLK mope OUTCLK i DCLK ope OUTCLK Figure 9 shows a valid connection and configuration example for multiple FPAA s being hosted from a single master SP port Du ring Primary Configuration each de vice in the chain received a un ique ADDR1 and a non unique ADDR2 The ADDR1 s were assigned via the ADDR1 fields
15. crystal is attached to master device s DCLK input rather than driving DCLK with a conventional clock source See Figure 23 for further details Note that the clocks of this master device will be running about 10 ns ahead of all the slaves For this reason the clock master s hould be t he last de vice in the analog chain i e Analog out puts from the clock master device should not be connected to analog inputs of clock slaves When this feature is not used DOUTCLK should be flo ated When this c onfiguration data bit i s not set DOUTCLK becomes a factory reserved test input with an internal pull down Setting this bit disables both the input and the pull down device 3 5 2 DCLK Data Clock The rising edge of the input on the DCLK pin is used to drive the configuration logic Until a clock is supplied the in ternal p ower up procedure c annot b e c ompleted T he ma ximum DCL K frequency is 40 MHz T he supplied clock can be free running or a strobe An inte resting feat ure of th e DCLK in put is thatit may bed riven with a s tandard logic signal or a se ries resonant c rystal can be connected to DV SS T he de vice s on chip os cillator au tomatically detects an attached crystal and uses it to establish a self generated internal clock that can be used by both the configu ration logic and analog portions of the device The allowable frequency range for an attached crystal is between 12 MHz and 24 MHz with 16 MHz being the optimal choi
16. of the Primary Configuration data streams The ADDR2 s were established within the configuration data sets down loaded into each of the devices Once Primary Configurations are complete for all of these devices each will respond to th e host SPI port only if th e TARGET ID fi eld of the Update configuration data stream contains either its ADDR1 or ADDR2 identifiers or OxXFF Assume that two of the devices perform identical analog functions X and the third a unique function Y Also assume that the X and Y configuration data sets contain ADDR2 values of X and Y respec tively During the Primary Configuration the host processor assigned the first device an ADDR1 of 1 and filled that device with the X configuration Likewise the ADDR1 2 device also got the X configu Copyright 2004 Anadigm Inc All Rights Reserved UM000221 U001b AN12x AN22x AnadigmVortex FPAA Family User Manual ration The ADDR1 3 device got the Y configuration Once these Primary Configurations are complete and analog operations go active the host processor may alter via Update both X devices concurrently by using TARGET ID X rather than sequentially by addressing TARGET ID 1 then TARGET ID 2 If the host instead uses OxFF in the TARGET ID field then all three devices will concurrently accept the subsequent reconfiguration data Versions of AnadigmDesigner2 previous to 2 5 refer to ID1 and ID2 rather than ADDR1 and ADDR2 3 1 3 Configura
17. of the hardware differences between the members of the AnadigmVortex family Device Number Unique CAM Library Features ANx20 Extensive standard library comparator differentiator divider filter gain voltage con trolled gain sample and hold integrator multiplier oscillator arbitrary waveform genera tor rectifier square root sum difference amp arbitrary transfer function reference voltage zero crossing detector ANx21 Same as ANx20 plus Analog to Digital Converter SAR ANx22 Same as ANx20 plus Analog to Digital Converter SAR ANx27 Specialized audio signal processing functions Copyright O 2004 Anadigm Inc All Rights Reserved 9 UM000221 U001b AN12x AN22x AnadigmVortex FPAA Family User Manual 3 Configuration Interface The configuration interface provides a flexible solution for transferring data into the configuration memory of the FPAA The interface supports both self booting via a serial EPROM and microprocessor hosted operation Master mode enables the FPAA to self configure from a companion SPI EPROM The FPAA provides all the necessary signaling for the serial transfer of dat a out of reset The Master mode is useful for non hosted stand alone operation where the FPAA functionality is set and forget Slave mode sets the FPAA to present itself as a SPI bus compatible slave The Slave mode is useful when the FPAA is to be configured from a host processor As a slave the FPAA can be configured anytime a
18. simply transferred out of the host s SPI port SPI Port Micro AN12x AN22x DIN ACTIVATE ERRb PORb CFGFLGb CS2b EXECUTE CS1b L LCCb acik DOUTCLK lt 40 MHz LT LTL pa DCLK gpg OUTCLK Figure 8 A Typical Host SPI Port Connection The device s ACTIVATE line is fed back to the host s general purpose input output GPIO pin to provide an indication that the configuration was successful Copyright 2004 Anadigm Inc All Rights Reserved 10 UM000221 U001b The configuration interface is synchronous but there is no requirement for the configuration clock to be unin terrupted For host processors lacking a SPI port a bit banging software emulation of the SPI transfer protocol is perfectly suitable 3 1 2 Multiple FPAAs Connection Details A system may contain an arbitrary number of slaved FPAA devices As with any multi slave SP compatible bus the slaves all connect to the Master s MOSI and SCLK signals in parallel The host micro selects the first device in the chain for configuration The upstream device holds off configuration for the next device down stream in the chain until its configuration is complete as signaled by assertion of its LCCb pin Using this scheme FPAAs are sequentially loaded in the order shown After the P rimary Configuration is complete for each device in the chain the devices can subsequently be ogically addressed by LOGICAL ID individually or
19. the power up state machine takes control Once po wer up is complete the c onfiguration state machine becomes ac tive and configuration proceeds Assume the device is configured and operating normally Driving ERRb low for longer than 15 configuration clock cycles will cause the device to reset The device will become active and configuration can occur once again Assume the device is configured and operating normally with ERRb pulled up high If PORb is driven low the device will reset Holding PORb low keeps the device in a power on reset condition When PORb is finally released to a high state the power on reset circuitry will recognize a rising edge on PORb and be tricked into thinking that the device is powering up The normal power up sequence will repeat On power up internal power on reset circuitry is activated which resets the device s Configuration SRAM and prepares the device for a first or Primary Configuration Primary Configuration then proceeds according to the protocol described later in this document Once completed reconfigurations can be executed as described above In the case of the AN121E04 reconfiguration data is ignored 3 4 Configuration Protocol The serial configuration data no matter how it comes into the device must adhere to the protocol defined in this section A nadigmDesigner2 constructs a c onfiguration d ata file which adh eres to th is protocol so that even for the simplest case of self booting from a
20. to generate a serial data stream and an accompanying sync pulse These two signals can be routed to either of the two dedicated output cells configured in Digital Output mode Only on the ANx21E04 devices offer this direct access to the SAR circuitry 2 7 Voltage Reference and IBIAS Generators All analog signal processing within the device is done with respect to Voltage Main Reference VMR which is nominally 2 0 V The VM R signal is derived from a hi gh precision tem perature co mpensated ban dgap reference source In addition to VMR VREF 1 5 V above VMR and VREF 1 5 V below VMR signals are also generated for the device as shown in the figure below Pkg Pins VREF Z Temperature Voltage gt MREFPO 7 Compensated Reference VMRclean Band Gap amp Reference Current G VMRC Reference ti Generators L O VREFMC EL Note 100nF Tantalum Capacitor To Array I VREF VMRclean and VREF are each used as reference voltages within the analog array VMR is the node onto which all switched capacitors dump charge Figure 6 Voltage Reference and Bias Current Generation There are two versions of VMR routed to the CABs VMR is the node onto which all switched cap acitor charges get dumped and can be relatively noisy VMRclean is also routed to the op amps within the CABs This quiet version of VMR is used by the op amps as the ground reference in order to improve
21. to sy nchronize all FPAAs in the system to the same incoming clock cycle Once ERRb goes high configuration can begin A user can manually delay the start of configuration by externally pulling ERRb low from power up An alternative method for delaying configuration is to hold the CS2b pin high during power up ERRb will not be released until CS2b is taken low ERRb remains high during configuration and reconfiguration unless an error occurs An error condition is indicated by ERRb being asserted low by the device in which the error occurs As controlled by the configuration data set it is possible to set the length of the error pulse to be short or long in the device which generates it Short pulses are ignored by all other devices in the system and the device which generated the error resets to the p oint where as imple Update is required If al ong ERRb pul se is generated then for both single and multiple device systems a Primary Configuration can begin immediately Long pulses are detected by all other devices in the system which reset to the point where a complete Primary Configuration is required The device which generated the error also resets to this state As an output a long ERRb pulse is asserted low for 15 DCLK clocks A short ERRb output pulse is 1 DCLK clock long As an input ERRb is recognized asserted when held low for 15 or more DCLK periods The ERRb pin may be used to force the device to do a Primary Configuration If ERRb
22. AN121E04 device this feature is superfluous RESET_ALL 1 On an error the ERRb output will pull low for 15 DCLK cycles and the device will be reset to a point where a Primary Configuration is required 0 On an error the ERRb output will be pulsed low for a single DLCK cycle and the device will be reset to a point where only an Update is required Review section 3 5 7 for further explanation 0 constant 0 Must be set to 0 Data downloaded into the device is placed into Shadow SRAM In or der to k eep any disruption of an alog processing to a minimum the transfer from Shadow SRAM to Configuration SRAM occurs in a single clock cycle Using the default control byte value in particular ENDEXECUTE 1 this transfer will happen automat ically at the completion of any configuration data download Copyright O 2004 Anadigm Inc All Rights Reserved 19 UM000221 U001b AN12x AN22x AnadigmVortex FPAA Family User Manual BYTE ADDRESS BYTE Bit Number 7 6 5 4 32 1 0 BYTE ADDRESS Starting byte address of Shadow SRAM to be loaded ENABLE CCITT CRC16 1 CCITT CRC16 error checking is enabled CHECK 0 DATA BLOCK END checking is enabled DATA_FOLLOWS 1 A subsequent Data Block will be expected by the configuration logic 0 This block is presumed to be the final block of configuration data CONSTANT 1 1 Must always be set to 1 0 Undefined operation
23. CLK should be greater than 2 nS Hold time is O nS Copyright O 2004 Anadigm Inc All Rights Reserved 13 UMO00221 U001b AN12x AN22x AnadigmVortex FPAA Family User Manual ACLK Al CFGFLGb OUTCLK OUTCLK becomes available as a digital output gt DIN XXX XXX 0000 OQ 400 k byte N 1 NULL byte Figure 13 SP EPROM Completion Sequence As the last configuration data byte a NULL byte is being clocked into the device CF GFLGb de asserts high One ACLK later OUTCLK becomes available as a digital output typically reflecting one of four internal clocks 3 2 2 Multiple FPAAs Connection Details Multiple FPAAs may be configured from a single SPI EPROM The first FPAA in the chain has both of its chip selects pulled low and soit begins configuring immediately after po wer up All downstream devices are stopped from configuring because their CS1b inputs are held high As the first FPAA in the chain completes its self configuration it asserts LC Cb low T his flags the n ext de vice in the chain to beg in its configuration sequence and so on down the chain p A SPI EPROM AN12x AN22x AN12x AN22x MISO DIN ACTIVATE L_4 DIN ACTIVATE SCLK K _ gt ERRb ERRb oe ye MOSI
24. EPROM In th is mode after the device powers up it will automatically load its configuration data from the EPROM and begin analog signal processing The configuration interface is also designed to be connected directly to a host microprocessor s SPI master port where it presents itself as a SPI compatible slave The configuration interface also allows multiple devices to be easily connected together to build up larger analog processing systems 2 Analog Architecture Details 2 1 Input Cell Each Input Cell contains a collection of resources which allow for high fidelity connections to and from the outside world with no need for additional external components In order to maximize signal fidelity all signal routing and processing within the device is fully differential Accordingly each Input Cell accepts a differential signal Device Number Unique Input Cell Features ANx20 Input only Chopper stabilized low offset input amplifier with programmable gain Standard input amplifier with programmable gain Programmable anti aliasing input filter Direct input ANx21 Bidirectional Chopper stabilized low offset input amplifier with programmable gain Stan dard input amplifier with programmable gain Programmable anti aliasing input filter Direct input Direct output ANx22 Bidirectional Direct input Direct output ANx27 Bidirectional Direct input Direct output Copyright O 2004 Anadigm Inc All Rights Reserved 2 UM000221 U001b
25. REFMC VMR 1 5 V will result in the output railing to either 7F or FF as appropriate The SAR result can be routed to either the LUT s address port or back into its host CAB The most common use of the SAR is to serve as an address generator for the Look Up Table At the end of every conversion the 8 bit result is recognized by the LUT as anew address The configuration circuitry takes the LUT contents pointed to by this address and loads it into one or two specific locations in the Shadow SRAM A typical use scenario is where an input signal needs to be linearized and or calibrated A signal comes in from the outside world and is presented to the CAB configured to do a SAR conversion The SAR result is routed to the LUT where a linearization table was stored as part of the device s configuration image Using the same mechanism as described for the LUT counter in section 2 5 the configuration circuitry takes the LUT contents pointed to by this address the SAR result byte and loads it into 1 or 2 specific Shadow SRAM loca tions For this example these locations would likely adjust the gain of an amplifier thus achieving the desired Copyright 2004 Anadigm Inc All Rights Reserved 7 UM000221 U001b AN12x AN22x AnadigmVortex FPAA Family User Manual linearization When the SAR conversion byte is routed directly back into the Configuration SRAM of its host CAB self modifying circuits can be constructed The SAR may also be used
26. T PIN g El N Bypass A p QIP z OUT PIN gt Programmable fg DIFF2SINGLE gt Y O1P 33 Ll VOUT gs 2 E vout 3 OUT PIN sq oo Ly O1N g ES a 2 A O1N 8 al BYPASS Figure 4 Fully Featured Output Cell for ANx20 amp ANx21 and Simplified ANx22 amp ANx27 Analog signal pairs sourced by CABs within the array are routed to an Output Cell via the Output Cell s input multiplexer It may be desirable to route the core analog signals to the outside world with no additional buffering or filtering The AN x20 and A Nx21 Output Cells have bypass paths which allow the core signals to come out with no further processing or buffering For special considerations governing the use of bypass mode outputs see Section 2 1 1 The ANx20 and ANx21 Output Cells contain a programmable filter identical to the one described for the Input Cells see Section 2 1 The filter may be bypassed or set to selected corner frequencies Whereas the filter structure served as an anti aliasing filter for the input in the Output Cell it serves as a 214 order reconstruction filter In this function it smooths out the sampling induced stair step nature of the output waveform A differential to single converter circuit follows the programmable filter After the programmable filter and the DIFF2SINGLE conversion the system designer may elect to utilize only one of the OUT signals referencing it to Voltage Main Reference VMR or use th
27. TM AN22x series AN12x series AnadigmVortex FPAA Family User Manual AnadigmVortex is th e se cond gen eration fi eld programmable an alog ar ray FPAA dev ice fa mily from Anadigm Nine members of the AnadigmVortex family are currently shipping providing a range of solutions to meet your analog signal processing requirements Static Dynamically Input In Out Output Confi R fi bl Cell Cell Cell CABs AN120E04 AN220E04 4 2 4 Specialized input cell features AN121E04 AN221E04 4 2 4 Bi directional input output cells AN12x devices are best suited for are geared towards high volume applications requiring consolidation of discrete analog functionality The configuration interface of the A N22x devices is enhanced to accommodate dynamic reconfiguration a breakthrough capability that allows analog functions to b e integrated within the system and controlled by companion processor AnadigmVortex devices consist of a 2 x2 or 1x2 SHIELD OUTCLK SPIMEM DOUTCLK z a z AVDD AVDD2 ACLK SPIP DCLK amp 8 56 matrix o ffu lly Configurable A nalog Blocks Ty Ty p ll CABs sur rounded bya fab ricof program ar tat Oscillator mable interconnect resources Fully differential Gol bel CKS E
28. The Anadigmvortex solution allows OEMs to deliver differentiated solutions faster and at lower overall system cost Copyright 2004 Anadigm Inc All Rights Reserved UM000221 U001b Legal Notice Anadigm reserves the right to make any changes without further notice to any products herein Anadigm makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Anadigm assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and al liabili ty including wit hout lim itation c onsequential or incident al damages T ypical parameters can and do var y in dif ferent applications All op erating parameters including T ypicals m ust be validated for each customer appli cation by cust omer s technical experts Anadigm does not in this manual convey any licens e under its patent rights nor the rights of others Anadigm software and ass ociated products cannot be used except strictly in acco rdance with an Anadigm software license The terms of the appropriate Anadigm software license shall prevail over the above terms to the extent of any inconsistency Copyright 2004 Anadigm Inc All Rights Reserved Anadigm AnadigmDesigner and SonicMaster are registered trademarks of Anadigm Inc The Anadigm logo is a trademark of Anadigm Inc Copyright 2004 Anadigm Inc All Rights Reserved UM000221 U001b Table of Content
29. al 4 2 Recommended PCB Design Practices The device is designed to perform with very few external components required However there is no fighting physics and some filtering capacitors are required for both the supply rails as well as the internally generated voltage references Digital Power A e v e amp e 8 a 2 5 3 z Digital Ground Plane 2 Y o g Analog Ground Plane be a TT Analog Power o o lt 19 El ma ge y Analog Power 2 75 a Analog Power x g ee 9 ho o 2 e e Analog Power Figure 25 Basic Guidelines for Optimal PCB Design Ground Planes Your PCB design should include some of the following features to ensure good separation between the digital and analog signal environments in your system Good PCB design practices dictate that the digital and analog power and ground planes be se parated It is important to maintain these planes at the same basic potential but care should be exercised to prevent the usual noise of a digital plane from coupling onto the analog plane In Figure 25 the e lectrical connection between the two pl anes is made at onl y two points through F errite bead choked wire The Ferrite beads act as low pass filters As with any mixed signal board design it is good practice to keep digital signals especially digital signals with high edge rates routed only over areas where digital power and groun
30. but does stop it from being clocked into the device After configuration CS2b continues to act with CS1b as a clock enable for the device A user can therefore hold CS2b high after configuration to reduce power consumption in the device 3 5 14 EXECUTE The EXECUTE input pin should normally be tied low Copyright 2004 Anadigm Inc All Rights Reserved 30 UM000221 U001b Tare 4 Mechanical 4 1 Package Pin Assignments 1 104PA Analog lO 2 104NA Analog IO 3 O1P Analog OUT 4 O1N Analog OUT 5 AVSS Analog VSS Analog Ground 0 Volts 6 AVDD Analog VDD Analog Power 5 Volts 5 7 O2P Analog OUT 8 O2N Analog OUT 9 101P Analog O 10 IO1N Analog lO 11 102P Analog O 12 102N Analog lO 13 SHIELD Analog VDD Low noise VDD bias for capacitor array n wells 5 Volt 14 AVDD2 Analog VDD Analog Power 5 Volts 5 15 VREFMC Vref Attach filter capacitor for VREF 16 VREFPC Vref Attach filter capacitor for VREF 17 VMRC Vref Attach filter capacitor for VMR Voltage Main Reference 18 BVDD Analog VDD Analog Power for Bandgap Vref Generators 5 Volts 19 BVSS Analog VSS Analog Ground for Bandgap Vref Generators O Volts 20 CFGFLGb Digital IN OUT Configuration flag A low output indicates configuration is in progress open drain optional pull up 21 CS2b Digital IN Chi
31. byte to write to starting address 0 XXXXXXXX DATA 1 Data byte to write to starting address 1 Remaining data bytes if any go in this region XXXXXXXX DATA n Data byte to write to starting address n XXXXXXXX CRC_MSB depending on Bit 5 of BYTE ADDRESS or or Most significant byte of CRC16 error code Data Block End or 00101010 2A Data Block End Constant of 0x2A XXXXXXXX CRC_LSB Least significant byte of CRC16 error code if used Remaining data blocks if any go in this region Data Block 10XXXXXX BYTE ADDRESS Starting Byte Address DATA_FOLLOWS 0 ast XXXXXXXX BANK ADDRESS Starting Bank address XXXXXXXX DATA COUNT Data byte count a value of 00 instructs 256 bytes XXXXXXXX DATA 0 Data byte to write to starting address 0 XXXXXXXX DATA 1 Data byte to write to starting address 1 Remaining data bytes if any go in this region XXXXXXXX DATA n Data byte to write to starting address n XXXXXXXX CRC_MSB depending on Bit 5 of BYTE ADDRESS or or Most significant byte of CRC16 error code Data Block End or Data Block End Constant of 0x2A XXXXXXXX CRC_LSB Least significant byte of CRC16 error code if used 00101010 2A Figure 19 Update Data Stream Structure 3 4 5 Configuration Examples The following examples assume a hos ted interface Data must be shifted into the F PAA most significant bit first White space and comments are included only to improve readability f
32. ce Manufacturer Frequency Part Number NDK 12 16 20 MHz NX8045GB C MAC 12 16 20 MHz 12 SMX AeL 12 16 20 24 MHz SXH Figure 21 Known Compatible Crystals 3 5 3 ACLK SPIP Analog Clock Serial PROM Clock In MODE 0 ACLK SPIP is an optional analog master clock input to drive the switched capacitor circuitry within the device In MODE 1 ACLK SPIP is SPI master clock for an attached SPI EPROM It is a divide down by16 version of DCLK 3 5 4 OUTCLK SPIMEM During power up the OUTCLK SPIMEM pin transmits control words to the attached SPI memory device if any A SPI EPROM requires a control word to be sent followed by a 16 bit start address After configuration the OUTCLK SPIMEM pin routes out any 1 of the 4 i nternal analog clocks as e nabled by the configuration data Copyright 2004 Anadigm Inc All Rights Reserved 26 UM000221 U001b TM and 3 5 5 MODE MODE controls the behavior of the analog and configuration clocks portion of the device The state of the MODE pin establishes a unique configuration for the device s clock pins as shown below A Any analog clock o SPI MOSI setup stream Configuration Done 1 OUTCLK SPIMEM lt DOUTCLK lt DOUTCLK Buffer RAM Crystal DCLK gt Oscillator N 16 0 Configuration 1 MODE gt 1 A RD Analog Clock ACLK SPIP amp 0 Dividers
33. ce IDis notas expected the de vice will assert ERRb and no data will be loaded into the array Incorrect data can cause high stress conditions to exist within the device possibly causing damage Family Member 32 bit Device ID AN120E04 AN220E04 AN121E04 AN221E04 AN221E02 AN122E04 AN222E04 AN127E04 AN227E04 Figure 17 Device IDs for the AnadigmVortex Family ADDR1 BYTE 0x300012B7 0x300022B7 0x800012B7 0x800022B7 0x000122B7 0x000212B7 0x000222B7 0x000312B7 0x000322B7 The ADDR1 field establishes one of the two logical addresses for the device ADDR1 is considered the primary logical address for the device The alternate logical address ADDR 2 is not part of the Header Block but rather it is established within the device s configuration data and is therefor delivered within a Data Block Having logical addresses for every F PAA in the s ystem allows the connection of many FPAAs in series consuming no extra physical host connections and once configured communication only with the specifically addressed device s See section 3 4 5 for further details Copyright 2004 Anadigm Inc All Rights Reserved 18 UM000221 U001b TM Tare 3 4 3 Data Block CONTROL BYTE Bit Number 7 6 5 4 3 2 1 0 ojpojojojo 1 jo Default bit values as generated by AnadigmDesigner 2 PULLUPS 1 Enable internal pull ups 0 Disable internal pull ups This bit is used to enable i
34. d planes underlay Care should be exercised to never route a high edge rate digital signal perpendicular to a plane split Doing so will cause a noise wavefront to launch left and right onto both planes along the split It is recommended that the digital supply DVDD be bypassed to DVS S using ceramic capacitors A 1 pu F capacitor in parallel with a 01 pF capacitor is usually sufficient The capacitor connections to the device should be made as close as practical to the package to reduce detrimental inductance This same bypassing scheme will work sufficiently for BVDD BVSS AVDD AVSS AVDD2 AVSS SHIELD AVSS pairs as well Copyright 2004 Anadigm Inc All Rights Reserved 32 UM000221 U001b TM gt Tare Copyright O 2004 Anadigm Inc All Rights Reserved 33 UM000221 U001b AN12x AN22x AnadigmVortex FPAA Family User Manual Copyright O 2004 Anadigm Inc All Rights Reserved 34 UM000221 U001b AN12x AN22x AnadigmVortex FPAA Family User Manual TM iare For more information logon to www anadigm com Copyright 2004 Anadigm Inc All Rights Reserved UM000221 U001b
35. e ID ADDR1 and Configuration Control bytes A Data Block contains data addressing information a configuration data byte count and from 1 to 256 configuration da ta bytes followed by a single data block terminator byte or two CRC 16 check bytes Copyright O 2004 Anadigm Inc All Rights Reserved 16 UMO00221 U001b TM lars Data Byte Name Description Header Block 11010101 D5 SYNC Synchronization byte always D5 10110111 B7 Device ID BYTE 0 Bits 7 0 of Device ID 0x800022B7 00100010 22 Device ID BYTE 1 Bits 15 8 of Device ID 00000000 00 Device ID BYTE 2 Bits 23 16 of Device ID 10000000 80 Device ID BYTE 3 Bits 31 24 of Device ID XXXXXXXX ADDR1 ADDR1 Byte Primary Logical Address for the FPAA XXXXXXXX CONTROL Configuration Control Byte Data Block 11XXXXXX BYTE ADDRESS Starting Byte Address DATA_FOLLOWS 1 a XXXXXXXX BANK ADDRESS Starting Bank address XXXXXXXX DATA COUNT Data byte count a value of 00 instructs 256 bytes XXXXXXXX DATA 0 Data byte to write to starting address 0 XXXXXXXX DATA 1 Data byte to write to starting address 1 Remaining data byt es go in this region 00101010 2A Data Block End XXXXXXXX DATA n Data byte to write to starting address n XXXXXXXX CRC_MSB depending on Bit 5 of BYTE ADDRESS or or Most significant byte of CRC16 error code or Data Block End Constant of 0x2A XXXXXXXX CRC_LSB Least significant byte o
36. ely fill the Shadow SRAM These blocks do not need to be prefaced by additional clocks nor do they require a Device ID ADDR1 or Control bytes These intermediate blocks all have the same form as the final block shown below The important point to note is that only the final block of Primary Configuration has the DATA FOLLOWS bit cleared in the BYTE ADDRESS byte DATA_FOLLOWS is cleared to 0 this means that at the conclusion of the transfer of this final block Shadow SRAM will get copied into Configuration SRAM with no additional action required by the host Ox1E is the starting BYTE address 0x17 is the starting BANK address 0x02 is byte count for this particular last block Second to the last configuration data byte The Last configuration data byte 0x2A is the Basic error checking constant expected 8 clocks are required by the configuration state machine to finish the transfer This is usually accomplished by sending out a single byte of don t care NULL data Copyright O 2004 Anadigm Inc All Rights Reserved 23 UM000221 U001b AN12x AN22x AnadigmVortex FPAA Family User Manual Update Format Example AN22x Only 11010101 00000001 00000101 10011110 00000011 00000011 datadata datadata datadata 00101010 00000000 0xD5 is the required sync header TARGET ID The ADDR1 or ADDR2 value of the target device or the universal target ID o
37. em both OUT and OUT as a differential pair Remember that a single ended output will have half the amplitude of a differential signal ANx22 and ANx27 devices have streamlined Output Cells These devices offer only the direct unbuffered signal paths out of the CABs Copyright 2004 Anadigm Inc All Rights Reserved 5 UM000221 U001b AN12x AN22x AnadigmVortex FPAA Family User Manual 2 4 Configurable Analog Block Within the FPAA there are two AN221E02 or four all other family members Configurable Analog Blocks CABs The functions available in the CAM library are mapped onto these programmable analog circuits Figure 5 shows an overview of the Configurable Analog Block CAB Control Shadow SRAM Logic Configuration SRAM Global Local EPP PETE NOL Clock LUT Generator Interface 12 3 4 Analog Clocks td an Figure 5 Overview of a Configurable Analog Block Among the many analog switches within the CAB some are static and determine things like the general CAB circuit connections capacitor values and which input is active Other switches are dynamic and can change under control of the analog input signal the phase of the clock selected and the SAR logic Whether static or dynamic all of the switches are controlled by the Configuration SRAM As part of the power on reset sequence SRAM is cleared to a known safe state It is the job of the configu ration logic to tr ansfer data from the ou ts
38. f CRC16 error code if used Remaining data blocks go in this region Data Block 10XXXXXX BYTE ADDRESS Starting Byte Address DATA_FOLLOWS 0 cast XXXXXXXX BANK ADDRESS Starting Bank address XXXXXXXX DATA COUNT Data byte count a value of 00 instructs 256 bytes XXXXXXXX DATA 0 Data byte to write to starting address 0 XXXXXXXX DATA 1 Data byte to write to starting address 1 Remaining data byt es go in this region 00101010 2A Data Block End XXXXXXXX DATA n Data byte to write to starting address n XXXXXXXX CRC_MSB depending on Bit 5 of BYTE ADDRESS or or Most significant byte of CRC16 error code or Data Block End Constant of 0x2A XXXXXXXX CRC_LSB Least significant byte of CRC16 error code if used Figure 16 Primary Configuration Data Stream Structure Copyright O 2004 Anadigm Inc All Rights Reserved 17 UM000221 U001b AN12x AN22x AnadigmVortex FPAA Family User Manual 3 4 2 Header Block SYNC BYTE The configuration logic always ex pects a sy nchronization header For the Primary Configuration and Update formats this sync header is always 11010101 D5 Device ID BYTE n Every Anadigm device type has a unique 32 bit Device ID Requiring the Device ID to m atch during Primary Configuration is a way of ensuring that configuration data intended for another device does not get ac cidentally loa ded Ifa Primary C onfiguration is attempted in wh ich the Devi
39. f OxFF Control Byte ENDEXECUTE and PULLUPS are enabled DATA_FOLLOWS is cleared to 0 so the configuration logic will expect no more data after this final block and because ENDEXECUTE is set 1 in the Control Byte Shadow SRAM will get copied into Configuration SRAM as soon as the data block is download with no additional action required by the host Ox1E decimal 30 is the starting BYTE address 0x03 is the starting BANK address 0x03 byte count field means 3 data bytes follow The 1st updated data byte goes to bank 3 byte 30 The 2nd updated data byte goes to bank 3 byte 31 The 3rd updated data byte goes to bank 4 byte 0 0x2A is the Basic error checking constant expected 8 don t care NULL bits to provide the necessary clocks to complete the load Because the EXECUTE bit was set on this block s control byte the immediate transfer from Shadow SRAM to the Configuration SRAM will occur here The 8 clocks at the end of each of these configurations are necessary only to complete the transfer at that time If it is not critical to complete the transfer at that particular moment then the clocking asso ciated with any subsequent Update block will be sufficient to complete the transfer With no clocks the configuration state machine simply freezes in place There are no unsafe states Copyright O 2004 Anadigm Inc All Rights Reserved 24 UM000221 U001b Tare 3 5 Con
40. figuration and Clock Pins Detailed Information The device has many advanced configuration features and as a consequence many of the pins of the config uration interface have multiple functions Subsequent sections describe the typical connection schemes Name Type Functions DOUTCLK Output Buffered version of DCLK Inactive floats until its associated configuration bit is set If unused this pin must be left floating Input Factory reserved test input Float if unused MODE Input 0 select clock support for synchronous serial interface 1 select clock support for SPI amp FPGA EPROM interface DCLK Input drive with lt 40 MHz external configuration clock or attach a 12 16 20 or 24 MHz crystal ACLK Input MODE 0 Analog Clock Switched Capacitor Clock lt 40 MHz SPIP Output MODE 1 SPI EPROM or Serial EPROM Clock OUTCLK Output During power up sources SPI EPROM initialization command string SPIMEM After power up sources selected internal analog clock or comparator output PORb Input 0 Chip Held in reset state Rising Edge re initiates power on reset sequence 30 mS to complete ERRb Input 0 Initiate Reset hold low for 15 clocks 1 No Action O D Output 0 Error Condition 10 KQ p u reqd Z No Error Condition ACTIVATE Input 0 Hold off completion of configuration Rising Edge Complete configuration O D Output 0 Device has not yet completed Primary Configuration Z
41. fter reset The AN22x devices offer the additional feature of allowing reconfiguration This feature not supported by the AN12x devices allows the reconfiguration of all or any part ofthe device repeatedly and at will using the reconfiguration protocol Thus the FPAA s behavior can be adjusted on the fly to meet dynamic requirements of an application Systems of multiple FPAAs can be booted using either the Master or Slave modes via a bused connection of configuration interface signals and logical device addressing part of the configuration protocol Slave mode FPAAs can be reconfigured concurrently or one at a time using fixed connections to the host Configuration speeds of up to 40MHz are supported 3 1 Slave Mode The FPAA can be set to function as a SPI bus compatible slave A fixed configuration data file may be sent in from the host processor to the FPAA as a one time post reset event A more powerful use model is to have the host processor make on the fly adjustments to the analog circuitry performing the calculation of new circuit parameters assembling the se new values into a configuration data block and transferring that data block into the FPAA 3 1 1 Single FPAA Connection Details Figure 8 shows a simple slave connection driven by a companion host processor s SPI port Master In this example the h ost processor man ually controls the FPAA s reset input This is not required The F PAA s configuration data file is then
42. g either an Output Cell or an Input Cell in bypass output mode special care must be taken to not overload the device In bypass mode there are no buffers between the CAB s signal source and the device s output pins The CAB op amps are not designed to drive low impedances Also too much load capacitance will destabilize the CAB op amps The minimum recommended external load resistance should be not less than 100 KQ and the maximum external load capacitance should be not more than 100 pF When using bypass mode outputs characterization of the final system is essential Copyright O 2004 Anadigm Inc All Rights Reserved 3 UM000221 U001b AN12x AN22x AnadigmVortex FPAA Family User Manual 2 2 Mu xed Analog Input Output There is a bi directional mu Itiplexer av ailable in front of on e of the In put C ells T his al lows th e ph ysical connection of 8 single ended inputs 4 differential pair inputs or 4 differential pair output loads at once though only one source or load at a time can be processed by the FPAA As with the regular Input Cells the optimal input connection is from a differential signal source If a single ended connection is programmed the negative side of the internal differential pair will be connected to Voltage Main Reference PINS From 7 Array 104PA gt A S IO4NA 3 y N 104PB Programmable Gai
43. ghts Reserved 20 UM000221 U001b TM ana Ge DATA COUNT BYTE Setting this field to a va lue of 0x00 signifies that 256 data bytes follow in this data block Setting this field to any integer value between 1 and 255 signifies that exactly that many data bytes follow This byte count only represents the number of c onfiguration data bytes that follow data bytes destined for the Shadow SRAM or LUT SRAM the count does not include the Error check byte DATA BYTE Configuration da ta bytes This is the d ata that ge ts loaded into the S hadow SRAM or LUT SRAM starting at the address defined in BYTE and BANK address bytes defined just above There may 1 up to 256 data bytes per block DATA BLOCK END BYTE If bit 5 of BYTE ADDRESS is 0 the only byte expected after the DATA bytes is the DATA BLOCK END constant 0x 2A If an y other value is read in E RRb will assert and the c onfiguration process will be aborted Reconfiguration will be required as described in section 3 5 7 CRC_MSB BYTE If bit 5 of BYTE ADDRESS is 1 CRC_MSB followed by a CRC_LSB byte is expected at the conclusion of end of each data block The 16 bit CRC is calculated using CCITT method with the polynomial x16 x412 x45 1 Calculation of a CRC is a compute intensive chore for a host processor and is not often used A pre calculated look up table based approach can be considerably faster for a but requires significant storage for all of the possible results Copyrig
44. hat canbe updated fully or partially in real time The FPAA contains either 2 or 4 Configurable Analog Blocks CABs in ts core Most of th e analog signal processing occurs within these CABs and is done with fully differential circuitry The CABs have access to a single Look Up Table LUT which offers a method of adjusting any programmable element within the device in response to a signal or time base It c an be used to implement arbitrary input to output transfer functions companding sensor linearization generate arbitrary signals and construct v oltage dep endent filtering A Voltage Reference Generator s upplies reference voltages to e ach of the CAB s within the device and has external pins for the connection of filtering capacitors x x al Q pm O xn 9 mi E gt s T e gz 32553 3 2 2 5 o 0 5 3 2506 A A Output Output y 4 Cell 2 Cell 1 Oscillator TT TT amp Clocks Output Only Analog Switch Fabric Analog Logic MODE Connects any CAB to any Output Cell 1234 3 Q 101P k 92 DVDD loin k _ 2 ks a D m s cjr DIN S l3lB caB1 caB2 I y w 183 5 IR g HO tce Ck y 3 a O qui sa S dE Ag S kK Erro
45. ht 2004 Anadigm Inc All Rights Reserved 21 UM000221 U001b AN12x AN22x AnadigmVortex FPAA Family User Manual 3 4 4 Update Format AN22x Only Once a Primary Configuration has been completed there is no longer any requirement for the host to transmit out Device ID information or reprogram the ADDR1 s of the devices along the communication path A config uration data stream doing so would be considered an error and devices would assert ERRb The host now only needs to send out a sync header and a valid ID for the target device or devices The remainder of the information is just as described above in section 3 4 1 As with Primary Configuration it is not a requirement of the Update format to contain a complete data set for the device Partial reconfiguration of the device is supported It is most often the case that only a few Shadow SRAM or LUT SRAM addresses need new data The Update format provides a quick and compact method for moving this new data into the device Data Byte Name Description Header Block 11010101 D5 SYNC Synchronization byte always D5 XXXXXXXX TARGET ID ADDR1 ADDR2 or OxFF Logical address of the target device s XXXXXXXX CONTROL Configuration Control Byte Data Block 11XXXXXX BYTE ADDRESS Starting Byte Address DATA_FOLLOWS 1 first XXXXXXXX BANK ADDRESS Starting Bank address XXXXXXXX DATA COUNT Data byte count a value of 00 instructs 256 bytes XXXXXXXX DATA 0 Data
46. ide world into the S hadow SRAM and from there copy it into the Configuration S RAM The AN22x devices allows reconfiguration While an AN22x de vice is operating the Shadow SRAM can be reloaded with values that will sometime later be used to update the Configuration SRAM In this fashion the F PAA c an b e r eprogrammed on the fly ac complishing anything fr om mi nor changes in circuit characteristics to complete functional context switches instantaneously and without inter rupting the signal path The AN12x devices must be reset between complete configuration loads and do not accept partial reconfigurations Analog signals route in from the cell s nearest neighbors using local routing resources These input signals connect up to a first bank of analog switches Feedback from the CAB s two internal op amps an d single comparator also route back into this input switch matrix Next is a bank of 8 programmable capacitors Each of these 8 capacitors is actually a large bank of small but equally sized capacitors Each of th ese 8 programmable capacitors can take on a relative value between 0 and 255 units of capacitance The actual value of capacitance is not all that important here The CAM library elements do not de pend on the absolute value of the se capacitors but rather on the ratio between them which tracks to better than an 0 1 There is a second switch matrix used to complete the circuit topology by making the appropriate connections The
47. is pulled low externally after power up completes then the device is reset and Primary Configuration will begin again once ERRb is released If used as an input for this purpose the input low period should be at least 15 DCLK periods long 3 5 8 ACTIVATE The ACTIVATE pin is an open drain input output with an internal pull up resistor selectable via configuration It de asserts low during power up and remains low until Primary Configuration is complete when it is released and pulls high using only the pu ll up resistor It remains de asserted tri stated and pulled high thereafter Once ACTIVATE pulls high configuration is allowed to complete if the ENDEXECUTE bit is set See section 3 4 1 for further detail If there is more than one FPAA in asystem all ACTIVATE signals should be tied together to ensure that all devices conclude their configuration at exactly the same time The ACTIVATE signal is also intended to be used to disable a standard FPGA Serial EPROM if used once configuration is complete See section 3 1 4 for further detail The internal pull up associated with the ACTIVATE pin is selectable through a control byte bit and becomes active immediately after the control byte is latched in 3 5 9 LCCb Local Configuration Complete During power up the LCCb output drives high So long as the Primary Configuration is incomplete the LCC b pin will continue to drive high Just before configuration completes the LCCb pin asserts low In mu
48. le te hata ae te 12 3 2 Master Mode sci tia 12 3 2 1 Single FPAA Connection Detalls ccccececesccceeeeeseeeeeteneeceeeneeseneeeseegeaeeneneneaedeeteeeeeeeenenteeseeeeees 13 3 2 2 Multiple FPAAs Connection Details 0 cccccceeceeeceeeceeceeeeeeeeeeeceaaeaecceceeeeeeeeetessencaeeeeeeeeeeeeeess 14 3 2 3 Special Considerations for Use of Pull Ups 0 cecececceeccccceceeeeeeeeececeeeeeeeeeeeeeeeeesseaaeaeeeeeeeseeeees 15 SO RESCl ae cs es ac alee A A O T 15 3 4 Contiguration Protocol weas labo lilas EE E EE EAE TE 16 3 4 1 Primary Configuration Format amp Byte Definitions cc ecceeeeeeeeeee eee eeneee eee teneeeeeeeeaeeeertneeeeeees 16 3 42 Header BIOOR anar a id 18 DANLOR DA E O a 18 Device ID BYTE Nuncio aria A AA ais E EE EE 18 e loo Neate atta cdas deal fect ente 18 ADOBE a a rl Ne deta di 18 3 4 3 Data BlOCK ci e T ta 19 CONTROL BY TE tcs dalla drid lidia bid 19 BYILEADDRESS BM Esc iii 20 BANK ADDRESS BV ME ed de eo qe te de atte 20 DATA COUN TF BYTE oraren e Rd aa 21 DATA BYTE viaccceliiiicckeiesleest ible cheanlidstetha lal tectatl bh holes dideested ibd lebael bbe ii ita tl 21 DATABLOCGKEND BYT Ecotrader coat teenie eee tienes 21 CROIMSB BY TBs isiiteii con sted a o ae ta lot 21 3 4 4 Update Format AN22x OMY Jesoo ateen Traa A EEEE nan cnn nana ERE NE NEAT ERARA KERARI 22 3 4 5 Configuration EXAMP ES seccional dd sisi EN EN EAE NTE 22 Primary Configuration Format Example oocooco
49. logic 1 out during the high period of the clock and reading the logic state on the pin during the low period of the clock On the next rising edge of the clock the logic state on the CS1b pin is latched internally See section 3 2 2 for further details on the LCCb to CS1b connection Copyright 2004 Anadigm Inc All Rights Reserved 29 UM000221 U001b AN12x AN22x AnadigmVortex FPAA Family User Manual 3 5 13 CS2b Chip Select 2 CS2b is an active low chip select input pin CS 2b should be synchronous to the c onfiguration clock It is sampled at the end of the power up period and if high it stops the ERRb pin from going high Completion of power up is delayed until CS2b goes low A user can therefore delay configuration by holding CS2b high from power up Once CS2b goes low ERRb goes high and configuration begins CS2b is logically NOR ed with CS1b and the output is used to gate the incoming clock to the configuration circuitry In other words when CS1b and CS2b are both low the clock is enabled To ensure that this gating always results in a clean clock to the main configuration state machine CS2b should be synchronous to the configuration clock It is important to note that when booting from either a Serial EPROM or SPI EPROM CS2b must remain low throughout configuration otherwise the data clocked out of the EPROM will not be clocked into the device This happens because CS2b does not stop data being clocked out of the EPROM
50. lti device systems this output is normally connected to the CS1b input pin of th e next device in the c onfiguration Copyright 2004 Anadigm Inc All Rights Reserved 28 UM000221 U001b chain allowing that device s configuration sequence to commence See section 3 2 2 for further details on the LCCb to CS1b connection Once configuration completes two clocks after ACTIVATE as serts hi gh the LCCb pin becomes a da ta output If the device is being read from then LCCb serves as the serial data output pin for the read data If the device is not being read from then LCCb is simply a registered version of CS1b allowing serial data to pass through the device for a multi device configuration serial data chain See Figure 9 for a detailed look at this configuration 3 5 10 CFGFLGb Configuration Flag The CFGFLGb pin is an open drain input output with an internal pull up resistor selectable via configuration CFGFLGb is first driven high then driven low during power up and remains low until Primary Configuration is complete when it is released and pulls high using the internal or external pull up The pin will drive low again at the beginning of reconfiguration and remain low until the end of reconfiguration when it is released and allowed to pull high once again In a multi device system the CFGFLGb pins should all be tied together Devices in a multi device system that are not be ing addressed for reconfiguration ignore input data un
51. n Programmable fo S Amplifier To IOANBKy Lo Sane 1 104PC k rO o 04 i VMR IO4NC H i i Chopper Stabilized LN uE Amp with Gain 2 Qui i n 4 5 6 7 y IO4PD k Single Ended Input 104NDE gt 3 The output path is not available on the ANx20 devices Differential 1 pair of 4 Single Ended 1 input of 8 PINS 104PA kK IO4NA k a O 104PB k is 104NBK Lor To I04PC k OS aray loanck 4 Out lO4PDk 4 IO4NDk Differential 1 pair of 4 Single Ended 1 input of 8 Figure 3 Fully Featured Muxed Input Cell for ANx20 amp ANx21 and Simplified ANx22 amp ANx27 Copyright O 2004 Anadigm Inc All Rights Reserved 4 UM000221 U001b TM ana Ge 2 3 Output Cell Like the Inpu t Cell s the O utput Cells are designed to en sure that y our sy stem s des ign ca n take full advantage of the fidelity and versatility that the core of the dev ice offers The outputs can serve to del iver digital data or differential analog voltage signals Device Number Unique Output Cell Features ANx20 Direct Output Unity Gain Buffer with Programmable Gain Reconstruction Filter ANx21 Direct Output Unity Gain Buffer with Programmable Gain Reconstruction Filter Digital Output SAR and Comparator ANx22 Direct output ANx27 Direct output BYPASS A Ml OU
52. nnncccccnnnnoccccnononcccnnn anar c cono nan n cnn nn rca 23 Update Format Example AN22x OMnly cccccceeeeeeeeeeeeeeeeeeeeeaeeeeeeeaaeeeeeeeaaeeeseeeaeeeeseenaeeeeeeeaes 24 3 5 Configuration and Clock Pins Detailed Information ooccccnnnnnncnnnnocccccnnnonnnnnonnnancnrcnnoncn rr naar nc narco 25 351 DOUTGEK ota laica cadetes edi he 26 30 2 DELK Data Clock licita VIIa ias 26 3 5 3 ACLK SPIP Analog Clock Serial PROM Clock ooooocooccconncoccccconnonnccconanoncncnonnanccncna nan nnncnnnnnncnninns 26 3 94 OUTO KSR MEM a eo 26 33525 MODE 00 titanes ltda bacilo aa eaaa dile 27 3 5016 PORD Power On Resolor iii ii 28 Copyright O 2004 Anadigm Inc All Rights Reserved i UM000221 U001b Table of Contents waT ERRD EFTOR sci ith edict tscndec cat stanlots cardiaca lianas 28 IIA TE tibet sheet acta eee EE ean halt aaa at ns et Os a a e ad tara ead 28 3 5 9 LCCb Local Configuration Complete ooonooccccnnnnncccccnnnocccccnnnnoncccnnn nono EEEE AEEA EA REREN AEEA E KAARE ENEE REA 28 3 5 10 CFGFLGb Configuration Flag oar eE nE E TERE TOA 29 3311 DIN Data I eiei la dls aaa aa a EE E a 29 3 5 12 651b Chip Select 1 o a E A AT AT 29 3 90 13E6S2b ChIp Select A umi E E E E E STD 30 SOMA EXECUTE ea 30 4 Mechanical 31 4 1 Package Pin Assignments scccnissieii dt a dd beca dec 31 4 2 Recommended PCB Design Practices ooccoonnnccccnonnocccccnnnnonccannn conc cnnn nono narran rca rr 32 Copyright O 2004 Anadigm Inc All Righ
53. nsfer of this data to its Configuration SRAM will be held off until signaled by the external EXECUTE pin This feature allows finer temporal control and coordination between the programmable analog circuitry and the digital host processor The device also features a Look Up Table LUT The LUT exists as part of the Configuration SRAM and can be read and written to as normal however Shadow SRAM for the LUT is not supported Thus data written to the LUT becomes effective as it is written 3 2 Master Mode The simplest method of configuring the FPAA is to wire it in Master mode and allow it to self boot from a previ ously programmed SPI EPROM Anadigm FPAAs are directly compatible with industry standard 25 series SPI EPROMs Manufacturer Pa rt Number Atmel AT25080 Xicor X5043 Microchip 25AA160 Figure 10 Known Compatible 25 Series SPI Memory Devices As system power comes up the FPAA completes its internal power on reset then provides the necessary signalling to read data out of the SP EPROM Once the transfer of configuration data is complete the FPAA will activate its analog circuitry The entire power on reset and configuration process is automatic Copyright 2004 Anadigm Inc All Rights Reserved 12 UM000221 U001b a a 3 2 1 Single FPAA Connection Details A typical connection scheme for a standard SP EPROM is shown in Figure 11 Once the FPAASs internal power on reset sequence completes CFGFLGb will a
54. nternal pull ups on the CFGFLGb and ACTIVATE pins PULLUPS is sticky i e Once set it stays set until a device reset If the pin is exter nally loaded then it is recommended that an external pull up resistor be used instead of the internal Note DIN pull up is controlled by configuration data only Note ERRb always requires an external pull up resistor 10KQ is the recommended value 0 constant 0 Must be set to 0 ENDEXECUTE 1 At the end of the current transfer cycle Shadow SRAM will be copied into Configuration SRAM 0 No action See below and section 3 5 14 further explanation SRESET 1 The device will perform a reset 0 No action This bit allows the host to initiate a soft reset The device will reset as soon this bit is latched READ 1 Sets the device in read mode Configuration SRAM and LUT only 0 Sets the device in write mode STOP_READBACK 1 Stop any data read back from the device 0 Allow data read back from the device This bit can be set during Primary Configuration or Update If set an internal flag is set which prevents all further data read backs This internal flag can only be reset by re powering the device thereby destroying the SRAM contents If any attempt to do a read back is made after this bit is set then ERRb will drive low for 14 DCLK cycles and the device will be reset to a point where a Primary Configuration is required In the
55. or these examples Copyright 2004 Anadigm Inc All Rights Reserved 22 UM000221 U001b Tare Primary Configuration Format Example 00000000 00000000 00000000 00000000 00000000 11010101 10110111 00100010 00000000 10000000 00000001 00000101 11000000 00000000 00000000 datadata datadata datadata 00101010 10011110 00010111 00000010 datadata datadata 00101010 00000000 40 clocks are required to be sent to complete the power up reset sequence This is usually accomplished by sending out 5 bytes of don t care NULL prefix data After the 40th clock the configuration logic is ready 0xD5 is the required sync header 0xB7 is Least Significant Byte of Device ID word AN221E04 0x22 is byte 2 of Device ID word 0x00 is byte 3 of Device ID word 0x80 is Most Significant Byte of Device ID word if if User assigns any Chip ID except OxFF Control Byte PULLUPS are enabled ENDEXECUTE Transfer Shadow SRAM to Configuration SRAM as soon as this download is complete Constant 1 DATA FOLLOWS 1 start BYTE address is 0 The starting BANK address is 0 0x00 byte count field means 256 data bytes follow The first configuration data byte The second configuration data byte the 256th configuration data byte 0x2A is the Basic error checking constant expected This is the region that the other blocks of data need to be sent to complet
56. p Select 2 22 CS1b Digital IN Chip Select 1 23 DCLK Digital IN Configuration data strobe and configuration state machine clock 24 SVSS Digital VSS Digital Ground Substrate Tie O Volts 25 MODE Digital IN Sets configuration mode 26 ACLK SPIP Digital IN OUT Analog sample clock or EPROM clock 27 OUTCLK SPIMEM Digital OUT Programmable Digital Output or EPROM MOSI data stream 28 DVDD Digital VDD 5 Volts 5 29 DVSS Digital VSS 0 Volts 30 DIN Digital IN Serial Configuration Data Input optional pull up 31 LCCb Digital OUT Local configuration complete 32 ERRb Digital IN OUT Configuration error signal open drain 10 KQ p u required 33 ACTIVATE Digital IN OUT Enables Shadow SRAM to Configuration SRAM transfer open drain optional pull up 34 DOUTCLK Digital OUT Buffered version of DCLK 35 PORb Digital IN OUT Power On Reset The minimum pulse width required is 25 nS open drain 36 EXECUTE Digital IN External trigger for Shadow SRAM to Configuration SRAM transfer 37 103P Analog O 38 IO3N Analog lO 39 104PD Analog O Analog multiplexer input output signals The multiplexer can accept 4 differential pairs or 8 single 40 104ND Analog lO ended connections 41 104PC Analog lO 42 O4NC Analog IO 43 1O4PB Analog lO 44 104NB Analog IO Figure 24 Package Pin Assignments Copyright O 2004 Anadigm Inc All Rights Reserved 31 UM000221 U001b AN12x AN22x AnadigmVortex FPAA Family User Manu
57. r normal conditions In such systems only one of the FPAAs should have its internal pull ups enabled In larger systems it may be necessary to use more robust external pull up resistors In such cases the pull up should be supplied with the external resistor alone and not in combination with any internal pull ups A DIN pull up either internal or external should always be used in EPROM booted Master mode systems EPROMs typically hold their data output pin in tri state and require a pull up on the node to get it into a safe logic state 3 3 Reset The available sources of reset include a hard power cycle asserting ERRb low for not less than 15 DCLK s pulsing PORb low issuing a software reset during the Primary Configuration or after an error occurs during a Primary Configuration and ERRb asserts low Assume ERRb is not actively driven and o nly pulled high through an e xternal pull up resistor and PORb is similarly pulled high After power is applied to the device an internally generated power on reset pulse resets the pow er up and configuration state machines T he po wer on r eset pulse al so r esets th e c onfiguration memory Copyright 2004 Anadigm Inc All Rights Reserved 15 UM000221 U001b AN12x AN22x AnadigmVortex FPAA Family User Manual The power up state machine does not start until a clock becomes valid and has clocked 5 times This help protect the system from functioning until the clock is stable Thereafter
58. re are two op amps and a single comparator at the heart of the CAB Outputs of these active devices are Copyright O 2004 Anadigm Inc All Rights Reserved 6 UM000221 U001b routed back into the first switch matrix so feedback circuits can be constructed These outputs also go to neighboring CABs Signal processing within the CAB is usually handled with a s witched capacitor circuit Switched c apacitor circuits need non overlapping NOL clocks in order to function correctly The NOL Clock Generator portion of the CAB takes one of the four available analog clocks and generates all the non overlapping clocks the CAB requires There is Successive Approximation Register SAR logic that when enabled uses the comparator within the CAB to implement an 8 bit analog converter Routing the SAR s output back into its own CAB or to the Look Up Table enables the creation of non linear analog functions like voltage multiplication companding linear ization and automatic gain control 2 5 Look Up Table The device contains a single 256 byte Look Up Table LUT The 8 bit address input to the LUT can come from either the a SAR 8 bit output or from a special 8 bit LUT counter The functional description of the SAR driving the LUT address inputs is given in the section below If the LUT counter is selected the counter continuously counts up resetting itself back to zero count each time th at its programmable roll over value is met Each new coun
59. s 1 Architecture Overview 1 2 Analog Architecture Details 2 ZN INPUt COM ida OA AA A AA did 2 2 1 1 Special Consideration for Bypass Outputs 0ooooocccccccccccoccnooncnncnnnnnnnnnnnnnnnnnnnnnncnnnnnnnnnnnnnnnnnnnnnnnnnncnnnns 3 2 2 Muxed Analog Input OUtpUt o oo se a a a ae nn nn nn nn nn a aa a a a a a a 4 2 3 Output Cell ici A Ready Landed ek aed nan lade adele 5 2 4 Contigurable Analog Blok risas na at 6 ZO EDO Up Table iii A a ae i eves Ae ee 7 2 0 SAR Operation tit td A AAA a a a a eai 7 2 7 Voltage Reference and IBIAS Generators oncccconnnoccccnnnconcccconanoncncnnnnn nn nn nnnnn o nn n nano rca rr rnn rra rra nr 8 AO NSE GIOCKS veia cit tt A A EA 9 2 9 Unique CAM Library Features o onccconnooccccccononccnnononncnccnnnnncncccnnnn nn n rca nnn nn rr rana rra rra rra rra 9 3 Configuration Interface 10 3 1Slave Mode cepa tai ali det ii ae ad ai 10 3 1 1 Single FPAA Connection DetallS oooooonnnnccnnnnnoccccnnnncoccccnnnannc cn nn nrnc cnn n nar nn cnn narrar rra rr 10 3 1 2 Multiple FPAAs Connection Details ooooooooccocncccnnoccocooconnnccnnnoconnnnnnnoncnnnnnnnnnnnnnnnnnnn nn nnnn nn nrnn nn 11 Logical Addressing of Multiple FPAAs AN22x OMly ooooooonocccconnnoccccnononcccccnnnnanc cana nanccnnanannnnns 11 3 1 3 Configuration Clocking Considerations oooccconnnnccccnnnncoccccnnnoorc conan nn c cnn nar rr nnn anar rr cnn rr 12 IIA ACTUA TE it ati adoos t dio 12 BF EXE CUES titel tts eos atte allt late E add b
60. serial EPROM all the requisite information is contained in the serial data stream delivered to the device during configuration In dynamic applications the host processor must not only determine the appropriate configuration data but also transfer that data to the device using the protocol defined herein There are two data formats which comprise the configuration protocol Primary Con figuration format and Update format Each is explained in detail in the following sections 3 4 1 Primary Configuration Format amp Byte Definitions The Primary Configuration format is the format of the data that is generated by AnadigmDesigner2 and is the format that must be us ed exactly once to configure the device for the first time after reset Out of r eset all Shadow SRAM locations are reset to zeros A Primary Configuration is therefore only required to send data to Shadow SRAM locations requiring ones The LUT SRAM is not expressly reset to zero The Primary Configuration is therefore also required to initialize the LUT SRAM if the LUT is intended to be used Primary Configuration data sets presume the device has been reset Configuration SRAM zeroed out In order to make configuration as efficient as possible Primary Configuration data sets only contain data where one s need to be programmed 5 The Primary Configuration format is comprised of a H eader Block followed by one or more Data Blocks A header block contains a Sync byte Devic
61. sing is required W here input signal frequencies are higher Anadigm does recommend the use of external anti aliasing A second unique input resource available wit hin each ANx 20 and ANx21 Inp ut Cellis an amplifier with programmable gain and optional chopper stabilizing circuitry The chopper stabilized amplifier greatly reduces the input offset voltage normally associated with op amps This can be very useful for applications where the incoming signal is very weak and requires a high gain amplifier at the input The programmable gain of the amplifier can be set to 2 wheren 4 through 7 The output of the amplifier can be routed through the programmable anti aliasing input filter or directly into the CABs Single ended input signals must use either the amplifier or the anti alias filter in order to get the required single to differential conversion The program mable ga in amplifier th e c hopper stabilized am plifier an d th e p rogrammable anti aliasing fi Iter ar e all resources available only on the input signal path When the Input Cell is used as a bypass mode input or as an output the connection is direct and unbuffered There are no active circuit elements available in the Input Cell when it is configured for either input or output bypass ANx22 and ANx27 devices have streamlined Input Cells These devices offer only the direct unbuffered signal paths into and out of the CABs 2 1 1 Special Consideration for Bypass Outputs When usin
62. ssert low selecting the memory device The OUTCLK SPIMEM pin sends serial command words to the SPI memory instructing it to begin delivering data starting from its internal address 0 If there is any error encountered during this process ERRb will assert low and the device will ignore all subsequent serial data AN13x AN23x TI PORb SPI EPROM mso ni ACTIVATE MOSI 6 DO ERRb SCLK kK DCLKO m DCLKI SSb E CFGFLG This example assumes internal pull ups A EXECUTE are enable for ACTIVATE CFGFLGb and DIN csob L cs1b LCCb lt 16 MHz LIT LT L a ALK MASTER Figure 11 A Typical SP EPROM Connection The open drain ERRb pin is released on the 8th rising ACLK edge then monitored as an input for a logic high The assertion of CFGLFGb is held of until one clock after ERRb is detected as a valid logic high In this example ERRb was detected as high on the the 9th ACLK rising edge and so CFGFLGb was asserted low on the 10th rising ACLK edge After power up internal Power On Reset releases and ACLK starts typically 30 mS ERRb q23456789 077 93 45 67 Myr 34 5 6 789 0H 1223415 1 2 5 4 5 6 7 942345679 le 8 bit read instruction A 16 bit starting address always SPI EPROM Dout begins in high Z x i y X X y Y Y Y x Y X Y Y Y X Eaa NULL_byte0 k NULL_byte1 Ci gt onfiguration data streams in here ACLK
63. stem ooinncccccnnnococccnnonccnncnnonono nono nonnn cnn nr rancio nana rrnnn rra 27 Mechanical Figure 24 Package Pin Assignments ooccccccconnnoccccnocooncncnnnonnn cnn nn nonnn nn nana n ocn n aran n nn narran nn narran nn narran nr arras 31 Figure 25 Basic Guidelines for Optimal PCB Design Ground Planes onccocinnncccnnnncccconnnccncccnonanrnc canarios 32 Copyright O 2004 Anadigm Inc All Rights Reserved iii UM000221 U001b TM anoe 1 Architecture Overview Anadigm offers the AN12x and the A N22x series Field Programmable A nalog Array FPAA devices The AN12x devices can be reprogrammed as many times as desired however the device must first be reset before issuing an other configuration data set Once a Primary Configuration is complete the configuration interface of the AN1 2x device ignores all further input No further data writes are accepted unless a reset sequence is first completed The AN22x devices are dynamically reconfigurable the behavior of th e FPAA can modified partially or completely while operating Dynamic Reconfiguration available on the AN22x devices allows the host processor to send new configu ration data to the FPAA while the old configuration is active and running Once the new data load is complete the transfer to the new analog signal processing configuration happens in a single clock cycle Dynamic Reconfiguration in the AN22x d evice allows th e us er tod evelop in novative an alog systems t
64. t value is presented to th e LUT asan address The data read back from this address is then written into 1 or 2 target locations within Shadow SRAM The target location s to be used and LUT contents are part of the device s configuration data set The clock to the LUT counter is sourced by one of the 4 internal analog clocks from one of the four clock dividers The subsequent transfer of these 1 or 2 bytes from Shadow SRAM into Configuration SRAM can occur as soon as the last configuration data byte is sent or an internal zero crossing is detected or a comparator trip point is met or an external EXECUTE signal is detected With pe riodic clocking of th e LUT counter aLUT CAB combination can form an ar bitrary wav eform generator or temporally modulate a signal 2 6 SAR Operation Circuitry is in cluded within the CAB which allows the construction of a n 8 bit Suc cessive App roximation Register SAR type analog converter The SAR requires two clocks with a frequency ratio of 16 to1 The slower clock SAR clock a k a CLOCKA determines the rate at which successive conversions will occur and should not exceed 250 KHz The faster clock SC clock a k a CLOCKB is used to do the conversion itself These clocks are generated by the normal clock divider circuitry The SAR result is in th e sign magnitude format 1 bit sign 7 bits magnitude The SAR in puts should be limited to VMR 1 5 V Inputs going above VREFPC VMR 1 5 V and below V
65. their settling times It is required that extemal filtering caps be provided on VREFPC VMRC and VREFMC to ensure optimal chip performance The recommended value for each is 75 to 100 nF Higher values will have an adv erse affect on settling time lower values will reduce node stability For highest possible performance capacitors with a low series inductance such as Tantalum should be used In most cases however standard ceramic capacitors will be sufficient VREF and VREF are most often used by CAMs which utilize the comparator In particular these signals bound the recommended input range of SAR conversion CAMs Copyright 2004 Anadigm Inc All Rights Reserved 8 UM000221 U001b 2 8 System Clocks Figure 7 provides a good high level overview of the various clock features and clock domains of the de vice Not all of the features shown in this diagram are available in configuration MODE 1 See section 3 5 5 for a complete explanation of these restrictions The clock going to the configuration logic is always sourced at the DCLK pin The DCLK pin may have an external clock applied to it up to 40 MHz The DCLK pin may otherwise be connected to a series resonant crystal in which case special circuitry takes over to form a crystal controlled oscillator No programming is required Connection of a crystal will result in a spontaneously oscillating DCLK Please see section 3 5 2 for complete details on this feature DOUTCLK Buffered DCLK
66. til CF GFLGb pulls high The CFGFLGb pin can be monitored by the user to indicate when configurations are in progress The CFGFLGb is also used to initialize and chip select a SPI memory if used as these memories require a falling edge on the ir chip select input to reset This edge is provided when CFGFLGb is driven low during power up T he ins truction an d ad dress d ata subsequently output by the O UTCLK pin to initialize the SP memory is synchronized to this falling edge The internal pull up is selectable through a control byte bit and becomes active immediately after the control byte is latched in 3 5 11 DIN Data In DIN is the serial data input pin During power up this pin is ignored During configuration or reconfiguration DIN is the serial data input for configuration data There is a weak internal pull up on DIN which if configured ensures a valid logic state after an attached serial EPROM goes tri state 3 5 12 CS1b Chip Select 1 Prior to Primary Configuration while CS1b and CS2b are both low DCLK is used to clock the configuration state machine Once Primary Configuration is complete signals on CS1b are delayed by 8 clocks and passed to LCCb CS1b therefore behaves as an active low chip select CS1b should be synchronous to the configuration clock DCLK Note that CS1b is actually an intelligent polling I O although this function is entirely transparent to the user It operates on a cyclic basis writing a weak
67. tion Clocking Considerations The state machines within the device s configuration logic are driven by DCLK In most of the configuration connection examples above the clock is not free running so in addition to adhering to the protocols described the host processor must also provide clocks to allow the state machines to complete the ir reset and data transfer sequences If the appropriate clocks are not provided the state machines will idle and the reset or configuration will not complete as expected 3 1 4 ACTIVATE In multi FPAA systems it may be beneficial to prevent any of the FPAAs from going active until they have all received the ir configuration data ACTIVATE is an open d rain bi directional pin c ontrolling ogic whi ch achieves this function Consider F igure 14 Out of reset each F PAA drives A CTIVATE ow Ea ch de vice will continue to d rive ACTIVATE low until its configuration is completed at which time it is released Only when the ACTIVATE net pulls high which in our example will only happen after the both devices receive their configuration will the analog circuitry be allowed to go active ACTIVATE has an optional internal pull up resistor that may be enabled via the device s configuration data set In a multi FPAA system it is recommended that a single external pull up be used 3 1 5 EXECUTE An advanced configuration feature allows the transfer of configuration data to the FPAA s Shadow SRAM to complete but the tra
68. ts Reserved ii UM000221 U001b Table of Figures Architecture Overview Figure 1 Chip Overview for a Typical Four CAB AnadigmVortex FPAA oooninccoconnocccccnnnconcnonanann nc nanannncnnnnn 1 Analog Architecture Details Figure 2 Fully Featured Input Cell for ANx20 8 ANx21 and Simplified ANx22 8 ANX27 ee 3 Figure 3 Fully Featured Muxed Input Cell for ANx20 amp ANx21 and Simplified ANx22 8 ANX27 inococco 4 Figure 4 Fully Featured Output Cell for ANx20 amp ANx21 and Simplified ANx22 8 ANX27 eee 5 Figure 5 Overview of a Configurable Analog Block CAB 0 eeeeccceeeeeceeeeeeeeeeeeeeeeeeeeeseeeeaeeeeeeeeeeeeteeeaaeees 6 Figure 6 Voltage Reference and Bias Current Generation ooooonnnccinnnncccccnnnconcccnonnnncc cnn nano ronca nr nc 8 Figure 7 Clock Features and Clock Domains 0occocinnoccccnnnnoccccnononncccnnnnnn conc crono nc narrar cnn ar rr carr 9 Configuration Interface Figure 8 A Typical Host SPI Port Connection occocincccccccnnnocccncnnonononcnnnononnnnn nono cnn rr nnnn cnn aran nr nr rra nn rnn ran 10 Figure 9 Configuring Multiple Devices from a Host Processor nccoccccnnccccccccnccconcncnnnnnnnnnnonnnnnnrnnnnn nn nnrnnnn nn 11 Figure 10 Known Compatible 25 Series SPI Memory Devices oococccnnnccccconnoccccnnnnoncccnnnnnn no cano nar ncn na nannnnn 12 Figure 11 A Typical SP EPROM Connection ooocoocccccccnnoconcccnanonononcnannnnnnnnnn EARO n cnn ran n nn nar rra rra EEA 13

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