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QSpan II User Manual - Digi-Key

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1. Ons 250ns 500ns 1201 QCLK Y 12116 gt t235b BR_ gt t218b BG_ 1234 94 1211 BGACK_ gt t210a gt t236a 31 0 12360 TC 3 0 gt t236f SIZ 1 0 gt t235 m gt 1226 D 31 0 gt t21De gt t236e R W_ a 7 t216a gt 215a gt t262 DS_ X 9 12166 gt t215b AS_ a s gt 812174 gt 1218d DSACKO0 gt 17d jt 41218 DSACKI BERR HALT a Normal gt 812174 441218 DSACKO_4 gt t217d jt 41218 DSACK1_4 gt t217a 4 gt 1218 BERR p gt 412176 9 1218e HALT b Retry gt 612174 441218 DSACK0_ gt 12174 41218 DSACKI gt t217a 9 t218a BERR_ HAIT c Bus Error Wait states are not required by the QSpan II QSpan II User Manual 319 8091862 001 08 Appendix B Timing B 4 2 1 QBus Slave Cycles MC68360 Figure 29 Delayed Single Read QSpan II as MC68360 Slave Ons 100ns 200ns 300ns 400ns Lob od I 4 wf ow pL ul 21 4201 QCLK gt 1219 gt CSPCI_
2. 262 Interrupt Control 265 Interrupt Direction 268 Interrupt Control Register 2 1 271 Mailbox O Register PUER DEREN PUER 272 Mailbox l Registers 2 m up EIER d Rae aden 2 273 Mailbox 2 R6eglStet ers ink vp ERREUR Ren er EN ENDS UL E 274 Mailbox 3 Resister pibe tet eee eins bc d 275 Miscellaneous Control and Status 276 Master Slave Mode MSTSLYV 8 278 EEPROM Control and Status 2779 Miscellaneous Control 2 280 PCI Bus Arbiter Control 283 Parked PCI Mastet z svo ges i Wem exte oobis s 284 QSpan II User Manual 8091862 001 08 List of Tables Table 133 QBus Slave Image 0 Control 285 Table 134 QSpan II Response to a Single Read Cycle Access 286 Table 135 QSpan II Response to a Burst Read Cycle Access
3. Ons 100ns 200ns 300ns PN t401 QCLK 2 1419 gt 15 31 0 t419b 415e CSPCI_ gt 14134 IMSEL X gt 14139 t415d BURST_ TIP_ gt 1419e 41 5j SIZ 1 0 gt t419f 14151 01 jt gt 419d 4 15 R W t4150 4190 TS_ 1416 gt t417 t418 D 31 0 t409a t410e t436e TEA a Norma t409a t410e t436e TA 4A t409b t410g t436 fj b Retry 14096 1436 TEA_ c Bus Error QSpan II User Manual 351 8091862 001 08 Appendix B Timing Figure 63 Single Write QSpan as M68040 Slave Ons 100ns 200ns 300ns 31401 QCLK k t419a gt 1415 31 0 gt 14190 gt 415 CSPCI k t413d t4 5h IMSEL X X k 14139 P t415d BURST TIP V gt 1419 41415 SIZ 1 0 gt 4194 gt 1415 01 gt 14194 gt t4 5i R W_ t4150 2114190 TS_ t415g gt t413c D 31 0 t409a t410e t436e TAa g gt TEA a Normal 1409 t410e t436e TA y 2 t409b 0114109 t436 TEA p b Retry TA
4. 2 2 61 4 4 Transaction 61 6 QSpan II User Manual 8091862 001 08 Contents 4 4 2 Address 71 64 4 4 3 Transaction Codes on the 66 444 PCI BIOS Memory 67 4 4 41 Block Size and PCI Address 67 4 44 Base Address ete Be RG I eee hae ee e es 67 45 Data Phases eere aera ae hae eae a eue eee ees Cales anes 68 45 l Endian Mapping is imd Poele dU 68 4 5 1 1 Write Cycle Mapping for PCI Target 68 4 5 1 2 Read Cycle Mapping for PCI Target 70 45 2 Data Path cec timens S taeda d E E da Ia RE DEM 74 4 5 2 1 Posted Writes gt iie bre uc ee ied sia dao 74 4 5 2 2 Delayed 22 2 22 4 24 Ere e d 75 4 5 2 3 Single Read 76 4 5 2 4 Prefetched Read 76 4 5 3 Parity Monitoring by PCI Target Module
5. 147 12 4 CompactPCI Hot Swap Card 149 Chapter 13 PCI Power Management Event 153 13 1 OVERVIEW i exe hava tO GU dade RR OUS UR MGR de CAT ee aS 153 13 2 Power Management Event PME 153 Chapter 14 Reset OpPtlons dace das dan OR eed tandems 155 14 1 TypesofR sets 2 cose ee E ERN ER e Rd d 155 14 1 1 PCI Transactions during QBus 156 14 1 2 IDMA Reset eere be ege br HER Redes pr eee hee WU e e une 156 14 1 3 Clocking and edm 156 14 2 Configuration Options at 157 14 2 1 PCI Bus Master Reset 157 14 2 2 QBus Master and Slave 158 14 2 3 EEPROM Loading as alid pre doa cau bene b a i a cre 158 14 2 4 PCI Register Access 158 14 2 5 PCI Bus Arbitration Option 1 158 Chapter 15 Hardware Implementation 1550 5 159 15 1 55 eo RR Re Un
6. 2 29 1 21 Signals ia awards t e rere ty ut 29 12 2 Ordering sireeni eae es 29 1 2 3 Numeric 29 1 2 4 Topographic Conventions 29 1225 Eoo 30 12 6 Document Status ocu alse cea ADS eee eS 30 13 Related 5 30 Chapter 2 Functional OVeEVIEW 444 65 62666546654464 8466450480504 44088 31 2 OVGEVIGW ce eec ehe 31 2 2 TheQBus Slave Channel 2 22 2 2 2 0 66 4 Hr eee 32 2 3 The PCI Target Channel 20 00 oue pe eee ecce ras eR 33 2 4 TheIDM A e Reo Ir ted e he re ete AE UR ne 33 2 5 The DMA Channel cs cieu esed e b e e 66 566666556648 RE EE URP ES Se 33 2 6 Register 11 1 33 2 7 The Interrupt Channel brem Ese Sete rede db de oti es 34 2 8 The EEPROM Channel ulieser Rp p RARO HORROR RA eR e kas 34 Chapter 3 The QBus Slave Channel 35 ONVGEVIGW eoe GAs vice dn dece et eia ha t Fan o dep dead
7. 385 QSpan II User Manual 23 8091862 001 08 List of Tables Table 168 Table 169 Table 170 Table 171 Table 172 Table 173 Table 174 Table 175 Table 176 Table 177 Table 178 Table 179 Table 180 24 PCI Bus Error Logging Programming 385 IDMA DMA Channel Programming 386 PCI Configuration and IACK Cycle Programming Summary 387 PCI Expansion ROM 389 Power Dissipation tep soen tes eb see shee ans elei ee ciae eee ee es 397 3 3 Volt Absolute Maximum 398 3 3 Volt Recommended Operating 398 3 3 Volt Package Thermal Resistance 399 Junction to Ambient 399 Thermal Characteristics 52222224 a eas ees eee dae whee eed 399 256 PBGA 17 mm Packaging 401 256 PBGA 27 mm Packaging 403 Ordering Information ien Padre Eae Rer Eg d ep deb Bees edge E 407 QSpan II User Manual 8091862 001 08 Chapter 1 General Information This chapter describes the main functions and features of the QSpa
8. 240 Inbound Free List Bottom Pointer 241 Inbound Post List Top Pointer 242 Inbound Post List Bottom Pointer Register 243 120 Outbound Free List Top Pointer Register 244 I20 Outbound Free List Bottom Pointer 245 I20 Outbound Post List Top Pointer 246 I20 Outbound Post List Bottom Pointer 247 IDMA Control and Status Register 248 IDMA DMA PCI Address 251 IDMA DMA Transfer Count 252 DMA QBus Address Register 253 DMA Control and Status 254 DMA Command Packet Pointer 257 Configuration Address 258 PCI AD 31 16 lines asserted as a function of DEV_NUM field 259 Configuration Data 260 IACK Cycle Generator 261 Interrupt Status
9. 1 398 Thermal Characteristics 398 Appendix G Mechanical Information 401 G 1 Mechanical Information 2 401 QSpan II User Manual 13 8091862 001 08 Contents 256 17 race ET URL eus 401 1 1 1 PBGA 7 402 1 2 256 27 403 G 1 2 1 PBGA 27 404 Appendix Ordering 407 Ordering 407 H 2 Part Numbering 408 Gloss ry DERE DE 411 413 14 QSpan II User Manual 8091862 001 08 List of Figures Figure 1 Bridging PCI and Processor 26 Figure 2 QSpan II Functional Diagram 32 Figure 3 QBus Slave Channel Functional Diagram 36 Figure 4 Address Generator for QBus Slave Channel
10. 355 Figure 67 Register Write QSpan II as M68040 356 Figure 68 Reset from PCI Interface RST related to _ 357 Figure 60 Software Reset sese EO bet bore 357 Figure 70 INT Interrupt to QINT_ 357 Figure 71 PERR Interrupt eee ete ete e tete ele as 357 Ligure 72 Intert pt nee pe nals eas ae ad ae ED dees 358 Figure 73 QINT Interrupt to INT Interrupt 358 Figure 74 Reset Options ccce sieo irere tr r oraa ere y 02 hes eee 359 Figure 75 MC68360 Interface pute bg aep ie aed eb die erba 362 Figure 76 MPC860 Interface eet Aer p E be beer x 367 Figure 77 MPC860 QSpan II Clocking Scheme 1 368 Figure 78 Example Code for Executing an MPC860 Delay 369 Figure 792 M68040 Interface eco eee eed ee 374 Figure 80 Big Endian System 1 392 Figure 81 Little Endian 393 Figure 82 Address Invariant 394 Figure 83 Data Invariant 1 395 Figure 84 256 PBGA 17
11. 322 Register Write QSpan as MC68360 323 MC68360 324 MC68360 IDMA Read Single Address Standard Terminations 325 MC68360 IDMA Write Single Address Standard Terminations 326 MC68360 IDMA Read Single Address Fast 327 MC68360 IDMA Write Single Address Fast Termination 327 MC68360 IDMA Read Dual Address Standard Termination 328 MC68360 Write Dual Address Standard Termination 329 MC68360 IDMA Read Dual Address Fast Termination 330 MC68360 IDMA Read Dual Address Fast Termination 331 QBus Arbitration 860 332 Single Read QSpan as MPC860 Master 333 Single Write QSpan II as MPC860 334 Burst Read QSpan as MPC860 335 Aligned Burst Write QSpan as MPC860 336 Single Read QSpan IL as MPC860 5 337 Single Write QSpan II as MPC860 338 Burst Read QSpan IL as MPC860 Slave
12. 10 PCI cycteFrame cycte Frame GNT Grant External Grant 7 HALT_ Hi Z Halt Transfer Retry TRETRY_ s Hot Swap Healthy ee Signal HS_LED H2 L2 Low LED control output for Hot Swap HS_SWITCH J2 L4 I TTL Switch input for PD Hot Swap IDSEL N12 Y16 I PCI PCI Initialization Device Select T 1 1 12 3S Hi Z PCI i 184 QSpan II User Manual 8091862 001 08 Chapter 17 Signals and DC Characteristics Table 56 Pin List for QSpan II Signals Continued Input Output Reset IOL IOH Type Type State mA mA Interface Signal Description I Power up option to ED enable PCI Bus Arbiter I Power up option to disable PCI config accesses to QSpan II e BE i Power management event cpm Request External Request 7 REY See HALT TRETRY SDACK See DSACK_ SDACK_ AE AO EAEE ET S See DSACK1_ TA_ eni Transaction Code QSpan II User Manual 185 8091862 001 08 Chapter 17 Signals and DC Characteristics Table 56 Pin List for QSpan II Signals Continued 27 mm PBGA Input Output Reset IOL IOH Pin Name Ball Type Type Type State mA mA Interface Signal Description TCK H13 J20 I TTL Hi Z JTAG JTAG Test Clock Input TDI 5 L18 I TTL Hi Z JTAG JTAG Test Data
13. 226 Table 91 PCI Address Lines Compared as a Function of Block 5 2 227 Table 92 PCI Bus Target Image 1 Control 228 Table 93 PCI Bus Target Image 1 Address Register 230 Table 94 PCI Address Lines Compared as a Function of Block 5 2 231 Table 95 PCI Bus Expansion ROM Control 232 Table 96 PCI Address Lines Compared as a Function of Block 5 2 233 Table 97 PCI Bus Error Log Control and Status Register 234 QSpan II User Manual 21 8091862 001 08 List of Tables Table 98 Table 99 Table 100 Table 101 Table 102 Table 103 Table 104 Table 105 Table 106 Table 107 Table 108 Table 109 Table 110 Table 111 Table 112 Table 113 Table 114 Table 115 Table 116 Table 117 Table 118 Table 119 Table 120 Table 121 Table 122 Table 123 Table 124 Table 125 Table 126 Table 127 Table 128 Table 129 Table 130 Table 131 Table 132 22 PCI Bus Address Error Log 236 PCI Bus Data Error Log 237 120 Control and Status 238 I20 Inbound Free List Top Pointer
14. 339 Burst Write QSpan Il as MPC860 340 Register Read QSpan as MPC860 1 341 Register Write QSpan as MPC860 342 MPC860 DREQ 343 MPC860 IDMA Read Single 4 344 MPC860 IDMA Write Single 4 345 MPC860 IDMA Read Dual 346 MPC860 IDMA Write Dual Address 347 QCLK Input Timing M68040 347 QBus Arbitration 68040 348 Single Read QSpan as M68040 349 Single Write QSpan II as M68040 Master 350 Single Read QSpan as M68040 351 QSpan II User Manual 8091862 001 08 List of Figures Figure 63 Single Write QSpan II as M68040 Slave 352 Figure 64 Delayed Burst Read QSpan as M68040 Slave 353 Figure 65 Posted Burst Write QSpan as M68040 Slave 354 Figure 66 Register Reads QSpan as M68040 Slave
15. 43 Figure 5 Target Channel Functional 58 Figure 6 Address Generator for PCI Target Channel 65 Figure 7 Channel Functional 86 Figure 8 DMA Channel Functional Diagram 96 Figure 9 Linked List DMA 101 Figure 10 Register Channel Functional Diagram 106 Figure 11 QSpan II Control and Status Registers 107 Figure 12 QCSR Access from the QBus 109 Figure 13 Example of a Register Access Synchronization 113 Figure 14 Interrupt Channel Functional 116 Figure 15 EEPROM Channel Functional 124 Figure 16 Sequential Read from 125 Figure 17 L O Messaging Unit Functional 134 Figure 18 I O 1 135 Figure 19 PCI Bus Arbiter Functional 142 Figure 20 PCI Bus Arbiter Arbitration S
16. Ons 50ns 100ns 150ns 200ns 250ns Mea apes ea al a deep eL alt all 0 4 1201 QCLK ANT NT W y k t253b 41259 1_ f k 1253a K t259a AS A 31 0 d4 t259c k t258 D 31 0 i t254 gt t259d DACK_ DONE_ 1212 1210 1236 DSACKO_ 7 212 t210c 236c DSACKI L QSpan II User Manual 329 8091862 001 08 Appendix B Timing Figure 40 MC68360 IDMA Read Dual Address Fast Termination Ons 25ns 50ns 75ns 100ns 125ns 5 sits STAN s tM bv pre Ep ze lt t201 QCLK a ns c o odit O 12530 gt 4 12590 CSPCI 259 k 1253a AS cape 82 A 31 0 1251 1252 6 0131 0 pou t259d 1254 DACK_ DONE_ During IDMA fast termination cycles the maximum MC68360 QCLK frequency is 30 MHz 330 QSpan II User Manual 8091862 001 08 Appendix B Timing Figure 41 MC68360 IDMA Read Dual Address Fast Termination Ons 5 50ns 75ns 100ns 125ns porri ps Aut she ai aiid lt t201 gt QCLK k 1253b 1259b CSPCI X 21259 k 1253a AS A 31 0 t259c 01125 D 31 0 4 DT 1254 e DACK Net ad DONE QSpan II User
17. LAUR CEU ERA Re 159 15 2 JTAG ise rese tice cie edes rer te ie RD Pom RO 160 15 3 Decoupling 2 4 160 Chapter 16 Signals i aab rer aetna acea rapta 161 161 JXernnimnology scel eade pasear dads dee see CoD st eta eds 161 16 2 Overview Ameis dereud hinder eder durer race deck d 162 16 3 MC68360 Signals QUICC rut e RR e Tee er a goce n 163 16 4 MPC860 Signals PowerQUICC 167 165 68040 171 16 6 PCI B s 22 2 222 2222 4 2 Eh Ra te 174 16 7 Hot Swap Signals se ce dee o o Re etd e Reb oe ade heads 176 16 8 Miscellaneous 0 2 177 16 9 JTAG Signals ha ee a dia a ea 178 10 QSpan II User Manual 8091862 001 08 Contents Chapter 17 Signals and DC Characteristics 179 171 Terminology sic inei We a ne Rete 179 17 2 Packaging and Voltage Level 180 17 3 Signals and DC Characteristics 180 17 4 ee RGR ee eT
18. QSpan II User Manual 8091862 001 08 November 2009 6024 Silver Creek Valley Road San Jose California 95138 Telephone 800 345 7015 408 284 8200 FAX 408 284 2775 Printed in U S A 2009 Integrated Device Technology Inc GENERAL DISCLAIMER Integrated Device Technology Inc reserves the right to make changes to its products or specifications at any time without notice in order to improve design or performance and to supply the best possible product IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent patent rights or other rights of Integrated Device Technology Inc CODE DISCLAIMER Code examples provided by IDT are for illustrative purposes only and should not be relied upon for developing applications Any use of the code examples below is completely at your own risk IDT MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND CONCERNING THE NONINFRINGEMENT QUALITY SAFETY OR SUITABILITY OF THE CODE EITHER EXPRESS OR IMPLIED INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICU LAR PURPOSE OR NON INFRINGEMENT FURTHER IDT MAKES NO REPRESENTATIONS OR WARRANTIES AS TO T
19. Ons 100ns 200ns 300ns bot gd dg lo sp de 4 Ld dod 1301 QCLK Vas CY GG _ k t337a gt 15 A 31 0 a k t337c gt 19155 CSREG_ gt 13d gt 13 15 BURST_ Mos 01337 gt 1315 SIZ 1 0 1337 gt 13157 TC 3 0 je 337d gt ej t315p k 9 03376 gt 15 TS_ tal 13e gt 81315 D 31 0 t335a 310f 01336 w J TEA TRETRY a Normal 1335 0003101 gt 1 336 TRETRY_ f b Retry Due to internal synchronization the number of wait states may vary 342 QSpan II User Manual 8091862 001 08 Appendix B Timing B 4 3 3 QBus IDMA Cycles MPC860 Figure 53 MPC860 DREQ_ Timing Ons 50ns 100ns LL dE d d dE dE d dd P 1301 4 SET 22 X X Maso DREQ_ tj Table 160 Direction of QBus Signals During MPC860 IDMA Cycles Single Address Dual Address CSPCI I eem asserted a SENE SEEN DEM I write I _ NES O read O read a I Input O Output N A Not Applicable b QSpanllignores DONE during MPC860 IDMA cycles QSpan II User Manual 343 8091862 001 08 Appendix B Timing Figure 54 MPC860 IDMA Read Single Address Ons 50ns 100ns 150ns 200ns fc es a D
20. 372 C 2 1 14 Software 1 373 M68040 Intertaces eir o tent fa aed 374 Hardware Interface Se or eed eS eer RR es 375 Clocking 25 375 C312 CRESCUS RSS 375 C313 Address Decoder da att ee 376 3 1 4 QBus Direct Connects 376 C3 LSS Interrupts ag a wegen cs e ea bs v b Rn 376 QSpan II User Manual 8091862 001 08 Contents 3 1 6 PCL Signals eh E Re aei Were ad en 377 C 3 1 7 EEPROM Interface i e Ee Re habe ee be 3T C318 Reset Options ci eiue a cbe bed cio big nie 377 C 3 1 9 Unused Inputs Requiring Pull Ups 378 C 3 1 10 NO cio eset ruo Qc Roe Rr e aci S order 378 3 1 11 JTAG Signals REEL ee eae a 378 Appendix D Software 7 379 D 1 Miscellaneous Control Register 380 D 2 Slave Channel Initialization 382 D 3 Register Access from the 383 D4 PCI Target Channel 2
21. B 4 3 2 QBus Slave Cycle MPC860 Figure 47 Single Read QSpan II as MPC860 Slave Ons 50ns 100ns 150ns 200ns 250ns Ld b Pob Robo oh 4d Pot d d P P d d td 31301 9 OUR Rl qo 442 5352 Xo k t337a 113154 A 31 0 k t337b 19213151 CSPCI 9113131 gt 131 5i IMSEL X X je t313d Pace BURST_ k91337e 1315 SIZ 1 0 113371 1315 TC 3 0 E911337d 11315 R W_ 1315p 1337 TS_ 1314 t314 t316 D 31 0 ex t335a t310f 1336 TA 4 7 TEA 4 TRETRY a Normal TEA p t335c I 9 131 0i I 9 1336i TRETRY p b Retry 1335b 9t310h t336h TEA X A TRETRY zi c Bus Error QSpan II User Manual 337 8091862 001 08 Appendix B Timing Figure 48 Single Write QSpan II as MPC860 Slave Ons 100ns 200ns 300ns lt 301 gt QCLK gt 1337 gt 1315 A 31 0 2113376 gt 13151 CSPCI_ gt t313f gt 315 IMSEL X X gt e t313d gt k1315e BURST_ gt 37 gt 1315 SIZ 1 0 k911337t gt 3 15 01 gt 1337 gt 1315 R W_ 1315p 13379 TS_ R 1313e 1 1315h D 31 0 1335 13101 1336 TA 4 jy TEA_ TRETRY_ a Normal TA 1335 0113101 gt 336i TRETRY g b Retry 1335
22. TRETRY_ c Bus Error QSpan II User Manual 333 8091862 001 08 Appendix B Timing Figure 44 Single Write QSpan II as MPC860 Master Ons 100ns 200ns 300ns 301 gt QCLK 1311 t311 BR gt 1313 e t315d BG 1312 13106 13366 _ u LI I 41310a 91336a A 31 0 gt t310c t336c BURST_ gt 1310 gt t336e SIZ 1 0 L4 13109 gt 1336g TC 3 0 29 gt t310d gt t336d R W_ A y t312b t310j gt t336j TS a uy t334 4t316 D 31 0 NP gt kt315l le 313g TEA TRETRY a Normal 13150 1131 TRETRY p b Retry TA X gt t315n e t313h TRETRY c Bus Error 334 QSpan II User Manual 8091862_MA001_08 Figure 45 Burst Read QSpan as MPC860 Master Appendix B Timing os 100ns 200ns 300ns 400ns 1301 gt QCLK 311 gt 1311 BR 7 gt 44313 13154 BG 1312a gt 10b gt 336b BB gt 1310 gt 1336 31 0 gt 1310 gt 1336 BURST_ a gt 310k gt 1336k BDIP_ hN gt 1336 SIZ 1 0 gt 336g 3 0 gt 13104 gt 13364 R W_
23. Register 384 BRSTWREN bit Bursting on the QBus 75 PBTIO_CTL Register 224 Register 228 BS field PBROM_CTL Register 232 389 PBTIO_CTL Register 224 384 413 Index PBTII Register 228 384 QBSIO AT Register 287 382 QBSII AT Register 291 382 Burst Transfer PCI Target Channel 74 78 target disconnect 82 83 QBus Slave Channel 41 53 286 289 290 translation 46 write 40 BURST_ TIP_ 168 172 183 BURST 4 bit DMA CS Register 255 MISC CTL2 Register 281 381 Bus Error 34 burst 286 290 IDMA 91 91 93 248 262 INT CTL register 265 INT DIR register 268 INT STAT register 262 logging PCI Target Channel 84 logging QBus Slave Channel 56 PB DERR register 237 PB ERRCS register 234 PCI Master Module 55 QB ERRCS register 293 QBus Master Module 81 QBus Slave Module 53 286 290 burst 49 50 signaling 54 QBus Slave Module signaling 54 translation PCI Target Channel 84 Bus Parking 42 144 PCI Bus Arbiter 144 Bus Request 183 PCI bus 42 176 185 QBus 78 164 167 BUS NUM field CON ADD Register 258 387 Byte Lane EEPROM 129 C C BE 1 183 C BE 2 183 C BE 3 183 C BE 3 0 45 174 183 Cacheline 74 83 CAP ID field 414 CPCI HS Register 221 PCI PMC Register 219 PCI VPD Register 222 CAP L bit PCI CS Register 204 CAP PT field PCI CP Register 217 Capacitors 160 CCODE field PCI MISCO Register 207 CDATA field CON DATA Register 260 387 CHAIN bit IDMA DMA CS Re
24. an 4136 410g a 312 QSpan II User Manual 8091862 001 08 Appendix B Timing Table 156 Timing Parameters for M68040 Interface Continued Timing Parameter Description Units Note m ns 41158 IMSEL hold from QCLK positive edge t415i R W_ hold from QCLK positive edge t415j SIZ hold from QCLK positive edge Epsom p Ea E 415m 52 we ones NES ES t417 D valid from QCLK positive edge slave reads t419f TC setup to QCLK positive edge t419g TS_ setup to QCLK positive edge t436a A negated from QCLK positive edge t436b BB_ negated from QCLK positive edge t4150 TS_ hold from QCLK positive edge t416 D tristated from QCLK positive edge 1 1 QSpan User Manual 313 8091862 001 08 Appendix B Timing Table 156 Timing Parameters for M68040 Interface Continued Timing Parameter Description Units Note negated from QCLK positive edge TC negated from QCLK positive edge d _ negated from QCLK positive edge TS_ negated from QCLK positive edge 1 Minimum output hold time specified for load of 10 pF Maximum output delay specified for load of 50 pF 2 Minimum output hold time specified for load of 10 pF Maximum output delay specified for load of 35 pF 3 Measured at 1 5 volts 314 QSpan II User Manual 8091862 001 08 App
25. Reset Reset By State Function G RST QBus Software Reset Control 0 software reset not active 1 software reset active G_RST See below Synchronous Bus Grant 0 BG_ input is asynchronous to QCLK 1 BG_ input is synchronous to QCLK G_RST See below Synchronous Bus Grant Acknowledge 0 BG_ input is asynchronous to QCLK 1 BG_ input is synchronous to QCLK G_RST QBus Byte Ordering Control MISC_CTL Description 0 QBus uses Big Endian byte ordering 1 QBus uses PCI Little Endian byte ordering the MA BE D bit should be set to 1 before any PCI configuration cycles are performed if the QSpan ILis being used as a host bridge This bit must be set to 0 This bit must be set to 0 RST Master Abort Bus Error Mapping Disable Applies to delayed transfers 0 When QSpan II issues a PCI Master Abort it maps this termination to the QBus as a bus error behaves in the same manner as previous QSpan designs 1 When QSpan II receives a PCI Master Abort it maps this as a normal termination on the QBus On writes data is flushed from the channel and on reads the QSpan II returns all ones In order to comply with the PCI 2 2 Specification 216 QSpan II User Manual 8091862 001 08 Appendix A Registers MISC_CTL Description Continued Reset Name Type Reset By State Function PRCNT 5 0 R W G_RST 000001 Prefetch Read Byte Count This field controls how much data the QSpan II prefetches on the QBus The numb
26. t409b t410g 1436 TEA c Bus Error 352 QSpan II User Manual 8091862 001 08 Appendix B Timing Figure 64 Delayed Burst Read QSpan II as M68040 Slave Ons 250ns 1401 gt X Ww Xo X Ae Duc Ar Qa v AL gt 419 15a A 31 0 4156 gt 41419 CSPCI_ Aula f k 9t413d 1415 IMSEL X X gt t413g 4 14154 BURST _ TIP_ gt kt4l9e 601415 SIZ 1 0 gt t419f 14151 TC 3 0 gt 4194 4151 R W_ V 314150 gt 0419 TS_ 418 418 418 418 t417 e417 417 910417 1417 D 31 0 t409a t410e t410e TA g TEA_ Wait states are inserted if the starting address is not aligned to 16 byte boundary QSpan II User Manual 353 8091862 001 08 Appendix B Timing Figure 65 Posted Burst Write QSpan as M68040 Slave QCLK 31 0 CSPCI_ IMSEL BURST_ TIP_ SIZ 1 0 TC 3 0 R W TS D 31 0 TA _ 250ns 401 gt E 0 N gt 1419 8 9 415 t415e pn 13 K t415h X 4136 6 6 415d gt 41 21415 gt lt t419F 4 t4 151 gt 104
27. 1 4 1 BERR a HALT a a Normal gt t212a gt f t210c gt t236c DSACKO p X lx gt 1212 gt t210c gt j t236c DSACKI p gt t212b gt t210b gt t236b BERR p 7 gt t212c gt t210d gt f t235d HALT p A TS b Retry t212a gt f t210c gt t236c N t212a gt t210c gt t236c DSACKI M 1212b Let 210b gt j t236b BERR HALT c Bus Error QSpan II User Manual 321 8091862 001 08 Appendix B Timing Figure 31 Register Read QSpan as MC68360 Slave Ons 100ns 200ns 300ns 201 QCLK gt 12190 gt 41220 CSREG_ gt 1219p 220a 31 0 4A 219 1220h TC 3 0 4 gt 42190 gt 412200 SIZ 1 0 4 gt 213 gt 1214 D 31 0 gt 1219 gt 1412201 R W_ EL t2 9b gt 219b gt 1240b AS 1212a 1210 1236 DSACKO a A e 1212a 1210 1236 DSACKI A BERR_ HALT_ a Normal t212a gt 1210 t236c DSACKO_ a gt t212a gt 1210 gt 1236c DSACKI vA E 212b 12106 i 1236b BERR p a fy gt l t212c t210d 12360 HALT_ Y 7 b Retry 322 QSpan II User Manual 8091862 001 08 Appendix B Timing Fi
28. 81 QSpan II User Manual 19 8091862 001 08 List of Tables Table 29 Table 27 Table 30 Table 32 Table 31 Table 34 Table 35 Table 36 Table 33 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 20 M68040 Cycle Terminations of QBus Master Module 81 MC68360 Cycle Terminations of QBus Master 81 Translation of Cycle Termination from QBus to PCI 84 Interrupt Source Enabling Mapping Status and Clear bits 92 QSpan I s Response to IDMA Errors 92 16 Bit Big Endian IDMA Cycle 94 32 Bit Little Endian IDMA Cycle Mapping 94 32 Bit Big Endian IDMA Cycle 94 16 Bit Little Endian IDMA Cycle 94 PCI Memory Cycle Access to bits 15 08 of the PCI CLASS register 108 Big Endian QBus Access to bits 15 08 of the PCI CLASS register 110 Little Endian QBus Access to bits 15 08 of the PCI CLASS register 110 PCI AD 31 16 lines asserted as a
29. Appendix A Registers Table 101 ILO Inbound Free List Top Pointer Register Register Name IIF TP Register Offset 204 Function QIBA Reserved IIF TP Description Reset Name Type Reset By State Function QIBA 31 20 BINE RST QBus LO Base Address specified in DO CS IF TP 19 2 R W G RST Inbound Free List Top Pointer This pointer gives the address offset for the Inbound Free List Top Pointer This register is initialized and maintained by the QBus Host 240 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 102 1 0 Inbound Free List Bottom Pointer Register Register Name IIF BP Register Offset 208 Function QIBA Reserved IIF BP Description Reset Name Type Reset By State Function QIBA 31 20 HEN RST QBus LO Base Address specified in DO CS IF BP 19 2 R W G RST Inbound Free List Bottom Pointer This pointer gives the address offset for the Inbound Free List Bottom Pointer This register is initialized by the QBus Host but is maintained by QSpan II and is incremented by four modulo boundary of FIFO SIZE QSpan II User Manual 241 8091862 001 08 Appendix A Registers Table 103 ILO Inbound Post List Top Pointer Register Register Name IIP TP Register Offset 20C Function QIBA Reserved IIP TP Description Reset Name Type Reset By State Function QIBA 31 20 BINE RST QBus LO Base Address specified in DO CS IP TP 19 2 R
30. If the CP LOC is set to 0 the DMA Channel reads the command packet from PCI memory using a burst read cycle If a PCI error is encountered during this read the Linked List DMA is terminated and the IPE status bit in IDMA DMA CS is set QSpan II User Manual 103 8091862 001 08 Chapter 6 The DMA Channel 6 4 2 Terminating a Linked List Mode DMA Operation To terminate a Linked List DMA operation set the IRST_REQ bit to 1 In this case the Linked List DMA is terminated and the IRST status bit is set in the IDMA DMA CS register once the DMA Channel finishes any active transfers The STOP bit in DMA_CS can temporarily stop the Linked List DMA This can be used to free up PCI bus or QBus bandwidth for time sensitive data transfers Any updates to the command packets can be completed before the STOP bit is cleared and the Linked List DMA is resumed The STOP STAT bit in DMA_CS indicates when the DMA Channel is stopped At this point any updates to the command packets in memory can be finished The ACT bit in IDMA DMA CS is still set when the DMA is temporarily stopped The ACT bit is cleared when the Linked List DMA is completed an IRST_REQ is generated or a bus error on PCI bus or QBus is encountered 104 QSpan II User Manual 8091862 001 08 Chapter 7 The Register Channel This chapter describes the QSpan II s Register Channel The following topics are discussed e Register Access Fairness on page 106 e Register
31. MC68360 users can indicate whether fast termination mode is to be used for dual address or single address IDMA cycle bits QTERM and STERM in the IDMA DMA CS register see Table 109 on page 248 The Programmable I FIFO Watermark IWM field controls the burst read length on the PCI bus if it is set to a non zero value see Table 113 on page 254 If IWM equals 0 then the QSpan II PCI burst read length equals the CLINE setting see Table 113 on page 254 The CLINE 1 0 field of the PCI MISCO register see Table 72 on page 207 determines how much data is read by the PCI Master Module either four or eight 32 bit transfers within a burst read if the IWM is set to zero The IDMA DMA PADD register contains the absolute PCI address for an IDMA transaction see Table 110 on page 251 This address is aligned to a 4 byte boundary A1 and AO always equal 0 If an IDMA transfer is required to cross an A24 boundary it must be programmed as two separate transactions 87 Chapter 5 The IDMA Channel 5 2 1 88 The CMD bit in the IDMA DMA CS register determines whether the read transaction on PCI proceeds as a Memory Read Line transaction or a Memory Read Multiple transaction see Table 109 on page 248 The IDMA DMA_CNT register must be programmed to indicate the amount of data to transfer see Table 111 on page 252 The MC68360 s count register and the QSpan II s IDMA DMA CNT register must be programmed with the same
32. MISC CTL MA BE D This bit should be set to 1 so that when a PCI Master Abort occurs during a PCI Configuration cycle a normal data acknowledgement is signaled to the QBus processor IACK GEN IACK VEC When the register is read the QSpan II will perform a PCI IACK Cycle The QBus master is retried until the cycle completes on the PCI Bus The value from the PCI IACK is stored temporarily in this register while waiting for the QBus master to perform an additional read to obtain the vector QSpan II User Manual 387 8091862 001 08 Appendix D Software Initialization D 9 EEPROM and VPD Initialization Many of the QSpan II s operating parameters be set by a serial EEPROM see Chapter 9 The EEPROM Channel on page 123 It is possible to program the serial EEPROM by accessing a QSpan II register EEPROM CS It is possible to program Vital Product Data VPD information into the serial EEPROM by writing to the PCI_VPD register For additional programming details about EEPROM and VPD see Chapter 9 The EEPROM Channel on page 123 D 10 1 0 Messaging Unit Initialization To initialize the I50 Messaging Unit complete the following steps 1 Start the QSpan II in PCI disable mode by setting the PCI DIS bit to 1 in the MISC CTL2 register see Table 130 on page 280 2 Setthe PCI CLASS register from the EEPROM or the QBus processor see Table 71 on page 206 3 Setthe I2O EN bitto 1 in the I2O CS register see Tabl
33. Only the PCI Configuration registers are accessible through PCI Configuration Type 0 cycles PCI Configuration registers that reside in the lower 256 bytes of QCSR space are accessible in PCI Configuration space QSpan II s PCI interface decodes AD 7 2 for accesses to its PCI Configuration registers IDSEL must be asserted for Type 0 Configuration access Configuration access from the QBus is discussed in PCI Configuration Cycles Generated from the QBus on page 110 QSpan II User Manual 107 8091862 001 08 Chapter 7 The Register Channel 108 QSpan II registers can be accessed in Memory space but not in I O space To access QCSRs from PCI bus Memory space it is necessary to set the Memory Space bit in the PCI_CS register to 1 see Table 70 on page 203 This step is required for any PCI Target Module access including register accesses The SPACE bit is fixed at 0 so that registers can be accessed in PCI Memory space BA 31 12 field of the PCI BSM register specifies the base address in memory space of the QCSRs The QCSRs are located in Memory space as address offsets of this base address see Figure 11 There is a direct mapping between values on the AD 11 0 lines and the register offsets The following table illustrates PCI Memory cycle access to bits 15 08 of the PCI CLASS register see Table 71 on page 206 This table shows the AD 11 0 and 3 0 signals required to access byte 1 This table al
34. 001 08 Appendix A Registers Table 106 ILO Outbound Free List Bottom Pointer Register Register Name IOF BP Register Offset 218 Function QIBA Reserved IOF BP Description Reset Name Type Reset By State Function QIBA 31 20 HE RST QBus LO Base Address specified in DO CS OF BP 19 2 R W G RST Outbound Free List Bottom Pointer This pointer gives the address offset for the Outbound Free List Bottom Pointer This register is initialized and maintained by the QBus Host QSpan II User Manual 245 8091862 001 08 Appendix A Registers Table 107 ILO Outbound Post List Top Pointer Register Register Name IOP TP Register Offset 21C Function QIBA Reserved IOP TP Description Reset Name Type Reset By State Function QIBA 31 20 G_RST QBus LO Base Address specified in DO CS OP TP 19 2 R W G RST Outbound Post List Top Pointer This pointer gives the address offset for the Outbound Post List Bottom Pointer This register is initialized and maintained by the QBus Host 246 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 108 ILO Outbound Post List Bottom Pointer Register Register Name IOP_BP Register Offset 220 Function QIBA Reserved IOP_BP Description Reset Name Type Reset By State Function QIBA 31 20 G_RST QBus 1 0 Base Address specified in I2O CS OP BP 19 2 R W G RST Outbound Post List Bottom Pointer T
35. 286 Table 136 QSpan II Response to a Single Write Cycle 286 Table 137 QSpan II Response to a Burst Write Cycle 286 Table 138 QBus Slave Image 0 Address Translation 287 Table 139 Address Lines Translated as a Function of Block 5 2 288 Table 140 QBus Slave Image 1 Control 289 Table 141 QSpan II Response to a Single Read Cycle Access 290 Table 142 QSpan II Response to a Burst Read Cycle Access 290 Table 143 QSpan II Response to a Single Write Cycle 290 Table 144 QSpan II Response to a Burst Write Cycle 290 Table 145 QBus Slave Image 1 Address Translation 291 Table 146 QBus Address Lines Compared as a function of Block 292 Table 147 QBus Error Log Control and Status 293 Table 148 QBus Address Error 1 294 Table 149 QBus Data Error 295 Table 150 120 Outbound Post List Interrupt Status 296 Table 151 120 Outbound Post List Interrupt Ma
36. Channel functions as an MC68360 or an MPC860 IDMA peripheral QSpan II only supports level sensitive handshaking with the MPC860 QSpan II supports single address and dual address IDMA transfers QSpan II determines the type of IDMA transfer by detecting the state of the CSPCI_ pin when the IDMA cycle begins If CSPCI_ is negated when AS_ MC68360 applications or TS_ MPC860 applications is asserted then single address mode is selected CSPCI_ must be detected asserted when the cycle begins in order to use dual address IDMA transfer mode This requires that the address programmed in the MPC860 s or MC68360 s buffer pointer register cause the QSpan s CSPCI chip select to be activated QSpan II does not latch the address off the QBus during dual address IDMA transfers 5 2 PCI Read Transactions This section describes the operation and programming of the QSpan II to move data from the PCI bus to the QBus using the processor s IDMA The IDMA registers within the QSpan II need to be programmed for a read transaction as follows QSpan II User Manual 8091862 001 08 The direction of the transfer must be set for reads To do this set the IDMA Direction DIR bit to 0 in the IDMA DMA CS register see Table 109 on page 248 The IDMA Channel can operate in one direction at a time The QBus Port 16 PORT10O bit of the IDMA DMA CS register indicates whether IDMA transfers will be 16 or 32 bit on the QBus see Table 109 on page 248
37. DSACKI tristated 9 4 10 4 ns from QCLK negative edge BERR_ tristated from QCLK 10 6 ns negative edge to12c HALT tristated from QCLK 9 1 10 1 ns negative edge t213 D asserted slave reads from 14 8 16 4 ns 1 QCLK negative edge QSpan User Manual 303 8091862 001 08 Appendix B Timing Table 154 Timing Parameters for MC68360 Interface Continued Frequency Temperature Options Timing Parameter Description EE e Units Note 14 D tristated Ee REN reads from positive Ee REN 2154 AS asserted from QCLK negative ns edge t215b DS_ asserted from QCLK negative 7 8 8 7 ns edge t216a AS tristated from QCLK positive 7 9 8 8 ns edge t216b DS tristated from QCLK 8 1 ns positive edge t217a BERR_ setup to QCLK negative ns edge t217b BG_ setup to QCLK negative 1 0 ns edge t217c BGACK_ setup to QCLK negative ns edge DSACKO DSACK1_ setup to ns QCLK negative edge 517e HALT setup to QCLK negative ns edge BERR_ hold from QCLK negative ns edge t218b BG hold from QCLK negative ns edge o18c BGACK hold from QCLK 1 4 1 5 ns negative edge t2184 DSACKO DSACK1_ hold from ns QCLK negative edge t218e HALT_ hold from QCLK negative edge tion 19a A ae to A setup to QCLK negative edge negative A setup to QCLK negative edge ee ee setup to QCLK negative 2 8 edge 304 QSpan II User Manual 8091862 001 08 Appe
38. Transaction Decoding and QBus Slave Images on page 39 Tables 141 to 144 indicate how the QSpan II Slave module responds to QBus masters as a function of the PWEN and PAS bits setting Unlike Slave Image 0 this register cannot be programmed with a serial EEPROM QSpan II User Manual 289 8091862 001 08 Appendix A Registers Table 141 QSpan II Response to a Single Read Cycle Access PREN Read Cycle R W negated Delayed Read Table 142 QSpan II Response to a Burst Read Cycle Access Read Cycle R W negated Delayed Read S 1 PA Delayed Read Write Cycle R W asserted Delayed Write Delayed Write 290 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 145 QBus Slave Image 1 Address Translation Register Register Name QBSI1 AT Register Offset F14 31 24 23 16 15 08 Reserved 5 AT Description Reset Name Type Reset By State Function TA 31 16 R W G RST Translation Address See below G RST Enable Address Translation 0 Disable 1 Enable The Translation Address specifies the values of the address lines substituted when generating the address for the transaction on the PCI bus Address translation is enabled by setting the EN bit The Block Size determines which address lines are translated see Table 146 Unlike Slave Image 0 this register cannot be programmed with a serial EEPROM QSpan
39. VPD_ADDR R W PCI_RST 0x00 VPD Address 7 0 4 byte aligned byte address of the VPD to be accessed NXT_IP 7 0 PCI_RST 0x00 Next Item Pointer This is the last item in the linked list so the pointer is set to 0 CAP_ID 7 0 PCI_RST 0x03 Capability ID Set to 0x03 to indicate that this linked list register supports the Vital Product Data access 222 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 88 PCI VPD Data Register Register Name VPD_DATA Register Offset 31 24 VPD_DATA 23 16 VPD_DATA 15 08 VPD_DATA 07 00 VPD_DATA PCI_VPD Description Reset Name Type Reset By State Function VPD_DATA R W PCI_RST VPD Data 31 0 This contains the VPD read or write data On a read this register will be valid after the read was initiated and the QSpan II sets the VPD_F bit to 1 On a write the data should be written to this field before the write is initiated by writing to the PCI_VPD register VPD DATA T7 0 will contain the byte specified by the VPD ADDR QSpan II User Manual 223 8091862 001 08 Appendix A Registers Table 89 PCI Bus Target Image 0 Control Register Register Name 0 Register Offset 100 Bits Function 15 08 TC DSIZE Reserved 07 00 PWEN Reserved PBTIO CTL Description Reset Name Type Reset By State Function EN R W RST Image Enable 0 Disable 1 Enable BS 3 0 See PCI_RST See Block Size 64 Kbyte 25 Below Below PREN R W G RST Prefe
40. be eA SGA a ep 187 OB s Address Pins cose e ERR UMS Bey 188 OBus Pins 189 External Request and Grant Pins 189 Pin Assignments for Power Vn 125 srl Bart RE Sri S CIR e i a 190 Voltage Required to be Applied to VH 190 QSpan II User Manual 8091862 001 08 List of Tables Table 63 Pin Assignments for Ground 191 Table 64 No connect Pin 191 Table 65 Pinout of 17x17 mm Package 192 Table 66 Pinout of 27 27 mm Package 193 lable67 Register Map isole b stes ie y edes 197 Table 68 120 Memory Map 4 201 Table 69 PCI Configuration Space ID 202 Table 70 PCI Configuration Space Control and Status Register 203 Table 71 PCI Configuration Class Register 206 Table 72 PCI Configuration Miscellaneous 0 207 Table 73 PCI Configuration Base Address for Memory Register 208 Table 74 120 Base Address 209 Table 7
41. 1 383 D 5 Error Logging of Posted Transactions 385 D 6 IDMA DMA Channel Initialization 386 D 7 Interrupt 1 386 D 8 Generation of PCI Configuration and IACK 387 D 9 EEPROM and VPD 2 388 D 10 1 0 Messaging Unit 388 D 11 PCI Expansion ROM Implementation 389 Appendix E Endian 391 Overview c cues ed sen ERI a Ga EA Adr ael dnos ores doen er d ee 391 B2 Systemic e cese eee rg once e t td Roa o a DR Er ae 392 B3 System cuossuuled sues cR Reb b ew Waleed Eb E ER nS 393 E A Endian Mapping 1 394 E 4 1 Address 394 2 DatalInvariance ode bee eR XH E RARE aa eee 395 B 43 Combined ER Ru EVE S 395 Appendix F Operating and Storage Conditions 397 El Power Dissipation ecce eR RC da Pk he Dae 397 E Operating Conditions
42. 190 QSpan II User Manual 8091862 001 08 Chapter 17 Signals and DC Characteristics Table 63 Pin Assignments for Ground o mmm C oe ff m9 Q a Route all N C signals out to vias on your board to allow for future migration to new QSpan II variants QSpan II User Manual 191 8091862 001 08 Chapter 17 Signals and DC Characteristics 17 4 Pinout Table 65 Pinout of 17x17 mm Package Al A2 A3 A4 AS A6 AT 8 9 D 25 D 23 D 22 DP 0 A 25 A 21 A 20 A 16 A10 D 17 All D 13 A12 A 14 A13 A 13 A14 TEST2 15 A 9 A16 VH Bl B2 B3 B4 B5 B6 B7 B8 B9 D 28 VH D 26 D 24 DP 2 D 20 22 18 D 18 B10 D 15 B11 A 15 B12 TEST1 B13 N C B14 D 10 B15 D 11 B16 7 Cl C2 C3 C4 C5 C6 C7 C8 C9 A 26 D 27 PCI ARB EN DP 1 A 24 A 19 D 19 D 16 CIO DS C11 A 11 C12 TEST3 C13 A 6 C14 A 8 C15 D 9 C16 D 8 DI D2 D3 D4 R W_ D 30 D 29 DP 3 192 DS D 21 D6 A 23 D7 A 17 D8 QCLK D9 D 14 D10 D 12 D11 A 12 D12 A 10 D13 N C D14 D 7 D15 D 4 D16 D 3 E1 A 29 E2 N C E3 A 27 E4 A 28 E5 VDD E6 VDD E7 VDD E8 VDD E9 VDD E10 VDD Ell VDD E12 VDD E13 D 6 E14 D 2 E15 D 1 E16 A 5 F1 DSACK1_ TA_
43. 2 Clear the status bit in the INT_STAT register To negate INT when its assertion is caused by the assertion of QINT_ negate QINT_ and then clear the QINT_IS bit in the INT_STAT register 8 3 Software Triggered Interrupts QSpan can generate interrupts based upon internal events provided that the interrupt source is enabled in the INT_CTL register see Table 120 on page 265 Interrupts can be mapped to an interrupt output pin on the PCI bus INT or the QBus QINT_ depending on the value of the interrupt mapping bit in the INT_DIR register see Table 121 on page 268 The status of the individual interrupt sources can be determined by reading the corresponding status bit see Table 119 on page 262 To clear an interrupt the original interrupt source must be cleared first For example to clear the Reset Interrupt the IRST bit in the IDMA DMA CS register must be cleared first see Table 109 on page 248 QSpan User Manual 117 8091862 001 08 Chapter 8 The Interrupt Channel Table 42 Interrupt Source Enabling Mapping Status and Clear bits Enable Bits Mapping Bits Interrupt Status Bits Source Bits INT_CTL see Table 120 INT_DIR see Table 121 INT_STAT see Table 119 Source Write 1 to clear on page 265 on page 268 on page 262 QBus Slave Channel Errors Error on the PCI bus PCI Bus Error ES in PB ERRCS PEL DIR see Table 97 on page 234 Data Parity Error MD PED in PCI CS MDPED EN MDPED DIR MDPED IS
44. 412 QSpan II User Manual 8091862 001 08 Index Numerics 17 x 17 mm package 401 27 x 27 mm package 403 A A 31 0 163 167 171 183 ACT bit EEPROM_CS Register 279 IDMA DMA CS Register 248 AD 31 0 174 183 ADDR field EEPROM CS Register 279 IDMA DMA PADD Register 251 386 Address Phase Configuration Cycle 111 258 IDMA Channel 87 89 QBus 39 43 Address Translation PCI Target Channel 64 QBus Slave Channel 42 APS bit PCI PMC Register 219 Arbitration PCI bus 42 QBus 78 80 164 167 Register Channel 105 Arbitration Scheme PCI Bus Arbiter 142 8 39 41 163 183 324 Assigning the Base Address 61 64 AT 0 3 167 AVEC 364 376 B BA bit PCI BSM Register 383 QSpan II User Manual 8091862 001 08 BA field I20 BAR Register 209 PBTIO ADD Register 226 384 PBTII ADD Register 230 384 PCI BSM Register 208 PCI BSROM Register 215 389 PCI BSTO Register 210 PCI BSTI Register 212 BASE field PCI CLASS Register 206 BB BGACK 80 81 163 167 171 183 59 75 158 163 167 171 183 365 370 BE ERR field PB ERRCS Register 234 385 BERR TEA 81 164 167 171 183 BG 78 79 80 164 167 172 183 BGACK_ 163 BISTC bit PCI_MISCO Register 207 BM bit PCI_CS Register 110 205 386 BM_EN FIFO_RDY_ 164 168 172 183 365 BM_PARK field PARB_CTL Register 283 382 Boundary scan support 27 BR_ 78 79 80 164 168 172 183 BRSTEN bit DMA_CS Register 255 BRSTWEN bit PBTIO_CTL Register 384
45. 77 4 6 Reads and PCI Transaction Ordering 77 4 6 1 Transaction Ordering Disable Option 78 47 QbBus Arbitration and Sampling 1 4 4 78 4 7 MC68360 Bus Arbitration 0 0 cece eee nee 78 4 7 3 MPC860 Bus Arbitration 79 4 7 3 M68040 Bus 80 48 Terminations ees ae E ody pee e ep OU Ce ace oe ee A ae 80 4 8 1 Master Module 80 4 8 2 MC68360 Cycle 80 4 8 3 MPC860 Cycle 81 4 8 4 68040 Cycle Terminations 81 4 8 5 Terminations driven by the PCI Target 82 4 8 5 1 82 4 8 5 2 83 4 8 5 3 Target ADOTT E 83 4 8 6 Terminations of Posted 84 Chapter 5 The Channel visa cand 85 a dain whe
46. F2 A 31 F3 A 30 F4 SIZ 1 F5 VDD F6 VSS F7 VSS F8 VSS F9 VSS F10 VSS F11 VSS F12 VDD F13 D 5 F14 A 3 F15 D 0 F16 A 4 G1 SDA G2 SIZ 0 G3 DSACKO_ G4 ENUM G5 VDD G6 VSS G7 VSS G8 VSS G9 VSS G10 VSS G11 VSS G12 VDD G13 DREQ_ G14 A 0 G15 A 2 G16 A 1 TMODE 1 H2 HS LED H3 SCL H4 IMSEL H5 VDD H6 VSS H7 VSS H8 VSS H9 VSS 10 VSS H11 VSS H12 VDD H13 TCK H14 TRST_ 15 ENID H16 QINT_ J1 PME J2 HS_SWITCH J3 TMODE 0 J4 RESETI J5 VDD 16 VSS J7 VSS J8 VSS J9 VSS J10 VSS J11 VSS J12 VDD J13 DACK_ SDACK_ J14 BM_EN FIFO_RDY_ J15 DONE_ J16 TMS K1 RESETO_ K2 TS_ K3 PCI_DIS K4 HS_HEALTHY_ K5 VDD K6 VSS K7 VSS K8 VSS K9 VSS K10 VSS VSS K12 VDD K13 TDO K14 BDIP_ K15 TDI K16 BG_ L1 BR_ L2 BB_ BGACK_ L3 N C L4 BURST_ TIP_ L5 VDD L6 VSS L7 VSS L8 VSS L9 VSS L10 VSS L11 VSS L12 VDD L13 TC3 114 115 BERR_ TEA_ 116 AS HALT_ TRETRY_ M2 RST M3 GNT M4 REQ M5 VDD VDD M7 VDD M8 VDD M9 VDD M10 VDD M11 VDD M12 VDD M13 CSREG_ M14 INT M15 SERR M16 TC 2 NI VH N2 AD 31 N3 AD 27 4 AD 28 N5 AD 22 N6 AD 20 N7 CBE 2 N8 TRDY N9 PERR N10 PAR N11 AD 10 N12 IDSEL N13 EXT_REQ 3 N14 AD 1 N15 AD 0 N16 TC 0 1 AD 30 P2 AD 2
47. Revision 2 1 PCI Bus Power Management Interface Specification Revision 1 1 Intelligent I O Architecture Specification Revision 1 5 QSpan 860 CompactPCI Evaluation Board Manual 6091862 001 QSpan II Software Development Kit Manual 6091862 002 Motorola M68040 User s Manual Motorola MC68360 User s Manual Motorola MPC860 PowerQUICC User s Manual QSpan II User Manual 8091862 001 08 Chapter 2 Functional Overview This chapter briefly discusses the main functional components also referred to as channels of the QSpan II Please see the following chapters for a detailed explanation of each component e Chapter 3 The QBus Slave Channel on page 35 e Chapter 4 The PCI Target Channel on page 57 e Chapter 5 The IDMA Channel on page 85 e Chapter 6 The DMA Channel on page 95 e Chapter 7 The Register Channel on page 105 e Chapter 8 The Interrupt Channel on page 115 e Chapter 9 The EEPROM Channel on page 123 e Chapter 10 I0 Messaging Unit on page 133 e Chapter 11 PCI Bus Arbiter on page 141 e Chapter 12 CompactPCI Hot Swap Friendly Support on page 145 e Chapter 13 PCI Power Management Event Support on page 153 e Chapter 14 Reset Options on page 155 e Chapter 15 Hardware Implementation Issues on page 159 2 1 Overview QSpan II has two interfaces a PCI Bus Interface and a QBus Interface see Figure 2 The PCI Interface con
48. TA field PBROM Register 232 389 PBTIO ADD Register 226 384 PBTII ADD Register 230 QBSIO AT Register 287 382 QSpan II User Manual 8091862 001 08 Index QBSII AT Register 291 382 170 173 185 343 TA BE EN bit MISC CTL2 Register 281 381 Target Abort 53 55 82 83 84 defined 83 Target Disconnect 53 74 82 defined 82 Target Retry 53 82 defined 83 TC field DMA CS Register 254 IDMA DMA CS Register 249 Register 232 389 PBTIO CTL Register 224 384 Register 228 384 TC EN bit IDMA DMA CS Register 249 TC ERR field ERRCS Register 293 385 TC 1 185 TC 2 185 TC 3 0 166 170 173 185 TC 3 185 TCK 178 186 TDI 178 186 TDO 178 186 TEA_ 170 174 Termination Mode IDMA 87 89 249 TEST1 177 186 TEST2 177 186 TEST3 177 186 Test Mode Operation 159 TFBBC bit PCI CS Register 204 TIP_ 174 186 TM 2 0 376 0 186 TMODE 1 0 159 177 1 186 TMS 186 Transaction Decoding PCI Target Module 61 68 QBus Slave Module 39 Transaction Ordering 51 52 77 78 TRDY 82 83 176 186 TRETRY 170 TRST 178 186 425 Index TS_ 39 41 170 186 TT 1 0 376 TYPE bit CON_ADD Register 258 387 Typical Applications 361 U UNL_QSC bit PB_ERRCS Register 234 V VGAPS bit PCI CS Register 205 VH 177 VID field PCI ID Register 202 Vital Product Data 130 VPD Reading VPD Data 131 Writing VPD Data 131 VPD ADDR fiel
49. Table 176 Junction to Ambient Characteristics Oja at Specified Airflow 29 67 C W 25 84 C W 24 18 C W The following table shows the simulated thermal characteristics and Osc for the QSpan package Table 177 Thermal Characteristics QSpan II User Manual 399 8091862 001 08 Appendix F Operating and Storage Conditions 400 QSpan II User Manual 8091862 001 08 Appendix G Mechanical Information This appendix discusses mechanical packaging information for the QSpan II G1 Mechanical Information The following mechanical information is discussed e QSpan II PBGA 256 ball configuration 17 mm package e QSpan II PBGA 256 ball configuration 27 mm package 1 1 256 PBGA 17 mm Table 178 256 PBGA 17 mm Packaging Features Package Type 2 layer 256 terminal Plastic Ball Grid Array PBGA Package Body Size 17 X 17 mm JEDEC Specification MO 151 Variation AAF 1 QSpan II User Manual 401 8091862 001 08 Appendix G Mechanical Information Figure 84 256 PBGA 17 mm Top and Side Views j CHAMFE ES 4 PLACES Al BALL CORNE 855 EF 0 qe S a tt g bIZ SEATI NAL EF I 4X IE SIDE PE G 1 1 1 PBGA Notes 17 mm 1 dimensions conform to ANSI Y14 5 1994 Dim in mi
50. There is an internal pull down resistor on this pin to maintain backward compatibility e Ifthe PCI DIS signal is sampled high on the negation of a reset event then the QSpan II s PCI interface is disabled QSpan II will retry any attempted PCI target accesses until the PCI DIS status bit in the MISC CTL2 register is cleared see Table 130 on page 280 There is an internal pull down resistor on this pin to maintain backward compatibility Reset options are described in Chapter 14 Reset Options on page 155 C 1 1 9 Unused Inputs Requiring Pull Ups The TS and BURST_ TIP_ signals are unused inputs when the QSpan II is interfaced with an MC68360 and therefore must be pulled high C 1 1 10 No Connects The BM EN FIFO RDY signal can be left as a no connect as there is an internal weak pull down resistor In this case in order for the QSpan II to become a PCI bus master a write to the PCI CS register is required C 1 1 11 JTAG Signals QSpan II supports JTAG QSpan II s JTAG signals should be connected to the JTAG controller or to the JTAG signals of another device if devices are to be chained together If JTAG will not be supported then the JTAG signals can be left open as the inputs have internal pull up resistors QSpan II User Manual 365 8091862 001 08 Appendix C Typical Applications C 1 1 12 C 1 2 C 1 3 366 Address Multiplexing for DRAM If DRAM is used on the QBus external address multiplexing is required T
51. This can be set as a reset option Memory Space 0 Disable 1 Enable Enables the QSpan II target to accept Memory space accesses IO Space 0 Disable 1 Enable Enables the QSpan II target to accept I O space accesses The following status bits can generate an external interrupt D PE 5 SERR R_MA TA 5 TA and MD PED for more information see Interrupt Generation due to PCI Configuration Register Status Bits on page 120 QSpan II User Manual 8091862 001 08 205 Appendix A Registers Table 71 PCI Configuration Class Register Register Name PCI_CLASS Register Offset 008 Function BASE SUB PCI_CLASS Description BASE 7 0 R WQ E __ PROG 7 0 PCI RST 206 Function Base Class Code 06 Bridge Device OEh 1 0 Controller Sub Class Code 80 Other Bridge Device if BASE 06 00 I20 device if BASE OE Programming Interface 00 Other Bridge Device if BASE 06 00 I20 Inbound and Outbound FIFOs at 40h and 44h if BASE 0E 01 120 Inbound and Outbound FIFOs at 40h and 44h and Interrupt Status and Mask registers at 30h and 34h if BASE OE Revision ID 0x00 QSpan II Prototype 0x01 QSpan II Production Part QSpan II User Manual 8091862 001 08 Appendix A Registers Table 72 PCI Configuration Miscellaneous 0 Register Register Name PCI MISCO Register Offset 00C 31 24 BISTC SBIST PCI Reserved CCODE 23 16 LAYOUT 15 0
52. and those that are powered on This isolation circuitry must be implemented externally on the add in card Transition between the different power states of the add in card can be initiated by either the Host or the QBus Host writing to the Power State bits in the Power Management Control and Status Register PCI PMCS QSpan II provides multiple options to allow maximum flexibility DOto D3hot Transition a Host initiated QSpan II generates a QINT_ if PSC EN bit in INT CTL register is set QBus Host initiated QSpan II sets PME ST bit in PCI PMCS register if PME SP 3 1 in PCI register it also asserts PME if PME EN 1 in PCI D3hotto DO Transition a Host Initiated If the add in card needs to be reset then setting the Power State Change PSC_QRST bit in MISC CTL2 register causes the QSpan II to generate an internal QSpan II reset It also causes RESETO signal to be asserted for 512 to 1024 PCI clocks QSpan II will load from EEPROM if enabled If the add in card should not be reset then the QSpan II can be programmed to generate a QINT 5 EN bit is set in INT register QBus Host initiated QBus Host powered up and configured QBus Host writes to the PWR ST bits in PCI PMCS register to change the power state QSpan II then sets PME ST bit in PCI PMCS register if PME 5 0 1 in PCI register and it also asserts PME if PME EN 1 in PCI PMCS Add in card init
53. gt f t219e p20e IMSEL X X gt 12198 gt 220a A 31 0 gt 0 gt 220h TC 3 0 gt 2200 SIZ 1 0 11413 241214 D 31 0 gt ed gt 1220 RW_ 1219 gt 220b AS_ f 1210 gt 1236 DSACKO 4 a 7 era t210c gt t235c DSACK1 a a BERR 4 HALT 4 a Normal gt 12124 gt 210 gt f t236c DSACKO p 7 gt 212a gt t210c gt t236c DSACK1 p gt t212b 12106 gt 12366 a Av gt l 1212c gt 210d gt t236d HALT p g 5 b Retry b 212a gt 1210 gt t236c DSACKO a gt 1212a gt 1210 gt t236c DSACK1 7 Lo 2125 12100 gt t t236b HALT amp Bus Error 320 QSpan II User Manual 8091862 001 08 Figure 30 Single Write QSpan II as MC68360 Slave Appendix B Timing Ons 100ns 200ns 300ns 400ns lt 1201 gt QCLK gt 4 1219 220 CSPCI_ gt 2196 220e IMSEL X X gt E t219a gt e 220a 31 0 gt 1219h 220 TC 3 0 eigo gt 2209 SIZ 1 0 gt T gt mp D 31 0 gt 121 lt gt 1420f R W_ gt 1219 12206 AS_ 1212 gt ft210c gt 1236 DSACKO 4 y t212a gt f t210c gt t236c
54. mma omes 8 meme ame pee Low clamp current lt 25 Vin Vp mA 1 0 015 High clamp current Vppt4 gt Vin gt Vppt 254 Vin Vpp 015 Output ise slew rate rise slew rate 0 02Vpp0 6Vpp load 6Vpp load EJ a Equation A Iggz7 98 0 Vpp Vour V pp Vour 0 4V pp for gt Vout gt 9 7Vpp b Equation B Ip 256 Vpp Vout Vour for Ov lt Vout lt 0 18Vpp QSpan II User Manual 181 8091862 001 08 Chapter 17 Signals and DC Characteristics Table 55 5V PCI I O Signaling AC DC Electrical Characteristics Low ome o oe 5 tristate condition Switching current high 1 4 0 024 95 2 2 gt gt 0 55 Vour 0 023 Test Point VoutT 0 71 ED 0 55 0 6 Du Low clamp current 5 lt lt 1 25 1 0 01 5 a signals are 5V tolerant b Equation 119 Vout 5 25 2 45 for gt Vout gt 3 1V c Equation D 78 5 Vout 4 4 Vout for lt Vout 0 71V 182 QSpan II User Manual 8091862 001 08 Chapter 17 Signals and DC Characteristics Table 56 Pin List for QSpan II Signals 27mm PBGA Input Output Reset IOL IOH Ball Type Type Type State mA mA Interface Signal Description A 31 0 See See QBus Address Lines Table 58 Table 58 AD 31 0 Hi Z
55. offset E4h CAP_ID 7 0 PCI_RST 0x01 Capability ID Set to 0x01 to identify the linked list item as PCI Power Management Register QSpan II User Manual 219 8091862 001 08 Appendix A Registers Table 85 PCI Power Management Control and Status Register Register Name PCI PMCS Register Offset 0 0 Function 31 24 Reserved 23 16 P2P_BSE 15 08 Reserved 07 00 PCI PMCS Description Reset Name Type Reset By State Function P2P_BSE 7 0 EESH PCI RST PCI to PCI Bridge Support Extensions PME ST R Write 1 PCI RST PME Status to clear This bit is set when QSpan II would normally assert PME PME EN PCI RST regardless of PME EN bit PWR ST 1 0 PCI RST PME Enable 0 Disable 1 Enable Enables the QSpan II to assert PME Power State This field is used to both determine the current power state and set the QSpan II into a new power state If an unimplemented power state is written to this register the QSpan II completes the write but ignores the write data DO and D3 are the only states implemented 00b DO 11b D3hot ui 220 QSpan User Manual 8091862 001 08 Appendix A Registers Table 86 CompactPCI Hot Swap Register Register Name CPCI_HS Register Offset 4 Function 31 24 Reserved 15 08 NXT_IP 07 00 CAP_ID Description Reset Name Type Reset By State Function R Write 1 PCI RST ENUMf Status Insertion to clear 0 Not asserted 1 ENUM a
56. or detecting the EXT bit set in CPCI_HS from polling the Host software writes to the EXT bit to clear the EXT bit and negate ENUM It also brings the card to a quiescent state and then writes to the LOO bit to turn on the LED This indicates to the operator that the board is ready to be extracted 1 This graphic is from the CompactPCI Hot Swap Specification QSpan II User Manual 149 8091862 MAOOI 08 Chapter 12 CompactPCI Hot Swap Friendly Support As the board is removed from the system the short pin breaks contact and the HS HEALTHY pin is negated causing the QSpan II to tri state the outputs except HS LED to keep the LED on until the long pins disengage Instead of taking the board out when the LED is on the operator can close the ejector latch to indicate an insertion process In this case the insertion sequence will begin from event Close Ejector Latch and the QSpan II will not load from the EEPROM unless H5 HEALTHY is negated or RST is asserted prior to closing the ejector latch Table 46 Extraction Sequence Enna ENUM s HS LED HS SWITCH LED INS EXT Normal Operation pins break Medium pins L open on break a The card can be inserted at this point then the insertion process is started from Close Ejector Latch of the insertion sequence Table Legend of Extraction Sequence e HS_LED L gt LED On HS_LED Z gt LED Off The bits INS EXT LOO and
57. see Table 70 on page 203 QBus Error ES in ERRCS QEL_DIR see Table 147 on page 293 a IQE in IDMA DMA_CS IQE_DIR see Table 109 on page 248 IDMA DMA IPE in IDMA DMA_CS IPE_DIR PCI Bus Error see Table 109 on page 248 IRST in IDMA DMA_CS IRST_DIR IRST_IS see Table 109 on page 248 DONE in DONE_DIR DONE_IS IDMA DMA_CS see Table 109 on page 248 PCI Bus Error ES in PB ERRCS i PEL DIR see Table 97 on page 234 Miscellaneous Events PCI CS Register Status bit s in Table 70 PCSR EN PCSR DIR PCSR IS Interrupt Stai on page 203 u MailBox 3 Interrupt Statu MailBox 2 Interrupt Statu u 5 5 5 5 5 MailBox 1 EN MB1_DIR MBI IS Interrupt Sta MailBox 0 0 MBO DIR MBO IS Interrupt Statu QBus Data QDPE EN QDPE DIR Parity Error 118 QSpan II User Manual 8091862 001 08 Chapter 8 The Interrupt Channel Table 42 Interrupt Source Enabling Mapping Status and Clear bits Continued Enable Bits Mapping Bits Interrupt Status Bits Source Bits INT_CTL see Table 120 INT_DIR see Table 121 INT_STAT see Table 119 Source Write 1 to clear on page 265 on page 268 on page 262 Power State PME_EN PCI_PMCS PSC_EN PSC_DIR PSC_S Changed Interrupt see Table 85 on Status page 220 OPNE_EN OPNE_DIR OPNE_S Inbound Post_List IPN_EN IPN_DIR IPN_S New Entry Interrupt Status Outbound Post_List Not Empty Status Inbound Free_List Empty Status
58. then the PCI address is not translated but applied directly to the QBus transaction The most significant bits of the translation address are used by the Address Generator as determined by the programming of the image s block size The number of these bits used depends on the programming of the BS bit The correlation between block size and the number of most significant TA bits used in generating the QBus address is shown in Table 18 With a 64 Kbyte block size the Address Generator copies the entire translation address into the QBus address but only copies the lower 16 bits from the PCI address signal for example the Address Generator translates AD 31 16 With a 2 Gbyte block size the Address Generator copies all but bit 31 from the PCI address signal for example the Address Generator translates AD 31 only and uses the top translation address bit as bit 31 of the QBus address This manual adopts the convention that the most significant bit is always the largest number MPC860 designers must ensure that they connect their pins accordingly For example pin A 31 on the QSpan II connects to pin A 31 on the MC68360 bus but connects to pin A 0 on the MPC860 bus This applies to all MPC860 buses D 31 0 AT 3 0 TSIZ 1 0 not only the address bus The QSpan chip select inputs CSREG_ CSPCI must not be asserted when the QSpan II is initiating a cycle on the QBus QSpan II User Manual 65 8091862 001 08 Chapter
59. 23 16 BUS_NUM 15 08 DEV NUM FUNC NUM 07 00 NUM EE TYPE CON ADD Description Reset Name Reset By State Function BUS NUM G RST Bus Number 7 0 3 0 FUNC NUM R W G RST Function Number 2 0 a ud NUM G_RST Register Number 5 0 TYPE G_RST Configuration Cycle Type 0 Type 0 1 1 An access to the PCI Configuration Data Register see Table 117 on page 260 from the QBus Interface performs a corresponding Configuration cycle on the PCI bus The type of configuration cycle generated by the QSpan II is a function of the TYPE bit If the TYPE bit set to 1 an access of the PCI Configuration Data register from the QBus interface performs a corresponding Configuration Type 1 cycle on the PCI bus During the address phase of the Configuration Type 1 cycle on the PCI bus the PCI address lines carry the values encoded in the Configuration Address Register AD 31 0 CON ADDR 31 0 The QSpan II cannot perform a Type 0 Configuration cycle to a PCI target that has its IDSEL input connected to one of the AD 15 11 signals bit 15 of the ADD register is hardcoded as 0 Therefore for host 2 bridging applications hardware designer must choose to drive each PCI target s IDSEL input from one of the AD 31 16 signals 258 QSpan II User Manual 8091862 001 08 Appendix A Registers If the TYPE bit set to 0 an access of the PCI Configuration Data register from the QBus inter
60. 274 Mailbox 2 Register 0 70 MBOX3 Table 126 on page 275 Mailbox 3 Register 0 710 0 7 Reserved 0x800 Table 127 on page 276 MISC CTL Miscellaneous Control and Status Register 0x804 EEPROM CS Table 129 on page 279 EEPROM Control and Status Register 0x808 MISC CTL2 Table 130 on page 280 Miscellaneous Control 2 Register 0 810 PARB PCI Bus Arbiter Control Register Table 131 on page 283 0 814 0 Reserved OxF00 Table 133 on page 285 QBSIO CTL QBus Slave Image 0 Control Register OxF04 Table 138 on page 287 QBSIO AT QBus Slave Image 0 Address Translation Register OxF08 OxFOF Reserved OxF10 QBSII Table 140 on page 289 QBus Slave Image 1 Control Register OxF14 5 AT Table 145 on page 291 QBus Slave Image 1 Address Translation Register OxF18 OxF7F Reserved OxF80 QB ERRCS Table 147 on page 293 QBus Error Log Control and Status Register OxF84 QB AERR Table 148 on page 294 QBus Address Error Log Register OxF88 Table 149 page 295 QBus Data Error Log Register OxF8C OxFFF Reserved 200 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 68 ILO Memory Map Lower 4K 0x030 I20 OPIS 1 0 Outbound Post List Interrupt Status Register Table 150 on page 296 0x034 I20 OPIM 150 Outbound Post List Interrupt Mask Register Table 151 on page 297 0x040 INQ 150 Inbound Queue Regis
61. 4 The PCI Target Channel Table 18 Translation of PCI Bus Address to QBus Address BS in PBTIO_CTL or PCI Address Bits Translation Address Bits Block Size Translated Copied 0000 64 Kbytes 64 Kbytes AD3I ADI6 1 AD16 TASI TALG 1 TA16 4 4 3 Transaction Codes on the QBus The address supplied on the A 31 0 lines on the QBus is the result of the address translation described in the previous section QSpan II also allows the user flexibly to generate various encodings on the QSpan II s TC 3 0 lines The TC 3 0 lines can be connected to the FC 3 0 lines of the MC68360 bus AT 0 3 lines of the MPC860 bus and a subset of the TT 1 0 and TM 2 0 lines of the M68040 bus QSpan copies the values from the TC field of the PCI Target Image of the current transaction to the TC 3 0 lines of the QBus This gives the user additional control over the address information provided on the QBus 66 QSpan II User Manual 8091862 001 08 Chapter 4 The PCI Target Channel 4 4 4 PCI BIOS Memory Allocation The PCI Target Image registers used by the QSpan II to decode PCI accesses work differently depending on the EEPROM implementation and the use of the PCI Access Disabled PCI_DIS bit in MISC_CTL2 see Table 130 on page 280 There are three possible cases 1 Case 1 The PCI BSTx register is enabled by the EEPROM see Table 75 on page 210 and Table 77 on page 212 For PCI Target Image 0 this means tha
62. 43 Outbound Free List FIFO ENSEM IOF BP incremented by QBus CPU Read from Register Wi External PCI Write to Outbound Queue gt QBus CPU Host lt Read from Outbound Queue lt A Write to Register IOP incremented by QBus CPU Outbound Post_List A FIFO IOP BP incremented by the QSpan Il OP_FIFO A incremented by the QSpan II gt Inbound Post List FIFO IP_FIFO a See incremented by QBus CPU Read from Register a External PCI Write to Inbound Queue gt gt QBus CPU Host lt Read from Inbound Queue lt lt A Write to Register lt penne incremented by QBus CPU Inbound Free List A FIFO incremented by the QSpan 11 IF_FIFO QBus Low Memory Address 10 3 Outbound Messaging The Outbound Post List FIFO OP_FIFO contains MFAs for message frames sent to system memory from the QBus Host The Outbound Free List FIFO OF_FIFO contains MFAs for message frames that are free to be filled by the QBus Host The QBus Host gets an MFA from the Bottom of the Outbound Free List FIFO writes a message to system memory and then posts the MFA to the Top of the OP_FIFO QSpan generates a PCI interrupt if enabled when an MFA is posted The host accesses the oldest outbound MFA by reading the outbound queue The outbound queue is offset 0x044 from the at offset 0x010 QSpan II User Manual 1
63. 5 PA Sets the PCI bus address space to either Memory or I O space Typically only Memory Space accesses are implemented PREN Enables the QSpan II to perform a burst read on the PCI bus Set this bit if the QBus processor is often reading from consecutive PCI addresses E and or QBSII1 AT BS 3 0 Block Size of slave image affects number of address lines translated if address translation is enabled TA 31 16 This field allows for independent memory maps to be created for the PCI bus and QBus EN bit must be set to 1 PCI CS BM This bit must be set before the QSpan II will initiate any transaction on the PCI bus S QBSIO AT This bit enables address translation when set to 1 382 QSpan II User Manual 8091862 001 08 Appendix D Software Initialization D 3 Register Access from the PCI Bus QSpan II s PCI Configuration registers are accessible from the PCI Bus in PCI Configuration or Memory Space QSpan II device specific registers are only accessible in Memory Space QSpan II s PCI Configuration Registers are accessible without any software initialization requirements To access the QSpan II device specific registers in PCI Memory Space configure the bits listed in the following table Table 165 Register Access PCI_CS MS Set this bit for the QSpan II to be able to respond to PCI Memory space cycles This is a global bit the PAS bit of each specific image also needs to be set PCI_BSM Specifies the base addres
64. 7 0 field of the EEPROM register EEPROM Access QSpan II supports access to the EEPROM after the QSpan II has powered up without loading from the EEPROM To access the EEPROM using this method set the ACC bit in the MISC CTL2 register see Table 130 on page 280 If the EEPROM_ACC bit is set the EEPROM related registers are enabled and the QSpan II can read and write to the EEPROM using the EEPROM CS register or the Vital Product Data VPD registers Vital Product Data Support Vital Product Data VPD is a PCI 2 2 Specification feature supported by the QSpan II VPD contains information that defines items such as hardware software and microcode elements of a system VPD also provides a mechanism for storing information such as performance and failure data on a device VPD resides in a local storage device With the QSpan II VPD is supported through the serial EEPROM If an external EEPROM is not used the VPD feature is not enabled VPD will not be a part of the Capabilities List Since the lower bytes in the EEPROM contain data for setting up the QSpan II before software initialization the lower portion of the EEPROM first 32 bytes is not accessible through the VPD registers The upper 224 bytes of the 256 byte EEPROM are designated as read write through the VPD Valid VPD byte addresses are 0x0 gt OxDC assuming a 2 Kbit serial EEPROM is installed on the board 130 QSpan II User Manual 8091862 001 08
65. 82 Terminations driven by the PCI Target Module This section lists the terminations generated by the PCI Target Module and summarizes the conditions under which the various terminations are issued Under most conditions the target is able to source or sink the data requested by the master until the master terminates the transaction But when the target is unable to complete the request it can use the STOP signal to initiate termination of the transaction QSpan PCI Target Module generates the following PCI terminations e Target Disconnect e Target Retry e Target Abort Target Disconnect During a Target Disconnect a termination is requested by the target because it is unable to respond within the latency requirements of the PCI 2 2 Specification or it requires a new address phase This termination is signaled when the target holds TRDY and STOP asserted Target Disconnect means that the transaction is terminated after data is transferred Target Disconnects can be issued by the QSpan II under the following conditions e A PCI master attempts to burst to a Target Image whose transfers are set to I O space In this case a target disconnect is issued after the first data phase e A PCI master attempts to burst to a Target Image with posted writes disabled and the current data phase processed as a delayed write has completed on the QBus see Acceptance of Burst Writes by the PCI Target Module on page 74 e A P
66. 9 7 1 9 7 2 Chapter 9 The EEPROM Channel VPD access to the EEPROM is similar to the EEPROM access implemented in QSpan II through the EEPROM_CS register Since they both access the same resource only one of these mechanisms can be used at a time to access the EEPROM Reading VPD Data QSpan II implements 8 bits of address for accessing the EEPROM maximum of 256 bytes The VPD address must be 32 bit aligned QSpan II will add 0x20 to the address to generate an EEPROM address in the upper 224 bytes of the EEPROM A single read access reads four consecutive bytes starting from the VPD address During a read access the VPD address and the VPD flag bit are written see Table 87 on page 222 The VPD flag bit must be set to 0 to indicate a VPD read access QSpan II sets the VPD flag bit to 1 when it has completed reading the four bytes from the EEPROM The VPD flag bit must be polled to identify when the read is complete Byte 0 bits 7 0 of the VPD data register contains the data referenced by the VPD address bytes 1 3 contain the successive bytes If PCI VPD register or EEPROM CS register is written to prior to the flag bit being set to one the results of the original read operation are unpredictable Writing VPD Data A write can occur to the upper 224 bytes of the EEPROM Similar to the read the QSpan II adds 0x20 to the VPD address to get the EEPROM address A single write operation writes four consecutive bytes starting f
67. AS A 31 0 t251 1252 D 31 0 K 1254 9 1259d 9 DACK DONE_ During IDMA fast termination cycles the maximum MC68360 QCLK frequency is 30 MHz Figure 37 MC68360 IDMA Write Single Address Fast Termination Ons 25ns 50ns 75ns 100ns 125ns gis 4 1201 gt QCLK _ 2530 gt 4 12590 CSPCI 1259 k 1253a AS d 31 0 t259c t25 D 31 0 2 21259 k t254 DACK_ Ld DONE QSpan II User Manual 327 8091862 001 08 Appendix B Timing Figure 38 MC68360 IDMA Read Dual Address Standard Termination Ons 50ns 100ns 150ns 200ns 250ns 3p KA teda p TCI p JE fpa 31201 5 QCLK jx 54 E e wk to X IEEE CR gt 253b 1259 CSPCI k t253a lt gt 11259a AS A A 31 0 _ 251 1252 0131 0 T 212544 4112594 _ DONE_ 212 _ 210 1236 DSACKO m 212a t210c 9236c DSACKI QSpan II does not issue retries or bus errors during dual address IDMA cycles 328 QSpan II User Manual 8091862 001 08 Appendix B Timing Figure 39 MC68360 IDMA Write Dual Address Standard Termination
68. Block Size PCI Address Space Translation Address and Enable Address Translation fields is discussed in Address Translation on page 42 and Address Phase on the PCI Bus on page 45 The QBus Slave Image Control registers specify how writes are processed see Table 133 on page 285 and Table 140 on page 289 If the PWEN bit is 1 the QSpan II will perform posted writes when the specific QBus Slave Image is accessed with a single write Otherwise writes are handled as single delayed transactions If the PREN bit is 1 the QSpan II will perform a burst read on the PCI bus when the MPC860 or MC68360 performs a single 32 bit read on the QBus Otherwise the QSpan II will handle this as a single delayed read transaction QBus Slave Image 0 can also be programmed from an external EEPROM for information see Mapping of EEPROM Bits to QSpan II Registers on page 126 40 QSpan II User Manual 8091862 001 08 Chapter 3 The QBus Slave Channel 3 4 1 1 MPC860 Cycles QSpan II behaves as an MPC860 slave in response to the assertion of the TS_ signal when it is powered up as an MPC860 slave see QBus Slave Module on page 37 When the QBus Slave Module receives TS_ it responds with DSACK1_ TA_ BERR TEA_ or HALT_ TRETRY_ QSpan acknowledges the transaction if either CSREG_ or CSPCI is sampled active in conjunction with TS_ QSpan II samples the address bus and control signals on the same rising edge of QCLK in which it samples
69. Configuration Type 0 cycle on the PCI bus If the Device Number is programmed it causes one of the upper address lines AD 31 16 to be asserted during the address phase of the Configuration Type 0 cycle the other lines are negated Table 40 shows which PCI address line is asserted as a function of the NUM 3 0 field The remaining address lines during the address phase of the Configuration cycle are controlled by the Function Number and Register Number fields of the CON ADD register e AD 15 11 00000 e AD 10 8 FUNC NUM 2 0 e AD 7 2 NUM 5 0 e AD 1 0 00 QSpan II User Manual 111 8091862 001 08 Chapter 7 The Register Channel 7 4 3 1 7 4 4 112 Table 40 PCI AD 31 16 lines asserted as a function of DEV NUM field Data Phase of PCI Configuration Cycles PCI Configuration accesses from the QBus proceed as delayed transactions This is true for Configuration reads as well as writes When the CON DATA register is accessed the QBus master is retried QSpan II then initiates a Configuration cycle on the PCI bus The PCI byte enable driver is dependent on the attributes of the QBus cycle for example QBus address and SIZ signals during the Configuration cycle Until the Configuration cycle completes on the PCI bus any further Configuration cycle attempt is retried In the case of a read read to CON DATA the data from the PCI bus 15 stored in the DATA register After the Configur
70. Description 40Cx M Units Note QCLK Frequency T N t400 t401 Period t402 Clock Pulse Width Low Clock Pulse Width High 3 t404 Clock Rise Time t 3 t405 Clock Fall Time ty 3 1406 TA tristated from QCLK negative edge 11 4 14093 TEA_ tristated from QCLK negative edge t409b t410a A asserted from QCLK positive edge t410b BB_ asserted from QCLK positive edge t410c R W_ asserted from QCLK positive edge t410d SIZ asserted from QCLK positive edge TA_ asserted from QCLK positive edge t410e t410f TC asserted from QCLK positive edge TEA_ asserted from QCLK positive edge BURST_ TIP_ asserted from QCLK positive edge 3 1 1 1 1 1 1 1 t410h 1 1 t410i TS_ asserted from QCLK positive edge 8 3 BR_ asserted from QCLK positive edge 2 412a BB tristated from QCLK negative edge t412b TS tristated from QCLK negative edge t413a BB_ setup to QCLK positive edge 2 1 1 3 5 t413b BG_ setup to QCLK positive edge t413 D setup to QCLK positive edge 7 IMSEL setup to QCLK positive edge t413e TA_ setup to QCLK positive edge 2 0 epu GEN 5 5 5 5 5 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 TEA_ setup to QCLK positive edge ON 4136 BURST_ TIP_ setup to QCLK positive edge
71. Description Continued Appendix A Registers Reset Name Type Reset By State Function i NNNM R W TC 3 0 G RST TC EN PORT16 QSpan User Manual 8091862 001 08 Programmable I FIFO Watermark for IDMA transfers 0000 use the value programmed into the CLINE 1 0 field of the PCI_MISCO register x when 16x bytes have been queued in the I FIFO the IDMA channel will request the PCI bus Watermark can be set to a maximum of 240 bytes Programmable TC Encoding with MPC860 IDMA Program to the value expected on the QSpan II s TC 3 0 lines during an IDMA transfer The intent of this field is to allow users to use the TC lines to encode an IDMA transaction for the QSpan II add a qualifier for SDACK assertion TC Encoding Enable IDMA transfers only 0 QSpan II does not decode TC 3 0 for IDMA accesses 1 QSpan II decodes TC 3 0 for IDMA accesses DMA chaining 0 Direct Mode DMA 1 Linked List Mode DMA DMA 0 QSpan does an IDMA transfer 1 QSpan II does a DMA transfer Direction 0 Transfer from PCI Bus to QBus 1 Transfer from QBus to PCI bus IDMA Mode 0 IDMA transfer is MC68360 1 IDMA transfer is MPC860 Termination Mode 0 QSpan uses normal termination during MC68360 dual address IDMA transfers 1 QSpan II uses fast termination during MC68360 dual address IDMA transfers Slave Termination Mode 0 External slave uses normal termination mode during MC68360 single address IDMA
72. EEPROM However the EEPROM loading cannot clear the PCI_DIS bit Therefore if PCI_DIS is enabled from the EEPROM loading then the Host must 2 configure QSpan 1 registers before QSpan allows register access from the PCI bus QSpan II supports reads from and writes to the EEPROM 256 bytes of data can be accessed with the EEPROM QSpan II normally loads the first 12 bytes of data for its own programming QSpan II can load the next 11 bytes from the EEPROM if the last three bits of the 12th byte are 010 124 QSpan II User Manual 8091862 001 08 9 2 9 3 Chapter 9 The EEPROM Channel EEPROM Configuration and Plug and Play Compatibility There are two ways to configure the EEPROM to allow the QSpan II to boot as a PCI Plug and Play compatible device e EEPROM can be configured before it is placed on the board e EEPROM can be configured after it is installed In this case the first time the QSpan II based board boots it will not be PCI Plug and Play compatible You will need to program the EEPROM from either the QBus or the PCI bus see Programming the EEPROM from the QBus or PCI Bus on page 129 for details The following sections discuss the implementation of the EEPROM EEPROM FC Protocol QSpan II supports the 2 wire PC protocol using a clock output SCL and a I directional signal SDA If the SDA or ENID pin is asserted as 1 during a PCI bus reset for example RST active then
73. FS de Ge CE VR ea SURE ea eee 192 Appendix Registers x E i ERR UO ORAE 195 Overview ci icsaec on ie ee head bue eed ber under hee bel der eee den 195 2 Terminology oso eere trees 196 A2 4 ead dr o bte d dete 197 no ME CaocR ERR IE 202 Appendix B RR EY RR RR ERR ORA EAR ERA RR Rc 301 Bil OvetvieWa s eb UR Cb AUR UR ede a p EUR V RE OE RO 301 B 2 Timing Parameters sce eem metto duc eot RR US e e ote ce der Cena 302 Wait State Insertion QBus Slave Module 316 B4 Timing Diagrams roba Ke teat es 317 4 1 QBus Interface 68360 317 B 4 2 QBus Master Cycles 68360 317 B 4 2 1 QBus Slave Cycles MC68360 320 4 2 2 QBus IDMA Cycles 8360 324 4 3 QBus Interface 860 332 B 4 3 1 QBus Master Cycles 860 332 4 3 2 QBus Slave Cycle 60 337 B 4 3 3 QBus IDMA Cycles MPC860 343 4 4 Q
74. Figure 77 MPC860 QSpan II Clocking Scheme Example XTAL LKOUT Buffer MPC860 QSpan II User Manual 8091862 001 08 Appendix C Typical Applications This issue can be eliminated by having the MPC860 execute a delay loop from its instruction cache during this time period This will prevent the MPC860 from asserting the cycle on the external bus that is TS_ will not be asserted An example of how this code could be implemented is in Figure 78 Figure 78 Example Code for Executing an MPC860 Delay Loop R4 Contains IMMR value bl icache_unlock_all ICache Unlock All bl icache_invalidate_all ICache Invalidate 11 bl icache_enable ICache Enable prefetch wait_delay subroutine into instruction cache li XL set delay counter for wait delay subroutine bl wait delay li r5 0xA0 multiply factor from 4MHZ b aligned align 4 align address to 16 bytes boundary aligned sth r5 PLPRCR r4 set the PLL register isync delay allows for QSpan II to receive a stable QCLK before external bus cycles begin the actual delay value required is dependent on the PLL clock buffer device s locking time li rl Ox7FFF set delay counter for wait delay subroutine bl wait delay Simple delay routine R1 delay counter input parameter wait delay execute required delay with 1 parameter blr C 2 1 2 Resets There are three reset scenarios depending on the use of the QSpan II in your application PCI
75. IDMA DMA Channel There are two situations to be aware of 1 The PBTIx_CTL and DMA_CS registers contain an INVEND bit which causes the QSpan II to use the logical inversion of the 2 The QB_BOC bit does not affect the presentation of data on the QBus Interface in the case where the Register Channel is accessed QSpan II User Manual 277 8091862 001 08 Appendix A Registers With the second situation the QSpan II does not perform byte swapping of data in the Register Channel regardless of whether the QBus is configured as Big or Little endian this applies to all QBus register accesses including the CON_DATA and IACK registers Bit 31 in any QSpan II register is presented on bit 31 of the QBus and bit 31 of the PCI bus regardless of the QB_BOC bit The MSTSLV field indicates the Master and Slave modes of the QSpan II The first bit of this field is determined by the value of BDIP_ at reset The second bit is determined by the value of SIZ 1 at reset The MSTSLV field is described in Table 127 Table 128 Master Slave Mode MSTSLV field po MC68360 MC68360 and M68040 MC68360 MC68360 and MPC860 M68040 MC68360 and M68040 MPC860 MC68360 and MPC860 278 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 129 EEPROM Control and Status Register Register Name EEPROM_CS Register Offset 804 31 24 ADDR 7 0 23 16 DATA 7 0 15 08 Reserved 07 00 READ Reserved EEPROM CS Descri
76. II is the QBus master and is tristated at all other times The Address Strobe is driven low after a falling edge of the QCLK The Address Strobe qualifies the following signals as valid when it is asserted A 31 0 TC 3 0 SIZ 1 0 and R W_ QSpan II guarantees a minimum set up time for the qualified signals before AS is asserted all qualified signals are driven from the rising edge of QCLK preceding the assertion of AS QSpan rescinds AS prior to tristate As an input AS_ is sampled on the falling edge of the QCLK AS_ must meet a minimum set up and hold time around the falling edge of the clock for correct operation QSpan II recognizes a transaction as intended for it and acknowledges it accordingly only if one of CSREG_ or CSPCI is sampled low in conjunction with AS_ QSpan II does not require that the input signals qualified by the AS be valid when it is asserted BB BGACK Rescinding Tristate bidirectional Bus Busy indicates ownership of the QBus It along with BR_ and BG_ provides the three wire handshake for QBus arbitration BGACK is intended to connect to the BGACK_ bus As an output the QSpan II asserts BB BGACK from the falling edge of QCLK while master QSpan II rescinds BB BGACK prior to tristate As an input the QSpan II double samples BGACK on the falling edge of QCLK when it is master QSpan II can also be programmed to use a synchronous mode for QBus arbitration BGACK _ Rescinding Tristate bidire
77. II s Interrupt Control Registers see Table 120 on page 265 See Chapter 5 The IDMA Channel on page 85 for more information QSpan II User Manual 8091862 001 08 Appendix A Registers Table 110 IDMA DMA PCI Address Register Register Name IDMA DMA_PADD Register Offset 404 31 24 ADDR 23 16 ADDR 15 08 ADDR IDMA DMA_PADD Description Reset Name Type Reset By State Function ADDR 31 2 RW 0 PCI Bus Address for IDMA DMA transfers PCI Bus Address for IDMA DMA transfers Bus Address for IDMA DMA transfers The ADDR field must be programmed with the absolute PCI address for an IDMA DMA transaction This address is aligned to a 4 byte boundary An IDMA DMA transfer wraps around at the A24 boundary If an IDMA DMA transfer is required to cross an A24 boundary it must be programmed as two separate transactions This field is incremented by the QSpan II during a transfer Progress of the IDMA DMA transfer on the PCI bus can be monitored by reading the IDMA DMA register see Table 111 on page 252 This register can be programmed from either bus or by the DMA controller when it loads a command packet from QBus or PCI memory QSpan II User Manual 251 8091862 001 08 Appendix A Registers Table 111 IDMA DMA Transfer Count Register Register Name IDMA DMA CNT Register Offset 408 m IDMA DMA_CNT Description Reset Name Type Reset By State Function CNT 23 2
78. Ifthe PCI DIS signal is sampled high on the negation of a reset event then the QSpan II s PCI interface is disabled QSpan II will retry any attempted PCI target accesses until the PCI DIS status bit in the MISC CTL2 register is cleared see Table 130 on page 280 There is an internal pull down resistor to maintain backward compatibility Reset options are described in Chapter 14 Reset Options on page 155 Unused Inputs Requiring Pull Ups The AS DSACKO and DONE signals are unused inputs when the QSpan II is interfaced with an MPC860 and therefore must be pulled high No Connects The DS output from the QSpan II should be left as a no connect when the QSpan II is interfaced with an MPC860 The BM EN FIFO RDY can be left as a no connect as there is an internal weak pull down resistor In this case in order for the QSpan II to become a PCI bus master a write to the PCI register is required JTAG Signals QSpan II supports JTAG QSpan II s JTAG signals should be connected to the JTAG controller or to the JTAG signals of another device if devices are to be chained together If JTAG will not be supported then the JTAG signals can be left open as the inputs have internal pull up resistors Bused Signals This manual adopts the convention that the most significant bit address data size and transaction codes is always the largest number When interfacing the MPC860 to the QSpan II designers must ensure that they connect the signal
79. Implicit QBus base address QSpan II User Manual 109 8091862 001 08 Chapter 7 The Register Channel 7 4 1 7 4 2 110 Examples of QBus Register Accesses The following table illustrates Big Endian access to bits 15 08 of the PCI CLASS register This table shows the address and size signals required to access this byte This table also shows how the data is presented to the QBus master Table 38 Big Endian QBus Access to bits 15 08 of the PCI CLASS register a This is a subset of A 11 0 The following table illustrates Little Endian access to bits 15 08 of the PCI CLASS register There is no real difference between Big Endian and Little Endian access to the QSpan 1 register The only difference between Tables 38 and 39 is the name not the location of the byte along the data lines Table 39 Little Endian QBus Access to bits 15 08 of the PCI CLASS register a This is a subset of A 11 0 PCI Configuration Cycles Generated from the QBus PCI Configuration cycles of Type 0 or Type 1 can be initiated from the QBus To initiate Configuration cycles complete the following 1 Write the Target PCI address in the Configuration Address Register see Table 115 on page 258 This step determines how the address of the Configuration cycle is generated on the PCI bus 2 Access the Configuration Data register see Table 117 on page 260 A read access generates a Configuration read on the PCI bus a write access
80. Manual 8091862 001 08 331 Appendix B Timing B 4 3 QBus Interface MPC860 B 4 3 1 QBus Master Cycles MPC860 Figure 42 QBus Arbitration MPC860 Ons 250ns 500ns 01 _ _ _ S amem 1 1311 BR gt 313 315d BG_ 13100 t312a 1313a gt 13156 t338b BB This figure depicts timing in the case where the QSpan II requests ownership of the QBus while another QBus master currently owns the bus BB BGACK asserted by the other master QSpan II obtains ownership of the bus after the other master negates BB BGACK 332 QSpan II User Manual 8091862 001 08 Appendix B Timing Figure 43 Single Read QSpan II as MPC860 Master Ons 100ns 200ns 300ns 1301 gt QCLK t311 t311 BR_ A 13 i gt 1315 BG_ 1312 t310b gt t336b BB_ 7 gt t310a gt 336 A 31 0 t310c t336c BURST_ r E r t310e gt 1336e SIZ 1 0 gt 13100 gt 3360 TC 3 0 13109 t336d R W_ X t312b 61310 11336 TS_ 7 gt det315h gt 181 D 31 0 gt I 13151 12130 TA 4 TEA TRETRY a a Normal TA TEA t3150 gt 3131 TRETRY_ b Retry t315n t313h lt
81. Outbound IFE_EN IFE_DIR IFE_S Free_List Empty OFE_EN OFE_DIR OFE_S Status Inbound Post_List IPF_EN IPF_DIR IPF_S Full Status Outbound OFF_EN OFF_DIR OFF_S Free_List Full Status a See also IDMA Errors Resets and Interrupts on page 91 b Any of the following bits in PCI CS D PE S_SERR R MA R_TA or S TA QSpan II User Manual 119 8091862 001 08 Chapter 8 The Interrupt Channel Four software interrupt bits are provided Software Interrupt 0 through 3 Setting a software interrupt bit SI3 SD SII or SIO triggers the interrupt status see the following table and causes the QSpan II to generate an interrupt on the QBus QINT or PCI bus INT depending on the relevant mapping bit There is no enable bit for software interrupts The interrupt line will be driven until the status bit is cleared To clear the status bit write a 1 Table 43 Software Interrupt Mapping Status and Source bits Mapping Bits Interrupt Status Bits INT CTL see INT DIR see Table 121 INT STAT Table 120 on page 265 on page 268 see Table 119 on page 262 INT CTL2 see Source Table 122 on page 271 a Write 1 to clear the interrupt Interrupts in one channel do not affect processing in the other channel 8 3 1 Interrupt Generation due to PCI Configuration Register Status Bits QSpan II can generate an interrupt QINT INT when any of the status bits in the PCI CS register is set The direction of the inte
82. PCI target When the IACK cycle completes on the PCI bus the IACK VEC 31 0 field is returned as read data when the QBus master returns after the retry Writing to this register from the QBus or PCI bus has no effect Reads from the PCI bus return all zeros The QSpan II does not perform byte swapping of data in the Register Channel regardless of whether the QBus is configured as big or little endian Bit 31 in the register is bit 31 on the QBus regardless of bit in the MISC register see Table 127 on page 276 Therefore software on the QBus may need to swap the data when performing IACK cycles QSpan II generates a bus error upon register access to the IACK_GEN register if the bus master BM bit in the PCI CS register is not set QSpan II User Manual 261 8091862 001 08 Appendix A Registers Table 119 Interrupt Status Register Register Name INT_STAT Register Offset 600 INT_STAT Description Reset Name Type Reset By State Function PEL_IS R Write 1 G_RST PCI Bus Error Log Interrupt Status to Clear QEL_IS R Write 1 G_RST QBus Error Log Interrupt Status to Clear MDPED_IS R Write 1 G_RST PCI Master Data Parity Detected Interrupt Status to Clear PCSR_IS R Write 1 G_RST PCI_CS Register Interrupt Status to Clear IQE_IS R Write 1 G_RST IDMA DMA QBus Error Interrupt Status to Clear IPE_IS G_RST IDMA DMA PCI Error Interrupt Status to Clear IRST_IS R Write 1 G_RST IDMA DMA Reset Interrupt S
83. QB_BOC setting Programmable I FIFO Watermark 0000 use the value programmed into the CLINE 1 0 field of the PCI MISCO register X when 16x bytes have been queued in the I FIFO the DMA channel will request the PCI bus Watermark can be set to a maximum of 128 bytes 1000 others Reserved QSpan II User Manual 8091862 001 08 Appendix A Registers CS Description Continued Reset Name Type Reset By State Function i DMA QBus Off Counter 000b 0 001b 64 010b 128 011b 256 100b 512 101b 1024 others Reserved The DMA controller will not request the QBus until the programmed number of QCLKs expires QBus Burst Four Dataphases 0 QSpan II will generate partial QBus burst 2 or 3 dataphases 1 QSpan II will only generate QBus burst with 4 dataphases BRSTEN QBus Burst Enable 0 Disable 1 Enable The generation of burst cycles is supported when the QSpan II is powered up in MPC860 Master mode The DMA QBus OFF counter is activated when a DMA transfer crosses a 256 byte address boundary on the QBus For example the counter is active after each 256 byte transfer on the QBus when MDBS 0 otherwise 64 byte boundary is used R W R W R W R W Maximum DMA Burst Size on QBus 0 256 Bytes 1 64 Bytes R W Command Packet Location 0 PCI Bus 1 QBus DMA Stop 0 Resume DMA transfer 1 Stop DMA transfer DMA Stop Status 0 DMA transfer is not st
84. QBus Slave Channel The No Transaction Ordering NOTO bit in MISC CTL2 register is used for this purpose see MISC_CTL2 Description on page 280 When this bit is set a read in one channel is unaffected by posted writes in the other channel This feature improves system performance especially when using the DMA and where strict transaction ordering is not required QBus Arbitration and Sampling The QBus Master Module requests the QBus when there is a read request or when there is a sufficient number of entries in the Px FIFO see Acceptance of Burst Writes by the PCI Target Module on page 74 MC68360 Bus Arbitration When the QSpan II requires control of the MC68360 bus it requests the bus by asserting Bus Request BR_ When the QSpan II samples Bus Grant BG_ asserted and Bus Grant Acknowledge negated the QSpan II asserts BB BGACK and negates BR The QBus MC68360 Master Module s default arbitration mode is asynchronous it double samples the BG_ and BB BGACK inputs using the falling and rising edge of QCLK The default mode of operation can be modified with the QSpan II in order to save one clock cycle during arbitration To enable synchronous arbitration set the Synchronous Bus Grant S BG bit and the Synchronous Bus Grant Acknowledge 5 BB bit to 1 in the MISC CTL register see Table 127 on page 276 The Arbitration Synchronous Timing Mode ASTM bit in the MC68360 must be set for asynchron
85. QSpan II s QCLK input and the M68040 s BCLK input should be clocked from the same clock source The AC timing waveforms for the QSpan II are based on this assumption C 3 1 2 Resets There are three reset scenarios depending on the use of the QSpan II in your application PCI adapter card bridge PCI Host bridge or CompactPCI adapter card supporting Hot Swap For a PCI Adapter card application use the following reset configuration connect the QSpan II s reset output RESETO to the external reset logic to the reset input RSTI on the M68040 This enables the QSpan II to reset the M68040 processor when PCI RST is asserted or when the software reset bit is asserted SW bit in the MISC register on Table 127 on page 276 QSpan II s reset input RESETI is normally unused and should be pulled high through a resistor For a PCI Host bridge application use the following reset configuration the QSpan II s PCI RST global reset for the QSpan II input is connected to the reset output RSTO on the M68040 QSpan II s reset output RESETO can be connected to the PCI RST inputs of the other PCI devices the QSpan II s RST input is not connected to the PCI bus RST signal Therefore at power up the M68040 s power on reset circuitry will assert RSTO which fully resets the QSpan II device QSpan II will assert RESETO to reset the agents on the PCI bus when RST is active This reset example also allows the M68040 processor to
86. QSpan II s registers to negate RESETO_ QSpan II s QCLK input must be identical to the QBus processor s clock source if transactions are occurring on the QBus Many applications use an external low skew PLL clock buffer to generate the clock outputs for the board for example QCLK input for QSpan II If the buffer s clock 5 outputs are not locked to the clock input frequency then transactions cannot occur on the QBus QSpan II must not detect AS_ or TS_ being asserted 14 2 Configuration Options at Reset The following QSpan II configuration options can be determined at Reset e whether the QSpan is enabled as a PCI bus master e the master and slave modes of the QBus which determines the type of cycles that the QSpan II can generate as a master and accept as a slave e whether the QSpan II loads registers from an EEPROM at reset see EEPROM Loading on page 158 and PCI Register Access Option on page 158 e the test mode see Test Mode Pins on page 159 e PCI access to QSpan II registers e PCI bus arbiter functionality 14 2 1 PCI Bus Master Reset Option If BM_EN FIFO_RDY_ is sampled as high while reset is asserted the QSpan II will set the Bus Master BM bit in the PCI CS register see Table 70 on page 203 This enables the QSpan II as a PCI bus master If this pin is not connected an internal pull down causes the QSpan II to power up with the BM bit set to 0 QSpan II User Manual 157 8091862 001 08 Chapter 1
87. R W G_RST IDMA DMA Transfer Count Number of Bytes to Transfer Max 2224 bytes a The IDMA DMA_CNT should not be programmed to be less than the specified value in the watermark field IWM CNT 23 2 indicates the number of bytes left to transfer in an IDMA DMA transaction see Table 111 on page 252 The QSpan II decreases this transfer counter by four with every 32 bit transfer on the PCI bus The IDMA DMA Channel on the PCI Interface transfers 32 bit data The amount of data that can be transferred within an IDMA DMA transaction is 16 Mbytes for example 222 39 bit transfers The CNT 23 2 field must be programmed with a minimum value of 0x000010 corresponding to 16 bytes otherwise the IDMA DMA channel will not start when the GO bit is set The CNT field must initially be programmed with the same value as the processor s IDMA s Byte Count register when IDMA transfers are initiated This register can be programmed from either bus or is programmed by the DMA controller when it loads a command packet from QBus or PCI memory The command packet only contains CNT 19 2 making the maximum Linked List transfer size 1 Mbyte 252 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 112 DMA QBus Address Register Register Name DMA_QADD Register Offset 40C 31 24 ADDR Pow CdS DMA_QADD Description Reset Name Type Reset By State Function Q_ADDRI31 2 ADDR 31 2 QADDRBI2 RW G RST 0 Q
88. The following signals are sampled on the rising edge of both RST and RESETI and the falling edge of HS HEALTHY to determine the QSpan II s mode of operation e The BDIP signal must be pulled low at reset to enable the QSpan II to perform as an MC68360 master QSpan II responds to MC68360 style slave cycles independent of the state of the SIZ 1 signal at reset see Chapter 14 Reset Options on page 155 SDA and ENID signals should be pulled high if the EEPROM is used The SDA signal should be pulled low if the serial EEPROM is not used in this design The ENID signal can be left open if the serial EEPROM is not used as there is an internal weak pull down resistor e TMODE 1 0 signals can be left open as there are internal pull down resistors on these pins within the QSpan II If an in circuit tester is used during the board manufacturing process then these two signals should be brought out as test points This allows the in circuit tester to place the QSpan in a tri state NAND TREE test mode e If the BM EN FIFO RDY signal is sampled high while RST is asserted the QSpan II sets the Bus Master BM bit in the PCI CS register see Table 70 on page 203 This enables the QSpan II as a PCI bus master This pin can be left as a no connect as there is an internal weak pull down resistor e Ifthe PCI ARB EN signal is sampled high on the negation of a reset event then the PCI bus arbiter within the QSpan is enabled
89. Tristate bidirectional See BURST TIP Tristate bidirectional Transfer Start asserted for one clock period to indicate the start of a transfer QSpan II User Manual 173 8091862 001 08 Chapter 16 Signals The following table describes the signal encoding for M68040 SIZ 1 0 signals Byte lane enabling is combined with A 1 0 as described in the Motorola M68040 User 5 Manual Table 52 M68040 Encoding for the SIZ 1 0 Signal QSpan IT as QSpan as SIZ 1 SIZ 0 M68040 Master M68040 Slave L9 ome we 16 6 PCI Bus Signals AD 31 0 Bidirectional t s PCI Address Data Bus address and data are multiplexed over these pins providing a 32 bit address data bus A bus transaction consists of an address phases followed by one or more data phases C BE 3 0 Bidirectional t s PCI Bus Command and Byte Enable Lines command information during address phase and byte line enables during data phase DEVSEL Bidirectional s t s PCI Device Select driven by the QSpan II when it is accessed as PCI slave Sampled by the QSpan II when it is PCI master External Grant used by the QSpan II to indicate to an external device that it has been granted access to the PCI bus this is an output EXT_REQ 6 1 Bidirectional External Request used by an external device to indicate to the QSpan II PCI bus arbiter that it wants ownership of the PCI bus The QSpan drives the unused EXT_REQ 6 1 pins high when an external ar
90. W G RST Inbound Post List Top Pointer This pointer gives the address offset for the Inbound Post List Top Pointer This register is initialized by the QBus Host but is maintained by QSpan II and is incremented by four modulo boundary of FIFO SIZE 242 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 104 Inbound Post List Bottom Pointer Register Register Name IIP BP Register Offset 210 Function QIBA Reserved IIP BP Description Reset Name Type Reset By State Function QIBA 31 20 G_RST QBus LO Base Address specified in DO CS IP 19 2 R W G RST Inbound Post List Bottom Pointer This pointer gives the address offset for the Inbound Post List Bottom Pointer This register is initialized and maintained by the QBus Host QSpan II User Manual 243 8091862 001 08 Appendix A Registers Table 105 Outbound Free List Top Pointer Register Register Name IOF_TP Register Offset 214 Function QIBA Reserved IOF_TP Description Reset Name Type Reset By State Function QIBA 31 20 G_RST QBus LO Base Address specified in DO CS OF TP 19 2 R W G RST Outbound Free List Top Pointer This pointer gives the address offset for the Outbound Free List Top Pointer This register is initialized by the QBus Host but is maintained by the QSpan II and is incremented by four modulo boundary of FIFO SIZE 244 QSpan II User Manual 8091862
91. access defaults to PCI bus 1 Register Access port is parked at the last bus to access the register block QBUS PAR G RST M QBus Parity Encoding R W R W R W R W R W R W 0 Even Parity 1 Odd Parity QSpan II User Manual 281 8091862 001 08 Appendix A Registers MISC_CTL2 Description Continued Reset Name Type Reset By State Function EEPROM _ R W G_RST EEPROM Access after Power up ACC R W 0 EEPROM access is disabled if powered up without EEPROM SDA and ENID low at power up 1 EEPROM access is enabled if powered up without EEPROM Power State Change 3 to DO causes QBus reset 0 Power State Change from D3 to DO does not cause a QBus reset 1 Power State Change from D3 to DO initiated by the Host causes an internal QSpan II reset and RESETO_ to be asserted If an EEPROM is only used for storing Vital Product Data VPD access to EEPROM can be enabled after power up SDA and ENID low during Reset by setting the EEPROM_ACC bit QINT assertion in D34 Power State generates PME 0 QINT assertion does not generate PME 1 QINT assertion in D3 Power State can generate if enabled by PME SP in PCI PMC register NOTO R W G_RST No Transaction Ordering 0 Enable Transaction Ordering between the PCI Target Channel and QBus Slave Channel 1 Disable Transaction Ordering between the PCI Target Channel and QBus Slave Channel To maximize the perform
92. adapter card bridge PCI Host bridge or CompactPCI adapter card supporting Hot Swap For a PCI adapter card application use the following reset configuration connect the QSpan II s reset output RESETO_ to the hard reset input RESETH_ on the MPC860 This enables the QSpan II to reset the MPC860 when PCI RST is asserted or when the software reset bit is asserted SW_RST bit in the MISC_CTL register on Table 127 on page 276 QSpan II s reset input RESETI is typically unused and should be pulled high through a resistor HS_HEALTHY_ should be left open as it has an internal pull down resistor QSpan II User Manual 369 8091862_MA001_08 Appendix C Typical Applications C 2 1 3 C 2 1 4 370 For a PCI Host bridge application use the following reset configuration the QSpan II s PCI RST global reset for the QSpan II input is connected to the hardware reset RESETH_ on MPC860 II s reset output RESETO can be connected to the PCI RST inputs of the other PCI devices the QSpan II s RST input is not connected to the PCI bus RST signal Therefore at power up the MPC860 s power on reset circuitry will assert RESETH_ which fully resets the QSpan II QSpan II will in turn assert RESETO to reset the agents on the PCI bus when RST is active This reset example also allows the MPC860 processor to reset all of the PCI agents under software control The MPC860 can write to the software reset bit in the QSpan IPs MI
93. bidirectional QBus Interrupt as an output this open drain signal is asserted by the QSpan II when an interrupt event occurs As an input this signal can be mapped to the PCI INT output QBus Reset Input resets the QSpan from the QBus side of the QSpan II RESETI does not reset PCI configuration and status registers RESETO Open drain output QBus Reset Output asserted whenever the QSpan II s PCI RST input is asserted or the internal software reset bit is set Tristate bidirectional Read Write indicates the direction of the data transfer on the Data bus High indicates a read transaction low indicates a write It has the same timing as the Address bus As a master the QSpan II drives R W and tristates it otherwise As a slave the R W pin is an input SIZ 1 0 Tristate bidirectional Size indicates the number of bytes to be transferred during a bus cycle The value of the Size bits along with the lower two address bits and the port width define the byte lanes that are active Table 51 on page 171 shows the encoding for the Size bits Tristate bidirectional Transaction Code provides additional information about a bus cycle when the QSpan is a QBus master Driven by the QSpan II when it is a QBus master and tristated otherwise As slave the QSpan II samples TC 3 0 on the first falling edge of the QCLK after AS_ is asserted TC 3 0 can optionally be used with DACK SDACK to decode an IDMA opera
94. bit Last Command Packet in Linked List 31 20 0 IDMA DMA_PADD Register DMA_QADD Register DMA_CS Register IDMA DMA_CNT Register DMA_CPP Register N c N 1 for last command packet The maximum data transfer size for a Linked List DMA is 1 Mbyte because only CNT 19 2 bits are loaded from the command packet QSpan II User Manual 101 8091862_MA001_08 Chapter 6 The DMA Channel 6 4 1 102 Initiating a Linked List Mode DMA Operation To initiate a Linked List Mode DMA the command packets described in the previous section must be set up in QBus memory or PCI bus memory The final command packet must have the NULL bit set to 1 The following fields in the DMA_CS register see Table 113 on page 254 must be programmed to the appropriate values e Q_OFF e BURST 4 e BRSTEN CP LOC e MDBS e TC e DSIZE e INVEND The DMA CPP must be programmed to point to the first command packet The following fields in the IDMA DMA CS register see Table 109 on page 248 must be programmed to the appropriate values CMD e DMA e CHAIN To enable an interrupt upon the completion of the Linked List DMA or due to PCI bus or QBus errors the appropriate bits must be set in the INT CTL and INT DIR registers Once all relevant data is programmed the GO bit in the IDMA DMA CS register must be set to 1 to initiate the Linked List DMA transfer Any status bit IRST DONE
95. bit is set when the Inbound Post_List is full OFF_S G_RST Outbound Free_List Full Status This bit is set when the Outbound Free_List is full SI3 IS R Wriel G RST Software Interrupt 3 Status to Clear 512 IS R Write Software Interrupt 2 Status to Clear SII IS R Write 1 G RST Software Interrupt 1 Status to Clear SIO IS R Write 1 G RST Software Interrupt 0 Status to Clear Interrupt status bits are set upon the assertion of the interrupt condition Each interrupt status bit in the Interrupt Status register will remain set until a 1 is written to it Clearing of the interrupt status bit will not clear the source status bit that may have caused the interrupt to be asserted As part of the interrupt handling routine a separate register transaction to the corresponding status register must occur QSpan II User Manual 263 8091862 001 08 Appendix A Registers For instance the MDPED_IS bit is set if it is enabled when the MD_PED bit in the PCI Configuration Control and Status Register is set To clear this interrupt clear both status bits 1 0 related status bits OPNE_S IFE_S OFE_S IPF S OFF 5 are set regardless of the corresponding interrupt enable bit in INT CTL register Only IPN IS status bit is set when the interrupt enable bit IPN EN in INT is set and a new entry MFA is posted into the Inbound Post List FIFO 264 QSpan II User Manual 8091862 001 08 Appendix A Registers T
96. bits 52 77 203 204 268 summary 118 PARK bit PARB CTL Register 283 382 PAS bit PBTIO_CTL Register 224 384 Register 228 384 PCI BSIO Register 210 PCI BSTI Register 212 QBSIO CTL Register 285 382 5 Register 289 382 PB AERR Register 236 PAERR field 56 QSpan II User Manual 8091862 001 08 PB_DERR 56 PB_DERR Register 237 PB_ERRCS 56 PB_ERRCS Register 234 BE_ERR field 56 CMDERR field 56 EN bit 55 56 ES bit 56 PBROM CTL Register 232 PBTIO ADD Register 226 PBTIO CTL Register 224 PBTII ADD Register 230 Register 228 PBTIx ADD BA field 61 TA field 62 PBTIx CTL Register BS field 61 DSIZE field 59 62 68 EN bit 62 PAS bit 62 PWEN bit 62 TC field 62 66 PCI Bus Arbiter 141 Arbitration Scheme 142 Bus Parking 144 PCI Interface 31 cycle types 45 PCI Master Module defined 38 PCI Power Management Support 153 PME 153 PCI Target Image base address 61 block size 61 enabling 62 PCI address space 62 port size 62 posted write enabling 62 registers 226 231 transaction code 62 translation address 62 PCI Target Image 64 PCI Target Module 58 PCI Target Prefetch Disconnect 82 PCI ARB EN 177 185 Reset Options 158 PCI ARB EN bit QSpan II User Manual 8091862 001 08 Index PARB_CTL Register 283 382 PCI BSM Register 208 BA field 108 PCI BSROM Register 215 PCI BSTO Register 210 PCI BSTI Register 212 PCI BSTXx Register BA field 67 68 PAS bit 67 68 PCI CLA
97. bus Memory Space transactions can be posted 228 QSpan II User Manual 8091862 001 08 Appendix A Registers The BS 3 0 and PAS fields can be loaded from an external serial EEPROM see Mapping of EEPROM Bits to QSpan II Registers on page 126 for more details There are three cases 1 Ifthe BS 3 0 and PAS fields are loaded from the EEPROM then the EEPROM determines their reset state and they become read only except as described in 3 In this case the PAS bit has the same value as the bit of the same name in the PCI_BST1 register see Table 77 on page 212 2 If the fields are not loaded from the EEPROM their reset state is 0 and they are writable Note that in this case the PCI BSTI register is disabled 3 Ifthe power up option PCI DIS is set high during reset then BS 3 0 and PAS fields are writable from the QBus even if they were loaded from the EEPROM QSpan II User Manual 229 8091862 001 08 Appendix A Registers Table 93 PCI Bus Target Image 1 Address Register Register Name PBTI1_ADD Register Offset 114 PBTI1 ADD Description Reset Name Type Reset By State Function BA 31 16 See PCI RST See Base Address Below Below See Note TA 31 16 G RST noa Translation Address The Base Address specifies the contiguous PCI bus address line values compared by the QSpan II during PCI bus address phases The number of address lines compared for this image is based on the Block Size program
98. discussed e Big Endian System on page 392 e Little Endian System on page 393 e Endian Mapping Methods on page 394 E 1 Overview The PCI bus and the Motorola processors have some differences because of their unique evolutionary histories PCI was born in the Intel world making it Little Endian while the Motorola processors used Big Endian QSpan II User Manual 391 8091862 001 08 Appendix E Endian Mapping E 2 392 Big Endian System In a Big Endian system the most significant byte is located at the lowest address in memory When data is moved to the data bus the least significant byte is moved to the lowest byte lane Byte 3 in lowest byte lane and the most significant byte is moved to the highest byte lane Byte 0 in highest byte lane The following figure shows a 4 byte operand being moved to the data bus in a Big Endian system Figure 80 Big Endian System Memory Organization Byte Lanes Byte 3 Byte 2 Byte 1 Byte 0 LSB MSB te e te te S S B 3 B 2 1 B 0 03 02 01 00 QSpan II User Manual 8091862 001 08 E 3 Appendix E Endian Mapping Little Endian System In a Little Endian system the most significant byte is located at the highest address location When data is moved to the data bus the least significant byte is moved to the lowest byte lane Byte 0 in lowest byte lane and the most significant byte is moved to the highest byte lane Byte 3 in highest byte lane It
99. edge t335c A negated from QCLK positive edge P t336a BB_ negated from QCLK positive edge 2 t336b ON P O io 1 10 7 BURST negated from QCLK positive 1 edge 3 1 8 1 1 1336 t336a R W_ negated from QCLK positive edge 1 8 8 t336e SIZ negated from QCLK positive edge TA_ negated from QCLK positive edge 2 7 t336f 1 TC negated from QCLK positive edge 10 5 1 7 t336g 9 TEA_ negated from QCLK positive edge 3 11 9 8 8 8 7 8 1336h 8 TRETRY_ negated from QCLK positive edge 3 1 1336i 95 n 7 8 2 TS_ negated from QCLK positive edge 5 8 336 0 0 2 BDIP_ negated from QCLK positive edge 10 336k 3 A setup to QCLK positive edge g t337a t337b CSPCI_ setup to QCLK positive edge 3 4 i 5 3 CSREG_ setup to QCLK positive edge 1337c 3374 R W_ setup to QCLK positive edge 3 6 SIZ setup to QCLK positive edge gt 1337e AR TC setup to QCLK positive edge 5 3 t337f 7 gt TS_ setup to QCLK positive edge 13375 3 5 3 7 4 1 3 8 4 6 4 4 4 4 8 3 7 11 oo t350 DREQ_ asserted or negated from QCLK ax 5 2 4 8 8 3 2 3 4 8 2 positive edge 8 D asserted valid from SDACK_ negative edge 10 310 QSpan II User Manual 8091862 001 08 Appendix B Timing Table 155 Timing Parameters for MPC860
100. empty QSpan II assumes that the FIFO is empty when the pointers are equal at start up To indicate that the FIFO for example the IF FIFO is full at start up the QBus Host needs to first program the Top pointer to the top of the FIFO and then increment it by four This places the Top pointer at the bottom of the FIFO 3 QBus Host enables bit I2O EN in register 2 CS and enables access from the PCI bus to the QSpan II clear bit PCI DIS in register MISC CTL2 4 The Host with a mechanism similar to step 1 above reserves a number of memory locations to hold Outbound 1 0 messages It then writes the address of these locations MFAs to the OF FIFO see Inbound L O Message on page 138 This causes the QSpan II to update the IOF TP pointer for example if the Host writes 100 MFAs into OF FIFO then IOF TP 6144 4 101 6548 QSpan II s registers now contain the following BP 0xA000 1800 TP 0 000 1994 OF FIFO contains 100 MFAs QSpan II User Manual 137 8091862 001 08 Chapter 10 1 0 Messaging Unit 10 5 1 1 10 5 1 2 138 Inbound Message 1 2 3 The host gets an MFA by reading from offset 0x040 from the first Base Address Register I2O BAR This causes the QSpan II to generate a QBus delayed read cycle at address IIF BP 0xA000 0000 to get the first MFA When the read data is available the QSpan II returns the data to the Host QSpan II also increas
101. for every 32 bit transfer on the PCI bus The maximum amount of data that can be transferred using the DMA is 16 Mbytes Terminating a Direct Mode Transfer The completion of the DMA is signaled by an interrupt or is determined by polling the DONE bit in IDMA DMA CS While the DMA transfer is active the ACT bit in IDMA DMA CS is set Any writes to the IDMA DMA registers when the DMA is active are ignored except for the IRST REQ bit in IDMA DMA 5 and the STOP bit in DMA CS The DMA transfer can be terminated by setting the IDMA DMA Reset Request IRST REQ bit in the IDMA DMA CS register to 1 When the DMA transfer is terminated with IRST REQ the IRST status bit is set in IDMA DMA CS once the DMA Channel finishes any active transfer An interrupt can also be generated by the IRST status bit If a QBus or PCI error Master Abort or Target Abort is encountered during a DMA transfer the DMA transaction is terminated and the IQE or IPE status bits are set in IDMA DMA CS Linked List Mode DMA Operation Linked List mode allows the DMA Channel to transfer a series of non contiguous blocks of data without software intervention see Figure 9 on page 101 Each entry in the Linked List is described by a command packet containing data for the QSpan II s DMA registers The data structure for each command packet is the same and contains the necessary information to program the DMA address and control registers Each command packet is a record of
102. for their cards on the PCI bus at reset The identifiers enable the PCI Bus Expansion ROM Control Register PBROM_CTL and set various address and image parameters If the QSpan II is configured with an EEPROM the QSpan II can boot up as a Plug and Play compatible device local processor initialization is also possible QSpan II supports reads from and writes to the EEPROM The EEPROM device is not included with the QSpan II for more information see Chapter 9 The EEPROM Channel on page 123 QSpan II User Manual 8091862 001 08 Chapter 3 The QBus Slave Channel 3 1 This chapter describes the QSpan II s QBus Slave Channel The following topics are discussed e OBus Slave Channel Architecture on page 36 e Channel Description on page 38 e Address Phase on page 39 e Data Phase on page 46 e Termination Phase on page 53 e PCI Master Retry Counter on page 56 Overview The QBus direct connects to an MC68360 QUICC bus an MPC860 PowerQUICC bus or an M68040 bus see Figure 3 The QBus can also be direct connected to a combination of buses such as an MC68360 bus and an MPC860 bus A QBus master uses the QBus Slave Channel or IDMA DMA Channel to access a PCI target QSpan II User Manual 35 8091862 001 08 Chapter 3 The QBus Slave Channel 3 2 36 Figure 3 QBus Slave Channel Functional Diagram PCI QBus Interface Interface Slave Channel dbus Master Target Qx FI
103. four 32 bit data elements for a total of 16 bytes The command packets must be aligned to a 16 byte address boundary The fourth word of data in the command packet contains the next command packet pointer DMA CPP The least significant bit NULL bit of the fourth command packet word contains control information for the Linked List processing The NULL bit indicates the termination of the entire Linked List If the NULL bit is set to 0 the DMA processes the next command packet pointed to by the command packet pointer If the NULL bit is set to 1 then this command packet is considered to be the last command packet in the Linked List and the DMA stops at the completion of the transfer described by this command packet The DONE bit in IDMA DMA CS is set upon the completion of the final command packet QSpan II User Manual 8091862 001 08 Chapter 6 The DMA Channel Figure 9 Linked List DMA Operation First Command Packet in Linked List 31 20 0 M IDMA DMA_PADD Register lt M Linked List Start Address in Register information DIS SDD Regist Command Packet copied to DMA Control pes Pointer Register and Address Registers Register IDMA DMA_CNT Register a DMA_CPP Register N 4 N nut bit Second Command Packet in Linked List 31 20 0 gt IDMA DMA_PADD Register DMA_QADD Register DMA_CS Register IDMA DMA_CNT Register DMA_CPP Register N N null
104. is a pointer to a linked list of new capabilities MFBBC N A Master Fast Back to Back Enable QSpan II does not generate fast back to back transfers SERR_EN R W PCI_RST SERR Enable 0 Disable SERR driver 1 Enable SERR driver Setting this and PERESP allows the QSpan II to report address parity errors with SERR as PCI target WAIT N A Wait Cycle Control 0 No address data stepping PERESP R W PCI RST Parity Error Response 0 Disable 1 Enable Controls the QSpan II response to data and address parity errors When enabled PERR is asserted and the MD_PED bit is set in response to data parity errors When this bit and SERR_EN are set the QSpan II reports address parity errors on SERR QSpan II parity generation for example its assertion of PAR is unaffected by this bit VGAPS N A VGA Palette Snoop 0 Disable 1 Enable 204 QSpan II User Manual 8091862 001 08 PCI CS Description Continued Reset Name Type Reset By State MWI EN PCI RST PCI RST Powerup Option PCI RST PCI RST Appendix A Registers Function Memory Write and Invalidate Enable 0 Disable 1 Enable The QSpan II generates Memory Write and Invalidate command as PCI master during IDMA DMA transfers CMD bit set in IDMA DMA_CS Special Cycles 0 Disable 1 Enable The QSpan II never responds to special cycles as PCI target Bus Master 0 Disable 1 Enable Enables the QSpan II to become PCI bus master
105. mapping of IDMA done interrupt 1 Enable mapping of interrupt sss os osos ose Appendix A Registers INT_CTL Description Continued Reset Name Reset By State Function INT_EN G_RST PERR_EN SERR_EN OPNE_EN 266 QSpan II User Manual 8091862 001 08 Map PCI bus Interrupt Input to QBus Interrupt Output Enable 0 Disable mapping 1 Enable mapping of interrupt Map Parity Error on PCI bus to QBus Interrupt Output Enable 0 Disable mapping 1 Enable mapping of interrupt Map SERR Input to QBus Interrupt Output Enable 0 Disable mapping 1 Enable mapping of interrupt Map QBus Interrupt Input to PCI Bus Interrupt Output Enable 0 Disable mapping 1 Enable mapping of interrupt MailBox3 Interrupt Enable 0 Disable mapping 1 Enable mapping of interrupt MailBox1 Interrupt Enable 0 Disable mapping 1 Enable mapping of interrupt MailBoxO Interrupt Enable 0 Disable mapping 1 Enable mapping of interrupt QBus Data Parity Error Interrupt Enable 0 Disable mapping 1 Enable mapping of interrupt Power State Changed Interrupt Enable 0 Disable mapping 1 Enable mapping of interrupt Outbound Post_List Not Empty Interrupt Enable read only copy based on IM in I20_OPIM register 0 Disable interrupt 1 Enable interrupt when Outbound Post List is not empty sss sonos ose MailBox2 Interrupt Enable 0 Disable mapping 1 Enable mapping of interrupt INT_CTL Descripti
106. memory or QBus memory by the QSpan II This allows the QSpan II to follow a list of buffer descriptors established by the local controller or the system host A block of DMA register contents stored in memory is called a Command Packet A command packet can be linked to another command packet When the DMA has completed the operations described by one command packet it automatically moves to the next command packet in the Linked List of command packets A command packet cannot initiate an IDMA transfer it can only initiate a DMA transfer 96 QSpan II User Manual 8091862 001 08 Chapter 6 The DMA Channel 6 2 DMA Registers The DMA Channel uses the IDMA registers starting at Register offset 400 as well as three additional registers DMA_QADD see Table 112 on page 253 DMA_CS see Table 113 on page 254 and DMA_CPP see Table 114 on page 257 The PCI address for the DMA transfer resides in IDMA DMA Address Register IDMA DMA_PADD The QBus address for the DMA transfer resides in DMA QBus Address Register DMA_QADD The PCI and QBus addresses are aligned to a four byte boundary If a DMA transfer is required to cross an A24 boundary it must be programmed as two separate transactions The IDMA DMA Transfer Count Register JDMA DMA_CNT contains the number of bytes to be transferred during the DMA transfer see Table 111 on page 252 The minimum value for the transfer count is 16 bytes and it must be a multiple of four bytes
107. not applicable to IDMA transfers when the QBus is a 16 bit port Terminology Standard termination is used in the following figures in contrast to fast termination Normal termination as opposed to abnormal terminations such as bus errors and retries Thus some standard terminations are abnormal terminations for example bus errors with non fast termination 324 QSpan II User Manual 8091862 001 08 Appendix B Timing Figure 34 MC68360 IDMA Read Single Address Standard Terminations Ons 50ns 100ns 150ns 200ns 250ns paipa Ld d 1201 gt QCLK 253b gt 12596 CSPCI je 1253a gt e t259a AS_ A 31 0 1251 01252 D 31 0 ax P 7 t254 259 DACK_ DONE_ gt 1255 gt M 1259e DSACKO gt 1255 gt kt259e DSACKI e t256 gt 12591 BERR_ gt 257 gt 2590 HALT_ a Normal 11255 1259 DSACKO_ fa gt t255 gt amp 259 DSACKI 11256 gt 12591 e t257 2590 HALT_ b Bus Erroi 791255 gt k t259e DSACKO_ 9 255 gt fe t259e DSACKI 11256 gt 12591 BERR k t257 125909 HALT c Retry A 31 0 is depicted for completeness It is not examined by the QSpan II during IDMA transfers however it be used to drive CSPCI If the Port16 bit of IDMA CS is di
108. ns 2 positive edge t235b BR_ negated from QCLK positive 3 2 7 3 3 5 8 1 ns 1 to36a A tristated or negated from QCLK 3 8 4 3 10 7 ns 1 positive edge t236b BERR_ tristated or negated from 3 7 9 2 4 1 10 2 ns 1 QCLK positive edge t236c DSACKO DSACK1_ tristated or 3 3 9 4 3 7 10 4 ns 1 negated from QCLK positive edge t236d HALT tristated or negated from 3 5 3 9 ns 1 QCLK positive edge t236e R W tristated or negated from 3 2 3 6 ns 1 QCLK positive edge t236f SIZ tristated or negated from QCLK 3 1 7 9 3 5 8 8 ns 1 positive edge 02365 TC tristated or negated from QCLK 3 3 8 4 3 7 9 3 ns 1 positive edge 050 DREQ_ asserted or negated from 4 9 3 4 4 10 4 ns 2 QCLK negative edge t251 D asserted valid from DACK_ 12 5 13 9 ns 1 negative edge t252 D tristated from DACK_ positive edge sw AS setup to QCLK negative edge setup to QCLK negative AS setup to QCLK negative edge 34 4 EE NE t253b CSPCI_ setup to QCLK negative 2 8 edge t254 DACK setup to QCLK negative 2 5 2 8 ns edge 306 QSpan II User Manual 8091862 001 08 Appendix B Timing Table 154 Timing Parameters for MC68360 Interface Continued Frequency Temperature Options Timing Parameter Description Sie d Units Note 304 DSACK1_ setup to EE negative 304 056 BERR_ setup to QCLK negative ns edge 057 HALT setup to QCLK negative edge D setup to D setup to QC
109. occur on the PCI bus If the QSpan II has already been selected by a PCI master QSpan II has asserted DEVSEL then the QSpan II will immediately negate DEVSEL but TRDY and STOP will not be asserted by the QSpan II IDMA Reset IDMA reset issues are discussed in IDMA Errors Resets and Interrupts on page 91 Clocking and Resets The PCLK can operate anywhere from DC to 33 MHz The maximum QCLK frequency depends on the host processor For MPC860 applications the maximum QCLK frequency is 50 MHz For MC68360 applications the maximum frequency is 33 MHz The QCLK input is not required to be operating to successfully complete QSpan II resistor accesses from the PCI bus QSpan II supports asynchronous assertion and negation of Resets Refer to the tables in Signals and DC Characteristics on page 179 for a description of the state of each QSpan II pin after reset When a PCI reset RST is asserted and H5 HEALTHY is low QSpan II s RESETO_ signal will be asserted and negated as shown in Appendix B Timing on page 301 QSpan II User Manual 8091862 001 08 Chapter 14 Reset Options The QCLK and PCLK inputs are necessary for software resets That is these clocks are required in order for the QSpan II to negate RESETO_ This is due to the fact that for a software reset the QSpan II s registers must be accessed to cause RESETO_ to negate If the QCLK or PCLK input stops toggling then it is impossible to write to the
110. od mm E T 40 15 1L E IH 2 334 i 8101512 G 1 2 1 PBGA Notes 27 mm 1 Alldimensions conform to ANSI Y 14 5 1994 Dim in millimeters mm 2 Measured at the maximum solder ball diameter parallel to primary datum Z 3 Primary datum Z and seating plane are defined by the spherical crowns of the solder balls 4 AJ Ball Corner ID Marked in ink for plate mold Indent if Automold A Corner is identified by chamfer ink mark metallized mark indentation or other feature of the package body or lid 6 Reference Specification QSpan II conforms to Jedec Registered Outline drawing MO 151 7 Ball pad is 0 60 mm diameter IDT recommend s customer s PCB pad has same diameter 404 QSpan II User Manual 8091862 001 08 Appendix G Mechanical Information Figure 87 256 PBGA 27 mm Bottom View QSpan User Manual 405 8091862 001 08 Appendix G Mechanical Information 406 QSpan II User Manual 8091862 001 08 Appendix H Ordering Information This appendix discusses ordering information for the QSpan II H 1 Ordering Information Table 180 Ordering Information CA91L862A 50IL 33MHz MC68360 40 to 85 C 17 mm PBGA 50MHz MPC860 CA91L862A 50IB 33MHz MC68360 40 to 85 C 27 mm PBGA 50MHz MPC860 CA91L862A 50IEV 33MHz MC68360 3 40 to 85 C 27 mm PBGA 50MHz MPC860 a The QSpan is compatible with all M68040 variants in large buff
111. output from the MC68360 processor All of the AC timing waveforms for the QSpan II MC68360 interface are based CLKOI QSpan II User Manual 361 8091862 001 08 Appendix C Typical Applications C 1 1 2 362 Memory Controller MC68360 Figure 75 MC68360 Interface EXTAL E Oscillator CLKO1 QCLK D 31 0 SIZ 1 0 DSACK O _ DSACKO DSACK 1 _ DSACK1_ TA_ QSpan 11 5 D 5_ BG_ BGACK_ BB_ BGACK_ BERR BERR_ TEA HALT_ HALT RETRY FC 3 0 TC 3 0 DREQ_ IRQ 7 1 QINT RESETI The QSpan Il is an autovector interrupter so the MC68360 must be configured to generate AVEC to terminate the IACK cycle re RESETH_ RST Connects to RESETO_ PCI bus RST 7 Reset Strategy for Host Bridging Applications m RESETH_ RESETO_ Reset Strategy for PCI H RESETI_ Adapter Applications Y m i BURST TIP SDA and ENID control the EEPROM port at reset p m 2 p gt p co BDIP_ BDIP must be pulled low for 360 master mode Resets There are three reset situations depending upon the use of the QSpan in your application PCI adapter card bridge PCI Host bridge or CompactPCI adapter card supporting Hot Swap QSpan II User Manual 8091862 001 08 Appendix C Typical Applications For a PCI adapter card application use the following reset configuration connect the QSpan II s r
112. reset all of the PCI agents under software control The M68040 can write to the software reset bit in the QSpan II s MISC register which will cause the QSpan II to assert its RESETO signal QSpan II s reset input RESETI is normally unused and should be pulled high through a resistor for more information about resets see Chapter 14 Reset Options on page 155 For a CompactPCI adapter card application that supports Hot Swap the QSpan II s HS HEALTHY signal should be connected to the Hot Swap controller s HEALTHY signal QSpan II User Manual 375 8091862 001 08 Appendix C Typical Applications 6 3 1 3 C 3 1 4 5 23 376 Address Decoder QSpan II requires two chip selects and an image select signal IMSEL to be generated in order to access the registers CSREG_ and the PCI bus CSPCI_ There is no internal memory controller within the M68040 and therefore an external address decoder must be implemented The IMSEL signal determines which QBus slave image is accessed when CSPCI_is asserted to the QSpan If IMSEL is low then QBus slave image 0 is selected otherwise QBus slave image 1 is selected IMSEL is typically dependent on the processor s memory map and is generated directly from one of the high order address lines An alternative method is to use a registered output which resides on the QBus When the opposite slave image must be accessed the M68040 would first perform a write to change the state of th
113. the hardware design this output can be used to reset the QBus processor This bit controls the QSpan II s response to the QBus processor when a Master Abort occurs on the PCI bus Set this bit to 1 before the QSpan II performs any PCI Configuration cycles This field controls the amount of data that is prefetched when a PCI burst read occurs to the QSpan II s PCI Target Channel If the PCI Initiators perform burst read cycles then prefetching should be enabled to improve the system s performance For more information see the PCI Target Channel s control registers in Appendix A Registers on page 195 QSpan II s MISC CTL2 register bits which affect the device s performance initialization are shown in Table 162 QSpan II User Manual 8091862 001 08 Appendix D Software Initialization Table 162 Summary of the QSpan II s Miscellaneous Control Register 2 MISC CTL2 PCI DIS PTP IB KEEP BB MAX RTRY 1 0 PTC PD TA BE EN BURST 4 SING PR CNT2 5 0 REG AC NOTO QSC PW QSpan II User Manual 8091862 001 08 Description This bit must be cleared before any PCI Target accesses will complete successfully This field allows the PCI Target Channel Prefetch Count to be Image Based Enable this feature if the PCI Initiators have different PCI bursting requirements This bit allows the QSpan II to hold onto the QBus for back to back cycles Setting this bit will improve the performance through the QSpan II
114. the IF FIFO at the Top pointer It must also increment the QSpan II s IIF TP pointer by four TP 0xA000 0328 using a QBus register access 1 0 Outbound Message 1 The QBus Host gets a pointer to the location of an MFA for the outbound message by reading QSpan II s Outbound Free List Bottom Pointer IOF_BP It needs to increase the IOF_BP by four IOF_BP 0xA000_1804 to point to the next MFA these are done through QBus register access The QBus Host writes the message to the host memory location pointed by the MFA The QBus Host places the MFA in the OP_FIFO using the Top pointer It also needs to increment the QSpan II s Outbound Post List Top Pointer register TP by four TP 0xA000 1004 QSpan II generates a PCI interrupt if not masked by the bit OP IM in register 2 OPIM when the OP FIFO is not empty and sets the OP ISR bit in the I2O OPIS register see Table 150 on page 296 QSpan II User Manual 8091862 001 08 Chapter 10 1 0 Messaging Unit 4 The Host is notified of the Outbound message either through the PCI interrupt or by polling the status bit It then initiates a PCI memory read access at offset 0x044 from the first BAR in the QSpan II s Configuration space I2O BAR to get the MFA This causes the QSpan II to generate a QBus delayed read cycle at address BP 0xA000 1000 When the read data is returned to the QSpan the data is passed back to the Host QS
115. the appropriate value 218 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 84 PCI Power Management Capabilities Register Register Name PCI_PMC Register Offset 31 24 PME_SP D2_SP DL SP 15 08 NXT IP 07 00 CAP_ID PCI_PMC Description Reset Name Type Reset By State Function PME SP 4 0 R WQ E PCI RST PME Support Indicates the power states in which QSpan II asserts PME 0X001b PME can be asserted from DO 0100Xb PME can be asserted from D3y 4 Bits 4 2 and 1 are set to 0 since QSpan never asserts PME when in D2 or D1 D2_SP PCI_RST D2 Support Set to 0 to indicate that D2 power state is not supported D1_SP PCI_RST D1 Support Set to 0 to indicate that D1 power state is not supported PCI_RST 0 Device Specific Initialization Device Specific Device Specific Initialization PCI_RST Auxiliary Power Source Set to 0 since PME is not supported from D314 PME_CLK PCI_RST PME Clock Set to 1 to indicate that a clock is required to assert PME when any of the PME SP bits are set to 1 Set to 0 when all the PME SP bits are 0 VER 2 0 R WQ E PCI RST 001 Power Management Version A value of 001 indicates that this device complies with Revision 1 0 of the PCI Power Management Interface Specification 1 1 NXT IP 7 0 PCI RST OxE4 Next Item Pointer Set to OxE4 to indicate that the next item in the QSpan capabilities list Compact PCI Hot Swap is located at
116. the start of the memory region specified by the I O base address Configuration register I2O BAR and the start of the message The inbound MFAs must be above the 4 Kbyte region for example Inbound MFAs must be greater than FFFh Each outbound MFA is specified as the offset from Host memory location 0000 0000h to the start of the message frame in shared Host memory Summary of Operations Initialization The following initialization operation allows the QSpan to take part in IO operations 1 The QBus Host reserves a number of memory locations in its local memory to hold inbound I O messages The locations do not have to be contiguous It then creates FIFO IF FIFO that contains the address to these memory locations MFAs It creates another FIFO IP FIFO that contains the Inbound Post List MFAs The QBus Host then creates two more circular FIFOs OF FIFO and OP FIFO All four FIFOs must be the same size They can be anywhere in a 1 Mbyte window from the base address defined by QIBA in I2O CS register without overlapping The four FIFOs are required to be in the same 1 Mbyte window so that the upper 12 bits 31 20 are the same for the eight pointers maintained by the QSpan II QSpan II User Manual 8091862 001 08 Chapter 10 1 0 Messaging Unit 2 The QBus Host then programs the Inbound Free List pointers in the QSpan II registers Inbound Free List Bottom Pointer BP must point to the 0
117. the transaction if it receives STOP from the PCI target TRDY Bidirectional s t s Target Ready used by the QSpan II as PCI target to indicate that it is ready to complete the current data phase During a read with QSpan II as PCI master the target asserts TRDY to indicate to the QSpan II that valid data is present on the data bus 16 7 Hot Swap Signals ENUM Open Drain Output Hot Swap Event Interrupt notifies the PCI host that either a board has been inserted or is about to be extracted Hot Swap Healthy QSpan internally OR s this input with PCI reset RST to determine when back end power is stable HS_LED Output Hot Swap LED Control This signal is driven by QSpan II to control the status of the LED The signal is driven low to turn on the LED during the hardware and software connection stages The signal is tri stated during normal operation to turn off the LED HS_SWITCH Hot Swap Switch QSpan II uses this input to monitor the state of the Hot Swap board ejector latch A low value on this signal indicates that the ejector latch is open 176 QSpan II User Manual 8091862 001 08 Chapter 16 Signals 16 8 Miscellaneous Signals ENID EEPROM Loading Reset Option If ENID is sampled high after a PCI reset then the QSpan II will download register information from the EEPROM PCI_ARB_EN PCI Arbiter Enable If PCI ARB EN is sampled high at the negation of Reset the QSpan II s PCI bus arbiter is enab
118. to from the other bus For example if mailbox 0 is programmed to generate a QBus interrupt by setting MBO EN to 1 in INT CTL register and MBO_DIR to 0 in INT DIR register then a PCI write with any of the byte lanes enabled to mailbox 0 will generate a QBus interrupt QINT_ In this case mailbox 0 can also be written to from the QBus but this will not generate a QBus interrupt Likewise if a mailbox is programmed to generate a PCI interrupt a PCI interrupt is only generated when that mailbox is written to from the QBus To clear an interrupt write a 1 to the corresponding status bit in INT STAT see Table 119 on page 262 114 QSpan II User Manual 8091862 001 08 Chapter 8 The Interrupt Channel This chapter describes the function of the QSpan II Interrupt Channel The following topics are discussed e Hardware Triggered Interrupts on page 116 e Software Triggered Interrupts on page 117 e Interrupt Acknowledge Cycle on page 121 e Disabling PCI Interrupts on page 121 8 1 Overview Certain hardware and software events can trigger interrupts on the QBus and the PCI bus through the Interrupt Channel see Figure 14 Two bidirectional interrupt pins are provided INT for the PCI bus QINT for the QBus QSpan II User Manual 8091862 001 08 115 Chapter 8 The Interrupt Channel 8 2 Hardware Triggered Interrupts In order for an input to trigger an interrupt on the opposite interface the co
119. to initialize the QSpan II QSpan II User Manual 8091862 001 08 7 4 Chapter 7 The Register Channel Register Access from the QBus QSpan registers be selected by an external master from the QBus with the CSREG chip select pin Since the QSpan II registers span 4K only the lower 12 bits of the QBus address are used see Figure 12 Register accesses of 8 bit 16 bit or 32 bit size can be preformed However the QSpan is a 32 bit slave device for more information see Table 8 on page 47 and Table 9 on page 48 If an external master on the QBus attempts to access the QSpan II s registers the transfer is retried on the QBus QSpan II will then make an internal request for register ownership by the QBus The request is removed if no register access is attempted within 2 QCLK clock cycles The request is also removed if a register access completes the QBus without a subsequent register access beginning within 32 QCLK clock cycles of the completion of the previous register access This type of access is implemented when the Register Access Control REG AC bit is set to 0 in the MISC_CTL2 register see Table 130 on page 280 QSpan registers do not support burst accesses If a burst to register space is attempted from the QBus a bus error is issued Figure 12 QCSR Access from the QBus A QBus Memory QSPAN DEVICE SPECIFIC REGISTERS 4 Kbytes _ of QCSR PCI CONFIGURATION SPACE
120. transfers 1 External slave uses fast termination during MC68360 single address IDMA transfers QBus Port 16 0 Source destination on QBus is a 32 bit port 1 Source destination on QBus is a 16 bit port 249 Appendix A Registers 250 with a value less than or equal to the value programmed in the IDMA The programmable I FIFO Watermark IWM 3 0 must be programmed N Transfer Count Register The QTERM bit is important when the QSpan II is operating as an MC68360 IDMA peripheral device during dual address IDMA transfers During all other conditions this bit does not affect the QSpan II s operation The STERM bit is important when the QSpan is operating as an MC68360 IDMA peripheral device during single address IDMA transfers During all other conditions this bit does not affect the QSpan II s operation The IDMA DMA Channel can be reset from either bus while it is in progress by writing 1 to the IRST REQ bit see Errors Resets and Interrupts on page 91 If the ACT bit is 0 then setting IRST_REQ to 1 has no effect The DONE bit is set by the QSpan II if its transfer count expires in the IDMA DMA Transfer Count register or the DONE signal is asserted by the MC68360 during IDMA transfers Under either condition the QSpan II s IDMA controller will return to the idle state which is indicated by the ACT bit The IRST DONE IPE and IQE events can be mapped to the interrupt pins on either bus using the QSpan
121. when it is a QBus slave and tristated otherwise As an output BERR_ TEA_ is driven by the QSpan II from the rising edge of QCLK QSpan II negates BERR_ TEA_ prior to tristate As an input the QSpan samples BERR_ TEA_ on the rising edge of QCLK during cycles in which it is a QBus master Bus Grant indicates that the QSpan II may become the next QBus master BG along with BR and BB BGACK provide the three wire handshake for QBus arbitration is sampled on the rising edge of QCLK QSpan II can be programmed to use a asynchronous mode for QBus arbitration QSpan II User Manual 167 8091862 001 08 Chapter 16 Signals 16 4 MPC860 Signals PowerQUICC Continued Bus Request used by the QSpan II to request ownership of the QBus BR_ along with and BB BGACK provide the three wire handshake for QBus arbitration BR is asserted and released from the rising edge of QCLK Bidirectional Bus Master Enable If this input is asserted set as 1 during a PCI Reset the Bus Master Enable bit in the PCI CS register will be set FIFO_RDY FIFO Ready functionality is not relevant to MPC860 applications BURST TIP Tristate bidirectional Burst indicates that the current initiated transfer is a burst cycle This signal matches the MPC860 signal of the same name PCI Chip Select indicates that the current transaction on the QBus is an access to the PCI Bus CSPCI_ can be sampled on the same clock as TS or up to
122. write transactions comprise five entries in the Qx FIFO one entry for address and command information and four data entries The QBus Slave Module accepts bursts if the Qx FIFO has enough room for the entire burst Burst transfers are never retried while they are in progress The MPC860 and M68040 perform bursts of 16 bytes Bursts accepted from the QBus are translated to the PCI bus as one or more burst transactions QSpan II always bursts using linear increment addressing Burst transactions are always posted regardless of the programming of the PWEN bit in the selected QBSIx_CTL register QSpan II accepts bursts targeted to Memory space but not to I O or Configuration space If the PCI address space PAS bit of the selected image is set to I O space and a burst is initiated by a QBus master then the QSpan II signals a bus error Similarly if a burst is attempted to the QSpan II registers a bus error is signaled by the QSpan II see Termination Phase on page 53 To improve performance of posted write transfers set QSC PW bit in the MISC CTL2 register see Table 130 on page 280 This configuration reduces the number of idle PCI clocks between posted write transfers initiated by the QSpan II s PCI master QSpan II User Manual 49 8091862 001 08 Chapter 3 The QBus Slave Channel 3 5 2 2 354 3 50 Read Transactions Burst and Single Cycle During a read transaction address data size and transaction code signa
123. zeros 236 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 99 PCI Bus Data Error Log Register Register Name PB_DERR Register Offset 148 31 24 PDERR 23 16 PDERR 15 08 PDERR 07 00 PDERR PB_DERR Description Reset Name Type Reset By State Function PDERR 31 0 G_RST PCI Data Error Log The QSpan II as PCI master will log errors if a posted write transaction results in a Target Abort or a posted write transaction results in a Master Abort This register logs the PCI bus data information Its content are qualified by bit ES of the PCI Bus Error Log Control and Status register see Table 97 The PDERR field contains valid information when the ES bit is set At all other times a read of this register will return all zeros QSpan II User Manual 237 8091862 001 08 Appendix A Registers Table 100 Control and Status Register Register Name I2O CS Register Offset 200 Function 31 24 QIBA CS Description Reset Name Reset By State Function QIBA 31 20 G RST QBus 1 0 Base Address i G_RST Outbound Free_List FIFO Empty 0 Not Empty 1 Empty Base address of the block of memory that contains the four FIFOs in QBus memory The four FIFOs two Inbound and two Outbound are of equal size but need not be in contiguous memory locations QIBA is aligned to a 1 Mbyte address boundary Inbound Free_List FIFO Empty 0 Not Empty 1 Empty Inbou
124. 0 can be ANE to four out of the five TT 1 0 and TM 2 0 M68040 signals The unused TC pins if any must be connected to pull up resistors see Appendix C Typical Applications on page 361 MPC860 signals do not necessarily operate in the same manner as MC68360 signals of the same name QSpan II User Manual 8091862 001 08 Chapter 16 Signals 16 3 MC68360 Signals QUICC A 31 0 Tristate bidirectional Address Bus address for the current bus cycle It is driven by the QSpan II when it is the QBus master and input when QBus slave It is qualified at the start of a transaction by AS_ As a slave the QSpan II samples A 31 0 on the same falling edge of the QCLK as AS Both A 31 0 and AS must meet the synchronous set up and hold time parameters about the falling edge of the QCLK to ensure correct operation As a master the QSpan II maintains the correct asynchronous timing relationships between A 31 0 and AS The address bus is driven valid after the rising edge of the QCLK while the AS is driven only after the subsequent falling edge of the same clock period ensuring the correct address before AS_ timing When accesses are made to QSpan II registers from the QBus only the lower 12 bits of the address bus are used to determine the offset Rescinding Tristate bidirectional Address Strobe indicates the beginning and duration of a transaction on the QBus As an output AS_ is driven by the QSpan II when the QSpan
125. 1 see Table 109 on page 248 Note that the IDMA DMA_PADD register the IDMA DMA_CNT register and the rest of the IDMA DMA CS register are not reset 5 If enabled an interrupt is generated on the QBus or the PCI bus see Chapter 8 The Interrupt Channel on page 115 5 7 IDMA Endian Issues The PCI bus and Motorola processors differ in the way they order and address bytes These differences are explained in Appendix A Registers on page 195 This section describes how the QSpan II translates cycles from the QBus to the PCI bus in the IDMA Channel The PCI bus is always a Little Endian environment The QBus can be configured as Little Endian or Big Endian depending on the value of the QBus Byte Ordering Control bit BOC in the MISC register see Table 127 on page 276 The default mode for the QBus is Big Endian QSpan II translates byte lane ordering when the QBus is Big Endian while preserving the addressing of bytes When the QBus is Little Endian according to BOC the QSpan II preserves byte lane ordering while translating the addressing of bytes Note that the QB_BOC bit affects transactions in all channels Table 33 describes mapping of 16 bit QBus transactions in Little Endian mode The byte lane ordering is preserved in Little Endian mode During a read transaction a full 32 bit PCI transaction is unpacked into two 16 bit QBus transfers During a write transaction two 16 bit QBus transactions are packe
126. 115 for more information about interrupts PCI Signals QSpan II s PCI signals can be directly connected to the appropriate PCI signal on the motherboard or the PCI connector Pull up resistors may be required to be added to the PCI bus control signals depending on the application If you are designing a local PCI bus on a motherboard then pull up resistors are required for more information see the PCI 2 2 Specification For host bridging applications possible implementations for the QSpan II s IDSEL signal include the following connect it to a spare AD signal AD 31 12 connect it to ground through a resistor if the host is not required to respond to PCI configuration cycles The QSpan II supports both 5V and 3 3V I O signaling environments Vy Highest I O voltage must be connected to the highest voltage level the QSpan II I Os will observe on either the QBus or the PCI bus EEPROM Interface A serial EEPROM may be required for applications which must support a Plug and Play environment for more information about EEPROM reset options see Reset Options on page 365 QSpan II also allows that QBus processor to initialize the QSpan II to support a Plug and Play environment for more information see EEPROM Configuration and Plug and Play Compatibility on page 125 QSpan II User Manual 8091862 001 08 Appendix C Typical Applications C 1 1 8 Reset Options A number of reset options exist with the QSpan II device
127. 16 510_ Enable long EEPROM load 7 6 5 4 1 BS BS BS BS EN PCI_ID 15 14 13 12 11 10 9 8 DID DID DID DID DID DID DID DID PCI ID 7 6 5 4 3 2 1 0 DID DID DID DID DID DID DID DID PCI_ID 15 14 13 12 11 10 9 8 VID VID VID VID VID VID VID VID PCI_ID 7 6 5 4 3 2 1 0 VID VID VID VID VID VID VID VID PCI_CLASS 7 6 5 4 3 2 1 0 BASE BASE BASE BASE BASE BASE BASE BASE PCI_CLASS 7 6 5 4 3 2 1 0 SUB SUB SUB SUB SUB SUB SUB SUB PCI_CLASS 7 6 5 4 3 2 1 0 PCI MISCI 7 6 5 4 3 2 1 0 MAX_LAT MAX LAT MAX LAT MAX LAT MAX LAT MAX LAT MAX LAT MAX LAT 128 QSpan II User Manual 8091862 001 08 Chapter 9 The EEPROM Channel Table 44 Destination of EEPROM Bits Read Continued PCI MISCI 7 6 5 4 3 2 1 0 20 MIN GND MIN_GNT MIN_GNT MIN_GNT MIN_GNT MIN_GNT MIN_GNT MIN GNT PCLMISCI MISCI 2 2 E eS 4 3 2 1 21 INT PINO 154 SP PME_SP 080 PM_VER PM_VER VER PCI BSTO PCL B
128. 16 9 JTAG Signals Test Mode Select Used to control the state of the Test Access Port controller Test Input Used in conjunction with TCK to shift data and instructions into the Test Access Port TAP in a serial bit stream Test Output Used in conjunction with TCK to shift data and instructions into the Test Access Port TAP in a serial bit stream Test Reset Used to force the Test Access Port TAP into a initialized state Test Clock Used to clock state information and data into and out of the device during boundary scan 178 QSpan II User Manual 8091862 001 08 Chapter 17 Signals and DC Characteristics This chapter discusses QSpan II signals and DC characteristics The following topics are explained e Packaging and Voltage Level Support on page 180 e Signals and DC Characteristics on page 180 e Pinout on page 192 17 1 Terminology The following abbreviations are used in this chapter 25 Two state output 35 Tristate output B Bidirectional I Input Output OD Open Drain PD Internal pull down PU Internal pull up TTL Input with TTL threshold TTL PU Input with TTL threshold the pull up resistor is internal TTL Sch TTL Schmitt trigger input QSpan II User Manual 179 8091862 001 08 Chapter 17 Signals and DC Characteristics 17 2 Packaging and Voltage Level Support QSpan is available in two packages 17 mm x 17 mm 1 0 mm ball pitch 256 PBGA e 27mm x 27 mm 1 27 mm ball pitc
129. 194 R 3 415i gt 414196 t415 4156 14 13 14152 15 gt 13 t409a t410e NN WA 7 Wait states be inserted if the starting address is not aligned to 16 byte boundary 354 QSpan II User Manual 8091862 001 08 Appendix B Timing Figure 66 Register Reads QSpan II as M68040 Slave Ons 100ns 200ns 300ns 400ns E Ww dE Jl pt ws is bL ow ib dp sj aen 1401 orek A S _ we A A a gt It 1419 t415a k 31 0 gt amp t419c 2114181 k CSREG_ 14130 gt 14154 BURST_ TIP_ gt t419e 94155 SIZ 1 0 gt 14198 1415144 TC 3 0 gt t419d 614151 R W V 14150 gt 41419 TS_ 011417 8141 t416 D 31 0 t409a t4t0e 01436 a s TEA_ a Normal t409a 1410 t486 TA y 14090 0114109 gt 360 a b Retry QSpan II User Manual 355 8091862 001 08 Appendix B Timing Figure 67 Register Write QSpan as M68040 Slave Ons 250ns 500ns 414015 OCLK A S A N A A NAE ey 14192 gt 11415a A 31 0 i k t419c gt 141
130. 266 PCI CS Register 204 SERR IS bit INT STAT Register 263 SERR 77 176 185 SIO bit INT CTL Register 267 510 DIR bit INT DIR Register 270 SIO IS bit INT STAT Register 264 SII bit INT CTL Register 267 5 DIR bit INT DIR Register 270 SII IS bit INT STAT Register 264 SD bit INT CTL2 Register 271 SD DIR bit INT DIR Register 270 SD IS bit INT STAT Register 264 SI3 bit INT CTL2 Register 271 5 DIR bit INT DIR Register 270 SI3 IS bit INT STAT Register 264 SID field PCI SID Register 214 QSpan II User Manual 8091862 001 08 SIZ_ERR field QB_ERRCS Register 293 385 SIZ 1 0 94 121 166 170 173 185 size encoding M68040 174 size encoding QUICC and PowerQUICC 171 SIZ 1 185 SIZ 3 0 364 Software Initialization 379 EEPROM and VPD 388 Error Logging of Posted Transactions 385 Generation of PCI Configuration and IACK Cycles 387 I20 Messaging Unit 388 IDMA DMA Channel 386 Interrupt Initialization 386 Miscellaneous Control Register Configuration 380 PCI Expansion ROM Implementation 389 PCI Target Channel 383 QBus Slave Channel 382 Register Access from the PCI Bus 383 SPACE bit I20 BAR Register 209 PCI BSM Register 208 Special Cycle 45 STERM bit IDMA DMA CS Register 249 STOP bit DMA CS Register 255 STOP STAT bit DMA CS Register 255 STOP 82 83 176 185 SUB field PCI_CLASS Register 206 SVID field PCI_SID Register 214 SW_RST bit MISC_CTL Register 276 380 T TA bit PBTI1_ADD Register 384
131. 3 1 82 er ke bbe SE UA Ss 48 3 5 2 2 Read Transactions Burst and Single 50 3 5 2 3 Pretetched Reads RUE E ra a 50 3 5 2 4 Delayed Reads and PCI Transaction 51 3 5 3 PCI Target Channel 52 3 5 4 Parity Monitoring by PCI Master Module 52 3 6 T rmination Phas able ane 53 3 6 1 Posted Write 55 3 7 PCI Master Retry 56 Chapter 4 The PCI Target Channel 4 wasnuas Rh Rr RR Rh 57 41 OVGIVIEW nec nets aad Sed ede Re PE EU Ded Run EO DR He aie dui d 57 4 2 PCI Target Channel Architecture 1 58 42 Target Module 00206 tette cec ao 58 4 2 2 4 59 4 23 QBus Master 59 4 2 3 1 QBus Data Parity Generation and 60 43 Channel Description ses ORAE ede Pa e ER PAS eee 60 44 Address
132. 35 8091862 001 08 Chapter 10 1 0 Messaging Unit 10 4 10 5 10 5 1 136 QSpan II then supplies the data from the Bottom of the Outbound Post List FIFO If the Outbound Post List FIFO is empty the QSpan returns OXFFFF FFFF to the PCI Host or IOP on the PCI bus The PCI host allocates available system message frames to the QBus Host by writing an available MFA to the outbound queue at offset 0x044 QSpan II then writes this MFA to the Top of the Outbound Free List FIFO in QBus memory 1 0 Operation When the QSpan is enabled for 1 0 operation I20 Enable I20_EN in register CS the base address register for PCI Target Image 0 PCI BSTO is moved to the first base address register in the Configuration space offset 0x010 and is renamed I20 BAR The base address register for accessing the QSpan II registers from PCI PCI BSM is then moved from offset 0x010 to 0x018 for more information see 1 0 Messaging Unit Initialization on page 388 The QBus translation address and other QBus options can be set in PBTIO_CTL and PBTIO ADD for message passing from the Host to the QBus memory The bottom 4 Kbytes of the I2O BAR is not translated into QBus memory In this 4 Kbyte region 16 bytes are predefined for operation offsets 0x030 and 0x034 are used for system interrupt generation and offsets 0x040 and 0x044 are defined as the location of the Inbound and Outbound queues Each inbound MFA is the offset between
133. 35 amp 21315 BDIP_ k 1337e 421315 SIZ 1 0 4 R t337f jtm TC 3 0 4 11337 lt gt 319 RW 1 gt t315p k 387g TS cy t315h t315h t315h t315h k t3ibe 4113 1 Fe 1313 1313 D 31 0 DATA DATA DATA3 DATAXY 1335a 310f gt 336f TA m g TEA_ TRETRY_ A minimum of one wait state is inserted if starting address is not aligned to a 16 byte boundary 340 QSpan II User Manual 8091862 001 08 Appendix B Timing Figure 51 Register Read QSpan as MPC860 Slave Ons 100ns 200ns 300ns li OM jm d 4 1301 4 eek _ CAL 05 C S C S 25 92 _ U k t337a gt k13 5a A 31 0 k t3370 gt 13159 CSREG_ gt Kt t313d gt t315e BURST 4 gt 1337 gt let315k SIZ 1 0 4 13371 gt lt315m TC 3 0 k t337d 1315 R W_ gt kt315p t337g TS 1314 t317 14 1316 D 31 0 NENNEN 1335 9131 2113361 LY TEA TRETRY a Normal TA_4 TEA_4 t335c 13101 336i TRETRY p b Retry QSpan II User Manual 341 8091862 001 08 Appendix B Timing Figure 52 Register Write QSpan II as MPC860 Slave
134. 36 32 Bit Big Endian IDMA Cycle Mapping PCI bus SIZ 1 0 A 1 0 D 31 0 BE 3 0 D 31 0 94 QSpan II User Manual 8091862 001 08 Chapter 6 The DMA Channel 6 1 This chapter examines the function of QSpan II s DMA Channel The following topics are discussed e DMA Registers on page 97 Direct Mode DMA Operation on page 99 e Linked List Mode DMA Operation on page 100 Overview QSpan II has a DMA Channel for high performance data transfer between the PCI bus and the QBus see Figure 8 The DMA Channel functions similarly to the IDMA Channel in that it uses the existing IDMA registers and some additional registers and shares the 256 byte I FIFO with the IDMA Channel Because of the shared FIFO the QSpan II cannot use its IDMA and DMA Channels at the same time IDT recommends using the DMA Channel over the IDMA Channel because it supports higher rates of data transfer between the PCI bus and 2 the QBus QSpan II User Manual 95 8091862 001 08 Chapter 6 The DMA Channel Figure 8 DMA Channel Functional Diagram QBus Interface Interface IDMA DMA Channel Module PCI Target Module There are two modes of operation for the DMA Channel Direct Mode and Linked List Mode also called Scatter Gather mode In Direct Mode the DMA registers are programmed directly by an external master In Linked List Mode the DMA registers are loaded from PCI Bus
135. 360 operates in Slave mode set the MC68360 s SYNC bit to 0 in the GMR register QSpan II User Manual 8091862 001 08 C 2 MPC860 Interface Appendix C Typical Applications This section describes how the QSpan II can be connected to the MPC860 communications controller and other MPC8xx devices Figure 76 MPC860 Interface CLKOUT Memory EXTCLK 2 CSREG_ Controller IMSEL AB TO D 0 31 TSIZ 0 1 D 31 0 SIZ 1 0 BDIP_ must be pulled up for 860 master mode BB BGACK BERR TEA RETRY _ DSACK1_ TA_ AT 0 3 TC 3 0 SDACK_ DACK_ IDMA DREQ_ IRQ 7 1 QINT_ RESETH_ Connects to PCI bus RST RESETI al i RST Reset Strategy for Host Bridging Applications _ QSpan User Manual 8091862 001 08 Reset Strategy for PCI RESETH_ RESETO_ Adapter Applications 1 RESET Fon DSACKO_ ENID i SDA _ SDA and ENID control the EEPROM AS port at reset TMODE 1 0 DS can be no connect 367 Appendix C Typical Applications C 2 1 C 2 1 1 368 Hardware Interface Clocking The QSpan II s QCLK input must be derived from the MPC860 s CLKOUT signal All of the AC timing waveforms for the QSpan II are based on this clock output It is recommended however to buffer the CLKOUT signal to the QSpan II with a low
136. 4 312b gt 1310 gt 1336 4 TS_ 7 313e lt 315 gt 315 3135 gt 315 gt 1e gt P gt Bes D 31 0 y lt 2 gt a gt 313g gt 43151 TAa 7 TEA TRETRY a Normal TEA p t3150 gt 44513 TRETRY_ b Retry gt t315n gt TEA_ RETRY c Bus Error QSpan II User Manual 335 8091862 001 08 Appendix B Timing Figure 46 Aligned Burst Write QSpan as MPC860 Master Ons 100ns 200ns 300ns 400ns _ 01 gt QCLK N N 311 gt t311 gt lt 1313c I 3154 BG_ t312a gt 310b gt 336b BB_ a VA WA gt 310a gt 336a A 31 0 gt t310c gt 1336 BURST_ m P d gt 10k gt 1336 BDIP_ gt 1310 gt 336e SIZ 1 0 gt 13106 336g TCI3 0 gt 310d gt 13364 R W_ 312b gt t310j gt 1336j TS_ s o t334 gt 1334 gt 1334 gt 1316 D 31 0 gt 313g gt 13151 TEA_ TRETRY a a Normal p gt 13150 gt iibi TRETRY p N b Retry 1315 6 gt 1313 TEA_ ES TRETRY c Bus Error 336 QSpan II User Manual 8091862_MA001_08 Appendix B Timing
137. 4 Reset Options 14 2 2 QBus Master and Slave Modes QSpan II has four Master and Slave modes that are determined by the BDIP_ and the SIZ 1 signals at reset The QBus can be in MC68360 QUICC MPC860 PowerQUICC or M68040 Master mode The QBus Slave Module is always capable of accepting MC68360 signals and either MPC860 or M68040 signals These reset options are listed in Table 48 Table 48 Reset Options for QBus Master and Slave Modes Reset sampling BDIP_ SIZ 1 Master Mode Slave Mode MC68360 MC68360 and M68040 MC68360 MC68360 and MPC860 Ls a These options are reset whenever the QSpan II is reset 14 2 3 EEPROM Loading If either ENID or SDA is sampled high at reset then the QSpan II will download register information from the EEPROM see Chapter 9 EEPROM Channel on page 123 14 2 4 PCI Register Access Option If PCI DIS is sampled high at reset the QSpan II will retry all PCI accesses until the PCI Access Disabled PCI DIS bit in MISC CTL2 is set to 0 by the QBus processor 14 2 5 PCI Bus Arbitration Option If PCI ARB EN is sampled high at reset the QSpan II s PCI bus arbiter is enabled and will function as the PCI bus arbiter for more information see Chapter 11 PCI Bus Arbiter on page 141 158 QSpan II User Manual 8091862 001 08 Chapter 15 Hardware Implementation Issues This chapter briefly describes hardware implementation issue for the QSpan II The following to
138. 4 Linked List Mode DMA 100 6 4 1 Initiating a Linked List Mode DMA Operation 102 6 4 2 Terminating a Linked List Mode DMA 104 Chapter 7 The Register 1 105 Overview he A kere iaa DERE ea hee ee ee OE E deb dient e 105 72 Register Access 2222 canes weg eae wa RI En DR ad 106 7 3 Register Access from the 107 7 4 Register Access from the 109 7 4 1 Examples of QBus Register Accesses 110 7 4 0 PCI Configuration Cycles Generated from the 110 7 4 3 Address Phase of PCI Configuration Cycles 111 7 4 3 1 Data Phase of PCI Configuration 112 7 4 4 Interrupt Acknowledge 112 7 5 Register Access Synchronization 113 7 6 Mailbox Registers ete bre ee eee 114 Chapter 8 The Interrupt Channel 5 4 5 222222222225925925529 52 115 S l OVERVIEW Lh ie cas 115
139. 436f TC 3 0 D gt t410c gt l t436c R W a t41Pb t410i t436i TS t415g k t413c D 31 0 t415k k t413e TEA a Normal gt e t415k gt t413e j p gt 15 gt t413f e TEA p b Retry t415m gt t413F TEA c Bus Error QSpan II User Manual 349 8091862_MA001_08 Appendix B Timing Figure 61 Single Write QSpan as M68040 Master Ons 100ns 200ns 300ns Roy od o3 deo Uh ape es te 46 d lt 01 QCLK gt 1411 BR_ I gt t413b gt etd15c BG_ 1412 gt 14106 14360 BB_ t410a f t436a A 31 0 T t410h t436h BURST TIP gt t410d gt t436d SIZ 1 0 D gt t410f gt t436f 3 0 2 gt t410c gt t436c R W_ L7 t41Pb t410i t436i X TS 1418 gt 1414 1416 D 31 0 gt 415 gt t413e TA Normal gt 41415 E 91413e TA amp gt 1415 14131 b Retry 15 14131 5 Bus Error 350 QSpan II User Manual 8091862 001 08 Appendix B Timing B 4 4 2 QBus Slave Cycles M68040 Figure 62 Single Read QSpan as M68040 Slave
140. 45 0 21 IOP TP 1 0 Outbound Post List Top Pointer Register Table 107 on page 246 0x220 IOP BP 10 Outbound Post List Bottom Pointer Register Table 108 on page 247 0x224 3FF Reserved IDMA DMA_CS IDMA DMA Control and Status Register IDMA DMA_PADD IDMA DMA_CNT Ox418 0x4FF Reserved 0x500 CON ADD 0x504 CON DATA 0x508 IACK GEN 0 50 0 5 Reserved INT_STAT INT_CTL2 0x610 0x6FF Reserved Table 109 on page 248 Table 110 on page 251 IDMA DMA PCI Address Register Table 111 on page 252 IDMA DMA Transfer Count Register DMA QBus Address Register Table 112 on page 253 Table 113 on page 254 DMA Control and Status Register Table 114 on page 257 DMA Command Packet Pointer Register Table 115 on page 258 Configuration Address Register Table 117 on page 260 Configuration Data Register Table 118 on page 261 IACK Cycle Generator Register Table 119 on page 262 Interrupt Status Register Table 120 on page 265 Interrupt Control Register Table 121 on page 268 Interrupt Direction Control Register Table 122 on page 271 Interrupt Control Register 2 QSpan II User Manual 199 8091862 001 08 Appendix A Registers Table 67 Register Map Continued Address Offset Hexidecimal Register Description See 0x700 MBOX0 Table 123 on page 272 Mailbox 0 Register 0x704 MBOXI Table 124 on page 273 Mailbox 1 Register 0x708 MBOX2 Table 125 on page
141. 47 on page 293 QSpan II User Manual 295 8091862 001 08 Appendix A Registers Table 150 1 0 Outbound Post List Interrupt Status Register Register Name I2O OPIS Register Offset 030 Function Reserved Reserved Reserved I20 OPIS Description Reset Name Type Reset By State Function OP ISR R W G RST Outbound Post List Interrupt Service Request 0 Outbound Post List FIFO is empty 1 Outbound Post List FIFO is not empty The value of the interrupt mask bit does not affect this bit 296 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 151 1 0 Outbound Post List Interrupt Mask Register Register Name I20_OPIM Register Offset 034 31 24 Reserved 23 16 Reserved 15 08 Reserved Reserved OP_IM Reserved 2 Description Reset Name Type Reset By State Function 1 OP_IM G_RST Outbound Post_List Interrupt Mask 0 Outbound Post_List Interrupt is enabled 1 Outbound Post_List Interrupt is masked QSpan II User Manual 297 8091862 001 08 Appendix A Registers Table 152 ILO Inbound Queue Register Register Name I2O INQ Register Offset 040 I20 INQ Description Reset Name Type Reset By State Function IN Q 31 0 R WP G RST IO Inbound Queue This register controls the access to the inbound queue The 32 bit value written into this register is written by QSpan II to the Inbound Post List FIFO which is located in Qbus memory at the address spe
142. 5 Signals ci i n e co eh aan 365 C 1 1 12 Address Multiplexing for 366 1 2 Software SSUeS 2 ss sepu OMEN Ie c away meen awed Rowe ives ney 366 1 3 68360 Slave Mode 366 MPCS60 Interface iseni cain delayed ote 367 CAL Hardware Interface os ei III 368 2 1 1 Cloeking is uir ete ea da eee Bie Melee bis 368 C2 L2 RESCUS Tye Ba Rte E Sod teak Fle Se OS eee ee RG iere 369 2 1 3 Memory Controllers ea ee ee 370 2 1 4 QBus Direct Connects 370 C25 Interr pts ged e pea d P pne gu d 371 2 1 6 PCI Signals ee ESE Sea eed Hes 371 C2 1 7 EEPROM Interface SI ok oie he a a 371 2 1 8 Reset Options Eee ee eis dabei des 371 C 2 1 9 Unused Inputs Requiring 372 C 2 1 10 No Connects 55295250 Ha RR net Re Sr Een SER Een Gg gran eS 372 emere teo cy ai ae 372 2 1 1 442 nc dee HE GUESS Gates 372 C 2 1 13 Address Multiplexing for DRAM
143. 5 PCI Configuration Base Address for Target 0 210 Table 76 PCI Address Lines Compared as a Function of Block 5 2 211 Table 77 PCI Configuration Base Address for Target 1 212 Table 78 PCI Address Lines Compared as a Function of Block 5 2 213 Table 79 PCI Configuration Subsystem ID Register 214 Table 80 PCI Configuration Expansion ROM Base Address 215 Table 81 Writable BA bits as a function of Block Size 216 Table 82 PCI Capabilities Pointer Register 217 Table 83 PCI Configuration Miscellaneous 1 218 Table 84 PCI Power Management Capabilities 219 Table 85 PCI Power Management Control and Status 220 Table 86 CompactPCI Hot Swap 221 Table 87 PCI Vital Product Data Register 222 Table 88 PCI Data 223 Table 89 PCI Bus Target Image 0 Control 224 Table 90 PCI Bus Target Image 0 Address Register
144. 5f CSREG_ gt 141304 415 BURST_ TIP_ E4196 211415 SIZ 1 0 k t419f 114151 TC 3 0 k t419d 6214151 R W_ gt 14150 gt 14199 TS_ ke t413c rlt415a D 31 0 je t409a t410e t436e TA TEA a Normal 1409 121141 Oe t436e TA y a sp t409b t4109 t4369 a b Retry 356 QSpan II User Manual 8091862 001 08 Appendix B Timing B 4 5 Interrupts and Resets Figure 68 Reset from PCI Interface RST related to RESETO_ Ons 100ns 200ns 300ns 400ns J d I tod I ol RST RESETO_ i Figure 69 Software Reset Ons 100ns 200ns 300ns 400ns I tod to I PCLK 1003 RESETO_ g Figure 70 INT Interrupt to QINT_ Interrupt Ons 50ns 200ns ons d d og Lo d d LR 132 X 29 52 4222 1005 1006 QINT_ va ff INT Figure 71 PERR Interrupt Ons 75ns e p Ld dd Ld dd L005 QINT wa 5 PERR QSpan II User Manual 357 8091862 001 08 Appendix B Timing Figure 72 SERR Interrupt Ons 25ns 50ns 75ns 100ns Hei TS cad Dy cr dl b ue c g X 005 Looe QINT_ f SERR Figure 73 QINT_ Interrupt to INT Interrupt 5 Us uj do
145. 6 t310h t336h TEA_ vA E TRETRY c Bus Error 338 QSpan II User Manual 8091862 001 08 Appendix B Timing Figure 49 Burst Read QSpan II as MPC860 Slave Ons 100ns 200ns 300ns 301 5 QcLK jp 4 77 Me o TM 40 75 4 gt t337a gt t315a 31 0 d y gt 315 k tB37b CSPCI_ V gt amp 13f gt 315i IMSEL X X gt 3134 gt 3 5 BURST_ m 1313b gt t315c BDIP_ N gt 337e gt fet315k SIZ 1 0 X k t337f 315m TC 3 0 4 6 gt 13374 111315 R W_ xcu gt t315p gt 1337 TS_ Ae cd t314 L 1314 t314 314 1316 D 31 0 Datal Data2 Dataa 1335a 310f gt 1336f TA_ ven TEA TRETRY_ QSpan II User Manual 339 8091862 001 08 Appendix B Timing Figure 50 Burst Write QSpan II as MPC860 Slave Ons 50ns 100ns 150ns 200ns 250ns I dd I dd d I to I to to 4 4301 5 aK _ __ 22 1337 amp amp 313a A 3 0 j gt kt315f k 9 87b CSPCI_ k gt t313f 0113151 IMSEL X X gt t313d 4 13152 BURST_ gt 131
146. 7 15 VDD 16 EXT 5 17 VSS 18 AD 1 19 VDD 20 SERR VSS AD 30 VDD V4 N C V5 V6 V7 V8 V9 EXT EXT GNT 4 R AD 22 AD 20 VSS V10 IRDY V11 STOP V12 AD 15 Chapter 17 Signals and DC Characteristics V13 AD 12 V14 AD 8 V15 N C V16 EXT REQ 2 Z V17 EXT 6 V18 AD 5 V19 AD 3 V20 AD 0 W1 AD 28 W2 AD 27 W3 AD 24 W4 CBE 3 W5 EXT GNT 2 amp Wo EXT_GNT 6 W7 VSS w8 AD 19 W9 AD 16 W10 FRAME W11 PCLK W12 CBE 1 W13 AD 13 W14 AD 10 W15 CBE 0 W16 W17 EXT_REQ 3 w18 AD 6 W19 VSS W20 AD 2 Y1 AD 26 Y2 AD 25 Y3 N C 4 Y5 EXT_GNT 3 Y6 N C Y7 AD 21 Y8 AD 18 Y9 CBE 2 Y10 TRDY Y11 DEVSEL Y12 PAR Y13 AD 14 Y14 AD 11 Y15 AD 9 Y16 IDSEL Y17 EXT_REQ 1 Y18 EXT_REQ 4 Y19 VDD Y20 AD 4 193 Chapter 17 Signals and DC Characteristics 194 QSpan II User Manual 8091862 001 08 Appendix A Registers A 1 This Appendix describes the QSpan II s registers The following topics are discussed e Register Map on page 197 e Registers on page 202 Overview The 4 Kbytes of QSpan II Control and Status Registers QCSRs promotes host system configuration and allows the user to control QSpan II operational characteristics The QCSRs are divided into two functional groups the PCI Configuration Registers and the QSpan II Dev
147. 79 Decoupling Capacitors 160 Delayed Transfer Configuration Cycles 34 PCI Target Channel 84 PCI Transaction Ordering 77 PWEN bit 74 single write 74 75 write 83 QBus Slave Channel 32 54 burst read 50 delayed write 53 PCI Transaction Ordering 51 QSpan II User Manual 8091862 001 08 Index single write 53 NUM field CON ADD Register 258 387 DEV 66 bit PCI CS Register 204 DEVSEL field PCI CS Register 203 DEVSEL 46 64 83 174 183 DID field PCI ID Register 202 DIR bit DMA CS Register 254 IDMA DMA CS Register 249 Direct Mode DMA Channel 96 discard timer 50 DMA Channel 33 Burst Cycles 98 description 95 Direct Mode 96 99 DMA Cycles on QBus 99 Linked List Mode 96 100 Registers 97 DMA Registers 97 DMA CPP Register 257 DMA CS Register 254 DMA_QADD Register 253 Document Conventions Bit Ordering 29 Document Status 30 Numeric Conventions 29 Signals 29 Symbols 30 Typograhic Conventions 29 DONE bit IDMA DMA CS Register 248 DONE 165 168 184 DONE DIR bit INT DIR Register 268 DONE EN bit INT CTL Register 265 IS bit INT STAT Register 262 DP D bit PCI CS Register 118 DPNE DIR bit INT DIR Register 269 DREQ_ 88 165 168 184 415 Index DS_ 165 184 DSACKO 165 184 DSACKI TA 165 169 172 184 DSI bit PCI_PMC Register 219 DSIZE bit PBTIO_CTL Register 224 DSIZE field DMA_CS Register 254 PBROM_CTL Register 232 389 PBTIO_CTL Register 384 Reg
148. 8 2 Hardware Triggered 1 116 8 QSpan II User Manual 8091862 001 08 Contents 8 3 Software Triggered 117 8 3 1 Interrupt Generation due to PCI Configuration Register Status Bits 120 8 4 Interrupt Acknowledge 1 121 8 5 Disabling PCI 2 121 Chapter 9 The EEPROM Channel 4 44254 ERRARE CR ERR 123 91 2252155 2 48 5 beaded LU howe ned 123 9 2 EEPROM Configuration and Plug and Play 125 9 3 EEPROM I C Protocol Uds Vue incite id un 125 9 4 Mapping of EEPROM Bits to QSpan II Registers 126 9 5 Programming the EEPROM from the QBus 129 9 5 1 Writing to the EEPROM 2 1 129 9 5 2 Reading from the 130 9 6 EEPROM ACCESS su ssa m ees a oa a ase ea sla aga dda eee eb en 130 9 7 Vital Product Data 2 2 130 977 1 Readme VPD Data sca oc hein deem cen tad edo 131 97 2 Wri
149. 8 LTIMER EUN oo o o o o ome o 9 PCI MISCO Description Reset Name Type Reset By State Function BISTC BIST Capable 0 Device not BIST capable SBIST N Start BIST 0 Device not BIST capable CCODE 3 0 N A Completion Code 0 Device not BIST capable MFUNCT N A Multifunction Device 0 QSpan II is not a multi function Device LAYOUT 6 0 eae Configuration Space Layout LTIMER 7 1 PCI_RST Latency Timer Number of PCI bus clocks before transaction is terminated CLINE 1 0 PCI RST CacheLine Size 00b treated as 01 01b 4 x 32 bit word 10b 8 x 32 bit word All other combinations written to this entry will return a value of zero The latency timer supports an increment of two PCI bus clocks The minimum value is eight PCI bus clocks The default value corresponds to eight PCI clock cycles CLINE 1 0 determines how the PCI Target module accepts burst write data see Acceptance of Burst Writes by the PCI Target Module on page 74 It also determines how the IDMA DMA Channel sinks data on and sources data from the PCI bus If CLINE 1 0 is set to 00 the QSpan II treats it as if it were set to O1 QSpan II User Manual 207 8091862 001 08 Appendix A Registers Table 73 PCI Configuration Base Address for Memory Register Register Name PCI_BSM Register Offset 010 PCI_BSM Description Reset Name Type Reset By State Function Base Address BA 31 12 R W PCI RST SPACE N A PCI Bus Ad
150. 862 001 08 Chapter 16 Signals 16 3 MC68360 Signals QUICC Continued IDMA Done indicates that the IDMA controller has completed the current sequence of IDMA operations and that the QSpan II should no longer use DREQ_ to request transactions Setup for DONE is to falling edge of QCLK IDMA Request request to the MC68360 to either transfer data to QSpan IL IFIFO PCI Write or remove data from I FIFO PCI Read It is asserted from the falling edge of QCLK in MC68360 mode DSACKO0 Rescinding tristate bidirectional Data and Size Acknowledge 0 in conjunction with DSACKI is driven by the addressed slave to acknowledge the completion of a data transfer on the QBus DSACKO has the same timing and characteristics as DSACK1_ TA_ see the following description DSACKI TA Rescinding tristate bidirectional Data and Size Acknowledge 1 Used in conjunction with DSACKO This signal is driven by the addressed slave to acknowledge the completion of a data transfer on the QBus QSpan II terminates all normal bus cycles by asserting both DSACK1_ TA_ and DSACKO indicating a 32 bit port width at all times The DSACKI TA output is driven high inactive after the release of AS_ until the next falling edge of the clock at which point it is tristated Rescinding tristate output Data Strobe used to indicate valid data on the data bus during write transactions and to request data during read transactions DS_ is driven by the Q
151. 9 P3 AD 26 P4 EXT_GNT 4 P5 AD 21 P6 AD 16 P7 FRAME P8 PCLK P9 AD 15 P10 AD 11 P11 AD 9 P12 AD 7 P13 EXT_REQ 4 P14 AD 6 P15 AD 3 P16 CSPCI_ RI EXT GNT 1 amp R2 AD 24 R3 AD 25 R4 EXT_GNT 2 R5 EXT GNT 5 amp R6 AD 19 R7 IRDY R8 DEVSEL R9 CBE 1 R10 AD 12 R11 CBE 0 R12 EXT REQ 2 R13 EXT_REQ 6 R14 N C R15 VH R16 N C T1 AD 23 T2 CBE 3 T3 EXT GNT 3 T4 EXT_GNT 6 T5 AD 18 T6 AD 17 T7 STOP T8 AD 14 T9 AD 13 T10 AD 8 T11 EXT REQ 1 T12 EXT REQ 5 T13 AD 5 T14 AD 4 T15 N C T16 AD 2 QSpan II User Manual 8091862 001 08 Table 66 Pinout of 27x27 mm Package Al VSS C13 A 14 A2 D 26 C14 A 11 A3 D 22 C15 TEST3 A4 DP 2 C16 A 10 A5 VDD C17 A 6 A 24 C18 D 8 AT A 22 C19 VDD A8 VSS C20 D 4 A9 A 17 D1 VSS 10 QCLK D2 VDD All D 17 D3 D 29 A12 VSS D4 VSS A13 DS_ DS D 24 14 A 13 D6 VDD A15 D7 D 21 A16 D8 VSS 17 N C D9 A 19 18 A 8 D10 A 16 A19 D 11 D11 VDD A20 D 9 D12 D 12 B1 D 28 D13 VSS B2 VDD D14 TEST2 B3 D 25 D15 VDD B4 PCI ARB EN D16 VDD B5 DP 1 D17 VSS B6 D 20 D18 D 5 B7 A 23 D19 VSS B8 A 20 D20 VDD B9 N C El A 27 B10 D 18 E2 VDD B11 D 15 E3 A 26 B12 D 14 E4 D 31 B13 A 15 E17 D 3 B14 A 12 E18 D 2 B15 TESTI E19 D 1 B16 A 9 E20 A 4 B17 A 7 F1 VSS B18 D 10
152. 91862 001 08 345 Appendix B Timing Figure 56 MPC860 IDMA Read Dual Address Ons 50ns 100ns 150ns 200ns d du Id d dg I deu al Ld dg 1 301 _ 31 0 _ gt 1353 lt gt 1359a CSPCI 13536 13590 TS_ 21360 lt gt 1361 4 t351 41352 D 31 0 gt 1354 gt 13590 SDACK_ 9 t310f 1336f t335a wa 31 0 is depicted for completeness It is not examined by the QSpan II during IDMA transfers however it can be used to drive CSPCI 346 QSpan II User Manual 8091862 001 08 Figure 57 MPC860 IDMA Write Dual Address Ons dd 50ns 1301 5 QCLK V 100ns 31 0 Appendix B Timing CSPCI_ t353a y LA 1359 13590 13536 TS_ gt t360 ke TC 3 0 1361 gt gt D 31 0 gt 1354 SDACK_ TA_ CAPE 1359 le t359b 131 39 t310f 1336f 1335a QSpan II does not issue retries or bus errors during dual address IDMA cycles B 4 4 QBus Interface M68040 Figure 58 QCLK Input Timing M68040 BCLK Ons 25ns Ld d d d d
153. 95 Vital Product Data PCI Local Bus Specification 2 2 compatible Vital Product Data Support on page 130 IO Messaging Unit IO Messaging Unit on page 133 Integrated PCI Bus Arbiter PCI Bus Arbiter on page 141 CompactPCI Hot Swap Friendly CompactPCI Hot Swap Friendly Support on page 145 PCI Bus Power Management PCI Bus Power Management Interface Specification 1 1 PCI Power compatible Management Event Support on page 153 Functional Enhancements Support for QBus Data Parity Generation and Detection QBus Data Parity Generation and Detection on page 37 Performance Improvement for QBus Posted Write Transfers Writes on page 48 Support for prefetching through the QBus Slave Channel Prefetched Reads on page 50 Option to Keep Bus Busy BB_ asserted on Back to Back Transfers on the QBus during Bursting on the PCI target cycles QBus on page 75 Option to use a different prefetch count in the PCI Target Channel based on the Target Prefetched Read Image Transactions on page 76 MPC860 UPM compliant burst reads and writes as processor bus master Burst Cycles on page 98 28 QSpan II User Manual 8091862 001 08 Chapter 1 General Information 1 2 Document Conventions 1 2 1 Signals Signals are either active high or active low Active low signals are defined as true asserted when they are at a logic low Similarly active high signals are defined as true at a logic hi
154. A field will be OXFFFF If the Block Size is 2 Gbytes BS 1111 then the BA field will be 0x8000 212 QSpan II User Manual 8091862 001 08 Appendix A Registers The PREF bit can be loaded from the EEPROM or written from the QBus The PREN bit in PBTI1_CTL register must be set to enable QSpan II to perform prefetched reads on the QBus Table 78 PCI Address Lines Compared as a Function of Block Size QSpan II User Manual 213 8091862 001 08 Appendix A Registers Table 79 PCI Configuration Subsystem ID Register Register Name PCI_SID Register Offset 02C Function SID SID PCI SID Description Reset Name Type Reset By State Function SID 15 0 R WQ E PCI RST See Subsystem ID Below Values for Subsystem ID are vendor specific SVID 15 0 R WQ E PCI RST See Subsystem Vendor ID Below Subsystem Vendor IDs are obtained from the PCI SIG and are used to identify the vendor of the add in board or subsystem The Subsystem ID and the Subsystem Vendor ID is loaded from an external serial EEPROM at the end of the PCI bus reset RST if the state of the SDA pin or ENID pin is latched as high during the reset If the state of the SDA pin or ENID pin is latched as low the reset state of the register will be all zeros Writes to the PCI SID register from the QBus will propagate to its contents except while the QSpan II is updating its contents from the EEPROM Writes to the PCI SID register from the PCI
155. ACK1_ TA_ prior to tristate HALT TRETRY Rescinding tristate bidirectional Transfer Retry used for generating retries As a MPC860 slave QSpan uses HALT TRETRY as stated in Table 12 on page 54 As a MPC860 master QSpan II uses HALT TRETRY as stated in Table 28 on page 81 As a slave HALT TRETRY has the same timing as DSACKI TA negates HALT TRETRY prior to tristate Image Select selects which QBus Slave Image to use when CSPCI is asserted The timing requirements for IMSEL are the same as those of the address bus when the QSpan II is a QBus slave QBus Clock All devices intended to interface with QBus side of the QSpan II must be synchronized to this clock The maximum QCLK frequency with a MPC860 is 50 MHz ew Open drain bidirectional QBus Interrupt as an output this open drain signal is asserted by the QSpan II when an interrupt event occurs As an input this signal can be mapped to the PCI INT output QBus Reset Input resets the QSpan II from the QBus side of the QSpan II Note that RESETI does not reset PCI configuration and status registers RESETO_ Open drain output QBus Reset Output asserted whenever the QSpan II s PCI RST input is asserted or the internal software reset bit is set Tristate bidirectional Read Write indicates the direction of the data transfer on the Data bus High indicates a read transaction low indicates a write It has the same timing as the Address bus As
156. Access from the PCI Bus on page 107 e Register Access from the QBus on page 109 e Register Access Synchronization on page 113 e Mailbox Registers on page 114 7 1 Overview QSpan II provides 4 Kbytes of QSpan II Control and Status Registers QCSRs These registers program PCI settings and the QSpan II s operating parameters see Figure 10 The QCSRs consist of two functional groups the PCI Configuration Registers and the QSpan II Device Specific Registers see Figure 11 on page 107 QCSR space is accessible from the PCI bus and the QBus Since QSpan II registers can be accessed from either the PCI bus or the QBus an internal arbitration occurs to indicate ownership The access mechanisms for the QCSRs including the arbitration protocol differ depending on whether the registers are accessed from the PCI bus or the QBus An internal pointer selects which bus can access the registers Default ownership of the Register Channel is granted to the QSpan II s PCI Target Module When ownership of the Register Channel is granted to the QBus Slave Module register accesses from the PCI bus are retried QSpan II User Manual 105 8091862 001 08 Chapter 7 The Register Channel Figure 10 Register Channel Functional Diagram QBus Interface Interface PCI Master Module QBus Slave Module PCI Bus QBus PCI Target Module 7 2 Register Access Fairness QSpan II can be configured to make register access fai
157. Arbitration Level for Qspan II 0 Low priority 1 High priority QSpan II s PCI Bus Arbiter 0 Disabled 1 Enabled PCI Bus Parking Scheme 0 Last Master 1 Select Master based on BM_PARK Select Master for PCI Bus Parking 283 Appendix A Registers QSpan II s internal PCI Bus arbiter is enabled by a power up option If the PCI ARB EN pin is sampled high at the negation of Reset the QSpan II arbiter is enabled When disabled an external arbiter is used and REQ GNT are used by the QSpan II to arbitrate for access to the PCI Bus If the internal arbiter is used the REQ GNT lines can be used by an external Bus master to arbitrate for the PCI Bus Table 132 Parked PCI Master PARK 2 0 Parked PCI Master External Pins EXT_REQ 1 EXT_GNT 1 EXT_REQ 2 EXT_GNT 2 EXT_REQ 3 EXT_GNT 3 EXT_REQ 5 EXT_GNT 5 EXT_REQ 6 EXT_GNT 6 REQ EXT_GNT 284 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 133 QBus Slave Image 0 Control Register Register Name QBSIO_CTL Register Offset F00 31 24 PWEN Reserved 23 16 PREN Reserved 15 08 Reserved 07 00 Reserved QBSIO CTL Description Reset Name Type Reset By State Function PWEN R W E PCI RST See Posted Write Enable Below 0 Disable 1 Enable PAS R W E PCI_RST See PCI Bus Address Space Below 0 PCI Bus Memory Space 1 PCI Bus I O Space PREN R W PCI_RST See Prefetch Read Enable Below 0 Disa
158. BB QBus PCI Target Images can be enabled or disabled by using the image enable bit Disabling both PCI Target Images disables the PCI Target Channel For more information about register settings that affect the PCI Target Channel s operation see the Miscellaneous Control registers MISC CTL see Table 127 on page 276 and MISC CTL2 see Table 130 on page 280 A PCI Target Image occupies a range of addresses within PCI Memory or I O space The PCI Address Space bit determines whether the Target Image lies in PCI Memory or I O space The range of addresses is specified by the base address field and the block size field Up to 2 Gbytes of PCI memory per image can reside on the QBus QSpan II User Manual 63 8091862 001 08 Chapter 4 The PCI Target Channel 4 4 2 64 There are constraints on the possible values of the block size and the base address The block size must be one of the 16 block sizes listed in Table 18 on page 66 The base address must be aligned to a combination of the upper address lines between AD31 and AD 16 The base address must be a multiple of the block size For example 128 Mbyte image must be aligned to a 128 Mbyte boundary Address decoding is performed by decoding the most significant address lines as a function of the block size For a 128 Mbyte PCI Target Image the PCI Target Module only needs to decode the top five PCI address lines to know whether this image has been accessed For a 64 Kb
159. BE 3 0 the number of 1s summed across these lines and PAR equal an even number PCLK Input in PCI Clock input for PCI interface used to generate fixed timing parameters PCLK can operate up to 33MHz PERR Bidirectional s t s Parity Error reports parity errors during all PCI transactions except a special cycle QSpan II asserts PERR within two clocks of receiving a parity error on incoming data and holds PERR for at least one clock for each errored data phase REQ Bidirectional t s Bus Request used by the QSpan to indicate that it requires the use of the PCI bus this is an output when the QSpan II uses an external arbiter REQ is also used by an external device to indicate to the QSpan II PCI bus arbiter that this device wants use of the PCI bus this signal is an input when the QSpan II PCI bus arbiter is used PCI Reset Asynchronous Reset that is used to bring PCI specific registers state machines and signals to a consistent state System Error reports address parity errors during all transactions QSpan II asserts SERR within two clocks of receiving a parity error on incoming address and holds SERR for at least one clock for each errored data phase QSpan II User Manual 175 8091862 001 08 Chapter 16 Signals 16 6 PCI Bus Signals Continued Stop used by the QSpan II as PCI target when it wishes to signal the PCI master to stop the current transaction As PCI master the QSpan II terminates
160. Bus Address for DMA transfers QBus QBus Address for DMA transfers for DMA transfers The Q ADDR 31 2 field must be programmed with the absolute QBus address for the DMA transaction This address is aligned to a 4 byte boundary A DMA transfer wraps around at an A24 boundary If a DMA transfer is required to cross an A24 boundary it must be programmed as two separate transactions This field is not incremented by the QSpan II during a transfer progress of the DMA transfer on the PCI bus can be monitored by reading the IDMA DMA_CNT register see Table 111 on page 252 This register can be programmed from either bus or is programmed by the DMA controller when it loads a command packet from QBus or PCI memory QSpan II User Manual 253 8091862 001 08 Appendix A Registers Table 113 DMA Control and Status Register Register Name DMA_CS Register Offset 410 31 24 23 16 IWM 15 08 BURST_4 BRSTEN 07 00 STOP STOP_ STAT DMA CS Description id DSIZE 1 0 B 254 Reset State Function Reserved DSIZE INVEND Q OFF MDBS CP_LOC Function QBus Transaction Code for DMA transfers User Defined DMA Direction 0 Transfer from PCI Bus to QBus 1 Transfer from QBus to PCI bus read only copy of DIR bit in IDMA DMA_CS QBus Destination Port Size 00 32 bit 01 8 bit 10 16 bit 11 reserved Invert Endian ness from QB_BOC Setting in MISC CTL 0 Use BCC setting 1 Invert
161. Bus Expansion ROM Control Register Register Name PBROM Register Offset 13C Function PBROM_CTL Description Reset Name Type Reset By State Function DSIZE 1 0 See PCI_RST See below QBus Destination Port Size Below 00b 32 bit 016 8 bit 10b 16 bit 11b reserved BS 2 0 See PCI RST See below Block Size 64 Kbyte 2P5 Below TC 3 0 See PCI RST See below QBus Transaction Code Below User Defined TA 31 16 See PCI RST See below Translation Address Below See below The PCI Bus Expansion ROM Control Register is loaded from an external serial EEPROM at the conclusion of the PCI bus reset if the state of the SDA I O pin or ENID is latched as high during the reset and bit 7 of byte 5 of the EEPROM is a 1 see Mapping of EEPROM Bits to QSpan II Registers on page 126 Otherwise the reset state of the register will be zero and the register will be write disabled The PCI Expansion ROM Base Address register specifies the address line values that are compared during the address decoding The number of address lines that are compared is based upon the value of Block Size value in the PCI Expansion ROM Control register The Translation Address field specifies the values of the address lines that are substituted when generating the address for the QBus If no translation is to occur the Translation Address field is programmed with the same value as that of the PCI Configuration Expansion R
162. Bus Interface M68040 347 B 4 4 1 QBus Master Cycles 68040 348 4 4 2 QBus Slave Cycles 68040 351 B 4 5 Interrupts and Resets 357 B 4 6 Reset Options 20 cea ced esas sea diee RN ERR ER EUR ehe ee 359 Appendix C Typical Applications 361 MC68360 Interface nico ped bis 361 11 Hardware Interface cce eo etae cit to ewe Reo n 361 CA Ll Clocking uoce eet eR eR REED ERE ter 361 CART 2 hehe dived EEG p RR EOS cea 362 QSpan II User Manual 11 8091862_MA001_08 Contents 2 1 1 3 Memory 2 22 22 2 92 2 06 Rx era ede e 363 CAL OBus Direct CONC Cts ole ace Adin eie eR ERR RR 364 CLES Intetr pts so aa emi o erem SUR S Wee ee dee ane Wed 364 CT 16 PGLSignalss wceinble4 eed Laces Bs DOE See Sl USSEPU mee 364 1 1 7 EEPROM Interface iet rune et ad eed hoe sd as 364 1 1 8 Reset Options be Se a es in ee Nese 365 C 1 1 9 Unused Inputs Requiring 365 No Pike SERE SES 36
163. CI Configuration Base Address for Target 0 PCI BSTO register see Table 75 on page 210 e PCI Configuration Base Address for Target 0 PCI_BST1 register see Table 77 on page 212 Table 44 Destination of EEPROM Bits Read PCI SID 31 30 29 28 27 26 25 24 SID SID SID SID SID SID SID SID PCI SID 23 22 21 20 19 18 17 16 1 SID SID SID SID SID SID SID SID PCI SID 15 14 13 12 11 10 9 8 2 SVID SVID SVID SVID SVID SVID SVID SVID PCI SID 7 6 5 4 3 2 1 0 3 SVID SVID SVID SVID SVID SVID SVID SVID Enables PCI_ PBROM_CTL BSROM 22 21 20 19 18 17 16 BS BS BS TC TC TC TC PBROM_CTL 15 14 13 12 11 10 9 8 TA TA TA TA TA TA TA TA PBROM CTL 7 6 5 4 3 2 1 0 PBROM_CTL Enables PBTIO_CTL PCI BSTO 25 24 27 26 25 24 6 7 DSIZE DSIZE BS BS BS BS PAS Enables QBSIO PCI BSTI 27 26 25 24 6 31 PWEN 24 BS BS BS BS PAS PAS QBSIO AT 31 30 29 28 27 26 25 24 TA TA TA TA TA TA TA TA QSpan II User Manual 127 8091862 001 08 Chapter 9 The EEPROM Channel Table 44 Destination of EEPROM Bits Read Continued Function QBSIO_AT 23 22 21 20 19 18 17
164. CI MISCI Register 218 MISC Register 37 276 MSTSLYV field 37 59 158 QB BOC bit 46 68 93 S BB bit 79 80 5 BG bit 79 80 SW RST bit 156 MISC register bit 63 MISC CTL2 Register 280 MS bit PCI CS Register 205 383 389 MSTSLYV field MISC Register 277 380 MWI EN bit PCI CS Register 205 Mx PRI bit PARB CTL Register 283 382 N NOTO bit MISC CTL2 Register 381 NXT IP field CPCI HS Register 221 PCI Register 219 PCI VPD Register 222 O OF_BP field IOF_BP Register 245 OF_E bit I20_CS Register 238 OF F bit CS Register 238 OF TP field IOF TP Register 244 OFE DIR bit INT DIR Register 269 OFE EN bit INT CTL Register 267 OFE 5 bit INT STAT Register 263 OFF DIR bit INT DIR Register 270 OFF EN bit INT CTL Register 267 OFF 5 bit INT STAT Register 264 420 OP BP field IOP BP Register 247 OP E bit CS Register 238 OP F bit CS Register 239 OP IM bit I20 OPIM Register 297 OP ISR bit 2 OPIS Register 296 OP TP field IOP TP Register 246 Open Drain Output 184 185 OPNE bit INT STAT Register 263 OPNE EN bit INT CTL Register 266 Ordering Information 407 OUT Q field I20 OUTQ Register 299 P P2P_BSE field PCI_PMCS Register 220 PAERR field PB_AERR Register 236 385 PAR 52 77 175 184 PARB_CTL Register 283 Parity PCI Master Module address parity 52 data parity 52 PCI Target Module address parity 64 77 data parity 77 register
165. CI master has attempted a burst read and the QBus Master Module has completed the single transfer e A 128 byte boundary is reached e Px FIFO fills during a burst write e A burst transfer requiring non linear burst address incrementing is attempted e TRDYf is negated for eight PCLKs during a PCI burst read This is optional for more information see PCI Target Prefetch Disconnect on page 82 PCI Target Prefetch Disconnect QSpan II can be programmed to perform a Target Disconnect while completing prefetch reads in the PCI Target Channel To enable this feature set the PCI Target Channel Prefetch Disconnect bit in the MISC CTL2 register see Table 130 on page 280 A disconnect is issued if the TRDY signal is negated for eight PCI clock cycles during a target prefetch read transaction A new prefetch is started on the QBus when the master continues the disconnected read QSpan II User Manual 8091862 001 08 4 8 5 2 4 8 5 3 Chapter 4 The PCI Target Channel Target Retry During a Target Retry a termination is requested by the target because it cannot currently process the transaction This termination is communicated by the target asserting STOP while not asserting TRDY Target Retry means that the transaction is terminated after the address phase without any data transfer The PCI Target Module retries accesses under the following conditions e Anexternal PCI bus master attempts to post a s
166. DIR _ G_RST PCI Error Log Interrupt Direction 0 Map PCT error log interrupt to the QBus 1 Map interrupt to the PCI bus QBus Error Log Interrupt Direction 0 Map QBus error log interrupt to the QBus 1 Map interrupt to the PCI bus PCI Master Data Parity Detected Interrupt Direction 0 Map Master Data Parity Detected interrupt to the QBus 1 Map interrupt to the PCI bus PCI_CS Register status bit set Interrupt Direction QEL_DIR MDPED_DIR G_RST G_RST el 0 Map PCI CS Register status bit set interrupt to the QBus 1 Map interrupt to the PCI bus G_RST IDMA DMA QBus Error Interrupt Direction 0 Map IDMA DMA QBus error interrupt to the QBus 1 Map interrupt to the PCI bus IQE_DIR IPE_DIR IRST_DIR DONE_DIR INT_DIR PERR_DIR G_RST IDMA DMA PCI Error Interrupt Direction 0 Map IDMA DMA PCI error interrupt to the QBus G_RST 1 Map interrupt to the PCI bus G_RST G_RST PCI Interrupt mapping Direction Always mapped to QBus G_RST PCI Parity Error mapping Direction Always mapped to the QBus 268 QSpan II User Manual 8091862 001 08 IDMA DMA Reset Interrupt Direction 0 Map IDMA DMA reset interrupt to the QBus 1 Map interrupt to the PCI bus IDMA DMA Done Interrupt Direction 0 Map IDMA done interrupt to the QBus 1 Map IDMA done interrupt to the PCI bus EERE EERE Appendix A Registers INT_DIR Description Continued Reset Name Type Reset By State Function SERR_DIR G_RST PC
167. Data Bus provides the data information for the QSpan II s inputs and outputs on the M68040 bus DSACKI TA _ Rescinding tristate bidirectional Transaction Acknowledge asserted by the addressed slave to acknowledge a bus transfer As a slave the QSpan II terminates all normal bus cycles by asserting DSACKI TA QSpan negates DSACK1_ TA_ prior to tristate Target retries are indicated by the simultaneous assertion of DSACKI and BERR TEA Image Select selects which QBus Slave Image to use when CSPCI is asserted The timing requirements for IMSEL are the same as those of the address bus when the QSpan II is a M68040 bus slave QBus Clock All devices intended to interface with QBus side of the QSpan II must be synchronized to this clock QCLK can operate up to 40MHz QINT Open drain bidirectional QBus Interrupt as an output this open drain signal is asserted by the QSpan II when an interrupt event occurs As an input this signal can be mapped to the PCI INT output QBus Reset Input resets the QSpan from the QBus side of the QSpan II RESETI does not reset PCI configuration and status registers RESETO Open drain output QBus Reset Output asserted whenever the QSpan II s PCI RST input is asserted or the internal software reset bit is set 172 QSpan II User Manual 8091862 001 08 Chapter 16 Signals 16 5 M68040 Signals Continued Tristate bidirectional Read Write indicates the direction of the da
168. EIM are defined in CPCI_HS register HS HEALTHY H gt Back end powered down HS HEALTHY L gt Back end powered up 150 QSpan II User Manual 8091862 001 08 Figure 23 Hot Swap Card Extraction Chapter 12 CompactPCI Hot Swap Friendly Support Ejector SW Clear SW Set Withdrawal Short Med Long Unlatched EXT bit LOO bit Starts disengage disengage disengage Early Power Back End Power BD SEL 4 Pull d up HEALTHY 1 x PCIRST Grom J1 pre charge PCI Clock Clock ng pre charge PCI Signals Engaged tracking bus pre charge Ejector State Closed Open ENUM A pre charge LED LED oft LED on by SW LED on by HW INS bit 2 Cleared Armed EXT bit Cleared Armed Set Cleared Unarmed Software Connection Hardware Connection Physical Connection lt 4 1 This graphic is from the CompactPCI Hot Swap Specification QSpan II User Manual 8091862_MA001_08 151 Chapter 12 CompactPCI Hot Swap Friendly Support 152 QSpan II User Manual 8091862 001 08 Chapter 13 Power Management Event Support This chapter explains PCI Power Management Support for the QSpan II It focusses on the Power Management Support output signal PME 13 1 Overview QSpan II provides a PCI Power Management interface that is compliant with PCI Bus Power Management Interface Specification 1 1 This interface enables the operati
169. F CC oda tss t ugue us il 4 1201 QCLK ea gt 13596 A 31 0 gt 353a gt t359a CSPCI_ kt t353b gt gt 359g TS_ X t351 t352 D 31 0 NB gt t354 11359 SDACK_ k 1355a t359d egy TEA_ TRETRY_ a Normal y TEA_ gt 3591 1356 TRETRY b Retry k t355b 9 t359e TEA TRETRY c Bus Error A 31 0 is depicted for completeness It is not examined by the QSpan II during IDMA transfer however it can be used to drive CSPCI 344 QSpan II User Manual 8091862 001 08 Figure 55 MPC860 IDMA Write Single Address Appendix B Timing Ons 50ns 100ns 150ns 200ns Pe ake a db o cde dS we HS odo ocb 1301 eC Ie X 31 0 _ gt 1353a gt 1359 CSPCI_ k 353b 4 359g TS_ gt 13596 21313 D 31 0 C 1359 t354 SDACK_ gt 3594 k t355a gt L_ TEA_ TRETRY_ a Normal y TEA_ gt 359 k t356 TRETRY b Retry gt 1359 13550 TEA S Bus Error A 31 0 is depicted for completeness It is not examined by the QSpan II during IDMA transfers however it can be used to drive CSPCI QSpan II User Manual 80
170. F2 A 28 B19 D 7 F3 N C B20 D 6 F4 VDD D 30 F17 VDD C2 D 27 F18 D 0 C3 N C 19 A 3 C4 D 23 F20 A 2 C5 DP 3 G1 N C C6 DP 0 G2 A 29 C7 A 25 G3 R W_ C8 A 21 G4 N C C9 A 18 G17 A 5 C10 D 19 G18 VDD C11 D 16 G19 A 1 C12 D 13 G20 0 QSpan User Manual 8091862_MA001_08 DSACK1_ TA_ H2 A 31 H3 A 30 H4 VSS H17 VSS H18 N C H19 VSS H20 N C J1 SDA J2 SIZ 0 J3 SIZ 1 J4 DSACKO_ J17 DREQ_ J18 ENID J19 QINT_ J20 TCK K1 ENUM K2 N C K3 SCL K4 VDD K17 DONE_ K18 TRST_ K19 DACK_ SDACK_ K20 TMS L1 IMSEL L2 HS_LED L3 TMODE 1 L4 HS_SWITCH L17 VDD L18 TDI L19 N C L20 VSS 0 2 PME M3 RESETI_ M4 PCI DIS M17 BDIP_ M18 BG_ M19 TDO M20 BM_EN FIFO_RDY 1 RESETO_ N2 HS_HEALTHY_ N3 BURST_ TIP_ N4 VSS N17 VSS N18 TC 3 N19 BERR_ TEA_ N20 AS_ P1 N C P2 TS_ P3 VSS P4 RST P P P 17 N C 18 TC 0 19 TC 1 P20 TC 2 BB BGACK R2 BR R3 VH R4 VDD R 17 VDD R18 N C R19 N C R20 CSPCI HALT TRETRY _ T2 VDD T3 REQ T4 AD 31 T T T 17 VSS 18 INT 19 T20 N C U U U U U U U U U U U U U U U U U U U U VI V2 V3 1 VSS 2 GNT 3 AD 29 4 VSS 5 AD 23 6 VDD 7 EXT GNT 5 amp 8 VSS 9 AD 17 10 VDD 11 PERR 12 VDD 13 VSS 14 AD
171. FF bit DMA CS Register 255 QAERR field QB AERR Register 294 385 QB AERR Register 204 QAERR field 84 BOC bit MISC Register 260 261 276 380 QB DERR Register 295 QDERR field 84 QB ERRCS Register 293 EN bit 84 ES bit 84 SIZ ERR field 84 TC ERR field 84 QBSIO AT Register 287 QBSIO CTL Register 285 QBSI1_AT Register 291 QBSI1_CTL Register 289 QBSIx_AT Register BS field 40 42 44 61 128 EN bit 40 42 TA field 40 42 127 QBSIx_CTL Register PAS bit 40 45 46 49 127 PWEN bit 40 48 49 127 QBus Bursting on the QBus 75 QBus defined 31 QBus Data Parity 37 60 QBus Master Mode 59 QBus Master Module 59 QBus Slave Image 39 40 enable address translation 40 PCI address space 40 posted write enabling 40 registers 201 QSpan II User Manual 8091862 001 08 Index QBus Slave Mode 37 59 QBus Slave Module 37 QCLK 166 169 173 185 QDERR field QB_DERR Register 295 385 QDPE DIR bit INT DIR Register 269 QDPE EN bit INT CTL Register 266 QDPE S bit INT STAT Register 263 QEL DIR bit INT DIR Register 268 QEL EN bit INT CTL Register 265 QEL IS bit INT STAT Register 262 QIBA field CS Register 238 IIF BP Register 241 IIF TP Register 240 IIP BP Register 243 IIP TP Register 242 IOF BP Register 245 IOF TP Register 244 IOP BP Register 247 IOP TP Register 246 QINT 117 166 169 173 185 364 376 QINT DIR bit INT DIR Register 269 QINT EN bit INT CTL Register 266 QINT IS bit INT STAT Regi
172. FO MPC860 un Posted Writes Slavo Module 236 Bytes Module i Qr FIFO i Prefetched Reads 32 Bytes l PCI Bus QBus QBus Slave Channel Architecture Figure 3 shows the QBus Slave Channel in relation to the QBus and the PCI bus The QBus is shown with an MPC860 processor the PCI bus is shown with a single PCI device The arrows represent data flow The QBus Slave Channel has the following components e QBus Slave Module Qx FIFO Qr FIFO e Master Module The QBus Slave Module and PCI Master Module are shared between the QBus Slave Channel and the IDMA DMA Channel These components are discussed in the following sections QSpan II User Manual 8091862 001 08 3 2 1 3 2 1 1 Chapter 3 The QBus Slave Channel QBus Slave Module The QBus Slave Module is a non multiplexed 32 bit address 32 bit data interface The QBus Slave Module accepts MC68360 cycles and either MPC860 or M68040 cycles The QBus Slave Module s mode is set by the SIZ 1 signal at reset This reset option is summarized in Table 2 for more information see Chapter 14 Reset Options on page 155 The MSTSLV 1 0 field in the Miscellaneous and Control Status register MISC_CTL indicates the slave and master mode of the QBus see Table 127 on page 276 The connections required for interfacing the QSpan II to an MC68360 MPC860 and or M68040 are described in Appendix C Typical Applications on page 361 Table 2 Reset Op
173. HE TRUTH ACCURACY OR COMPLETENESS OF ANY STATEMENTS INFORMATION OR MATERIALS CONCERNING CODE EXAMPLES CONTAINED IN ANY IDT PUBLICATION OR PUBLIC DISCLOSURE OR THAT IS CONTAINED ON ANY IDT INTERNET SITE IN NO EVENT WILL IDT BE LIABLE FOR ANY DIRECT CONSEQUENTIAL INCIDENTAL INDIRECT PUNITIVE OR SPECIAL DAMAGES HOWEVER THEY MAY ARISE AND EVEN IF IDT HAS BEEN PREVIOUSLY ADVISED ABOUT THE POSSIBILITY OF SUCH DAMAGES The code examples also may be subject to United States export control laws and may be subject to the export or import laws of other countries and it is your responsibility to comply with any applicable laws or regulations LIFE SUPPORT POLICY Integrated Device Technology s products not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user 2 A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectivene
174. I FIFO Watermark 89 IIF BP Register 241 IIF TP Register 240 IIP BP Register 243 Register 242 IMODE bit IDMA DMA CS Register 249 IMSEL 165 169 172 184 376 IN Q field I20 INQ Register 298 INS bit CPCI HS Register 221 INT CTL Register 265 DONE EN bit 91 92 118 DPD EN bit 52 118 IPE EN bit 92 118 IQE EN bit 91 92 118 IRST EN bit 91 92 118 PEL EN bit 56 QEL EN bit 84 118 SIO bit 120 SII bit 120 INT CTL2 Register 271 INT DIR bit INT DIR Register 268 INT DIR Register 268 DPD DIR bit 118 IPE DIR bit 92 118 IQE DIR bit 92 118 IRST DIR bit 92 118 PEL DIR bit 56 QEL DIR bit 84 118 510 DIR bit 120 5 DIR bit 120 INT EN bit 417 Index INT_CTL Register 266 INT_IS bit INT_STAT Register 262 INT_LINE field PCI MISCI Register 218 INT_PIN field PCI MISCI Register 218 INT_STAT Register 262 DONE_IS bit 92 118 DPD_IS bit 118 IPE_IS bit 92 118 IQE_IS bit 92 118 IRST_IS bit 92 118 QEL_IS bit 118 SIO_IS bit 120 SII IS bit 120 INT 117 175 184 Interrupt Acknowledge Cycle 45 121 Interrupt Channel 34 address parity 77 description 115 IDMA Channel 91 interrupt enabling 118 interrupt mapping 118 interrupt sources 118 PCI Target Module posted writes 84 QBus slave module posted writes 56 INVEND bit DMA_CS Register 254 PBTIO_CTL Register 224 384 Register 228 384 IOF BP Register 245 Register 244 Register 247 Register 246 IOS bit PCI_CS Re
175. I RST See Enable Address Translation Below 0 Disable 1 Enable QSpan II User Manual 287 8091862 001 08 Appendix A Registers The Translation Address specifies the values of the address lines substituted when generating the address for the transaction on the PCI bus Address translation is enabled by setting the EN bit Block Size is used to determine which address lines are translated see Table 139 and Mapping of EEPROM Bits to QSpan II Registers on page 126 Otherwise their reset state is 0 Table 139 Address Lines Translated as a Function of Block Size 288 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 140 QBus Slave Image 1 Control Register Register Name QBSI1_CTL Register Offset F10 31 24 PWEN Reserved 23 16 PREN Reserved 15 08 Reserved 07 00 Reserved QBSI1_CTL Description Reset Name Type Reset By State Function PWEN R W G_RST Posted Write Enable 0 Disable 1 Enable PAS R W G_RST PCI Bus Address Space 0 PCI Bus Memory Space 1 PCI Bus I O Space PREN R W G_RST Prefetch Read Enable 0 Disable 1 Enable This slave image definition is used when QSpan II is selected by the assertion of CSPCI_ and IMSEL Image Select is 1 It indicates among other things that the QSpan II does not burst to PCI I O space and responds to such attempts by generating a bus error on the QBus Single posted writes to I O space are treated as delayed writes see
176. I SERR mapping Direction Always mapped to QBus QINT_DIR G_RST 1 QBus Interrupt mapping Direction Always mapped to PCI Bus MB3_DIR R W G_RST MailBox3 Interrupt Direction 0 Map MailBox3 interrupt to the QBus 1 Map MailBox3 interrupt to the PCI bus MailBox2 Interrupt Direction 0 Map MailBox2 interrupt to the QBus 1 Map MailBox2 interrupt to the PCI bus MailBox1 Interrupt Direction MB2 DIR RST DIR RST 0 Map MailBox1 interrupt to the QBus 1 Map MailBox1 interrupt to the PCI bus MBO DIR G RST MailBox0 Interrupt Direction 0 Map MailBox0 interrupt to the QBus 1 Map MailBoxO interrupt to the PCI bus G_RST QBus Data Parity Error Interrupt Direction 0 Map QBus Data Parity Error interrupt to the QBus 1 Map interrupt to the PCI bus G_RST Power State Changed Interrupt Direction Always mapped to QBus G_RST 1 Outbound Post_List Not Empty Interrupt Direction Always mapped to PCI Bus G_RST QDPE_DIR PSC_DIR OPNE_DIR IPN_DIR IFE_DIR R W G_RST Inbound Post_List New Entry Interrupt Direction Always mapped to QBus Inbound Free_List Empty Interrupt Direction 0 Map Inbound Free_List Empty interrupt to QBus 1 Map interrupt to the PCI bus OFE_DIR Outbound Free_List Empty Interrupt Direction 0 Map Outbound Free_List Empty interrupt to QBus 1 Map interrupt to the PCI bus IPF_DIR G_RST OFF_DIR G_RST QSpan II User Manual 269 8091862 001 08 Inbound Post_List Full Interrupt Directi
177. I tri states the HS_LED signal low when the LED is supposed to be turned off during normal operation QSpan II User Manual 8091862 001 08 12 3 Chapter 12 CompactPCI Hot Swap Friendly Support QSpan II also monitors the board healthy signal HEALTHY in the Hot Swap specification This connects to QSpan II s input signal H5 HEALTHY QSpan internally OR s the H8 HEALTHY and PCI Reset RST to generate an internal reset When H8 HEALTHY is high the QSpan is in reset and all outputs are tri stated except for 5 LED QSpan II will drive out RESETO_ low due to a PCI Reset RST low if H5 HEALTHY is low indicating that the back end is powered up QSpan II samples the power up option pins BDIP PCI DIS etc on HS HEALTHY going low as well as going high or RESETI going high CompactPCI Hot Swap Card Insertion When a CompactPCI add in card containing QSpan II is inserted into a powered on system power and ground are first supplied to the QSpan II The remaining subsystem components do not have power From the long pins the HEALTH Y signal is generated and applied to QSpan HS HEALTHY This causes QSpan to generate an internal reset to drive HS LED low and to tri state all other outputs When the board is fully inserted and power is supplied to the rest of the subsystem or back end the H8 HEALTHY can be asserted low causing the QSpan to come out of reset If the PCI Reset RST is
178. II User Manual 291 8091862 001 08 Appendix A Registers 292 Table 146 QBus Address Lines Compared as a function of Block Size Block Size 64 Kbytes 128 Kbytes 256 Kbytes 512 Kbytes 1 Mbyte 2 Mbytes 4 Mbytes 8 Mbytes 16 Mbytes 32 Mbytes 64 Mbytes 128 Mbytes 256 Mbytes 512 Mbytes 1 Gbyte 2 Gbytes QSpan II User Manual 8091862 001 08 Appendix A Registers Table 147 QBus Error Log Control and Status Register Register Name QB_ERRCS Register Offset F80 23 16 Reserved 15 08 Reserved Enable QBus Error Log 0 Disable error logging 1 Enable error logging QB_ERRCS Description QBus Error Status 0 No error currently logged 1 Error currently logged TC ERR 3 0 QBus Transaction Code Error Log SIZ ERR 1 0 QBus SIZ Field Error Log The QBus Master Module logs errors when a posted write transaction from the Px FIFO results in a bus error The assertion of the ES bit can be mapped to the QSpan II s interrupt pins by programming the Interrupt Control Register and the Interrupt Direction Register see Table 120 on page 265 and Table 121 on page 268 respectively The mapping of interrupts occurs if the EN bit in the QBus Error Log Control and Status Register is set To disable the QBus Error Logging after it is enabled the ES bit must not be set If the ES bit is set it can be cleared by writing a 1 at the same time as a 0 is written to the EN bit The TC ERR and SIZ ERR fields contain va
179. II can generate PCI Configuration cycles through a QBus master accessing QSpan II registers In order to generate a PCI Configuration read or write cycle two registers must be accessed First the Configuration Address register must be programmed Second a write to the CON_DATA register is performed which causes the PCI configuration write cycle to occur on the bus In order to generate a PCI Configuration read the QBus master should perform a read of the CON_DATA Register see PCI Configuration Cycles Generated from the QBus on page 110 In order to generate a PCI IACK Cycle the QBus processor should perform a read of the IACK Cycle Generator Register see GEN on page 261 Table 170 PCI Configuration and IACK Cycle Programming Summary CON ADD See the PCI 2 2 Specification and the QSpan II register descriptions TYPE Determines whether the Configuration cycle generated is Type 0 or Type 1 CON DATA CDATA 31 0 When this register is written to its contents are driven onto the PCI data bus during a Configuration write cycle The QBus master is retried until the write completes on the PCI bus for example writes are delayed transactions A read of this register initiates a PCI Configuration read cycle The value returned from the PCI target is stored temporarily in this register while waiting for the QBus master to perform an additional read to obtain the data for example reads are also implemented as delayed transactions
180. IMSEL input pin When the opposite QBus slave image must to be accessed the MC68360 will first perform a write to change the state of this I O port pin QSpan II User Manual 363 8091862 001 08 Appendix C Typical Applications C 1 1 4 C 1 1 5 C 1 1 6 6 1 1 7 364 QBus Direct Connects All other QBus interface signals can be directly connected to the appropriate MC68360 signal External pull up resistors should be connected to all bus control signals excluding SIZ 1 and BDIP_ which are reset options and should be pulled to the desired state to ensure that they are held in the inactive state See Figure 75 to determine which signals require external pull ups Interrupts QSpan II device can pass interrupts between the PCI bus and the QBus For host bridging applications the QSpan II can accept INT as an input and assert QINT_ as an output QSpan II s interrupt output QINT_ should be connected to one of the seven possible interrupt inputs IRQ 7 1 on the MC68360 processor When the MC68360 is acknowledging a QSpan II interrupt it must be programmed to generate the cycle termination QSpan is an autovector interrupter and does not have the ability to assert AVEC_ during the interrupt acknowledge cycle For PCI adapter card applications the QSpan can accept interrupts from the QBus on the QINT_ pin and pass them through the QSpan II to its PCI INT output See Chapter 8 The Interrupt Channel on page
181. IPE or IQE set by a previous transfer must be cleared prior to or when the GO bit is set The Linked List DMA Channel ignores the setting of IDMA DMA PADD DMA QADD and IDMA DMA CNT when the DMA bit and CHAIN bit are set to 1 in IDMA DMA CS It uses the CPP and LOC to read the first command packet from either QBus or PCI bus memory If it reads the command packets from the QBus it saves the setting of TC DSIZE and INVEND fields in the DMA CS register at the start of the Linked List DMA and uses these values on subsequent loading of the command packets The command packet may change the values of these fields in DMA CS for the DMA transfer initiated by that command packet The following registers are updated from the contents of the command packet e IDMA DMA PADD 31 2 e QADD 31 2 e CS 31 20 QSpan II User Manual 8091862 001 08 Chapter 6 The DMA Channel e IDMA DMA_CNT 19 2 e CPP 31 4 The DMA Channel then starts the DMA transfer described by the command packet The command packet pointer register CPP points to the next command packet and not to the command packet that is being executed At the completion of the current command packet the next command 5 packet is loaded and the sequence continues until a command packet with the NULL bit set to 1 is loaded Once the software has set the GO bit the software can monitor Linked List DMA completion by either waiting for the
182. Input PU JTAG JTAG Test Data Output See BERR TEA TESTI CMOS Manufacturing Test PU Pin TEST2 TT Manufacturing Test PD Pin TEST3 TT Manufacturing Test PD Pin See BURST TIP JTAG Mode Select ae ZEIT JTAG JTAG Test Reset 186 QSpan II User Manual 8091862 001 08 Chapter 17 Signals and DC Characteristics Table 57 PCI Bus Address Data Pins QSpan II User Manual 187 8091862 001 08 Chapter 17 Signals and DC Characteristics Table 58 QBus Address Pins 188 QSpan II User Manual 8091862 001 08 Chapter 17 Signals and DC Characteristics Table 59 QBus Data Pins 17 mm 27 mm 17 mm 27 mm Signal PBGA PBGA Signal PBGA PBGA J J a gt ajl olo J wW N Table 60 External Request and Grant Pins cas oe me Signal PBGA PBGA Signal PBGA PBGA Low pem EXT_REQ 2 EXT_REQ 6 QSpan II User Manual 189 8091862 001 08 Chapter 17 Signals and DC Characteristics Table 61 Pin Assignments for Power Vpp 17 mm PBGA 27 mm PBGA F12 a These power pins are called VH These pins must be connected to the highest voltage level that the QSpan II I Os will observe on either the QBus or the PCI bus see Table 62 Table 62 Voltage Required to be Applied to VH a VIO denotes the signal connection to the PCI bus connector for Universal Signaling
183. Interface Continued Frequency Temperature Options 50 501 40 Timing Parameter Description Min Max D tristated from TA_ positive edge CSPCI setup to QCLK positive edge TS setup to QCLK positive edge SDACK setup to QCLK positive edge TA setup to QCLK positive edge TEA_ setup to QCLK positive edge TRETRY setup to QCLK positive edge asserted to SDACK positive edge TEA asserted to SDACK positive edge t357 TRETRY asserted to SDACK_ positive edge CSPCI hold from QCLK positive edge D hold from QCLK positive edge SDACK_ hold from QCLK positive edge TA_ hold from QCLK positive edge TEA_ hold from QCLK positive edge TRETRY_ hold from QCLK positive edge TS_ hold from QCLK positive edge TC setup to QCLK positive edge TC hold from QCLK positive edge 1 Minimum output hold time specified for load of 10 pF Maximum output delay specified for load of 50 pF Max Units Note 4 1 12 4 3 Az 3 3 3 1 4 2 2 2 1 a 2 A CA 7 1 P z 2 Minimum output hold time specified for load of 10 pF Maximum output delay specified for load of 35 pF 3 QSpan II s DP 3 0 signals have the same timing as the data bus D 31 0 QSpan II User Manual 311 8091862 001 08 Appendix B Timing Table 156 Timing Parameters for M68040 Interface Timing Parameter
184. LK negative edge negative D setup to QCLK negative edge es to50a AS_ hold from QCLK negative 0 5 0 5 ns edge t259b CSPCI_ hold from QCLK negative 1 ns edge tosod DACK_hold from QCLK negative 0 7 ns edge to50 DSACKO DSACK1_ hold from 0 7 ns QCLK negative edge tosor BERR_ hold from QCLK negative 0 5 ns edge t259g HALT hold from QCLK negative 1 2 1 3 ns edge t260 DONE_ setup to QCLK negative 0 1 0 1 ns edge t261 DONE_ hold from QCLK negative 1 8 2 ns edge to62a AS_ negated from QCLK negative 3 4 3 8 ns 1 edge de p Bh a edge 1 Minimum output hold time specified for load of 10 pF Maximum output delay specified for load of 50 pF QSpan II User Manual 307 8091862 001 08 Appendix B Timing 2 Minimum output hold time specified for load of 10 pF Maximum output delay specified for load of 35 pF During IDMA fast termination cycles the maximum MC68360 QCLK frequency is 30 MHz This applies to every variant of QSpan II Table 155 Timing Parameters for MPC860 Interface EE YI Timing Parameter Description Units Note ee aie pes Clock Pulse Width Low Clock Pulse Width High Clock Rise Time t Clock Fall Time t A asserted from QCLK positive edge BB asserted from QCLK positive edge t310 BURST asserted from QCLK positive edge R W_ asserted from QCLK positive edge SIZ
185. MA DMA CS see Table 109 on page 248 CMD DMA CHAIN DIR e DMA CS see Table 113 on page 254 TC DSIZE INVEND IWM OFF BURST 4 BRSTEN MDBS e DMA DMA PADD see Table 110 on page 251 ADDR PCI address e DMA_QADD see Table 112 on page 253 Q ADDR QBus address e IDMA DMA_CNT see Table 111 on page 252 CNT Transfer count Interrupts can be produced by enabling the appropriate bits in the INT CTL and INT DIR registers Interrupts can be generated to indicate the following e thecompletion of the DMA e occurrence of PCI bus or QBus errors 6 3 1 Initiating a Direct Mode Transfer Once all relevant data is programmed set the GO bit in the IDMA DMA CS register to 1 to initiate the direct mode DMA transfer see Table 109 on page 248 Any status bit such as IRST DONE IPE or IQE set by a previous transfer must be cleared prior to or when the GO bit is set QSpan II User Manual 99 8091862 001 08 Chapter 6 The DMA Channel 6 3 2 6 4 100 QSpan II initiates read transfers on the source bus to fill the I FIFO Once data is available in the I FIFO the destination bus master drains the data from the I FIFO The IWM field in DMA_CS register determines the amount of data transferred on the PCI bus for each DMA transaction initiated by the PCI Master Module The IDMA DMA_CNT register indicates the number of bytes left to transfer in the transaction QSpan II decreases this transfer counter by four
186. Mailbox Registers 114 Master Abort 46 53 55 56 77 Master Completion 53 84 LAT field PCI MISCI Register 218 MAX RTRY field MISC 2 Register 280 381 DATA field Register 272 MBOXI Register 273 MBOX2 Register 274 MBOXG Register 275 DIR bit INT DIR Register 269 EN bit INT CTL Register 266 MBO IS bit INT STAT Register 263 DIR bit INT DIR Register 269 MB1_EN bit INT CTL Register 266 MBI IS bit INT STAT Register 263 MB2 DIR bit QSpan II User Manual 8091862 001 08 Index INT DIR Register 269 2 EN bit INT CTL Register 266 MB2 IS bit INT STAT Register 263 MB3 DIR bit INT DIR Register 269 MB3 EN bit INT CTL Register 266 MB3 IS bit INT STAT Register 263 Register 272 MBOX Register 273 MBOX2 Register 274 MBOXG Register 275 MC68302 26 MD PED bit PCI CS Register 204 MDBS bit DMA CS Register 255 MDPED DIR bit INT DIR Register 268 MDPED EN INT 265 MDPED IS bit INT STAT Register 262 Mechanical Information 401 Memory Controller M68040 376 PowerQUICC 370 QUICC 363 Memory Read 64 Memory Read Line 45 64 Memory Read Multiple 45 64 Memory Space IDMA Channel 86 PCI Target Channel image programming 62 QBus Slave Channel burst 49 50 image programming 40 Memory Write 45 46 64 Memory Write and Invalidate 45 64 MFBBC bit PCI CS Register 204 MFUNCT bit PCI MISCO Register 207 MIN GNT field 419 Index P
187. Master mode selected at reset This reset option is determined jointly by the value of BDIP_ and SIZ 1 at reset Table 15 presents the QBus Master mode options For completeness this table also includes the QBus Slave Module options The Master Slave mode MSTSLYV field in the MISC_CTL register indicates the Master and Slave modes of the QBus see Table 127 on page 276 The connections required for interfacing the QSpan II to an MC68360 MPC860 and or M68040 are given in Appendix C Typical Applications on page 361 The QBus Master Module supports bursts reads and burst writes in MPC860 mode only Table 15 Reset Options for QBus Master and Slave Modes Reset sampling BDIP_ SIZ 1 Master Mode Slave Modes MC68360 MC68360 and M68040 MC68360 MC68360 and MPC860 1 68040 MC68360 and M68040 1 1 MPC860 MC68360 and MPC860 a This column is included because the Master mode options can restrict which slave option that can be used the M68040 Master mode is incompatible with the MPC860 Slave mode QSpan II User Manual 59 8091862 001 08 Chapter 4 The PCI Target Channel 4 2 3 1 4 3 60 QBus Data Parity Generation and Detection The QBus Master Module supports the generation and detection of QBus data parity The use of QBus data parity is optional The data parity is valid on the same clock cycle as the QBus data QSpan II supports Odd and Even parity and is controlled by the QBus Parity Enc
188. OM Base Address register 232 QSpan User Manual 8091862 001 08 Appendix A Registers Table 96 PCI Address Lines Compared as a Function of Block Size 1 Mbyte 1 20 2 Mbytes A31 A21 4 Mbytes 1 22 NEN NM QSpan II User Manual 233 8091862 001 08 Appendix A Registers Table 97 PCI Bus Error Log Control and Status Register Register Name PB_ERRCS Register Offset 140 31 24 Reserved 23 16 Reserved 15 08 Reserved PB_ERRCS Description Reset Reset By State Function G_RST Enable PCI Error Log R Write 1 G_RST to Clear 0 disable error logging 1 enable error logging Error Status 0 no error currently logged 1 error currently logged Unlock QBus Slave Channel 0 Transfers in QBus Slave Channel are suspended when ES bit is set 1 Transfers in QBus Slave Channel continue while ES bit is set CMD ERR N A 0111 PCI Command Error Log 3 0 BE ERR 3 0 G RST PCI Byte Enable Error Log 0 byte enable active 1 byte enable inactive The PCI Master Module sets the ES bit if one of the following occurs e aposted write transaction results in a Target Abort e aposted write transaction results a Master Abort The assertion of the ES bit can be mapped to the QSpan H s interrupt pins by programming the Interrupt Control and Interrupt Direction Control registers The mapping of interrupts can only occur if the EN bit in the PCI Bus Error Log register is set To dis
189. ONE bit This will require the MC68360 to reprogram the QSpan II s IDMA DMA CNT register in order to complete the remainder of the transaction If the MC68360 is programmed with a smaller transfer count than the QSpan II the MC68360 will assert the DONE signal when its IDMA count reached zero causing the QSpan to negate DREQ The MC68360 must then assert the IRST_REQ bit in the IDMA DMA CS register to reset the QSpan II s IDMA Channel During MPC860 transfers the QSpan ignores the DONE signal TC 3 0 Encoding with MPC860 IDMA If the MPC860 s I O Port pins are being shared between multiple functions for example IDMA and Ethernet then the TC 3 0 decoding must be implemented This allows peripheral devices QSpan II or Ethernet devices to determine when they are involved in a transaction QSpan II s TC 3 0 inputs can be used with SDACK to decode transactions The value that is decoded is programmed by the user through the TC 3 0 field in the IDMA DMA CS register QSpan II will decode the TC 3 0 lines for IDMA transactions if the TC Encoding Enable TC bit in the IDMA DMA CS register 15 set to 1 If the EN bit is set and an IDMA transfer is attempted where the TC 3 0 input does not match the TC 3 0 IDMA DMA CS field the QSpan II will not accept the IDMA transaction This manual adopts the convention that the most significant bit is always the largest number MPC860 designers must ensure that the
190. PCI Address data Lines 57 57 BB_ BGACK_ Hi Z QBus Bus Busy bus Grant Acknowledge BDIP_ Hi Z QBus Burst Data In Progress And IDT QSpan II Master Mode BERR_ TEA_ 115 N19 TTL 3S Hi Z QBus Bus Error Transfer Sch Error Acknowledge e fepe i im EE BGACK See BB_ BGACK_ BM ES M20 Hi Z QBus Bus Master Enable FIFO RDY Li Bus Request 0 Bus Request 0 EM Em Hi Z Burst transaction In Progress wis Command And Byte o 9 Pee om er CSREG_ QBus QSpan Register Chip Select MUS 0 QBus Data Lines E 59 EN 59 Data Parity Line pus EM DACK QBus IDMA Acknowledge SDACK_ QSpan II User Manual 183 8091862 001 08 Chapter 17 Signals and DC Characteristics Table 56 Pin List for QSpan II Signals Continued 27mm PBGA Input Output Reset IOL IOH Pin Name Ball Type Type Type State mA mA Interface Signal Description o p poppe eee m spe pee spp o we eee DSACKO_ G3 J4 3S Hi Z QBus Data And Size Sch Acknowledge 0 DSACKI Fl 35 Hi Z QBus Data And Size TA_ Sch Acknowledge 1 Transfer Acknowledge ENID 15 J18 I TTL EEPROM Loading PD Reset Options ENUM G4 K1 Hi Z CompactPCI Hot Swap event output EXT_GNT See See PCI 3S Hi Z PCI External Grant 6 1 Table 60 Table 60 EXT_REQ External Request 6 1 ne 60 o 60
191. PTC PD TA BE BURST 4 PR EN SING 07 00 Reserved QBUS_ EEPROM NOTO PSC_ QINT_ PAR _ACC QRST PME MISC_CTL2 Description Reset Name Type Reset By State Function PCI DIS R W G RST See below PCI Access Disabled 0 Access from PCI interface is enabled 1 All access to QSpan II from PCI interface is retried PTP IB R W RST PCI Target Channel Prefetch Count Image Based 0 Prefetch count is not image based use PRCNT in MISC CTL 1 Prefetch count is image based PRCNT Image 0 PRCNT2 Image 1 KEEP G_RST Keep Bus Busy BB_ asserted for back to back cycles This bit applies to all QSpan II PCI target cycles 0 Bus Busy is negated after each cycle allows change of Bus mastership 1 Bus Busy is kept asserted for multiple cycles Note Do not set this bit when the QSpan DMA channel is used with the PowerQUICC memory controller UPM PCI Target Channel Prefetch Disconnect 0 TRDY is negated between databeats until the next data is available 1 Cycle is terminated with Disconnect if the TRDY is going to be negated for more than eight PCI clocks MAX RTRY R W G RST Maximum Number of Retries completed by QSpan II as 1 0 a master on the PCI Bus 00b Forever 01b 128 10b 256 11b 384 280 QSpan User Manual 8091862 001 08 Appendix A Registers MISC_CTL2 Description Continued Reset Name Type Reset By State Function TA_BE_EN G_RST PCI Target Abort Bus Error Ma
192. QSpan II will prematurely assert the DONE bit If this happens the MC68360 must reprogram the QSpan II s IDMA DMA CNT register to complete the remainder of the transaction If the MC68360 is programmed with a smaller transfer count than the QSpan II the MC68360 will assert the DONE signal when its IDMA count reaches zero causing the QSpan II to negate DREQ The MC68360 will then have to assert the IDMA DMA Reset Request IRST_REQ bit in the IDMA DMA CS register to reset the QSpan Is Channel During MPC860 IDMA transfers the QSpan ILignores the DONE signal QSpan II User Manual 8091862 001 08 Chapter 5 The IDMA Channel 5 3 PCI Write Transactions This section describes the operation and programming of the QSpan II to move data from the QBus to the PCI bus using the MC68360 or MPC860 IDMA IDMA registers need to be programmed for a write transaction as follows e direction of the transfer must be set for writes DIR bit in the IDMA DMA_CS register set to 1 see Table 109 on page 248 The IDMA Channel operates in one direction at a time e MC683060 users can indicate whether fast termination mode is used for dual address or single address IDMA cycle bits QTERM and STERM in the IDMA DMA CS register see Table 109 on page 248 e The PORTIO bit of the IDMA DMA CS indicates whether IDMA transfers will be 16 bit or 32 bit on the QBus see Table 109 on page 248 e The IWM field of the IDMA DMA CS register dete
193. SC register which will cause QSpan II to assert its RESETO signal QSpan II s reset input RESETI is typically unused and should be pulled high through a resistor Resets are described in Chapter 14 Reset Options on page 155 HS HEALTHY should be left open as it has an internal pull down resistor For a CompactPCI adapter card that supports Hot Swap use the following reset configuration the QSpan I s H8 HEALTHY input should be connected to the Hot Swap Controllers HEALTHY output Also connect the QSpan II s reset output RESETO to the hard reset input RESETH_ on the MPC860 This enables the QSpan II to reset the MPC860 when PCI RST is asserted or when the software reset bit is asserted SW RST bit in the MISC register on Table 127 on page 276 QSpan II s reset input RESETI is typically unused and should be pulled high through a resistor Memory Controller QSpan II requires that two chip selects be generated in order to access the registers CSREG and the PCI bus CSPCI This can be accomplished by using two of the chip select outputs from the memory controller within the MPC860 There are two QBus slave images within the QSpan II which are used to access the PCI bus The image that is selected when the PCI chip select is asserted is dependent on the state of the Image Select signal IMSEL If IMSEL is low then QBus slave image 0 is selected otherwise QBus slave image 1 is selected IMSEL is typically ge
194. SS Register 206 PCI CP Register 217 PCI CS Register 203 BM bit 110 157 164 168 172 382 D PE bit 52 DEVSEL field 64 DP D bit 52 118 MS bit 108 PERESP bit 52 77 S SERR bit 77 SERR EN bit 77 PCI DIS 177 185 Reset Options 158 PCI DIS bit MISC CTL2 Register 280 381 PCI ID Register 202 PCI MISCO Register 207 CLINE field 83 87 89 92 PCI MISCI Register 218 PCI Register 219 PCI PMCS Register 220 PCI SID Register 214 SID field 127 SVID field 127 PCI VPD Register 222 223 PCLK 175 185 PCSR DIR bit INT DIR Register 268 PCSR EN bit INT CTL Register 265 PCSR IS bit INT STAT Register 262 PDERR field PB DERR Register 237 385 PEL DIR bit INT DIR Register 268 PEL EN bit INT CTL Register 265 PEL IS Register 421 Index INT_STAT Register 262 PERESP bit PCI_CS Register 204 PERR_DIR bit INT_DIR Register 269 PERR_EN bit INT_CTL Register 266 PERR_IS bit INT_STAT Register 263 PERR 52 175 185 P FIFO 59 Pin Out 17x17 mm Package 192 193 Plug and Play 27 PM_VER field PCI_PMC Register 219 PME_CLK bit PCI_PMC Register 219 PME_EN bit PCI_PMCS Register 220 PME_SP field PCI_PMC Register 219 PME_ST bit PCI_PMCS Register 220 PME 153 177 185 Port Size IDMA Channel 87 88 89 IDMA CS register 87 249 PBROM CTL register 232 PBTIO CTL register 224 PBTI1_CTL register 228 254 PCI Target Image 62 PORT16 bit IDMA DMA CS Register 249 Posted Write error 56 84 PCI Target Channel 74 enabling 62 74 error lo
195. STI Reserved Reserved Reserved Reserved Reserved Reserved 7 PREF 6 PREF The top part of each byte row indicates the register name Bit locations within the register are in square brackets and field names are within round brackets b Unlike the other non reserved bits read from the EEPROM bit 7 of byte 4 bit 5 of byte 7 and bit 7 of byte 8 are not written to a QSpan II register These bits determine whether certain other register bits are loaded from the EEPROM c If the last three bits of the 12th byte are 010 then the QSpan II will read the next 11 bytes from the EEPROM If no further loading is required these bits must be programmed as 000 d PCI DIS If 0 PCI DIS in MISC CTL2 is set to 1 if 1 it has no effect on the PCI DIS setting in the MISC_CTL2 register 9 5 Programming the EEPROM from the QBus or PCI Bus EEPROM can be accessed from the QBus or the PCI bus either by a read or write using 32 bit writes to the EEPROM_CS register EEPROM read and write transactions are described in the following sections 9 5 1 Writing to the EEPROM EEPROM values are loaded by the QSpan II when the QSpan II is reset The user must reset the QSpan II after writing to the EEPROM through the QSpan II in order to load new EEPROM data written to the lower 32 bytes To write to the EEPROM complete the following 1 Read the EEPROM_CS register and make sure that the EEPROM Active ACT bit is set to 0 this indicates prior EEPROM acce
196. Span II behaves as an M68040 slave in response to the assertion of the TS_ signal when it is powered up as an M68040 slave see QBus Master and Slave Modes on page 158 When the QBus Slave Module receives TS_ it responds with DSACK1_ TA_ or BERR_ TEA_ QSpan II recognizes a transaction as intended for it and acknowledges it accordingly only if one of CSREG_ or CSPCI_ is sampled active in conjunction with TS QSpan II samples the address bus and other TS_ qualified signals on the same rising edge of QCLK in which it samples TS_ asserted The QBus Slave Module accepts bursting of incoming data When the QSpan II operates as an M68040 slave it functions as a 32 bit peripheral in synchronous mode and must be addressed as a 32 bit peripheral External QBus masters must comply with the M68040 timing specification QSpan II User Manual 41 8091862 MAOOI 08 Chapter 3 The QBus Slave Channel 3 4 2 3 4 3 42 PCI Bus Request The PCI Master Module requests the PCI bus when one of the following occurs e write data is received in the Qx FIFO e after the last data phase of a burst write is received in the Qx FIFO e if there is a read request If the QSpan II is powered up to use an external PCI bus arbiter when it requires control of the PCI bus it asserts REQ and gains bus mastership when the PCI arbiter asserts grant If the QSpan is powered up to use the internal PCI bus arbiter the request grant signals are internal If the
197. Span II is isolated from the power being supplied to other devices on the board by 0 1uF decoupling capacitors It is recommended every fourth Vpp Vss pair has a decoupling capacitor 160 QSpan II User Manual 8091862 001 08 Chapter 16 Signals This chapter describes the signals which are supported by the QSpan II The following topics are discussed MC68360 Signals QUICC on page 163 MPC860 Signals PowerQUICC on page 167 M68040 Signals on page 171 PCI Bus Signals on page 174 Hot Swap Signals on page 176 Miscellaneous Signals on page 177 JTAG Signals on page 178 16 1 Terminology The following abbreviations are used in this chapter in out t s s t s o d QSpan II User Manual 8091862 001 08 Defines a signal as a standard input only signal Defines a signal as a standard output only signal Defines a signal as a bidirectional tristate input output signal Defines a signal as a sustained tristate signal that is driven by one owner at a time Defines a signal as an open drain 161 Chapter 16 Signals 16 2 162 Overview QSpan II s QBus Interface defines a number of signals that can be mapped to MC68360 QUICC MPC860 PowerQUICC or M68040 buses see the following table Table 50 QBus Signal Names Compared to Motorola Signals BB BB BGACK BGACK 0 500 0 TSIZ 0 1 SIZ 1 0 0 E 0 AT 0 3 TT 1 0 TM 2 0 a TC 3
198. Span II when it is a QBus master and is tristated otherwise As a slave the QSpan II assumes write data is valid on the rising edge of QCLK following the clock edge where AS _ is sampled asserted For read transactions the QSpan II provide information independent of DS DS is output only As a master on the QBus the QSpan asserts DS to qualify data during reads and writes For write transactions the DS is driven from the falling edge of QCLK one half a clock period after the data is driven onto the Data bus For read transactions DS is driven at the same time as AS QSpan II negates DS_ prior to tristate HALT TRETRY Rescinding tristate bidirectional Halt Suspends external bus activity It is used for generating retries As an MC68360 slave QSpan uses HALT TRETRY as stated in Table 11 on page 54 an MC68360 master QSpan uses HALT TRETRY as stated in Table 27 on page 81 Image Select selects which QBus Slave Image to use when CSPCI is asserted The timing requirements for IMSEL are the same as those of the address bus when the QSpan II is a QBus slave QBus Clock All devices intended to interface with QBus side of the QSpan II must be synchronized to this clock The QCLK can operate up to 33 MHz with an MC68360 bus During IDMA fast termination cycles the maximum MC68360 QCLK frequency is 30 MHz QSpan II User Manual 165 8091862 001 08 Chapter 16 Signals 16 3 MC68360 Signals QUICC Continued Open drain
199. TIO CTL Table 89 on page 224 PBTI1_CTL Table 92 on page 228 Block Size Determines the number of AD lines BS 3 0 that are examined when decoding accesses from the PCI bus QSpan II User Manual 61 8091862 001 08 Chapter 4 The PCI Target Channel Table 16 Address Fields for PCI Target Image Continued PCI Address Space Memory space or I O space PCI BSTO or Table 75 on PAS PBTIO CTL page 210 or Table 89 on page 224 PCI BSTI or Table 77 on page 212 or Table 92 on page 228 Translation Address Address bits that are substituted to PBTIO_ADD Table 90 on TA 31 16 generate the QBus address page 226 1 PBTII ADD Table 93 on page 230 Table 17 Control Fields for PCI Target Image Image Enable EN Enable bit PBTIO CTL Table 89 on page 224 1 Table 92 on page 228 Posted Write Enable Determines whether writes are posted PBTIO_CTL Table 89 on PWEN or processed as delayed transactions page 224 1 Table 92 page 228 Transaction Code Transaction code generated on the PBTIO_CTL Table 89 on TC 3 0 QBus page 224 Table 92 page 228 PBTIO_CTL Table 89 on page 224 Port Size DSIZE QBus destination port size Prefetch Read Enable Determines whether the QSpan II PREN prefetches data on the QBus PBTIO CTL Table 89 on page 224 Table 92 page 228 1 Table 92 page 228 62 QSp
200. The BDIP and SIZ 1 signals must be pulled high at reset to enable the QSpan II to perform as an MPC860 master and slave see Chapter 14 Reset Options on page 155 SDA and signals should be pulled high if the EEPROM is used The SDA signal should be pulled low if the serial EEPROM is not used in this design The ENID signal can be left open if the serial EEPROM is not used as there is an internal weak pull down resistor QSpan II User Manual 371 8091862 001 08 Appendix C Typical Applications C 2 1 9 C 2 1 10 2 1 11 2 1 12 2 1 13 372 e TMODE 1 0 signals can be left open as there are internal pull down resistors on these pins within the QSpan IL If an in circuit tester is used during the board manufacturing process then these two signals should be brought out as test points This allows the in circuit tester to place the QSpan in a tri state NAND TREE test mode e Ifthe BM EN FIFO RDY signal is sampled high while RST is asserted the QSpan II sets the Bus Master BM bit in the PCI CS register see Table 70 on page 203 This enables the QSpan II as a PCI bus master This pin can be left as a no connect as there is an internal weak pull down resistor e Ifthe PCI EN signal is sampled high on the negation of a reset event then the PCI bus arbiter within the QSpan is enabled There is an internal pull down resistor on this pin to maintain backward compatibility e
201. The DMA Command Packet Pointer CPP points to 16 byte aligned address location This location is in QBus memory or PCI bus memory that contains the command packet to be loaded for Linked List DMA Some of the register bits in the IDMA DMA Control and Status IDMA DMA CS register are used by the DMA Channel The following bits are not used by the DMA Channel because they are only used during IDMA transfers IWM TC TC EN IMODE QTERM STERM PORTI6 The IDMA DMA CS register uses two additional bits to support a DMA transfer DMA which indicates a DMA transfer is requested and CHAIN which indicates a Linked List DMA transfer is requested All other register bits have the same function in a DMA transfer as in an IDMA transfer An additional register DMA Control and Status Register CS defines other fields to control the QBus transaction generated by the QSpan II during DMA transfers QSpan II generates DMA transfers on the QBus as an MC68360 QUICC master as an MPC860 PowerQUICC master or as an M68040 master depending on the QBus Master mode selected at reset MSTSLV field in MISC The QBus master only generates burst cycles as an MPC860 master The Transaction Code TC field determines the transaction code generated on the QBus during a DMA transfer The INVEND bit inverts the endian setting of setting in MISC The QBus Destination Size DSIZE determines the destin
202. The QBus Slave Module accepts new accesses In the case of QBus Slave Channel single reads 8 The QBus Slave Module allows the read to complete on the QBus 9 The QBus allows posted writes to the Qx FIFO even if the single read has not completed 10 The PCI Target Module allows posted writes to the Px FIFO QSpan User Manual 51 8091862 001 08 Chapter 3 The QBus Slave Channel 3 5 3 3 5 4 22 Transaction Ordering Disable Option The No Transaction Ordering bit in the MISC CTL2 register disables transaction ordering between the QBus Slave Channel and the PCI Target Channel see Table 130 on page 280 When this bit is set a read in one channel is unaffected by posted writes in the other channel This feature improves system performance especially when using the DMA and where strict transaction ordering is not required PCI Target Channel Reads In PCI Target Channel reads the PCI Target Module latches the read request even when there is data in the Px FIFO The PCI Target Module only passes the information onto the QBus Master Module when the Px FIFO is empty see Reads and PCI Transaction Ordering on page 77 Parity Monitoring by PCI Master Module QSpan II monitors the Parity signal PAR when it accepts data as a PCI master during a read and drives PAR when it provides data as a PCI master during a write QSpan II also drives PAR during the address phase of a transaction when it is a PCI maste
203. User Manual 39 8091862 001 08 Chapter 3 The QBus Slave Channel The following tables summarize the QBus Slave Image control and address fields Table 3 Address Fields for QBus Slave Image Abbreviation and Field Register Page Description Block Size BS Table 138 on page 287 and Table 145 Amount of PCI memory on page 291 accessible from QBus PCI Address Space PAS Table 133 on page 285 and Table 140 Mapping to PCI memory on page 289 space or I O space Translation Address TA Table 138 on page 287 and Table 145 Address bits that are substituted to generate on page 291 the PCI bus address Enable Address EN Table 138 on page 287 and Table 145 Enables address translation using TA field Translation on page 291 Table 4 Control Fields for QBus Slave Image Posted Write PWEN Table 133 on page 285 and Posted write enable bit Table 140 on page 289 Prefetch Read PREN Table 133 on page 285 and Prefetch read enable bit Table 140 on page 289 The QBus Slave Channel allows a QBus master to access a range of addresses in PCI Memory or I O space The PCI address space bit PAS of the selected image determines whether the current transfer is directed towards PCI Memory or I O space The range of addresses that can be accessed through a Slave Image is controlled by the block size BS field Up to 2 Gbytes of PCI Memory or I O space can be accessed from the QBus in one Slave Image if address translation is required The use of the
204. a Target Image must not overlap with the 4 Kbytes of QSpan II Register Space or the other target image The parameters for register accesses are discussed in Register Access from the PCI Bus on page 107 The type of cycle generated on the QBus is determined by the Target Image selected and C BE 3 0 A Target Image is a set of parameters that determines what addresses are decoded on the PCI bus and how cycles are translated from the PCI bus to the QBus Two Target Images of equal capability are provided so that PCI Masters can quickly access different QBus devices or the same device in different ways without having to reconfigure QSpan II registers The two Target Images are independent from one another For example one Target Image can be set up to access 1 Mbyte of 16 bit SRAM on the QBus using delayed writes while the other can access 64 Mbytes of 32 bit SDRAM on the QBus with posted writes PCI Masters do not need to reconfigure QSpan II registers to access either of these devices For a third type of access it would be necessary to share one of the Target Images The following tables summarize the PCI Target Image control and address fields Table 16 Address Fields for PCI Target Image m o Base Address Address lines compared in decoding PCI BSTO or Table 75 on BA 31 16 PBTIO ADD page 210 or Table 90 on page 226 1 PCI BSTI or Table 77 on ADD page 212 or Table 93 on page 230 PB
205. a from the Px FIFO onto the QBus When enabled all byte lanes are assumed to be active for data written to the image Generation of burst writes is only supported while in MPC860 Master mode see Table 15 on page 59 Burst length on the QBus is controlled by the BDIP_ signal by negating BDIP_ the QSpan II signals the QBus slave that the current data beat is the second last beat of the transaction This allows the QSpan II to perform bursts of two three or four data beats QSpan can be programmed to generate a burst of four data beats to be compatible with the MPC860 s memory controller UPM This can be completed by setting the QBus Burst Four Dataphases BURST_4 bit in the MISC_CTL2 register see Table 130 on page 280 If the write transfer is not cacheline aligned then the QSpan II will perform single writes up until a cacheline boundary Similarly if a PCI write transaction completes the QSpan II will perform single write cycles for the entries that remained in the Px FIFO at a non cacheline aligned address The KEEP BB bit in the MISC CTL2 register see Table 130 on page 280 is not supported for DMA operation As such do not set this bit when the QSpan II DMA channel is used with the PowerQUICC memory controller UPM Delayed Writes If a write is attempted when posted writes are disabled for the PCI Target Image PWEN is set to 0 or the address space bit is set to 1 for I O transfers then write cycles are treated as
206. able Below 0 Not Prefetchable 1 Prefetchable reads have no side effects PAS PCI RST See PCI Bus Address Space of PCI Target Image 1 Below 0 Memory Space 1 Space This register is enabled if the state of the SDA or ENID pin is latched as high during PCI reset and bit 7 of byte 8 of the EEPROM is 1 This register is also enabled if the power up option PCI_DIS is latched high during Reset If this register is not enabled for example there is no EEPROM or bit 7 of byte 8 of the EEPROM is 0 the entire register is read only and reads return all zeros If enabled this register specifies the Base Address and PAS fields for PCI Bus Target Image 1 The Base Address is used during transaction decoding it specifies the contiguous PCI bus address line values compared by the QSpan II during PCI bus address phases The number of address lines compared for this image is based on the value of the Block Size field in the PBTI1_CTL register see Transaction Decoding on page 61 If this register is enabled the number of writable bits in BA 31 16 is determined by the Block Size field of the PBTI1_CTL register see Table 92 on page 228 After power up the serial EEPROM contents are loaded and a PCI host can write all 1s to the BA field of this register The number of 1s that are read back can be used to compute the block size of the image Block Size 2 64Kbytes 2N For example if the Block Size is 64 Kbytes BS 0000 then the B
207. able 120 Interrupt Control Register Register Name INT_CTL Register Offset 604 Function 31 24 PEL_EN QEL_EN MDPED EN PCSR EN IQE EN IPE EN IRST EN DONE EN 23 16 INT EN EN SERR EN QINT EN MB3 EN MB2 EN EN EN 15 08 QDPE EN PSC EN OPNE EN IPN EN IFE EN OFE EN IPF EN OFF EN 07 00 Reserved 510 INT_CTL Description Reset Name Reset By State Function G_RST PCI Bus Error Log Interrupt Enable PEL_EN 0 Disable mapping of PCI error log interrupt 1 Enable mapping of interrupt QEL_EN G_RST G_RST MDPED_EN G_RST QSpan II User Manual 265 8091862 001 08 QBus Error Log Interrupt Enable 0 Disable mapping of QBus error log interrupt 1 Enable mapping of interrupt PCI Master Data Parity Detected Interrupt Enable 0 Disable mapping of Master Data Parity Detected interrupt 1 Enable mapping of interrupt PCI_CS Register status bit set Interrupt Enable 0 Disable mapping of PCI_CS Register status bit set interrupt 1 Enable mapping of interrupt PCSR_EN IQE_EN IPE_EN IRST_EN DONE_EN IDMA DMA QBus Error Interrupt Enable 0 Disable mapping of IDMA QBus error interrupt 1 Enable mapping of interrupt IDMA DMA PCT Error Interrupt Enable 0 Disable mapping of IDMA PCI error interrupt 1 Enable mapping of interrupt IDMA DMA Reset Interrupt Enable 0 Disable mapping of IDMA reset interrupt 1 Enable mapping of IDMA reset interrupt IDMA DMA Done Interrupt Enable 0 Disable
208. able 71 on page 206 0 00 PCI MISCO PCI Configuration Miscellaneous 0 Register Table 72 on page 207 0x010 PCI BSM PCI Configuration Base Address for Memory Register 150 Table 73 on I20 BAR Base Address Register when I 0 operation is enabled page 208 0 014 PCI Unimplemented Ee 0x018 PCI BSTO PCI Configuration Base Address for Target 0 Register PCI Table 75 on PCI BSM Configuration Base Address for Memory Register when page 210 1 0 operation is enabled 0x01C PCI BSTI PCI Configuration Base Address for Target 1 Register Table 77 on page 212 0x020 PCI Unimplemented P 0x024 PCI Unimplemented 0 02 PCI_SID PCI Configuration Subsystem ID Register Table 79 on page 214 0x030 PCI BSROM PCI Configuration Expansion ROM Base Address Register Table 80 on page 215 0x034 PCI CP PCI Capabilities Pointer Register Table 82 on page 217 0x038 PCI Reserved 0x03C PCI MISCI PCI Configuration Miscellaneous 1 Register Table 83 on page 218 0x040 0x0DB PCI Unimplemented PCI Power Management Capabilities Register Table 84 on page 219 OxOEO PCI PMCS PCI Power Management Control and Status Register Table 85 on page 220 0 0 4 CPCI HS CompactPCI Hot Swap Register Table 86 on page 221 QSpan II User Manual 197 8091862 001 08 Appendix A Registers Table 67 Register Map Continued Address Offset Hexidecimal Register Description See 0 0 8 PCI_VPD PCI Vital Product Data VPD Regi
209. able the PCI Error Logging after it has been enabled the ES bit must not be set If ES is set it can be cleared by writing a 1 at the same time as a 0 is written to the EN bit 234 QSpan II User Manual 8091862 001 08 Appendix A Registers The BE_ERR field only contains valid information when the ES bit is set At all other times these fields return all zeros when read Setting the UNL_QSC enables the QBus Master to service the QBus Slave Channel while the ES bit is set and the Error log is frozen The ES bit must be cleared to log a new error If error logging is enabled it recommended that the UNL_QSC bit be set to 1 QSpan II User Manual 235 8091862 001 08 Appendix A Registers Table 98 PCI Bus Address Error Log Register Register Name PB_AERR Register Offset 144 31 24 PAERR 23 16 PAERR 15 08 PAERR 07 00 PAERR PB_AERR Description Reset Name Type Reset By State Function PAERR 31 0 pues G RST 0 PCI Address ErrorLog PClAddesEmorlog 000000 Address Error Log The QSpan II as PCI master will log errors if a posted write transaction results in a Target Abort or a posted write transaction results in a Master Abort This register logs the PCI bus address information Its content are qualified by bit ES of the PCI Bus Error Log Control and Status Register see Table 97 The PAERR field contains valid information when the ES bit is set At all other times a read of this register will return all
210. active low at this time the QSpan II drives out RESETO low until is negated On the assertion of HEALTHY or the negation of RST if RST was active when H5 HEALTHY was asserted the QSpan II loads from the EEPROM if enabled After the EEPROM loading the QSpan II sets the Insertion INS bit in CPCI HS register signals the Host using if enabled and accepts Configuration cycles from the Host QSpan II can also be set using a power up option PCI DIS to hold off asserting and retry Configuration cycles while the QBus Host programs the QSpan II s Configuration registers At the end of this programming the PCI DIS bit in the MISC CTL2 register see Table 130 on page 280 can be cleared to enable the QSpan II to set the INS bit to assert ENUM and to accept Configuration cycles from the Host The Host can clear ENUM by writing to the INS or EIM bit in CPCI HS register The Host can then configure the QSpan II based add in card QSpan II User Manual 147 8091862 001 08 Chapter 12 CompactPCI Hot Swap Friendly Support Table 45 Insertion Sequence Long pins a open connect Medium pins connect Short pins High Z L open on connect HS_ Low Z L open on HEALTHY_ asserted mma ww o9 Close Ejector Low Z Z closed off latch Host clears Low Z Z closed off ENUM a QSpan II will load from externa
211. ad transaction on the QBus if the following conditions are met 1 The PREN bit in the selected Target Image must be 1 2 Prefetch Read Byte Count PRCNT 5 0 bit in the MISC_CTLx register must be programmed The PRCNT2 5 0 and PTP_IB bits in the MISC_CTL2 register can also be programmed to enable image based prefetching see Table 130 on page 280 3 The PCI master must keep FRAME asserted when IRDY is asserted for example PCI burst read cycle QSpan II will read the amount of data specified in the appropriate PRCNTx 5 0 field of the MISC_CTLx register see Table 127 on page 276 and Table 130 on page 280 QSpan II retries the PCI master until read data is available in the Pr FIFO If the PREN bit is cleared which is the default setting the transfer is processed as a delayed single read see Single Read Transactions on page 76 QSpan II will prefetch whether it is in MC68360 MPC860 or M68040 Master mode see QBus Master Module on page 59 However it will only prefetch with burst reads on the QBus when it is MPC860 Master mode If the external QBus slave does not support bursting setting the QBus Prefetch Signal Dataphase PR_SING bit will cause the QSpan II to prefetch in MPC860 mode using only single reads If a read request is not cacheline aligned then the QSpan II will perform single beat transactions on the MPC860 bus until it reaches a cacheline boundary The QBus Master Module as MPC860 master onl
212. ading the timing diagrams in this appendix Figure 24 Reference Voltages for AC Timing Specification Ons 50ns 100ns 150ns Ld dg Ld d Ig Ld d dg QCLK 2 0V osv V 0 8V 2 0V A 2 0V 2 0V Outputs Bn a AT 2 0V 20V Output uv P D C 20V 2 0V Inputs e 2 nas Coma Input 2 0 2 0 0 8V 0 8V A Max Output Delay B Min Output Hold C Min Input Setup D Min Input Hold In order to condense the diagrams and tables certain multifunctional QBus signals are presented in their bus specific forms for example DSACKI is referred to as in the MPC860 and M68040 sections 302 QSpan II User Manual 8091862 001 08 Appendix B Timing Table 154 Timing Parameters for MC68360 Interface Frequency Temperature Options Timing Parameter Description eS eee Units Note mme I IIS t210a A asserted from QCLK positive 10 7 ns 2 edge t210b BERR_ asserted from QCLK 9 2 10 2 ns 2 positive edge t210c DSACKO DSACKI asserted 9 4 10 4 ns 2 from QCLK positive edge to10d HALT asserted from QCLK ns 2 positive edge o10e R W asserted from QCLK ns 2 positive edge t210f SIZ asserted from QCLK positive 7 9 8 8 ns 2 edge t210g TC asserted from QCLK positive 8 4 9 3 ns 2 edge BGACK asserted from QCLK 9 2 10 2 ns 1 positive edge t211b BR_ asserted from QCLK positive 7 4 8 2 ns 2 edge t212a DSACKO
213. affected by a previous transfer must be cleared prior to or while the GO bit is set 5 3 1 Data Path QSpan II requests data from the IDMA by asserting DREQ_ By asserting SDACK IDMA acknowledges that data is being written to the I FIFO With a 16 bit QBus port the QSpan II packs two 16 bit transfers from the QBus into one 32 bit entry in the I FIFO When the I FIFO is full the QSpan II negates DREQ QSpan II User Manual 89 8091862 001 08 Chapter 5 The IDMA Channel 5 4 90 QSpan II requests the PCI bus when there is as much data in the I FIFO as is specified by IWM field of the IDMA DMA_CS register if the IWM equals 0 the QSpan II requests the PCI bus when a cacheline is queued in the I FIFO QSpan II burst writes data to the PCI target The IDMA DMA_CNT register indicates the number of bytes to transfer in an IDMA transaction see Table 111 on page 252 QSpan II decreases the transfer count by four with every 32 bit transfer on the PCI bus the IDMA Channel on the PCI Interface transfers 32 bit data The amount of data that can be transferred within an IDMA transaction is 16 Mbytes for example 222 32 bit transfers When the IDMA DMA_CNT expires the QSpan II sets the DONE bit in the IDMA DMA CS register The MC68360 IDMA asserts the DONE signal when its transfer counter expires If the MC68360 is programmed with a larger transfer count than the QSpan II the QSpan II will prematurely assert the D
214. an II User Manual 8091862 001 08 Chapter 4 The PCI Target Channel Table 17 Control Fields for PCI Target Image Continued Burst Write Enable Determines whether the QSpan II burst PBTIO_CTL Table 89 on BRSTWREN writes data on the QBus page 224 PBTII Table 92 on page 228 Invert Endianness Determines whether the QSpan II INVEND inverts the endian setting of the bit in the MISC register PBTIO CTL Table 89 on page 224 Table 92 page 228 1 1 PCI Target Channel Determines whether image based Prefetch Count Determines the amount of data the 0 and or MISC_CTL Table 127 on PRCNT 5 0 QSpan II prefetches on the QBus 1 page 276 1 MISC_CTL2 Table 130 on Prefetch is image based prefetching is enabled page 280 PTP_IB Prefetch Count Determines the amount of data that the 1 MISC_CTL2 Table 130 on PR_CNT2 5 0 QSpan prefetches on the QBus for page 280 accesses to Image 1 if PTP_IB 1 QBus Burst 4 Data Determines whether the QBus bursts 0 and 1 MISC_CTL2 Table 130 on Phases BURST_4 four data phases versus two or three page 280 data phases QBus Prefetch Single Determines whether the QSpan II will 0O and 1 MISC_CTL2 Table 130 on Dataphase PR_SING generate single cycles to prefetch data page 280 as an MPC860 master Keep Bus Busy for Determines whether Bus Busy is 0 and 1 MISC CTL2 Table 130 on Back to back cycles asserted for multiple cycles on the page 280 KEEP
215. an active master the QSpan II drives R W and tristates it otherwise As an addressed slave the R W_ pin is an input SIZ 1 0 Tristate bidirectional Size indicates the number of bytes to be transferred during a bus cycle The value of the Size bits along with the lower two address bits and the port width define the byte lanes that are active Table 51 on page 171 shows the encoding for the Size bits SIZ 1 0 is intended to connect to MPC860 TSIZ 0 1 QSpan II User Manual 169 8091862 001 08 Chapter 16 Signals 16 4 MPC860 Signals PowerQUICC Continued Rescinding tristate bidirectional See DSACK1_ TA_ TC 3 0 Tristate bidirectional Transaction Code Bus provides additional information about a bus cycle when the QSpan II is a QBus master Driven by the QSpan II when it is a QBus master and tristated otherwise As a slave the QSpan II samples TC 3 0 on the first rising edge of the QCLK after TS is asserted TC 3 0 can optionally be used with DACK SDACK to decode an IDMA operation For use in IDMA transfers TC 3 0 should be set to all ones The timing for the TC 3 0 outputs is the same as the timing for the address bus when the QSpan II is a QBus master The values output on the TC 3 0 bus during a transaction in which the QSpan II is the bus master is determined by the value programmed in the Transaction Code field of the corresponding QSpan II PCI target image TC 3 0 is intended to connect to the MPC860
216. ance improvements of the QSpan II set the following bits to 1 BURST_4 PWEN bit in PBTIx_CTL REG_AC QSC_PW and NOTO This will maximize performance if there are no ordering requirements between transactions in the PCI Target Channel and the QBus Slave Channel QSpan II can be setup to retry all PCI access while the QBus processor is used to configure the PCI configuration registers This can be accomplished using the PCI_DIS bit in MISC_CTL2 The power up pin PCI_DIS must be pulled high during PCI reset to set the PCI_DIS bit to 1 The PCI_DIS bit can be set to 0 by the QBus processor when it completes programming the QSpan II registers Once completed this will then allow the QSpan II to respond to PCI configuration cycles The PCI_DIS bit can also be programmed from the EEPROM in this case after the QSpan II registers are loaded from EEPROM the registers can be modified by the QBus processor before the external Host configures the QSpan II 282 QSpan II User Manual 8091862 001 08 Table 131 PCI Bus Arbiter Control Register Register Name PARB_CTL Register Offset 810 31 24 23 16 15 08 M7_PRI M6_PRI M5 PRI 4 PRI E Appendix A Registers Reserved Reserved M3 PRI QS PRI M2 PRI PRI 07 00 PCI_ Reserved PARK BM_PARK ARB_EN PARB_CTL Description Reset State QSpan User Manual 8091862 001 08 Function Arbitration Level for PCI Master Device x 0 Low priority 1 High priority
217. apter 8 The Interrupt Channel on page 115 QSpan II User Manual 91 8091862 001 08 Chapter 5 The IDMA Channel Table 31 QSpan IPs Response to Errors PCI Bus Transfer PCI Bus Error QBus Error Prefetching stops IPE is set in the IDMA DMA_CS register Then the QSpan II negates DREQ_ If enabled an interrupt is generated on the PCI bus or the QBus PCI writes from I FIFO are halted IPE is set in the IDMA DMA CS register If enabled an interrupt is generated on the PCI bus or the QBus The QSpan II negates DREQ QSpan II negates DREQ_ Transfers on QBus stop IQE is set in the IDMA DMA_CS register If enabled an interrupt is generated on the PCI bus or the QBus Prefetching stops when the current IDMA PCI transfer if any is complete QSpan negates DREQ_ IQE is set in the IDMA DMA CS register If enabled an interrupt is generated on the PCI bus or the QBus If a PCI transfer from the I FIFO is in progress any complete CLINE of data in the I FIFO is transferred to the PCI target See the following section Table 32 IDMA Interrupt Source Enabling Mapping Status and Clear bits IDMA QBus IQE in IQE EN IQE DIR IQE IS Error IDMA DMA CS IDMA PCI Bus IPE in EN IPE DIR IPE IS Error IDMA DMA CS IDMA Reset IRST in IRST EN IRST DIR IRST IS IDMA DMA CS IDMA Done DONE in DONE EN DONE DIR DONE IS IDMA DMA CS Source Bits IDMA DMA CS Table 109 on page 248 Write 1 to c
218. arbiter removes grant after the QSpan II has begun its PCI transaction the QSpan II completes the current cycle and releases the PCI bus This means that the QSpan II PCI Master Module will have to re arbitrate for the PCI bus after every cycle if its grant is removed QSpan II performance as PCI master can be enhanced through bus parking as defined in the PCI Local Bus Specification 2 2 for more information about bus parking see Bus Parking on page 144 QSpan II cannot be master and target on the PCI bus at the same time Address Translation The QBus Slave Channel contains an Address Generator see Figure 4 which is used if address translation is enabled EN bit in Table 138 or Table 145 The Address Generator produces the PCI address using three inputs the address of the QBus signal A 31 0 the block size of the QBus Slave Image BS field of the QBSIx register and the translation address of the QBus Slave Image TA field of the QBSIx AT register The translation address is a 16 bit number whose upper bits specify the location of the Target Image on the PCI bus The correlation between BS and the number of TA bits to use in generating the PCI address is shown in Table 5 on page 44 For example with a 64 Kbyte block size the Address Generator copies the entire translation address into the PCI address but only copies the lower 16 bits from the QBus address signals With a 2 Gbyte block size the Address Generator copies all b
219. asserted from QCLK positive edge asserted from QCLK positive edge TC asserted from QCLK positive edge TEA_ asserted from QCLK positive edge t310i TRETRY asserted from QCLK positive edge TS_ asserted from QCLK positive edge BDIP_ asserted from QCLK positive edge BR_ asserted or negated from QCLK positive edge BB tristated from QCLK negative edge TS tristated from QCLK negative edge BB setupto QCLK positive edge 10 10 2 2 10 7 8 8 Nn 95 1 1 1 1 1 1 1 2 1 1 ES 28 3 6 8 10 9 4 8 2 10 2 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns A UA 308 QSpan User Manual 8091862 001 08 Appendix B Timing Table 155 Timing Parameters for MPC860 Interface Continued Frequency Temperature Options ow to 50 501 40 Timing Parameter Description Max Units Note t313b BDIP_ setup to QCLK positive edge t313c BG setup to QCLK positive edge t313d BURST_ setup to QCLK positive edge t313 D setup to QCLK positive edge 7 t313f IMSEL setup to QCLK positive edge t313g TA_ setup to QCLK positive edge t313h TEA_ setup to QCLK positive edge t313i TRETRY_ setup to QCLK positive edge D valid slave reads from QCLK positive edge t314 t315a A_ hold from QCLK positive edge t315b BB_ hold from QCLK positive edge BDIP_ hol
220. aster Abort 1 QSpan generated Master Abort The QSpan II sets this bit when a transaction it initiated had to be terminated with a Master Abort R Write 1 PCI RST Received Target Abort to Clear 0 Master did not detect Target Abort 1 Master detected Target Abort The QSpan II sets this bit when a transaction it initiated was terminated with a Target Abort R Write 1 PCI RST Signaled Target Abort to Clear 0 Target did not terminate transaction with Target Abort 1 Target terminated transaction with Target Abort Device Select Device Select Timing The QSpan II is a medium speed device QSpan II User Manual 203 8091862 001 08 Appendix A Registers PCI CS Description Continued Reset Name Type Reset By State Function MD_PED R Write 1 PCI_RST Master Data Parity Error Detected to Clear 0 Master Module did not detect generate data parity error 1 Master Module detected generated data parity error The QSpan II sets this bit if the PERESP bit is set and either a it is the master of transaction in which it asserts PERR or b the addressed target asserts PERR TFBBC N A 1 Target Fast Back to Back Capable QSpan II can accept fast back to back transactions from different agents DEV66 N A Device 66 MHz Capable The QSpan is not capable of running at 66 MHz it is a 33 MHz capable device CAP_L N A 1 Capabilities List The QSpan II implements the new Capabilities List The capabilities pointer at offset 34h
221. at the conclusion of this reset the QSpan II reads 12 bytes of data from the EEPROM QSpan II can also load the next 11 bytes from the EEPROM if the last three bits of the 12th byte are 010b The read of the 12 bytes from the EEPROM is performed as a Sequential Read After the START condition the QSpan II puts out a 7 bit device select code of 1010000 The four most significant bits of the device select code for the PC protocol are required to be 1010 The following three bits are chip enable signals that are 000 The chip enable lines on the EEPROM must be tied low QSpan II expects the data delivered from the EEPROM starting at address zero Figure 16 shows this Sequential Read transaction After reset the EEPROM port completes a STOP then a START before loading from the EEPROM Figure 16 Sequential Read from EEPROM ACK ACK ACK ACK DEV SEL BYTE ADDR TTT tt td DEV SEL BYTE 1 START RW START RW ACK NO ACK 12 STOP QSpan II User Manual 125 8091862 001 08 Chapter 9 The EEPROM Channel While the registers are being loaded from the EEPROM all accesses to the QSpan II by an external PCI bus master are terminated with a retry During this period write accesses to the EEPROM programmable registers from the QBus have no effect and reads return all zeros Some EEPROM device
222. ation cycle completes on the PCI bus when the QBus master attempts to access the DATA register at the same address the cycle completes successfully on the QBus In the case of a write write to CON DATA the cycle completes on the QBus after the Configuration write completes on the PCI bus Interrupt Acknowledge Cycle A mechanism is provided for a QBus register read to generate a PCI Interrupt Acknowledge cycle see Interrupt Acknowledge Cycle on page 121 QSpan II User Manual 8091862 001 08 7 5 Chapter 7 The Register Channel Register Access Synchronization QSpan II supports non simultaneous access to its registers from the QBus Interface and the PCI Interface This feature presents a synchronization issue QSpan II does not have the ability to lock out register accesses from one interface so that accesses can be performed on the other interface QSpan also does not have semaphore capabilities If a master on one interface is executing a test and set procedure reading from a register and then setting part or all of the register there is the possibility that between the test and the set a master on the other interface sets the same register This issue is most relevant to the Interrupt Control register see Table 120 on page 265 Figure 13 Example of a Register Access Synchronization Problem PCI Master QBus Processor 1 PCI master reads entire INT_CTL register liL m 2 QBus processor writes
223. ation port size of the external QBus slave QSpan II User Manual 97 8091862 001 08 Chapter 6 The DMA Channel 6 2 1 98 The three fields described in the previous paragraph are similar to the fields of the same name in PCI Target Image registers PBTIx_CTL The IWM field controls the burst size on PCI If the IWM is set to zero the burst length stored in the CLINE field which is stored in the PCI MISCO register is used The maximum burst size on PCI during DMA transfers is 128 bytes The QBus OFF OFF timer which is set in the CS register see Table 113 on page 254 limits the DMA Channel s access to the QBus during DMA transfers For large DMA transfers set this field to a non zero value to allow the PCI Target Channel regular access to the QSpan II s QBus master Depending on the value programmed in the Q OFF field the DMA Channel will not request the QBus for the programmed number of QBus clocks when the DMA transfer on the QBus crosses the following any 256 byte address boundary or a 64 byte boundary depending on the setting of Maximum DMA Burst Size on QBus MDBS bit in the CS register see Table 113 on page 254 To temporarily stop a DMA transfer in order to free up PCI bus or QBus bandwidth the DMA Stop STOP bit in DMA CS can be set see Table 113 on page 254 The DMA transfer is stopped once any active DMA transfers are completed Once the DMA is stopped on the PCI and QBus the STOP STAT
224. ations on the PCI bus are performed as a series of 8 bit write operations on the QBus QSpan II User Manual 8091862 001 08 Chapter 4 The PCI Target Channel 32 Bit QBus Port Tables 19 and 20 describe write transfers of various sizes to 32 bit peripherals on the QBus The following table describes mapping of 8 16 and 32 bit write transfers through the PCI Target Channel with the QBus set to Little Endian The byte lane ordering is preserved in Little Endian mode Table 19 Little Endian PCI Target Write Cycle Mapping 32 Bit QBus Port Transfer size BE 3 0 D 31 0 SIZ 1 0 A 1 0 D 31 0 9 s xw ome o9 oemem The following table describes mapping of 8 16 and 32 bit write transfers through the PCI Target Channel in Big Endian mode to 32 bit QBus peripherals The addressing of bytes is preserved in Big Endian mode Table 20 Big Endian PCI Target Write Cycle Mapping 32 Bit QBus Port Transfer size oe 9 0 BO B1 xx xx B2 B3 B2 B3 BO B1 B2 B3 0 0 0 1 1 1 1 1 1 0 QSpan II User Manual 69 8091862 001 08 Chapter 4 The PCI Target Channel 4 5 1 2 70 16 Bit QBus Port 16 bit QBus port transfers are explained in terms of the 32 bit transfers described in Tables 19 and 20 The first of these operations involves unpacking data A 32 bit write operation to a QBus peripheral with a 16 b
225. bit is set in DMA CS To restart a stopped DMA transfer the STOP bit must be cleared by writing a zero to the STOP bit The DMA Channel restarts from where it stopped once the STOP bit is cleared and the Q OFF counter has expired if this function is enabled The Command Packet Location CP LOC field is used during Linked List mode operation to determine if the command packets reside in QBus memory or PCI Bus memory All the command packets in a Linked List must reside in QBus memory or PCI Bus memory but not in both Burst Cycles The BURST 4 field in CS enables the QSpan II to generate burst cycles with four dataphases on the QBus This allows the QSpan II to work with the UPM of the MPC860 For DMA transfers that begin at an address that is not 16 byte aligned the QSpan II generates single QBus cycles until a 16 byte boundary is reached and then performs burst cycles For DMA wrrite transfers to the QBus which end at an address that is not 16 byte aligned the QSpan II generates single write cycles to finish the transfer For DMA read transfers on the QBus which end at an address not 16 byte aligned the QSpan II generates a burst cycle to the next 16 byte boundary for example prefetch data up to the next cacheline boundary and discards the extra data The Burst Enable BRSTEN field in IDMA DMA CS disables QBus burst cycles during DMA transfers when the QSpan II is MPC860 master This allows the QSpan II to operate in systems wh
226. biter is used FRAME Bidirectional s t s Cycle Frame for PCI Bus driven by the QSpan II when it is PCI master and is monitored by the QSpan II when it is PCI target This signal indicates the beginning and duration of an access 174 QSpan II User Manual 8091862 001 08 Chapter 16 Signals 16 6 PCI Bus Signals Continued PCI Grant As an input when the QSpan II uses an external arbiter it indicates to the QSpan II that it has been granted ownership of the PCI bus GNT can be parked at QSpan II to improve its PCI master performance As an output when the QSpan is the PCI bus arbiter it indicates to an external device that it has been granted access to the PCI bus IDSEL Input in PCI Initialization Device Select used as a chip select during configuration read and write transactions INT Bidirectional o d PCI Interrupt As an output it indicates that the QSpan is generating an internal interrupt As an input this signal will cause QINT to be asserted on the QBus bus if enabled The signal can be used as an input for an application where the MPC860 is the system host IRDY Bidirectional s t s Initiator Ready used by the QSpan II to indicate that it is ready to complete the current data phase of the transaction As PCI target the QSpan II monitors this signal during reads to determine when the PCI master is ready to accept data Bidirectional t s Parity parity is even across AD 31 0 and C
227. ble 1 Enable The QBSIO slave image is used when QSpan II is selected by the assertion of CSPCI_ and IMSEL Image Select is 0 It indicates among other things that the QSpan II does not burst to PCI I O space and responds to such attempts by generating a bus error on the QBus see Transaction Decoding and QBus Slave Images on page 39 Tables 134 to 137 indicate how the QSpan II Slave module responds to QBus masters as a function of the PWEN and PAS bits settings Values in this register except PREN can be programmed from a serial EEPROM for more information see Chapter 9 EEPROM Channel on page 123 If they are not their reset state is 0 QSpan II User Manual 285 8091862 001 08 Appendix A Registers Table 134 QSpan IT Response to a Single Read Cycle Access PREN Read Cycle R W_ negated Delayed Read Table 135 QSpan II Response to a Burst Read Cycle Access Read Cycle R W negated Delayed Read S 1 PA Delayed Read Write Cycle R W_ asserted Delayed Write Delayed Write 286 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 138 QBus Slave Image 0 Address Translation Register Register Name QBSIO_AT Register Offset F04 31 24 TA 23 16 TA QBSIO AT Description Reset Name Type Reset By State Function TA 31 16 R W E PCI RST See Translation Address Below BS 3 0 R W E PCI RST See Block Size 64 Kbyte 2P5 Below R W E PC
228. ble 90 PCI Bus Target Image 0 Address Register Register Name PBTIO_ADD Register Offset 104 PBTIO ADD Description Reset Name Type Reset By State Function BA 31 16 See PCI RST See below Base Address Below TA 31 16 G RST Lr Translation Address The Base Address specifies the contiguous PCI bus address line values compared by the QSpan II during PCI bus address phases The number of address lines compared for this image is based on the Block Size programmed in the PBTIO_CTL register on Table 89 on page 224 The Translation Address specifies the values of the address lines substituted when generating the address for the transaction on the QBus If no translation is to occur the Translation Address must be programmed with the same value as that of the Base Address see Transaction Decoding on page 61 and Address Translation on page 42 for more details 226 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 91 PCI Address Lines Compared as a Function of Block Size 7 e Block Size Compared Translated The read write type and reset value of the BA 31 16 field depends on whether the PCI BSTO register see Table 75 on page 210 is enabled for example whether bit 5 of byte 7 of the EEPROM is 1 or power up pin PCI DIS is latched high during PCI reset There are two cases 1 Ifthe EEPROM bit is 1 or PCI DIS is latched high the BA field of PBTIO_ADD is read only and has the same val
229. bus do not affect its contents 214 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 80 PCI Configuration Expansion ROM Base Address Register Register Name PCI_BSROM Register Offset 030 31 24 BA 23 16 BA IIO Ie 0 epe PCI_BSROM Description Reset Name Type Reset By State Function BA 31 16 See PCI_RST See Expansion ROM Base Address Below Below EN See PCI_RST Enable Address Decode Below 0 Disable 1 Enable The number of writable bits in BA 31 16 determines the size of the external QBus Expansion ROM for more information see the PCI Local Bus Specification 2 2 The number of bits itself is determined by the Block Size field of the PCI Expansion ROM Control register see PBROM_CTL on page 232 After power up a PCI host can write all 1s to the BA field of this register The number of 1s that are read back will indicate the size of the Expansion ROM of the QSpan II This register is enabled if bit 7 of byte 5 of the EEPROM is latched as 1 see Table 44 on page 127 If the state of this bit is 0 or if the state of the SDA pin or pin is latched as low during PCI reset then all bits in the entire register will be set to 0 and will be read only QSpan II User Manual 215 8091862 001 08 Appendix A Registers The PCI Expansion ROM Base Address register can be written from either bus if write enabled except whi
230. c parameters see Figure 2 QCSR space is accessible from the PCI bus and the QBus An internal arbitration mechanism grants access to the QCSRs The access mechanisms for the QCSRs including the arbitration protocol differ depending on whether the registers are accessed from the PCI bus or the QBus QSpan II User Manual 33 8091862 001 08 Chapter 2 Functional Overview 2 7 2 8 34 PCI Configuration cycles can be generated from the QBus by accessing II registers The cycles proceed as delayed transfers for information see Chapter 7 The Register Channel on page 105 The Interrupt Channel QSpan II can generate interrupts based on hardware or software events see Figure 2 Two bidirectional interrupt pins are provided one on the PCI Interface the other on the QBus Interface Interrupt registers track the status of errors They also allow users to enable clear and map errors Interrupts can be generated using one of the four available software interrupt sources for information see Chapter 8 The Interrupt Channel on page 115 QSpan II also contains four mailbox registers which can be used for message passing for information see Mailbox Registers on page 114 These mailbox registers can generate an interrupt when data is written to them The EEPROM Channel Some of QSpan II s registers can be programmed by data in an EEPROM at system reset This allows board designers to set identifiers
231. cheme 143 Figure 21 CompactPCI Hot Swap Functional Diagram 146 Figure 22 Hot Swap Card Insertion 149 Figure 23 Hot Swap Card 151 Figure 24 Reference Voltages for AC Timing 302 Figure 25 QCLK Input Timing 68360 317 Figure 26 QBus Arbitration 68360 317 Figure 27 Single Read QSpan as MC68360 Master 318 QSpan II User Manual 15 8091862 001 08 List of Figures Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Single Write QSpan II as MC68360 319 Delayed Single Read QSpan as MC68360 Slave 320 Single Write QSpan II as MC68360 Slave 321 Register Read QSpan as MC68360 51
232. cified by the Inbound Post List Top Pointer Accesses to this register result in retries from the time of the PCI write until the write completes on the QBus PCI reads to this register return data from the Inbound Free List FIFO located in Qbus memory on the QBus at the address specified by the Inbound Free List Bottom Pointer A value of OXFFFF FFFF is returned if the Inbound Free List FIFO is empty 298 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 153 ILO Outbound Queue Register Register 2 Register Offset 044 31 24 OUT_Q I20_OUTQ Description Reset Name Type Reset By State Function OUT QI31 0 R WP RST IO Outbound Queue This register controls the host processor access to the outbound queue The 32 bit value written into this register is written by QSpan II to the Outbound Post_List FIFO which is located in Qbus memory at the address specified by the Outbound Post_List Top Pointer Accesses to this register result in retries from the time of the PCI write until the write completes on the QBus PCI reads to this register return data from the Outbound Free_List FIFO located in Qbus memory on the QBus at the address specified by the Outbound Free_List Bottom Pointer A value of OXFFFF FFFF is returned if the Outbound Free_List FIFO is empty QSpan II User Manual 299 8091862 001 08 Appendix A Registers 300 QSpan II User Manual 8091862 001 08 Appe
233. cle and generate an interrupt back to the PCI master or the QBus processor See Terminations of Posted Writes on page 84 for an explanation of error recording in the PCI Target channel Table 167 QBus Error Logging Programming Summary QB ERRCS Indicates if a failed cycle is currently logged Logs the 32 bits of data for the failed transaction Similarly error logging can be enabled for the QBus Slave Channel see the following table Table 168 PCI Bus Error Logging Programming Summary PB ERRCS Indicates if a failed cycle is currently logged Enables error logging UNL 28 Allows the PCI Interface to serve the QBus Slave Channel after an error is logged QSpan User Manual 385 8091862 001 08 Appendix D Software Initialization D 6 IDMA DMA Channel Initialization The IDMA DMA Channel has a single FIFO which can perform burst writes or burst reads on the PCI Bus During an IDMA cycle the QSpan II is an IDMA peripheral while either the MC68360 or the MPC860 is the bus master of the cycle The MC68360 or the MPC860 must program three registers in order to initiate an IDMA transfer During DMA transfers the QSpan II is the master on both the QBus and the PCI Bus See Chapter 5 The Channel on page 85 and Chapter 6 DMA Channel on page 95 for more information about register programming Table 169 IDMA DMA Channel Programming Summary IDMA ADDR 31 2 The starting address
234. completed before the following write can be posted The Qr FIFO is a 32 byte buffer which stores data read from PCI Targets PCI Master Module The PCI Master Module is a 32 bit 33MHz PCI 2 2 Specification compliant master interface PCI signals supported by the QSpan are outlined in PCI Bus Signals on page 174 QSpan II masters the PCI bus through its PCI Master Module The PCI Master Module is available to the QBus Slave Channel access from a remote QBus master and the IDMA DMA Channel Channel Description The operation of the QBus Slave Channel is described in the following sections by tracing the path of a transaction from the QBus to the PCI bus This is completed by dividing a transaction into three phases e Address Phase This section describes transaction decoding and how address information from the QBus is passed to a corresponding address space on the PCI bus e Data Phase This section describes endian mapping and byte lane translation through the QBus Slave Channel This section also describes the methods that data is buffered in the QBus Slave Channel depending on the programming of the QBus Slave images e Termination Phase This section discusses how terminations from a PCI target are communicated to the master on the QBus It also describes how the QSpan II PCI Master Module handles terminations for example retries or Target Aborts We also describe the terminations the QSpan II issues as a QBus slave dev
235. ctional See BB BDIP Input MC68360 mode Bidirectional MPC860 Burst Data In Progress On the MC68360 interface this pin is used only to determine the QBus master mode of the QSpan II This is determined at reset by sensing the level of this pin If BDIP_ is sampled as low at power up or reset the QBus master module will operate as an MC68360 master If the BDIP_ signal is sampled as high at power up or reset the QSpan II will operate as an MPC860 master see Table 48 on page 158 QSpan II User Manual 163 8091862 001 08 Chapter 16 Signals 16 3 MC68360 Signals QUICC Continued BERR TEA Rescinding tristate birectional pin Bus Error used to indicate a bus error that occurs during a transaction It can be used in conjunction with HALT TRETRY to indicate a busy retry to the bus master As an MC68360 master the QSpan II samples BERR TEA on the falling edge of QCLK during cycles in which it is a QBus master As an MC68360 slave BERR TEA is driven by the QSpan II from the falling edge of QCLK QSpan II negates BERR TEA prior to tristate Bus Grant indicates that the QSpan II may become the next QBus master BG along with BR and BB BGACK provide the three wire handshake for QBus arbitration BG is doubled sampled on the falling edge of QCLK QSpan II can be programmed to use a synchronous mode for QBus arbitration BM EN FIFO RDY Bidirectional Bus Master Enable FIFO Ready If
236. ctly connected to the appropriate PCI signal on the motherboard or the PCI connector Pull up resistors may be required to be added to the PCI bus control signals depending on the application If you are designing a local PCI bus on a motherboard then pull up resistors will be required for more information see the PCI Specification 2 2 For host bridging applications possible implementations for the QSpan II s IDSEL signal are as follows e connect it to a spare AD signal AD 31 12 connect it to ground through a resistor if the host is not required to respond to PCI configuration cycles The QSpan II supports both 5V and 3 3V I O signaling environments Vy Highest I O voltage must be connected to the highest voltage level the QSpan II I Os will observe on either the QBus or the PCI bus 2 1 7 EEPROM Interface A serial EEPROM may be required for applications which must support a Plug and Play environment for more information about EEPROM reset options see Reset Options on page 365 QSpan II also allows that QBus processor to initialize the QSpan II to support a Plug and Play environment for more information see EEPROM Configuration and Plug and Play Compatibility on page 125 C 2 1 8 Reset Options A number of reset options exist with the QSpan II device The following signals are sampled on the rising edge of both RST and RESETI and the falling edge of HS HEALTHY to determine the QSpan II s mode of operation e
237. d QSpan II User Manual 8091862 001 08 Chapter 4 The PCI Target Channel Table 27 MC68360 Cycle Terminations of QBus Master Module DSACKO0 DSACKI TA _ BERR TEA HALT TRETRY Termination Asserted Negated Negated Don t Care Bus Error Don t Care Don t Care Asserted Asserted Negated Don t Care Don t Care Negated Asserted Negated Negated Retry Don t Care Don t Care Asserted Asserted Don t Care Asserted Don t Care Don t Care Negated Asserted Don t Care Asserted to First sample on falling edge of QCLK t Second sample on falling edge of QCLK a QSpan II as QBus master will sample DSACKx 2 QCLK rising edges after HALT negation 4 8 3 MPC860 Cycle Terminations When MPC860 transfers are completed BB_ BGACK_ is negated by the QBus Master Module on the rising clock edge and tristated on the next falling clock edge to terminate the transaction currently in progress see Table 28 Table 28 860 Cycle Terminations of QBus Master Module 4 8 4 M68040 Cycle Terminations When M68040 transfers are completed BB_ BGACK_ is negated by the QBus Master Module on the rising clock edge and tristated on the next falling clock edge see Table 29 Table 29 M68040 Cycle Terminations of QBus Master Module Termination Type DSACKI TA BERR TEA QSpan II User Manual 81 8091862 001 08 Chapter 4 The PCI Target Channel 4 8 5 4 8 5 1
238. d PCI VPD Register 222 VPD DATA field PCI VPD Register 223 VPD F bit PCI VPD Register 222 W WAIT bit PCI CS Register 204 426 QSpan II User Manual 8091862 001 08 CORPORATE HEADQUARTERS for SALES for Tech Support 6024 Silver Creek Valley Road 800 345 7015 or 408 284 8200 email EHBhelp idt com San Jose 95138 fax 408 284 2775 phone 408 360 1538 m www idt com Document 8091862_MA001_08 DISCLAIMER Integrated Device Technology Inc IDT and its subsidiaries reserve the right to modify the products and or specifications described herein at any time and at IDT s sole discretion All information in this document including descriptions of product features and performance is subject to change without notice Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products The information contained herein is provided without representation or warranty of any kind whether express or implied including but not limited to the suitability of IDT s products for any particular purpose an implied warranty of merchantability or non infringement of the intellectual property rights of others This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties IDT s products are not intended for use in life support
239. d see Table 133 on page 285 and Table 140 on page 289 The level of IMSEL determines which QBSIx_CTL register is used see Transaction Decoding and QBus Slave Images on page 39 If the PWEN bit is cleared this is the default setting single write transactions are treated as delayed transactions Burst write transfers are always treated as posted writes Both posted and delayed writes travel through the Qx FIFO With posted writes data acknowledgment is provided on the QBus as soon as the write data is queued in the Qx FIFO Multiple posted writes can be queued up to the 256 byte capacity of the Qx FIFO With delayed writes data acknowledgment is provided on the QBus after completion on the PCI bus This means only one delayed write at a time Additional writes are retried while a delayed write is in progress QSpan II User Manual 8091862 001 08 Chapter 3 The QBus Slave Channel Posted write transfers are stored in the Qx FIFO Address and data are stored as separate entries in the Qx FIFO For example one single cycle data beat transaction is stored as two Qx FIFO entries one entry for the address of the transaction and one for the data The address entry contains the translated PCI address space and command information mapping relevant to the QBus Slave Image which is accessed see Address Phase on page 39 The data entry contains the data and the byte enables Thus any reprogramming of QBus Slave Image attributes
240. d from QCLK positive edge 7 t315 t3154 BG hold from QCLK positive edge t315e BURST hold from QCLK positive edge CSPCI hold from QCLK positive edge 5 t315f Mi 4 4 5 5 0 0 0 CSREG_ hold from QCLK positive edge 315g t315h D hold from QCLK positive edge a t315i IMSEL hold from QCLK positive edge o A Al a E R W hold from QCLK positive edge 6 9 1315 1 3 7 5 7 7 3 0 0 2 t315k SIZ hold from QCLK positive edge 1 2 N t3151 TA_ hold from QCLK positive edge TC hold from QCLK positive edge 5 315m 2 TEA_ hold from QCLK positive edge 0 t315n 0 TRETRY hold from QCLK positive edge t3150 t315p TS_ hold from QCLK positive edge BI DE s 7 TEM PII AMEN D tristated from QCLK positive edge 15 2 E 1316 ojo N D enabled from QCLK positive edge 15 2 t317 QSpan User Manual 309 8091862 001 08 Appendix B Timing Table 155 Timing Parameters for MPC860 Interface Continued Frequency Temperature Options EN EN EN 99 50 501 40 Timing Parameter Description M M M Max Units Note t334 D valid master writes from QCLK 1 positive edge tristated from QCLK negative edge 1335a 5 TEA tristated from QCLK negative edge P t335b TRETRY tristated from QCLK negative
241. d into the I FIFO for one PCI transfer The table also shows the order in which the 16 bit QBus cycles appear QSpan II User Manual 93 8091862 001 08 Chapter 5 The IDMA Channel Table 33 16 Bit Little Endian IDMA Cycle Mapping PCI bus First 16 bit transfer 2 Full 32 bit PCI bus Transfer Second 16 bit transfer BO xx xx 0000 B3 B2 B1 BO The following table describes mapping of 16 bit QBus transactions in Big Endian mode The addressing of bytes is preserved in Big Endian mode During a read transaction a full 32 bit PCI transaction is unpacked into two 16 bit QBus transfers During a write transaction two 16 bit QBus transactions are packed into the I FIFO for one PCI transfer The table also shows the order in which the 16 bit QBus cycles appear Table 34 16 Bit Big Endian IDMA Cycle Mapping PCI bus QBus Timing SIZ 1 0 A 1 0 D 31 0 BE 3 0 D 31 0 First 16 bit transfer BO B1 xx xx Full 32 bit PCI bus Transfer Second 16 bit transfer B2 B3 xx 0000 B3 B2 B1 BO The following table describes mapping of 32 bit QBus transactions in Little Endian mode The byte lane ordering is preserved in Little Endian mode Table 35 32 Bit Little Endian IDMA Cycle Mapping PCI bus SIZ 1 0 A 1 0 D 31 0 BE 3 0 D 31 0 The following table describes mapping of 32 bit QBus transactions in Big Endian mode The addressing of bytes is preserved in Big Endian mode Table
242. dd a sequential numeric digit For example the first prototype version of device would have a Z a second version would have 271 so on The prototype version code is dropped once the product reaches production status 409 Appendix H Ordering Information 410 QSpan II User Manual 8091862 001 08 Glossary CompactPCI Cycle DMA Master QBus Slave Slave Image Target image QSpan II User Manual 8091862 001 08 CompactPCI is an adaptation of the PCI Specification for Industrial and embedded applications requiring a more robust mechanical form factor than desktop PCI Cycle refers to a single data beat a transaction is composed of one or more cycles Direct Memory Access A process for transferring data from main memory to a device without passing it through the Host processor Master initiator is the owner of the PCI bus Itis used for both the QBus and the PCI bus QBus is a generic term which refers to the interface between the QSpan II and the Host processor bus to which QSpan II is connected Slave target is the device which is accessed by the bus master It is reserved for addresses accessed by PCI masters Slave image is a memory range which is mapped on the QBus Host processor bus Two slave images reside in the QSpan II QBus Slave Channel Target image is a memory range which is mapped on the PCI bus Two target images reside in the QSpan II PCI Target Channel Glossary
243. delayed transactions During a delayed write transaction the PCI master is retried until the transaction completes on the QBus If the PCI transaction completes normally on the QBus then when the PCI bus master retries the same transaction qualified by the latched address and command information the original PCI master is given a normal cycle termination If the QBus transaction does not complete normally then the appropriate termination is communicated back to the PCI master see Terminations on page 80 QSpan II User Manual 75 8091862 001 08 Chapter 4 The PCI Target Channel 4 5 2 3 4 5 2 4 76 Single Read Transactions When the QSpan II receives a target read request it latches the address and C BE information and retries the PCI master QSpan then becomes QBus master and initiates a read on the QBus The external PCI master is retried until the read is completed on the QBus When the external PCI master retries the same transaction qualified by the latched information it is provided with the data and the transaction terminates normally on the PCI bus If the QBus transaction does not complete normally then the appropriate termination is communicated back to the PCI bus master see Terminations on page 80 Prefetched Read Transactions QSpan supports different prefetch data amounts based on the PCI target image accessed during a read of the PCI Target Channel QSpan II initiates a prefetch re
244. dian Mapping E 4 2 Data Invariance The second approach is data invariance which preserves the relative byte significance but translates the byte addressing The following figure shows that with data invariance Byte 0 is still the most significant byte in the data structure but is now located at address 03 in memory rather than address 00 Figure 83 Data Invariant Mapping Motorola Big Endian Byte Lanes PCI Little Endian Byte 0 MSB oc eL Byte 3 Byte 2 Byte 1 Byte 0 LSB MSB 00 B 3 B 1 0 03 02 01 00 E 4 3 Combined Method By enforcing certain constraints on the system it is possible to implement both options in a PCI to Motorola bridge By assuming that all data structures are 32 bit integers the bridge could be powered up in either of these mapping modes In address invariant mode byte lanes would be swapped independent of the data path width assuming that the bytes are part of a 32 bit word In data invariant mode the byte lanes would be passed straight through assuming that the bytes are again part of a 32 bit word QSpan II User Manual 395 8091862 001 08 Appendix E Endian Mapping 396 QSpan II User Manual 8091862 001 08 Appendix F Operating and Storage Conditions This appendix discusses operating and storage conditions for the QSpan II The following topics are discussed e Power Dissipation on page 397 e Operating Conditions on page 398 e Thermal Characteri
245. dress Space 0 Memory Space This register is at this location when the I 0 messaging unit in the QSpan II is not used the I20 EN bit is set to 0 in the I2O CS register If the I 0 messaging unit is enabled this register is moved to offset 018 and PCI BSTO register from offset 018 is moved to this offset and renamed I20 BAR This register specifies the 4 Kbyte aligned base address of the QSpan II register space on PCI in Memory Space The QSpan II register space is 4 Kbytes therefore the PCI address lines 11 0 are used to select the QSpan II register A write must occur to this register before the QSpan II register space can be accessed from the PCI bus This write can be performed with a PCI configuration transaction or a QBus register access 208 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 74 1 0 Base Address Register Register Name I2O BAR Register Offset 010 23 16 CIL TI I LDILITAI I20 BAR Description Reset Name Type Reset By State Function BA 31 12 ESAE NONE EMI ANNE Base Base Address 000000000000 SPACE PCI Bus Address Space 0 Memory Space This register is at this location when the messaging unit in the QSpan II is enabled the I2O_EN bit is set to 1 in I2O CS register When the I2O EN bit is set the first Base address register must provide a window to the QBus memory space Essentially the PCI BSTO register is moved from register offset 018 to 010 see Tabl
246. dress Space PAS and Prefetch Read Enable PREN bits in the QBus Slave Image Control Registers see Table 133 on page 285 or Table 140 on page 289 The following table lists the C BE encoding supported by the QSpan II Table 6 Command Type Encoding for Transfer Type C BE 3 0 Command Type QSpan II Capability 0000 Interrupt Acknowledge See Interrupt Acknowledge Cycle on page 121 a These commands are aliased to a memory read b This command is aliased to a memory write QSpan II User Manual 45 8091862 001 08 Chapter 3 The QBus Slave Channel PCI Targets are expected to assert DEVSEL if they have decoded the access If a target does not respond with DEVSEL within 6 clocks a Master Abort is generated by the QSpan II The following shows the mapping from QBus transaction type to PCI transaction type as a function of PAS programming Table 7 Translation from QBus Transaction to PCI Transaction Type QBus transaction received PAS bit programming PCI transaction type Single or Burst Read Memory Read a In this case an error is signaled on the QBus 3 5 Data Phase This section describes how endian mapping is executed in the QBus Slave Channel It also discusses the data path for different transaction types 351 Endian Mapping The PCI bus and Motorola processors differ in the way they order and address bytes These differences are explained in Appendix E Endian Mapping on page 391 This section describe
247. e 100 on page 238 This bit moves the PCI BSM register to offset O18h 4 Clear the I20 EN bit Enable PCI access by clearing the PCI DIS bit in the MISC CTL2 register This allows the PCI Host to create the PCI memory map The QBus processor initializes the 1 0 Messaging Unit Set the I2O EN bit to 1 388 QSpan II User Manual 8091862 001 08 Appendix D Software Initialization D 11 PCI Expansion ROM Implementation An Expansion ROM can be implemented on the QBus which will contain additional information for the PCI host In order for the PCI host to be able to read from this ROM the base address of this image must be programmed This address can be programmed from an external serial EEPROM Table 171 PCI Expansion ROM programming PBROM_CTL DSIZE 1 0 This field defines the size of the Expansion ROM read only field programmed by serial EEPROM BS 2 0 This field defines the block size of the Expansion ROM image read only programmed by serial EEPROM TC 3 0 This field defines how the QSpan II drives the TC lines read only programmed by serial EEPROM TA 31 16 This field defines the Translation Address field read only programmed by serial EEPROM QSpan II User Manual 389 8091862 001 08 Appendix D Software Initialization 390 QSpan II User Manual 8091862 001 08 Appendix E Endian Mapping This appendix explains Endian Mapping for the QSpan II and Motorola processors The following topics are
248. e 123 Mailbox 0 Register Register Name MBOX0 Register Offset 700 31 24 MB_DATA 23 16 MB_DATA 15 08 MB_DATA 07 00 DATA 0 Description Reset Name Type Reset By State Function MB_DATA GEN_RST al MailBox Data 31 0 272 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 124 Mailbox 1 Register Register Name MBOX1 Register Offset 704 31 24 MB_DATA 23 16 MB_DATA 15 08 MB_DATA 07 00 MB_DATA MBOX Description Reset Name Type Reset By State Function MB_DATA GEN_RST Data 31 0 QSpan II User Manual 273 8091862 001 08 Appendix A Registers Table 125 Mailbox 2 Register Register Name MBOX2 Register Offset 708 31 24 MB_DATA 23 16 MB_DATA 15 08 MB_DATA 07 00 MB_DATA MBOX2 Description Reset Name Type Reset By State Function MB_DATA GEN_RST al MailBox Data 31 0 274 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 126 Mailbox 3 Register Register Name MBOX3 Register Offset 70C 31 24 MB_DATA 23 16 MB_DATA 15 08 MB_DATA 07 00 MB_DATA MBOX3 Description Reset Name Type Reset By State Function MB_DATA GEN_RST Data 31 0 QSpan II User Manual 275 8091862 001 08 Appendix A Registers Table 127 Miscellaneous Control and Status Register Register Name MISC_CTL Register Offset 800 31 24 SW_RST Reserved i Cue i ODE i PRCNT 5 0 MSTSLY
249. e 155 H8 HEALTHY should be left open as it has an internal pull down resistor For a CompactPCI adapter card that supports Hot Swap use the following reset configuration the QSpan I s H8 HEALTHY input should be connected to the Hot Swap Controllers HEALTHY output Also connect the QSpan II s reset output RESETO to the hard reset input RESETH_ on the MC68360 This enables the QSpan II to reset the MC68360 when PCI RST is asserted or when the software reset bit is asserted SW bit in the MISC register on Table 127 on page 276 QSpan II s reset input RESETI is typically unused and should be pulled high through a resistor C 1 1 3 Memory Controller QSpan II requires that two chip selects be generated in order to access the registers 5 and the PCI bus CSPCI This is accomplished by using two of the chip select outputs from the memory controller within the MC68360 There are two QBus slave images in the QSpan II which are used to access the PCI bus The image that is selected when the PCI chip select is asserted depends upon the state of the Image Select signal IMSEL If IMSEL is low then QBus slave image 0 is selected otherwise QBus slave image 1 is selected IMSEL is typically generated directly from one of the high order address lines on the QBus for example dependent on the processor s memory map An alternative method is to use a spare I O port pin on the MC68360 processor to control the QSpan II s
250. e 75 for more information about the programming options The lower 4K of this space is reserved The region above this space provides a window to the QBus memory QSpan II User Manual 209 8091862 001 08 Appendix A Registers Table 75 PCI Configuration Base Address for Target 0 Register Register Name PCI BSTO Register Offset 018 31 24 23 16 07 00 PCI_BSTO0 Description Reset Name Type Reset By State Function BA 31 16 PCI RST Base Address of PCI bus Target Image 0 Below PREF R WQ E PCI_RST See Prefetchable Below 0 Not Prefetchable 1 Prefetchable reads have no side effects PAS PCI_RST See PCI Bus Address Space Below 0 Memory Space 1 T O Space This register is enabled if the state of the SDA pin or ENID pin is latched as high during PCI reset and bit 5 of byte 7 of the EEPROM is 1 for information see Mapping of EEPROM Bits to QSpan II Registers on page 126 This register is also enabled if the power up option PCI DIS is latched high during Reset If this register is not enabled for example there is no EEPROM or bit 5 of byte 7 of the EEPROM is 0 the entire register is read only and reads return all Os If enabled this register specifies the Base Address and PCI Bus Address Space settings for PCI Bus Target Image 0 The Base Address is used during transaction decoding it specifies the contiguous PCI bus address line values compared by the QSpan II during PCI bus address
251. e o Re td 35 3 2 QBus Slave Channel Architecture 36 3 21 Slave 37 QSpan II User Manual 5 8091862 001 08 Contents 3 2 1 1 QBus Data Parity Generation and 37 3 2 2 OX FIFO and andi ad d e eR e bok woke 38 3 2 3 PCI Master bera ee dae ERES 38 3 3 Channel Description 22 22 2 2 2 4 4 Red RR EL EI oe es 38 2 4 Address Phase oed Slee oy P ue eS bg rtr t e 39 3 4 1 Transaction Decoding and QBus Slave Images 39 3 4 1 1 MPC860 Cycles i ses ana ee ada 41 3 4 1 2 68360 Cycles 41 3 4 1 3 M69040 Cycles see es re ena e ta er aa hac 41 342 PCEBus Request 5 x Ea 42 3 4 3 Address Translation 5 42 3 4 4 Address Phase on the 45 9 Data Se ee PUn ds 46 3 5 Mapping S TR ER opa 46 292 Data Path tu ed ave RODA S sath SU Un SARS 48 3 9
252. ed on the QBus only the valid byte on the data bus is checked for example D 31 24 Channel Description The operation of the PCI Target Channel is described in the following sections by tracing the path of a transaction from the PCI bus to the QBus This is completed by dividing a transaction into the following components e Address Phase This section describes how PCI bus accesses are decoded and how address information from the PCI bus is passed through to the QBus e Data Phase This section describes endian mapping and byte lane translation through the PCI Target Channel e QBus Arbitration and Sampling This section describes QBus arbitration e Terminations This section explains how terminations from the QBus are communicated back to the master on the PCI bus It describes how the PCI Target Module handles different terminations for example retries or target aborts This section also explains the conditions that drive the terminations the QSpan II issues as a PCI target and error logging mechanisms for posted writes QSpan II User Manual 8091862 001 08 Chapter 4 The PCI Target Channel 4 4 Address Phase 4 4 1 Transaction Decoding All decoding by the PCI Target Module is based on the address and command information produced by a PCI bus master The PCI Target Module claims a cycle if there is an address driven on the PCI bus that matches an image programmed into the PCI Target Image registers The parameters of
253. egister are processed as delayed transfers The QSpan II does not perform byte swapping of data in the Register Channel regardless of whether the QBus is configured as big or little endian Bit 31 in the register is bit 31 on the QBus regardless of the QB_BOC bit in the MISC_CTL register see Table 127 on page 276 Therefore software on the QBus may need to swap the data when performing configuration cycles The QSpan II generates a bus error upon a register access to the CON_DATA register if the bus master BM bit in the PCI_CS register is 2 not set 260 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 118 IACK Cycle Generator Register Register Name Register Offset 508 31 24 IACK VEC IACK GEN Description Reset Name Type Reset By State Function IACK VEC EN EM PCI IACK Cycle Vector 31 0 This register generates an Interrupt Acknowledge cycle originating on the QBus Reading this register from the QBus causes an IACK cycle to be generated on the PCI bus The byte lanes enabled on the PCI bus are determined by SIZ 1 0 and A 1 0 of the QBus read The address on the QBus used to access the GEN register is passed to the PCI bus during the PCI IACK cycle Address information however is ignored during PCI IACK cycles so this has no effect Reads from this register act as delayed transfers This means that the QBus master is retried until the read data is latched from the
254. either CSPCI or CSREG asserted If BURST TIP is asserted at the beginning of the bus cycle along with the address the QSpan II accepts the incoming cycle as a burst During bursts the QSpan II monitors BDIP_ which when negated indicates the current data phase is second last When the QSpan II operates as an MPC860 slave for non IDMA transfers it functions as a 32 bit peripheral and must be addressed as a 2 32 bit peripheral External QBus masters must comply with the MPC860 timing specification 3 4 1 2 MC68360 Cycles QSpan II behaves as a MC68360 slave in response to the assertion of the Address Strobe AS_ signal When it receives AS_ it asserts a subset of DSACK1_ TA_ DSACKO_ BERR_ TEA_ and HALT_ TRETRY_ QSpan II acknowledges the transaction if either CSREG_ or CSPCI_ is sampled active in conjunction with AS_ QSpan II does not require that the input signals qualified by AS_ be valid when AS_ is asserted it requires only that they meet the set up time before the same falling clock edge when AS_ is first sampled asserted When the QSpan II operates as a MC68360 slave it functions as a 32 bit peripheral in synchronous mode As a master the QSpan II also operates synchronously and therefore the Bus Synchronous Timing mode BSTM bit in the MC68360 must be set to 1 for more information see the Motorola MC68360 User s Manual External QBus masters must comply with the MC68360 timing specification 3 4 1 3 M68040 Cycles Q
255. en the Outbound Post List FIFO contains MFAs for example when the Outbound Post List FIFO is not empty The interrupt can be masked by setting the IM bit in I2O OPIM register The corresponding status bit is in 2 OPIS register A copy of this status bit is also provided in the INT STAT register To generate QBus interrupt when new MFA is posted into the Inbound Post List FIFO set the EN bit in INT see Table 120 on page 265 If the interrupt is generated the IPN IS status bit is set The QBus interrupt can be negated by writing a 1 to the IPN IS status bit The following four conditions can also cause external interrupts Inbound Free List FIFO empty Outbound Free List FIFO empty Inbound Post List FIFO full and Outbound Free List FIFO full These interrupts are enabled by setting the corresponding bits in the INT CTL and INT DIR registers QSpan II User Manual 139 8091862 001 08 Chapter 10 1 0 Messaging Unit 140 QSpan II User Manual 8091862 001 08 Chapter 11 PCI Bus Arbiter This chapter explains the QSpan II s PCI bus arbiter The following topics are discussed e Arbitration Scheme on page 142 e Bus Parking on page 144 11 1 Overview QSpan II has an integrated PCI bus arbiter with dedicated support for the QSpan II PCI master and up to seven external Masters see Figure 19 The PCI bus arbiter uses a fairness algorithm to prevent deadlocks QSpan II s PCI bus arbite
256. endix B Timing Table 157 Timing Parameters for Interrupts and Resets Timing Parameter Description Units Note RETO wim CERI e s Table 158 Timing Parameters for Reset Options All Parts Timing Parameter Description Max Units Note 1 1 5021 setup to RESETI_ RST rising edge setup to RESETI_ or RST rising 51211 setup to RESETI_ or RST rising edge toog TMODE 1 setup to RESETI or RST rising edge 2 E 0 7 CMS UNS 5 5 N N a 1 a Un tA N nlo wo walolol l o N a n n n n n n n n n n n n n n n n N UA QSpan II User Manual 315 8091862 001 08 Appendix B Timing Table 158 Timing Parameters for Reset Options Continued All Parts Timing Parameter Description Units Note PCI DIS hold from RESETI_ or RST rising edge HHE PCI_ARB_EN setup to RESETI_ or RST rising edge EAESES3ES PCI ARB EN hold from RESETI or RST rising edge 25 on fo 1 These setup and hold times also apply to the falling edge of 5 HEALTHY B 3 Wait State Insertion QBus Slave Module The following wait state list does not apply to IDMA transfers QSpan II as QBus slave inserts wait states as follows e One wait state for all retried cycles e One wait state for burst wr
257. eported if Parity Error Response PERESP and SERR Enable SERR EN are set in the PCI CS register see Table 70 on page 203 Address parity errors are reported by the QSpan II by asserting the SERR signal and setting the S SERR signaled SERR bit in the PCI CS register Assertion of SERR can be disabled by clearing the SERR_EN bit in the PCI CS register An interrupt may be generated and regardless of whether assertion of SERR is enabled or not the QSpan II does not respond to the access with DEVSEL Normally the master of the transaction terminates the cycle with a Master Abort The PERESP bit in the PCI CS register affects how the QSpan II responds to PCI parity errors If the PERESP bit and the SERR EN bit are set the QSpan II reports address parity errors by asserting SERR and setting the S SERR bit in the PCI CS register If the PERESP bit is set the QSpan II reports data parity errors during writes by asserting PERR Reads and PCI Transaction Ordering PCI Transaction Ordering rules affect the relationship between delayed reads in the PCI Target Channel and posted writes in the PCI Target Channel These rules also affect the relation between delayed reads in the PCI Target Channel and posted writes in the QBus Slave Channel When a read request is latched the PCI Target Module retries non register accesses to the PCI Target Module until the read completes on the QBus Once the read completes on the QBus the QSpan II ens
258. equent reads retrieve the data from the Qr FIFO Delayed transactions both reads and writes require data acknowledgment on the PCI bus before data acknowledgment is provided on the QBus PCI Memory and I O spaces are accessible through two Slave images associated with the QBus Slave Channel Configuration space is accessible through the CON_DATA register see Table 117 on page 260 The QBus Slave images are selected using a pair of chip select signals on the QSpan II for information see Chapter 3 QBus Slave Channel on page 35 QSpan II User Manual 8091862 001 08 2 3 2 4 2 5 2 6 Chapter 2 Functional Overview The PCI Target Channel The PCI Target Channel transfers data between the PCI bus and the QBus see Figure 2 It supports posted writes to ensure zero wait state bursting prefetched reads and delayed single reads and writes The 256 byte Px FIFO supports the queuing of long PCI burst writes Delayed reads and writes must complete on the QBus before data acknowledgment occurs on the PCI bus Reads are executed as delayed transactions but the QSpan can be configured to prefetch read data Prefetched reads are queued in a 256 byte Pr FIFO QSpan provides two programmable Target images on the PCI bus These images can be mapped anywhere in Memory or I O space for information see Chapter 4 PCI Target Channel on page 57 The IDMA Channel QSpan II can operate as a
259. er If error logging is enabled with UNL_QSC set to 1 and the QBus Slave Channel is errored the QSpan II s PCI bus Master interface is not halted However the error logs are frozen with the first failed transaction until the status bit is cleared If error logging is not enabled and the QBus Slave Channel incurs an error while dequeuing data the errored transfer is lost and the Qx FIFO operation continues with the next enqueued transfer An interrupt will be generated upon the logging of an error ES bit in PB ERRCS only if the PCI Bus Error Log Interrupt Enable PEL EN bit in the INT register is set see Table 119 on page 262 If generated the interrupt is directed to the QBus or the PCI bus depending on the PCI Error Log Interrupt Direction PEL DIR bit in the INT DIR register see Table 121 on page 268 Interrupts are described in Chapter 8 The Interrupt Channel on page 115 PCI Master Retry Counter QSpan PCI master limits the number of times a cycle is repeated on the PCI bus due to an external PCI target terminating the cycle with a retry QSpan II can be programmed to accept the following number of retires 128 256 384 or indefinitely depending on the setting of the MAX_RTRY in the MISC CTL2 register see Table 130 on page 280 Once the maximum number of retries is completed the QSpan II discards the cycle and terminates the cycle on the QBus Read cycles and delayed write cycles on the QBus Slave Chan
260. er Therefore for each data phase in the burst the external PCI master will see a series of retries and then one Target Completion 2 Ifthe Px FIFO fills while a burst is in progress the PCI Target Module generates a Target Disconnect 3 If there are fewer data entries available in the Px FIFO than specified by the cacheline CLINE 1 0 field of the PCI MISCO register and a PCI master attempts a new burst to the QSpan II the external PCI master is retried 4 The PCI Target Module only accepts linear burst address incrementing Any transfers requiring other addressing modes are disconnected after the first data phase For more information see Terminations driven by the PCI Target Module on page 82 QSpan II User Manual 8091862 001 08 4 5 2 2 Chapter 4 The PCI Target Channel The Px FIFO stores the address and data entries of PCI bursts For example if a burst of four is received by the PCI Target Module the QSpan II stores the burst as five new entries of the following types address data data data data Because the QBus Master Module can write data at the same time as the PCI Target Module accepts data the Px FIFO might not contain these five entries by the end of the burst some of the data may already have been written to the QBus before the burst completes on the PCI bus Bursting on the QBus If the Burst Write Enable BRSTWREN bit of the selected PCI Target Image is 1 the QSpan II will burst dat
261. er mode up to 40 MHz The QSpan is compatible with all M68040 variants in small buffer mode up to 33 MHz CA91L862A 50ILV 33MHz MC68360 3 3V 40 to 85 C 17 mm PBGA 50MHz MPC860 3V b The QSpan II supports universal PCI 3 3 5V tolerant inputs and 3 3 5V compliant output signaling QSpan II User Manual 407 8091862 001 08 Appendix H Ordering Information H 2 408 Part Numbering Information The IDT CA part numbering system is explained as follows CA NNNNNNN SS S G Z L l IDT CA product identifier Package type Product number RoHS Green compliance Prototype version statu Operating frequency Operating environment Indicates optional characters CA IDT product identifier NNNNNNN Product number SS S Maximum operating frequency of the fastest interface in MHz If the speed of this interface exceeds 999 MHz then the number will be followed by a G for GHz for example a 10 GHz part would be marked as 10G E Operating environment in which the product is guaranteed This code may be one of the following characters C Commercial temperature range 0 to 70 C Industrial temperature range 40 to 85 C Extended temperature range 55 to 125 C J Junction rated temperature range 0 to 105 C Junction rated extended temperature range 40 to 105 C P The Package type o
262. er of bytes prefetched is four times the number programmed into this register for example 001100b is 48 bytes MSTSLV 1 0 G RST See Master Slave Mode Table 128 a If you want to map a PCI Target Abort as an Error on the QBus and the MA BE D bit is set the EN bitin MISC CTL2 register must also be set The SW RST bit allows the QBus reset output RESETO to be controlled in software from the PCI bus When 1 is written to this bit the QSpan II asserts RESETO There are three ways to cause the QSpan II to terminate the software reset state 1 Clear SW bit by writing 0 to it In this case RESETO is immediately negated 2 Assert RESETI In this case the SW bit is immediately cleared set to 0 and RESETO is immediately negated 3 Assert RST In this case SW RST is immediately cleared set to 0 however RESETO continues to be asserted until RST is negated Unexpected results can occur if the output RESETO on the QBus Interface of the QSpan II is used to generate the input RESETI The reset state of S BG and S BB depends on the master mode of the QSpan II see Table 127 If the Master Mode is MC68360 then the reset state of S BG and 5 BB is 0 If the Master Mode is MPC860 or M68040 then the reset state of S BG and S BB is 1 The QB_BOC bit affects the transfer of data onto the QBus Interface in cases where the data passes through the QBus Slave Channel the PCI Target Channel or the
263. ere the MPC860 is used with local memory that does not support bursting QSpan II User Manual 8091862 001 08 Chapter 6 The DMA Channel The KEEP_BB bit in the MISC_CTL2 register see Table 130 on page 280 is not supported for DMA operation As such do not set this bit when the QSpan DMA channel is used with the PowerQUICC memory controller UPM 6 2 2 DMA Cycles on QBus QSpan can limit the number of single reads and writes performed on the QBus to service the DMA QSpan can complete a maximum of 16 single cycles or 16 burst cycles If the QBus OFF timer in the DMA_CS register is set the OFF timer becomes effective on every 64 byte boundary when completing single cycles on the QBus and on every 256 byte boundary when completing burst cycles see Table 113 on page 254 QSpan can also limit the number of clocks a DMA burst cycle is active on the QBus If this option is set through the MDBS bit in the DMA_CS register it forces the QSpan II to perform four burst cycles 64 bytes at a time on the QBus see Table 113 on page 254 This allows the PCI Target Channel or an external QBus master to access the QBus with lower latency In this case the QBus OFF timer becomes effective on every 64 byte boundary 6 3 Direct Mode DMA Operation When operated in Direct Mode the DMA is initiated by programming the QSpan II s registers The following fields in the listed registers must be set to the appropriate values e J D
264. es the BP pointer by 4 BP 0xA000 0004 The Host writes the IO message to the shared local memory through the QSpan II using the offset specified by the MFA from 2 The Host then places the MFA into the FIFO for example the Host writes to offset 0x040 with MFA as the data This causes the QSpan II to generate a QBus delayed write cycle at address IIP TP 0xA000 0800 with MFA as the data QSpan also increases the TP pointer by four TP 0xA000 0804 QSpan II can be programmed to generate a QBus interrupt when the IP FIFO is written with a new MFA It also sets the Inbound Post List New Entry Interrupt Status IPN IS bit in the INT STAT register see Table 119 on page 262 4 The QBus Host is notified of the Inbound message either through the QBus interrupt or by polling IP FIFO Empty Status E bit in the I2O CS register see Table 109 on page 248 It then reads the QSpan II s BP register to get the next Bottom pointer in the Inbound Post List FIFO this is a normal QBus register access The QBus Host can then get the MFA for the message and process the message The QBus Host must complete a write to increment the IIP BP by four BP 0 000 0804 to point to the next MFA in the The incrementing is completed by the QBus Host It writes the new value of the pointer to the BP register 5 The QBus Host releases the used MFA by writing the MFA back to
265. eset output RESETO_ to the hard reset input RESETH_ on the MC68360 This enables the QSpan II to reset the MC68360 when PCI RST is asserted or when the software reset bit is asserted SW_RST bit in the MISC_CTL register on Table 127 on page 276 QSpan II s reset input RESETI is typically unused and should be pulled high through a resistor HS HEALTHY should be left open as it has an internal pull down resistor For a PCI Host bridge application use the following reset configuration the QSpan II s PCI RST global reset for the QSpan II input is connected to the hardware reset signal RESETH_ on the MC68360 QSpan Is reset output RESETO can be connected to the PCI RST inputs of the other PCI devices the QSpan II s RST input is not connected to the PCI bus RST signal Therefore at power up the MC68360 s power on reset circuitry will assert RESETH_ which fully resets the QSpan II device QSpan will assert RESETO to reset the agents on the PCI bus when RST is active The reset example described in the previous paragraph also allows the MC68360 processor to reset all of the PCI agents under software control The MC68360 can write to the software reset bit in the QSpan IPs MISC register which will cause the QSpan II to assert its RESETO signal QSpan II s reset input RESETI is typically unused and should be pulled high through a resistor for more information about resets see Chapter 14 Reset Options on pag
266. f the QBus while another QBus master currently owns the bus BB BGACK asserted by the other master QSpan II obtains ownership of the bus after the other master negates BB BGACK QSpan II User Manual 317 8091862 001 08 Appendix B Timing Figure 27 Single Read QSpan II as MC68360 Master Ons 500ns 4201 X t 211b BR_ W gt Lwin 1218b BG_ 1234 I t211a 1235a BGACK_ N W gt t210a f 1236 A 31 0 v 2 gt t21pg 12360 TC 3 0 P t236f SIZ 1 0 v gt 1222 gt t221 D 31 0 t21pe Hf t236e RIWL 7 1216a gt 1215 gt 126 DS_ a 12166 12156 gt f t262b AS_ gt t218d gt f t217d DSACKO 4 gt 1218 gt 912174 DSACK1 a BERR 4 HALT 4 a Normal gt fe t218d gt 12174 DSACKO p c fe t218d gt 12170 DSACK1 p 12184 gt 4 1217 BERR p gt 1218e gt 9 t217e HALT p b Retry js t218d 1217d DSACKO 412180 gt 412174 DSACK1 1218a qmi217a BERR HALT c Bus Error Wait states are not required by the QSpan II 318 QSpan II User Manual 8091862 001 08 Appendix B Timing Figure 28 Single Write QSpan as MC68360 Master
267. f the error is on the PCI bus then the IPE bit in the IDMA DMA CS register is set see Table 109 on page 248 If the error is on the QBus then the IQE bit is set How the transfer proceeds following the error depends on whether the transfer is a read or a write and on what bus the error occurred Table 31 summarizes the sequence of events following bus errors for each of these four cases If a QBus bus error occurs during an IDMA write transfer the QSpan II continues to write data until the IWM level is reached This is possible because the QSpan only initiates PCI activity once the IWM value is queued in the I FIFO Once the IWM amount is transferred the QSpan responds to the bus error on the QBus as indicated in the following table The assertion of IRST IPE IQE and DONE can be mapped to the interrupt pins on either bus using the QSpan II s Interrupt Control Register bits IRST EN IPE EN IQE EN and DONE EN see Table 120 on page 265 The bus that is interrupted depends on the Interrupt Direction Register INT DIR see Table 121 on page 268 The status of the individual interrupt sources can be determined by reading the corresponding status bit see Table 42 on page 118 and Table 119 on page 262 To clear the interrupt the original interrupt source must be cleared For example to clear the Reset Interrupt the IRST bit in the IDMA DMA CS register must be cleared see Table 109 on page 248 The following table is extracted from Ch
268. f the product B Ceramic ball grid array CBGA Plastic ball grid array PBGA G Ceramic pin grid array CPGA J Ultra ball grid array EBGA 1 mm pitch K Ultra ball grid array EBGA 1 27 mm pitch L Plastic ball grid array PBGA 1 mm pitch M Small outline integrated circuit SOIC Q Plastic quad flatpack QSpan II User Manual 8091862 001 08 QSpan User Manual 8091862 001 08 Appendix Ordering Information G IDT CA products fit into one of three RoHS compliance categories RoHS Compliant 6of6 These products contain none of the six restricted substances above the limits set in the EU Directive 2002 95 EC Y RoHS Compliant Flip Chip These products contain only one of the six restricted substances Lead Pb These flip chip products are RoHS compliant through the Lead exemption for Flip Chip technology Commission Decision 2005 747 EC which allows Lead in solders to complete a viable electrical connection between semiconductor die and carrier within integrated circuit Flip Chip packages RoHS Compliant Green These products follow the above definitions for RoHS Compliance and are denoted as Green as they contain no Halogens Zit Prototype version status optional If a product is released as a prototype then a Z is added to the end of the part number Further revisions to the prototype prior to production release would a
269. face performs a corresponding Configuration Type 0 cycle on the PCI bus Programming the Device Number causes one of the upper address lines AD 31 16 to be asserted during the address phase of the Configuration Type 0 cycle Table 115 shows which PCI address line is asserted as a function of the NUM 3 0 field The remaining address lines during the address phase of the Configuration cycle are controlled by the Function Number and Register Number e AD 15 11 00000 e AD 10 8 FUNC_NUM 2 0 AD 7 2 REG_NUMJ5 0 e AD 1 0 00 Table 116 PCI AD 31 16 lines asserted as a function of DEV_NUM field QSpan II User Manual 259 8091862 001 08 Appendix A Registers Table 117 Configuration Data Register Register Name CON_DATA Register Offset 504 31 24 CDATA CON_DATA Description Reset Name Reset By State Function CDATA 31 0 EA G_RST 0 Configuration Data Configuration Configuration Data 00000000000 A write to the PCI Configuration Data register from the PCI bus has no effect A read from the PCI bus always returns all zeros A write to the Configuration Data register from the QBus causes a Configuration Write Cycle to be generated on the PCI as defined by the Configuration Address register see Table 115 A read of this register from the QBus causes a Configuration Read Cycle to be generated on the PCI bus The PCI bus Configuration cycles generated by accessing the Configuration Data r
270. function of NUM field 112 Mapping of Hardware Initiated 117 Interrupt Source Enabling Mapping Status and Clear bits 118 Software Interrupt Mapping Status and Source bits 120 Destination of EEPROM Bits 127 5 oe 148 Extraction 5 Ms od ad SEN ur 150 Hardware Reset 155 Reset Options for QBus Master and Slave 158 Test Mode Operation 204 0 Sheng Se RN ieee enol 159 QBus Signal Names Compared to Motorola 5 162 MC68360 MPC860 Encoding for the SIZ 1 0 81 171 M68040 Encoding for the SIZ 1 0 174 Non PCI DC Electrical Characteristics Vpp 5 180 3 3V PCI I O Signaling AC DC Characteristics 5 181 5V PCI I O Signaling AC DC Electrical 182 Pin List for QSpan 183 PCI Bus Address Data
271. g les jx capot SB d QCLK The timing parameters t405 and t406 are measured between 0 8 and 2 Volts The timing parameters t405 and t406 can be found in Table B 4 QSpan II User Manual 8091862 001 08 347 Appendix B Timing B 4 4 1 QBus Master Cycles M68040 Figure 59 QBus Arbitration M68040 Ons pus lara 1000ns Ld d d d LI d d d Lo dog I d 41401 QCLK _ 25 Ne NEMESIS IM 1411 lut BR gt 1413 t415c BG gt 1413 gt a _ This figure depicts timing in the case where the QSpan II requests ownership of the QBus while another QBus master currently owns the bus BB BGACK asserted by the other master QSpan II obtains ownership of the bus after the other master negates BB BGACK 348 QSpan II User Manual 8091862 001 08 Appendix B Timing Figure 60 Single Read QSpan as M68040 Master Ons 100ns 200ns 300ns lt 1401 gt QCLK t411 BR_ Ww 2 gt 14130 gt 1415 BG_ 1412 gt f 14106 gt t436b BB_ N gt 1410 gt t436a A 31 0 D gt t410h t436h BURST_ TIP_ gt t410d gt t436d SIZ 1 0 D gt i 141 of t
272. g 16 Bit QBus Port Transfer size BE 3 0 D 31 0 SIZ 1 0 A 1 0 D 31 0 ow o one om poems om The following table describes mapping of 8 bit and 16 bit read transfers through the PCI Target Channel in Big Endian mode from 16 bit QBus peripherals The addressing of bytes is preserved in Big Endian mode Table 24 Big Endian PCI Target Read Cycle Mapping 16 Bit QBus Port Transfer size BE 3 0 D 31 0 SIZ 1 0 A 1 0 D 31 0 1100 xx xx BO BO Bl xx xx 0011 B3 B2 xx xx B2 B3 xx xx All tri byte misaligned and non contiguous byte read operations from a peripheral with a 16 bit QBus port size are performed like a series of 8 bit read operations from a 16 bit peripheral xx B3 xx xx o o9 72 QSpan II User Manual 8091862 001 08 Chapter 4 The PCI Target Channel A 32 bit read operation from a peripheral with a 16 bit QBus port size is performed as two 16 bit read operations from a peripheral with a 16 bit QBus port size 8 Bit QBus Port The following table describes mapping of 8 bit read transfers through the PCI Target Channel in Little Endian mode from 8 bit QBus peripherals The byte lane ordering is preserved in Little Endian mode Table 25 Little Endian PCI Target Read Cycle Mapping 8 Bit QBus Port Transfer size BE 3 0 D 31 0 SIZ 1 0 A 1 0 D 31 0 ow 4 The following table describes mapping
273. geld gL gw 2 3 S wb ZU perk Ses wl mf MES zie dcus cy jf QINT_ AN INT 358 QSpan II User Manual 8091862 001 08 Appendix B Timing B 4 6 Reset Options The parameters for the following figure are in Table 158 on page 315 Figure 74 Reset Options Ons 25ns 50ns n 1019 gt RESETI_ or RST 1007 gt 1013 gt SIZ 1 1008 t014 TMODEJ 0 4 1009 gt 4 1015 gt 4 010 gt 4 1016 BDIP_ t01 1 gt lt 1017 BM_EN 1012 t018 SDA 4 020 4 1021 ENID 1022 1023 PCI DIS 1024 1025 PCI ARB EN QSpan II User Manual 359 8091862 001 08 Appendix B Timing 360 QSpan II User Manual 8091862 001 08 Appendix C Typical Applications This appendix describes how to connect the QSpan II to the following Motorola based buses MC68360 QUICC MPC860 PowerQUICC and M68040 Glue logic is not required for any of these applications The following topics are discussed e 68360 Interface on page 361 e 860 Interface on page 367 e M68040 Interface on page 374 C 1 MC68360 Interface This section describes how the QSpan II can be connected to the MC68360 communications controller C 1 1 Hardware Interface CALI Clocking QSpan II must be clocked by CLKO1
274. generates a Configuration write on the PCI bus This step causes the Configuration cycle to occur on the PCI bus The following subsections describe these two aspects of Configuration cycles The Bus Master BM bit in the PCI CS register must be set before attempting a PCI configuration cycle see Table 70 on page 203 QSpan II User Manual 8091862 001 08 7 4 3 Chapter 7 The Register Channel Address Phase of PCI Configuration Cycles The type of Configuration cycle that is generated on the PCI bus Type 0 or Type 1 is determined by the TYPE bit of the CON_ADD register see Table 115 on page 258 This determines how the address of the Configuration cycle is generated on the PCI bus When the QSpan is being used as a host bridge the MA BE D bit in the MISC register must be set to a 1 If you set this bit to 1 it allows the QSpan II to signal a successful Configuration cycle to the host processor even if a Master Abort occurs on the PCI bus If the TYPE bit is set to 1 an access of the CON DATA register from the QBus interface performs a corresponding Configuration Type 1 cycle on the PCI bus see Table 117 on page 260 During the address phase of the Configuration Type 1 cycle on the PCI bus the PCI address lines carry the values encoded in the ADD register AD 31 0 CON ADDR 31 0 If the TYPE bit set to 0 an access of the DATA register from the QBus interface performs a corresponding
275. generation of an interrupt or by polling for the DONE status bit in IDMA DMA CS To determine the current command packet being executed the software can read DMA CPP register to determine whether the command packet previous to this is being executed The software can also read the IDMA DMA CNT register to determine the amount of data that is left to be transferred in the current command packet If the Linked List is set up in a circular queue where each packet points to the next in the list and the last points to the first and the software wants the DMA Channel to skip over some of the command packets the software can set the transfer count in the command packet bits 19 0 of the third element to 0 When the DMA Channel reads a command packet that has a transfer count of 0 it reads and processes the next command packet If the CP LOC is set to 1 when the Linked List DMA Channel reads the next command packet from the QBus memory it reads it in a single 16 byte burst if BRSTEN in DMA CS is set to 1 Otherwise it takes four single reads to load the command packet If a QBus error is encountered while reading the command packet the Linked List DMA is terminated and the IQE status bit in IDMA DMA CS is set If a QBus or PCI bus error is encountered while a DMA transfer described by the command packet is in progress the Linked List DMA is terminated and the appropriate status bit IQE or IPE is set in the IDMA DMA CS register
276. gging 84 PCI transaction ordering 51 52 QBus Slave Channel 48 49 enabling 40 PCI transaction ordering 51 transaction ordering 52 Posted Write Termination QBus Slave Channel error logging 55 Power Dissipation 397 422 PowerQUICC 26 31 Bus Arbitration 79 Connection Caution 43 cycle termination 54 81 DONE signal 88 master and slave modes 158 signals 167 PowerQUICC Interface 367 Power Up Options 155 159 PR CNT2 bit MISC CTL2 Register 381 PR CNT2 field MISC CTL2 Register 281 PR SING bit MISC CTL2 Register 63 281 381 PRCNT bit MISC CTL Register 380 PRCNT field MISC CTL Register 277 PREF bit PCI BSIO Register 210 PCI BSTI Register 212 PREN bit PBTIO_CTL Register 224 384 Register 228 384 QBSIO_CTL Register 285 382 5 Register 289 382 PROG field PCI CLASS Register 206 PSC DIR bit INT DIR Register 269 PSC EN bit INT CTL Register 266 PSC IS bit INT STAT Register 263 PSC QRST bit MISC CTL2 Register 282 MISC_CTL2 Register 280 381 PTP_IB bit MISC_CTL2 Register 280 381 Pull Downs 159 Pull Up M68040 signals 376 378 PowerQUICC signals 370 QUICC signals 54 364 365 372 Pull Ups 162 PWEN bit QSpan II User Manual 8091862 001 08 PBTIO_CTL Register 224 384 PBTII_CTL Register 228 384 QBSIO CTL Register 285 382 QBSII CTL Register 289 382 PWR ST field PCI PMCS Register 220 Q Q ADDR field DMA CS Register 386 DMA_QADD Register 253 Q O
277. gh Signals are considered asserted when active and negated when inactive irrespective of voltage levels For voltage levels the use of 0 indicates a low voltage while a 1 indicates a high voltage The following signal conventions are used e SIGNAL Active low signals on the PCI bus interface e SIGNAL_ Active low signals on the Host processor bus interface 1 2 2 Bit Ordering This document adopts the convention that the most significant bit is always the largest number also referred to as Little Endian bit ordering For example the PCI address data bus consists of AD 31 0 where AD 31 is the most significant bit and 0 is the least significant bit of the field 1 2 3 Numeric Conventions The following numeric conventions are used e Hexadecimal numbers are denoted by the prefix 0x For example 0x004 e Binary numbers are denoted by the suffix b For example 010b 1 2 4 Topographic Conventions The following typographic conventions are used e Italic type is used for the following purposes Book titles For example PCI Local Bus Specification Revision 2 2 Important terms For example when a device is granted access to the PCI bus it is called the bus master Undefined values For example the device supports two or three ports depending on the setting of the PCI Dx register e Courier type is used to represent a file name or text that appears on a computer display For example run loadext e
278. gister 205 383 IP_BP field Register 243 IP_E bit I20_CS Register 238 IP F bit CS Register 238 IP TP field IIF TP Register 242 IPE bit IDMA DMA CS Register 248 IPE DIR bit 418 INT DIR Register 268 IPE EN bit INT CTL Register 265 IPE IS bit INT STAT Register 262 DIR bit INT DIR Register 269 IPF EN bit INT CTL Register 267 IPF_S bit INT STAT Register 263 IPL 2 0 376 IPN DIR bit INT DIR Register 269 IPN EN bit INT CTL Register 267 IPN IS bit INT STAT Register 263 IQE bit IDMA DMA CS Register 248 IQE DIR bit INT DIR Register 268 IQE EN bit INT CTL Register 265 IQE IS bit INT STAT Register 262 IRDY 175 184 IRQ 7 1 364 371 IRST bit IDMA DMA CS Register 248 5 DIR bit INT DIR Register 268 IRST EN bit INT CTL Register 265 IRST IS bit INT STAT Register 262 IRST REQ bit IDMA DMA CS Register 248 IWM field DMA CS Register 254 IDMA DMA CS Register 249 J JTAG 27 K KEEP BB bit 75 MISC CTL2 Register 280 381 QSpan II User Manual 8091862 001 08 L LAYOUT field PCI MISCO Register 207 Linear address incrementing 74 Linked List Mode DMA Channel 96 LOCK 58 LOO bit CPCI HS Register 221 LTIMER field PCI MISCO Register 207 M M68040 31 158 bus arbitration 80 Compatibility of QSpan with variants of 375 407 cycle termination 81 Interface 374 master and slave modes 158 signals 171 MA BE D bit MISC Register 276 380 387
279. gister 249 Chip Select 164 168 172 175 CLINE field PCI MISCO Register 207 CLKOI 361 Clocking M68040 375 PowerQUICC 368 QUICC 361 CMD bit IDMA DMA CS Register 248 CMD ERR field PB ERRCS Register 234 385 CNT field IDMA DMA CNT Register 252 386 CompactPCI Hot Swap Card Extraction 149 Card Insertion 147 CompactPCI Hot Swap Friendly 145 CON ADD Register 258 NUM field 111 NUM field 111 REG NUM field 111 TYPE bit 111 CON DATA Register 260 CDATA field 111 Configuration Space from PCI bus 64 from PCI bus how to access 387 from QBus 32 39 45 49 from QBus how to access 110 112 IDMA Channel 86 PCI Target Channel 107 Register Channel 105 CP LOC bit QSpan II User Manual 8091862 001 08 DMA_CS Register 255 1_ Register 221 CPP field DMA_CPP 257 CSPCI_ 164 168 172 183 CSREG_ 109 164 168 172 183 Customer Support Information 30 Cycle Termination PCI Target Channel 80 QBus Slave Channel 53 56 D D_PE bit PCI CS Register 203 D 31 0 164 168 172 183 D SP bit PCI PMC Register 219 D2 SP bit PCI Register 219 DACK SDACK 164 168 183 DATA field EEPROM CS Register 279 Data Packing Unpacking 70 IDMA Channel 88 89 93 PCI Target Channel 70 74 QBus Slave Channel 49 Data packing unpacking IDMA Channel 94 Data Parity Error see Parity Data Phase PCI Configuration Cycle 112 PCIInterface and PAR 52 PCI Target Channel burst 74 DC Characteristics 1
280. gister accesses are occurring from both the QBus and PCI bus Set this bit to 1 to improve the system s performance by disabling the PCI transaction ordering rules between the QBus Slave and PCI Target Channels see Transaction Ordering Disable Option on page 78 Set this bit to 1 to improve the posted write performance in the QBus Slave Channel 381 Appendix D Software Initialization The PCI Arbiter Control Register PCI_ARB should be initialized if the QSpan II is the PCI Host and its arbiter was enabled at power up see the following table Table 163 PCI Arbiter Control Register Summary PARB_CTL Mx_PRI This bit selects low or high priority for each PCI master QS_PRI This bit selects the QSpan II s priority PCI ARB EN Read this status bit to verify whether the QSpan II has powered up with the correct setting for enabling the arbiter PARK This bit allows you to park the PCI bus at different masters BM PARK 2 0 3 bit encoded field to select the master at which to park the bus see Bus Parking on page 144 D 2 QBus Slave Channel Initialization To support two QBus processor slave images you must program QBus slave image 0 and 1 registers Once these registers are programmed the QBus processor can read and write data from the PCI bus Table 164 QBus Slave Channel Programming Summary QBSIO CTL PWEN Set this bit to 1 to allow write transactions to be posted this will and or improve system throughput
281. gure 32 Register Write QSpan II as MC68360 Slave QCLK CSREG_ A 31 0 TC 3 0 SIZ 1 0 D 31 0 AS_ DSACKO_ DSACKI BERR HALT DSACKO_ D DSACKI D BERR p HALT QSpan User Manual 8091862 001 08 100 5 200ns 300ns 1201 gt 122009 gt t219d i t220d gt t219a gt j 1220a gt mt219h gt t220h 12190 gt 223 224 jue 7 gt 1219f gt 12201 12190 gt 219b gt 12200 1212 gt 1210 t236 A J 1212 gt 1210 1236 a L a Normal gt 1212 gt 1210 12366 1212a gt t210c t236Gg r gt 9112120 1112106 12360 J 212c t210d gt 2360 VA L b Retry Appendix B Timing B 4 2 2 QBus IDMA Cycles MC68360 Figure 33 MC68360 DREQ Timing Ons 100ns 200ns 300ns 400ns ub we a a I ie a ME ir eae 1201 QCLK Xy xy 1250 1250 DREQ_ LY tj i Table 159 Direction of QBus Signals During MC68360 IDMA Cycles I write O read D gt I write O read I write O read I Input Output N A Not Applicable b DSACKO is
282. h 256 PBGA Both packages require a 3 3V power supply and provide 3 3V or 5V I O signaling characteristics on the PCI bus Both devices are also 5V tolerant For more information on QSpan II packaging see Appendix Mechanical Information on page 401 17 3 Signals and DC Characteristics Table 53 Non PCI DC Electrical Characteristics 5 o9 Cw weememe o memes o LO mmm p Lo Lx eem ww eeeemen mu Vor Voltage Output low IoL 8 0 mA 0 4V Vpp 3 0 V Von Voltage Output high 8 0 ma 2 4V VDD 3 0 V TIL Input Leakage Current low With no pull up or pull down 10 04 A 10 04 A resistance Vss or Vpp Ir Input Leakage Current Low 100 0uA 4 with Pull up Im Input Leakage Current 4uA 100 High with Pull down Ioz Tristate Output Vout Vpp 0r Vss 10 0uA 10 0uA Leakage a For more information on PCI signal characteristics see the PCI Local Bus Specification Revision 2 2 b Depends on customer design 180 QSpan II User Manual 8091862_MA001_08 Chapter 17 Signals and DC Characteristics Table 54 3 3V PCI I O Signaling AC DC Characteristics Vpp 5 Lx pom op 0 e INE a tristate condition Switching current high OVours03 pp 10 3Vpp Pp 0 NU 9Vpp Ha PR MONIS Vpp Vour WERE TENE IL msan
283. has no effect Reads from the PCI bus return all zeros Disabling PCI Interrupts QSpan IIis a single function device so it implements a single PCI interrupt INT One restriction of this option is that it s always enabled INT PIN is set to 1 in the PCI MISC register If the system does not require the QSpan II to interrupt on the PCI bus the QSpan II can be disabled from requesting an interrupt on the PCI bus The Interrupt Pin INT PIN field in PCI MISCI register can be loaded from EEPROM or programmed from the QBus side before the PCI BIOS can access this register see Table 83 on page 218 The INT PIN setting does not affect the assertion of the QSpan II s INT output The INT LINE field in PCI MISCI will still be R W default 0 Software must set this field to Oxff to indicate unknown or no connection For more information see the PCI Local Bus Specification 2 2 QSpan II User Manual 121 8091862 001 08 Chapter 8 The Interrupt Channel 122 QSpan II User Manual 8091862 001 08 Chapter 9 The EEPROM Channel This chapter describes the QSpan II s EEPROM Channel The following topics are discussed e EEPROM Configuration and Plug and Play Compatibility on page 125 e EEPROM IC Protocol page 125 e Mapping of EEPROM Bits to QSpan II Registers on page 126 e Programming the EEPROM from the QBus or PCI Bus on page 129 e EEPROM Access on page 130 e Vital Product Data S
284. hich of the two QBus Slave Images is used If IMSEL is 0 QBus Slave Image 0 is selected see Table 133 on page 285 and Table 138 on page 287 if IMSEL is 1 QBus Slave Image 1 is selected see Table 140 on page 289 and Table 145 on page 291 The levels of BURST_ and R W determine whether the QSpan II will generate a single PCI cycle or a burst a PCI read or a write respectively There is some interaction between images and hardware signals as described in Tables 133 to 145 A Slave Image is a set of parameters which are encoded in QSpan II registers A Slave Image controls transfers between the QBus and the PCI bus Similar Target Images are provided in the PCI Target Channel Two QBus Slave images of equal capability are provided so that designers can quickly access on the basis of hardware rather than software PCI addresses from the QBus or access addresses in different ways The two Slave Images are completely independent from one another For example the designer can set up QBus Slave Image 0 to access a hard disk using 128 Mbytes of memory in PCI memory space The designer can simultaneously have QBus Slave Image 1 available to access a different device with its own memory size The designer can access the first device with posted writes Posted Write Enable PWEN bit set to 1 and the other with delayed writes PWEN set to 0 For a third type of access it would be necessary to share one of the Slave Images QSpan II
285. his is described in Motorola 5 MC68360 User Manual Software Issues When using the MC68360 with the QSpan II there are register bits which must be altered from the MC68360 s default reset state The register bits should be set as follows e Set the Bus Synchronous Timing Mode BSTM bit to 1 in MCR register because the QSpan II is a synchronous bus master e Set the Arbitration Synchronous Timing Mode ASTM bit to 0 in the MCR register because the QSpan II is not able to meet the MC68360 s set up requirements Setting the S_BG and S_BB bits to 1 was a requirement for the QSpan CA91C860B CA91L860B devices This setting is not required for the QSpan II However setting these bits to a 1 will save one clock cycle If both these bits are set to 1 the QSpan II will synchronously sample the MC68360 s arbitration outputs and the MC68360 will asynchronously sample the QSpan II s arbitration outputs MC68360 Slave Mode Interface If the MC68360 operates in Slave mode its processor core is disabled an external QBus arbiter must be used to support arbitration between the MC68360 and the QSpan II QSpan II s arbitration interface does not support the use of the MC68360 s internal bus arbiter when the processing core is disabled If the processing core is disabled the external arbiter receives bus requests BR from both the MC68360 and QSpan II and then issues bus grants BG back to the appropriate device If the MC68
286. his pointer gives the address offset for the Outbound Post List Bottom Pointer This register is initialized by the QBus Host but is maintained by QSpan II and is incremented by four modulo boundary of FIFO SIZE QSpan II User Manual 247 8091862 001 08 Appendix A Registers Table 109 IDMA Control and Status Register Register Name IDMA DMA_CS Register Offset 400 Bits Function 07 00 TC_EN CHAIN IMODE QTERM STERM PORTI6 IDMA DMA_CS Description Reset Name Type Reset By State Function GO W ReadO RST IDMA DMA Go Always 0 2 No effect 1 Enable IDMA DMA transfers IRST REQ W Read 0 G RST IDMA DMA Reset Request Always 0 2 No effect 1 Request reset of IDMA DMA control A G RST IDMA DMA Active Status 0 No IDMA DMA transfer is active 1 ZIDMA DMA transfer in progress IRST R Write 1 G RST IDMA DMA Reset Status to Clear 0 Not reset 1 Reset DONE R Write 1 G_RST IDMA DMA Done Status to Clear 0 Not done 1 Done R Write 1 G_RST IDMA DMA PCI Bus Error Status to Clear 0 No error occurred 1 Error occurred on the PCI bus during IDMA DMA transfer I IQ T PE R Write 1 G_RST IDMA DMA QBus Error Status to Clear 0 No error occurred 1 Error occurred on the QBus during IDMA DMA transfer CMD R W G_RST PCI Command Option for IDMA DMA PCI Transaction 0 PCI Memory Write or Memory Read 1 PCI Memory Write Invalidate or Memory Read Line 248 QSpan II User Manual 8091862 001 08 IDMA DMA CS
287. however it will sometimes increase the latency for the QBus processor to obtain the QBus Note Do not set this bit when the QSpan II DMA channel is used with the PowerQUICC memory controller UPM This field can be set to a non zero value to allow the QBus processor to detect a cycle which has not completed successfully on the PCI bus This bit can be set to 1 to allow the QSpan II to signal a PCI disconnect if TRDY has been negated for more than eight PCI clocks Set this bit to 1 so that the QSpan II will signal a bus error to the QBus processor if a PCI Target Abort occurs Set this bit to 1 to enable the QSpan II to perform burst cycles in MPC860 applications For MC68360 and M68040 applications this bit can be left cleared Used in conjunction with the BRSTWREN bit in the PBTIx CTL register see Table 89 on page 224 and Table 92 on page 228 Set this bit to 1 if the memory on the QBus does not support burst accesses This bit is only applicable when the QSpan is configured as an MPC860 QBus master This field controls the amount of data that is prefetched when a PCI burst read occurs through PCI Target Channel 1 of the QSpan II If the PCI Initiators perform burst read cycles then prefetching should be enabled to improve the system s performance For more information about the PCI Target Channel control registers see Appendix A Registers on page 195 Set this bit to 1 to improve the system s performance if QSpan II re
288. iated QBus Host in sleep mode QSpan can be programmed to generate a PME from the assertion of QINT_ in the D3hot Power state if QINT PME I MISC CTL2 register PME SP 3 1 in PCI and PME_EN 1 in PCI PMCS PME ST bit will also be set The Host can then write to the PWR ST bits in PCI PMCS to change it to DO and generate an add in card reset For more information about PCI power management states see the PCI Bus Power Management Interface Specification 1 1 154 QSpan II User Manual 8091862 001 08 Chapter 14 Reset Options This chapter discusses Reset options for the QSpan II The following topics are examined e Types of Resets on page 155 e Configuration Options at Reset on page 157 14 1 Types of Resets QSpan can be reset from the QBus or the PCI bus through hardware QSpan II uses four pins and one register for reset operation The reset pins are listed in Table 47 Table 47 Hardware Reset Mechanisms RST PCI Input Resets all the QSpan II circuits and registers and asserts RESETO_ when HS_HEALTHY_ is low RESETO_ remains asserted until RST is released Also clears the SW_RST bit in the MISC_CTL see Table 127 on page 276 register RESETI_ QBus Input Resets most of the QSpan II circuits and registers see Appendix A Registers on page 195 RESETO Resets devices on QBus HS HEALTHY E This input indicates the state of the back end system The term Reset is u
289. ice QSpan II User Manual 8091862 001 08 Chapter 3 The QBus Slave Channel 3 4 Address Phase 3 4 1 Transaction Decoding and QBus Slave Images QSpan II accepts a transaction through its QBus Slave Module when one of its chip selects is asserted along with the Address Strobe AS_ or Transaction Start signal TS_ The chip selects CSREG_ and CSPCI do not need to be detected asserted the same clock edge as TS_ for QBus Slave Channel accesses This allows for wait states to be inserted to perform address decoding However the IDMA Channel requires that CSPCI_ be detected asserted on the same clock edge as TS_ for dual address IDMA transfers Single address IDMA transfers do not require CSPCI_ to be asserted If CSREG is asserted then the transaction is decoded as a QSpan II register access if the address 0x504 is a PCI Configuration cycle see Chapter 7 The Register Channel on page 105 In order to access the PCI bus the QBus master or address decoder circuitry asserts the PCI chip select pin CSPCI and the QBus Slave Module claims the cycle for the QBus Slave Channel One of the two QBus Slave Images is selected during this transaction The QBus Slave Image is qualified by the Image Select Signal IMSEL The type of PCI cycle generated by the QSpan II depends on the following e which QBus Slave Image is selected e the type of transaction initiated by the external QBus master The level of IMSEL determines w
290. ice Specific Registers All of the QCSR space is accessible from both the PCI bus and the QBus The QSpan II CA91C862A is backwards software compatible with the QSpan CA91C860B CA91L860B However some register differences will be experienced for example device ID changes from one version to the other QSpan II User Manual 195 8091862 001 08 Appendix A Registers 2 196 Terminology G_RST N A PCI_RST Ox R R W R W E R WQ R WP R WQ E General reset Active when either RST or RESETI 15 driven low or H5 HEALTHY is driven high Not applicable PCI Reset driven low RST or H5 HEALTHY driven high Hexadecimal prefix binary numbers have no prefix Read Only Writes have no effect Read Write from PCI or QBus Read Write from PCI or QBus Loadable from EEPROM after PCI RST Read Write from QBus only Read Write from PCI only Read Write from QBus only Loadable from EEPROM after PCI RST The bit combinations listed as Reserved must not be set to 1 All bits listed as Reserved must read back a value of 0 QSpan II User Manual 8091862 001 08 Appendix A Registers Register Table 67 Register Address Offset Hexidecimal Register Description See 0x000 PCI ID PCI Configuration Space ID Register Table 69 on page 202 0x004 PCI CS PCI Configuration Space Control and Status Register Table 70 on page 203 0x008 PCI CLASS PCI Configuration Class Register T
291. ification 1 5 QSpan complies with the 1 0 specification by enabling intelligent I O cards also called IOP agents to implement four FIFOs in QBus memory see Figures 18 and 17 These FIFOs queue Message Frame Addresses MFAs which point to message frame locations There are two FIFOs for inbound messages and two FIFOs for outbound messages Inbound Free List FIFO IF Inbound Post List FIFO FIFO Outbound Free List FIFO OF FIFO and Outbound Post List FIFO OP FIFO There are two pointers for each circular FIFO or queue Top referred to as Tail in the 150 Specification and Bottom referred to as Head in the 1 0 Specification Therefore there are eight pointer registers for the four FIFOs in QSpan II register space These pointers are offsets from a fixed QBus address QBus 1 0 Base Address or QIBA QIBA is aligned to a 1 Mbyte boundary The four FIFOs must be the same size the start address for each FIFO must also be aligned to the FIFO size boundary Writes to the queue add an MFA to the Top of the FIFO and reads draw an MFA from the Bottom of the FIFO QSpan II User Manual 133 8091862 001 08 Chapter 10 1 0 Messaging Unit 10 2 134 Figure 17 1 0 Messaging Unit Functional Diagram QBus Interface Interface QBus Slave Module PCI Bus O Messaging QBus Register Channel Interrupt Channel PCI QBus Target Master Module Module Inbound Messaging The Inbound Pos
292. ignals to the non asserted state Table 13 M68040 Cycle Terminations of QBus Slave Module Termination Type DSACKI TA BERR TEA a External pull ups bring tri stated signals to the non asserted state 54 QSpan II User Manual 8091862 001 08 Chapter 3 The QBus Slave Channel The following table summarizes the QSpan II s response to abnormal terminations on the PCI bus Table 14 QBus Slave Channel Error Responses Transfer MA BE Din TA_BE_EN in type PCI Error Type MISC_CTL MISC_CTL2 Flush FIFO QBus Termination Yes Normal return all 1 Yes Normal return all 1 Bus error Target Abort No Lose one entry Normal continue sinking data P No Lose one entry Normal continue sinking data b Ifa single posted write transfer results in a Master Abort then this complete transaction is lost and the QSpan will continue sinking any subsequent posted write entries If a burst write results in a Master Abort on the first data beat then this data entry is lost It is likely that the second third and fourth entries of the burst will also result in a Master Abort and this data will be lost as well posted Master Abort No Lose one entry Normal write continue sinking data No Lose one entry Normal continue sinking data This column pertains to Qr FIFO for reads and Qx FIFO for writes 3 6 1 Posted Write Termination QBus terminations of posted writes are not influenced by the PCI bus termina
293. in circuit tester will be used during the board manufacturing process then these two signals should be brought out as test points This would allow the in circuit tester to place the QSpan II in a tri state NAND TREE test mode e Ifthe BM EN FIFO RDY signal is sampled high while RST is asserted the QSpan II sets the Bus Master BM bit in the PCI CS register see Table 70 on page 203 This enables the QSpan II as a PCI bus master This pin can be left as a no connect as there is an internal weak pull down resistor QSpan II User Manual 371 8091862 001 08 Appendix C Typical Applications C 3 1 9 C 3 1 10 C 3 1 11 378 e Ifthe PCI EN signal is sampled high on the negation of a reset event then the PCI bus arbiter within the QSpan is enabled There is an internal pull down resistor on this pin to maintain backward compatibility e If the PCI DIS signal is sampled high on the negation of a reset event then the QSpan II s PCI interface is disabled QSpan II will retry any attempted PCI target accesses until the PCI DIS status bit in the MISC CTL2 register is cleared see Table 130 on page 280 There is an internal pull down resistor to maintain backward compatibility Reset options are described in Chapter 14 Reset Options on page 155 Unused Inputs Requiring Pull Ups The AS DSACKO HALT TRETRY DONE and DACK signals are unused inputs when the QSpan II is interfaced with a M68040 and therefore must be pu
294. ination Phase Except during posted writes the termination generated by the QBus Slave Module is determined by the termination on the PCI bus see Posted Write Termination on page 55 For read transactions and delayed write transactions the QBus master is retried until the PCI transaction is complete Once the PCI transaction is complete the QBus master receives a translated version of the PCI termination The following table shows how PCI terminations are translated to the QBus Slave Module during delayed transactions such as delayed single reads delayed single writes and reads Table 10 Translation of Cycle Termination from PCI Bus to QBus PCI Bus Termination Received QBus Termination Issued Master Abort Bus Error if MA D bit is 0 Normal if MA BE D bit is 1 reads return all 15 write data flushed Target Retry Target Abort Bus Error if MA D bit is 1 and the TA BE EN bit is 1 Normal if MA BE D bit is 1 and the TA BE EN bit is O reads all 1s write data flushed a This table applies to delayed transfers b These cycles are not translated The QBus Slave Module retries the master during delayed transactions until one of the other terminations is received The QBus Slave Module retries accesses under the following conditions e A QBus master attempts to post another write to the QBus Slave Channel and the Qx FIFO does not have enough room for the write e A QBus master attempts a burst write tran
295. ing on page 391 The PCI bus is always a Little Endian environment The QBus can be configured as Little Endian or Big Endian depending on the value of the QBus Byte Ordering Control bit QB_BOC in the MISC_CTL register see Table 127 on page 276 The default mode for the QBus is Big Endian This global ordering can be inverted on an image by image basis by programming the INVEND bit of the PBTIx_CTL register QSpan II translates byte lane ordering when the QBus is Big Endian while preserving the addressing of bytes When the QBus is Little Endian according to QB_BOC and INVEND the QSpan II preserves byte lane ordering while translating the addressing of bytes The QB_BOC bit affects transactions in all channels whereas the INVEND bit only affects the PCI Target Channel PCI bus transactions have the following characteristics e They can be translated as 32 bit 16 bit or 8 bit on the QBus e The data width of the QBus transaction is controlled by the DSIZE field of the PCI bus Target Image Control register With 16 bit peripherals they can be 8 bits or 16 bits wide With 8 bit peripherals they can be 8 bits wide e Packing and unpacking of data performed by the QBus Master Module is a function of byte enables BE 3 0 and the port size Write Cycle Mapping for PCI Target Channel This section describes write cycle mapping as a function of port size All tri byte misaligned and non contiguous byte write oper
296. ingle write or the first phase of a burst write and the Px FIFO does not have the number of data entries free that are specified by the cacheline CLINE 1 0 in the PCI MISCO register This Target Retry only occurs if the PWEN bit is set to 1 e delayed transaction is in progress in the PCI Target Channel e A burst read is requested but the ensuing read has not terminated on the QBus e A PCI bus master attempts a write through the PCI Target Channel while a read is in progress in either the QBus Slave Channel or the PCI Target Channel and that read has not completed on the read destination bus for example the PCI bus or the QBus respectively For more information see Reads and PCI Transaction Ordering on page 77 Target Abort During a Target Abort a termination is issued by a target for a transaction which it can not respond to or during which a fatal error occurred This is signaled by the target asserting STOP and negating DEVSEL Although there may be a fatal error for the initiating application the transaction completes gracefully ensuring normal PCI operation for other PCI resources Except during posted writes see Terminations of Posted Writes on page 84 the termination generated by the PCI Target Module is determined by the termination on the QBus For read transactions and delayed write transactions the master is retried until the QBus transaction is complete Once the QBus transaction is complete the PCI bu
297. input the QSpan II samples TEA during M68040 style cycles in which it is a M68040 bus master on the rising edge of QCLK Target retries are indicated by the simultaneous assertion of DSACKI and BERR TEA Bus Grant indicates that the QSpan II may become the next M68040 bus master BG along with BR_ and BB provide the three wire handshake for M68040 bus arbitration is sampled on the rising edge of QCLK QSpan II can be programmed to use an asynchronous mode for M68040 bus arbitration BM EN FIFO RDY Bidirectional Bus Master Enable If this input is asserted set as 1 during a PCI Reset the Bus Master Enable bit in the PCI CS register will be set Bus Request asserted by the QSpan to request ownership of the M68040 bus along with and BB provide the three wire handshake for M68040 bus arbitration BR is asserted and released from the rising edge of QCLK QSpan II User Manual 171 8091862 001 08 Chapter 16 Signals 16 5 M68040 Signals Continued BURST TIP Tristate bidirectional Transaction In Progress asserted for the length of an M68040 transfer This signal uses the same pin as the MPC860 BURST signal PCI Chip Select indicates that the current transaction on the QBus is an access to the PCI Bus Register Chip Select indicates that the current transaction on the QBus is an access to the QSpan registers D 31 0 Tristate bidirectional
298. is important that the PCI bridge provides flexibility in how endian systems are mapped across the interface The following figure shows a 4 byte operand being moved to the data bus in a Little Endian system Figure 81 Little Endian System Memory Organization Byte Lanes Byte Byte 2 Byte 1 Byte 0 MSB LSB Some host bus adapters for example SCSI for the PCI environment expect their descriptor blocks to be stored in main memory in Little Endian format This means that a PCI to Motorola bridge must provide a flexible endian mapping scheme to allow for PCI adapter control information to be stored in Motorola memory QSpan II User Manual 393 8091862 001 08 Appendix E Endian Mapping E 4 Endian Mapping Methods There are two standard approaches to endian mapping in a PCI to Motorola bridge address invariance and data invariance A third approach involves using a combination of both methods E 4 1 Address Invariance With address invariance the addressing of the bytes in memory is preserved The following figure shows that by performing byte lane swapping the bytes appear in the same address but their relative significance is not preserved This method works for text information but scrambles operands Figure 82 Address Invariant Mapping Motorola Big Endian Byte Lanes PCI Little Endian Byte 3 Byte 2 Byte 1 Byte 0 LSB MSB B 3 394 QSpan II User Manual 8091862 001 08 Appendix E En
299. is parked Bus parking is performed when there are no requests and the bus is idle 144 QSpan II User Manual 8091862 001 08 Chapter 12 CompactPCI Hot Swap Friendly Support This chapter discusses CompactPCI Hot Swap Friendly capabilities of the QSpan II The following topics are explained e Hot Swapping with the QSpan II on page 146 e CompactPCI Hot Swap Card Insertion on page 147 e CompactPCI Hot Swap Card Extraction on page 149 12 1 Overview QSpan II is a CompactPCI Hot Swap Friendly Device see Figure 21 CompactPCI s Hot Swap Specification defines a process for installing and removing adapter boards without adversely affecting a running system QSpan II supports programmable access to Hot Swap services This allows system reconsideration and fault recovery to take place with no system down time and minimum operator interaction Hot Swap defines three classes of devices Hot Swap Capable Hot Swap Friendly and Hot Swap Ready Hot Swap Friendly device requirements include the following e Hot Swap Control Status Register and Extended Capabilities Pointer This supports the use of the Hot Plug System Driver e Support of the Hot Swap event pin ENUM This signal informs the Host that the configuration of the system has changed that is the card has been inserted or is about to be removed e Support for sensing the switch connected to the ejector latch and controlling the LED Two pins are used for this fu
300. is registered output QBus Direct Connects All other bus interface signals can be connected directly together External pull up resistors should be connected to all bus control signals excluding SIZ 1 and BDIP_ which are power up options and should be pulled to the desired state to ensure that they are held in the inactive state see Figure 79 to determine which signals require external pull ups Depending on the version and speed of the M68040 device selected for a design an extra wait state may need to be inserted on the transfer start signal TS This may be required because the external address decoding circuitry may not be able to generate the chip selects to the QSpan II to meet the input setup requirements An alternate solution is to use large output buffer mode in the M68040 to eliminate the need for this wait state The M68040 s output propagation delays are much quicker in this mode and therefore there is more timing margin available for interfacing the QSpan II However if large output buffer mode is chosen it must be used in an unterminated method as the QSpan II s output drivers do not have the ability to drive a 50 ohm transmission line terminated at 2 5 V QSpan II has four transaction code TC 3 0 signals which can be connected to any four of the five following signals on the M68040 TT 1 0 and TM 2 0 Interrupts QSpan II device can pass interrupts between the PCI bus and the QBus For host bridging applicati
301. ister 228 384 Dual Address Cycle 87 89 324 343 termination mode 250 timing 249 328 330 E EEPROM channel description 123 130 Control and Status Register 200 PCI BSTO register enabled 210 PCI BSTI register enabled 212 programming 129 SCL signal 177 SDA signal 177 EEPROM CS Register 279 ADDR field 130 EIM bit CPCI HS Register 221 EN bit PB ERRCS Register 234 385 PBTIO CTL Register 224 384 Register 228 384 PCI_BSROM Register 215 389 ERRCS Register 293 385 QBSIO AT Register 287 382 QBSII AT Register 291 382 Endian Issues PCI Target Channel 68 73 228 254 QBus Slave Channel 46 47 Register Channel 110 Endian Mapping 391 ENID 177 178 184 ENUM 176 184 ES bit PB ERRCS Register 234 385 QB ERRCS Register 293 385 Expansion ROM 215 216 232 416 EXT bit CPCI HS Register 221 EXT GNT 184 EXT 6 1 174 EXT REQ t 184 EXT_REQ 6 1 175 F FIFO_SIZE field CS Register 239 FRAME 64 175 184 189 Frequency PCLK 175 QCLK M68040 173 312 PowerQUICC 169 308 QUICC 166 303 IDMA fast termination 308 327 330 QUICC IDMA fast termination 166 FUNC NUM field CON ADD Register 258 387 Functional Diagram QSpan II 32 G GNT 175 184 GO bit IDMA DMA CS Register 248 H HALT TRETRY 165 169 184 Hot Swap Friendly 145 HS HEALTHY 176 184 HS LED 176 184 HS SWITCH 176 184 I I O Read 45 46 64 I O Space IDMA Channel 86 PCI Target Channel bur
302. it QBus port size is performed as two 16 bit write operations to a 32 bit peripheral A 16 bit write operation to a QBus peripheral with a 16 bit QBus port size is performed as a 16 bit write operation to a 32 bit peripheral An 8 bit write operation to a QBus peripheral with a 16 bit QBus port size is performed as an 8 bit write operation to a 32 bit peripheral 8 bit QBus port 8 bit QBus port transfers are explained in terms of the 32 bit transfers described in Tables 19 and 20 The first two operations involve unpacking data A 32 bit write operation to a QBus peripheral with an 8 bit QBus port size is performed as four 8 bit write operations to a 32 bit peripheral A 16 bit write operation to a QBus peripheral with an 8 bit QBus port size is performed as two 8 bit write operations to a 32 bit peripheral An 8 bit write operation to a QBus peripheral with an 8 bit QBus port size is performed as an 8 bit write operation to a 32 bit peripheral All tri byte misaligned and non contiguous byte write operations are performed as a series of 8 bit write operations to a 32 bit peripheral Read Cycle Mapping for PCI Target Channel This section describes cycle mapping and packing of data by the QBus Master Module 32 bit QBus Port Tables 21 and 22 describe transfers of various sizes to 32 bit peripherals QSpan II User Manual 8091862 001 08 Chapter 4 The PCI Target Channel The following table describes mapping of 8 bit 16 bit a
303. ites One wait states for single posted writes e Two wait states for complete delayed reads and writes e One wait state for complete delayed burst reads See the following section for register accesses When the QBus processor is accessing the QSpan II s registers the maximum number of retries the QSpan II asserts is two The minimum response time for successful non retried QBus accesses from TS or AS asserted to or DSACKx_ asserted is three QCLKs including two wait states for reads and six for writes Use Figure 24 when reading the timing diagrams in this Appendix 316 QSpan II User Manual 8091862 001 08 Appendix B Timing B 4 Timing Diagrams B 4 1 QBus Interface MC68360 Figure 25 QCLK Input Timing MC68360 CLKO1 Ons 25ns 50ns 75ns Ld dE dE P P PE dE d Pd P P P P d Pd Pd Pd I 44 io 202 94 104 QCLK The timing parameters t005 and t006 are measured between 0 8 and 2 Volts The timing parameters t005 and t006 can be found in Table 154 on page 303 B 4 2 QBus Master Cycles MC68360 Figure 26 QBus Arbitration MC68360 Ons 250ns 500ns 1201 QCLK pe Weg 24779 12116 gt t235b BR X 1 Hit t217b t218b BG _ 1234 gt t217c gt t218c t211a 1235a BGACK WV W f This figure depicts timing in the case where the QSpan II requests ownership o
304. l 373 8091862 001 08 Appendix C Typical Applications C 3 M68040 Interface This section describes how the QSpan II can be connected to the M68040 Figure 79 M68040 Interface BOLK External Address Decode Logic A 31 0 D 31 0 SIZ 1 must be pulled SIZ 1 0 M68040 master mode if down SIZ 0 pulled up TS SIZ 1 0 and BDIP 1 at reset R W _ M68040 QSpan II TIP_ BURST_ TIP_ BR BR 2 __ Arbiter BB 5 BB _ BERR_ TEA_ DSACK1_ TA_ TT 1 0 TM 2 0 TC 3 0 If not used should be pulled up RESETI_ RSTI_ H RESETO Reset Stratedgy for PCI Adapter Card Applications RSTI RESETI_ Reset Circuitry Reset Stratedgy for Host RSTO_ pele Po Application Generates the PCI bus RESET RST signal a f meo PCI Bus RST Signal The QSpan is an IPL 2 0 QINT autovector interrupter V soexternal logic will be Prioritizing Logie required to assert AVEC to the M68040 AS_ DACK_ DONE DSACKO BDIP_ RETRY Separate pull ups SDA SDA and ENID control the ENID EEPROM port at reset DREQ and DS_ can be no connects 374 QSpan II User Manual 8091862_MA001_08 Appendix C Typical Applications 21 Hardware Interface to 40 MHz QSpan II is compatible with all M68040 variants in small QSpan II is compatible with all M68040 variants in large buffer mode up N buffer mode up to 33 MHz C 3 1 1 Clocking
305. l EEPROM if enabled Table Legend of Insertion Sequence e HS_LED L gt LED on HS LED Z gt LED off HS HEALTHY High gt Back end powered down HS HEALTHY Low Back end powered up e bits INS EXT LOO and EIM are defined in HS register 148 QSpan II User Manual 8091862 001 08 Chapter 12 CompactPCI Hot Swap Friendly Support Figure 22 Hot Swap Card Insertion Long Engage Early Power W Back End Power BD_SEL MW Pulled HEALTHY W PCI RST from J1 Pre charge 3 Med Short Fully Back End Powered QSpan Clears Ejector Engage Engage Seated Board goes Healthy LOO bit Latched POI Clock pre charge Clocking PCI Si T Cl Signals pre charge Ehgaged tratking bus Ejector State Open Closed ENUM _ pre charge Em LED LED on by Hardware LED off INS bit Cleared Unarmed Cleared Armed ET Set EXT bit Cleared Unarmed Cleared Unarmed Physical Connection Hardware Connection Start of Software Connection Process lt gt gt lt gt 12 4 CompactPCI Hot Swap Card Extraction The extraction process is signaled by opening the ejector handle this causes the HS_SWITCH to be low When QSpan II detects the falling edge on HS_SWITCH it starts the extraction process It sets the EXT bit in CPCI_HS see Table 86 on page 221 and asserts ENUM if it is enabled After sensing ENUM
306. le 12 860 Cycle Terminations of QBus Slave 54 Table 13 M68040 Cycle Terminations of QBus Slave 54 Table 14 QBus Slave Channel Error 55 Table 15 Reset Options for QBus Master and Slave 59 Table 16 Address Fields for PCI Target Image 61 Table 17 Control Fields for PCI Target 62 Table 18 Translation of PCI Bus Address to QBus Address 66 Table 19 Little Endian PCI Target Write Cycle Mapping 32 Bit QBus Port 69 Table 20 Big Endian PCI Target Write Cycle Mapping 32 Bit QBus Port 69 Table 21 Little Endian PCI Target Read Cycle Mapping 32 Bit QBus Port 71 Table 22 Big Endian PCI Target Read Cycle Mapping 32 Bit QBus Port 71 Table 23 Little Endian PCI Target Read Cycle Mapping 16 Bit QBus Port 72 Table 24 Big Endian PCI Target Read Cycle Mapping 16 Bit QBus Port 72 Table 25 Little Endian PCI Target Read Cycle Mapping 8 Bit QBus Port 73 Table 26 Big Endian PCI Target Read Cycle Mapping 8 Bit QBus Port 73 Table 28 860 Cycle Terminations of QBus Master
307. le the QSpan II is loading data from an external serial EEPROM Writes to bits in the PCI Expansion ROM Base Address register that are not write enabled will have no effect Table 81 Writable BA bits as a function of Block Size SNS RE RA EE MUN _ 216 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 82 PCI Capabilities Pointer Register Register Name PCI_CP Register Offset 034 31 24 24 PCI Reserved E PCI Reserved 15 08 PCI Reserved 07 00 CAP PT PCI CP Description 7 0 PCI RST Capabilities Pointer Points to the first entry of the linked list of new capabilities implemented by QSpan II QSpan II User Manual 217 8091862 001 08 Appendix A Registers Table 83 PCI Configuration Miscellaneous 1 Register Register Name PCI_MISC1 Register Offset 03C 31 24 MAX_LAT 23 16 MIN_GNT 15 08 INT PIN 07 00 INT_LINE PCI_MISC1 Description Reset Name Type Reset By State Function INT_PIN 7 1 EE i PCI RST BENI Interrupt Pin 7 to 1 INT PIN 0 R WQ E PCI RST Interrupt Pin 0 The INT_PIN 0 can be loaded from the serial EEPROM or written from the QBus before configuration by an external Host A value of 1 indicates that the QSpan II uses a single PCI interrupt INT A value of 0 indicates that the QSpan II does not use any PCI interrupts When QSpan is setup to not use any PCI interrupts it is up to an external agent to set the INT_LINE to
308. lear Enable Bits INT CTL Interrupt Status Bits INT STAT Table 120 on Table 119 on Mapping Bits INT DIR Table 121 on page 268 92 QSpan II User Manual 8091862 001 08 Chapter 5 The IDMA Channel An IDMA transfer that is halted due to an IDMA error IPE or IQE asserted will not resume once the error condition is cleared The IDMA Channel needs to be reset by setting IRST_REQ bit of the IDMA DMA_CS see Table 109 on page 248 The IRST status bit is set when the QSpan II has reset the IDMA Channel Then a new IDMA transfer can be programmed either from where the error happened or the previous transfer can be attempted again The QBus Slave Channel is not affected by IDMA Channel errors The IDMA Channel can be reset by setting the IRST_REQ bit in the IDMA DMA_CS register depending on the value of the ACT bit in the IDMA DMA CS register see Table 109 on page 248 If the ACT bit is 0 then setting IRST_REQ to 1 has no effect If the ACT bit is 1 then setting the IRST_REQ bit has the following effects 1 QSpan negates DREQ which halts transfers on the QBus 2 Ifthe QSpan is writing IDMA data on the PCI bus the QSpan II will terminate the transfer by negating at the next cacheline if the QSpan is reading data FRAME is negated immediately QSpan II flushes the I FIFO after negating FRAME 4 The ACT bit in the IDMA DMA CS register is set to 0 while the IRST bit is set to
309. led and will function as the PCI bus arbiter PCI Configuration Disable This is a power up option which makes the QSpan hold off on ENUM assertion and retry PCI configuration cycles to allow the Host processor to perform local configuration QSpan II accepts PCI configuration cycles after the PCI DIS bit is cleared in the MISC_CTL2 register PME Open Drain Output Power Management Event Interrupt This signal is asserted to request a change in its current power management state and or to indicate that a power management event has occurred Serial Clock EEPROM Serial clock The frequency of the SCL is the PCLK frequency divided by zv SDA Bidirectional Serial Data EEPROM Serial data line If SDA is sampled high after a PCI reset then the QSpan II will download register information from the EEPROM This is a manufacturing test input which should be left open This pin has an internal pull up resistor This is a manufacturing test input which should be left open This pin has an internal pull down resistor This is a manufacturing test input which should be left open This pin has an internal pull down resistor Test Mode Selects the QSpan II test mode These pins have internal pull down resistors Highest I O Voltage VH is a power pin which must be connected to the highest voltage level that the QSpan II I Os will observe on either the QBus or the PCI bus QSpan II User Manual 177 8091862 001 08 Chapter 16 Signals
310. lid information when the ES bit is set At all other times these fields will return all zeros when read QSpan II User Manual 293 8091862 001 08 Appendix A Registers Table 148 QBus Address Error Log Register Name QB_AERR Register Offset F84 31 24 QAERR QB_AERR Description Reset Name Type Reset By State Function QAERRI31 0 0 QAERRBLOD R G RST 0 QBus Address ErrorLog QBus QBus Address Error Log 000000000 Error Log The QBus Master Module will log errors when a posted write transaction results in a bus error This register logs the QBus address information Its contents are qualified by bit ES of the QBus Error Log Control and Status Register see Table 147 on page 293 The QAERR field contains valid information when ES is set At all other times a read of this register will return all zeros 294 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 149 QBus Data Error Log Register Register Offset F88 31 24 QDERR QB_DERR Description Reset Name Type Reset By State Function QDERRI3I 0 0 G_RST 0 QBus Data ErrorLog QBus QBus Data Error Log 00000000 Error Log The QBus Master Module will log errors when a posted write transaction results in a bus error This register logs the QBus data information Its contents are qualified by bit ES of the QBus Error Log Control and Status register see Table 1
311. lled high No Connects The DS and DREQ outputs from the QSpan II should be left as no connects when the QSpan is interfaced with a M68040 The BM EN FIFO RDY can be left as a no connect as there is an internal weak pull down resistor In this case in order for the QSpan II to become a PCI bus master a write to the PCI CS register is required JTAG Signals QSpan II supports JTAG QSpan II s JTAG signals should be connected to the JTAG controller or to the JTAG signals of another device if devices are to be chained together If JTAG will not be supported then the JTAG signals can be left open as the inputs have internal pull up resistors QSpan II User Manual 8091862 001 08 Appendix D Software Initialization This appendix explains how to initialize the QSpan II It describes which registers must be configured before you can initiate a transaction through the QSpan II s channels This appendix also recommends how to set QSpan Is register bits in order to achieve maximum performance This appendix discusses the following topics e Miscellaneous Control Register Configuration on page 380 e Slave Channel Initialization on page 382 e Register Access from the PCI Bus on page 383 e Target Channel Initialization on page 383 e Error Logging of Posted Transactions page 385 e IDMA DMA Channel Initialization on page 386 e Interrupt Initialization on page 386 e Generation
312. llimeters mm 2 Measured at the maximum solder ball diameter parallel to primary datum Z 3 Primary datum Z and seating plane are defined by the spherical crowns of the solder balls 4 Al Corner is identified by chamfer ink mark metallized mark indentation or other feature of the package body or lid 5 Reference Specification QSpan II conforms to Jedec Registered Outline drawing MO 151 Variation AAF 1 except for these dimensions 6 Ball pad is 0 4 mm diameter IDT recommends customer s PCB pad have same diameter 402 QSpan II User Manual 8091862 001 08 Appendix G Mechanical Information Figure 85 256 PBGA 17 mm Bottom View a 2 ilg 0000 00600 t OC FO F 0000 xS k gH G 1 2 256 PBGA 27 mm Table 179 256 PBGA 27 mm Packaging Features Package Type 256 terminal Plastic Ball Grid Array PBGA 1 power and 1 ground plane Package Body Size 27 X 27 mm JEDEC Specification MO 151 Variation BAL 2 QSpan II User Manual 403 8091862 001 08 Appendix G Mechanical Information Figure 86 256 PBGA 27 mm Top and Side Views N 41 CORNER EF be EF 1 44 0 5 EF N e 2 j a zn ona EN 45 5 15 F im 3 P 12 44
313. location in the Inbound Free List FIFO for example if the location of IF_FIFO is at QIBA then 0 The 1 0 Inbound Free List Top Pointer TP must point to the first free entry for example last available MFA 1 If the size of the FIFO is 256 and there are 200 MFAs then TP 201 4 804 0x324 The Inbound Post_List Top and Bottom IIP_TP _ pointers must also be programmed for example if the IP_FIFO starts at QIBA 2048 then TP 2048 The four Outbound pointers IO Outbound Post List Top Pointer TP 1 0 Outbound Post List Bottom pointer IOP_BP 0 Outbound Free List Top Pointer TP 1 0 Outbound Free List Bottom Pointer BP must be programmed to their respective starting offset from the QIBA for example if OP FIFO starts at QIBA 4096 and OF FIFO starts at OIBA 6144 then BP TP 4096 and IOF BP IOF TP 6144 If the QBus IO base address is 0xA000 0000 then QSpan s 1 registers will contain the following for the above settings CS QIBA 0xA00 SIZE 0x0 BP 0xA000 0000 TP 0 000 0324 IF FIFO contains 200 MFAs BP 0xA000 0800 TP 0xA000 0800 FIFO is empty BP 0xA000 1000 TP 0xA000 1000 OP FIFO is empty IOF BP 0xA000 1800 0xA000 1800 FIFO is empty If the Top and Bottom pointers are equal the FIFO can either be full or
314. ls are latched by the QBus Slave Module After latching the information the QSpan II retries all incoming QBus cycles but does not latch them until the read completes on the QBus QSpan II becomes PCI bus master and performs a read transaction on the PCI bus The read data is queued in the Qr FIFO If the PCI transaction completes normally then the QBus master is provided with the data from the Qr FIFO and the transaction terminates normally on the QBus see Termination Phase on page 53 If the QBus master attempts a burst read to the QBus Slave Module and the Slave Image is programmed for PCI Memory Space then the QSpan II initiates a read cycle If the read is attempted to a Slave Image programmed for PCI I O Space or to QSpan II registers then the QBus Slave Module terminates the access with a bus error A burst read is four beats in length 16 bytes Prefetched Reads QSpan II supports prefetched reads in the QBus Slave Channel for MPC860 and MC68360 cycles M68040 cycles are not supported To enable prefetching on an image basis set the PREN bit in QBSIO or QBSI1_CTL When this bit is set and the QSpan II decodes a single 32 bit aligned 4 byte read on the QBus from an external master it initiates a prefetch of 32 bytes on the PCI bus using linear address incrementing Once all 32 bytes are available in the Qr FIFO the external QBus master receives the first four bytes of read data If a subsequent read is performed at the
315. med in the PBTI1_CTL register on Table 92 on page 228 The Translation Address specifies the values of the address lines substituted when generating the address for the transaction on the QBus If no translation is to occur the Translation Address must be programmed with the same value as that of the Base Address see Transaction Decoding on page 61 and Address Translation on page 42 for more details 230 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 94 PCI Address Lines Compared as a Function of Block Size The read write type of this register depends on whether the PCI_BST1 register see Table 77 on page 212 is enabled For example whether bit 7 of byte 9 of the EEPROM is 1 or power up pin PCI_DIS is latched high during PCI reset There are two cases 1 Ifthe EEPROM bit is 1 or PCI DIS pin is latched high the BA field of PBTI1_ADD is read only and has the same value as the PCI_BST1 register from reset onwards 2 Ifthe EEPROM bit is 0 or the SDA pin and ENID pins are 0 at PCI reset or PCI_DIS pin is latched low then the entire BA field of PBTI1_ADD is readable and writable A read from this field after reset returns a 16 bit vector of Os In this case the BA field of this register is independent of the PCI_BST1 register the PCI_BST1 register does not exist The presence of EEPROM does not affect TA 31 16 QSpan II User Manual 231 8091862 001 08 Appendix A Registers Table 95 PCI
316. mm Top and Side Views 402 Figure 85 256 PBGA 17 mm Bottom 403 Figure 86 256 PBGA 27 mm Top and Side Views 404 Figure 87 256 PBGA 27 mm Bottom 405 QSpan II User Manual 17 8091862 001 08 List of Figures 18 QSpan II User Manual 8091862 001 08 List of Tables Table 1 QSpan II New Features and Functional 28 Table 2 Reset Options for QBus Slave 37 Table 3 Address Fields for QBus Slave 40 Table 4 Control Fields for QBus Slave Image 40 Table 5 Translation of QBus Address to PCI 4 44 Table 6 Command Type Encoding for Transfer Type 45 Table 7 Translation from QBus Transaction to PCI Transaction Type 46 Table 8 Little Endian QBus Slave Channel Cycle Mapping 47 Table 9 Big Endian QBus Slave Channel Cycle 48 Table 10 Translation of Cycle Termination from PCI Bus to 53 Table 11 MC68360 Cycle Terminations of QBus Slave 54 Tab
317. n IDMA peripheral for data transfer between the QBus and the PCI bus see Figure 2 For transfers going to or from PCI software can perform bulk data movement using the QSpan II s Channel The IDMA Channel supports single and dual address cycles and fast termination A separate set of IDMA handshake signals are provided on the QBus The IDMA Channel can be used by external QBus masters to read data from or write data to a PCI target in one direction at a time The IDMA Channel contains a 256 byte I FIFO and a set of IDMA registers for information see Chapter 5 The IDMA Channel on page 85 The DMA Channel QSpan II has a DMA Channel for high performance data transfer between the QBus and the PCI bus see Figure 2 The DMA controller uses the existing IDMA registers as well as a few additional registers and shares the 256 byte I FIFO with the IDMA Channel Because of the shared FIFO the QSpan II cannot use its IDMA and DMA Channels at the same time The DMA Channel operates in two modes Direct Mode and Linked List Mode In Direct Mode the DMA registers are programmed directly by an external master In Linked List Mode the DMA registers are loaded from PCI bus memory or QBus memory by the QSpan II for information see Chapter 6 The DMA Channel on page 95 The Register Channel QSpan II provides 4 Kbytes of Control and Status Registers QCSRs to program PCI settings as well as the QSpan II s device specifi
318. n II It also discusses general document elements and technical support information The following topics are discussed e What is the QSpan II on page 26 e Document Conventions on page 29 e Motorola MPC860 PowerQUICC User s Manual on page 30 e Related Documentation on page 30 QSpan II User Manual 25 8091862 001 08 Chapter 1 General Information 1 1 What is the QSpan II The QSpan II chip is a member of growing family of PCI bus bridging devices QSpan II enables board designers to bring PCI based embedded products to market faster for less cost and with high performance Developed as part of an ongoing strategic relationship with Motorola QSpan II is designed to gluelessly bridge the MC68360 QUICC the MPC860 PowerQUICC other MPCxxx devices and the M68040 M 68060 to PCI see Figure 1 With additional glue logic QSpan II can also be connected to lower end communications controllers and processors such as the MC68302 and MC68030 Figure 1 QSpan II Bridging PCI and Processor Buses Motorola MC68360 MPC860 MPC850 PCI J9 Me8040 MPC801 821 MC68302 MC68030 26 QSpan II User Manual 8091862 001 08 Chapter 1 General Information 1 1 1 QSpan Features QSpan II has the following features QSpan II User Manual 8091862 001 08 A direct connect interface to the PCI bus for Motorola s MC68360 and MPC860 communications c
319. n the MISC_CTL register see Table 127 on page 276 Note that except for termination signals with an MC68360 and for arbitration the QBus is always synchronous See Appendix B Timing on page 301 for the arbitration timing waveform QSpan II can hold onto the QBus for multiple transactions if the KEEP BB bit is set in the MISC CTL2 register see Table 130 on page 280 If set this configuration improves the performance of the PCI Target Channel by eliminating the arbitration delay The KEEP BB bit in the MISC CTL2 register see Table 130 on page 280 is not supported for DMA operation As such do not set this bit when the QSpan II DMA channel is used with the PowerQUICC memory controller UPM QSpan II User Manual 79 8091862 001 08 Chapter 4 The PCI Target Channel 4 7 3 4 8 4 8 1 4 8 2 80 M68040 Bus Arbitration When the QSpan II requires control of the M68040 bus it arbitrates for the bus by asserting BR_ When the QSpan II samples BG_ asserted and BB_ BGACK_ negated the QSpan II asserts BB_ BGACK_ and negates BR_ The M68040 Master Module s default operation is synchronous This default mode can be overridden by setting S_BG and S_BB to 0 in the MISC_CTL register see Table 127 on page 276 Note that except for termination signals with an MC68360 and arbitration the QBus is always synchronous See Appendix B Timing on page 301 for the arbitration timing waveform QSpan can hold onto the QB
320. nctionality H5 SWITCH Input to detect the state of the ejector latch and HS LED Open Drain Output to control the LED QSpan II User Manual 145 8091862 001 08 Chapter 12 CompactPCI Hot Swap Friendly Support 12 2 146 Figure 21 CompactPCI Hot Swap Functional Diagram QBus Interface Interface QBus Slave Channel PCL ag QBus Module 2 Module IFIFO IDMA I FIFO DMA PCI Bus Arbiter PCI Bus CompactPCI 1 0 Messaging Hot Swap Register Channel Interrupt Channel PCI Target PCI Target Channel Module QBus Processor Bus 8091862 BK001 01 Hot Swapping with the QSpan II The CompactPCI Hot Swap Specification defines a switch located in the ejector handle that indicates to QSpan II if the ejector handle is open or closed The specification also defines a LED that can be controlled by hardware and software by setting the LED On Off LOO bit in the CPCI_HS register see Table 86 on page 221 QSpan II drives the HS_LED signal low to turn on the LED during the Physical and Hardware Connection process when HS_HEALTHY_ is high and when the LOO bit is set to minimize the number of external components A blue LED with an internal resistor can be directly connected between the 5V rail and the HS_LED pin A low value on HS_SWITCH input indicates that the ejector latch is open A high value on HS_SWITCH indicates that the ejector latch is closed QSpan I
321. nd 32 bit read transfers through the PCI Target Channel in Little Endian mode to 32 bit QBus peripherals The byte lane ordering is preserved in Little Endian mode Table 21 Little Endian PCI Target Read Cycle Mapping 32 Bit QBus Port Transfer size BE 3 0 D 31 0 SIZ 1 0 A 1 0 D 31 0 4 xw The following table describes mapping of 8 bit 16 bit and 32 bit read transfers through the PCI Target Channel in Big Endian mode from 32 bit QBus peripherals The addressing of bytes is preserved in Big Endian mode Table 22 Big Endian PCI Target Read Cycle Mapping 32 Bit QBus Port Transfer size a 9 0 BO B1 xx xx xx xx B2 B3 BO B1 B2 All tri byte misaligned and non contiguous byte delayed read operations from a peripheral with a 32 bit QBus port size are performed as a series of 8 bit read operations would be from a 32 bit peripheral 0 0 0 1 1 1 1 1 1 0 QSpan II User Manual 71 8091862 001 08 Chapter 4 The PCI Target Channel 16 Bit QBus Port Tables 23 and 24 describe 8 bit and 16 bit read transfers from 16 bit QBus peripherals The following table describes mapping of 8 bit and 16 bit read transfers through the PCI Target Channel in Little Endian mode from 16 bit QBus peripherals The byte lane ordering is preserved in Little Endian mode Table 23 Little Endian PCI Target Read Cycle Mappin
322. nd Post_List FIFO Empty 0 Not Empty 1 Empty G_RST Outbound Post_List FIFO Empty 0 Not Empty 1 Empty Inbound Free_List FIFO Full 0 Not Full 1 Full G_RST G_RST G_RST 238 QSpan II User Manual 8091862 001 08 Inbound Post_List FIFO Full 0 Not Full 1 Full i Outbound Free List FIFO Full 0 Not Full Full Appendix A Registers CS Description Continued Reset Type Reset By State Function RST Outbound Post List FIFO Full 0 Not Full 1 Full FIFO_SIZE 2 0 This field specifies the size of the circular FIFO All four FIFOs are the same size and queue 32 bit entries Total FIFO memory allocation is four times the single FIFO size 000b 256 entries 1 Kbyte FIFO size 001b 1K entries 4 Kbyte FIFO size 010b 4K entries 16 Kbyte FIFO size 011b 16K entries 64 Kbyte FIFO size 100b 64K entries 256 Kbyte FIFO size others Reserved Register Read of Bottom Pointer 0 Register read of bottom pointer will return value of bottom pointer 1 same as 0 except when the top and bottom pointers equal returns OxFFFFFFFF 1 0 Enable 0 accesses to I 0 Inbound and Outbound Queue are enabled 1 accesses to Inbound and Outbound Queue disabled Writes are accepted but ignored reads return OXFFFF FFFF All pointer initialization and frame allocation should be completed before enabling this bit QSpan II User Manual 239 8091862 001 08
323. nd Pr FIFO on page 59 Address and data are stored as separate entries in the Px FIFO For example a single data transaction is stored as two entries in the Px FIFO one for the translated address and one for the data see Address Translation on page 64 Any reprogramming of PCI Target Image attributes will only be reflected in Px FIFO entries queued after the reprogramming Transactions queued before the reprogramming are delivered to the PCI bus with the PCI Target Image attributes that were in use before the reprogramming QSpan II never packs data in the Px FIFO For example two non burst 16 bit data beats are not packed as a single 32 bit data entry but as four separate entries in the Px FIFO 32 bit address 16 bit data 32 bit address 16 bit data Acceptance of Burst Writes by the PCI Target Module The PCI Target Module can accept burst write transactions from PCI bus Masters This section explains the following about PCI burst writes when PCI bursts are accepted how they are stored and how data is transferred on the QBus QSpan II will not accept a PCI burst write under the following conditions 1 If posted writes for the selected Target Image are disabled see Table 84 on page 219 or Table 92 on page 228 then each successive data phase is processed as a delayed single write When the write completes on the QBus the QSpan II issues a Target Completion the next time the transfer is attempted by the external PCI mast
324. nd to PCI configuration cycles The QSpan II supports both 5V and 3 3V I O signaling environments Highest I O voltage must be connected to the highest voltage level the QSpan II I Os will observe on either the QBus or the PCI bus C17 EEPROM Interface A serial EEPROM may be required for applications which must support a Plug and Play environment for more information about EEPROM reset options see Reset Options on page 365 QSpan II also allows that QBus processor to initialize the QSpan II to support a Plug and Play environment for more information see EEPROM Configuration and Plug and Play Compatibility on page 125 C 3 1 8 Reset Options QSpan supports a number of reset options The following signals are sampled on the rising edge of both RST and RESETI_ to determine the QSpan II s mode of operation e The BDIP_ signal must be pulled high and SIZ 1 pulled low at reset to enable the QSpan II to perform as an M68040 master The SIZ 1 signal must be pulled low at reset in order for the QSpan II to decode an M68040 cycle SDA and ENID signals should be pulled high if the EEPROM is used The SDA signal should be pulled low if the serial EEPROM is not used in this design The ENID signal can be left open if the serial EEPROM is not used as there is an internal weak pull down resistor e TMODE 1 0 signals can be left open as there are internal pull down resistors on these pins within the QSpan IL If an
325. ndix B Timing Table 154 Timing Parameters for MC68360 Interface Continued Frequency Temperature Options Timing Parameter Description Bass eee Units Note 194 CSREG_ setup to QCLK eT 2196 IMSEL setup to QCLK negative ns edge t219f _ setup to QCLK negative 19g SIZ setup to SIZ setup to QCLK negative edge negative SIZ setup to QCLK negative edge e eee NEN to20b AS_ hold from QCLK negative 0 5 0 5 ns edge t220c CSPCI_ hold from QCLK negative 1 ns edge t2204 CSREG_ hold from QCLK 1 5 1 7 ns negative edge t220e IMSEL hold from QCLK negative ns edge t220f R W_ hold from QCLK negative 1 ns edge t220g SIZ hold from QCLK negative ns edge to20h TC hold from QCLK negative ns edge t221 D setup master reads to QCLK ns negative edge t222 D hold master reads from QCLK 2 1 2 3 ns negative edge t223 D setup slave writes to QCLK ns positive edge t224 D hold slave writes from QCLK 1 8 2 ns positive edge t225 D asserted master writes from 10 9 ns 1 QCLK positive edge QSpan User Manual 305 8091862 001 08 Appendix B Timing Table 154 Timing Parameters for MC68360 Interface Continued Frequency Temperature Options Timing Parameter Description SES un Units Note ELE D tristated master from positive t234 BGACK tristated from QCLK 2 0 2 ns negative edge to35a BGACK_ negated from QCLK 3 2 7 4 3 6 8 2
326. ndix B Timing This appendix provides timing information for the QBus interface PCI interface timing is not detailed since the QSpan II is PCI 2 2 Specification compliant Timing parameters for all processors are listed first followed by the timing diagrams The following topics are discussed e Timing Parameters on page 302 e Wait State Insertion QBus Slave Module on page 316 e Timing Diagrams on page 317 B 1 Overview The timing tables described in this appendix include the following Table 154 Timing Parameters for MC68360 Interface on page 303 e Table 155 Timing Parameters for MPC860 Interface on page 308 e Table 156 Timing Parameters for M68040 Interface on page 312 e Table 157 Timing Parameters for Interrupts and Resets on page 315 e Table 158 Timing Parameters for Reset Options on page 315 The sets of diagrams described in this appendix include the following e QBus Interface MC68360 on page 317 e QBus Interface MPC860 on page 332 e OBus Interface M68040 on page 347 e Interrupts and Resets on page 357 e Reset Options on page 359 QSpan II User Manual 301 8091862 001 08 Appendix B Timing B 2 Timing Parameters Test conditions for timing parameters in Table 154 to Table 158 are e Test Conditions for 3 3V Commercial C 0 C to 70 C 3 3 5 Industrial D 40 C to 85 C 3 3V 596 Use the following figure as a reference when re
327. nects the QSpan II to the PCI bus The QBus Interface connects the QSpan II to the processor bus Both interfaces support master and slave transactions The QBus Interface can be directly connected to an MC68360 QUICC bus an MPC860 PowerQUICC bus or an M68040 bus The QBus Interface can also be connected to other buses with glue logic Each interface has two functional modules a Master Module and a Slave Target Module These modules are connected to QSpan II s functional channels QSpan II User Manual 31 8091862 001 08 Chapter 2 Functional Overview 2 2 32 Figure 2 QSpan II Functional Diagram QBus Interface Interface QBus Slave Channel POL MEM 3 5 QBus Master Slave Module IDMA DMA Channel Module PCI Bus Arbiter PCI Bus CompactPCI 10 Messaging Hot Swap Register Channel Interrupt Channel PCI Target PCI Target Channel Module MEM 2 QBus Processor Bus 8091862 BK001 01 The QBus Slave Channel The QBus Slave Channel transfers data between the QBus and the PCI bus see Figure 2 It supports posted writes prefetched reads and delayed single reads and writes Write transactions from the QBus to the PCI bus can be posted or delayed Posted writes are queued in the Qx FIFO with immediate data acknowledgment on the QBus QSpan then completes the write on the PCI bus For delayed reads the data is prefetched on the PCI bus and stored in the Qr FIFO Subs
328. nel are terminated on the QBus with a bus error For posted writes to the Qx FIFO and if error logging is enabled the QSpan II captures the discarded transfer in the PCI Error log QSpan II User Manual 8091862 001 08 Chapter 4 The PCI Target Channel 4 1 This chapter describes the QSpan II s PCI Target Channel The following topics are discussed e PCI Target Channel Architecture on page 58 e Channel Description on page 60 e Address Phase on page 61 e Data Phase on page 68 e Reads and PCI Transaction Ordering on page 77 e QBus Arbitration and Sampling on page 78 e Terminations on page 80 Overview An external PCI bus master can access a QBus slave through the QSpan II using its PCI Target Channel see Figure 5 The initialization of this channel is discussed in PCI Target Channel Initialization on page 383 QSpan II User Manual 57 8091862 001 08 Chapter 4 The PCI Target Channel 4 2 4 2 1 58 Figure 5 PCI Target Channel Functional Diagram QBus Interface Interface QBus PCI Target Channel Px FIFO Posted Writes 1 256 Bytes QBus Pr FIFO Master Module PCI Master DMA Prefetched Reads 256 Bytes PCI Target Channel Architecture Figure 5 shows the PCI Target Channel in relation to the QBus and the PCI bus The arrows represent data flow The QBus is shown as having one slave the PCI b
329. nerated directly from one of the high order address lines on the QBus for example dependent on the processor s memory map An alternative method is to use a spare I O port pin on the MPC860 processor to control the QSpan II s IMSEL input pin If the opposite QBus slave image is desired to be accessed the MPC860 first performs a write to change the state of this I O port pin QBus Direct Connects The bus interface signals can be directly connected together External pull up resistors should be connected to all bus control signals including SIZ 1 and BDIP which are reset options and should be pulled high to support MPC860 mode to ensure that they are held in the inactive state see Figure 76 to determine which signals require external pull ups QSpan II User Manual 8091862 001 08 Appendix C Typical Applications 2 1 5 Interrupts QSpan II can pass interrupts between the PCI bus and the QBus For host bridging applications the QSpan II can accept INT as an input and assert QINT_ as an output QSpan interrupt output QINT_ should be connected to one of the seven possible interrupt inputs IRQ 7 1 on the MPC860 processor For PCI adapter card applications the QSpan II can accept interrupts from the QBus on the QINT_ pin and pass them through the QSpan II to its PCI INT output Interrupts are described in Chapter 8 The Interrupt Channel on page 115 C 2 1 6 PCI Signals QSpan II s PCI signals can be dire
330. next address which is the current address 0x4 the QSpan II returns the data from Qr FIFO instead of completing another read on PCI Transaction ordering is strictly enforced for the first data read Before the read is completed on the PCI bus any posted writes in the Qx FIFO are emptied on the PCI bus Before the first read data is returned on the QBus any posted writes in the Px FIFO are emptied on the QBus When reading subsequent prefetched data from the Qr FIFO the QSpan II does not check whether the posted FIFOs Qx FIFO and Px FIFO are empty The prefetched data not including the first 4 bytes is invalidated under the following conditions e QBus discard timer expires 32768 QCLKs after the first read data is available e Delayed write cycle is latched in the QBus Slave Channel e Delayed read cycle to an address that is not the current address 0x4 or a non 4 byte access through the QBus Slave Channel e Burst MPC860 read cycle through the QBus Slave Channel QSpan II User Manual 8091862 001 08 Chapter 3 The QBus Slave Channel When the QSpan II detects a single read cycle that is not 32 bit aligned or is not a 4 byte access it performs a single read on the PCI bus with the appropriate byte enables If the QSpan II detects a prefetchable cycle when it is active during an MPC860 IDMA transfer DREQ_ asserted it converts the prefetch cycle into a normal delayed read cycle because the DACK_ can be delayed with respec
331. ng system to control the hardware an add in card for example that implements power saving features in a platform independent manner The Power Management interface supports the minimum requirements of powered up and sleep or low power states QSpan II does not implement any power saving features in silicon it merely passes the Power Management information between the Host OS and the I O subsystem The Power Management registers can be loaded from the EEPROM or programmed by the QBus Host before initialization by the Host 13 2 Power Management Event PME Support The QSpan II provides support for the PME output signal This signal is asserted to request a change in its current power management state and or to indicate that a power management event has occurred QSpan II asserts PME when the PME EN bit is set to 1 in the Power Management Control and Status PCI PMCS register and if the Power State bits PWR_ST in PCI are written to the value in PME support field in PCI PMCS register by the QBus Host The PME Status bit in PCI is set in the above case regardless of the setting of PME EN QSpan II negates PME if the PME Status bit is cleared or PME EN bit 1s disabled QSpan II User Manual 153 8091862 001 08 Chapter 13 PCI Power Management Event Support has additional electrical requirements beyond standard an open drain signal that allows it to be shared between devices which are powered off
332. nsfers from the processor s IDMA on the QBus Once the processor s IDMA is requested for write data it loads posted writes into the I FIFO When sufficient data is available in the I FIFO the QSpan II requests the PCI bus and begins bursting data to the PCI target This process continues until the number of transfers programmed in the QSpan II s IDMA DMA Transfer Count register completes see Table 111 on page 252 When programmed to perform IDMA transfers from the PCI bus to the QBus the QSpan II reads data from a PCI target and loads the data into the I FIFO As the I FIFO fills the QSpan II requests the processor s IDMA to transfer data from the QSpan II to the destination on the QBus The processor s IDMA then transfers data from the QSpan Is I FIFO until the number of transfers programmed into the QSpan II s IDMA registers completes or the QSpan II signals to the processor s IDMA that there is no additional data in the I FIFO 86 QSpan II User Manual 8091862 001 08 Chapter 5 The IDMA Channel QSpan can be programmed to operate as a QBus peripheral Although the QBus Master and Slave mode is determined at reset this does not affect the QBus Slave Module which dynamically accepts MC68360 QUICC or MPC860 PowerQUICC IDMA cycles The following list defines the IDMA Channel s features The Mode IMODE bit of the IDMA DMA_CS register see Table 109 on page 248 must be set to indicate whether or not the
333. oding QBUS_PAR bit the in MISC_CTL2 register see Table 130 on page 280 The default is Even parity which is the same as the PCI bus The detection of a QBus data parity error does not affect the operation of the QSpan II PCI bus parity generation and detection is independent of QBus data parity generation and detection Four pins are used for the QBus Data Parity signals DP 3 0 When parity is set to Even the number of ones on the QBus Data lines D 7 0 and DP 0 equal an even number Similarly for Odd parity the number of ones on D 7 0 and DP 0 equal an odd number e DP 0 contains the parity for Data lines D 7 0 e DP 1 contains the parity for Data lines D 15 8 e DP 2 contains the parity for Data lines D 23 16 e DP 3 contains the parity for Data lines D 31 24 The QBus Master Module generates the data parity when it completes a master write cycle If it detects a parity error during a master read cycle it sets the QBus Data Parity Error Status QDPE 5 bit in the INT STAT register see Table 119 on page 262 QSpan II can generate an external interrupt INT or QINT depending on the settings of the QDPE EN bit in the INT EN register and the QDPE DIR bit in the INT DIR register see Table 121 on page 268 Writing a 1 to the QDPE 5 bit in the INT STAT register negates the interrupt and clears the status bit see Table 119 on page 262 QSpan II only checks data parity on valid data If a single byte transfer is complet
334. of 8 bit read transfers through the PCI Target Channel in Big Endian mode from 8 bit QBus peripherals The addressing of bytes is preserved in Big Endian mode Table 26 Big Endian PCI Target Read Cycle Mapping 8 Bit QBus Port PCI bus Transfer size BE 3 0 D 31 0 SIZ 1 0 A 1 0 D 31 0 ome om o9 pom 1 All tri byte misaligned and non contiguous byte read operations from a peripheral with an 8 bit QBus port size are performed like a series of 8 bit read operations from an 8 bit peripheral A 32 bit read operation from a peripheral with an 8 bit QBus port size is performed as four 8 bit read operations from a peripheral with an 8 bit QBus port size A 16 bit read operation from a peripheral with an 8 bit QBus port size is performed as two 8 bit read operations from a peripheral with an 8 bit QBus port size QSpan II User Manual 73 8091862 001 08 Chapter 4 The PCI Target Channel 4 5 2 4 5 2 1 74 Data Path This section explains how data flows between the PCI bus and the QBus through the PCI Target Channel Posted Writes If the Posted Write Enable PWEN bit in the Target Image is 1 writes to the PCI Target Module are posted into the Px FIFO see Transaction Decoding on page 61 If the bit is cleared writes are treated as delayed transactions The default setting for the PWEN bit is 0 which is delayed transactions Write transfers are stored in the Px FIFO see Px FIFO a
335. of PCI Configuration and IACK Cycles on page 387 e EEPROM and VPD Initialization on page 388 e Messaging Unit Initialization on page 388 e PCI Expansion ROM Implementation on page 389 QSpan II User Manual 379 8091862 001 08 Appendix D Software Initialization D 1 Miscellaneous Control Register Configuration QSpan II has two general purpose control registers MISC_CTL and MISC_CTL2 which must be configured for the appropriate application for example MPC860 PowerQUICC MC68360 QUICC and M68040 processors For more information about the control registers see Tables 161 and 162 Table 161 Summary of the QSpan II s Miscellaneous Control Register MISC CTL MSTSLV 1 0 QB BOC S BG S BB SW RST MA BE D PRCNT Description This field determines the types of cycles the QSpan II Slave Module accepts and the type of cycles the Master Module generates Read this field to verify that the QSpan II has powered up in the correct mode of operation This bit determines whether the QSpan II generates Little endian or Big endian QBus cycles see also INVEND bit in PCI target and DMA control registers If using the MPC860 s arbiter use default settings If using the MC68360 s arbiter then these bits may be altered from their default settings for example set to 1 This will improve the performance by saving a clock cycle during arbitration This bit controls the assertion of RESETO Depending on
336. of the IDMA DMA transaction on the PCI bus PADD IDMA CNT 23 2 This register specifies the number of bytes which will be transferred DMA_CNT IDMA various Fields in this register should be set according to the transaction DMA_CS requirements see Table 109 on page 248 DMA_QADD Q ADDR 31 2 The starting address of the DMA transaction on the QBus DMA CS various Fields in this register should be set according to the transaction requirements see Table 113 on page 254 PCI CS Enables the QSpan II to become the PCI bus master Interrupts can be generated based on different IDMA or DMA event types The status bits in the IDMA CS or DMA CS register will cause an interrupt if enabled in the INT CTL register see Chapter 8 The Interrupt Channel on page 115 D 7 Interrupt Initialization QSpan II has many different interrupting capabilities See Chapter 8 The Interrupt Channel on page 115 for a detailed discussion These interrupt capabilities include software doorbells mailboxes error conditions DMA completion 1 0 power management and hardware interrupt sources There are enable bits for each interrupt source INT CTL register interrupt direction QBus or PCI bits for each source INT DIR register and interrupt status bits for each source in the INT STAT register 386 QSpan II User Manual 8091862 001 08 Appendix D Software Initialization D 8 Generation of PCI Configuration and IACK Cycles QSpan
337. on As an output the QSpan II asserts BB BGACK from the rising edge of QCLK while master QSpan II drives BB BGACK to the prior to tristate Note in the MPC860 mode the QSpan II asserts one clock after receiving BG in compliance with the MPC860 arbiter As an input the QSpan II samples BB BGACK the rising edge of QCLK QSpan II can also be programmed to use a asynchronous mode for QBus arbitration BDIP_ Bidirectional Burst Data In Progress As MPC860 master the QSpan uses BDIP_ in burst writes to indicate the second last data beat of a transaction This allows the QSpan II to perform burst writes of two three or four beats QSpan II does not use BDIP_ in the same manner for burst reads Burst reads are always cacheline aligned and four beats in length As MPC860 slave the QSpan II monitors BDIP_ as a signal indicating the second last data beat in the burst This allows the QSpan II to support bursts of two three or four data beats The QBus master mode of the QSpan is determined at power up and reset by sensing the level of this pin If BDIP_ is sampled as low at reset the QBus master module will operate as a MC68360 master At reset if the BDIP_ signal is sampled as high the QSpan II will operate as an MPC860 or M68040 master see Table 48 on page 158 BERR_ TEA_ Rescinding tristate bidirectional Transfer Error Acknowledge indicates that a bus error occurred in the current transaction Driven by the QSpan II
338. on 0 Map Inbound Post_List Full interrupt to QBus 1 Map interrupt to the PCI bus Outbound Free_List Full Interrupt Direction 0 Map Outbound Free_List Full interrupt to QBus 1 Map interrupt to the PCI bus EEEEEEEEEEERELE Appendix A Registers INT_DIR Description Continued Reset Name Reset By State Function SB_DIR G_RST Software Interrupt 3 Direction 0 Map software interrupt to the QBus 1 Map interrupt to the PCI bus SI2_DIR G_RST Software Interrupt 2 Direction 0 Map software interrupt to the QBus 1 Map interrupt to the PCI bus 5 DIR G RST Software Interrupt 1 Direction 0 Map software interrupt to the QBus 1 Map interrupt to the PCI bus SIO DIR G RST Software Interrupt 0 Direction 0 Map software interrupt to the QBus 1 Map interrupt to the PCI bus In order for an interrupt to be mapped to either bus it must also have its corresponding interrupt enable set in the Interrupt Control Register see Table 120 on page 265 270 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 122 Interrupt Control Register 2 Register Name INT_CTL2 Register Offset 60C Reserved Reserved Reserved Reset Reset By State Function W Read 0 Software Interrupt 3 Always 0 No effect 2 Sets SI3 IS status bit W Read 0 Software Interrupt 2 Always 0 No effect 1 Sets SD IS status bit QSpan II User Manual 271 8091862 001 08 Appendix A Registers Tabl
339. on Continued Reset Reset By State G_RST W Read 0 Always W Read 0 Always QSpan II User Manual 8091862 001 08 Appendix Registers Function Inbound Post_List New Entry Interrupt Enable 0 Disable interrupt 1 Enable interrupt when a new entry is posted into Inbound Post_List Inbound Free_List Empty Interrupt Enable 0 Disable interrupt 1 Enable interrupt when Inbound Free_List Empty Status is set Outbound Free_List Empty Interrupt Enable 0 Disable interrupt 1 Enable interrupt when Outbound Free_List Empty Status is set Inbound Post_List Full Interrupt Enable 0 Disable interrupt 1 Enable interrupt when Inbound Post_List Full Status is set Outbound Free_List Full Interrupt Enable 0 Disable interrupt 1 Enable interrupt when Outbound Free_List Full Status is set Software Interrupt 1 0 No effect 1 Sets SII IS status bit Software Interrupt 0 0 No effect 1 Sets SIO_IS status bit 267 Appendix A Registers Table 121 Interrupt Direction Register Register Name INT_DIR Register Offset 608 31 24 PEL_DIR QEL_DIR MDPED_DIR PCSR_DIR IQE DIR IPE DIR IRST_DIR DONE DIR 23 16 INT DIR PERR DIR SERR DIR OINT DIR MB3 DIR MB2 DIR MB1 DIR DIR 15 08 QDPE DIR PSC DIR OPNE DIR DIR IFE DIR OFE DIR IPF DIR OFF DIR 07 00 Reserved SI3 DIR SD DIR SI1 DIR 510 DIR INT DIR Description Reset Name Reset By State Function G RST PEL
340. ons the QSpan II can accept INT as an input and assert QINT as an output QSpan II s interrupt output QINT_ should be connected to the interrupt prioritizing logic which is connected to the IPL 2 0 lines on the M68040 processor When the M68040 is acknowledging a QSpan II interrupt there must be external logic to terminate the cycle External logic is required because the QSpan II is an autovector interrupter which does not have the ability to assert AVEC or TA_ during the interrupt acknowledge cycle For PCI adapter card applications the QSpan II can accept interrupts from the QBus on the QINT pin and pass them through the QSpan II to its PCI INT output see Chapter 8 The Interrupt Channel on page 115 for more information about interrupts QSpan II User Manual 8091862 001 08 Appendix C Typical Applications C 3 1 6 PCI Signals QSpan II s PCI signals can be connected directly to the appropriate PCI signal on the motherboard or the PCI connector Pull up resistors may be required to be added to the PCI bus control signals depending on the application If you are designing a local PCI bus on a motherboard then pull up resistors will be required for more information see the PCI 2 2 Specification For host bridging applications possible implementations for the QSpan II s IDSEL signal are as follows e connect it to a spare AD signal AD 31 12 connect it to ground through a resistor if the host is not required to respo
341. ontrollers and the M68040 Host processor QSpan compatible Support for up to 50 MHz MPC8xx bus frequencies industrial temperature range 40 C to 85 C Available in two low thermal resistance packages 17 mm x 17 mm PBGA and 27 mm x 27 mm PBGA Both packages have 3 3V power requirements and are 5V tolerant 32 bit PCI interface Integrated PCI bus arbiter Flexible high performance DMA engine which operates in both Direct and Scatter Gather mode Five FIFO buffers for multiple transactions in both directions Accepts and generates burst reads and writes on the PCI bus MPC860 UPM compliant burst reads and writes as processor bus master Separate channel supports MC68360 and MPC860 IDMA Flexible address space mapping and translation between the PCI and processor buses Programmable endian byte ordering Serial EEPROM interface for Plug and Play compatibility Support for PCI and processor bus operation at different clock frequencies IEEE 1149 1 JTAG boundary scan support CompactPCI Hot Swap Friendly support Support for Vital Product Data and Power Management IO Messaging Unit Mailbox registers for user designed message passing 277 Chapter 1 General Information 1 1 2 QSpan verses QSpan The following table summarizes the main QSpan II features that were unavailable in the QSpan device Table 1 QSpan New Features and Functional Enhancements Description Features DMA Channel The DMA Channel on page
342. opine Ped Seda eked cuerda 85 5 2 PCIReadTransactions 1 87 QSpan User Manual 7 8091862 001 08 Contents 521 Data edoceri de hr be UP Rer GU ebd eu wel a Gs v 88 9 9 PCI Waite Transactions si t ey aeu eR eee 89 Sod aed U 89 5 4 TC 3 0 Encoding with MPC860 1 90 35 IDMA Status Tracking Rub es Rh Rc Ae ee ee 91 5 6 Errors Resets and 91 24 Bndian Issues e UE 93 Chapter 6 The DMA E RR RR ES 95 OL OVerVIEW cis lancea epa or eigene bora eed eig debeas abc iso d daw dob edo eos 95 62 Registers o oc ciated ed deca iiaa Be e Rr i ee Se Ee ES Ede 97 OZE B rst Cycles ou ia eere doses e but de de tates eae 98 6 2 2 DMA Cycles on QBUS siar eee x dra e pe 99 6 3 Direct Mode DMA 99 6 3 1 Initiating a Direct Mode 99 6 3 2 Terminating a Direct Mode Transfer 100 6
343. opped 1 DMA transfer is stopped A DMA transfer in progress can be stopped by setting the STOP bit The DMA transfer is stopped once any active transfer is completed The STOP_STAT is set when the DMA is stopped To restart the DMA a 0 must be written to the STOP bit QSpan II User Manual 255 8091862 001 08 Appendix A Registers This register can be programmed from either bus The upper 12 bits 31 20 can also be loaded from a command packet when in Linked List mode The CP_LOC indicates the location of the command packet in either QBus or PCI Bus memory All the command packets in a linked list must be in either PCI or QBus memory and not both 256 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 114 DMA Command Packet Pointer Register Register Name DMA_CPP Register Offset 414 DE mw DMA_CPP Description Reset Name Type Reset By State Function CPP 31 4 G_RST DMA Command Packet Pointer This register contains the pointer to the next command packet Initially it is programmed to the starting packet of the Linked List and is updated with the address to the next command packet when a command packet is loaded from memory The packets must be aligned to a 16 byte address QSpan II User Manual 257 8091862 001 08 Appendix A Registers Table 115 Configuration Address Register Register Name CON_ADD Register Offset 500 Bits Function LAN EO
344. or is indicated by the ES bit of the QB_ERRCS register Transfers in the PCI Target Channel are suspended until the ES bit is cleared The QB_ERRCS register also records the TC and SIZ information of the transaction error The address of the transaction error is latched in the AERR register see Table 148 on page 294 The data of the transaction error is latched in the QB DERR register see Table 149 on page 295 If error logging is enabled and the PCI Target Channel is errored the Px FIFO is frozen until the ES bit in the ERRCS register is cleared Posted write operation continues with the next enqueued posted write once the ES bit of the ERRCS is cleared However if error logging is not enabled and the PCI Target Channel is errored the errored transfer is lost and posted write operation continues with the next enqueued transfer An interrupt is generated upon the logging of an error ES bit in ERRCS only if the QEL EN bit in INT CTL register is set see Table 120 on page 265 If generated the interrupt is directed to the QBus or the PCI bus depending on DIR bit in the INT DIR register see Table 121 on page 268 Interrupts are described in Chapter 8 The Interrupt Channel on page 115 QSpan II User Manual 8091862 001 08 Chapter 5 The IDMA Channel This chapter describes the QSpan II s IDMA Channel The following topics are discussed PCI Read Transactions on page 87 PCI Write Tran
345. ous mode of operation by setting the ASTM bit to 0 in the MCR register QSpan II User Manual 8091862 001 08 4 7 2 Chapter 4 The PCI Target Channel QSpan can operate synchronously because all timing parameters can be met by the MC68360 However the MC68360 must be programmed for asynchronous mode in order for the QSpan II to meet the MC68360 s input setup requirements See Appendix B Timing on page 301 for the arbitration timing waveform If the MC68360 s processing core is disabled Companion mode Slave mode an external arbiter must be implemented to support arbitration between the MC68360 and the QSpan II for more information see Appendix C Typical Applications on page 361 QSpan can hold onto the QBus for multiple transactions if the KEEP_BB bit is set in the MISC_CTL2 register see Table 130 on page 280 If set this configuration improves the performance of the PCI Target Channel and the DMA Channel by eliminating the arbitration delay MPC860 Bus Arbitration When the QSpan II requires control of the MPC860 bus it arbitrates for the bus by asserting BR_ When the QSpan II samples BG_ asserted and BB_ BGACK_ negated the QSpan II asserts BB_ BGACK_ and negates BR_ QSpan II asserts BB_ one clock after BG_ in accordance with MPC860 arbitration requirements The MPC860 Master Module s default arbitration mode is synchronous This default mode can be overridden by setting 5 BG and 5 BB to 0 i
346. pan II also increases the BP by four BP 0 000 1004 The OP ISR status bit is cleared if the OP FIFO is empty 5 The Host processor then reads the message pointed by the MFA and consumes it 6 The Host then releases the used MFA by writing to offset 0x044 from 2 BAR see Table 74 on page 209 This causes QSpan to generate a QBus write cycle at address TP 0xA000 1994 with the MFA as the data Upon completion of the write the QSpan II increments the IOF_TP by four IOF TP 0 000 1998 The four pointers updated automatically by QSpan II are BP TP BP and TP When the pointer is at the top of the FIFO the next increment puts it at the bottom of the FIFO the increments are accomplished on a modulo boundary of the FIFO SIZE The other four pointers TP BP IOP TP and IOF BP must be incremented by the QBus Host This is achieved by completing a QBus register write with 7 the new pointer value The two Top pointers incremented by QSpan IIP TP and IOF TP are not incremented if the corresponding FIFO becomes full Likewise the two Bottom pointers IIF BP and IOP_BP are not incremented if the corresponding FIFO is empty 10 6 LO Interrupts QSpan provides status bits in Control and Status I20_CS register for each of the four I O list FIFOs to indicate if they are empty or full see Table 100 on page 238 A PCI interrupt can be generated wh
347. phases The number of address lines compared for this image is based on the value of the Block Size field in the PBTIO CTL register see Table 89 on page 224 and Transaction Decoding on page 61 for more information If this register is enabled the number of writable bits in BA 31 16 is determined by the Block Size field of the PBTIO CTL register After power up the serial EEPROM contents are loaded and a PCI host can write all 1s to the BA field of this register The number of 1s that are read back can be used to compute the block size of the image Block Size 64Kbytes 2N For example if the Block Size is 64 Kbytes BS 0000 then the BA field will be OxFFFF If the Block Size is 2 Gbytes BS 1111 then the BA field will be 0x8000 210 QSpan II User Manual 8091862 001 08 Appendix A Registers The PREF bit can be loaded from the EEPROM or programmed from QBus This bit does not enable prefetching on the QBus The PREN bit in PBTIO_CTL register must be set to enable prefetching on QBus Table 76 PCI Address Lines Compared as a Function of Block Size QSpan II User Manual 211 8091862 001 08 Appendix A Registers Table 77 PCI Configuration Base Address for Target 1 Register Register Name PCI_BST1 Register Offset 01C 31 24 23 16 07 00 PCI_BST1 Description Reset Name Type Reset By State Function BA 31 16 PCI RST EE Base Address of PCI Target Image 1 Below PREF R WQ E PCI RST See Prefetch
348. pics are discussed e Mode Pins on page 159 e JTAG Support on page 160 e Decoupling Capacitors on page 160 15 1 Test Mode Pins QSpan II can operate in normal mode or test mode In test mode a NAND tree is activated and all outputs are tristated except for the SCL output pin The output of the NAND tree is on the SCL pin QSpan II has two test mode input pins TMODE 1 0 For normal operations these inputs must be pulled down The following table indicates the operation modes of the QSpan II as a function of the TMODE 1 0 input At reset the TMODE 1 0 inputs are latched by the QSpan II to determine the mode of operation QSpan II remains in this mode until the TMODE 1 0 inputs have changed and a reset event has occurred Table 49 Test Mode Operation TMODE 1 0 Operation Mode QSpan II User Manual 159 8091862 001 08 Chapter 15 Hardware Implementation Issues 15 2 JTAG Support The QSpan II includes dedicated user accessible test logic that is fully compatible with the IEEE 1149 1 Standard Test Access Port and Boundary Scan Architecture The following pins are provided TCK TDI TDO TMS and TRST There is an internal pull up resistor on TMS which will keep the QSpan II s JTAG controller in a reset state without requiring TRST to be low 15 3 Decoupling Capacitors When routing the power Vpp and ground Vss tracks to the QSpan II during board layout care should be taken to ensure that the Q
349. pping Enable 1 When the QSpan II receives a PCI Target Abort it maps it to a Bus Error termination on the QBus for delayed cycles QBus Burst 4 Data phases for PCI target channel write transfers 0 QSpan II will generate partial burst on QBus 2 or 3 data phases 1 QSpan II will only generate QBus burst with 4 data phases required for use with MPC860 s memory controller 0 When QSpan II receives a PCI Target Abort it maps this as a normal termination on the QBus if MA_BE_D BURST_4 G_RST PR_SING G_RST QBus Prefetch Single Dataphase 0 QSpan II will prefetch using burst cycles as an MPC860 master 1 QSpan II will generate single cycles to prefetch data as an MPC860 master 000001 Prefetch Read Byte Count 2 This field controls how much data the Qspan II prefetches on the QBus for an access through the PCI target image 1 when above PTP IB bit is set The number of bytes prefetched is 4 times the number programmed into this field for example 001100 is 48 bytes QBus Slave Channel Posted Write 0 Default mode for QSpan CA91C860B CA91L860B backward compatibility bit in MISC is set to 1 If MA BE D is set to 0 then both PCI Master Abort and Target Abort terminations are translated to a Bus Error on QBus for delayed cycles PR CNT2 5 0 G RST QSC PW G RST 1 Improves the dequeuing of posted writes in the QBus Slave Channel REG AC G RST Register Access Control 0 Normal Mode register
350. ption Reset Name Type Reset By State Function ADDRIT 01 0 PCI RST EEPROM read and writeaddress read and write address E PCI RST EEPROM read and write PCI_RST EEPROM Active 0 No 1 Yes READ R W PCI_RST EEPROM Read bit 0 Write to EEPROM 1 Read to EEPROM This register is provided for users to read to or write from the EEPROM through the QBus or the PCI bus This register accepts reads or writes when the ACT bit is 0 therefore the ACT bit might need to be polled before a write is attempted The ACT bit is 1 when the QSpan II is loading data from the EEPROM or is in the process of completing a read or write to the EEPROM caused by an access to this register Writes complete on the QBus or the PCI bus regardless of the state of the ACT bit and therefore regardless of whether the write to the DATA field was effective It there is no EEPROM the SDA pin and ENID pin are low at PCI reset then this register is read only and reads return all zeros see Programming the EEPROM from the QBus or PCI Bus on page 129 for more information Access to EEPROM can be enabled after power up using the EEPROM_ACC bit in the MISC_CTL2 register see EEPROM Access on page 130 QSpan II User Manual 279 8091862 001 08 Appendix A Registers Table 130 Miscellaneous Control 2 Register Register Name MISC_CTL2 Register Offset 808 Bits Function 31 24 PCI DIS Reserved 23 16 PTP IB KEEP BB MAX RTRY
351. r In both address and data phases the PAR signal provides even parity for C BE 3 0 and AD 31 0 The PERESP Parity Error Response bit in the PCI CS PCI Configuration Space Control and Status register determines whether or not the QSpan II responds to parity errors as PCI master see Table 70 on page 203 Data parity errors are reported through the assertion of PERR if the PERESP bit is set The Detected Parity Error D PE bit in the PCI CS register is set if the QSpan II encounters one of the following situations e aparity error during an address phase e aparity error during a write when QSpan II is the target aparity error during a read when QSpan II is the master The Master Data Parity Error Detect MD PED bit in the PCI CS register is set if parity checking is enabled through the PERESP bit and the QSpan II detects a parity error while it is PCI master for example it asserts PERR during a read transaction or receives PERR during a write If the QSpan II sets the MD PED bit while the MDPED EN Data Parity Detected Interrupt Enable bit in the INT register is set see Table 120 on page 265 then the QSpan II asserts an interrupt on the QBus or PCI bus interface see Chapter 8 The Interrupt Channel on page 115 QSpan II continues the transaction regardless of any parity errors reported during the transaction QSpan II User Manual 8091862 001 08 Chapter 3 The QBus Slave Channel 3 6 Term
352. r is enabled at power up if the PCI ARB EN pin is sampled high at the negation of Reset The request lines of the external bus Masters can be connected to the and EXT REQ 1 6 1 pins Any unused request pins must be externally pulled up The grant lines of the external bus Masters can be connected to GNT and 6 11 If an external arbiter is used the QSpan II uses the REQ GNT line to acquire the PCI bus QSpan II drives the unused 6 11 and EXT_GNT 6 1 high when an external arbiter is used QSpan II User Manual 141 8091862 MAOOI 08 Chapter 11 PCI Bus Arbiter Figure 19 PCI Bus Arbiter Functional Diagram QBus Interface Interface QBus Slave Channel PCI Bus Arbiter Bus QBus QBus Target PCI Target Channel Master Module E Module P FIFOs 11 2 Arbitration Scheme To maintain arbitration fairness the PCI bus arbiter assigns bus masters to one of two priority levels Level 0 or Level 1 see Figure 20 Bus Masters assigned to Level 0 are of lower priority than Masters assigned to Level 1 Bus Masters assigned to the same level have equal priority in the arbitration scheme Bus Masters on Level 0 get a single access during each round robin arbitration on Level 1 Arbitration is performed among Masters asserting request to the QSpan II s PCI bus arbiter The bus arbiter removes a grant to a master if it has not started an access after its gran
353. rer by setting the Register Access Control REG AC bit in MISC CTL2 see Table 130 on page 280 If this bit is set the register access port is parked at the bus that completed the last register access For example if there was a QBus register access then the register access port defaults to the QBus Any additional QBus register access receives an immediate response while a PCI register access gets retried first and then succeeds when the register access port switches to the PCI bus If register access is performed mainly from the QBus set the AC bit in the MISC CTL2 register see Table 130 on page 280 106 QSpan II User Manual 8091862 001 08 Chapter 7 The Register Channel 7 3 Register Access from the PCI Bus The QCSRs can be accessed through Configuration cycles or in Memory space see the following figure These accesses are discussed in the following sections Default ownership of the Register Channel is granted to the PCI Target Module If an external master on the PCI bus attempts to access the registers of the QSpan II and the ownership has been granted to the QBus Slave Module the transfer will be retried on the PCI bus Figure 11 QSpan II Control and Status Registers 4 Gbytes QSPAN II of Memory DEVICE Space SPECIFIC All 4 Kbytes of REGISTERS QCSRs Accessible in Memory Space Accessible through PCI PCI Configuration CONFIGURATION Cycle Es SPACE PCICS Y
354. rmines when the QSpan II will begin to burst the data onto the PCI bus Table 109 on page 248 Once the I FIFO contents equal IWM the QSpan II burst writes up to the values of IWM throttled only by the PCI target The IWM must not be programmed with a value greater than the IDMA transfer byte count e The CLINE 1 0 field of the PCI MISCO register determines the length of the burst writes initiated by the PCI Master Module see Table 72 on page 207 The burst writes are either four or eight 32 bit transfers if the IWM bit is set to zero e IDMA DMA PADD register see Table 110 on page 251 contains the absolute PCI address for an IDMA transaction This number is aligned to a 4 byte boundary An IDMA transfer wraps around at the A24 boundary If an IDMA transfer is required to cross an A24 boundary it must be programmed as two separate transactions The IWM must not be programmed with a value greater than the IDMA transfer byte count e IDMA DMA register indicates the number of bytes to transfer in an IDMA transaction see Table 111 on page 252 CMD bit in the IDMA DMA CS register determines whether the write transaction on PCI proceeds as a Memory Write Invalidate or a Memory Write transfer see Table 109 on page 248 Once all the relevant data is programmed in the IDMA register the GO bit in the IDMA DMA CS register must be set to 1 to initiate the IDMA transfer Any status bit IRST DONE IPE or IQE
355. rom the address specified by the VPD Address The VPD data register is written with the 4 bytes of data Byte 0 register bits 7 0 contains the data to be written to the location referenced by the VPD address bytes 1 3 contain the data for the successive bytes The VPD Address and VPD flag then must be written The VPD flag bit must be set to 1 to indicate a VPD write The VPD flag bit must be polled to determine when the write to the EEPROM is completed QSpan II sets the VPD flag bit to 0 when the write is completed The PCI or EEPROM CS register must not be written while a write operation is taking place otherwise results are unpredictable If a read or write is attempted to VPD address above OxEO then the QSpan II does not perform any EEPROM access and the VPD address will contain the previous value QSpan II User Manual 131 8091862 001 08 Chapter 9 The EEPROM Channel 132 QSpan II User Manual 8091862 001 08 Chapter 10 LO Messaging Unit This chapter discusses the IO Messaging Unit capabilities of QSpan II The following topics are described e Inbound Messaging on page 134 e Outbound Messaging on page 135 e 5O Operation on page 136 Summary of I O Operations on page 136 e 5O Interrupts on page 139 10 1 Overview QSpan II s 1 0 Messaging Unit reduces Host processor utilization by using an I O processor to complete I O transactions QSpan II is compliant with LO Spec
356. rresponding enable bit must be set in the INT_CTL register see Table 120 on page 265 For example for INT to trigger QINT_ the INT_EN bit must be set The status of the interrupt is logged in the INT_STAT register It is only possible to route interrupts in one direction at a time For example it is not possible to allow PCI interrupt sources to be mapped to 5 QINT_ while allowing QINT_ sources to be mapped to INT Figure 14 Interrupt Channel Functional Diagram QBus Interface Interface QBus Master Slave Module Module PCI Bus QBus Register Channel Interrupt Channel PCI QBus Target Master Module Module 116 QSpan II User Manual 8091862 001 08 Chapter 8 The Interrupt Channel Table 41 Mapping of Hardware Initiated Interrupts Enable bits Status Bits INT_CTL see Table 120 INT_STAT see Input on page 265 Table 119 on page 262 Output INT INT_EN INT_IS QINT_ PERR PERR_EN PERR_IS SERR SERR_EN SERR_IS QINT_ QINT_EN QINT_IS INT If INT_EN is set then the assertion of INT causes QINT_ to be asserted until INT is negated and the INT_IS bit is cleared Because INT is level sensitive if the INT_IS bit is cleared before INT is negated the clearing of the bit will have no affect and QINT_ will remain asserted To negate QINT_ when its assertion is caused by the assertion of PERR or SERR complete the following procedure 1 Clear the error status bit in the source PCI device
357. rrupt is controlled by the PCSR bit in the INT DIR register see Table 121 on page 268 QSpan II generates the interrupt and sets the PCSR IS bit in the INT STAT register when any of the following status bits is set see Table 119 on page 262 DPE e 5 SERR RMA R TA S TA e excluding MD PED 120 QSpan II User Manual 8091862 001 08 8 4 8 5 Chapter 8 The Interrupt Channel The MD_PED bit already generates an interrupt so this functionality will not cause the PCSR_EN status bit to be set To clear the interrupt and interrupt status bit write a 1 to PCSR_IS in the INT_STAT see Table 119 on page 262 Interrupt Acknowledge Cycle Reading the IACK_GEN register from the QBus causes an IACK cycle to be generated on the PCI bus see Table 118 on page 261 The byte lanes enabled on the PCI bus are determined by SIZ 1 0 and A 1 0 of the QBus read The address on the QBus used to access the IACK GEN register is passed directly over to the PCI bus during the PCI IACK cycle However address information is ignored during PCI IACK cycles so this has no effect Reads from this register behave as delayed transfers the QBus master is retried until the read data is latched from the PCI Target When the IACK cycle completes on the PCI bus the data is latched into the GEN register which is returned as read data when the QBus master attempts the cycle again Writing to this register from the QBus or PCI bus
358. s INT STAT register see Table 119 on page 262 QSpan II can generate an external interrupt INT or QINT depending on the setting of QBus Data Parity Error Interrupt Enable QDPE_EN bit and QBus Data Parity Error Interrupt Direction QDPE DIR bit in INT EN and INT DIR registers respectively Writing a 1 to the QDPE_S bit negates the interrupt and clears the status bit QSpan II User Manual 37 8091862 001 08 Chapter 3 The QBus Slave Channel 3 2 2 3 2 3 3 3 38 When the QBus Slave Module detects a parity error it sets the QDPE_S bit but continues the transfer as if there were no parity error For example if a write is directed to the QSpan II with a data parity error the QBus Slave Module terminates the cycle normally and passes it onto the QSpan II s PCI interface QSpan II s PCI master generates the write cycle with the correct parity for the data on the PCI bus QSpan II only checks data parity on valid bytes of data If a single byte transfer is completed on the QBus only the valid byte on the data bus is checked for example 0 31 24 Qx FIFO Qr FIFO The Qx FIFO is a 256 byte buffer for posted writes from the QBus to the PCI bus The Qx FIFO supports sixty four 32 bit entries The Qx FIFO accepts data from an external QBus master while transferring data to a PCI target for information see Writes on page 48 The Qx FIFO is on the data path for single delayed writes A delayed write must be
359. s AT 0 3 but can be used for other special decoding purposes Rescinding tristate bidirectional See BERR TEA TRETRY Rescinding tristate bidirectional See HALT TRETRY _ TS Rescinding Tristate bidirectional Transfer Start TS is a three state bi directional signal used to indicate the beginning of an MPC860 bus transaction on the QBus The TS output is driven by the QSpan II when the QSpan II is the QBus master and is tri stated at all other times As an output TS_ is driven low after a rising edge of the QCLK Transfer Start indicates the following signals will be valid on the next rising edge of the QCLK A 31 0 TC 3 0 SIZ 1 0 and R W QSpan II rescinds TS prior to tri state As an input TS is sampled on the rising edge of the QCLK QSpan II samples the address bus and other TS_ qualified signals on the same rising edge of QCLK in which it samples TS asserted CSPCI_ and CSREG_ may have up to three wait states after TS_ is sampled The following table applies to MC68360 and MPC860 SIZ 1 0 signals Table 51 MC68360 MPC860 Encoding for the SIZ 1 0 Signal QSpan II QSpan II QSpan II SIZ 1 SIZ 0 Master MC68360 slave MPC860 slave s o ome Lo umo 170 QSpan II User Manual 8091862 001 08 Chapter 16 Signals 16 5 M68040 Signals A 31 0 Tristate bidirectional Address bus Address for the current bus cycle It is driven by the QSpan II
360. s accordingly for example pin A 31 on the QSpan II connects to pin A 0 on the MPC860 Address Multiplexing for DRAM Whenever DRAM is used on the QBus external address multiplexing is required This is described in the MPC860 UM AD QSpan II User Manual 8091862 001 08 Appendix C Typical Applications C 2 1 14 Software Issues When using the MPC860 with the QSpan there are a few register bits that must be changed from the MPC860 s default reset state These register bits include the following e MLRC bits in the MPC860 s SIUMCR register must be changed to 10 state This configures the KR RETRY IRQ4 SPKROUT pin to function as a RETRY input e The SEME bit in the MPC860 s SIUMCR register must be set to a 1 because the QSpan II is a synchronous external master e The SETA bit in the MPC860 s Option register must be set to a 1 for the two QSpan II chip selects CSREG_ and CSPCI QSpan II will always provide the cycle termination to the MPC860 e The BIH bit in the MPC860 s Option register must be set to 1 for the QSpan II s register chip select CSREG QSpan PCI chip select CSPCI pin supports burst accesses when using the MPC860 s GPCM Therefore the BIH bit can be set to either state The 860 User s Manual states that the GPCM machine does not support burst accesses however with the QSpan II s architecture it will function correctly for the CSPCI_ chip select QSpan II User Manua
361. s how the QSpan II translates cycles from the QBus to the PCI bus The PCI bus is always a Little Endian environment The QBus can be configured as Little Endian or Big Endian depending on the value of the QBus Byte Ordering Control bit BOC in the MISC register see Table 127 on page 276 The default mode for the QBus is Big Endian QSpan II translates byte lane ordering when the QBus is Big Endian while preserving the addressing of bytes When the QBus is Little Endian the QSpan II preserves byte lane ordering while translating the addressing of bytes Note that the QB_BOC bit affects transactions in all channels 46 QSpan II User Manual 8091862 001 08 Chapter 3 The QBus Slave Channel The following tables describe cycle mapping for Little Endian and Big Endian of all sizes 8 16 24 or 32 bits Table 8 Little Endian QBus Slave Channel Cycle Mapping ow xx B2 B1 BO 1000 xx B2 B1 BO QSpan II User Manual 47 8091862 MAOOI 08 Chapter 3 The QBus Slave Channel 3 5 2 3 5 2 1 48 Table 9 Big Endian QBus Slave Channel Cycle Mapping PCI Bus o m eee Low ow e poem Lo e o pom poems om Low ow poemes om essem Low ow posee pom T omes Low os poems om T ow o Data Path Writes If the PWEN bit is set in the QBSIx_CTL register single write transactions from the QBus will be poste
362. s master receives a translated version of the QBus termination The following table shows how QBus terminations are translated to the PCI bus in the case of delayed transactions As this table shows the PCI Target Module generates a Target Abort when a delayed transfer results in a bus error on the QBus QSpan II User Manual 83 8091862 001 08 Chapter 4 The PCI Target Channel 4 8 6 84 Table 30 Translation of Cycle Termination from QBus to PCI Bus QBus Termination Received PCI Bus Termination Issued a This table applies to read transactions and delayed write transactions b This cycle is not translated The PCI Target Module retries the PCI bus master during delayed transactions until the QBus Master Module receives a normal termination or a bus error Terminations of Posted Writes PCI bus terminations of posted writes are not influenced by QBus terminations If a posted write leads to a bus error on the QBus this termination is not signalled on the PCI bus to the PCI bus master However errors on the QBus are accessible to PCI Masters through error logging registers if error logging is enabled by the EN bit of the QB ERRCS register QBus errors can be configured as a source of interrupts If the EN bit in the ERRCS register see Table 147 on page 293 is set then the QSpan II records the address transaction code data and size of a posted write transaction that results in a bus error In this case an err
363. s of the PCI memory image for access registers size of image is 4K D 4 PCI Target Channel Initialization There are two possible memory ranges on the PCI bus which can be used to gain access to QBus memory These two ranges and the associated registers which need to be programmed to access them are referred to as target images Each PCI target image can have independent features as described in the following table To support two PCI target images you must program both PCI Target Image 0 and Image 1 registers Table 166 PCI Target Image Programming Summary B Set this bit to allow the QSpan II to respond to PCI Memory space cycles This is a global bit the PAS bit of each specific image also needs to be set Set this bit to allow the QSpan II to respond to PCI I O space cycles This is a global bit the PAS bit of each specific image also needs to be set QSpan II User Manual 383 8091862 001 08 Appendix D Software Initialization Table 166 PCI Target Image Programming Summary Continued PBTIO_CTL EN Set this bit to enable the Target image and or PWEN Set this bit to 1 to allow write transactions to be posted this improves system throughput PREN Set this bit if the PCI Initiator is attempting to perform PCI burst reads This bit is used in conjunction with the PRCNTx field in the MISC_CTL and MISC CTL2 registers BRSTWREN Set this bit to enable the QSpan II to perform burst transac
364. s require a write control signal This signal should not be pulled inactive if the intention is to program the EEPROM device with the QSpan II then the EEPROM s contents may not be loaded correctly If RESETI_ is asserted when the QSpan II is reading from the EEPROM 9 4 Mapping of EEPROM Bits to QSpan II Registers This section describes the mapping between EEPROM bits and the QSpan 5 registers The following registers can be programmed by the EEPROM 126 PCI Configuration PCI SID register see Table 79 on page 214 PCI Expansion ROM PCI BSROM and registers see Table 80 on page 215 and Table 95 on page 232 PCI Bus Target Image 0 PCI BSTO and registers see Table 75 on page 210 and Table 89 on page 224 PCI Bus Target Image 1 PCI and PBTI1_CTL registers see Table 77 page 212 and Table 92 on page 228 QBus Slave Image 0 QBSIO CTL and QBSIO AT registers see Table 133 on page 285 and Table 138 on page 287 PCI Configuration Space ID PCI ID register see Table 69 on page 202 PCI Configuration Class PCI CLASS register see Table 71 on page 206 PCI Configuration Miscellaneous 1 PCI MISCI register see Table 83 on page 218 Miscellaneous Control 2 MISC CTL2 register see Table 130 on page 280 PCI Power Management Capabilities PCI PMC register see Table 84 on page 219 QSpan II User Manual 8091862 001 08 Chapter 9 The EEPROM Channel e P
365. s to determine the address allocation for the QSpan II based board It does this by writing all 1s to the BA field of the PCI BSTx register and then reading back from the same location The number of bits in the BA field of the PCI BSTx register that are writable is determined by the Target Image s block size BS 3 0 field in the PBTIx_CTL register For example if the PCI Target Image is programmed to a block size of 128 Mbytes then the BS field in the PBTIx CTL register has been programmed to all 1s see Table 18 on page 66 This means that only the most significant five bits of the BA field of PCI BSTx register are writable When the BIOS reads back from the BA field in the PCI 5 register the read returns only the most significant five bits of BA as 1 indicating a 128 Mbyte image size QSpan II User Manual 67 8091862 001 08 Chapter 4 The PCI Target Channel 4 5 4 5 1 4 5 1 1 68 When PCI address information is not loaded from an EEPROM or initiated by the processor on the QBus the base address can only be set through the PBTIx_ADD registers The PBTIx_ADD registers do not support the image sizing functionality described in the previous paragraph Data Phase Endian Mapping This section describes how the QSpan II translates cycles from the PCI bus to the QBus The PCI bus and Motorola processors differ in the way they order and address bytes These differences are explained in Appendix Endian Mapp
366. sabled DSACKO_ is not asserted CSPCI_ is negated during single address IDMA cycles QSpan II User Manual 325 8091862 001 08 Appendix B Timing Figure 35 MC68360 IDMA Write Single Address Standard Terminations Ons 50ns 100ns 150ns 200ns 250ns p oed ue e ap ap om qe ds dero qs veas rop dle ae dy do ALT 1201 5 QCLK 112536 gt 1259 CSPCI_ k t253a gt 259 AS A 31 0 gt 259 gt 1258 D 31 0 231254 gt 25948 _ DONE gt 255 259 DSACKO_ gt 1255 amp 259 DSACKI 1256 gt e t259f BERR gt 1257 t2599 HALT a Normal gt 1255 amp 259 DSACKO gt 1255 amp 259 1_ 1256 gt e t259f BERR p 1257 gt 125909 HALT p b Bus Error gt 1255 e t259e DSACKO gt 255 1259e DSACKI k t256 gt t259F BERR_ 1257 gt 2590 HALT_ c Retry 326 QSpan II User Manual 8091862 001 08 Appendix B Timing Figure 36 MC68360 IDMA Read Single Address Fast Termination Ons 25ns 50ns 75ns 100ns 125ns to tl 4 t201 gt QCLK 1253b 9 t259b CSPCI N 24259 k 1253a
367. sactions on page 89 TC 3 0 Encoding with MPC860 IDMA on page 90 IDMA Status Tracking on page 91 IDMA Errors Resets and Interrupts on page 91 IDMA Endian Issues on page 93 5 1 Overview QSpan II can operate as a QBus IDMA peripheral or a DMA master for data transfers between the QBus and the PCI bus see Figure 7 For transfers going to or from the PCI bus software can perform bulk data movement using the QSpan II s IDMA or DMA Channel The IDMA Channel supports single address and dual address cycles and fast termination QSpan II User Manual 8091862 001 08 IDT recommends using the DMA Channel instead of the IDMA Channel because it supports higher rates of data transfer between the PCI bus and the QBus 85 Chapter 5 The IDMA Channel Figure 7 IDMA Channel Functional Diagram QBus Interface Interface IDMA DMA Channel Module PCI Target Module The IDMA Channel contains a bi directional 256 byte 64 entry deep FIFO called I FIFO IDMA transactions are initiated on the QBus The IDMA Channel can only access PCI Memory space it cannot access I O or Configuration space The QBus Slave Module accepts IDMA read and write transfers of 16 or 32 bits The MPC860 s IDMA must be programmed for level sensitive mode with the QSpan II edge sensitive mode is not supported When programmed to perform writes to the PCI bus the QSpan II requests tra
368. sed when PCI Reset RST or QBus Reset input RESET1_ is driven low or H5 HEALTHY is driven high QSpan II User Manual 155 8091862 001 08 Chapter 14 Reset Options 14 1 1 14 1 2 14 1 3 156 The QBus Software Reset Control SW_RST bit in the MISC_CTL register see Table 127 on page 276 controls the QBus Reset output RESETO One of the uses of this mechanism is to keep the QBus in reset while an operating system and driver are downloaded to on board memory When a 1 is written to the SW_RST bit the QSpan II asserts RESETO and keeps it asserted until the software reset state is terminated There are three ways to cause the QSpan II to terminate the software reset state 1 Clear the SW bit by writing 0 to it In this case RESETO is immediately negated 2 Assert RESETI In this case the SW bit is immediately cleared set to 0 and RESETO is immediately negated 3 Assert RST In this case SW RST is immediately cleared set to 0 however RESETO continues to be asserted until RST is negated addition asserting the SW bit does not cause an internal reset of the We do not recommend RESETO being looped back to RESETI In N QSpan II PCI Transactions during QBus Reset Assertion of RESETI may interfere with the QSpan II s response to PCI Masters If a PCI master attempts to access the QSpan II while RESETI is asserted the QSpan II will not decode the incoming cycle and a Master Abort will
369. sfer and there is not enough room in the Qx FIFO for the complete burst The QBus Slave Module never retries an ongoing burst transaction e A prefetched read is in progress in the QBus Slave Channel A delayed transfer read or write is in progress in the QBus Slave Channel The QBus Slave Module generates a bus error under the following conditions e A QBus master attempts to burst to a Slave Image whose transfers have been set to I O space QSpan II User Manual 53 8091862 001 08 Chapter 3 The QBus Slave Channel e delayed transfer or a prefetched read results in a Target Abort and the MA BE D bit in the MISC CTL register is 0 or the MA BE D bit is 1 and the BE EN bit in the MISC CTL2 register is 1 e A delayed transfer results in a Master Abort and the BE D bit in the MISC register 15 0 Set the MA BE D see Table 127 on page 276 and TA BE EN see Table 130 on page 280 bits if the QSpan II is used as a host bus bridge 2 This is in compliance with the PCI Local Bus Specification 2 2 The mapping of the QBus terminations to the MC68360 MPC860 and M68040 buses is shown in Tables 11 to 13 Table 11 MC68360 Cycle Terminations of QBus Slave Module DSACKO Termination Type DSACKI TA _ BERR TEA _ HALT TRETRY a External pull ups bring tri stated signals to the non asserted state Table 12 MPC860 Cycle Terminations of QBus Slave Module a External pull ups bring tri stated s
370. sk 297 Table 152 120 Inbound Queue 298 Table 153 120 Outbound Queue 299 Table 154 Timing Parameters for MC68360 303 Table 155 Timing Parameters for MPC860 308 Table 156 Timing Parameters for M68040 312 Table 157 Timing Parameters for Interrupts and 315 Table 158 Timing Parameters for Reset Options 315 Table 159 Direction of QBus Signals During MC68360 IDMA Cycles 324 Table 160 Direction of QBus Signals During MPC860 Cycles 343 Table 161 Summary of the QSpan II s Miscellaneous Control 380 Table 162 Summary of the QSpan II s Miscellaneous Control Register 2 381 Table 163 PCI Arbiter Control Register Summary llle 382 Table 164 QBus Slave Channel Programming 382 Table 165 Register ACCESS Sete cao er ers e Re eR eeu 383 Table 166 PCI Target Image Programming 383 Table 167 QBus Error Logging Programming
371. skew PLL based clock buffer because of the low drive strength of the CLKOUT signal care must be taken to ensure the QSpan II s set up and hold times are not If an external PLL clock buffer generates the QSpan I s QCLK input N violated while the PLL clock buffer is locking Clocking the QSpan s QCLK Input with a PLL Clock Buffer Chip QSpan II does not tolerate external bus cycles occurring on the QBus when it does not have a stable clock input In the MPC860 QSpan II application shown in Figure 77 the QSpan II may not respond to a register or PCI access if MPC860 bus cycles are occurring when the QSpan II does not have a stable clock In this example the XTAL clock input to the MPC860 is only 4 MHz The MPC860 s PLPRCR register can be written to increase the clock s frequency When the frequency is increased the MPC860 will stop generating a CLKOUT signal for a period of time while the PLL is locking to this higher frequency The MPC860 will then continue executing instructions once the CLKOUT signal is stable at this higher frequency However the QSpan II will not yet have a stable QCLK input due to the PLL locking requirement of the external PLL Clock buffer chip the PLL locking time is dependent on the selected clock buffer chip but is typically around 1 ms During this period while the external PLL is locking the MPC860 must not perform any cycles on the bus or the QSpan II will not respond to the next register or PCI access
372. so shows how the data is presented to the PCI master Table 37 PCI Memory Cycle Access to bits 15 08 of the PCI CLASS register AD 11 0 register offset BE 3 0 AD 31 0 a Data phase In systems where the QSpan II is on an add in card the MPC860 is the QBus Host An external host will read QSpan II s PCI Configuration registers to program the QSpan II s PCI registers for example Base Address Registers In this case the QSpan II s Configuration registers can be programmed by reading from an external EEPROM When the QSpan II loads the registers from EEPROM all PCI access to QSpan II are retried A power up option pin called PCI Access Disabled PCI DIS sets a bit in the MISC 2 register to retry all access to the QSpan from external PCI Masters PCI accesses to the QSpan II are retried until the QBus Host programs the QSpan II registers and clears this bit The host can then read the Configuration registers and program the remaining QSpan II s PCI registers Even if an EEPROM is used on the board the QBus Host can still change certain registers before the PCI host can access the QSpan II registers In this case the PCI DIS bit can also be loaded from EEPROM and the QBus Host can clear it after it modifies the QSpan II registers The PCI DIS pin allows the QBus Host to initialize the QSpan II before the QSpan II will respond to PCI configuration accesses The serial EEPROM is no longer the only method available
373. ss IDT the IDT logo and Integrated Device Technology are trademarks or registered trademarks of Integrated Device Technology Inc Revision History 8091862 MA001 08 Final Manual November 2009 This version of the document was rebranded as IDT It does not include any technical changes 8091862 MA001 07 Final Manual January 2007 e Corrected the description of the BS field in the PBTIO_CTL PBTI1_CTL QBSIO_AT and QBSI1_AT registers see Register Map on page 197 e Updated the Ordering Information section to indicate a reduction in the variety of QSpan II parts available to customers see Ordering Information on page 407 8091862 MA001 06 Final Manual September 2000 8091862 MA001 05 Final Manual September 2000 8091862 MA001 04 Preliminary Manual December 1999 8091862 MA001 03 Preliminary Manual September 1999 8091862 MA001 02 Preliminary Manual September 1999 8091862 MA001 01 Preliminary Manual August 1999 QSpan II User Manual 8091862 001 08 Revision History 4 QSpan II User Manual 8091862 001 08 Contents Chapter 1 General Information ccna teas sue ines 25 1 34 Whatis the QSpan M secesii eL Rer ot ete eio os eg eww aw c RUD 26 1 1 1 QQSpan II Features Ruhk RP eed 27 1 1 2 QSpan verses 7 28 12 Document
374. ss has completed see Table 129 on page 279 2 Perform a 32 bit write to the EEPROM_CS register This write cycle should supply the appropriate values for the ADDR 7 0 and DATA 7 0 fields as well as setting the READ bit to 0 QSpan II User Manual 129 8091862 001 08 Chapter 9 The EEPROM Channel 9 5 2 9 6 9 7 Writes complete normally on QBus and PCI bus regardless of the state of the ACT bit However if the ACT bit is to 1 the write does not change the content of the EEPROM CS register The master is not informed that the EEPROM_CS register access failed due to the status of the ACT bit see Table 129 on page 279 To make sure that the register write has been successful the user can read from the CS register after the write Reading from the EEPROM To read from the EEPROM complete the following 1 Read the EEPROM CS register and make sure that the ACT bit is set to 0 this indicates prior EEPROM access has completed see Table 129 on page 279 2 Write the appropriate address in the ADDR 7 0 field of the EEPROM C S register 3 Set the READ bit of the EEPROM CS register to 1 if it has not already been set QSpan II initiates a read from the EEPROM at the address specified in the ADDR 7 0 field The ACT bit is cleared set to 0 when the read completes QSpan II stores the read data in the DATA 7 0 field of the EEPROM_CS register Only one byte can be read at a time 4 Read the DATA
375. sserted The QSpan II sets this bit when EEPROM load is completed and PCI Disable bit PCI DIS in MISC CTL2 is cleared R Write 1 PCI RST ENUM Status Extraction to clear 0 Not asserted 1 ENUM asserted The QSpan II sets this bit when HS_SWITCH is sampled high and RST is negated LOO R W PCI_RST LED On Off 0 LED off 1 LED on EIM R W PCI_RST ENUM Interrupt Mask 0 Enable Interrupt 1 Mask Interrupt NXT_IP 7 0 R W PCI_RST See Next Item Pointer Below CAP_ID 7 0 R W PCI_RST 0x06 Capability ID Set to 0x06 to identify the linked list item as Compact PCI Hot Swap Register If the QSpan II is enabled for Vital Product Data VPD access the next pointer will point to the VPD register NXT_IP OxE8 Otherwise NXT_IP will be set to 0x00 which indicates that it is the last item in the Capabilities Linked List QSpan II User Manual 221 8091862 001 08 Appendix A Registers Table 87 PCI Vital Product Data Register Register Name PCI_VPD Register Offset 0 8 23 16 VPD_ADDR 15 08 NXT_IP Reset Reset By State Function VPD_F R W PCI_RST VPD Flag Initiates a VPD serial EEPROM access and indicates completion When written with a 1 QSpan II writes the 4 bytes in VPD_DATA to the EEPROM QSpan II sets VPD_F to 0 when the write is complete When written with a 0 QSpan II reads the 4 bytes from the EEPROM and store them in VPD DATA QSpan II sets VPD_F to 1 when the read is complete PCI_VPD Description
376. st 82 image programming 62 64 QBus Slave Channel 32 40 burst 49 50 53 image programming 40 I O Write 45 46 64 QSpan II User Manual 8091862 001 08 Inbound Messaging 134 Interrupts 139 Operation 136 Outbound Messaging 135 IO Messaging Unit 133 I20 BAR Register 209 I20 CS Register 238 I20 INQ Register 298 I20 OPIM Register 297 OPIS Register 296 OUTOQ Register 209 Register 261 IACK VEC field 121 VEC bit GEN Register 387 IACK_VEC field GEN Register 261 IDMA Channel Endian issues 93 94 error see Bus Error IDMA interrupt see Interrupt IDMA port size 87 88 89 249 reset 91 248 250 status 91 IDMA signals direction 324 343 IDMA ADD Register ADDR field 87 89 CNT Register IDMA_CNT field 88 89 90 IDMA_CS Register ACT bit 91 DIR bit 87 89 DONE bit 88 89 90 91 92 118 GO bit 88 89 IMODE bit 87 IPE bit 88 89 91 92 93 118 IQE bit 91 92 93 118 IRST bit 88 89 91 92 93 117 118 IRST_REQ bit 88 90 93 PORT16 bit 87 89 QTERM bit 87 89 STERM bit 87 89 IDMA DMA_CNT Register 252 IDMA DMA CS Register 248 IDMA DMA_PADD Register 251 IDSEL 107 175 184 IF BP field QSpan II User Manual 8091862 001 08 Index IIF BP Register 241 IF E bit CS Register 238 IF F bit CS Register 238 IF TP field IIF TP Register 240 IFE DIR bit INT DIR Register 269 IFE EN bit INT CTL Register 267 IFE_S bit INT STAT Register 263
377. ster 263 QINT PME bit MISC CTL2 Register 282 QS PRI bit PARB_CTL Register 283 382 QSC PW bit MISC CTL2 Register 381 QSpan II Device Specific Registers 195 QTERM bit IDMA DMA CS Register 249 QUICC bus arbitration 78 cycle termination 80 master and slave modes 158 signals 163 423 Index QUICC Interface 361 R R_MA bit PCI_CS Register 203 R_TA bit PCI_CS Register 203 R W_ 166 169 173 185 READ bit EEPROM_CS Register 279 Read Transactions 76 REG_AC bit MISC_CTL2 Register 281 381 REG_NUM field CON_ADD Register 258 387 Register Channel 33 105 112 from PCI bus 107 from QBus 109 112 Register Map 197 201 Related Documentation 30 REQ 42 176 185 Reset EEPROM 123 from PCI bus 176 options 155 QBus 166 169 QSpan from QBus 169 173 QSpan II from PCI bus 155 QSpan II from QBus 166 QSpan II through sofware 156 timing parameters 315 RESETH 375 RESETI 155 166 169 173 185 RESETO 155 166 169 173 185 Resets 155 IDMA Channel 91 RESETS 369 RID field PCI CLASS Register 206 RR BP bit CS Register 239 RST 155 176 185 375 S S BB bit MISC Register 276 380 S BGbit 424 MISC CTL Register 276 380 S_SERR bit PCI_CS Register 203 S_TA bit PCI CS Register 203 SBIST bit PCI MISCO Register 207 SBO 58 SC bit PCI CS Register 205 SCL 125 159 177 185 SDA 125 177 185 SDACK 185 SDONE 58 SERR DIR bit INT DIR Register 269 SERR EN bit INT CTL Register
378. ster Table 88 on page 223 OxOEC VPD DATA PCI VPD Data Register Table 88 on page 223 OxOF0 OxOFF PCI Unimplemented 0x100 PBTIO CTL 0 104 PBTIO_ADD 0 108 10 Reserved 0 110 0x114 PBTI1_ADD Ox118 0x13B Reserved PBROM CTL PCI Bus Expansion ROM Control Register PB ERRCS Ox14C 1FF Reserved 1 0 Control and Status Register 150 Inbound Free_List Top Pointer Register 1 0 Inbound Free List Bottom Pointer Register 10 Inbound Post List Top Pointer Register 1 0 Inbound Post List Bottom Pointer Register I50 Outbound Free List Top Pointer Register Table 89 on page 224 PCI Bus Target Image 0 Control Register Table 90 on page 226 PCI Bus Target Image 0 Address Register Table 92 on page 228 PCI Bus Target Image 1 Control Register Table 93 on page 230 PCI Bus Target Image 1 Address Register Table 95 on page 232 Table 97 on page 234 PCI Bus Error Control and Status Register PCI Bus Address Error Log Register Table 98 on page 236 PCI Bus Data Error Log Register Table 99 on page 237 Table 100 on page 238 Table 101 on page 240 Table 102 on page 241 Table 103 on page 242 Table 104 on page 243 Table 105 on page 244 198 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 67 Register Map Continued Address Offset Hexidecimal Register Description See 0x218 IOF BP 1 0 Outbound Free List Bottom Pointer Register Table 106 on page 2
379. stics on page 398 F 1 Power Dissipation Table 172 Power Dissipation 25 MHz 0 28W 0 50W 0 63W a PCIclock always runs at 33 MHz QSpan II User Manual 397 8091862 001 08 Appendix F Operating and Storage Conditions F 2 Operating Conditions Table 173 3 3 Volt Absolute Maximum Ratings DC Supply Voltage 0 5 to 7 0 ee Storage Temperature 40 to 125 a Power available on Vjo without power to Vpp Vm can result in reliability impact b QSpanllis 5V tolerant on all pins Table 174 3 3 Volt Recommended Operating Conditions EM DC Supply Voltage 3 0 to 3 6 Industrial Temperature 40 to 85 Thermal Characteristics The maximum ambient temperature of the QSpan II can be calculated as follows Ta lt Tj 0 P Where T Ambient temperature C T Maximum QSpan II Junction temperature C 125 C Junction to Ambient Thermal Impedance C Watt see Table 175 P QSpan II power consumption Watts see Table 172 398 QSpan II User Manual 8091862 001 08 Appendix F Operating and Storage Conditions The ambient to junction thermal impedance Oja is dependent on the air flow in meters per second over the QSpan II Table 175 3 3 Volt Package Thermal Resistance Are these numbers for the 17 mm or 27 mm package The junction to ambient thermal impedance 0 is dependent on the air flow in meters per second over the QSpan II
380. systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users Anyone using an IDT product in such a manner does so at their own risk absent an express written agreement by IDT Integrated Device Technology IDT and the IDT logo are registered trademarks of IDT Other trademarks and service marks used herein including protected names logos and designs are the property of IDT or their respective third party owners Copyright 2009 All rights reserved November 2009 2009 Integrated Device Technology Inc Notice The information in this document is subject to change without notice
381. t List FIFO IP FIFO contains MFAs for message frames that are sent from the host or other IOPs on the PCI bus to QBus memory The Inbound Free List FIFO FIFO contains MFAs for message frames that are free to be filled by the sender The sender which can be either the host or other IOPs receives the MFA from the Bottom of the IF FIFO and writes a message to the shared QBus memory at the address pointed to by the MFA The sender then posts the MFA for the message frame in the inbound queue register which is at offset 0x040 from the L O PCI Base Address Register BAR at offset 0x010 When this occurs the QSpan II writes this MFA to the Top of the Inbound Post List FIFO and generates a QBus interrupt if enabled The Host for example MPC860 then picks up the MFA from the Bottom of the Inbound Post List FIFO processes the message and then releases the MFA by posting it to the Top of the Inbound Free List FIFO The PCI host reads from the Inbound queue offset 0x040 to see if there is an MFA available for a new posting If the Inbound Free List FIFO is empty the QSpan II returns OXFFFF FFFF to the PCI Host or IOP on the PCI bus QSpan II User Manual 8091862 001 08 Chapter 10 1 0 Messaging Unit Figure 18 1 0 Implementation QBus High Memory Address A TP incremented by QSpan I
382. t bit 5 of byte 7 in the EEPROM is 1 For PCI Target Image 1 this means that bit 7 of byte 8 in the EEPROM is 1 see Table 44 on page 127 2 Case 2 The PCI BSTx register is not enabled see Table 75 on page 210 and Table 77 on page 212 For PCI Target Image 0 this means that bit 5 of byte 7 in the EEPROM is 0 For PCI Target Image 1 this means that bit 7 of byte 8 in the EEPROM is 0 see Table 44 on page 127 3 Case 3 By setting the power up option PCI_DIS the QSpan II will retry all PCI accesses and the QBus Host can program the registers and then clear the PCI_DIS bit in MISC CTL2 Once cleared this enables the PCI Host to read the Configuration registers 4 4 4 1 Block Size and PCI Address Space If PCI address programming from the EEPROM is enabled Case 1 the Block Size and PCI Address Space PAS fields are set from the EEPROM and they are read only The PAS bit can be read from either the 5 or the PBTIx_CTL register If the reset state of the Block Size and Address Space fields is zero Case 2 these fields are only writable from the PBTIx_CTL registers 4 4 4 2 Base Address If PCI address information is loaded from an EEPROM Case 1 the base address of the Target Image can only be set through the PCI BSTx register for example BA 31 16 of PCI BSTO or PCI The base address be read from either the PCI BSTx register or the PBTIx ADD register The PCI BIOS uses the PCI BSTx register
383. t has been issued and the bus is in the idle state for 16 clock cycles 142 QSpan II User Manual 8091862 001 08 Chapter 11 PCI Bus Arbiter Figure 20 PCI Bus Arbiter Arbitration Scheme Arbitration Order Level 1 Level 1 Level 1 Level 0 For example if all bus masters assert Request A B C X A B C Y A B C 2 To assign a priority level set the Arbitration Level priority Mx_PRI bit in the PARB_CTL register see Table 131 on page 283 Background arbitration is implemented which means arbitration occurs during the previous access so that no PCI cycles are consumed due to arbitration except when the bus is in the idle state In general the arbiter negates the current grant when the current master asserts FRAME It issues a new grant when the current master negates FRAME if there is pending new request If the bus is idle when a new request is received the arbiter negates the current grant then issues a new grant on the next clock QSpan II User Manual 143 8091862_MA001_08 Chapter 11 PCI Bus Arbiter 11 3 Bus Parking Bus parking is supported on the last bus master or on a pre determined bus master This depends on the setting of the PCI Bus Parking Scheme PARK bit and the Select Master for PCI Bus Parking BM PARK bit in the PARB_CTL register see Table 131 on page 283 If PARK is set to 0 the last bus master is parked If PARK is set to 1 the bus master identified by BM PARK
384. t to TS_ QSpan II does not need to convert prefetchable cycles of the MC68360 because DACK_ has the same timing as AS_ During a burst read on the PCI bus which is a result of a prefetch if one of the data beats is terminated with an error the 32 bytes are invalidated and the QSpan II terminates the cycle on the QBus with a Bus Error 3 5 2 4 Delayed Reads and PCI Transaction Ordering In order to satisfy PCI Transaction Ordering requirements the rules described in this section are implemented in the QSpan II see Delayed Reads in the PCI 2 2 Specification These rules affect the relation between delayed reads and posted writes in the QBus Slave Channel The rules also affect the relation between delayed reads in the QBus Slave Channel and posted writes in the PCI Target Channel The following list summarizes the sequence of QSpan II events 1 The QBus Slave Module receives a read request 2 The QBus Slave Channel empties the Qx FIFO of any writes or completes any current reads The QBus Slave Module latches the read request The QBus Slave Module retries subsequent non register accesses The PCI Master Module completes the read on the PCI bus The PCI Target Module retries all non register accesses The Px FIFO is emptied SO In the case of QBus Slave Channel burst reads 8 The PCI Target Module allows posted writes to the Px FIFO 9 The QBus Slave Module allows the burst read to complete on the QBus 10
385. ta transfer on the Data bus High indicates a read transaction a low indicates a write It has the same timing as the Address bus As a master the QSpan II drives R W and tristates it otherwise As a slave the R W pin is an input SIZ 1 0 Tristate bidirectional Size indicates the number of bytes to be transferred during a bus cycle The value of the Size bits along with the lower two address bits and the port width define the byte lanes that are active Table 52 on page 174 shows the encoding for the Size bits SIZ 1 1 indicates a M68040 burst cycle Rescinding tristate bidirectional See DSACKI TA TC 3 0 Tristate bidirectional Transaction Code Bus provides additional information about a bus cycle when the QSpan II is a M68040 bus master Driven by the QSpan II when it is a M68040 bus master As a slave the QSpan II samples TC 3 0 on the rising edge of QCLK and is qualified by Transfer Start TS_ The timing for the TC 3 0 outputs is the same as the timing for the address bus when the QSpan II is a M68040 bus master The values output on the TC 3 0 bus during a transaction in which the QSpan II is the bus master is determined by the value programmed in the Transaction Code field of the corresponding PCI target image TC 3 0 may be connected to a subset of the TT 1 0 and TM 2 0 M68040 pins Unused TC 3 0 pins if any should be connected to pull up resistors Rescinding tristate bidirectional See BERR TEA
386. tatus to Clear DONE IS R Write 1 G RST IDMA DMA Done Interrupt Status to Clear INT IS R Write 1 RST Status of PCI interrupt input to QBus interrupt output to Clear PERR IS R Write 1 G RST Status of PCI bus PERR input to QBus interrupt output to Clear SERR IS R Write 1 G Status of PCI bus SERR input to QBus interrupt output to Clear QINT IS R Write 1 G Status of QBus interrupt input to PCI interrupt output to Clear MB3 IS R Write 1 G RST MailBox3 Interrupt Status to Clear 262 QSpan II User Manual 8091862 001 08 Appendix A Registers Reset State Function MailBox2 Interrupt Status MailBox1 Interrupt Status MailBox0 Interrupt Status QBus Data Parity Error Status Power State Changed Interrupt Status Outbound Post_List Not Empty Status This bit is set when the Outbound Post_List is not empty Inbound Post_List New Entry Interrupt Status This bit is set when a new entry is posted into the Inbound Post_List INT_STAT Description Continued 2 IS R Write 1 G RST to Clear MBI IS R Write 1 G RST to Clear MBO IS R Write 1 G RST to Clear QDPE S R Write 1 G RST to Clear PSC IS R Write 1 G RST to Clear OPNE S G_RST IPN_IS R Write 1 G_RST to Clear G_RST 1 Inbound Free_List Empty Status This bit is set when the Inbound Free_List is empty G_RST 1 Outbound Free_List Empty Status This bit is set when the Outbound Free_List is empty G_RST Inbound Post_List Full Status This
387. tch Read Enable 0 Disable 1 Enable Burst Write Enable 0 Disable 1 Enable Invert Endianness from QB_BOC Setting in MISC_CTL 0 Use QB_BOC setting 1 Invert QB_BOC setting QBus Destination Port Size 00b 32 bit 01b 8 bit 10b 16 bit 11b Reserved Posted Write Enable 0 Disable PWEN R W G_RST 1 Enable PAS See PCI_RST See PCI Bus Address Space Below Below 0 PCI Bus Memory Space 1 PCI Bus I O Space a Only PCI bus memory space transactions can be posted QBus Transaction Code User Defined 224 QSpan II User Manual 8091862 001 08 Appendix A Registers The BS 3 0 and PAS fields can be loaded from an external serial EEPROM see Mapping of EEPROM Bits to QSpan II Registers on page 126 There are three cases 1 QSpan User Manual 8091862 001 08 If the fields are loaded from the EEPROM then the EEPROM determines their reset state and they become read only except as described in 3 In this case the PAS bit has the same value as the bit of the same name in the PCI BSTO register see Table 75 on page 210 If the BS 3 0 and PAS fields are not loaded from the EEPROM their reset state is 0 and they are writable Note that in this case the PCI BSTO register is disabled If the power up option PCI DIS is set high during reset then BS 3 0 and PAS fields are writable from the QBus even if they were loaded from the EEPROM 225 Appendix A Registers Ta
388. ter Table 152 on page 298 0x044 I20 OUTQ 150 Outbound Queue Register Table 153 on page 299 QSpan II User Manual 201 8091862 001 08 Appendix A Registers A 4 Registers Table 69 PCI Configuration Space ID Register Register Name PCI_ID Register Offset 000 DID DID VID VID PCI ID Description Reset Name Type Reset By State Function DID 15 0 R WQ E G RST 0x0862 Device ID IDT allocated Device Identifier VID 15 0 R WQ E G RST 0 10 3 Vendor ID PCI SIG allocated vendor Identifier for Tundra Note IDT acquired Tundra Semiconductor 202 QSpan II User Manual 8091862 001 08 Appendix A Registers Table 70 PCI Configuration Space Control and Status Register Register Name PCI_CS Register Offset 004 Bits Function 23 16 TFBBC DEV66 CAP_L PCI Reserved 15 08 PCI Reserved MFFBC SERR EN PCI CS Description Reset By Function R Write 1 PCI RST Detected Parity Error to Clear 0 No parity error 1 Parity error This bit is set by the QSpan II whenever the PCI Master Module detects a data parity error or the PCI Target Module detects address or data parity errors R Write 1 PCI RST Signaled SERR to Clear 0 SERR not asserted 1 SERR asserted The QSpan II as PCI target sets this bit when it asserts SERR to signal an address parity error SERR_EN must be set before SERR can be asserted R Write 1 PCI RST Received Master Abort to Clear 0 QSpan II did not generate M
389. this input is asserted set as 1 during a PCI Reset the Bus Master Enable bit in the PCI CS register will be set Bus Request used by QSpan to request ownership of the QBus BR along with BG and BB BGACK provide the three wire handshake for QBus arbitration BR is asserted and negated from the falling edge of QCLK in MC68360 mode PCI Chip Select indicates that the current transaction on the QBus is an access to the PCI Bus During IDMA cycles if this is sampled high a single address transfer is indicated if sampled low a dual address transfer is indicated It is sampled on the falling edge of clock Register Chip Select indicates that the current transaction on the QBus is an access to the QSpan registers t is sampled on the falling edge of clock nm Tristate bidirectional Data Bus provides the data information for the QSpan II s inputs and outputs on the QBus As an MC68360 slave the QSpan II does not use DS to qualify data on writes It also provides data on reads without decoding DS since DS is output only As an MC68360 master the QSpan II does use DS to qualify data on writes and to request data on reads DACK SDACK _ IDMA Acknowledge indicates to the QSpan II that the current transaction is an IDMA transaction The timing of DACK should be the same as for AS Using the IDMA handshakes the QSpan II is capable of supporting MC68360 fast termination cycles 164 QSpan II User Manual 8091
390. three clocks following TS assertion During IDMA cycles if this is sampled high a single address transfer is indicated otherwise a dual address transfer is indicated Register Chip Select indicates that the current transaction on the QBus is an access to the QSpan 1 registers CSREG be sampled on the same clock as 5 or up to three clocks following TS_ assertion This signal is sampled synchronously on the rising edge of clock after TS DP 3 0 Bidirectional Data Parity provides the parity information for the data on D 31 0 It is valid on the same clock as the data D 31 0 Tristate bidirectional Data Bus provides the general purpose data path between the QSpan II the MPC860 and other devices IDMA Acknowledge indicates to the QSpan II that the current transaction is an IDMA transaction IDMA Done This signal is not used with MPC860 transfers oma IDMA Request request to the MPC860 IDMA to either transfer data to QSpan II IFIFO PCI Write or remove data from I FIFO PCI Read It is asserted from the rising edge of QCLK in MPC860 mode 168 QSpan II User Manual 8091862 001 08 Chapter 16 Signals 16 4 MPC860 Signals PowerQUICC Continued DSACKI TA Rescinding tristate bidirectional Transaction Acknowledge driven by the addressed slave to acknowledge the completion of a data transfer on the QBus As a slave QSpan terminates all normal bus cycles by asserting TA_ QSpan negates DS
391. ting VPD Data iced es pus RR ae ee pe ae 131 Chapter 10 LO Messaging Unit 24s RR E ER RES ERE 133 OVERVIEW Soe ose 133 10 2 Inbound Me ssaging eda Twas GaSe Madea ed nei eee 134 10 3 Outbound Messaging 1 135 10 4 DO Operation PER S m 136 10 5 Summary of LO Operations 136 10 5 1 Initialization iiio cbr ad dias a Alou sates 136 10 5 1 1 Inbound DO Message 138 10 5 1 2 Outbound 138 10 6 50 Interrupts 225 cunt xs bb OR RARO UR T CORR de P TR ee 139 Chapter 11 PCI Bus Arbiter s o36ii6464 006000404065040058000040286400068 141 WT OVERVIEW uibus eds GAs Pe was Poa ie Dh eA ee ase 141 11 2 Arbitration Schemes i cio law eave Ca ania indie cee 142 113 Bus Parking ics eee ee deel uae seed ER VERG Re ee 144 Chapter 12 CompactPCI Hot Swap Friendly Support 145 12 1 OVEIVICW bob ad rad ene ee hee ea stad ee che eal 145 QSpan II User Manual 9 8091862 001 08 Contents 12 2 Hot Swapping with the QSpan 146 12 3 CompactPCI Hot Swap Card Insertion
392. tion For use in IDMA transfers TC 3 0 should be set to all ones The timing for the TC 3 0 outputs is the same as the timing for the address bus when the QSpan II is a QBus master The values output on the TC 3 0 bus during a transaction in which the QSpan II is the bus master is determined by the value programmed in the Transaction Code field of the corresponding QSpan II PCI target image TC 3 0 is intended to connect to the MC68360 s FC 3 0 but may be used for other special decoding purposes 166 QSpan II User Manual 8091862 001 08 Chapter 16 Signals 16 4 MPC860 Signals PowerQUICC A 31 0 Tristate bidirectional Address bus address for the current bus cycle It is driven by the QSpan II when it is the QBus master and input as slave It is qualified at the start of a transaction by TS_ As a slave the QSpan II samples A 31 0 on the rising edge of QCLK and is qualified by Transaction Start TS on the same rising clock edge As a master the address is driven out following a rising edge of the QCLK When accesses are made to QSpan II registers from the QBus only the lower 12 bits of the address bus are used to determine the register offset ATT 0 3 Tristate bidirectional See TC 3 0 BB BGACK Rescinding tristate bidirectional Bus Busy indicates ownership of the QBus BB is asserted low by a master to show that it owns the bus BB along with BR_ and BG provides the three wire handshake for QBus arbitrati
393. tion If a posted write is terminated by a Target Abort or Master Abort on the PCI bus this termination is not signaled on the QBus to the QBus master However errors on the PCI bus are accessible to external QBus Masters through error logging Error logging is enabled by the EN bit of the PCI Bus Error Log Control and Status Register PB_ERRCS register Errors can be enabled to cause interrupts see Table 98 on page 236 QSpan II User Manual 55 8091862_MA001_08 Chapter 3 The QBus Slave Channel 2 7 56 QSpan II can record the address command data byte enables of a posted write transaction that results in a Master Abort or Target Abort The EN bit of the PB_ERRCS register enables error recording If enabled the occurrence of an error is indicated by the ES bit of the PB ERRCS register Transfers in the QBus Slave Channel are suspended until the ES bit is cleared if the Unlock QBus Slave Channel UNL_QSC bit in the PB ERRCS register is set to 0 see Table 98 on page 236 IDT recommends that the UNL_QSC bit always be set to 1 if error logging is enabled If enabled the PB ERRCS register latches the command information of the transaction error CMDERR field as well as the byte enables of the transaction error BE ERR field The address of the transaction error is latched in the PCI Bus Address Error Log PB AERR register The data of the transaction error is latched in the PCI Bus Data Error Log Register PB DERR regist
394. tions for QBus Slave Modes Reset sampling of SIZ 1 Slave Mode QBus Data Parity Generation and Detection The QBus Slave Module QSM supports the generation and detection of QBus data parity The use of QBus data parity is optional Data parity is valid on the same clock cycle as the QBus data QSpan II supports Odd and Even parity and is controlled by QBUS PAR in the MISC CTL2 register see Table 130 on page 280 Even parity is the default setting which is the same as the PCI bus The detection of a QBus data parity error does not affect the operation of the QSpan II The PCI bus parity generation and detection is independent of the QBus data parity generation and detection Four pins are used for the QBus Data Parity signals DP 3 0 When parity is set to Even the number of 1s on the QBus Data lines D 7 0 and DP 0 equal an even number Similarly for Odd parity the number of 1s on D 7 0 and DP 0 equal an odd number The following list shows which data parity signals DP 3 0 are used for which data lines e DP 0 contains the parity for data lines D 7 0 e DP 1 contains the parity for data lines D 15 8 e DP 2 contains the parity for data lines D 23 16 e DP 3 contains the parity for data lines D 31 24 The QBus Slave Module generates the data parity when it completes a slave read cycle If it detects a parity error during a slave write cycle it sets the QBus Data Parity Error Status bit QDPE 5S in the Interrupt Statu
395. tions when configured as an MPC860 QBus master See also the BURST 4 bit in the MISC CTL2 register on Table 130 on page 280 INVEND This bit Inverts the endian state from the state of the QB_BOC bit BS 3 0 Block Size of Target Image affects number of address lines translated PAS This bit allows the PCI Target Image to respond to a Memory or I O cycle Typically only Memory Space is implemented TC 3 0 This field determines how the TC 3 0 lines of the QSpan II are driven DSIZE 1 0 This field specifies the size of the destination port memory on the QBus PBTIO_ADD BA 31 16 This field specifies the base address of the PCI memory image which and or PBTI1_ADD the QSpan II monitors see Address Translation on page 64 TA 31 16 This field specifies part of the value for the translated local address see Address Translation on page 64 a Seealso PCI BSTO and PCI BSTI registers in Appendix A Registers on page 195 Once the target images are programmed PCI masters can read from and write to the QBus address space 384 QSpan II User Manual 8091862 001 08 Appendix D Software Initialization D 5 Error Logging of Posted Transactions QSpan II has registers which allow the processor to recover from a failed write cycle from either the Px FIFO or Qx FIFO This section discusses posted writes delayed reads and delayed writes are treated differently QSpan II has the ability to log the failed posted write cy
396. to entire INT CTL register in order to set the DONE EN bit so that the QSpan II will interrupt the QBus when the IDMA is finished with a transaction 3 PCI master performs a 32 bit write to the register in order to set the SI1 bit and inadvertently clears the DONE EN bit because it was clear in Step 1 above 4 does not generate interrupt when the IDMA transaction completes because the DONE_EN bit is clear Two possible solutions to this problem include the following 1 Perform byte wide writes on the PCI bus as opposed to 32 bit writes This does not solve all the register access synchronization problems because the other 7 bits in the write may change between a read and a write Since the 511 bit and the DONE_EN bit see Table 120 on page 265 are separated by two bytes it would solve the problem described in Figure 13 2 Design the system to always set the DONE_EN bit or whatever other bit is susceptible to this problem However this may lead to the generation of more interrupts and consequently an impact on performance QSpan II User Manual 113 8091862 001 08 Chapter 7 The Register Channel 7 6 Mailbox Registers QSpan II has four 32 bit mailbox registers which provide an additional communication path between the PCI bus and the QBus The mailboxes support read and write accesses from either bus and can be enabled to generate an interrupt on either bus when they are written
397. ue as the PCI BSTO register from reset onwards 2 If one of the following occurs then the entire BA field of PBTIO ADD is readable and writable the EEPROM bit was 0 the SDA pin and ENID pins are 0 at PCI reset or PCI DIS is latched low A read from this field after reset returns all Os In this case the BA field of this register is independent of the PCI BSTO register the PCI BSTO register does not exist The presence of EEPROM does not affect TA 31 16 QSpan II User Manual 227 8091862 001 08 Appendix A Registers Table 92 PCI Bus Target Image 1 Control Register Register Name PBTI1_CTL Register Offset 110 Bits Function 15 08 TC DSIZE Reserved 07 00 PWEN Reserved PBTI1_CTL Description Reset Name Type Reset By State Function EN R W G_RST Image Enable 0 Disable 1 Enable BS 3 0 See PCI RST See Block Size 64 Kbyte 2P5 Below Below PREN R W G RST Prefetch Read Enable 0 Disable 1 Enable BRSTWREN R W G_RST Burst Write Enable 0 Disable 1 Enable INVEND R W G_RST Invert Endian ness from QB_BOC Setting in MISC_CTL 0 Use QB_BOC setting 1 Invert QB_BOC setting TC 3 0 R W G_RST QBus Transaction Code User Defined DSIZE 1 0 R W G_RST QBus Destination Port Size 00b 32 bit 01b 8 bit 10b 16 bit 11b Reserved PWEN R W G RST Posted Write Enable 0 2 Disable 1 Enable PAS See PCI RST See PCI Bus Address Space Below Below 0 PCI Bus Memory Space 1 PCI Bus I O Space a Only PCI
398. upport on page 130 9 1 Overview Some QSpan II registers can be programmed by data in an EEPROM at system reset for more information see Table 44 on page 127 This allows board designers to perform the following e setidentifiers for their cards on the PCI bus at reset e enable the PCI Bus Expansion ROM Control Register e set various address and parameters of images If the QSpan II is configured with EEPROM or by an external QBus master using the PCI DIS pin the device can boot up as a Plug and Play compatible device see EEPROM Configuration and Plug and Play Compatibility on page 125 QSpan II User Manual 123 8091862 001 08 Chapter 9 The EEPROM Channel Figure 15 EEPROM Channel Functional Diagram QBus Interface Interface QBus Slave Module Bus QBus Register Channel Target Module QBus Master Module EEPROM QSpan II supports an additional scheme to be Plug and Play compatible without the use of an EEPROM In this case the power up option PCI Access Disabled PCI_DIS is pulled high during reset see Table 130 on page 280 This forces the QSpan II to retry all PCI access During this time the QBus Host can program the necessary registers for example the registers that are normally loaded from the EEPROM and then write a 0 to the PCI_DIS bit This allows the QSpan II to accept PCI cycles The PCI_DIS option can also be enabled by loading from the
399. ures that all writes previously posted in the Qx FIFO complete on the PCI bus before the read data is passed back to the PCI bus master that initiated the read transaction During the period when the Qx FIFO is being emptied attempts to access the QBus Slave Channel are retried register accesses are not affected The following list summarizes the sequence of events 1 The PCI Target Module receives a read request from a PCI master which it latches 2 The PCI Target Module retries all non register accesses 3 The PCI Target Channel empties the Px FIFO QSpan II User Manual 71 8091862 001 08 Chapter 4 The PCI Target Channel 4 6 1 4 7 4 7 1 78 The QBus Master Module completes the read on the QBus The QBus Slave Module retries all non register accesses The Qx FIFO is emptied The PCI Target Module allows the read to complete on the PCI bus o 8 The PCI Target Module allows posted writes to the Px FIFO even if the delayed read has not completed 9 The QBus Slave Module allows posted writes to the Qx FIFO Similar principles apply to QBus Slave Channel reads see Delayed Reads and PCI Transaction Ordering on page 51 The IDMA Channel is independent from the PCI transaction ordering rules that affect the QBus Slave Channel and the PCI Target Channel Transaction Ordering Disable Option QSpan II has a register option to disable transaction ordering between the PCI Target Channel and the
400. us for multiple transactions if the KEEP_BB bit is set in the MISC_CTL2 register see Table 130 on page 280 If set this configuration improves the performance of the PCI Target Channel and the DMA Channel by eliminating the arbitration delay Terminations QBus Master Module Terminations This section explains the QBus Master Module s handling of cycle termination for the MC68360 MPC860 and M68040 buses MC68360 Cycle Terminations When a transaction is completed BB BGACK is negated by the QBus Master Module on the rising clock edge and tristated on the next falling clock edge Termination of MC68360 cycles is described in Table 27 The QBus Master Module samples all of the MC68360 termination signals on the falling edge of QCLK In contrast the QBus Master Module samples the MPC860 termination signals on the rising edge of QCLK The MC68360 termination inputs to the QBus Master Module can be skewed by as much as one clock period However they must meet the required setup and hold time required with respect to the falling edge of QCLK HALT TRETRY is ignored if asserted alone In a Normal and Halt condition the QBus Master Module delays the termination until HALT TRETRY _ 1 negated This feature of the MC68360 allows software to verify the internal state of the MC68360 during an error During MC68360 Retry terminations the QBus master negates and will re request the bus assert BR when HALT is negate
401. us is shown with a single PCI master The PCI Target Channel has the following components e PCI Target Module e Px FIFO e Pr FHFO e QBus Master Module PCI Target Module QSpan II s PCI Target Interface is a PCI Local Bus Specification 2 2 compliant port QSpan II does not implement SBO SDONE or PCI LOCK functionality A list of the PCI signals supported by the QSpan II is in PCI Bus Signals on page 174 The PCI Target Module accepts Type 0 Configuration cycles and ignores Type 1 Configuration cycles Configuration cycles are not passed to the QBus for information see PCI Configuration Cycles Generated from the QBus on page 110 QSpan II User Manual 8091862 001 08 Chapter 4 The PCI Target Channel 4 2 2 Px FIFO and Pr FIFO The Px FIFO is a 256 byte buffer for posted writes from the PCI bus to the QBus The Px FIFO can accept data from a PCI master while writing data to a QBus slave see Posted Writes on page 74 The Pr FIFO is a separate 256 byte buffer for read data from the QBus see Prefetched Read Transactions on page 76 4 2 3 QBus Master Module The QBus Master Module is a non multiplexed 32 bit address 32 bit data interface This module can be treated as a 32 bit 16 bit or 8 bit interface by programming the DSIZE field of the PCI Target Image see Table 17 on page 62 The QBus Master Module can generate MC68360 QUICC MPC860 PowerQUICC or M68040 cycles depending on the QBus
402. ut bit 31 from the QBus address signal For example the Address Generator translates A 31 only while copying A 30 0 and uses the top translation address bit as bit 31 of the PCI address QSpan II User Manual 8091862 001 08 Chapter 3 The QBus Slave Channel Figure 4 Address Generator for QBus Slave Channel Transfers Translation Address QBus Address Block Size Address Generator PCI Address This manual adopts the convention that the most significant bit address or data is always the largest number MPC860 designers must ensure that they connect their pins accordingly For example pin A 31 on the QSpan II connects to pin A 31 on the MC68360 bus but connects to pin 0 on the MPC860 bus This applies to all MPC860 buses D 31 0 AT 3 0 TSIZ 1 0 not only the address bus QSpan II User Manual 43 8091862 001 08 Chapter 3 The QBus Slave Channel Table 5 Translation of QBus Address to PCI Address BS in QBSIO CTL or Address Lines Translation Address Bits 5 Block Size Translated Copied 44 QSpan II User Manual 8091862 001 08 Chapter 3 The QBus Slave Channel 3 4 4 Address Phase on the PCI Bus The address supplied on the AD 31 0 lines on the PCI bus is the result of the address translation described in the previous section The PCI command encoding on the 3 0 lines is determined by the type of transaction on the QBus and the programming of the PCI Bus Ad
403. value Once all the relevant data is programmed into the IDMA register the IDMA DMA Go GO bit in the IDMA DMA CS register must be set to 1 to initiate the IDMA transfer Any status bit IRST DONE IPE or IDE affected by a previous transfer must be cleared prior to or while the GO bit is set Data Path The PCI Master Module performs burst reads on the PCI bus to fill the I FIFO When data is available in the I FIFO the QSpan II asserts DREQ to request IDMA service The processor acknowledges with DACK SDACK at which point the QSpan II drives the data onto the QBus With a 16 bit QBus port the QSpan II unpacks each 32 bit read data from the PCI into two 16 bit transfers on the QBus The IDMA DMA CNT register indicates the number of bytes to transfer in an IDMA transaction see Table 111 on page 252 QSpan II decreases the transfer count by four with every 32 bit transfer on the PCI bus the IDMA Channel on the PCI Interface only transfers 32 bit data The maximum amount of data that can be transferred within an IDMA transaction is 16 Mbytes for example 222 32 bit transfers QSpan II can prefetch data up to the next cacheline boundary and discard the extra data When the IDMA DMA CNT expires the QSpan II sets the IDMA DMA Done Status DONE bit in the IDMA DMA CS register The MC68360 asserts the DONE _ signal when its transfer counter expires If the MC68360 is programmed with a larger transfer count than the QSpan II the
404. when the QSpan II is the M68040 master and input when the QSpan is the slave It is qualified at the start of a transaction by TS_ As a slave the QSpan II samples A 31 0 on the rising edge of QCLK and is qualified by Transaction Start TS As a master the address is driven out following a rising edge of the QCLK When accesses are made to QSpan II registers from the QBus only the lower 12 bits of the address bus are used to determine the register offset BB Rescinding tristate bidirectional Bus Busy This signal is asserted by the current bus master to indicate ownership of the M68040 bus BB_ along with and BG provide the three wire handshake for M68040 bus arbitration As an output the QSpan II asserts BB BGACK from the rising edge of QCLK while master QSpan II negates BB BGACK prior to tristate As an input the QSpan II samples BB BGACK the rising edge of QCLK while master QSpan II can also be programmed to use an asynchronous mode for M68040 bus arbitration Burst Data In Progress This signal is only used in the 68040 mode at reset QSpan II Master Slave mode is determined at reset by sensing the level of this pin in conjunction with SIZ 1 See Table 48 on page 158 BERR TEA Rescinding tristate bidirectional Transfer Error Acknowledge indicates an error condition exists for a bus transfer Driven by the QSpan II when it is a M68040 bus slave to signal an errored transaction As an
405. will only be reflected in Qx FIFO entries queued after the reprogramming Transactions queued before the reprogramming are delivered to the PCI bus with the QBus Slave Image attributes that were in use before the reprogramming QSpan II never packs data in the Qx FIFO For example two 16 bit data beats are not packed as a single 32 bit data entry but as four separate entries in the Qx FIFO address data address data If a QBus master attempts to post a write transaction when the Qx FIFO does not have enough space the QBus Slave Channel retries the master The exact manner in which the master is retried depends on whether the master is an MC68360 MPC860 or M68040 device see Termination Phase on page 53 Since single transfers require two entries in the Qx FIFO two entries must be available before the QBus Slave Module accepts a single write transaction However the 256 byte depth of the Qx FIFO ensures a very low probability that the Qx FIFO is too full to accept write transactions The PCI Master Module requests the PCI bus when there is a complete transaction in the Qx FIFO During write transactions the PCI Master Module uses transactions queued in the Qx FIFO to generate transactions on the PCI bus No address phase deletion is performed thus the length of a transaction on the PCI bus corresponds to the length of the queued QBus transaction Only MPC860 and M68040 Masters are capable of initiating burst transactions Incoming burst
406. xe by typing it at a command prompt QSpan II User Manual 29 8091862_MA001_08 Chapter 1 General Information 1 2 5 1 2 6 1 3 30 Symbols This symbol directs the reader to useful information or suggestions 1 This symbol alerts the reader to procedures or operating levels which may result in misuse or damage to the product This symbol alerts the reader to an initialization process that must be performed as a minimum to access the required channel or interface Document Status IDT technical documentation is classified as either Advance Preliminary or Final These classifications are briefly explained Advance The Advance manual contains information that is subject to change The Advance manual exists until device prototypes are available This type of manual can be downloaded from our website Preliminary The Preliminary manual contains information about a device that is near production ready and is revised on an as needed basis The Preliminary manual exists until the device is released to production This type of manual can be downloaded from our website Formal The Formal manual contains information about a customer ready device This type of manual can be downloaded from our website Related Documentation Before you read this manual you should be familiar with the following PCI Local Bus Specification Revision 2 2 CompactPCI Hot Swap Specification Revision 1 0 CompactPCI Specification
407. y connect their pins accordingly For example pin A 31 on the QSpan II connects to pin A 31 on the MC68360 bus but connects to pin A 0 on the B 860 bus This applies to all MPC860 buses D 31 0 AT 3 0 TSIZ 1 0 not only the address bus QSpan II User Manual 8091862 001 08 5 5 5 6 Chapter 5 The IDMA Channel IDMA Status Tracking The following bits in the IDMA DMA CS register record the status of the transaction IDMA DMA Active Status ACT bit in the IDMA DMA CS is set by the QSpan II to indicate that an transfer is in progress IDMA DMA Done Status DONE bit indicates that the transfer is complete IDMA DMA PCI Bus Error Status IPE bit is asserted when an error is signaled on the PCI bus during an IDMA transfer e IDMA DMA QhBus Error Status IQE bit is asserted when an error is signaled on the QBus during an IDMA transfer e The IDMA DMA Reset Status IRST bit is asserted when the QSpan II has reset the IDMA Channel For more information about errors and resets see Errors Resets and Interrupts on page 91 IDMA Errors Resets and Interrupts This section describes how the QSpan II responds to PCI bus errors and QBus errors during IDMA reads and writes This section also discusses IDMA resets and interrupts When there is an error on either bus during IDMA transfers the QSpan II will assert an IDMA error status bit I
408. y performs burst reads at cacheline boundaries This feature makes QSpan II burst reads compatible with the MPC860 UPM The module requests the bus for a burst when there is enough room in the Pr FIFO for an entire cacheline of data The PR SING bit in the MISC_CTL2 register supports QSpan II prefetching as single or burst cycles in the PCI Target Channel The PR SING bit should be set to a 1 if the QBus memory does not support bursting when the QSpan II is powered up as an MPC860 master see Table 130 on page 280 QSpan II User Manual 8091862 001 08 4 5 3 4 6 Chapter 4 The PCI Target Channel Parity Monitoring by PCI Target Module The PCI Target Module monitors parity during the address phase of transactions and during the data phase of write transfers For example the QSpan II compares the PAR signal with the parity of AD 31 0 and C BE 3 0 The PAR signal provides even parity for C BE 3 0 and AD 31 0 QSpan II drives PAR when it provides data as a target during a read If the PCI Target Module detects an address or data parity error during a write it sets the Detected Parity Error D PE bit in the PCI CS register see Table 70 on page 203 regardless of the PERESP setting in the PCI CS register For more information about parity errors and the D PE bit see Parity Monitoring by PCI Master Module on page 52 If the QSpan II signals SERR it sets the 5 SERR bit in the PCI CS register Address parity errors are r
409. yte image the PCI Target Module needs to decode the top 16 PCI address lines When one of its PCI Target Images is accessed the QSpan II responds with DEVSEL within two clocks of FRAME This makes the QSpan II a medium speed device as indicated by the Device Select DEVSEL field in the PCI CS register see Table 70 on page 203 As a PCI target the QSpan II responds to the following command types e O Read e O Write e Memory Read e Memory Write e Configuration Type 0 Read e Configuration Type 0 Write e Memory Read Multiple aliased to Memory Read e Memory Read Line aliased to Memory Read e Memory Write and Invalidate aliased to Memory Write Address Translation Figure 6 illustrates the general implementation of address translation in the QSpan II PCI Target Channel QSpan II User Manual 8091862 001 08 Chapter 4 The PCI Target Channel Figure 6 Address Generator for PCI Target Channel Transfers Translation Address PCI Address Block Size Address Generator The Address Generator produces the QBus address using three inputs the address generated by the PCI master AD 31 0 the block size of the PCI Target Image BS field of the Target Image and the translation address of the PCI Target Image TA The translation address is a 16 bit number whose upper bits specify the location of the Target Image on the QBus If the translation address is programmed with the same value as that of the base address

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