TREX C1 - Terasic
Contents
1. Vertical display position shift for SYNC mode 32 Appendix 0 1 1 1 1 NCLK 1 1 NCLK 0 2 NCLK RO7 5 0 high pulse width adjustment Set 0x20 for normal operation H08 5 0 non overlap adjustment Set 0x20 for normal operation around 0 RO9 5 0 ENB to CKH1 non overlap adjustment Set 0x20 for normal operation around 1 2us ROA 5 0 ENB low pulse width adjustment Set 0x20 for normal operation around 2 8us Notice that CKV transition timing is in the middle of ENB low pulse EE Ed IER 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 ROB 5 0 R Gain of Contrast oso Gan of Contras 33 Appendix 1 00000 Default initial setting value ROC 5 0 G Gain of Contrast _ owe sm 0 ROD 5 0 B Gain of Contrast EN NN ROE 5 0 R Offset of Brightness EN EE x s ROF 5 0 G Offset of Brightness ono ofset of Brightness i Set Default initial setting value 34 Appendix R10 5 0 B Offset of Brightness NENNEN T ia The gamma correction is done by 11 segment piecewise linear interpolation The 11 segments are defined with 12 register values for level 0 8 16 32 64 96 128 192 224 240 248 and 256 for positive polarity Negative polarity data are generated symmetrically The gamma correction output is then fed to 8 bit D2. www terasic com TRDB LIM 4 3 Inch Digital Touch Panel Development Kit With complete reference design and source code for digital photo display and pattern generator using Altera DE2 DE1 board Terasic TRDB_LTM CHAPTER 1 ABOUT THE KIT 1 J TITO NID ER 1 1 2 CONNECTING LTM TO THE ALTERA DE BOARPD ru utere oramus vt eur ee incus edi ee ee Se 2 1 3 GETTING EWP ees osse de oe ee oe oe oe oe se noe ee ee ge ie ee ee ee n ae n Go ee Ge oe ei ee DE 3 CHAPTER 2 ARCHITECTURE OF THE LINM d 2 1 FEATURES ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee 4 2 2 BLOCK DIAGRAM OF THE LTM ee iese de ee ee ee Ge Ge ee N AEE Ge oe EE ee ee ee ee ie 5 2 3 PIN DESCRIPTION OF THE 40 PIN INTERFACE OF 6 CHAPTER 3 USING THE LINM 8 3 1 THE SERIAL PORT INTERFACE OF THE LCD DRIVER IO ee ee ee ee nemen nn enne nnne ee
3. the bit stream is downloaded into the FPGA the register values of the LCD driver using to control the LCD display function will be configured by the LCD_SPI_Controller block which uses the serial port interface to communicate with the LCD driver IC Meanwhile the Flash to SDRAM Controller block will read the RGB data of one picture stored in the Flash and then write the data into SDRAM buffer Accordingly both the synchronous control signals and the picture data stored in the SDRAM buffer will be sent to the LTM the LCD Timing Controller block When users touch LTM screens the x and y coordinates of the touch point will be obtained by the ADC SPI Controller block through the ADC serial port interface Then the 7ouch Point Detector block will determine whether these coordinates are in a specific range If the coordinates fit the range the Touch Point Detector block will control the Flash to SDRAM Controller block to read the next or previous picture s data from the Flash and repeat the steps as mentioned before to command the LTM to display the next or previous picture Digital Panel Design Demonstration Borad Core LOSP Controller ADC_SPI_ Touch_Point_ Controller Detector LCD_Timing Muti Port Flash_to_ n SDRAM 4 SDRAM Controller Controller Contoller SDRAM Flash F
4. 8 of gamma Correction 7 6 GAMMA 224 9 8 of gamma Correction 5 4 GAMMA 240 9 8 of gamma Correction 3 2 GAMMA 248 9 8 of 0x13 OxFF R W gamma Correction 1 0 GAMMA 256 9 8 of gamma Correction OX00 RW 9 GAMMA 0 7 0 of gamma Correction 28 Appendix 0 15 0 20 R W 7 0 GAMMA 8 7 0 of gamma Correction mum ww parem reme ma mae mw fror onmacarar onaren eme wm mw Er os IIO I 7 0 GAMMA 192 7 0 of gamma Correction 7 4 Positive gamma output voltage level for source driver 0 20 OxD2 R W input FFH 3 0 Positive gamma output voltage level for source driver input OOH 7 4 Negative gamma output voltage level for source driver 0 21 OxD2 R W input FFH 3 0 Negative gamma output voltage level for source driver input OOH Boy DC VCOM leva 5 4 Register Definition of the LCD Driver IC H02 7 6 Dot inversion method selection Default initial setting value RO2 5 VD polarity lowpuse Defaut ital seting value High pulse R02 4 HD polarity 29 Appendix Default initial setting value RO2 3 Input clock latch data edge 0 Latch data at NCLK falling edge Default initial setting value R02 2 0 Resolution selection R02 2 0 Input Sequence Output Resolution oo o o o omen ammon mes _ ges NE NN r o o Smet t mee 5 HENNE NN EN R03 7 Hardware or Software se
5. logic inverter the logic level of the SCEN should be inverse when it is used to control the ADC SCEN EN taca ADC_DCLK 1 8 1 8 1 JSER s e food START IDLE ACQUIRE CONVERSION IDLE BUSY Ti ESTATE X or Y coordinate THREE STATE THREE STATE ADC_DOUT MSB LSB X Y SWITCHES OFF ON OFF SER DFR HIGH SWITCHES SER DFR LOW Figure 3 4 Conversion timing of the serial port interface 14 Digital Panel Design Demonstration Chapter Digital Panel Design Demonstration This chapter illustrates how to exercise the reference design provided with the kit Users can follow the instructions in this chapter to build a 4 3 inch Ephoto demonstration and pattern generator using the DE2 DE1 DEN in 10 minutes 4 1 Demonstration Setup The demonstration configuration is illustrated as Figure 4 1 Display the bmp format photos which are saved into the flash of DE2 DE1 on LTM module through the control of FPGA on DE2 DE1 board Users can change the displayed photo by touching touch panel X is d E uss y AL m os Arm SETETE O MEEL LIS m PTTL ud wmm P p ves M L t h Wo 1 1T Vr we B ES EM SM s ME Figure 4 1 The Ephoto demonstration configuration setup 15 Digital Panel Design D
6. panel the corresponding synchronous signals from FPGA to the LCD panel should follow the timing specification Figure 3 2 illustrates the basic timing requirements for each row horizontal that is displayed on the LCD panel An active low pulse of specific duration time in the figure is applied to the hpw horizontal synchronization HD input of the LCD panel which signifies the end of one row of data and the start of the next The data RGB inputs on the LCD panel are not valid for a time period called the hsync back porch after the hsync pulse occurs which is followed by the display area t During the data display area the RGB data drives each pixel in turn across the row being displayed Also during the period of the data display area the data enable signal DEN must be driven to logic high Finally there is a time period called the hsync front porch where hfp the RGB signals are not valid again before the next hsync pulse can occur The timing of the vertical synchronization VD is the same as shown in Figure 3 3 except that a vsync pulse signifies the end of one frame and the start of the next and the data refers to the set of rows in the frame horizontal timing Table 3 2 and 3 3 show for different resolutions the durations of time periods p t for both horizontal and vertical timing Finally the timing specification of the synchronous signals is shown in the Table 3 4
7. setup for the pattern generator demo with DE1 board Download the bitstream DE2 LTM DE1 LTM Test to the DE2 DE1 board Press KEYO on the DE2 DE1 board to reset the circuit Touch the LTM screen to switch to the other Pattern dw X9 The following table summarizes the Pattern type of this demonstration Gray bar Color bar 6 When you touch the LTM panel the 7 segment displays HEX6 HEX4 and HEX2 HEXO on the DE2 will display the X and Y coordinates in Hexadecimal format of the LTM panel respectively DE2 board only 24 Digital Panel Design Demonstration 4 7 Configuring the Pattern Generator for DEN Board 1 Ensure the connection is made correctly as shown in Figure 4 13 Make sure the IDE cable is connected to the extension header of the DEN board d ER E Ew ura we mur CI ala 55 Er s QB sn 48 Em EEN Figure 4 13 The connection setup for the pattern generator demo with DEN board Download the bitstream DEN_LTM_Test pof to the DEN board Press BUTTON1 on the DEN board to reset the circuit Touch the LTM screen to switch to the other Pattern e T9 The following table summarizes the Pattern type of this demonstration Pattern Gray bar Color bar 25 Appendix Appendix 5 1 Absolute Maximum Ratings of the LCD Panel Module Logic Power Supply Vo
8. 800 x RGB x480 dot Architecture of the 2 2 Block Diagram of the LTM 40 pin expansion connector Serial port interface gt gt Synchronous timing LCD touch panel To Altera DE2 DE1 signals and RGB data expansion connector Analog coordinates signals Serial port interface lt 4 AD converter Figure 2 1 The block diagram of the LTM The LTM consists of three major components LCD touch panel module AD converter and 40 pin expansion header All of the interfaces on the LTM are connected to Altera DE2 DE1 board via the 40 pin expansion connector The LCD and touch panel module will take the control signals provided directly from FPGA as input and display images on the LCD panel Finally the AD converter will convert the coordinates of the touch point to its corresponding digital data and output to the FPGA via the expansion header Architecture of the 2 3 Pin Description of the 40 pin Interface of LTM ADC PENIRQ n ADC BUSY ADC DCLK B2 DEN VD B5 B7 Gl G3 G5 G7 VCC33 RI R3 R5 R7 SCEN 4 1 ADC DOUT ADC DIN B3 NCLK GND HD B4 B6 G0 G2 G4 G6 GND R4 R6 GREST SDA Figure 2 2 The pin out of the 40 pin connector Pin Numbers Name Direction Description 1 ADC_PENIRQ_n output ADC pen Inter
9. AC and OP to drive the source lines on the panel VIER Yn register value dy Vou Na Y Yn dy X Xn Xn 1 Xn Output Data Y 9 0 8 Input Data 255 R20 7 4 defines positive polarity DAC reference voltage for code FFH Default pee el lel ele Appendix x Level x x x x x x x x x x x x x x x x x R20 3 0 defines positive polarity DAC reference voltage for code 0 2 R20 3 0 oo ra 0x3 0 4 0 5 0x6 0 7 0 8 0x9 OxB OxC OxD OxE OxF Default Gamma 0 2 0 25 0 3 0351 0 4 10 45 0 5 1055 0 65 0 7 0 75 0 85 0 95 Level R21 7 4 defines negative polarity DAC reference voltage for code FFH OxD Default R22 3 0 defines DC VCOM level 0x5 R22 3 0 bo oe oe o Lom 0x6 0x7 0x8 0x9 OxB OxC OxD OxE OxF Default VCOM 0 5 0 4 0 3 0 2 0 1 0 1 0 2 0 3 0 4 0 5 0 7 1 Level 5 5 Revision History Version Change Log 36 Appendix Initial Version Preliminary Edit appendix 1 21 Edit Figure 4 1 Figure 4 11 Figure 4 12 and Figure 4 13 V1 22 Edit chapter contents 5 6Always Visit LTM Webpage for New Applications We will continually provide interesting examples and labs on our LTM webpage Please visit www altera com or Itm terasic com for more information 37
10. Using the LTM Tipe J NCLK RO R7 G0 G7 BO B7 Figure 3 2 LCD horizontal timing specification Panel Resolution 800xRGBx480 480xRGBx272 400xRGBx240 NCLK Frequency FNCLK k Horizontal valid data 1 Horizontal Line HSYNC Pulse Width Hsync back porch Hsync front porch thip DEN Enable Time Table 3 2 LCD horizontal timing parameters 11 Using the LTM RO R7 G0 G7 BO B7 tva 1 Vertical Line ty Figure 3 3 LCD vertical timing specification Panel Resolution Parameter Symbol 800xRGBx480 480xRGBx272 400xRGBx240 Vertical valid data 8 241 Vertical period 25 2 VSYNC Pulse Width Typ Vertical back porch s 12 2 Vertical front porch 2 2 Vertical blanking 15 DEN Enable Time Bl Table 3 4 The timing parameters of the LCD synchronous signals 12 Using the LTM 3 3 The serial interface of the AD converter The LTM also equipped with an Analog Devices AD7843 touch screen digitizer chip The AD7843 is a 12 bit analog to digital converter ADC for digitizing x and y coordinates of touch points applied to the touch screen The coordinates of the touch point stored in the AD7843 can be obtained by the serial port interface To obtain the coordinate from the ADC the first thing users need to do is monitor the interrupt signal ADC_PENIRQ_n outputted from the ADC By connecting a pull high resisto
11. ch panel module on the LTM is equipped with a LCD driver IC to support three display resolution and with functions of source driver serial port interface timing controller and power supply circuits To control these functions users can use FPGA to configure the registers in the LCD driver IC via serial port interface Also there is an analog to digital converter ADC on the LTM to convert the analog X Y coordinates of the touch point to digital data and output to FPGA through the serial port interface of the ADC Both LCD driver IC and ADC serial port interfaces are connected to the FPGA via the 40 pin expansion header and IDE cable Because of the limited number of I O on the expansion header the serial interfaces of the LCD driver IC and ADC need to share the same clock ADG DCLK and chip enable SCEN signal VO on the expansion header To avoid both the serial port interfaces may interfere with each other when sharing the same clock and chip enable signals the chip enable signal CS which is inputted into the ADC will come up with a logic inverter Users need to pay attention controlling the shared signals when designing the serial port interface controller The detailed register maps of the LCD driver IC are listed in appendix chapter The specifications of the serial port interface of the LCD driver IC are described below The LCD driver IC supports a clock synchronous serial interface as the interface to a FPGA to enable instructi
12. ee ee ee nnt isis aires sss artes essa ee 8 3 2 INPUT TIMING OF THE LCD PANEL DISPLAY FUNCTION ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee 10 3 3 THE SERIAL INTERFACE OF THE AD CONVERTER ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee 13 CHAPTER 4 DIGITAL PANEL DESIGN DEMONSTRATIONN 15 4 1 DEMONSTRATION SETUP ccccccccccsecccccccscccccccuccecccccuccececcauseeccccuuuceccccauscececcusceccceuuuseceecuuucececeususeseecuueeeeeecuauceseceuaueeseeeaees 15 4 2 LOADING PHOTOS INTO THE FLASH soes see see ee se oe ee eo ee ee ee eo ee ed cvs reme Ee ee ee ie bee 16 4 3 CONFIGURING THE EPHOTO DEMONSTRATION se ee Or ee Ee usua ee Ge eye ee Ge Se ee ee e Ur aw Re Ge ee ee Ne oe ee de 18 4 4 BLOCK DIAGRAM OF THE EPHOTO DESIGN siese Es se ei OE ees ee EN ee oe be be ee N ee GE sennae 20 4 5 PREPROCESSING THE DESIRED DISPLAY PHOTO ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee 21 4 6 CONFIGURING THE PATTERN GENERATOR FOR 2 0 1 BOARD ee ee ee ee ee ee ee ee ee ee ee ee eed 23 4 7 CONFIGURING THE PATTERN GENERATOR FOR DEN BOARD sssscccccccsseeeeecccccccusseeeccceccccusceeecceccesauceesececceauaceeececeeeaas 25 CHAPTER 5APPENDIX en diese Gee eie eene den de ee oe ee N de ee een ee es ee ee ee ed e
13. emonstration 4 2 Loading Photos into the Flash 1 Make sure the USB Blaster download cable is connected into the host PC 2 Load the Control Panel bit stream DE2 USB API DE1 USB into the FPGA Please also refer to Chapter 3 DE2 DE1 Control Panel in the Altera DE2 DE1 User Manual for more details in the Control Panel Software Hardware Setup USB Blester USB 0 Mode JTAG v Progress Enable real time ISP to allow background programming for MAX II devices Pr ecur ISP O EEN Eel C DE2 DE2 USB EP2C35F672 0063 129 gii Auto Detect Figure 4 2 Programming window Execute the Control Panel application software Open the USB port by clicking Open gt Open USB Port 0 The DE2 DE1 Control Panel application will list all the USB ports that connect to DE2 DE1 board 5 Switch to FLASH page and click on the Chip Erase 40 Sec bottom to erase Flash data 16 Digital Panel Design Demonstration DE DEZ Control Panel Open Help About FLASH SDRAM SRAM LED HEX HEX 5 0 M 0 M HEX3 HEX 1 PS2 Keyboard Figure 4 3 DE2 control panel window Click on the File Length checkbox to indicate that you want to load the entire file Click on the Write a File to FLASH bottom When the Control Panel responds with the standard Windows dialo
14. g box and asks for the source file select the 480x3 bmp file in the Photo directory 17 Digital Panel Design Demonstration 4 3 Configuring the Ephoto Demonstration 1 Ensure the connection is made correctly as shown in Figure 4 4 and Figure 4 5 Make sure the IDE cable is connected to JP1 of the DE2 DE1 board 2 Download the bitstream DE2 LTM Ephoto DE1 Ephoto to the DE2 DE1 board 3 As shown in Figurate 4 5 touch the bottom left corner and top right corner of the LTM touch panel to display the next and previous photos respectively m i NE le nd SEU bun n P RETENE um um EXE Figure 4 4 The connection setup for the Ephoto demonstration with DE2 board 18 Digital Panel Design Demonstration Tuch here for the previous photo Touch here for the next photo Figure 4 6 The touch function of changing displayed photo 19 Digital Panel Design Demonstration 4 When users touch the LTM screen the 7 segment displays HEX6 HEX4 and HEX2 HEXO on the DE2 board will display the X and Y coordinates in Hexadecimal format of the touch point respectively DE2 board only Figure 4 7 indicates that the x and y coordinates of the corners on the LTM touch screen Figure 4 7 The x and y coordinates of the corners on the LTM touch screen 4 4 Block Diagram of the Ephoto Design Figure 4 8 shows the block diagram of the EPhoto demonstration As soon as
15. igure 1 3 and Figure 1 4 Figure 1 2 Connect the IDE cable to the TRDB_LTM board w Ad MA i 1 ut An M a hah Dal eam T hii P Figure 1 3 Connect the other end of IDE cable to the DE2 board s expansion port innermost expansion port About the Kit i sie se Al je 5 B i x i Figure 1 4 Connect the other end of IDE cable to the DE1 board s expansion port innermost expansion port 1 3 Getting Help Email to support terasic com Taiwan amp China 886 3 550 8800 Korea 82 2 512 7661 Japan 81 428 77 7000 lt lt lt Architecture of the LTM Architecture of the LIM This chapter will illustrate the architecture of the LTM including device features and block diagram 2 1 Features 1 Equipped with TDO43MTEA1 active matrix color TFT LCD module Support 24 bit parallel RGB interface 3 wire register control for display and function selection Built in contrast brightness and gamma modulation Je Converting the X Y coordination of the touch point to its corresponding digital data via the Analog Devices AD7843 AD converter o The general specifications of the LTM are listed below Item Description Unit Display Size Diagonal 4 3 Inch Aspect ratio 15 9 Display Type Transmissive Active Area HxV 93 6 x 56 16 mm Number of Dots HxV
16. igure 4 8 The block diagram of the Ephoto demonstration 4 5 Preprocessing the Desired Display Photo 1 Prepar three 24 bit bmp format photos and image resolution should be 800 high x 480 width as shown in Figure 4 9 H4 480 pixels r 800 pixels Picture 2 Picture 3 Figure 4 9 Original photo s resolution format 2 Usethe image processing software such as Photoshop or Photoimpact to rotate the images counterclockwise and then merge these photos into a new photo image The new photo s image resolution should be 1440 high x 800 width as shown in Figure 4 10 21 Digital Panel Design Demonstration Original Photos LTM Display photo format amp lt 480 pixels 3 4 800 pixels 800 pixels _ 9 480 pixels 1440 pixels Figure 4 10 The photo format of the DE2 LTM Ephoto DE1 LTM Ephoto demonstration 22 Digital Panel Design Demonstration 1 Ensure the connection is made correctly as shown in Figure 4 11 and Figure 4 12 Make sure the IDE cable is connected to JP1 of the DE2 DE1 board EL IE 3 b pue Me dd Figure 4 11 The connection setup for the pattern generator demo with DE2 board 23 Digital Panel Design Demonstration T EB pc aedi m ig Dep ume Ae SE tu xix Xi LX LL TY rl H KI AE a IET G dude E B BR BB B Figure 4 12 The connection
17. lection for resolution and standby Hardware pin RS 3 1 STBY Default initial setting value R03 6 Pre charge ON OFF Pre charge enable Default initial setting value R03 5 4 Driving capability Default ial sting value 30 Appendix 1 1 200 R03 3 PWM output ON OFF PWM disable PWM enable Default initial setting value RO3 2 VGL pump output ON OFF pump enable Default initial setting value RO3 1 CP output ON OFF CP CLK enable Default initial setting value Power management Normal operation Default initial setting value Note In standby mode DOUT 400 1 when VCOM are connected to GND PWM disabled Control signals STV CKV CKH1 CKH6 and XENB are low while XCKV XCKH1 XCKHE6 and ENB are high CLK1 is pulled high and is pulled low R04 5 4 VGL pump frequency RO4 5 4 Period Frequency for WVGA 1 H 32KHz Default initial setting value R04 3 2 CLK frequency 04 5 4 Period Frequency for WVGA P si H 32KHz Default initial setting value 31 Appendix 1 0 1 2 H 64KHz RO4 1 Vertical reverse function 1 Norma CSV H Default initial setting value R04 0 Horizontal reverse function x EE ee o o R05 5 0 Horizontal display position shift for SYNC mode display shift right Default initial setting value display shift left H06 3 0
18. ltage Input Signal Voltage Back Light Forward Current Operating Temperature Storage Temperature 26 Appendix 5 2 Power ON OFF and Mode Change Sequence of the LCD Panel Module PWM CP_CLK VGL Charge Pump Panel control signal DOUT Normal Out VDDP GRSTB Normal CP_CLK VGL Charge Pump a T Panel control signal Code 00h DOUT Normal Out 27 Appendix 5 3 Register map of the LCD Driver IC d 0x00 0x00 R W 7 0 Testing register 7 6 Dot inversion method selection 5 VD polarity 4 HD 0 02 0 07 R W polarity 3 Input clock latch data edge 2 0 Resolution selection 7 Hardware or software selection for resolution and standby 6 Pre charge on off 5 4 Output driving capability 3 PWM 0x03 Ox5F R W output on off 2 VGL pump output on off 1 CP_CLK output on off 0 Power management TYT 5 4 VGL pump frequency 3 2 CP_CLK frequency 1 0x04 0x17 R W Vertical reverse mode 0 Horizontal reverse mode 7 6 GAMMA 0 9 8 of gamma Correction 5 4 GAMMA 0x11 0x00 R W 8 9 8 of gamma Correction 3 2 GAMMA 16 9 8 of gamma Correction 1 0 GAMMA 32 9 8 of gamma Correction 7 6 GAMMA 64 9 8 of gamma Correction 5 4 GAMMA 0x12 Ox5B R W 96 9 8 of gamma Correction 3 2 GAMMA 128 9 8 of gamma Correction 1 0 GAMMA 192 9
19. n Geen ee Ge N Gee Re N ee Ged We de 26 5 1 ABSOLUTE MAXIMUM RATINGS OF THE LCD PANEL MODULE ee ee e ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee 26 5 2 POWER ON OFF AND MODE CHANGE SEQUENCE OF THE LCD PANEL MODULE ee ee ee ee ee ee ee ee ee 27 5 3 REGISTER MAP OF THE LCD DRIVER ee ee ee ee ee ee ee ee 28 5 4 REGISTER DEFINITION OF THE LCD DRIVER C een ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee 29 aims TORY 36 5 6 ALWAYS VISIT LTM WEBPAGE FOR NEW APPLICATIONS ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee 37 About the Kit About the Kit The TRDB_LTM LTM Kit provides everything you need to develop applications using a digital touch panel on an Altera DE2 DE1 board The kit contains complete reference designs and source code for implementing a photo viewer demonstration and a color pattern generator using the LTM kit and an Altera DE2 DE1 board This chapter provides users key information about the kit 1 1 Kit Contents 1 The Terasic LCD Touch Panel Module LTM board 2 A40 pin IDE cable 3 Complete reference design with source code Figure 1 1 The TRDB LTM Package About the Kit 1 2 Connecting LTM to the Altera DE Board 1 Connect the IDE cable to the back of the board as shown in Figure 1 2 2 Connect the other end of the IDE cable to your DE2 DE1 board s innermost expansion port JP1 as shown in F
20. on setting Please notice that in addition to the serial port interface signals NCLK input should also be provided while setting the registers Figure 3 1 and Table 3 1 show the frame format and timing diagram of the serial port interface The LCD driver IC recognizes the start of data Using the LTM transfer on the falling edge of SCEN input and starts data transfer When setting instruction the TPG110 inputs the setting values via SDA on the rising edge of input SCL The first 6 bits A5 specify the address of the register The next bit means Read Write command 0 is write command 1 is read command Then the next cycle is turn round cycle Finally the last 8 bits are for Data setting D7 DO The address and data are transferred from the MSB to LSB sequentially The data is written to the register of assigned address when End of transfer is detected after the 16th SCL rising cycles Data is not accepted if there are less or more than 16 cycles for one transaction tal ee Im ADC DCLK ito tiL toii Mito SCEN Figure 3 1 the frame format and timing diagram of the serial port interface SDA Setup Time SDA Hold Time EIE tw1L Pulso Width Cook Table 3 1 The timing parameters of the serial port interface Using the LTM 3 2 Input timing of the LCD panel display function To determine the sequencing and the timing of the image signals displayed on the LCD
21. r the ADC_PENIRQ_n output remains high normally When the touch screen connected to the ADC is touched via a pen or finger the ADC_PENIRQ_n output goes low initiating an interrupt to a FPGA that can then instruct a control word to be written to the ADC via the serial port interface The control word provided to the ADC via the DIN pin is shown in Table 3 5 This provides the conversion start channel addressing ADC conversion resolution configuration and power down of the ADC The detailed information on the order and description of these control bits can be found from the datasheet of the ADC in the DATASHEET folder on the LTM System CD ROM MSB LSB m commen ON Dmm mn PPD PT Using the LTM Table 3 5 Control register bit function description Figure 3 4 shows the typical operation of the serial interface of the ADC The serial clock provides the conversion clock and also controls the transfer of information to and from the ADC One complete conversion can be achieved with 24 ADC_DCLK cycles The detailed behavior of the serial port interface can be found in the datasheet of the ADC Note that the clock DCLK and chip enable signals SCEN of the serial port interface SHRAE the same signal VO with LCD driver IC Users should avoid controlling the LCD driver IC and ADC at the same time when designing the serial port interface controller Also because the chip enable signal SCEN inputted to the ADC comes up with a
22. rupt 2 ADC_DOUT output ADC serial interface data out 9 ADC BUSY output ADC serial interface busy 4 ADC DIN input ADC serial interface data in 5 ADC DCLK input ADC LCD serial interface clock 6 B3 Input LCD blue data bus bit 3 7 2 Input LCD blue data bus bit 2 8 B1 Input LCD blue data bus bit 1 9 BO Input LCD blue data bus bit 0 10 NCLK Input LCD clock signal 11 NC N A N A 12 GND N A Ground 13 DEN Input LCD RGB data enable 14 HD Input LCD Horizontal sync input 15 VD Input LCD Vertical sync input 16 B4 Input LCD blue data bus bit 4 17 5 Input LCD blue data bus bit 5 18 B6 Input LCD blue data bus bit 6 19 B7 Input LCD blue data bus bit 7 20 GO Input LCD green data bus bit 0 21 G1 Input LCD green data bus bit 1 22 G2 Input LCD green data bus bit 2 23 G3 Input LCD green data bus bit 3 Architecture of the 24 G4 Input LCD green data bus bit 4 25 G5 Input LCD green data bus bit 5 26 G6 Input LCD green data bus bit 6 27 G7 Input LCD green data bus bit 7 28 RO Input LCD red data bus bit 0 Table 2 1 The pin description of the 40 pin connector Using the LTM Using the LTM This chapter illustrates how to use the including how to control the serial port interface of the LCD driver IC and AD converter Also the timing requirement of the synchronous signal and RGB data which are outputted to the LCD panel module will be described 3 1 The Serial Port Interface of the LCD Driver IC The LCD and tou
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