Home

Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbyte Flash

1. Address Block Register label Register name vee status 0x00 7F90 DM BK1RE DM breakpoint 1 register OXFF extended byte 0x00 7F91 DM BK1RH DM breakpoint 1 register ayer high byte 0x00 7F92 DM BK1RL DM breakpoint 1 register oxFf x low byte 0x00 7F93 DM BK2RE DM breakpoint 2 register ayer extended byte 0x00 7F94 DM_BK2RH DM breakpoint 2 register ayer high byte 0x00 7F95 DM DM BK2RL DM breakpoint 2 register OxFF low byte 0x00 7F96 DM CR1 DM debug module control 0x00 register 1 0x00 7F97 DM CR2 DM debug module control 0x00 register 2 0x00 7F98 DM CSR1 DM debug module 0x10 a control status register 1 0x00 7F99 DM_CSR2 DM debug module 0x00 control status register 2 0x00 7F9A DM_ENFCTR DM enable function register OxFF 0x00 7F9B to 0x00 7F9F Reserved area 5 byte 1 Accessible by debug module only 2 DoclD14771 Rev 15 43 121 Interrupt vector mapping STM8S105x4 6 7 Interrupt vector mapping Table 10 Interrupt mapping PHAT Wakeup from Wakeup from IRQ no Source block Description halt mode a tive halt mode Vector address RESET Reset Yes Yes 0x00 8000 TRAP Software interrupt 0x00 8004 0 TLI External top level y 0x00 8008 interrupt 1 AWU Auto wakeup from Yes 0x00 800C halt 2 CLK Clock controller 0x00 8010 3 EXTIO va yea Yes 0x00 8014 interrup
2. 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off 58 121 DoclD14771 Rev 15 2 STM8S105x4 6 Electrical characteristics Table 23 Total current consumption in wait mode at Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 1 75 HSE user ext clock fcpu MASTER 16 MHz 16 MHz 1 55 2 0 Supply HSI RC osc 16 MHz 1 5 1 9 IDowrn current in mA waitmods fopy fuasrER 128 125 kHz HSI RC osc 16 MHz 1 3 fopu fmasTER 5128 2 15 625 kHz HSI RC osc 16 MHz 8 0 7 fopu fmAsTER 128 kHz LSI RC osc 128 kHz 0 5 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off Total current consumption in active halt mode Table 24 Total current consumption in active halt mode at Vpp 5 V Conditions Main Max at Max at i Symbol Parameter voltage 5 Sm Typ 85 C 85 acl Unit regulator Flash mode ock source MVR HSE crystal osc Operating mode 16 MHz 1080 Operating mode 587 LSI RC osc 128 kHz 200 320 400 On Supply Power down HSE crystal osc 1030 i current in mode 16 MHz UA DD AH active halt moda a Ben LSIRC osc 128kHz 140 270 350 Operating mode 58 LSI RC osc
3. not guaranteed in p this area 16 12 F nctiojalty guaranteed 7 QTA 40to0125 C 8 2 95 4 0 5 0 5 5 Supply voltage MSv36469V1 Table 19 Operating conditions at power up power down Symbol Parameter Conditions Min Typ Max Unit Vpp rise time rate 20 oo too ys V Vpp fall time rate 20 oo TEMP Reset release delay Vpp rising 170 ms DoclD14771 Rev 15 55 121 Electrical characteristics STM8S105x4 6 Table 19 Operating conditions at power up power down continued Symbol Parameter Conditions Min Typ Max Unit Power on reset Vit threshold 2 65 2 8 2 95 B V rown out reset Vi threshold 2 58 2 65 2 88 Brown out reset VHYS BOR hysteresis 70 mV 1 Guaranteed by design not tested in production d 56 121 DoclD14771 Rev 15 STM8S105x4 6 Electrical characteristics 10 3 1 10 3 2 VCAP external capacitor The stabilization for the main regulator is achieved by connecting an external capacitor Cexr to the VcAp pin Cex7 is specified in Table 18 Care should be taken to limit the series inductance to less than 15 nH Figure 12 External capacitor Cext C ESL PO id et ESR RLeak MSv36488V1 1 ESR is the equivalent series resistance and ESL is the equivalent inductance Supply current characteristics The current consumption is measured as illustrated in Figure 10 Pin input vol
4. Rm i E fuse to core gt Lm CoT Rr Cu Cm RR e OSCIN e 9m Resonator E Consumption E R i control esonator I C OSCOUT L2 STM8 MS36490V3 HSE oscillator critical g equation 2x1 x fyge 2 x R 2Co C Omeri Rm Notional resistance see crystal specification Lm Notional inductance see crystal specification Cm Notional capacitance see crystal specification Co Shunt capacitance see crystal specification C 4 Cj C Grounded external capacitance Im e 9merit d 68 121 DoclD14771 Rev 15 STM8S105x4 6 Electrical characteristics 10 3 4 Internal clock sources and timing characteristics Subject to general operating conditions for Vpp and T High speed internal RC oscillator HSI Table 33 HSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fusi Frequency 16 MHz User trimmed with Accuracy of HSI oscillator CLE HSITRIMR registenior 12 given Vpp and Ta conditions 5V VDD ACCus Ta 25 c 1 0 1 0 HSI oscillator accuracy Vpp 5 V 20 20 factory calibrated 25 C lt Tas 85 C 2 95 V lt Vpp lt 5 5V 3 3 40 C lt TA lt 125 C SN abo HSI oscillator wakeup E 2 su HS time including calibration S lupos HSI oscillator power 7 170 2508 pA consumption 1 Refer to application note 2 Guaranteed by de
5. Memory area Size byte Start address End address 32K 0x00 8000 0x00 FFFF Flash program memory 16K 0x00 8000 0x00 BFFF RAM 2K 0x00 0000 0x00 07FF Data EEPROM 1024 0x00 4000 0x00 43FF 6 2 Register map 6 2 1 O port hardware register map Table 7 I O port hardware register map Address Block Register label Register name Reset status 0x00 5000 PA_ODR Port A data output latch register 0x00 0x00 5001 PA IDR Port A input pin value register Oxxx 0x00 5002 Port A PA_DDR Port A data direction register 0x00 0x00 5003 PA_CR1 Port A control register 1 0x00 0x00 5004 PA_CR2 Port A control register 2 0x00 0x00 5005 PB_ODR Port B data output latch register 0x00 0x00 5006 PB_IDR Port B input pin value register Oxxx 0x00 5007 Port B PB_DDR Port B data direction register 0x00 0x00 5008 PB CR1 Port B control register 1 0x00 0x00 5009 PB_CR2 Port B control register 2 0x00 0x00 500A PC_ODR Port C data output latch register 0x00 0x00 500B PB_IDR Port C input pin value register 0xxx 0x00 500C Port C PC DDR Port C data direction register 0x00 0x00 500D PC CR1 Port C control register 1 0x00 0x00 500E PC CR2 Port C control register 2 0x00 0x00 500F PD ODR Port D data output latch register 0x00 0x00 5010 PD IDR Port D input pin value register 0xxx 0x00 5011 Port D PD DDR Port D data direction register 0x00 0x00 5012 PD CR1 Port D control register 1 0x02 0x00 5013 PD CR2 Port D control register 2 0x00 32 121 DoclD14771 Rev 15 ky STM8S10
6. 16 121 DoclD14771 Rev 15 2 STM8S105x4 6 Product overview 4 6 4 7 2 Power management For efficient power management the application can be put in one of four different low power modes You can configure each mode to obtain the best compromise between lowest power consumption fastest start up time and available wakeup sources e Wait mode In this mode the CPU is stopped but peripherals are kept running The wakeup is performed by an internal or external interrupt or reset e Active halt mode with regulator on In this mode the CPU and peripheral clocks are stopped An internal wakeup is generated at programmable intervals by the auto wake up unit AWU The main voltage regulator is kept powered on so current consumption is higher than in active halt mode with regulator off but the wakeup time is faster Wakeup is triggered by the internal AWU interrupt external interrupt or reset e Active halt mode with regulator off This mode is the same as active halt with regulator on except that the main voltage regulator is powered off so the wake up time is slower e Halt mode In this mode the microcontroller uses the least power The CPU and peripheral clocks are stopped the main voltage regulator is powered off Wakeup is triggered by external event or reset Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications Activation of the watc
7. STM8S105x4 6 Package information 2 Table 52 LQFP44 44 pin 10 x 10 mm low profile quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 300 0 370 0 450 0 0118 0 0146 0 0177 0 090 0 200 0 0035 0 0079 D 11 800 12 000 12 200 0 4646 0 4724 0 4803 D1 9 800 10 000 10 200 0 3858 0 3937 0 4016 D3 8 000 0 3150 E 11 800 12 000 12 200 0 4646 0 4724 0 4803 E1 9 800 10 000 10 200 0 3858 0 3937 0 4016 E3 8 000 0 3150 e 0 800 0 0315 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 3 5 7 0 3 5 7 ccc 0 100 0 0039 1 Values in inches are converted from mm and rounded to 4 decimal digits DoclD14771 Rev 15 95 121 Package information STM8S105x4 6 96 121 Figure 51 LQFP44 44 pin 10 x 10 mm low profile quad flat package recommended footprint A LO UUdBagdn tg La pasa 3 ELI Co CT CJ CJ CJ CJ o o A E eo CJ CJ Co CJ Co 10 3 Co ET LI O 2C Y 1 2 0000000000 la 12 7 A Y 4Y_FP 1 Dimensions are expressed in millimeters Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location d
8. node wakeup t ae eee al Flash in operating mode 52 i i WEE mode to run mode n 9 t ARANEAE Famina Flash in power down mode 54 I WURI mode to run mode P 1 Data based on characterization results not tested in production 2 Measured from interrupt event to interrupt vector fetch 3 twuqwen 2 X 1fmaster 67 x 1 fcpu 4 Configured by the REGAH bit in the CLK_ICKR register 5 Configured by the AHALT bit in the FLASH CR1 register 6 Plus 1 LSI clock depending on synchronization Total current consumption and timing in forced reset state Table 29 Total current consumption and timing in forced reset state Symbol Parameter Conditions Typ Max Unit Supply current in reset Vpp 75V 500 E IDD R state HA Vpp 3 8 V 400 Reset pin release to RESETBL vector fetch 150 pS 1 Data guaranteed by design not tested in production 2 Characterized with all I Os tied to Vss Current consumption of on chip peripherals Subject to general operating conditions for Vpp and T Ly DoclD14771 Rev 15 61 121 Electrical characteristics STM8S105x4 6 62 121 HSI internal RC fepy fMASTER 16 MHz Vpp 5V Table 30 Peripheral current consumption Symbol Parameter Typ Unit Ipocrima TIM1 supply current mm Ippctimz TIM2 supply current sis Ipocrim3 TIM3 supply current T lppcrima TIM4 supply current 2 Ipo uART2 UART2 supply current 2 Tm UA Ipp sPl SPI supply
9. 2 Absolute maximum ratings Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 15 Voltage characteristics Symbol Ratings Min Max Unit Vppx Vss Supply voltage including VppA and Vopio 0 3 6 5 V Input voltage on true open drain pins PE1 PE2 2 Vgg 0 3 6 5 i Input voltage on any other pin Vss 0 3 Vpp 0 3 IVppx Vppl Variations between different power pins 50 IVssx Vss Variations between all the different ground pins 50 id see Absolute maximum ratings Vesp Electrostatic discharge voltage electrical sensitivity on page 89 1 All power Vpp and ground Vss pins must always be connected to the external power supply 2 lingcpin must never be exceeded This is implicitly insured if Vjy maximum is respected If V y maximum cannot be respected the injection current must be limited externally to the li py value A positive injection is induced by Vin gt Vpp while a negative injection is induced by Vjn lt Vss For true open drain pads there is no positive injection current and the corresponding Vjy maximum must always be respected Table 16 Current characteristics Symbol
10. Figure 59 SDIP32 package outline 104 121 76_ME Table 55 SDIP32 package mechanical data mm inches Dim Min Typ Max Min Typ Max A 3 556 3 759 5 080 0 1400 0 1480 0 2000 A1 0 508 0 0200 A2 3 048 3 556 4 572 0 1200 0 1400 0 1800 B 0 356 0 457 0 584 0 0140 0 0180 0 0230 B1 0 762 1 016 1 397 0 0300 0 0400 0 0550 0 203 0 254 0 356 0 0079 0 0100 0 0140 D 27 430 27 940 28 450 1 0799 1 1000 1 1201 9 906 10 410 11 050 0 3900 0 4098 0 4350 E1 7 620 8 890 9 398 0 3000 0 3500 0 3700 e 1 778 0 0700 eA 10 160 0 4000 DoclD14771 Rev 15 d Package information STM8S105x4 6 Table 55 SDIP32 package mechanical data continued mm inches Dim Min Typ Max Min Typ Max eB 12 700 0 5000 L 2 540 3 048 3 810 0 1000 0 1200 0 1500 2 1 Values in inches are converted from mm and rounded to 4 decimal digits Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 60 SDIP32 marking example package top view Product identification 1 Revision code Pin 1 identifier Standard ST logo Date code MS38332V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from suc
11. STM8S105x4 6 Product overview 4 12 TIM4 8 bit basic timer e 8 bit auto reload adjustable prescaler ratio to any power of 2 from 1 to 128 e Clock source CPU clock e Interrupt source 1 x overflow update Table 3 TIM timer features Timer Ti Counter Counting CAPCOM Complementary Ext pay imer s Prescaler a synchronization size bits mode channels outputs trigger an chaining Any integer TIM1 16 from 1 to Up down 4 3 Yes 65536 Any power TIM2 16 of 2 from 1 Up 3 0 No to 32768 No Any power TIM3 16 of 2 from 1 Up 2 0 No to 32768 Any power TIM4 8 of 2 from 1 Up 0 0 No to 128 4 13 Analog to digital converter ADC1 The STM8S105x4 6 products contain a 10 bit successive approximation A D converter ADC1 with up to 10 multiplexed input channels and the following main features e Input voltage range 0 to VDD e Conversion time 14 clock cycles e Single and continuous and buffered continuous conversion modes e Buffer size n x 10 bits where n number of input channels e Scan mode for single and continuous conversion of a sequence of channels e Analog watchdog capability with programmable upper and lower thresholds e Analog watchdog interrupt e External trigger input e Trigger from TIM1 TRGO e Endof conversion EOC interrupt Note Additional AIN12 analog input is not selectable in ADC scan mode or with analog watchdog 2 Values converted from AIN12 are stored only into the ADC_DRH
12. 1 Port D7 alternate function TIM1_CH4 AFR3 Alternate function remapping option 3 0 AFR3 remapping option inactive Default alternate function 1 Port DO alternate function TIM1 BKIN AFR2 Alternate function remapping option 2 0 AFR2 remapping option inactive Default alternate functions 2 1 Port DO alternate function CLK_CCO Note AFR2 option has priority over AFR3 if both are activated AFR1 Alternate function remapping option 1 0 AFR1 remapping option inactive Default alternate functions 1 Port A3 alternate function TIM3 CH1 port D2 alternate function TIM2_CH3 AFRO Alternate function remapping option 0 0 AFRO remapping option inactive Default alternate functions 1 Port D3 alternate function ADC_ETR 2 1 Do not use more than one remapping option in the same port 2 Refer to STM8S105x4 6 pin descriptions DoclD14771 Rev 15 49 121 Unique ID STM8S105x4 6 9 50 121 Unique ID The devices feature a 96 bit unique device identifier which provides a reference number that is unique for any device and in any context The 96 bits of the identifier can never be altered by the user The unique device identifier can be read in single byte and may then be concatenated using a custom algorithm The unique device identifier is ideally suited e For use as serial numbers e For use as security keys to increase the code security in the program memory while using and combinin
13. 128 kHz 68 120 220 Off Power down LSI RC osc 128 kHz 12 60 150 mode 1 Data based on characterization results not tested in production 2 Configured by the REGAH bit in the CLK_ICKR register 3 Configured by the AHALT bit in the FLASH CR1 register Ly DoclD14771 Rev 15 59 121 Electrical characteristics STM8S105x4 6 Table 25 Total current consumption in active halt mode at Vpp 3 3 V Conditions Main Max at Max at Symbol Parameter voltage m Typ 85 C 85 acl Unit regulator Flash mode ock source MVR HSE crystal osc Operating mode 16 MHz 680 Operating mode 58 LSI RC osc 128 kHz 200 320 400 Supply On Power down HSE crystal osc 630 i i i current in mode 16 MHz A DD AH active halt H mode kaa How LSI RC osc 128 kHz 140 270 350 Operating mode 758 LSI RC osc 128 kHz 66 120 220 Off Power down LSI RC osc 128 kHz 10 60 150 mode 1 Data based on characterization results not tested in production 2 Configured by the REGAH bit in the CLK_ICKR register 3 Configured by the AHALT bit in the FLASH CR1 register Total current consumption in halt mode Table 26 Total current consumption in halt mode at Vpp 5 V 2 Maxat Maxat Symbol Parameter Conditions Typ 85 C 85 acl Unit Flash in operating mode HSI 62 90 150 Supply current in halt Clock after wakeup WA SERE mode Flash i
14. Figure 17 Typ Ippcwe VS fcpu HSE external clock Vpp 5 V locremuse mA 10 15 20 fcpu MHz 64 121 DoclD14771 Rev 15 2 STM8S105x4 6 Electrical characteristics Figure 18 Typ Ipp wen VS Vpp HSI RC osc fcpy 16 MHz 5 BB 5 B3 GG BG 8 888 8 8 a 2 15 hame ae a COSO 9 O a O CSI CI CS CS E 14 25 3 3 5 4 45 5 5 5 6 2 DoclD14771 Rev 15 65 121 Electrical characteristics STM8S105x4 6 10 3 3 HSE user external clock Subject to general operating conditions for Vpp and T Table 31 HSE user external clock characteristics External clock sources and timing characteristics Symbol Parameter Conditions Min Max Unit II o 5 me Vusgu Edo pin high 0 7xVpp Vpp 0 3 V v Vusg ee pM E Vss 0 3 x Vpp ILEAK HSE pia pute Vss lt Vin lt Vpp 1 1 pA 1 Data based on characterization results not tested in production Figure 19 HSE external clock source 66 121 External clock source JUUL DoclD14771 Rev 15 MS36489V2 2 STM8S105x4 6 Electrical characteristics HSE crystal ceramic resonator oscillator The HSE clock can be supplied with a 1 to 16 MHz crystal ceramic resonator oscillator All the information given in this paragraph is based on characterization results with specified typical external components In the application the resonator and the load capacitors have to
15. k y life augmented STM85105C4 6 STM8S105K4 6 STM8S105S4 6 Access line 16 MHz STM8S 8 bit MCU up to 32 Kbyte Flash integrated EEPROM 10 bit ADC timers UART SPI PC Features Core e 16 MHz advanced STM8 core with Harvard architecture and 3 stage pipeline e Extended instruction set Memories e Program memory up to 32 Kbyte Flash data retention 20 years at 55 C after 10 kcycle e Data memory up to 1 Kbyte true data EEPROM endurance 300 kcycle e RAM up to 2 Kbyte Clock reset and supply management e 2 95 to 5 5 V operating voltage e Flexible clock control 4 master clock sources Low power crystal resonator oscillator External clock input Internal user trimmable 16 MHz RC Internal low power 128 kHz RC e Clock security system with clock monitor e Power management Low power modes wait active halt halt Switch off peripheral clocks individually e Permanently active low consumption power on and power down reset Interrupt management e Nested interrupt controller with 32 interrupts e Up to 37 external interrupts on 6 vectors Timers e Advanced control timer 16 bit 4 CAPCOM channels 3 complementary outputs dead time insertion and flexible synchronization September 2015 Datasheet production data qu DR LQFP48 7x7 mm LQFP44 10x10 mm LQFP32 7x7 mm i UFQFPN32 5x5 mm 1 SDIP32 400ml e 2x16 bit general purpose timer with
16. ports two high sink 443 EM ports and two open a Power dissipation at TA 85 C drain ports Pp for suffix 6 or Taz 125 C for simultaneously mW suffix 3 32 pin package with output on eight standard ports and 360 two high sink ports simultaneously d 54 121 DoclD14771 Rev 15 STM8S105x4 6 Electrical characteristics d Table 18 General operating conditions continued Symbol Parameter Conditions Min Max Unit T Ambient temperature for suffix Maximum power 40 85 5 6 version dissipation T Ambient temperature for suffix Maximum power 40 125 A 3 version dissipation C Suffix 6 version 40 105 Tj Junction temperature range Suffix 3 version 40 130 Care should be taken when selecting the capacitor due to its tolerance as well as the parameter dependency on temperature DC bias and frequency in addition to other factors The parameter maximum value must be respected for the full application range This frequency of 1 MHz as a condition for VcAp parameters is given by design of internal regulator To calculate Ppmax Ta use the formula Pomax TJmax TANG ja see Section 12 Thermal characteristics with the value for T max given in the previous table and the value for O a given in Section 12 Thermal characteristics See Section 12 Thermal characteristics Figure 11 fcpumax Versus Vpp fceu MHz Functionality
17. 0x00 5400 ADC_CSR ADC control status register 0x00 0x00 5401 ADC CR1 ADC configuration register 1 0x00 0x00 5402 ADC CR2 ADC configuration register 2 0x00 0x00 5403 ADC_CR3 ADC configuration register 3 0x00 0x00 5404 ADC_DRH ADC data register high OxXX 0x00 5405 ADC_DRL ADC data register low OxXX 0x00 5406 ADC_TDRH ADC Schmitt trigger disable 0x00 register high 0x00 5407 ADC TDRL ADC Schmitt trigger disable 0x00 register low 0x00 5408 ADC_HTRH Dh high threshold register 0x03 ADC1 0x00 5409 cont d ADC_HTRL den high threshold register OxFF 0x00 540A ADC LTRH a low threshold register 0x00 0x00 540B ADC_LTRL pa low threshold register 0x00 0x00 540C ADC_AWSRH ADC analog watchdog status 0x00 register high 0x00 540D ADC AWSRL ADC analog watchdog status 0x00 register low 0x00 540E ADC AWCRH ADC analog watchdog control Pasan register high 0x00 540F ADC_AWCRL ADC analog watchdog control 0x00 register low 0x00 5410 to 0x00 57FF Reserved area 1008 byte 1 Depends on the previous reset source 2 Write only register 2 DoclD14771 Rev 15 41 121 Memory and register map STM8S105x4 6 6 2 3 CPU SWIM debug module interrupt controller registers Table 9 CPU SWIM debug module interrupt controller registers Address Block Register label Register name
18. 1 32 PD2 HS TIM3_CH1 TIM2 CH3 BEEP TIM2_CH1 HS PD4 2 31 Pb1 Hsyswim UART2 TX PD5 3 UART2 RX PD6 4 TIM1_CH4 TLI PD7 5 29 Pc7 HsysPI Miso 28 Pce HsysPi vos NRsT 6 27 Pcs HsysPI_sck OSCIN PA1 7 26 Pc4 HsyTIM1 cH4 oscour PA2 8 25 Pc3 HS TIM1_CH3 vss 9 24 Pc2 HsyTIM1_CH2 vcaP 10 23 Pct HS TIM1_CH1 UART2_CK vpD 11 22 PEs sPi Nss VDDIO 12 21 PBO AINO TIM1_CH1N AIN12 PF4 13 20 PBt AIN1 TIM1_CH2N vppA 14 19 PB2 aiN2 Tim1_CH3N 18 PBs AIN3 TIM1 ETR 17 PB4 AIN4 12C_SCL VSSA I2C_SDA AINS PB5 16 30 ppo HS TIM3 CH2 TIM1 BKIN CLK CCO MS38308V1 HS high sink capability T True open drain P buffer and protection diode to Vpp not implemented 3 J alternate function remapping option if the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function Table 5 STM8S105x4 6 pin description Pin number Input Output e Alternate S pa i a AP function Default arer 2 TF G N Pinname Type 2 E cl v alternate Aa A ILIA 3 2 8 ala after i remap LiLI2z G cle ola unction A GIGI3 A 9e 5 5 5 amp reset option pa e FA bit rm Lu o d 1 1 1 6 NRST 1 0 X Reset Resonato 2 2 2 7 PA1 OSC IN VO XIX O1 X X PortA1 r crystal in Resonato 3
19. 4 11 TIM2 TIM3 16 bit general purpose timers 18 4 12 TIM4 8 bit basic timer ooo 19 4 13 Analog to digital converter ADC1 0 0 00 cee ee eee 19 4 14 Communication interfaces llle 20 4141 CUARTA Oe RV oes Yee ERE ee RM 20 Ang SPA KAGAT NA NA NANANA Bata ae LA 21 AMES NG maana sas AGANG GAANO 21 5 Pinout and pin description cece eee 22 5 1 Alternate function remapping cece eee ee eee 30 6 Memory and register map 2222 eee eee eee 31 6 1 Memory map sapang 2 haaa kaaa RR ee Shade wee Reames 31 6 2 Register map AA 32 6 2 1 I O port hardware register map eee e eee eee 32 6 2 2 General hardware register map eee o 34 2 121 DoclD14771 Rev 15 Ly STM8S105x4 6 Contents 10 11 2 6 2 3 CPU SWIM debug module interrupt controller registers 42 Interrupt vector mapping eeeennn iile 44 Option DYE xico xa na ELENA cee eee Re RE ewe ee cane 46 8 1 Alternate function remapping bits 000000 c eee ees 49 Ubique IB oracle a i ak aka AA 50 Electrical characteristics oooooocoonocornmmmmmmmm o 51 10 4 Parameter conditions lille 51 10 1 1 Minimum and maximum values 22000 eee eee eee 51 10 1 2 Typical values tee 51 10 1 3 Typical CUIVES ui ciues RR Rx a Peas aaa 51 10 1 4 Typical current consumption lessen 51 10 1 5 Load
20. 75 Typ Voy O Vpp 5 0 V standard ports 000202 75 Typ Vo O Vpp 3 3 V true open drain ports 00 000000000008 76 Typ Vo O Vpp 5 0 V true open drain ports 00 0 0 00000008 76 Typ Vo Vpp 3 3 V high sink ports 0 2 ee 76 Typ Vo Vpp 5 0 V high sink ports 0 ee 76 Typ Vpp Vou O Vpp 3 3 V standard ports 00 00 0000 77 Typ Vpp Vou O Vpp 5 0 V standard ports aaneen 77 Typ Vpp Vou O Vpp 3 3 V high sink ports annnars a 77 Typ Vpp Vou O Vpp 5 0 V high sink ports oo 77 Typical NRST Vj and Vj vs Vpp 4 temperatures 0 0 illii sells 78 Typical NRST pull up resistance Rpy vs Vpp 4 temperatures 79 Typical NRST pull up current lp vs Vpp 4 temperatures a 79 Recommended reset pin protection 2 020 eee 80 SPI timing diagram where slave mode and CPHA 0 2202200 ee eee 82 SPI timing diagram where slave mode and CPHA 1 22200200e eee 82 SPI timing diagram master Mode 1 2 0 ce eee 83 Typical application with 12C bus and timing diagram 00 eee 84 ADC accuracy characteristics lee 87 Typical application with ADC 87 LQFP48 48 pin 7 x 7 mm low profile quad flat package outline 91 LQFP48 48 pin 7 x 7 mm low profile quad flat package DoclD14771 Rev 15 7 121 List of figures ST
21. A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 300 0 370 0 450 0 0118 0 0146 0 0177 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 600 0 2205 E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 600 0 2205 e 0 800 0 0315 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 3 5 7 0 3 5 7 ccc 0 100 0 0039 1 Values in inches are converted from mm and rounded to 4 decimal digits Ky DoclD14771 Rev 15 99 121 Package information STM8S105x4 6 100 121 Figure 54 LQFP32 32 pin 7 x 7 mm low profile quad flat package recommended footprint TT 00000003 A Co sC 50 m 030 i C L1 Ca 7 30 610 LL a LI 7 30 L 1 C mE 00000004 a 6 10 y lt 9 70 gt 5V_FP_V2 1 Dimensions are expressed in millimeters Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 55 LQFP32 marking example package top view ani STMAS10 5K4T3C Date code Standard ST logo Revision code Pin 1 identifier MS38330V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not
22. Inventory Delivery amp Lifecycle Information STMicroelectronics STM8S105C4T6TR STM8S105C4T3 STM8S105C6T6TR STM8S105K4T6CTR STM8S105K6T3C STM8S105C6T3TR STM8S105K4U6ATR
23. independent watchdogs with a separate clock source and a clock security system Short development cycles are guaranteed due to application scalability across common family product architecture with compatible pinout memory map and modular peripherals Product longevity is ensured in the STM8S family thanks to their advanced core which is made in a state of the art technology for applications with 2 95 V to 5 5 V operating supply Full documentation is offered as well as a wide choice of development tools 2 10 121 DoclD14771 Rev 15 STM8S105x4 6 Description Table 1 STM8S105x4 6 access line features Device STM8S105C6 STM8S105C4 STM8S105S6 STM8S105S4 STM8S105K6 STM8S105K4 Pin count 48 48 44 44 32 32 Maximum number of 38 38 34 34 25 25 GPIOs Ext Intermupt 35 35 31 31 23 23 pins Timer CAPCOM 9 9 8 8 8 8 channels Timer complementar 3 3 3 3 3 3 y outputs A D Converter 10 10 9 9 7 7 channels High sink I Os 16 16 15 15 12 12 Medium density Fl sh 32K 16K 32K 16K 32K 16K Program memory byte Data EEPROM 1024 1024 1024 1024 1024 1024 bytes RAM bytes 2K 2K 2K 2K 2K 2K Peripheral set Advanced control timer TIM1 General purpose timers TIM2 and TIM3 Basic timer TIM4 SPI I2C UART Window WDG Independent WDG ADC 2 DoclD14771 Rev 15 11 121 Block diagram STM8S105x4 6 3 Block diagram Figure 1 STM8S105x4 6 b
24. 0x00 502A Port PI DDR Port data direction register 0x00 0x00 502B PI CR1 Port control register 1 0x00 0x00 502C PI CR2 Port control register 2 0x00 1 Depends on the external circuitry Ky DoclD14771 Rev 15 33 121 Memory and register map STM8S105x4 6 6 2 2 General hardware register map Table 8 General hardware register map Address Block Register label Register name Reset status 0x00 5050 to 0x00 5059 Reserved area 10 byte 0x00 505A FLASH CR1 Flash control register 1 0x00 0x00 505B FLASH_CR2 Flash control register 2 0x00 0x00 505C FLASH NCR2 Flash complementary control Gee x register 2 0x00 505D Flash FLASH FPR Flash protection register 0x00 0x00 505E FLASH _NFPR Pan COMPEMENAN OxFF protection register 0x00 505F FLASH IAPSR Plast it apple a 0x00 programming status register 0x00 5060 to 0x00 5061 Reserved area 2 byte 0x00 5062 Flash FLASH PUKR Flash program memory 0x00 unprotection register 0x00 5063 Reserved area 1 byte 0x00 5064 Flash FLASH _DUKR Data EEPROM unprotection 0x00 register 0x00 5065 to 0x00 509F Reserved area 59 byte 0x00 50A0 EXTI CR1 External interrupt control 0x00 register 1 ITC 0x00 50A1 EXTI_CR2 External interrupt control 0x00 register 2 0x00 50A2 to 0x00 50B2 Reserved area 17 byte 0x00 50B3 RST RST SR Reset status register oxxx 1 0x00 50B4 to 0x00 50BF Reserved area 12 byte 0x0
25. 1x for X x PortB5 Adee 2C_SDA P AFR6 PB4 AIN4 Analog 12C_SCL 18 17 12 17 me say VO X X x JOt X xX PotB4 iota TERI PB3 AIN3 Analog TIM1 ET 19 18 13 8 mim rey YO X X X 01 X X PotB3 73 R AFR5 TIM1 CH 20 19 14 19 Si ea vo x x x fot x x PotB2 ae 3N TIM1_ Mpy AFR5 TIM1_CH 21 20 15 20 a ee vo XIX X O1 X Xx PortB1 Ka 2N E E AFR5 TIM1 CH 22 21 16 21 napag ani vo XIX X O1 X X PortBO d 1N p AFR5 oe lal PEZ AN8 vo XIX X ot x x Potez Analog input 8 Ky DoclD14771 Rev 15 27121 Pinout and pin description STM8S105x4 6 Table 5 STM8S105x4 6 pin description continued Pin number Input Output e Alternate 9 a a function Default arer 2 Q3g g Pinname Type 2 E els alternate Aa anui ng zig g2g v S9 ai a after remap LiuLtLi2i iz o ele ola function GIG ala 9 5 046 amp reset option eere m u ZI bit LL Ww G l 24 22 Pesang vo XIX x O1 x x Portes Analog input 9 SPI 25 23 17 22 PE5 SPI NSS IO XIX X O1 x X Portes bod select Timer 1 PC1 channel 26 24 18 23 TIM1 CH1 VO XI X X HS OS X X PortC1 1 UART2 UART2 CK synchron ous clock PC2 Timer 1 27 25 19 24 mw cuo VO X X X HS OS X X PortC2 hannel z PC3 Timer 1 28 26
26. ADC_DRL registers DoclD14771 Rev 15 19 121 Product overview STM8S105x4 6 4 14 4 14 1 20 121 Communication interfaces The following communication interfaces are implemented e UART1 Full feature UART synchronous mode SPI master mode Smartcard mode IrDA mode single wire mode LIN2 1 master capability e SPI Full and half duplex 8 Mbit s ee C Up to 400 kbit s UART2 Main features e 1 Mbit s full duplex SCI e SPI emulation e High precision baud rate generator e Smartcard emulation e IrDA SIR encoder decoder e LIN master mode e LIN slave mode Asynchronous communication UART mode e Full duplex communication NRZ standard format mark space e Programmable transmit and receive baud rates up to 1 Mbit s fCPU 16 and capable of following any standard baud rate regardless of the input frequency e Separate enable bits for transmitter and receiver e Two receiver wakeup modes A Address bit MSB dle line interrupt e Transmission error detection with interrupt generation e Parity control Synchronous communication e Full duplex synchronous transfers e SPI master operation e 8 bit data communication e Maximum speed 1 Mbit s at 16 MHz fCPU 16 LIN master mode e Emission Generates 13 bit synch break frame e Reception Detects 11 bit break frame d DoclD14771 Rev 15 STM8S105x4 6 Product overview LIN slave mode e Autonomous header handling one
27. DoclD14771 Rev 15 STM8S105x4 6 Package information Figure 52 LQFP44 marking example package top view Product identification S T M S l 5 Standard ST logo Revision code Pin 1 identifier MS38329V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity 2 DoclD14771 Rev 15 97 121 Package information STM8S105x4 6 11 3 98 121 LQFP32 package information Figure 53 LQFP32 32 pin 7 x 7 mm low profile quad flat package outline SEATING PLANE Pt cd fAAHHHHHHH CCC AG 0 25 mm GAUGE PLANE 5V ME V2 1 Drawing is not to scale DoclD14771 Rev 15 2 STM8S105x4 6 Package information Table 53 LQFP32 32 pin 7 x 7 mm low profile quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059
28. Heset status 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 0x00 7F04 XH X index register high 0x00 0x00 7F05 cpu XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x03 0x00 7F09 SPL Stack pointer low OxFF 0x00 7FOA CCR Condition code register 0x28 0x00 7FOB to 0x00 7F5F Reserved area 85 byte 0x00 7F60 CPU CFG_GCR GlabaPtaniiguralak 0x00 register 0x00 7F70 ITC SPR1 Interrupt software priority opf register 1 0x00 7F71 ITC_SPR2 Interrupt software priority opf register 2 0x00 7F72 ITC_SPR3 Interrupt software priority ber register 3 0x00 7F73 ITC_SPR4 Interrupt software priority opf E register 4 ITC 0x00 7F74 ITC_SPR5 Interrupt software priority opf register 5 0x00 7F75 ITC_SPR6 Interrupt software priority nec E register 6 0x00 7F76 ITC SPR7 Interrupt software priority os B register 7 0x00 7F77 ITC_SPR8 Interrupt software priority opf register 8 0x00 7F78 to 0x00 7F79 Reserved area 2 byte 0x00 7F80 SWIM SWIM_CSR que 0x00 E register 0x00 7F81 to 0x00 7F8F Reserved area 15 byte 2 42 121 DoclD14771 Rev 15 STM8S105x4 6 Memory and register map Table 9 CPU SWIM debug module interrupt controller registers continued
29. cece eee 25 SDIP32 PIQUE AKA cece aang e Bok ROCA EI ROREM ae AER pe A a Re de A AER 26 Memory Map iii coin comen Pda eae el e mor ee poe ed god ee a 31 Supply current measurement conditions cc eee ees 51 Pin loading conditions sioe rem temen rh mem nm ee dae eae 52 Pin input voltage 6 RR RR RR 3 err 52 TepUimax VOFSUS VDD isa Ir dc aen e pe eec cea Eg ce RU AR cen n OR n Nga 55 External capacitor CExr e 57 Typ Ipp Ruw VS Vpp HSE user external clock fepy 16 MHz a 62 Typ Ipp Ruw VS fcpu HSE user external clock Vpp 25V 1 6 aa 63 Typ IDD RUN vs Vpp HSI RC osc feru S16 MHZ cti ste e Sa ee 63 Typ Ipp wri VS Vpp HSE external clock fepy 16 MHZ 1 eee eee 64 Typ Ipp wri VS fcpu HSE external clock Vpp 25V ow eee eee 64 Typ IDD WEN vs Vpp HSI RC osc fopy 16 MHZ os a LE RICE aa es 65 HSE external clock source 0 0 cee nee 66 HSE oscillator circuit diagram 0 0 eee 68 Typical HSI accuracy Vpp 5 V vs 5 temperatures 0 000 eee 69 Typical HSI frequency variation vs Vpp 4 temperatures aaaea 70 Typical LSI frequency variation vs Vpp 4 temperatures a 71 Typical Vj and Vi vs Vpp 4 temperatures 000 000 0002 000000 74 Typical pull up current vs Vpp 4 temperatures 0 0 ce ee 74 Typical pull up resistance vs VDD 4 temperatures 2 74 Typ Vol O Vpp 3 3 V standard ports 0 00022
30. consumption in halt mode at Vpp 2 33V 60 Wakeup times cec Rcs IGAN ae Raa AA hee Rp AKLATAN NN ga ae d E 61 Total current consumption and timing in forced reset state 61 Peripheral current consumption 000 e eee ee tenes 62 HSE user external clock characteristics llle 66 HSE oscillator characteristics e sidane iea 67 HSI oscillator characteristics lille 69 LSI oscillator characteristics lille 71 RAM and hardware registers 0 0 00 rn 72 Flash program memory data EEPROM memory 0000 eee eres 72 VO static characteristics illie eae 73 Output driving current standard ports cee eee 74 Output driving current true open drain ports 0 0 ee ee 75 Output driving current high sink ports l l 75 NRST pin characteristics a ei n a a E d a a A a a a a aE 78 SPI characteristics i Tikiu ka Eei ma rrr 80 I G characteristics AA 84 ADG characteristics a a NA e UR a ae 85 ADC accuracy with Rajns 10 KO Vppa 9M ee 86 ADC accuracy with Rajn lt 10 KO Vppa 33V 86 EMS ce m 88 EMidata TT n a ias y 89 DoclD14771 Rev 15 5 121 List of tables STM8S105x4 6 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 6 121 ESD absolute maximum ratings 0 0 0 cee eae Electrical sensitivities 0 0 lille LQFP48 48 pin 7 x 7
31. current 2 x Ipp 2C 12C supply current E Ipp apc1t ADC1 supply current when converting J55 1 Data based on a differential Ipp measurement between reset configuration and timer counter running at 16 MHz No IC OC programmed no I O pads toggling Not tested in production 2 Data based on a differential IDD measurement between the on chip peripheral when kept under reset and not clocked and the on chip peripheral when clocked and not kept under reset No I O pads toggling Not tested in production 3 Data based on a differential IDD measurement between reset configuration and continuous A D conversions Not tested in production Current consumption curves The following figures show typical current consumption measured with code executing in RAM Figure 13 Typ Ipp nuw VS Vpp HSE user external clock fcpy 16 MHz Irene m ra no A o il 2 DoclD14771 Rev 15 STM8S105x4 6 Electrical characteristics Figure 14 Typ Ipp nuw VS fcpu HSE user external clock Vpp 5 V loonunyse mA 10 15 20 fcpu MHz Figure 15 Typ Iporun VS Vpp HSI RC osc fcpy 16 MHz T 26 tt tt tt Z 25 24 23 22 21 2 2 5 3 8 5 4 4 5 5 55 6 Voo V 2 DoclD14771 Rev 15 63 121 Electrical characteristics STM8S105x4 6 Figure 16 Typ Ipp wen VS Vpp HSE external clock fcpy 16 MHz born ese mA 25 3 3 5 4 45 5 5 5 6 Vool
32. development cycle STice provides in circuit programming of the STM8 Flash microcontroller on the application board via the SWIM protocol Additional tools include a low cost in circuit programmer as well as ST socket boards which provide dedicated programming platforms with sockets for the STM8 programming For production environments programmers will include a complete range of gang and automated programming solutions from third party tool developers already supplying programmers for the STM8 family DoclD14771 Rev 15 115 121 Revision history STM8S105x4 6 15 116 121 Revision history Table 57 Document revision history Date 05 Jun 2018 Revision 1 Changes Initial release 23 Jun 2018 Corrected the number of high sink outputs to 9 in I Os in Features Updated part numbers in STM8S105xx access line features 12 Aug 2008 Updated the part numbers in STM8S105xx access line features USART renamed UART1 LINUART renamed UART2 Added Table Pin to pin comparison of pin 7 to 12 in 32 pin access line devices 17 Sep 2008 Removed STM8S102xx and STM8S104xx root part numbers corresponding to devices without data EEPROM Updated STM8S103 pinout section Added low and medium density Flash memory categories Added Note 1 in Section Current characteristics Updated Section Option bytes 05 Feb 2009 27 Feb 2009 DoclD14771 Rev 15 Updated STM8S103 pinout Updated n
33. input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for lj pm and 2lins einy in Section 10 3 6 does not affect the ADC accuracy Table 46 ADC accuracy with Rain lt 10 kQ VppA 3 3 V Symbol Parameter Conditions Typ Max fApc 2 MHz 1 1 2 0 Ex Total unadjusted error fADC 4 MHz 1 6 2 5 fApc 2 MHz 0 7 1 5 Eol Offset error fapc 4 MHz 1 3 2 0 fApc 2 MHz 0 2 1 5 Ecl Gain error fADC 4 MHz 0 5 2 0 fapc 2 MHz 0 7 1 0 Epl Differential linearity error fapc 4 MHz 0 7 1 0 fapc 2 MHz 0 6 1 5 EL Integral linearity error fADC 4MHz 0 6 1 5 Unit LSB 1 Data based on characterization results not tested in production DoclD14771 Rev 15 2 STM8S105x4 6 Electrical characteristics ADC accuracy vs negative injection current Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified f
34. on the product toggling 2 LEDs through the I O ports the product is monitored in terms of emission This emission test is in line with the norm IEC 61967 2 which specifies the board and the loading of each pin Table 48 EMI data Conditions 1 Symbol Parameter Max fuse fcpu Unit General conditions Monitored frequency band 8 MHz 8 MHz 8 MHz 16 MHz Vos Y 0 1 MHz to 30 MHz 13 14 Peak level Ta 25 C 30 MHz to 130 MHz 23 19 dBpV Sem LQFP48 package EMI level IEC 61967 2 EMI level 2 0 1 5 1 Data based on characterization results not tested in production Absolute maximum ratings electrical sensitivity Based on two different tests ESD DLU and LU using specific measurement methods the product is stressed to determine its performance in terms of electrical sensitivity For more details refer to the application note AN1181 Electrostatic discharge ESD Electrostatic discharges a positive then a negative pulse separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts x n 1 supply pin One model can be simulated Human body model This test conforms to the JESD22 A114A A115A standard For more details refer to the application note AN1181 Table 49 ESD absolute maximum ratings Maximum Symbol Ratings Conditions Class
35. the maximum time to validate the data 4 Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi Z 2 DoclD14771 Rev 15 81 121 Electrical characteristics STM8S105x4 6 Figure 41 SPI timing diagram where slave mode and CPHA 0 NSS input E 1 tSU NSS Iere te SCK th NSS tp I 1 3 CPHA 0 c CPOL 0 I 1 1 I 1 tw SCKH 14 Yi i i i 1 CPHA 0 y tw SCkKL T 1 T l D CPOL 1 i i r 1 I I l it tw so 150 24 ali tr SCK tdis SO Dama a SO T4 h ti SCK i MISO Ease MSB OUT BITS Our issouT 3 OUT OUTPUT ii MSBOUT tsu SI Pr t MOSI r INPUT io MSB IN BIT1 IN Y ism Y I lq thsi gt ai14134c 1 Measurement points are at CMOS levels 0 3 Vpp and 0 7 Vpp Figure 42 SPI timing diagram where slave mode and CPHA 1 NSS input I tSU NSS 4 gt r tc SCk th NSS HI 1 i i 5 CPHA 1 o pre j I E CPOL 0 megan i i T lt gt O CPHA 1 twscxty i i i i e CPOL 1 we aeu 2 i 1 1 i l 1 T so Pe o a UO uie tdis SO li ta S0 i sar MISO OUTPUT Mwsdour 1 OUT BITS OUT Bou OUT tsu SI y gt th Sl UM MOSI ai14135b 1 Measurement points are at CMOS levels 0 3 Vpp and 0 7 Vpp d 82 121 DoclD14771 Rev 15 STM8S105x4 6 Electrical characteristics Fig
36. 0 register 0x00 5325 TIM3_CCMR1 IA compare ede nang register 1 0x00 5326 TIM3_CCMR2 TIMY med Locos m register 2 0x00 5327 TIM3 CCER1 TIM3 capture compare enable 0x00 register 1 0x00 5328 TIM3 TIM3_CNTRH TIM3 counter high 0x00 0x00 5329 TIM3_CNTRL TIM3 counter low 0x00 0x00 532A TIM3_PSCR TIM3 prescaler register 0x00 0x00 532B TIM3_ARRH TIM3 auto reload register high OxFF 0x00 532C TIM3_ARRL TIM3 auto reload register low OxFF 0x00 532D TIM3_CCR1H TMS apr re compare 0x00 register 1 high 0x00 532E TIM3 CCR1L TINS API col pale 0x00 register 1 low 0x00 532F TIM3_CCR2H Nang capture compare reg 2 0x00 0x00 5330 TIM3_CCR2L TIME capt re compare 0x00 register 2 low 0x00 5331 to 0x00 533F Reserved area 15 byte 0x00 5340 TIM4 CR1 TIM4 control register 1 0x00 0x00 5341 TIMA IER TIM4 interrupt enable register 0x00 0x00 5342 TIM4_SR TIM4 status register 0x00 0x00 5343 TIM4 TIM4_EGR TIBIA oveni generalan 0x00 register 0x00 5344 TIM4 CNTR TIM4 counter 0x00 0x00 5345 TIM4_PSCR TIM4 prescaler register 0x00 0x00 5346 TIM4_ARR TIM4 auto reload register OxFF 0x00 5347 to 0x00 53DF Reserved area 153 byte 0x00 53E0 to 0x00 53F3 ADC1 ADC_DBxR ADC data buffer registers 0x00 2 STM8S105x4 6 Memory and register map Table 8 General hardware register map continued Address Block Register label Register name Reset status
37. 0 50C0 CLK_ICKR Internal clock control register 0x01 CLK 0x00 50C1 CLK_ECKR External clock control register 0x00 0x00 50C2 Reserved area 1 byte 34 121 DoclD14771 Rev 15 Ly STM8S105x4 6 Memory and register map Table 8 General hardware register map continued Address Block Register label Register name Reset status 0x00 50C3 CLK_CMSR Clock master status register OXE1 0x00 50C4 CLK_SWR Clock master switch register OxE1 0x00 50C5 CLK_SWCR Clock switch control register OxXX 0x00 50C6 CLK_CKDIVR Clock divider register 0x18 0x00 50C7 CLK PCKENR1 a clock gating OxFF 0x00 50C8 CLK CLK CSSR Clock security system register 0x00 0x00 50C9 CLK CCOR Ha ES SOGN COMDE odo 0x00 50CA CLK_PCKENR2 Una clock gating OxFF 0x00 50CC CLK_HSITRIMR En calibration trimming 0x00 0x00 50CD CLK_SWIMCCR SWIM clock control register ObXXXX XXX0 0x00 50CE to 0x00 50D0 Reserved area 3 byte 0x00 50D1 WWDG_CR WWDG control register Ox7F WWDG 0x00 50D2 WWDG WR WWDR window register Ox7F 0x00 50D3 to 00 50DF Reserved area 13 byte 0x00 50E0 IWDG_KR IWDG key register Oxxx 2 0x00 50E1 IWDG IWDG PR IWDG prescaler register 0x00 0x00 50E2 IWDG RLR IWDG reload register OxFF 0x00 50E3 to 0x00 50EF Reserved area 13 byte 0x00 50F0 AWU CSR1 AWU control status register 1 0x00 0x00 50F1 AUI AWU APR Mi
38. 0x00 5268 0x00 5269 Register label Register name Reset status TIM1_CR1 TIM1 control register 1 0x00 TIM1_CR2 TIM1 control register 2 0x00 TIM1 SMCR TIM1 slave mode control 0x00 a register TIM1_ETR TIM1 external trigger register 0x00 TIM1_IER TIM1 interrupt enable register 0x00 TIM1_SR1 TIM1 status register 1 0x00 TIM1_SR2 TIM1 status register 2 0x00 TIM1 EGR TIM1 event generation 0x00 register TIM1 CCMR1 TIM1 capture compare mode 0x00 register 1 TIM1 CCMR2 TIM1 capture compare mode 0x00 RS register 2 TIM1 CCMR3 TIM1 capture compare mode 0x00 x register 3 TIM1 CCMR4 TIM1 capture compare mode 0x00 register 4 TIM1 CCER1 TIM1 capture compare enable 0x00 B register 1 TIM4 CCER2 TIM1 capture compare enable 0x00 register 2 TIM1 CNTRH TIM1 counter high 0x00 TIM1 CNTRL TIM1 counter low 0x00 TIM1 PSCRH TIM1 prescaler register high Ox00 TIM1 PSCRL TIM1 prescaler register low 0x00 TIM1 ARRH TIM1 auto reload register high OxFF TIM1 ARRL TIM1 auto reload register low OxFF TIM1 RCR TIM1 repetition counter 0x00 register TIM1 CCR1H TIMT capture compare 0x00 register 1 high TIM1 CCRIL TIM1 capture compare 0x00 B register 1 low TIM1 CCR2H TIM1 capture compare 0x00 register 2 high TIM1 CCR2L TIM1 capture compare 0x00 E register 2 low TIM1_CCR3H TIM1 capture compare 0x00 register 3 high Ly DoclD14
39. 1 Unit value V Electrostatic discharge voltage Ta 25 C conforming to A 2000 ESD HBM Human body model JESD22 A114 V V Electrostatic discharge voltage Taz 25 C conforming to IV 1000 ESD CDM Charge device model SD22 C101 1 Data based on characterization results not tested in production DoclD14771 Rev 15 89 121 Electrical characteristics STM8S105x4 6 90 121 Static latch up Two complementary static tests are required on 10 parts to assess the latch up performance e A supply overvoltage applied to each power supply pin and e A current injection applied to each input output and configurable I O pin are performed on each sample This test conforms to the EIA JESD 78 IC latch up standard For more details refer to the application note AN1181 Table 50 Electrical sensitivities Symbol Parameter Conditions Class Ty 25 C LU Static latch up class Ta 85 C A Ta 125 C 1 Class description A Class is an STMicroelectronics internal specification All its limits are higher than the JEDEC specifications that means when a device belongs to class A it exceeds the JEDEC standard B class strictly covers all the JEDEC criteria international standard d DoclD14771 Rev 15 STM8S105x4 6 Package information 11 Package information In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their
40. 20 25 mcus VO X X X Hs 0o3 X X PortC3 hannel 3 2 PC4 Timer 1 29 21126 mr cna VO X X X Hs 03 X X Portca 30 27 22 27 PC5 SPISCK VO X X HS 03 X X PortC5 SPIclock F 31 26 2 VSSIO 2 S s a il Se eee I O ground E 32 29 VDDIO_2 S 1 O power supply SPI 33 30 23 28 PCe sPI MOSI vo X x X HS O3 X X Portce Master out slave in PC7 SPI SPI 34 31 24 29 miso YO X X X Hs 03 x x PortC7 masterin E slave out 35 132 PGO V O XIX 1 01 x x PotGO 36 33 PG1 V O XIX 01 x Xx PotG1 E 37 PEDE vo x x x 01 X X Pot E3 pe 17 gt TIMIBKIN 4 j input 38 34 PEZ12C SDA vo X x o1 HA PortE2 12C data 39 35 PE112C_scL vo X x ot d PortE1 12C clock 28 121 DocID14771 Rev 15 Ky STM8S105x4 6 Pinout and pin description Table 5 STM8S105x4 6 pin description continued Pin number Input Output e Alternate S P P satan Default nator 2 Qiog Sg Pinname Type 2 E els alternate Aa anui ng g g2 v S9 ai a after remap LiuLtLi2i iz o EIc 00 A function GIOIA a o E ali reset option st E u 3 bit L Lu O d Configura 40 36 PE0 CLK CCO I O X X X HS 03 X X Port EO ble clock output PDO NS 41 37 25 30 TIM3CH ig x x x Hs
41. 2010 Revision 10 Changes Table Legend Abbreviations for pinout tables updated reset state removed HS T and Section Pin description for STM8S105 microcontrollers added footnotes to the PF4 and PD1 pins Table I O port hardware register map changed reset status of Px_IDR from 0x00 to OxXX Table General hardware register map Standardized all address and reset state values updated the reset state values of the RST_SR CLK_SWCR CLK_HSITRIMR CLK_SWIMCCR IWDG_KR UART2_DR and ADC_DRx registers replaced reserved address 0x00 5248 with the UART2 CR5 Section Recommended reset pin protection replaced 0 01 uF with 0 1 uF Updated Figure Typical application with I2C bus and timing diagram Updated Table ADC accuracy with RAIN lt 10 kohm VDDA 5 V footnote 1 in and Table ADC accuracy with RAIN lt 10 kohm RAIN VDDA 3 3 V Section STM8S105 FASTROM microcontroller option list removed bits 6 and 7 from OPT1 user boot code area UBC added disable to 00h and enable to 55h of OPTBL bootloader option byte Section VFQFPN Package Mechanical data replaced note 1 and added note 2 04 Apr 2012 11 Removed VFQFPN32 package Modified Section Description Remove weak pull up input for PE1 and PE2 in Table Pin description for STM8S105 microcontrollers Updated Table Interrupt mapping for TIM2 and TIM4 Updated notes related to VCAP in xm replace_text General operating conditions Ad
42. 243 CAPCOM channels IC OC or PWM e 8 bit basic timer with 8 bit prescaler e Auto wake up timer e Window watchdog and independent watchdog timers Communication interfaces e UART with clock output for synchronous operation SmartCard IrDA LIN master mode e SPlinterface up to 8 Mbit s e 2C interface up to 400 kbit s Analog to digital converter ADC e 10 bit 1 LSB ADC with up to 10 multiplexed channels scan mode and analog watchdog I Os e Up to 38 I Os on a 48 pin package including 16 high sink outputs e Highly robust I O design immune against current injection Unique ID e 96 bit unique key for each device DoclD14771 Rev 15 1 121 This is information on a product in full production www st com Contents STM8S105x4 6 Contents 1 Introd ttion ue hip Sa AA 9 2 Description siii ei ica a Ra de i a 10 3 Block diagram 4 sana kaaa cee ees ad OEE c aca od oC Cee B eR eee So 12 4 Product overview a aide nian mtv Qr le AP a ia 13 4 1 Central processing unit STM8 0 00 ee eee eee 13 4 2 Single wire interface module SWIM and debug module DM 14 4 3 Interrupt controller 14 4 4 Flash program and data EEPROM memory 000 00 14 4 5 Clock controller 16 4 6 Power management AG 17 4 7 Watchdog timers us KABA MAAM dar ERU EROR kak oe Rou KAKA bad 17 4 8 Auto wakeup counter o 18 4 9 Beeper m LT 18 410 TIM1 16 bit advanced control timer llle 18
43. 2C_CCRL 12C Clock control register low 0x00 0x00 521C I2C_CCRH 12C Clock control register high 0x00 0x00 521D 12C_TRISER 12C TRISE register 0x02 0x00 521E I2C PECR a error checking 0x00 0x00 521F to 0x00 522F Reserved area 17 byte 0x00 5230 to 0x00 523F Reserved area 6 byte 0x00 5240 UART2_SR UART2 status register OxCO 0x00 5241 UART2_DR UART2 data register OxXX 0x00 5242 UART2 BRR1 UART2 baud rate register 1 0x00 0x00 5243 UART2 BRR2 UART2 baud rate register 2 0x00 0x00 5244 UART2 CR1 UART2 control register 1 0x00 0x00 5245 UART2 CR2 UART2 control register 2 0x00 0x00 5246 e UART2 CR3 UART2 control register 3 0x00 0x00 5247 UART2 CR4 UART2 control register 4 0x00 0x00 5248 UART2 CR5 UART2 control register 5 0x00 0x00 5249 UART2 CR6 UART2 control register 6 0x00 0x00 524A UART2 GTR UART2 guard time register 0x00 0x00 524B UART2 PSCR UART2 prescaler register 0x00 0x00 524C to 0x00 524F Reserved area 4 byte 36 121 DoclD14771 Rev 15 2 STM8S105x4 6 Memory and register map Table 8 General hardware register map continued Address 0x00 5250 Block 0x00 5251 0x00 5252 0x00 5253 0x00 5254 0x00 5255 0x00 5256 0x00 5257 0x00 5258 0x00 5259 0x00 525A 0x00 525B 0x00 525C TIM1 0x00 525D 0x00 525E 0x00 525F 0x00 5260 0x00 5261 0x00 5262 0x00 5263 0x00 5264 0x00 5265 0x00 5266 0x00 5267
44. 3 3 8 PR DSE VO X X 01 X X PortA1 r crystal OUT in 4 4 VSSIO_1 S 1 O ground 5 5 4 9 VSS S Digital ground 6 6 5 10 VCAP S i i i i 1 8 V regulator i capacitor 26 121 DoclD14771 Rev 15 Ly STM8S105x4 6 Pinout and pin description Table 5 STM8S105x4 6 pin description continued Pin number Input Output e Alternate z Main function a o Default x 9 Glo Pinname Type 2 Flecls function alternate 2 Aa A ILIA zz g g2 v S9 ai a after remap LiuLtLi2i iz o EIc 00 A function GIOIA a o E ali reset option 21219 m g t bit LL LU G l 7 7 6 11 VDD S Digital power supply 8 7 12 VDDIO_1 S 1 O power supply TIM3_ Bs ells ss AG vo XIX X 01 x x Port A3 Hila CH1 AFR1 10 9 PA4 vo x x X HS 03 x X Port A4 1141 10 PA5 vo x Hs 03 X X Port A5 12 347 8 la PAG vo XIX X HS OS x X Port A6 Analog 8 13 PFA AINI2 0 VO X X O1 X X PortFA input 120 13 12 9 14 VDDA S Analog power supply 14 13 10 15 VSSA S Analog ground 15 14 PB7 AIN7 vo x x x for x x Port7 Analog input 7 16 15 PB amp ANG vo x x x lolx x Potes mag input 6 17 16 11 16 aC SDA vo xX x
45. 3 121 Product overview STM8S105x4 6 4 2 4 3 4 4 14 121 Single wire interface module SWIM and debug module DM The single wire interface module and debug module permits non intrusive real time in circuit debugging and fast memory programming SWIM Single wire interface module for direct access to the debug module and memory programming The interface can be activated in all device operation modes The maximum data transmission speed is 145 bytes ms Debug module The non intrusive debugging module features a performance close to a full featured emulator Beside memory and peripherals also CPU operation can be monitored in real time by means of shadow registers e R W to RAM and peripheral registers in real time e R W access to all resources by stalling the CPU e Breakpoints on all program memory instructions software breakpoints e Two advanced breakpoints 23 predefined configurations Interrupt controller Nested interrupts with three software priority levels e 32 interrupt vectors with hardware priority Up to 37 external interrupts on 6 vectors including TLI e Trap and reset interrupts Flash program and data EEPROM memory e Up to 32 Kbyte of Flash program single voltage Flash memory Up to 1 Kbyte true data EEPROM e Read while write writing in data memory possible while executing code in program memory e User option byte area Write protection WP Write protection of Fla
46. 5x4 6 Memory and register map Table 7 1 O port hardware register map continued Address Block Register label Register name Reset status 0x00 5014 PE_ODR Port E data output latch register 0x00 0x00 5015 PE_IDR Port E input pin value register OxXX 0x00 5016 Port E PE DDR Port E data direction register 0x00 0x00 5017 PE_CR1 Port E control register 1 0x00 0x00 5018 PE_CR2 Port E control register 2 0x00 0x00 5019 PF_ODR Port F data output latch register 0x00 0x00 501A PF_IDR Port F input pin value register 0xxx 0x00 501B Port F PF DDR Port F data direction register 0x00 0x00 501C PF CR1 Port F control register 1 0x00 0x00 501D PF CR2 Port F control register 2 0x00 0x00 501E PG ODR Port G data output latch register 0x00 0x00 501F PG IDR Port G input pin value register 0xxx 0x00 5020 Port G PG DDR Port G data direction register 0x00 0x00 5021 PG CR1 Port G control register 1 0x00 0x00 5022 PG CR2 Port G control register 2 0x00 0x00 5023 PH ODR Port H data output latch register 0x00 0x00 5024 PH IDR Port H input pin value register 0xxx 0x00 5025 Port H PH DDR Port H data direction register 0x00 0x00 5026 PH CR1 Port H control register 1 0x00 0x00 5027 PH CR2 Port H control register 2 0x00 0x00 5028 PI ODR Port data output latch register 0x00 0x00 5029 PI IDR Port input pin value register Oxxx
47. 771 Rev 15 37 121 Memory and register map STM8S105x4 6 Table 8 General hardware register map continued Address 0x00 526A 0x00 526B 0x00 526C 0x00 526D 0x00 526E 0x00 526F Block TIM1 Register label Register name Reset status TIM1_CCR3L TIM1 capture compare 0x00 register 3 low TIM1 CCR4H IM capture compare 0x00 register 4 high TIM1 CCR4L TIM1 capture compare 0x00 B register 4 low TIM1 BKR TIM1 break register 0x00 TIM1 DTR TIM1 dead time register 0x00 TIM1 OISR TIM1 output idle state register 0x00 0x00 5270 to 0x00 52FF Reserved area 147 byte 38 121 DoclD14771 Rev 15 2 STM8S105x4 6 Memory and register map Table 8 General hardware register map continued Address Block Register label Register name Reset status 0x00 5300 TIM2_CR1 TIM2 control register 1 0x00 0x00 5301 TIM2_IER TIM2 Interrupt enable register 0x00 0x00 5302 TIM2_SR1 TIM2 status register 1 0x00 0x00 5303 TIM2_SR2 TIM2 status register 2 0x00 0x00 5304 TIM2_EGR TIME event generation 0x00 a register 0x00 5305 TIM2_CCMR1 TIM2 capture compare mode 0x00 register 1 0x00 5306 TIM2_CCMR2 TIME capture compare mode 0x00 register 2 0x00 5307 TIM2_CCMR3 TIME capture compare mode 0x00 register 3 0x00 5308 TIM2_CCER1 TIM2 capture
48. 9 0 1969 0 2008 E1 3 400 3 500 3 600 0 1339 0 1378 0 1417 E2 3 400 3 500 3 600 0 1339 0 1378 0 1417 e 0 500 0 0197 L 0 300 0 400 0 500 0 0118 0 0157 0 0197 ddd 0 080 0 0031 1 Values in inches are converted from mm and rounded to 4 decimal digits Figure 57 UFQFPN32 32 pin 5 x5 mm 0 5 mm pitch ultra thin fine pitch quad flat package recommended footprint 5 30 a 3 80 A0B8 FP V2 1 Dimensions are expressed in millimeters DoclD14771 Rev 15 d STM8S105x4 6 Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 58 UFQFPN32 marking example package top view Ah ASLOSKL Date code Standard ST logo LL LI uu Revision code MO Pin 1 identifier MS38331V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity 2 DoclD14771 Rev 15 103 121 Package information STM8S105x4 6 11 5 SDIP32 package information
49. D14771 Rev 15 STM8S105x4 6 Electrical characteristics 10 3 6 O port pin characteristics General characteristics Subject to general operating conditions for Vpp and T4 unless otherwise specified All unused pins must be kept at a fixed voltage using the output mode of the I O for example or an external pull up or pull down resistor Table 37 I O static characteristics Symbol Parameter Conditions Min Typ Max Unit ViL Input low level voltage 0 3 V E 0 3 x Vpp y Vin Input high level voltage Vpp 5 V 0 7 x Vpp Vpp 0 3 V Vhys Hysteresis 700 mV Rpu Pull up resistor Vpp 5 V Vin Vss 30 55 80 kQ Fast I Os 352 to t Rise and fall time Load 50 pF HE Ro IF 10 90 Standard and high sink I Os 1252 Load 50 pF Fast I Os E 7 20 2 to t Rise and fall time Load 20 pF Ro IF 10 90 Standard and high sink I Os f s02 Load 20 pF Digital input leakage likg Pi die j d Vss lt Vin Vpp s 116 pA Analog input leakage likg ana d p 9 Vss lt Vins Vpp 250 nA 7 Leakage current in HA 3 liko inj adjacent I O Injection current 4 mA 1 HA 1 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results 2 Data guaranteed by design 3 Data based on characterization results not tested in production 2 DoclD14771 Rev 15 not tested in production 73 121 Electrical charact
50. Electrical characteristics Figure 33 Typ Vpp Vou Vpp 3 3 V Figure 34 Typ Vpp Von O Vpp 5 0 V standard ports standard ports Voo Vou V lo mA Figure 35 Typ Vpp Von O Vpp 3 3 V high Figure 36 Typ Vpp Von Y Vpp 5 0 V high sink ports sink ports Voo Vou V Voo Vou V d DoclD14771 Rev 15 77 121 Electrical characteristics STM8S105x4 6 10 3 8 78 121 Reset pin characteristics Subject to general operating conditions for Vpp and Ta unless otherwise specified Table 41 NRST pin characteristics Symbol Conditions Min Typ Max Unit VIL NRST NRST input low level voltage 0 3 0 3 x Vpp Vinwrst NRST input high level voltage lo 52MA O07xVpp Vpp 0 3 V VOL NRST NRST output low level voltage lo 3 MA 0 5 Rpeynrst NRST pull up resistor 30 55 80 kQ tre nrsT NRST input filtered pulse 75 tinep vRst NRST Input not filtered pulse 500 ns top NRsT NRST output pulse 20 us 1 Data based on characterization results not tested in production 2 The Rpy pull up equivalent resistor is based on a resistive transistor 3 Data guaranteed by design not tested in production Figure 37 Typical NRST Vj and Vj Vs Vpp 4 temperatures Mus ay DoclD14771 Rev 15 2 STM8S105x4 6
51. Electrical characteristics Figure 38 Typical NRST pull up resistance Rpy vs Vpp 4 temperatures NRESET pull up esblarca ko VM Figure 39 Typical NRST pull up current lj vs Vpp O 4 temperatures NRESET Pull Lip current The reset network shown in Figure 40 protects the device against parasitic resets The user must ensure that the level on the NRST pin can go below Vi nrsT max see Table 41 NRST pin characteristics otherwise the reset is not taken into account internally For power consumption sensitive applications the external reset capacitor value can be reduced to limit the charge discharge current If NRST signal is used to reset external circuitry attention must be taken to the charge discharge time of the external capacitor to fulfill the external devices reset timing conditions Minimum recommended capacity is 100 nF 2 DoclD14771 Rev 15 79 121 Electrical characteristics STM8S105x4 6 10 3 9 80 121 Figure 40 Recommended reset pin protection Vas STM8 External reset NRST Upa Filter ins o gt circuit 0 1 uF Optional MSv36491V1 SPI serial peripheral interface Unless otherwise specified the parameters given in Table 42 are derived from tests performed under ambient temperature fyasTER frequency and Vpp supply voltage conditions tMASTER 1 fMASTER Refer to I O port characte
52. M8S105x4 6 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 8 121 recommended footprint 2 0 0 eee es 93 LQFP48 marking example package top view 000 eee eee eee 93 LQFP44 44 pin 10 x 10 mm low profile quad flat package outline 94 LQFP44 44 pin 10 x 10 mm low profile quad flat package recommended footprint 0c tees 96 LQFP44 marking example package top view liliis 97 LQFP32 32 pin 7 x 7 mm low profile quad flat package outline 98 LQFP32 32 pin 7 x 7 mm low profile quad flat package recommended footprint 0 00000 cts 100 LQFP32 marking example package top view 0 00 cece eee eee ee 100 UFQFPN32 32 pin 5x5 mm 0 5 mm pitch ultra thin fine pitch quad flat package outline 1 1 0 2 0 eee 101 UFQFPN32 32 pin 5 x5 mm 0 5 mm pitch ultra thin fine pitch quad flat package recommended footprint 0 000 cee 102 UFQFPN32 marking example package top view 00000 eee eee eaee 103 SDIP32 package outline 6 RI 104 SDIP32 marking example package top view eee eee eee 105 STM8S105x4 6 access line ordering information scheme ooo oo 108 2 DoclD14771 Rev 15 STM8S105x4 6 Introduction 1 Introduction This datasheet contains the description of the device fe
53. O3 X x Portpo 93 7 array TIM1 BKIN channel 2 CLK CCO CLK GU O AFR2 SWIM 42 38 26 31 PD1 Swim VO X X X X HS O4 X Port D1 data interface PD2 43 39 27 32 TIM3CH1 1 0 XIX X Hs o3 X X PortD2 n i PERE TIM2_CH3 PD3 44 40 28 1 TIM2CH2 vo X X X HS 03 X X PortD3 Rud lt AER ADC_ETR PD4 Timer 2 BEEP 45 41 29 2 TIM2 CH1 1 0 X X X HS 03 X X Port D4 chianmel 1 output BEEP AFR7 PD5 UART2 46 42 30 3 UART2 TX 1 0 X X X O1 X X PortD5 data transmit PD6 UART2 47 43 31 4 UART2 RX 1 0 X X X O1 X X Port D6 data receive PD7 TLI Top level TIM1_CH 48 44 32 5 TIM1_CH4 1 0 X X X O1 X X Port D7 interrupt 4 AFR4 1 A pull up is applied to PF4 during the reset phase This pin is input floating after reset release 2 AIN12 is not selectable in ADC scan mode or with analog watchdog 3 In 44 pin package AIN9 cannot be used by ADC scan mode 4 Inthe open drain output column T defines a true open drain I O P buffer weak pull up and protection diode to Vpp are not implemented 5 The PD1 pin is in input pull up during the reset phase and after internal reset release 2 DoclD14771 Rev 15 29 121 Pinout and pin description STM8S105x4 6 5 1 30 121 Alternate function remapping As shown in the rightmost column of the pin description table some alternate functions can be remapped at different I O por
54. PT5 HSECNT 7 0 Ox00 0x480A Startup NOPT5 NHSECNT 7 0 OxFF 0x480B OPT6 Reserved 0x00 Reserved Ox480C NOPT6 Reserved OxFF 0x480D OPT7 Reserved 0x00 Reserved 0x480E NOPT7 Reserved OxFF 0x480F Reserved Reserved 0x48FD Reserved 46 121 DocID14771 Rev 15 Ky STM8S105x4 6 Option byte Table 11 Option byte continued A Option Option bits Factory Addr d byte default no 7 6 5 4 3 2 1 0 setting 0x487E OPTBL BL 7 0 0x00 Bootloader 0x487F NOPTBL NBL 7 0 OxFF 2 Table 12 Option byte description Option byte no OPTO Description ROP 7 0 Memory readout protection ROP OxAA Enable readout protection write access via SWIM protocol Note Refer to the family reference manual RM0016 section on Flash EEPROM memory readout protection for details OPT1 UBC 7 0 User boot code area 0x00 no UBC no write protection 0x01 Page 0 to 1 defined as UBC memory write protected 0x02 Page 0 to 3 defined as UBC memory write protected 0x03 Page 0 to 4 defined as UBC memory write protected Ox3E Pages O to 63 defined as UBC memory write protected Other values Reserved Note Refer to the family reference manual RM0016 section on Flash write protection for more details OPT2 AFR 7 0 Refer to the following table for the description of the alternate function remapping description of bits 7 2 OPT3 HSITRIM High speed internal clock trimming regist
55. Ratings Max Unit lvpp Total current into Vpp power lines source 100 mA lyss Total current out of Vss ground lines sink 80 i Output current sunk by any I O and control pin 20 10 Output current source by any I Os and control pin 20 Total output current sourced sum of all I O and control pins 200 for devices with two Vppio pins Total output current sourced sum of all I O and control pins 3 100 zI for devices with one Vppjo pin 10 Total output current sunk sum of all I O and control pins for 160 devices with two Vssjo pins 9 Total output current sunk sum of all I O and control pins for p 3 80 devices with one Vggjg pin Injected current on NRST pin 4 lxi Injected current on OSCIN pin 4 Injected current on any other pin 9 4 linuem Total injected current sum of all I O and control pins 20 1 Data based on characterization results not tested in production 2 All power Vpp Vppio Vppa and ground Vss Vssio Vssa pins must always be connected to the external supply DoclD14771 Rev 15 53 121 Electrical characteristics STM8S105x4 6 3 I O pins used simultaneously for high current source sink must be uniformly spaced around the package between the VDDIO VSSIO pins 4 liny pin must never be exceeded This condition is implicitly insured if Vj maximum is respected If Vin maximum cannot be respected the injection current must be limited externally to the lj piv value A po
56. SE crystal osc 16 MHz 2 8 HSE user ext clock fcpu MASTER 16 MHz 16 MHz 2 6 3 2 Supply HSI RC osc 16 MHz 2 5 3 2 current in Run mode HSE user ext clock l y 1 6 2 2 mA DD RUN code fopu fuaster 128 125 kHz 16 MHz executed HSI RC osc 16 MHz 1 3 2 0 from RAM fopu fmasTER 128 15 625 kHz HSI RC osc 16 MHz 8 0 75 feru fmastER 128 kHz LSI RC osc 128 kHz 0 55 i HSE crystal osc 16 MHz 7 3 HSE user ext clock feru MASTER 16 MHz 16 MHz 7 0 8 0 Supply current in HSI RC osc 16 MHz 7 0 8 0 Een et mode fopu fuasrER 2 MHz HSI RC osc 16 MHz 8 2 1 5 mA code executed feru fuaster 128 125 kHz HSI RC osc 16 MHz 1 35 2 0 from Flash f m7 128 CPU MASTER HSI R 16 MHz 8 0 75 15 625 kHz kaaa a fcpu fMASTER 128 kHz LSI RC osc 128 kHz 0 6 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off Total current consumption in wait mode Table 22 Total current consumption in wait mode at Vpp 5 V Symbol Parameter Conditions Typ Max 1 Unit HSE crystal osc 16 MHz 2 15 HSE user ext clock feru fMASTER 16 MHz 16 MHz 1 55 2 0 Supply HSI RC osc 16 MHz 1 5 1 9 Ippwri current in mA wait mode fcru faster 128 125 kHz HSI RC osc 16 MHz 1 3 fopu fmasTER 5128 2 0 7 15 625 kHz HSI RC osc 16 MHz 8 fopu fuasrER 128 kHz LSI RC osc 128 kHz 0 5 3
57. STM8S products this option is checked by the boot ROM code after reset Depending on the content of addresses 0x487E 0x487F and 0x8000 reset vector the CPU jumps to the bootloader or to the reset vector Refer to the UM0560 STMBL S bootloader manual for more details For STM8L products the bootloader option bytes are on addresses OxXXXX and OxXXXX 1 2 byte These option bytes control whether the bootloader is active or not For more details refer to the UM0560 STM8L S bootloader manual for more details d DoclD14771 Rev 15 STM8S105x4 6 Option byte 8 1 2 Alternate function remapping bits Table 13 Alternate function remapping bits 7 0 of OPT2 Option byte no OPT2 Description AFR7 Alternate function remapping option 7 0 AFR7 remapping option inactive Default alternate functions 1 Port D4 alternate function BEEP AFR6 Alternate function remapping option 6 0 AFR6 remapping option inactive Default alternate function 2 1 Port B5 alternate function I2C_SDA port B4 alternate function I2C_SCL AFR5 Alternate function remapping option 5 0 AFR5 remapping option inactive Default alternate function 2 1 Port B3 alternate function TIM1_ETR port B2 alternate function TIM1_NCC3 port B1 alternate function TIM1_CH2N port BO alternate function TIM1 CH1N AFRA Alternate function remapping option 4 0 AFR4 remapping option inactive Default alternate functions
58. and tables of High speed internal RC oscillator HSI replaced Figure 23 Figure 24 Figure 26 and Figure 39 Section Package information updated Section Thermal characteristics and removed Table 57 Junction temperature range Updated Section STM8S105xx access line ordering information scheme Document status changed from preliminary data to datasheet 10 Jun 2009 8 Standardized the name of the VFQFPN package Removed wpu from I2C pins Section Pinout and pin description 2 DoclD14771 Rev 15 117 121 Revision history STM8S105x4 6 118 121 Table 57 Document revision history continued Date 21 Apr 2010 Revision DoclD14771 Rev 15 Changes Added UFQFPN32 package silhouette to the title page In Features added unique ID Section Clock controller updated bit positions for TIM2 and TIM3 Section Beeper added information about availability of the beeper output port through option bit AFR7 Section Analog to digital converter ADC1 added a note concerning additional AIN12 analog input Section STM8S105 pinouts and pin description added UFQFPN32 package details updated default alternate function of PB2 AIN2 TIM1_CH3N pin in the Pin description for STM8S105 microcontrollers table Section Option bytes added description of STM8L bootloader option bytes to the option byte description table Added Section Unique ID Section Operating conditions ad
59. ane 4MH2 bid BS tconv including sampling time 10 fanc 6 MHz 2 33 us bit resolution 14 Hang 1 Data guaranteed by design not tested in production 2 During the sample time the sampling capacitance Cay 3 pF max can be charged discharged by the external source The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tg After the end of the sample time ts changes of the analog input voltage have no effect on the conversion result Values for the sample clock tg depend on programming 2 DoclD14771 Rev 15 85 121 Electrical characteristics STM8S105x4 6 86 121 Table 45 ADC accuracy with Rajn lt 10 KO Vppa 5 V Symbol Parameter Conditions Typ Max fapc 2 MHz 1 0 2 5 Ex Total unadjusted error fApc 4 MHz 1 4 3 0 fanc 6 MHz 1 6 3 5 fapc 2 MHz 0 6 2 0 Eol Offset error fApc 4 MHz 1 1 2 5 fapc 6 MHz 1 2 2 5 fapc 2 MHz 0 2 2 0 IEcl Gain error fApc 4 MHz 0 6 2 5 fapc 6 MHz 0 8 2 5 fApc 2 MHz 0 7 1 5 Epl Differential linearity error fapc 4 MHz 0 7 1 5 fapc 6 MHz 0 8 1 5 fApc 2 MHz 0 6 1 5 JE Integral linearity error fapc 4 MHz 0 6 1 5 fApc 6 MHz 0 6 1 5 1 Data based on characterization results not tested in production Unit LSB 2 ADC accuracy vs negative injection current Injecting negative current on any of the analog
60. atures pinout electrical characteristics mechanical data and ordering information e For complete information on the STM8S microcontroller memory registers and peripherals please refer to the STM8S microcontroller family reference manual RM0016 e For information on programming erasing and protection of the internal Flash memory please refer to the STM8S Flash programming manual PM0051 e For information on the debug and SWIM single wire interface module refer to the STM8 SWIM communication protocol and debug module user manual UM0470 e For information on the STM6 core please refer to the STM8 CPU programming manual PM0044 2 DoclD14771 Rev 15 9 121 Description STM8S105x4 6 2 Description The STM8S105x4 6 access line 8 bit microcontrollers offer from 16 to 32 Kbyte Flash program memory plus integrated true data EEPROM The STM8S microcontroller family reference manual RM0016 refers to devices in this family as medium density All devices of the STM8S105x4 6 access line provide the following benefits reduced system cost performance and robustness short development cycles and product longevity The system cost is reduced thanks to an integrated true data EEPROM for up to 300 k write erase cycles and a high system integration level with internal clock oscillators watchdog and brown out reset Device performance is ensured by a 16 MHz CPU clock frequency and enhanced characteristics which include robust I O
61. be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity DoclD14771 Rev 15 Ly STM8S105x4 6 Package information 11 4 UFQFPN32 package information Figure 56 UFQFPN32 32 pin 5x5 mm 0 5 mm pitch ultra thin fine pitch quad flat package outline y A y k4 I Al ddd c Pg A1 E A2 SEATING PLANE E2 PIN 1 Identifier A0B8 ME V2 Drawing is not to scale All leads pads should be soldered to the PCB to improve the lead pad solder joint life There is an exposed die pad on the underside of the UFQFPN package It is recommended to connect and solder this backside pad to PCB ground 4 Dimensions are in millimeters 2 DoclD14771 Rev 15 101 121 Package information STM8S105x4 6 102 121 Table 54 UFQFPN32 32 pin 5x5 mm 0 5 mm pitch ultra thin fine pitch quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 0 500 0 550 0 600 0 0197 0 0217 0 0236 A1 0 000 0 020 0 050 0 0000 0 0008 0 0020 A3 0 152 0 0060 0 180 0 230 0 280 0 0071 0 0091 0 0110 D 4 900 5 000 5 100 0 1929 0 1969 0 2008 D1 3 400 3 500 3 600 0 1339 0 1378 0 1417 D2 3 400 3 500 3 600 0 1339 0 1378 0 1417 E 4 900 5 000 5 100 0 192
62. be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time Refer to the crystal resonator manufacturer for more details frequency package accuracy Table 32 HSE oscillator characteristics 1 Cis approximately equivalent to 2 x crystal Cload 2 The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value Refer to crystal manufacturer for more details Data based on characterization results not tested in production tsu Hse is the start up time measured from the moment it is enabled by software to a stabilized 16 MHz oscillation is Symbol Parameter Conditions Min Typ Max Unit External high speed fuse oscillator frequency E 7 1 MHz Rp Feedback resistor 220 kQ c t O load E 20 pF capacitance C 20 pF 6 start up HSE oscillator power fosc 16 MHz 1 6 stabilized 9 Ipp HsE mA consumption C 10 pF 6 start up fosc 16 MHz 1 2 stabilized 9 Oscillator 9m transconductance O O O Lid tsu HsE Startup time Vpp is stabilized 1 ms reached This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer 2 DoclD14771 Rev 15 67 121 Electrical characteristics STM8S105x4 6 Figure 20 HSE oscillator circuit diagram
63. compare enable ba 260 register 1 0x00 5309 TIM2_CCER2 TIM2 capture compare enable 0x00 register 2 0x00 530A TIM2_CNTRH TIM2 counter high 0x00 0x00 530B TIM2 TIM2_CNTRL TIM2 counter low 0x00 0x00 530C TIM2_PSCR IM2 prescaler register 0x00 0x00 530D TIM2_ARRH TIM2 auto reload register high OxFF 0x00 530E TIM2_ARRL TIM2 auto reload register low OxFF 0x00 530F TIM2_CCR1H NE capturercompare 0x00 register 1 high 0x00 5310 TIM2 CCR1L TIMA capt re compare 0x00 register 1 low 0x00 5311 TIM2_CCR2H ae capture compare reg 2 0x00 0x00 5312 TIM2_CCR2L TIME capture compar 0x00 ES register 2 low 0x00 5313 TIM2_CCR3H TIM2 capile sompsie 0x00 register 3 high 0x00 5314 TIM2_CCR3L NE compara 0x00 B register 3 low 0x00 5315 to 0x00 531F Reserved area 11 byte 2 DoclD14771 Rev 15 39 121 Memory and register map STM8S105x4 6 Table 8 General hardware register map continued 0x00 53F4 to 0x00 53FF 40 121 Reserved are a 12 byte DoclD14771 Rev 15 Address Block Register label Register name Reset status 0x00 5320 TIM3 CR1 TIM3 control register 1 0x00 0x00 5321 TIM3 IER TIM3 Interrupt enable register 0x00 0x00 5322 TIM3_SR1 TIM3 status register 1 0x00 0x00 5323 TIM3_SR2 TIM3 status register 2 0x00 0x00 5324 TIM3_EGR TE eden ae 0x0
64. cters max and k Temperature range 40 C to 85 C or 40 C to 125 C DoclD14771 Rev 15 109 121 Ordering information STM8S105x4 6 110 121 Padding value for unused program memory check only one option OxFF Fixed value 0x83 TRAP instruction code 0x75 Illegal opcode causes a reset when executed OTPO memory readout protection check only one option Disable or Enable OTP1 user boot code area UBC Ox _ fill in the hexadecimal value referring to the datasheet and the binary format below UBC bitO 0 Reset 1 Set UBC bit1 0 Reset 1 Set UBC bit2 0 Reset 1 Set i 0 Reset UBC bit ak 1 Set UBC bit4 0 Reset 1 Set UBC bit5 0 Reset 1 Set OTP2 alternate function remapping AFRO check only one option 0 Remapping option inactive Default alternate functions used Refer to pinout description 1 Port D3 alternate function ADC_ETR AFR1 check only one option 0 Remapping option inactive Default alternate functions used Refer to pinout description 1 Port A3 alternate function TIM3 CH1 port D2 alternate function TIM2_CH3 AFR2 check only one option 0 Remapping option inactive Default alternate functions used Refer to pinout description 1 Port DO alternate function CLK_CCO Note if both AFR2 and AFR3 are acti
65. ded introductory text removed low power dissipation condition for TA replaced CEXT by VCAP and added ESR and ESL data in table general operating conditions Section Total current consumption in halt mode replaced max value of IDD H at 85 C from 20 pA to 25 pA for the condition Flash in powerdown mode HSI clock after wakeup in the table total current consumption in halt mode at VDD 5 V Section Low power mode wakeup times added first condition 0 to 16 MHz for the tyy wri parameter in the table wakeup times Section Internal clock sources and timing characteristics In the table HSI oscillator characteristics replaced min and max values of ACCHSI factory calibrated parameter and removed footnote 4 concerning further characterization of results Section Functional EMS electromagnetic susceptibility IEC 1000 replaced with IEC 61000 Section Designing hardened software to avoid noise problems IEC 1000 replaced with IEC 61000 Section Electromagnetic interference EMI SAE J 1752 3 replaced with IEC61967 2 Section Thermal characteristics Replaced the thermal resistance junction ambient temperature of LQFP32 7X7 mm from 59 C to 60 C in the thermal characteristics table Added Section 32 lead UFQFPN package mechanical data Added Section STM8S105 FASTROM microcontroller option list d STM8S105x4 6 Revision history Table 57 Document revision history continued Date 21 Sep
66. ded the footnotes related to Figure 56 UFQFPNS2 32 pin 5x5 mm 0 5 mm pitch ultra thin fine pitch quad flat package outline DoclD14771 Rev 15 d STM8S105x4 6 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections enhancements modifications and improvements to ST products and or to this document at any time without notice Purchasers should obtain the latest relevant information on ST products before placing orders ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement Purchasers are solely responsible for the choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right is granted by ST herein Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product ST and the ST logo are trademarks of ST All other product or service names are the property of their respective owners Information in this document supersedes and replaces information previously supplied in any prior versions of this document 2015 STMicroelectronics All rights reserved 2 DoclD14771 Rev 15 121 121 Mouser Electronics Authorized Distributor Click to View Pricing
67. ded values of tp tp for 50 pF load capacitance and updated note in Section I O static characteristics Updated typical and maximum values of RPU in Table VO static characteristics and Table RST pin characteristics Changed SCK input to SCK output in Table SPI serial peripheral interface Added for UFQFPN32 and SDIP32 in Table Thermal characteristics and updated Section Selecting the product temperature range 28 Jun 2012 12 Added UFQFPN package thickness in Figure STM8S105xx access line ordering information scheme 2 DoclD14771 Rev 15 119 121 Revision history STM8S105x4 6 120 121 Table 57 Document revision history continued Date 07 Feb 2014 Revision 13 Changes UART2_CK mapped to correct pin pin 24 in Figure LQFP 44 pin pinout Reserved area updated in Table Option bytes Package Information updated in Table 32 lead ultra thin fine pitch quad flat no lead package mechanical data 01 Jul 2015 23 Sep 2015 14 15 Added Figure 49 LQFP48 marking example package top view Figure 52 LQFP44 marking example package top view Figure 55 LQFP32 marking example package top view Figure 58 UFQFPN32 marking example package top view Figure 60 SDIP32 marking example package top view Updated Figure 41 SPI timing diagram where slave mode and CPHA 0 the standard for EMI data in Table 48 EMI data Ad
68. default state after reset Output speed float floating Input wpu weak pull up Port and control configuration T True open drain Output OD Open drain PP Push pull Bold X pin state after internal reset release Reset state Unless otherwise specified the pin state is the same during the reset phase and after the internal reset release 2 22 121 DoclD14771 Rev 15 STM8S105x4 6 Pinout and pin description Figure 3 LQFP48 pinout o o 9 x e i 9 yo z L x E m 5 d a N Hgs axe E Y rg9r 290 S 550 09 4 TES iaa JOoOZ Ss O SSSES NAS Z aa 22325 Mm EFEEEEQE OGG I Sere RR RARANN ES 2 0000002cLcxrz E23 23ETLITLTEEE NGDTFTONTO Or N o qgqqgqaqgaqgqaqgaoqgqoagaww Ww Ww DOON OO OO DN O O O O 000000 48 47 46 45 44 43 42 41 40 39 38 37 NRST 1 e 36 PG1 OSCIN PA1 O2 35 PGO OSCOUT PA2 O3 34 JPC7 HS SPI_MISO VSSIO 1 4 33 JPC6 HS SPI_MOSI vss U5 32 HIVDDIO_2 VCAP U6 31 FIVSSIO_2 vpp L7 30 JPC5 HS SPI SCK VDDIO 1 8 29 PC4 HS TIM1_CH4 TIM3 CH1 TIM2 CH3 PA3 O9 28 PC3 HS TIM1_CH3 HS PA4 O10 27 PC2 HS TIM1_CH2 Hs Pas On 26 1PC1 HS TIM1_CH1 UART2_CK HS pas H12 25 LIPE5S SPI NSS 13 14 15 16 17 18 19 20 21 22 23 24 DUN NU X X Oase ON TO NG egeeepeeceeea gt gt DFAS IDA 2222222222 TITA Ce ZIXZZZ Sour Dj d 999 Q Sec SEE5S5S EEE MS38305V1 HS high sink ca
69. document ce cece cette eens 106 12 2 Selecting the product temperature range 107 13 Ordering information ii ea ee ew e eee a a CR RC 108 13 1 STM8S105 FASTROM microcontroller option list 109 14 STM8 development tools esseleeeses 113 14 1 Emulation and in circuit debugging tools ocoo o oooo 113 14 1 4 STice key features 00 00 eee ee 113 142 Software toolS 0 0 tenes 114 14 2 4 STMB8 toolset 0 02020 ee 114 14 2 2 C and assembly toolchains 0c e eee eee 114 14 3 Programming tools e aed nadal BAG aa dos NG ta da and 115 15 Revision history sir Wk ewe AR Rc e 116 4 121 DoclD14771 Rev 15 Ly STM8S105x4 6 List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Ly STM8S105x4 6 access line features 0 0 0 eee 11 Peripheral clock gating bit assignments in CLK_PCKENR1 2 registers 16 TIM timer featu
70. er size 0 3 bit trimming supported in CLK_HSITRIMR register 1 4 bit trimming supported in CLK_HSITRIMR register LSI_EN Low speed internal clock enable 0 LSI clock is not available as CPU clock source 1 LSI clock is available as CPU clock source IWDG_HW Independent watchdog 0 IWDG Independent watchdog activated by software 1 IWDG Independent watchdog activated by hardware WWDG_HW Window watchdog activation 0 WWDG window watchdog activated by software 1 WWDG window watchdog activated by hardware WWDG HALT Window watchdog reset on halt 0 No reset generated on halt if WWDG active 1 Reset generated on halt if WWDG active DoclD14771 Rev 15 47 121 Option byte STM8S105x4 6 48 121 Table 12 Option byte description continued Option byte no OPT4 Description EXTCLK External clock selection 0 External crystal connected to OSCIN OSCOUT 1 External clock signal on OSCIN CKAWUSEL Auto wake up unit clock 0 LSI clock source selected for AWU 1 HSE clock with prescaler selected as clock source for AWU PRSC 1 0 AWU clock prescaler Ox 16 MHz to 128 kHz prescaler 10 8 MHz to 128 kHz prescaler 11 4 MHz to 128 kHz prescaler OPT5 HSECNT 7 0 HSE crystal oscillator stabilization time 0x00 2048 HSE cycles OxB4 128 HSE cycles OxD2 8 HSE cycles OxE1 0 5 HSE cycles OPT6 OPT7 Reserved Reserved OPTBL BL 7 0 Bootloader option byte For
71. eristics STM8S105x4 6 Figure 24 Typical Vj and Vy vs Vpp O 4 temperatures VIL VIH V Figure 25 Typical pull up current vs Vpp 4 temperatures Pul up current pa 74 121 Figure 26 Typical pull up resistance vs VDD 4 temperatures 40 25 C 60 85C 55 50 5 A 125 C Pull up resistance O W 4 4 5 VDD V MS37434V1 Table 38 Output driving current standard ports 1 Symbol Parameter Conditions Min Max Unit Output low level with 8 lio 10 mA i T7 pins sunk Vpp 25V i VoL Output low level with 4 lo 4 mA 4 00 pins sunk Vpp 3 3 V S y Output high level with 8 lio 10 mA Ha i pins sourced Vpp 25V VoH Output high level with 4 llio 4 mA 2 00 i pins sourced Vpp 3 3 V l Data based on characterization results not tested in production DoclD14771 Rev 15 2 STM8S105x4 6 Electrical characteristics Table 39 Output driving current true open drain ports Symbol Parameter Conditions Min Max Unit Output low level with 2 lio 10 mA NAG pins sunk Vpp 25V j VoL Output low level with 2 lo 10 mA g 4 500 V pins sunk Vpp 3 3 V Output high level with 2 lio 10 mA 1 VoH 2 0 pins sourced Vop 5V 1 Data based on characterization results not tested in production Table 40 Output driving curre
72. ernally connected to TIM1 input capture channel 1 for calibration Beeper The beeper function outputs a signal on the BEEP pin for sound generation The signal is in the range of 1 2 or 4 kHz The beeper output port is only available through the alternate function remap option bit AFR7 TIM1 16 bit advanced control timer This is a high end timer designed for a wide range of control applications With its complementary outputs dead time control and center aligned PWM capability the field of applications is extended to motor control lighting and half bridge driver e 16 bit up down and up down autoreload counter with 16 bit prescaler e Four independent capture compare channels CAPCOM configurable as input capture output compare PWM generation edge and center aligned mode and single pulse mode output e Synchronization module to control the timer with external signals e Break input to force the timer outputs into a defined state e Three complementary outputs with adjustable dead time e Encoder mode e Interrupt sources 3 x input capture output compare 1 x overflow update 1 x break TIM2 TIM3 16 bit general purpose timers e 16 bit auto reload AR up counter e 15 bit prescaler adjustable to fixed power of 2 ratios 1 32768 e Timers with 3 or 2 individually configurable capture compare channels e PWM mode e Interrupt sources 2 or 3 x input capture output compare 1 x overflow update 2 DoclD14771 Rev 15
73. evelopment environment and STVP programming software is available for free download at www st com This package includes ST visual develop Full featured integrated development environment from STMicroelectronics featuring e Seamless integration of C and ASM toolsets e Full featured debugger e Project management e Syntax highlighting editor e Integrated programming interface e Support of advanced emulation features for STice such as code profiling and coverage ST visual programmer STVP Easy to use unlimited graphical interface allowing read write and verification of the STM8 Flash program memory data EEPROM and option bytes STVP also offers project mode for the saving of programming configurations and the automation of programming sequences C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment making it possible to configure and control the building of user applications directly from an easy to use graphical interface Available toolchains include C compiler for STM8 Available in a free version that outputs up to 16 Kbytes of code For more information see www cosmic software com STM8 assembler linker Free assembly toolchain included in the STVD toolset used to assemble and link the user application source code 2 DoclD14771 Rev 15 STM8S105x4 6 STM8 development tools 14 3 2 Programming tools During the
74. ew clock source is ready The design guarantees glitch free switching e Clock management to reduce power consumption the clock controller can stop the clock to the core individual peripherals or memory e Master clock sources four different clock sources can be used to drive the master clock 1 16 MHz high speed external crystal HSE Up to 16 MHz high speed user external clock HSE user ext 16 MHz high speed internal RC oscillator HSI 128 kHz low speed internal RC LSI e Startup clock After reset the microcontroller restarts by default with an internal 2 MHz clock HSI 8 The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts e Clock security system CSS This feature can be enabled by software If an HSE clock failure occurs the internal RC 16 MHz 8 is automatically selected by the CSS and an interrupt can optionally be generated e Configurable main clock output CCO This outputs an external clock for use by the application Table 2 Peripheral clock gating bit assignments in CLK_PCKENR1 2 registers Peripheral Peripheral 3 Peripheral Peripheral EM clock all clock Bil clock E clock PCKEN17 TIM1 PCKEN13 UART2 PCKEN27 Reserved PCKEN23 ADC PCKEN16 TIM3 PCKEN12 Reserved PCKEN26 Reserved PCKEN22 AWU PCKEN15 TIM2 PCKEN11 SPI PCKEN25 Reserved PCKEN21 Reserved PCKEN14 TIM4 PCKEN10 12C PCKEN24 Reserved PCKEN20 Reserved
75. further information on any aspect of this device please go to www st com or contact the nearest ST Sales Office 108 121 DoclD14771 Rev 15 Ly STM8S105x4 6 Ordering information 13 1 Note STM8S105 FASTROM microcontroller option list last update September 2010 Customer Address Wesaebbteectscsceececeausdbsetoinciaasessucentysfadesiancteanemtsaveaiiviieneee Contact qj o oeenn aieeaa aaeoa s ere E Eaa ASSO TESA Es Phone number FASTROM code reference 1 The FASTROM code name is assigned by STMicroelectronics The preferable format for programing code is Hex s19 is accepted If data EEPROM programing is required a separate file must be sent with the requested data See the option byte section in the datasheet for authorized option byte combinations and a detailed explanation Device type memory size package check only one option FASTROM device 16 Kbyte 32 Kbyte LQFP32 STM8S105K4 STM8S105K6 LQFP44 STM8S105S4 STM8S105S6 LQFP48 STM8S105C4 STM8S105C6 2 Conditioning check only one option Tape and reel or Tray Special marking check only one option No Yes Authorized characters are letters digits and spaces only Maximum character counts are LQFP32 2 lines of 7 characters max and LQFP44 2 lines of 7 characters max and LQFP48 2 lines of 8 chara
76. g this unique ID with software cryptographic primitives and protocols before programming the internal memory e To activate secure boot processes Table 14 Unique ID registers 96 bits Address fies Unique ID bits meets ala 2 1 0 0x48CD X co ordinate on U_ID 7 0 0x48CE the wafer U ID 15 8 Ox48CF Y co ordinate on U ID 23 16 0x48D0 the wafer U ID 31 24 0x48D1 Wafer number U ID 39 32 0x48D2 U ID 47 40 0x48D3 U ID 55 48 Ox48D4 U ID 63 56 Ox48D5 Lot number U ID 71 64 0x48D6 U_ID 79 72 0x48D7 U_ID 87 80 0x48D8 U_ID 95 88 d DoclD14771 Rev 15 STM8S105x4 6 Electrical characteristics 10 10 1 10 1 1 10 1 2 10 1 3 10 1 4 2 Electrical characteristics Parameter conditions Unless otherwise specified all voltages are referred to Vss Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at T4 25 C and Ta Tamax given by the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Based on characterization the minimum and maximum values refer to sample tests and represent the mean value plus or minus th
77. h usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity DoclD14771 Rev 15 105 121 Thermal characteristics STM8S105x4 6 12 12 1 106 121 Thermal characteristics The maximum junction temperature T max of the device must never exceed the values specified in Table 18 General operating conditions otherwise the functionality of the device cannot be guaranteed The maximum junction temperature T jmax in degrees Celsius may be calculated using the following equation TJmax Tamax PDmax X Oya Where e Tamax is the maximum ambient temperature in C e OjyAis the package junction to ambient thermal resistance in C W e Ppmax is the sum of Pintmax and Pijomax PDmax Pintmax Promax e PinTmax S the product of Ipp and Vpp expressed in Watts This is the maximum chip internal power e Pyomax represents the maximum power dissipation on output pins Where Promax VoL loL Vpp Vou lon taking into account the actual Ve lo and Voy loy of the I Os at low and high level in the application Table 56 Thermal characteristics Symbol Parameter Value Unit Thermal resistance junction ambient LQFP48 7x7 mm Thermal resistance junction ambient LQFP44 10x10 mm Thermal resistance juncti
78. hdog timers is controlled by option bytes or by software Once activated the watchdogs cannot be disabled by the user program without performing a reset Window watchdog timer The window watchdog is used to detect the occurrence of a software fault usually generated by external interferences or by unexpected logical conditions which cause the application program to abandon its normal sequence The window function can be used to trim the watchdog behavior to match the application perfectly The application software must refresh the counter before time out and during a limited time window A reset is generated in two situations 1 Timeout At 16 MHz CPU clock the time out period can be adjusted between 75 us up to 64 ms 2 Refresh out of window The downcounter is refreshed before its value is lower than the one stored in the window register Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures It is clocked by the 128 kHz LSI internal RC clock source and thus stays active even in case of a CPU clock failure DoclD14771 Rev 15 17 121 Product overview STM8S105x4 6 4 8 4 9 4 10 4 11 18 121 The IWDG time base spans from 60 us to 1 s Auto wakeup counter e Used for auto wakeup from active halt mode Clock source Internal 128 kHz internal low frequency RC oscillator or external clock e LSI clock can be int
79. ing capacitor n 52 10 4 6 Pin input voltage RII 52 10 2 Absolute maximum ratings lille 53 10 3 Operating conditions esaet es acea qan Re gone KAY FA dace es 54 10 3 4 VCAP external capacitor llle 57 10 3 2 Supply current characteristics 20000 e eee eee 57 10 3 3 External clock sources and timing characteristics 66 10 3 4 Internal clock sources and timing characteristics 69 10 3 5 Memory characteristics ee 72 10 3 6 I O port pin characteristics 000 cc eee eee 73 10 3 7 Typical output level curves 0 00000 eee eee eee 75 10 3 8 Reset pin characteristics 0202 eee 78 10 3 9 SPI serial peripheral interface 0c eee eee 80 10 3 10 C interface characteristics oss Naan KAN NGA KANA vr pud KG WG 84 10 3 11 10 bit ADC characteristics llle 85 10 3 12 EMC characteristics lille 88 Package information 0c cece eee eee 91 11 1 LQFP48 package information 00 0 c eee eee 91 11 2 LQFP44 package information 0 00 0 cee eee 94 11 9 LQFP3Z package information cad re E bee KWAN NG KAKA EE RR RES 98 114 UFQFPN32 package information 0 0 00 ee eee 101 DoclD14771 Rev 15 3 121 Contents STM8S105x4 6 11 5 SDIP32 package information 0 0000 104 12 Thermal characteristics eee eee 106 12 1 Reference
80. ization Data Data memory area 1Kbyte EEPROM memory Option bytes Programmable area UBC area from 1 Kbyte Remains write protected during IAP 2 first pages up to 32 Kbyte 1 page step Medium density Flash program memory up to 32 Kbyte Program memory area Write access possible for IAP MSv38304V1 Read out protection ROP The read out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode and debug mode Once the read out protection is activated any attempt to toggle its status triggers a global erase of the program and data memory Even if no protection can be considered as totally unbreakable the feature provides a very high level of protection for a general purpose microcontroller 2 DoclD14771 Rev 15 15 121 Product overview STM8S105x4 6 4 5 Clock controller The clock controller distributes the system clock fMASTER coming from different oscillators to the core and the peripherals It also manages clock gating for low power modes and ensures clock robustness Features e Clock prescaler to get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler e Safe clock switching clock sources can be changed safely on the fly in run mode through a configuration register The clock signal is not switched until the n
81. l RM0016 Central processing unit STM8 The 8 bit STM8 core is designed for code efficiency and performance It contains 6 internal registers which are directly addressable in each execution context 20 addressing modes including indexed indirect and relative addressing and 80 instructions Architecture and registers e Harvard architecture e 3 stage pipeline e 32 bit wide program memory bus single cycle fetching for most instructions e Xand Y 16 bit index registers enabling indexed addressing modes with or without offset and read modify write type data manipulations e 8 bit accumulator e 24 bit program counter 16 Mbyte linear memory space e 16 bit stack pointer access to a 64 K level stack e 8 bit condition code register 7 condition flags for the result of the last instruction Addressing e 20addressing modes e Indexed indirect addressing mode for look up tables located anywhere in the address space e Stack pointer relative addressing mode for local variables and parameter passing Instruction set e 80 instructions with 2 byte average instruction size e Standard data movement and logic arithmetic functions e 8 bit by 8 bit multiplication e 16 bit by 8 bit and 16 bit by 16 bit division e Bit manipulation e Data transfer between stack and accumulator push pop with direct stack access e Data transfer using the X and Y registers or direct memory to memory transfers DoclD14771 Rev 15 1
82. level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark 11 1 LQFP48 package information Figure 47 LQFP48 48 pin 7 x 7 mm low profile quad flat package outline SEATING PLANE sm cl GAUGE PLANE y K 5B_ME_V2 1 Drawing is not to scale Ly DoclD14771 Rev 15 91 121 Package information STM8S105x4 6 Table 51 LQFP48 48 pin 7 x 7 mm low profile quad flat package mechanical data 92 121 millimeters inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 500 0 2165 E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 500 0 2165 e 0 500 0 0197 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 3 5 T 0 3 5 7 ccc 0 080 0 0031 1 Values in inches are converted from mm and rounded to 4 decimal digits DoclD14771 Rev 15 2 STM8S105x4 6 Package information 2 Figure 48 LQFP48 48 pin 7 x 7 mm low profile quad flat package recommended foo
83. lock diagram Reset block XTAL 1 16 MHz Clock controller Reset Reset RCint 16 MHz Detector POR BOR RCint 128 kHz Clock to peripherals and core L T Window STM8 WDG core Independent WDG Single wire it Debug SWIM Up to 32 Kbyte debug interf Program Flash 1 Kbyte da data EEPROM E 400 Kbit s 12C S gt s Up to 2 Kbyte o RAM o c o 8Mbit s lt SPI 8 Boot ROM o 2 Up to 4 CAPCOM Master slave 16 bit advanced ma channels 3 autosynchro UART2 lt gt control timer TM1 complementary LIN master outputs SPI emul 16 bit general purpose Up to 5 CAPCOM timer TIM2 TIM3 channels Up to 10 8 bit basic timer p to TIM4 channels gt ADC1 1 2 4 kHz Beeper AWU timer beep MSv38303V1 12 121 DoclD14771 Rev 15 ky STM8S105x4 6 Product overview 4 4 1 2 Product overview The following section provides an overview of the basic features of the device functional modules and peripherals For more detailed information please refer to the corresponding family reference manua
84. mm low profile quad flat package mechanical data 2 oc aa a ba ee a Ex a ee RC LQFP44 44 pin 10 x 10 mm low profile quad flat package mechanical data uta ii ates each aoe BO a a Raa E RO c E noe RE ap ae RC LQFP32 32 pin 7 x 7 mm low profile quad flat package mechanical data a UFQFPN32 32 pin 5x5 mm 0 5 mm pitch ultra thin fine pitch quad flat package mechanical data 00 0000 eee eee SDIP32 package mechanical data 0c eee eee Thermal characteristics 00000 cect eee Document revision history 0 0000 ee DoclD14771 Rev 15 2 STM8S105x4 6 List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Ly STM8S105x4 6 block diagram II 12 Flash memory organization eee 15 LOFP48 PINQUE ETT 23 EQEPA24 pIBIOUL 4 sacks koa eee Oe eee Re oe SR ae eee aes wea ewe NG 24 UFQFPN32 LQFP32 pinout 2 00
85. n power down mode 6 5 25 80 HSI clock after wakeup 1 Data based on characterization results not tested in production Table 27 Total current consumption in halt mode at Vpp 3 3 V Maxat Maxat Symbol Parameter Conditions Typ 85 CM 85 cl Unit Flash in operating mode HSI 60 90 150 Supply current in halt Clock after wakeup WA DD H e mode Flash in power down mode 45 20 80 HSI clock after wakeup 60 121 1 Data based on characterization results not tested in production DoclD14771 Rev 15 2 STM8S105x4 6 Electrical characteristics Low power mode wakeup times Table 28 Wakeup times Symbol Parameter Conditions Typ Max Unit Wakeup time from wait twu wrl mode to run model 0 to 16 MHz See note Wakeup time from run t fopy f 16 MHz 0 56 WU WFI mode CPU MASTER Wakeup time active halt MVR voltage Flash n HSI after 6 6 twU AH Q 4 operating 4 6 2 6 mode to run mode regulator on Jal wakeup Wakeup time active halt MVR voltage drea HSI after 6 1 WU AH mode to run mode 2 regulator off En wakeup 3 us i Wakeup time active halt MVR voltage mn HSI after 180 1 WU AH mode to run mode regulator off See wakeup Wakeup time active halt MVR voltage Flash in HSI after 6 twu aH 2 4 power down 508 mode to run mode regulator off
86. ned in Table 56 Thermal characteristics T max is calculated as follows For LQFP32 60 C W T Jmax 82 C 60 C W x 443 mW 82 C 27 C 109 C This is within the range of the suffix 6 version parts 40 lt Tj lt 131 C Parts must be ordered at least with the temperature range suffix 3 DoclD14771 Rev 15 107 121 Ordering information STM8S105x4 6 13 Ordering information Figure 61 STM8S105x4 6 access line ordering information scheme Example Family type STM8 Product class STMB8 microcontroller s S Standard Sub family type 105 K 10x Access line 105 sub family Pin count K 32 pins S 44 pins C 48 pins Program memory size 4 4 16 Kbyte 6 32 Kbyte Package type B SDIP T LQFP U UFQFPN Temperature range 3 40 to 125 C 6 40 to 85 C Package pitch thickness T 6 TR Blank 0 5 mm C 0 8 mm A 0 55 mm thickness for UFQFPN32 Packing No character Tray or tube TR 7 Tape and reel 1 Adedicated ordering information scheme will be released if in the future memory programming service FastROM is required The letter P will be added after STM8S Three unique letters identifying the customer application code will also be visible in the codification Example STM8SP103K3MACTR For a list of available options for example memory size package and orderable part numbers or for
87. nt high sink ports Symbol Parameter Conditions Min Max Unit Output low level with 8 lio 10 mA aa pins sunk Vpp 25V lio 10 mA VoL D 1 1 Output low level with 4 Vpp 3 3 V pins sunk lio 20 mA 160 Vop 5V V Output high level with 8 lio 10 mA 38 i pins sourced Vpp 25V lio 10 mA VoH E 1 9 0 gt Output high level with 4 Vpp 3 3 V pins sourced lio 20 mA T Vop 5V 1 Data based on characterization results not tested in production 10 3 7 Typical output level curves The following figures show the typical output level curves measured with the output on a single pin 25 C 125 85 C Figure 27 Typ VoL O Vpp 3 3 V standard ports 125 C Vo V AC 25 C 25 85 C ports 125 C Vot V lot mA Figure 28 Typ Vo Vpp 5 0 V standard 2 DoclD14771 Rev 15 75 121 Electrical characteristics STM8S105x4 6 Figure 29 Typ Vo Vpp 3 3 V true open drain ports Va V lou mA Figure 30 Typ Vo Vpp 5 0 V true open drain ports 10 15 lot mA Figure 31 Typ Vo O Vpp 3 3 V high sink ports Va V Figure 32 Typ Vo O Vpp 5 0 V high sink ports 2 DoclD14771 Rev 15 76 121 STM8S105x4 6
88. on ambient Osa LQFP32 7x7 mm SM Thermal resistance junction ambient UFQFPN32 5x5 mm Thermal resistance junction ambient SDIP32 400 ml 1 Thermal resistances are based on JEDEC JESD51 2 with 4 layer PCB in a natural convection environment Reference document JESD51 2 integrated circuits thermal test method environment conditions natural convection still air Available from www jedec org 2 DoclD14771 Rev 15 STM8S105x4 6 Thermal characteristics 12 2 2 Selecting the product temperature range When ordering the microcontroller the temperature range is specified in the order code see Section 13 Ordering information The following example shows how to calculate the temperature range needed for a given application Assuming the following application conditions Maximum ambient temperature Tamax 82 C measured according to JESD51 2 lDDmax 15 mA Vpp 5 5V Maximum 8 standard l Os used at the same time in output at low level with loL 10 mA Vg 2 2 V Maximum 4 high sink I Os used at the same time in output at low level with loi 20 MA Vo 7 1 5 V Maximum 2 true open drain I Os used at the same time in output at low level with lo 20 MA Vg 2 2 V Pintmax 19 mA x 5 5 V 82 5 mW Piomax 10 mA x 2 V x 8 20 mA x 2 V x2 20 mA x 1 5 V x4 360 mW This gives Pintmax 82 5 mW and Piomax 360 mW Ppmax 82 5 MW 360 mW Thus Ppmax 443 mW Using the values obtai
89. or IINJ PIN and YliNJ piv in Section 10 3 6 does not affect the ADC accuracy Figure 45 ADC accuracy characteristics A LL 1022 4 ise sD P8 1021 _ IDEAL 1024 e 777 2 wa E 77 gt 1 A 1 7 6 f M s pi 5 1 zl ng E 7 E a osse 1 cs a i Ep 2 5 nme lt gt NUN E 1 LSBipEaL al HILL ol E 1021102210231024 Vssa DDA 1 Example of an actual transfer curve 2 The ideal transfer curve 3 End point correlation line ET Total unadjusted error maximum deviation between the actual and the ideal transfer curves Eo Offset error deviation between the first actual transition and the first ideal one Eg Gain error deviation between the last ideal transition and the last actual one Ep Differential linearity error maximum deviation between actual steps and the ideal one E Integral linearity error maximum deviation between any actual transition and the end point correlation line Figure 46 Typical application with ADC Voo STM8 Vr Vain Rain RIN T 0 6 V DAD x bit C A 1 rN sear ch A Vr n Dosv Dir Cave MSv38300V1 1 2 Legend Ran external resistance Cain capacitors Csamp internal sample and hold capacitor DoclD14771 Rev 15 87 121 Electrical characteristics STM8S105x4 6 10 3 12 88 121 EMC cha
90. ot implemented 3 J alternate function remapping option if the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function 24 121 DoclD14771 Rev 15 STM8S105x4 6 Pinout and pin description Figure 5 UFQFPN32 LQFP32 pinout O 9 x a O os Z r w O a B d al m usos m xr E T NT N KI TETE GI 5 900 0 TIE Saa ol o J22222 EEEEELAZEL 3 E woo EDIIIILII N Q 0 t 20 N o DOOD ODADO TAO ON Ol 32 31 30 29 28 27 26 25 Y NRSTL e 24 1 PC7 HS SPI MISO OSCIN PA1 L 2 230 Pce HS SPI MOSI OSCOUT PA2 L 3 2210 PC5 HSySPI SCK vss 4 2111 PC4 HS TIM1_CH4 VCAP 5 20 1 PC3 HS TIM1_CH3 VDD Os 191 PC2 HS TIM1_CH2 VDDIOLI7 180 PC1 HS TIM1 CH1 UART2 CK AIN12 PF4 LI8 70 PE5 SPI NSS 9 10 11 12 13 14 15 16 VDDA VSSA N5 PB5 N4 PB4 N3 PB3 N2 PB2 N1 PB1 NO PBO IC SDA A 2C SCL A TIM1 ETR A TIM1 CH3N A TIM1 CH2N A TIM1 CH1N A MS38307V1 2 HS high sink capability alternate function remapping option if the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function DoclD14771 Rev 15 25 121 Pinout and pin description STM8S105x4 6 Figure 6 SDIP32 pinout ADC ETRITIM2 CH2 HS PD3
91. pability T True open drain P buffer and protection diode to Vpp not implemented alternate function remapping option if the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function 2 DoclD14771 Rev 15 23 121 Pinout and pin description STM8S105x4 6 Figure 4 LQFP44 pinout NRST O OSCIN PA1 OSCOUT PA2 VSSIO 1 vss VCAP VDD VDDIO 1 HS PA4 HS PAS HS PAG A o O M Xx ed 2 gt FT Ko x P3 gu di o N uos E m x Fr E gt TNT N X IIT TB O x 000 08 2 lt x mala pa TO 4 L NNADEL lan S Na EZE 52T 071 ERREEEDEDOOOQ Deer AAAAAASGS GILL NNNNA EDDETZTILTILEL NODION TQOTr N qgaqggoangaauuY DOO O OD OO O Oo o 44 43 42 41 40 39 38 37 36 35 34 Y_ 1e 33H PG1 2 3210 PGO 3 310 4 30 O 5 29 O 6 28 O 7 27 O 8 ale 9 25 10 240 11 23 O 12 13 14 15 16 17 18 19 20 21 22 OUDOUOUUUOUOUU IKAN Q DO TAN O Q do t m m da m aam wW Q 0 X 0 n n nn n OL gt gt N DASANE 222222222 LIX TIWKZZZ DOH 9QoN rtr now rir ol Aa 555 SS2555 SEE 55S EGEE PC7 HS SPI MISO PC6 HS SPI_MOSI VDDIO 2 VSSIO 2 PC5 HS SPI SCK PC3 HS PC2 HS TIM1_CH2 PC1 HS TIM1_CH1 UART2_CK PE5 SPI NSS MS38306V1 HS high sink capability T True open drain P buffer and protection diode to Vpp n
92. racteristics Susceptibility tests are performed on a sample basis during product characterization Functional EMS electromagnetic susceptibility While executing a simple application toggling 2 LEDs through I O ports the product is stressed by two electromagnetic events until a failure occurs indicated by the LEDs e ESD Electrostatic discharge positive and negative is applied on all pins of the device until a functional disturbance occurs This test conforms with the IEC 61000 4 2 standard e FTB A burst of fast transient voltage positive and negative is applied to Vpp and Vss through a 100 pF capacitor until a functional disturbance occurs This test conforms with the IEC 61000 4 4 standard A device reset allows normal operations to be resumed The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 EMC design guide for STM microcontrollers Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application Software recommendations The software flowchart m
93. ree times the standard deviation mean 3 2 Typical values Unless otherwise specified typical data are based on T4 25 C Vpp 5 0 V They are given only as design guidelines and are not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range where 95 of the devices have an error less than or equal to the value indicated mean 2 2 Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested Typical current consumption For typical current consumption measurements VDD VDDIO and VDDA are connected together in the configuration shown in the following figure Figure 8 Supply current measurement conditions 5Vor3 3V Vppa Vppio m Vssa Vssio MSv38309V1 DoclD14771 Rev 15 51 121 Electrical characteristics STM8S105x4 6 10 1 5 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 9 Figure 9 Pin loading conditions STM8S PIN 50 pF MSv36480V1 10 1 6 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 10 Figure 10 Pin input voltage STM8S PIN MSv36481V1 d 52 121 DoclD14771 Rev 15 STM8S105x4 6 Electrical characteristics 10 2
94. res 0 422 4 a ea See ek eee ed eee 19 Legend abbreviations for pin description tables 2 0 00000 c eee eee 22 STM8S105x4 6 pin description 000002 ee 26 Flash data EEPROM and RAM boundary address 000 32 I O port hardware register MaP o oooooooo 32 General hardware register map cee rns 34 CPU SWIM debug module interrupt controller registerS oooo o oo o o 42 Interrupt Mapping 44 OPTION byte ies PNG ANA a A a a D ER RATE a A a ae 46 Option byte description 00 0000 eee 47 Alternate function remapping bits 7 0 of OPT2 00 e eee 49 Unique ID registers 96 bits llli 50 Voltage characteristics 2 0 0 0c te hh a 53 Current characteristics 0 0 fe eee 53 Thermal characteristics 0 0 n 54 General operating conditions eee 54 Operating conditions at power up power down 55 Total current consumption with code execution in run mode at Vpp 2 5 V 57 Total current consumption with code execution in run mode at Vpp 3 3V 58 Total current consumption in wait mode at Vpp 5V 0 0 0 002 eee eee 58 Total current consumption in wait mode at Vpp 2 3 3V 0000000002 59 Total current consumption in active halt mode at Vpp 25V a 59 Total current consumption in active halt mode at Vpp 2 3 3V a 60 Total current consumption in halt mode at Vpp 5V eee 60 Total current
95. ristics for more details on the input output alternate function characteristics NSS SCK MOSI MISO Table 42 SPI characteristics Symbol Parameter Conditions Min Max Unit T tctsck 2 DoclD14771 Rev 15 STM8S105x4 6 Electrical characteristics Table 42 SPI characteristics continued enable edge Symbol Parameter Conditions Min Max tyscx SPI clock rise and fall Capacitive load 25 tySck time C 30 pF tsunss NSS setup time Slave mode 4 tMASTER trnss NSS hold time Slave mode 70 2 bu SCKH SCK high and low time Master mode tsck 2 15 tsck 2 15 w SCKL t 2 Master mode 5 su MI Data input setup time tsu si Slave mode 5 2 Master mode 7 thm Data input hold time thsi Slave mode 10 taso Data output access time Slave mode 3 MASTER tuis so Data output disable time Slave mode 25 2 Slave mode i tso Data output valid time after enable edge 73 2 LM Master mode after f two Data output valid time enable edge 36 2 Slave mode after i nso enable edge 28 Data output hold time th 2 Master mode after 12 MO Unit ns Parameters are given by selecting 10 MHz I O output frequency 2 Values based on design simulation and or characterization results and not tested in production Min time is for the minimum time to drive the output and the max time is for
96. ses a prescaler Gap 0x00 50F2 AWU_TBR Eu selection 0x00 0x00 50F3 BEEP BEEP_CSR BEEP control status register 0x1F 0x00 50F4 to 0x00 50FF Reserved area 12 byte 0x00 5200 SPI_CR1 SPI control register 1 0x00 0x00 5201 SPI_CR2 SPI control register 2 0x00 0x00 5202 SPI ICR SPI interrupt control register 0x00 0x00 5203 SPI SR SPI status register 0x02 0x00 5204 xd SPI DR SPI data register 0x00 0x00 5205 SPI CRCPR SPI CRC polynomial register 0x07 0x00 5206 SPI RXCRCR SPI Rx CRC register OxFF 0x00 5207 SPI TXCRCR SPI Tx CRC register OxFF Ly DoclD14771 Rev 15 35 121 Memory and register map STM8S105x4 6 Table 8 General hardware register map continued Address Block Register label Register name Reset status 0x00 5208 to 0x00 520F Reserved area 8 byte 0x00 5210 I2C_CR1 12C control register 1 0x00 0x00 5211 I2C_CR2 12C control register 2 0x00 0x00 5212 I2C_FREQR 12C frequency register 0x00 0x00 5213 I2C_OARL I2C Own address register low 0x00 0x00 5214 I2C OARH ac address register 0x00 0x00 5215 Reserved 0x00 5216 I2C DR I2C data register 0x00 0x00 5217 12C I2C_SR1 12C status register 1 0x00 0x00 5218 I2C_SR2 12C status register 2 0x00 0x00 5219 I2C_SR3 12C status register 3 0x0X 0x00 521A I2C_ITR I2C interrupt control register 0x00 0x00 521B I
97. sh program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction There are two levels of write protection The first level is known as MASS memory access security system MASS is always enabled and protects the main Flash program memory data EEPROM and option bytes To perform in application programming IAP this write protection can be removed by writing a MASS key sequence in a control register This allows the application to write to data EEPROM modify the contents of main program memory or the device option bytes A second level of write protection can be enabled to further protect a specific area of memory known as UBC user boot code Refer to the figure below DoclD14771 Rev 15 Ly STM8S105x4 6 Product overview The size of the UBC is programmable through the UBC option byte in increments of 1 page 512 byte by programming the UBC option byte in ICP mode This divides the program memory into two areas e Main program memory up to 32 Kbyte minus UBC e User specific boot code UBC Configurable up to 32 Kbyte The UBC area remains write protected during in application programming This means that the MASS keys do not unlock the UBC area It protects the memory used to store the boot program specific code libraries reset and interrupt vectors the reset routine and usually the IAP and communication routines Figure 2 Flash memory organ
98. sign not tested in production 3 Data based on characterization results not tested in production Figure 21 Typical HSI accuracy Vpp 5 V vs 5 temperatures 3 00 2 00 1 00 0 00 1 00 2 00 3 00 4 00 5 00 40 0 25 85 125 2 DoclD14771 Rev 15 69 121 Electrical characteristics STM8S105x4 6 Figure 22 Typical HSI frequency variation vs Vpp 4 temperatures 1 00 0 506 0 00 10 0 e accuracy 1 00 LENG 2 00 d 70 121 DoclD14771 Rev 15 STM8S105x4 6 Electrical characteristics d Low speed internal RC oscillator LSI Subject to general operating conditions for Vpp and Ta Table 34 LSI oscillator characteristics Symbol fi si Parameter Frequency Conditions Min 110 Typ 128 Max 150 Unit kHz tsu LsI LSI oscillator wakeup time 70 us IDD LSI LSI oscillator power consumption pA 1 Guaranteed by design not tested in production Figure 23 Typical LSI frequency variation vs Vpp 4 temperatures 96 accuracy 5 00 4 00 3 00 2 00 1 00 0 00 1 00 2 00 3 00 4 00 5 00 DoclD14771 Rev 15 71 121 Electrical characteristics STM8S105x4 6 10 3 5 72 121 Memory characteristics RAM and hardware registers Table 35 RAM and hardware registers Symbol Parameter Conditions Min Unit VRM Data reten
99. single interrupt per valid message header e Automatic baud rate synchronization maximum tolerated initial clock deviation 115 e Synch delimiter checking e 11 bit LIN synch break detection break detection always active e Parity check on the LIN identifier field e LIN error management e Hot plugging support 4 14 2 SPI e Maximum speed 8 Mbit s MASTER 2 both for master and slave e Full duplex synchronous transfers e Simplex synchronous transfers on two lines with a possible bidirectional data line e Master or slave operation selectable by hardware or software e CRC calculation e 1 byte Tx and Rx buffer e Slave master selection input pin 4 14 3 PRC e 2C master features Clock generation Start and stop generation e PC slave features Programmable I2C address detection Stop bit detection e Generation and detection of 7 bit 10 bit addressing and general call e Supports different communication speeds Standard speed up to 100 kHz A Fast speed up to 400 kHz 2 DoclD14771 Rev 15 21 121 Pinout and pin description STM8S105x4 6 5 Pinout and pin description Table 4 Legend abbreviations for pin description tables Type l Input O Output S Power supply Input CM CMOS Level Output HS High sink O1 Slow up to 2 MHz O2 Fast up to 10 MHz O3 Fast slow programmability with slow as default state after reset OA Fast slow programmability with fast as
100. sitive injection is induced by V y gt Vpp while a negative injection is induced by Viy lt Vss For true open drain pads there is no positive injection current allowed and the corresponding Viy maximum must always be respected 5 Negative injection disturbs the analog performance of the device See note in Section TIM2 TIM3 16 bit general purpose timers 6 When several inputs are submitted to a current injection the maximum 2l pi is the absolute sum of the positive and negative injected currents instantaneous values These results are based on characterization with 2 liN PIN maximum current injection on four I O port pins of the device Table 17 Thermal characteristics Symbol Ratings Value Unit TsTG Storage temperature range 65 to 150 C Ty Maximum junction temperature 150 10 3 Operating conditions The device must be used in operating conditions that respect the parameters described in the table below In addition full account must be taken of all physical capacitor characteristics and tolerances Table 18 General operating conditions Symbol Parameter Conditions Min Max Unit fopu Internal CPU clock frequency E 0 16 MHz Vpp Vppio Standard operating voltage 2 95 5 5 V Cext capacitance of external 470 3300 nF capacitor VcAp ESR of external capacitor 0 3 Q H at 1 MHz ESL of external capacitor 15 nH 44 and 48 pin devices with output on eight standard
101. t allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers STice key features e Occurrence and time profiling and code coverage new features e Advanced breakpoints with up to 4 levels of conditions e Data breakpoints e Program and data trace recording up to 128 KB records e Read write on the fly of memory during emulation e In circuit debugging programming via SWIM protocol e 8 bit probe analyzer e 1 input and 2 output triggers e Power supply follower managing application voltages between 1 62 to 5 5 V e Modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements e Supported by free software tools that include integrated development environment IDE programming software interface and assembler for STM8 DoclD14771 Rev 15 113 121 STM8 development tools STM8S105x4 6 14 2 14 2 1 14 2 2 114 121 Software tools STM8 development tools are supported by a complete free software package from STMicroelectronics that includes ST Visual Develop STVD IDE and the ST Visual Programmer STVP software interface STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8 which are available in a free version that outputs up to 16 Kbytes of code STM8 toolset The STM8 toolset with STVD integrated d
102. tage Total current consumption in run mode Table 20 Total current consumption with code execution in run mode at Vpp 5 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 3 2 HSE user ext clock feru fMASTER 16 MHz 16 MHz 2 6 3 2 Supply HSI RC osc 16 MHz 2 5 3 2 current in Run mode HSE user ext clock 1 6 2 2 DD RUN code fopu fuAsrER 128 125 kHz 16 MHz 2d EM HSI RC osc 16 MHz 13 2 0 fopy f 128 Hai m m HSI RC osc 16 MHz 8 0 75 g fopu fmasTER 128 kHz LSI RC osc 128 kHz 0 55 HSE crystal osc 16 MHz 7 7 HSE user ext clock fopu fmastER 16 MHz 16 MHz 7 0 8 0 Supply currentin HSI RC osc 16 MHz 7 0 8 0 IDD RUN ia mode fopy faster 2 MHz HSI RC osc 16 MHz 8 1 5 mA code executed fopy fuaster 128 125 kHz HSI RC osc 16 MHz 1 35 2 0 from Flash f Er 128 ee aa HSI RC osc 16 MHz 8 0 75 g fopu fmasTeR 128 kHz LSI RC osc 128 kHz 0 6 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off Ly DoclD14771 Rev 15 57 121 Electrical characteristics STM8S105x4 6 Table 21 Total current consumption with code execution in run mode at Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit H
103. te eerie te tenue epe RMR eles 112 121 DoclD14771 Rev 15 Ky STM8S105x4 6 STM8 development tools 14 14 1 14 1 1 2 STM8 development tools Development tools for the STM8 microcontrollers include the full featured STice emulation system supported by a complete software tool package including C compiler assembler and integrated development environment with high level language debugger In addition the STMB is to be supported by a complete range of tools including starter kits evaluation boards and a low cost in circuit debugger programmer Emulation and in circuit debugging tools The STice emulation system offers a complete range of emulation and in circuit debugging features on a platform that is designed for versatility and cost effectiveness In addition STMB8 application development is supported by a low cost in circuit debugger programmer The STice is the fourth generation of full featured emulators from STMicroelectronics It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application In addition STice offers in circuit debugging and programming of STM8 microcontrollers via the STMB8 single wire interface module SWIM which allows non intrusive debugging of an application while it runs on the target microcontroller For improved cost effectiveness STice is based on a modular design tha
104. tion mode Halt mode or reset Vir max V 1 Minimum supply voltage without losing data stored in RAM in halt mode or under reset or in hardware registers only in halt mode Guaranteed by design not tested in production 2 Refer to Section 10 3 Operating conditions for the value of Vir may Flash program memory data EEPROM memory Table 36 Flash program memory data EEPROM memory Symbol Parameter Conditions Min Typ Max Unit Operating voltage VoD all modes execution write erase lepus 16 MHz sa SE So M Standard programming time including erase for byte word block 6 6 6 frog 1 byte 4 byte 128 byte Fast programming time for 1 block i 3 3 33 ms 128 byte terase Erase time for 1 block 128 byte 3 3 33 Erase write cycles pa Ta 85 C 10k New program memory cycle Erase write cycles data memory Ta 125 C 300k 1M Data retention program and data memory after 10k erase write cycles Tret 55 C 20 at Taz 55 C tRET year Data retention data memory after 300k erase write cycles at Tret 85 C 1 Taz 125 C Supply current Flash programming or 2 i a d erasing for 1 to 128 byte 1 Data based on characterization results not tested in production 2 The physical granularity of the memory is 4 byte so cycling is performed on 4 byte even when a write erase operation addresses a single byte 2 Docl
105. tprint N 1 a Lu A o y o Y ai14911d 1 Dimensions are expressed in millimeters Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 49 LQFP48 marking example package top view Product identification STM amp S105 Date code Standard ST logo Revision code Pin 1 identifier MS38328V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such DoclD14771 Rev 15 93 121 Package information STM8S105x4 6 11 2 94 121 usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity LQFP44 package information Figure 50 LQFP44 44 pin 10 x 10 mm low profile quad flat package outline SEATING PLANE C a ba EVE lt al FOO AA AIA AA m A 0 25 mm GAUGE PLANE Ol ccc C v xi Vk o Dra la gt D1 L1 gt 4 D3 gt E3 E1 E PIN 1 IDENTIFICATION gt 4Y_ME 1 Drawing is not to scale d DoclD14771 Rev 15
106. ts 4 EXTI1 Port Bextemal e Yes 0x00 8018 interrupts 5 EXTI2 Port C external Ves Yes 0x00 801C interrupts 6 EXTI3 Port D extemal ds Yes 0x00 8020 interrupts 7 EXTI4 Port E extemal as Yes 0x00 8024 interrupts 8 Reserved 0x00 8028 9 Reserved 0x00 802C 10 SPI End of transfer Yes Yes 0x00 8030 TIM1 update overflow H UM underflow trigger O 0x00 8034 break 12 TIM1 apa kh 0x00 8038 compare 13 TIM2 TS pn 0x00 803C overflow 14 TIM2 nc pue ik 0x00 8040 compare 15 TIM3 T PUE 0x00 8044 overflow 16 TIM3 TIM caper 0x00 8048 compare 17 Reserved 0x00 804C 18 Reserved 0x00 8050 19 12C 12C interrupt Yes Yes 0x00 8054 44 121 DoclD14771 Rev 15 ky STM8S105x4 6 Interrupt vector mapping Table 10 Interrupt mapping continued e Wakeup from Wakeup from IRQ no Source block Description halt mada active halt moda Vector address 20 UART2 Tx complete Ox00 8058 Receive register 21 UART2 DATA FULL 0x00 805C ADC1 end of 22 ADC1 conversion analog 0x00 8060 watchdog interrupt 23 TIM4 Te ai 0x00 8064 overflow 24 Flash EOP WR_PG_DIS 0x00 8068 Basta 0x00 806C to 0x00 807C 1 Except PA1 Ly DoclD14771 Rev 15 45 121 Option byte STM8S105x4 6 8 Option byte Option byte contain configurations for device hardware features as well as the memory protection of the device They are stored in a dedicated block of the memor
107. ts by programming one of eight AFR alternate function remap option bits When the remapping option is active the default alternate function is no longer available To use an alternate function the corresponding peripheral must be enabled in the peripheral registers Alternate function remapping does not effect GPIO capabilities of the I O ports see the GPIO section of the family reference manual RM0016 2 DoclD14771 Rev 15 STM8S105x4 6 Memory and register map 6 Memory and register map 6 1 Memory map Figure 7 Memory map 0x00 0000 RAM 2 Kbyte 0x00 07FF 512 byte stack 0x00 4000 1 Kbyte data EEPROM 0x00 43FF 0x00 47FF 0x00 4800 Option bytes 0x00 487F 0x00 4900 0x00 4FFF BEEN 0x00 5000 GPIO and periph reg 0x00 57FF 0x00 5800 0x00 5FFF 0x00 6000 2 Kbyte boot ROM 0x00 67FF 0x00 6800 0x00 7EFF 0x00 7F00 CPU SWIM debug ITC registers 0x00 7FFF 0x00 8000 32 interrupt vectors 0x00 807F Flash program memory 16 to 32 Kbyte 0x00 FFFF 0x01 0000 0x02 7FFF MSv38308V1 The following table lists the boundary addresses for each memory size The top of the stack is at the RAM end address in each case 2 DoclD14771 Rev 15 31 121 Memory and register map STM8S105x4 6 Table 6 Flash data EEPROM and RAM boundary address
108. umber of High Sink I Os in the pinout section TSSOP20 pinout modified PD4 moved to pin 1 etc Added WFQFN20 package Updated Section Option bytes Added Section Memory and register map Removed STM8S103x products separate STM8S103 datasheet created Updated Section Electrical characteristics 2 STM8S105x4 6 Revision history Table 57 Document revision history continued Date Revision Changes Added SDIP32 silhouette and package to Features and Section SDIP32 package mechanical data updated Section Pinout and pin description Updated VDD range 2 95 V to 5 5 V on Features Amended name of package VQFPN32 Added Table 5 on page 22 Updated Section Auto wakeup counter Updated pins 25 30 and 31 in Section Pinout and pin description Removed Table 7 Pin to pin comparison of pin 7 to 12 in 32 pin access line devices Added Table Description of alternate function remapping bits 7 0 of OPT2 12 May 2009 7 Section Electrical characteristics Updated VCAP specifications updated Table 15 Table 18 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 29 Table 35 and Table 42 added current consumption curves removed Figure 20 typical HSE frequency vs fcpu 4 temperatures updated Figure 13 Figure 14 Figure 15 Figure 16 and Figure 17 modified HSI accuracy in Table 33 added Figure 44 modified fsck tv so and tymo in Table 42 updated figures
109. ure 43 SPI timing diagram master mode High NSS input t to SCKj gt gt 3 crHaso Y f 5 CPOL 0 4 i hs a O i i L E x CPHA 0 i i n Oo 1 I wn 1 SCK Output OO ii it Os p tw SCKH TT tg I SCK I d i Isu MI gt a gt e t Da MISO hes T T INPUT 1 lo 1 MSBIN IN BITS IN LBN IN nich BIT1 OUT O tssour OUT OUTPUT Ll MsBour Col tv MO lt gt EE Du ai14136c 1 Measurement points are at CMOS levels 0 3 Vpp and 0 7 Vpp Ly DoclD14771 Rev 15 83 121 Electrical characteristics STM8S105x4 6 10 3 10 84 121 12C interface characteristics Table 43 12C characteristics 1 faster Must be at least 8 MHz to achieve max fast 12C speed 400 kHz 2 Data based on standard 12C protocol requirement not tested in production Standard mode I C Fast mode 1 C Symbol Parameter Unit Min Max Min Max tw SCLL SCL clock low time 4 7 1 3 tw SCLH SCL clock high time 4 0 0 6 di tsu SDA SDA setup time 250 100 E tH SDA SDA data hold time o o9 goo mi amag mco Jao UMEN MENE th STA START condition hold time 4 0 0 6 tsu STA Repeated START condition setup time 4 7 0 6 tusro STOP condition setup time 4 0 0 6 HS WeToSti STOP to START condition time 4 7 13 i i bus free Cb Capacitive load for each bus line 400 400 pF The ma
110. ust include the management of runaway conditions such as e Corrupted program counter e Unexpected reset e Critical data corruption control registers Prequalification trials Most of the common failures unexpected reset and program counter corruption can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring See application note AN1015 Software techniques for improving microcontroller EMC performance Table 47 EMS data Symbol Parameter Conditions Level class Vpp 9 V Taz 25 C fMASTER 16 MHz HSI clock 2180 Conforms to IEC 1000 4 2 Voltage limits to be applied on any I O pin VFESD to induce a functional disturbance Fast transient voltage burst limits to be Vpp 5 V TA 25 C Verrg applied through 100 pF on Vpp and Vss fmaster 16 MHz HSI clock AIAU pins to induce a functional disturbance Conforms to IEC 1000 4 4 DoclD14771 Rev 15 Ly STM8S105x4 6 Electrical characteristics 2 1 Data obtained with HSI clock configuration after applying the hardware recommendations described in AN2860 EMC guidelines for STM8S microcontrollers Electromagnetic interference EMI Based on a simple application running
111. vated AFR2 option has priority over AFR3 AFR3 check only one option 0 Remapping option inactive Default alternate functions used Refer to pinout description 1 Port DO alternate function TIM1 BKIN 2 DoclD14771 Rev 15 STM8S105x4 6 Ordering information 2 AFR4 check only one option 0 Remapping option inactive Default alternate functions used Refer to pinout description 1 Port D7 alternate function TIM1_CH4 AFR5 check only one option 0 Remapping option inactive Default alternate functions used Refer to pinout description 1 Port B3 alternate function TIM1_ETR port B2 alternate function TIM1_NCC3 port B1 alternate function TIM1_CH2N port BO alternate function TIM1_CH1N AFR6 check only one option 0 Remapping option inactive Default alternate functions used Refer to pinout description 1 Port B5 alternate function I2C_SDA port B4 alternate function I2C_SCL AFR6 check only one option 0 Remapping option inactive Default alternate functions used Refer to pinout description 1 Port D4 alternate function BEEP OPT3 watchdog WWDG_HALT 0 No reset generated on halt if WWDG active check only one option 1 Reset generated on halt if WWDG active WWDG HW 0 WWDG activated by software check only one option 1 WWDG activated by hardware IWDG_HW 0 IWDG acti
112. vated by software check only one option 1 IWDG activated by hardware LSI EN 0 LSI clock is not available as CPU clock source check only one option 1 LSI clock is available as CPU clock source HSITRIM 0 3 bit trimming supported in CLK_HSITRIMR register check only one option 1 4 bit trimming supported in CLK HSITRIMR register OPT4 watchdog PRSC check only one option for 16 MHz to 128 kHz prescaler for 8 MHz to 128 kHz prescaler for 4 MHz to 128 kHz prescaler CKAWUSEL check only one option HSE clock with prescaler selected as clock source for AWU EXTCLK External crystal connected to OSCIN OSCOUT check only one option LSI clock source selected for AWU External signal on OSCIN DoclD14771 Rev 15 111 121 Ordering information STM8S105x4 6 OPT5 crystal oscillator stabilization HSECNT check only one option 2048 HSE cycles 128 HSE cycles 8 HSE cycles 0 5 HSE cycles OTP6 is reserved OTP7 is reserved OTPBL bootloader option byte check only one option Refer to the UM0560 STM8L S bootloader manual for more details Disable 00h Enable 55h Comments OOOH NA A Pan AA thes Supply operating range in the application 7227 000 aa aanaana aaa aaana nauna nn cnn nnnnnn cnn cnn naar nnne nnn AA lamas Date 0 RA AA a Signature Cs eget te cet
113. ximum hold time of the start condition has only to be met if the interface does not stretch the low time 4 The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL Figure 44 Typical application with 12C bus and timing diagram Vpp Vpp 4 7 KQ C bus Repeated START y MO cuan tsuista tw STO STA a eet ae START sba N A X X f e a trsDA tyspa 1 tsu SDA tr sDA STOP lt gt lt S SCL m tasta twscin twscLt tyscL tysct tsu sTO MSv36492V1 DoclD14771 Rev 15 2 STM8S105x4 6 Electrical characteristics 10 3 11 10 bit ADC characteristics Subject to general operating conditions for Vppa faster and Ta unless otherwise specified Table 44 ADC characteristics Symbol Parameter Conditions Min Typ Max Unit Vpp 2 95 to 5 5 V 1 4 fapc ADC clock frequency A a 4 1 MHz Vpp 4 5 to 5 5 V 1 6 VDDA Analog supply 3 0 5 5 Vngr Positive reference voltage 2 75 VDDA V Vrer _ Negative reference voltage Vssa 0 5 1 Vssa Vopa VAIN Conversion voltage range Devices with V external VREF VREF VREF VREF Internal sample and hold Canc capacitor pF fADC 4MHz 0 75 s tg Minimum sampling time OQ A us fapc 6 MHz 0 5 tsTAB Wakeup time from standby gt 7 7 0 us Minimum total conversion time l
114. y Except for the ROP read out protection byte each option byte has to be stored twice in a regular form OPTx and a complemented one NOPTx for redundancy Option byte can be modified in ICP mode via SWIM by accessing the EEPROM address shown in the table below Option byte can also be modified on the fly by the application in IAP mode except the ROP option that can only be modified in ICP mode via SWIM Refer to the STM8S Flash programming manual PM0051 and STM8 SWIM communication protocol and debug module user manual UM0470 for information on SWIM programming procedures Table 11 Option byte Option Option bits Factor Option p p y Addr name byte default no 7 6 5 4 3 2 1 0 setting Read out 0x4800 protection OPTO ROP 7 0 0x00 ROP 0x4801 User basi OPT1 UBC 7 0 0x00 0x4802 code UBC NOPT1 NUBC 7 0 OxFF 0x4803 Alternate OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFRO 0x00 function 0x4804 remapping NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFRO OxFF AFR HSI IWDG WWDG WWDG 0x4805h OPT3 Reserved LSI EN 0x00 TRIM x _HW _Hw _HALT Misc option NHSI NLSI NIWDG NWWDG NWWG 0x4806 NOPT3 Reserved OxFF TRIM EN _HW _Hw _HALT CKAWU 0x4807 OPT4 Reserved EXT CLK SEL PRS C1 PRS CO 0x00 Clock option NEXT NCKA 0x4808 NOPT4 Reserved NPRSC1 NPR SCO OxFF CLK WUSEL 0x4809 HSE clock O

Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbyte Flash

Contents

Download Pdf Manuals

Related Search

Related Contents