SMT148FX User Manual - Sundance Multiprocessor Technology Ltd.
Contents
1. 32 11 Accessing the Hash e u u uQ 33 111 Programming EE eege 33 11 2 Erase and Program of the 33 11 3 Booting the Spartan and Virtex 4 from flash 34 12 Firmware for the Spartan 34 12 1 36 13 RSL and Comport connections 37 15 1 RSL 066B c ti nS cela 37 13 2 ele e EEN 39 14 Spartan firmware explanation 42 15 DIP daaa Ae 45 16 Support Packages E 46 17 Physical ProperBe S u UU i 46 18 Thermal Management 47 IS SI cc 48 20 EN 48 21 Ordering Information 48 1 Introduction The SMT148FX is a four site stand alone TIM carrier board with several external interfaces Connectors are provided to interface to 9232 From FPGA or USB controller e LVDS 48 pairs e JTAG e RSL e SATA Connectors carrying RSL signals only e SHB e RS485 16 pairs e USB2 e Firewire 1394 interface only No IP core e Ethernet 10 100 1000 e LED x32 ZBT memory e Local clock buffer generator output 2 Rela2. Unit Module Description Unit Module Number SMT148FX DC SMT148FX ATX Document Issue Number 1 4 Issue Date 3 8 09 Original Author GKP User Manual for SMT148FX DC and ATX versions Sundance Multiprocessor Technology Ltd Chiltern House VVaterside Chesham Bucks HP5 1PS This document is the property of Sundance and may not be copied nor communicated to a third party without prior written permission Sundance Multiprocessor Technology Limited 2006 DEES Revision History E Chawa ha eg 221 Update LVDS FPGA connectivity 20 8 07 EM Added LVDS buffer drawing 20 8 07 ESE Differentiated DC and ATX versions 13 6 08 3 1 Corrected LVDs connector pin out tables 3 7 08 Added additional detail about IL715 isolators Added connector info for RS485 19 8 08 Spartan firmware explanation 3 8 09 Important comments or cautions are displayed next to this symbol Table of Contents 1 Introduction o Ann 5 2 Related D c UMentS ia 6 2 1 Referenced DocumentSs ail 6 3 Acronyms Abbreviations and Definitions 6 3 1 AGIATA Ra 6 4 Functional E 7 4 0 inc Diagrama u La aa Bala 7 2115100507 ii 0 AI ERA 8 S Spartan 3 duan ai 8 ilo TIM salario rara 8 41 4 10 100 1000
3. Option C is with the use of an external ATX power supply Refer to the relevant power supply specification in this case MTBF 18 Thermal Management Although provision is made to attach DC fans to the SMT148FX powered directly from the input voltage correct enclosure air flow should be ensured Sundance are able to provide a heat pipe type thermal management solution for two TIM sites sites 2 and 3 This involves increased height TIM and RSL connectors for these sites the fixing of the heat pipe system direct to the TIMs components and the addition of an off board heatsink and fan Please consult Sundance for pricing and availability for this option Several components in both the onboard 3 3V and 5 0V supplies are rated at 125 C maximum Without adequate cooling the inductors in this circuit can reach in excess of 170 C when running at full rated load Some of the major components are located on the underside of the carrier board This will allow heatsinks or indeed an enclosure to be fitted 19 Safety This module presents no hazard to the user when in normal use 20 EMC This module is designed to operate from within an enclosed host system which is built to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system This unit is protected from damage by fast voltage transients originating from outside the host system
4. TIM SITE 1 TIM SITE 4 TIM SITE 4 TIM SITE 3 3 0 Implementation in the bitsream entitled default_anticlockwise Fx2lp Implementation in the bitsream entitled default Implementation in the bitsream entitled default dual_TIM Usb cable Figure 2 Default bitstream comport configuration 12 1 Hardwired comport connections A hardwired comport pipe is implemented between TIM sites It links the TIM sites in a clockwise manner using comport 2 and comport 5 as per Figure 3 TIM SITE 2 2 5 TIM SITE 3 TIM SITE 1 5 SS 2 TIM SITE 4 PCB Comport connections between TIM sites Figure 3 PCB comport connections between TIM sites 13 RSL and Comport connections 13 1 RSL connections gt A Ol s 9 E 9 3 9 3 3 H z 290399 9909 P 9999 fesa Virtex 4 FX60 gang tes 9099 LT Es H m in TEN 20 2422 Figure 4 Virtex 4 RSL connections KH 22 22 T BEI O ip 4 Figure 6 PCB RSL connections between TIM sites User Manual SMT148FX Page 38 of 48 Last Edited 03 08 2009 11 42 00 13 2 Comport connections KE ED d 188 1122112119112 L TEN 20 2422 Figure 7 PCB comport connections between TIM sites B MERA CP 0 2 cpa ces CP 16
5. program a new firmware for it Browse to the firmware of your choice for the SMT148FX Spartan or the Virtex 4 after the next power up it will be loaded from Flash in the Spartan and or the Virtex4 It can be found in Program Files SundanceSMT6002 Firmware Smtl 48FX You always need to delete the current bitstream before replacing it with a new bitstream in Flash Deleting a bitstream is quick but erasing the whole flash can take 2 minutes Programming takes about 1 minute 11 3 Booting the Spartan and Virtex 4 from flash Then set the switch SW4 4 3 2 1 OFF OFF OFF OFF The Spartan and Virtex 4 will configure from Flash next time you issue a hard reset or power on the SMT148FX Any Spartan design available flashes led 2 while the Virtex4 example design provided flashes the whole raw of leds next to led2 12 Firmware for the Spartan It can be found in Program Files Sundance SMT6002 Firmware Smt148FX The default firmware com sundance smt148 fx sc3s1500 usb_default app present in flash enables default comport connections between TIM sites and a direct connection between USB and TIM site 1 comport 3 The connections are represented by Figure 2 Default bitstream comport configuration More firmware are available to allow different TIM connections The default_anticlockwise firmware com sundance smt148 fx sc3s1500 usb default anticlockvvise app provides the same comport connections as
6. Ethernet Phy a 8 2 al A o A n s b 9 cH e nas 12 AE o e 12 ND 14 IE 14 211100 RO enten A 15 Sn A o A 15 AARDS A aa IE 15 G LZ WT a a aa 15 A da qhasa haqa aaa ad ala 16 4 1 15External 17 domna om or 19 4 1 1 7ZPow r input DC VEO 20 E e input E MR E e E 21 LOBO WEr OU Dil nados 22 101 aa baa baba 22 dl Local Te 23 ZEE N POWEL E 23 CAPRI e oo e 23 4 1 24External FPGA Clock Input cana 24 4 1 25FPGA Virtex4 and Spartan 24 5 Jumper Position Function 25 6 Footprint 26 Cl Pop Eeer 26 62 BOOM TE 27 7 Virtex4 FPGA Pin Allocation 28 8 Virtex4 FPGA Bank Allocation 29 9 Programming the Cpld 31 10 Application to program the Flash 32 10 1 Connections provided on the SMT148FX
7. GN Res CR C215 aca USB USB_MICRO FPGA POWER RS232 RS232 6 Footprint 6 1 Top View Spray ul uyq llonuo den 91019941409 y yoos pue VLVS Ein 1SM Xuyeuu 031 8 5 11040102 jewapg SHOJWOD noyu DVLP peoq peog Sers e pue e 19S9Y ni HE NI e RE II 6 FR uno n nnm r 7 SP o ee JeMOd BEE HA aa Shee da sit ES Boa d iH sa mios S sa NSd XLV 2 E Wo 2 Jemod S jeug OG R INN E RININII FEN T TTTT A presi bun x se 2090 D Wm p elosi AC E Sx90 9 404 10 99UU09 Y SS VINS 3 oo 00077 ss eoosssosssosss 3 as b r 6 MA e o o J p ds pue d q 1Jolo uuoo SQAT 404 2625 6 13331 Jojoauuos adAy q lew 2 Bottom
8. SN75HVD12 They are arranged into two groups of 8 bits each and have a single control signal which selects the group to be a transmitter or receiver Connector RSI carries these signals pin i Function GND GND 23 GND S8 25 S8 S9 27 S9 29 S10 31 S11 sz 15 6 s S E EA s 9 To seo 12 s 14 33 S12 35 S13 te 37 514 GND S15 39 T S15 4 1 11 SHB A single SHB connector Samtec QSH 030 01 provides two independent 16 bit SDBs or a single 32 bit SDB interface These signals are connected directly to the 60 4 1 12 LEDs 32 LEDs are connected to the Virtex 4 FPGA in a matrix of 8x4 4 1 13 ZBT Memory Two 16 bit wide ZBT memories are connected directly to the FPGA This provides a memory bank of 2Mx16 bits 4Mbytes The standard FPGA firmware does not include functions to control the ZBTRAM VHDL test code is available Please contact Sundance for further information 4 1 14 RSL The Virtex 4 FX FPGA provides 16 RSL Rocket Serial Link interfaces 8 of these are connected to the 4 TIM sites 2 per site Four RSLs are connected to 4 SATA style connectors thus allowing inter board connectivity The remaining 4 are presented on a standard RSL connector See the RSL specification for details on the connector type The SATA style connectors do NOT provide a SATA interface using the standard Sundance FPGA firmware RSL interfaces provide a high speed 250Mbytes s per li
9. V 6 AHd SJ9Al9ISUEN pue aJa SJO E OSI STAT 9 000 9000 009 96 e eeo eo b SH n 0 0 Hi O 00 9000 900 E du plat 999099900 009 Se ee ee Ca et eee SOOO ON eee tee er eet eee et dOd Ott ere tee tee et eet tots VOdI uepeds Se Gett dei O m m Leen dd G de D te 1 Zeie LS Zeie d i UI CH UI D ee iowew 182 D Wi dh i U O sueyng DO S8YSY 000 d VvOdd XI POHIA o mm CH qi asn NOYd33 i AHd ul uyq uonenfyuoo Kous 10 0140 4521 USB2 controller CLK il 22 SDB type interface Data 16 Control 3 User Def 2 Firewire OXUF922 All 29 IDE interface to OXUF922 Address 12 23 From OXUF922 Data 8 V4 Configuration data Control 3 RS485 All 18 16 data and two control LVDS All 56 8 groups of 7 normally routed to McBSPs via FPGA LEDs All 12 8 x 4 matrix Ethernet PHY All 12 4 bit data 2 control for each direction 4 RS
10. connection to the FPGA pin H17 This has 50 Ohm termination and is suitable for LVTTL maximum 3 3V signals only 4 1 25 FPGA Virtex4 and Spartan configuration The Virtex4 FPGA can be configured from flash USB or ComPort This is determined by the setting of switch bank SW3 and is detailed in the following table Note that SW4 1 must be set to OFF The Jumpers 1 2 of SW3 control the Spartan configuration The Jumpers 3 4 of SW3 control the Virtex4 configuration SW3 Position 2 or 4 Position 1 or 3 Flash ON ON Comport OFF ON USB ON OFF Examples Both devices configure from Flash ON ON ON ON Direct configuration via USB ON OFF ON OFF needs a host application to send the bitstreams via USB Configuration of Spartan via Flash and of Virtex 4 via CP3 OFF ON ON ON connected to TIM site 1 CPO The Spartan is always the device configured first It is possible to download a new configuration to the FPGA using a Xilinx JTAG cable connected to a PC and to JP6 on the SMT148FX carrier This uses the standard 14 way ribbon cable supplied by Xilinx Refer to Xilinx document DS300 v3 1 page 8 for details of the pinout 5 Jumper Position Function EEPROM RESET ENABLE vo v33 PES GND RIB RIB MM C39 B H B IIA IIIIII I I IIOIIIAII R e n nnn n n n E e C214 4 240 CLKOUT si ME me WAKEU
11. for further information 4 1 5 LVDS Isolators 48 single ended signals are connected from the Virtex 4 to LVDS drivers and receivers SN65LVDS390 1 via galvanic isolators type IL715 3 The transmitter part is enabled via control signals The LVDS outputs are arranged in groups of 6 hence there are 8 control signals The LVDS receivers are enabled continuously The isolation provided is up to 150V rms maximum The isolation provided is up to 150V rms whilst still enabling a baud rate of up to 100Mbps The LVDS transmitters and receivers are external to the FPGA itself The devices used are SN65LVDS390 and 391 LVTTL input from FPGA Output Enable goes to 3 drivers TX LVTTL input from FPGA i LVDS driver Differential output to D connector TX RX LVTTL output to FPGA Differential input LVDS receiver from D connector RX 100 Ohm termination resistor The IL715 3 galvanic isolators require a simple initialisation sequence before use Simply toggle the driving pins from the FPGA to the IL715 3 devices at start up Typically The TIMs are configured to route their McBSPs to the global bus connector pins which in turn are routed to the LVDS I O The following table shows the pin out for the 37 way D type connectors This is only applicable if the TIM is using non standard firmware which routes McBSP signals onto the global bus Contact Sundance for further information GND McBSP_CLKR
12. top jed Select the CPLD XC2C512 from the 3 components and download the file top jed e It can be found in Program Files Sundance SMT6048 FlashProgramming This is a one off operation iMPACT X SMT148FX Firmware CPLD synthesis smt148FX top default ipf Boundary Scan Db Ub File Edit View Operations Output Debug Window Help X DE BEX BRET i 230 9002 H BalBoundary Scan a SlaveSerial Ta SelectMAP lDesktop Configuration lDirect SPI Configuration E SystemACE xc4vfx60 xc2c512 xc3s1500 a PROM File Formatter file top jed usb2cpld bit mi Get Device ID mb Get Device Signature Usercode Check Idcode mb Read Status Register B Boundary Scan legacy input error status of GT3_CFG_B status of GUE status of GHIGH value of HODE pin H value of MODE pin Hi value of MODE pin HZ value of CFG RDY INIT B DONEIN input from DONE pin ID ERROR RESERVED RESERVED INFO iHPACT 2219 Status register values INFO iMPACT 0011 0111 0111 1000 0000 0000 0000 0000 INFO iMPACT 579 3 Completed downloading bit file to device INFO iMPACT 3 Checking done pin done 35 Programmed successfully PROGRESS_END End Operation Elapsed time 1 sec DOORRRRORRRO T tan cript lt ut Output Error Waring Configuration Parallel IV 5 MHz LPT1 Figure 1 SMT148FX JTAG chain 10 Application to program the Flash The Host can a
13. which may be introduced through the output cables Short circuiting any output to ground except the bi directional reset output does not cause the system to lock up or reboot 21 Ordering Information Several variations of this product are available SMT148 FX DC Standard product vvith on board voltage converters SMT148 FX ATX Standard product vvith ATX PSU input connector SMT148 FX nn Fxxx With additional local ADC oscillator xxx refers to the oscillator frequency nn refers to power input type
14. 6 15 pipe_wrapper_ngc_14 IN 2 palo i 5 32 c13 root CP 15 TX pipe_wrapper_ngc_12 IN lt Default gt BN com sundance smt46 fx scs1500 fx60tofiash 33 c12 root CP 14 TX pipe_wrapper_ngc_7 IN 0 lt Default gt SE com sundance smt148 fx sc3s 1500 Tim 2Cpid 30 c11 root CP 13 RX pipe_wrapper_ngc_13 IN 0 lt Default gt com sundance smt148 fx sc3s1500 usb_default 0 c32 root CP 12 RX pipe_wrapper_ngc_16 IN 0 lt Default gt EE root 31 c10 root CP 11 TX pipe_wrapper_ngc_15 IN 0 lt Default gt CH fx2lprxtx ngc 20 c9 root 10 TX pipe_wrapper_ngc_5 IN 0 lt Default gt CH pipe_wrapper_ngc_8 21 root CP 9 RX pipe_wrapper_ngc_11 IN 0 lt Default gt CH pipe_wrapper_ngc_9 22 c7 root CP 8 RX pipe_wrapper_ngc_6 IN 0 lt Default gt pipe_wrapper_ngc_6 16 c6 root CP 7 TX pipe_wrapper_ngc_9 IN 0 lt Default gt si pipe_wrapper_ngc_7 17 c5 root CP 6 TX pipe_wrapper_ngc_3 IN 0 lt Default gt Tu pipe_wrapper_ngc_ 4 18 c4 root CP 5 RX pipe_wrapper_ngc_10 IN 0 lt Default gt i 237 19 c3 root CP 4 RX pipe_wrapper_ngc_4 IN 0 lt Default gt 4 c34 root CP 3 TX pipe_wrapper_ngc_17 1N 0 lt Default gt pipe_wrapper_ngc_5 28 c2 root 2 pipe_wrapper_ngc IN 0 lt Default gt pipe_wrapper_ngc_2 27 ci root CP 11RX pipe_wrapper_ngc_8 IN 0 lt Default gt pipe_wrapper_ngc_3 29 cO root CP 0 RX pipe_wrapper_ngc_2 IN 0 lt D
15. CP 13 cP 15 lepa cP tz cra CP 18 CP 17 CP 20 CP 19 Figure 9 Spartan comport connections User Manual SMT148FX Page 40 of 48 Last Edited 03 08 2009 11 42 00 op Qs 000000000000 o e v w w w 8 gu ml E 4 Figure 10 Spartan to Virtex 4 CPLD and USB comport connections The comport used to configure the Virtex 4 can t be re used after the FPGA configuration It s why the comport 5 is used in a Diamond project this comport is not connected on the PCB If you select one of the three comport available on the Virtex 4 as its configuration comport you will not be able to use this comport for data transfer after the FPGA configuration User Manual SMT148FX Page 41 of 48 Last Edited 03 08 2009 11 42 00 14 Spartan firmware explanation Sundance provides many Spartan firmwares you can design your own firmware in following the next instructions PE 3L Diamond 3L Diamond File Edit Navigate Search Project Diamond Run Window Help CS Ska 4AU HOQ 9 0 Q x EZ 3L Diamond 4 Diamond source view 22 E 7 7 5 4 Connections 22 8 com sundance fpga general release s heartbeat_wrapper_ngc DI com sundance fx2lp release Connections This is a list of all the current connections d E 75 Order Name From Source To Destination Type Pla pipe_wrapper_ngc 35 c14 root CP 1
16. JP16 provides several voltages and has the following pinout Pin number 12V 1 12V 2 5V 3 3 3V 4 GND 5 GND 6 GND 7 Key 8 Table 2 Power out pinout Connector position 8 is filled to prevent plugging in the power input cable the connectors are the same type A modified plug pin 8 removed must be used for power output 4 1 20 JTAG A single JTAG chain connects all 4 TIM sites and the JTAG in amp out connectors This chain is used with the TI Code Composer Studio software suite Although in essence it is a chain the chain exists internally to a Xilinx CPLD The CPLD drives and receives signals to the 4 TIM sites independently This allows JTAG clock frequencies in excess of 30MHz to work reliably The JTAG out JTAG2 connector can be connected to the JTAG in JTAG1 connector of other SMT148FX thus extending the chain see cable SMT503 All JTAG chaining and TIM bypass is performed within the CPLD 4 1 21 Local Clock for ADCs etc The full functionality of the SMT399 F is also included This comprises an external clock input phase shifter local OCXO and 4 way power splitter Selection between local OCXO and VGA is made with the position of a O Ohm resistor link This link labelled R125 is located on the reverse of the board near the RS232 s 9 way d connector Moving this link will not invalidate any warranty Some soldering is necessary to select between the two optio
17. P 1 root CP 2 root CP 16 TIM Site 1 1 T1CP1 T1CP3 T1CP4 root CP 4 root CP 5 root CP 6 root CP 7 TIM Site 2 T2CP0 T2CP1 T2CP3 T2CP4 root CP 8 root CP 9 root CP 10 root CP 11 TIM Site 3 T3CP0 T3CP1 T3CP3 T3CP4 root CP 12 rootCP 13 root CP 14 root CP 15 TIM Site 4 T4CP0 T4CP1 T4CP3 T4CP4 root CP 21 root CP 22 root CP 23 Virtex 4 comports V4CP0 V4CP1 V4CP3 root CP 3 Virtex 4 configuration CBUF root CP 17 root CP 18 root CP 19 root CP 20 Connection to another SMT148FX 1 JPCP3 JPCP4 Table 3 Spartan connections Don t forget to edit all the connection and select the ifclk clock domain and select D the right link starts up properties Edit a connection Provide details of the connection Connection name Connect from pipe_wrapper_ngc_1 0 Connect to root CP 2 clock ifclk Clock domain for connector Default ifclk Link starts up as transmitter O Link starts up as receiver Finish Cancel Figure 12 Connection properties At reset you must connect a comport from RX to TX or TX to RX For the default firmware the TICP3 of the TIM root processor is RX at reset to get its bitstream The Spartan firmware comport root CP 2 will have the link starts up as transmitter properties The next Diagram shows the Default firmware connection with all the connections properties SPARTAN 3 Figure 13 Default Spartan firmware diagram 15 DIP Switches S
18. T COMA MDC and MDIO TIM misc TCLK 2 4 48 Config d IIOF NMI 4 IACK 1 Reset 1 Individual resets to TIM sites Clock 3 CLKIN H1 and H3 RS232 All z Tx Rx Other 2 BDRESET CLK50 User Manual SMT148FX Page 28 of 48 Last Edited 03 08 2009 11 42 00 8 Virtex4 FPGA Bank Allocation Interface Bank Comment Global Bus A 5 12 Address 16 Data 4 Control STRB RDY WR PAGE Global Bus B 6 10 12 Address 16 Data 4 Control STRB RDY WR PAGE Global Bus C 8 12 Address 16 Data 4 Control STRB RDY WR PAGE Global Bus D 11 12 Address 16 Data 4 Control STRB RDY WR PAGE ZBT Bank 1 10 Clock uses GCK on bank ZBT Bank 2 12 Clock uses GCK on bank Ethernet 12 SHB 7 RS485 7 8 Direction control is on bank 8 ComPorts 11 5 2 ports per bank used LVDS 9 USB 8 Appears as a 16 bit SDB LEDs 5 9 Misc TIM 14344 RS232 5 Tx Rx RST Clock 5 TEEE1394 6 TIM reset 11 V4 to S3 interface 8 CLK DATA LOAD RESET This is shown graphically here 8 AAA AAA EL 1 o o e o o o ee eee eee ee eee eee eee eee eee ee ee eee me User Manual SMT148FX Page 30 of 48 Last Edited 03 08 2009 11 42 00 9 Programming the Cpid The cpld firmware is necessary to access the flash and to configure the SMT148 FX FPGAs Please use Xilinx download cable to download the cpld jedec file
19. VV4 Programming Erase of the Flash ON Flash Reads in a view to configure FPGAs OFF Table 4 Switch SVV4 The Spartan and Virtex 4 configuration sources can be identified using SVV3 The Jumpers 1 2 of SW3 are controlling the Spartan configuration The Jumpers 3 4 of SW3 are controlling the Virtex4 configuration SW3 Jumper 2 or jumper 4 Jumper 1 or Jumper3 Flash ON ON Comport OFF ON USB ON OFF Table 5 Switch SW3 The Comport as a source is a feature only supported for Virtex 4 configuration Examples When SW4 1 is OFF Both devices configure from Flash ON ON JON ON Direct configuration via USB ON OFF ON OFF needs a host application to send the bitstreams via USB Configuration of Spartan via Flash and of Virtex 4 via CP3 OFF ON ON ON connected to TIM site 1 CPO Table 6 Examples of Switch configuration The Spartan is always the device configured first Do not try to configure the Virtex 4 before configuring the Spartan or the configuration will fail When SW4 1 is ON SW3 4321 should be set to ON ON ON ON 16 Support Packages To be added 17 Physical Properties Dimensions 250 x 200mm VVeight 350g The following table indicates the power capabilities of the on board supplies Option A B C Supply Current 12V 1 67A 0 83A 7 5V 10A 10A 3 3V 10A 10A 5V OA OA 12V OA 0 83A
20. X3 F30 J27 N28 R31 TX4 17 35 TX4 G32 H30 N30 R28 G30 K28 N29 R32 TX5 18 36 TX5 GND 19 37 GND The LVDS transmitters are enabled in groups Two groups per D connector Eg FPGA pin J30 is the transmitter enable for connector P3 s TX pins The LVDS receivers are continuously enabled and terminated by a 100 Ohm resistor 4 1 6 Firewire A single IEEE1394 interface is provided by an Agere FW801A PHY The following table shows the pinout of the connector Cable Power GND TPB TPB TPA TPA DU b CO ro This will allow high speed firewire data to be routed directly to the FPGA The standard FPGA firmware does not include an IEEE1394 IP core These are available from 3 parties Please contact Sundance for further information 4 1 7 USB2 The USB2 interface is provided by the Cypress CY7C68013A device The Cypress part in addition to providing USB functions with a FIFO type interface also contains a USART and an 8051 micro controller The USB connector pin out is shown here USB_ind Data Data GND l l EE The interface provided by this controller looks identical to a 16 bit SDB interface and is routed directly to the Spartan FPGA and the CPLD The standard Cypress firmware does not include functions to control the USART Please contact Sundance for further information The following table show
21. _Tx_0 McBSP_FSR_Tx_0 a 1 McBsP_DR_Tx_0 sl Gp GND 6 ciKx Tx or 25 McBSP_CLKX_Tx_0 7 mcpsp_rsx tx o 26 MeBSPFSX Tx 0 8 MeBsP DxIx0 zl MeBSPDX Tx0 Lal Gp GND ml Gop ul op gt 39 GND McBSP_CLKR_Tx_1 MCBSP_ESR_Tx_1 14 McBSP2DR Tx 1 32 MCBSP_DR Tx 1 Losch DR GND 16 MeBsp ciKx txt 34 McBSP_CLKX_Tx_1 iz wes mel L 0 35 McBSP_FSX_Tx_1 18 mcgsp_pxtxi 36 mcBSPDX Tx 1 ml Gp x GND As the LVDS drivers are connected directly to the FX60 FPGA they can be driven from this device without need for the above McBSP method The following table shows the connectivity between the FPGA and the D connectors P2 3 4 amp 5 FPGA Signal D D Signal FPGA signal pin 7 77 enable pin P2 P3 P4 P5 P2 P3 P4 P5 GND 1 20 GND D29 K29 M26 P31 RX0 2 21 RXO F31 C32 L30 P26 RX1 3 22 RX1 E32 D32 L31 P27 RX2 4 23 RX2 GND 5 24 GND D31 E29 K31 M31 TXO 6 25 TX0 E31 F29 K32 M32 TXl 7 26 TXI H27 J30 H32 N32 C29 J29 M25 P30 TX2 8 27 TX2 GND 9 28 GND GND 10 GND 11 29 GND C30 128 M28 P29 RX3 12 30 RX3 D30 L29 N27 R29 RX4 13 31 RX4 G31 H29 M30 R27 RX5 14 32 RX5 GND 15 33 GND H28 J31 132 P32 TX3 16 34 T
22. before but this time going from TIMI to TIM4 to TIM3 to TIM2 to TIMI The default dual TIM firmvvare com sundance smt148 fx sc3s1500 usb_default dual_TIM app provides the same comport connections as before but this time going from TIM4 to TIM1 to TIM2 to TIM3 to TIM4 For more advanced use the SMT148 FX Virtex4 FPGA is available for customisation A custom firmware for the Spartan to show that the Virex 4 can be part of the network of processors in a Diamond application is provided with com sundance smtl 48 fx sc3s1500 Tim2Cpld app The comport link used between TIM1 and the virtex4 is TIM1 CPO to Virtex4 CP3 this link is only for configuration and not yet available as a valid link after configuration will be in the next release Another link is declared and can be used for communicaton once the application is loaded The connections made are TIM1 CP4 to Virtex4 CP1 Feel free to make a Diamond application including a TIM on TIM site 1 and a design on the Virtex 4 Use the Diamond server to load the app and you should see the virtex 4 configuring do not forget to check the SMT148 FX switches A new firmware can be made for you or you can get the project to allow you to customise the Spartan at will 0 3 TIM SITE 4 TIM SITE 3 TIM SITE 2 TIM SITE 3 TIM SITE 1 TIM SITE 2 3 0 0 3 TIM SITE 1 TIM SITE 2
23. ccess the SMT148FX flash via the USB Before the Spartan is configured the CPLD provides a link to the USB It also is the Flash controller 10 1 Connections provided on the SMT148FX Coolrunner Il CPLD Switch control signals Flash control signals and address bus E Independent configuration control Common signals and buses for configuration purposes Independent configuration signals signals USB DEVICE USB DEVICE Configuration Switch SMT148FX D oC mo lt mu 11 Accessing the Flash This section describes the various steps to follow to access the Flash 11 1 Programming the Spartan Set the switches of the SMT148FX with SW3 4 3 2 1 ON ON ON ON and SW4 4 3 2 1 OFF OFF OFF ON SW4 1 ON provides Programming and erase accesses of the Flash SW4 1 OFF disables these accesses and enables read accesses only of the Flash in a view to program the FPGAs Reset or power off and on the SMT148FX evytime you change the switch settings 11 2 Erase and Program of the Flash Sundance provides 2 download utilities e The SMT6002 is a free utility downloadable with the Sundance wizard o The Spartan firmware MUST be located at address 0x0 o The Virtex 4 firmware MUST be located at address 0x800000 e The SMT6048 package provides a host utility called FlashUtility exe o Tick the option for the relevant FPGA and you can delete
24. e the 5V 3 3V 2 5V and 1 5V supply to the TIM sites carrier FPGA and other on board devices When using a 24V input the power consumption of an unpopulated SMT148X is approximately 6W Alternatively the input power can be provided at 9 to 18V using alternative DCDC parts Contact Sundance for further information The fan connectors FAN1 4 are powered directly from the input supply 4 1 18 Power input ATX version Power is supplied directly from an ATX style power supply connected to JP15 Note that most off the shelf PC ATX power supplies have a minimum load rating for their 12V output Typically this can be about 1A Fitting a couple of cooling fans is often sufficient Alternatively there are zero load power supplies available Eg Lambda NV 175 series NV1 453TTH N3 I Sundance are able to provide a power harness for this model The fan connectors FAN1 4 are powered at 12V The ATX Power Connector Pin Out is shown here 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Main 20 pin connector Name Pin Pin Name 3 3V 1 11 3 3V 3 3V 2 12 12V GND 3 13 GND 5V 4 14 ON input GND 5 15 GND 5V 6 16 GND GND 7 17 GND 5 8 18 I 9 19 5V 12V 10 20 5V Extension for BTX 12V 5V 3 3V GND 4 1 19 Power output Power can be supplied to external devices or modules The 8 pin connector Receptacle mini fit 8 Way Molex
25. efault gt CH pipe_wrapper_ngc_16 3 c31 pipe_wrapper_ngc_9 OUT 0 root CP 1 RX lt Default gt ES SMT148FX 2 c30 pipe_wrapper_ngc_8 OUT 0 root CP 7 TX lt Default gt C pipe_wrapper_ngc_15 6 c29 pipe_wrapper_ngc_7 OUT 0 root CP 8 RX lt Default gt a pipe_wrapper_ngc_14 7 c28 pipe_wrapper_ngc_6 OUT 0 root CP 14 TX lt Default gt pipe_wrapper_ngc_13 8 c27 5 OUT 0 root CP 4 RX lt Default gt 4 _ TEZZE 12 c26 pipe_wrapper_ngc_4 OUT 0 root CP 10 TX lt Default gt su pipe_wrapper_ngc_12 13 c25 pipe_wrapper_ngc_3 0 root CP 0 RX lt Default gt Y pipe_wrapper_ngc_11 14 c24 pipe_wrapper_ngc_2 OUT 0 root CP 6 TX lt Default gt CH pipe_wrapper_ngc_10 5 c35 17 OUT 0 root CP 12 RX lt Default gt eg pipe_wrapper_ngc_1 1 c33 pipe_wrapper_ngc_16 OUT 0 root CP 3 TX lt Default gt s heartbeat_wrapper_ngc 15 c23 pipe_wrapper_ngc_15 OUT 0 root CP 5 RX lt Default gt s pipe_wrapper_ngc_17 9 c22 pipe_wrapper_ngc_14 OUT 0 root CP 131RX lt Default gt Connections 10 c21 pipe_wrapper_ngc_13 OUT 0 root CP 15 TX lt Default gt AP wires 11 c20 pipe_wrapper_ngc_12 OUT root CP 9 RX spetto i 25 c19 pipe_wrapper_ngc_11 OUT 0 root CP 15 TX lt Default gt E com sundance smt148 fx sc3s1500 usb_default dual_TIM 26 c18 SET ED OUT m root CP 11 lt Default gt a m com sundance smt148 fx sc3s 1500 usb_defaui
26. is also configured by the CPLD and uses slave SelectMAP mode 8 bit parallel but is also part of the Xilinx JTAG chain 4 1 3 TIM Sites The 148FX provides 4 TIM sites In addition to the standard specification requirements the 148FX also provides the 3 3V supply to the two TIM mounting holes Each TIM site has 4 ComPorts connected directly to the Spartan 3 device The two remaining ComPorts are used to create a simple pipe with each site connecting to its nearest neighbours The TIM site s interrupt timer config and reset pins are all connected to the Virtex 4 FPGA The reset signals are asserted during power up when pressing the on board reset button or when signalled to via one of the external ComPort connectors A global bus connection 16 bit data 12 bit address is also made from each site to the Virtex 4 The global bus connector normally contains one 16 bit SDB interface this is unlike the TIM specification which describes the global bus as an Address Data structure These SDBs are the primary method of communication to the resources shared by the Virtex 4 eg USB Firewire etc 4 1 4 10 100 1000 Ethernet Phy A Marvell Ethernet PHY connects directly to the Virtex 4 FPGA This interfaces to a 10 100 1000 network via a standard RJ45 socket This socket has built in magnetics The PHY is controlled by a MAC within the Virtex 4 An Ethernet IP core is not supplied in the standard firmware Please contact Sundance
27. nk bi directional connection Fast communication between TIMs should use these links wherever possible 4 1 15 External ComPorts Four ComPorts are connected to SHB style connectors Two output type ComPorts 0 and 1 and two input type ComPorts 3 and 4 are provided All 4 ComPorts are connected to both SHB style connectors Connector A is arranged 0 1 3 and 4 and connector B 3 4 O and 1 With this scheme a simple one to one SHB cable can be used to connect connector A on one 148FX to connector B on another 148FX External Comports 0 1 3 and 4 are routed to two SHB connectors Samtec OSH 030 01 to allow connection to another SMT148FX carrier and its ComPorts The pin out is as follow 1 STRB_O 2 RDY_0 3 4 5 DO_O 6 D1_0 7 020 8 D3_0 9 D4_0 10 D5_0 11 D6_0 12 D7_0 13 14 15 STRB_1 16 RDY_1 17 REQ_1 18 ACK_1 19 DO_1 20 1DI 1 21 D2_1 22 1 D3 1 23 D4_1 24 D5_1 25 D6_1 26 D7_1 27 28 29 STRB_3 30 RDY_3 31 REO_3 32 ACK_3 33 D0_3 34 D1_3 35 D2_3 36 D3_3 37 D4_3 38 D5_3 39 D6_3 40 D7_3 41 42 43 STRB_4 44 RDY_4 45 REO_4 46 4 47 004 48 1014 49 1024 50 D3_4 51 D4_4 52 054 53 D6_4 54 D7_4 55 56 57 58 59 60 RESET Compatible with the 148 and 148LT an active low RESET signal is provided When two 148FX boards are interconnected with a 60 way cable as
28. ns J1 4 are outputs from a power splitter which is fed from the OCXO These outputs are intended for the Sundance range of ADC DAC modules Connector J5 is used for an external clock input which enters the VGA variable gain amplifier 4 1 22 Fan Power Four two pin connectors are provided to supply fans using power directly from the power input connector Note that if power is provided via an ATX type supply then these fan connectors will be powered at 12V 4 1 23 Reset Scheme A power rail monitor observes the state of the 3 3V supply This device will generate a reset to the SMT148FX RESET148 during power up or if the 3 3V supply drops below 3V This signal is an open collector output and is also driven to the inter card ComPort connector and thus to another SMT148FX The POR power on reset signal is driven to the RESETOUT pin on the external ComPortl connector The RESETIN pin on the above connector is buffered by an open collector device which in turn can also drive the RESET148 signal An additional 4 pin header is provided to allow other devices to share the open collector RESET1 48 signal The TIM reset pins are connected to the FPGA and will be reset when RESET148 is active as well as when some firmware conditions trigger a reset to the different TIMs see Firmware description for more details about TIM reset 4 1 24 External FPGA Clock Input Located near the DSP JTAG headers connector J6 provides a direct
29. s the Cypress pin connectivity to the Sundance SDB signal SDB Signal Cypress Pin CLK IFCLK DO PBO D1 PB1 D2 PB2 D3 PB3 D4 PB4 D5 PB5 D6 PB6 D7 PB7 DS PDO D9 PD1 D10 PD2 D11 PD3 D12 PD4 D13 PD5 D14 PD6 D15 PD7 VVEN RDYO REQ CTL2 ACK RDYI UDO PA7 001 RDY3 4 1 8 RS232 Two devices generate RS232 data simple TX and RX the FPGA and the USB2 controller The Rx data pin from a 9 way D type connector is connected to both serial interfaces The Tx data pin from each device is routed to a jumper block JP12 which allows the selection of one Tx data output The RS232 levels are generated using a MAX3227 converter TX GND DMI Uy RP WIN Insert only one jumper in positions shown in section 7 4 1 9 Flash The flash memory connected to the CPLD and contains configuration data for the two FPGAs Any additional space within this device can be used to store application programs The flash can be directly programmed by the CPLD only The external ComPort is directly connected to the CPLD This allows the reprogramming of the flash using an identical procedure as that employed on the SMT348 After configuration the CPLD ComPort is tri stated and the external ComPort functions as an input to the ComPort switch Spartan 3 4 1 10 RS485 Each of the 16 RS485 signal pairs is driven by an
30. sembly the RESET is propagated from one 148FX to the other Another ComPort is available via a 26 way connector where cable SMT502 can be used to connect to a SMT3100 and download applications from a PC This connector has the following pin out 1 CSTRB 2 GND 3 CRDY 4 GND 5 CREQ 6 GND 7 CACK 8 GND 9 DO 10 D1 11 D2 12 D3 13 D4 14 D5 15 D6 16 D7 17 3 3V 18 GND 19 RESETOUT 20 GND 21 RESETIN 22 GND 23 NC 24 NC 4 1 16 Internal ComPorts Each TIM site has 6 ComPorts Four of these are connected directly to the Spartan 3 FPGA These are ComPorts 0 1 3 amp 4 ComPorts 2 amp 5 are connected between TIM sites in a pipe configuration as follows TIM1 ComPort 2 connects to TIM2 ComPort 5 TIM2 ComPort 2 connects to TIM3 ComPort 5 TIM3 ComPort 2 connects to TIM4 ComPort 5 TIM4 ComPort 2 connects to TIM ComPort 5 4 1 17 Power input DC version Power is supplied from an external source The voltage of the external source needs to be in the range 18V to 30V This enters the board via an 8 pin connector Receptacle mini fit 8 Way Molex JP14 18 30V 18 30V 18 30V 18 30V GND GND GND GND 8 NE OD Up BP wl rm e Table 1 Power in connector pinout The external source is input to a DC DC converter module which produces 12V to the TIM sites It is also used as an input to two DC DC converters that produc
31. t DVIP 23 c17 pipe_wrapper_ngc_1 OUT 0 root CP 2 TX lt Default gt com sundance smt148 fx sc3s1500 usb_default sdrkit2 24 c16 pipe_wrapper_ngc OUT 0 fx2lprxtx ngc unnamed 0 lt Default gt com sundance smt148 fx sc3s1500 usb_default_anticlockwise 34 c15 fx2lprxtx_ngc unnamed pipe_wrapper_ngc_1 IN 0 lt Default gt com sundance smt148fx fx60 led 4 gt Figure 11 Default Spartan firmware project The firmware must contain the clock manager task SMT148FX_CM The clock domain named here ifclk must be used for all the tasks and all the connections The SMT148FX_CM task is used to generate this clock domain at 48MHz it s the only one that uses the default clock The heartbeat_wrapper_ngc task corresponds to the LED Spartan status this task just has to be added to the project and doesn t need any connection The fx2lprxtx_ngc task corresponds to the USB connection connect this task to your root processor location for the default firmware it s T1CP3 Between all the connections you must add a pipe_wrapper_ngc task You have to connect the two comport direction for example with the default firmware for the connection between the USB and the T1CP3 we will have fx2Iprxtx_ngc pipe_wrapper_ngc_1 root CP 2 TX root CP 2 TX lt gt pipe_wrapper_ngc lt gt fx2lprxtx_ngc The Spartan comport connection is list in the following table root CP 0 root C
32. ted Documents 2 1 Referenced Documents Sundance SLB specification hyperlink Sundance RSL specification hyperlink Datasheets as specified above Texas Instruments Module specification SMT118 Carrier with 3 Module sites and I O facilities SMT180 Carrier with 8 Module sites 3 Acronyms Abbreviations and Definitions 3 1 Acronyms and Abbreviations A list of acronyms etc hyperlink sng Ieqolo YOUMS HOdul00 g ueyeds Svir Hod dew joajeg SHO quo xol jonuoo uonein nuoo yed i 0140 ovir 4 Functional Description 4 1 Block Diagram SV LP od dew joejes 8109 AZ ebexoed ZSL 43 09X 4AYOX PXSHIA 4 1 1 Virtex 4 FX The primary controlling device on the 148FX is the Xilinx Virtex4 FX60 FPGA This device is an FF1152 package which provides 16 MGTs high speed serial I O and 576 normal I O signals This device can be configured via a Xilinx compatible JTAG header In normal operation this device is configured by the CPLD XC2C512 The configuration data is stored in flash memory and is loaded using slave SelectMAP mode 8 bit parallel 4 1 2 Spartan 3 The Xilinx Spartan 3 device is similar in nature to that employed on the SMT150Q and SMT329 carrier boards It acts as a pre configured ComPort routing switch Different ComPort routing schemes are easy to implement using supplied tools requires Xilinx ISE development software This device
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