User`s Manual
Contents
1. 53 CLS 211 Dump Example continued BG tj PR PQ PQ PQ PX gt 6 0 00 000 t Hr Hj Hj Hj Hj Hj 0x0000 0x0000 0x0000 0x0000 0x00 0x00 0x00 0x00 0x0000 0x0000 0x0000 0x0000 0x00 DIO DD CD CCD CS 0 0x01 x00 x00 x00 x01 x01 x01 x01 x01 x01 x01 0x00 0x00 Oxtt tt tH 0x14 0x01 0x00 0x00 0x0000 0x00 0x00 0x01 0x30 DL DS Na Ta Nan Na 54 DIOS opa 0 OD 10 0 00 00 00 OD 0 o Bp 6 6 CO 6 RAN es co 1 5 Typical Application A typical CLS 211 Camera Link Simulator application is shown in Figure 1 12 The CLS 211 is being used to simulate a 4 tap 8 bit medium configuration area scan camera To support this medium configuration application two standard Camera Link cables are connected between the CLS 211 and the frame grabber Note that base configuration applications require only one cable To control the CLS 21 1 the included serial cable connects the CLS 211 to a standard PC serial port An example configuration file cls211_example txt with user selected parameters is shown in Table 1 4 HyperTerminal included with Windows or oth2. The CLS 211 is housed in a sturdy aluminum enclosure The body is extruded aluminum with detachable front and rear endplates The enclosure incorporates a mounting flange The flange contains four predrilled holes for convenient equipment mounting The mounting holes are 11 64 diameter and are suitable for 8 machine screws A mounting hole template drawing is provided in Figure 3 2 Vivid Engineering Camera Link Simulator CLS 211 ae le eje MEDIUM FULL 5595992522 2 Figure 3 1 CLS 211 Cabinet Dimensions Front Panel Mounting Holes 4 11 64 dia 6 00 Rear Panel 5 85 6 25 Figure 3 2 Mounting Hole Template 3 2 External Power Supply The CLS 211 is powered by 5 7 VDC and incorporates a standard 2 1 x 5 5 mm DC power jack Power plug polarity is center positive The multi nation wall mount power supply handles a wide power range 90 264 VAC 47 63 Hz and comes with a set of outlet plugs suitable for most countries US Europe UK etc The CLS 211 is protected by an internal resettable fuse 67 4 Revision History Table 5 1 CLS 211 User s Manual Revision History Document ID Date Changes 200463 1 0 3 31 05 Initial release of manual 200463 1 1 5 27 05 Minor updates 68
3. 1 6 Specifications 2 INTERFACE 2 1 Front Panel Connections 2 1 1 Camera Connector Signals 2 1 2 Cable Shield Grounding 2 2 Rear Panel 2 2 1 DB9 Connector Signals 3 MECHANICAL 3 1 Dimensions 3 2 External Power Supply 4 REVISION HISTORY 53 55 59 60 60 61 64 66 66 67 68 1 Introduction 1 1 Overview The CLS 211 Camera Link simulator is a high performance video test pattern generator supporting all Camera Link configurations base medium full Fully programmable video timing enables the CLS 211 to mimic the timing characteristics of virtually any Camera Link camera with video clock rates up to 85 MHz The CLS 211 is controlled using any PC workstation or terminal with a standard RS 232 serial port CLS 211 control is performed via a simple straightforward Command Line Interface CLI No special software is required Template configuration files are easily modified with user parameters and downloaded to the CLS 211 CLS 211 default power up configuration is user programmable This provides convenient recall of saved parameters and enables CLS 211 operation without a host computer The CLS 211 also accepts configuration files developed for our original CLS 201 simulator The CLS 211 Camera Link Simulator is extremely useful for the development test integration and field service of Camera Link products and systems Housed in a sturdy aluminum enclosure the CLS 21
4. 19 1 4 Command Line Interface CLI The CLS 211 Camera Link Simulator incorporates a Command Line Interface CLI which enables CLS 211 control and monitoring using virtually any PC workstation or terminal The CLS 211 requires no special software Once the CLS 211 is connected to a host computer RS 232 port the user accesses the CLS 211 using standard communications software Hyper Terminal Y included in the Windows software works well as does almost any basic communications software package By default the CLS 211 echoes back all characters received The Echo Control ECHO command enables the user to enable disable echo Disabling echo is sometimes desired in particular when large configuration files are being downloaded to the CLS 211 Serial port settings are listed in Section 1 3 7 HyperTerminal Note The CLS 211 serial port interface does not incorporate flow control While data buffering is performed it is still possible to overrun the CLS 211 receive buffer especially when downloading large configuration files This will be visible as lost characters on the console and or invalid entry responses from the CLS 211 The following methods may be used to avoid these problems 1 Turn off message echo when downloading large configuration files Turning of echo is performed via the Echo Control ECHO command 2 In HyperTerminal click on the Files menu Then click on Properties Settings ASCII Setup and ente
5. 1 0x1 Horizontal Wedge 2 0x2 Vertical Wedge 3 0x3 Diagonal Wedge Type Read Write Write Example H_PATSEL 0x3 Read Example H PATSEL 2 30 1 4 19 Pixel A Fixed Value A FIXED The Pixel A Fixed Value A FIXED command determines the pixel A value when the fixed pattern is selected A PATSEL 0 The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL_MODE command See Section 1 3 4 for further information Parameter A FIXED Range Depends on pixel size 0 65535 hex 0x0 OXFFFF max Type Read Write Write Example A FIXED 0xA5A5 Read Example A FIXED 1 4 20 Pixel 8 Fixed Value B FIXED The Pixel B Fixed Value B FIXED command determines the pixel B value when the fixed pattern is selected B PATSEL 0 The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL MODE command See Section 1 3 4 for further information Parameter B FIXED Range Depends on pixel size 0 4095 hex 0x0 OxF FF max Type Read Write Write Example B FIXED 0x5A5 Read Example B FIXED 31 1 4 21 Pixel C Fixed Value C FIXED The Pixel C Fixed Value C FIXED command determines the pixel C value when the fixed pattern is selected C PATSEL 0 The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL MODE command
6. FVAL LO 2 Frame Valid High 512 lines FVAL HI 512 Frame Valid Setup 0 clocks FVAL SETUP 0 Frame Valid Hold 0 clocks FVAL HOLD 0 X Offset 8 clocks X OFFSET 8 X Active 512 clocks X ACTIVE 54 2 Y Offset 0 lines Y OFFSET 0 56 Y Active 512 lines Y_ACTIVE 51 2 Pixel A B C D E F G H Pattern Select a h diagonal wedge 3 A PATSEL B PATSEL C PATSEL D PATSEL E PATSEL F PATSEL G PATSEL H PATSEL CO CO CO 00 CO LV ly CO Pixel A B C D E F G H Fixed Value a h 0 8 2 gt 3 7 R Hulu zj nj XX XX pA KM gt Ed 2 2 0 0 0 m A B C D E F G H BacRground Value h 0 Pixel A B C D E F G H pattern step size h 1 patterns increment by 1 Camera LinX Mode mode full 8x8 15 CL MODE 5 57 Pattern Roll roll disabled 0 ROLL 0 Clock Synthesizer Code Not used using Clock Frequency instead SYNTH CODE 0x33543D Clock Frequency 20 MHz FREQUENCY 20 Continuous Mode continuous mode enabled 1 CONTINUOUS 1 Exsync Enable exsync triggering disabled 0 EXSYNC_ENB 0 Exsync Select CCl rising edge 0 EXSYNC SEL 0 integration time 0 0 mS delay disabled NTEG TIME 0 58 Linescan
7. In the Crystal Load Capacitance box select 007 Click on the Calculate button Example Running the tool for a desired frequency of 27 375 MHz will return several codes based on best accuracy lowest jitter etc The best accuracy code is 0x248939 To load this code into CLS 211 type SYNTH CODE 0x248939 at the command line prompt 1 3 2 Timing Generator The CLS 211 Camera Link Simulator timing generator establishes the basic video timing characteristics by generating the Line Valid LVAL and Frame Valid FVAL timing signals The circuit operates at the reference clock frequency programmed into the clock synthesizer LVAL is used to envelope lines of video data and is defined in the Camera Link specification as high for valid line data Two CLS 211 timing parameters LVAL LO and LVAL HI determine the duration of LVAL low and high states in pixel clock cycles respectively The frequency of the pixel clock is determined by the clock synthesizer The CLS 211 supports LVAL low and LVAL high times from 1 65535 pixel clocks LVAL timing characteristics are shown in Figure 1 2 Note The LVAL timing signal is continuously output whenever the CLS 211 is operated in framescan mode For linescan mode LVAL is continuous when in operating in continuous mode For linescan mode with exsync triggering a single LVAL pulse is issued in response to each triggering event Line Valid LVAL QUE A ED e a ES ys Line Va
8. PATSEL parameters are defined in Table 1 1 Table 1 1 PATSEL Parameter Definition Pattern Select Value A PATSEL B PATSEL C PATSEL D PATSEL Video Test Pattern E PATSEL PATSEL G PATSEL PATSEL Fixed Value rectangular Horizontal Wedge Vertical Wedge Diagonal Wedge For the fixed value pattern eight Pixel Fixed Value A FIXED B FIXED C FIXED D FIXED E FIXED F FIXED G FIXED H FIXED parameters are provided to individually select static pixel values for the up to eight pixels that are being simultaneously output 13 The CLS 211 enables the user to select background pixel values These are the default output pixel values at all times outside the active video region defined by the window generator The CLS 211 enables the user to individually select the background value for each of the up to eight pixel outputs A B C D E F G H To support this feature eight Pixel Background Value A BACK 5 BACK C BACK D BACK E BACK F BACK G BACK H BACK parameters are provided The CLS 211 provides a selectable pixel step size when generating wedge horizontal vertical diagonal The step size determines the amount by which pixel values are incremented from pixel to pixel in the test patterns The default setting of 1 causes the pixel values to increment by 1 Step sizes of 2 4 8 16 32 64 and 128 are also supported The pixel step size feature is particul
9. 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL MODE command See Section 1 3 4 for further information Parameter C STEP Settings 1 0x1 Increment by 1 0 1 2 2 0x2 Increment by 2 0 2 4 4 0x2 Increment by 4 0 4 8 8 0x8 Increment by 8 0 8 16 16 0x10 Increment by 16 0 16 32 32 0x20 Increment by 32 0 32 64 64 0x40 Increment by 64 0 64 128 128 0x80 Increment by 128 0 128 256 Type Read Write Write Example C_STEP 0x2 Read Example C_STEP 2 40 1 4 38 Pixel D Pattern Step D STEP The Pixel D Pattern Step D STEP command determines the amount by which the D pixel value increments in the wedge horizontal vertical diagonal video test patterns The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL MODE command See Section 1 3 4 for further information Parameter D STEP Settings 1 0x1 Increment by 1 0 1 2 2 0x2 Increment by 2 0 2 4 4 0x2 Increment by 4 0 4 8 8 0x8 Increment by 8 0 8 16 16 0x10 Increment by 16 0 16 32 32 0x20 Increment by 32 0 32 64 64 0x40 Increment by 64 0 64 128 128 0x80 Increment by 128 0 128 256 Type Read Write Write Example D STEP 0x2 Read Example D STEP 1 4 39 Pixel E Pattern Step E STEP The Pixel E Pattern Step
10. BACK 37 1 4 33 Pixel G Background Value G BACK The Pixel G Background Value G BACK command determines the default value for video data pixel G The default value is output whenever the CLS 211 is not outputting video test pattern data The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL MODE command See Section 1 3 4 for further information Parameter G BACK Range 0 255 hex 0x0 OxFF Type Read Write Write Example G BACK 0xC3 Read Example G BACK 1 4 34 Pixel H Background Value H BACK The Pixel H Background Value H BACK command determines the default value for video data pixel H The default value is output whenever the CLS 211 is not outputting video test pattern data The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL MODE command See Section 1 3 4 for further information Parameter H BACK Range 0 255 hex 0x0 OxFF Type Read Write Write Example H BACK 0xC3 Read Example H BACK 38 1 4 35 Pixel A Pattern Step A STEP The Pixel A Pattern Step A STEP command determines the amount by which the A pixel value increments in the wedge horizontal vertical diagonal video test patterns The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL_ MODE command See Section 1 3 4 for further inform
11. Camera Link Configuration File syntax example VAL LO 0x0020 hexadecimal notation VAL HI 500 decimal notation Fval lo 0x20 hexadecimal notation Methods for downloading text txt files to the CLS 211 vary depending on the communications software used For HyperTerminal included with Windows click on the Transfer toolbar and select Send Text File HyperTerminal will then prompt for the location of the file The CLS 211 command set is defined in the following sections 21 1 4 1 Line Valid Lovv LVAL LO The Line Valid Low LVAL LO command is used to establish the duration in clock cycles for the low logic 0 portion of the Camera Link Line Valid timing signal See Section 1 3 2 for further information Parameter LVAL LO Range 1 65535 clocks hex 0x1 OxFFFF Type Read Write Write Example LVAL LO 0xA000 Read Example LVAL LO 1 4 2 Line Valid High LVAL HI The Line Valid High LVAL HI command is used to establish the duration in clock cycles for the high logic 1 portion of the Camera Link Line Valid timing signal See Section 1 3 2 for further information Parameter LVAL HI Range 1 65535 clocks hex 0x1 OxXFFFF Type Read Write Write Example LVAL HI 0xB000 Read Example LVAL HI 22 1 4 3 Frame Valid Lovv FVAL LO The Frame Valid Low FVAL LO command is used to establish the duration in lines for the low logic 0 portion of the Camera
12. FG X1 3 CLS 211 FG X1 16 CLS 211 FG X2 4 CLS 211 FG X2 17 CLS 211 FG Xclk 5 CLS 211 FG Xclk 18 CLS 211 FG X3 6 CLS 211 FG X3 19 CLS 211 FG SerTC 7 FG gt CLS 211 serial comm SerTC 20 FG gt CLS 211 SerTFG 8 CLS 211 FG serial comm SerTFG 21 CLS 211 FG x CC1 9 FG CLS 211 CC1 22 FG CLS 211 CC2 10 FG CLS 211 CC2 23 FG gt CLS 211 CC3 11 FG CLS 211 CC3 24 FG gt CLS 211 CC4 12 FG CLS 211 CC4 25 FG CLS 211 Inner shield 13 N A tied to digital ground Inner shield 26 N A tied to digital ground FG Frame Grabber 62 Table 2 2 CLS 211 Medium Full Connector y Medium Full alia Signal Direction Notes camera pinout Inner shield 1 N A tied to digital ground Inner shield 14 N A tied to digital ground YO 2 CLS 211 FG YO 15 CLS 211 FG Y1 3 CLS 211 FG Y1 16 CLS 211 FG Y2 4 CLS 211 FG Y2 17 CLS 211 FG Yelk 5 CLS 211 FG Yclk 18 CLS 211 FG Y3 6 CLS 211 FG Y3 19 CLS 211 FG 100 ohm 7 N A 100 ohm termination 7 20 terminated 20 N A 100 ohm termination 7 20 0 8 CLS 211 FG 0 21 CLS 211 FG 1 9 CLS 211 FG 1 22 CLS 211 FG Z2 10 CLS 211 FG Z2 23 CLS 211 FG Zclk 11 CLS 211 FG Zclk 24 CLS 211 FG Z3 12 CLS 211 FG Z3t 25 CLS 211 FG Inner shi
13. Section 1 3 5 for further information NOTE ALWAYS SET REGISTER TO 0 WHEN NOT USING THIS FEATURE Parameter INTEG TIME Range 0 65535 mS hex 0x0 OXFFF Type Read Write Write Example INTEG TIME 0x4000 Read Example INTEG TIME 1 4 51 Linescan Mode LINESCAN The Linescan Mode LINESCAN command places the CLS 211 in linescan mode When linescan mode is disabled the CLS 211 defaults to framescan mode See Section 1 3 2 for further information Parameter LINESCAN Settings 0 0x0 Framescan Mode 1 0x1 Linescan Mode Type Read Write Write Example LINESCAN 0x0 Read Example LINESCAN 49 1 4 52 DVAL State DVAL The DVAL State DVAL command determines the static state of the Camera Link Data Valid output signal Parameter DVAL Settings 0 0x0 DVAL output set to O 1 0x1 DVAL output set to 1 Type Read Wnte Write Example DVAL 0x0 Read Example DVAL 1 4 53 CC State CC The CC State CC command is used to read the current state of the Camera Link camera control inputs CC1 CC2 CC3 CC4 This register is read only See Section 1 3 8 for further information Parameter CC Bit positions bit 0 CCI lsb bit 1 CC2 bit 2 CC3 bit 3 CC4 bit 4 7 0 Type Read Read Example CC 50 1 4 54 FPGA Version VERSION The FPGA Version VERSION command is used to read the hardware version code for the CLS 211 Field Programmable Gate Array FPGA device The standard vers
14. See Section 1 3 4 for further information Parameter C FIXED Range Depends on pixel size 0 4095 hex 0x0 OxFFF max Type Read Write Write Example C FIXED 0x3C3 Read Example C FIXED 1 4 22 Pixel D Fixed Value D FIXED The Pixel D Fixed Value D FIXED command determines the pixel D value when the fixed pattern is selected D PATSEL 0 The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL MODE command See Section 1 3 4 for further information Parameter D FIXED Range Depends on pixel size 0 4095 hex 0x0 OxF FF max Type Read Write Write Example D FIXED 0xC3C Read Example D FIXED 32 1 4 23 Pixel E Fixed Value E FIXED The Pixel E Fixed Value E FIXED command determines the pixel E value when the fixed pattern is selected E PATSEL 0 The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL MODE command See Section 1 3 4 for further information Parameter E FIXED Range 0 255 hex 0x0 OxFF Type Read Write Write Example E FIXED 0x3C Read Example E FIXED 1 4 24 Pixel F Fixed Value F FIXED The Pixel F Fixed Value F FIXED command determines the pixel F value when the fixed pattern is selected F PATSEL 0 The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL MODE command See
15. the camera control inputs CC1 CC2 CC3 CC4 The exsync camera control input source and active edge are selected using the EXSYNC_SEL command See Section 1 3 8 for further information Parameter EXSYNC_ENB Settings 0 0x0 Exsync Triggering Disabled 1 0x1 Exsync Triggering Enabled Type Read Write Write Example EXSYNC_ENB 0x1 Read Example EXSYNC ENB 2 1 4 49 Exsync Select EXSYNC SEL The Exsync Select EXSYNC SEL command select which camera control input and active edge is used when generating exsync triggered video patterns The CLS 211 supports exsync triggered frame generation using any of Camera Link camera control inputs The triggering edge is selectable as rising low to high transition or falling high to low transition See Section 1 3 8 for further information Parameter EXSYNC SEL Settings 0 0x0 CCI rising edge 1 0x1 001 falling edge 2 0x2 CC2 rising edge 3 0x3 CC2 falling edge 4 0x4 CC3 rising edge 5 0x5 CC3 falling edge 6 0x6 CCA rising edge 7 0x7 CCA falling edge Type Read Write Write Example EXSYNC_SEL 0x7 Read Example EXSYNC_SEL 1 4 50 Integration Time INTEG TIME The Integration Time INTEG TIME command determines the amount of time in milliseconds to delay the generation of video frames to simulate camera integration 48 exposure characteristics The INTEG TIME command may be used in both triggered exsync and continuous modes See
16. the video test pattern When disabled the wedge test patterns are static no change from frame to frame See Section 1 3 4 for further information Parameter ROLL Settings 0 0x0 Roll disable 1 0x1 Roll enabled Type Read Write Write Example ROLL 0x1 Read Example ROLL 45 1 4 45 Clock Synthesizer Code SYNTH CODE The Clock Synthesizer Code SYNTH CODE command enables the user to directly enter a 24 bit code into the clock synthesizer device that generates the CLS 211 reference clock This allows the user to program the reference clock to virtually any frequency in the 20 85 MHz extended Camera Link range Two commands are provided in the CLS 211 to establish pixel clock frequency SYNTH CODE and FREQUENCY SYNTH CODE provides maximum flexibility by allowing direct entry of the 24 bit synthesizer code FREQUENCY provides convenience by allowing the user to select any integer frequency value between 20 and 85 The most recent SYNTH CODE or FREQUENCY command determines the frequency Reads of the clock command not used returns HHH Reads of the clock command used return a value See Section 1 3 1 for further information NOTE MUST BE ENTERRED IN HEXADECIMAL 0x NOTATION Parameter SYNTH CODE Settings 24 bit Synthesizer Device Code Hex Type Read Write Write Example SYNTH CODE 0x33543D Read Example SYNTH CODE 46 1 4 46 Clock Frequency FREQUENCY The Clock Frequency FREQUENCY command en
17. 0 Increment by 16 0 16 32 32 0x20 Increment by 32 0 32 64 64 0x40 Increment by 64 0 64 128 128 0x80 Increment by 128 0 128 256 Type Read Write 43 Write Example H STEP 0x2 Read Example H STEP 1 4 43 Camera Link Mode CL MODE The Camera Link Mode CL MODE command determines the test pattern pixel format The CLS 211 generates video test patterns for all Camera Link modes supported by the Camera Link base medium and full configurations See Section 1 3 4 for further information Parameter Settings Type CL MODE 0 0x0 8 bit x 1 3 base config 1 0x1 10 bit 1 2 base config 2 0x2 12 bit x 1 2 base config 3 0x3 14 bitx 1 base config 4 0x4 16 bit x 1 base config 5 0x5 24 bit RGB base config 8 0x8 8 bit x 4 medium config 9 0x9 10 bit x 3 4 medium config 10 0xA 12 bit x 3 4 medium config 11 0xB 30 bit RGB medium config 12 0xC 36 bit RGB medium config 15 0xF 8 bit x 8 full config Read Write Write Example CL MODE 0x2 Read Example CL MODE 44 1 4 44 Pattern Roll ROLL The Pattern Roll ROLL command adds motion to video test patterns Roll is used in conjunction with the horizontal diagonal or vertical wedge patterns When ROLL is enabled the starting pixel value is incremented every frame This changes all pixel values each frame and adds a rolling affect to
18. 1 is well suited for industrial environments 1 The Camera Link interface standard enables the interoperability of cameras and frame grabbers regardless of vendor The Automated Imaging Association AIA sponsors the Camera Link program including the oversight Camera Link Committee the self certification program and the product registry The Camera Link specification may be downloaded from the AIA website found at www machinevisiononline org Camera Link is a trademark of the Automated Imaging Association Windows is a trademark of Microsoft Corporation HyperTerminal is a trademark of Hilgraeve Inc CLS 211 Vivid Engineering Camera Link Simulator o uy le MEDIUM FULL o 1 2 Features A high performance video test pattern generator Supports all Camera Link configurations base medium full Fully programmable video timing mimics virtually any camera Advanced chipset supports video clock rates up to 85 MHz Area and line scan formats image sizes to 64Kx64K Box line horizontal vertical diagonal wedge test patterns Programmable video pattern step sizes Roll feature adds pattern motion Triggered exsync mode amp Integration timer Connects to host PC workstation terminal serial port RS 232 Controlled via a simple Command Line Interface CLI Example downloadable configuration file is easily modified w user settings Requires no special softwa
19. 128 256 Type Read Write Write Example F_STEP 0x2 Read Example F STEP 2 42 1 4 41 Pixel G Pattern Step G STEP The Pixel G Pattern Step G STEP command determines the amount by which the G pixel value increments in the wedge horizontal vertical diagonal video test patterns The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL MODE command See Section 1 3 4 for further information Parameter G STEP Settings 1 0x1 Increment by 1 0 1 2 2 0x2 Increment by 2 0 2 4 4 0x2 Increment by 4 0 4 8 8 0x8 Increment by 8 0 8 16 16 0x10 Increment by 16 0 16 32 32 0x20 Increment by 32 0 32 64 64 0x40 Increment by 64 0 64 128 128 0x80 Increment by 128 0 128 256 Type Read Write Write Example G_STEP 0x2 Read Example G_STEP 1 4 42 Pixel H Pattern Step H_STEP The Pixel H Pattern Step H_STEP command determines the amount by which the H pixel value increments in the wedge horizontal vertical diagonal video test patterns The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL_ MODE command See Section 1 3 4 for further information Parameter H_STEP Settings 1 0x1 Increment by 1 0 1 2 2 0x2 Increment by 2 0 2 4 4 0x2 Increment by 4 0 4 8 8 0x8 Increment by 8 0 8 16 16 0x1
20. CLS 211 CAMERA LINK SIMULATOR User s Manual Document 200463 Rev 1 1 05 27 05 O Vivid Engineering 418 Boston Turnpike 4104 Shrewsbury MA 01545 Phone 508 842 0165 Fax 508 842 8930 Email info vividengineering com Web www vividengineering com Table of Contents 1 INTRODUCTION 1 1 Overview 1 2 Features 1 3 Functional Description 1 3 1 1 3 2 1 3 3 Clock Synthesizer Timing Generator Window Generator Pattern Generator Integration Timer Microcontroller RS 232 Serial Port Camera Control Inputs Channel Link Transmitters 1 4 Command Line Interface CLI Line Valid Low LVAL_LO Line Valid High LVAL HD Frame Valid Low FVAL LO Frame Valid High FVAL HI Frame Valid Setup FVAL SETUP Frame Valid Hold FVAL HOLD X Offset X OFFSET X Active X ACTIVE Y Offset Y OFFSET Y Active Y ACTIVE Pixel A Pattern Select A PATSEL Pixel B Pattern Select B_PATSEL 1 4 13 1 4 14 1 4 15 1 4 16 1 4 17 1 4 18 1 4 19 1 4 20 1 4 21 1 4 22 1 4 23 1 4 24 1 4 25 1 4 26 1 4 27 1 4 28 1 4 29 1 4 30 1 431 1 4 32 1 4 33 1 4 34 1 4 35 1 4 36 1 4 37 1 4 38 1 4 39 1 4 40 1 4 41 1 4 42 1 4 43 1 4 44 1 4 45 1 4 46 1 4 47 1 4 48 1 4 49 1 4 50 1 4 51 1 4 52 1 4 53 1 4 54 1 4 55 1 4 56 1 4 57 1 4 58 Pixel C Pattern Select C PATSEL Pixel D Pattern Select D PATSEL Pixel E Pattern Select E PATSE
21. E STEP command determines the amount by which the E pixel value increments in the wedge horizontal vertical diagonal video test patterns The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL MODE command See Section 1 3 4 for further information Parameter E STEP Settings 1 0x1 Increment by 1 0 1 2 2 0x2 Increment by 2 0 2 4 4 0x2 Increment by 4 0 4 8 8 0x8 Increment by 8 0 8 16 16 0x10 Increment by 16 0 16 32 32 0x20 Increment by 32 0 32 64 64 0x40 Increment by 64 0 64 128 128 0x80 Increment by 128 0 128 256 Type Read Write 41 Write Example E STEP 0x2 Read Example E STEP 1 4 40 Pixel Pattern Step F STEP The Pixel F Pattern Step F STEP command determines the amount by which the F pixel value increments in the wedge horizontal vertical diagonal video test patterns The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL MODE command See Section 1 3 4 for further information Parameter F STEP Settings 1 0x1 Increment by 1 0 1 2 2 0x2 Increment by 2 0 2 4 4 0x2 Increment by 4 0 4 8 8 0x8 Increment by 8 0 8 16 16 0x10 Increment by 16 0 16 32 32 0x20 Increment by 32 0 32 64 64 0x40 Increment by 64 0 64 128 128 0x80 Increment by 128 0
22. EL 0x3 Read Example E PATSEL 1 4 16 Pixel F Pattern Select F PATSEL The Pixel F Pattern Select F PATSEL command assigns the test pattern for video data pixel F The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL MODE command See Section 1 3 4 for further information Parameter F PATSEL Settings 0 0x0 Fixed Value 1 Ox1 Horizontal Wedge 2 0x2 Vertical Wedge 3 0x3 Diagonal Wedge Type Read Write Write Example F PATSEL 0x3 Read Example F PATSEL 2 1 4 17 Pixel G Pattern Select G PATSEL The Pixel G Pattern Select G PATSEL command assigns the test pattern for video data pixel G The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL_ MODE command See Section 1 3 4 for further information Parameter G PATSEL Settings 0 0x0 Fixed Value 1 0x1 Horizontal Wedge 2 0x2 Vertical Wedge 3 0x3 Diagonal Wedge Type Read Write 29 Write Example G PATSEL 0x3 Read Example G PATSEL 2 1 4 18 Pixel H Pattern Select H PATSEL The Pixel H Pattern Select H_PATSEL command assigns the test pattern for video data pixel H The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL MODE command See Section 1 3 4 for further information Parameter H_PATSEL Settings 0 0x0 Fixed Value
23. FFSET 1 4 10 Y Active Y ACTIVE The Y Active Y ACTIVE command determines the vertical size y dimension of the test pattern in lines See Section 1 3 3 for further information Parameter Y ACTIVE Range 1 65535 lines hex 0x1 OXFFFF Type Read Write Write Example Y ACTIVE 0x5000 Read Example Y ACTIVE 26 1 4 11 Pixel A Pattern Select A PATSEL The Pixel A Pattern Select A PATSEL command assigns the test pattern for video data pixel A The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL_ MODE command See Section 1 3 4 for further information Parameter A PATSEL Settings 0x0 Fixed Value 0x1 Horizontal Wedge 0x2 Vertical Wedge 0x3 Diagonal Wedge Type Read Write Write Example A PATSEL 0x0 Read Example A PATSEL 1 4 12 Pixel B Pattern Select B PATSEL The Pixel B Pattern Select B PATSEL command assigns the test pattern for video data pixel B The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL MODE command See Section 1 3 4 for further information Parameter B PATSEL Settings 0 0x0 Fixed Value 1 0x1 Horizontal Wedge 2 0x2 Vertical Wedge 3 0x3 Diagonal Wedge Type Read Write Write Example B PATSEL 0x2 Read Example B PATSEL 27 1 4 13 Pixel Pattern Select C PATSEL The Pixel C Pattern Select C PATSEL
24. L Pixel F Pattern Select F PATSEL Pixel G Pattern Select G PATSEL Pixel H Pattern Select H PATSEL Pixel A Fixed Value A FIXED Pixel B Fixed Value B FIXED Pixel C Fixed Value C FIXED Pixel D Fixed Value D FIXED Pixel E Fixed Value E FIXED Pixel F Fixed Value F FIXED Pixel G Fixed Value G FIXED Pixel H Fixed Value H FIXED Pixel A Background Value A BACK Pixel B Background Value B BACK Pixel C Background Value C BACK Pixel D Background Value D BACK Pixel E Background Value E BACK Pixel F Background Value F BACK Pixel G Background Value G BACK Pixel H Background Value H BACK Pixel A Pattern Step A STEP Pixel B Pattern Step B STEP Pixel C Pattern Step C STEP Pixel D Pattern Step D STEP Pixel E Pattern Step E STEP Pixel F Pattern Step F STEP Pixel G Pattern Step G STEP Pixel H Pattern Step H STEP Camera Link Mode CL MODE Pattern Roll ROLL Clock Synthesizer Code SYNTH CODE Clock Frequency FREQUENCY Continuous Mode CONTINUOUS Exsync Enable EXSYNC ENB Exsync Select EXSYNC SEL Integration Time INTEG TIME Linescan Mode LINESCAN DVAL State DVAL CC State CC FPGA Version VERSION One Shot Trigger ONE SHOT Parameter Save SAVE Parameter Recall RECALL Echo Control ECHO 1 4 59 Parameter Dump DUMP 1 5 Typical Application
25. Link Frame Valid timing signal See Section 1 3 2 for further information Parameter FVAL LO Range 1 65535 lines hex 0x1 OXFFFF Type Read Write Write Example FVAL_LO 0xC000 Read Example FVAL LO 2 1 4 4 Frame Valid High FVAL HI The Frame Valid High FVAL HD command is used to establish the duration in lines for the high logic 1 portion of the Camera Link Frame Valid timing signal See Section 1 3 2 for further information Parameter FVAL HI Range 1 65535 lines hex 0x1 OxFFFF Type Read Write Write Example FVAL HI 0xD000 Read Example FVAL HI 23 1 4 5 Frame Valid Setup FVAL SETUP The Frame Valid Setup FVAL SETUP command determines the number of clock cycles that the rising edge of the Camera Link FVAL signal occurs in advance of the falling edge ofthe LVAL signal When FVAL SETUP is set to 0 the rising edge of FVAL is coincident with the falling edge of LVAL See Section 1 3 2 for further information Parameter FVAL SETUP Range 0 65535 clocks hex 0x0 OxFFFF Type Read Write Write Example FVAL SETUP 0xE000 Read Example FVAL SETUP 1 4 6 Frame Valid Hold FVAL HOLD The Frame Valid Hold FVAL HOLD command determines the number of clock cycles that the falling edge of the Camera Link FVAL signal occurs following the falling edge of the LVAL signal When FVAL HOLD is set to 0 the falling edge of FVAL is coincident with the falling edge of LVAL See Section 1 3 2 for furt
26. Mode linescan mode disabled framescan mode 0 LINESCAN 0 DVAL State dval signal state 1 DVAL 1 20 512x512 active image area 1 6 Specifications Table 1 5 CLS 211 Specifications Feature Specification Camera Interface Camera Link Spec base medium amp full configurations Camera Connectors 26 pin MDR type 2 Frequency Range 20 85 MHz Serial Port Interface RS 232 Serial Port Connector Male 9 pin D Sub DB9 Serial Port Cable 3 meter DB9 female DB9 female null modem cable Chipset National Semi DS90CR287 2 Power Supply US Europe Transformer w Outlet Plug Set Power Jack 2 1 5 5 mm center positive Power Requirements 5 7 VDC 700 mA typical Cabinet Dimensions 6 25 L x 1 14 H 6 16 D Weight 15 oz Operating Temperature Range 0 to 50 C Storage Temperature Range 25 to 75 C Relative Humidity 0 to 90 non condensing 59 2 Interface 2 1 Front Panel Connections The CLS 211 Camera Link Simulator front panel is shown in Figure 2 1 The front panel contains two video connectors for connecting to the frame grabber Camera Link medium amp full configurations utilize both video connectors Base configurations utilize only the base connector The camera connectors are 26 pin MDR type MDR 26 3M p n 10226 55G3VC as specified in the Camera Li
27. Section 1 3 4 for further information Parameter F FIXED Range 0 255 hex 0x0 OxFF Type Read Write Write Example F FIXED 0x3C Read Example F FIXED 33 1 4 25 Pixel G Fixed Value G FIXED The Pixel G Fixed Value G FIXED command determines the pixel G value when the fixed pattern is selected G PATSEL 0 The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL_MODE command See Section 1 3 4 for further information Parameter G_FIXED Range 0 255 hex 0x0 OxFF Type Read Write Write Example G_FIXED 0x3C Read Example G FIXED 7 1 4 26 Pixel H Fixed Value H FIXED The Pixel H Fixed Value H FIXED command determines the pixel H value when the fixed pattern is selected H_PATSEL 0 The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL_MODE command See Section 1 3 4 for further information Parameter H FIXED Range 0 255 hex 0x0 OxFF Type Read Write Write Example H FIXED 0x3C Read Example H FIXED 2 34 1 4 27 Pixel A Background Value A BACK The Pixel A Background Value A BACK command determines the default value for video data pixel A The default value is output whenever the CLS 211 is not outputting video test pattern data The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL MODE c
28. ables the user to select integer values for the Camera Link reference clock in the 20 85 MHz range Two commands are provided in the CLS 211 to establish pixel clock frequency SYNTH_CODE and FREQUENCY SYNTH_CODE provides maximum flexibility by allowing direct entry of the 24 bit synthesizer code FREQUENCY provides convenience by allowing the user to select any integer frequency value between 20 and 85 The most recent SYNTH CODE or FREQUENCY command determines the frequency Reads of the clock command not used returns HHH Reads of the clock command used return a value See Section 1 3 1 for further information Parameter FREQUENCY Range 20 85 MHz hex 0x14 0x55 Type Read Write Write Example FREQUENCY 0x14 Read Example FREQUENCY 1 4 47 Continuous Mode CONTINUOUS The Continuous Mode CONTINUOUS command enables continuous output of video test patterns When continuous mode is enabled the CLS 211 outputs continuous video data When disabled video pattern data is suspended awaiting an exsync pulse one shot or return to continuous mode See Section 1 3 2 for further information Parameter CONTINUOUS Settings 0 0x0 Continuous Mode Disabled 1 0x1 Continuous Mode Enabled Type Read Write Write Example CONTINUOUS 0x1 Read Example CONTINUOUS 2 47 1 4 48 Exsync Enable EXSYNC ENB The Exsync Enable EXSYNC ENB command enables triggered output of pattern frames or lines in LINESCAN mode using
29. arly valuable when working with high resolution i e 12 or 16 bit video The CLS 211 enables the user to individually select the step size for each of the up to eight pixel outputs A B C D E F G H To support this feature eight Pixel Step Size STEP 8 STEP 6 STEP STEP E STEP F STEP G STEP H_ STEP parameters are provided The CLS 210 roll feature used in conjunction with the wedge patterns horizontal vertical diagonal to introduce test pattem motion When roll is enabled the starting pixel value in the video test pattern increments every frame This changes all pixel values within the pattern every frame and adds a rolling motion to the displayed pattern This feature is particularly useful during testing and for debugging image acquisition problems The CLS 211 supports all modes defined in the Camera Link specification for the base medium and full configurations These modes range from simple 8 bit single tap to 12 bits by 4 taps to 8 bits by 8 taps The desired mode is selected using the Camera Link Mode CL MODE parameter The CL MODE parameter is defined in Table 1 2 For simplicity the CLS 211 refers to A B C D E F G H pixels not ports The CLS 211 outputs up to eight pixels simultaneously depending on Camera Link mode The pixel values are automatically mapped to the corresponding port assignments as defined in the Camera Link specification 14 Table 1 1 CL MODE Parame
30. ation Parameter A STEP Settings 1 0x1 Increment by 1 0 1 2 2 0x2 Increment by 2 0 2 4 4 0x2 Increment by 4 0 4 8 8 0x8 Increment by 8 0 8 16 16 0x10 Increment by 16 0 16 32 32 0x20 Increment by 32 0 32 64 64 0x40 Increment by 64 0 64 128 128 0x80 Increment by 128 0 128 256 Type Read Write Write Example A STEP 0x2 Read Example A STEP 2 1 4 36 Pixel B Pattern Step B_STEP The Pixel B Pattern Step B_STEP command determines the amount by which the B pixel value increments in the wedge horizontal vertical diagonal video test patterns The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL MODE command See Section 1 3 4 for further information Parameter B STEP Settings 1 0x1 Increment by 1 0 1 2 2 0x2 Increment by 2 0 2 4 4 0x2 Increment by 4 0 4 8 8 0x8 Increment by 8 0 8 16 16 0x10 Increment by 16 0 16 32 32 0x20 Increment by 32 0 32 64 64 0x40 Increment by 64 0 64 128 128 0x80 Increment by 128 0 128 256 Type Read Write 39 Write Example B STEP 0x2 Read Example B STEP 1 4 37 Pixel Pattern Step C STEP The Pixel C Pattern Step C STEP command determines the amount by which the C pixel value increments in the wedge horizontal vertical diagonal video test patterns The CLS
31. command assigns the test pattern for video data pixel C The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL MODE command See Section 1 3 4 for further information Parameter C PATSEL Settings 0 0x0 Fixed Value 1 0x1 Horizontal Wedge 2 0x2 Vertical Wedge 3 0x3 Diagonal Wedge Type Read Write Write Example C_PATSEL 0x2 Read Example C_PATSEL 1 4 14 Pixel D Pattern Select D PATSEL The Pixel D Pattern Select D PATSEL command assigns the test pattern for video data pixel D The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL MODE command See Section 1 3 4 for further information Parameter D PATSEL Settings 0 0x0 Fixed Value 1 0x1 Horizontal Wedge 2 0x2 Vertical Wedge 3 0x3 Diagonal Wedge Type Read Write Write Example D_PATSEL 0x3 Read Example D_PATSEL 1 4 15 Pixel E Pattern Select E PATSEL The Pixel E Pattern Select E PATSEL command assigns the test pattern for video data pixel E The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL MODE command See Section 1 3 4 for further information 28 Parameter E PATSEL Settings 0 0x0 Fixed Value 1 0x1 Horizontal Wedge 2 0x2 Vertical Wedge 3 0x3 Diagonal Wedge Type Read Write Write Example E PATS
32. eld 13 N A tied to digital ground Inner shield 26 N A tied to digital ground FG Frame Grabber 63 2 2 Rear Panel The CLS 211 Camera Link Simulator rear panel is shown in Figure 2 3 The rear panel contains an RS 232 connector power on indicator on off switch and DC power jack The DC power jack accepts 5 7 volts DC center positive The RS 232 serial port connector is a standard 9 pin male D Sub type DB9 Tyco p n 747840 4 Figure 2 4 identifies the DB9 pin positions POWER 5 7 VDC Figure 2 3 CLS 211 Rear Panel pin 1 pin 5 oe pin 6 pin 9 Figure 2 4 DB9 Connector Pin Positions 64 2 2 1 DB9 Connector Signals The DB9 connector signal assigaments are compliant with the RS 232 serial interface standard Table 2 3 identifies the DB9 signal assignments Table 2 3 DB9 Connector SUNT 089 Pin Signal Direction Notes Received Line Signal Detect 1 N A tied to pins 4 amp 6 Received Data 2 PC CLS 211 Transmitted Data 3 CLS 211 PC Data Terminal Ready 4 N A tied to pins 1 amp 6 Signal Ground common 5 N A tied to digital ground DCE Ready 6 N A tied to pins 1 amp 4 Request To Send 7 N A tied to pin 8 Clear To Send 8 N A tied to pin 7 Ring Indicator 9 N A no connection PC Control PC workstation or terminal e5 3 Mechanical 3 1 Dimensions The CLS 211 Camera Link Simulator cabinet dimensions are shown in Figure 3 1
33. er communications software program is used to download the configuration file to the CLS 211 PC serial port settings are conventional and are specified in Section 1 3 7 9600 baud 8 data bits no parity 1 stop bit no flow control Using HyperTerminal the configuration file is sent to the CLS 211 by selecting the Transfer tab and clicking on Send Text File The user then specifies the location of cls211_example txt and file download commences Alternately the parameters may be individually entered via the CLI Subsequent changes to CLS 211 parameters can be made by downloading a new configuration file or by manually entering commands with the keyboard CLS 211 Camera Link Simulator Computer Camera Link Cables Camera Link Frame Grabber Figure 1 12 CLS 211 Typical Application 55 Table 1 4 Example Configuration File cls211_example txt CLS 211 Camera Link Simulator Configuration File Example Test Pattern Characteristics 512x512 active image area 20 MHz pixel clock rate Continuous output mode Camera Link full configuration Eight 8 bit pixels 8x8 Diagonal wedge pattern on all pixels Line Valid Low 32 clocks LVAL LO 32 Line Valid High 576 clocks LVAL HI 576 Frame Valid Low 2 lines
34. he default value is output whenever the CLS 211 is not outputting video test pattern data The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL MODE command See Section 1 3 4 for further information Parameter D BACK Range Depends on pixel size 0 4095 hex 0x0 OxF FF max Type Read Write Write Example D BACK 0x3C3 Read Example D BACK 36 1 4 31 Pixel E Background Value E BACK The Pixel E Background Value E BACK command determines the default value for video data pixel E The default value is output whenever the CLS 211 is not outputting video test pattern data The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL MODE command See Section 1 3 4 for further information Parameter E BACK Range 0 255 hex 0x0 OxFF Type Read Write Write Example E BACK 0xC3 Read Example E BACK 1 4 32 Pixel F Background Value F BACK The Pixel F Background Value F BACK command determines the default value for video data pixel F The default value is output whenever the CLS 211 is not outputting video test pattern data The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL MODE command See Section 1 3 4 for further information Parameter F BACK Range 0 255 hex 0x0 OxFF Type Read Write Write Example F BACK 0xC3 Read Example F
35. he generation of a video frame in response to a triggering event is delayed by the time programmed into the counter in order to mimic an integration interval 1 3 6 Microcontroller The CLS 211 Camera Link Simulator utilizes a microcontroller device to implement a Command Line Interface CLI The CLI enables a PC or workstation to control and monitor CLS 211 functions The microcontroller interprets commands received over the CLI and configures the CLS 211 circuitry accordingly The serial communication protocol between the PC workstation and the CLS 211 is supported by the microcontroller s built in Universal Asynchronous Receiver Transmitter UART The microcontroller incorporates non volatile configuration memory for the storage of user selected parameters Upon povver up initialization the CLS 211 automatically recalls the parameter set stored in memory This feature enables operation of the CLS 211 vvithout a control port connection The CLI Parameter Save SAVE command is used to store the current parameter set to the configuration memory The CLI Parameter Recall RECALL command configures the CLS 211 using the parameter set currently stored 1 3 7 RS 232 Serial Port The CLS 211 Camera Link Simulator incorporates an industry standard RS 232 serial port for linking the CLS 211 to a host PC or workstation The serial port provides RS 232 signal characteristics and incorporates a standard 9 pin D Sub DB9 18 connector The
36. her information Parameter FVAL HOLD Range 0 65535 clocks hex 0x0 OxFFFF Type Read Write Write Example FVAL HOLD 0x1000 Read Example FVAL HOLD 24 1 4 7 X Offset X OFFSET The X Offset X OFFSET command determines the number of clock cycles from the rising edge of the Camera Link LVAL signal to the start of test pattern data i e horizontal start position When X OFFSET is set to 0 line test pattern data begins immediately following the rising edge of LVAL See Section 1 3 3 for further information Parameter X OFFSET Range 0 65535 clocks hex 0x0 OxFFFF Type Read Write Write Example X OFFSET 0x2000 Read Example X OFFSET 1 4 8 X Active X ACTIVE The X Active X ACTIVE command determines the horizontal size x dimension of the test pattern in clock cycles See Section 1 3 3 for further information Parameter X ACTIVE Range 1 65535 clocks hex 0x1 OxFFFF Type Read Write Write Example X ACTIVE 0x3000 Read Example X ACTIVE 25 1 4 9 Y Offset Y OFFSET The Y Offset Y OFFSET command determines the number of lines from the rising edge of the Camera Link FVAL signal to the start of test pattern data i e vertical start position When Y OFFSET is set to 0 the test pattern data begins with the next line See Section 1 3 3 for further information Parameter Y OFFSET Range 0 65535 clocks hex 0x0 OxFFFF Type Read Write Write Example Y OFFSET 0x4000 Read Example Y O
37. ion code is 48 0x30 Parameter VERSION Settings 8 bit FPGA version code 48 0x30 standard Type Read Read Example VERSION 1 4 55 One Shot Trigger ONE SHOT The One Shot Trigger ONE SHOT command enables the triggering of a single frame or line for linescan mode via the CLI Note that continuous mode must be disabled to use this feature see CONTINUOUS command There is no read or write data associated with this command See Section 1 3 2 for further information Parameter ONE SHOT Settings None command only Type Command Example ONE SHOT 1 4 56 Parameter Save SAVE The Parameter Save SAVE command stores the current CLS 211 parameter set to non volatile memory The saved parameters are recalled automatically following power up or in response to the RECALL command Saved parameters are maintained until altered via a subsequent SAVE command There is no read or write data associated with this command See Section 1 3 6 for further information Parameter SAVE Settings None command only Type Command Example SAVE 51 1 4 57 Parameter Recall RECALL The Parameter Recall RECALL command retrieves the parameter set currently stored in non volatile memory The saved parameters are also automatically recalled during power up initialization There is no read or write data associated with this command See Section 1 3 6 for further information Parameter RECALL Settings None command only Type Comma
38. k for the video test patterns The clock synthesizer is capable of generating virtually any reference clock frequency in the extended Camera Link 20 85 MHz range The reference clock is used by the timing window and pattern generation circuitry and is also sent to the frame grabber via the Camera Link interface As with all CLS 211 user parameters clock frequency settings are stored to non volatile memory in response to a parameter save command Stored clock settings are automatically retrieved from memory upon power up or in response to a parameter recall command The CLS 211 clock synthesizer chip is an 1CS307M 02 made by Integrated Clock Solutions Inc ICS The CLS 211 Command Line Interface CLI incorporates two commands for selecting the reference clock frequency With the frequency command the user simply specifies an integer frequency between 20 and 85 MHz i e 20 21 22 85 For fractional frequencies i e 27 375 MHz the synth code command allows direct input of the programming code into the clock synthesizer chip An online synthesizer code generation tool is available on the Integrated Clock Solutions ICS website at http www icst com calculators ics307inputForm html Simply follow the link and enter the following parameters into the window In the Input Frequency box enter 14 31818 Enter desired frequency Enter desired accuracy In the Clock 2 Output box select OFF In the Output Driver box select CMOS
39. lid High Line Valid Low Parameter LVAL HI Parameter LVAL LO Range 1 65535 clocks Range 1 65535 clocks Figure 1 2 Line Valid LVAL Timing Characteristics FVAL is used to envelope frames of video data from framescan cameras and is defined in the Camera Link specification as high for valid frame data Two CLS 211 timing parameters FVAL LO and FVAL HI determine the duration of FVAL low and high states in video lines respectively Video lines refer to the Line Valid LVAL signal vvhich vvas discussed in the prior paragraph The CLS 211 supports FVAL low and FVAL high times from 1 65535 lines FVAL timing characteristics are shown in Figure 1 3 Frame Valid FVAL P d Frame Valid High Frame Valid Low Parameter FVAL HI Parameter FVAL LO Range 1 65535 lines Range 1 65535 lines Figure 1 3 Frame Valid FVAL Timing Characteristics The relative positioning of the FVAL and LVAL timing signals is programmable and is specified using the Frame Valid Setup FVAL SETUP and Frame Valid Hold FVAL HOLD parameters When FVAL SETUP and FVAL HOLD are both set to 0 the default condition occurs whereby transitions on the FVAL signal occur coincident with the falling edge of the LVAL signal the start of the horizontal blank interval This relationship is illustrated in Figure 1 4 Line Valid LVAL Frame Valid FVAL FVAL SETUP 0 FVAL HOLD 0 Figure 1 4 Default LVAL FVAL Timi
40. nd Example RECALL 1 4 58 Echo Control ECHO The Echo Control ECHO command controls CLS 211 echo back of characters received via the control interface Upon CLS 211 power up echo is enabled and the CLS 211 will echoes back all characters received Turning off echo disables the echo until re enabled or a subsequent power up reset ECHO ON and ECHO OFF are useful in configuration files to avoid large amounts of returned data during file download See Section 1 4 for further information Parameter ECHO Settings ON Enable echo default OFF Disable echo Type Write Write Example ECHO ON 52 1 4 59 Parameter Dump DUMP The Parameter Dump DUMP command causes the CLS 211 to return the entire current parameter set to the host computer Information is displayed in both hexadecimal and decimal format except for SYNTH CODE A typical DUMP command response is shown below Parameter DUMP Settings None command only Type Command Example DUMP CLS 211 Dump Example LVAL LO 0x0020 fo 32 LVAL HI 0x0100 256 FVAL LO 0x0002 2 FVAL HI 0x0100 256 FVAL SETUP 0x0000 0 FVAL HOLD 0x0000 0 X OFFSET 0x0000 0 X ACTIVE 0x0100 256 Y OFFSET 0x0000 0 Y ACTIVE 0x0100 256 A PATSEL 0x03 3 B PATSEL 0x00 0 C PATSEL 0x00 0 D PATSEL 0x00 0 E PATSEL 0x00 0 F PATSEL 0x00 0 G PATSEL 0x00 0 H PATSEL 0x00 0
41. ng Relationship The FVAL SETUP and FVAL HOLD parameters allow CLS 211 timing characteristics to be fine tuned in order to mimic camera characteristics verify frame grabber functionality etc Figure 1 5 illustrates how a value inserted in the FVAL_SETUP results in the rising edge of FV AL occurring in advance of the falling edge of LVAL The figure also illustrates how FVAL HOLD values result in the falling edge of FVAL occurring after the falling edge of LVAL Line Valid LVAL or 3p eL Ad Frame Valid FVAL X 1 a Frame Valid Setup Frame Valid Hold Parameter FVAL_SETUP Parameter FVAL_HOLD Range 0 65535 clocks Range 0 65535 clocks Figure 1 5 FVAL Setup Hold Timing Parameters 10 1 3 3 Window Generator The CLS 211 Camera Link Simulator incorporates a programmable window generator that determines the size and position of the video test pattem The window generator accepts four parameters to determine the position and size of the video test pattern relative to the FVAL and LVAL timing signals described in Section 1 3 2 The starting position of the video test pattern is determined by the X Offset XOFF and Y Offset YOFF parameters XOFF determines the staring position within a line x position and the YOFF parameter determines the starting row y position Test pattern image size is defined using the XACT and XOFF parameters X Active XACT determines the horizontal test pattern size in pixels and Y Acti
42. nk Specification Figure 2 2 identifies the MDR 26 pin positions Vivid Engineering Camera Link Simulator CLS 211 e C e MEDIUM FULL BASE Figure 2 1 CLS 211 Front Panel pin 13 pin 1 Ele pin 26 pin 14 Figure 2 2 MDR 26 Connector Pin Positions 2 1 1 Camera Connector Signals The MDR 26 camera connector signal assignments are compliant with the Camera Link Specification for the base and medium configurations Table 2 1 and 2 2 identify the signal assignments for the MDR 26 base and medium full camera connectors respectively Note that the connector pin assignments are as defined for the camera interface in the Camera Link Specification This provides compatibility with standard Camera Link cables 2 1 2 Cable Shield Grounding Camera Link cable outer shields are connected to the CLS 211 aluminum case The case is isolated from the CLS 211 circuitry and the cable inner shields The frame grabber cable inner shield connects to circuit digital ground maintaining signal reference levels between the CLS 211 and the frame grabber 61 Table 2 1 CLS 211 Base Connector y Base SINE Venu Signal Direction Notes camera pinout Inner shield 1 N A tied to digital ground Inner shield 14 N A tied to digital ground X0 2 CLS 211 FG X0 15 CLS 211
43. ommand See Section 1 3 4 for further information Parameter A BACK Range Depends on pixel size 0 65535 hex 0x0 OxFFFF max Type Read Write Write Example A BACK 0xA5AS Read Example A BACK 1 4 28 Pixel 8 Background Value B BACK The Pixel B Background Value B BACK command determines the default value for video data pixel B The default value is output whenever the CLS 211 is not outputting video test pattern data The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL MODE command See Section 1 3 4 for further information Range Depends on pixel size 0 4095 hex 0x0 OxF FF max Type Read Write Write Example B BACK 0x5A5 Read Example B BACK 35 1 4 29 Pixel C Background Value C BACK The Pixel C Background Value C BACK command determines the default value for video data pixel C The default value is output whenever the CLS 211 1s not outputting video test pattern data The CLS 211 outputs up to eight pixels simultaneously A B C D E F G H depending on output mode see CL MODE command See Section 1 3 4 for further information Parameter C BACK Range Depends on pixel size 0 4095 hex 0x0 OxFFF max Type Read Write Write Example C BACK 0xC3C Read Example BACK 2 1 4 30 Pixel D Background Value D BACK The Pixel D Background Value D BACK command determines the default value for video data pixel D T
44. r a 1 for the character delay and or the line delay Upon power up the CLS 211 performs system initialization and will respond with a message similar to the following CLS 211 initializing please wait ready Following initialization the CLS 211 then sends the PC a message similar to the following 20 CLS211 Camera Link Simulator CLI Vivid Engineering Rev 1 01 The CLS 211 recognizes the commands defined in the following sections The DUMP SAVE and RECALL commands are particularly useful In the case of invalid syntax the CLS 211 responds with the following invalid entry All numeric entries are made using either decimal or hexadecimal 0x notation The only exception is the long Clock Synthesizer Code SYNTH CODE command which is always entered as hexadecimal CLS 211 parameters may be entered manually on the keyboard or may be downloaded to the CLS 211 as a configuration file Configuration files are plain text format 1 e txt files and may be created with an editor word processor etc Spaces and returns may be inserted as desired for readability Comments are indicated using a backslash and may be located at the start of a line or following a command The following is an example of comments located in a configuration file Note that all numeric information must be in either decimal or hexadecimal 0x format An example configuration file is found in Section 1 5
45. re Non volatile save recall of user settings Can operate stand alone Sturdy compact aluminum enclosure w mounting flange External multi nation power supply and RS 232 cable included 3 year warrantee 1 3 Functional Description The CLS 211 Camera Link Simulator is a programmable video test pattern generator supporting all Camera Link configurations base medium full A block diagram of the CLS 211 is provided in Figure 1 1 Descriptions of the functional blocks are provided in the follovving sections The CLS 211 combines video test pattern generation circuits implemented in Field Programmable Gate Array FPGA technology vvith an on board microcontroller The FPGA based video test pattern circuitry provides the desired video timing active window and test pattern characteristics The microcontroller links the pattern generation circuitry to the host computer and incorporates a simple straightforward Command Line Interface CLI This enables the CLS 211 to be controlled using any computer incorporating a standard RS 232 serial port Users may interactively assign settings via the CLL or may download configuration files created in advance The CLS 211 incorporates non volatile memory for storing user configuration settings Saved settings are automatically loaded upon power up enabling operation of the CLS 211 using pre loaded parameters without a host computer The CLS 211 Camera Link Simulator incorporates a clock synthesizer
46. serial port protocol settings are conventional and are defined in Table 1 3 Connector information is provided in Section 2 2 Table 1 3 RS 232 Serial Port Settings Port Characteristic Setting Rate bits per second 9600 Data Bits 8 Parity None Stop Bits 1 Flow Control None 1 3 8 Camera Control Inputs The CLS 211 Camera Link Simulator receives four Camera Control CC1 CC2 CC3 CC4 from the frame grabber as defined in the Camera Link specification The camera control signal states can be monitored using the CLI or used as an exsync input to trigger frame line output CLS 211 can be programmed to select a camera control input CC1 CC2 CC3 or CC4 for use as an exsync trigger Exsync trigger polarity rising or falling edge is also programmable When configured the CLS 211 will issue a single frame or line in linescan mode in response to each exsync trigger received 1 3 9 Channel Link Transmitters The CLS 211 Camera Link Simulator incorporates Channel Link transmitter devices for outputting video timing data and clock in compliance with the Camera Link specification Three Channel Link transmitter devices are used one for the base connector and two for the medium full connector High performance devices are utilized to support the extended Camera Link maximum pixel clock frequency of 85 MHz The Channel Link transmitter chips are National Semiconductor DS90CR287MTD
47. ter Definition CL MODE Parameter Setting Camera Link Mode decimal 0 8 bit x 1 3 base configuration 1 10 bitx 1 2 base configuration 2 12 bitx 1 2 base configuration 3 14 bitx 1 base configuration 4 16 bitx 1 base configuration 5 24 bit RGB base configuration 8 8 bit x 4 medium configuration 9 10 bit x 3 4 medium configuration 10 12 bit x 3 4 medium configuration 11 30 bit RGB medium configuration 12 36 bit RGB medium configuration 15 8 bitx 8 full configuration 15 Figure 1 8 Fixed Rectangular Test Pattern Figure 1 9 Horizontal VVedge Test Pattern 16 Figure 1 10 Vertical Wedge Test Pattern Figure 1 11 Diagonal Wedge Test Pattern 17 1 3 5 Integration Timer The CLS 211 incorporates an integration timer which may be used to simulate camera exposure characteristics The integration timer operates off a fixed clock reference and has a range of 0 to 65 seconds in 1ms steps The integration timer is used to mimic camera integration exposure characteristics by delaying the generation of video frames for a period of time representing the integration interval The integration timer may be used in conjunction with either continuous or triggered exsync mode In continuous mode the integration timer determines the video frame rate and can be set to mimic very long up to 65s integration periods In triggered exsync mode t
48. ve Y ACT determines the vertical pattern size in lines Figure 1 6 shows the test pattern line positioning relative to LVAL Figure 1 7 illustrates the window generation characteristics based on XOFF YOFF XACT and XACT Line Valid LVAL 8 Test Pattern Pixels ED ED ED A RP feces gt X Offset Parameter X OFFSET X Active Range 0 65535 clocks Parameter X_ACTIVE Range 1 65535 clocks Figure 1 6 Horizontal X Offset Active Parameters 11 Total Lines per Frame FVAL HI n Total Pixels per Line LVAL HI 5 TEST PATTERN ACTIVE WINDOW Figure 1 7 Window Generator Characteristics 12 1 3 4 Pattern Generator The CLS 211 Camera Link Simulator incorporates a programmable pattern generator to create a variety of test pattems The CLS 211 1s capable of generating rectangular fixed value horizontal wedge vertical wedge and diagonal wedge patterns as shown in Figures 1 8 through 1 11 The rectangular fixed value pattern may be any width or height 1 e vertical line horizontal line dot square etc in any position and with selectable foreground and background pixel values The CLS 211 enables the user to individually select the test pattern for up to eight pixel outputs A B C D E F G H in the multi tap and color modes To support this feature eight Pattern Select A PATSEL B PATSEL C PATSEL D PATSEL E PATSEL F PATSEL G PATSEL H PATSEL parameters are provided The
49. which enables the user to select virtually any test pattern clock frequencies in the extended Camera Link 20 85 MHz range The camera control inputs of the Camera Link interface are sent to timing generator for use as exsync inputs enabling the frame grabber to trigger pattern generation and an integration timer adds camera exposure characteristics The serial link in the Camera Link interface is looped back to the frame grabber enabling loopback test of the serial interface The CLS 211 camera interface incorporates the connector signals pinout and chipset in compliance with the Camera Link specification The CLS 211 incorporates the base medium and full configuration signal sets consisting of video data camera control and serial communications The CLS 211 is powered by an external multi nation wall plug in power supply which is included Also included is an RS 232 serial cable LVDS Receiver Camera Control Video Data Timing Window Pattern Generator Generator Generator 29998 9 9 8 84900020 01 Configuration Memory TER Serial i Comm Serial i Serial Port RS 232 Ll Corm f t Micro ontroller To PC RS 232 Port Figure 1 1 CLS 211 Block Diagram 1 3 1 Clock Synthesizer The CLS 211 Camera Link Simulator incorporates a clock synthesizer circuit to generate the reference cloc
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