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1. 194 LQFP144 marking package top 195 UFBGA132 132 ball 7 7 mm ultra thin fine pitch ball grid array package 4 196 UFBGA132 marking package top view 197 LQFP100 100 pin 14 x 14 mm low profile quad flat package outline 198 LQFP100 100 pin 14 x 14 mm low profile quad flat recommended 199 LQFP100 marking package top 200 WLCSP81 81 pin 4 4084 x 3 7594 mm 0 4 mm pitch wafer level chip scale package 4 2 4 0 44 201 WLCSP81 81 pin 4 4084 x 3 7594 mm 0 4 mm pitch wafer level chip scale package recommended footprint 202 WLCSP72 72 pin 4 4084 x 3 7594 mm 0 4 mm pitch wafer level chip scale package sos leases RA Rub UR ee s 203 WLCSP72 marking package top 204 LQFP64 64 pin 10 x 10 mm low profile quad flat package outline 205 LQFP64 64 pin 10 x 10 mm low profile quad flat package recommended 206 LQFP64 marking package top
2. Symbol Parameter Min Max Unit tw NE FMC_NE low time 1 3Tuci k 2 tuNwE FMC NEx low to NWE low 0 5 1 5 twinwe FMC_NWE low time 1 1 NwE FMC_NWE high to NE high hold time 0 5 tA ne FMC_NEx low to valid 2 0 nwe Address hold time after NWE high 1 FMC_NEx low to BL valid 1 5 tg NwE BL hold time after NWE high 0 5 tv Data ne Data to NEx low to Data valid 4 1 Data hold time after FMC_NWE high 1 tvNADV_NE FMC_NEx low to FMC_NADV low 1 tuNApv FMC_NADV low time 0 5 1 30 pF 2 Based characterization not tested production DocID025976 Rev 2 q STM32L476xx Electrical characteristics Table 88 Asynchronous non multiplexed SRAM PSRAM NOR write NWAIT timings Symbol Parameter Min Max Unit low time 8 0 5 8 0 5 tw NWE FMC_NWE low time 6 0 5 6 0 5 tsu NWAIT_NE FMC_NWAIT valid before NEx high 6Tucik 2 25 NEx hold time after NWAIT invalid 4Tucik 2 1 CL 30 pF 2 Based on characterization not tested in production Figure 37 Asynchronous multiplexed PSRAM NOR read
3. 207 LOFP64 Pp Max vs Fa uere e AUR ace e Te n De e ERR un Ia 210 q DocID025976 Rev 2 STM32L476xx Introduction 1 Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32L476xx microcontrollers This document should be read in conjunction with the STM32L4x6 reference manual RM0351 The reference manual is available from the STMicroelectronics website www st com For information on the ARM Cortex M4 core please refer to the Cortex M4 Technical Reference Manual available from the www arm com website mu Cortex NI Intelligent Processors ARM POWERED q DocID025976 Rev 2 11 213 Description STM32L476xx 2 Description The STM32L476xx devices are the ultra low power microcontrollers based on the high performance Cortex M4 32 bit RISC core operating at a frequency of up to 80 MHz The Cortex M4 core features a Floating point unit FPU single precision which supports all ARM single precision data processing instructions and data types It also implements a full set of DSP instructions and a memory protection unit MPU which enhances application security The STM32L476xx devices embed high speed memories Flash memory up to 1 Mbyte up to 128 Kbyte of SRAM a flexible external memory controller FSMC for static memories for devices with packages of 100 pins and m
4. XXQZVTIZEINLS uonduosep uid pue s ynould 12 08 94 9768c0GI oq Table 16 Alternate function AF8 to AF15 for AF0 to AF7 see Table 15 continued AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 Port UARTA SDMMC1 1 TIM2 TIM15 UARTS CAN1 TSC OTG FS QUADSPI LCD 2 SAI2 TIM16 TIM17 EVENTOUT LPUART1 SWPMI1 LPTIM2 PCO od N LCD SEG18 3 2 IN1 EVENTOUT PC1 LPUART4 TX LCD SEG19 EVENTOUT PC2 LCD_SEG20 EVENTOUT PC3 z LCD_VLCD F SAM SD A LPTIM2 ETR EVENTOUT PC4 LCD_SEG22 z EVENTOUT 5 LCD SEG23 EVENTOUT PC6 TSC G4 101 LCD SEG24 SDMMC1 D6 lt 2 EVENTOUT PC7 TSC G4 102 LCD_SEG25 SDMMC1_D7 ii EVENTOUT PC8 TSC G4 103 LCD SEG26 SDMMC1_DO EVENTOUT Port TIM8 BKIN2 PC9 TSC G4 104 OTG FS LCD SEG27 SDMMC1_D1 SAI2 EXTCLK Coup EVENTOUT LCD PC10 UARTA TX TSC G3 102 LCD SEG28 5 1 D2 SAI2 SCK B EVENTOUT LCD SEG40 LCD PC11 UART4_RX TSC G3 103 LCD SEG29 SDMMC1_D3 Mc EVENTOUT LCD SEG41 LCD 6 12 UARTS TX TSC G3 104 i LCD SEG3O SDMMC1_CK SAI2 SD B EVENTOUT LCD SEG42 PC13 5 EVENTOUT 14 F EVENTOUT PC15 i EVENTOUT uonduosep uid pue XXQZV
5. 134 Flash memory endurance and data 134 EMS cliaracteristics ela x bia dad me p edd RIVER ROO 135 EMI 136 ESD absolute maximum 08 136 Electrical sensitivities 137 current injection susceptibility llle 137 I O static characteristics 138 Output voltage characteristics 141 41 142 NRST characteristics 144 Analog switches booster 145 ADC characteristics 146 Maximum ADC 148 222 Sad eed aa 149 DAC characteristics 152 2 2555 402 Obes sayu AUS yeu ipsa 154 VREFBUF 157
6. 175 Asynchronous non multiplexed SRAM PSRAM NOR read waveforms 176 Asynchronous non multiplexed SRAM PSRAM NOR write waveforms 178 Asynchronous multiplexed PSRAM NOR read 179 Asynchronous multiplexed PSRAM NOR write waveforms 181 Synchronous multiplexed NOR PSRAM read timings 183 Synchronous multiplexed PSRAM write 06 185 Synchronous non multiplexed NOR PSRAM read 187 Synchronous non multiplexed PSRAM write 188 controller waveforms for read access 190 controller waveforms for write 190 controller waveforms for common memory read 190 controller waveforms for common memory write 191 LQFP144 144 20 x 20 mm low profile quad flat package outline 192 LQFP144 144 pin 20 x 20 mm low profile quad flat package DoclD025976 Rev 2 9 213 List of figures STM32L476xx Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 10 213 recommended
7. Quad SPI O Backup Registers Y Y Y Y Y Y Y Y Y Brown out reset BOR Y Y Y Y Y Y VW Y Vv Programmable Voltage Detector PVD Peripheral Voltage Monitor PVMx O O O 1 2 3 4 DMA O O High Speed Internal 5 f 5 i q _ n HSI16 o 2 2 High Speed External HSE 7 u I I I I i I i I Low Speed Internal LSI O O O O O O O Low Speed External LSE 2 9 7 EM RE B Multi Speed Internal MSI 9 9 9 9 I I i I E I I I Clock Security System CSS x I I i K I i I I Clock Security System on LSE O O Auto wakeup O O O O 3 3 3 EB ED 3 3 Tamper pins 26 213 DoclD025976 Rev 2 Ly STM32L476xx Functional overview Table 5 Functionalities depending on the working model continued Stop 1 Stop 2 Standby Shutdown gt gt gt Low Low 5 5 5 5 Sleep power power 8 8 8 8 VBAT run sleep 5 2 2 2 LCD USB OTG FS of o 8 USARTx 6 m9l _ _ _ 1 2 3 4 5 9 9 2 o oL Low power UART 6 ER _
8. 122 DocID025976 Rev 2 Ly STM32L476xx List of tables Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 Table 80 Table 81 Table 82 Table 83 Table 84 Table 85 Table 86 Table 87 Table 88 Table 89 Table 90 Table 91 Table 92 Table 93 Ly High speed external user clock 123 Low speed external user clock 124 HSE oscillator 125 LSE oscillator characteristics fj sg 32 768 2 126 HS116 oscillator 128 MSI oscillator eae 129 LSI oscillator 132 PLL PLLSAM PLLSAI2 133 Flash memory
9. Reference document JESD51 2 Integrated Circuits Thermal Test Method Environment Conditions Natural Convection Still Air Available from www jedec org Selecting the product temperature range When ordering the microcontroller the temperature range is specified in the ordering information scheme shown in Section 8 Part numbering Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and to a specific maximum junction temperature q DocID025976 Rev 2 STM32L476xx Package information Note q As applications do not commonly use the STM32L476xx at maximum dissipation it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application The following examples show how to calculate the temperature range needed for a given application Example 1 High performance application Assuming the following application conditions Maximum ambient temperature 82 C measured according to JESD51 2 20 mA Vpp 3 5 V maximum 20 I Os used at the same time in output at low level with Io 8 mA Vg 0 4 V and maximum 8 I Os used at the same time in output at low level with 20 mA Vo 1 3 V PiNTmax gt 50 mA x 3 5 175 mW Piomax 20 x 8 mA x 0 4 8 x 20 mA x 1 3 272 mW This gives PiNTmax 175 mW and Piomax 272 mW Pp
10. q 94 213 DocID025976 Rev 2 STM32L476xx Electrical characteristics 6 3 Operating conditions 6 3 1 General operating conditions Table 21 General operating conditions Symbol Parameter Conditions Min Max Unit fucik Internal AHB clock frequency 0 80 Internal APB1 clock frequency 0 80 MHz Internal APB2 clock frequency 0 80 Vpp _ Standard operating voltage 3 6 V At least PG 15 2 used 1 08 3 6 Vppio2 PG 15 2 l Os supply voltage PG 15 2 not used 0 3E V ADC or COMP used 1 62 DAC or OPAMP used 1 8 VppA Analog supply voltage VREFBUF used 24 3 6 V ADC DAC OPAMP COMP 0 VREFBUF not used Vpgar Backup operating voltage 1 55 3 6 V USB used 3 0 3 6 Vppusa USB supply voltage TP 35 V TT_xx I O 0 3 0 3 0 9 Vin I O input voltage MIN MIN Vpp Vppa V All O except BOOTO and TT xx 0 3 koc rr 5 5 9 LQFP144 625 Power dissipation at LQFP100 476 P 85 C for suffix 6 LQFP64 5 E 444 mW 105 C for suffix 7 4 UFBGA132 363 WLCSP72 434 LQFP144 156 LQFP100 119 eo L R UFBGA132 90 WLCSP72 108 Ky DoclD025976 Rev 2 95 213 Electrical characteristics STM32L476xx Table 21 General operating conditions continued Symbol Parameter Conditions Min
11. Port H PH1 9 TIZEINLS uonduosep uid pue s ynould L12 8A 94 9768c0GI oq Table 16 Alternate function AF8 to AF15 for AF0 to AF7 see Table 15 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 Port UARTA SDMMC1 1 TIM2 TIM15 UARTS CAN1 TSC OTG FS QUADSPI LCD COMP2 FMC SAM SAI2 TIM16 TIM17 EVENTOUT LPUART1 SWPMI1 LPTIM2 UART4 TX SAM EXTCLK 2 EVENTOUT PA1 UART4_RX LCD SEGO 2 TIM15 CH1N EVENTOUT PA2 F LCD_SEG1 SAI2 TIM15 CH1 EVENTOUT PA3 LCD_SEG2 TIM15 CH2 EVENTOUT PA4 SAM FS B LPTIM2 OUT EVENTOUT PA5 gt 2 ETR EVENTOUT PAG QUADSPI_BK1_103 LCD SEG3 TIM16 CH1 EVENTOUT PA7 3 QUADSPI BK1 102 LCD_SEG4 TIM17 1 EVENTOUT pag OTG FS SOF LCD COMO LPTIM2 OUT EVENTOUT PA9 LCD COMI TIM15 BKIN EVENTOUT PA10 OTG FS ID LCD COM2 TIM17 BKIN EVENTOUT PA11 CAN1_RX OTG FS DM MS EVENTOUT PA12 OTG FS DP EVENTOUT PA13 OTG_FS_NOE E EVENTOUT PA14 2 EVENTOUT PA15 Mn TSC G3 101 LCD SEG17 SAI2_FS_B EVENTOUT uonduosep uid pue sjnouid 9 TIZEINLS 97 6 20 62
12. 49 Legend abbreviations used the pinout table 57 STM32L476xx pin definitions 58 Alternate function AFO to AF7 for AF8 to AF15 see Table 16 71 Alternate function AF8 to AF15 for to AF7 see Table 15 78 STM32L476xx memory map and peripheral register boundary addresses mu qua Peu Qaya awa MI RUE 87 Voltage 93 Current characteristics 94 Thermal 94 General operating conditions 1 95 Operating conditions at power up power down 96 Embedded reset and power control block 97 Embedded internal voltage 99 Current consumption in Run and Low power run modes code with data processing running from Flash ART enable Cache ON Prefetch OFF 101 Current consumption in Run and Low power run modes code with data processing running from Flash ART disable 102 Current consumption in Run and Low power run m
13. 40 lt TA lt 105 TBD Temperature coefficient ppm C i 40 lt T4 lt 50 TBD Acoett Long term stability 1000 hours T 25 C TBD ppm Voltage coefficient 3 0 V Vpp 3 6 V TBD ppm V VREFINT pivi 1 4 reference voltage 24 25 26 0 VREFINT Div2 1 2 reference voltage 49 50 51 i VREFINT VnEriNT piv3 3 4 reference voltage 74 75 76 1 The shortest sampling time can be determined in the application by multiple iterations 2 Guaranteed by design not tested in production Ly DoclD025976 Rev 2 99 213 Electrical characteristics STM32L476xx 6 3 5 100 213 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage ambient temperature pin loading device software configuration operating frequencies I O pin switching rate program location in memory and executed binary code The current consumption is measured as described in Figure 14 Current consumption measurement scheme Typical and maximum current consumption The MCU is placed under the following conditions e AI I O pins in analog input mode e peripherals are disabled except when explicitly mentioned e The Flash memory access time is adjusted with the minimum wait states number depending on the 1 frequency refer to the table Number of wait states according to CPU
14. 1 Refer to Table 59 AC characteristics NRST pin characteristics The NRST pin input driver uses the CMOS technology It is connected to a permanent pull up resistor Rpu Unless otherwise specified the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21 General operating conditions Table 60 NRST pin characteristics 1 Symbol VIL NRST Parameter Conditions Min Typ Max Unit NRST input low level voltage 7 I 7 0 35 VIH NRST NRST input high level voltage 7 0 7 7 Vhys NRST NRST Schmitt trigger 200 voltage hysteresis Rpu Weak pull up E equivalent resistor Vin Vss 25 40 55 kO VF NRST VNF NRST NRST input filtered pulse NRST input not filtered nie 1 71 V lt Vpp lt 3 6 V 350 z ns 1 Guaranteed by design not tested in production 2 The pull up is designed with a true resistance in series with a switchable PMOS This PMOS contribution to the series resistance is minimal 10 order 144 213 q DocID025976 Rev 2 STM32L476xx Electrical characteristics Figure 22 Recommended NRST pin protection External reset circuit 1 lt a EN Rpy NRST Internal reset z I t 7 Filter j MS19878V2
15. VINP lt lt 16b 8 ah lt gt 5 LCD Booster Vico 2 5V to 3 6V E wee sf SA lt gt LCD 8x40 gt SEGx COMx as AF lt gt DFSDM KC VDDA VDDA Kc LPUART1 gt Rx TX CTS RTS as AF lt 1 10 SEMI LL Rx TX SUSPEND as AF lt COMP2 DAC2 K gt Int IN2 OUT ETR as AF Firewall lt LPTIM2 D INT OUT ETR as AF OUT OUT2 AF alternate function I O pins Flexible static memory controller FSMC SRAM PSRAM NOR Flash NAND Flash NE 4 1 NL NBL 1 0 25 0 D 15 0 NOE NWE NWAIT as AF DoclD025976 Rev 2 MS31263V5 15 213 Functional overview STM32L476xx 3 3 1 3 2 3 3 16 213 Functional overview ARM Cortex M4 core with FPU The ARM Cortex M4 with FPU processor is the latest generation of ARM processors for embedded systems It was developed to provide a low cost platform that meets the needs of MCU implementation with a reduced pin count and low power consumption while delivering outstanding computational performance and an
16. consumption load 500 pA 18 30 from 4 4 35 50 1 Data guaranteed by design tested production unless otherwise specified 2 In degraded mode the voltage reference buffer can not maintain accurately the output voltage which will follow VppA drop voltage 3 Tested in production Ly DoclD025976 Rev 2 157 213 Electrical characteristics STM32L476xx 6 3 20 Comparator characteristics Table 68 COMP characteristics Symbol Parameter Conditions Min Typ Max Unit VppA Analog supply voltage 1 62 3 6 Comparator input voltage VIN range 0 VppA V Vac Scaler input voltage VREFINT Vsc Scaler offset voltage 5 10 i BRG 0 bridge disable 200 300 nA IDDA SCALER Scaler static consumption from VppA BRG_EN 1 bridge enable 0 8 1 tsTART_SCALER Scaler startup time 100 200 us High speed Vppa 2 2 7 V 5 mode gt Comparator startup time to Vppa lt 2 7 V tsTART reach propagation delay gt 2 7 V 15 us ificati Medium mode specification lt 2 7 V _ 25 Ultra low power mode 80 High speed Vppa 2 2 7 V i 55 80 mode _ Propagation delay for lt 2 7 V 100 tp 200 mV step m VppA 2 2 7 V 0 55 09 i i edium mode with 100 mV overdrive lt 2 7 V I 065 1 ds Ultra l
17. 2 2 7 HS S USARTX to USARTx SYSCLK X 2 5 to LPUART1 1 MSI RC HSI z SYSCLK to 12 100 kHz 48 MHz x 1 2 3 LSI gt 15 to LPTIMx HSI x 1 2 HSI n 4 to SWPMI MSI PCLK2 PEE 1 IM HSN HSE PREBE 2 peripherals to peripherals PLLSAI3CLK 11 2 4 8 16 PLLUSB1CLK xlorx2 gt o x IR PLLCLK x 1 8 15 16 17 LSE PLLSAI1 o HSI 4 to PLLSAI1CLK SYSCLK USART1 MSI 48 MHz clock to USB RNG SDMMC IR PLLADC1CLK SYSCLK to ADC PLLSAI2 gt PLLSAI2CLK to IR PLLADC2CLK 4 SAM to SAI2 SAI2 EXTCLK MS32440V2 Ly DoclD025976 Rev 2 33 213 Functional overview STM32L476xx 3 12 3 13 34 213 General purpose inputs outputs GPIOs Each of the GPIO pins can be configured by software as output push pull or open drain as input with or without pull up or pull down or as peripheral alternate function Most of the GPIO pins are shared with digital or analog alternate functions Fast I O toggling can be achieved thanks to their mapping on the AHB2 bus The I Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I Os registers Direct
18. A Hardware Packet Error Checking generation and verification with control A Address resolution protocol ARP support SMBus alert e Power System Management Protocol PMBus specification rev 1 1 compatibility e Independent clock a choice of independent clock sources allowing the 2 communication speed to be independent from the PCLK reprogramming Refer to Figure 3 Clock tree e Wakeup from Stop mode on address match e Programmable analog and digital noise filters e 1 byte buffer with DMA capability Table 11 12 implementation 12C features I2C1 I2C2 I2C3 Standard mode up to 100 kbit s Fast mode up to 400 kbit s Fast mode Plus with 20mA output drive I Os up to 1 Mbit s Programmable analog and digital noise filters SMBus PMBus hardware support Independent clock x x Wakeup from Stop 1 mode on address match gt x XxX XxX x x Wakeup from Stop 2 mode on address match 1 X supported q 46 213 DocID025976 Rev 2 STM32L476xx Functional overview 3 27 3 28 q Universal synchronouslasynchronous receiver transmitter USART The STM32L476xx devices have three embedded universal synchronous receiver transmitters USART1 USART2 and USART3 and two universal asynchronous receiver transmitters UART4 UART5 These interfaces provide asynchronous communication SIR ENDEC support
19. 1 The reset network protects the device against parasitic resets 2 The user must ensure that the level on the NRST can go below the Vi max level specified in Table 60 NRST pin characteristics Otherwise the reset will not be taken into account by the device 6 3 16 Analog switches booster Table 61 Analog switches booster characteristics Symbol Parameter Min Typ Max Unit Vpp Supply voltage 1 62 3 6 VBoosT Boost supply 2 7 4 tsu goosr Booster startup time 240 HS Booster consumption for _ _ 250 1 62 V lt Vpp lt 2 0 V Booster consumption for 10080087 20 V lt vop S 27 V poe HA Booster consumption for 900 2 7 V lt Vpp S 3 6 V 1 Data guaranteed by design tested in production q DocID025976 Rev 2 145 213 Electrical characteristics STM32L476xx 6 3 17 Analog to Digital converter characteristics Unless otherwise specified the parameters given in Table 62 are preliminary values derived from tests performed under ambient temperature fpc frequency and supply voltage conditions summarized in Table 21 General operating conditions Note It is recommended to perform a calibration after each power up Table 62 ADC characteristics 2 Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage 1 62
20. 6 Industrial temperature range 40 to 85 C 105 C junction 7 Industrial temperature range 40 to 105 C 125 C junction 3 Industrial temperature range 40 to 125 C 130 C junction Packing TR tape and reel XXX programmed parts DoclD025976 Rev 2 211 213 Revision history STM32L476xx 9 212 213 Revision history Table 108 Document revision history Date Revision Changes 29 May 2015 1 Initial release 45 Jun 2015 2 Updated Table 1 Device summary and Table 68 COMP characteristics DocID025976 Rev 2 q STM32L476xx IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections enhancements modifications and improvements to ST products and or to this document at any time without notice Purchasers should obtain the latest relevant information on ST products before placing orders ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement Purchasers are solely responsible for the choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right is granted by ST herein Resale of ST products with provisions different from the information set forth herein shall void any warranty grante
21. 8 22 2 22 22 0 4 4124 E RR 158 OPAMP characteristics 1 1 159 TS characteristics c eee RUE RC 162 Veat monitoring characteristics 162 Vpar charging 162 LCD controller 163 TIMx characteristics 164 IWDG min max timeout period at 32 kHz 1851 164 WWDG min max timeout value at 80 MHz 165 2 analog filter 165 SPI characteristics 166 Quad SPI characteristics in SDR 169 QUADSPI characteristics DDR 169 SAI characteristics 171 SD MMC dynamic characteristics VDD 2 7 03 6 173 eMMC dynamic characteristics VDD 1 71 01 9 174 USB electrical 175 Asynchronous non multiplexed SRAM PSRAM NOR read ti
22. NEx low to FMC A valid 3 tvNADvV_NE FMC_NEx low to FMC_NADV low 0 1 twNApv FMC low time 0 5 1 ns arene 2 valid hold time after Tucuc2 _ gh tha nwe Address hold time after FMC_NWE high 1 tni NwE BL hold time after NWE high 0 5 FMC NEx low to FMC BL valid 1 5 NADV high to Data valid 4 tn Data Data hold time after NWE high 0 5 1 CL 30 pF 2 Based on characterization not tested in production Table 92 Asynchronous multiplexed PSRAM NOR write NWAIT timings 1 2 Symbol Parameter Min Max Unit tw NE FMC_NE low time 0 5 9 2 tw NWE FMC NWE low time TTucuc1 5 1 5 Hs tsu NWAIT_NE FMC_NWAIT valid before NEx high 6Tucik 2 FMC_NEx hold time after NWAIT invalid 4TuciK 3 1 CL 30 pF 2 Based on characterization not tested in production Synchronous waveforms and timings Figure 39 through Figure 42 represent synchronous waveforms and Table 93 through Table 96 provide the corresponding timings The results shown in these tables are obtained with the following FMC configuration e BurstAccessMode BurstAccessMode Enable e MemoryType MemoryType CRAM e WriteBurst FMC WriteBurst Enable e CLKDivision 1 DataLatency 1 for NOR Flash DataLatency 0 for PSRAM D
23. load middle 185 240 DAC output code 0x800 buffer ON No load worst code OxF1C 340 400 DAC output No load middle buffer OFF code 0x800 I 193 299 Ippv DAC viis consumption from 185 400 uA REF Sample and hold mode buffer ON _ Ton Ton Ton Ton 100 nF worst case Toff Toff 4 4 155 x 205 x Sample and hold mode buffer OFF 100 nF worst case Toff Toff 4 4 1 Data guaranteed by design not tested production 2 In buffered mode the output can overshoot above the final value for low input code starting from min value 3 Refer to Table 57 static characteristics 4 Ton is the Refresh phase duration Toff is the Hold phase duration Refer to RM0351 reference manual for more details Ly DoclD025976 Rev 2 153 213 Electrical characteristics STM32L476xx Figure 25 12 bit buffered non buffered DAC Buffered Non buffered DAC Buffer 1 12 bit digital to analog converter ai17157d 1 The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register Table 66 DAC accuracy Symbol Parameter Conditions Min Typ Max Unit DNL Differential non DAC output buffer ON 5 E 2 2 lineari
24. millimeters inches Symbol Min Typ Max Min Typ Max A 0 460 0 530 0 600 0 0181 0 0209 0 0236 A1 0 050 0 080 0 110 0 0020 0 0031 0 0043 A2 0 400 0 450 0 500 0 0157 0 0177 0 0197 A3 0 270 0 320 0 370 0 0106 0 0126 0 0146 b 0 230 0 280 0 330 0 0091 0 0110 0 0130 D 6 950 7 000 7 050 0 2736 0 2756 0 2776 E 6 950 7 000 7 050 0 2736 0 2756 0 2776 e 0 500 0 0197 F 0 700 0 750 0 800 0 0276 0 0295 0 0315 0 080 0 0031 0 150 0 0059 fff 0 050 0 0020 196 213 DocID025976 Rev 2 STM32L476xx Package information 1 Values in inches are converted from mm and rounded to 4 decimal digits Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location Figure 51 UFBGA132 marking package top view Product identification STM32L u bocGrIb Date code Ball A1 indentifier Revision code MSv36851V3 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity q DocID025976 Rev 2 197 213 Package information STM32L476x
25. 125 25 C 55 C 85 105 125 C 18 6 59 24 7 92 7 208 437 16 62 232 520 1093 Regulator in low LCD 24 6 65 248 929 209 439 17 62 232 523 1098 d disabled Sbi 7999111995 isable 3v 6 65 24 9 933 20 442 17 62 233 525 1105 in Stop 1 36V 6 70 25 1 938 212 447 17 63 285 530 1118 Stop 1 d mode LCD 18V 7 00 252 972 219 461 18 63 243 548 1153 RTC disabled I gutator in low enabled2 24V 7 14 254 97 5 220 463 18 64 244 550 1158 power mode clocked by 3v 7 24 25 7 977 221 465 18 64 244 553 1163 36V 7 36 261 98 7 223 471 18 65 247 558 1178 18V 6 88 25 0 93 1 209 439 17 63 283 523 1098 LCD 24V 7 02 25 2 937 210 441 18 63 234 525 1103 disabled 3V 7 12 25 4 94 2 212 444 18 64 236 530 1110 e 2 3 6V 725 257 952 214 449 18 64 238 535 1123 regulator In low power mide 18V 701 264 99 0 223 467 18 65 248 558 1168 LCD 24V 744 263 996 225 470 18 66 249 563 1175 bled Supplyeumert enable 7 31 26 6 100 0 226 474 18 67 250 565 1185 Stop 1 in stop 1 3 6V 741 26 9 102 0 229 480 19 67 255 573 420 with mode RTC clocked by 18 6 91 25 2 93 4 210 440 17 63 234 525 1100 enabled mee aie LCD 24V
26. NE2 SAI2 SCK TIM15_CH1N EVENTOUT PG10 FMC NE3 SAI2 FS A TIM15 CH1 EVENTOUT PG11 dir TIM15 CH2 EVENTOUT PG12 4 SAI2 SD A EVENTOUT PG13 FMC A24 EVENTOUT PG14 FMC A25 EVENTOUT PG15 EVENTOUT uonduosep uid pue sjnouid XXQZV TZEINLS c 94 9768c0GI oq L S8 Table 16 Alternate function AF8 to AF15 for AF0 to AF7 see Table 15 continued AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 Port UART4 SDMMC1 COMP1 TIM2 TIM15 UART5 1 5 OTG FS QUADSPI LCD COMP2 FMC SAI2 16 17 EVENTOUT LPUART1 SWPMI1 LPTIM2 PH0 EVENTOUT Port H PH1 EVENTOUT 9 TZEINLS uonduosep uid pue Memory mapping STM32L476xx 5 Memory mapping Figure 10 STM32L476 memory map OxFFFF FFFF OxBFFF FFFF TM Reserved te 0xA000 1400 Internal QUADSPI registers 0 000 1000 Peripheral ee FMC registers 0xA000 0000 Ox5FFF FFFF 0x5006 0 00 AHB2 0x4002 4400 FMC and AHB1 5 QUADSPI 0x4002 0000 0x4001 6400 APB2 QUADSPI Flash 0x4001 0000 x 4 0 9000 0000 asa FMC bank 3 0x4000 0000 Ox1FFF F810 FMC bank 1 amp Option Bytes 3 bank 2 Ox1FFF F800 Ox1FFF F000 System memory Ox1FFF 8000 Ox1FFF 7810 Options Bytes Ox1FFF 7800 Ox1FFF 7400 Ox1FFF 7000 System memory Ox1
27. q DocID025976 Rev 2 STM32L476xx Functional overview 3 35 q The major features are e Combined Rx and Tx FIFO size of 1 25 KB with dynamic FIFO sizing e Supports the session request protocol SRP and host negotiation protocol HNP e 1 bidirectional control endpoint 5 IN endpoints 5 OUT endpoints e 8 host channels with periodic OUT support e inside no need for any external resistor e Software configurable to OTG 1 3 OTG 2 0 modes of operation 2 0 Supports ADP Attach detection Protocol e USB 2 0 LPM Link Power Management support e Battery Charging Specification Revision 1 2 support e Internal FS OTG PHY support For OTG Host modes a power switch is needed in case bus powered devices are connected Flexible static memory controller FSMC The Flexible static memory controller FSMC includes two memory controllers e The NOR PSRAM memory controller e The NAND memory controller This memory controller is also named Flexible memory controller FMC The main features of the FMC controller are the following e Interface with static memory mapped devices including Static random access memory SRAM NOR Flash memory OneNAND Flash memory PSRAM 4 memory banks Flash memory with ECC hardware to check up to 8 Kbyte of data 8 16 bit data bus width e Independent Chip Select control for each memory bank e Independent configuration for each
28. IO logic IN g ADCs DACs OPAMPs COMPs VREFBUF MS35001V3 Each power supply pair Vpp Vss Vppa Vssa etc must be decoupled with filtering ceramic capacitors as shown above These capacitors must be placed as close as possible to or below the appropriate pins on the underside of the PCB to ensure the good functionality of the device DoclD025976 Rev 2 q STM32L476xx Electrical characteristics 6 1 7 Current consumption measurement Figure 14 Current consumption measurement scheme IDD USB j VDDUSB IDD_VBAT O VBAT 1 w LI VDDIO2 IDDA O VDDA MS35002V2 6 2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 18 Voltage characteristics Table 19 Current characteristics and Table 20 Thermal characteristics may cause permanent damage to the device These are stress ratings only and functional operation of the device at these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 18 Voltage characteristics Symbol Ratings Min Max Unit External main supply voltage including V V 0 3 4 0 V DDX 88 vpp VppA Vico Vear _ min Vppiq2 VDDUSB Input voltage pins Vss 0 3 Viso 4 96 Vin Input volta
29. Prequalification trials Most of the common failures unexpected reset and program counter corruption can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see application note AN1015 Electromagnetic Interference EMI The electromagnetic field emitted by the device are monitored while a simple application is executed toggling 2 LEDs through the ports This emission test is compliant with IEC 61967 2 standard which specifies the test board and the pin loading Table 53 EMI characteristics Monitored Max vs fuse fucud Symbol Parameter Conditions equencvband 4 Unit 24 MHz 8 MHz 80 MHz 0 1 to 30 MHz 9 2 Vpp 3 6 V TA 25 C LQFP144 package 30 to 130 MHz 8 3 dBuV Peak level compliant with IEC 130 MHz to 1 GHz 10 14 61967 2 Level 1 5 3 5 6 3 12 Electrical sensitivity characteristics 136 213 Based on three different tests ESD LU using specific measurement methods the device is stressed in order to determine its performance in terms of electrical sensitivity Electrostatic discharge ESD Electrostatic discharges a positive then a negative pulse se
30. STM32L476xx Memory mapping Table 17 STM32L476xx memory map and peripheral register boundary addresses continued Bus Boundary address 0 4000 9800 0 4000 26 Reserved 0x4000 9400 0x4000 97FF 1 2 0 4000 8 00 0 4000 93FF 2KB Reserved 0x4000 8800 0x4000 8BFF 1 KB SWPMI1 0x4000 8400 0x4000 87FF 1 Reserved 0x4000 8000 0x4000 83FF 1 KB LPUART1 0 4000 7 00 0 4000 7FFF 1 LPTIM1 0x4000 7800 0x4000 7BFF 1 KB OPAMP 0x4000 7400 0x4000 77FF 1 KB DAC 0x4000 7000 0x4000 73FF 1 PWR 4 0 4000 6800 0 4000 6FFF 1 Reserved 0x4000 6400 0x4000 67FF 1 1 0 4000 6000 0 4000 63FF 1 Reserved 0x4000 5C00 0x4000 5FFF 1 I2C3 0x4000 5800 0x4000 5BFF 1 I2C2 0x4000 5400 0x4000 57FF 1 KB I2C1 0x4000 5000 0x4000 53FF 1 KB UART5 0x4000 4 00 0x4000 4FFF 1 KB UART4 0x4000 4800 0x4000 4BFF 1 KB USART3 0x4000 4400 0x4000 47FF 1 KB USART2 Ky DoclD025976 Rev 2 89 213 Memory mapping STM32L476xx 90 213 Table 17 STM32L476xx memory map and peripheral register boundary addresses continued Bus APB1 Boundary address erat Peripheral 0x4000 4000 0x4000 43FF 1 KB Reserved 0x4000 3 00 0x4000 3FFF 1 SPI3 0x4000 3800 0x4000 3BFF 1 KB SPI2 0x4000 3400 0x4000 37FF 1 KB Reserved
31. eee 193 UFBGA132 132 ball 7 7 mm ultra thin fine pitch ball grid array package mechanical 4 196 LQPF100 100 pin 14 x 14 mm low profile quad flat package mechanical data ulia sa RA ER ATA ERR IA 198 WLCSP81 81 pin 4 4084 x 3 7594 mm 0 4 mm pitch wafer level chip scale package mechanical 4 201 WLCSP81 recommended design rules 0 4 mm 202 WLCSP72 72 pin 4 4084 x 3 7594 mm 0 4 mm pitch wafer level chip scale package mechanical 203 LQFP64 64 pin 10 x 10 mm low profile quad flat package mechanical 205 Package thermal 208 STM32L476xx ordering information scheme 211 Document revision history 212 q DocID025976 Rev 2 STM32L476xx List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure
32. 97 C3 141 FT 1 NBLO TIM16 1 EVENTOUT LCD SEG37 NBL1 98 2 142 PE1 1 17 CH1 EVENTOUT 63 A8 99 D3 143 VSS S 64 A9 A9 100 C4 144 VDD S 1 PC13 PC14 and PC15 are supplied through the power switch Since the switch only sinks a limited amount of current 3 mA the use of GPIOs PC13 to PC15 in output mode is limited The speed should not exceed 2 MHz with a maximum load of 30 pF These GPIOs must not be used as current sources e g to drive an LED 2 After a Backup domain power up PC13 PC14 and PC15 operate as GPIOs Their function then depends on the content of the RTC registers which are not reset by the system reset For details on how to manage these GPIOs refer to the Backup domain and RTC register descriptions in the 0351 reference manual These GPIOs offer a reduced touch sensing sensitivity It is thus recommended to use them as sampling capacitor I O 4 After reset these pins are configured as JTAG SW debug alternate functions and the internal pull up PA15 PA13 4 pins and the internal pull down on 14 pin are activated 70 213 DoclD025976 Rev 2 q c 94 9768c0GI oq Table 15 Alternate function AF0 to AF7 for AF8 to AF15 see Table 16 AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 Port TIM1 TIM2 TIM1 TIM2 USART1 SYS
33. BOR RTC IWDG 0 12 uA w o em configuration can be 0 42 pA wi RTC floating pull up or pull down RTC other peripherals are Reset pin Powered Powered 0 03 uA w o RTC hutd OFF ff LSE d off 5 I Os WKUPx 10 256 Shutdown off Of S powered o Os x 0 33 uA w RTC Hs 777 configuration can be floating pull up or pull down e zo Qo wo d LPR means Main regulator is OFF and Low power regulator is ON LPRun LPSleep SWPMI1 wakeup by resume from suspend 0 The I Os with wakeup from Standby Shutdown capability are PC13 PE6 2 PC5 1 I Os can be configured with internal pull up pull down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode All peripherals can be active or clock gated to save power consumption The Flash memory can be put in power down and its clock can be gated off when executing from SRAM The SRAM1 and 5 2 clocks can be gated on or off independently U S ART and LPUART reception is functional in Stop mode and generates a wakeup interrupt on Start address match or received frame event I2C address detection is functional in Stop mode and generates a wakeup interrupt in case of address match OTG FS wakeup by resume from suspend and attach detection protocol event Typical current at Vpp 7 1 8 V 25 C Consumptions values provided running from SRAM Flash memory Off 80 MHz in Range 1 26 M
34. PD1 SPI2 55 DFSDM DATINT CAN1 RX FMC D2 EVENTOUT SPI2 SCK DFSDM CKIN7 1 TX D3 EVENTOUT 54 A3 A3 83 C8 116 PD2 RTS DE UART5 RX TSC SYNC LCD COM7 LCD SEG31 LCD SEG43 SDMMC1 CMD EVENTOUT 84 B8 117 PD3 SPI2 MISO DFSDM DATINO USART2 CTS FMC CLK EVENTOUT q DocID025976 Rev 2 67 213 Pinouts description STM32L476xx Table 14 STM32L476xx pin definitions continued Pin Number Pin functions 9 functi ft o 5 5 2 8 8 E Alternate functions Additional m reset gt 3 functions G i diu 112211515 a z SPI2 MOSI DFSDM CKINO 5 85 B7 118 PD4 USART2 RTS DE FMC NOE EVENTOUT USART2 TX FMC NWE D4 86 A6 119 PD5 EVENTOUT 120 vss s 4 121 VDD S DFSDM DATIN 1 USART2 RX D5 87 B6 122 PD6 NWAIT SAH SD A EVENTOUT DFSDM CKIN1 D6 88 5 123 PD7 USART2 EVENTOUT SPI3 SCK USART1 TX NE2 4 4 D9 124 9 s SAI2 SCK
35. ta CLKL NADVL td CLKL NADVH i NADV i A 25 0 ta CLKL NOEL D 15 0 FMC_NWAIT WAITCFG 1b WAITPOL 0b FMC_NWAIT WAITCFG 0b WAITPOL 0b c tqCUKL AV EE TN l 1 4 1 1 1 k 4 t a 1 1 1 1 t z d CLKL NExL gt NEM NExH 532759 1 Table 95 Synchronous non multiplexed NOR PSRAM read timings 1 2 Symbol Parameter Min Max Unit tw CLk FMC_CLK period 2THCLK ta CLKL NExL FMC_CLK low to FMC_NEx low x 0 2 2 5 ta CLKH NExH FMC_CLK high to NEx high 0 2 0 5 ty CLKL NADVL FMC_CLK low to NADV low 2 ta cLkL NApvH FMC_CLK low to FMC_NADV high 0 5 ta CLKL AV FMC_CLK low to FMC_Ax valid x 16 25 3 5 tacLkH Alv CLK high to FMC_Ax invalid x 16 25 ns taCLKL NOEL FMC_CLK low to FMC_NOE low 2 ta CLKH NOEH FMC_CLK high to FMC_NOE high 0 5 FMC_D 15 0 valid data before high 0 FMC_D 15 0 valid data after high 5 tsu NWAIT CLKH FMC_NWAIT valid before high 0 th CLKH NwAIT FMC_NWAIT valid after FMC_CLK high 4 DoclD025976 Rev 2 187 213 STM32L476xx l
36. 3 78 8MHz 1 26 1 29 1 40 1 57 1 89 1 40 1 50 1 64 2 06 2 68 Range2 4 MHz 0 71 0 75 0 85 1 02 1 34 0 79 088 1 06 1 38 221 Cn 2MHz 0 42 045 055 072 1 04 0 46 0 55 0 73 1 09 1 88 HCLK 7 HSE Supo 48M Hz included 1MHz 0 27 0 30 0 40 0 57 089 0 30 0 8 0 57 0 90 1 61 PPY bypass mode 100 kHz 0 14 0 17 0 27 043 0 75 0 17 0 22 0 40 0 74 144 Ipp Run current in PLL ON ab mA Run mode 80 MHz 10 0 10 1 10 3 10 6 11 0 11 00 11 35 11 64 12 26 13 10 7 72 9 06 9 13 9 28 9 51 9 92 9 97 10 36 10 65 11 06 11 69 64 MHz 8 96 904 922 948 992 9 86 10 25 10 54 10 95 11 79 Range 1 48 MHz 7 64 772 7 91 8 17 862 840 876 8 90 9 52 10 36 32 MHz 5 49 5 57 574 598 640 6 04 640 6 69 7 10 7 94 24 MHz 4 16 4 22 4 36 4 57 4 96 4 60 4 86 5 15 5 56 6 19 16 MHz 2 93 2 99 3 13 3 35 3 75 3 22 3 43 3 72 4 13 4 97 2MHz 358 392 503 683 1050 435 501 694 1069 1819 Supply ico LPRun current in fus 1MHz 197 230 340 519 880 245 312 512 887 1637 B Low power all peripherals disable 400kHz 97 126 235 414 778 130 202 402 777 1527 run 100kHz 47 77 186 365 726 85 147 347 711 1472 1 Based on cha
37. 6 VBAT S lt RTC_ 4 TAMP1 2 B8 B8 7 C1 7 PC13 2 EVENTOUT RTC_TS RTC OUT WKUP2 9 9 8 D1 8 POIA EVENTOUT OSC32 IN OSC32 IN 2 a PC15 1 OSC32_ 4 8 8 9 9 OSC32 OUT Q EVENTOUT OUT I2C2 SDA AQ 06 10 PFO lO EVENTOUT I2C2 SCL 1 05 11 PF1 f EVENTOUT 58 213 DoclD025976 Rev 2 Ly STM32L476xx Pinouts and pin description Table 14 STM32L476xx pin definitions continued Pin Number Pin functions e i 5 o 7 3 Alternate functions Additional m reset gt 3 functions Qu dig 9 32 1Z Z 31313 a z 2 2 5 FMC_A2 D4 12 2 EVENTOUT E4 13 PF3 _ IN5 14 PF4 FT a FMC A4 EVENTOUT ADC3 IN6 F4 15 _ 5 IN7 10 F2 16 VSS S 11 G2 17 VDD 5 5 TIM5 1 18 PF6 FT_a SAM SD EVENTOUT ADC3 IN8 TIM5 CH2 19 PF7 FT a SAI1 MCLK B ADC3 IN9 EVENTOUT 5 CH3 SAM SCK 20 PF8 FT a EVENTOUT ADC3 IN10 5 SAI1 FS
38. 7 lt y life augmented STM32L476xx Ultra low power ARM Cortex M4 32 bit MCU FPU 100DMIPS up to 1MB Flash 128 KB SRAM USB OTG FS LCD analog audio Features e Ultra low power with FlexPowerControl 1 71 V to 3 6 V power supply 40 C to 85 105 125 C temperature range 300 nA in Vgar mode supply for RTC and 32x32 bit backup registers 30 nA Shutdown mode 5 wakeup pins 120 nA Standby mode 5 wakeup pins 420 nA Standby mode with 1 1 pA Stop 2 mode 1 4 pA Stop 2 with RTC 100 pA MHz run mode Batch acquisition mode BAM 4 ys wakeup from Stop mode Brown out reset BOR in all modes except shutdown Interconnect matrix e Core ARM 32 bit Cortex M4 CPU with FPU Adaptive real time accelerator ART Accelerator TM allowing O wait state execution from Flash memory frequency up to 80 MHz MPU 100DMIPS 1 25DMIPS MHz Dhrystone 2 1 and DSP instructions e Clock Sources 4to 48 MHz crystal oscillator 32 kHz crystal oscillator for RTC LSE Internal 16 MHz factory trimmed RC 1 Internal low power 32 kHz RC 5 Internal multispeed 100 kHz to 48 MHz oscillator auto trimmed by LSE better than 0 25 96 accuracy for system clock USB audio ADC RTC with HW calendar alarms and calibration LCD 8 x 40 or 4 x 44 with step up converter Upto 24 capacitive sensing channels support touchkey linear and rotary touch sensors
39. 71 A12 104 PA12 I O FT u CAN1 TX OTG FS DP EVENTOUT JTMS SWDAT OUT 46 2 2 72 A11 105 13 y o FT 4 OTG_FS_NOE EVENTOUT 47 B1 B1 VSS 5 48 A1 A1 73 C11 106 VDDUSB S 74 F11 107 VSS S 75 G11 108 VDD S 4 JTCK SWCLK _ 49 B2 B2 76 A10 109 PA14 EVENTOUT 66 213 DocID025976 Rev 2 Ky STM32L476xx Pinouts and pin description Table 14 STM32L476xx pin definitions continued Pin Number LQFP64 WLCSP72 WLCSP81 LQFP100 UFBGA132 LQFP144 Pin name function after reset PA15 Pin type VO structure FT I Notes Pin functions Alternate functions JTDI TIM2 CH1 2 SPI1 55 SPI3 NSS UARTA RTS DE TSC G3 101 LCD SEG17 SAI2 FS EVENTOUT Additional functions 51 D3 D3 78 B11 111 PC10 I SCK USARTS TX UARTA TX TSC G3 102 LCD COM4A LCD SEG28 LCD 5 40 SDMMC1 D2 SAI2 SCK B EVENTOUT 52 C3 C3 79 C10 112 PC11 FT I SPI3 MISO USART3 RX UART4 RX TSC G3 103 LCD COMS LCD SEG29 LCD SEG41 SDMMC1_D3 SAI2 MCLK B EVENTOUT 53 B3 B3 80 B10 113 PC12 I SPI3 MOSI USART3_ CK UART5 TX TSC G3 104 LCD COM6 LCD SEG30 LCD SEG42 SDMMC1 CK SAI2 SD B EVENTOUT 81 82 C9 B9 114 115 PDO
40. 73 181 359 718 75 138 331 706 1456 mous 100 kHz 33 63 171 348 708 65 128 322 691 1441 1 Based on characterization not tested in production unless otherwise specified sonsiuoj2eJeuo 212 XXQZVTIZEINLS c 94 9768c0GI oq 12 20L Table 32 Current consumption in Low power sleep modes Flash in power down Symbol Ipp LPSleep Conditions TYP MAX Parameter Voltage 25 55 85 C 105 125 25 55 scaling 85 105 125 Supply current in low power 2MHz 81 110 217 395 754 115 182 375 750 1500 fast 1MHz 50 78 185 362 720 80 149 342 717 1456 sleep mode l Peripherals disable 400 kHz 28 57 163 340 698 60 122 314 689 1429 100kHz 18 47 155 332 686 50 114 313 688 1438 Unit HA 1 Based on characterization not tested in production unless otherwise specified 9 1651 212 12 80L 94 9768c0GI oq Table 33 Current consumption in Stop 1 mode Conditions TYP MAX Symbol Parameter Unit 25 C 55 C 85 C 105
41. 8 analog inputs common to the 3 ADCs 8 analog inputs common to the ADC1 amp 2 8 analog inputs for ADC3 VREF 114 AF D 7 0 CMD CK as AF compl channels TIM1_CH 1 3 N 4 channels TIM1 CH 1 4 ETR BKIN BKIN2 as AF compl channels TIM1_CH 1 3 N 4 channels TIM1 CH 1 4 ETR BKIN BKIN2 as AF 2 channels 1 compl channel BKIN as AF 1 channel 1 compl channel BKIN as AF 1 channel 1 compl channel BKIN as AF RX TX CK CTS RTS as AF MOSI MISO SCK NSS as AF MCLK_A SD_A FS_A SCK_A EXTCLK MCLK_B SD_B FS_B SCK_B as AF MCLK A SD A FS A SCK A EXTCLK MCLK B SD B FS B B as AF SDCKIN 7 0 SDDATIN 7 0 SDCKOUT SDTRIG as AF INP INM OUT INP INM OUT Note ETM NVIC BK1 IO 3 0 D BUS Quad SPI memory interface CLK ARM Cortex M4 NoS 80 MHz caris FPU RNG Flash X S BUS gt r55 upto lt 5 1MB VDDUSB SRAM 96 DP BB feo E KC SRAM 32 KB ore a SCL SDA INTN ID VBUS SOF a 5 gt K VDD Power management ne kaa lt VDD 1 71 to 3 6 V 3 3to 12 V VSS DMA1 L VDD VDD MSI reset Supply supervision lt Touch sensing controller RC HSI Int BOR CS YDDIO PHS 4 VDDA VSSA RC SI VDD VSS NRST lt lt AES criororrs lt a 2
42. C 125 C 25 55 85 C 105 C 125 C scaling 26 MHz 0 92 096 1 07 125 1 59 1 012 1 14 1 36 177 240 16MHz 0 61 065 075 0 92 127 069 0 78 0 97 1 32 2 04 8 MHz 0 36 0 40 050 066 1 01 042 0 50 0 68 1 03 1 75 Range 2 4MHz 0 24 0 27 0 37 0 53 0 87 0 28 0 36 0 54 0 89 1 60 tcu up 2 MHz 0 18 020 0 30 0 47 0 81 0215 0 29 0 46 0 82 1 53 Supply included bypass 1MHz 0 15 0 17 0 27 043 0 77 0 18 025 044 0 78 1 49 current mode 100kHz 0 12 0 14 024 0 41 0 74 0 15 021 0 39 0 74 1 44 Ipp Sleep mA 2 4 80 MHz 2 96 3 00 3 13 3 33 3 73 326 3 43 372 4 13 4 97 mode za 72 2 2 69 273 285 3 05 345 296 321 3 50 371 4 54 disable 64 MHz 2 41 245 2 58 277 3 17 2 65 288 3 17 3 58 4 21 Range 1 48 MHz 1 88 1 93 2 07 2 27 2 67 240 227 241 2 83 3 66 32MHz 1 30 1 35 1 48 168 2 08 1 43 1 56 1 85 226 3 10 24 MHz 1 01 1 05 1 17 1 37 1 76 1 11 1 23 1 52 1 93 2 77 16 2 0 71 0 75 0 87 107 145 080 0 90 1 19 1 60 2 44 Supply 2MHz 96 126 233 412 775 130 202 402 777 1527 currentin f 1MHz 65 94 202 381 742 95 166 358 733 1483 Ipp LPSleep low power HCLK MSI sleep l Peripherals disable 400kHz 43
43. EVENTOUT PF1 3 FMC_A1 EVENTOUT PF2 FMC A2 EVENTOUT PF3 z FMC A3 EVENTOUT PF4 FMC A4 EVENTOUT PF5 _ 5 EVENTOUT PF6 SAM SD B EVENTOUT a _ _ Port B PF8 SAM SCK B EVENTOUT PF9 SAM FS B TIM15 CH1 EVENTOUT PF10 E TIM15 CH2 EVENTOUT PF11 EVENTOUT PF12 6 EVENTOUT PF13 FMC A7 EVENTOUT PF14 TSC G8 101 8 EVENTOUT PF15 TSC G8 102 A9 EVENTOUT XXQZVTIZEINLS uonduosep uid pue sjnouid L r8 97 6 20 Table 16 Alternate function AF8 to AF15 for AF0 to AF7 see Table 15 continued AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 Port UART4 SDMMC1 COMP1 TIM2 TIM15 UARTS CAN1 TSC OTG FS QUADSPI LCD COMP2 FMC SAM SAI2 TIM16 TIM17 EVENTOUT LPUART1 SWPMI1 LPTIM2 PGO TSC G8 IO3 FMC A10 EVENTOUT PG1 TSC G8 104 FMC A11 EVENTOUT PG2 FMC A12 SAI2 SCK B EVENTOUT PG3 FMC A13 SAI2 FS B EVENTOUT PG4 FMC A14 EVENTOUT PG5 _ 15 SAI2 SD B EVENTOUT LPUART1 PG6 RTS DE EVENTOUT LPUART1 TX FMC INT3 EVENTOUT Port G LPUART1_ _ EVENTOUT RX FMC NCE3 PG9
44. HSI16 oscillator frequency E Aypp HS 16 drift over Vpp 1 62 V to 3 6 V 0 1 0 2 TBD te HS116 oscillator start up _ _ 0 8 1 2 us HSI16 oscillator _ I Istap HS116 Stabilization time xx Ipg HSI16 9 HS116 oscillator power _ I 155 190 UA consumption Data based on characterization results not tested in production 2 0 05 MHz corresponds to typical deviation after factory trim Guaranteed by design not tested in production q 128 213 DocID025976 Rev 2 STM32L476xx Electrical characteristics Multi speed internal MSI RC oscillator Table 47 MSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit Range 0 100 0 6 TBD Range 1 200 1 2 TBD T 2 2 400 2 4 TBD 3 800 4 8 TBD 4 1 0 006 TBD 5 TBD 2 0 012 TBD MSI mode Range 6 4 0 024 TBD 7 TBD 8 0 048 TBD MHz Range 8 TBD 16 0 096 TBD Range 9 TBD 24 0 144 TBD MSI frequency Range 10 TBD 32 0 192 TBD after factory Range 11 TBD 48 0 288 TBD fusi calibration done at Vpp 3 V and Range 0 98 304 Ta 30 C Range 1 196 608 kHz Range 2 393 216 Range 3 786 432 Range 4 1 016 PLL mode Range 5 1 999 XTAL
45. Pin Number Pin functions functi ft 9 o 7 Alternate functions Additional reset gt D 3 functions oG g dg o 3a Z Z 3 35 1 2 TIM1 1 TIM3 CH2 TIM8 CH1N SPI1 MOSI 5 23 H4 H4 32 45 43 PA7 FT la QUADSPI BK1 102 Apei LCD_SEG4 TIM17_CH1 IN32 EVENTOUT COMP1_ USART3_TX INM 24 J7 J7 33 44 PC4 O FT_la LCD SEG22 EVENTOUT ADC12_ IN13 COMP1 USART3 RX INF 25 J6 J6 34 L5 45 PC5 O FT la LCD SEG23 EVENTOUT WKUP5 TIM1_CH2N TIM3_CH3 TIM8 CH2N OPAMP2 USART3 CK vouT 3 26 45 J5 35 M5 46 PBO TT la QUADSPI BK1 101 ADC12 LCD_SEG5 IN15 COMP1_OUT EVENTOUT TIM1_CH3N TIM3_CH4 TIM8 CH3N DFSDM DATINO edd t 27 J4 J4 36 M6 47 PB1 FT la USART3 RTS DE 12 QUADSPI BK1 100 Nie LCD_SEG6 LPTIM2_IN1 EVENTOUT RTC_OUT LPTIM1_OUT I2C3 SMBA COMP1_ 28 J3 J3 37 L6 48 PB2 O DESDM CKINO NP EVENTOUT 1 6 49 11 J7 50 PF12 6 51 vss s i i i 52 VDD 5 DFSDM DATING Exp nes ide 5 P i FMC_A7 EVENTOUT i DFSDM_CKIN6 8 54 PF14 TSC G8 101 A8 EVENTOUT TSC 68 102 9 55 15 EVENTOUT Ly DoclD025976
46. TIM15 CH1N EVENTOUT LPTIM1 IN1 SPI3 MISO USART1 RX FMC NE3 4 B4 D8 125 PG10 s SAI2 FS TIM15 CHI EVENTOUT LPTIM1 IN2 SPI3 MOSI USART1 CTS C4 C4 G3 126 PG11 5 SAI2 TIM15 CH2 EVENTOUT LPTIM1 ETR SPI3 NSS USART1 RTS DE 5 5 07 127 PG12 5 4 SAI2 SD EVENTOUT I2C1 SDA USART1 CK 5 5 7 128 PG13 FT_fs A24 EVENTOUT I2C1 SCL FMC A25 A5 5 C6 129 PG14 FT fs EVENTOUT F7 130 VSS 5 6 B6 G7 131 VDDIO2 s LPTIM1_OUT FS I2C1 SMBA EVENTOUT 7 68 213 00 10025976 Rev 2 Ky STM32L476xx Pinouts and pin description Table 14 STM32L476xx pin definitions continued Pin Number LQFP64 WLCSP72 WLCSP81 LQFP100 UFBGA132 LQFP144 Pin name function after reset PB3 Pin type VO structure FT_la Notes Pin functions Alternate functions JTDO TRACESWO TIM2_CH2 SPI1_SCK SPI3_SCK USART1_RTS_DE LCD 5 7 5 1 SCK B EVENTOUT Additional functions COMP2_ INM 56 C6 C6 90 AT 134 4 la 4 NJTRST TIM3 1 SPI1_MISO SPI3 MISO USART1_CTS UART5_RTS_DE TSC_G2_101 LCD_SEG8 _ B 17 BKIN EVENTOUT COMP2_ INP 57 C7 C7 91 C5 135 PB5 FT la LPTIM1 IN1 TIM3
47. _ LPUART 2 1 2 EM F I2C3 o MEN SPIx 1 2 3 z CAN 2 SDMMC1 SWPMI1 SAlx 1 2 2 DFSDM ADCx 1 2 3 i s z DACx x 1 2 2 VREFBUF 2 OPAMPx 1 2 COMPXx x 1 2 Temperature O J z sensor Timers TIMx Low power timer 1 LPTIM1 Low power timer 2 LPTIM2 Independent watchdog o 2 o EMO EMO KU im Window watchdog WWDG e am E BEN Ma SysTick timer O O O O 5 2 Touch sensing controller TSC B B o u I i z 1 Ly DoclD025976 Rev 2 27 213 Functional overview STM32L476xx Table 5 Functionalities depending on the working mode continued Stop 1 Stop 2 Standby Shutdown 2 2 2 2 2 2 Low Low 5 5 8 8 Peripheral Run Sleep power power a 8 2 a VBAT run sleep 5 5 5 5 5 5 5 5 5 5 5 5 Random
48. multiprocessor communication mode single wire half duplex communication mode and have LIN Master Slave capability They provide hardware management of the CTS and RTS signals and RS485 Driver Enable They are able to communicate at speeds of up to 10Mbit s USART1 USART2 and USART3 also provide Smart Card mode ISO 7816 compliant and SPI like communication capability All USART have a clock domain independent from the CPU clock allowing the USARTx 1 2 3 4 5 to wake up the from Stop mode The wake up events from Stop mode are programmable and can be e Start bit detection e received data frame e specific programmed data frame All USART interfaces can be served by the DMA controller Low power universal asynchronous receiver transmitter LPUART The device embeds one Low Power UART The LPUART supports asynchronous serial communication with minimum power consumption It supports half duplex single wire communication and modem operations CTS RTS It allows multiprocessor communication The LPUART has a clock domain independent from the CPU clock and can wakeup the system from Stop mode The wake up events from Stop mode are programmable and can be e Start bit detection e received data frame e Aspecific programmed data frame Only a 32 768 kHz clock LSE is needed to allow LPUART communication up to 9600 baud Therefore even in Stop mode the LPUART can wait for an incoming frame while having
49. 16xtimers 2x 16 bit advanced motor control 2x 32 bit and 5x 16 bit general purpose 2x 16 bit basic 2x low power 16 bit timers available in Stop mode 2x watchdogs SysTick timer e Up to 114 fast I Os most 5 V tolerant up to 14 I Os with independent supply down to 1 08 V June 2015 Datasheet production data WLCSP72 WLCSP81 M LQFP144 20 x 20 LQFP100 14 x 14 UFBGA132 LQFP64 10 x 10 7 7 Memories Upto 1 MB Flash 2 banks read while write proprietary code readout protection Up to 128 KB of SRAM including 32 KB with hardware parity check External memory interface for static memories supporting SRAM PSRAM NOR and NAND memories Quad SPI memory interface 4x digital filters for sigma delta modulator Rich analog peripherals independent supply 3x 12 bit ADC 5 Msps up to 16 bit with hardware oversampling 200 2x 12 bit DAC low power sample and hold 2xoperational amplifiers with built in PGA 2x ultra low power comparators e 18x communication interfaces USB 2 0 full speed LPM and BCD 2 SAls serial audio interface 126 FM 1 Mbit s SMBus PMBus 6x USARTs ISO 7816 LIN IrDA modem SPls 4x SPIs with the Quad SPI CAN 2 0B Active and SDMMC interface SWPMI single wire protocol master I F 14 channel DMA controller e True random number generator e CRC calculation unit 96 bit unique ID e
50. 2 ta CLKH NWEH FMC_CLK high to FMC_NWE high 1 ta cLKL Data FMC_D 15 0 valid data after low 4 5 _ low to FMC_NBL low 1 5 ty CLKH NBLH CLK high to NBL high Tucik 1 tsu NWAIT CLKH NWAIT valid before CLK high 0 FMC NWAIT valid after high 4 CL 30 pF 2 Based on characterization not tested in production NAND controller waveforms and timings Unit ns Figure 43 through Figure 46 represent synchronous waveforms and Table 97 and Table 98 provide the corresponding timings The results shown in these tables are obtained with the following FMC configuration COM FMC SetupTime 0x02 COM FMC_WaitSetupTime 0x03 COM FMC_HoldSetupTime 0x02 COM FMC_HiZSetupTime 0x03 ATT FMC_SetupTime 0x01 ATT FMC_WaitSetupTime 0x03 ATT FMC_HoldSetupTime 0x02 ATT FMC_HiZSetupTime 0x03 Bank FMC_Bank_NAND MemoryDataWidth FMC_MemoryDataWidth_16b ECC FMC_ECC_Enable ECCPageSize FMC_ECCPageSize_512Bytes TCLRSetupTime 0 TARSetupTime 0 In all timing tables the is the HCLK clock period DoclD025976 Rev 2 189 213 Electrical characteristics STM32L476xx 190 213 Figure 43 NAND controller waveforms for read access FMC_NCEx M ALE A17 CLE FMC A16 FMC NWE la NCE NOE th NOE ALE FMC_NOE NRE
51. 3 6 V gt 2 V 2 VppA VREF Positive reference voltage lt 2 V VppA V Negative reference VREF voltage VssA V Range 1 80 fADC ADC clock frequency MHz Range 2 26 Resolution 12 bits 5 33 Sampling rate for FAST Resolution 10 bits 6 15 channels Resolution 8 bits 7 27 Resolution 6 bits 8 88 fs Msps Resolution 12 bits 4 21 Sampling rate for SLOW Resolution 10 bits 4 71 channels Resolution 8 bits 5 33 Resolution 6 bits 6 15 fapt BO Mie 5 33 MHz frRIG External trigger frequency Resolution 12 bits Resolution 12 bits 15 1 3 Conversion voltage _ _ range 2 0 VREF V RAIN External input impedance 50 kQ Internal sample and hold Canc capacitor 7 I 5 pr Power up time 1 cycle fApc 80 MHz 1 45 us tcaL Calibration time 3 116 1 fapc CKMODE 00 1 5 2 2 5 Trigger conversion t latency Regular and CKMODE 01 i 2 0 4t LATR injected channels without CKMODE 10 _ _ 225 ADC conversion abort CKMODE 11 2 125 146 213 DocID025976 Rev 2 Ly STM32L476xx Electrical characteristics Table 62 ADC characteristics 2 continued Symbol Parameter Conditions Min Typ Max Unit CKMODE 00 2 5 3 3 5 Trigger conversion t latency Injected channels CKMODE 01 3 0 LATRINJ aborting a regular CKMODE 10 3 25 ADC conversion
52. 32 768 kHz Range 6 3 998 Range 7 7 995 MHz Range 8 15 991 Range 9 23 986 Range 10 32 014 Range 11 48 005 MSI oscillator 0 to 85 1 55 1 2 frequency drift MSI mode oO over temperature 40 to 125 C 4 TBD Ly DoclD025976 Rev 2 129 213 Electrical characteristics STM32L476xx Table 47 MSI oscillator characteristics continued Symbol Parameter Conditions Min Typ Max Unit Vpp 1 62 V to 3 6V 0 3 1 TBD Range 0 to 3 DD lt io 36 V 0 3 0 4 TBD MSI oscillator Ml 0 5 2 TBD i Aypo Msiy2 freauency drit MSi mode Range 4 07 Vpp 2 4 V reference is 3 V to 3 6 V 0 5 0 7 TBD Vpp 1 62 V i6 36V 0 8 4 5 TBD Range 8 to 11 TTET DD lt _ 3 036V 0 8 1 4 TBD AF Frequency 40 to 85 C 1 2 PANGON variation in MSI mode Man sampling mode 40 to 125 2 4 amp 3 458 P USB Period jitter for mode transition Jitter MSI USB clock Range 11 for paired ass transition for next _ _ _ 2 MT_USB Medium term jitter PLL mode transition Jitter MSI for USB clock Range 11 for paired transition CC cycleto bii mode Range 11 60 ps cycle jitter 51 9 RMS Period jitter PLL mode Range 11 50 ps Range 0 10 20 Rang
53. APB clock External clock source over LPTIM input working even with no internal clock source running used by pulse counter application e Programmable digital glitch filter e Encoder mode LPTIM1 only Independent watchdog IWDG The independent watchdog is based on a 12 bit downcounter and 8 bit prescaler It is clocked from an independent 32 kHz internal RC LSI and as it operates independently from the main clock it can operate in Stop and Standby modes It can be used either as a watchdog to reset the device when a problem occurs or as a free running timer for application timeout management It is hardware or software configurable through the option bytes The counter can be frozen in debug mode System window watchdog WWDG The window watchdog is based on a 7 bit downcounter that can be set as free running It can be used as a watchdog to reset the device when a problem occurs It is clocked from the main clock It has an early warning interrupt capability and the counter can be frozen in debug mode SysTick timer This timer is dedicated to real time operating systems but could also be used as a standard down counter It features e A 24 bit down counter Autoreload capability e Maskable system interrupt generation when the counter reaches 0 e Programmable clock source q DocID025976 Rev 2 STM32L476xx Functional overview 3 25 q Real time clock RTC and backup registers is
54. CKMODE 11 3 125 fapc 80 MHz 0 03125 8 00625 Hs ts Sampling time 2 5 640 5 1 fapc ADC voltage regulator 20 tADCVREG_STUP start up time E 80 2 Resolution 12 bits p 1875 I 8 1625 us t Total conversion time CONV including sampling time ts 12 5 cycles for Resolution 12 bits successive approximation 1 15 to 653 fs 5 Msps 740 1100 ADC consumption from Ippa ADC the supply fs 1 Msps 160 310 fs 10 ksps 16 TBD ADC consumption from pompe 125 280 Ippv_s ADC Vgge single ended 15 1 Msps 30 60 mode fs 10 ksps 2 0 6 ADC consumption from e o I em 400 p ADC the Vggr differential fs 1 Msps 60 120 mode fs 10 ksps 1 3 TBD Data guaranteed by design not tested in production 2 I O analog switch voltage booster is enable when Vppa lt 2 4 V BOOSTEN 1 in the SYSCFG_CFGR1 when VppA lt 2 4 It is disable when 2 2 4 V 3 Vper be internally connected to and Vref can be internally connected to depending on the package to Section 4 Pinouts and description for further details q DocID025976 Rev 2 147 213 Electrical characteristics STM32L476xx Equation 1 Rajj max formula Rain Ts N 2 X Canc X In 2 Ranc The formula above Equation 1 1 used to determine the maximum external imp
55. High speed external clock source AC timing diagram VHSEH VHSEL it 1 I 4 0 1 t tr HSE iare 2 gt e HsE D tw HSEL ij Tusg MS19214V2 Ly DoclD025976 Rev 2 123 213 Electrical characteristics STM32L476xx Low speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO The external clock signal has to respect the characteristics in Section 6 3 14 However the recommended clock input waveform is shown in Figure 16 Table 43 Low speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit fisg ext User external clock source frequency 32 768 1000 kHz OSC32 IN input pin high level voltage 0 7 Vppiox Vppiox OSC32 IN input pin low level voltage Vss 0 3 Vppiox IwLSEH OSC32_IN high or low time 250 ns tw LSEL 1 Guaranteed by design not tested in production 124 213 Figure 16 Low speed external clock source AC timing diagram VLSEL MS19215V2 q DocID025976 Rev 2 STM32L476xx Electrical characteristics q High speed external clock generated from resonator The high speed external HSE clock can be supplied with a 4 to 48 MHz crystal ceramic resonator oscillator All
56. SDMMC1_D6 SAI2 MCLK A EVENTOUT TIM3 2 TIM8 CH2 DFSDM DATIN3 TSC G4 102 38 1 1 64 E11 97 VO LCD_SEG25 SDMMC1_D7 SAI2_MCLK_B EVENTOUT DoclD025976 Rev 2 65 213 Pinouts description STM32L476xx Table 14 STM32L476xx pin definitions continued Pin Number Pin functions functi ft 9 o 7 Alternate functions Additional reset gt D 3 functions Olalla O u o 2a2a Z Z 3 3 24 a z TIM3_CH3 TIM8_CH3 TSC_G4_IO3 39 F2 F2 65 E10 98 FT I LCD SEG26 SDMMC1 DO EVENTOUT TIM8 BKIN2 TIM3 4 TIM8 CH4 TSC G4 104 OTG FS NOE LCD SEG27 40 E1 E1 66 D12 99 9 FT I SDMMCH D1 SAI2 EXTCLK TIM8 BKIN2 COMP 1 EVENTOUT TIM1 1 5 1 CK 41 E2 E2 67 D11 100 PA8 FT I OTG FS SOF LCD COMO LPTIM2 OUT EVENTOUT TIM1 CH2 USART1 TX OTG FS 42 68 D10 101 9 FT lu LCD 1 15 BKIN VBUS EVENTOUT TIM1 CH3 USART1 RX 43 02 D2 69 C12 102 PA10 VO FT lu FS ID LCD 2 TIM17 BKIN EVENTOUT TIM1 CH4 TIM1 BKIN2 USART1_CTS CAN1_RX 44 1 01 70 12 103 PA11 FT_u OTG_FS_DM 1 2 1 1 USART1 RTS DE 45 C1 C1
57. Table 16 Alternate function AF8 to AF15 for AF0 to AF7 see Table 15 continued AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 Port UARTA SDMMC1 1 TIM2 TIM15 5 CAN1 TSC OTG FS QUADSPI LCD COMP2 FMC SAM SAI2 TIM16 TIM17 EVENTOUT LPUART1 SWPMI1 LPTIM2 PBO i QUADSPI BK1 101 LCD_SEG5 COMP1 OUT 2 EVENTOUT PB1 QUADSPI BK1 100 LCD SEG6 LPTIM2 IN1 EVENTOUT PB2 EVENTOUT PB3 LCD_SEG7 SAM SCK B B EVENTOUT PB4 a a TSC_G2_IO1 LCD_SEG8 17 EVENTOUT PB5 UART5_CTS TSC G2 102 LCD_SEG9 COMP2_OUT SAM SD B TIM16 BKIN EVENTOUT PB6 gt TSC_G2_103 TIME BENZ SAM FS B TIM16 CH1N EVENTOUT COMP2 TIM8 BKIN 7 UARTA CTS TSC G2 104 LCD_SEG21 FMC_NL COMP4 TIM17_CH1N EVENTOUT PortB PB8 CAN1 RX LCD SEG16 SDMMC1 D4 TIM16 CH1 EVENTOUT PB9 CAN1 TX LCD SDMMC1 D5 SAM FS A 17 CH1 EVENTOUT PB10 ik j QUADSPI_CLK LCD_SEG10 COMP1_OUT SAI1_SCK_A EVENTOUT PB11 LPUART1 TX QUADSPI NCS LCD_SEG11 COMP2_OUT EVENTOUT LPUART1 PBi2 ors pe 180201101 i LCD_SEG12 SWPMI1_IO SAI2 FS A TIM15 BKIN EVENTOUT LPUART1 PB13 cre 18061108 LCD_SEG13 SWPMI1_TX SAI2 SCK A TIM15_CH1N EVENTOUT PB14 TSC G1 103 LCD_SEG14 SWPMI1_RX dr cae TIM15 CH1 EVENTOUT PB15 TSC G1 104 LCD 5 15 SWPMI1_SUSPEND SAI2 SD A TIM15 CH2 EVENTOUT
58. Table 22 Operating conditions at power up power down Symbol Parameter Conditions Min Max Vpp rise time rate 0 tvpp a Vpp fall time rate 10 Vppa rise time rate 0 WDDA time rate 10 Vppussg rise time rate 0 10 Vpplio2 rise time rate 0 10 Unit us V Embedded reset and power control block characteristics The parameters given in Table 23 are derived from tests performed under the ambient temperature conditions summarized in Table 21 General operating conditions DoclD025976 Rev 2 q STM32L476xx Electrical characteristics Table 23 Embedded reset and power control block characteristics Symbol Parameter Conditions Min Typ Max Unit 2 Reset temporization after 55 _ tRsTTEMPO BORO is detected Yap rising 290 200 Hs Rising edge 1 62 1 66 1 7 VBoro 2 Brown out reset threshold 0 V Falling edge 1 6 1 64 1 69 Rising edge 2 06 2 1 2 14 VBOR1 Brown out reset threshold 1 V Falling edge 1 96 2 2 04 Rising edge 2 26 2 31 2 35 VBoR2 Brown out reset threshold 2 V Falling edge 2 16 2 20 2 24 Rising edge 2 56 2 61 2 66 VBoR3 Brown out reset threshold 3 V Falling edge 2 47 2 52 2 57 Rising edge 2 85 2 90 2 95 VBOR4 Brown out reset threshold 4 V Falling edge 2 76 2 81 2 86 Programmable
59. VppA lt 2 4 V Low power mode 80 Normal mode 55 110 AO Open loop gain dB Low power mode 45 110 Normal mode VopDA _ V 3 High saturation max or Rigag 100 OMSAT voltage min Input at Vppa IVan Low power mode ca mV Vo sar Low saturation Normal mode load 100 voltage Low power mode min Input at 0 50 Normal mode 74 Om Phase margin i Low power mode 66 Normal mode 13 GM Gain margin dB Low power mode 20 CLOAD lt 50 pf Normal mode RLoan 5 4 5 10 follower Wake up time configuration twAKEUP us from OFF state lt 50 pf Low power mode 20 kQ 10 30 follower configuration Dedicated input BGA132 only 4 OPAMP input A Ibias bias current General purpose input all packages _ _ 4 n except BGA132 2 4 gain Non inverting _ _ gain value 8 i 16 160 213 00 10025976 2 STM32L476xx Electrical characteristics Table 69 OPAMP characteristics continued Or P w N gt q Data based on characterization not tested in production Data guaranteed by design not tested in production unless otherwise specified The temperature range is limited to 0 C 125 C when Vppa is below 2 V DocID025976 Rev 2 Mostly I O leakage when used in analog mode Refer to ly parameter in Table 57 I O static cha
60. e Readout protection to protect the whole memory Three levels are available Level 0 no readout protection Level 1 memory readout protection the Flash memory cannot be read from or written to if either debug features are connected boot in RAM or bootloader is selected Level 2 chip readout protection debug features Cortex M4 JTAG and serial wire boot in RAM and bootloader selection are disabled JTAG fuse This selection is irreversible Table 3 Access status versus readout protection level and execution modes er xecution Debug boot from RAM or boot A Protection from system memory loader rga level Read Write Erase Read Write Erase Main 1 Yes Yes Yes No No No memory 2 Yes Yes Yes N A N A N A System 1 Yes No No Yes No No memory 2 Yes No No N A N A N A Option 1 Yes Yes Yes Yes Yes Yes bytes 2 Yes No No N A N A N A Backup 1 Yes Yes N AC No No N AC registers 2 Yes Yes N A N A N A N A 1 Yes Yes 01 1 SRAM2 2 Yes Yes Yes N A N A N A 1 Erased when RDP change from Level 1 to Level 0 e Write protection WRP the protected area is protected against erasing and programming Two areas per bank can be selected with 2 Kbyte granularity e Proprietary code readout protection PCROP a part of the flash memory can be protected against read and write from third parties The protected area is execute only it can only be reached by the
61. lt Vpp lt 3 6 V Voltage Range 1 Slave mode 1 71 Vpp 3 6 V 450 Voltage Range 1 129 30 12 5 19 Data output valid time ns Slave mode 1 71 lt Vpp lt 3 6 V Voltage Range 2 Slave mode 1 08 lt Vppio2 lt 1 32 V9 25 62 5 12 5 33 tv MO Master mode 2 5 12 5 tn so Slave mode 9 Data output hold time Slave mode 1 08 lt Vppiog lt 1 32 24 ns tho Master mode 0 Data based characterization results not tested production 2 Maximum frequency in Slave transmitter mode is determined by the sum of tv so and tsumi which has to fit into SCK low or high phase preceding the sampling edge This value can be achieved when the SPI Communicates with a master having 0 while Duty SCK 50 3 SPI mapped on Port G Figure 26 SPI timing diagram slave mode and CPHA 0 NSS input tsu NSs ee th NSS y I 1 1 CPHA 0 CPOL 0 1 I CPHA 0 i 4450 betes phe tSc tdis S0 la OUT SCK Input ta SO gt d 1 1 1 er 1 1 6 OUT LSB OUT OUTPUT X em h 1 I I tsu S r MOSI BUT MSBIN BIT1 IN o isn X IN ai14134c q DocID025976 Rev 2 167 213 Electrical characteristics STM32L476xx Figure 27 SPI timing diagram slave mode and CPHA
62. 0 0039 ddd 0 050 0 0020 eee 0 050 0 0020 1 Values in inches are converted from mm and rounded to 4 decimal digits 2 Back side coating 3 Dimension is measured at the maximum bump diameter parallel to primary datum Z Figure 56 WLCSP81 81 pin 4 4084 x 3 7594 mm 0 4 mm pitch wafer level chip scale package recommended footprint Dpad Dsm 000000000 000000000 000000000 000000000 000000000 000000000 00000000 00000000 99980 057 V1 Table 103 WLCSP81 recommended design rules 0 4 pitch Dimension Recommended values Pitch 0 4 mm Dpad 0 225 mm 0 290 mm typ depends on the soldermask Dsm registration tolerance Stencil opening 0 250 mm Stencil thickness 0 100 mm 202 213 DocID025976 Rev 2 Ky STM32L476xx Package information T 5 q WLCSP72 package information Figure 57 WLCSP72 72 pin 4 4084 x 3 7594 mm 0 4 mm pitch wafer level chip scale package outline 77 bbb Z N x Detail 1 2 1 location Bottom view A Top view Bump side Side view Wafer back side Bump eee z N A1 b 2 did i M ccc Q Z XIY Seati 2 Detail A Sag p ane rotated by 90 A02R_ME V1 1 Drawing is not to scale T
63. 1 NSS input N I 50 558 r c SCK th NSS 5 1 1 s CPHA 1 N 1 2 CPOL 0 TS i T n 1 mtwsck p 1 ii 73 CPOL 1 ld el 1 1 h T gt SCK tdis S0 ta S0 9 14 MISO OUTPUT OUT BITS OUT OUT 50 51 i th si MOSI ai14135b 1 Measurement points are done at CMOS levels 0 3 Vpp and 0 7 Vpp Figure 28 SPI timing diagram master mode High NSS input 4 tsch 8 0 N 5 CPOL 0 ES 1 x 0 1 T o i 3 1 N 5 0 i 1 i 1 1 n i i E 1 1 1 i SCKH ie p tr ScK MISO ji lw SCKL Uc mem E TEN SCK INPUT i MSBIN BITS IN I th M MOSI S UTPUT MSBOUT BIT1 OUT ai14136c 1 Measurement points are done at CMOS levels 0 3 Vpp and 0 7 Vpp q 168 213 DocID025976 Rev 2 STM32L476xx Electrical characteristics Quad SPI characteristics Unless otherwise specified the parameters given in Table 79 and Table 80 for Quad SPI are derived from tests performed under the ambient temperature fayp frequency and Vpp supply voltage conditions summarized in Table 21 General operating conditions with the fo
64. 1 54 424 157 367 816 3 3 11 39 92 204 3 6V 1 75 4 47 16 1 38 3 85 4 3 5 11 40 96 214 sonsiuoj2eJeuo e2129 3 XXQZVTIZEINLS 97 6 0 Table 35 Current consumption Stop 2 mode continued Conditions TYP 1 Symbol Parameter Unit 25 C 55 85 C 105 C 125 25 55 85 C 105 C 125 C 18V 1 42 404 15 34 9 77 2 3 1 10 38 87 193 RTC clocked by LSI 24V 15 4 22 154 357 79 2 32 11 39 89 198 LCD disabled 3V 164 4 37 158 36 7 81 4 3 4 11 40 92 204 3 6 1 79 465 166 38 4 854 36 12 42 96 214 1 8V 1 53 4 07 151 351 774 33 10 38 88 194 RTC clocked by LSI 2 4V 1 62 432 155 359 79 5 34 11 39 90 199 LCD enabled 169 443 159 368 817 35 11 40 92 204 Ipp Stop 2 id E 3 6V 1 86 465 167 385 855 37 12 42 96 214 with RTC enabled 1 8V 15 443 152 353 77 6 92 10 38 88 194 RTC clocked by LSE 24 163 4 33 156 36 79 6 34 11 39 90 199 bypassed at 32768Hz LCD disabled 3V 179 455 16 1 37 818 36 11 40 93 205 36V 204 49 168 387 856 39 12 42 97 214 RTC clocked by LSE 18V 143 399 147 35 E 3 2 10 37 88 quartz 24V 1 54 411 15 35 8 I 3 3 10 38 90 P in low drive mode 3v 167 429
65. 155 36 7 3 4 11 39 92 Eee disabled 36V 1 87 457 162 383 37 11 41 96 wakeup clock is MSI 48 MHz 19 Voltage Range 1 Supply wakeup clock is Ipp wakeup during wakeup MSI 4 MHz 3V 21 _ _ E _ mA from Stop2 from Stop Voltage Range 2 2mode wakeup clock is 5116 16 MHZ 2 24 I Voltage Range 1 y Based on characterization not tested in production unless otherwise specified Tested in production LCD enabled with external voltage source Consumption from VLCD excluded Refer to LCD controller characteristics for ly cp Based on characterization done with a 32 768 kHz crystal MC306 G 06Q 32 768 manufacturer JFVNY with two 6 8 pF loading capacitors 9 TZEINLS 212 94 926S20C190d Table 36 Current consumption Standby mode Conditions TYP MAX Symbol Parameter Unit 25 55 C 85 C 105 125 C 25 C 55 85 C 105 C 125 C 18V 114 355 1540 4146 10735 176 888 3850 10365 26838 24V 138 407 1795 4828 12451 223 1018 4488 12070 31128 Supply current no independent watchdog 150 486 2074 5589 14291 263 1215 5185 13973 35728 mode backup 3 6V 198 618 2608 6928 17499 383
66. 25 7 67 8 50 32MHz 422 428 442 4 63 5 03 464 4 86 5 15 5 56 6 19 24MHz 3 20 3 25 3 38 3 59 3 99 3 52 3 70 384 426 5 09 16 MHz 2 18 222 235 2 55 2 94 240 2 55 2 84 325 4 09 2MHz 242 275 384 562 924 300 380 573 927 1677 Suppl 2 fusi 1MHz 130 162 269 445 809 180 243 435 810 1560 Ipp LPRun all peripherals disable HA M raid FLASH in power down 400 kHz 61 90 197 374 734 95 160 353 728 1478 100 kHz 26 56 163 339 702 55 122 314 679 1429 1 Based characterization not tested in production unless otherwise specified XXQZVTIZEINLS 212 Electrical characteristics STM32L476xx Table 28 Typical current consumption in Run and Low power run modes with different codes running from Flash ART enable Cache ON Prefetch OFF Symbol Ipp Run Ipp LPRun Parameter Supply current in Run mode Supply current in Low power run Conditions TYP TYP Unit Unit Voltage Code 25 C 25 C scaling Reduced code 2 9 111 I lt gt 3 1 118 2 Dhrystone 2 1 3 1 mA 119 HA MHz f f u y 3 Fibonacci 2 9 112 included bypass While 1 2 8 108 mode PLL ON above 48
67. 7 04 253 942 211 443 18 63 236 528 1108 2 i disabled regulator in lowi 749 257 950 212 446 18 64 238 530 1115 power mode 36V 7 97 260 961 215 451 20 65 240 538 1128 RTC clocked by 18V 6 85 25 0 93 0 208 3 17 63 233 521 3 a LCD 24V 6 94 251 932 209 3 17 63 233 523 i ow qrive moqe disabled s regulator ii lods 7 10 252 93 6 210 3 18 63 234 526 power mode 36V 7 34 254 941 2123 18 64 235 531 sonsiuoj2eJeuo 212 9 TIZEINLS c 94 9768c0GI oq 12 60L Table 33 Current consumption in Stop 1 mode continued Conditions TYP MAX Symbol Parameter Vpp 25 C 55 C 85 105 125 25 55 85 C 105 125 2 E em 48 MHz 3V 1 47 P Supply current orage sange 155 wakeup during wakeup clock MSI 4 1 62 _ _ _ _ from Stop1 wakeup from Voltage Range 2 Stop 1 wakeup clock 5116 3V 17 I _ 16 MHz Voltage Range 1 Unit mA 1 Based on characterization not tested in production unless otherwise specified 2 LCD enabled with external voltage source Consumption from VLCD excluded Refer to LCD controller characteristics for cp 3 Basedon characterization done with a 32 768 kHz crystal MC306 G 06Q 32 768
68. AF TIM5 TIM8 TIM3 TIM4 TIM8 12C1 12C2 12C3 SPIT SPI2 SPI3 DFSDM USART2 LPTIM1 TIM5 USART3 PAO 2 CH1 5 1 TIM8 ETR USART2 CTS PA1 TIM2 CH2 TIM5 CH2 uui PA2 TIM2 CH3 TIM5 CH3 USART2 TX PA3 TIM2 4 TIM5 CH4 USART2 RX 4 SPI1 NSS SPI3 NSS USART2 CK PA5 TIM2 CH1 TIM2 ETR TIM8 CH1N SPI1 SCK PA6 TIM1 BKIN TIM3 CH1 TIM8 BKIN SPI1 MISO USART3 CTS PA7 TIM1 CH1N TIM3 CH2 TIM8 CH1N SPI1 MOSI Port A TIM1 CH1 USART1 PA9 TIM1 CH2 USART1_TX PA10 TIM1_CH3 USART1_RX PA11 TIM1 4 1 2 USART1 CTS PA12 TIM1 ETR USARTI RIS DE PA13 JTMS SWDAT IR_OUT PA14 JTCK SWCLK PA15 JTDI TIM2 CH1 TIM2 ETR SPI1 NSS SPI3 NSS XXQZV TZEINLS uonduosep uid pue sjnouid ELe el c 94 9768c0GI oq Table 15 Alternate function AF0 to AF7 for AF8 to AF15 see Table 16 continued AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 Port TIM1 TIM2 TIM1 TIM2 USART1 SYS_AF TIM5 TIM8 TIM3 TIM4 TIM8 12C1 12C2 12C3 SPI1 SPI2 SPI3 DFSDM USART2 LPTIM1 TIM5 USART3 PBO TIM1_CH2N TIM3_CH3 8 2 5 1 TIM1 CH3N TIM3 4 TIM8 CH3N DFSDM DATINO 2 RTC OUT LPTIM1 OUT I2C3 SMBA DFSDM CKINO PB3 JTDOMRACES TIM2_CH2 SPI1_SCK 5
69. B 21 PF9 FT a TIM15 CH1 EVENTOUT ADC3 IN11 22 10 VO 15 CH2 EVENTOUT ADC3 IN12 5 D9 D9 12 F1 23 PHO OSC OSC IN 6 08 08 13 G1 24 PH1 OSC OUT I O FT EVENTOUT OSC OUT 7 9 E9 14 H2 25 NRST RST LPTIM1_IN1 I2C3 SCL DFSDM DATINA 8 F9 F9 15 H1 26 PCO FT fla LPUART1 RX LCD_SEG18 LPTIM2_IN1 EVENTOUT LPTIM1 OUT I2C3 SDA DFSDM CKINA ADC123 9 F8 F8 16 42 27 PC1 FT fla LPUART4 TX IN2 LCD SEG19 EVENTOUT LPTIM1 IN2 SPI2 MISO ADC123 10 F7 F7 17 J3 28 PC2 FT la DFSDM CKOUT N3 LCD_SEG20 EVENTOUT LPTIM1_ETR SPI2_MOSI LCD_VLCD ADC123_ 11 G7 G7 18 K2 29 SAM SD A INA LPTIM2 ETR EVENTOUT 19 30 VSSA 20 31 VREF Ly DoclD025976 Rev 2 59 213 Pinouts description STM32L476xx Table 14 STM32L476xx pin definitions continued Pin Number Pin functions Pin name e 5 83 a o 7 5 Alternate functions Additional amp reset gt D 3 functions G g G u OG 31 Z Z 3 3 2 12 69 69 J1 VSSANREF VREFBUF G8 G8 21 L1 32 VREF s OUT 13 H9 H9 22 1 33 VDDA s 2 1 TIM5_CH1 OPAMP1_ TIM8
70. I Os state under and after reset is analog state the schmitt trigger is disable In addition the internal reset pull up is deactivated when the reset source is internal 3 9 6 VBAT operation The VBAT pin allows to power the device VBAT domain from an external battery an external supercapacitor or from Vpp when no external battery and an external supercapacitor are present The VBAT pin supplies the RTC with LSE and the backup registers Three anti tamper detection pins are available in VBAT mode VBAT operation is automatically activated when Vpp is not present An internal VBAT battery charging circuit is embedded and can be activated when Vpp is present Note When the microcontroller is supplied from VBAT external interrupts and RTC alarm events do not exit it from VBAT operation 28 213 DoclD025976 Rev 2 Ly STM32L476xx Functional overview 3 10 Several peripherals have direct connections between them This allows autonomous Interconnect matrix communication between peripherals saving CPU resources thus power supply consumption In addition these hardware connections allow fast and predictable latency Depending on peripherals these interconnections can operate in Run Sleep low power run and sleep Stop 1 and Stop 2 modes Table 6 STM32L476xx peripherals interconnect matrix Interconnect source Interconnect Interconnect acti
71. IEC 61000 4 4 standard A device reset allows normal operations to be resumed The test results are given in Table 52 They are based on the EMS levels and classes defined in application note AN1709 Table 52 EMS characteristics Level Symbol Parameter Conditions Class Voltage limits to be applied on any pin 3 3 V Ta 25 C VrFESD 80 MHz 3B to induce a functional disturbance conforming to IEC 61000 4 2 Fast transient voltage burst limits to be Vpp 3 3 V 25 Verte applied through 100 pF on Vss 80 MHz 4 pins to induce functional disturbance conforming to IEC 61000 4 4 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application Software recommendations The software flowchart must include the management of runaway conditions such as Corrupted program counter e Unexpected reset e Critical Data corruption control registers DocID025976 Rev 2 135 213 Electrical characteristics STM32L476xx
72. MSv35083V5 1 The above figure shows the package top view q 56 213 DocID025976 Rev 2 STM32L476xx Pinouts and pin description Figure 9 STM32L476Rx LQFP64 pinout VBAT PC13 PC14 OSC32 IN 15 05 32 OUT PHO OSC PH1 OSC OUT NRST PCO PC1 PC2 PC3 VSSANREF VDDA VREF PAO PA1 PA2 VDDUSB VSS PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC6 PB15 PB14 PB13 PB12 LQFP64 MS31272V3 1 The above figure shows the package top view Table 13 Legend abbreviations used in the pinout table Name Abbreviation Definition Unless otherwise specified brackets below the function during after Pin name reset is the same as the actual pin name S Supply pin Pin type Input only Input output FT 5 V tolerant I O TT 3 6 V tolerant I O B Dedicated RST Bidirectional reset pin with embedded weak pull up resistor Option for TT or FT I Os structure E Fm capable 409 I O with LCD function supplied by Vi cp 8 with USB function supplied by Vppusg _ 4 with Analog switch function supplied by ss 9 supplied only by Vppioz Notes Unless otherwise specified by a note all l Os are set as analog inputs during and after reset Alternate Functions selected through GPIOx AFR registers Pin functio
73. Max Unit Ambient temperature forthe Maximum power dissipation 40 85 suffix 6 version Low power dissipation 40 105 Ambient temperature for the Maximum power dissipation 40 105 suffix 7 version Low power dissipation 40 125 Ambient temperature for the Maximum power dissipation 40 125 suffix 3 version Low power dissipation 40 130 Suffix 6 version 40 105 TJ Junction temperature range Suffix 7 version 40 125 Suffix 3 version 40 130 When is released functionality is guaranteed down to Min 2 This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table Maximum I O input voltage is the smallest value between MIN Vpp Vppio2 Vicp 3 6 V 5 5V 3 operation with voltage higher than Min Vpp VppA Vppio2 Vr cp 0 3 V the internal Pull up and Pull Down resistors must be disabled 4 If T is lower higher Pp values are allowed as long as does not exceed see Section 7 7 Thermal characteristics In low power dissipation state Ta can be extended to this range as long as does not exceed jmax see Section 7 7 Thermal characteristics 6 3 2 6 3 3 96 213 Operating conditions at power up power down The parameters given in Table 22 are derived from tests performed under the ambient temperature condition summarized in Table 21
74. Rev 2 61 213 Pinouts description STM32L476xx Table 14 STM32L476xx pin definitions continued Pin Number Pin functions Pin name e 3 o 7 Alternate functions Additional amp reset gt i 3 functions cGl3 3 G u o 32 Z Z 3 41 a z TSC 68 A10 H9 56 PG0 y o FT EVENTOUT TSC G8 04 A11 G9 57 PG1 yo FT EVENTOUT TIM1 ETR DFSDM DATIN2 Ee 38 7 58 y o FT 04 SAM SD B EVENTOUT TIM1 CH1N F6 39 L7 59 PE8 yo FT DESDM CKIN2 FMC D5 SAI1 SCK B EVENTOUT TIM1 CH1 DFSDM CKOUT 40 8 60 9 yo FT D6 FS B EVENTOUT F6 61 VSS S G6 62 VDD S TIM1 CH2N DFSDM_DATIN4 TSC_G5_101 41 18 63 PE10 QUADSPI 07 SAI1 MCLK B EVENTOUT TIM1 CH2 DFSDM_CKIN4 42 9 64 PE11 TSC G5 102 QUADSPI NCS FMC D8 EVENTOUT TIM1 SPI1 NSS DFSDM DATIN5 43 19 65 12 y o FT TSC G5 103 QUADSPI 1 100 9 EVENTOUT TIM1 CHS3 SPI1 SCK DFSDM CKIN5 44 M10 66 PE13 y o FT TSC G5 104 QUADSPI BK4 101 D10 EVENTOUT TIM1 4 TIM1 BKIN2 TIM1 BKIN2 COMP2 45
75. STMTouch touch sensing firmware library The number of capacitive sensing channels is dependent on the size of the packages and subject to availability DoclD025976 Rev 2 39 213 Functional overview STM32L476xx 3 21 3 22 40 213 Liquid crystal display controller LCD The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320 pixels e Internal step up converter to guarantee functionality and contrast control irrespective of Vpp This converter can be deactivated in which case the VLCD pin is used to provide the voltage to the LCD e Supports static 1 2 1 3 1 4 and 1 8 duty e Supports static 1 2 1 3 and 1 4 bias e Phase inversion to reduce power consumption and EMI e Integrated voltage output buffers for higher LCD driving capability e Upto 8 pixels can be programmed to blink e Unneeded segments and common pins can be used as general I O pins e LCD RAM can be updated at any time owing to a double buffer e The LCD controller can operate in Stop mode Digital filter for Sigma Delta Modulators DFSDM The device embeds one DFSDM with 4 digital filters modules and 8 external input serial channels transceivers or alternately 8 internal parallel inputs support The DFSDM peripheral is dedicated to interface the external 2A modulators to microcontroller and then to perform digital filtering of the received data streams which represent analog value on 2A modulators inputs DFSDM can al
76. Symbol fsck l tcisck Parameter SPI clock frequency Conditions Master mode receiver full duplex 2 7 lt Vpp lt 3 6 V Voltage Range 1 Master mode receiver full duplex 1 71 lt Vpp lt 3 6 V Voltage Range 1 Master mode transmitter 1 71 lt Vpp lt 3 6 V Voltage Range 1 Slave mode receiver 1 71 lt Vpp lt 3 6 V Voltage Range 1 Slave mode transmitter full duplex 2 7 lt Vpp lt 3 6 V Voltage Range 1 Slave mode transmitter full duplex 1 71 lt Vpp lt 3 6 V Voltage Range 1 Voltage Range 2 1 08 lt Vppio2 lt 1 32 V 24 13 40 40 26 2 160 Unit MHz tsu NSS NSS setup time Slave mode SPI prescaler 2 4 ns 35 NSS hold time Slave mode SPI prescaler 2 2xTpcLk ns tw SCKH tw SCKL SCK high and low time Master mode 2 ns tsu MI tsu SI Data input setup time Master mode 3 5 Slave mode ns tha thsi Data input hold time Master mode 6 5 Slave mode ns ta so tuis SO 166 213 Data output access time Data output disable time Slave mode Slave mode DoclD025976 Rev 2 36 16 ns ns q STM32L476xx Electrical characteristics Table 78 SPI characteristics continued Symbol Parameter Conditions Min Typ Max Unit Slave mode 2 7
77. USART2 CTS VINP 14 H8 H8 23 L2 34 PAO I O FT_a UART4_TX ADC12_IN5 SAI1_EXTCLK RTC_TAMP TIM2_ETR EVENTOUT 2 WKUP1 M3 1 15 G4 G4 24 2 35 1 FT la UART4 RX LCD SEGO E TIM15_CH1N EVENTOUT TIM2_CH3 TIM5_CH3 ADC12_IN7 16 G6 G6 25 36 PA2 FT la S ED SEST WKUP4 SAI2 EXTCLK LSCO TIM15 CH1 EVENTOUT TIM2 5 OPAMP1 17 7 H7 26 13 37 IO TT USART2_RX LCD_SEG2 VoUT 15 2 EVENTOUT ADC12 IN8 18 J9 J9 27 38 VSS 19 J8 J8 28 39 VDD SPI1 NSS SPI3 NSS ADC12 20 G5 G5 29 J4 40 4 TT USART2_CK SAI1 FS B 9 DAC1_ LPTIM2 OUT oUT1 TIM2 CH1 2 21 H6 H6 30 K4 41 TT TIM8 CH1N SPI1 SCK DAC1 LPTIM2_ETR EVENTOUT ouT2 TIM1 BKIN TIM3 1 TIM8 BKIN SPI1 MISO USARTS3 CTS OPAMP2 QUADSPI BK1 103 VINP 22 H5 H5 31 L4 42 6 FT la LCD SEG3 ADC12_ 1 2 11 8 2 16 1 2_ TT 5 60 213 DocID025976 Rev 2 ky STM32L476xx Pinouts and pin description Table 14 STM32L476xx pin definitions continued
78. USART3 RX PC6 TIM3 CH1 TIM8 CH1 DFSDM PC7 TIM3 CH2 TIM8 CH2 DFSDM DATIN3 PC8 TIM3 CH3 TIM8 CH3 Port C PC9 TIM8 BKIN2 TIM3 CH4 TIM8 4 PC10 SPI3 SCK USART3 TX PC11 SPI3 MISO USART3 RX PC12 SPI3 MOSI USART3 CK PC13 PC14 PC15 9 TIZEINLS uonduosep uid pue s ynould 10174 c 94 926S20d190d Table 15 Alternate function AF0 to AF7 for AF8 to AF15 see Table 16 continued AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 Port 2 TIM1 TIM2 USART1 SYS_AF 5 8 4 TIM8 2 1 2 212 3 SPM SPI2 SPI3 DFSDM USART2 LPTIM1 TIM5 USART3 PDO 2 SPI2 55 DFSDM DATIN7 PD1 2 SPI2 SCK DFSDM CKIN7 PD2 TIM3 ETR Eons DE PD3 SPI2 MISO DFSDM DATINO USART2 CTS PD4 I SPI2_MOSI DFSDM CKINO id c PD5 USART2 TX PD6 s DFSDM DATIN1 USART2 RX PotD PD7 2 DFSDM_CKIN1 USART2 PD8 USART3 TX PD9 USART3 RX PD10 USART3 CK PD11 USART3_CTS PD12 TIM4 CH1 USART3_RTS_ DE PD13 TIM4 CH2 PD14 TIM4 CH3 PD15 I TIM4 CH4
79. advanced response to interrupts ARM Cortex M4 with 32 bit RISC processor features exceptional code efficiency delivering the high performance expected from an ARM core in the memory size usually associated with 8 and 16 bit devices The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution Its single precision FPU speeds up software development by using metalanguage development tools while avoiding saturation With its embedded ARM core the STM32L476xx family is compatible with all ARM tools and software Figure 1 shows the general block diagram of the STM32L476xx family devices Adaptive real time memory accelerator ART Accelerator The ART Accelerator is a memory accelerator which is optimized for STM32 industry standard ARM Cortex M4 processors It balances the inherent performance advantage of the ARM Cortex M4 over Flash memory technologies which normally requires the processor to wait for the Flash memory at higher frequencies To release the processor near 100 DMIPS performance at 80 2 the accelerator implements an instruction prefetch queue and branch cache which increases program execution speed from the 64 bit Flash memory Based on CoreMark benchmark the performance achieved thanks to the ART accelerator is equivalent to 0 wait state program execution from Flash memory at a CPU frequency up to 80 MHz Memory protecti
80. an extremely low energy consumption Higher speed clock can be used to reach higher baudrates LPUART interface can be served by the DMA controller DoclD025976 Rev 2 47 213 Functional overview STM32L476xx 3 29 3 30 48 213 Serial peripheral interface Three interfaces allow communication up to 40 Mbits s in master and up to 24 Mbits s slave modes in half duplex full duplex and simplex modes The 3 bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits interfaces support NSS pulse mode mode and Hardware CRC calculation All SPI interfaces can be served by the DMA controller Serial audio interfaces SAI The device embeds 2 SAI Refer to Table 12 SAI implementation for the features implementation The SAI bus interface handles communications between the microcontroller and the serial audio protocol The SAI peripheral supports e Two independent audio sub blocks which can be transmitters or receivers with their respective FIFO e 8 word integrated FIFOs for each audio sub block e Synchronous or asynchronous mode between the audio sub blocks e Master or slave configuration independent for both audio sub blocks e Clock generator for each audio block to target independent audio frequency sampling when both audio sub blocks are configured in master mode e Data size configurable 8 10 16 20 24 32 bit e Peripheral
81. below V ss or above Vppiox for standard 3 3 V capable I O pins should be avoided during normal product operation However in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens susceptibility tests are performed on a sample basis during device characterization Functional susceptibility to I O current injection While a simple application is executed on the device the device is stressed by injecting current into the pins programmed in floating input mode While current is injected into the pin one at a time the device is checked for functional failures The failure is indicated by an out of range parameter ADC error above a certain limit higher than 5 LSB TUE out of conventional limits of induced leakage current on adjacent pins out of the 5 HA 0 pA range or other functional failure for example reset occurrence or oscillator frequency deviation The characterization results are given in Table 56 Negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection Table 56 current injection susceptibility Functional susceptibility Symbol Description Unit Negative Positive injection injection Injected current on BOOTO pin 0 NA ling Injected current on pins except PA4 PAS BOOTO 5 0 mA Injected current PA4 5 pins 5 0 DoclD0
82. for 1000 captures over 28 cycles For paired transitions min and max jitter of 2 consecutive frame of 56 cycles of the MSI 948 MHz for 1000 captures over 56 cycles 6 Guaranteed by design not tested in production q DocID025976 Rev 2 131 213 Electrical characteristics STM32L476xx Figure 19 Typical current consumption versus MSI frequency uA Range 0 to 3 Range 4 to 7 Range 8 to 11 256 48MHz 8 16MHz 64 32 8MHz 16 8 1MHz 4 2 100KHz 800KHz 1 0 5 0 1 0 2 0 4 0 8 1 6 3 2 6 4 12 8 25 6 Freq MHz Low speed internal LSI RC oscillator Table 48 LSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit LSI Frequency Vpp 3 0 V Ta 30 C TBD 32 0 5 2 TBD kHz LSI oscillator Continuous Mode 40 to 125 1 5 TBD Atemp LSl frequency drift with temperature Sampling Mode 40 125 1 5 TBD LSI oscillator Continuous Mode Mg IDE 0 1 0 2 TBD Aypp LSI O frequency drift with Vpp Sampling on 1 62 V to 2 0 5 1 5 TBD 6 LSI oscillator start _ tsu LSI up time 80 130 us LSI oscillator _ tsrAB LSI stabilisation time 5 of final frequency 125 180 us 10 308 LSI oscillator power _ _ 110 180 nA consomption 1 Data based on characterization results not tested in production 2 0 5 2 corresponds to typical devi
83. frIMxCLK 80 MHz _ 53 68 s 1 TIMx is used as a general term in which x stands for 1 2 3 4 5 6 7 8 15 16 or 17 Table 75 min max timeout period at 32 kHz LSI Min timeout RL 11 0 Max timeout RL 11 0 Prescaler divider PR 2 0 bits 0x000 OxFFF Unit 14 0 0 125 512 18 1 0 250 1024 116 2 0 500 2048 132 3 1 0 4096 ms 164 4 2 0 8192 1128 5 4 0 16384 256 7 8 0 32768 1 The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty 164 213 DoclD025976 Rev 2 q STM32L476xx Electrical characteristics Table 76 WWDG min max timeout value at 80 MHz PCLK Prescaler WDGTB Min timeout value Max timeout value Unit 1 0 0 0512 3 2768 2 1 0 1024 6 5536 ms 4 2 0 2048 13 1072 8 3 0 4096 26 2144 6 3 26 Communication interfaces characteristics interface characteristics The 2 interface meets the timings requirements of the I C bus specification and user manual rev 03 for e Standard mode Sm with a bit rate up to 100 kbit s e Fast mode Fm with a bit rate up to 400 kbit s e Fast mode Plus with a bit rate up to 1 Mbit s The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured refer to RM0351 reference manual The SDA and SCL requirements are met with the following restrictions the SDA and
84. inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 1 0 050 0 150 0 0020 0 0059 2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 0 090 0 200 0 0035 0 0079 D 21 800 22 000 22 200 0 8583 0 8661 0 8740 D1 19 800 20 000 20 200 0 7795 0 7874 0 7953 D3 17 500 0 6890 E 21 800 22 000 22 200 0 8583 0 8661 0 8740 E1 19 800 20 000 20 200 0 7795 0 7874 0 7953 E3 17 500 0 6890 e 0 500 0 0197 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 3 5 7 0 3 5 Z ccc 0 080 0 0031 1 Values in inches are converted from mm and rounded to 4 decimal digits DocID025976 Rev 2 193 213 q Package information STM32L476xx 194 213 Figure 48 LQFP144 144 pin 20 x 20 mm low profile quad flat package recommended footprint k 1 0 35 o a F 722 144 22 6 3 19 9 22 6 Y Y ai14905e 1 Dimensions are expressed in millimeters DocID025976 Rev 2 STM32L476xx Package information q Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 49 LQFP144 marking package top view Optional gate mark Revision code Product i
85. is reached This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For C 4 and 2 it is recommended to use high quality external ceramic capacitors in the 5 pF to 20 pF range typ designed for high frequency applications and selected to match the requirements of the crystal or resonator see Figure 17 C 2 are usually the same size The crystal manufacturer typically specifies a load capacitance which is the series combination of C and Cj gt PCB and pin capacitance must be included 10 pF can be used as a rough estimate of the combined pin and board capacitance when sizing Cu and Cio DoclD025976 Rev 2 125 213 Electrical characteristics STM32L476xx Note For information on selecting the crystal refer to the application note AN2867 Oscillator design guide for ST microcontrollers available from the ST website www st com Figure 17 Typical application with an 8 MHz crystal Resonator with integrated capacitors Bias controlled gain MS19876V1 1 RExr value depends on the crystal characteristics Low speed external clock generated from a crystal resonator The low speed external LSE clock can be supplied with a 32 768 kHz crystal resonator oscillator All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 45 In the applica
86. low power brown out reset BOR active in all modes except Shutdown and ensuring proper operation after power on and during power down The device remains in reset mode when the monitored supply voltage Vpp is below a specified threshold without the need for an external reset circuit The lowest BOR level is 1 71V at power on and other higher thresholds can be selected through option bytes The device features an embedded programmable voltage detector PVD that monitors the Vpp power supply and compares it to the VPVD threshold An interrupt can be generated when Vpp drops below the VPVD threshold and or when Vpp is higher than the VPVD threshold The interrupt service routine can then generate a warning message and or put the MCU into a safe state The PVD is enabled by software In addition the devices embeds a Peripheral Voltage Monitor which compares the independent supply voltages VppA Vppusp Vppio2 With a fixed threshold in order to ensure that the peripheral is in its functional supply range q DocID025976 Rev 2 STM32L476xx Functional overview 3 9 3 3 9 4 q Voltage regulator Two embedded linear voltage regulators supply most of the digital circuitries the main regulator MR and the low power regulator LPR e The MR is used in the Run and Sleep modes e The LPR is used in Low Power Run Low Power Sleep Stop 1 and Stop 2 modes It is also used to supply the 32 Kbyte 5 2 in Standby with RAM2 retention
87. memory bank e Write FIFO e The Maximum FMC_CLK frequency for synchronous accesses is HCLK 2 LCD parallel interface The FMC can be configured to interface seamlessly with most graphic LCD controllers It supports the Intel 8080 and Motorola 6800 modes and is flexible enough to adapt to specific LCD interfaces This LCD parallel interface capability makes it easy to build cost effective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration DoclD025976 Rev 2 51 213 Functional overview STM32L476xx 3 36 52 213 Quad SPI memory interface QUADSPI The Quad SPI is a specialized communication interface targeting single dual or quad SPI flash memories It can operate in any of the three following modes Indirect mode all the operations are performed using the QuadSPI registers Status polling mode the external flash status register is periodically read and an interrupt can be generated in case of flag setting Memory mapped mode the external flash is memory mapped and is seen by the System as if it were an internal memory The Quad SPI interface supports Three functional modes indirect status polling and memory mapped SDR and DDR support Fully programmable opcode for both indirect and memory mapped mode Fully programmable frame format for both indirect and memory mapped mode Each of the 5 following phases can be configured
88. of the MCU sunk Vss cannot exceed the absolute maximum rating gt Ivss see Table 18 Voltage characteristics q DocID025976 Rev 2 STM32L476xx Electrical characteristics Output voltage levels Unless otherwise specified the parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21 General operating conditions All Os are CMOS TTL compliant FT OR TT unless otherwise specified Table 58 Output voltage characteristics Symbol Parameter Conditions Min Max Unit VoL Output low level voltage for an CMOS port 0 4 liol 8 mA Output high level voltage for an I O pin Vppiox gt 2 7 V Vppiox 0 4 Vo Output low level voltage for an I O TTL port 0 4 8 mA Vou Output high level voltage for an Vppiox gt 2 7 V 24 Vo Output low level voltage for an I O pin lo 20 mA 1 3 Output high level voltage for an I O pin Vppiox 2 2 7 V Vppiox 1 3 Vo Output low level voltage for an pin lol 4 mA 0 45 Von Output high level voltage for an I O pin Vppiox 2 1 62 V Vppiox 0 45 M VoL Output low level voltage for I O pin 2 mA 0 35xXVppiox Voy Output high level voltage for an WO pin 1 62 V 2 Vppiox gt 1 08 V 0 65 Vppiox llio 20 mA _ Vppiox gt 2 7 V om V Output low leve
89. otherwise specified 2 Based on characterization done with a 32 768 kHz crystal MC306 G 06Q 32 768 manufacturer JFVNY with two 6 8 pF loading capacitors sonsiuoj2eJeuo 212 XXQZVTIZEINLS c 94 9768c0GI oq ELZ SLL Table 38 Current consumption in VBAT mode Symbol Ipp VBAT Parameter Backup domain supply current Conditions TYP 1 25 C 55 C 85 C 105 125 25 55 C 85 C 105 125 C 1 8 V 4 29 196 587 1663 108 73 490 1468 4158 24V 527 36 226 673 1884 132 90 565 1683 4710 disabled 3V 6 42 264 775 2147 155 106 660 1938 5368 36V 10 58 323 919 2488 258 144 808 2298 6220 18V 183 201 367 729 E P RTC enabled and 24V 268 295 486 901 P P 2 clocked by LSE bypassed at 32768 Hz 3V 376 412 602 1075 d 7 u u 7 3 6V 508 558 752 1299 z 18V 302 344 521 915 1978 2 E enabled 24 388 436 639 1091 2289 z clocked by LSE guanine 3V 494 549 784 1301 2656 z p z p 36V 630 692 971 1571 3115 z Unit nA 1 Based on characterization not tested in production unless otherwise specified 2 Based on characterization done with a 32 768 kHz crystal MC306 G 06Q 32 768 manufactu
90. output bufferON _ 42 75 setting the ENx bit in the CL lt 50 pF RL 2 5 WAKEUP i DAC Control register until Normal mode DAC output buffer final value 1 LSB OFF CL lt 10 pF 2 5 PSRR Vppa supply rejection ratio ee cose Rice 22 80 28 dB DAC output buffer _ 0 7 35 DAC OUT 100 nF Sampling time in sample pin connected and hold mode code tee E transition between the 1 7SH teAMP lowest input code and the OUT ms highest input code when pin not DACOUT reaches final connected DAC output buffer value 1LSB internal OFF I TEP connection only Sample and hold mode lleak Output leakage current DAC QUT pin connected 43 nA 152 213 00 10025976 Rev 2 STM32L476xx Electrical characteristics Table 65 DAC characteristics continued Symbol Parameter Conditions Min Typ Max Unit Clint Internal sample and hold I 5 2 7 8 8 pF capacitor trRIM eae code OSEE UM DAC output buffer ON 50 HS Middle code offset for 1 Vngr 3 6 V 1500 Voffset trim code step HV VREF 1 8 V 750 load middle 315 500 DAC output code 0x800 buffer ON No load worst code 0xF4C 450 670 IppA DAC va consumption from DAC output No load middle _ _ 02 DDA buffer OFF code 0x800 315 x 670 x Sample and hold mode _ Ton Ton Ton Ton 100 nF Toff Toff 4 4
91. quadrature encoders e TIM15 16 and 17 They are general purpose timers with mid range features They have 16 bit auto reload upcounters and 16 bit prescalers TIM15 has 2 channels and 1 complementary channel TIM16 and TIM17 have 1 channel and 1 complementary channel All channels can be used for input capture output compare PWM or one pulse mode output The timers can work together via the Timer Link feature for synchronization or event chaining The timers have independent DMA request generation The counters can be frozen in debug mode Basic timers TIM6 and TIM7 The basic timers are mainly used for DAC trigger generation They can also be used as generic 16 bit timebases Low power timer LPTIM1 and LPTIM2 The devices embed two low power timers These timers have an independent clock and are running in Stop mode if they are clocked by LSE LSI or an external clock They are able to wakeup the system from Stop mode is active in Stop 1 and Stop 2 modes LPTIM2 is active in Stop 1 mode DoclD025976 Rev 2 43 213 Functional overview STM32L476xx 3 24 5 3 24 6 3 24 7 44 213 This low power timer supports the following features e 16 bitup counter with 16 bit autoreload register e 16 bit compare register e Configurable output pulse PWM e Continuous one shot mode e Selectable software hardware input trigger e Selectable clock source Internal clock sources LSE LSI HSI16
92. the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 44 In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time Refer to the crystal resonator manufacturer for more details on the resonator characteristics frequency package accuracy Table 44 HSE oscillator characteristics Symbol Parameter Conditions 2 Min Typ Max Unit fosc_in_ Oscillator frequency 4 8 48 MHz Feedback resistor 200 kQ During startup 5 5 Vpp 3 V Rm 300 0 44 CL 10 pF 8 MHz Vpp 3 V Rm 45 0 45 10 pF 8 MHz HSE current consumption Vpp 3 V mA Rm 300 068 CL 5 pF 48 MHz Vpp 3 V Rm 300 0 94 CL 10 pF 48 MHz Vpp 3 V Rm 300 1 77 CL 20 48 MHz Maximum critical crystal G m transconductance Startup 1 55 Startup time Vpp is stabilized 2 ms Guaranteed by design not tested in production Resonator characteristics given by the crystal ceramic resonator manufacturer This consumption level occurs during the first 2 3 of the tsu usg startup time Bow NM tsu HseE is the startup time measured from the moment it is enabled by software to a stabilized 8 MHz oscillation
93. uonduosep uid pue XXQZV TIZEINLS 94 9768c0GI oq ELe Gl Table 15 Alternate function AF0 to AF7 for AF8 to AF15 see Table 16 continued AFO AF1 AF2 AF3 AF4 AF5 AF6 AF7 Port TIM1 TIM2 TIM1 TIM2 USART1 SYS AF TIM5ITIM8 TIM3 TIM4 TIM8 I2C1 I2C2 2C3 2 SPI3 DFSDM USART2 LPTIM1 TIM5 USART3 PEO 1 1 4 2 2 PE1 2 TRACECK TIM3_ETR PE3 TRACEDO TIM3 CH1 PE4 TRACED TIM3_CH2 2 DFSDM_DATIN3 TRACED2 TIM3_CH3 DFSDM CKIN3 6 TRACED3 TIM3_CH4 gt PE7 TIM1 DFSDM DATIN2 PortE PE8 TIM1_CH1N DFSDM_CKIN2 9 2 TIM1 CH1 s DFSDM CKOUT 10 TIM1_CH2N DFSDM_DATIN4 11 TIM1 CH2 DFSDM_CKIN4 12 TIM1 CH3N SPM NSS DFSDM_DATIN5 PE13 TIM1 CH3 SPM SCK DFSDM CKIN5 PE14 CH4 TIM1 BKIN2 MM E SPI MISO E 15 TIM1_BKIN E SPI MOSI E 9 TIZEINLS uonduosep uid pue sjnouid 6 92 94 9768c0GI oq Table 15 Alternate function AF0 to AF7 for AF8 to AF15 see Table 16 continued AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 Port TIM1 TIM2 TIM1 TIM2 USART1 SYS AF TIM5 TIM8 TIM3 TIM4 TIM8 I2C
94. voD 8 XTAL OSC lt OSC_IN lt 4 16MHz Osc_our lt Ly 5 VBAT 1 55 to 3 6 V Y Standby Y GPIO PORT E i lt Reset amp clock interface control VBAT lt cploportr IN XTAL 32 kHz lt Y T Y OSC32 OUT qM GPIO PORT G RTC Ts 5 2 AWU gt RTC_TAMPx lt Backup register lt s GPIO PORTH Qe RTC OUT VDD KS TIM2 32b 4 channels ETR as AF VDDA KS TIM3 16b C gt 4 channels ETR as AF oct s 4 16b lt gt 4 channels ETR as AF ADC2 gt 5 32b K gt 4 channels ETR as AF ADC3 smcard ce USART2 gt RX TX CK CTS RTS as AF ES smcard RX TX CK CTS RTS as AF C VREF Buffer KK AHB APB2 1 USARTS irDA a TX u as C EXT IT WKUP gt UARTA RX TX CTS RTS as AF TX u as UART5 RX TX CTS as AF o lt gt SP2 MOSI MISO SCK NSS as AF gt Timt PwM 16b gt Ke SP3 gt MOSI MISO SCK NSS as AF lt 12C1 SMBUS Y SCL SDA SMBAas AF TIMB PWM 16 lt s I2C2 SMBUS SDA SMBA as AF 16b C TIM15 lt gt gt I2C3 SMBUS LL SCL SDA SMBA as AF TIM16 16b i o Kc bxCAN1 B gt TX RX as AF E lt gt 1 gt lt lt gt VOUT VIN smcard lt USART1 gt lt gt VOUT
95. voltage Rising edge 2 1 2 15 2 19 y PVD0 detector threshold 0 Falling edge 2 2 05 2 1 Rising edge 2 26 2 31 2 36 Vpvp1 PVD threshold 1 V Falling edge 2 15 2 20 2 25 Rising edge 2 41 2 46 2 51 Vpvp2 PVD threshold 2 V Falling edge 2 31 2 36 2 41 Rising edge 2 56 2 61 2 66 Vpvp3 PVD threshold 3 V Falling edge 2 47 2 52 2 57 Rising edge 2 69 2 74 2 79 PVD threshold 4 Falling edge 2 59 2 64 2 69 Rising edge 2 85 2 91 2 96 5 PVD threshold 5 V Falling edge 2 75 2 81 2 86 Rising edge 2 92 2 98 3 04 VPype PVD threshold 6 V Falling edge 2 84 2 90 2 96 Hysteresis in continuous 20 Vnyst Hysteresis voltage of BORHO mode mV Hysteresis in _ 30 _ other mode Hysteresis voltage of BORH Vhyst_BOR_PVD except BORH0 and PVD T lop BOR except BORO and _ _ i A BOR_PVD PVD consumption from Vpp i H V DDusg Peripheral voltage 1 18 122 126 V monitoring DoclD025976 Rev 2 97 213 Electrical characteristics STM32L476xx Table 23 Embedded reset and power control block characteristics continued Symbol Parameter Conditions Min Typ Max Unit Vppio2 peripheral voltage _ 2 monitoring 0 92 0 96 1 Vppa Peripheral voltage Rising edge 1 61 1 665 1 69 Won V monitoring Falling edge 1 6 164 1 68 VppA Peripheral voltage Rising edge 1 78 1 82 1 86 Hori V monitoring Falling edge 177 181 1 85 Vnyst PV
96. when buffer is OFF and from code giving 0 2 V and Vggr 0 2 V when buffer is ON q 156 213 DocID025976 Rev 2 STM32L476xx Electrical characteristics 6 3 19 Voltage reference buffer characteristics Table 67 VREFBUF characteristics Symbol Parameter Conditions Min Typ Max Unit Vrs 0 2 4 3 6 Normal mode Analog supply Vrs 1 2 8 3 6 voltage 9 0 1 65 2 4 Degraded mode VRs 1 1 65 2 8 V Ves 0 2 046 2 048 2 049 Normal mode Voltage Voe 1 2 498 3 25 2 50209 VREFBUF_ reference BS OUT Vrs 0 Vppa 150 mV Vp A output Degraded mode 2 2 Vrs 1 Vppa 1 50 mV VppA TRIM im Stee 0 05 01 resolution CL Load capacitor 0 5 1 1 5 HF Equivalent esr Serial Resistor 2 Q of Cload Static load lioad current I I j I 500 pA 700 TBD line reg Line regulation 2 8 V lt VppA 3 6 V ppm V 4 mA 400 TBD Load VppA 2 8 V 50 TBD lload reg reaulation 500 pA lt S4 mA ppm mA g VppA 3 6 V 120 TBD Temperature 40 lt TJ lt 125 C TBD TBD fficient ppm C 0 C lt TJ lt 50 C TBD DC 60 TBD T ower supply dB rejection 100 kHz 30 TBD CL 0 5 300 TBD tsTART Start up time CL 1 1 uF 500 TBD us CL 1 5 uF 650 TBD VREFBUF load 0 WA 18 gt
97. 0 pF 2 Based on characterization not tested in production Table 90 Asynchronous multiplexed PSRAM NOR read NWAIT timings Symbol Parameter Min Max Unit tw NE FMC_NE low time 8Tucik 2 8 4 tw NOE FMC NWE low time 5Tucuc1 5 1 5 tsu NWAIT_NE NWAIT valid before FMC_NEx high 5Tucik 1 5 NwAr NEx hold time after FMC_NWAIT invalid 47 1 1 CL 30 pF 2 Based on characterization not tested in production 180 213 DoclD025976 Rev 2 q STM32L476xx Electrical characteristics q Figure 38 Asynchronous multiplexed PSRAM NOR write waveforms tw NE th NE_NWE FMC_NWE A 25 16 Address NE th BL_NWE tv A_NE BE tv Data_NADV h Data_NWE 0 15 0 Address B Data 4 tv NADV_NE th AD_NADV FMC_NADV FMC_NWAIT th NE_NWAIT tsu NWAIT_NE MS32756V1 DoclD025976 Rev 2 181 213 Electrical characteristics STM32L476xx 182 213 Table 91 Asynchronous multiplexed PSRAM NOR write timings Symbol Parameter Min Max Unit low time 0 5 2 tynwe_ne FMC_NEx low to NWE low 0 5 1 twNwE FMC_NWE low time 2xTucuc1 5 2xThoLk 1 thine nwe FMC_NWE high to high hold time 0 5
98. 05 LQFP64 64 pin 10 x 10 mm low profile quad flat package mechanical data continued millimeters 7 Symbol Min Typ Max Min Typ Max E3 7 500 0 2953 0 500 0 0197 K 0 3 5 72 0 3 5 7 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 ccc 0 080 0 0031 1 Values in inches are converted from mm and rounded to 4 decimal digits Figure 60 LQFP64 64 pin 10 x 10 mm low profile quad flat package recommended footprint 1 p na s 0 5 s 1 Dimensions expressed millimeters Device marking ai14909c The following figure gives an example of topside marking orientation versus pin 1 identifier location 206 213 DocID025976 Rev 2 q STM32L476xx Package information q Figure 61 LQFP64 marking package top view Revision code Product identification 1 Ly STM3eLu b RGTE Date code Pin 1 identifier MSv36854V2 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted p
99. 0x4000 3000 0x4000 33FF 1 IWDG 0 4000 2 00 0x4000 2FFF 1 KB WWDG 0x4000 2800 0x4000 2BFF 1 KB RTC 0x4000 2400 0x4000 27FF 1 KB LCD 0x4000 1800 0x4000 23FF 3 KB Reserved 0x4000 1400 0x4000 17FF 1 TIM7 0x4000 1000 0x4000 13FF 1 KB TIM6 0x4000 0 00 0x4000 OFFF 1 KB TIM5 0x4000 0800 0x4000 OBFF 1 KB TIM4 0x4000 0400 0x4000 07FF 1 KB TIM3 0 4000 0000 0x4000 1 KB TIM2 1 The gray color is used for reserved boundary addresses DoclD025976 Rev 2 q STM32L476xx Electrical characteristics 6 6 1 q Electrical characteristics Parameter conditions Unless otherwise specified all voltages are referenced to Vss Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at T4 25 C and TA TAmax given by the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Based on characterization the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation mean 3o Typical values Unless otherwise specified typical data are based on TA 25 Vpp Vppa V They are
100. 1 12C2 12C3 SPH SPI2 SPI3 DFSDM USART2 LPTIM1 TIM5 USART3 PFO I2C2 SDA PF1 I2C2 SCL PF2 I2C2 SMBA PF3 4 5 TIM5 CH1 TIM5 CH2 Port PF8 TIM5 CH3 E PF9 TIM5 CH4 PF10 PF11 PF12 PF13 DFSDM DATING PF14 DFSDM_CKIN6 PF15 uoldiuosap uid pue XXQZVTIZEINLS 97 6 20 622 Table 15 Alternate function AF0 to AF7 for AF8 to AF15 see Table 16 continued AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 Port TIM1 TIM2 TIM1 TIM2 USART1 SYS AF TIM5 TIMS TIM3 TIM4 TIM8 2 1 12 2 12 3 SPI1 SPI2 SPI3 DFSDM USART2 LPTIM1 TIM5 USART3 PGO PG1 PG2 SPI1_SCK PG3 SPI1_MISO PG4 SPI1_MOSI PG5 SPI1_NSS PG6 I2C3 SMBA PG7 I2C3 SCL PG8 I2C3 SDA Port G PG9 SPI3 SCK 1 TX PG10 LPTIM1 IN1 SPI3 MISO USART1 RX PG11 LPTIM1 IN2 SPI3 MOSI USART1 CTS PG12 LPTIM1 ETR SPI3 NSS c E PG13 I2C1 SDA USART1 PG14 1261 SCL PG15 LPTIM1 OUT I2C1 SMBA PHO
101. 10 pF 1 08 lt lt 1 62 V 0 1 50 pF 2 7 lt lt 3 6 V 25 C 50 pF 1 62 lt lt 2 7 V 52 Tr Tf Output rise and fall time ns C 10 pF 2 7 V lt VppioxS3 6 V 17 C 10 pF 1 62 lt lt 2 7 V 37 C 10 pF 1 08 lt lt 1 62 V 110 50 pF 2 7 lt lt 3 6 V 25 C 50 pF 1 62 lt lt 2 7 V 10 Fmax Maximum frequency i MHz C 10 pF 2 7 V lt VppioxS3 6 V 50 C 10 pF 1 62 VXVppjoX2 7 V 15 C 10 pF 1 08 lt lt 1 62 V 1 21 C 50 pF 2 7 lt lt 3 6 V 9 C 50 pF 1 62 lt lt 2 7 V 16 Tr Tf Output rise and fall time THEN i ns C 10 pF 2 7 VSVppioxS3 6 V 4 5 C 10 pF 1 62 lt lt 2 7 V 9 C 10 pF 1 08 lt lt 1 62 V 21 142 213 DoclD025976 Rev 2 Ly STM32L476xx Electrical characteristics Table 59 I O AC characteristics continued Speed Symbol Parameter Conditions Min Max Unit C 50 pF 2 7 VSVppjoxS3 6 V 50 C 50 pF 1 62 lt lt 2 7 V 25 Fmax Maximum frequency 5 MHz C 10 pF 2 7 VSVppioxS3 6 V 100 9 C 10 pF 1 62 lt lt 2 7 V 37 5 C 10 pF 1 08 lt lt 1 62 V 5 10 C 50 pF 2 7 VSVppioxS3 6 V 5 8 C 50 pF 1 62 lt lt 2 7 V 11 Tr Tf Output rise and fall tim
102. 1545 6520 43748 Ipp Standby nA registers retained 18V 317 E E i RTC disabled with independent 24V 391 watchdog 3V 438 5 3 6V 566 18V 377 621 1873 4564 11318 491 1207 4250 10867 27537 RTC clocked by LSI no 24V 464 756 2210 5348 13166 614 1436 4986 12694 31986 independent watchdog 572 913 2599 6219 15197 770 1727 5815 14729 36815 3 6V 722 1144 3253 7724 18696 1012 2176 7294 18275 45184 A n 1 8 V 456 I RTC clocked by LSI with 24 V 557 Supply current independent watchdog 3V 663 i n in Standby Ipp Standby mode backup 3 6 V 885 x 7 I x with registers 18V 289 527 1747 4402 11009 I retained RTC P clocked LSE 24V 396 671 2108 5202 12869 bypassed at 32768 2 528 853 2531 6095 14915 I 36V 710 1111 3115 7470 18221 E m n 18V 416 640 1862 4479 11908 RTC clocked by LSE 24 514 796 2193 5236 13689 quartz 8 in low drive mode 3V 652 961 2589 6103 15598 3 6V 821 1226 3235 7551 17947 e2129 3 XX97T 1C IN LS c 94 9768c0GI oq Tabl
103. 185 213 DocID025976 Rev 2 Electrical characteristics STM32L476xx 186 213 Table 94 Synchronous multiplexed PSRAM write timings Symbol Parameter Min Max Unit tw CLk FMC_CLK period 2 1 ta CLKL NExL FMC_CLK low to FMC_NEx low x 0 2 2 ta CLKH NExH FMC_CLK high to FMC_NEx high 0 2 0 5 ta CLKL NADVL FMC_CLK low to FMC_NADV low 2 5 ta CLKL NADVH FMC_CLK low to FMC_NADV high 1 tatcLKL AV CLK low to Ax valid 16 25 3 5 ta cLKH AiV FMC CLK high to Ax invalid x 16 25 ta CLKL NWEL FMC_CLK low to NWE low 2 ta CLKH NWEH FMC_CLK high to FMC_NWE high 1 T ta cLKL Apv CLK low to AD 15 0 valid 4 CLK low to AD 15 0 invalid 0 A D 15 0 valid data after CLK low 5 5 ta CLKL NBLL CLK low to NBL low 2 5 ta CLKH NBLH FMC_CLK high to NBL high Tucik 1 tsu NWAIT CLKH FMC_NWAIT valid before CLK high 0 th CLKH NWAIT FMC NWAIT valid after FMC_CLK high 4 1 CL 30 pF 2 Based on characterization not tested in production DoclD025976 Rev 2 Ky STM32L476xx Electrical characteristics q Figure 41 Synchronous non multiplexed NOR PSRAM read timings vO D tw CLK i
104. 2 8x28 or 4x32 8x28 or 4x32 Random generator Yes GPIOs 114 109 82 65 57 51 Wakeup pins 5 5 5 4 4 4 Nb of I Os down to 1 08 V 14 14 0 6 6 0 Capacitive sensing 24 24 21 12 12 12 Number of channels 12 bit ADCs 3 3 3 3 3 3 Number of channels 24 19 16 16 16 16 12 bit DAC channels 2 Internal voltage reference buffer Yes No Analog comparator 2 Operational amplifiers 2 Ly DoclD025976 Rev 2 13 213 Description STM32L476xx Table 2 STM32L476xx family device features and peripheral counts continued STM32L476 STM32L476 STM32L476 Peripheral Zx Vx Max CPU frequency STM32L476 STM32L476 Mx Jx STM32L476 Rx 80 MHz Operating voltage 1 71 to 3 6 V Ambient operating temperature 40 to 85 40 to 105 40 to 125 perating temperature Junction temperature 40 to 105 40 to 125 C 40 to 130 C Packages LQFP144 UFBGA132 LQFP100 WLCSP81 WLCSP72 LQFP64 1 For the LQFP100 package only FMC 1 is available Bank1 can only support a multiplexed NOR PSRAM memory using the NE1 Chip Select 14 213 DoclD025976 Rev 2 q STM32L476xx Description Figure 1 STM32L476xx block diagram NJTRST JTDI JTCK SWCLK JTDO SWD JTDO TRACECLK JTAG amp SW TRACED 3 0 8 Groups of 4 channels max as AF PA 15 0 PB 15 0 PC 15 0 PD 15 0 PE 15 0 PF 15 0 PG 15 0 PH 1 0
105. 2 1 125 13 3 peripherals disable 72MHz 924 9 31 9 47 969 10 1 10 16 107 11 0 11 4 122 64 MHz 8 25 832 846 8 68 909 9 08 96 9 9 10 3 11 1 Range 1 48 628 6 35 6 5 672 7 11 6 91 73 7 6 8 0 8 8 32 MHz 4 24 4 30 444 465 504 466 497 526 5 67 6 51 24 MHz 3 21 327 3 4 3 61 3 98 3 53 3 76 4 05 4 46 5 30 16 MHz 2 19 224 2 36 2 56 294 241 2 66 2 95 3 16 3 99 2MHz 272 303 413 592 958 330 393 579 954 1704 rm 22 fucik fusi 1MHz 154 184 293 473 835 195 265 457 822 1572 ER popu all peripherals disable 400kHz 78 108 217 396 758 110 180 380 755 1505 run mode 100kHz 42 73 182 360 723 75 138 331 706 1456 1 Based on characterization not tested in production unless otherwise specified XXQZVTIZEINLS sonsioj2eJeuo 212 12 201 c 94 9768c0GI oq Table 26 Current consumption in Run and Low power run modes code with data processing running from Flash ART disable Conditions TYP MAX Symbol Parameter Voltaqe Unit Scio fucuk 25 C 55 85 C 105 125 25 55 85 C 105 C 125 C 26 MHz 3 15 3 19 3 31 3 50 3 85 347 3 70 3 84 426 4 88 16 MHz 2 24 228 239 2 57 2 90 246 2 60 2 74 3 16
106. 2 APB clock domain 24 2 1 2 2 2 independent clock 47 39 42 SDMMC1 clock domain 2 5 1 9 2 1 APB2 SPI1 2 0 1 6 1 9 SYSCFG VREFBUF COMP 0 6 0 4 0 5 TIM1 8 3 6 9 7 9 TIM8 8 6 7 1 8 1 TIM15 4 1 3 4 3 9 16 3 0 2 5 2 9 17 3 0 2 4 2 9 2 independent clock 49 40 44 USART1 clock domain 1 5 1 3 1 7 All APB2 56 8 43 3 48 2 ALL 256 8 189 6 215 5 Unit HA MHz 119 213 Electrical characteristics STM32L476xx 1 The BusMatrix is automatically active when at least one master is ON CPU DMA 2 The AHB to APB1 Bridge is automatically active when at least one peripheral is ON on the APB1 3 The AHB to APB2 Bridge is automatically active when at least one peripheral is ON on the APB2 6 3 6 Wakeup time from low power modes and voltage scaling transition times The wakeup times given in Table 40 are the latency between the event and the execution of the first user instruction The device goes in low power mode after the WFE Wait For Event instruction Table 40 Low power mode wakeup timings Symbol Parameter Conditions Max Unit Wakeup time from twusLEEP Sleep mode to Run 6 mode Nb of Wakeup time from CPU t Low power sleep Wakeup in Flash with Flash in power down during low 6 cycles WULPSLEEP mode to Low power power sleep mode SLEEP PD 1 in FLASH ACR run mode 120 213 DoclD025976 Rev 2 Ly STM32L476xx Electrical characteristics Table 40
107. 25976 Rev 2 137 213 Electrical characteristics STM32L476xx 6 3 14 I O port characteristics General input output characteristics Unless otherwise specified the parameters given in Table 57 are derived from tests performed under the conditions summarized in Table 21 General operating conditions I Os are designed as CMOS and TTL compliant except BOOTO Table 57 I O static characteristics Symbol Parameter Conditions Min Typ Max Unit I O input low level voltage except 1 62 V lt Vppiox lt 3 6 V 0 3xVppiox input low level voltage except 1 62 V lt Vppiox lt 3 6 V 2 0 39xVppiox 0 06 v 2 BOOTO V I O input low level voltage except 1 08 V lt Vppiox lt 1 62 V 0 43xVppiox 0 1 input low voltage 1 62 V Vpp ox 3 6 V 0 1 I O input high level voltage except 1 62 V lt Vppiox 3 6 V 0 7XVppiox input high level voltage except 1 62 V lt Vppiox 3 6 V 0 49xVppiox 0 26 v0 BOOT0 V I O input high level voltage except 1 08 V lt Vppiox lt 1 62 V 0 61xVppjox 0 05 Booro BOOTO I O input high level voltage 1 62 V Vpp ox 3 6 V 0 77xVppiox TT_xx FT_xxx and NRST input 1 62 lt lt 3 6 V 200 hysteresis 2 Vhys FT_sx 1 08 V lt Vppiox lt 1 62 V 150 Ld BOOTO I O input hysteresis 1 62 V lt Vppiox lt 3 6 V B 200 138 213 DocID025976 Rev 2 L
108. 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Ly STM32L476xx block 2 15 Power supply 20 eus P TT 33 STM32L476Zx LQFP144 pinout U 54 STM32L476Qx UFBGA132 55 STM32L476Vx LQFP100 9 55 STM32L476Mx WLCSP81 56 STM32L476Jx WLCSP72 56 STM32L476Rx LQFP64 9 2 2222222222222222 57 STM32L476 memory 1 86 Pin loading 91 IM PUL VONAGE e mete Rated eee RR ee PR a 91 Power supply 92 Current consumption measurement scheme 93 High speed external clock source AC timing diagram 123 Low speed external clock source AC timing diagram 124 Typical
109. 3 1 1 1 5 2 2 independent clock domain 3 7 3 0 3 2 2 2 clock domain 1 4 1 1 1 5 I2C3 independent clock domain 2 9 2 3 2 5 2 3 APB clock domain 0 9 0 9 1 1 LCD 1 0 0 8 0 9 2 independent clock 21 16 20 LPUART1 clock domain 0 6 0 6 0 6 piii a independent clock 33 26 29 LPTIM1 APB clock domain 0 9 0 8 1 0 APB1 2 piis independent clock 34 27 29 LPTIM2 APB clock domain 0 8 0 6 0 7 OPAMP 0 4 0 4 0 3 PWR 0 5 0 5 0 4 SPI2 1 8 1 6 1 6 SPI3 2 1 1 7 1 8 independent clock 23 1 8 22 SWPMI1 APB clock domain 1 1 1 1 1 0 TIM2 6 8 5 7 6 3 TIM3 5 4 4 6 5 0 TIM4 5 2 4 4 4 9 TIM5 6 5 5 5 6 1 TIM6 1 1 1 0 1 0 TIM7 1 1 0 9 1 0 118 213 DocID025976 Rev 2 Ky STM32L476xx Electrical characteristics Table 39 Peripheral current consumption continued q DocID025976 Rev 2 Peripheral Range 1 Range 2 2 independent clock 44 3 6 38 USART2 APB clock domain 1 4 1 1 1 5 FADE independent clock 47 41 42 USART3 clock domain 1 5 1 3 1 7 RB 2 independent clock 3 9 3 2 35 UARTA clock domain 1 5 1 3 1 6 2 independent clock 3 9 3 2 35 UART5 clock domain 1 3 1 2 1 4 WWDG 0 5 0 5 0 5 All APB1 on 84 2 70 7 80 2 AHB to APB2 bridge 1 0 0 9 0 9 DFSDM 5 6 46 5 3 FW 0 7 0 5 0 7 independent clock domain 2 6 2 1 2 3 SAI1 APB clock domain 2 1 1 8 2 0 SAI2 independent clock domain 3 3 2 7 3 0 SAI
110. 385 192 1 Reduced code used for characterization results provided in Table 25 Table 26 Table 27 Table 30 Typical current consumption in Run and Low power run modes with different codes running from SRAM1 Conditions TYP TYP Symbol Parameter Voltage Unit Unit g Code 25 C 25 C scaling N Reduced code 2 9 111 2 2 9 111 fuck fuse upto 2 Dhrystone 2 1 29 mA 111 pA MHz 48 MHz included X Fibonacci 2 6 100 Supply bypass mode Ipp Run currentin PLL ON above While 28 100 Run mode 48 MHz all I Reduced code 10 2 127 peripherals 10 4 130 disable Dhrystone 2 1 10 3 mA 129 pA MHz x Fibonacci 9 6 120 5 1 9 3 116 Reduced code 242 121 Coremark 242 121 current in HCLK MSI 2 Ipp LPRun Low power all peripherals disable Dhrystone 2 1 242 HA 121 run Fibonacci 225 112 While 1 242 121 1 Reduced code used for characterization results provided in Table 25 Table 26 Table 27 Ly DoclD025976 Rev 2 105 213 6 90 97 6 20 Table 31 Current consumption Sleep Low power sleep modes Flash Conditions TYP MAX Symbol Parameter Voltage Unit age f 25 C 55 C 85 C 105
111. 4 decimal digits Figure 53 LQFP100 100 14 x 14 mm low profile quad flat recommended footprint 75 51 oono 176 150 0 5 cS Y O 0 3 co co co co 16 7 14 3 co co co co co co co co co co ca co 100 126 12 12 3 16 7 14906 1 Dimensions expressed millimeters Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location DoclD025976 Rev 2 199 213 Package information STM32L476xx 200 213 Figure 54 LQFP100 marking package top view Product identification NTM3eLu B Optional gate mark Revision code indentifier MSv36845V2 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity q DocID025976 Rev 2 STM32L4
112. 44 3 237 1310 3798 10473 111 593 3275 9495 26183 Ipp Shutdown backup E 64 1 293 1554 4461 12082 160 733 3885 11153 30205 registers retained RTC 3 6V 112 420 2041 5689 15186 280 1050 5103 14223 37965 disabled 9 TIZEINLS 212 z A8Y 926S20d190d Table 37 Current consumption in Shutdown mode continued Conditions TYP MAX Symbol Parameter Unit Vpp 25 55 C 85 C 105 125 C 25 55 85 C 105 C 125 C 1 8V 210 378 1299 3437 9357 Supply current RTC clocked by LSE 2 4V 303 499 1577 4056 10825 in Shutdown bypassed at 32768 Hz 3v 422 655 1925 4820 12569 mode Ipp Shutdown backup 3 6V 584 888 2511 6158 15706 T with RTC registers 1 8V 329 499 1408 3460 retained RTC clocked by LSE 24v 431 634 1688 4064 enabled quartz in low drive mode 3V 554 791 2025 4795 3 6 729 1040 2619 6129 Supply current Ipp wakeup during wakeup wakeup clock is MSI from 3V 0 6 mA from Shutdown 4 MHz Shutdown mode 1 Based on characterization not tested in production unless
113. 5 TBD E Ted LSB linearity error Fast channel max speed 1 TBD Differential Slow channel max speed 1 TBD Fast channel max speed TBD 10 3 Single ended i Slow channel max speed TBD 10 3 bits number of bits Fast channel max speed TBD 10 9 Differential Slow channel max speed TBD 10 9 Fast channel max speed TBD 63 8 5 5 Single ended Signal to noise Slow channel max speed TBD 63 8 SINAD distortion ratio Fast channel max speed TBD 67 4 Differential Slow channel max speed TBD 67 4 Fast channel max speed TBD 65 Single ended i Pm Slow channel max speed TBD 65 SNR Signal to noise dB ratio Fast channel max speed TBD 68 Differential Slow channel max speed TBD 68 Fast channel max speed 72 TBD Single ended Total Slow channel speed 72 TBD distortion Fast channel max speed 79 TBD Differential Slow channel max speed 79 TBD 1 Guaranteed by design not tested in production ADC DC accuracy values are measured after internal calibration ADC accuracy vs negative Injection Current Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to analog pins which may potentially inject negative current Vppa lt 2 4 V It is disable w
114. 76xx Package information 7 4 q WLCSP81 package information Figure 55 WLCSP81 81 pin 4 4084 x 3 7594 mm 0 4 mm pitch wafer level chip scale package outline A1 ball location D gt 1 location Bottom view Top view Bump side Wafer back side Side view Detail A PEEL rotated by 90 A1 NIN ddd Seating plane 057 ME V1 1 Drawing is not to scale Table 102 WLCSP81 81 pin 4 4084 x 3 7594 mm 0 4 mm pitch wafer level chip scale package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 0 525 0 555 0 585 0 0207 0 0219 0 0230 A1 0 175 0 0069 A2 0 380 0 0150 A30 0 025 0 0010 p 0 220 0 250 0 280 0 0087 0 0098 0 0110 D 4 3734 4 4084 4 4434 0 1722 0 1736 0 1749 E 3 7244 3 7594 3 7944 0 1466 0 1480 0 1494 e 0 400 0 0157 I 1 3 200 0 1260 e2 3 200 0 1260 DocID025976 Rev 2 201 213 Package information STM32L476xx Table 102 WLCSP81 81 pin 4 4084 x 3 7594 mm 0 4 mm pitch wafer level chip scale package mechanical data continued millimeters 7 Symbol Min Typ Max Min Typ Max F 0 6042 0 0238 G 0 2797 0 0110 aaa 0 100 0 0039 bbb 0 100 0 0039 ccc 0 100
115. AF13 AF14 AF15 Port UART4 SDMMC1 COMP1 TIM2 TIM15 UART5 CAN1 TSC OTG FS QUADSPI LCD COMP2 FMC SAI2 TIM16 TIM17 EVENTOUT LPUART1 SWPMI1 LPTIM2 PEO LCD SEG36 FMC NBLO TIM16 CH1 EVENTOUT PE1 LCD SEG37 FMC NBL1 TIM17 CH1 EVENTOUT PE2 TSC G7 101 LCD SEG38 FMC A23 Hn dE EVENTOUT PE3 TSC G7 IO2 LCD SEG39 FMC A19 SAM SD B EVENTOUT 4 TSC G7 IO3 FMC A20 SAM FS A EVENTOUT PE5 TSC G7 104 FMC A21 SAI1 SCK A EVENTOUT PE6 FMC A22 SAI1 SD A EVENTOUT D4 SAI SD B EVENTOUT Port E PE8 FMC_D5 SAI1_SCK_B EVENTOUT 9 D6 SAI1 FS EVENTOUT PE10 TSC G5 101 QUADSPI CLK FMC D7 dur be EVENTOUT PE11 TSC G5 IO2 QUADSPI NCS FMC D8 EVENTOUT PE12 TSC G5 IO3 QUADSPI BK1 100 FMC D9 EVENTOUT PE13 TSC G5 04 QUADSPI BK1 101 FMC D10 EVENTOUT PE14 QUADSPI BK1 102 FMC D11 EVENTOUT PE15 QUADSPI BK1 IO3 FMC D12 EVENTOUT uonduosep uid pue sjnouid XXQZVIZEINLS 94 9 6 20 Table 16 Alternate function AF8 to AF15 for AF0 to AF7 see Table 15 continued AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 Port UARTA SDMMC1 COMP4 2 15 UART5 CAN1 TSC OTG FS QUADSPI LCD COMP2 FMC 2 TIM16 TIM17 EVENTOUT LPUART1 SWPMI LPTIM2 PFO 0
116. BD DAC output buffer OFF DAC output buffer ON _ 30 Total CL lt 50 pF RL gt 5 kQ unadjusted LSB error DAC output buffer OFF _ _ 12 CL lt 50 pF RL Total unadjusted DAC output buffer ON TUECal error after CL lt 50 pF RL gt 5 i E LSB calibration DAC output buffer ON CL lt 50 pF RL gt 5 71 2 1 kHz BW 500 kHz SNR Signal to noise dB ratio DAC output buffer OFF CL lt 50 pF no RL 1 kHz 71 6 BW 500 kHz DAC output buffer ON _ 78 _ Total harmonic CL lt 50 pF RL 2 5 kO 1 kHz THD dB distortion DAC output buffer OFF _ m _ CL lt 50 pF no RL 1 kHz DAC output buffer ON 70 4 Signal to noise CL lt 50 pF RL gt 5 kO 1 kHz I I SINAD and distortion dB ratio DAC output buffer OFF _ 71 _ CL lt 50 pF no RL 1 kHz DAC output buffer ON _ 11 4 _ Effective CL lt 50 pF RL gt 5 1 kHz ENOB 7 bits number of bits DAC output buffer OFF _ _ CL lt 50 pF no RL 1 kHz Ky DoclD025976 Rev 2 155 213 Electrical characteristics STM32L476xx Guaranteed by design not tested in production Difference between two consecutive codes 1 LSB Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095 Difference between the value measured at Code 0x001 and the ideal value af WN gt Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and OxFFF
117. CH2 2 1 SMBA SPI1 MOSI SPI3 MOSI USART1 UARTS5 CTS TSC G2 IO2 LCD SEGS COMP2 OUT SAM SD B TIM16 BKIN EVENTOUT 58 59 B7 AT B7 AT 92 93 B5 B4 136 137 PB6 PB7 FT fa FT fla LPTIM1 ETR TIM4_CH1 TIM8 BKIN2 I2C1 SCL DFSDM DATIN5 USART1 TX TSC G2 103 TIM8 BKIN2 COMP2 SAI FS B TIM16 CH1N EVENTOUT LPTIM1 IN2 TIM4_CH2 TIM8 BKIN I2C1 SDA DFSDM 5 USART1 RX UARTA CTS TSC G2 104 LCD SEG21 NL TIM8 BKIN COMP 1 TIM17 CH1N EVENTOUT COMP2_ INP COMP2_ INM PVD_IN 60 D7 D7 94 A4 138 BOOTO 61 E7 E7 95 A3 139 PB8 FT fl TIM4 CH3 I2C1 SCL DFSDM DATING CAN1 RX LCD 5 16 SDMMC1_D4 SAI1_MCLK_A TIM16_CH1 EVENTOUT q DocID025976 Rev 2 69 213 Pinouts description STM32L476xx Table 14 STM32L476xx pin definitions continued Pin Number Pin functions co e e 5 5 5 2 8 8 E Alternate functions Additional reset gt D 3 functions lt di diu 231 Z Z 3 a z IR_OUT TIM4_CH4 I2C1 SDA SPI2 NSS DFSDM CKING 62 E8 E8 96 B3 140 9 FT fl CAN1 TX LCD COMS3 SDMMC1 D5 SAI FS A TIM17 1 EVENTOUT 4 LCD SEG36
118. Cs and also as voltage reference for external components through the VREF pin The internal voltage reference buffer supports two voltages e 2 048V 2 5 An external voltage reference can be provided through the VREF pin when the internal voltage reference buffer is off The VREF pin is double bonded with VDDA on some packages In these packages the internal voltage reference buffer is not available Comparators COMP The STM32L476xx devices embed two rail to rail comparators with programmable reference voltage internal or external hysteresis and speed low speed for low power and with selectable output polarity The reference voltage can be one of the following e External I O e DAC output channels e internal reference voltage or submultiple 1 4 1 2 3 4 All comparators can wake up from Stop mode generate interrupts and breaks for the timers and can be also combined into a window comparator q DocID025976 Rev 2 STM32L476xx Functional overview 3 19 3 20 Note q Operational amplifier OPAMP The STM32L476xx embeds two operational amplifiers with external or internal follower routing and PGA capability The operational amplifier features e Low input bias current e Low offset voltage e Low power mode e Railto rail input Touch sensing controller TSC The touch sensing controller provides a simple solution for adding capacitive sensing functionality to any application Capacitiv
119. Development support serial wire debug SWD JTAG Embedded Trace Macrocell Table 1 Device summary Reference Part number STM32L476RG STM32L476JG STM32L476MG STM32L476ME STM32L476VG STM32L476QG STM32L476xx STM32L476ZG STM32L476RE STM32L476JE STM32L476VE STM32L476QE STM32L476ZE STM32L476RC STM32L476VC DoclD025976 Rev 2 1 213 This is information on a product in full production www st com Contents STM32L476xx Contents 1 Introd ction a a S s Rs AS 11 2 Description 12 3 Functional overview 16 3 1 Cortex M4 core with FPU 16 3 2 Adaptive real time memory accelerator ART Accelerator V 16 3 3 Memory protection 16 3 4 Embedded Flash memory 17 3 5 Embedded 18 3 6 Firewall OD dde qe 18 3 7 Boot modes ERE a dae abe pate S id 19 3 8 Cyclic redundancy check calculation unit 19 3 9 Power supply management 19 3 9 1 Power supply schemes 19 3 9 2 Power supply supervisor 20 3 9 3 Voltage regulator 21 3 9 4 Low pow
120. EVENTOUT q DocID025976 Rev 2 63 213 Pinouts description STM32L476xx Table 14 STM32L476xx pin definitions continued Pin Number Pin functions Pin name function after reset Additional Alternate functions functions LQFP64 WLCSP72 WLCSP81 LQFP100 UFBGA132 LQFP144 Pin type VO structure Notes TIM1_CH2N TIM8_CH2N I2C2_SDA SPI2_MISO DFSDM_DATIN2 USART3 RTS DE 35 G2 G2 53 75 PB14 VO FTA TSC_G1_IO3 LCD_SEG44 SWPMI1_RX SAI2 MCLK A TIM15 CH1 EVENTOUT REFIN TIM1_CH3N TIM8 CH3N SPI2 MOSI DFSDM CKIN2 TSC G1 104 36 G1 G1 54 K10 76 PB15 LCD SWPMI1 SUSPEND SAI2 SD A TIM15 CH2 EVENTOUT TX 25 55 K9 77 PD8 FT I LCD SEG28 FMC D13 EVENTOUT USART3 RX LCD SEG29 FMC D14 24 56 78 PD9 FT I 5 2 MCLK USART3_CK TSC_G6_IO1 57 J42 79 PD10 VO FTI LCD_SEG30 015 SAI2 5 A EVENTOUT USART3 CTS TSC G6 102 58 J11 80 PD11 UO LCD SEG31 16 SAI2 SD A LPTIM2 ETR EVENTOUT TIM4 CH1 USART3 DE TSC G6 103 59 40 81 PD12 VO FTI LCD_SEG32 17 SAI2 FS 2 IN1 EVENTOUT 4 CH2 TSC G6 104 60 12 82 PD13 UO LCD SEG33 18 LPTIM2_OUT EVE
121. FF 3KB Reserved 0x4002 2000 0x4002 23FF 1 KB FLASH registers 0 4002 1400 0 4002 1FFF 3 KB Reserved 0x4002 1000 0x4002 13FF 1 KB RCC 0x4002 0800 0x4002 OFFF 2KB Reserved 0x4002 0400 0x4002 07FF 1 KB DMA2 0x4002 0000 0x4002 1 KB DMA1 Ky DoclD025976 Rev 2 87 213 Memory mapping STM32L476xx 88 213 Table 17 STM32L476xx memory map and peripheral register boundary addresses continued Bus Boundary address 0 4001 6400 0x4001 FFFF 39 Reserved 0x4001 6000 0x4000 63FF 1 DFSDM 0x4001 5C00 0x4000 5FFF 1 Reserved 0x4001 5800 0x4000 5BFF 1 KB SAI2 APB2 0x4001 5400 0x4000 57FF 1 KB 0 4001 4 00 0 4000 53FF 2 Reserved 0x4001 4800 0x4001 4BFF 1 17 0 4001 4400 0 4001 47FF 1 KB 16 0 4001 4000 0 4001 43FF 1 15 0 4001 3C00 0 4001 3FFF 1 Reserved 0x4001 3800 0x4001 3BFF 1 USART1 0x4001 3400 0x4001 37FF 1 KB TIM8 0x4001 3000 0x4001 33FF 1 KB SPI1 0x4001 2 00 0x4001 2FFF 1 TIM1 0x4001 2800 0x4001 2BFF 1 KB SDMMC1 APB2 0x4001 2000 0x4001 27FF 2KB Reserved 0x4001 1 00 0x4001 1FFF 1 FIREWALL 0x4001 0800 0x4001 1BFF 5 KB Reserved 0x4001 0400 0x4001 07FF 1 EXTI 0 4001 0200 0x4001 O3FF COMP 0x4001 0030 0x4001 01FF 1 KB VREFBUF 0x4001 0000 0x4001 002F SYSCFG DoclD025976 Rev 2 q
122. FFF 0000 0x1000 8000 SRAM2 0x2000 0000 0x1000 0000 0x0810 0000 0 CODE Flash memory MM eserve 0x0000 0000 0x0010 0000 Flash system memory or SRAM depending on Reserved 0x0000 0000 BOOT configuration 0 000 0000 0 4800 0000 0 000 0000 0 8000 0000 0 6000 0000 Peripherals 38 0 4000 0000 MS34100V3 86 213 DoclD025976 Rev 2 Ly STM32L476xx Memory mapping Table 17 STM32L476xx memory map and peripheral register boundary addresses 7 Bus Boundary address OxA000 1000 0xA000 13FF 1 QUADSPI OxA000 0000 0xA000 OFFF 4 FMC 0x5006 0800 0x5006 OBFF 1 KB RNG 0x5004 0400 0x5006 07FF 129 KB Reserved 0x5004 0000 0x5004 1 ADC 0x5000 0000 0x5003 FFFF 16 KB OTG FS 0x4800 2000 Ox4FFF FFFF 127 MB 0x4800 1 00 0x4800 1FFF 1 KB GPIOH AHB2 0x4800 1800 0x4800 1BFF 1 GPIOG 0x4800 1400 0x4800 17FF 1 KB GPIOF 0x4800 1000 0x4800 13FF 1 KB GPIOE 0 4800 0 00 0x4800 OFFF 1 GPIOD 0x4800 0800 0x4800 0BFF 1KB GPIOC 0x4800 0400 0x4800 07FF 1 GPIOB 0x4800 0000 0x4800 1 KB GPIOA 0x4002 4400 Ox47FF FFFF 127 MB Reserved 0x4002 4000 0x4002 43FF 1 TSC 0x4002 3400 0x4002 3FFF 1KB Reserved 0x4002 3000 0x4002 33FF 1 KB CRC 0x4002 2400 0x4002 2F
123. FFSETN at high common _ _ 1 TBD TRIMLPOFFSETN input voltage 0 9 x VppA i Normal mode y 5 500 LOAD rive current DDA gt Low power mode 100 pA Drive current in Normal mode Un 22 V 450 LOAD_PGA mode Low power mode 50 Resistive load Normal mode 4 connected RLOAD VppA lt 2 V VSSA or to Low power mode 20 VDDA Resistive load Normal mode 4 5 kO in PGA mode RLoAD PGA connected to VDDA lt 2 V T VSSA or to Low power mode 40 VppA Ci oAD Capacitive load 50 pF ME Common mode Normal mode 85 3d rejection ratio ow power mode 2 90 Normal mode CLOAD 50 pf 70 85 PSRR Power supply 2 4 DC dB rejection ratio C lt 50 pf LOAD 99 _ Low power mode Rioap 20 DC 72 90 Ly DoclD025976 Rev 2 159 213 Electrical characteristics STM32L476xx Table 69 OPAMP characteristics continued Symbol Parameter Conditions Min Typ Max Unit Normal mode VppA gt 2 4 V 550 1600 2200 Gain Bandwidth Low power mode _ 1 100 420 600 GBW kHz Product Normal mode 24 V 250 700 950 Low power mode RANGE 0 40 180 280 Normal mode 700 Slew rate VppA gt 2 4 V 10 Low power mode 180 ms 90 of output Normal mode 300 voltage
124. Hz in Range 2 2 MHz in XXQZVIZEINLS M IAJBAO Functional overview STM32L476xx 24 213 By default the microcontroller is in Run mode after a system or a power Reset It is up to the user to select one of the low power modes described below Sleep mode In Sleep mode only the CPU is stopped All peripherals continue to operate and can wake up the CPU when an interrupt event occurs Low power run mode This mode is achieved with VCORE supplied by the low power regulator to minimize the regulator s operating current The code can be executed from SRAM or from Flash and the CPU frequency is limited to 2 MHz The peripherals with independent clock can be clocked by HSI16 Low power sleep mode This mode is entered from the low power run mode Only the CPU clock is stopped When wakeup is triggered by an event or an interrupt the system reverts to the low power run mode Stop 1 and Stop 2 modes Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers All clocks in the VCORE domain are stopped the PLL the MSI RC the HSI16 RC and the HSE crystal oscillators are disabled The LSE or LSI is still running The RTC can remain active Stop mode with RTC Stop mode without RTC Some peripherals with wakeup capability can enable the HSI16 RC during Stop mode to detect their wakeup condition Two Stop modes are available Stop 1 and Stop 2 modes In Stop 2 mode most of the
125. Low power mode wakeup timings continued Symbol Parameter Conditions Unit Wakeup clock MSI 48 MHz 5 6 TBD Range 1 Regulator in Wakeup clock HSI16 16 MHz 4 7 TBD Wakeup clock MSI 24 MHz 57 TBD during Stop 1 mode Range 2 Wakeup clock HSI16 16 MHz 4 5 TBD Wake up time from Wakeup clock MSI 4 MHz 6 6 TBD Stop 1 mode to Run mode in Flash Wakeup clock MSI 48 MHz 6 2 TBD Range 1 Regulator in Wakeup clock HSI16 16 MHz 6 3 TBD low power Wakeup clock MSI 24 MHz 6 3 TBD mode during Stop 1 mode Range 2 Wakeup clock 5116 16 MHz 6 3 TBD Wakeup clock MSI 4 MHz 8 0 TBD Wakeup clock MSI 48 MHz 0 7 TBD Range 1 Regulator in Wakeup clock 5116 16 MHz 1 7 TBD mode Wakeup clock MSI 24 MHz 0 8 TBD twUSTOP1 uring us Stop 1 mode Range 2 Wakeup clock HSI16 16 MHz 1 7 TBD Wake up time from Wakeup clock MSI 4 MHz 2 4 TBD Stop 1 mode to Run mode in SRAM1 Wakeup clock MSI 48 MHz 4 5 TBD Range 1 Regulator in Wakeup clock HSI16 16 MHz 5 5 TBD ee power Wakeup clock MSI 24 MHz 5 0 TBD mode during Stop 1 mode Range 2 Wakeup clock 5116 16 MHz 5 5 TBD Wakeup clock MSI 4 MHz 8 2 TBD Wake up time from Stop 1 mode to Low 12 7 TBD power run mode in Flash Regulator in low power mode LPR 1 in Wakeup clock MSI 2 MHz Wake up time from P
126. M11 67 PE14 SPI1 MISO QUADSPI BK1 102 D11 EVENTOUT 62 213 DoclD025976 Rev 2 Ly STM32L476xx Pinouts and pin description Table 14 STM32L476xx pin definitions continued Pin Number LQFP64 WLCSP72 WLCSP81 LQFP100 UFBGA132 M12 LQFP144 Pin name function after reset PE15 Pin type VO structure Notes Pin functions Alternate functions TIM1_BKIN TIM1_BKIN_COMP1 SPI1 MOSI QUADSPI BK1 103 D12 EVENTOUT Additional functions 29 H3 H3 47 L10 69 PB10 FT fl TIM2 CHS3 I2C2 SCL SPI2 SCK DFSDM_DATIN7 USART3_TX LPUART1_RX QUADSPI_CLK LCD_SEG10 COMP1_OUT SAI1_SCK_A EVENTOUT 30 G3 G3 48 L11 70 PB11 FT fl TIM2 I2C2 SDA DFSDM_CKIN7 USART3_RX LPUART1_TX QUADSPI_NCS LCD_SEG11 COMP2_OUT EVENTOUT 31 J2 J2 49 F12 71 VSS 32 33 J1 H1 J1 H1 50 51 G12 L12 72 73 VDD PB12 TIM1 TIM1 2 I2C2 SMBA 5 2 55 DFSDM_DATIN1 USART3_CK LPUART1_RTS_DE TSC_G1_101 LCD_SEG12 SWPMI1_IO SAI2 FS A TIM15 BKIN EVENTOUT 34 H2 H2 52 K12 74 PB13 FT fl TIM1 CH1N 2 2 SCL SPI2 SCK DFSDM 1 USART3 CTS LPUART1 CTS TSC G1 102 LCD 5 13 SWPMM TX SAI2 SCK A TIM15 CH1N
127. M3 hysteresis 10 Vnyst hysteresis 10 E mV lbp 1 and PVM2 PVM1 PVM2 0 2 2 consumption from Vpp PVM3 and PVM4 PVM3 PVM4 2 2 consumption from Vpp 1 Continuous mode means Run Sleep modes or temperature sensor enable in Low power run Low power sleep modes Guaranteed by design not tested in production BORO is enabled in all modes except shutdown and its consumption is therefore included in the supply current characteristics tables q 98 213 DocID025976 Rev 2 STM32L476xx Electrical characteristics 6 3 4 Embedded voltage reference The parameters given in Table 24 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21 General operating conditions Table 24 Embedded internal voltage reference Symbol Parameter Conditions Min Typ Max Unit VREFINT Internal reference voltage 40 C lt TA lt 130 C 1 182 1 212 1 232 V ADC sampling time when 15 vrefint 1 reading the internal reference 40 Hs voltage Start time of reference voltage start_vrefint buffer when ADC is enable x 7 120 HS Vrerint buffer consumption from Vpp when converted by 12 5 200 Ipp VREFINTBUF ADC Internal reference voltage AVREFINT spread over the temperature Vpp 3 V TBD
128. MC_NADV high 1 low to FMC valid 16 25 3 5 tacLKH alv FMC_CLK high to Ax invalid x 16 25 THCLK ta CLKL NOEL FMC_CLK low to FMC_NOE low 1 5 ns ta CLKH NOEH FMC_CLK high to FMC_NOE high Tucikt1 tacLKL apv FMC_CLK low to FMC_AD 15 0 valid 4 FMC_CLK low to FMC_AD 15 0 invalid 0 tsu ADV CLKH FMC_A D 15 0 valid data before FMC_CLK high 0 FMC_A D 15 0 valid data after FMC_CLK high 2 5 tsu NWAIT CLKH NWAIT valid before FMC_CLK high 0 th CLKH NWAIT FMC_NWAIT valid after high 4 1 CL 30 pF 2 Based characterization not tested production DocID025976 Rev 2 q Electrical characteristics STM32L476xx Figure 40 Synchronous multiplexed PSRAM write timings 0 BUSTURN d CLKH NExH t d CLKH AIV MSv38001V1 d LKH NWEH t d GLKH NBLH ITV t ta cLKL Data Data latency 0 NExL ta cLKL FMC_CLK ta cLKuLNADVH gt Q lt 5 iB lt o z LL FMC A 25 16 NWEL ae eee ae dl a ee 3 9 4 lt X dl omen um a lt a4 8 EN z g 288 m z Z 2 a 209 gt Q SEE u lt lt
129. MHz Reduced code 10 2 127 all peripherals _ Coremark 10 9 136 disable oo 2 0 Dhrystone 2 1 11 0 137 HA MHz 5 Fibonacci 10 5 131 Em While 1 9 9 124 Reduced code 272 136 Coremark 291 145 fuck fusi 2 MHz all peripherals disable Dhrystone 2 1 302 151 2 Fibonacci 269 135 While 1 269 135 1 Reduced code used for characterization results provided in Table 25 Table 26 Table 27 104 213 DoclD025976 Rev 2 q STM32L476xx Electrical characteristics Table 29 Typical current consumption in Run and Low power run modes with different codes running from Flash ART disable Conditions TYP TYP Symbol Parameter Volt Unit Unit Code 25 C 25 C scaling Reduced codel 3 1 119 2 Coremark 2 9 111 fucik fuse up to E Dhrystone 2 1 2 8 mA 111 HA MHZ 48 MHz included X Fibonacci 2 7 104 Supply bypass mode 1565 current PLL ON above u T 100 Run mode 48 MHz Reduced code 10 0 125 all peripherals 9 4 117 disable 9 Dhrystone 2 1 91 mA 14 2 A Fibonacci 9 0 112 5 While 1 9 3 116 Reduced codel 358 179 Coremark 392 196 current HCLK MSI z Ipp LPRun Low power all peripherals disable Dhrystone 2 1 390 HA 195 WA MHZz run Fibonacci 385 192 While 1
130. MSv38002V1 X gt E 2 x cm p Sj ENEI ENERE i z m 5 x 2 2 I 5 5 g lt mm or 2 x 2 5 Electrical characteristics 30 pF 2 Based on characterization not tested in production CL 1 Figure 42 Synchronous non multiplexed PSRAM write timings Data latency 0 ey ta CLKL NExL FMC_CLK CLKII NADVH ta ta CLKL NADVL FMC_NEx FMC_NADV FMC_A 25 0 NWEL t ir d CLKL Data t D 15 0 WAITCFG E lt gt O iL INWAITV CLKH tsu 0b WAITPOL 0b FMC_NBL DocID025976 Rev 2 188 213 STM32L476xx Electrical characteristics q Table 96 Synchronous non multiplexed PSRAM write timings 1 2 1 Symbol Parameter Min Max tw CLK FMC_CLK period 2 0 5 taCLKL NExL FMC_CLK low to FMC_NEx low 0 2 2 ta CLKH NExH FMC_CLK high to FMC_NEx high 0 2 0 5 taCcLKL NADVL FMC_CLK low to FMC_NADV low 2 ta CLKL NADVH FMC_CLK low to FMC_NADV high 2 5 ta CLKL AV FMC_CLK low to FMC_Ax valid x 16 25 5 FMC_CLK high to FMC_Ax invalid 16 25 1 ta CLKL NWEL FMC_CLK low to FMC_NWE low
131. NTOUT ee 209 VSS Sij a e EXPE MEET VDD B lt ss al 64 213 DoclD025976 Rev 2 STM32L476xx Pinouts and pin description Table 14 STM32L476xx pin definitions continued Pin Number Pin functions Pin name 2 Role 5 f ti ft 8 o 7 lt Alternate functions Additional amp reset gt i 3 functions G u 31 Z Z 3 3 a z TIM4_CH3 LCD_SEG34 61 85 PD14 VO FTI 00 EVENTOUT TIM4_CH4 LCD SEG35 62 10 86 PD15 FTI D1 EVENTOUT SPI1 SCK FMC A12 S e pes 610 87 PGZ Oh eee SAI2_SCK_B EVENTOUT SPI1 MISO FMC A13 dE 88 d nO es SAI2_FS_B EVENTOUT I SPI1 MOSI FMC_A14 F10 89 PG4 FTs SAI2 MCLK B EVENTOUT SPI1 NSS LPUART1 CTS es S eer ee 15 SAI2 SD I EVENTOUT I2C3 5 64191 PG6 LPUART1_RTS_DE EVENTOUT I2C3 SCL LPUART1 TX me cee pen MEI PN FMC INT3 EVENTOUT I2C3 SDA LPUART1 6 93 8 FT fs EVENTOUT 94 VSS S 95 VDDIO2 s TIM3_CH1 TIM8_CH1 DFSDM_CKIN3 TSC_G4_IO1 37 63 E12 96 6 LCD_SEG24
132. SCK USART1_RIS_ WO PB4 NJTRST TIM3_CH1 SPI1 MISO SPI3 MISO 1 CTS PB5 LPTIM1 IN1 TIM3 CH2 2 1 SMBA SPI1 MOSI SPI3 MOSI USART1 CK PB6 LPTIM1 ETR 4 CH1 TIM8 BKIN2 12 1 SCL DFSDM DATIN5 USART1 TX PB7 LPTIM1_IN2 TIM4_CH2 TIM8_BKIN 12C1_SDA DFSDM CKIN5 USART1_RX Port B PB8 4 CH3 2 1 SCL DFSDM DATING PB9 IR OUT TIM4_CH4 I2C1 SDA SPI2 NSS DFSDM CKIN6 PB10 TIM2 CH3 2 2 SCL SPI2 SCK DFSDM DATIN7 USART3 TX PB11 TIM2 CH4 2 2 SDA DFSDM CKIN7 USART3 RX PB12 1 BKIN 2 2 5 5 2 55 DFSDM_DATIN1 USART3 CK PB13 TIM1 CH1N 2 2 SCL SPI2 SCK DFSDM CKIN1 USART3 CTS PB14 TIM1 CH2N TIM8 CH2N 2 2 SDA SPI2 MISO DFSDM_DATIN2 15 RTC REFIN TIM1 CH3N TIM8 CH3N SPI2 MOSI DFSDM CKIN2 uonduosep uid pue XXQZV TZEINLS c 94 9768c0GI oq 12 62 Table 15 Alternate function AF0 to AF7 for AF8 to AF15 see Table 76 continued AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 Port TIM1 TIM2 TIM1 TIM2 USART1 SYS_AF TIM5 TIM8 TIM3 TIM4 TIM8 12C1 12C2 12C3 SPI1 SPI2 SPI3 DFSDM USART2 LPTIM1 TIM5 USART3 PCO LPTIM1_IN1 I2C3 SCL DFSDM_DATIN4 PC1 LPTIM1_OUT I2C3 SDA DFSDM 4 PC2 LPTIM1 IN2 SPI2 MISO DFSDM_CKOUT PC3 LPTIM1 ETR SPI2 MOSI PC4 USART3 TX PC5
133. SCL pins are not true open drain When configured as open drain the PMOS connected between the I O pin and Vppjo is disabled but is still present Only FT_f I O pins support Fm low level output current maximum requirement Refer to Section 6 3 14 port characteristics for the I2C 1 characteristics All I2C SDA SCL I Os embed an analog filter Refer to the table below for the analog filter characteristics Table 77 I2C analog filter characteristics Symbol Parameter Min Max Unit Maximum pulse width of spikes tAF that are suppressed by the analog 502 2600 ns filter 1 Guaranteed by design not tested in production 2 Spikes with widths below are filtered Spikes with widths above are not filtered Ky DoclD025976 Rev 2 165 213 Electrical characteristics STM32L476xx SPI characteristics Unless otherwise specified the parameters given in Table 78 for SPI are derived from tests performed under the ambient temperature fpc frequency and supply voltage conditions summarized in Table 21 General operating conditions Output speed is set to OSPEEDRy 1 0 11 e Capacitive load C 30 pF e Measurement points are done at CMOS levels 0 5 x Vpp Refer to Section 6 3 14 I O port characteristics for more details on the input output alternate function characteristics NSS SCK MOSI MISO for SPI Table 78 SPI characteristics 7
134. STM32 CPU as an instruction code while all other accesses DMA debug and CPU data read write and erase are strictly prohibited One area per bank can be selected with 64 bit granularity An additional option bit PCROP RDP allows to select if the PCROP area is erased or not when the RDP protection is changed from Level 1 to Level 0 DoclD025976 Rev 2 17 213 Functional overview STM32L476xx 3 5 3 6 18 213 The whole non volatile memory embeds the error correction code ECC feature supporting e single error detection and correction e double error detection e The address of the ECC fail can be read in the ECC register Embedded SRAM STM32L476xx devices feature up to 128 Kbyte of embedded SRAM This SRAM is split into two blocks e 96 Kbyte mapped at address 0x2000 0000 SRAM1 e 32 Kbyte located at address 0x1000 0000 with hardware parity check SRAM2 This block is accessed through the ICode DCode buses for maximum performance These 32 Kbyte SRAM can also be retained in Standby mode The SRAM2 can be write protected with 1 Kbyte granularity The memory can be accessed in read write at CPU clock speed with 0 wait states Firewall The device embeds a Firewall which protects code sensitive and secure data from any access performed by a code executed outside of the protected areas Each illegal access generates a reset which kills immediately the detected intrusion The Firewall main features are the fol
135. TZEINLS 94 9768c0GI oq Table 16 Alternate function AF8 to AF15 for AF0 to AF7 see Table 15 continued AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 Port UARTA SDMMC1 1 TIM2 TIM15 UART5 CAN1 TSC OTG FS QUADSPI LCD COMP2 FMC SAM SAI2 TIM16 TIM17 EVENTOUT LPUART1 SWPMI1 LPTIM2 PDO CAN1_RX D2 PD1 CAN1 TX FMC D3 EVENTOUT LCD COM7 PD2 UART5 RX TSC SYNC LCD SEG31 SDMMC1_CMD EVENTOUT LCD SEG43 PD3 FMC CLK EVENTOUT PD4 EVENTOUT PD5 FMC NWE EVENTOUT PD6 NWAIT SAM SD A EVENTOUT Pot p PD7 NE1 EVENTOUT PD8 LCD SEG28 FMC D13 EVENTOUT PD9 LCD SEG29 FMC D14 imr gt EVENTOUT PD10 TSC G6 101 LCD SEG30 D15 SAI2 SCK A EVENTOUT PD11 TSC G6 102 LCD SEG31 FMC A16 SAI2 SD A LPTIM2 ETR EVENTOUT PD12 TSC G6 103 LCD SEG32 FMC A17 SAI2 FS LPTIM2 IN1 EVENTOUT PD13 TSC G6 104 LCD SEG33 FMC A18 LPTIM2 OUT EVENTOUT PD14 LCD SEG34 DO EVENTOUT PD15 LCD SEG35 FMC D1 EVENTOUT XXQZVTIZEINLS uonduosep uid pue s ynould 6 8 94 9 6 20 Table 16 Alternate function AF8 to AF15 for AF0 to AF7 see Table 15 continued AF8 AF9 AF10 AF11 AF12
136. VCORE domain is put in a lower leakage mode Stop 1 offers the largest number of active peripherals and wakeup sources a smaller wakeup time but a higher consumption than Stop 2 The system clock when exiting from Stop1 or Stop2 modes can be either MSI up to 48 MHz HS116 depending on software configuration Standby mode The Standby mode is used to achieve the lowest power consumption with BOR The internal regulator is switched off so that the VCORE domain is powered off The PLL the MSI RC the HSI16 RC and the HSE crystal oscillators are also switched off The RTC can remain active Standby mode with RTC Standby mode without RTC The brown out reset BOR always remains active in Standby mode The state of each I O during standby mode can be selected by software I O with internal pull up internal pull down or floating After entering Standby mode SRAM1 and register contents are lost except for registers in the Backup domain and Standby circuitry Optionally SRAM2 can be retained in q DocID025976 Rev 2 STM32L476xx Functional overview q Standby mode supplied by the low power Regulator Standby with RAM2 retention mode The device exits Standby mode when an external reset NRST pin an IWDG reset WKUP pin event configurable rising or falling edge or an RTC event occurs alarm periodic wakeup timestamp or a failure is detected on LSE CSS LSE The system clock after wakeup is MSI u
137. WR CR1 Stop 1 mode to Low 107 TBD power run mode in SRAM1 DoclD025976 Rev 2 121 213 Electrical characteristics STM32L476xx Table 40 Low power mode wakeup timings continued Symbol Parameter Conditions Unit Wakeup clock MSI 48 MHz 8 0 TBD Range 1 Regulator Wakeup clock HSI16 16 MHz 7 3 TBD Wake up time from l w Dower Stop 2 mode to Run p Wakeup clock MSI 24 MHz 8 2 TBD mode in Flash mode during Stop 2 mode Range 2 Wakeup clock HSI16 16 MHz 7 3 TBD Wakeup clock MSI 4 MHz 10 6 TBD t Wakeup clock MSI 48 2 5 1 TBD Range 1 2 Regulator Wakeup clock 5116 16 MHz 5 7 TBD Wake up time from l w towaf Hs Stop 2 mode to Run pawel Wakeup clock MSI 24 MHz 5 5 TBD mode SRAM1 Stop 2 mode Range 2 Wakeup clock HSI16 16 MHz 5 7 TBD Wakeup clock MSI 4 MHz 8 2 TBD Wakeup time from Standby mode to Wakeup clock MSI 8 MHz 14 3 TBD twusTBY p d Range 1 un mode Wakeup clock MSI 4 MHz 20 1 TBD IWUSHDN 2 from Shutdown mode Range 1 clock MSI 4 MHz 256 TBD 1 Based on characterization not tested in production Table 41 Regulator modes transition times Symbol Parameter Conditions Typ Max Unit Wakeup time from Low Code run with MSI 2 MHz TBD TBD power run mode to Run wakeup with Regulator in Range 2 twULPRUN mode regulator tr
138. able 104 WLCSP72 72 pin 4 4084 x 3 7594 mm 0 4 mm pitch wafer level chip scale package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 0 525 0 555 0 585 0 0207 0 0219 0 0230 A1 0 175 0 0069 A2 0 380 0 0150 I A30 0 025 I 0 0010 pb 0 220 0 250 0 280 0 0087 0 0098 0 0110 D 4 3734 4 4084 4 4434 0 1722 0 1736 0 1749 E 3 7244 3 7594 3 7944 0 1466 0 1480 0 1494 e 0 400 0 0157 1 3 200 0 1260 e2 3 200 0 1260 F 0 6042 0 0238 DocID025976 2 203 213 Package information STM32L476xx 204 213 Table 104 WLCSP72 72 pin 4 4084 x 3 7594 mm 0 4 mm pitch wafer level chip scale package mechanical data continued millimeters 7 Symbol Min Typ Max Min Typ Max G 0 2797 0 0110 aaa 0 100 0 0039 bbb 0 100 0 0039 ccc 0 100 0 0039 ddd 0 050 0 0020 eee 0 050 0 0020 1 Values in inches are converted from mm and rounded to 4 decimal digits 2 Back side coating 3 Dimension is measured at the maximum bump diameter parallel to primary datum Z Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location Figure 58 WLCSP72 marking package top view Ball A1 identifier Product identification Lu bJGYE LL JL Re
139. al trigger Y Y Y Y DFSDM 1 LPTIM1 only 30 213 DocID025976 Rev 2 q STM32L476xx Functional overview 3 11 Clocks and startup The clock controller see Figure 3 distributes the clocks coming from different oscillators to the core and the peripherals It also manages clock gating for low power modes and ensures clock robustness It features e Clock prescaler to get the best trade off between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler Safe clock switching clock sources can be changed safely on the fly in run mode through a configuration register e Clock management to reduce power consumption the clock controller can stop the clock to the core individual peripherals or memory e System clock source four different clock sources can be used to drive the master clock SYSCLK 4 48 MHz high speed external crystal or ceramic resonator HSE that can supply a PLL The HSE can also be configured in bypass mode for an external clock 16 MHz high speed internal RC oscillator HSI16 trimmable by software that can supply a PLL Multispeed internal RC oscillator MSI trimmable by software able to generate 12 frequencies from 100 kHz to 48 MHz When a 32 768 kHz clock source is available in the system LSE the MSI frequency can be automatically trimmed by hardware to reach better than 0 25 accuracy In this mode the MSI
140. an independent BCD timer counter It supports the following features e Calendar with subsecond seconds minutes hours 12 or 24 format week day date month year in BCD binary coded decimal format e Automatic correction for 28 29 leap year 30 and 31 days of the month e Two programmable alarms e On the fly correction from 1 to 32767 RTC clock pulses This can be used to synchronize it with a master clock e Reference clock detection a more precise second source clock 50 or 60 Hz can be used to enhance the calendar precision e Digital calibration circuit with 0 95 ppm resolution to compensate for quartz crystal inaccuracy e Three anti tamper detection pins with programmable filter Timestamp feature which can be used to save the calendar content This function can be triggered by an event on the timestamp pin or by a tamper event or by a switch to VBAT mode e 17 bit auto reload wakeup timer WUT for periodic events with programmable resolution and period The RTC and the 32 backup registers are supplied through a switch that takes power either from the Vpp supply when present from the VBAT pin The backup registers are 32 bit registers used to store 128 bytes of user application data when VDD power is not present They are not reset by a system or power reset or when the device wakes up from Standby or Shutdown mode The RTC clock sources can be e A32 768 kHz external crystal LSE e An externa
141. ansition time from low power mode Code run with MSI 2 MHz TBD us to main mode wakeup with Regulator in Range 1 Regulator transition time tvosT from Range 2 to Range 19 Code run with MSI 24 MHz TBD TBD 1 Based on characterization not tested in production Time until REGLPF flag is cleared in PWR 5 2 Time until VOSF flag is set PWR SR2 122 213 DoclD025976 Rev 2 q STM32L476xx Electrical characteristics 6 3 7 External clock source characteristics High speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO The external clock signal has to respect the characteristics in Section 6 3 14 However the recommended clock input waveform is shown in Figure 15 High speed external clock source AC timing diagram Table 42 High speed external user clock characteristics 1 Symbol Parameter Conditions Min Typ Max Unit Voltage scaling _ 8 48 Range 1 fuse ex User external clock source frequency MHz Voltage scaling _ 8 26 Range 2 VuseH OSC_IN input pin high level voltage 0 7 Vppiox Vppiox V VuseL OSC IN input pin low level voltage Vss 0 3 Vppiox Voltage scaling 7 t Range 1 w HSEH OSC_IN high or low time ns tw HSEL Voltage scaling 18 Range 2 1 Guaranteed by design not tested in production Figure 15
142. application with 8 MHz 126 Typical application with a 32 768 kHz 127 Typical current consumption versus MSI 132 I O input characteristics 140 AC characteristics definition 144 Recommended pin protection 145 ADC accuracy 151 Typical connection diagram using the ADC 151 12 bit buffered non buffered 154 SPI timing diagram slave mode and 0 167 SPI timing diagram slave mode 1 168 SPI timing diagram master 168 Quad SPI timing diagram SDR 170 Quad SPI timing diagram DDR 170 SAI master timing 172 SAI slave timing waveforms 22 2 2 2 173 SDIO high speed mode 174 SD default
143. ation after factory trim 3 This is a deviation for an individual part once the initial frequency has been measured 132 213 DocID025976 Rev 2 Ly STM32L476xx Electrical characteristics 4 Continuous mode means Run Sleep modes or temperature sensor enable in Low power run Low power sleep modes Sampling mode means Low power run Low power sleep modes with temperature sensor disable or Stop 1 Stop 2 Standby modes 6 Guaranteed by design not tested in production 6 3 9 PLL characteristics The parameters given in Table 49 are derived from tests performed under temperature and Vpp supply voltage conditions summarized in Table 21 General operating conditions Table 49 PLL PLLSAI1 PLLSAI2 characteristics Symbol Parameter Conditions Min Typ Max Unit PLL input 2 d 4 L 16 MHz IN PLL input clock duty cycle 45 55 Voltage scaling Range 1 2 0645 80 P our PLL multiplier output clock P MHz Voltage scaling Range 2 2 0645 26 Voltage scaling Range 1 8 80 f PLL multiplier output clock Q MHz Voltage scaling Range 2 8 26 Voltage scaling Range 1 8 80 our PLL multiplier output clock R MHz mE Voltage scaling Range 2 8 26 Voltage scaling Range 1 64 344 fvco OUT PLL VCO output MHz Voltage scaling Range 2 64 128 ti ock PLL lock time 15 40 us RMS cycle to cycle jitter 40 Jitter Syst
144. ation to measure the battery voltage using the internal ADC channel ADC1 IN18 or ADC3 IN18 As the voltage may be higher than VDDA and thus outside the ADC input range the VBAT pin is internally connected to a bridge divider by 3 As a consequence the converted digital value is one third the voltage Digital to analog converter DAC Two 12 bit buffered DAC channels can be used to convert digital signals into analog voltage signal outputs The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration This digital interface supports the following features e Upto two DAC output channels e 8 bitor 12 bit output mode e Buffer offset calibration factory and user trimming DoclD025976 Rev 2 37 213 Functional overview STM32L476xx 3 17 3 18 38 213 e Left or right data alignment 12 bit mode e Synchronized update capability e Noise wave generation e Triangular wave generation e Dual DAC channel independent or simultaneous conversions e DMA capability for each channel e External triggers for conversion e Sample and hold low power mode with internal or external capacitor The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels Voltage reference buffer VREFBUF The STM32L476xx devices embed an voltage reference buffer which can be used as voltage reference for ADCs DA
145. bus on the go full speed OTG 5 50 3 35 Flexible static memory controller FSMC 51 3 36 Quad SPI memory interface QUADSPI 52 3 37 Development 53 3 37 1 Serial wire JTAG debug port 5 53 3 37 2 Embedded Trace Macrocell 53 4 Pinouts and pin description 54 5 Memory 86 Ky DoclD025976 Rev 2 3 213 Contents STM32L476xx 6 Electrical characteristics 91 6 1 Parameter conditions 91 6 1 1 Minimum and maximum values 91 6 1 2 Typical values 91 6 1 3 Typical CUrVOS erede zou a a cea Te eu ae 91 6 1 4 Loading capacitor 91 6 1 5 Pin input voltage esses ccm rr Epod X Ra h E d 91 6 1 6 Power supply scheme 92 6 1 7 Current consumption measurement 93 6 2 Absolute maximum 08 93 6 3 Operating conditions 95 6 3 1 General operating conditions 95 6 3 2 Operating conditions a
146. by sum of all I Os and control pins 100 IO PIN PIN Total output current sourced by sum of all I Os and control pins 100 Injected current on FT_xxx TT_xx RST and B pins except PA4 4 lIN PIN Injected current on PA4 PAS 5 0 2 liNJ PIN Total injected current sum of all I Os and control pins 25 1 All main power Vpp 2 Vear and ground Vss Vssa pins must always be connected to the external power supplies in the permitted range 2 This current consumption must be correctly distributed over all 1 and control pins The total output current must not be sunk sourced between two consecutive power supply pins referring to high pin count QFP packages 3 Positive injection is not possible on these I Os and does not occur for input voltages lower than the specified maximum value 4 A positive injection is induced by gt Vppiox while a negative injection is induced by lt Vss must never be exceeded Refer also to Table 18 Voltage characteristics for the maximum allowed input voltage values 5 When several inputs are submitted to a current injection the maximum gt is the absolute sum of the positive and negative injected currents instantaneous values Table 20 Thermal characteristics Symbol Ratings Value Unit TsrG Storage temperature range 65 to 150 C Tj Maximum junction temperature 150
147. can feed the USB device saving the need of an external high speed crystal HSE The MSI can supply a PLL System PLL which can be fed by HSE 5116 or MSI with a maximum frequency at 80 MHz e Auxiliary clock source two ultralow power clock sources that can be used to drive the LCD controller and the real time clock 32 768 kHz low speed external crystal LSE supporting four drive capability modes The LSE can also be configured in bypass mode for an external clock 32 kHz low speed internal RC LSI also used to drive the independent watchdog The LSI clock accuracy is 5 accuracy e Peripheral clock sources Several peripherals USB SDMMC RNG SAI USARTS I2Cs LPTimers ADC SWPMI have their own independent clock whatever the system clock Three PLLs each having three independent outputs allowing the highest flexibility can generate independent clocks for the ADC the USB SDMMC RNG and the two SAls e Startup clock after reset the microcontroller restarts by default with an internal 4 MHz clock MSI The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts e Clock security system CSS this feature can be enabled by software If a HSE clock failure occurs the master clock is automatically switched to HSI16 and a software q DocID025976 Rev 2 31 213 Functional overview STM32L476xx 32 213 interrupt is generated if enabled LSE fail
148. clock HCLK frequency available in the RMO351 reference manual e When the peripherals are enabled fpci The parameters given in Table 25 to Table 38 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 21 General operating conditions q DocID025976 Rev 2 94 926S20d190d ELZ LOL Table 25 Current consumption in Run and Low power run modes code with data processing running from Flash ART enable Cache ON Prefetch OFF Conditions TYP 1 Symbol Parameter Unit Voltage 25 55 C 85 C 105 125 25 55 85 C 105 C 125 scaling 26MHz 288 2 93 3 05 323 3 58 3 20 3 37 3 51 3 93 4 76 16 MHz 1 83 1 87 1 98 2 16 249 2 01 2 16 2 30 272 3 34 8 MHz 0 98 1 02 1 12 1 29 1 62 1 10 1 17 1 31 1 73 2 56 Range 2 4 MHz 0 55 0 59 0 69 0 85 1 18 0 61 0 70 0 89 124 1 95 2 MHz 0 34 0 37 0 47 0 64 0 96 0 37 046 0 64 0 98 1 71 fucik fuse up to 1MHz 0 23 0 26 0 36 053 0 85 027 0 33 0 50 0 86 1 57 Suppl 48MHz included PPIY bypass mode 100 0 14 0 17 0 27 043 0 75 0 17 0 21 0 38 0 74 144 Ipp Run current in PLL ON above mA Run mode Vr al 80 MHz 10 2 10 3 10 5 107 11 1 1122 11 8 1
149. d by ST for such product ST and the ST logo are trademarks of ST All other product or service names are the property of their respective owners Information in this document supersedes and replaces information previously supplied in any prior versions of this document 2015 STMicroelectronics All rights reserved q DocID025976 Rev 2 213 213
150. de 7 for 41 us 1 Guaranteed by design not tested in production Table 51 Flash memory endurance and data retention Symbol Parameter Conditions Min Unit Neno Enduance Ta 40to 105 C 10 1 2 at TA 85 C 30 1 2 at TA 105 C 15 1 2 at TA 125 C 7 tRET Data retention F O T Years 10 kcycles 2 at 55 C 30 10 kcycles 2 at TA 85 C 15 10 kcycles 2 at TA 105 C 10 1 Data based on characterization results not tested in production 2 Cycling performed over the whole temperature range q 134 213 DocID025976 Rev 2 STM32L476xx Electrical characteristics 6 3 11 q EMC characteristics Susceptibility tests are performed on a sample basis during device characterization Functional EMS electromagnetic susceptibility While a simple application is executed on the device toggling 2 LEDs through 1 ports the device is stressed by two electromagnetic events until a failure occurs The failure is indicated by the LEDs e Electrostatic discharge ESD positive and negative is applied to all device pins until a functional disturbance occurs This test is compliant with the IEC 61000 4 2 standard e FTB A Burst of Fast Transient voltage positive and negative is applied to Vpp and Vss through a 100 pF capacitor until a functional disturbance occurs This test is compliant with the
151. dentification 1 Ly O Date code Pin 1 identifier 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity MSv36848V2 DoclD025976 Rev 2 195 213 Package information STM32L476xx 7 2 UFBGA132 package information Figure 50 UFBGA132 132 ball 7x7 mm ultra thin fine pitch ball grid array package outline Seating plane Sdad Z Y 1 A3 1 1 A1 ball X identifier index area E OOOOOOOOOOOO oooo B OOOO OO 000000000006 id LY i 12 b 132 balls TOP VIEW z Y X Ig fff Q Z A0G8 ME V1 BOTTOM VIEW 1 Drawing is not to scale Table 100 UFBGA132 132 ball 7x7 mm ultra thin fine pitch ball grid array package mechanical data
152. ditions summarized in Table 18 Voltage characteristics e The power consumption of the digital part of the on chip peripherals is given in Table 39 The power consumption of the analog part of the peripherals where applicable is indicated in each related section of the datasheet Table 39 Peripheral current consumption Peripheral Range 1 Range 2 dec Unit Bus Matrix 4 5 3 7 4 1 ADC independent clock domain 0 4 0 1 0 2 ADC AHB clock domain 5 5 4 7 5 5 CRC 0 4 0 2 0 3 DMA1 1 4 1 3 1 4 DMA2 1 5 1 3 14 FLASH 6 2 5 2 5 8 FMC 8 9 7 5 8 4 4 8 3 8 4 4 GPIOB 4 8 4 0 4 6 GPIOC 4 5 3 8 4 3 AHB GPIOD 4 6 3 9 4 4 2 GPIOE 5 2 4 5 4 9 GPIOF 5 9 4 9 5 7 GPIOG 4 3 3 8 4 2 GPIOH 0 7 0 6 0 8 d independent clock 23 2 NA NA OTG FS AHB clock domain 16 4 NA NA QUADSPI 7 8 6 7 7 3 RNG independent clock domain 2 2 NA NA RNG AHB clock domain 0 6 NA NA SRAM1 0 9 0 8 0 9 Ky DoclD025976 Rev 2 117 213 Electrical characteristics STM32L476xx Table 39 Peripheral current consumption continued Peripheral Range 1 Range 2 Unit SRAM2 1 6 1 4 1 6 AHB TSC 1 8 1 4 1 6 2 All AHB Peripherals 118 5 77 3 87 6 AHB to APB1 bridge 2 0 9 0 7 0 9 CAN1 4 6 4 0 4 4 DAC1 2 4 1 9 2 2 I2C1 independent clock domain 3 7 3 1 3 2 I2C1 clock domain 1
153. e E ns C 10 pF 2 7 VSVppio 3 6 V 2 5 C 10 pF 1 62 lt lt 2 7 V 5 C 10 pF 1 08 lt lt 1 62 V 12 C 30 pF 2 7 lt 53 6 V 120 C 30 pF 1 62 VSVppioxS2 7 V 50 Maximum frequency ind MHz C 10 pF 2 7 lt 53 6 V 180 11 C 10 pF 1 62 VSVppio S2 7 V 75 C 10 pF 1 08 lt lt 1 62 V 10 C 30 pF 2 7 lt lt 3 6 V 3 3 Tr Tf Output rise and fall time C 30 pF 1 62 lt lt 2 7 V 6 ns C 30 pF 1 08 lt lt 1 62 V 16 Fmax Maximum frequency 1 MHz Fm Output fall ime C 50 pF 1 6 VSVppiox 3 6 V a z 1 The I O speed is configured using the OSPEEDRy 1 0 bits The Fm mode is configured in the SYSCFG CFGRI1 register Refer to the 0351 reference manual for a description of GPIO Port configuration register q Guaranteed by design not tested in production This value represents the capability but the maximum system frequency is limited to 80 MHz DocID025976 Rev 2 The fall time is defined between 70 and 30 of the output waveform accordingly to 2 specification 143 213 Electrical characteristics STM32L476xx 6 3 15 Figure 21 I O AC characteristics definition 90 10 1 1 1 1 l 4 Maximum frequency is achieved if tr lt 2 3 and if the duty cycle is 45 55 when loaded by the specified capacitance MS32132V2
154. e falling edge both and can be masked independently A pending register maintains the status of the interrupt requests The internal lines are connected to peripherals with wakeup from Stop mode capability The EXTI can detect an external line with a pulse width shorter than the internal clock period Up to 114 GPIOs can be connected to the 16 external interrupt lines DoclD025976 Rev 2 35 213 Functional overview STM32L476xx 3 15 3 15 1 36 213 Analog to digital converter ADC The device embeds 3 successive approximation analog to digital converters with the following features 12 bit native resolution with built in calibration 5 33 Msps maximum conversion rate with full resolution Down to 18 75 ns sampling time Increased conversion rate for lower resolution up to 8 88 for 6 bit resolution Up to 24 external channels some of them shared between ADC1 and ADC2 or ADC1 ADC2 and ADC3 5 Internal channels internal reference voltage temperature sensor VBAT 3 DAC1 and DAC2 outputs One external reference pin is available on some package allowing the input voltage range to be independent from the power supply Single ended and differential mode inputs Low power design Capable of low current operation at low conversion rate consumption decreases linearly with speed Dual clock domain architecture ADC speed independent from CPU frequency Highly versatile digital interface Sing
155. e 1 5 10 2 4 8 tsu MSI 9 MSI oscillator start up time Range 3 3 7 Range 4 to 7 3 6 Range 8 to 11 2 5 6 10 96 of final 5 _ 0 25 500 frequency 6 MSI oscillator PLL mode 5 of final _ _ tsraB MSI stabilization time Range 11 frequency wh ms 0 1 of final I _ _ 25 frequency 130 213 DocID025976 Rev 2 q STM32L476xx Electrical characteristics Table 47 MSI oscillator characteristics continued Symbol Parameter Conditions Min Typ Max Unit Range 0 0 6 1 Range 1 0 8 1 2 Range 2 1 2 1 7 Range 3 1 9 2 5 Range 4 4 7 6 Ipp Msi i T Range 5 E 6 5 9 ih consumption Range 6 11 15 Range 7 18 5 25 Range 8 62 80 Range 9 85 110 Range 10 110 130 Range 11 155 190 Data based on characterization results not tested in production This is a deviation for an individual part once the initial frequency has been measured Sampling mode means Low power run Low power sleep modes with Temperature sensor disable S dede Average period of MSI 48 MHz is compared to a real 48 MHz clock over 28 cycles It includes frequency tolerance jitter of MSI 948 MHz clock 5 Only accumulated jitter of MSI 48 MHz is extracted over 28 cycles For next transition min and max jitter of 2 consecutive frame of 28 cycles of the MSI 48 MHz
156. e 36 Current consumption Standby mode continued Conditions TYP 1 Symbol Parameter Unit Vpp 25 55 C 85 C 105 125 25 55 85 C 105 C 125 Supply current 18 V 235 641 2293 5192 11213 588 1603 5733 12980 28033 Ipp SRAM2 2 24V 237 645 2303 5213 11246 593 1613 5758 13033 28115 4 andby mode when SRAM2 3V 236 647 2306 5221 11333 593 1618 5765 13053 28333 is retained 3 6V 235 646 2308 5200 11327 595 1620 5770 13075 28350 Supply current Ipp wakeup during wakeup wakeup clock is MSI from 3 V 1 7 mA from Standby 4 MHz Standby mode 1 Based on characterization not tested in production unless otherwise specified 2 Tested in production 3 Based on characterization done with a 32 768 kHz crystal MC306 G 06Q 32 768 manufacturer JFVNY with two 6 8 pF loading capacitors 4 The supply current in Standby with SRAM2 mode is Ipp Standby Ipp SRAM2 The supply current in Standby with RTC with SRAM2 mode is Ipp Standby RTC Ipp SRAM2 Table 37 Current consumption in Shutdown mode Conditions TYP MAX Symbol Parameter Unit Vpp 25 55 85 105 125 25 C 55 85 C 105 C 125 C Supply current 1 8V 29 8 194 1110 3250 9093 75 485 2775 8125 22733 n 24 1
157. e Both regulators are power down in Standby and Shutdown modes the regulator output is in high impedance and the kernel circuitry is powered down thus inducing zero consumption The ultralow power STM32L476xx supports dynamic voltage scaling to optimize its power consumption in run mode The voltage from the Main Regulator that supplies the logic VCORE can be adjusted according to the system s maximum operating frequency There are two power consumption ranges e Range 1 with the CPU running at up to 80 MHz e Range 2 with a maximum CPU frequency of 26 MHz All peripheral clocks are also limited to 26 MHz The VCORE can be supplied by the low power regulator the main regulator being switched off The system is then in Low power run mode e Low power run mode with the CPU running at up to 2 MHz Peripherals with independent clock can be clocked by 5116 Low power modes The ultra low power STM32L476xx supports seven low power modes to achieve the best compromise between low power consumption short startup time available peripherals and available wakeup sources DoclD025976 Rev 2 21 213 94 926S20d190d Table 4 STM32L476 modes overview Mode Reg Rer CPU Flash SRAM Clocks DMA amp Peripherals 2 Wakeup source Consumption oe Range 1 All 112 HA MHz Run Yes ON ON Any N A N A Range2 All except FS RNG 100 pA MHz Any LPRun LPR Yes ON except All e
158. e sensing technology is able to detect finger presence near an electrode which is protected from direct touch by a dielectric glass plastic The capacitive variation introduced by the finger or any conductive object is measured using a proven implementation based on a surface charge transfer acquisition principle The touch sensing controller is fully supported by the STMTouch touch sensing firmware library which is free to use and allows touch sensing functionality to be implemented reliably in the end application The main features of the touch sensing controller are the following e Proven and robust surface charge transfer acquisition principle e Supports up to 24 capacitive sensing channels e Up to 3 capacitive sensing channels can be acquired in parallel offering a very good response time e Spread spectrum feature to improve system robustness in noisy environments e Full hardware management of the charge transfer acquisition sequence e Programmable charge transfer frequency Programmable sampling capacitor e Programmable channel I O e Programmable max count value to avoid long acquisition when a channel is faulty e Dedicated end of acquisition and max count error flags with interrupt capability e One sampling capacitor for up to 3 capacitive sensing channels to reduce the system components e Compatible with proximity touchkey linear and rotary touch sensor implementation e Designed to operate with
159. edance allowed for an error below 1 4 of LSB Here N 12 from 12 bit resolution Table 63 Maximum ADC 1 02 RAIN Q Sampling cycle Sampling time ns Resolution 80 80 z Fast channels Slow channels 2 5 31 25 100 N A 6 5 81 25 330 100 12 5 156 25 680 470 24 5 306 25 1500 1200 12 bits 47 5 593 75 2200 1800 92 5 1156 25 4700 3900 247 5 3093 75 12000 10000 640 5 8006 75 39000 33000 2 5 31 25 120 N A 6 5 81 25 390 180 12 5 156 25 820 560 24 5 306 25 1500 1200 10 bits 47 5 593 75 2200 1800 92 5 1156 25 5600 4700 247 5 3093 75 12000 10000 640 5 8006 75 47000 39000 2 5 31 25 180 N A 6 5 81 25 470 270 12 5 156 25 1000 680 24 5 306 25 1800 1500 8 bits 47 5 593 75 2700 2200 92 5 1156 25 6800 5600 247 5 3093 75 15000 12000 640 5 8006 75 50000 50000 148 213 DoclD025976 Rev 2 q STM32L476xx Electrical characteristics Table 63 Maximum ADC RAIN 2 continued Sampling cycle Sampling time ns RAIN max O Resolution 80 MH 80 MH s Fast channels Slow channels 2 5 31 25 220 N A 6 5 81 25 560 330 12 5 156 25 1200 1000 24 5 306 25 2700 2200 6 bits 47 5 593 75 3900 3300 92 5 1156 25 8200 6800 247 5 3093 75 18000 15000 640 5 8006 75 50000 50000 Guaranteed by design not tested in production 2 The I O analog switch voltage booste
160. em clock 80 MHz 17 ps RMS period jitter 30 VCO freq 64 MHz 150 200 Ipp PLL PLL power consumption on VCO freq 96 MHz i 200 260 1 Vpp VCO freq 192 MHz 300 380 VCO freq 344 MHz 520 650 1 Guaranteed by design not tested in production 2 Take care of using the appropriate division factor M to obtain the specified PLL input clock values The M factor is shared between the 3 PLLs q DocID025976 Rev 2 133 213 Electrical characteristics STM32L476xx 6 3 10 Memory characteristics Flash memory The characteristics are given at 40 to 105 C unless otherwise specified Table 50 Flash memory characteristics Symbol Parameter Conditions Typ Max Unit torog 64 bit programming time 81 69 90 76 us row 32 double normal programming 2 61 2 90 rog row word programming time fast programming 1 91 2 12 2 Kbyte normal programming 20 91 23 24 ms prog_Pag programming time fast programming 15 29 16 98 terase Page 2 KB erase time 5 22 02 24 47 bank 512 Kbyte normal programming 5 35 5 95 iprog bank programming time fast programming 3 91 4 35 i Mass erase time two banks 22 13 24 59 ms Average consumption Write mode 3 4 from Erase mode 3 4 i Write mode 7 for 2 us Maximum current peak Erase mo
161. ent points are done at CMOS levels 0 5 x Vpp Refer to Section 6 3 14 I O port characteristics for more details on the input output alternate function characteristics CK SD FS Table 81 SAI characteristics Symbol Parameter Conditions Min Max Unit fMCLK SAI Main clock output 50 MHz Master transmitter 2 7 lt Vpp 3 6 18 5 Voltage Range 1 Master transmitter 1 71 Vpp lt 3 6 12 5 Voltage Range 1 Master receiver Voltage Range 1 I aa fox SAI clock frequency Slave transmitter MHz 2 7 lt Vpp lt 3 6 22 5 Voltage Range 1 Slave transmitter 1 71 lt Vpp lt 3 6 14 5 Voltage Range 1 Slave receiver Voltage Range 1 I 29 Voltage Range 2 12 5 Master mode _ 22 2 7 lt Vpp lt 3 6 tWFS FS valid time ns Master mode 40 1 71 lt Vpp lt 3 6 th FS FS hold time Master mode 10 ns tsu FS FS setup time Slave mode 1 ns th FS FS hold time Slave mode 2 ns tsu SD MR Master receiver 2 5 Data input setup time ns tsu SD_B SR Slave receiver 3 0 A MR Master receiver 8 Data input hold time ns th SD_B_SR Slave receiver 4 DoclD025976 Rev 2 171 213 Electrical characteristics STM32L476xx Table 81 SAI characteristics continued Symbol Parameter Conditions Min Max Unit Slave transmitter after enable ed
162. er modes 21 3 9 5 Resetiriode raars serae e ak Rr Ree S deu Ratte 28 3 9 6 VBAT operation 28 3 10 Interconnect 29 3 11 Clocks and startup 31 3 12 General purpose inputs outputs 34 3 13 Direct memory access controller 34 3 14 Interrupts and events 35 3 14 1 Nested vectored interrupt controller 35 3 14 2 Extended interrupt event controller EXTI 35 3 15 Analog to digital converter 36 3 15 1 Temperature 36 3 15 2 Internal voltage reference 37 3 15 3 VBAT battery voltage monitoring 37 3 16 Digital to analog converter 37 2 213 DoclD025976 Rev 2 Ly STM32L476xx Contents 3 17 Voltage reference buffer 38 4 18 Comparators COMP 38 3 19 Operational amplifier OPAMP 39 3 20 Touch sensing controller TSC 39 3 21 Liquid crystal display con
163. ge An external capacitor must be connected to the VLCD pin to decouple this converter Table 73 LCD controller characteristics 7 Symbol Parameter Conditions Min Typ Max Unit Vicp LCD external voltage 3 6 Vicpo LCD internal reference voltage 0 2 62 Vi cp LCD internal reference voltage 1 2 76 Vicp2 LCD internal reference voltage 2 2 89 LCD internal reference voltage 3 3 04 V Vi LCD internal reference voltage 4 3 19 cps LCD internal reference voltage 5 3 32 gt Vi cpe LCD internal reference voltage 6 3 46 Vi cpz LCD internal reference voltage 7 3 62 Buffer OFF 0 2 2 0 is LCD_CR register 7 V external capacitance gt Buf er z BUFEN 1 is LCD_CR register Supply current from Vpp at Buffer OFF _ 3 _ Vpp 2 2 V BUFEN 0 is LCD_CR register Supply current from Vpp at Buffer OFF _ 15 _ Vpp 3 0 V BUFEN 0 is LCD_CR register Buffer OFF _ 0 5 E BUFFEN 0 PON 0 Buffer _ 0 6 _ Supply current from V cp BUFFEN 1 1 2 Bias UA VLCD Buffer ON 08 BUFFEN 1 1 3 Bias I I Buffer ON _ 1 _ BUFFEN 1 1 4 Bias Run Total High Resistor value for Low drive resistive network 5 5 MQ Rin Total Low Resistor value for High drive resistive network 240 V44 Segment Common highest level voltage V34 Segment Common 3 4 level v
164. ge I 22 2 7 lt Vpp lt 3 6 twsp_B st Data output valid time ns nm Slave transmitter after enable edge _ 34 1 71 lt Vpp 3 6 sr Data output hold time Slave transmitter after enable edge 10 ns Master transmitter after enable edge I 27 2 7 lt Vpp lt 3 6 tsp A Mr Data output valid time ns Master transmitter after enable edge E 40 1 71 lt Vpp 53 6 tnsp A Mr Data output hold time Master transmitter after enable edge 10 ns 1 Data based on characterization results not tested in production 2 clock frequency must be at least twice SAI clock frequency Figure 31 SAI master timing waveforms output SAI SD X transmit SAI SD X receive FS 9 sus _f _ SAI FS X C a tv SD Me tsu SD_MR gt lt gt th FS gt th SD_MT MS32771V1 172 213 DocID025976 Rev 2 q STM32L476xx Electrical characteristics Figure 32 SAI slave timing waveforms fsck SAI_SCK_X tw CKH_ x P9 tw CKL X i 4 SAI FS X input tsu FS 4 SD ST ST transmit tsu SD_SR lt v lt hisD SR receive MS32772N1 SDMMC characteristics Unless otherwise specified the parameters given in Table 82 for SDIO are derived from tests performed under the ambient temperature fpc frequency and Vpp supply voltage conditions
165. ge on TT_xx pins Vss 0 3 4 0 V Input voltage on BOOTO pin Vss 9 0 Input voltage on any other pins Vss 0 3 4 0 Variations between different Vppx power AVpxl pins of the same domain I m Variations between all the different ground MssxVssl ins 9 50 1 All main power Vppio2 VppusB Vi cp Vear and ground Vss Vssa pins must always be connected to the external power supply in the permitted range Ly DoclD025976 Rev 2 93 213 Electrical characteristics STM32L476xx 2 Vin maximum must always be respected Refer to Table 19 Current characteristics for the maximum allowed injected current values This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table 4 To sustain a voltage higher than 4 V the internal pull up pull down resistors must be disabled Table 19 Current characteristics Symbol Ratings Max Unit gt Total current into sum of all Vpp power lines source 150 lVas Total current out of sum of all Vss ground lines sink 150 IV Maximum current into each Vpp power pin source 1 100 DD PIN DD IVss PIN Maximum current out of each Vas ground pin sink 100 Output current sunk by any I O and control pin except FT f 20 lio PIN Output current sunk by any FT f pin 20 Output current sourced by any I O and control pin 20 mA I Total output current sunk
166. gh 0 tw BL_NE FMC_NEx low to FMC_BL valid 2 th BL_NOE FMC_BL hold time after FMC_NOE high 0 tsu Data_NE Data to high setup time 1 tsu Data NOE Data to high setup time 0 5 th Data Data hold time after NOE high 0 th Data_NE Data hold time after FMC_NEx high 0 tvNADV_NE FMC_NEx low to FMC_NADV low 1 tw NADV FMC_NADV low time 0 5 CL 30 pF 2 Based on characterization not tested in production Table 86 Asynchronous non multiplexed SRAM PSRAM NOR read NWAIT timings Symbol Parameter Min Max Unit low time 0 5 0 5 tw NOE FMC_NWE low time 5 0 5 5 0 5 twnwait FMC_NWAIT low time 0 5 ns tsu NWAIT_NE FMC_NWAIT valid before FMC_NEx high 5Tucik 2 NEx hold time after NWAIT invalid 4 1 30 2 Based characterization not tested production Ly DoclD025976 Rev 2 177 213 Electrical characteristics STM32L476xx 178 213 Figure 36 Asynchronous non multiplexed SRAM PSRAM NOR write waveforms FMC_NEx FMC_NOE FMC_NWE A 25 0 NBL 1 0 FMC D 15 0 NADV 1 NWAIT tv NADV NE tw NADV tw NE th NE_NWAIT tsu NWAIT_NE th NE_NWE MS32754V1 Table 87 Asynchronous non multiplexed SRAM PSRAM NOR write timings 1 2
167. given only as design guidelines and are not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range where 95 of the devices have an error less than or equal to the value indicated mean 2o Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 11 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 12 Figure 11 Pin loading conditions Figure 12 Pin input voltage MCU pin MCU pin C 50 pF MS19210V1 MS19211V1 DoclD025976 Rev 2 91 213 Electrical characteristics STM32L476xx 6 1 6 Caution 92 213 Power supply scheme Figure 13 Power supply scheme 1 55 3 6 V n x 100 nF 1 x 4 7 UF m x100 nF 10 nF 1 UF 4 7 uF Em om Power switch Backup circuitry LSE RTC Backup registers Vcore nx VDD SS Regulator Vppiot I ae OUT E E Kernel logic IO M GPIOs e logi CPU Digital IN ogic amp Memories gt 5 I nx VSS gt EA m x VDDIO2 Vppio2 I OUT
168. hen 2 2 4 V No oversampling 150 213 DocID025976 Rev 2 The analog switch voltage booster is enable when Vppa lt 2 4 V BOOSTEN 1 the SYSCFG_CFGR1 when q STM32L476xx Electrical characteristics Figure 23 ADC accuracy characteristics 4093 4094 4095 4096 1 Example of an actual transfer curve 2 The ideal transfer curve 3 End point correlation line Total Unajusted Error maximum deviation between the actual and ideal transfer curves Eo Offset Error maximum deviation between the first actual transition and the first ideal one Ec Gain Error deviation between the last ideal transition and the last actual one Ep Differential Linearity Error maximum deviation between actual steps and the ideal ones EL 7 Integral Linearity Error maximum deviation between any actual transition and the end point correlation line VDDA MS19880V2 Figure 24 Typical connection diagram using the ADC Sample and hold ADC con verter R ADC 12 bit converter MS33900V1 1 Refer to Table 62 ADC characteristics for the values of Rain and 2 represents the capacitance of the PCB dependent on soldering and PCB layout quality plus the pad capacitance roughly 7 pF A high value will downgrade conversion accuracy To remedy this fapc should be reduced General PCB design guidelines P
169. heral and peripheral to peripheral transfers e Access to Flash SRAM APB and AHB peripherals as source and destination e Programmable number of data to be transferred up to 65536 Table 7 DMA implementation DMA features DMA1 DMA2 Number of regular channels 7 7 q DocID025976 Rev 2 STM32L476xx Functional overview 3 14 3 14 1 3 14 2 q Interrupts and events Nested vectored interrupt controller NVIC The devices embed a nested vectored interrupt controller able to manage 16 priority levels and handle up to 81 maskable interrupt channels plus the 16 interrupt lines of the Cortex 4 benefits the following e Closely coupled NVIC gives low latency interrupt processing e interrupt entry vector table address passed directly to the core e Allows early processing of interrupts e Processing of late arriving higher priority interrupts e Support for tail chaining e Processor state automatically saved e Interrupt entry restored on interrupt exit with no instruction overhead The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency Extended interrupt event controller The extended interrupt event controller consists of 36 edge detector lines used to generate interrupt event requests and wake up the system from Stop mode Each external line can be independently configured to select the trigger event rising edg
170. independently enable length single dual quad communication Instruction phase Address phase Alternate bytes phase Dummy cycles phase Data phase Integrated FIFO for reception and transmission 8 16 and 32 bit data accesses are allowed DMA channel for indirect mode operations Programmable masking for external flash flag management Timeout management Interrupt generation on FIFO threshold timeout status match operation complete and access error q DocID025976 Rev 2 STM32L476xx Functional overview 3 37 3 37 1 3 37 2 q Development support Serial wire JTAG debug port SWJ DP The ARM SWJ DP interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target Debug is performed using 2 pins only instead of 5 required by the JTAG JTAG pins could be re use as GPIO with alternate function the JTAG TMS and TCK pins are shared with SWDIO and SWCLK respectively and a specific sequence on the TMS pin is used to Switch between JTAG DP and SW DP Embedded Trace Macrocell The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32L476xx through a small number of ETM pins to an external hardware trace port analyzer TPA device Real time instruction and data flow activity be
171. ion the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only To improve the accuracy of the temperature sensor measurement each device is individually factory calibrated by ST The temperature sensor factory calibration data are stored by ST in the system memory area accessible in read only mode Table 8 Temperature sensor calibration values Calibration value name Description Memory address TS ADC raw data acquired at a TS_CAL1 temperature of 30 C 5 C 0x1FFF 75A8 0x1FFF 75A9 VREF 3 0V 10 TS ADC raw data acquired TS_CAL2 temperature of 110 C 5 0x1FFF 75CA 0x1FFF 75CB VppA Vrer 3 0 V 10 mV Internal voltage reference The internal voltage reference VREFINT provides a stable bandgap voltage output for the ADC Comparators VREFINT is internally connected to the ADC1 INO input channel The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area It is accessible in read only mode Table 9 Internal voltage reference calibration values Calibration value name Description Memory address Raw data acquired at a VREFINT temperature of 30 C x 5 C Ox1FFF 75AA Ox1FFF 75AB VppA Vrer 3 0 V 10 mV battery voltage monitoring This embedded hardware feature allows the applic
172. l resonator or oscillator LSE e internal low power RC oscillator LSI with typical frequency of 32 kHz e high speed external clock HSE divided by 32 The RTC is functional in VBAT mode and in all low power modes when it is clocked by the LSE When clocked by the LSI the RTC is not functional in VBAT mode but is functional in all low power modes except Shutdown mode All RTC events Alarm WakeUp Timer Timestamp or Tamper can generate an interrupt and wakeup the device from the low power modes DoclD025976 Rev 2 45 213 Functional overview STM32L476xx 3 26 Inter integrated circuit interface 2 The device embeds 3 2 Refer to Table 11 I2C implementation for the features implementation The 12 bus interface handles communications between the microcontroller and the serial 2 bus It controls all 2 bus specific sequencing protocol arbitration and timing The I2C peripheral supports e l C bus specification and user manual rev 5 compatibility Slave and master modes multimaster capability Standard mode Sm with a bitrate up to 100 kbit s Fast mode Fm with a bitrate up to 400 kbit s Fast mode Plus Fm with a bitrate up to 1 Mbit s and 20 mA output drive I Os T bit and 10 bit addressing mode multiple 7 bit slave addresses Programmable setup and hold times Optional clock stretching e System Management Bus SMBus specification rev 2 0 compatibility
173. l voltage for an FT 10 mA pin in FM mode FT with f 2451004 0 4 option DDIOx lio 2mA _ 0 4 1 62 V 2 Vppiox 2 1 08 V 1 The ljo current sourced or sunk by the device must always respect the absolute maximum rating specified in Table 18 Voltage characteristics and the sum of the currents sourced or sunk all the I Os I O ports and control pins must always respect the absolute maximum ratings 2 Vppiox represents VDD or 2 TTL and CMOS outputs are compatible with standards JESD36 and JESD52 4 Guaranteed by design not tested in production q Input output AC characteristics The definition and values of input output AC characteristics are given in Figure 21 and Table 59 respectively Unless otherwise specified the parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in Table 21 General operating conditions DoclD025976 Rev 2 141 213 Electrical characteristics STM32L476xx Table 59 I O AC characteristics Speed Symbol Parameter Conditions Min Max Unit 50 pF 2 7 lt lt 3 6 V 5 C 50 pF 1 62 lt lt 2 7 V 1 frequency ee ee i MHz C 10 pF 2 7 V lt VppioxS3 6 V 10 C 10 pF 1 62 VXVppjoX2 7 V 1 5 C
174. lculation unit CRC The CRC cyclic redundancy check calculation unit is used to get a CRC code using a configurable generator polynomial value and size Among other applications CRC based techniques are used to verify data transmission or storage integrity In the scope of the EN IEC 60335 1 standard they offer a means of verifying the Flash memory integrity The CRC calculation unit helps compute a signature of the software during runtime to be compared with a reference signature generated at link time and stored at a given memory location Power supply management Power supply schemes e Vpp 1 71 to 3 6 V external power supply for I Os the internal regulator and the system analog such as reset power management and internal clocks It is provided externally through Vpp pins e VppA 1 62 V ADCs COMPs 1 8 DACs OPAMPs to 3 6 V external analog power supply for ADCs DACs OPAMPs Comparators and Voltage reference buffer The Vppa voltage level is independent from the Vpp voltage e VppusB 3 0 to 3 6 V external independent power supply for USB transceivers The Vppuss Voltage level is independent from the Vpp voltage e Vppio2 1 08 to 3 6 V external power supply for 14 I Os PG 15 2 The Vppio2 voltage level is independent from the Vpp voltage e 2 5 to 3 6 V the LCD controller can be powered either externally through VLCD pin or internally from an internal voltage generated by the embedded step up con
175. le shot or continuous discontinuous sequencer based scan mode 2 groups of analog signals conversions can be programmed to differentiate background and high priority real time conversions Handles two ADC converters for dual mode operation simultaneous or interleaved sampling modes Each ADC support multiple trigger inputs for synchronization with on chip timers and external signals Results stored into 3 data register or in RAM with DMA controller support Data pre processing left right alignment and per channel offset compensation Built in oversampling unit for enhanced SNR Channel wise programmable sampling time Three analog watchdog for automatic voltage monitoring generating interrupts and trigger for selected timers A Hardware assistant to prepare the context of the injected channels to allow fast context switching Temperature sensor The temperature sensor TS generates a voltage VSENSE that varies linearly with temperature The temperature sensor is internally connected to the ADC1 IN17 and ADC3_IN17 input channels which is used to convert the sensor output voltage into a digital value The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement As the offset of the temperature sensor varies DoclD025976 Rev 2 Ly STM32L476xx Functional overview 3 15 2 3 15 3 3 16 q from chip to chip due to process variat
176. llowing configuration Output speed is set to OSPEEDRy 1 0 11 e Capacitive load C 20 pF e Measurement points are done at CMOS levels 0 5 x Vpp Refer to Section 6 3 14 I O port characteristics for more details on the input output alternate function characteristics Table 79 Quad SPI characteristics SDR mode Symbol Parameter Conditions Min Typ Max Unit 1 71 lt lt 3 6 40 Voltage Range 1 F 2 lt lt 3 6 Quad SPI clock frequency DD 48 MHz 1 t ck Voltage Range 1 1 71 lt Vpp lt 3 6 26 Voltage Range 2 t i tick 2 2 t c lt y2 w CKH Quad SPI clock high and f 48 MHz presc 0 CK CK low time AFBCLK tw CKL 2 2 2 ts IN Data input setup time 4 ns Data input hold time 6 5 Voltage Range 1 and 2 tv OUT Data output valid time 2 5 5 tour Data output hold time 1 5 1 Data based on characterization results not tested in production Table 80 QUADSPI characteristics DDR mode Symbol Parameter Conditions Min Typ Max Unit 1 71 lt Vpp lt 3 6 40 Voltage Range 1 F 2 lt V lt 3 6 CK Quad SPI clock DD _ _ 48 MHz frequency Voltage Range 1 1 71 lt Vpp lt 3 6 26 Voltage Range 2 Ly DoclD025976 Rev 2 169 213 Electrical characteristics STM32L476xx Table 80 QUADSPI characteristics in DDR mode continued Symbol Para
177. lowing e Three segments be protected and defined thanks to the Firewall registers Code segment located in Flash or SRAM1 if defined as executable protected area Non volatile data segment located in Flash Volatile data segment located SRAM1 e start address and the length of each segments are configurable code segment up to 1024 Kbyte with granularity of 256 bytes Non volatile data segment up to 1024 Kbyte with granularity of 256 bytes Volatile data segment up to 96 Kbyte with a granularity of 64 bytes e Specific mechanism implemented to open the Firewall to get access to the protected areas call gate entry sequence e Volatile data segment can be shared or not with the non protected code e Volatile data segment can be executed or not depending on the Firewall configuration The Flash readout protection must be set to level 2 in order to reach the expected level of protection q DocID025976 Rev 2 STM32L476xx Functional overview 3 7 3 8 3 9 3 9 1 Note Note q Boot modes At startup pin and BOOT1 option bit are used to select one of three boot options e Boot from user Flash e Boot from system memory e Boot from embedded SRAM The boot loader is located in system memory It is used to reprogram the Flash memory by using USART 2 SPI CAN and USB OTG FS in Device mode through DFU device firmware upgrade Cyclic redundancy check ca
178. manufacturer JFVNY with two 6 8 pF loading capacitors 9 TZEINLS 291139919 ELC OLL A8Y 926S20d190d Table 34 Current consumption in Stop 1 mode with main regulator Conditions TYP MAX Symbol Parameter Unit Vpp 25 55 85 C 105 125 C 25 C 55 C 85 C 105 125 C Supply 18 V 108 132 217 356 631 153 213 426 773 1461 gurent fn 24V 110 134 219 358 634 158 218 431 778 1468 Ipp Stop 1 Main regulator ON HA Stop 1 mode 3V 111 135 220 360 637 161 221 433 783 1476 Pro giganla 36V 113 137 222 363 642 166 226 438 7912 1488 1 Based on characterization not tested in production unless otherwise specified 2 Tested in production Table 35 Current consumption in Stop 2 mode Conditions TYP 1 Symbol Parameter Unit Vpp 25 C 55 85 C 105 C 125 25 C 55 85 C 105 125 1 8 V 1 14 3 77 14 7 34 7 77 2 7 9 37 87 193 2 4V 1 15 3 86 15 35 5 79 1 2 7 10 38 89 198 LCD disabled 3V 1 18 3 97 15 4 36 4 81 3 2 8 10 39 91 203 Supply currentin 36V 126 411 16 38 85 1 3 0 10 40 952 213 Ipp Stop 2 Stop 2 mode HA RTC disabled 1 8V 1 43 3 98 15 35 773 32 10 38 88 193 LCD enabled 2 24V 149 407 153 358 794 32 10 38 90 199 clocked by LSI
179. max 175 272 447 Using the values obtained in Table 106 T is calculated as follows For LQFP64 45 C W 82 45 C W x 447 mW 82 20 115 102 115 C This is within the range of the suffix 6 version parts 40 lt T lt 105 C see Section 8 Part numbering In this case parts must be ordered at least with the temperature range suffix 6 see Part numbering With this given we can find the allowed for a given device temperature range order code suffix 6 or 7 Suffix 6 T jmax 45 C W x 447 mW 105 20 115 84 885 C Suffix 7 T jmax 45 C W x 447 mW 125 20 115 104 885 C Example 2 High temperature application Using the same rules it is possible to address applications that run at high ambient temperatures with a low dissipation as long as junction temperature remains within the specified range Assuming the following application conditions Maximum ambient temperature 100 C measured according to JESD51 2 Ippmax 20 mA Vpp 3 5 V maximum 20 I Os used at the same time in output at low level with Io 8 mA Vor 2 0 4 V Pintmax 20 mA x 3 5 V 70 mW Piomax 20 x 8 mA x 0 4 V 64 mW This gives 70 mW and Piomax 64 mW Ppmax 70 64 134 mW Thus Ppmax 134 mW DoclD025976 Rev 2 209 213 Package information STM32L476xx 210 213 Using the
180. memory access controller DMA The device embeds 2 DMAs Refer to Table 7 DMA implementation for the features implementation Direct memory access DMA is used in order to provide high speed data transfer between peripherals and memory as well as memory to memory Data can be quickly moved by DMA without any CPU actions This keeps CPU resources free for other operations The two DMA controllers have 14 channels in total each dedicated to managing memory access requests from one or more peripherals Each has an arbiter for handling the priority between DMA requests The DMA supports e 14 independently configurable channels requests e Each channel is connected to dedicated hardware DMA requests software trigger is also supported on each channel This configuration is done by software e Priorities between requests from channels of one DMA are software programmable 4 levels consisting of very high high medium low or hardware in case of equality request 1 has priority over request 2 etc e Independent source and destination transfer size byte half word word emulating packing and unpacking Source destination addresses must be aligned on the data size e Support for circular buffer management 3 event flags DMA Half Transfer DMA Transfer complete and DMA Transfer Error logically ORed together in a single interrupt request for each channel e Memory to memory transfer Peripheral to memory and memory to perip
181. meter Conditions Min Typ Max Unit MO Quad high 48 MHz presc 0 D tw CKL ticky 2 2 2 Data input setup time 3 5 SAUNE S Voltage Range 1 and 2 nr IN Data input hold time 6 5 He 5 a Voltage Range 1 8 9 5 tytoUTYytvr OUT ata output valid time Voltage Range 2 15 19 Voltage Range 1 6 thr ouT Data output hold time F 1 Data based on characterization results not tested in production Figure 29 Quad SPI timing diagram SDR mode f wecken e x e Clock k 1 I tdg gt than MSv36878V1 Figure 30 Quad SPI timing diagram DDR mode tick tw CKH tw CKL e t 4 ff HF Mf NK x EE itout n our MSv36879V1 q 170 213 DocID025976 Rev 2 STM32L476xx Electrical characteristics SAI characteristics Unless otherwise specified the parameters given in Table 81 for SAI are derived from tests performed under the ambient temperature fpc frequency and Vpp supply voltage conditions summarized in Table 21 General operating conditions with the following configuration Output speed is set to OSPEEDRy 1 0 10 e Capacitive load 30 pF e Measurem
182. mings 177 Asynchronous non multiplexed SRAM PSRAM NOR read NWAIT timings 177 Asynchronous non multiplexed SRAM PSRAM NOR write timings 178 Asynchronous non multiplexed SRAM PSRAM NOR write NWAIT timings 179 Asynchronous multiplexed PSRAM NOR read timings 180 Asynchronous multiplexed PSRAM NOR read NWAIT timings 180 Asynchronous multiplexed PSRAM NOR write timings 182 Asynchronous multiplexed PSRAM NOR write NWAIT timings 182 Synchronous multiplexed NOR PSRAM read timings 184 DoclD025976 Rev 2 7 213 List of tables STM32L476xx Table 94 Table 95 Table 96 Table 97 Table 98 Table 99 Table 100 Table 101 Table 102 Table 103 Table 104 Table 105 Table 106 Table 107 Table 108 8 213 Synchronous multiplexed PSRAM write timings 186 Synchronous non multiplexed NOR PSRAM read 187 Synchronous non multiplexed PSRAM write 1 06 189 Switching characteristics for NAND Flash read 191 Switching characteristics for Flash write 191 LQFP144 144 pin 20 x 20 mm low profile quad flat package mechanical data u u s uuu puru ee ER ERR AIR
183. n triggered by software trigger internal timers external events start of conversion synchronously with first digital filter module DFSDMO analog watchdog feature low value and high value data threshold registers dedicated configurable Sincx digital filter order 1 3 oversampling ratio 1 32 input from final output data or from selected input digital serial channels continuous monitoring independently from standard conversion short circuit detector to detect saturated analog input values bottom and top range up to 8 bit counter to detect 1 256 consecutive 0 or 175 on serial data stream monitoring continuously each input serial channel break signal generation on analog watchdog event or on short circuit detector event extremes detector storage of minimum and maximum values of final conversion data refreshed by software DMA capability to read the final conversion data interrupts end of conversion overrun analog watchdog short circuit input serial channel clock absence regular or injected conversions regular conversions can be requested at any time or even in continuous mode without having any impact on the timing of injected conversions injected conversions for precise timing and with high conversion priority DoclD025976 Rev 2 41 213 Functional overview STM32L476xx 3 23 Random number ge
184. n vary significantly with the crystal manufacturer Note For information on selecting the crystal refer to the application note AN2867 Oscillator design guide for ST microcontrollers available from the ST website www st com Figure 18 Typical application with a 32 768 kHz crystal Resonator with integrated capacitors Drive programmable amplifier 2 32 768 kHz resonator MS30253V1 Note An external resistor is not required between OSC32 IN and OSC32 OUT and it is forbidden to add one ky DocID025976 Rev 2 127 213 Electrical characteristics STM32L476xx 6 3 8 Internal clock source characteristics The parameters given in Table 46 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 21 General operating conditions The provided curves are characterization results not tested in production High speed internal HSI16 RC oscillator Table 46 HSI16 oscillator characteristics Symbol Parameter Conditions Min Typ Unit 516 5116 Frequency Vpp 3 0 V 30 16 0 05 2 MHz Trimming code is not a multiple of 64 e 0 4 TRIM HSI16 user trimming step Trimming code is a 4 6 8 multiple of 64 DuCy HSI16 Duty Cycle 45 55 Vpp 5 0 V 0 8 TBD 96 1 6 oscillator frequency 10 to 85 C drift over temperature Vpp 3 0 V 40 to 125 C Atemp HSI16 0 9 1 8 TBD
185. nerator RNG All devices embed RNG that delivers 32 bit random numbers generated by an integrated analog circuit 3 24 Timers and watchdogs The STM32L476 includes two advanced control timers up to nine general purpose timers two basic timers two low power timers two watchdog timers and a SysTick timer The table below compares the features of the advanced control general purpose and basic timers Table 10 Timer feature comparison Counter Counter Capturel Complementary Timer type Timer request compare resolution type factor 5 outputs generation channels Any integer TIM1 TIM8 16 bit He 2 between 1 Yes 4 3 P and 65536 Any integer wasa TIM2 TIM5 32 bit ye bal between 1 Yes 4 No Rae P and 65536 Any integer 4 16 bit js us between 1 Yes 4 No purp P and 65536 Any integer 2 15 16 bit Up between 1 Yes 2 1 purp and 65536 Any integer 2 16 TIM17 16 bit between 1 Yes 1 1 65536 Any integer Basic TIM6 TIM7 16 bit Up between 1 Yes 0 No and 65536 3 24 1 Advanced control timer TIM1 TIM8 42 213 The advanced control timer can each be seen as a three phase PWM multiplexed on 6 channels They have complementary PWM outputs with programmable inserted dead times They can also be seen as complete general purpose timers The 4 independent channels can be used for e Inputcapture e Output compare e PWM generation edge or center aligned mode
186. ns functions iti ACANNA Functions directly selected enabled through peripheral registers functions 1 The related I O structures in Table 14 FT f FT fa FT fl FT fla Ly DoclD025976 Rev 2 57 213 Pinouts description STM32L476xx The related I O structures in Table 14 are FT fl FT lu The related I O structures in Table 14 FT lu The related structures in Table 14 FT a FT la FT fa FT fla TT a TT la The related I O structures in Table 14 are FT s FT fs meom Table 14 STM32L476xx pin definitions Pin Number Pin functions 2 9 i 5 5 5 5 lt Alternate functions Additional m reset gt L7 3 functions oG zg dg G u Gc 12 33 3 4 a z TRACECK TIM3_ETR TSC_G7_101 1 B2 1 PE2 LCD SEG38 A23 x SAI1_MCLK_A EVENTOUT TRACEDO TIM3_CH1 TSC G7 102 VO LCD_SEG39 19 I SAI SD B EVENTOUT TRACED1 TIM3 CH2 DFSDM DATING izo 3 B1 3 PES EL TSC G7 103 A20 SAI1 FS A EVENTOUT TRACED2 TIM3 CH3 DFSDM_CKIN3 PES m ET TSC G7 104 21 i SAI1 SCK A EVENTOUT TRACEDS TIM3 RTC _ 5 021 5 PE6 FMC_A22 SAI1_SD_A TAMP3 EVENTOUT WKUP3 1 9 9 6
187. number I I _ _ I I _ _ I generator RNG CRC calculation _ 7 s _ _ _ unit 5 GPIOs O O o UU pinsi 10 10 1 Legend Y Yes Enable O Optional Disable by default be enabled software Not available 2 The Flash can be configured in power down mode By default it is not in power down mode 3 The SRAM clock can be gated on or off 4 SRAM2 content is preserved when the bit RRS is set in PWR register 5 Some peripherals with wakeup from Stop capability can request HSI16 to be enabled In this case HSI16 is woken up the peripheral and only feeds the peripheral which requested it 5116 is automatically put off when the peripheral does not need it anymore 6 UART and LPUART reception is functional in Stop mode and generates a wakeup interrupt on Start address match or received frame event 7 2C address detection is functional in Stop mode and generates a wakeup interrupt in case of address match 8 Voltage scaling Range 1 only 9 I Os can be configured with internal pull up pull down or floating in Standby mode 10 The with wakeup from Standby Shutdown capability are PC13 6 2 PC5 11 l Os can be configured with internal pull up pull down or floating in Shutdown mode but the configuration is lost when exiting the Shutdown mode 3 9 5 Reset mode In order to improve the consumption under reset the
188. oclD025976 Rev 2 q STM32L476xx Electrical characteristics In all timing tables the is the HCLK clock period Figure 39 Synchronous multiplexed NOR PSRAM read timings tw CLK 9 tw CLk BUSTURN 0 may FMC_CLK 4 2 i I 1 Data latency 0 ta CLKL NExL td CLKH NExH 1 1 1 _ i 1 1 1 ta CLKL NADVL ta CLKL NADVH 1 1 1 1 1 FMC NADV l td CUKL AV td CUKH AIV FMC A 25 16 ta CLKL NOEL td CLKH NOEH FMC_NOE 1 td CLKL ADIV th CLKH ADV tsu ADV CLKH ta CLKL ADV FMC AD 15 0 FMC NWAIT WAITCFG 1b WAITPOL Ob a 5 2 A i A 2 5 gt NWAIT WAITCFG 0b WAITPOL 0b 1 1 1 tsu NWAITV CLKH CLKH NWAITV MS32757V1 q DocID025976 Rev 2 183 213 Electrical characteristics STM32L476xx 184 213 Table 93 Synchronous multiplexed NOR PSRAM read timings 1 2 Symbol Parameter Min Max Unit tw CLk FMC_CLK period 2 1 taCLKL NExL FMC_CLK low to _ low 0 2 2 FMC_CLK high to NEx high 0 2 0 5 ta CLKL NADVL FMC_CLK low to NADV low 2 5 taCLKL NADVH FMC_CLK low to F
189. odes code with data processing running from 1 103 Typical current consumption in Run and Low power run modes with different codes running from Flash ART enable Cache ON Prefetch OFF 104 Typical current consumption in Run and Low power run modes with different codes running from Flash ART disable 105 Typical current consumption in Run and Low power run modes with different codes running from 1 105 Current consumption in Sleep and Low power sleep modes Flash ON 106 Current consumption in Low power sleep modes Flash in power down 107 Current consumption in Stop 1 108 Current consumption in Stop 1 mode with main 110 Current consumption in Stop 2 110 Current consumption in Standby mode 112 Current consumption in Shutdown 113 Current consumption VBAT 115 Peripheral current consumption 117 Low power mode wakeup timings 120 Regulator modes transition
190. ol Parameter Min Max Unit Tw NWE NWE low width 1 4Tucikt1 Tv NWE D FMC_NWE low to FMC_D 15 0 valid 2 5 Th NWE D FMC_NWE high to FMC_D 15 0 invalid 4 ns Ta D NWE D 15 0 valid before NWE high 5 nwe valid before low 3THcLKt1 Th NWE ALE FMC_NWE high to FMC_ALE invalid 2Tucuc2 1 CL 30 pF 2 Based on characterization not tested in production DoclD025976 Rev 2 191 213 Package information STM32L476xx 7 7 1 192 213 Package information In order to meet environmental requirements ST offers these devices in different grades of depending their level of environmental compliance specifications grade definitions and product status are available at www st com is an ST trademark LQFP144 package information Figure 47 LQFP144 144 pin 20 x 20 mm low profile quad flat package outline SEATING PLANE 0 25 mm GAUGE PLANE IDENTIFICATION 1A ME V4 1 Drawing is not to scale DoclD025976 Rev 2 Ly STM32L476xx Package information Table 99 LQFP144 144 pin 20 x 20 mm low profile quad flat package mechanical data millimeters
191. oltage 3 4 Vi cp V23 Segment Common 2 3 level voltage 2 3 Vi cp V42 Segment Common 1 2 level voltage 1 2 gt V V13 Segment Common 1 3 level voltage 1 3 Vi ep Segment Common 1 4 level voltage 1 4 Vi Segment Common lowest level voltage 0 14 Vo Ly DoclD025976 Rev 2 163 213 Electrical characteristics STM32L476xx 1 Guaranteed by design not tested in production 2 LCD enabled with 3 V internal step up active 1 8 duty 1 4 bias division ratio 64 all pixels active LCD connected 6 3 25 Timer characteristics The parameters given in the following tables are guaranteed by design Refer to Section 6 3 14 port characteristics for details on the input output alternate function characteristics output compare input capture external clock PWM output Table 74 TIMx characteristics Symbol Parameter Conditions Min Max Unit m 1 trIMxCLK tres tim Timer resolution time fTrIMxCLK 80 MHz 12 5 ns 4 external clock 0 2 MHz EXT frequency on CH1 to CH4 frIMxCLK 80 MHz 0 40 MHz TIMx except TIM2 16 Resp Timer resolution and 5 bit TIM2 and 5 32 1 16 bit counter clock 1 65536 trIMxCLK COUNTER i period frIMxCLK 80 MHz 0 0125 819 2 us t Maximum possible count E E 65536 x 65536 trIMxCLK MAX COUNT wi with 32 bit counter
192. on S 9 88 destination 9 0 9 50 0 5 S 6 3 TIMx Timers synchronization or chaining Y Y ADCx DACx Conversion triggers Y Y Y Y us DFSDM DMA Memory to memory transfer trigger Y Y Y COMPx Comparator output blanking Y Y I Y Y I TIM1 8 Timer input channel trigger break from y y ylyl 2 3 analog signals comparison COMPx LPTIMERx Low power timer triggered by analog y yl ylyly i signals comparison ADCx TIM1 8 Timer triggered by analog watchdog Y Y Y Y TIM16 Timer input channel from RTC events Y Y I Y Y I RTC i LPTIMERx Low power timer triggered by RTC alarms y yl ylyly d or tampers All clocks sources internal TIM2 Clock source used as input channel for vivivivi i and external TIM15 16 17 RC measurement and trimming USB TIM2 Timer triggered by USB SOF Y Y CSS CPU hard fault RAM parity error Flash memory ECC error TIM1 8 COMPx break Y Y Y 15 16 17 PVD DFSDM analog watchdog short circuit detection DoclD025976 Rev 2 29 213 Functional overview STM32L476xx Table 6 STM32L476xx peripherals interconnect matrix continued s 5 3 2 Interconnect source Interconnect Interconnect action S 9 eg destination cl o 9 9 6 mp TIMx External trigger Y Y Y Y LPTIMERx External trigger Y Y I Y Y Y M GPIO ADCx DACx Conversion extern
193. on unit The memory protection unit MPU is used to manage the CPU accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task This memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory The MPU is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks It is usually managed by an RTOS real time operating system If a program accesses a memory location that is prohibited by the MPU the RTOS can detect it and take action In an RTOS environment the kernel can dynamically update the MPU area setting based on the process to be executed The MPU is optional and can be bypassed for applications that do not need it q DocID025976 Rev 2 STM32L476xx Functional overview 3 4 q Embedded Flash memory STM32L476xx devices feature up to 1 Mbyte of embedded Flash memory available for storing programs and data The Flash memory is divided into two banks allowing read while write operations This feature allows to perform a read operation from one bank while an erase or program operation is performed to the other bank The dual bank boot is also supported Each bank contains 256 pages of 2 Kbyte Flexible protections can be configured thanks to option bytes
194. ore a Quad SPI flash memories interface available on all packages and an extensive range of enhanced I Os and peripherals connected to two APB buses two AHB buses and a 32 bit multi AHB bus matrix The STM32L476xx devices embed several protection mechanisms for embedded Flash memory and SRAM readout protection write protection proprietary code readout protection and Firewall The devices offer up to three fast 12 bit ADCs 5 Msps two comparators two operational amplifiers two DAC channels an internal voltage reference buffer a low power RTC two general purpose 32 bit timer two 16 bit PWM timers dedicated to motor control seven general purpose 16 bit timers and two 16 bit low power timers The devices support four digital filters for external sigma delta modulators DFSDM In addition up to 24 capacitive sensing channels are available The devices also embed an integrated LCD driver 8x40 or 4x44 with internal step up converter They also feature standard and advanced communication interfaces e Three 2 e Three SPIs e Three USARTs two UARTs and one Low Power UART e TwosSAls Serial Audio Interfaces e One SDMMC e One CAN e One USB OTG full speed e One SWPMI Single Wire Protocol Master Interface The STM32L476xx operates in the 40 to 85 105 C junction 40 to 105 125 C junction and 40 to 125 130 C junction temperature ranges from a 1 71 to 3 6 V power supply A comprehensi
195. ow power mode 5 12 Full common Voffset Comparator offset error mode range 5 20 mV No hysteresis 0 Low hysteresis 8 Vhys Comparator hysteresis mV Medium hysteresis 15 High hysteresis 27 Static 400 600 Ultra low With 50 kHz nA power mode 100 mV overdrive 120 square signal Static 5 7 Comparator consumption Medium mode With 50 kHz from VppA 100 mV overdrive 6 square signal HA Static 70 100 High speed With 50 kHz mode 100 mV overdrive 75 square signal 158 213 DocID025976 Rev 2 Ly STM32L476xx Electrical characteristics 1 Data guaranteed by design not tested in production unless otherwise specified 2 Refer to Table 24 Embedded internal voltage reference 3 Data based on characterization not tested in production 6 3 21 Operational amplifiers characteristics Table 69 OPAMP characteristics Symbol Parameter Conditions Min Typ Max Unit Analog supply VppA voltage 2 1 8 3 6 V Common mode I I V Input offset 25 C No Load on output 1 5 VloFFSET voltage mV All voltage Temp 3 Input offset Normal mode 5 4 AVloFFSET e drift ME 9 Low power mode 10 Offset trim step TRIMOFFSETP at low common _ _ 0 8 TBD TRIMLPOFFSETP input voltage 0 1 x VppA mV Offset trim step TRIMO
196. ower supply decoupling should be performed as shown in Figure 13 Power supply scheme The 10 nF capacitor should be ceramic good quality and it should be placed as close as possible to the chip q DocID025976 Rev 2 151 213 Electrical characteristics STM32L476xx 6 3 18 Digital to Analog converter characteristics Table 65 DAC characteristics Symbol Parameter Conditions Min Typ Max Unit Analog supply voltage for VDDA DAC ON 1 8 3 6 VREF Positive reference voltage 1 8 VDDA V V Negative reference _ V REF voltage SSA connected to Vss 5 Resistive load DAC output i kQ buffer ON connected to 25 Ro Output Impedance DAC output buffer OFF 9 6 11 7 13 8 kQ CL DAC output buffer ON 50 pF Capacitive load Sample hold mode 0 1 1 Voltage DAC OUT DAC output buffer ON 0 2 m VDAC OUT output V DAC output buffer OFF 0 VREF 0 5 LSB 1 7 3 Settling time full scale for Normal mode a 12 bit code transition DAC output 1 LSB 1 6 2 9 between the lowest and buffer ON 2 LSB 1 55 2 85 the highest input codes CL lt 50 pF tSETTLING when DAC OUT reaches RL gt 5kO 4 LSB I 1 48 2 8 PS final value 0 5LSB 8 LSB 1 4 2 75 1 LSB 2 LSB 4 LSB 8 LSB Normal mode DAC output buffer s 2 25 OFF 1LSB CL 10 pF Wakeup time from off state Normal mode DAC
197. p to 8 MHz Shutdown mode The Shutdown mode allows to achieve the lowest power consumption The internal regulator is switched off so that the VCORE domain is powered off The PLL the HSI16 the MSI the LSI and the HSE oscillators are also switched off The RTC can remain active Shutdown mode with RTC Shutdown mode without RTC The BOR is not available in Shutdown mode No power voltage monitoring is possible in this mode therefore the switch to Backup domain is not supported SRAM1 SRAM2 and register contents are lost except for registers in the Backup domain The device exits Shutdown mode when an external reset NRST pin a WKUP pin event configurable rising or falling edge or an RTC event occurs alarm periodic wakeup timestamp tamper The system clock after wakeup is MSI at 4 MHz DoclD025976 Rev 2 25 213 Functional overview STM32L476xx Table 5 Functionalities depending on the working mode Stop 1 Stop 2 Standby Shutdown Low Low 5 5 5 5 Sleep power power 8 8 8 8 VBAT run sleep 5 5 5 2 5 5 5 5 5 CPU Y Y Flash memory up 2 2 2 2 _ E _ _ B to 1 B SRAM1 up to 3 3 1 P B x E E 96 KB Y Y Y Y Y Y SRAM2 32 KB Y y Y y Y Y 09 P FSMC O
198. package top view DocID025976 Rev 2 STM32L476xx Pinouts and pin description Figure 5 STM32L476Qx UFBGA132 ballout 2 3 ES ES OSC32 E VBAT OSC OUT H NRST OPAMP1_ VINM BOOTO OPAMP2_ VINM 5 6 EXE ias VDDUSB MSv35003V6 1 The above figure shows the package top view Figure 6 STM32L476Vx LQFP100 pinout g 1 VDD 2 vss PE4 g VDDUSB 4 PA13 PE6 5 PA12 VBAT L 6 PA11 PC13 g 7 10 PC14 OSC32 IN 8 PA9 PC15 OSC32 OUT PA8 vss PC9 PHO OSC PH1 OSC OUT LQFP100 PC6 NRST PD15 PCO PD14 PC1 PD13 PC2 PD12 PC3 PD11 VSSA PD10 VREF PD9 VREF PD8 VDDA PB15 14 1 13 PA2 PB12 MS31271V2 1 The above figure shows the package top view DoclD025976 Rev 2 55 213 Pinouts and pin description STM32L476xx Figure 7 STM32L476Mx WLCSP81 ele Pete OSC32_OUT OSC32_IN PC9 PA8 VDD PE7 PB8 PB9 MSv38020V2 1 The above figure shows the package top view Figure 8 STM32L476Jx WLCSP72 ballout 1 2 3 4 5 6 7 8 9 Te T ele ele lel ee foe oa B BOOTO osc our Tete Te 1 1 1 1 1
199. parated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts x n 1 supply pins This test conforms to the ANSI JEDEC standard Table 54 ESD absolute maximum ratings Symbol Ratings Conditions Class M Unit T TA 25 C conformin 2 2000 ESD HBM voltage human body model 16 001 V Electrostatic discharge 25 C VEsp cpM Voltage charge device conforming to ANSI ESD 250 model 55 3 1 1 Data based characterization results not tested production q DocID025976 Rev 2 STM32L476xx Electrical characteristics 6 3 13 q Static latch up Two complementary static tests are required on six parts to assess the latch up performance e A supply overvoltage is applied to each power supply pin e A current injection is applied to each input output and configurable pin These tests are compliant with EIA JESD 78A IC latch up standard Table 55 Electrical sensitivities Symbol Parameter Conditions Class LU Static latch up class 105 C conforming to JESD78A II level 1 Negative injection is limited to 30 mA for PFO PF1 PG6 PG7 PG8 PG12 PG13 PG14 current injection characteristics As a general rule current injection to the I O pins due to external voltage
200. r is enable when lt 2 4 V BOOSTEN 1 in the SYSCFG CFGR1 when Vppa lt 24V It is disable when gt 2 4 V 3 Fast channels are PCO PC1 PC2 PC3 PA0 1 4 Slow channels are all ADC inputs except the fast channels Table 64 ADC accuracy 1 2 Symbol Parameter Conditions Min Typ Max Unit Fast channel max speed 4 TBD Single ended Total Slow channel max speed 4 TBD ET unadjusted error Fast channel max speed 3 5 TBD Differential Slow channel max speed 3 5 TBD Fast channel max speed 1 TBD Single ended Slow channel max speed 1 TBD EO Offset error Fast channel max speed 1 5 TBD Differential Slow channel max speed 1 5 TBD T Fast channel max speed 2 5 TBD Single ended Slow channel max speed 2 5 TBD EG Gain error Fast channel max speed 2 5 TBD Differential Slow channel max speed 2 5 TBD Fast channel max speed 1 TBD Single ended ED Differential Slow channel max speed 1 TBD linearity error Fast channel max speed 1 TBD Differential Slow channel max speed 1 TBD DoclD025976 Rev 2 149 213 Electrical characteristics STM32L476xx Table 64 ADC 1 2 3 continued Symbol Parameter Conditions Min Typ Max Unit Fast channel max speed 1 5 TBD Single ended Slow channel max speed 1
201. racteristics Symbol Parameter Conditions Min Typ Max Unit PGA Gain 2 80 80 120 R2 R1 internal PGA Gain 4 40 resistance Rnetwork values PGA Gain 8 _ 140 _ Gain 16 bs 10 Resistance Delta R variation R1 or 15 15 R2 PGA gain error PGA gain error 1 1 Gain 2 GBW 2 E GBW PGA bandwidth Gain 4 5 4 7 PGA BW for different non MHz inverting gain Gain 8 2 odd 1 SM GBW Gain 16 16 at 1 kHz Output Mera mo loaded with 4 kQ eee at 1 kHz Output Low power mode loaded with 20 kQ 600 Voltage noise en 2 So Normal mode at 10 kHz Output 180 loaded with 4 at 10 kHz Output Low power mode with 20 299 OPAMP Normal mode ne Toad 120 260 9 consumption q from VppA Low power mode mode 45 100 R2 is the internal resistance between OPAMP output and OPAMP inverting input R1 is the internal resistance between OPAMP inverting input and ground The gain 1 R2 R1 161 213 Electrical characteristics STM32L476xx 6 3 22 Temperature sensor characteristics Table 70 TS characteristics Symbol Parameter Min Typ Max Unit T Vsense linearity with temperature 1 2 Avg 5 2 Average slope 2 3 2 5 2 7 mV C Voltage at 30 C 5 C 0 742 0 76 0 785 tsTART VE 4 _ TS BUF Sensor Buffer S
202. racterization not tested in production unless otherwise specified sonsiuoj2eJeuo e2129 3 XXQZVTIZEINLS 97 6 20 L12 0L Table 27 Current consumption in Run and Low power run modes code with data processing running from SRAM1 Conditions TYP MAX Symbol Parameter Unit Voltage E ee 105 125 I ee 105 125 scaling 25 C 55 C 85 sc 25 C 55 85 C ic 26 MHz 2 88 2 94 3 05 323 3 58 3 18 326 340 402 4 65 16 MHz 1 83 1 87 1 98 2 15 2 50 2 01 2 16 2 30 2 72 3 34 8MHz 0 97 1 00 1 11 1 27 1 62 1 07 1 16 1 32 1 73 2 36 Range2 4MHz 0 54 0 57 0 67 0 84 1 18 0 59 0 69 0 88 1 23 1 96 2MHz 0 33 0 36 0 46 0 62 0 96 0 37 0 45 0 63 0 98 1 70 fuse up to ABMHz included 1 MHz 0 22 0 25 0 35 0 51 0 85 0 25 0 33 0 50 0 86 1 57 SUPPIY bypass mode 100kHz 0 12 0 15 0 25 0 41 0 75 0 15 0 21 0 39 0 74 145 Ipp Run current in mA Run mod 2 m 80MHz 10 2 10 3 10 5 10 7 11 1 11 22 11 57 11 86 12 07 13 11 za Denpherars disable 72MHz 925 9 31 946 9 68 10 1 10 18 10 41 10 55 10 76 11 80 64 MHz 825 8 31 8 46 8 67 9 08 9 08 9 37 9 66 9 87 10 91 Range 1 48 MHz 6 26 6 33 6 48 6 69 7 11 6 89 7 11 7
203. recorded and then formatted for display on the host computer that runs the debugger software TPA hardware is commercially available from common development tool vendors The Embedded Trace Macrocell operates with third party debugger software tools DoclD025976 Rev 2 53 213 Pinouts and pin description STM32L476xx 4 54 213 Pinouts and pin description Figure 4 STM32L476Zx LQFP144 pinout O PC10 110 1 PA15 109 1 PA14 a a gt 143 D VSS 142 D 141 PEO 140 PB9 139 1 PB8 138 1 137 PB7 136 D PB6 135 5 134 D 4 133 D n N 8 131 VDDIO2 130 VSS TON 929494940 amp c hn 124 PG9 123 D 122 121 O VDD 120 VSS 19 PD5 118 PD4 117 B 116 D PD2 115 PD1 114 PDO Ne aa on 2 PE4 PE5 PE6 VBAT PC13 PC14 OSC32_IN PC15 OSC32_OUT PF0 PF1 PF2 PF3 PF4 PF5 vss VDD PF6 x LQFP144 PF8 PF9 PF10 5 1 05 NRST PCO PC1 PC2 PC3 VSSA VREF VREF VDDA PAO PA1 PA2 VDD VSS VDDUSB PA13 PA12 PA11 PA10 PA9 PA8 PC9 6 VDDIO2 vss PG8 PG7 PG6 PG5 PG4 PG3 PG2 PD15 PD14 VDD VSS PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12 MS31270V3 1 above figure shows the
204. rer JFVNY with two 6 8 pF loading capacitors 9 TZEINLS 291139919 Electrical characteristics STM32L476xx Caution 116 213 I O system current consumption The current consumption of the system has two components static and dynamic I O static current consumption All the I Os used as inputs with pull up generate current consumption when the pin is externally held low The value of this current consumption can be simply computed by using the pull up pull down resistors values given in Table 57 I O static characteristics For the output pins any external pull down or external load must also be considered to estimate the current consumption Additional I O current consumption is due to I Os configured as inputs if an intermediate voltage level is externally applied This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value Unless this specific configuration is required by the application this supply current consumption can be avoided by configuring these in analog mode This is notably the case of ADC input pins which should be configured as analog inputs Any floating input pin can also settle to an intermediate voltage level or switch inadvertently as a result of external electromagnetic noise To avoid current consumption related to floating pins they must either be configured in analog mode or forced internally to a defini
205. rior to any decision to use these Engineering samples to run qualification activity DocID025976 Rev 2 207 213 Package information STM32L476xx 7 7 7 7 1 7 7 2 208 213 Thermal characteristics The maximum chip junction temperature T jmax must never exceed the values given in Table 21 General operating conditions The maximum chip junction temperature max in degrees Celsius may be calculated using the following equation Ty max TA max Pp max x Where TA max is the maximum ambient temperature in C is the package junction to ambient thermal resistance in C W e max is the sum of PiNr max and max Pp max e is the product of Ipp and Vpp expressed in Watts This is the maximum chip internal power max represents the maximum power dissipation on output pins where Pio max 2 Voi loi gt Vppiox taking into account the actual Vo loj and Vor lop of the I Os at low and high level in the application Table 106 Package thermal characteristics Symbol Parameter Value Unit Thermal resistance junction ambient 45 LQFP64 10 x 10 mm 0 5 mm pitch Thermal resistance junction ambient 42 LQFP100 14 x 14mm Thermal resistance junction ambient 5 Osa LQFP144 20 x 20 mm ue ci Thermal resistance junction ambient 55 UFBGA132 7 x 7 mm Thermal resistance junction ambient 46 WLCSP72
206. s Symbol Parameter Conditions Min Typ Max Unit _ USB transceiver operating voltage 3 00 3 6 V tstartup USB transceiver startup time TBD us Rpui Embedded USB DP pull up value during idle 900 1250 1600 i kQ Bann e USB DP pull up value during 1400 2300 3200 2 3 Driving high ZpRV Output driver impedance and low 280 360 440 Q 1 STM32L476xx USB functionality is ensured down to 2 7 V but not the full USB electrical characteristics which are degraded in the 2 7 to 3 0 V voltage range 2 Guaranteed by design not tested in production 3 No external termination series resistors are required on USB_DP D and USB_DM D the matching impedance is already included in the embedded driver CAN controller area network interface Refer to Section 6 3 14 I O port characteristics for more details on the input output alternate function characteristics CAN_TX and CAN_RX FSMC characteristics Unless otherwise specified the parameters given in Table 85 to Table 98 for the FMC interface are derived from tests performed under the ambient temperature fyc frequency and Vpp supply voltage conditions summarized in Table 21 with the following configuration Output speed is set to OSPEEDRy 1 0 11 e Capacitive load C 30 pF e Measurement points are done at CMOS levels 0 5Vpp Refer to Section 6 3 14 port characteristics for more details on the input outp
207. s Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 6 213 Device SUMMAN ersa ienien Un Rc m Rn Rx n RR 1 STM32L476xx family device features and peripheral 13 Access status versus readout protection level and execution modes 17 STM32L476 modes 22 Functionalities depending on the working 26 STM32L476xx peripherals interconnect matrix 29 DMA implementation 34 Temperature sensor calibration 37 Internal voltage reference calibration values 37 Timer feature 42 I2C 2 46
208. s with full modulation capability 0 100 e One pulse mode output In debug mode the advanced control timer counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs DocID025976 Rev 2 Ly STM32L476xx Functional overview 3 24 2 3 24 3 3 24 4 q Many features are shared with those of the general purpose TIMx timers described in Section 3 24 2 using the same architecture so the advanced control timers can work together with the TIMx timers via the Timer Link feature for synchronization or event chaining General purpose timers TIM2 TIM3 TIM4 TIM5 TIM15 TIM16 TIM17 There are up to seven synchronizable general purpose timers embedded in the STM32L476 see Table 10 for differences Each general purpose timer be used to generate PWM outputs or act as a simple time base e 2 TIM4 TIM5 They are full featured general purpose timers TIM2 and TIM5 have 32 bit auto reload up downcounter and 32 bit prescaler TIM3 and has 16 bit auto reload up downcounter and 16 bit prescaler These timers feature 4 independent channels for input capture output compare PWM or one pulse mode output They can work together or with the other general purpose timers via the Timer Link feature for synchronization or event chaining The counters can be frozen in debug mode All have independent DMA request generation and support
209. so interface PDM Pulse Density Modulation microphones and perform PDM to PCM conversion and filtering in hardware DFSDM features optional parallel data stream inputs from microcontrollers memory through DMA CPU transfers into DFSDM DFSDM transceivers support several serial interface formats to support various 2A modulators DFSDM digital filter modules perform digital processing according user selected filter parameters with up to 24 bit final ADC resolution DoclD025976 Rev 2 q STM32L476xx Functional overview The DFSDM peripheral supports q 8 multiplexed input digital serial channels configurable interface to connect various SD modulator s configurable Manchester coded 1 wire interface support PDM Pulse Density Modulation microphone input support maximum input clock frequency up to 20 MHz 10 MHz for Manchester coding clock output for SD modulator s 0 20 MHz alternative inputs from 8 internal digital parallel channels up to 16 bit input resolution internal sources device memory data streams DMA 4 digital filter modules with adjustable digital signal processing Sinc filter filter order type 1 5 oversampling ratio up to 1 1024 integrator oversampling ratio 1 256 up to 24 bit output data resolution signed output data format automatic data offset correction offset stored in register by user continuous or single conversion start of conversio
210. summarized in Table 21 General operating conditions with the following configuration Output speed is set to OSPEEDRy 1 0 11 e Capacitive load 30 pF e Measurement points are done at CMOS levels 0 5 x Vpp Refer to Section 6 3 14 I O port characteristics for more details on the input output characteristics Table 82 SD MMC dynamic characteristics Vpp 2 7 V to 3 6 1 Symbol Parameter Conditions Min Typ Max Unit fpp Clock frequency in data transfer mode 0 50 MHz SDIO CK fPCLK2 frequency ratio 4 3 tw CKL Clock low time fpp 50 MHz 8 10 ns tw CkH Clock high time fpp 50 MHz 8 10 ns CMD D inputs referenced to CK in MMC and SD HS mode tisu Input setup time HS 50 MHz 2 ns Input hold time HS 50 MHz 4 5 ns CMD D outputs referenced to CK in MMC and SD HS mode tov Output valid time HS fpp 50 MHz 12 14 ns toH Output hold time HS 50 MHz 9 i ns CMD D inputs referenced to CK in SD default mode tisup Input setup time SD fpp 50 MHz 2 ns Input hold time SD 50 MHz 4 5 ns q DocID025976 Rev 2 173 213 Electrical characteristics STM32L476xx 174 213 Table 82 SD MMC dynamic characteristics Vpp 2 7 V to 3 6 V continued Symbol Parameter Conditions Min Typ Max Unit CMD D outp
211. t Maskable interrupts Software efficient mailbox mapping at a unique address space Secure digital input output and MultiMediaCards Interface SDMMC The card host interface SDMMC provides an interface between the APB peripheral bus and MultiMediaCards MMCs SD memory cards and SDIO cards The SDMMC features include the following e Full compliance with MultiMediaCard System Specification Version 4 2 Card support for three different databus modes 1 bit default 4 bit and 8 bit e Ful compatibility with previous versions of MultiMediaCards forward compatibility e Full compliance with SD Memory Card Specifications Version 2 0 e Full compliance with SD I O Card Specification Version 2 0 card support for two different databus modes 1 bit default and 4 bit e Data transfer up to 48 MHz for the 8 bit mode e Data write and read with DMA capability Universal serial bus on the go full speed OTG FS The devices embed an USB OTG full speed device host OTG peripheral with integrated transceivers The USB OTG FS peripheral is compliant with the USB 2 0 specification and with the OTG 2 0 specification It has software configurable endpoint setting and supports suspend resume The USB OTG controller requires a dedicated 48 MHz clock that can be provided by the internal multispeed oscillator MSI automatically trimmed by 32 768 kHz external oscillator LSE This allows to use the USB device without external high speed crystal HSE
212. t be disabled 7 Pull up and pull down resistors are designed with a true resistance in series with a switchable PMOS NMOS This PMOS NMOS contribution to the series resistance is minimal 71096 order q DocID025976 Rev 2 139 213 Electrical characteristics STM32L476xx All I Os are CMOS TTL compliant no software configuration required Their characteristics cover more than the strict CMOS technology or TTL parameters The coverage of these requirements is shown in Figure 20 for standard l Os and in Figure 20 for 5 V tolerant I Os Figure 20 input characteristics 25 0 5 Vil Vih all IO except BOOTO TTL requirement Vih min 2V spec 30 vih spec 70 vil spec ttl vih spec ttl Vil rule rule TTL requirement Vil max 0 8V MSv37613V1 140 213 Output driving current The GPIOs general purpose input outputs can sink or source up to 8 mA and sink or source up to 20 mA with a relaxed Vol In the user application the number of I O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6 2 e The sum of the currents sourced by all the I Os on Vppiox plus the maximum consumption of the MCU sourced on Vpp cannot exceed the absolute maximum rating Zlypp see Table 18 Voltage characteristics e The sum of the currents sunk by all the I Os on Vas plus the maximum consumption
213. t power up power down 96 6 3 3 Embedded reset and power control block characteristics 96 6 3 4 Embedded voltage 99 6 3 5 Supply current characteristics 100 6 3 6 Wakeup time from low power modes and voltage scaling transition 120 6 3 7 External clock source characteristics 123 6 3 8 Internal clock source characteristics 128 6 3 9 PLL characteristics 133 6 3 10 Memory characteristics 134 6 3 11 characteristics 135 6 3 12 Electrical sensitivity characteristics 136 6 3 13 current injection characteristics 137 6 3 14 port characteristics 138 6 3 15 NRST pin characteristics 144 6 3 16 Analog switches booster 145 6 3 17 Analog to Digital converter characteristics 146 6 3 18 Digital to Analog converter characteristics 152 6 3 19 Voltage reference buffer characteristics 157 6 3 20 Comparator characteristics 158 6 3 21 Operational amplifiers charac
214. tart up time in continuous mode 8 15 HS terARnT 7 Start up time when entering in continuous mode 70 120 us ts temp sampling time when reading the temperature 5 us Temperature sensor consumption from Vpp when 1 DD Ipp TS selected by ADC d HA Guaranteed by design not tested in production 2 Data based on characterization not tested in production Measured at Vppa 3 0 V 10 mV The ADC conversion result is stored in the TS_CAL1 byte Refer to Table 8 Temperature sensor calibration values 4 Continuous mode means Run Sleep modes or temperature sensor enable in Low power run Low power sleep modes 6 3 23 Vpar monitoring characteristics Table 71 monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for 39 kQ Q Ratio on Vgar measurement 3 Er Error on Q 10 10 ts veat ADC sampling time when reading the VBAT 12 us 1 Guaranteed by design not tested in production Table 72 charging characteristics Symbol Parameter Conditions Min Typ Max Unit Battery VBRS 0 5 VBRS 1 1 5 162 213 DocID025976 Rev 2 q STM32L476xx Electrical characteristics 6 3 24 LCD controller characteristics The devices embed a built in step up converter to provide a constant LCD reference voltage independently from the Vpp volta
215. te digital value This can be done either by using pull up down resistors or by configuring the pins in output mode dynamic current consumption In addition to the internal peripheral current consumption measured previously see Table 39 Peripheral current consumption the l Os used by an application also contribute to the current consumption When an I O pin switches it uses the current from the I O supply voltage to supply the pin circuitry and to charge discharge the capacitive load internal or external connected to the pin Isw Vppiox X fsw x C where lsw is the current sunk by a switching I O to charge discharge the capacitive load Vppiox is the supply voltage fsw is the switching frequency C is the total capacitance seen by the I O pin C Cs Cs is the board capacitance including the pad pin The test pin is configured in push pull output mode and is toggled by software at a fixed frequency q DocID025976 Rev 2 STM32L476xx Electrical characteristics On chip peripheral current consumption The current consumption of the on chip peripherals is given in Table 39 The MCU is placed under the following conditions e AI I O pins are in Analog mode e given value is calculated by measuring the difference of the current consumptions when the peripheral is clocked on when the peripheral is clocked off e Ambient operating temperature and supply voltage con
216. teristics 159 6 3 22 Temperature sensor characteristics 162 6 3 23 Vpaz monitoring characteristics 162 6 3 24 LCD controller characteristics 163 6 3 25 Timer characteristics 164 4 213 DocID025976 Rev 2 Ly STM32L476xx Contents 6 3 26 Communication interfaces characteristics 165 6 3 27 FSMC 175 7 Package information 192 7 1 LQFP144 package 192 7 2 UFBGA132 package information 196 7 3 LQFP100 package information 198 7 4 WLCSP81 package information 201 7 5 WLCSP72 package information 203 7 6 LQFP64 package 205 7 7 Thermal characteristics 208 7 7 1 Reference document 208 7 72 Selecting the product temperature range 208 8 Part numbering 211 9 Revision history 212 DocID025976 Rev 2 5 213 List of tables STM32L476xx List of table
217. tion the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time Refer to the crystal resonator manufacturer for more details on the resonator characteristics frequency package accuracy Table 45 LSE oscillator characteristics f s 32 768 2 1 Symbol Parameter Conditions 2 Min Typ Max Unit LSEDRV 1 0 00 Low drive capability LSEDRWV 1 0 01 _ 315 _ Medium low drive capability LSE current consumption nA LSEDRV 1 0 10 Medium high drive capability LSEDRV 1 0 11 High drive capability LSEDRV 1 0 00 Low drive capability LSEDRV 1 0 01 Bm Maximum critical crystal Medium low drive capability critmax gm LSEDRV 1 0 10 Medium high drive capability LSEDRV 1 0 11 High drive capability 250 630 tuse Startup time Vpp is stabilized 2 S 126 213 DoclD025976 Rev 2 Ly STM32L476xx Electrical characteristics Guaranteed by design not tested in production 2 Refer to the note and caution paragraphs below the table and to the application note AN2867 Oscillator design guide for ST microcontrollers 3 tsu sg is the startup time measured from the moment it is enabled by software to a stabilized 32 768 kHz oscillation is reached This value is measured for a standard crystal and it ca
218. troller LCD 40 3 22 Digital filter for Sigma Delta Modulators DFSDM 40 3 23 Random number generator 42 4 24 Timers and watchdogs 42 3 24 1 Advanced control timer TIM1 TIM8 42 3 24 2 General purpose timers TIM2 TIM4 TIM5 TIM15 16 Duro 43 3 24 3 Basic timers TIM6 43 3 24 4 Low power timer LPTIM1 and LPTIM2 43 3 24 5 Independent watchdog 44 3 246 System window watchdog WWDG 44 3 24 7 Syslickt mer ek meer REX EE WEM Ed wa wa E 44 3 25 Real time clock RTC and backup registers 45 3 26 Inter integrated circuit interface 2 Ra RARE AL 46 3 27 Universal synchronous asynchronous receiver transmitter USART 47 3 28 Low power universal asynchronous receiver transmitter LPUART 47 3 29 Serial peripheral interface 48 3 30 Serial audio interfaces 5 48 3 31 Single wire protocol master interface SWPMI 49 3 32 Controller area network 49 3 33 Secure digital input output and MultiMediaCards Interface SDMMC 50 3 34 Universal serial
219. tsu D NOE FMC D 15 0 MSv38003V1 Figure 44 NAND controller waveforms for write access FMC NCEx ALE A17 CLE FMC A16 ta NCE NWE th NWE ALE _ FMC_NOE NRE FMC D 15 0 MSv38004V1 Figure 45 NAND controller waveforms for common memory read access NCEx ALE 17 CLE A16 la NCE NOE 4 th NOE ALE FMC_NWE FMC_NOE th NOE D FMC_D 15 0 MSv38005V1 DoclD025976 Rev 2 Ly STM32L476xx Electrical characteristics q Figure 46 NAND controller waveforms for common memory write access FMC_NCEx ALE 17 CLE A16 la NCE NWE gt lt lu NWE gt n NOE ALE NWE 55 FMC D 15 0 MSv38006V1 Table 97 Switching characteristics for NAND Flash read cycles Symbol Parameter Min Max Unit Tw NOE NOE low width 4Tucuc1 1 Tsu D NOE FMC D 15 0 valid data before FMC NOE high 16 TnwoE p FMC D 15 0 valid data after NOE high 6 ns Ta NCE NOE FMC_NCE valid before NOE low 1 FMC_NOE high to invalid 2Tucuc2 1 CL 30 pF 2 Based on characterization not tested in production Table 98 Switching characteristics for NAND Flash write cycles 1 2 Symb
220. ty 2 DAC output buffer OFF 2 monotonicity 10 bits guaranteed DAC output buffer ON E 4 Integral CL lt 50 pF RL gt 5 INL li 3 inearity DAC output buffer OFF _ CL lt 50 pF RL VREF 3 6 V 12 DAC output buffer ON LSB Offset error at CL lt 50 pF gt 5 Offset 0 800 3 VREF 1 8 V 25 DAC output buffer OFF _ _ 8 CL lt 50 pF RL Offset error DAC output buffer OFF Offset code 0x0014 CL lt 50 pF no RL i VREF 3 6 V 5 OffsetCal Bs on a DAC output buffer ON ft librati CL lt 50 pF RL gt 5 after calibration VRaEF 1 8 V 7 154 213 DoclD025976 Rev 2 q STM32L476xx Electrical characteristics Table 66 DAC accuracy continued Symbol Parameter Conditions Min Typ Max Unit VDDA 3 0 V VREF 3 0V TBD Offset error 5 0 ne a output buffer emperature coefficient Vppa 3 0 V code 0x800 VREF 3 0 V BB TA 0to 50 C I I DAC output buffer OFF DAC output buffer ON _ _ 0 5 CL lt 50 pF RL gt 5 TU Gain Gain error DAC output buffer OFF _ _ 05 CL lt 50 pF RL m VDDA 9 0 V VREF 3 0V 0 to 50 C TBD Gain error DAC output buffer ON dGain dT temperature uV C coefficient Vppa 3 0 V VreF 3 0 V TA 0 to 50 C T
221. ure can also be detected and generated an interrupt e Clock out capability microcontroller clock output it outputs one of the internal clocks for external use by the application LSCO low speed clock output it outputs LSI or LSE in all low power modes except VBAT Several prescalers allow to configure the AHB frequency the high speed APB APB2 and the low speed APB APB1 domains The maximum frequency of the AHB and the APB domains is 80 MHz q DocID025976 Rev 2 STM32L476xx Functional overview Figure 3 Clock tree PLLUSB2CLK to LSI RC 32 kHz gt LSCO to RTC and LCD OSC32_OUT LSE OSC 32 768 kHz 82 OSC32 IN LSE LSI Ey 11 16 iem gt to PWR SYSCLK 6 gt HS o AHB bus core memory and DMA Clock source control AHB HCLK FCLK Cortex free running clock OSC OUT HSE OSC PRESC gt 11 2 512 4 48 MHz HSE to Cortex system timer e 18 gt MSI detector HSI SYSCLK APB1 PCLK1 PRESC 11 2 4 8 16 to 1 peripherals e xlorx2 ME 4 to
222. ut characteristics DoclD025976 Rev 2 175 213 Electrical characteristics STM32L476xx 176 213 Asynchronous waveforms and timings Figure 35 through Figure 38 represent asynchronous waveforms and Table 85 through Table 92 provide the corresponding timings The results shown in these tables are obtained with the following FMC configuration e AddressSetupTime 0x1 e AddressHoldTime 0x1 e DataSetupTime 0x1 except for asynchronous NWAIT mode DataSetupTime 0x5 e BusTurnAroundDuration 0x0 In all timing tables the THCLK is the HCLK clock period Figure 35 Asynchronous non multiplexed SRAMIPSRAMINOR read waveforms FMC_NE ly NOE NE th NE_NOE FMC_NOE FMC_NWE FMC_A 25 0 Address FMC NBL 1 0 th Data NE tsu Data NOE th Data_NOE tsu Data_NE FMC_D 15 0 t NE tw NADV NADV 1 FMC NWAIT th NE_NWAIT tsu NWAIT_NE MS32753V1 q DocID025976 Rev 2 STM32L476xx Electrical characteristics Table 85 Asynchronous non multiplexed SRAM PSRAM NOR read timings 1 2 Symbol Parameter Min Max Unit tw NE FMC_NE low time 2 0 5 2THcLK 0 5 NE NEx low to NOE low 0 1 tw NOE FMC_NOE low time 2THcLK 0 5 2THcLK 1 th NE_NOE FMC_NOE high to FMC_NE high hold time 0 NE FMC_NEx low to valid 3 5 th A_NOE Address hold time after FMC_NOE hi
223. uts referenced to CK SD default mode tovp Output valid default time SD fpp 50 MHz 4 5 5 ns Output hold default time SD 50 2 0 ns 1 Data based on characterization results not tested in production Table 83 eMMC dynamic characteristics 1 71 V to 1 9 V 1 2 Symbol Parameter Conditions Min Typ Max Unit fpp Clock frequency in data transfer mode 0 50 MHz SDIO CK fpci o frequency ratio 4 3 tw CKL Clock low time 50 MHz 8 10 ns tw CKH Clock high time fpp 50 MHz 8 10 ns CMD D inputs referenced to CK in eMMC mode tisu Input setup time HS fpp 50 MHz 0 ns Input hold time HS 50 MHz 5 ns CMD D outputs referenced to CK in eMMC mode tov Output valid time HS fpp 50 MHz 13 5 15 5 ns tou Output hold time HS 50 MHz 9 ns 1 Data based on characterization results not tested in production 2 Ci oAD 20pF Figure 33 SDIO high speed mode D CMD output D CMD input tr ai14887 DocID025976 Rev 2 Ly STM32L476xx Electrical characteristics 6 3 27 q Figure 34 SD default mode CK D CMD output ai14888 USB characteristics The STM32L476xx USB interface is fully compliant with the USB specification version 2 0 and is 05 certified for Full speed device operation Table 84 USB electrical characteristic
224. values obtained in Table 106 T is calculated as follows For LQFP64 45 C W 100 45 C W x 134 mW 100 C 6 03 C 106 03 This is above the range of the suffix 6 version parts 40 lt T lt 105 C In this case parts must be ordered at least with the temperature range suffix 7 see Section 8 Part numbering unless we reduce the power dissipation in order to be able to use suffix 6 parts Refer to Figure 62 to select the required temperature range suffix 6 or 7 according to your ambient temperature or power requirements Figure 62 LQFP64 Pp max vs TA 700 600 500 300 200 100 0 Pp mW 65 75 85 95 105 115 125 135 C e Suffix 6 Suffix 7 MSv32143V1 DoclD025976 Rev 2 q STM32L476xx Part numbering 8 q Part numbering Table 107 STM32L476xx ordering information scheme Example STM32 L Device family STM32 ARM based 32 bit microcontroller Product type L ultra low power Device subfamily 476 STM32L476xx Pin count R 64 pins J 72 pins M 81 pins V 100 pins Q 132 pins Z 144 pins Flash memory size R G T 6 TR C 256 KB of Flash memory E 512 KB of Flash memory G 1 MB of Flash memory Package T LQFP 2 I UFBGA 2 Y CSP 2 Temperature range
225. ve set of power saving modes allows the design of low power applications Some independent power supplies are supported analog independent supply input for ADC DAC OPAMPs and comparators 3 3 V dedicated supply input for USB and up to 14 I Os can be supplied independently down to 1 08V A VBAT input allows to backup the and backup registers The STM32L476xx family offers six packages from 64 pin to 144 pin packages q 12 213 DocID025976 Rev 2 STM32L476xx Description Table 2 STM32L476xx family device features and peripheral counts 4 STM32L476 STM32L476 STM32L476 STM32L476 STM32L476 STM32L476 Peripheral Zx Qx Vx Mx Jx Rx Flash memory 512 1MB 512 1MB 256KB 512KB 1MB 512 1MB 512 1 256KB 512KB 1MB SRAM 128KB External memory controller for Yes Yes Yes No No No static memories Quad SPI Yes Advanced 2 16 bit control General 5 16 bit purpose 2 32 bit Basic 2 16 bit Timers Low power 2 16 bit SysTick timer 1 Watchdog timers 2 independent window SPI 3 Pc 3 USART 3 UART 2 LPUART 1 Comm interfaces SAI 2 CAN 1 USB OTG FS Yes SDMMC Yes SWPMI Yes Digital filters for sigma delta Yes 4 filters modulators Number of channels 8 RTC Yes Tamper pins 3 2 2 2 LCD Yes Yes Yes Yes Yes Yes COM x SEG 8x40 or 4x44 8x40 or 4x44 8x40 or 4x44 8x30 or 4x3
226. verter e Vgar 1 55 to 3 6 V power supply for RTC external clock 32 kHz oscillator and backup registers through power switch when Vpp is not present When the functions supplied by Vppa Vppioa are not used these supplies should preferably be shorted V pp If these supplies are tied to ground the I Os supplied by these power supplies are not 5 V tolerant refer to Table 18 Voltage characteristics DoclD025976 Rev 2 19 213 Functional overview STM32L476xx 3 9 2 20 213 Figure 2 Power supply overview Vppa domain 3 x A D converters VppA 2 x comparators V 2 x D A converters 55 2 x operational amplifiers Voltage reference buffer LCD Ac r USB transceivers ss Vppio2 domain Vppio2 ring Vss PG 15 2 Vpp domain uo ring Reset block Vcore domain Temp sensor 3 x PLL HSI MSI Core V Standby circuitry ds SS Wakeup logic dd IWDG Digital Vpp VcoRE peripherals Voltage regulator ri Low voltage detector Flash memory Backup domain LSE crystal 32 K osc BKP registers RCC BDCR register RTC H 519671 3 Power supply supervisor The device has an integrated ultra
227. vision code MSv36870V3 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity DoclD025976 Rev 2 q STM32L476xx Package information T 6 LQFP64 package information Figure 59 LQFP64 64 pin 10 x 10 mm low profile quad flat package outline SEATING PLANE 0 25 GAUGE PLANE K m L1 PIN IDENTIFICATION 5W ME V3 1 Drawing is not to scale Table 105 LQFP64 64 pin 10 x 10 mm low profile quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 1 0 050 0 150 0 0020 0 0059 2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 0 090 0 200 0 0035 0 0079 D 12 000 0 4724 D1 10 000 0 3937 D3 7 500 0 2953 E 12 000 0 4724 E1 10 000 0 3937 DocID025976 Rev 2 205 213 q Package information STM32L476xx Table 1
228. waveforms tw NE FMC_ NE FMC_NOE FMC_NWE FMC D h Data NE tsu Data_N th Data_NOE nuc tv A_ w tv NADV NE Too th AD_NADV tw NADV FMC_NADV w FMC_NWAIT tsu Data_ th NE_NWAIT tSu NWAIT NE MS32755V1 q DocID025976 Rev 2 179 213 Electrical characteristics STM32L476xx Table 89 Asynchronous multiplexed PSRAM NOR read timings 1 2 Symbol Parameter Min Max Unit tw NE FMC_NE low time 0 5 2 FMC_NEx low to FMC_NOE low 2 0 5 2TycLK 0 5 NOE low time 0 5 1 NOE high to NE high hold time 0 tA FMC_NEx low A valid 5 3 tvNADv_NE FMC_NEx low to FMC_NADV low 0 1 twNApv FMC_NADV low time 0 5 1 D RAD valid hold time after 0 _ th A NOE Address hold time after NOE high 0 5 BL time after NOE high 0 tg NExlow to FMC BL valid 2 tsu Data_NE Data to NEx high setup time 2 tsu Data_NOE Data to NOE high setup time 1 x tn pata NE Data hold time after NEx high 0 th Data Data hold time after FMC NOE high 0 1 CL 3
229. with large configurability and flexibility allowing to target as example the following audio protocol 125 LSB or MSB justified PCM DSP AC 97 and SPDIF out e Upto 16 slots available with configurable size and with the possibility to select which ones are active in the audio frame e Number of bits by frame may be configurable e Frame synchronization active level configurable offset bit length level e First active bit position in the slot is configurable e first or MSB first for data transfer e Mute mode e Stereo Mono audio frame capability e Communication clock strobing edge configurable SCK e Error flags with associated interrupts if enabled respectively Overrun and underrun detection Anticipated frame synchronization signal detection in slave mode Late frame synchronization signal detection in slave mode Codec not ready for the AC 97 mode in reception e Interruption sources when enabled Errors FIFO requests DMA interface with 2 dedicated channels to handle access to the dedicated integrated FIFO of each SAI audio sub block DoclD025976 Rev 2 Ly STM32L476xx Functional overview 3 31 3 32 q Table 12 SAI implementation SAI features SAI2 125 LSB or MSB justified PCM DSP AC 97 X X Mute mode X X Stereo Mono audio frame capability X X 16 slots X X Data size configurable 8 10 16 20 24 32 bit X X FIFO Si
230. x 7 3 198 213 LQFP100 package information Figure 52 LQFP100 100 pin 14 x 14 mm low profile quad flat package outline SEATING PLANE IDENTIFICATION 0 25 mm GAUGE PLANE 1L ME V5 1 Drawing is not to scale Table 101 LQPF100 100 pin 14 x 14 mm low profile quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 0 090 0 200 0 0035 0 0079 D 15 800 16 000 16 200 0 6220 0 6299 0 6378 D1 13 800 14 000 14 200 0 5433 0 5512 0 5591 DoclD025976 Rev 2 q STM32L476xx Package information q Table 101 LQPF100 100 pin 14 x 14 mm low profile quad flat package mechanical data continued millimeters inches Symbol Min Typ Max Min Typ Max D3 12 000 0 4724 E 15 800 16 000 16 200 0 6220 0 6299 0 6378 E1 13 800 14 000 14 200 0 5433 0 5512 0 5591 E3 12 000 0 4724 e 0 500 0 0197 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 0 3 59 7 0 0 0 3 5 7 0 0 080 0 0031 1 Values inches converted from mm rounded to
231. xcept OTG FS RNG N A 136 2 TBD PLL Range 1 All 37 uA MHz 6 cycles Sleep No ON ON Any Any interrupt or event Range 2 All except OTG FS RNG 35 uA MHz 6 cycles Any LPSleep LPR No ON ON except All except OTG FS RNG Any interrupt or event 40 pA MHz 6 cycles PLL BOR PVD PVM i Reset pin all I O RTC LCD IWDG ien dg B COMPXx 1 2 DACx x 1 2 RTC LCD IWDG DEAMPS 2 COMPx x 1 2 4 us in LSE a USARTx x 1 5 6 6 6 uA SRAM Stop 1 LPR N ff ON SARTx x 1 5 x LSI P LPUART1 69UAWRTC 6usin LPUART1 7 Flash 4 aD I2Cx x 1 3 as I2Cx x 1 3 LPTIMx 651 2 2 Fs 1 9 All other peripherals are frozen BOR PVD PVM LCD IWDG Reset pin all I Os COMPx x 1 2 BOR PVD PVM 5 us in RTC LCD IWDG SRAM LSE I2C3 1 1 uA RTC Stop 2 LPR No Off ON 6 COMPx 1 2 LSI LPUART1 peat 14 iets eM LPUART1 O Flash LPTIM1 All other peripherals are frozen J EUOIoUn XXQZV TIZEINLS 9 6 20 10 56 Table 4 6 321 476 modes overview continued Mode Regulator CPU Flash SRAM Clocks DMA amp Peripherals 2 Wakeup source Consumption AM SRAM2 BOR RTC IWDG 0 35 pA RTC LPR ON 0 65 All other peripherals Reset LSE Standby Boc Off powered off 5 I Os WKUPx 19 14 us OFF Powered
232. y STM32L476xx Electrical characteristics Table 57 static characteristics continued Symbol Parameter Conditions Min Typ Max Unit Vin lt 0 9 100 _ input leakage 65026 curent ax Vppxxx Max Vppxx 1 V lt 5 VIN lt 5 5 VU I I 2009 Vin lt 150 lik lt lt nA lu FT_u and phim 250026 PC3 IO DDXXX Max Vppxx 1 lt 6 lt 5 5 I I 2500 Vin lt 9 150 TT input leakage current Max Vppxxx lt ViN lt 2 e v 200002 Weak pull up _ equivalent resistor 7 ViN Vss 28 40 E Weak pull down m Rpp equivalent resistor Vin Vppiox 29 9n l O pin capacitance 2 5 pF 1 Vppiox represents Vppio1 Vppio2 Vppio1 2 Guaranteed by design not tested in production 3 Max Vppxxx is the maximum value of all the I O supplies Refer to Table Legend Abbreviations used the pinout table 4 All TX xx IO except lu FT u 5 This value represents the pad leakage of the IO itself The total product pad leakage is provided by this formula 10 number of IOs where VIN is applied on the pad x lk Max 6 To sustain a voltage higher than MIN Vpp VppA Vppio2 Vicp 0 3 V the internal Pull up and Pull Down resistors mus
233. ze X 8 Word X 8 Word SPDIF X X 1 X supported Single wire protocol master interface SWPMI The Single wire protocol master interface SWPMI is the master interface corresponding to the Contactless Frontend CLF defined in the ETSI TS 102 613 technical specification The main features are e full duplex communication mode e automatic SWP bus state management active suspend resume e configurable bitrate up to 2 Mbit s e automatic SOF EOF and CRC handling SWPMI can be served by the DMA controller Controller area network CAN The CAN is compliant with specifications 2 0A and B active with a bit rate up to 1 Mbit s It can receive and transmit standard frames with 11 bit identifiers as well as extended frames with 29 bit identifiers It has three transmit mailboxes two receive FIFOs with 3 stages and 14 scalable filter banks The CAN peripheral supports e Supports CAN protocol version 2 0 A B Active e Bitrates up to 1 Mbit s DoclD025976 Rev 2 49 213 Functional overview STM32L476xx 3 33 3 34 50 213 e Transmission Three transmit mailboxes Configurable transmit priority e Reception Two receive FIFOs with three stages 14 Scalable filter banks Identifier list feature Configurable FIFO overrun e Time triggered communication option Disable automatic retransmission mode 16 bit free running timer Time Stamp sent in last two data bytes e Managemen

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