Home

SystemC Methodology - ESA Microelectronics Section

Contents

1. CC C C pure Algorithm refinement tints sae e E SystemC ho DUE X CEDE Vie XD EDGE t IE A POP EUR E LE XP RENT 1 TLM l Bus arbitration H H Cycle accurate computation B 1 4 Main SystemC concepts Some basic concepts built specially for hardware design using C language are commonly understood by the SystemC community The main important entities are listed below Entity Description Module Hierarchical entity which contains other modules or processes Process Describe the behaviour between modules They are contained in the SystemC modules There are 3 different types of processes SC METHOD SC THREAD and SC CTHREAD Ports Connections between modules Could be either unidirectional or bi directional Signals Supports resolved and non resolved signals resolved signals can be connected to several sources unlike non resolved signals Port and Signal In order to support the modeling at many abstraction levels from a functional level to type RTL level SystemC library does support a large amount of port and signal types Data type Idem required to grant all abstraction levels Nicolas Lain TEC EDM 5 Research on new SoC design Methodology using SystemC issue 1 revision 0 1 5 Modelling Overview
2. AAA AU AAA AA AA AA AA AA AAA AAA AE do lib SpW compile spw uod do AAA AA AAA AA AAA AA AAA AA AE AA AA A ARE Compiling spwrlink echo compile spwrlink AAA AU AAA AA AE AA AAA AA AAA AAA AE vcom 93 work init lib SpW Spwb src vhdl top spwrlink vhd HEHHHHHHHHHHHHHHHHHHHHHHHHHHHHHH EHEHEHEH Compiling OCP_TARGET_SpW_TX echo compile OCP_TARGET_SpW_TX BHHRHRHHHPHEHEHEHEHEHERHRHRHHHHHHHEH EG BG HEHE vcom 93 work init lib SpW Spwb wrapper SpW TX vhd vcom 93 work init lib SpW Spwb wrapper OCP SpW TX vhd HAE HAE HE AE AE AE HAE HAE HE AE HAE HAE HE AE AE AE HAE AE E AE E A AE AE AE BG Compiling OCP MASTER SpW RX echo compile OCP MASTER SpW RX AREA HAE HE AE AE AE HAE HAE HE AE HAE HAE AE AE AE AE HAE HAE EE AE AE AE ERE vcom 93 work init lib SpW Spwb wrapper memblock vhd vcom 93 work init lib SpW Spwb wrapper SpW RX vhd vcom 93 work init lib SpW Spwb wrapper SpW RX top vhd vcom 93 work init lib SpW Spwb wrapper OCP SpW RX top vhd RAA AA AAA AA AAA AA AAA AAA AAA AN AAA HAE Compiling top level echo compile top level RAA AA AU AAA AA AAA AA AAA AAA AAA AN ERE EEE vcom 93 work init src init VHDL initiator vhd HAE HE AFF HAE HAE HAE HE HAE AE HAE AE HAE HAE HE HAE AE HAE HAE AE HE EE AE AA EEE AE HE AE AE AA HE AE HE DEEE AE AA AE AE AE RAF AAA AAA COMPILING SRAM Simulation Model w timing constraintstHHHHHHHHHH
3. lib SpW spw v12 SpW12 top vhd HEH HHHHE Compiling LEON3 AAA AA AE AAC A AE do lib leon compile leon3 do vcom 93 work work lib leon simple irq vhd RHEI HHHHE Compiling leon3 top RAA A AAA AA AAA AA AAA vcom 93 work work lib leon leon3 top vhd AAA AA AAA AA AA HAE AA AA AAA Compiling MEMORY AHB slave BHHRHRHHHEHEHBHEHEHERHRHRHRHRHPH E BG B EG A A vcom work work 93 lib leon grlib0 15 lib gaisler misc ahbram vhd vcom work work 93 lib leon grlib0 15 lib gaisler misc ahbram top vhd vcom work work 93 lib slave ram gaisler ahbmem ram vhd BHRHRHRHHHEHEHEHEHEHGHGHRHRHR EEE Compiling SoC Synthesis SNAPSHOT HEFFER EA AE ERGATA EERE EEE vcom work work 93 synth SoC rev_rice_socl rice_rtl_vhdl_wrapper vhm AAA AA AAA AA AA AA AA AA AA AAA AAA AA AAA EHEH Compiling Top Rice Encoder IP OCP Interfaces HEHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHEHHHHHHHHHH EA HEE vcom work work 93 src rice soc VHDL rice rtl vhdl vhd HEFFER HAE HE HE HE AE HAE HAE AE HE HAE AE HAE HAE AE HE DEEE AE AA EEE AE HE DEEE AE HAE EE HAE HE AE AE ERA AE ERE HAR HE EU HARAS COMPILING INITIATOR 4 AAIE A HA AAA AAA AFF ERE HEE AAA DEA AE HE AE REE AFF EEEE AAA EU E HAE HE AE HAE HAE AE ERE AE HAE HAE AA ERE AE HAE HAE AE HE EE AE HAE HAE AE EAA AE HE ERA AE HAE AE AA RAAT ERE AR HE E echo Compiling the VHDL files of SoC INITIATOR HAE HAE AE E AE REET RE RR HA E AE HE AE AE AE ERE HE H
4. src SoC rice soc VHDL ipbridge vhd Leon3 Files add file vhdl lib virage t src lib leon grlib0 15 lib tech virage vcomponents virage_vcomponents vhd add file vhdl lib actel add file vhdl lib grlib add file vhdl lib grlib add file vhdl lib grlib add file vhdl lib grlib add file vhdl lib grlib LAARAARAI add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib fpu add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib grlib add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib gaisler add file vhdl lib work add file vhdl lib work add file vhdl lib work add file vhdl lib work Rice Files a
5. Then co simulation is used if a SystemC testbench is used with a Verilog or VHDL design representation A SystemC system consists of a set of modules interconnected at each other with channels Inside a module we can find concurrent processes which describe functionality of the system Inter module communication is also done with channels CORE LANGUAGE DATA TYPES Modules Logic Type Ports Logic Vectors Processes Bits and Bit Vectors Interfaces Arbitrary Precision Integers Channels Fixed Point Integers Events For each module we need to specify ports to communicate through channels Depending what the module represents the ports will represent the interface pins and so forth An interface is a set of access methods It does not provide any implementation but is purely functional Interfaces are bound to ports in a sense that they define what can be done through a particular port A process accesses the channel by applying the interface methods a port 1 5 1 FUNCTIONAL MODELING Nicolas Lain TEC EDM 6 Research on new SoC design Methodology using SystemC issue 1 revision 0 The behaviour of this model at this level is purely described algorithmically The timing is not cycle accurate but could describe the time to generate or consume data or to model buffering or data access The behaviour of the interface is entirely done by communication protocols The goal of this level modeling is firs
6. We expect that for a well chosen predictor small values of Ai are more likely than large values as shown below the PDF Power Density Function of delta values should reach its maximum value for zero samples Nicolas Lain TEC EDM 14 Research on new SoC design Methodology using SystemC issue 1 revision 0 Power Density Function PDF Xmin Xi 0 Xmax Xi 2 2 2 2 Adaptive entropy coder The following schematic shows the architecture of the entropy coder which represents the main part of the encoder engine Selected Code ption ID Compressed Datas Nicolas Lain TEC EDM 15 Research on new SoC design Methodology using SystemC issue 1 revision 0 The principle of this module is to choose the smallest compressed datas issued from the options processes A unique identifier ID bit sequence is attached to the code block to indicate to the decoder which decoding option to use Then we get final compressed datas We will not explain in depth each option but in the following table are some descriptions of each option knowing that each of them is best suited for a special case of input data Note that each option is working on a block unit Remember that a block of data is defined as a set of J samples sample s resolution is fixed to 8 bits in this implementation Option name Description Option Zero Block This option is chosen when one or more than one consecuti
7. COMPRESSION END NBR BLOCKS TO COMPRESS The RTL implementation shown above displays in a black box architecture all signals 7connections and ports for the encoder engine The state machine will give the output for the following register 5 Output registers of STATE MACHINE Name Description INTERNAL REGISTERS Enable preprocessor Enables the preprocessing stage Enable encoder Enables the encoding stage i e receiving data from preprocessor computing compression data Enable formatter Enables the formatting stage i e format amp send the compressed data to the output State out current state Fsm valid out Enables to send data to the output grant from the state machine part only but need also the grant of the encoder part PORTS Data accept in Handshake communication Data ready out Handshake communication Also the output registers of the encoder unit Nicolas Lain TEC EDM 26 Research on new SoC design Methodology using SystemC issue 1 revision 0 Output registers of ENCODER Name Description INTERNAL REGISTERS Stop_run Stops the RUN mode because either the encoder needs to send more datas or it has to send zero block option datas End_data_reached Set to 1 once all input blocks were compressed Enc_data_valid The encoder unit is ready to send compressed datas PORTS Data_out Handshake communication 2 3 2 3 Description of
8. Consequently a simple modification needed in the SystemC code may be time consuming in some cases Nicolas Lain TEC EDM 36 Research on new SoC design Methodology using SystemC issue 1 revision 0 YES Simulation with Simulation with Modification in testbench RTL amp Translation testbench RTL RTL SystemC TLM Systeme ESC vupp amp TLM code using MS visual SystemC using C Modelsim C Compilation A short draw is showed above mentioning previous steps concerning the refinement or translation from SystemC to final synthesizable VHDL code 2 6 Results 2 6 1 COMPRESSION RATIO In order to get some figures about how powerful the compression algorithm is we need to send big amount of datas We chose to send raw data pictures to the encoder and then to decode it in order to find the original data It was a good way to show the IP doesn t have bugs anymore indeed when you send a lot of datas you will increase the probability to find an error in the algorithm It was also a good way to compare simulation speed of TLM Level with RTL model In order to convert raw data file ASCII format into an input testbench file compliant with the TLM testbench a PERL script was built for format file conversion PERL is a language very well suited for file management knowing that building your own input testbench will take more time and would restrict test cases A well suited output parameter to apprecia
9. RTL SystemC using local variables Better solution SC_MODULE module_1 PORTS DECLARATION Sc out int gt c SIGNALS DECLARATION Int b Void module 1 main B b 1 c write b SC MODULE module 1 PORTS DECLARATION Sc out lt int gt c Void module 1 main Int b B b 1 c write b I notice that the translation inserted some type conversions in the VHDL code and after it requires the pre compilation of conversion functions stored in prosilog_sc2v_conv vhd package file Note that these conversion functions may slow down the simulation speed for the RTL VHDL code 2 5 3 The output of this experience is the following CONCLUSION ON THE TRANSLATION Name of the sub module file name systemc file name vhdl Problem of translation Output work FSM Finite State Machine No The RTL VHDL translation is up to fsm1 cpp fsm1 vhd gt date with its SystemC counterpart Preprocessor No The RTL VHDL translation is up to lt preprocessor_gold h preprocessor_rtl vhd gt date with its SystemC counterpart Encoder Unit Yes Due to some bugs of the translator lt encoder_gold h encoder_rtl vhd gt tool the translation is not the VHDL output file straightforward and requires manual modification after having translated Concerning the encoder unit the translation is not click amp use due to some bugs in the SC2VHDL converter
10. flag ready in 1 ready in cnt ready in 0 ready in cnt 0 amp amp flag ready in 0 ready in cnt randomize time2 flag ready in 1 ready in 0 ready in cnt 0 amp amp flag ready in 1 ready in cnt randomize time flag ready in 0 ready in 1 ready in 0 int random time random time rand 400 random time lt 5 if random time 5 return random time int randomize time2 int random time random time rand random time 5 if 50 random time 5 return random time int ready in cnt int flag ready in int ready in SC CTOR adapter in SC THREAD init SC METHOD adapt in sensitive clk pos it can send datas to RICE IP INPUT FIFO is busy cannot send datas to RICE IP you can select here the gap average length Gap should be at least 6 clk cycles at high level you can select here the burst average length burst should be at least 2 clk cycles at 0 level Counter for for ready_in burst generation u Adapt in cpp Adapter TLM gt RTL prototype AMAIA SC_FIFO ADAPTER to HANDSHAKE SIGNALS 8 Bits 1 11 A LIU HMM IE E E LL LL M g g IMP EI III P P P gg EI AAA TT I include adapt in h void adapter in init data in rtl write sc lv 8 0 data ready in write 0 ready in cnt randomize time flag ready in 0 while tlm2rtl rice data in num available
11. out data accept out nb blocks tocompress nb blocks tocompress Nicolas Lain TEC EDM int size int size top decoder goldl top decoder gold2 ouput Decoder2 FIFO work top encoder rtl for SYSTEMC DESIGN data ready out data accept out compression end enable preprocessor enable encoder 32 FIFO at the output of encoder stage 32 FIFO between encoder amp TB enable decoder enable postprocessor from TLM from RTL encoder Model encoder Model one decoder for TLM encoder one decoder for RTL encoder adapter inl from RTL encoder Model adapter outl checkerl for VHDL DESIGN 59 Research on new SoC design Methodology using SystemC issue 1 revision 0 compression_end compression_end enable_preprocessor enable_preprocessor enable encoder enable encoder data to preprocess rtl data to preprocess rtl data to preprocess tlm data to preprocess tlm data compressed data compressed 32 data compressed log data compressed log 32 enable decoder enable decoder enable postprocessor enable postprocessor stop simu stop simu HB Bg B INSTANCIATION JTI FFLAT I RTL tb encoder bothl reset rst tb encoder bothl enable preprocessor enable preprocessor tb encoder bothl enable encoder enable encoder tb encoder bothl data in tlm data to preprocess tlm tb encoder bothl d
12. 05 05 05 Choice of the application 4 0 0 0 Reading Documentation 4 1 1 1 1 DEFINITION AND SETUP PHASE 8 1 1 1 1 12 impl SystemC encoder 7 0 0 0 0 impl SystemC decoder 4 1 0 0 0 impl SystemC testbench 2 2 1 0 0 TLM SystemC simulation amp validation 1 5 0 0 0 refine the encoder to RTL level 0 7 2 0 0 RTL SystemC encoder validation 0 5 8 0 0 Translation using tool to VHDL 0 0 1 0 0 RTL VHDL encoder Simulation amp Validation 0 0 2 0 0 DESIGN METHODOLOGY STUDY 14 20 14 0 0 48 OCP interfacing 0 0 2 4 0 Simple SoC implementations 0 0 0 8 2 SoC with Rice IP and SpW impl 0 0 0 0 8 Tests 0 0 0 2 6 SYSTEM ON CHIP IMPLEMENTATION 0 0 2 14 16 32 writing report amp oral presentation 0 0 4 6 3 SUPPORT 0 0 4 6 3 13 TOTAL number of days 22 22 21 21 20 106 Nicolas Lain TEC EDM 67
13. 1 1 k i data_sample length compressed bits k 2 k J for i 0 i lt J i FS split data range NB BITS k 1 0 2data sample tmr Fil data_tmp_out k 2 set length_compressed_bits k 2 e for j 1 j FS split data j F10 data_tmp_out k 2 length_compressed_bits k 2 Shift F 1 1 length_compressed_bits k 2 FS_split_data 1 CHF10 Name Value E sc time stamp E El data tmp out k 2 dad El sc dt sc unsigned CRE sgn 0 nbits 129 ndigits 5 E digit Dz0065eac8 k 1 j 11 El F8 split data cL Nicolas Lain TEC EDM 30 Research on new SoC design Methodology using SystemC issue 1 revision 0 The main advantage in using MS Visual C for SystemC implementation is the debug mode this mode authorizes you to stop simulation whenever by introducing some breakpoints in the code However as Visual C was not originally built for hardware development purposes it cannot display waveforms such as tools like Modelsim or NC SIM So if you are using some timing constraints in your TLM model you may use Modelsim first That was the basic features of the debugger but you can also use more complex debug options if you like exceptions handling thread suspension Below are shown all actions or triggers you can have during debugging For each statement in your code you can either choose to go on to the next statement by choosing STEP OVER function or step into the C function called by this statement if it was compiled
14. 2 0 1b msvc60 where is whatever parent directory you saved SystemC to 2 Click on the subdirectory systemc which contains the project and workspace files to compile the systemc lib library Double click on the systemc dsw file to launch Visual C with the workspace file The workspace file will have the proper switches set to compile for Visual C 6 0 Select Build systemc lib under the Build menu or press F7 to build systemc lib Creating a new des gn 1 Start Microsoft Visual C 6 0 2 Create a Project Workspace a Click on File then New select Projects then click on Win32 Console Application b For the Project Name we will use rice as the example Type OK c Choose An empty project and click Finish Then click OK Nicolas Lain TEC EDM 29 Research on new SoC design Methodology using SystemC issue 1 revision 0 3 You can now see a folder named rice classes in the workspace window Left part of screen 4 Port SystemC libraries to Microsoft Visual C 6 0 a Go EM Restart Eal Stop Debugging T9 Step Into TP Step Over P Step Out H Run to Cursor Eh Exceptions El Threads Modules Click on Project then Settings then select the C C tab and then finally select the C Language category Make sure that the Enable Run Time Type Information RTTI checkbox is checked Also make sure that the
15. SpW spw v12 spacewire source delay cnt vhd src lib SpW spw v12 spacewire source disconnection vhd src lib SpW spw v12 spacewire source ds gen vhd src lib SpW spw v12 spacewire source host int vhd src lib SpW spw v12 spacewire source init fsm vhd src lib SpW spw v12 spacewire source rx vhd src lib SpW spw v12 spacewire source rx decod vhd src lib SpW spw vl2 spacewire source rx mgt vhd src lib SpW spw v12 spacewire source rx resync vhd src lib SpW spw v12 spacewire source rx shiftreg vhd src lib SpW spw v12 spacewire source spacewire vhd src lib SpW spw v12 spacewire source sw vhd src lib SpW spw v12 spacewire source sw counters vhd src lib SpW spw vi2 spacewire source sw fifo vhd src lib SpW spw v12 spacewire source sw reg vhd src lib SpW spw v12 spacewire source sw resync vhd src lib SpW spw v12 spacewire source tx vhd src lib SpW spw v12 spacewire source txcnt vhd src lib SpW spw v12 spacewire source tx ack vhd src lib SpW spw vl2 spacewire source tx mgt vhd src lib SpW spw v12 spacewire source tx resync vhd src lib SpW spw v12 spacewire source tx select vhd src lib SpW spw v12 SpW12 top vhd src SoC rice soc VHDL rice rtl vhdl vhd rice rtl vhdl sdc add file vhdl lib sw lib add file vhdl lib sw lib add file vhdl lib sw lib add file vhdl lib spw v12 add file vhdl lib spw v12 add file vhdl lib spw v12 add fi
16. SystemC header files are included by switching to the Preprocessor on the C C tab and then typing C SystemC systemc 2 0 1 src in the text entry field labelled Additional include directories Next click on the Link tab and make sure the SystemC library is included to your project by typing C SystemC systemc 2 0 1 msvc60 systemc Debug in the text entry field labelled Additional library path Add the SystemC object files by first clicking on Project then Add to Project then Files In the File Browser navigate to the C SystemC systemc 2 0 1 msvc6O systemc Debug directory In the text entry field labelled File Name type obj and press enter Click on the file sc attribute obj and then simultaneously press the Ctrl amp A keys CTRL A Click the OK button to add the files In your workspace window under the File View Tab you should see a number of object files with the sc_ prefix such as sc_attribute obj sc_bit obj etc Find the file sc_isdb_trace obj click that file name and press delete on your keyboard ASS EPIPIPOP LIT IS FLED EP EL OL ALP t OPP yr Ur a uh ur gl p EPELEE 4 4 Options Sample splitting from k 1 to k NB BITS 3 FS BB Bg B B M MR ng gn gggggpgpok e nn F FS split data 0 Ctri shift F5 for int k 1 k lt NB_BITS 2 k k 0 is FS option like Shift F5 e for i 0 i lt J i gt data_tmp_out k 2 range k i
17. TLM RTL results comparison Compilation script for the System On Chip used by Modelsim Synthesis script for the System On Chip used by Synplify Hierarchy diagram Detailed time organization chart Nicolas Lain TEC EDM 54 Research on new SoC design Methodology using SystemC issue 1 revision 0 Appendix 1 Top entities for TLM and RTL Rice encoder in SystemC TOP TLM Rice Encoder SystemC JC III IRI CC IR IRI CC IO IO OO IO OO RR IOI II II II I TLM Model of Rice compression IP SystemC Model N Laine ARR ICICI ICICI III ISI ICICI II ICICI ICICI ICICI I IIIA I ICICI A III f include global h include preprocessor_gold h include encoder gold h SC MODULE top encoder gold sc in lt bool gt enable preprocessor sc in bool enable encoder Sc fifo in lt sc uint lt 8 gt gt enc data in sc fifo out lt sc uint lt 8 gt gt enc data out ONLY FOR DEBUG PURPOSE Sc fifo out lt sc uint lt 8 gt gt enc data out log file preprocessor gold PREP_GOLD1 encoder_gold ENCODER_GOLD1 sc_fifo lt sc_uint lt 8 gt gt prep_data_out SC CTOR top encoder gold PREP_GOLD1 new preprocessor gold preprocessor gold PREP_GOLD1 gt enable_preprocessor enable preprocessor PREP GOLD1 prep data in enc data in PREP GOLD1 prep data out prep data out ENCODER GOLD1 new encoder gold encoder gold ENCODER GOLD1 enable encoder enable
18. before by choosing STEP INTO 2 4 2 2 Using Mentor Graphics Modelsim Modelsim implements also the SystemC language based on the Open SystemC Initiative SystemC 2 0 1 reference simulator The main advantage compared with Visual C is the extensive support for mixing SystemC VHDL and Verilog in the same design However you will need to modify your SystemC source code to be simulated on Modelsim below are the main steps in order to get your first simulation of your design 1 Create and map the working design library with vlib and vmap commands 2 Modify your main SystemC source code e Replace sc main with an SC MODULE e Replace sc start by using the run command in the GUI e Remove calls to sc initialize e Export the top level SystemC design unit using the SC MODULE EXPORT macro 3 Compile all your SystemC source code with sccom command 4 Perform a final link of the C source using sccom link 5 Simulate the design using vsim command and run the simulation using run command Note that if you are choosing to work on both Modelsim and Visual C you can use the same file for the top level design unit by specifying with the MTI SYSTEMC macro the Modelsim specific code Nicolas Lain TEC EDM 31 Research on new SoC design Methodology using SystemC issue 1 revision 0 24 3 RTL LEVEL VALIDATION 2 4 3 1 Testbench with several levels of abstraction One of the biggest benefits to start from TL
19. cycles in the design without altering performance i e simulation speed It can be done for instance by adding a wait line after each write at the output as written below output port write output port tmp Write at the output of the IP wait CLOCK PERIOD SC NS WAIT statement for Modelsim debug Finally there s no way to display waveforms for local variables defined in a process To resolve this issue the designer may need to define module member variables knowing that it may slow down the simulation in Modelsim Visual Studio Visual C constraint One important limitation occurred when handling long variables such as sc biguint or sc bigint Indeed MS Visual Studio is limited with 32 bits when trying to examine the values of these variables gt SystemC bugs or missing parts in libraries In the entire project I used SystemC v2 0 1 and it suffered with few bugs or missing part such as e Concatenation between sc biguint and sc uint not handled This problem is fixed in SystemC v2 1 I did not use this version since it was not provided with the Visual Studio librairies 2 3 2 IMPLEMENTATION IN RTL LEVEL OF THE ENCODER 2 3 2 1 TLM to RTL refinement After validating the TLM level of the DUT we need to refine our model into a synthesizable level which is the RTL level Basically there are 2 types of refinement Refinement Model refinement Communication refinement This ability to separate
20. een sans tt a res uota v dea a edt 50 4 2 What next si awi yd a qun Y ica tate adea uas 50 vi Research on new SoC design Methodology using SystemC issue 1 revision 0 1 INTRODUCTION 1 1 General overview The goal of this research developed from April 1 to August 31st 2005 is to show benefits of a new design methodology for hardware implementation and more precisely all concerning System On Chip design using a new standard SystemC based originally on the C language SystemC was released to the public in Sept 1999 by the Open SystemC Initiative OSCI It comes from the idea that developers need using a same language for both modelling software and hardware components of a system A survey made by Doulos Ltd a company offering training courses in SystemC concerning the question What are you using SystemC for now in or in the future had the following results the current usage is concentrated to system optimization high level modelling and co simulation A brief chart is showed below giving the most common usage of SystemC and its expected usage in this project even though we will see later in details why SystemC is used in our case Perfomance Modeling Eee 68 Architecture Exploration 68 Transaction Level Modeling 56 Hardware Software Co Simulation ee 56 Bus Modeling 48 Co simulation With VHDL Or Verilog M 4 Algorithm Development 36 Behavioural Synthesis 32 Software Operatio
21. encoder ENCODER GOLD1 enc data in prep data out ENCODER GOLD1 enc data out enc data out ENCODER GOLD1 enc data out log file enc data out log file TOP RTL Rice Encoder SystemC RC CCR CC RC CC ICIS ICICI I ICI II ISIS RR I RR RR OR A II I RTL Model of Rice compression IP SystemC Model N Laine CCR RC CARR CAR ACA RC CAU CR A II IGE f include systemc h include fsml h include preprocessor rtl h include encoder rtl h SC MODULE top encoder rtl PORTS g Bg 01111111111 sc in bool gt clk Sc in lt bool gt reset Asynchroneous reset sc in bool gt data ready in Ready signal to receive input datas Sc out bool data accept in Grant signal to receive input datas sc in lt sc_lv lt 8 gt gt data_in Input datas bus 8 bits sc_out lt sc_lv lt 8 gt gt data_out Output datas bus 8 bits sc_out lt bool gt data_ready_out Ready signal to send output datas Sc in bool gt data accept out Grant signal to send output datas CONTROL amp STATUS REGISTERS sc in lt sc lv lt 16 gt gt nb blocks tocompress Number of blocks to compress sc out bool compression end set to 1 when all input datas were compressed and sent to the output MM LE LIL LILI LEE IE TL I INTERNAL SIGNALS Sc signal bool enable preprocessor Sc signal bool enable encoder
22. engineers have traditionally been faced with the lack of a cohesive methodology for algorithm validation system architecture exploration and co verification of hardware and software In a way to prevent costly redesign effort a new design methodology is described in the following paper The purpose of this research is to give an overview of the new design flow using a recent standard library SystemC a C library dedicated for hardware modeling One big advantage of using this language compared with the traditional design flow is to provide transaction level modeling TLM as an intermediate level between the algorithm level and the hardware implementation aimed at close the gap between these abstraction levels We will focus on the design of one space dedicated application using this new methodology showing advantages and drawbacks This presentation elaborates on the concepts mentioned above and introduces a resulting SoC platform Research on new SoC design Methodology using SystemC issue 1 revision 0 page iii of vi iii e S a Research on new SoC design Methodology using SystemC issue 1 revision 0 page iv of vi Preface As a part of the one year specialized master Mast re Sp cialis in electronics and aerospace communications done in SUPAERO Toulouse France this year I have performed this internship at the European Space Agency Technical Centre ESA ESTEC from April 4 to August 26 in the Microelectronics
23. for a user all on a single microchip Today CMOS technologies like 90 nanometers allow reaching integration such as 50 Millions gates on a die Starting from zero would represent an investment in time and debugging effort an alternative consist in making use of pre checked module called IPs for this purpose ESA had purchased a tool Magillem from Prosilog allowing the integration and interconnection of IPs between them or to different bus system AMBA from ARM or CoreConnect from IBM A small SoC platform using this tool had already been designed at VHDL level and had been implemented on a Xilinx breadboard The stage proposed will be directly linked to the previous development and will consist in setting up a SystemC application and map it to the existing SoC platform 2 1 2 DIFFERENT STEPS The algorithm of the application will have to be translated in SystemC at several levels of abstractions and then in a first time translate into synthesizable hardware language such as VHDL At the end of this task we should map the full hardware application on to the SoC platform and we should show some advantages of this new design methodology compared with normal design flow described previously In the remaining time we will define the best suited partionning between hardware and software and perform the refinement steps to map the application on to the SoC platform Nicolas Lain TEC EDM 10 Research on new SoC design Methodology
24. initiator was to send datas to the SpW initiator SpW UoD sending the software or the microprocessor application code to the chip ram and then sending uncompressed data to the SRAM This SoC design was designed to validate the following points e Validation of the RICE IP on a SoC implementation Nicolas Lain TEC EDM 46 Research on new SoC design Methodology using SystemC issue revision 0 Validation of the Memory Controller combined with external SRAM Use the Spacewire as a way to communicate with the board using high speed link e Switching to a new trap table for the Leon3 and using a new microcode stored in chip ram during its run After having implemented the system on chip on the FPGA board sending datas to the board is used with a Spacewire link SpaceWire connected to a Spacewire Initiator portal which provides remote access from a transparent Ethernet interface SO that SpaceWire packets can be directly sent and received over Ethernet via a TCP IP socket connection can be simply the PC lab in our case There is no limit to the length of the SpaceWire packets transferred 3 5 FPGA Implementation We may have three different possibilities after having mapped the System On Chip on the board Loading the software using e UART connexion UART from a boot flash e UART connexion from Linux platform e Debug Support unit furnished with the Leon3 library The first possibility was used for the impleme
25. section from the Data System Division For have been given this opportunity I would like to thank all the helpful staff in the TEC ED division and more especially my supervisor Laurent Hili and the young graduate trainee Matthias Carlqvist hardware engineers for their support throughout the whole project I would like to thank also all the following persons Claudio Monteleone TEC EDD engineer Agustin Fern ndez Le n TEC EDM section head Roland Weigand TEC EDM engineer Boris Glass TEC EDM engineer Finally I would like to thank my examiner Vincent Calmettes SUPAERO and my mast re responsible Michel Bousquet SUPAERO Noordwijk 26th August 2005 Nicolas Lain e S a Research on new SoC design Methodology using SystemC issue 1 revision 0 page v of vi Table Of Contents 1 agieppieuem 2 1 1 General overload cite Mc du EN M du Es 2 1 2 Traditional system design T1035 ees A t Pres MR i adv se RC oes anaes 4 13 Design Flow Usiiig gt ysteml 421522502259 i a a Prod Y GY AMAF Yda 5 14 Main SystemC Concepts sursis ore ete rte YFC y FF Pede qua Eo GOG 5 15 Modelling Overview en ee TL 6 1 5 1 Funetional MONS Ge GU a eub ensure LL nn lead de 6 1 5 2 Transaction Level Modele amendement phe added eden inv ee egenis YC 7 1 5 3 Register Transfer Level Modeling sene ue e ras Ro a dut oae e Ex deco Pul ated eed Es DRA Rd 8 1 6 SIMILIS MN NN RS TS 9 2 DESIGN APPLICATION FOR SOC DATA COMPRESSIO
26. synthesizable code Writing RTL style code in SystemC is quite similar to writing RTL code in either the Verilog or VHDL hardware description languages Nicolas Lain TEC EDM 8 Research on new SoC design Methodology using SystemC issue revision 0 1 6 Summary SystemC provides an easy way to design at many levels of abstraction It works perfectly for functional modeling as well as transaction modeling so that the move between modeling methods is made easier while using the same language Moreover when switching to higher level design descriptions it will allow a greater performance in terms of speed and flexibility Nicolas Lain TEC EDM 9 Research on new SoC design Methodology using SystemC issue 1 revision 0 2 DESIGN APPLICATION FOR SOC DATA COMPRESSION 2 1 Objectives 2 1 1 REASONS TO LOOK FOR A NEW DESIGN METHODOLOGY Complexity in microelectronics requires a different approach in the way to design ASIC or System On Chip What does System On Chip stand for System on a chip SoC technology is the packaging of all the necessary electronic circuits and parts for a system such as a cell phone or digital camera on a single integrated circuit IC generally known as a microchip For example a system on chip for a sound detecting device might include an audio receiver an analog to digital converter ADC a microprocessor necessary memory and the input output logic control
27. the state machine of RTL encoder The state machine designed here is a Mealy state machine structure since the output logic is a function of the current state and a function of the inputs In my case I decided to build an explicit state machine to make easier the synthesis 9 states are in total and the state machine diagram is showed below EE 1 From all states except reset o back to SETUP when 1 1 compression end is high a IDLE lenc data valid OR data ready in AND data accept out data accept out AND stop run data ready in OR data accept out AND end data react ed data ready in AND data accept out data ready Af AND C gnaw gt data accept o stop run data gecept out data ready in OR data accept out stop run OR Idata accept out FORMAT ONLY Nicolas Lain TEC EDM 27 Research on new SoC design Methodology using SystemC issue 1 revision 0 Basically the state machine set the IDLE mode when both preprocessor and encoder are not working and the RUN mode is when both of them are working together following a pipelined architecture When the IDLE mode is set and as soon as the input and output are ready to be sent and received datas we can switch to PREP mode and then FIRST mode which are corresponding to 2 clock cycles latency due to handshake signals and the 2 pipelined stages between the preprocessor and the encoder While both inputs data_ready_in and data_accep
28. to produce a netlist from SystemC even RTL based code Thus the following report part deals with Replace the non synthesizable SystemC code with synthesizable code for the Design Under Test module To translate SystemC to VHDL code we chose to use a Prosilog tool SC2VHDL v1 0 2 5 2 ISSUES AND RECOMMENDATIONS During this translation we noticed some important points underlined below e Short documentation concerning the tool Nicolas Lain TEC EDM 34 Research on new SoC design Methodology using SystemC issue 1 revision 0 e Bugs found in the translator and forwarded to the Prosilog support team these bugs are 1 Impossible to use arrays signals in several processes a temporary solution is then to replace this array by several signals for each process 2 Incorrect translation of one internal loop in a loop when the first one depends on the iteration variable of the second one for instance for inti i 10 i for int j j lt 8 i j Recommendation to get correct RTL synthesizable codes Indeed one of the biggest traps after designing in TLM level or higher abstraction level is that you don t respect RTL coding rules anymore Thus when you are starting the translation to RTL level several modifications need to be done in the code gt Non constant variables used as parameters In the algorithmic version TLM Level for instance we can design loops using non con
29. update models cp 0 verification mode 0 fixgatedclocks 0 modular 0 retiming 0 no sequential opt 0 simulation options set option set option write verilog 0 write vhdl 1 VIF options set option automatic place and route write vif 1 vendor options set option write apr constraint 1 set result format file last project result file rev rice socl rice rtl vhdl wrapper edf implementation attributes set_option vlog_std v2001 set_option synthesis_onoff_pragma 0 set option project relative includes 1 impl active rev rice soci Nicolas Lain TEC EDM Research on new SoC design Methodology using SystemC issue revision 0 65 Research on new SoC design Methodology using SystemC issue 1 revision 0 Appendix 6 Hierarchy of the project data source files work Main directory I src Source directory lib Used IP s libraries peel lib leon Leon3 library I lib mem_ctrl Memory Controller Library I lib ocp ocp32 PROM and OCP interfaces libraries l lib slave_ram Slave internal memory library I lib sram SRAM simulation model I lib systemc debug SystemC debug unit for SoC P RICE RICE IP Library I systemc IP SystemC source and compilation files I src bench Testbench source files src golden_ref TLM source files encoder amp decoder src rtl RTL source file for encoder I src rtl_tlm Adapters TLM RTL and checker l vhdl IP VHDL Source files src
30. v6 1 In a first experience we compared simulation speeds between RTL SystemC and VHDL SystemC offers greater speed even though it was not as big as expected Typically the CR obtained here is very similar as expected despite some compression algorithm features related to the CCSDS recommendation were not implemented see 2 3 3 Conclusion and future possible improvements 2 6 2 COMPARISON TLM SYSTEMC VS RTL VHDL As we have seen earlier one good thing to use intermediate level such like TLM allow designers to either explore new architectures for the system or start earlier SW HW partitioning In the traditional flow people need to wait for the validation of RTL level before doing these optimizations In this case it will be interesting to compare simulation speeds between TLM SystemC and RTL VHDL Picture Size of picture Simulation speed Simulation Speed Gain TLM SystemC speed RTL rate VHDL spot la b1 raw 250kBytes 18 1 30 xb spot la b2 raw 250kBytes 14 131 X6 5 spot la_b3 raw 250kBytes 15 130 X6 spot la_panchr raw 1 Mbytes 46 5 20 X7 Lena512 262kBytes 16 1 35 X6 Results show that higher abstraction levels have a clear speed advantage The biggest difference in speed comes from the use of abstract timing in the communication instead of using cycle accurate communication Nicolas Lain TEC EDM 38 Research on new SoC design Methodology using SystemC iss
31. vcom work work 93 src rice soc VHDL AHB decoder 2 vhd vcom work work 93 src rice soc VHDL AHB decoder boot 2 vhd vcom work work 93 src rice soc VHDL timing wheel 2 vhd vcom work work 93 S src rice soc VHDL Request multiplexor d4 m5 vhd vcom work work 93 src rice soc VHDL Response multiplexor d4 e9 vhd vcom work work 93 src rice soc VHDL AHB arbiter 2 vhd vcom work work 93 src rice soc VHDL AHB controller 2 vhd vcom work work 93 src rice soc VHDL ahb controller vhd vcom work work 93 src rice soc VHDL APB bridge 1l vhd vcom work work 93 src rice soc VHDL apb controller soc vhd vcom work work 93 src rice soc VHDL ipbridge vhd RHEI Compiling RTL Rice Encoder AAA AREA AE AA A AE vcom work work 93 rice_dir vhdl src rtl encoder prosilog_sc2v_conv vhd vcom work work 93 rice dir vhdl src rtl encoder fsml vhd vcom work work 93 rice dir vhdl src rtl encoder encoder rtl vhd vcom work work 93 rice dir vhdl src rtl encoder preprocessor rtl vhd vcom work work 93 rice dir vhdl src rtl encoder top encoder rtl vhd vcom work work 93 rice dir vhdl src rtl encoder top encoder rtl wrapper vhd RAA HA AA AA AA AAA A A AA AAA AAA AA AAC AA AA ANA A GE Compiling snapshot RTL Encoder after synthesis RAA AA AA AA AA AA PREAH EA AA AA A AA EA AC AA AA AA ANA HE GE vcom work work 93 rice_dir vhdl synth rev_3 top_encoder_rtl vhm RAA AA AI AA AA AAA HA AAA AAA AA A AA AAA AAA ANA HI GE Compil
32. vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add file vhdl lib prosilog C SoC Files Appendix 5 Synthesis script SoC SoC_final prj 41 2005 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Pr
33. will be re executed while there are still some data in the input file Top level files can be found in Appendix 1 2 3 1 4 Problems encountered During the implementation of the Rice compression algorithm using TLM model in SystemC we were faced with some problems related to the following causes gt Set up the environment No problems related to the setup of SystemC Nevertheless the UNIX Modelsim version rebooted sometimes the computer for network slow response reasons related to NFS Interdrive I was greatly dependent of the ESA network status that s why after that I decided to switch on windows platform for debugging TLM Model Nicolas Lain TEC EDM 23 Research on new SoC design Methodology using SystemC issue 1 revision 0 gt Limitation of debugging tools Modelsim constraint C debug is not really convenient based on the old GDB UNIX debug tool it does have typical debugging commands such as setting breakpoints or stepping mode Nevertheless speed of the debugger is limited by the Modelsim speed which is not really as big as Visual C speed We can explain this because Modelsim was designed first for hardware variable types handling and not C variable types That s why I do not recommend the use of Modelsim v6 or less to debug C entities Moreover simulating TLM model using waveforms is possible but quite difficult when the design is not clocked A solution to bypass this problem is to introduce clock
34. 0 wait CLK PERIOD SC NS data in rtl write sc lv 8 tlm2rtl rice data in read void adapter in adapt in int flag stop if tlm2rtl rice data in num available 0 flag stop ready in cnt 0 return counter ready in cnt flag ready in ready in data ready in write ready in if data accept in read amp amp ready in 1 ready in 0 amp amp flag stop 1 data in rtl write sc lv 8 tlm2rtl rice data in read else data ready in write 0 Nicolas Lain TEC EDM 57 Research on new SoC design Methodology using SystemC issue 1 revision 0 Adapt_out h Adapter RTL gt TLM prototype AANA SC_SIGNAL to SC_FIFO ADAPTER 8 Bits RTL TLM Simulation LIL FT TH B I include systemc h SC MODULE adapter out Sc in lt bool gt Sc in lt bool gt sc out bool Bc in Sc lW lt 8 gt gt Sc fifo out sc uint lt 8 gt gt rtl rice data out rtl2tlm rice data out MEEI clk data_ready_out data_accept_out void return counter int amp accept out cnt int amp flag accept out int amp accept out VIDmHBMMMIEMMBPBGMBMGMMIELHMCBGMPMllll COUNTER FOR ACCEPT OUT BURST GENERATION RER EEE TH MM B gU gU AT ATE if accept out cnt gt 0 amp amp flag accept out 0 accept out cnt accept out 1 else if accept out cnt gt 0 amp amp flag accept out 1 accept out cnt accept out 0 else if accept o
35. 0 master2 2 OCP Slave 2 0 Interruption Handler MEMORY CTRL Nicolas Lain TEC EDM 44 Research on new SoC design Methodology using SystemC issue 1 revision 0 The SoC source files can be found in the directory work src SoC leon RB32 sram A SoC was designed in order to validate the new design methodology both TLM and RTL Rice implementations were successfully connected to a RTL VHDL SoC The core of the SoC is the AMBA bus controller it does consist of a router which handles requests from a master and sends it to the slave The host is a widely used processor in space applications Gaisler LEON3 4 It is a 32 bit processor core conforming to the SPARC V8 architecture 5 It has been designed for on board applications and has high performance with low power consumption Moreover it has two main units integer and floating point unit but in our case only the integer unit will be used Then the controller receives the corresponding response of the slave The following table gives the main steps when compressing an input datas We will assume in this case that external SRAM is already filled with uncompressed input datas Leon reads its microcode stored into the OCP PROM Leon configures both OCP IP s interfaces for direct memory access to the SRAM 1 2 3 OCP MASTER IN reads from the memory controller input datas and sends it to the Rice IP OCP MASTER OUT writes to the memory con
36. 15 lib gaisler leon3 libiu vhd 15 lib gaisler leon3 mmuiface vhd 15 lib gaisler leon3 libcache vhd 15 lib gaisler leon3 libproc3 vhd 15 lib gaisler leon3 cachemem vhd 15 lib gaisler devices devices vhd 15 1ib gaisler leon3 acache vhd lib grlib sparc sparc vhd 15 lib gaisler leon3 dcache vhd 15 lib gaisler leon3 icache vhd 15 lib gaisler leon3 cache vhd 15 lib gaisler leon3 iu3 vhd 15 lib gaisler leon3 tbufmem vhd 15 lib gaisler leon3 dsu3 vhd 15 lib gaisler leon3 proc3 vhd lib gaisler leon3 leon3s vhd lib gaisler misc ahbram vhd er ahbmem ram vhd l encoder prosilog sc2v conv vhd l encoder encoder rtl vhd 1 encoder fsm1 vhd l encoder preprocessor rtl vhd l encoder top encoder rtl vhd l encoder top encoder rtl wrapper vhd re load prom vhd to32 RX vhd to32 TX vhd op encoder rtl masterl vhd op encoder rtl master2 vhd 7C 32 vhd amba source amba vha 64 8rc 1ib SpW spw v12 spacewire source sw pack vhd src 1ib SpW spw v12 spacewire source scoc tech generic vhd src 1ib SpW spw v12 spacewire source scoc ramlib vhd src lib SpW spw v12 spacewire source ahb mst_rx vhd src lib SpW spw v12 spacewire source txshiftreg vhd src lib SpW spw v12 spacewire source ahb mst slv tx vhd src lib SpW spw v12 spacewire source ahb tx int vhd src lib SpW spw v12 spacewire source clk tx gen vhd src lib SpW spw v12 spacewire source clk tx gen2 vhd src lib
37. DESIGN AND VERIFICATION TOOLS USED The following tools have been used to implement and test the IP Rice encoder Textpad 4 53 uu a E Text file editor e Microsoft Visual Studio 6 0 pp C C design compiler e Mentor Graphics Modelsim v6 0d amp v6 1 C VHDL Waveforms viewer amp SystemC 2 0 D oes be es e MOSS QUE UT RARO ORG RI ERI E MET REOR CE DU EIS C library e Prosilog SC2VHDL A ar urs e y O Eg RTL SystemC to VHDL translator e Prosilog Magillem v2 2 Yndi RAN A RYN dd AX Up C ed FO IP Interconnect tool e Synplicity Synplify Pro 8 0 Y SR pos x Ha tutors Synthesis tool 8 In ISE 6 3i secuti OD RETRO ne Place amp route amp board implementation 2 2 Algorithm of Rice compression 2 2 1 GENERAL There are two classes of source coding methods Lossless and Lossy gt A Lossless source coding technique preserves source data accuracy and removes redundancy in the data source In the decoding process the original data can be reconstructed from the compressed data by restoring the removed redundancy the decompression process adds no distortion This technique is particularly useful when data integrity cannot be compromised It has been suggested for many space science exploration mission applications either to increase the amount of information return or to reduce the requirement for on board memory The price to pay is generally a lower Compression Ratio which is defined as the ratio of the number of origi
38. E E E EUER Compiling AHB initiator and AHB slave BEAT HE AE AE AE RE RE EERE EE HE AE AE AE RE HE E E EE vcom work init 93 magillemdir IP_Library ahb_slave_ram lib vhd vcom work init 93 magillemdir IP Library ahb slave ram vhd vcom work init 93 magillemdir Verification OCP_GUI_Initiator vhd vcom work init 93 magillemdir Verification ocp_ gui initiator top vhd HEHEHE ERR ERE RE HE E E GER Compiling AHB system AAA AE AE AE AE AE E AE AE FE AE HER E E EE HF vcom work init 93 src init VHDL AHB decoder 1 vhd vcom work init 93 src init VHDL AHB decoder boot 1 vhd vcom work init 93 src init VHDL timing wheel 1 vhd vcom work init 93 src init VHDL Request multiplexor d4 m2 vhd vcom work init 93 src init VHDL Response multiplexor d4 e5 vhd vcom work init 93 S src init VHDL AHB arbiter 1 vhd vcom work init 93 src init VHDL AHB controller 1 vhd vcom work init 93 src init VHDL ahb controller soc vhd vcom work init 93 src init VHDL APB bridge 2 vhd vcom work init 93 src init VHDL apb controller soc vhd vcom work init 93 S src_init VHDL ipbridge vhd BHHRHRHPHEHEHBHEHEHEHRHRHRHRHHHEH EG BHE E Compiling APB to OCP control wrapper echo APB to OCP control wrapper BHHEHHHPHEHEHBHEHEHEHRHRHRHRHHH B BG B GN vcom 93 work init lib SpW Spwb wrapper APB to OCP control wrapper vhd RAA AI AAA AA AA AA AAA AA AAA AAA AA Compiling spw codec echo compile spacewire codec
39. ENCODER GOLD1 enable encoder enable encoder ENCODER GOLD1 enc data in prep data out ENCODER GOLD1 enc data out enc data out ENCODER GOLD1 enc data out log file enc data out log file One internal fifo called prep data out is used to connect the preprocessor result to the encoder stage The preprocessor will not be discussed in details here since its implementation was straight forward following the CCSDS recommendation it was designed as a one delay predictor the current data is saved and will be used at the next clock cycle The encoder part was from far the hardest and most design timing intensive module to implement as we have already seen why before this module has to determine the best option for each input block till the total number of blocks is reached I chose to split the encoder engine into 4 parts or processes since we re working inside a module SystemC module is defined by the SC MODULE macros or by explicitly deriving a new class from sc module A process looks like normal C functions with slight exceptions A process is invoked by the scheduler based on its sensitivity list SC MODULE SystemC module Actions or processes encoder gold Void init This thread initializes the encoder like the no compression option is chosen by default long int get length input data This function gives the total number of blocks to compress from the input uncompressed file
40. ENTATION ON THE EXISTING SOC 40 3 1 Sus pr E EM 40 3 2 Presentation of the IP interconnection tool Magillem v2 3 Prosilog pp 40 3 2 1 TOG SOURS OSE sr a a P S GN TG 40 3 2 2 Bugs or missing parts Teported su o e NE den ben EUER OUS TS a RN es 40 3 3 OCP Interface implementation for IP Rice desee e inte eren eter ease i pec ene at 41 3 3 1 IP Creator OO sisi nent dat aan tas dd FFO DG YR tre FN odd 41 3 3 2 Implementation at RTE level iie tet toti sire ee ecu FR Y A ux f 42 3 3 3 At TLM level for validation purpose sans to roe ert tue eo enn eek ene ro Pre rena eg Bn SS 43 34 SoGdesign using Magillem 0 a a o noL e edm PR Co ls 44 3 4 1 One simple example of SoC using the Rice IP 44 3 4 2 SoC using Rice IP combined with SpaceWIte u dace one eta Het tapa Y Fd RR 46 59 PPG A Implem ntatiom ss ee tec Rer RT eee ci ae DNE Made cca sape ids 47 2001 RECU en ot ope data epa aea odes M tte 48 Sov Possible improvements a nn A A i Mom ML Uu Ree tese ee 48 4 CONCLUSION ce ceccu cu danaa ce ener eo eere cuacevencvedeves cuasevencwesevescueneveucweceweccweneue 49 4 1 Results regarding specifications 224 hihihi o rc rad echa rita lee tbi por RY RD aa tesi uad es 49 4 1 1 Steps er hed o Me ne ee diu sula Mon WT e a od pe ste 49 4 1 2 Benefits of the systeme design methodology su uei cte secca iem ient e cts ee 49 4 1 3 Points to be still clarified 7 e Sas a a Sea sae anao t Rd abe dins 49 4 1 4 Project time Ol PANI ZATION sm er
41. FIFO s 4 4 Lg 4444494444 sc signal bool sc signal bool sc fifo sc uint 8 gt sc fifo sc uint lt 8 gt tlm data rtl data gt ouput Decoderl FIFO gt ouput Decoder2 FIFO top_decoder_gold top_decoder_gold JUDITH ETAT TTT MB MM ATTA TAT Gg IM ADAPTER FIFO gt HANDSHAKE SIGNALS adapter_in RARE EEE EEE EEE III TAT TAT TTT AAA AAT ADAPTER HANDSHAKE gt FIFO SIGNALS sc_fifo lt sc uint lt 8 gt gt rtl2tlm data out adapter out RER EEE EEE EEE LEE IEEE EEE EI EE EE II EEE EI EI EE EEE E LL BG ggg 1 CHECKER AFTER DECOMPRESSION sc_signal lt bool gt checker HMM MM MM MHIL gU LL GG MM TI IEEE IE ILE EI stop simu SC CTOR rice rtl vhdl clk clk CLK PERIOD SC NS rst rst M1 CHOOSE ONE TO BE SIMULATED top encoder rtl INST top encoder rtl INST top encoder rtl INST top encoder rtl INST JT IMG LEE EI EEE IEEE EI EEE LEE EEE top encoder goldl top encoder goldl tb encoder bothl tb encoder bothl top decoder goldl top decoder goldl top decoder gold2 top decoder gold2 adapter inl adapter inl adapter outl adapter outl checkerl checkerl data ready in data ready in data accept in data accept in data in data in rtl data out rtl data out data ready out data ready out data accept
42. HHHHHHHH Nicolas Lain TEC EDM Research on new SoC design Methodology using SystemC issue revision 0 62 Research on new SoC design Methodology using SystemC issue 1 revision 0 HEAT TERRE RE RE EERE HE ER ERE ERE RE RAE AE HE RHR ET HE RAE AEE HE ERR HHT RE RARE AT HEAR HR ERE BE HE E E HER echo Compiling the VHDL files of SRAM vcom work sram 93 lib sram sram vhd HAE AE AAA HAE HAE HE AE AE AE AE E BERE EE COMPILING TOP TESTBENCH HAE HAE AAA HAE AE HE B A AE ERE HEAR vcom work work 93 rice_tb vhd set StdArithNoWarnings 1 vsim t Ins work rice tb do wave do run all Nicolas Lain TEC EDM 63 Research on new SoC design Methodology using SystemC issue revision 0 Synplicity Inc version Synplify Pro 8 0 Project file C work synth Written on Sun Aug 21 16 35 Prosilog Library add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file vhdl lib prosilog add_file
43. ION AND SETUP PHASE s DESIGN METHODOLOGY STUDY SYSTEM ON CHIP IMPLEMENTATION x SUPPORT Apr 05 May 05 Jun 05 Jul 05 Aug 05 Note that the System On Chip implementation could have been started earlier since the TLM encoder model was ready at the end of April 05 see Appendix 7 The support part dedicated to report and PowerPoint writing started approximately at half project time 4 2 What next gt SystemC v2 1 Imports interesting new features vs previous versions e New class allowing multiple outstanding events like Verilog s scheduled events e New facility which allows a module to expose internal channels gt High level synthesis Some new tools available on the market Towards algorithmic synthesis Catapult C Mentor Graphics CoWare s SystemC based ESL design Celoxica for SystemC synthesis These synthesis tools perform some new features such as e Scheduling and resource allocation the algorithm model is encapsulated in a module whose communication protocol is represented either in a communication class or directly as a signal level handshake Nicolas Lain TEC EDM 50 Research on new SoC design Methodology using SystemC issue 1 revision 0 e Creates a state machine and data path e Schedule functional units for the data path appropriately using control logic satisfying area constraints and latency constraints However latency and area cannot be determined unt
44. M level is the ability to use TLM entities with RTL models The next figure shows the environment around the testbench based on a comparison between both levels of abstraction Note that it was not needed to refine the testbench into RTL model the only refinement step is the introduction of some adapters between TLM and RTL transactions ENCODER TLM DECODER TLM Design Under Test Testbench TLM Model E AMOMIO DECODER TLM 7 TLM Transaction RIL Transaction The detail and source code of this testbench can be found in Appendix 3 Note also that a Modelsim compilation script for this testbench can be found in Appendix 4 2 4 3 2 Adapters needed for TLM 2RTL and RTL 2TLM Adapter TLM gt RTL This adapter converts SC_FIFO signal to RTL handshake signals and can be directly used between a TLM testbench and RTL DUT Nicolas Lain TEC EDM 32 Research on new SoC design Methodology using SystemC issue 1 revision 0 sc_fifo_in data_in data_in data_ready_in data_accept_in IP clock For the generation of handshake signals a random function was used so that it can approximately take care of busy states at the input The average length in terms of clock cycle for gap period during data_ready_in will be high and for burst period during data_ready_in will be low can be selected by the user However it will be necessary to recompile SystemC file after each modification S
45. N 10 2 1 ODJECUVE Ses OG a Uu E E E EEE TEA 10 DAS Reasons to look for a new design methodology Us 10 2 1 2 Different Steps acoso ride cate nn be E FF Y nee nent 10 2 1 3 Design and verification tools Used lk wiki ae ae toga ea aun etd ce SA Y do 12 2 2 Algorithm of Rice compression Y CR Y cet dena lod ime e ple RR 12 2 21 Generals oe ate M M dE m e da 12 2 22 ETS SOULCE CMC ODER s r ADY YNN teen nana an ten anne le 13 2 22 PrOeptOCOSSOL usce eei an Non iv aeu dec nie iei d eiue i tec icio 13 2224 2 Adaptive entropy COURT sa md M tues ange ta neem Qr 15 2 2 2 3 Whe Coded output toriad s cose ec nd eb og e D DL QU VHS et oes clea UNS UU 16 23 3 The d coder ende eto certe a co tO eee os RA a erg doe A E us 17 2 2 3 1 The adaptive entropy decoder nn 17 22 2 Thepostproeessor UTE cam ibt da pa ceste epi OE E E ns 18 2i lmplemeni aton nD a atten ee dde DEL S quere 18 2 3 1 Impl mentationin l ENEMOdl uu re en a a a E ia 18 2311 Eneoder ee a Y Y Y RWY WYN AR y ave Aes 18 PS PR MM ge DP RE 2 2 3 1 3 Tope and tesiDeneh em Deed b ERE OS aco MI a LIE ced D A UE 22 2 3 1 4 Problems encountered iiyn TWF a tec eve e oti o ve e iere x Ra dedos 23 2 3 2 Implementation in RTL level of the encoder Ne 24 2321 TEM to RPE refinements nm aa ea cad tha het os a a toa 24 2 3 2 2 Implementation of the RTL encoder ose WN retos hag e EN eek Meee 26 2 3 2 3 Description of the state machine of RTL encoder pp 27 2 3 3 Co
46. Sc signal lt bool gt enable formatter sc signal lt sc lv lt 8 gt gt prep data out Sc signal bool fsm valid out Sc signal bool enc data valid Sc signal bool stop sc signal lt sc lv lt 8 gt gt state Sc signal bool end data reached Sc signal bool end AAA fsml FSMl preprocessor_rtl PREP1 encoder rtl ENCl SC CTOR top encoder rtl FSM1 new fsml fsml FSM1 clk clk FSM1 gt reset reset FSM1 in ready data ready in FSMl in accept data accept in FSM1 out accept data accept out FSM1 out ready fsm valid out FSMl enable preprocessor enable preprocessor FSMl enable encoder enable encoder FSMl enable formatter enable formatter FSM1 gt stop_run stop FSM1 gt valid_from_encoder enc data valid FSMl state out state FSMl end data reached end data reached FSM1 gt compression_end end PREPl new preprocessor rtl preprocessor rtl Nicolas Lain TEC EDM 55 Research on new SoC design Methodology using SystemC issue 1 revision 0 PREP1 gt clk clk PREP1 gt enable_preprocessor enable_preprocessor PREP1 gt state_in state PREP1 gt prep_data_in data_in PREP1 gt prep_data_out prep data out ENC1 new encoder rtl encoder rtl ENC1 gt clk clk ENCl enable encoder enable_encoder ENCl enable formatter enable_formatter ENC1 gt state_in state ENC1 gt
47. Void option Nicolas Lain TEC EDM 20 Research on new SoC design Methodology using SystemC issue 1 revision 0 This thread is the main part of the module for each option the compressed data is calculated determines the best option and then calls the format data function Void get block int amp int amp sc uint NB BITS If the input FIFO is not empty then this function will read at its interface the next block 16 bytes in our case stored in this FIFO Void format data int sc_biguint J NB BITS sc biguint lt J NB_BITS 6 gt amp long amp int amp int This function will encapsulate the compressed data with some header corresponding to the best option ID Note that the function option is a thread which means that it is executed only once during simulation that s why most of them contain some loops for instance while end while and can be easily clocked by inserting some WAIT statements As seen earlier we chose to use blocking transactions that means for instance that if you read one input FIFO which does not have any data simulation will stop automatically without finishing the current thread or process unless you check that FIFO is empty and then you wait for its filling That may cause some difficulties concerning the last input data block to compress if the encoder does not know in advance how big the size of input data is it will be stuck at the last block of d
48. acted first Then the following datas will be decompressed with the corresponding code option ID and then sent to the post processor to recover original datas Reminds that once the code option ID was found in the compressed input datas the decoder unit still doesn t know how big the compressed datas will be Nicolas Lain TEC EDM 17 Research on new SoC design Methodology using SystemC issue revision 0 2 2 3 2 The postprocessor unit i Aj Xj The inverse mapper function can be expressed as if lt 20 Ss when 6 is even A 7 du when 6 is odd if 20 A 0 when O Xi Xin 0 when O2 Xmax Xi Where 0 muc Ax pn WE 2 3 Implementations 2 3 1 IMPLEMENTATION IN TLM MODEL 2 3 1 1 Encoder The implementation of the rice compression algorithm in this level was described previously following a top down approach As mentioned earlier the TLM level is very close syntax language speaking from the pure Rice algorithm in C we re just using a sub library SystemC which is well tuned for hardware implementation Data transfers are modeled as transactions such as read and write Concerning read and write transactions we chose to use blocking transactions instead of non blocking transactions because it requires less communication handling Nicolas Lain TEC EDM 18 Research on new SoC design Methodology using SystemC issue 1 revision 0 Typically we declare the cha
49. al IP to one OCP Master for example OCP MASTER IN but in our case the IP is defined externally to the OCP if someone wants later connect the Rice IP to one other interface protocol How does each interface work The OCP MASTER IN does contain an OCP master block OCP data port generating external data READ requests a master FIFO module storing the data read and one OCP Target block used for configuration port OCP configuration port It is able to access any memory independently to perform READ transfers on the bus in order to feed the IP with uncompressed datas The advantage of this interface is that the access to the memory does not require a host processor that s basically what we call the DMA protocol Direct Memory Access used by each OCP Master interface The OCP MASTER OUT is quite similar as the input interface For each interface the size of the FIFO was set to 64 bytes length Since the Compression IP accepts data of 8 bits wide and that each transaction on the data bus is 32 wide the FIFO module in each interface has been modified to make the conversion 32 bits gt 8 bits and 8 bits gt 32 bits with the introduction of a state machine in each interface Below is displayed the configuration registers for each OCP Master unit these registers can be directly overwritten by a host processor or even a GUI or API for debug purposes Note that these values were optimized for a compression of picture of 15625 blocks 250kByte
50. arget vhd 2 src VHDL delivery ip creator ocp dataflow target 1 vhd 2 src VHDL delivery ip creator ocp dataflow master vhd 2 src VHDL delivery ip creator ocp request fifo vhd 2 src VHDL delivery ip creator ocp response fifo vhd 2 src VHDL delivery ip creator Master Output FIFO modified vhd 2 src VHDL delivery ip creator Master Output FIFO modified rice vhd 2 src VHDL delivery ip creator Master Input FIFO modified rice vhd 2 src VHDL delivery ip creator memlike fsm 3 vhd 2 src VHDL delivery ip creator memlike fsm 1 vhd 2 src VHDL delivery ip creator IPCreator pkg vhd 2 src VHDL delivery prosilog functions package vhd add file vhdl lib prosilog src SoC rice soc VHDL AHB decoder 2 vhd add file vhdl lib prosilog src SoC rice soc VHDL AHB decoder boot 2 vhd add file vhdl lib prosilog src SoC rice soc VHDL timing wheel 2 vhd add file vhdl lib prosilog src SoC rice soc VHDL Request multiplexor d4 m5 vhd add file vhdl lib prosilog src SoC rice soc VHDL Response multiplexor d4 e9 vhd add file vhdl lib prosilog src SoC rice soc VHDL AHB arbiter 2 vhd add file vhdl lib prosilog src SoC rice soc VHDL AHB controller 2 vhd add file vhdl lib work src SoC rice soc VHDL ahb controller vhd add file vhdl lib prosilog src SoC rice soc VHDL APB bridge 1 vhd add file vhdl lib work src SoC rice soc VHDL apb controller soc vhd add file vhdl lib work
51. ata and thus will not compress it That s why before starting compression the encoder needs to check the total length of input data in terms of block In order to compress a data block 16 samples of 8 bits each 128 bits we need to use big unsigned integers instead of normal unsigned integers limited to 32 bits wide Indeed before determining the best option for each block full data first is required The most difficult part in coding the TLM encoder was about the formatting part since the output port is only 8 bits wide the compressed data has to be divided its length is an integer ranged between 6 and 132 bits into byte Compress d dath block A C mpressed data bldck B 1 1 1 D Y 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Output byte Concatenation between bits of blocks A amp B The problem comes from the fact that compressed data may be not a multiple of 8 in this case we need to save the last bits until 8 bits and wait for the next data block then this last byte will be sent followed directly with the compressed data of the next block That is why we need to know the total input number of blocks to compress otherwise the last byte of the last block may not be sent to the output 2 3 1 2 Decoder As seen before the decoder is composed of a decoder engine and a postprocessor unit The TLM decoder interface is even simpler than TLM encoder interface Nicolas Lain TEC EDM 21 Researc
52. ata in rtl data to preprocess rtl tb encoder bothl nb blocks tocompress nb blocks tocompress tb encoder bothl compression end compression end tb encoder bothl data compressed log file data compressed log adapter inl clk clk adapter inl tlm2rtl rice data in data to preprocess rtl adapter inl data in rtl data in adapter inl data ready in data ready in adapter inl data accept in data accept in top encoder rtl INST clk clk top encoder rtl INST reset rst top encoder rtl INST data ready in data ready in top encoder rtl INST data accept in data accept in top encoder rtl INST data in data in top encoder rtl INST data out rtl data out top encoder rtl INST data ready out data ready out top encoder rtl INST data accept out data accept out top encoder rtl INST nb blocks tocompress nb blocks tocompress top encoder rtl INST compression end compression end TLM top encoder goldl enable preprocessor enable preprocessor top encoder goldl enable encoder enable encoder top encoder goldl enc data in data to preprocess tlm top encoder goldl enc data out data compressed top encoder goldl enc data out log file data compressed log top decoder goldl enable decoder enable decoder top decoder goldl enable postprocessor enable postprocessor top decoder goldl dec data in data compressed top decoder goldl dec data out tlm data top d
53. b leon grlibo src lib leon grlibo src lib leon grlibo src lib leon grlib0 15 src lib leon leon3 top vhd src lib leon grlib0 15 src lib slave ram gaisl src IP RICE vhdl src rt src IP RICE vhdl src rt src IP RICE vhdl src rt src IP RICE vhdl src rt src IP RICE vhdl src rt src IP RICE vhdl src rt src SoC rice soc softwa src lib ocp ocp32 Rice_ src lib ocp ocp32 Rice_ src lib ocp ocp32 OCP t src lib ocp ocp32 OCP t src lib mem ctrl OCP2AS src 1ib ocp OCP prom vhd src lib leon simple irq vhd 8rc lib SpW spw v12 lib tech actel comp actel components vhd lib grlib amba amba vhd 1ib grlib stdlib stdlib vhd lib grlib tech tech vhd lib grlib modgen multlib vhd lib grlib modgen leaves vhd 15 lib gaisler arith arith vhd 15 lib gaisler arith div32 vhd 15 lib gaisler arith mul32 vhd 15 1ib gaisler memory memory vhd 15 lib gaisler memory mem gen vhd 15 lib gaisler memory mem gen gen vhd 15 lib gaisler memory mem actel vhd 15 lib gaisler memory mem actel gen vhd 15 lib gaisler memory mem xilinx vhd 15 lib gaisler memory mem xilinx gen vhd 15 lib gaisler memory mem virage vhd 15 lib gaisler memory mem virage gen vhd 15 lib gaisler memory syncram vhd 15 lib gaisler memory syncram 2p vhd 15 lib gaisler memory syncram dp vhd 15 lib gaisler memory regfile 3p vhd ib fpu libfpu libfpu vhd 15 lib gaisler leon3 leon3 vhd 15 lib gaisler leon3 mmuconfig vhd
54. could be carried out with the LEON3 processor stored into the PROM The resulting effect will be an increase of the clock frequency since the formatting part may be software oriented However due to the lack of time this part could have not been done during the project Nicolas Lain TEC EDM 48 Research on new SoC design Methodology using SystemC issue 1 revision 0 4 CONCLUSION 4 1 Results regarding specifications 4 1 STEPS REACHED At the end of the study a complete system design flow with SystemC has been established In more details the following steps were successfully accomplished TLM model of the Rice compression algorithm encoder and decoder Set up the testing environment testbench and test 1 0 files debug tools Refine by hand the encoder in a RTL model Set up the dual abstraction levels simulation Validate the lossless data compression IP Implement a System On Chip with the OCP interfaced IP combined with a SpaceWire for data transfers Post Place amp Route Simulation was successful e Writing a full documentation about the details of the new design methodology and provide easy to use source files VHDL SystemC environments for the compression IP and the resulting System On Chip 4 2 BENEFITS OF THE SYSTEMC DESIGN METHODOLOGY The development of SystemC for system modeling and design is something enabling technology for top down iterative system design Also the development of the co
55. d by the name TLM model is based on transaction monitoring and recording a testbench generates stimuli and sends them to the DUT Design Under Test without taking care about communication implementation both entities TESTBENCH MODULE 1 sign Under Test TLM model will then be used for verification as previously seen as a golden reference verification will take place with comparison between results from golden reference model and refined model of the DUT which could be either TLM or RTL level model Note that the refinement of the DUT also needs the introduction of adapters connected to the testbench However having a constant testbench is crucial for design exploration Indeed if the testbench is modified during the different steps of the design flow and if at the same time some change is made to the DUT then it is difficult to conduct reliable experiments We chose to start design flow of the lossless compression data module with the implementation of this level Principal benefits that we can expect are Faster compared to RTL models Simpler to design and set up during simulation Time to implementation reduced significantly 1 5 3 REGISTER TRANSFER LEVEL MODELING RTL models will describe hardware and contain a full functional description of the algorithm moreover every signals buses and registers values are defined at every clock cycle The main difficult part when writing RTL code is to keep in mind that we have to write a
56. dd file vhdl lib work add file vhdl lib work add file vhdl lib work add file vhdl lib work add file vhdl lib work add file vhdl lib work Others add file vhdl lib work add file vhdl lib work add file vhdl lib work add file vhdl lib work add file vhdl lib work add file vhdl lib work add file vhdl lib work add file vhdl lib work add file vhdl lib amba lib LE Spacewire files Nicolas Lain TEC EDM SSSSSSSLSSSSSSSSSESSSSSSSSSSSSSSSS src lib leon grlib0 15 l src lib leon grlib0 15 src lib leon grlib0 15 src lib leon grlib0 15 src lib leon grlib0 15 I src lib leon grlib0 15 src lib leon grlibo src lib leon grlibo src lib leon grlibo src lib leon grlibo src lib leon grlibo src lib leon grlibo src lib leon grlibo src lib leon grlibo src lib leon grlibo src lib leon grlibo src lib leon grlibo src lib leon grlibo src lib leon grlibo src lib leon grlibo src lib leon grlibo src lib leon grlibo rc lib leon grlib0 15 1 src lib leon grlib0 src lib leon grlibo src lib leon grlibo src lib leon grlibo src lib leon grlibo src lib leon grlibo src lib leon grlibo src lib leon grlibo src lib leon grlib0 src lib leon grlib0 15 src lib leon grlib0 src lib leon grlibo src lib leon grlibo src lib leon grlibo src li
57. e S a Research on new SoC design Methodology using SystemC issue revision 0 RESEARCH ON NEW SOC DESIGN METHODOLOGY USING SYSTEMC END OF MASTERE STUDIES PROJECT SUPAERO COLE NATIONALE SUPERIEURE DE L AERONAUTIQUE ET DE L ESPACE prepared by pr par par Nicolas Lain reference reference issue dition 1 revision r vision date of issue date d dition status tat Final Document type type de document Final stage report European Space Agency Agence spatiale europ enne ESTEC final doc Keplerlaan 1 2201 AZ Noordwijk The Netherlands Tel 31 71 5656565 Fax 31 71 5656040 e S a Research on new SoC design Methodology using SystemC issue 1 revision 0 page ii of vi APPROVAL Title issue 1 revision O titre issue revision author Nicolas Laine date auteur date approved by date approuv by date CHANGE LOG reason for change raison du changement issue issue revision revision date date CHANGE RECORD Issue 1 Revision 0 reason for change raison du changement page s page s paragraph s paragraph s ii esa ABSTRACT Until a few years ago Register Transfer Level RTL corresponding to the hardware implementation was sufficient to enable designers to handle with the complexity of integrated circuits IC But the sheer complexity of current s System On Chip SoC combined with a rise in IP reuse has made an upward shift in abstraction a necessity System
58. e to be replaced with handshake signals such as Port Name Direction Description Clk IN IP Clock Resetn IN IP Asynchronous reset negative edge sensitive COMMUNICATION HANDSHAKE PORTS data ready in IN The Input initiator says if ready or not data n IN Incoming datas 8 bits wide in our case data accept in OUT The IP accepts or not incoming datas data ready out OUT The IP has ready datas at the output data out OUT Outputting datas data accept out IN The output receiver says if ready to receive datas or not PARAMETER PORTS Nbr blocks to compress IN Total number of blocks to compress Compression end OUT Set to 1 when all blocks have been compressed and sentto the output To handle this handshake communication we need a new entity in our compression module which will be dedicated to the IP s interface In our case this job is carried out with a finite state machine Nicolas Lain TEC EDM 25 Research on new SoC design Methodology using SystemC issue 1 revision 0 2 3 2 2 Implementation of the RTL encoder DATA READY IN DATA ACCEPT OUT FSM VALID OUT d DATA READY OUT ENABLE ENCODER i ENABLE FORMATIER En bi END DATA REACHED State Machine FSM DATA_ACCEPT_IN ENABLE_PREPROCESSOR STATE OUT DATA IN 8 700 000 CLK RESETn
59. ecoder gold2 enable decoder enable decoder top decoder gold2 enable postprocessor enable postprocessor top decoder gold2 dec data in rtl2tlm data out top decoder gold2 dec data out rtl data adapter outl clk clk adapter outl data ready out data ready out adapter outl data accept out data accept out adapter outl rtl rice data out rtl data out adapter outl rtl2tlm rice data out rtl2tlm data out checkerl rst rst checkerl enable decoder enable decoder checkerl enable postprocessor enable postprocessor checkerl tlm rice data i tlm data checkerl rtl rice data i rtl data checkerl stop simulation stop simu checkerl compression end compression end di SC_MODULE_EXPORT rice rtl vhdl endif Nicolas Lain TEC EDM 60 Appendix 4 Compilation library script for Research on new SoC design Methodology using SystemC issue revision 0 the final SoC and testbench Modelsim Script for compilation of System On Chip based on Leon3 coupled with Rice IP SpW Astrium N Laine TEC EDM 15 08 2005 set internal modelsim variable for this do file set magillemdir env MAGILLEMROOT set rice dir IP RICE set xilinxdir env XILINX set syndir C Program Files Synplicity set src rice soc rice soc set src init initiator setting compiled library path set lib all dir compiled libs compiled libs v58 set lib soc compiled libs
60. ee Appendix 2 for the source code of each adapter Adapter RTL gt TLM It converts RTL handshake signals from the IP to SC_FIFO signal Both length average of gap and burst can also be selected by the user Note that also data_out is dumped into a file data_out _ gt data_ready_out sc_fifo_out data_out E data_accept_out 2 4 3 3 Checker to compare results between RTL and TLM Nicolas Lain TEC EDM 33 Research on new SoC design Methodology using SystemC issue 1 revision 0 data out from TLM stop simulation compression end data out from RTL reset The checker compares results from TLM and RTL levels Some extra signals are required for the TLM decoder two decoders one for decoding TLM encoder data and the other one for the RTL encoder The compression end signal coming from the RTL encoder will arrive as soon as the last block of data was handled If results are not the same then stop simulation will go high and may be used for instance as a trigger to stop the simulation A checker is not required in the validation process but it is just a way to speed the verification up 2 5 Translation RTL SystemC to RTL VHDL 2 5 1 GOALS Following a typical top down architecture using SystemC after designing in RTL level with SystemC the data compression encoder the design flow requires the translation into RTL VHDL for synthesize since up to now no tool on the market is able
61. eference sample is missing Remainder Of Segment ROS is missing for the Zero Block option Data packetization module according to CCSDS recommended data packet format A pre existing IP for encapsulating CCSDS packet PTME is already on the ESA market Nicolas Lain TEC EDM 28 Research on new SoC design Methodology using SystemC issue 1 revision 0 2 4 Simulation and validation of the Design Under Test 24 1 DEBUG ISSUES e There is right now no debugger tool for SystemC based module To debug SystemC code we can use some new debugger such as DDD furnished with NC Sim or internal debugger in Modelsim However it s kind of difficult to debug using these tools in a quick way without putting some flags like cout or printf in your code e Moreover and as seen before there is no possibility to display local variables defined in a process in waveforms since there are only defined during execution of the process 24 2 TLM MODEL VALIDATION 2 4 2 1 Using Microsoft Visual Studio You can use Microsoft Visual C to design your SystemC module before you need to set up the tool for SystemC files Installing To Your Local Computer 1 The SystemC distribution includes project and workspace files for MS Visual C If you use these project and workspace files the SystemC source files are available to your new project For Visual C 6 0 the project and workspace files are located in directory systemc
62. enc_data_in prep_data_out ENC1 gt enc_data_out data_out ENC1 gt stop_run stop ENC1 gt enc_data_valid enc_data_valid ENC1 gt nb_blocks_tocompress nb blocks tocompress ENCl end data reached end data reached ENC1 compression end end SC METHOD valid register sensitive enc data valid fsm valid out end void valid register Nicolas Lain TEC EDM 56 Research on new SoC design Methodology using SystemC issue 1 revision 0 Appendix 2 Adapters TLM gt RTL RTL gt TLM Adapt_in h Adapter TLM gt RTL prototype TILTALTLELATTT LAT TLL ATLL EAT ALATA TTT TATA AAT ATTA AY ERA 114 SC SIGNAL to SC FIFO ADAPTER 8 Bits 11g ANN include systemc h include global h SC MODULE adapter in sc in lt bool gt Sc fifo in sc uint lt 8 gt gt sc out sc 1v 8 gt gt sc out lt bool gt sc in bool void init void adapt in tlm2rtl rice data in data in rtl JT clk data_ready_in data accept in void return counter int amp ready in cnt int amp flag ready in int amp ready in RER EEE IEEE HF TH EI LEE TH HT TT gg COUNTER FOR READY_IN BURST GENERATION RER EEE TH III EL TT TTT ATTA ATT if else else else else int randomize time if if if ready in cnt gt 0 amp amp flag ready in 0 INPUT FIFO is ready ready in cnt ready in l ready in cnt gt 0 amp amp
63. ept out accept out if data accept out read amp amp data ready out read data o sc uint lt 8 rtl rice data out read rtl2tlm rice data out write data 0 FOR DEBUG ONLY fout lt lt data o to string SC BIN US false HIMMEL G TH THL TI lt lt flush lt lt endl data_accept_out write accept_out Nicolas Lain TEC EDM rout Cannot open Output compressed data file lt lt endl YLIT Binary Display 58 Research on new SoC design Methodology using SystemC issue 1 revision 0 Annexe 3 Top SystemC testbench to compare results between TLM and RTL compressed datas CCCII III II III III II III III II IOI IOI II II II II II II II II IOI II II II II He RTL TLM Simulation Model of Rice compression IP SystemC Model ni RTL amp TLM compressed bytes are compared A mismatch is indicated when stop simu goes high N Laine FOCI III ICICI IIIS ICICI RAR A III f include systemc h include lt iostream gt include systemc src global h 117 CHOOSE ONE TO BE SIMULATED HM II include top_encoder_rtl h FOR VHDL DESIGN include systemc src rtl encoder top_encoder_rtl h JUDITH TH TH TH FFF MB Gg M HT TH THL TT LI bash rt FOR SYSTEMC DESIGN include systemc src golden ref encoder top encoder gold h include systemc src golden ref decoder top decoder gold h include systemc src bench tb encoder bo
64. h on new SoC design Methodology using SystemC issue 1 revision 0 Name Direction Type Description enable decoder IN lt bool gt Enables the decoder amp postprocessor dec_data_in IN sc_fifo_in lt sc_uint lt 8 gt gt Input data to decompress 8 bits dec_data_out OUT sc_fifo_in lt sc_uint lt 8 gt gt Output uncompressed data 8 bits Below are showed functions or processes used for the decoder and brief description of them SC_MODULE SystemC module Actions or processes decoder_gold Void init This thread initializes the decoder no compression option is chosen by default Void identif_option This thread is determining the code option corresponding to the input data knowing that the ID option is always at the beginning of a new CDS Coded Data Set compressed data format Then it calls the function decode_CDS to decode the current CDS with the appropriate compression option Void decode CDS int int amp sc_uint lt NB_BlTS gt amp sc_uint lt NB_BITS gt It will decode the CDS with the corresponding option ID The output of this function is the output uncompressed datas stored in an array of unsigned integers of 8 bits each Void check_index sc_uint lt NB_BITS gt amp int amp If the bit index is 0 then we finished handling the current byte and we need to get one new byte at the input The bit index will be then set to 7 The main difference in the TLM algorit
65. hm with the encoder is that here we are working with byte to byte unlike the encoder with block to block Indeed the decoder is not able to know in advance the size of the input compressed data 2 3 1 3 Top and testbench top is the use of both the encoder and the decoder in TLM level It does consist of a main function in SystemC which instantiates the encoder decoder and testbench In order to be able to use our TLM level we finally need to build the testbench which will have 2 goals sends input uncompressed data to the encoder and receives the output uncompressed data from the decoder and then compares them The testbench has a fundamental goal here since it will be used again with the RTL implementation of the encoder with some external refinement such as the introduction of adapters between the testbench and the RTL design under test We will come back later on about the adapters when dealing with the TLM RTL co simulation include global h SC_MODULE tb_encoder_both PORTS sc_out lt bool gt reset sc_out lt bool gt enable_preprocessor sc out lt bool gt enable encoder sc fifo out sc uint 8 gt gt data in tlm FIFO Outto the TLM Encoder sc fifo out sc uint 8 gt gt data in rtl FIFO Out to the RTL Encoder sc out sc lv 16 nb blocks tocompress sc in lt bool gt compression end Nicolas Lain TEC EDM 22 Research on new SoC design Methodology usi
66. ictor enable_encoder IN lt bool gt Enables the adaptive encoder part enc_data_in IN sc_fifo_in lt sc_uint lt 8 gt gt Input data to compress 8 bits enc_data_out OUT sc_fifo_in lt sc_uint lt 8 gt gt Output compressed data 8 bits enc data out log file OUT sc_fifo_in lt sc_uint lt 8 gt gt Copy of the previous one for dumping file The top which is defined as the definition of the black box of the encoder is showed below in details include global h include preprocessor_gold h include encoder_gold h SC_MODULE top_encoder_gold PORTS DECLARATION Nicolas Lain TEC EDM 19 Research on new SoC design Methodology using SystemC issue 1 revision 0 sc in lt bool gt enable_preprocessor sc_in lt bool gt enable encoder sc fifo in sc uint 8 enc data in sc fifo out sc uint lt 8 gt gt enc data out sc fifo out sc uint lt 8 gt gt enc data out log file INSTANCIATION preprocessor gold PREP GOLD1 encoder gold ENCODER GOLD1 INTERNAL SIGNALS amp amp FIFO S sc fifo lt sc_uint lt 8 gt gt prep_data_out CONSTRUCTOR SC CTOR top encoder gold PREP GOLD1 new preprocessor gold preprocessor gold PREP_GOLD1 gt enable_preprocessor enable_preprocessor PREP_GOLD1 gt prep_data_in enc_data_in PREP_GOLD1 gt prep_data_out prep_data_out ENCODER_GOLD1 new encoder_gold encoder_gold
67. il the design has reached the RTL or netlist stage With the new high level synthesis tool backing up after the translation to RTL has been made A high level synthesis technology may bridge the gap between a GPL representation and an HDL representation including also the gap between algorithmic level and register transfer level It will improve both the time to market and the quality of the target design Nicolas Lain TEC EDM 5 AHB APB AMBA BCA CCSDS CPU DMA DUT ESA ESTEC ESL FSM FPGA GUI IC OSCI OCP PCA RTL soc SPW SRAM TF TLM UTF Nicolas Lain TEC EDM Research on new SoC design Methodology using SystemC issue 1 revision 0 GLOSSARY Advanced High Performance Bus Advanced Peripheral Bus Open standard on chip bus specification Bus Cycle Accurate Consultative Committee for Space Data System Central Processor Unit Direct Memory Access Design under Test European Space Agency European Space Research and Technology Centre Electronic System Level Finite State Machine Field Programmable Gate Array Graphical User Interface Integrated Circuit Open SystemC Initiative Open Core Protocol Pin Cycle Accurate Register Transfer Level System On a Chip Spacewire ESA s IP Static Random Access Memory Timed Functional Transaction Level Modeling Untimed Functional 52 1 2 3 4 5 6 7 8 9 10 Nic
68. ing OCP Interface 32 bits for the IP Rice RAA AA AA AA AA BA AA A AA AA AA AA A AA AAA AAA AAA HE GE vcom work work 93 lib ocp ocp32 Rice to32 RX vhd vcom work work 93 lib ocp ocp32 Rice to32 TX vhd vcom work work 93 lib ocp ocp32 OCP top encoder rtl masterl vhd vcom work work 93 lib ocp ocp32 OCP top encoder rtl master2 vhd AAA AAA AA AAA A AAA Compiling OCP prom AAA AAA E AA UHR HHH HE vcom 93 work work src rice soc software boot program vhd vcom 93 work work lib ocp OCP prom vhd HAE HEAR HAE HAE ERE TEE ERE REESE RE RE Compiling OCP MEMORY CTRL HERAT HAE DEA HAE ERATE ERE AAA vcom work work 93 lib mem ctrl OCP2AS7C 32 vhd AAA AAA AA AAA AA A AAA AA Compiling APB system echo compile apb files AAA AAA AAA AA AAA AAA AA vcom 93 work work src_rice_soc VHDL APB_bridge_1 vhd Nicolas Lain TEC EDM 61 vcom 93 work work src rice soc VHDL apb controller soc vhd AAA AAA AA AAA AA AA AAA A AE Compiling IP bridge echo compile IP bridge AAA AIR AA AA AAC AA AA AAA AE vcom 93 work work src rice soc VHDL ipbridge vhd AAA AAA AA AAA AA AAA AAA AE Compiling SPW12 echo compile ASTRIUM SPACEWIRE AAA AAA AAC AA AAA AA AAA ERLE EE do lib SpW compile spwl2 do AAA AAA AA AAA AA AAA AA AE Compiling SpW12 top echo compile SpW12 top AAA AAA AA AAA AA AA AAA AE vcom 93 work work
69. le vhdl lib spw v12 add file vhdl lib spw v12 add file vhdl lib spw v12 add file vhdl lib spw v12 add file vhdl lib spw v12 add file vhdl lib spw v12 add file vhdl lib spw v12 add file vhdl lib spw v12 add file vhdl lib spw v12 add file vhdl lib spw v12 add file vhdl lib spw v12 add file vhdl lib spw v12 add file vhdl lib spw v12 add file vhdl lib spw v12 add file vhdl lib spw v12 add file vhdl lib spw v12 add file vhdl lib spw v12 add file vhdl lib spw v12 add file vhdl lib spw v12 add file vhdl lib spw v12 add file vhdl lib spw v12 add file vhdl lib spw v12 add file vhdl lib spw v12 add file vhdl lib spw v12 add file vhdl lib spw v12 add file vhdl lib work Top files add file vhdl lib work add file constraint implementation rev rice soci impl add rev rice soci device options set option technology VIRTEX E set option set option set option compilation mapping options set option set option set option set option set option part XCV2000E package BG560 speed grade 6 default enum encoding default symbolic fsm compiler 1 resource sharing 1 use fsm explorer 0 top module rice rtl vhdl map options set_option set_option set_option set_option set_option set_option set_option set_option set_option set_option set_option frequency 100 000 run_prop_extract 1 fanout_limit 100 disable io insertion 0 pipe 1
70. ls appeared twice in the generated VHDL testbench file 3 3 OCP Interface implementation for IP Rice 3 3 1 IP CREATOR TOOL The new design methodology using SystemC has one other important key the designer is still building an IP with an IP re use mind after A tool from Prosilog IP Creator is able to generate the source code in RTL level of the IP with a OCP corresponding interface OCP is AMBA bus compliant meaning that it can be connected directly to one AMBA bus controller IP Creator 1 3 OCP version Ca X IfF description file op encoder rl mastert ifd MEMORY INTERFACE DEFINITION Output directory C iworkisrolibiocpiocn321 Memory FIFO Rice to32 TX IP Name Master In P top encoder rtl master1 Top level Name TARGET Data Width MASTER Data Width IP Interface Properties FIFO depth B4 MASTER Address Width Synchronous O Asynchronous C Extern IP IP Ports Direction RangeNwidth Interface Semantic Extern ACEEPT loutput DIN_ACCEPT Ll input 31 0 DN Li input DIN_RDY O input P_CLOCK Ll input __ RESET_ m dita output fo INONE v early i loutput NONE M RTE Lia 1 ENS Ez Console writen acarot Removepot Remove an The user can choose define the IP top level name Interface IP the FIFO depth in number of bytes cl
71. m in this report 2 2 2 THE SOURCE ENCODER The Lossless source coder consists of two separate functional parts the preprocessor and the adaptive entropy coder as shown below Input Data Block x y Coded Block X 2X4 X2 XJ 01 67 2 2 2 1 Preprocessor The preprocessor does a reversible function to input data samples x to produce a preferred source Nicolas Lain TEC EDM 13 Research on new SoC design Methodology using SystemC issue revision 0 6 26 6 0 6 where each i is an n bit integer 0 lt 6i lt 2n 1 For an ideal preprocessing stage will have the following properties a The 87 is statistically independent and identically distributed b The preferred probability pm that any sample 6 will take on integer value m is a non increasing function of value m for m 0 1 2n 1 Its architecture can be summarized within the following schematic Prediction Error Preprocessed Samples The preprocessor function is a reversible operation and in general the best lossless preprocessor will meet the above conditions and produce the lowest entropy which is a measure of the smallest average number of bits that can be used to represent each sample A X Xi 2 O lt A lt 242 1 0 lt A lt 0 6 A otherwise X Xi With x min max where 0 min x x 0 and x 2 1 255 in our case min
72. mmunication layer in SystemC along with the corresponding RTL model has given SystemC an effective means of expressing designs at several levels of abstraction TLM implementation proved to be a nice technique to overcome the gap present in the traditional design flow between algorithmic and RTL models All benefits that SystemC brings may open doors to improved architecture exploration and performance optimization sooner during the project elaboration with better performance 4 1 3 POINTS TO BE STILL CLARIFIED gt The notion of TLM Level is not really clear it can include several models depending on the abstraction degree For instance we can split TLM regarding if the design is either untimed or timed It has to be standardized for creating some specific models in order for people to be able to build IP that they can exchange The translation by hand from TLM level to RTL design is not straight forward and may go up the duration of the project A solution to this could be a design flow around a high level synthesis cf 4 2 What next Nicolas Lain TEC EDM 49 Research on new SoC design Methodology using SystemC issue 1 revision 0 4 1 4 PROJECT TIME ORGANIZATION Below I showed the approximate project time organization between April 2005 and September 2005 The main part was concerning the research on the new design methodology with the implementation of the Rice compression IP 25 20 e DEFINIT
73. model refinement from communication refinement is a powerful feature of SystemC Nicolas Lain TEC EDM 24 Research on new SoC design Methodology using SystemC issue 1 revision 0 In order to proceed there are several general areas to pay attention e Algorithmic descriptions untimed need to be replaced with register transfer accurate descriptions For example if the root square C function sgrf is used in the TLM level it needs to be replaced or refined with a collection of simple functions that can be performed by an embedded microprocessor or directly implemented in hardware e Abstract channels like sc fifo need also to be changed with hardware channels such like sc signal e If some C data types are present they need to be translated with SystemC data types for example unsigned int may become sc v 32 to define a tristate bus e User defined types not used in the Rice TLM implementation are not allowed anymore they also need to be replaced with SystemC types e Thread i e functions executed once during simulation has to be replaced into Methods i e functions executed every time a signal in the sensitivity list is changing In my case the biggest issue was to translate all transactional interfaces in TLM level implicit because the SystemC user doesn t have to care about interface handling at this level to an explicit request acknowledge handshake That means that every sc fifo ports will hav
74. n System Development En 20 RTL Synthesis 12 EN Expected project usage 10 20 30 40 50 60 70 80 90 100 Our first goal will be to know what SystemC could bring new compared with a traditional flow in our case the architecture exploration when designing a System On Chip See 2 1 1 for its definition could be an interesting usage But on a first outlook implementing a new transaction level modeling may be the most interesting point since it will overcome the gap between RTL and TLM level Nicolas Lain TEC EDM 2 Research on new SoC design Methodology using SystemC issue 1 revision 0 Some new extensions from the standard C language were added such as Time notion Parallel execution of entity called Processes Introduction of data types An entity can both describe a behaviour and hierarchy Several models levels are used in SystemC to describe a component The most important ones are listed below Functional Model Transaction Level Model TLM Register Transfer Level RTL model These models come with terms to characterize them Untimed Functional UTF UTF refers both the model interface and the model functionality Time is not used for execution Timed Functional TF TF refers to both the model interface and the model functionality Time is used for execution Bus Cycle Accurate BCA BCA refers to the model interface and not the model functionality Timing is cycle acc
75. nal uncompressed bits to the number of compressed bits including overhead bits necessary for signalling parameters After compression has been performed the variable length output is then packetized using CCSDS packet format Then these packets will be transmitted through a space to ground communication link to a data sink on the ground using a packet data system Nicolas Lain TEC EDM 12 Research on new SoC design Methodology using SystemC issue revision 0 J 7p D RN On Board i Ground We chose this simple algorithm in our case in order to validate a new design methodology Consequently note that all details of this algorithm provided in the CCSDS report concerning lossless data compression cf 2 and 3 were not fully implemented i e a specified resolution for input data samples is required or also the fact that the CCSDS packet formatting module was not done during the trainee period gt A Lossy source coding method removes some of the source information content along with the redundancy The original data cannot be fully restored and data distortion occurs However if some distortion can be tolerated lossy source coding generally achieves a higher compression ratio By controlling the amount of acceptable distortion and compression this technique may enable acquisition and dissemination of mission data within a critical time span We will not attempt to explain the theory underlying the operation of the algorith
76. nclusion amp future possible improvements ss 28 2 4 Simulation and validation of the Design Under Test 29 2 4 1 Debug SS asses oe tae Ste da ssn Qs bc eta cusan da hate dU A 29 2 4 2 TEM model Validation ettet reni teet OR aW FY ee dde aei tap een 29 242 1 Using Microsoft Visual Studio a E pare Eee pa un abel QU TE a NF 29 2 4 2 2 Using Mentor Graphics ModelsimG nt tote e Ee e pee ete be rb ed ae eet 31 issue 1 revision 0 C e S a Research on new SoC design Methodology using SystemC page vi of vi 2 4 3 Iy cL 3n daHon ss ne a ee ne 32 243 1 Testbench with several levels of abstractio uu uu nine NG GAA odid NA GYG YY 32 2 4 3 2 Adapters needed for TLM gt RTL and RIE TLEM nrbt tarta FUD ges 32 2 4 3 3 Checker to compare results between RTL and TEM 33 2 5 Translation RTL SystemC to RTL VEDLE nea eene o d c te I ee ere ia Y AE UNE 34 2 5 1 C 34 2 5 2 Issues and recommendations sivc ed re SE e opa yd Nyd R8 34 2 5 3 Conclusion on the translatigon io o dece i utt idend enr ai eat ec pt a tru be de aea d edd 36 2 0 Results a sa 37 2 6 1 COnIpressioti Tatio uu hs stare dn DY dd DI CY YDY FAN 37 2 6 2 Comparison TLM SystemC vs RTL VHF Wd a e aaa ote ard 38 2 6 3 Setting time of the different steps 2s eu S be EOS e REDE RIRs A rp a b MA Aem 39 3 IP S IMPLEM
77. ng amp validation 3096 SystemC RTL Encoder coding amp validation 4096 Refinement for the translation to RTL VHDL Encoder 2096 Synthesis validation 1096 The refinement TLM to RTL for the encoder was not straight forward see 2 3 2 1 TLM to RTL Refinement since the TLM level does not include any timing issues and uses only abstract channels for communicate the biggest issue was the implementation of an explicit state machine Note that the first aim of a higher abstraction model here was to validate the algorithm However besides once the TLM model of the encoder was done in a more complex and reliable project the high abstract level of the IP would have been given to the system engineer in charge of interconnecting each IP on the SoC bus and exploring the miscellaneous architectures Nicolas Lain TEC EDM 39 Research on new SoC design Methodology using SystemC issue 1 revision 0 3 IP S IMPLEMENTATION ON THE EXISTING SOC 3 1 Goals Once the IP was implemented and tested using the new design methodology we needed validate the IP in a higher system level thus the first step was to check if the IP could work correctly when implemented in a System On Chip One important goal of this part of the project is also the possibility to interface the IP with one of the most common IP interface protocol OCP See section 3 3 1 for details concerning the interface encapsulation Encapsulation using OCP interface Se
78. ng SystemC issue 1 revision 0 sc fifo in lt sc_uint lt 8 gt gt data compressed log file THREADS void init void send tlm void send rtl long int get length input data void receive data INTERNAL SIGNALS sc string input file sc string output file int init finished int num block sent tlm int num block sent rtl int num byte received from tlm SC CTOR tb encoder both num block sent tlm num block sent rti num byte received from tlm init finished 0 input_file tests uncompressed_datas txt output_file tests RTL_VHDL compressed_datas txt SC_THREAD init SC THREAD send tlm SC THREAD send rtl SC THREAD receive data Above is showed the testbench module declaration for TLM validation However it will also be used as testbench for the RTL encoder First we can notice that there s no clock timing introduced in the ports definition but only an asynchronous reset port Basically the testbench is made around two main processes send data to the encoder and then receive its compressed data Two test files need to be declared one which contains input uncompressed datas in a RAW format i e each line is one byte in decimal value ranged between 0 and 255 the other one to store the resulting compressed data Note finally that all functions are used as threads i e executed only once during simulation and thus contain loops which
79. nnel by se fifo sc uint lt 8 gt gt CHANNEL it means a FIFO channel of unsigned integers values of 8 bits each and the length of the FIFO is set to 16 by default so a FIFO size of 16x8 bytes Then if we want to read in this channel first we need to check if the FIFO is not empty By declaring specialized port such as sc fifo in sc uint lt 8 gt gt CHANNEL1 IN the SystemC code to access the FIFO in such cases may be if CHANNEL1 IN num available 0 data in CHANNEL1 IN read else wait CLOCK PERIOD SC NS wait for one clock cycle if no data in the input FIFO Same thing for writing into a fifo using the following specialized port sc fifo out sc uint 8 CHANNEL1 OUT if CHANNEL1 OUT num free 0 CHANNEL1 OUT write data out else wait CLOCK PERIOD SC NS wait for one clock cycle if no more free spaces available in the output FIFO We can see through this example one more advantage of using SystemC TLM level authorizes some methods calls such as the checking of the number of available samples for reading port and number of free spaces for writing port As we saw previously the encoder can be separated between 2 parts the preprocessor and the encoder Below is reminded all the input output of the encoder engine at TLM Level Name Direction Type Description enable preprocessor IN lt bool gt Enables the preprocessor part one delay pred
80. ntation Below is showed a simple description of the download application environment A tool provided by Xilinx called mpact downloaded the corresponding program to the FPGA Nicolas Lain TEC EDM 47 Research on new SoC design Methodology using SystemC issue 1 revision 0 irtex E XCV2000E MEMORY CTRL LEON3 Core g PC1 43 Windows l PC2 Linux l l UART2 3 l l Debug I F l Debug l Support Unit GDB 3 6 Results One implementation was done on a FPGA Virtex E XCV200E running at 10 Mhz in a first try Unfortunately and due to lack of time the breadboard implementation part began only two weeks before the end of the stage the compression was not completely successful even through all the steps before reading from the SRAM was completely working The problem may come from the pinning associated to the SRAM and the configuration of the memory controller But still some datas were sent back by the Compression IP and the SpW However the post place and route simulation was working well and compression was done with 10 Mhz for the system clock and 40 Mhz for the SpW transfer clock To check if compressed datas were correct SystemC was still used in decoding these datas using the TLM decoder in order to retrieve original datas 3 7 Possible improvements Partitioning between software amp hardware the Rice encoder For instance the formatting part in the encoder unit
81. o used for functional verification using the power of C language In conclusion SystemC can have several models levels to describe the design and can be used both for modelling and verification of a system But when verification and implementation become very important an efficient methodology is required which involves the creation of a minimum number of models To achieve this on complex designs with adequate simulation performance high level models are not just needed to simulate the software on a model of the hardware but also to accelerate the process of modeling hardware IP in a bus independent 1 2 Traditional system design flow In traditional system design architectural design and hardware design are separated from each other In others words a gap in the development process exists between modelling and Register Transfer Level modelling This break may introduce errors in the translation from functional models to RTL models Nicolas Lain TEC EDM 4 Research on new SoC design Methodology using SystemC issue revision 0 1 3 Design flow using SystemC When starting from a very high abstraction level such as a functional model we need to refine our model to go through TLM models and finally to get a RTL model which can be synthesized and them mapped into the final model which will be at gate level typically written in VHDL or Verilog Abstraction level feedback Math software Algorithmic model
82. ock synchronous or not and finally the IP ports definition you can either specify if the port is a IP special port Control or Status registers or a specific FIFO port such as din_accept or din Then the user just needs to press the button to get the corresponding VHDL and Verilog source files Nicolas Lain TEC EDM 4 Research on new SoC design Methodology using SystemC issue 1 revision 0 3 3 2 IMPLEMENTATION AT RTL LEVEL OCP MASTER IN OCP MASTER OUT OCP Control Master Output FIFO modified DO EE oI a a 0T r r oc OCP Target ME Reguest part Response part OCP CONFIG PORT OCP CONFIG PORT The OCP implementation carried out for this project is showed above The compression IP is surrounded by two main FIFO like interfaces one for sending uncompressed data to the IP OCP MASTER IN and the other one for receiving compressed datas from the IP OCP MASTER OUT These interfaces were generated from IP Creator tool from Prosilog cf 3 4 1 IP Creator tool This tool was easy to use mainly because the user just needs to specify if he wishes a Master in or a Master out which kind of interface either Memory like or Fifo like and finally the size of every config registers Once this step is done we have to define corresponding IP ports Nicolas Lain TEC EDM 42 Research on new SoC design Methodology using SystemC issue 1 revision 0 The user has also the possibility to define an intern
83. olas Lain TEC EDM Research on new SoC design Methodology using SystemC issue 1 revision 0 References S Swan et al SystemC v2 0 1 Users Guide 2002 http www systemc org projects sitedocs document v201 Users guide en l Lossless Data Compression Report Concerning Space Data Systems Standards CCSDS 120 0 G 1 Green Book Issue 1 Washington D C CCSDS May 1997 Lossless Data Compression Report Concerning Space Data Systems Standards CCSDS 120 0 B 1 Blue Book Issue 1 Washington D C CCSDS May 1997 Bj rn Jonsson A JPEG Encoder in SystemC Thesis report Doulos Ltd Fundamentals of SystemC version 3 3 Golden Reference Guide Release 1 1 May 2002 http www doulos com Jiri Gaisler LEON3 Processor User s Manual Gaisler Research 2004 SPARC International Inc The SPARC Architecture Manual Version 8 Revision SAV080SI9308 Prosilog Magillem 2 1 SystemC Tutorial September 2004 Ver 1 0e http www prosilog com Prosilog Prosilog SystemC Compiler User s Guide Version 1 0 http www prosilog com Alan Ma and Allan Zacharda SystemC Utilizing SystemC for Design and Verification http www model com 53 Appendix 1 Appendix 2 Appendix 3 Appendix 4 Appendix 5 Appendix 6 Appendix 7 Research on new SoC design Methodology using SystemC issue 1 revision 0 Annexes Top files for the Rice encoder TLM and RTL SystemC Adapters TLM RTL RTL gt TLM Top SystemC testbench
84. osilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 Prosilog Magillem SE 2 2 src VHDL delivery split machine vhd 2 src VHDL delivery split machines vhd 2 src VHDL delivery ahb master wrapper datapath split vhd 2 src VHDL delivery ahb master wrapper fsm split vhd 2 src VHDL delivery ahb bvci slave machine split vhd 2 src VHDL delivery ahb bvci slave wrapper split vhd 2 src VHDL delivery ahb bvci slave wrapper vhd 2 src VHDL delivery ahb bvci slave wrapper wait vhd 2 src VHDL delivery ahb bvci slave machine wait vhd 2 src VHDL delivery ahb master wrapper split vhd 2 src VHDL delivery data width manager vhd 2 src VHDL delivery minififo synchrone vhd 2 src VHDL delivery pipeline stage vhd 2 src VHDL delivery bridge bvci 1 vhd 2 src VHDL delivery BVCI shortcut vhd 2 src VHDL delivery interconnect pkg vhd 2 src VHDL delivery Arbiter interface m5 vhd 2 src VHDL delivery default slave vhd 2 src VHDL delivery sub timing wheel vhd 2 src VHDL delivery BVCI OCP20 slave vhd 2 src VHDL delivery BVCI OCP20 master vhd 2 src VHDL delivery roundrobinsimple m5 vhd 2 src VHDL delivery ip creator counter vhd 2 src VHDL delivery ip creator dpram vhd 2 src VHDL delivery ip creator fifo vhd 2 src VHDL delivery fifo synchro vhd 2 src VHDL delivery ram vhd 2 src VHDL delivery ip creator ocp t
85. rtl encoder RTL Encoder source files I SoC System On Chip libraries I leon RB32 sram Simple SoC library debug_soc SoC with Systemc debug unit 1 both_soc Top testbench for rice soc SoC I initiator SoC simulation model for SpW Link l rice_soc SoC using SpW and Rice IP dgbug Debug directory for MS Visual C I l tice_tim Project files for TLM encoder tb p rice rtl Project files for RTL encoder tb rice rtl tlm Project files for RTL TLM comparison tb I synth Synthesis directory Synplify Pro 8 0 I rice Project files for Rice IP L___1 Soc Project files for SoC par Place amp route directory Xilinx I SE l I rice for Rice 1P Loo SoC for SoC tests Test files for simulation I examples of pictures Examples of pictures from CNES L RTL_VHDL Simulation results files when testing RTL Encoder TLM Simulation results files when testing TLM Encoder I SoC Simulation files when simulating SoC I sram SRAM memory contents 1 doc Documentation compiled libs Compiled libraries for Modelsim compiled libs v58 compiled libs v61 Work rice WOrk soc Nicolas Lain TEC EDM for Modelsim v5 8 for Modelsim v6 1 Rice compiled library SoC compiled library 66 Research on new SoC design Methodology using SystemC issue 1 revision 0 Appendix 7 Project time organization chart Apr May Jun Jul Aug 05 05
86. s Knowing that the OCP transaction unit is a word of 32 bits one input block would composed of 4 words each OCP MASTER IN OCP MASTER OUT Start address 0x00004000 0x00006000 End Address 0x00005FFF 0x00007FFF Transfer Length 15625 4 62500 words Infinite Mode Wrap addressing inactive Transfer Wrap addressing inactive Transfer length limited length unlimited Address Increment 4 4 Burst Length 8 bytes 1 2 block or 2 words 1 byte Threshold register 5 Number of empty slots bytes inthe 1 Minimal number of data received FIFO after which OCP read request are by FIFO before activation of OCP activated request 3 3 3 AT TLM LEVEL FOR VALIDATION PURPOSE One other possibility in the new design flow is once the TLM IP level is done and validated engineers can directly go through SoC architecture exploration and HW SW partitioning without waiting for the RTL IP design This is one of the biggest advantages of designing a higher abstract level However the introduction of TLM level in a pre existing RTL level design requires the introduction of adapters as seen previously Nicolas Lain TEC EDM 43 Research on new SoC design Methodology using SystemC issue 1 revision 0 data_ready_in data_accept_out data_out data_accept_in 3 4 SoC design using Magillem 3 4 1 ONE SIMPLE EXAMPLE OF SOC USING THE RICE IP AMBA Bus Controller ee aaa a 20CP Slave 2 0 P L 10CP Master 2
87. stant variables in parameters without any problems as shown below length tmp is non constant variable ranged between 0 and 8 for int i 0 i lt length tmp i MEM i MEM OLD il However when switching to RTL level the designer has to take care when using using non constant parameters in loops because it will not be synthesizable by commercial synthesis tool The previous code may be translated into this one for int i 0 i lt 8 itt f if i lt length tmp MEM i MEM OLD i gt Local variables vs member variables One other trap is when using member variables in SystemC SystemC distinguishes member variables from member or internal signals where as VHDL does not Thus if some member variables are defined into a SC MODULE the SystemC to VHDL converter will translate them into signals and they will be synchronous with the clock signal However member variables in SystemC are not synchronous with clock but are defined like local variables Nicolas Lain TEC EDM 35 Research on new SoC design Methodology using SystemC issue 1 revision 0 That s why it is recommended to use local variables defined in a process or function rather than using member variables defined in the SC MODULE header Moreover when more than one process is accessing a member variable it will not be synthesizable use signals instead RTL SystemC using member variables
88. t to validate the algorithm however in my case I did not choose to start with this model I started directly with TLM level because our first goal was to show a new design methodology and not to design a new super efficient compression module 1 5 2 TRANSACTION LEVEL MODELING Instead of driving the individual signals of a bus protocol the goal is to exchange only what is really necessary the data payload Data transfers are modelled as transactions read write operations Characteristics of TLM level Model Model behaviour is either timed or untimed algorithmic descriptions No pin level detail for interfaces Cycle accurate or not depending upon the level of modelling desired Since TLM model is not giving any pin level details for its interfaces model descriptions are much simpler and faster during simulation The implementation is event based that may be not clock driven When RTL level model is using hardware channels TLM level model will use abstract or elementary channels such as sc fifo in its most primitive form an implicit handshaking is done in TLM level model for communication with external buses of the design Where as RTL level model uses explicit handshaking i e with the implementation of request and acknowledge signals MODULE 1 Abstract channel Process A C semo Process B Nicolas Lain TEC EDM 7 Research on new SoC design Methodology using SystemC issue 1 revision 0 As specifie
89. t up of a System On Chip implementation according to the Rice encoder using Magillem Prosilog Implementation on the FPGA board 3 2 Presentation of the IP interconnection tool Magillem v2 3 Prosilog 3 2 1 TOOL PURPOSE The aim of this tool is to interconnect IP or entities dedicated to be mapped on a System On Chip so that the designer is not taking care of interface connection between IP and bus controllers anymore A library is furnished with the tool consisting of several VHDL files for special interfaces protocols such as OCP Master Slave protocols or the widely used AMBA bus controller interface Note that some TLM sources files are available also with the implementation of adapters or bridge OCP protocols to TLM FIFO signals 3 22 BUGS OR MISSING PARTS REPORTED These problems had been seen on the v2 3 of Magillem When two IP s are connected at each other with port A STD LOGIC for the first IP and port B BIT for the 2 one type s conversion are not automatically done when the top VHDL testbench is generated by Magillem Inthe AMBA Verification Platform the mask BE is not working properly Nicolas Lain TEC EDM 40 Research on new SoC design Methodology using SystemC issue 1 revision 0 When an 8 bits output port is connected to one other IP to a 32 bits input port the 24 highest bits are not set to 0 When importing the top VHDL Leon3 with Multi IP button some signa
90. t_out are still set to one during RUN mode the state machine will remain in this state However if one of these goes to 0 then we need to exit the RUN mode and switch to EXIT_RUN mode and SECOND mode which will handle last current data before finally going back to IDLE mode A dedicated state deals with too big compressed data at the output FORMAT_ONLY mode it is also used for instance when the compressed data has not been entirely sent at the output while a new block is arriving at the input If this special mode is run then only formatting compressed data and sent it to the output will work not preprocessor and encoder 2 3 3 CONCLUSION amp FUTURE POSSIBLE IMPROVEMENTS TLM implementation was much easier to design regarding the desired design flow it can use easily all C C benefits One of its great benefits is to get the model independent to communications As the time ran fast during this project I did not have time to implement entirely the Rice compression following the CCSDS recommendation cf 2 and 3 Below are listed some missing parts or extensions which were not implemented knowing that the first goal of the internship was to validate a new design methodology based on SystemC and not to get a complete design of a compression algorithm which already exists in the IP database of ESA Only RAW format accepted for input data file Constant resolution 8 bits required could be extended to 32 bits for instance R
91. te the compression power is the compression ratio CR defined by the ratio of the number of bits per sample before compression to the encoded data rate so for the Lossless compression algorithm applied with the entire datas to compress nJ x NumberOfBlocks TotalLengthOfCompressedDatas where n is the sample resolution and J is the block size Nicolas Lain TEC EDM 37 Research on new SoC design Methodology using SystemC issue 1 revision 0 Picture Size of Compression Simulation Simulation Speed Gain picture ratio speed RTL speed RTL Factor SystemC VHDL spot la b1 raw 250kBytes 1 496 58 1 30 x1 6 spot la b2 raw 250kBytes 1 507 59 131 x1 54 spot la b3 raw 250kBytes 1 558 56 1 30 x1 61 spot la_panchr raw 1 Mbytes 1 653 2732 520 X2 1 Lena512 262kBytes 1 582 1 06 1 35 x1 44 Above is showed some results on the compression ratio obtained from typical space pictures and the traditional LENA picture The first 3 space pictures represent a satellite view of an urban area it means that these pictures should be quiet difficult to compress with an excellent compression ratio compared with star pictures for instance Concerning the simulation speed it was carried out with the testbench sending datas both to TLM and RTL encoder amp decoder plugged to a checker for comparing results from both sides It is important here to note that these tests were performed on Modelsim
92. th h include systemc src rtl_tlm checker h include systemc src rtl tlm adapt in h include systemc src rtl_tlm adapt_out h fifdef MTI SYSTEMC if using the modelsim simulator sccom compiles this SC MODULE rice rtl vhdl sc clock M M14g1l1111417 TLM RTL TESTBENCH Lg Lg g MM tb encoder both sc fifo sc uint 8 data to preprocess tlm sc fifo sc uint 8 data to preprocess rtl RER ER EEE IEEE ELLE EEE LEE PC Bg M LLL PL B M LLL TAT ATTA AT AAA TT 14111 RTL ENCODER SIGNALS 1 1 1117 clk tb encoder bothl Input Encoder FIFO Input Encoder FIFO for for TLM encoder Model RTL encoder Model Sc signal bool rst sc signal bool data ready in sc signal bool gt data_accept_in sc_signal sc_signal sc_signal sc_signal ac lat 489 sc_lv lt 8 gt gt bool gt bool gt data_in rtl data out AAAAA A sc signal sc signal sc Ay 16 gt gt gt bool gt nb_blocks_tocompress top encoder rtl top encoder rtl INST JUDITH TH BM EEE IEEE EEE III TI EE EI ATT TUM ENCODER SIGNALS amp FIFO S Sc signal bool Sc signal bool sc fifo sc uint 8 gt gt sc fifo sc uint lt 8 gt gt data compressed data compressed log top encoder gold top encoder goldl MM MB MM B gU P B PP MM MM B GM I TLM DECODER SIGNALS amp
93. to the output In our case we chose to output with a 8 bits wide bus which is the most common case for IP output The formatting part is showed as below with the example of the split sample option Nicolas Lain TEC EDM 16 Research on new SoC design Methodology using SystemC issue revision 0 k J split bits field Coded Data Set variable length field As the compressed data will be variable length data the encoder never knows in advance how big in terms of number of output bytes the compressed data will be and all we know is that the output will be less than 132 bytes corresponding to the No compression option in addition with 4 bytes of Option ID As we will see later on formatting the variable length data to the output will represent the main issue in the implementation of the encoder we can see through this example that we need to store into a memory the next byte which will be sent to the output 2 2 3 THE DECODER ENGINE The decoder engine is composed of two main parts as the encoder engine a decoder module and a postprocessor unit The postprocessor performs both the inversion prediction and the inverse of the standard mapper operation A global system point of view is showed below y x compressed original datas datas uncompressed 2 2 3 1 The adaptive entropy decoder Basically the selected code option ID bits which are at the beginning of the CDS will be extr
94. troller output compressed datas from the Rice IP Once all input datas were compressed the Rice IP sends an interrupt to the Leon so that the host knows when to reset the IP interface for new optional datas Nicolas Lain TEC EDM 45 Research on new SoC design Methodology using SystemC issue 1 revision 0 3 4 SOC USING RICE IP COMBINED WITH A SPACEWIRE AMBA Bus Controller SpW Astrium PROM Interruption CHIP RAM Handler 10CP Master2 0 RICE IP 20cP slave 2 0 P MEMORY CTRL 10cPMaster2 0 master2 Ir In the last SoC we assumed that SRAM was already preloaded with the correct uncompressed datas before starting compression Since it will not be the truth in the reality we would like to use a spacewire SPW to handle loading SRAM SpW is a high speed serial link to transmit and receive packets of data containing AHB and APB interfaces First we load the CHIP RAM with the microcode software used by the microprocessor LEON3 this step will be done by the SpaceWire Then the SPW will load the SRAM with the uncompressed data loaded from the external SPW link The compression Rice IP will then compress data and stores compressed data straight into the SRAM Finally Leon3 will pick these data up to give it to the SPW connected to the external link To simulate external SPW link we used one other SoC based on a GUI initiator associated with a SpW from the University of Dundee The goal of this
95. ue 1 revision 0 However the results showed above performed on Modelsim v6 1 are not really big as expected First it can be explained by the fact that rice compression implementation is based on a simple communication scheme a more complex communication implementation such as a bus would most likely increase the speed difference considerably Finally one other factor may be the complexity of the model itself a model with more complex parallel processes would also increase the speed of abstract timing For instance the TLM model of the Rice decoder is based on a complex main thread one possible improvement should be to split this one into small concurrent threads Note that these results may have to be minimized since the RTL VHDL contains some conversion functions produced by the translator tool Thus a comparison with RTL VHDL written by hand i e without any use of conversion functions would have given higher speed for VHDL but will be still lower than TLM SystemC Unfortunately time was missing to implement by hand a VHDL code for the Rice encoder 2 6 3 SETTING TIME OF THE DIFFERENT STEPS One goal of this study was also to show a faster design time using the new design methodology thus below it is displayed roughly the time rate for each design flow steps I spent discarding documentation reading and report writing time Design flow step Time rate overall 1s period project SystemC TLM Encoder and Decoder codi
96. urate and usually tied to a system clock It does not infer pin level detail and transfer of information is modeled as transactions Pin Cycle Accurate PCA PCA refers to the model interface and not the model functionality Timing is cycle accurate and tied to a system clock It contains pin level detail Register Transfer RT Accurate Everything is fully timed with a complete detailed functional description for every clock cycle What are the benefits to split into several models of hierarchy First we can start to describe a design from a functional model that means that only the algorithm is described using a language typically C language and then can be used as a golden reference or a starting point to our design flow We can also leave from the TLM model and always serves as an executable platform that is accurate enough to execute software on Second and not the least the fact to leave from the TLM model may significantly increase the simulation speed compared with RTL model using typical hardware modelling descriptions languages such as VHDL or Verilog typically will increase by a factor of 300 400 in terms of cycles per second for a standard System On Chip TLM SystemC will serve Nicolas Lain TEC EDM 3 Research on new SoC design Methodology using SystemC issue revision 0 as a platform allowing for early software development and co simulation of hardware and software e Finally SystemC can be als
97. using SystemC issue 1 revision 0 The chosen application for this project is based on a lossless data compression dedicated for space applications Rice algorithm It is an adaptive algorithm applicable to a wide range of digital data both imaging and non imaging recommended by CCSDS for lossless data compression on board spacecraft Only the encoder of this data compression algorithm will be mapped to the FPGA board that s why only this part was implemented in several levels of abstraction regarding top down architecture However the decoder has also to be designed in a high abstraction level TLM Model in our case for validation purpose For more convenience the adopted design flow for this study is showed below COMPARE D LATIS TOP DOWN D D GATE LEVEL teneu ARCHITECTURE Nicolas Lain TEC EDM 11 Research on new SoC design Methodology using SystemC issue 1 revision 0 AS we saw previously it is not required to modify the testbench when refining the design under test even for the after placed and routed design Note that it is also possible to start to explore some miscellaneous SoC architectures starting from the TLM level In this case system engineers will not have to wait for the RTL level of the IP before looking for the best suited system On Chip In the SoC implementation we will discuss in more details about TLM possibilities on a system point of view 2 1 3
98. ut cnt 0 amp amp flag accept out 0 accept out 0 flag accept out 1 accept out cnt randomize_time2 else if accept out cnt 0 amp amp flag accept out 1 accept out 1 flag accept out 0 accept out cnt randomize time else accept out 0 int randomize time int random time random time rand 400 if random time 5 random time 5 return random time int randomize time2 int random time random time rand 50 if random time 5 random time 5 return random time Gap should be at least 6 clk cycles at high level burst should be at least 2 clk cycles at low level Counter for for accept out burst generation int accept out cnt int flag accept out int accept out ofstream fout void init void adapt out SC CTOR adapter out fout open tests RTL VHDL compressed datas rtl txt ios if fout cout lt lt ERROR SC_THREAD init SC METHOD adapt out sensitive clk pos di Adapt_out cpp Adapter RTL gt TLM functions JTI TH TT B MIEL BM M MB Gg MP MB ATT AAA ED SC SIGNAL to SC FIFO ADAPTER 8 Bits RTL TLM Simulation 114 ANN include adapt_out h void adapter out init data accept out write 0 accept out cnt randomize time flag accept out 0 void adapter out adapt out sc uint lt 8 gt data o return counter accept out cnt flag acc
99. ve blocks are all null samples blocks Then the output value is roughly the number of consecutive zero blocks Option Fundamental Sequence The most basic option consists of zeros followed by a one when preprocessed sample i m A Fundamental Sequence is the concatenation of FS codewords Option 2 extension Each pair of preprocessed samples in a sample block is transformed and encoded using an FS codeword Let 5 and di 1 be adjacent pairs of samples from a sample preprocessed data block They are transformed into a single new symbol y by the following equation 6 6 6 1 y i y i dag The Split Sample options The Ath split sample option is obtained by removing the Aleast significant bits LSBs from the binary representation of each preprocessed sample di and encoding the remaining bits with an FS codeword see figure 3 2 This produces a varying codeword length codewords for the current block of preprocessed samples are transmitted along with the removed LSBs preceded by an ID field indicating the value of amp This process enables the adaptation of codeword length to source data statistics No compression If all above options were unsuccessful to get a smaller compressed data than input data then the input data is sent to the output without any modifications 2 2 2 3 The coded output format Once the best compression option was determined we have to format the corresponding data
100. work soc both soc Set PROM VHDL file name set boot_program load_prom Delete work library if already exist if file exists lib_soc echo Deleting the current working libraries vdel lib 1ib soc all vlib vlib vlib vlib vlib vlib 1ib soc compiled libs 1ib soc work soc 1ib soc 1ib soc rice soc 1ib soc sram 1ib soc init soc vmap vmap vmap work 1ib soc rice soc sram 1ib soc sram init 1ib soc init soc Verify if prosilog library exist if not if file exists lib_soc prosilog echo Prosilog Library is already mapping else echo vlib vmap map this library Map Prosilog Library to current project 1ib soc prosilog prosilog magillemdir Simulation Modelsim prosilog v58 echo Compiling the VHDL files vlib vmap 1ib soc synplify synplify lib all dir synplify vlib vmap 1ib soc unisim unisim lib all dir unisim vlib vmap 1ib soc simprim simprim lib all dir simprim echo Compiling the VHDL files of SoC RICE SpW HER AAE AE AAA A AA HAE A A AA AA AE AH A HAE A AA AA AE AE A A AE AA AAA EEE HG HG HG E H HHA HHH COMPILING SOC WITH IP RICE SpW ASTRIUM i4HHEWCHEHBEEEEEEHEEBEBEEHEEHBEEEHERHBERERERHEHBE HE E E HAE HE AE HAE HAE AE HE AE A AE HAE HAE AE HE EF AE HAE HAE AE HE EE AE AA EEE AE HE DEA AE HAE HAE AE HAE AE AA EE EEEE RARE E E HAE AE AE AE AE AE AE AE AE FE AE HE E E E EN Compiling AHB system HART AE AE AE E AE AE RE HE E E AE

Download Pdf Manuals

Related Search

Related Contents

Deutsch - Schuss Home Electronic  Crystal Surround Air Track - Migros  Inoxpa Prolac HP  MANUAL DO USUÁRIO  Samsung Galaxy Ace 2 Hướng dẫn sử dụng  DMR2116i    Sanyo UPF385374 User's Manual  User Guide - Performance Audio  

Copyright © All rights reserved. Failed to retrieve file