SMT130 User Manual - Sundance Multiprocessor Technology Ltd.
Contents
1. Page 19 of 46 SMT130 User Manual V1 0 Table 8 Interrupt Control Register The JTAG controller which generates TBC INT must be cleared of all interrupt sources in order to clear the interrupt SUNDANCE 3 9 JTAG Controller The SMT130 has an on board Test Bus Controller TBC The TBC is controlled from the PCI bus giving access to the on site TIM and or any number of external TIMs The TBC is a SN74ACT8990 from Texas Instruments Please refer to the Texas Instruments data sheet for details of this controller The TBC is accessed in I O space at the Base address 0x80 J1 E TIM Test Bus Switching Ss J2 E Matrix JTAG Stacking Connectors Test Bus Controller PCI bridge Figure 1 TBC Data Routing The SMT130 can operate in two TBC modes Master mode and Slave mode In Master mode the Test Bus Controller on the SMT130 drives the JTAG scan chain through the TIM site on the SMT130 If the site is not populated with a TIM then the modules SENSE signal is used to enable a tri state buffer connecting the TDI and TDO JTAG Data In and Data Out on the site maintaining the integrity of the JTAG data path This switching is automatic The External JTAG Connector J2 is intended to connect to a second SMT130 in the PCI 104 stack When this is the case the SMT130 automatically detects the device and routes the test data accordingly The SMT130 is configured in Slave mode if the TBC and JTAG chain from another SMT130 is be2. SUNDANCE 3 16 Mechanical Dimensions The SMT130 size is 95 8 mm by 115 5 mm The SMT130 conforms to the physical specification defined by the PC 104 Consortium The inter stack height may be violated if the SMT130 is populated with a tall TIM In this case connector extensions and longer fixing pillars maybe used 17 Power consumption The SMT130 is powered from the PCI stack connector on the host PC controller The card uses the 5v supply only The following current consumption figures were measured using a LEM current clamp during a quiescent period No TIM was fitted to the SMT130 during this test Current drawn from 5v supply 200mA Certificate Number FM 55027 User Manual QCF42 Version 3 0 8 11 00 O Sundance Multiprocessor Technology Ltd 1999 SUNDANCE 3 18 Cables and Connectors 18 1 Comports The cables used with FMS connectors are not supplied with the SMT130 You can order them separately from Sundance with part number SMT500 FMSxx where xx is the cable length in centimetres Certificate Number FM 55027 User Manual QCF42 Version 3 0 8 11 00 O Sundance Multiprocessor Technology Ltd 1999 Page 46 of 46 SMT130 User Manual V1 0 19 Where s that Jumper Below is a diagram to help locate the jumpers SNTIS vI AVIS v1I PC I 4 Single Site Module Carrier Rotary switch SW1 _ r Comport 4 J4 L SC Comport 0 J6 HE e A i underneath LED ic ia LED2 LEDI D 3
3. De Bin E lei 32 18 2 DEE Meruelo 33 839 MEET Ee 33 13 3 1 PCI Interrupt Configuration Register Offset 0x4C BARO ooccccccccccccnnccccoccononocononnnoss 33 13 3 2 PCI Interrupt Status Register Offset 0x48 BAU 35 13 3 3 Local Bus Interrupt Mask Register Offset 0x77 BARO 36 13 3 4 Local Bus Interrupt Status Register Offset 0x76 BARON 37 13 3 5 PCI Mailbox WRITE READ Interrupt Control Register Offset Write OxDO BARO Read OD BARO a cen nn ease baddies bata is ee eee 37 13 3 6 Local Bus Mailbox WRITE READ Interrupt Control Register Offset Write 0OxD4 BARO Read OXD6 AO ld e ld ana lO oceania 38 14 15 16 17 18 Page 4 of 46 SMT130 User Manual V1 0 13 3 7 Mailbox Write Read Interrupt Status Register Offset Write OxD8 BARO Read OxDA BARO 39 13 3 8 INTREG Register Offset 0x40 BART use 39 134 EXAMPIO EE 40 oland o RS RD ne ne Ge 42 Performance Figures EEN 43 Mechanical DIMENSIONS nn naine pide 44 POWGEr CONSUMPUON ME 44 Gabl s e e Ree te EE 45 18i COMPOSER SR ee ee D da ataco 45 19 Wheres Haten ee eege eege eene Eege 46 Page 5 of 46 SMT130 User Manual V1 0 Table of Tables Fable tz Table of ADDreViatiOn seccion diia 7 Table 2 UO address Space map 11 Table 9 Memo Saca Ma ts o o o do 12 Table 4 Memory space map ie 13 Table 5 Comport Connector reference ccooccccccnccncnccncnccnnnconnnnonnnonnnnnonnnnonnnnnnnnnnanannns 15 Table 0 CONTO NARCO rra 16 Tal AS TACO Et A E E E
4. FIFO The following section describes the bit definitions for these registers 8 1 Comport Registers Offset 0x10 BAR1 The host is connected to the first TIM site using Comport 3 This port is bi directional and will automatically switch direction to meet a request from either the host or the DSP Both input and output registers are 32 bits wide Data can only be written to COMPORT_ OUT when STATUS OBF is O Data received from the DSP is stored in COMPORT IN and STATUS IBF is set to 1 Reading COMPORT_IN will clear STATUS IBF and allow another word to be received from the DSP 8 2 Control Register Offset 0x14 BAR1 The CONTROL register can only be written It contains flags which control the boot modes of the first TIM site po RESET Write a 1 to this bit to assert the reset signal to the TIM module on the SMT130 These bits connect to the corresponding pins on the TIM site 1 Writing O causes the corresponding IIOF line to go low NotNMI A O written to this bit will assert the active low NMI to the TIM Table 6 Control Register Note 1 On PCI system reset RESET is asserted to the TIM site Note 2 The TIM reset signal on the STM130 is connected to a stacking connector that can common up the TIM reset signals If there is more than one SMT130 card in a system stack the TIM reset signal can be connected together if the reset enable jumper is inserted This maybe required where all TIMs in a system are to be res
5. e Shared SRAM 1MB e Control EPLD that manages Comport access e JTAG controller e Module Global Bus e PCI Bridge device An on board arbitration unit controls which device Master Module or PCI Bridge has access to this local PCI bus resource The local PCI bus has a 33MHz clock to control transfers between the various resources This is available on the CLKIN pin on the Master site and should be selected in preference to the on board oscillator to allow the DSP to synchronise its accesses to and from the PCI Bridge registers The PCI Bridge has an input and output FIFO capable of transferring 256 32 bit words of data to and from the DSP at 33MHz thus bursting a maximum local bus transfer rate of 132MBj Ss The TIM Module can access the SRAM over the PCI local bus at transfer rates up to 100MB s The number of wait states required by the Master Module will vary depending on the speed of the module Maximum access rates use a 20ns strobe cycle The JTAG controller is based on the Tl 8990 device and drivers can be supplied for Code Composer Studio Part Number SMT6012 Certificate Number FM 55022 User Manual QCF42 Version 3 0 8 11 00 Sundance Multiprocessor Technology Ltd 1999 SUNDANCE 3 3 Setting Up the SMT130 The SMT130 should be set up in the following way e Turn the system off and add the SMT130 With TIM already installed to the PCI 104 stack Take care to ensure that all stacking connector pins locate corr
6. 18 Table 8 Interrupt Control Register 19 Fable EE TAG Header pin TUNCUON a eee nn 24 Table 10 PCI Interrupt Configuration Register 35 Table 11 PCI Interrupt Status Register 36 Table 12 Local Bus Interrupt Mask Register 37 Table 13 Local Bus Interrupt Status Heger 37 Table 14 PCI Mailbox WRITE READ Interrupt Control Register 38 Table 15 Local Bus Mailbox WRITE READ Interrupt Control Register 38 Table 16 Mailbox Write Read Interrupt Status Register 39 Fable TIN TRES e sacre ee ans ae can amant ce mie nee er sen nt 40 Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Page 6 of 46 SMT130 User Manual V1 0 Table of Figures TBC Data e tte EE 20 JTAG header pin EE Susi 23 OCAl Busto DS GONE do do ta 25 DSP Transfer via the Local Aperture 0 28 Timing diagram for DSP local bus access nsesseeennseenrenerrnrerrrreer rrene 30 IMT P30 RO IS sgeine ein RT en 32 POFROSMTISO INENUDIS aria 33 Jumper Finder Diada Midas ld 46 Page 7 of 46 SMT130 User Manual V1 0 Table Of Abbreviations Base Address Region Dua Direct Memory Access EPLD Electrically Programmable Logic Device Peripheral Component Interconnect SDB Sundance Digital Bus SRAM Static Random Access Memory TBC Test Bus Controller Table 1 Table of Abbreviations SUNDANCE 3 1 Introduction The SMT130 is a single site module c
7. 7 User Manual QCF42 Version 3 0 8 11 00 O Sundance Multiprocessor Technology Ltd 1999 Page 28 of 46 SMT130 User Manual V1 0 Receive Target address via Com Port Link i e OxFE12 3000 Unlock the system register in PCI Bridge define LB CFG_SYSTEM 0x78 gt gt 2 divide by 4 to word align offset address of PCI bridge register WritePCIRegisters unsigned int LB_CFG_SYSTEM 0xA05F Unlock Code WritePCIRegisters unsigned int LB_CFG_SYSTEM 0x22008800 Restore Value Write Lower 24 bits of byte TargetAddress to the LB_MAPO_RES register define LB MAPO RES Ox5C gt gt 2 define LB_MAPO_MEMORY_RW 0x00060000 define LP MAPO_ADDRESS_MASK 0xFF000000 WritePCIRegisters unsigned int LB_MAPO_RES unsigned int TargetAddress amp LB_MAPO_ ADDRESS MASK LB_MAPO_MEMORY_RW The LB_MAPO_MEMORY_RW must be Or ed with the data to ensure the other register in the 32 bit word has its correct value Write WORD Aligned data to Local Aperture space 0 WritePClApperture0 ByteToWord32 TargetAddress amp LB_MAPO_ADDRESS_MASK Length buffer Where void WritePCIAppertureO unsigned int address unsigned long Length unsigned int buffer unsigned int Index globalbuswriteClockMB 0x18000000 address Length buffer Figure 4 DSP Transfer via the Local Aperture 0 Page 29 of 46 SMT130 User Manual V1 0 12 3 1 Global bus access protocol In Figure 6 the WritePClApperture function calls a function C6xGloba
8. 8 5 A21 Ie ia in a D D DN Comport 5 J13 Comport 1 J3 underneath E EEE 1124 1481 a vi Ld CE 124 EEE C147 HI Ag JTAG Master J2 JTAG Slave Ji underneath Ca ER ER SR D Eu a m LD a Ui D H BB N kl 2 RABE e o JE I N gt D ILE Sal Stand alone mode J9 nadas A Aux Power J8 Reset enable J5 La iS m T A CI C124 HA W i C132 Sundance Multipracasaar Tachnalogy Ltd Advanced Vision Tachnalagy Ltd Figure 8 Jumper Finder Diagram CPLD JTAG Connector
9. B interrupt mode as MODE D 17 16 MODE_A INTA interrupt mode as MODE D 15 INTD_TO LB 1 INTD will request LICU interrupts when the input is active O INTD will never request LICU interrupts 14 INTC_TO_D When set INTC will act as interrupt request for INTD output 13 INTB_ TO D When set INTB will act as interrupt request for INTD output 12 INTA TO D When set INTA will act as interrupt request for INTD output INTD_TO C When set INTD will act as interrupt request for INTC output 10 INTC TO LB 1 INTC will request LICU interrupts when the input is active O INTC will never request LICU interrupts INTB_ TO C When set INTB will act as interrupt request for INTC output INTA_TO_C When set INTA will act as interrupt request for INTC output 7 INTD TO B When set INTD will act as interrupt request for INTB output KM INTC_TO B When set INTC will act as interrupt request for INTB output Page 35 of 46 SMT130 User Manual V1 0 5 INTB_ TO LB 1 INTB will request LICU interrupts when the input is active O INTB will never request LICU interrupts 4 INTA TO B When set INTA will act as interrupt request for INTB output INTD_TO A When set INTD will act as interrupt request for INTA output 2 INTC_TO_A When set INTC will act as interrupt request for INTA output INTB_TO_A When set INTB will act as interrupt request for INTA output INTA_TO_LB 1 INTA will request LICU interrupts when the input is active
10. O INTA will never request LICU interrupts Table 10 PCI Interrupt Configuration Register 13 3 2 PCI Interrupt Status Register Offset 0x48 BARO 31 MAILBOX Mailbox Interrupt 1 Mailbox interrupt request active O No mailbox interrupts pending Cleared by clearing MAIL_RD_STAT and MAIL_WR_STAT 30 LOCAL Local bus direct interrupt 1 Local bus master requests a PCI interrupt O No operation This bit is set by writing 1 and cleared by writing O OUT POST 120 outbound post list not empty see V3 datasheet e Resened o om mei Page 36 of 46 SMT130 User Manual V1 0 o p JoccuredoniNTe 13 INTB_TO_D INTD output from INTB input when set 1 an interrupt has occurred on INTB 12 INTA TO D INTD output from INTA input when set 1 an interrupt has occurred on INTA 11 INTD_TO_C INTC output from INTD input when set 1 an interrupt has occurred on INTD nl eea INTB_TO_C INTC output from INTB input when set 1 an interrupt has occurred on INTB INTA_TO_C INTC output from INTA input when set 1 an interrupt has occurred on INTA 7 INTD_ TO B INTB output from INTD input when set 1 an interrupt has occurred on INTD INTC_TO_B INTB output from INTC input when set 1 an interrupt has occurred on INTC e nee 4 INTA TO B INTB output from INTA input when set 1 an interrupt has occurred on INTA 3 INTD_TO_A INTA output from INTD input when set 1 an interrupt has occurred on INTD 2 INTC_TO
11. R interrupt e g Mailbox TIMIIOFO IE LINT gt LINT TIMIIOF1 IE gt TIMIOF2 IE Figure 7 PCI to SMT130 Interrupts 13 3 Interrupt Registers The following register are used to control PCI To DSP and DSP To PCI interrupts Note that Control Register Offset 0x14 BAR1 and Interrupt Control Register Offset 0x18 BAR1 are also used to control interrupts 13 3 1 PCI Interrupt Configuration Register Offset 0x4C BARO 31 MAILBOX Mailbox Interrupt Enable Enables a PCI interrupt from the mailbox unit 30 LOCAL Local Bus Direct Interrupt Enable Enables direct local bus to PCI interrupts MASTER PI PCI Master Local Interrupt Enable see V3 datasheet SLAVE Pl PCI Slave Local Interrupt Enable see V3 datasheet OUT POST 120 Outbound Post List Not Empty see V3 datasheet Certificate Number FM 55027 User Manual QCF42 Version 3 0 8 11 00 Sundance Multiprocessor Technology Ltd 1999 Page 34 of 46 SMT130 User Manual V1 0 es o pees 25 DMA1 DMA Channel 1 interrupt enable DMAO DMA Channel 0 interrupt enable 23 22 MODE D INTD interrupt mode Determines use of corresponding interrupt pin 00 Active low level triggered input 01 High to low edge triggered input Software cleared output INTD pin is asserted via an interrupt event and cleared through PCI_INT_STAT register 11 Reserved 21 20 MODE GC INTC interrupt mode as MODE D 19 18 MODE P INT
12. SUNDANCE Y SMT130 User Manual V1 0 Certificate Number FM 55022 User Manual QCF42 Version 3 0 8 11 00 Sundance Multiprocessor Technology Lid 1999 Page 2 of 46 SMT130 User Manual V1 0 Revision History Date Comments Engineer Version S E Page 3 of 46 SMT130 User Manual V1 0 Table of Contents 1 It ge leede WE 8 2 Elhclional Describa 9 3 etma UD h SMS ne rada 10 4 MEMO Mars RE Cus 11 4 1 PCI Bridge Chip Internal Register DAOU 11 4 2 I O Space Register Assignments BART oooocccncccccccccconccnncccnononnncnonononononanncnnnnnnnnnannnennnnnnnss 11 4 3 Memory Space Assignments BAR2 iii 12 5 DSP ReSourCe Memon MAI E 13 6 Shared Memory Resol Cea A 14 Le EENEG 15 8 Compor POMENI CE sirina acia tala 16 8 1 Comport Registers Offset 0X10 BAH 16 8 2 Control Register Offset 0x14 BAR1 16 8 3 Status Register Offset 0x14 BAR1 Read Only occcccocconncccnncccccccconcnnoconononanccnnnnncnononanonos 17 8 4 Interrupt Control Register Offset 0x18 BA 18 D TAG ie oae r A 20 10 Using the SMT130 External Internal JTAG with TI Tools 22 Jl Primare Upgrade S aii ios 23 12 Global lbocalBus Transters DS Peso PG lisesi isa Raa o ls las 25 12 1 Mailbox ACCESSES ina uen aa aa aa da aE e a Ea ci 25 12 1 1 Doorbell Ieu lic 26 te DSPACE OLE o 26 12 3 DSP To Local Aperture 0 control and Accessing 27 12 3 1 Global DUS ACCESS POCO us 29 ES IMC de E ER SA OR NEE e
13. _A INTA output from INTC input when set 1 an interrupt has occurred on INTC 1 INTB_TO_A INTA output from INTB input when set 1 an interrupt has occurred on INTB Table 11 PCI Interrupt Status Register 13 3 3 Local Bus Interrupt Mask Register Offset 0x77 BARO MAILBOX Global mailbox interrupt enable e PCI_RD PCI read error interrupt enable PCI_WR PCI write error interrupt enable 4 PCL INT Global PCI interrupt to local interrupt enable PCI PERR PCI parity error interrupt enable 120 QWR 120 inbound post queue write interrupt enable Page 37 of 46 SMT130 User Manual V1 0 DMA1 DMA channel 1 interrupt enable o DMAO DMA channel 0 interrupt enable Table 12 Local Bus Interrupt Mask Register 13 3 4 Local Bus Interrupt Status Register Offset 0x76 BARO MAILBOX 1 interrupt has been requested by one or more of the mailbox registers O no mailbox interrupts pending PCI RD See V3 datasheet 5 PCI WR See V3 datasheet PCI PERR See V3 datasheet o omo sevsen Table 13 Local Bus Interrupt Status Register 13 3 5 PCI Mailbox WRITE READ Interrupt Control Register Offset Write OxDO BARO Read 0xD2 BARO 15 EN15 Local interrupts on PCI bus writes reads to mailbox15 enable Same as above for mailbox 14 EN13 Same as above for mailbox 13 EN12 Same as above for mailbox 12 EN11 Same as above for mailbox 11 a ee eege Same as above for mailbox 8 6 ENS Sameas above ormalllox6 A PagesBo
14. arrier board that provides access to a single TIM module over the PCI bus in a PCI 104 stack system An on board JTAG controller allows systems to be debugged using Code Composer Studio There is also a JTAG input and JTAG output connector on the SMT130 This allows the debugging of all the TIM modules in the PCI 104 stack from a single JTAG controller The main connection to the PCI bus is via the module Global Bus A single Comport is also mapped to the PCI bus providing support for application boot and data transfer A 1 MB of SRAM is mapped on to the Global Bus and can be accessed by the TIM as a global resource or by the PCI Bridge A through board header is provided for RESET_IN and RESET OUT to allow multiple SMT130 carriers in a stack to be synchronised The board requires a 5 volt supply only which is taken from the PCI 104 stack connector or an auxiliary power connector from stand alone applications The 3 3 volt supply required for supplying power to the TIM module is generated locally Certificate Number FM 55022 User Manual QCF42 Version 3 0 8 11 00 Sundance Multiprocessor Technology Ltd 1999 SUNDANCE 3 2 Functional Description The PCI interface connects to a Quick Logic EPC363 Bridge device lt has a 32 bit 33MHz PCI interface that supports IFC control mailbox register access and direct memory reads and writes The PCI bus is translated to a Local PCI bus which is connected to the following devices
15. come Bus Master Once the DSP is Master the arbitration unit drives AE and DE low to enable the DSP s address and data lines RDY1 is driven low by the arbitor to indicate to the DSP on the next rising LCLK that the data packet has been transferred If the input FIFO 256 Words Deep becomes Certificate Number FM 55022 User Manual QCF42 Version 3 0 8 11 00 Sundance Multiprocessor Technology Ltd 1999 Page 31 of 46 SMT130 User Manual V1 0 full the arbitration logic de asserts the RDY1 signal to indicate a hold off state Once the data has been transferred from the FIFO to the PCI bus RDY1 is re asserted to continue the transfer The end of the burst access Is indicated by asserting STATO low If RDY1 is not active then STATO should remain asserted until ready is asserted and the final data transaction has been completed Situations can arise where a deadlock condition car arrive Le the PCI bus is trying to read from the SMT130 resources while the DSP is reading from the PCI Bus If this Situation arises the arbitration unit gives the PCI Bridge device priority and services the HOST PCI access before giving bus ownership back to the DSP When running code composer applications to debug the DSP a reduction in the speed of the debugger will be noticed The DSP has priority when accessing the local bus and any other accesses will only occur under the following conditions e Burst access is finished e Deadlock condition occurs wh
16. de firmware Xilinx JTAG programming software is required together with a lead to connect to the SMT130 s header The image below shows the location of pin 1 of the CPLD JTAG connector J21 This connector is a 2x3 2mm pin header SAP J5 NM c148 E dis EPE R57 H3 121 Sundance Multi pro Advanced Vision Ti Pin 1 J21 CPLD JTAG connector QO 000 Figure 2 JTAG header pin numbers Certificate Number FM 55022 User Manual QCF42 Version 3 0 8 11 00 Sundance Multiprocessor Technology Ltd 1999 Page 24 of 46 SMT130 User Manual V1 0 Vcc 5v Table 9 JTAG Header pin function SUNDANCE 7 12 Global Local Bus Transfers DSP lt gt PCI The traditional global bus interface on C6x DSP modules interfaces to the SMT130 via a local bus This allows Global bus transfers on the DSP to be converted into local bus accesses This allows direct DSP accesses to the PCI Bridge chip The resources in the PCI Bridge chip are illustrated in the figure below PCI Bridge Device MailBox Read Write Interrupt Control DSP Global Local Bus Bus Access Local To PCI Bus Apperture Control LOCAL lt gt PCI Apperture O 16MB Address E p Space Arbitration Unit Figure 3 Local Bus to DSP Connectivity 12 1 Mailbox Accesses The mailbox registers can be used if small amounts of data or comman
17. ds between the PCI bus and the DSP via the local bus need to be transferred Rather than sending Comport data and therefore require the DSP to be checking its Comport for commands a mailbox write by the PCI bus can be initialized to generate an interrupt on an DSP IIOF line indicating to the DSP that data is available The PCI Bridge device provides 16 8 bit mailbox registers which may be used to transmit and receive data between the DSP and Host Cortificato Number FM 55022 User Manual QCF42 Version 3 0 8 11 00 Sundance Multiprocessor Technology Ltd 1999 Page 26 of 46 SMT130 User Manual V1 0 The mailbox registers are accessed from the DSP through the Local to Internal Register LB_IO_BASE aperture As illustrated in section 5 table 4 of this document this region is accessed by the DSP via a global bus access to the PCI Bridge Registers Address 0x1C00 0000 The mailbox registers themselves are on byte boundaries with offsets OxCO gt OxCF from the LB IO BASE As DSP global bus accesses are carried out on WORD 32 bit boundaries a write access over the global bus to 0x1C00 0000 OxCO will write to the first 4 mailbox registers in the PCI Bridge device The mailbox registers are accessed from the PCI bus through the PCI to Internal Register PCI IO BASE aperture This is accessed via the PCI Bridge Chip Internal Register BARO byte offset OxCO gt OxCF 12 1 1 Doorbell Interrupts Each of the 16 mailbox regi
18. ectly Secure the SMT130 in the stack with the pillars and screws provided Adjust rotary switch SW1 to ensure that the SMT130 has a unique stack position No two cards in the PCI 104 stack must have the same setting Note only positions O to 3 are valid e Switch on PC and wait for the OS to boot up e Windows 95 98 NT 2000 will detect a new hardware e Windows should automatically find the drivers from the CD if not browse to the CD or if you downloaded from the ftp site to the folder where you unzipped the SMT6300 software e 3L application software will detect the SMT130 if the SET TISLINK variable is set to SMT320 e You can run the SMTBoardinfo application to detect the number of SMT130s in your system and report their stack positions and I O addresses This information is required when setting up code composer for the board SMTBoardinfo is part of the SMT6300 package Certificate Number FM 55027 User Manual QCF42 Version 3 0 8 11 00 Sundance Multiprocessor Technology Ltd 1999 SUNDANCE 2 4 Memory Map All address information is given in bytes 4 1 PCI Bridge Chip Internal Register BARO Please see V363EPC Local Bus PCI Bridge User Manual V1 04 http www quicklogic com home asp PagelD 2238sMenulD 114 Docs for details of internal registers Note Where required registers from the V datasheet have been included 4 2 1 0 Space Register Assignments BART In target mode the SMT130 is accessed by a hos
19. eserved elt Ip D CN ni Deene o Certificate Number FM 55022 User Manual QCF42 Version 3 0 8 11 00 O Sundance Multiprocessor Technology Ltd 1999 Page 40 of 46 SMT130 User Manual V1 0 Co Deeg 9 Reserved e Deene SSCS nr Deene SS e Deene SSCS DS Reeves SCS CSC DS Rene o IOF2EN PC to DSP TIMIIOF2 interrupt enable IOFIEN PC to DSP TIMIIOF 1 interrupt enable o NOFOEN PC to DSP TIMIIOFO interrupt enable Table 17 INTREG Register 13 4 Example The example below shows how the DSP can cause an interrupt on the PC by writing to mailbox register 0 The PC must first enable the interrupts to do this the following register bits must be altered and an interrupt thread handler needs to be created PCI Interrupt Configuration Register Offset 0x4C BARO bit 31 must be set Local Bus Interrupt Mask Register Offset 0x77 BARO bit 7 must be set PCI Mailbox WRITE READ Interrupt Control Register Offset Write OxDO BARO Read OxD2 BARO bit O of the write register 0xD4 must be set An Interrupt service routine must be set up in this the following register will need to be cleared SUNDANCE 3 Mailbox Write Read Interrupt Status Register Offset Write 0xD8 BARO Read OxDA BARO bit O of the write register 0xD8 must be cleared Local Bus Interrupt Status Register Offset 0x76 BARO bit 7 must be cleared To cause the interrupt the DSP needs to write to the mailbox reg
20. et at the same time SUNDANCE 3 8 3 Status Register Offset 0x14 BAR1 Read Only PRE 8 RDY or e s 4 3 2 0 OBE IE Set if Comport output buffer empty interrupts enabled IBF IE Set if Comport input buffer full interrupts enabled TBC IE Set if JTAG interrupts enabled Set if interrupt from TIM DSP enabled OBE INT Set if the Comport output buffer becomes empty Cleared by writing a 1 to the corresponding bit in the interrupt control register IBF INT set if the Comport input buffer receives a word Cleared by writing a 1to the corresponding bit in the interrupt control register TBC INT Set when the TBC asserts its interrupt Cleared by removing the source of the interrupt in the TBC C40 INT set when the TIM DSP sets its host interrupt bit Cleared by writing a 1 to the corresponding bit in the interrupt control register enable bit Ee when the word has been transmitted to the DSP Interrupt mask 0 Returns Interrupt Control de a Bit 8 TBC RDY Reflects the current state of the TBC RDY pin This bit is active high and therefore and inversion of the TBC pin Certificate Number FM 55027 User Manual QCF42 Version 3 0 8 11 00 O Sundance Multiprocessor Technology Ltd 1999 Page 18 of 46 SMT130 User Manual V1 0 CONFIG_L Reflects the state of the TIMs CONFIG signal Active low Table 7 Status Register INTD is the input interrupt into the PCI Bridge from the SMT130 this can be routed to ei
21. f the TIM site connector must be decoded as high and GADD7 and GADD5 must be decoded as low Note 2 These mirrors of Addresses in the l O Space BAR1 allow increased transfer speeds across the host Comport link in excess of 10X increase Certificate Number FM 55022 User Manual QCF42 Version 3 0 8 11 00 O Sundance Multiprocessor Technology Ltd 1999 SUNDANCE 3 5 DSP Resource Memory Map The Master module on the SMT130 can access the various resources available including the Shared SRAM and the PCI Bridge Access to the PCI Bridge allows the DMA engine in the PCI Bridge to be initiated by the DSP mailbox registers can also be manipulated The table below illustrates the resources and their corresponding address region when accessed by the Master module 0xD000 0000 OxDOOF FFFF Shared Memory Bank 1Mbyte SRAM 0x1C00 0000 0x1C00 OOFF PCI Bridge Registers PCI Bridge Internal resisters 0x1800 0000 0x183F FFFF Local to PCI Aperture O PCI Bridge Aperture O Space Table 4 Memory space map Certificate Number FM 55022 User Manual QCF42 Version 3 0 8 11 00 Sundance Multiprocessor Technology Ltd 1999 SUNDANCE 6 Shared Memory Resource There is 1Mbyte of SRAM on the SMT130 this shared memory can be accessed by the PCI host and the TIM module This allows applications to transfer data between the host PC and the DSP at data rates approaching 100MB s The address of the shared memory is sh
22. fer acknowledgement This is driven by the SMT130 to indicate that the current transfer has been completed STATO 3 DSP Status line When all of the signals are logic 1 then the DSP Global bus interface is in an idle state When any of these signals is driven low the DSP requesting ownership of the SMT130 s local bus STATO has a special status and indicates the last data packet transfer when driven low by the DSP SUNDANCE 3 A0 A30 DSP s global Bus address lines DO D31 DSP s global Bus data lines HOFO IIOF1 amp IIOF2 DSP s Interrupt signals These are open collector signals on the SMT130 They can be driven by the DSP to generate an interrupt to the host or they can be driven by the host to interrupt the DSP In the timing diagram below all signals change relative to the rising LCLK signal This Signal is the H1 clock signal of the DSP when using the DSP global bus in synchronous mode see SMT335 User Guide TIMReq FIFO Full LK LLL a a STATE AAA STRB1 bm Ez IS STATO a lU T AE DE ooo E T A30 0 D D D D D DD D D D DDD O OOOOH Figure 5 Timing diagram for DSP local bus access LCLK Period 30nS frequency is 33MHz The DSP initiates a global bus R W by asserting the STRB1 low and STAT 1 3 change see TIM Spec for details of STAT 1 3 details Once the arbitration unit detects this it waits for the last cycle of the Local bus to be completed by the PCI Bridge before allowing the DSP to be
23. ich releases DSP ownership of the Bus For multi threaded applications the length of the DSP burst can be lowered to allow PCI bus R W cycles to snatch cycles from the DSP SUNDANCE E 13 Interrupts 13 1 SMT130 To PCI Interrupts CONTROL EPLD o STATUS INTERRUPT Ka REGISTER CONTROL REGISTER REES DSP IIOFO TIMIIOFO ENABLE DSPINT gt C40 IE DSP IIOF1 idge TIMIIOF 1 ENABLE IBF INT IBF IE E EGE DSP IIOF2 INTD TIMIIOF2 dee OBE INT vCpEI UNID NA a gt INTE TAG INT gt TBC INT J T TBC Ei gt INTC Figure 6 SMT130 to PCI Interrupts Interrupts can also be caused by the SMT130 by writing or reading the mailbox registers in the PCI Bridge Certificate Number FM 55022 User Manual QCF42 Version 3 0 8 11 00 Sundance Multiprocessor Technology Ltd 1999 SUNDANCE 7 13 2 PCI To SMT130 Interrupts CONTROL CPLD CONTROL REGISTER PCI Bridae gt IIOFO gt TIMIIOFO 9 gt WOP gt TIMINOF gt IIOF2 gt TIMIIOF2 LINT can be caused INTREG by any PCI REGISTE
24. ing used In this case the JTAG master is connected to the SMT130 on connector J1 When stacking SMT130 carriers in a PCI 104 system the Certificate Number FM 55022 User Manual QCF42 Version 3 0 8 11 00 Sundance Multiprocessor Technology Ltd 1999 Page 21 of 46 SMT130 User Manual V1 0 JTAG chain can be automatically connected through the stack by inserting a JTAG coupling connector lf this coupling connector is inserted into the stack the Lower SMT130 controls the JTAG chain All other TBCs in the PCI 104 stack will be disabled Any software used to access the TBC must target ONLY the lowest SMT130 in the stack If the TJAG coupling connectors are omitted from the stack each TBC operates independently SUNDANCE 3 10 Using the SMT130 External Internal JTAG with TI Tools For details on using the SMT130 with T I Code Composer range see the SMT6012 documentation The SMT6012 is Sundance s driver for the T I Code Composer range of products and can be purchased separately The SMT6012 is free of charge when the SMT130 is bought with the Code Composer software from Sundance Certificate Number FM 55022 User Manual QCF42 Version 3 0 8 11 00 O Sundance Multiprocessor Technology Ltd 1999 SUNDANCE E 11 Firmware Upgrades Much of the SMT130 s control interface is achieved using CPLD s Sometime customers require slightly different interface protocols which can be catered for by a firmware upgrade To upgra
25. ister in the V chip this is done by writing to address 0Ox1C0000C0 this will write to the first four mailboxes These are two separate registers one to enable interrupts on reads from the mailbox registers the other to enable interrupts on writes to the mailbox registers These are two separate registers one shows interrupt status for reads from the mailbox register the other to show interrupt status on writes to the mailbox registers Certificate Number FM 55027 User Manual QCF42 Version 3 0 8 11 00 Sundance Multiprocessor Technology Ltd 1999 Page 42 of 46 SMT130 User Manual V1 0 14 Stand alone mode For the SMT130 to operate in stand alone mode Jumper J9 Figure 8 Jumper Finder Diagram must be installed and the Auxiliary power header J8 connected The connector type and pin out is compatible with the floppy drive power connector in on a PC power supply SUNDANCE 2 15 Performance Figures Following are the performance figures for the SMT130 Performance figures are stated for the SMT130 with the Rev A1 V PCI bridging device fitted Further performance figures will be issued as faster V PCI bridging devices become available and are fitted to the SMT130 Transfer type Speed in Comments Mbytes second andara rom Sos EE 1 EECH DMA res rom Gb us II A te bas BA Deise BA Certificate Number FM 55022 User Manual QCF42 Version 3 0 8 11 00 Sundance Multiprocessor Technology Ltd 1999
26. lWriteClockMB This function enables the DSP s global bus to transfer Length words from the DSP s internal memory map pointed to by buffer The function puts the Global bust into burst mode This interface allows a synchronous stream of data to be written to the 256 WORD input FIFO of the Local To PCI aperture O For more information on setting this mode from the DSP can be found in the SMT335 Users Guide This section concentrates on the burst mode interface and arbitration mechanism for the DSP to PCI Bridge aperture access The Global bus interface of the DSP uses the following signals to interface to the local bus of the SMT130 DSP Signals AE DEI CEO AE DE are active low address Data enable signal driven by the SMT130 when the DSP has ownership of the Bus this signal is driven low by the SMT130 allowing the DSP to drive the Address pins and Data pins CEO is the Tri state control for the DSP s global bus control pins This is permanently tied low by the SMT130 as the control signal is always enable STRB1 Data strobe signal from the DSP s global bus This is driven low when the DSP is carrying out an access cycle The DSP waits for the RDY1 to be driven low by the SMT130 to indicate transfer has been completed This interface is carried out in synchronous burst mode This requires the DSP to indicate when the burst transfer is completed This is accomplished by the DSP by pulling STATO low RDY1 Active low trans
27. lsa SMT130 User Manual V1 0 38 of 46 SMT130 User Manual V1 0 A E Same as above for mailbox 3 2 Same as above for mailbox 2 Same as above for mailbox 1 0 EN Same as above for mailbox 0 Table 14 PCI Mailbox WRITE READ Interrupt Control Register 13 3 6 Local Bus Mailbox WRITE READ Interrupt Control Register Offset Write 0xD4 BARO Read 0xD6 BARO 15 EN15 PCI interrupts on Local bus writes reads to mailbox15 enable Same as above for mailbox 13 9 ENS Sameasaboveformaibox9 A A A Same as above for mailbox 7 RUE CS et ame as ebove fo maitors O ENS Same as above for maiboxs 2 Ep Same as above for mailbox2 EN Same as above for mailbox 1 ME ENO Same as above for mailbox 0 Table 15 Local Bus Mailbox WRITE READ Interrupt Control Register bh SUNDANCE 2 13 3 7 Mailbox Write Read Interrupt Status Register Offset Write 0xD8 BARO Read OxDA BARO 15 EN15 1 Mailbox 15 has requested a PCI or Local write read interrupt ape 0 Mailbox 15 has not requested a PCI or Local write read interrupt Same as above for mailbox 9 ene same a above ormas e EN6 Sameasaboveformaibox 5 Ens Sameas above for maiboxs 1 em eebe 3 Same as above for mailbox 3 en Teater O O 1 EM Same asaboveformaiboxt o Em Sameas above for maiboXO Register cleared by writing 1 writing O has no effect Table 16 Mailbox Write Read Interrupt Status Register 13 3 8 INTREG Register Offset 0x40 BAR1 e R
28. o PCI Aperture O in the PCI Bridge device A DSP unit may be required to transfer large amounts of acquired data to the PC host for data storage or post processing etc Allowing the DSP to take control of the PCI bus means that the HOST only requires to transfer data from an internal allocated region of memory after the transfer has been completed by the DSP Alerting the Host that data has been transferred can be accomplished in a number of ways Le writing to the mailbox register which can then generate an interrupt As shown in Table 4 section 5 The Local to PCI Aperture 0 is mapped as a region of addressable space from 0x1800 0000 0x183F FFFF words There are a number of registers in initialise before data can be read or written via this address space e Unlock the PCI Bridge System register This requires a write to e Write the upper 8 bits of your destination address in bytes to the upper 8 bits of the 32 bit Local Bus to PCI Map 0 register LB MAPO_RES offset in bytes Ox5c e Convert you lower 24 bit address to a word aligned value e Write Read data from Local to PCI Aperture 0 The diagram below illustrates this procedure In the example below the WritetoPClregisters offset data function writes data over the DSP s Global bus at a base address of 0x1800 0000 words the first parameter passed to this function in the offset address in words and the second is the data to be written Certificate Number FM 5502
29. own in the memory map The PCI Bridge DMA processor sees the shared memory at a different address from that used for normal accesses For normal memory access the memory base address register offset is 0x0000 0000 For DMA access address line A28 On hardware interface must be high therefore DMA memory access starts at 0x4000 0000 Not 0x1000 0000 as addressing is in bytes Certificate Number FM 55022 User Manual QCF42 Version 3 0 8 11 00 Sundance Multiprocessor Technology Ltd 1999 SUNDANCE 3 7 Comports The SMT130 gives access to five of the six TIM Comports Comports 0 1 4 and 5 are connected to 14 way surface mount FMS connectors This gives external access to the TIM Note this external access must be with in the same system stack Comport 3 is hard wired to the PCI interface This gives provision to boot the TIM and configure FPGAs on the TIM Comport 2 has no physical connection and therefore can t be used on a SMT130 Comport Number SMT130 Connector reference J6 1 J3 Table 5 Comport connector reference Certificate Number FM 55027 User Manual QCF42 Version 3 0 8 11 00 O Sundance Multiprocessor Technology Ltd 1999 Page 16 of 46 SMT130 User Manual V1 0 8 Comport to PCI Interface The Comport interface is memory mapped to the PCI Bridge as illustrated in table 2 I O address space map The Comport uses the Control and Data registers to detect the state of the input and output
30. sters can generate four different interrupt requests called doorbell interrupts Each of these requests can be independently masked for each mailbox register The four doorbell interrupt types are e DSP interrupt request on read from PCI side e DSP interrupt request on write from PCI side e PCI interrupt request on read from DSP side e PCI interrupt request on write from DSP side The PCI read and DSP read interrupts are OR d together and latched in the mailbox read interrupt status register MAIL_RD_STAT Similarly the PCI write and DSP write interrupts are OH d together and latched in the mailbox write interrupt status register MAIL_WR_STAT All of the interrupt request outputs from the status registers are OH d together to form a single mailbox unit interrupt request and routed to both the Local and PCI Interrupt Control Units When a block of mailbox registers are accessed simultaneously for example when 4 mailbox registers are read as a word quantity then each register affected will request a separate interrupt if programmed to do so See section 14 for further information on Interrupts 12 2 DSP Interrupt Control Interrupts can be enabled from a number of different sources i e DSP gt Host and Host gt DSP See section 14 for a description of these functions SUNDANCE 3 12 3 DSP To Local Aperture 0 control and Accessing The quickest way to transfer information from the DSP to PCI Bus or vice versa is to use the Local t
31. t device across the PCI bus This allows access to the target mode registers The operating system or BIOS will normally allocate a base address for the target mode registers of each SMT130 Access to each register within the SMT130 is then specified by this base address and the offset shown in the table below The I O address space is decoded as shown in the table below Offset Register Read Width PS o PS S Coo EN COMPORT Configuration 0x80 to OxAF TBC Write TBC Read 16 Table 2 I O address space map Certificate Number FM 55027 User Manual QCF42 Version 3 0 8 11 00 O Sundance Multiprocessor Technology Ltd 1999 SUNDANCE E 4 3 Memory Space Assignments BAR2 ges Beete es 0x0000 0000 0x000F FFFF Shared Memory Bank 1MB SRAM 0x00200090 Comport Data Mirror of COMPORT_OUT COMPORT_IN in I O Space Mirror i i Register Assignments BAR1 See Note 2 0x00200094 Comport Status Mirror of Control Status in I O Space Register Assignments BAR1 See Note 2 0x00200098 Comport Int Control Mirror of Int_Control in I O Mirror Space Register Assignments BAR1 See Note 2 0x0020 0000 0x0020 007F Global Bus See Note 1 0x0020 0240 0x0020 025F SDB Data Register Input Output 16 bit SDB Interface 0x0020 0260 0x0020 027F SDB Control Register SDB Control Status Table 3 Memory space map Mirror Note 1 In order for the TIM to respond to accesses for this area address line GADD30 and GADD19 o
32. ther INTA INTB or INTC using the PCI Interrupt Configuration Register offset 0x4C BARO 8 4 Interrupt Control Register Offset 0x18 BART This write only register controls the generation of interrupts on the PCI bus Each interrupt source has an associated enable and clear flag This register can be written with the contents of bits 7 0 of the Status Register II DSP PC IIOF2 En DSP PC IIOF1 En 8 5 4 3 2 1 0 DSP PC CLEAR CLEAR CLEAR OBE C40 IE TBC IE IBF IE OBE IE NOFO En C40 INT IBF INT INT DSP PC IIOF2 En Enables DSP PC interrupts on IIOF2 DSP PC IIOF1 En Enables DSP PC interrupts on IIOF 1 DSP PC IIOFO En Enables DSP PC interrupts on IIOFO IBF IE Comport Input Buffer Full Interrupt Enable Allows an interrupt to be generated when the host Comport input register is loaded with data from the C40 OBE IE Comport Output Buffer Empty Interrupt Allows an interrupt to be generated when the host Comport register has transmitted its contents TBC IE Test Bus Controller Interrupt Enable Interrupts from the Texas JTAG controller are enabled when set C40 IE C40 Interrupt Enable Allows a programmed interrupt to be generated by the C40 when set CLEAR OBE INT Write a one to this bit to clear the interrupt resulting from a Comport output event CLEAR IBF INT Write a one to this bit to clear the interrupt event resulting from Comport input CLEAR C40 INT Write a one to this bit to clear down the C40 INT event
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