User`s Manual - BCM Advanced Research
Contents
1. Research FM519 External Product Specification April 30 1997 Revision X0 1 Written By John Zwaans Revision History 519 Specification PRELIMINARY 04 30 97 Preliminary release for internal review 05 12 97 Changes and additions pup Cyrix is a registered trademark of Cyrix Corporation Copyright 1996 BCM Advanced Research Preface BCM Advanced Research ii 519 Specification PRELIMINARY This document specifies the architecture for a Cyrix Processor based MultiMedia motherboard The FM519 is a High volume Integrated desktop motherboard incorporating advanced Graphics and a sound subsystem The system incorporates the recommended functionality to support Windows 95 Features Processor Cache Processor System Memory Memory Size Memory Sites SIMM Type Access Time Chipset Integrated Graphics Graphics Controller Video Memory Organization TV Output Integrated I O I O Controller Serial Ports Infrared Interface Parallel Port Hard Disk Controller Hard Disk Connector Floppy Controller Keyboard Port Mouse Port Real Time Clock Integrated Sound Sound Chip CODEC BCM Advanced Research Cyrix GX86 Single Chip Computer 30 120 33 133 30 150 Operation 8 MB minimum to 128 MB maximum With Single and Double sided SIMM s EDO DRAM 4x72 pin SIMM Sockets 4 8 16 32 64 with Parity and Non parity x32 or x36 60ns EDO or faster2. 2 14 E 2 17 Advanced Research Vii 519 Specification PRELIMINARY IDE Hard Disk Drive Interface 2 17 Floppy Disk Drive Interface 2 Sek oie eae oe eS 2 18 VO SUBS 2 19 Seral 2 19 au m Sua s 2 20 Keyboard Interface zu asa man dora aS u ee SAG 2 21 Mouse Interface ie t 2 22 R al me qana S tidie 2 22 Nonvolatile CMOS Memory Battery 2 23 Ik Chitra red Support e N am eee ace 2 23 IRDA CODDOCQED 2 23 Miscellaneous Connectors 2 24 PC Speaker Connector 2 24 Modem In COBHeCIOE lt 2 24 Hard Drive LED Connecctor 2 25 suspend Resume Connector ee eap 2 25 Reset Connector au au esaet enn m 2 25 CPU aii COGOR ARD HU 2 26 Power Ori OUHOCEOE cies eoe eM Is QS Eta ER Deu OH OHNE SUR 2 26 Section 3 Configuration Product Contig uration cua dede 3 1 DRAM Subsystem Configurations 3 1 Section 4
3. 0 5 5 Table 5 10 Back Panel Interfaces enne enne 5 6 BCM Advanced Research xi 519 Specification PRELIMINARY 1 Introduction This section provides an overview for a Cyrix 6x86 based PCI ISA Printed Wiring Assembly PWA code named FM519 It describes functional blocks and their relationship The following diagram shows the functional blocks of the 519 Figure 1 1 FM519 Motherboard Block Diagram w lock Gen Crystal Media GX GX86 VGA System Controller RAMDAC PCI Bus ENCODER t Y C Video RCA Jack GX 5510 PCI IDE Bus Master Secondary IDE i SMC Ultra 37C93X RTC DS1287 PS 2 MOUSE IRDA CON IR BCM Advanced Research 1 1 gt FDD RTC COM 1 COM 2 519 Specification PRELIMINARY Overview The FM519 is an implementation of BCM Advanced Research for a High Volume motherboard featuring these subsystems Cyrix GX86 Single Chip Processor Cyrix 5510 Chipset One EISA Riser Card Sound Blaster Pro compatible sound Wavetable upgrade socket Integrated PCI Graphics Video Accelerator PCI IDE
4. 2 25 Table 2 23 Reset Connector Pinout eese eene enne 2 25 Table 2 24 CPU Fan Connector 2 26 Table 2 25 Power LED Connector Pinout 2 27 Table 3 1 SIMMs Configurations NITA SS SIA Nasta 3 1 Table 4 1 Main Menu Selections 4 3 Table 4 1 1 Standard CMOS eo 4 5 Table 4 1 2 BIOS Features 4 7 Table 4 1 3 Power Menu Selections a 4 9 Table 4 1 4 Integrated Peripherals Selections 4 11 Table 5 1 Absolute Maximum 5 1 Table 5 2 5 Volt DC Specifications 5 2 Table 5 3 3 6 Volt DC Specuican OD er oq He ee beca topi tone 5 2 Table 5 4 Power Supply Connector ee deoa dapes 5 3 Table 5 5 FM519 Motherboard Power Budget 5 4 Table 5 6 Environmental Specifications 5 4 Table 5 7 Motherboard nennen 5 5 Table 5 8 Accessible 5 5 Table 5 9 Accessible
5. 519 Specification PRELIMINARY Video Monitor Connector Connection to VGA monitor is via a connector on the rear panel on the system PWA Reference P1 VGA Connector Type female high density DB15S 15 pin AT compatible Connector Part Number 3M 927F55 01 15 10 or equivalent Table 2 7 Video Monitor Connector Pinout RED 1 6 RED GROUND RETURN 8 BLUEGROUNDRETURN 9 1 5V PULL UP LOGIC GROUND 1 Pins 16 and 17 are connector mounting holes connected to logic ground TV Output The TV output is generated by the CH7002 which is a fully integrated system solution for converting analog RGB and synchronization signals from a standard VGA source into high quality NTSC or PAL video signals This solution involves both hardware and software elements which work together to produce an optimum TV screen image based oh the original computer generated pixel data All essential circuitry for this conversion are integrated on chip On chip circuitry includes memory memory control scaling PLL ADC DAC filters and NTSC PAL encoder All internal signal processing including NTSC PAL encoding is performed using digital techniques to ensure that the high quality video signals are not affected by drift issues associated with analog components BCM Advanced Research 2 8 519 Specification PRELIMINARY The CH7002 is a complete TV output subsystem which uses both hardware and software element to produce an i
6. AUTO will automatically select which mode to use NORMAL can be used for drive smaller than 514MB LBA and LARGE can be used for drives larger than 514MB Select the type of floppy disk drive installed in your system Select the default video device System displays the error found and Press F1 to continue DEL to enter Setup unless disabled Base Memory N A Displays amount of conventional memory detected during bootup Extended Memory Other Memory N A N A A Displays the amount of extended memory detected during bootup Displays the amount of other memory detected during bootup Displays the total amount of memory detected during bootup DE drives do not require setting Landing Zone and Write Precomp These settings can only be changed when the Hard Disk is set to USER WARNING Incorrect settings can cause your system to malfunction BCM Advanced Research 4 5 519 Specification PRELIMINARY BIOS Features Setup You can make the following selections on the BIOS Features Setup Menu Figure 4 1 2 BIOS Features Setup ROM PCI ISA BIOS 2A59GB3J BIOS FEATURES SETUP AWARD SOFTWARE INC Virus Warning Enabled Quick Power On Self Test Enabled Boot Sequence A C Security Option Setup PS 2 mouse function control Enabled Ouit 41 gt lt Select Item Help PU PD Modify Old Values Shift F2 Color Load BIOS Defau
7. R aa 2 1 DRAM SIMM SOC KES if cet 2 1 System a a Mitth pn ce defui 2 2 Addres S conet taste AE boas ce pan I 2 2 e MI aa UR 2 2 VO Addr ss 2 3 Interrupt is ees 2 4 DMA Channels u E eee dde dat Foto adit 2 5 Video SUDSYSTISIN isa kaavaa Tm 2 6 x56 Integrated Functions 2 6 Graphics CELE ALON yaaa sett eee Et 2 6 Wis play Conta a aa uni hun 2 6 Video DA Canis 2 7 Video Monitor Connector esses 2 8 d eiue 2 8 TV Output CODBHOCIOEPS eode 2 10 Sound ei D ETSI LR m 2 10 edere SU UNT 2 11 Line Out Connector 2 12 DATS Out Hedqder s NK ve ane eiae iat 2 12 Microphone In Connectors a a der tdt UN er nep ive BOG 2 12 Microphone In Headef tico Ve erat ve 2 12 ISAJPCLI O RISCE CE s oeste da on tuv astitit 2 13 tete ben aree cc E ties cat aa 2 13 AT cae eat i 2 13 POL Titi ACG Ma ER OTT 2 13 ISA PCI I O Riser Connector
8. 519 system will support an ISA only PCI only or shared ISA PCI slots riser card The ISA PCI I O riser card contains decoupling capacitors between the voltage planes and ground to assist in both EMI and general voltage plane noise reduction The ISA PCI riser will be inserted into the system PWA during the system assembly process The riser connects to the system PWA through the J10 connector ISA Interface The FM519 incorporates a fully ISA bus compatible master and slave interface It is capable of driving five 5 ISA Slots without external data buffers This drive capability is required to ensure signal integrity for the ISA bus under loading conditions with the ISA PCI I O riser and expansion cards installed The ISA interface also provides byte swap logic and I O recovery support AT Bus Refresh The Cx5510 supports the standard ISA refresh function ISA refreshes are enabled by setting bit 6 in the ISA Configuration Register When enabled Timer 1 in the programmable interval timer is used to generate an internal refresh request signal When the ISA bus is not in use by the ISA bus controller the DMA controller or an ISA bus master the refresh control logic generates the ISA refresh cycle No DMA or PCI to ISA cycles occur until after the completion of this refresh cycle If the ISA bus is in use when the refresh request occurs the refresh controller waits until the bus is free and then generate a refresh cycle The Cx5510 al
9. Cyrix 5510 PCI ISA Chipset Integrated PCI Graphics amp Video Accelerator Shared Frame Buffer in Main Memory 1 to 2MB TV Output using Chrontel CH7002 SMC FDC37C935 Plug amp Play Compliant Two Asynch serial ports two 9 Pin connectors using High Speed 16C550 compatible ports with 16 byte FIFOs One 6 pin infrared port with Ir DA and ASKIR One 25 pin supporting EPP ECP and Centronics Interface PCI Bus Mastering IDE Native and Compatible Mode Support IDE Transfer with Scatter Gather Multiword DMA Transfers Mode 0 1 2 Enhanced IDE PIO Mode 3 amp 4 2 PCI IDE Connectors for 4 Drives Support 1 2 1 44 and 2 88 MB support PS 2 Integrated in the FDC37C935 PS 2 Integrated in the FDC37C935 Integrated in the FDC37C935 DS1287 Compatible Sound Blaster compatible sound Analog Devices AD1874DAC 16 bit Stereo iii 519 Specification PRELIMINARY FM Synthesis Built in OPL3 compatible System BIOS BIOS Type Phoenix Technologies Phoenix BIOS 95 2MB Flash BIOS Award BIOS also available Hard Disk Driver IDE Auto configuring Plug amp Play Support Steerable DMA Channels and Interrupts ISA Plug amp Play Special Features Windows 95 ready Multi Boot PCI add in card auto configuration Power Management Green Features APM1 2 Meets EPA Mod 2 0 SMI Stop Clock HDD and Monitor Shutdown Jumpers and Front Panel Connectors Connectors Reset Switch Green Suspend Resume Button Green LED PC Speaker HD L
10. ROM PCI ISA BIOS 2A59GB3J STANDARD CMOS SETUP AWARD SOFTWARE INC Date mm dd yy Wed Jan 1 1997 Time hh mm ss 16 12 21 HARD DISKS TYPE SIZE CYLS HEAD PRECOMP LANDZ SECTOR MODE Primary Master User 2576 624 128 63 LBA Primary Slave Auto 0 0 0 0 AUTO Secondary Master Auto 0 0 0 Secondary Slave None 0 0 Drive 1 44M 3 5 in None Base Memory 640K EGA VGA Extended Memory 15360K All Errors Other Memory 384K Total Memory 16384 11 gt lt Select PU PD Modify F10 Save amp Exit Setup Shift F2 Change Color BCM Advanced Research 4 4 519 Specification PRELIMINARY Table 4 1 1 Standard CMOS Setup Options Description MM DD YYYY Set the system date HH MM SS Set the system time Primary Master TYPE Primary Slave TYPE Secondary Master TYPE Secondary Slave TYPE Auto autotypes the drive at each boot User prompts the user to fill in remaining fields None indicates no drive is attached 1 45 fills in all remaining fields with values for predefined disk types SIZE Indicates the Size of the Hard Drive CYLS HEAD 1 16 384 1 16 Number of Cylinders Number of read write Heads PRECOMP Obsolete LANDZ Obsolete SECTOR Number of sectors per track MODE 16 63 AUTO 1 44M 3 1 2 88MB 3 None Video CG Halt On No Errors All But Keyboard All But Diskette All But Disk Key All Errors
11. Video OFF Method V H IRQ4 COM 1 ON SYNC Blank IRQ5 LPT 2 OFF MODEM Use IRQ 3 IRQ6 Floppy Disk OFF IRQ7 LPT 1 OFF Doze Mode 1 Min IRQ8 Alarm OFF Standby Mode 1 Min IRQ9 IRQ2 OFF Suspend Mode 1 Min IRQ10 Reserved OFF HDD Power Down 1 Min IRQ11 Reserved OFF IRQ12 PS 2 Mouse ON Wake Up Events in Doze amp Standby IRQ13 Coprocessor OFF IRQ3 Wake Up Event ON IRQ14 Hard Disk ON IRQ4 Wake Up Event ON Reserved OFF IRQ8 Wake Up Event ON IRQ12 Wake Up Event ON Quit 4 lt Select Item Help PU PD Modify Old Values Shift F2 Color Load BIOS Defaults BCM Advanced Research 4 8 519 Specification PRELIMINARY Table 4 1 3 Power Menu Selections Power Disable Max and Min set power mana ement options Management Min Saving with pre defined values Select User Define to Mode make your own selections from the following User Define fields Disabled turns off all power Max Saving management PM Control by When Yes is selected the Power Management APM features are controlled by an advanced operating system such as Windows95 When No is selected the BIOS will control power management Video Off Blank Screen V H When Blank Screen is selected the system Method SYNC Blank will only blank the screen when going into DPMS power saving mode When V H Sync Blan
12. Operating Environments PH 4 1 4 1 BIOSS eUID N 4 1 The Main 4 2 Standard CMOS S etUD u 2 a 4 3 BIOS Features e sai mu ase a a LE SE Ries 4 5 Power Management 4 7 Load BIOS 4 8 Integrated Peripherals 4 9 88 4 11 cen tee ule 4 11 Saye Exit Setup u as ie eec aee Ud c Hd ELTE uu Ce RR US 4 11 Operating 4 13 ata ea meee pace 4 14 s a SA S e RR antes 4 16 Section 5 Electrical Environmental and Mechanical Specification Absolute Maximum Ratings n 5 1 Electrical u rr 5 2 DC Specifications for 5V and 3 6 Signals 5 2 Power 5 3 Power Supply Connectors 5 3 BCM Advanced Research viii 519 Specification PRELIMINARY Input Power Budget 1 5 3 Environmental 5 4 Reliability Specific ation sus aie tole ged 5 5 Mechanica
13. SIMM4 Connector Type female 72 pin SIMM in line connector Connector Part Number AMP 822110 3 or equivalent BCM Advanced Research 2 1 519 Specification PRELIMINARY Table 2 2 DRAM SIMM Pinout Description DESCRIPTION PIN DESCRIPTION 1 SIGNAL GROUND 37 PARITY DATA 1 8 PARITY DATA 2 PARITY DATA 0 LOGIC GROUND BCM Advanced Research 2 2 519 Specification PRELIMINARY System BIOS The system and video BIOS are stored in a 2MB 256KBx8 Flash Memory device U4 The system BIOS is shadowed and cached Address Maps Memory Map The following table describes the breakdown of the FM519 memory areas and how they are assigned Table 2 3 Memory Map 000C0000 000C7FFF 32KB 800KB Video BIOS Shadowed in DRAM 000A0000 000BFFFF 128KB 768KB Video Buffer SMM space Non Cacheable 00080000 0009FFFF 128KB 640KB Optional memory space gap DOS Apps 00000000 0007FFFF 512KB 512KB DOS applications No read write protect Always cacheable I O Address Map The following table represents the system I O address map I O address range 000H to OFFH are reserved for the system board Address range 100h to are available to the I O on board resources Table 2 4 I O Address Map HEX RANGE SIZE Plug amp Play USAGE 0060 1 byte N A KEYBOARD CONTROLLER DATA BYTE N A KEYBOARD CONT CMD STATUS BYTE 0070 007F N A REAL TIME CLOCK NMI MASK 00 0 00 16 bytes N A RESERVED
14. for polygon fill of the pipeline operations described in the following list can be applied to any operation Pattern Memory Render with 8x8 dither 8 8 monochrome or 8x1 color pattern Color Expansion Expand monochrome bitmaps to full depth 8 bit or 16 bit colors Transparency Suppresses drawing of background pixels for transparent text Raster Operations Boolean operation combines source destination and pattern bitmaps Display Controller The display port interfaces directly to RAMDAC to drive a CRT display The display controller retrieves image data from the frame buffer region of memory performs a color look up if required inserts the cursor overlay into the pixel stream generates display timing and formats the pixel data for output to a variety of display devices The display controller contains Display Compression Technology that allows the Gx86 processor to refresh the display from a compressed copy of BCM Advanced Research 2 6 519 Specification PRELIMINARY the frame buffer DCT typically decreases the screen refresh bandwidth requirement by a factor of 15 to 20 further minimizing bandwidth contention Video DAC The ICS5342 GENDAC is a combination of dual programmable clock generators a 256 x 18 bit RAM and a triple 8 bit video DAC The GENDAC supports 8 bit pseudo color applications as well as 15 bit 16 bit and 24 bit True Color bypass for high speed direct access to
15. 00 0 1 byte CLEAR MATH COPROCESSOR ERROR N A RESET MATH COPROCESSOR N A MATH COPROCESSOR BCM Advanced Research 2 3 519 Specification PRELIMINARY 200 202 207 YES Rev GAME I O 1 1 1 1 238 23F SERIAL PORT 4 USED FOR REMAPPING PARALLEL PORT 2 DBO2DF 48bys ALTERNATE EGA ADAPTER SERIAL PORT 2 338 33F 8 bytes Y ES SERIAL PORT 3 USED FOR REMAPPING ES ADDRESS PORT PORT NO 378 37F YES PARALLEL PORT 1 3B0 3BF 16 bytes MONO DISPLAY amp PRINTER ADAPTER EGA ADAPTER CGA ADAPTER 3D0 3DF 16 bytes AIN 3 0 3 5 3F7 7 bytes YES FLOPPY CONTROLLER e S jomman 2 _ 3C0 3CF 16 bytes 3F83FF 8 SERIAL PORT 1 PCI CONFIGURATION SPACE BCM Advanced Research 2 4 519 Specification PRELIMINARY Interrupt Allocation Table 25 Interrupts Allocation INTERRUPT Plug amp Play DESCRIPTION IRQO N A TIMER KEYBOARD CONTROLLER IRQ2 N A IRQ FROM SECOND INTERRUPT poer CONTROLLER COM2 AND COM4 COMI AND COM3 YES SOUND PORT YES FLOPPY DISK CONTROLLER YES PRIMARY LPT N A YES YES YES IRQ8 NA REAL TIME CLOCK IRQ9 AVAILABLE IRQIO AV AILABLE AVAILABLE IRQ12 YES ON BOARD PS 2 MOUSE 18013 MATH COPROCESSOR 18014 PRIMARY IDE HARD DRIVE O 15 SECONDARY IDE HARD DRIVE IF PRESENT ELSE USER AVAILABLE DMA Channels Table 2 6 DMA Channels Allocation CHANNEL Plug amp Play DESCRIPTION DMAO YES Rev
16. 103321 4 BCM Advanced Research 2 24 519 Specification PRELIMINARY Table 2 20 MODEM IN Conn Pinout SIGNAL N 2 M 1 LOGIC GROUND Ea ODEM MIC OUT LOGIC GROUND MODEM SPKR IN Hard Drive LED Connector 1 2 straight header is available to the Hard Disk Drive LED on the front panel to indicate hard drive activity Reference J27 HD LED Connector Type 1 2 male straight 100 centers Connector Part Number AMP 103321 2 or eguivalent Table 2 21 HD Activity Indicator Pinout SIGNAL 1 5 V Pull Up HDACTIVE d GREEN Suspend Resume Connector 1 x 2 straight header is available for the suspend resume function of the power management logic it provides the system access to power management functions Reference J19 SUSPEND Connector Type 1X2 male straight 100 centers Connector Part Number AMP 103322 2 or equivalent Table 2 22 Suspend Resume Conn Pinout SIGNAL 1 LOGIC GROUND EXTERNAL SMI d zZ BCM Advanced Research 2 25 519 Specification PRELIMINARY RESET Connector A 1 2 straight header is available for the suspend resume function of the power management logic it provides the system access to power management functions Reference J25 RESET Connector Type 1X2 male straight 100 centers Connector Part Number AMP 103322 2 or equivalent Table 2 23 Reset Conn Pinout SIGNAL 1 RESET LOGIC GROUND FAN Connector A 1 3straight header is av
17. 2 5 Table 2 6 DMA Channels Allocation enne 2 5 Table 2 7 Video Monitor Connector Pinout esee 2 8 Table 2 8 RCA Jack Connector 60000000000 2 10 Table 2 9 Y C Video Connector 2 10 Table 2 10 GAME Port Header Pinout 2 11 Table 2 11 ISA PCI I O Reser Connector Pinoutl 2 14 Table 2 12 IDE Connector Pinout essere uquspa huq 2 17 Table 2 13 Floppy Connector PIIOUL eso o uot rtu s sett or 2 18 Table 2 14 Serial Port Connector Pinout 2 20 Table 2 15 Printer Port Connector 2 20 Table 2 16 Keyboard Connector Pinout 2 21 Table 2 17 Mouse Connector Pinout esee 2 22 Table 2 18 Infrared IrDA Connector Pinout 2 23 Table 2 19 PC Speaker Connector Pinoutl 2 24 Table 2 20 Modem In Connector Pinoutl 2 24 Table 2 21 Hard Drive LED Header Pinout 2 25 Table 2 22 Suspend Resume Connector 4
18. Buffers the input and output with two 128 byte FIFOs each holding 32 32 bit samples the 32 bit sample is 16 bits per stereo channel One FIFO is for audio input and one FIFO is for audio output For audio input output it interfaces with AD1847 Serial Port Codec Generates an SMI to alert software of required data update SMI is generated when either FIFO drops below separately programmable thresholds or when output FIFO is empty or input FIFO is full Also generates an SMI on I O traps Traps I O accesses for Sound Blaster compatibility at either 220h 22Fh 240h 24Fh 260h 26Fh or 280h 28Fh Traps I O accesses for ADLIB compatibility at 388h 38Bh Traps I O accesses for Roland MPU 401UART interface at 300h 301h or 330h 3318 Traps I O accesses for MIDI serial input and output at COM2 2F8h 2FFh or COM4 2E8h 2EFh Supports I O trapping for low 00h 0Fh and or high COh DFh DMA accesses Supports hardware status register reads in Cx5510 minimizing SMI overhead Generates IRQs for SB DSP chip compatibility support for software generated IRQs on IRO 2 3 5 7 10 11 12 13 14 and 15 GAME Port Header The FM519 provides access to the Joystick game compatible interface through a header in the system PWA Reference HDRI GAME Connector Type male 2 x 8 0 100 centerline straight BCM Advanced Research 2 11 519 Specification PRELIMINARY Connector Part Number AMP 103322 8 or equivalent Tab
19. ON BOARD AUDIO default 1 1 YES Rev ON BOARD AUDIO default 1 1 FLOPPY DISK CONTROLLER DMA4 N A 16 BIT DRQ DACK FROM SECOND DMA5 AVAILABLE DMA6 AVAILABLE DMA7 AVAILABLE BCM Advanced Research 2 5 519 Specification PRELIMINARY Video Subsystem Gx86 Integrated Functions The Cyrix Gx86 Integrated Processor integrates the following functions typically implemented using external devices High performance graphics accelerator Display Controller for the CRT EDO memory controller PCI Bridge Power management The processor has also been enhanced to support Cyrix s proprietary Virtual Systems Architecture implementation The Gx86 Integrated Processor is the first processor to implement a Unified Memory Architecture By using Cyrix s Display Compression Technology DCT the performance degradation inherent in traditional UMA systems is eliminated Graphics Accelerator The graphics accelerator is a full featured GUI accelerator The graphics pipeline implements a bitBLT engine for frame buffer bitBLTs and rectangular fills The bitBLT engine also assists the CPU in bitBLTs between system memory and the frame buffer by cooperating with new instructions in the integer core This combination of hardware and software is used by the display driver to provide very fast transfers in both directions between system memory and the frame buffer The bitBLT engine also draws randomly oriented vectors and scanlines
20. SA9 B24 IRQ4 A24 SAT SA6 SA5 SA4 SA3 SA2 GND SAO D6 IRQ13 C6 19 DE DACKO Al po DRQ X MRDC GND GND GND F2 GND E2 GND BCM Advanced Research 2 15 519 Specification PRELIMINARY KEY F9 GND KE GND NIC NIC N C N C PAR BCM Advanced Research 2 16 519 Specification PRELIMINARY 019 GND Storage Subsystem IDE Hard Disk Drive Interface The FM519 provides two 2 independent high performance PCI IDE interfaces capable of supporting PIO Mode 3 and Mode 4 devices The integrated IDE interface can control up to four IDE devices allowing for both CD ROM and Hard Disk drives IDE PRI amp IDE SEC are the primary and secondary IDE connectors Both IDE controllers can be disabled through BIOS to allow for external disk drive controllers Connection to the IDE hard disks is via headers on the system PWA Reference J6 J4 PRIMARY SECONDARY Connector Type male 2 x 20 0 100 centerline straight Connector Part Number AMP 2 103322 0 Table 2 12 IDE Connector Pinout 5 H6 06122 7 7 H DI 9 10 HDII HDO 25 O READ 26 LOGIC GROUND LOGIC GROUND 1 Pin 20 is removed as a key pin BCM Advanced Research 2 17 519 Specification PRELIMINARY Floppy Disk Drive Interface The FM519 has an integrated 765B compatible floppy disk controller using the SMC FDC37C935 component The FDC sub sec
21. stated benchmarks are for the 200MHz Pentium 55 MMX Processor using 32MB of main system memory with 256KB of external Pipeline Burst cache and a Ouantum 1280MB HD in Mode 4 The Video mode is set to 800x600 at 256 colors Table 4 6 Benchmark Figures WinBench97 V1 CPU mark 16 CPU mark 32 H G disk kb s WinStone97 H E Image WinStone32 Graphic DTP Word P S Overall CPU mark 16 CPU mark 32 Video mark Disk mark WinStone96 Graphic DTP Spreadsheet Word P S Norton 8 0 WinBench96 V1 Landmark BCM Advanced Research 4 14 519 Specification PRELIMINARY Compatibility BCM will supply necessary information and resources to assist the customer in the FM519 product qualification testing The product is designed for compatibility and shall be tested to the requirements set forth in the FM519 System Compatibility Test Plan BCM Advanced Research 4 15 519 Specification PRELIMINARY 5 Electrical Environmental and Mechanical Specifications This section specifies Electrical and Environmental parameters for the FM519 motherboard and describes its Mechanical characteristics Absolute Maximum Ratings Stresses beyond those shown in the following table may cause permanent damage to the system provided for stress testing only Table 5 1 Absolute Maximum Ratings Operating Temperature 0 C to 55 Supply Voltage with Respect to VSS 0 3 to 5 5 The
22. up to 128MB 2 Banks of DRAM Each bank can be single or double sided EDO Extended Data Out DRAM The BCM Advanced Research 1 2 519 Specification PRELIMINARY installed DRAM type can be 4MB 8MB 16MB 32MB or 64MB SIMMs and both Symmetrical or Asymmetrical DRAM technology are supported When only one bank of SIMMs is used it must be installed in Bank 0 PCI I O Bus The primary I O bus for the FM519 is PCI It supports up to three masters on the PCI bus The PCI bus operates at 33 MHz Embedded PCI Devices The PCI bus contains 2 embedded PCI devices PCI IDE interface and PCI Video Graphics controller using the Gx86 processor s internal video interface Arbitration for the PCI bus is performed by the Gx86 PCI GX Arbiter PCI Video Graphics Controller A high performance graphics Accelerator is integrated into the Cyrix Gx86 Processor Video memory is shared with system memory however by using Cyrix s Display Compression Technology DCT the performance degradation inherent in traditional UMA systems is eliminated An external video RAM DAC provides the output for the monitor TV Output A Chrontel CH7002 chip provides video output for a TV Both RCA and a S Video connectors are provided for this purpose PCI Bus Master IDE The Cyrix Cx5510 chip provides two integrated IDE controllers with two high performance IDE interfaces for up to four devices such as Hard Drives and CD ROM BCM Advanced Research 1 3 5
23. 19 Specification PRELIMINARY PCI Add in Cards High Performance PCI I O cards can be used in the FM519 through the expansion connectors in the riser card The PCI bus is specified to support 10 loads Each embedded controller or bridge Video PCI to ISA bridge count as 1 load each PCI expansion slot used in the riser card count as 1 5 loads the connector to the riser card count as 1 5 loads Sound Subsystem The Sound Section is intended to provide an integrated audio solution for business audio education entertainment sound games and multimedia applications Full compatibility with all of the De facto standards is provided The 519 incorporates all of the functions and interfaces for compatibility with the Sound Blaster card Embedded I O Subsystem The SMC Standard Microsystems Corp Plug and Play Ultra I O controller FDC37C935 represents the newest technology in functionality and integration While providing the standard PC I O requirements the Ultra I O complies with the ISA Plug and Play standard version 1 0a and provides for the recommended functionality to support Windows 95 The Ultra I O qualifies 16 bit address to allow relocation of 480 different addresses with 13 IRQ options and 3 DMA channels available for each logical device Other features of the Ultra I O are 8042 keyboard controller Real Time Clock An Infrared interface for and Floppy interface Two serial ports with 16 byte FIF
24. 80 2V 5 02 08 BCM Advanced Research 5 4 519 Specification PRELIMINARY Environmental The FM519 motherboard is intended for use in a Class environment residential The following table summarizes environmental limits for the FM519 operating and non operating Table 5 6 Environmental Specifications Thermal Map Must not exceed maximum IC junction temperature Non operating Random input 0 01 g2 Hz at 5Hz sloping to 0 02 g2 Hz at 20Hz and maintaining 0 02 g2 Hz from 20Hz to 500Hz Operating Not applicable 10K feet pressure altitude Specification Operating Indirect radiated only Test to ISKV with limited errors and to 25KV with no damage Specification Operating Required to meet EMI emission requirements tested as part of the system Reliability Specification The following table lists the hard MTBF for the motherboard A hard failure indicates that a permanent or repeatable failure that can be readily remedied by replacing the faulty part with a good one The listed MTBF is for the motherboard without a CPU or memory components Table 5 7 Motherboard MTBF BCM Advanced Research 5 5 519 Specification PRELIMINARY Configuration MTBF With Audio 198 316 Hours 35 Without Audio 227 737 Hours With Audio 153 390 Hours Without Audio 175 684 Hours BCM Advanced Research 5 6 519 Specification PRELIMINARY Mechanical System Interfaces User A
25. Bus Master interface Embedded advanced I O support LPX form factor motherboard The target Operating Systems for the FM519 are DOS Windows Windows 95 Windows NT OS 2 and UNIX Processor Subsystem The FM519 has the Cyrix Gx86 Processor soldered on the motherboard The Cyrix Gx86 Processor is an integrated 64 bit x86 compatible microprocessor The integration includes a high performance 2D graphics subsystem an integrated PCI interface and a unified memory subsystem Enhancements to the SMM architecture enable Cyrix s Virtual System Architecture VSA for Virtual VGA and Virtual Audio Cyrix s Display Compression Technology eliminates the performance degradation associated with traditional UMA system designs Cache and Memory Subsystem The cache and main memory DRAM control functions are part of the Cyrix Gx86 Processor The 16 KByte internal write back unified cache is a data instruction cache and is configured as four way set associative The cache stores up to 16 KBytes of code and data in 1024 cache lines The Gx86 provides the ability to allocate a portion of the L1 Cache as a scratchpad which is used to accelerate the Virtual Systems Architecture algorithms as well as for some graphics operations The 519 provides no second level cache Main Memory is provided through four 4 72 pin SIMM socket sites supporting either single or double sided DRAM modules in a 64 bit wide two bank arrangement The FM519 can support
26. DA Select mode for the second serial ASK IR Standard is used for normal seria communications IrDA is used for Infra Red communications at a rate of up to 115 kBaud ASK IR is used for Infra Red communication at up to 19 2kBaud Duplex Select Half Select Half or Full duplex to match the Full specification of the IR capable peripheral that is being used TxD RxD Active Sets the transmit and receive active level i e Hi Lo means that the transmit output is active high V and the receive input is active low Logic Ground Onboard Disabled Disable or Enable the Parallel Port 3BC 378 Parallel Port 3BC IRQ7 278 correspond to printer ports LPT3 LPT2 378 IRQ7 LPT1 respectively 278 IRQ5 Parallel Port Normal can be selected when the port is used Mode EPP1 74 SPP for printer only The Enhanced Parallel Port 1 7 EPP protocol is meant to be used with SPP eripherals such as CD ROM and Tape EPP1 9 SPP ackup The Extended Capabilities Port ECP protocol is meant to be used with multi function ECP EPP1 9 such as Fax Printer Modem evice ECP Mode used 1 3 Select the Dynamic Memory Address DMA DMA channel to be used by the parallel port Only available when ECP mode is selected Onboard Audio Enabled Enable or Disable the audio chip on the Chip Disabled motherboard BCM Advanced Research 4 11 519 Specification PRELIMINARY Supervisor Passwo
27. ED IRDA IR Remote Jumpers Password CMOS Clear BIOS Recovery NTSC PAL TV Out selection Headers and Rear Panel Connectors Headers Floppy IDE 1 amp 2 Serial 2 Port Game Port CD IN Modem In Connectors VGA Port Serial 1 Keyboard amp Mouse Parallel Port TV Out Mic In Line Out Mechanical Board Style LPX form factor Board Size Type 9 0 x 8 0 four layer board Expansion Slots Description One EISA riser slot for ISA and PCI buses BCM Advanced Research iv 519 Specification PRELIMINARY Document Structure and Outline The information contained in this document is organized into 5 sections Each section is of a modular format with non numbered headings for each major topic and sub topics First level headings 16 point Times New Roman always appear at the top of a new page and indicate the beginnings of a new major topic Pages are numbered by chapter and page e g 1 1 Figures and tables are numbered by chapter and sequence within the chapter The modular format allows for easy update of the documents as new information becomes available or as specifications change Some pages may contain more blank spaces than others this is done to confine major topics to page boundaries References from one section to topics in another are by section title rather than number This is done to maintain modularity For example a reference to a topic in Section 3 would be as follows Refer to Topic Heading in the
28. Functional Architecture section The content of each section is summarized below Section 1 Introduction Provide an overview of the FM519 motherboard showing functional blocks Section 2 Functional Architecture Describes the way each functional block of the 519 motherboard works Summarizes major bus interface signal pin names and their meaning Their mnemonics appear throughout this document Section 3 Configuration The 519 configuration tables with considerations for all the different environments the hardware can be set to is given Section 4 Operating Environments Describes the Software and Operating System environment The current Performance benchmarks are listed Section 5 Electrical Environmental and Mechanical Specifications Specifies electrical and operational parameters considerations and other hardware specifications BCM Advanced Research 519 Specification PRELIMINARY References The Following documents should be available for reference when using this document Order of Preference In the event of conflict between the requirements set forth in this document and the documents herein the requirements of this document shall prevail The order of precedence shall be 1 FM519 Specification this document 2 Referenced BCM internal documents 3 Referenced external documents Referenced BCM Internal Documents Several documents are reguired during the process of design reg
29. IC GROUND 6 DATA SET READYDSR 8 CLEAR TO SEND CTS 9 RING INDICATORRD 1 Pins 10 and 11 Shell Ground are mounting holes connected to the metal connector housing on serial port 2 Not used on serial port 1 Parallel port The system PWA has a single bi directional parallel port EPP ECP compatible The parallel port is capable of being disabled or remapped to either the secondary LPT address or the tertiary LPT address through BIOS if other parallel ports are installed in the system The parallel port I O address can be relocated within 480 different locations 3 DMA channels options and 13 different IRQ options are available to the parallel port A connector is located on the rear panel of the system PWA for the external connection to the port The parallel port interface contains 12mA source output drivers on the drive interface and incorporates ChipProtect circuitry for protection against damage due to printer Power On Reference J11 PRINTER Connector Type female 25 pin metal shell D SUB Connector Part Number AMP 750096 3 or equivalent Table 2 15 Printer Port Connector Pinout PIN DESCRIPTION BCM Advanced Research 2 20 519 Specification PRELIMINARY pat rats Sree AUTO FEED _ LOGIC GROUND TOGICGROUND 1 Pins 26 and 27 are connector mounting holes connected to the metal connector housing Keyboard Interface The system PWA has a
30. MC146818 compatible and provides the time of day clock 100 year calendar with alarm features and is accurate to within 1 minute per month it consumes less than 1 UA of standby current Typ The RTC supports 256 bytes of battery backed Non volatile CMOS memory in two banks of 128 bytes each both banks being reserved for BIOS use One bank of CMOS memory is used to maintain the clock and user system setting configuration parameters when the main system power is removed The other bank 128 bytes is lockable in 4x32 byte blocks and can be used to store and lock miscellaneous information BCM Advanced Research 2 22 519 Specification PRELIMINARY The CMOS RAM can be set to specific values or cleared to the system default values using the BIOS SETUP program Also to prevent a lock up situation the CMOS RAM values can be cleared to the system defaults by using the CLR CMOS jumper on the PWA Nonvolatile CMOS Memory Battery An external coin cell style battery provides power to the RTC and CMOS memory when system power is removed The battery has an estimated lifetime of seven years and is socketed for easy replacement Reference BTI Socket Type COIN TYPE IR Infra Red Support The FM519 I O subsystem incorporates an IR interface connector supporting the following industry standards HP SIR and ASK IR One header J24 labeled IRDA provides the interface allowing a two way wireless communication port using infrared as th
31. OUND Reference J2 Y C Video Connector Type TBD Connector Part Number TBD Table 2 9 Y C Video Connector Pinout SIGNAL GROUND GROUND GROUND GROUND 7 GROUND BCM Advanced Research 2 10 519 Specification PRELIMINARY Sound Subsystem The Cx5510 System controller incorporates features of the Virtual System Architecture VSA for the generation and capture of audio using an external DAC or Codec Virtual Audio is compatible with software written for the Sound Blaster II Pro and 16 and the Adlib audio cards Virtual Audio also emulates an MPU 401 UART using a COM port for MIDI serial transmit and receive The Cx5510 Virtual Audio hardware includes two 128 byte audio FIFOs to hold 32 audio samples two channels at 16 bits per channel for buffering digitized audio input and output from to the external DAC or Codec The audio FIFOs provide communication between the internal parallel bus and an external serial DAC or Codec The Cx5510 also contains a full set of configuration audio registers and hardware comparators for trapping and signalling I O accesses to the audio address range Cyrix Virtual Audio software emulates audio functions that are trapped by the Cx5510 This software is available to OEMs for incorporation into the system BIOS ROM The Cx5510 interfaces to the Analog Devices AD1847 Codec for audio playback and record The VSA Virtual Audio hardware resources in the Cx5510 perform the following functions
32. Os One EPP ECP supported bi directional parallel port BCM Advanced Research 1 4 519 Specification PRELIMINARY 2 Functional Architecture Processor Subsystem The Cyrix Gx86 processor that is used on the FM519 motherboard is soldered directly on the FM519 Motherboard and runs at either 30 120 33 133 MHz or 30 150 MHz A large heat sink is glued on the processor to eliminate the danger of over heating Memory Subsystem DRAM Subsystem The 519 supports four 36 bit 72 pin SIMM sockets SIMMI SIMM2 SIMM3 SIMMA allowing system memory from 8 MB to 128 MB of main DRAM Population must be done in pairs of SIMMs of the same memory type There are no jumpers settings required for the memory size or type which is automatically detected by the system BIOS The SIMM sockets have tin lead contacts rather than the more expensive gold contacts The SIMMs are rated at 60ns or better Only EDO Extended Data Out SIMMs are supported When only one bank is used the EDO SIMMs must be placed in bank 0 SIMMI and SIMM2 All the allowable memory size configurations are described on table 2 1 Refer to Table 3 2 in the Configuration section for the different combinations and sizes of SIMMs Table 2 1 DRAM memory configurations in Megabytes 8 16 24 32 40 48 64 72 80 96 128 DRAM SIMM Sockets Connection to the main system DRAM is via four 4 connectors on the system PWA Reference SIMM1 SIMM2 SIMM3
33. PS 2 compatible keyboard interface The shielded keyboard interface connector has a PS 2 compatible pinout and is located on the rear panel on the system PWA To meet the requirements for UL compliance the pin pin 4 is connected through a fuse prior to connection to the external connector Reference J2 KEYBOARD Connector Type female 6 pin metal shield mini DIN Connector Part Number 749231 1 or equivalent Table 2 16 Keyboard Connector Pinout KEYBOARD Vcc KEYBOARD CLOCK 6 INC SHELL GROUND BCM Advanced Research 2 21 519 Specification PRELIMINARY 8 SHELL GROUND 9 SHELL GROUND l Pins 7 9 are connector mounting hole pins connected to the metal connector housing Mouse Interface The system PWA has a PS 2 compatible mouse interface The shielded mouse port can be disabled through SETUP A connector utilizing PS 2 pinouts is located on the rear panel on the system PWA meet the requirements for UL compliance the Vcc pin pin 4 was connected through a fuse prior to connection to the external connector Reference J5 MOUSE Connector Type female 6 pin metal shield mini DN Connector Part Number AMP 749231 1 or equivalent Table 2 17 Mouse Connector Pinout 1 MOUSE DATA NIC SHELL GROUND SHELL GROUND SHELL GROUND 1 Pins 7 9 are connector mounting hole pins connected to the metal connector housing Real Time Clock The integrated Real Time Clock RTC is DS12887
34. ROM PCI ISA BIOS 2A59GB3J INTEGRATED PERIPHERALS AWARD SOFTWARE INC On Chip Primary PCI IDE Enabled Onboard Audio Chip Enabled On Chip Secondary PCI IDE Enabled USB Controller Disabled Onboard FDC Controller Enabled Onboard Serial Port 1 3F8 IRQ4 Onboard Serial Port 2 2F8 IRQ3 UART2 Mode IrDA Duplex Select Half TxD RxD Active Hi Lo Onboard Parallel Port 378 IRQ7 Parallel Port Mode ECP ECP Mode Use DMA 3 44 gt lt Select Item PU PD Modify Old Values Shift F2 Color Load BIOS Defaults BCM Advanced Research 4 10 519 Specification PRELIMINARY Table 4 1 4 Integrated Peripherals Selections Feature Options On Chip Primary Enabled Enable or Disable the corresponding on board Disabled IDE adapter USB Controller Enabled Disabled Enable or Disable the on board Universal Serial Bus USB controller Onboard FDC Enabled Enable or Disable the on board Floppy Disk Controller Disabled Drive controller Onboard Serial Disabled Disable or Enable the first onboard serial port Port 1 3F8 IRQ4 3F8 through 2E8 correspond to Com1 through 2F8 IRQ3 4 assignments respectively 3E8 IRQ4 2E8 IRQ3 Auto Onboard Serial Disabled Disable or Enable the second onboard serial Port 2 3F8 IRQ4 port 3F8 through 2E8 correspond to Com1 2F8 IRQ3 hrough 4 assignments respectively 3E8 IRQ4 2E8 IRQ3 Auto UART2 Mode Standard Ir
35. SETUP SUPERVISOR PASSWORD POWER MANAGEMENT SETUP USER PASSWORD LOAD BIOS DEFAULTS SAVE amp EXIT SETUP Esc Quit 11 gt lt Select Item F10 Save amp Exit Setup Shift F2 Change Color Time Date Hard Disk Type BCM Advanced Research 4 2 519 Specification PRELIMINARY Main Menu Selections The Main Menu Selections are as follows Table 4 1 Main Menu Selections Standard Use this menu for basic system configuration CMOS Setup such as Date Time Hard Drive Parameters and Floppy Drive Parameters BIOS Features Use this menu to set certain BIOS Features Setup available on your system s chipset Power Use this menu to configure Power Management Management features Setup Load BIOS Use this to load the BIOS Defaults except the Defaults Standard CMOS Setup Integrated Use this menu to configure the Onboard Peripherals peripherals such as Serial and Parallel Ports and Hard Drive and Floppy Drive Controllers Supervisor Setting a Supervisor Password restricts access Password to the BIOS Setup menus User User Password restricts access to the Password BIOS Setup menus or the System Save amp Exit Save all changes to CMOS and Exit the Setup Setup Utility Use the lt T gt J arrow keys to make a selection BCM Advanced Research 4 3 519 Specification PRELIMINARY Standard CMOS Setup You can make the following selections on the Standard CMOS Setup Menu Figure 4 1 1 Standard CMOS Setup
36. ailable for connecting a CPU Fan Reference J21 FAN Connector Type 1X3 male straight 100 centers Connector Part Number AMP 103322 3 or equivalent Table 2 24 Fan Conn Pinout PIN SIGNAL 1 GROUND BCM Advanced Research 2 26 519 Specification PRELIMINARY POWER ON LED Connector A 1 x 2 straight header is available for connecting an LED which indicates whether the system is fully powered up or in suspend mode The LED will be on when the system is fully powered up and flashing when the system is in suspend mode Reference J22 P S LED Connector Type 1X2 male straight 100 centers Connector Part Number AMP 103322 2 or equivalent Table 2 25 Power On LED Conn Pinout SIGNAL 1 P S 5V BCM Advanced Research 2 27 519 Specification PRELIMINARY 3 Configuration Product Configuration The PWA component will be produced by BCM with the microprocessor soldered directly on the board Therefore no jumpers need to be set for processor speed The only user selectable jumper is the Password CMOS Clear jumper DRAM Subsystem Configurations Table 3 6 SIMMs Configurations SIMMI SIMM2 SIMM3 SIMM4 Total Memory Advanced Research 3 1 519 Specification PRELIMINARY BCM Advanced Research 3 2 519 Specification PRELIMINARY 4 Operating Environments Software This product s software is referred to as BIOS Basic I
37. ccessible Sockets The following user accessible sockets are located on the top of the system PWA Table 5 9 Accessible Sockets User accessible Connectors The following user accessible connectors are located on top of the system PWA Table 5 10 Accessible Connectors NAME REFERENCE J9 CD IN CD Audio input connector J8 COM2 Serial Port 2 header J25 RESET Reset Switch connector J19 SUSPEND DE SECONDARY IDE SECONDARY Back Panel Interfaces The following interface connections are located on the rear panel of the system PWA Table 5 11 Back Panel Interfaces Keyboard connector BCM Advanced Research 5 7 519 Specification PRELIMINARY PS 2 Mouse connector Monitor connector J 1 TV Output RCA Jack J7 COM I portconnector Parallel port connector BCM Advanced Research 5 8 519 Specification PRELIMINARY Manufacturability Serviceability FM519 is designed to be both easy to manufacture and service The items specifically related to the system PWA are e Connector location amp labeling Jumper location amp labeling e PWA bar code label part number and revision Flash BIOS Memory location amp socket SIMM sockets labeling amp location BCM Advanced Research 5 9 519 Specification PRELIMINARY Regulatory BCM will supply information and resource to assist in the FM519 product qualification testing for compliance with the regulatory agency appr
38. device The Ultra I O device provides two 2 high speed NS16C550 compatible serial ports with send receive 16 Byte FIFOs One IR two pin port One Multi Mode Parallel Port with ChiProtect and ECP EPP modes And a Floppy Tape Controller supporting up to 2 88MB transfer rates Serial Ports The FM519 has two 2 NS16C550 AT compatible serial ports configured as Data Terminal Equipment DTE The electrical characteristics are compliant with the EIA 232 D Serial Communications Specifications The serial ports may be remapped above other installable serial ports or disabled through BIOS As a minimum the first serial port COM1 at J7 must be capable of remapping to COM3 The second serial port COM2 at J8 must be able to be remapped to COM4 The serial ports I O address can be relocated within 480 different locations The default address for COM1 COM2 COM3 and are 3F8H 338H 2F8H and 238H respectively 13 different IRQ options are available to the serial ports Connectors located on the rear panel of the system PWA are provided for external connection to the serial ports Reference J7 COMI Connector Type male 9 pin metal shell D SUB Connector Part Number Amp 750529 3 or equivalent Reference J8 COM2 Connector Type male 2x5 0 100 centerline straight Connector Part Number Amp 1 103322 5 or equivalent BCM Advanced Research 2 19 519 Specification PRELIMINARY Table 2 14 Serial Port Connector Pinout LOG
39. e transmission medium The user can transfer files to from portable devices such as laptops PDA s and printers using application software such as LapLink The IrDA port shares the registers and logic block with COM2 port once configured in the BIOS for IR a serial device in COM2 will stop transmitting IRDA Connector A 1 x 6 straight header is available for a cable connection to the IR module Reference J24 IRDA Connector Type 1 x 6 male straight 0 100 centers Connector Part Number AMP 103321 6 BCM Advanced Research 2 23 519 Specification PRELIMINARY Table 2 18 Infrared Conn Pinout PIN IR TX CIR_RX PIN 5 EN MISCELLANEOUS CONNECTORS PC Speaker Connector 1 4 straight header 718 is available to drive a chassis mounted speaker if desired Reference 718 SPEAKER Connector Type 1 x 4 male straight 0 100 centers Connector Part Number AMP 103321 4 Table 2 19 PC Speaker Conn Pinout ON BOARD BUZZER N C MODEM IN Connector A 1 x 4 straight header J12 is available to allow a speakerphone configuration when a Modem card is used in the system The circuitry will allow the voice from a phone line coming through a Modem card to be sent to the external speakers It will also send voice input from an external microphone through the Modem card and into the phone line Reference J12 MODEM IN Connector Type 1 x 4 male straight 0 100 centers Connector Part Number AMP
40. k is selected the system will also turn off the V SYNC and H SYNC signals DPMS mode can only be used by video card that adhere to the DPMS Standard Modem Use IRQ NA 3 4 5 7 9 Enter the Tanp that is used by the modem 10 11 if one smile Select NA if no modem is installe Doze Mode Time of inactivity required to enter the next Standby Mode i consecutive power saving ose These a selections are only available when the above Suspend Mode 6 Power Management feature is set to User efine Time without any disk access before the hard goes into standby mode i e motor turns off Wake Up events When the system is in Doze or Standby mode in Doze and accessing the enabled IRO turns the system Standby back to full power mode IRO 3 4 8 12 Power Down Any activity on the enabled IRO will reset the and Resume Power Management Timers to 0 If the system Events is in Power Saving Mode accessing the IRO 3 15 enabled IRO turns the system back to full power Load BIOS Defaults This feature allows the CMOS Settings to be reset to the original default values The values in the Standard CMOS Setup Menu such as date time and disk drive parameters are unaffected BCM Advanced Research 4 9 519 Specification PRELIMINARY Integrated Peripherals Selecting Integrated Peripherals from the Main Menu displays a menu like the one shown here Figure 4 1 4 Integrated Peripherals Menu
41. l 5 5 Systems LECT ACES Aus 5 5 USer ACCOSSIDIG Sockets y sa nu L 5 5 User accessible Connectors teet va AAA 5 5 Back Panel asa t tess ae TA oes 5 6 Manutacturabthty Serviceabllity sa kotaa ae 5 7 Kesulatoty oou EKS A STT ae cs e tfc mu a ds 5 8 Appendix A PWA xe etate ue at deitate de eet Du esteso sepes 5 10 BCM Advanced Research ix 519 Specification PRELIMINARY Figures Figure 1 1 FM519 Motherboard Block Diagram 1 1 Figure 4 1 BIOS Setup Main 4 1 Figure 4 1 1 Standard CMOS Setup 2 2 4 21 4 4 Figure 4 1 2 BIOS Features Setup Menu 4 6 Figure 4 1 3 Power Management Setup 4 8 Figure 4 1 4 Integrated Peripherals 4 10 BCM Advanced Research x 519 Specification PRELIMINARY Tables Table 2 1 DRAM memory configurations in Megabytes 2 1 Table 2 2 DRAM SIMM Pinout 2 2 Table 2 3 Memory 2 3 Table 2 4 Address eR pera da e eoe e Arena 2 3 Table 2 5 Interrupts Allocation
42. le 2 10 MIDI Game port Connector Pinout tr eil Bale o 1 ss 73 Line Out Connector The audio subsystem provides external sound through a user accessible stereo jack connector J16 soldered to the PWA This jack will allow the connection of self amplified speakers Reference J14 LINE OUT Connector Type 1 8 in Banana Jack Connector Connector Part Number Vendor 10XXXX 2 Line Out Header The audio subsystem also provides external sound through a header J15 soldered to the PWA This header will allow a jack on the front panel of the enclosure to be connected via a cable Reference J15 Connector Type 1X3 male straight 100 centers Connector Part Number AMP 103321 3 or equivalent Microphone In Connector An external accessible jack connector J14 is soldered to the PWA to allow the connection of a microphone for voice input Reference J12 MIC IN Connector Type 1 8 in Banana Jack Connector Connector Part Number Vendor 10XXXX 2 BCM Advanced Research 2 12 519 Specification PRELIMINARY Microphone In Header The audio subsystem also provides a microphone input through a header J13 soldered to the PWA This header will allow a jack on the front panel of the enclosure to be connected via a cable Reference J13 Connector Type 1X3 male straight 100 centers Connector Part Number AMP 103321 3 or equivalent ISA PCI VO Riser Card The
43. lts BCM Advanced Research 4 6 519 Specification PRELIMINARY Table 4 1 2 BIOS Features Setup Options Description Virus Warning Enabled If Enabled a warning message will appear on the Disabled Screen when any attempt is made to write to the boot sector of the Hard Disk Drive Quick Power Enabled If Enabled the system will shorten or skip certain On Self Test Disabled checks during the Power On Self Test POST The system will boot more quickly C The BIOS attempts to load the Operating System A from the disk drives in the sequence selected here Boot A Sequence C C CDROM A CDROM C A C only Security Setup When Setup is selected the system will neither Option System boot nor allow access to the CMOS Setup without entering the correct password When System is selected the system will boot but access to the CMOS Setup is restricted by password PS 2 Mouse Enabled Enables or Disables the on board PS 2 Mouse Disabled functionality ontro BCM Advanced Research 4 7 519 Specification PRELIMINARY Power Management Setup Selecting Power Management Setup from the Main Menu displays a menu like the one shown here Figure 4 1 3 Power Management Setup ROM PCI ISA BIOS 2A59GB3J POWER MANAGEMENT SETUP AWARD SOFTWARE INC Power Management Max Saving Power Down amp Resume Events PM Control by APM Yes IRQ3 COM 2 ON
44. mage on TV which is virtually identical to the image that would be displayed on a monitor Simply creating a compatible TV output from a VGA input is a relatively straightforward process This process includes a standard conversion from RGB to YUV color space converting from a non interlaced to an interlaced frame sequence and encoding the pixel stream into NTSC or PAL compliant format However creating an optimum computer generated image on a TV screen involves a highly sophisticated process of scaling deflickering and filtering This results in a compatible TV output that displays a sharp and stable image of the right size with minimal artifacts from the conversion process As a key part of the overall system solution the CH7002 software establishes the correct framework for the VGA input signal to enable this process Once the display is set to a supported resolution either 640x480 or 800x600 the CH7002 software may be invoked to establish the appropriate TV output display The software then programs the various timing parameters of the VGA controller to create an output signal that will be compatible with the chosen resolution operating mode and TV format Adjustments performed in software include pixel clock rates total pixels per line and total lines per frame By performing these adjustments in software the CH7002 can render a superior TV image without the added cost of a full frame buffer memory normally used to implement features
45. nput and Output Subroutine the BIOS resides as firmware in a non volatile memory device using Flash technology This technology gives the user the ability to be able to update the BIOS and accommodate changes to features or optimizations to better the performance of the system The user need only to load a diskette with the new BIOS firmware and follow the manufacturer instructions to update the BIOS General This product will have an Award Software Inc developed system Flash BIOS The BIOS will have a menu driven SETUP utility The specific features amp implementation requirements are to be provided by the OEM Customer if so desired BIOS Setup The SETUP Menu on your BIOS maybe slightly different than the one represented in here Different OEMs will require certain user access to advanced functions while other OEMs may not allow the user any access at all The exact BIOS Menu representation can be extracted from the BIOS supplied with your platform BCM Advanced Research 4 1 519 Specification PRELIMINARY The Main Menu To start the Award BIOS CMOS Setup utility 1 Turn on or reboot your system The Award BIOS displays this message at the bottom of the screen Press DEL to enter SETUP 2 Press the DELete Key to display the Main Menu which looks like this Figure 4 1 BIOS Setup Main Menu ROM PCI ISA BIOS 2A59GB3J CMOS SETUP UTILITY AWARD SOFTWARE INC STANDARD CMOS SETUP INTEGRATED PERIPHERALS BIOS FEATURES
46. ovals BCM Advanced Research 5 10 519 Specification PRELIMINARY BLANK BCM Advanced Research 5 11 519 Specification PRELIMINARY Appendix A PWA Layout HDDLED Speaker Reset IRDA P S LED CHRONTEL CH7002B 0000000000000 ANALOG DEVICES AD1847JP GENDAC 1655342 3 Riser Card 00000000 00000000 SMC FDC37C935 Cyrix CX5510 FLOPPY CMOSBatt IDE Primary IDE Secondary Keyboard mm pn pn Advanced Research 5 12
47. put Low Voltage Iout 1 5mA 2 041 3 BCM Advanced Research 5 2 519 Specification PRELIMINARY Power Supply Power Supply Connectors The input power is supplied via a pair of power supply connectors on the system PWA The connectors are positioned end to end to create a single row 1x12 Reference Connector male 1x12 156 centers Connector Part Number MOLEX 87218 1204 AMP 6440445 6 Table 5 4 Power Supply Connector PIN DESCRIPTION GROUND 6 8 GROUND S NOTE The shell may be keyed per customer s request to allow proper installation of the mating connectors Input Power Budget The 5V current available reflects the rating of the power connector The Power itself may deliver more so the system integrator must be sure that the total load does not exceed the system power supply or board power connector rating whichever is less The rating of the ISA slots is 4 5A per slot The ISA specification recommends supporting an average of 3 0A per slot The average current consumption may not exceed 3A per slot The system integrator must also guarantee that worst case power consumption does not exceed the maximum allowed by the motherboard power connector BCM Advanced Research 5 3 519 Specification PRELIMINARY Table 5 5 FM519 Motherboard Power Budget Voltage Current Load A DyV w5 L 00 01 00 55 30
48. rd Select a supervisor password to prevent access to the CMOS Setup Utility program without entering the proper password If the security option in the BIOS Features Setup is set to System a password must also be entered before the system will boot User Password Select a user password to prevent access to the CMOS Setup Utility program without entering the proper password If the security option in the BIOS Features Setup is set to System a password must also be entered before the system will boot If a supervisor password is also set up the CMOS Setup Utility program will be unavailable unless the supervisor password is entered Save amp Exit Setup This feature allows the changes to be made to the CMOS setup to be saved The system will resume booting after a successful save BCM Advanced Research 4 12 519 Specification PRELIMINARY Operating Systems The following operating system are required to be tested prior to First Customer Shipment FCS Windows 95 DOS 6 22 Netware 3 12 Netware 4 0 BCM Advanced Research 4 13 519 Specification PRELIMINARY Performance The benchmarks used to qualify performance include but are not limited to e Winstone96 97 Ver 1 0 e ZD Labs WINBENCH amp WINMARK 96 97 V1 0 e Norton SI version 8 0 and 9 0 Landmark System Speed Test 2 0 The following table is an expected minimum performance for FM519 systems under several of the common user benchmarks The
49. so supports refresh requests initiated by ISA masters PCI Interface The Gx86 CPU includes an integrated PCI controller with the following features BCM Advanced Research 2 13 519 Specification PRELIMINARY X bus PCI Slave 16 byte PCI write buffer 16 byte PCI read buffer from X bus Synchronization of 1x 2x 4x 5x PCI to X bus e Supports cache line bursting Write Inv line support Pacing of data for read or write operations with X bus No active byte enable transfers supported X bus PCI Master 16 byte X bus to PCI write buffer Synchronization of 1x 2x 4x 5x X bus to PCI Configuration read write Support nt Acknowledge support Lock conversion Support fast back to back cycles as slave Arbiter Fixed rotating hybrid or ping pong arbitration programmable Support four masters three on PCI Internal REQ for CPU Master retry mask counter Master dead timer Resource or total system lock support ISA PCI I O Riser Connector Connection to the PCI ISA riser is via a connector on the system PWA Reference J10 Connector Type female 198 pin edge connector Connector Part Number AMP 646039 1 or equivalent Table 2 11 PCI ISA Riser Connector SIGNAL NAME SIGNAL NAME GND IOCHK RSTDRV SD4 Bo DRQ A6 SD3 SD2 B9 0 A9 SDO BCM Advanced Research 2 14 519 Specification PRELIMINARY GND B16 DRQ3 16 SAIS
50. such as scaling and full synchronization Without this added system software TV output solutions can only guarantee compatible operation in VGA standard mode 12 640x480x16 color 60 Hz The CH7002 hardware accepts direct VGA output analog RGB inputs which is digitized on a pixel by pixel basis by three 8 bit video A D converters The digitized RGB inputs are then color space converted into YUV in 4 2 2 format encoded into luminance Y and color difference U V signals and stored in a line buffer memory The stored pixels are fed into a block where scan rate conversion underscan scaling and 3 line vertical flicker filtering are performed The scan rate converter transforms the VGA horizontal scan rate to either NTSC or PAL scan rates the vertical flicker filter eliminates flicker at the output while the underscan scaling reduces the size of the displayed image to fit onto a TV screen The resulting YW signals are filtered through digital filters to minimize aliasing problems The digital encoder receives the filtered signals and transforms them to composite and S video outputs which are converted by the three 8 bit DACs into analog outputs BCM Advanced Research 2 9 519 Specification PRELIMINARY TV Output Connectors Two connectors are provided to connect a TV to the board Reference RCA JACK Connector Type TBD Connector Part Number TBD Table 2 8 RCA Jack Connector Pinout PIN SIGNAL Composite Video GROUND 3 GR
51. the DACs The RAM makes it possible to display 256 colors selected from a possible 262 144 colors The dual clock generators use Phase Locked Loop PLL technology to provide programmable freguencies for use in the graphics subsystem The video clock contain 8 freguencies all of which are programmable by the user The memory clock has two programmable freguency locations The three 8 bit DACs on the ICSS342 are capable of driving singly or doubly terminated 752 loads to nominal 0 0 7 volts at pixel rates up to 135 MHz Differential and integral linearity errors are less than 1 LSB over full temperature and VDD ranges Monotonicity is guaranteed by design On chip pixel mask register allows displayed colors to be changed in a single write cycle rather than by modifying the color palette Features e Triple video DAC dual clock generator and 16 bit pixel port Dynamic mode switch allows switching color depth on a pixel by pixel basis 24 packed and sparse 16 15 or 8 bit pseudo color pixel mode supports True Color Hi Color and VGAmodes High speed 256x6x3 color palette 135MHz with bypass mode amp 8 bit DACs Eight programmable video pixel clock frequencies CLKO DAC power down in blanking mode Anti sparkle circuitry On chip loop filters reduce external components Standard CPU interface Single external crystal typically 14 318 MHz Monitor sense Internal voltage reference Very low clock jitter BCM Advanced Research 2 7
52. tion can control two 1 2 1 44 and 2 88MB floppy disks or compatible tape drives The floppy I O address can be relocated to 480 different locations 13 IRQ and 3 DMA channel options are available as well Includes multiple power down modes for reduced power use Connection to the floppy drives is via a header on the PWA The floppy disk interface contains 48mA drivers and Schmitt trigger inputs on the drive interface Reference J6 FLOPPY Connector Type male 2 x 17 0 100 centerline straight Connector Part Number AMP 1 103322 7 or equivalent Table 2 13 Floppy Connector Pinout PIN DESCRIPTION PIN DESCRIPTION 1 LOGIC GROUND 2 DENSITY SELECT LOGIC GROUND 6 LOGIC GROUND 8 INDEX 5 MEDIA IDO WRITE PROTECT 9 4 1 Pin 5 is removed as a key pin NM N I O SUBSYSTEM The I O Subsystem is consists of a single component from SMC Standard Microsystems Corp The FM519 uses the Plug and Play Compatible Ultra I O Controller FDC37C935 this device provides support for the ISA Plug and Play version 1 0a and includes the recommended functionality to support Windows 95 Through internal configuration registers each of the FDC37C935 s logical device s I O address DMA channel and IRO channel may be programmed There BCM Advanced Research 2 18 519 Specification PRELIMINARY are 480 I O address location options 13 IRQ options and 3 DMA channel options for each logical
53. topics in this section specify the normal operating conditions for the FM519 motherboard Exposure to absolute maximum rating conditions for extended periods may affect the system reliability BCM Advanced Research 5 1 519 Specification PRELIMINARY Electrical 519 DC specifications are summarized here for motherboard signaling environment power connectors and 5V power budget Refer to PCI Local Bus Specification Rev 2 0 and ISA Bus Specification for PCI and ISA DC and AC electrical specifications Refer also to the documentation for ASIC devices used on the FM519 motherboard DC Specifications for 5V and 3 6V Signals The following tables show the required DC specifications for 5V and 3 6V CPU bus signaling environment Table 5 2 5 Volt DC Specifications Supply Voltage 45 155 TA Operating Temperature Sat Air 0 15 Vih Input High Voltage 22 Vee 12 Vil InptLow Voltage 47 08 V Input High Current Vin 27 110 Input Low Current Vin 05 146 pe pese Vcc min Vcc min Table 5 3 3 6 Volt DC Specifications Vec3 Supply Voltage 30 36 Vih Input High Voltage 10475 x Vec3 Vee 05 V yil Input Low Voltage 05 V Input High Leakage Vin 2 7 10 Current Input Low Leakage Current Output High Voltage 0 5 0 9 C V Ou
54. ulatory approvals manufacturing and servicing the FM519 product family The reguired documents are as follows e 519 PWB Fabrication Drawing FM519 PWB Layout Artwork for each revision of PWB FM519 PWB Gerber Files FM519 Schematics for each revision of PWB amp PWA FM519 Assembly Drawings and Process Instructions All production level ECOs Bill of Material BOM with Approved Vendor List AVL Configuration Jumper combinations Referenced External Documents e PCI System Design Guide Revision 1 0 IBM AT Technical Reference Manual Cyrix GX86 Processor User s Manual and Data Sheet Cyrix 5510 External Design Specification AD AD1874DAC Data Book SMC FDC37C935 Data Sheet BCM Advanced Research vi 519 Specification PRELIMINARY TABLE OF CONTENTS Section 1 Introduction 1 2 Processor S BDSVSIETR 1 2 Cache and Memory Subsystem 1 2 PCLI O BUS detenti dere usi e t 1 3 Embedded PCLD6VICeS uu u a betae os Shae op a Theia 1 3 PCI Video Graphics Controller 1 3 1 3 PCT Bus Master IDE 1 3 PCI Add in Cards 1 3 SOUBd SUDSY SET i aede vius 1 4 Embedded VO Subsystem 1 4 Section 2 Functional Architecture Processor S 2 1 Memory 2 1 DRAM SuUDSystem
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