CLC021 SMPTE 259M Digital Video Serializer
Contents
1. Pin Name Description 1 Reset Manual Reset Input High True 2 NRZ NRZI NRZ to NRZI Conversion Control NRZ High NRZI Low 3 Test Out Test Out BIST Pass Fail Indicator 4 Vss Negative Power Supply Input Digital Logic 5 Vss Negative Power Supply Input Digital Logic 6 Vop Positive Power Supply Input Digital Logic 7 Vop Positive Power Supply Input Digital Logic 8 EDH Force Force Insertion of New EDH and Flags in Serial Output Data High True 9 EDH Enable EDH Enable Input Low True 10 SMPTE Mode SMPTE non SMPTE Mode Select Input SMPTE Mode Low 11 N C No Connect 12 DO Parallel Data Input Internal Pull Down to Vss 13 D1 Parallel Data Input Internal Pull Down to Vss 14 D2 Parallel Data Input Internal Pull Down to Vss 15 D3 Parallel Data Input Internal Pull Down to Vss 16 D4 Parallel Data Input Internal Pull Down to Vss 17 D5 Parallel Data Input Internal Pull Down to Vss 18 D6 Parallel Data Input Internal Pull Down to Vss 19 D7 Parallel Data Input Internal Pull Down to Vss 20 D8 Parallel Data Input Internal Pull Down to Vss 21 D9 Parallel Data Input Internal Pull Down to Vss 22 Polk Parallel Clock Input Internal Pull Down to Vss 23 H Line Field b0 LSB H Bit Output Component Line Field ID Composite 24 V Line Field b1 V Bit Output Component Line Field ID Composite 25 F Line Field b2 MSB F Bit Output Compone2. Supply Voltage Vpp Vss CLC021AVGZ 5 0V 6 0V CLC021AVGZ 3 3V 4 0V CMOS TTL Input Voltage Vi CLC021AVGZ 5 0V 0 5V to Vpp 0 5V CLC021AVGZ 3 3V 0 3V to Vpp 0 3V CMOS TTL Output Voltage Vo CLC021AVGZ 5 0V 0 5V to Vpp 0 5V CLC021AVGZ 3 3V 0 3V to Vpp 0 3V CMOS TTL Input Current single input Vi Vss 0 5V 5 mA Vi Vpp 0 5V 5 mA Input Current Other Inputs 1 mA CMOS TTL Output Source Sink Current 16 mA SDO Output Source Current 22 mA Package Thermal Oj 44 lead Metric PQFP 0 LFM airflow 60 C W Resistance 500 LFM airflow 43 C W Ojc 44 lead Metric PQFP 17 C W Storage Temp Range 65 C to 150 C Junction Temperature 150 C Lead Temperature Soldering 4 Sec 260 C ESD Rating HBM 2 kV ESD Rating MM 150V Transistor Count 33 400 1 Absolute Maximum Ratings are those parameter values beyond which the life and operation of the device cannot be ensured The stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values The table of Electrical Characteristics specifies acceptable device operating conditions 2 Itis anticipated that this device will not be offered in a military qualified version If Military Aerospace specified devices are required please contact the Texas Instruments Sales Office Distributors for availability and specifications RECOMMENDED OPERATING CO
3. 1 kHz filter bandwidth Hanning window Specification is ensured by design 5 Measured from rising edge of first Pok cycle until Lock Detect output goes high true 4 6 Submit Documentation Feedback Copyright 2000 2013 Texas Instruments Incorporated Product Folder Links CLC021 I TEXAS INSTRUMENTS www ti com CLC021 SNLS068H MAY 2000 REVISED APRIL 2013 TEST LOADS 1 0 uF 750 test equipment 500 test equipment attenuation 0 0 dB CMOS outputs attenuation 20 d8 SDO SDO c 453 o 75 Ro 500 test equipment L L attenuation 3 5 dB R 0 for 750 or 24 9 for 500 test eqpt 1 0 uF Hi Z test equipment gt 5kQ NA Hi Z test equipment gt 7500 En outputs attenuation 0 dB la ds 2 attenuation 0 dB i l 75 75 L C represents probe and test fixture capacitance Figure 2 Test Loads PARALLEL DATA amp CONTROL INPUTS 12 DO DO LOCK DET FLAG AND 13 INDICATOR D1 D1 TEST OUT OUTPUTS 14 D2 D2 H LFbO 15 D3 D3 V LFb1 16 D4 D4 F LFb2 17 ES D5 D5 PAL NTSC SER 18 VIDEO D6 D6 ANC 0 1uF OUTPUTS 19 EHH D7 D7 O SD 20 D8 D8 21 ae D9 D9 0 1 uF 22 Pork Perk O SDO 8 EDH FORCE 9 1 69kQ 750 750 EDH ENAB 1 1 1 10 _______ SMPTE MODE 41 gt Vop SYNC DET ENAB O NRZ NRZI uE RESET 4 7 uF 0 1 uF 29 TPG ENAB Q Vss Figure 3 Test Circuit Copyright 2000 2013 Texas Instruments Incorporated Submit Documentation Feedback
4. As such the jitter characteristics or jitter floor of the measurement equipment particularly the measurement analyzer become integral to the resulting jitter value The method and equipment were chosen so that the test can be easily duplicated by the design engineer using most standard digital video test equipment In so doing similar results should be achieved The intrinsic jitter floor of the CLC021 s PLL is approximately 25 of the typical jitter given in the electrical specifications In production device jitter is measured on automatic IC test equipment ATE using a different method compatible with that equipment Jitter measured using this ATE yields values approximately 50 of those obtained using the video test equipment The jitter test setup used to obtain values quoted in the data sheet consists of e Texas Instruments SD021 5EVK SD021 3EVK CLC021 evaluation kit e Tektronix TG2000 signal generation platform with DVG1 option e Tektronix VM700T Option 1S Video Measurement Set e Tektronix TDS 794D Option C2 oscilloscope e Tektronix P6339A passive probe e 750 coaxial cable 3 ft Belden 8281 or RG59 2 required e ECL to TTL CMOS level converter amplifier see Figure 12 Apply the black burst reference clock from the TG2000 signal generator s BG1 module 27 MHz clock output to the level converter input The clock amplitude converter schematic is shown in Figure 12 Adjust the input bias control to give a 50 duty cycle output as
5. 7 Product Folder Links CLC021 CLC021 gi ane SNLS068H MAY 2000 REVISED APRIL 2013 www ti com TIMING DIAGRAM TPG Enable Lock Detect Figure 4 Setup and Hold Timing 8 Submit Documentation Feedback Copyright 2000 2013 Texas Instruments Incorporated Product Folder Links CLC021 14 Ti INS FRUMENES CLC021 www ti com SNLS068H MAY 2000 REVISED APRIL 2013 DEVICE OPERATION The CLC021 SMPTE 259M Serial Digital Video Serializer is used in digital video signal origination equipment cameras video tape recorders telecines and video test and other equipment It converts parallel component or composite digital video signals into serial format Logic levels within this equipment are normally TTL compatible as produced by CMOS or bipolar logic devices The encoder produces ECL compatible serial digital video SDV signals conforming to SMPTE 259M 1997 The CLC021 operates at all standard SMPTE and ITU R parallel data rates In addition the CLC021 can serialize other 8 and 10 bit data VIDEO DATA PROCESSING CIRCUITS The input data register accepts 8 or 10 bit parallel data and clock signals having HCMOS LSTTL compatible signal levels Parallel data may conform to any of several standards SMPTE 125M SMPTE 267M SMPTE 244M or ITU R BT 601 If the data is 8 bit it is converted to a 10 bit representation according to the type of data being input component 4 2 2 per SMPTE 259M paragraph 7 1 1 composite NTSC per pa
6. Folder Links CLC021 CLC021 SNLS068H MAY 2000 REVISED APRIL 2013 AC ELECTRICAL CHARACTERISTICS CLC021 AVGZ 5 0 Over Supply Voltage and Operating Temperature ranges unless otherwise specified I TEXAS INSTRUMENTS www ti com Symbol Parameter Conditions Reference Min Typ Max Units BRspo Serial Data Rate See 2 SDO SDO 100 400 Mbps Foa pat Frequency Pork 10 40 MHz aa Clock Duty Paik 45 50 55 tr t Rise Time Fall Time Dn Perk 1 0 1 5 3 0 ns ti Serial Output Jitter 270 Mbps See Figure 3 220 PSp p tit Serial Output Jitter See 2 4 a 100 200 PSp p 5 SDO SDO tr Rise Time Fall Time 20 80 2 4 500 800 1500 ps Output Overshoot See 4 1 tLock Lock Time See 2 5 75 us tsu Setup Time See and Figure 4 Dy to Pork 3 2 ns tut Hold Time See and Figure 4 Dy from Perk 3 2 ns Leen Output inductance See 4 spe s0 6 nH Raen Output Resistance See 4 25k Q 1 Typical values are stated for Vpp 5 0V CLC021AVGZ 5 0 or 3 3V CLC021AVGZ 3 3 and Ta 25 C 2 2 Ri 750 AC coupled 270 Mbps Rrer 1 69 KQ 1 See TEST LOADS and Figure 3 3 CLC021 mounted in the SD021EVK board configured in BIST mode NTSC colour bars with Perk 27 MHz derived from Tektronix TG2000 black burst reference Timing jitter measured with Tektronix VM700T using jitter measurement FFT mode frame rate 1 kHz filter bandwidt
7. Test Pattern Generators and Digital Video Test Equipment Video Signal Generators e Non SMPTE Video Applications e Other High Data Rate Parallel Serial Video and Data Applications DESCRIPTION The CLC021 SMPTE 259M Digital Video Serializer with EDH Generation and Insertion is a monolithic integrated circuit that encodes serializes and transmits bit parallel digital data conforming to SMPTE 125M and 267M component video and SMPTE 244M composite video standards The CLC021 can also serialize other 8 or 10 bit parallel data The CLC021 operates at data rates from below 100 Mbps to over 400 Mbps The serial data clock frequency is internally generated and requires no external frequency setting trimming or filtering components CLC014 Adaptive Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet All trademarks are the property of their respective owners PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of the Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters Copyright 2000 2013 Texas Instruments Incorporated CLC021 OE SNLS068H MAY 2000 REVISED APRIL 2013 www ti com DESCRIPTION CONTINUED Functions performed by
8. measured on the oscilloscope probe system Connect the level translator to the SD021EVK board connector P1 Perk pins the outer most row of pins is ground Configure the SD021EVK to operate in the NTSC colour bars BIST mode Configure the VM700T to make the jitter measurement in the jitter FFT mode at the frame rate with 1 kHz filter bandwidth and Hanning window Configure the setup as shown in Figure 11 Switch the test equipment on from standby mode and allow all equipment temperatures stabilize per manufacturer s recommendation Measure the jitter value after allowing the instrument s reading to stabilize about 1 minute Consult the VM700T Video Measurement Set Option 1S Serial Digital Measurements User Manual document number 071 0074 00 for details of equipment operation The VM700T measurement system s jitter floor specification at 270 Mbps is given as 200 ps 20 100 ps 5 typical of actual components from 50 Hz to 1 MHz and 200 ps 60 30 of actual components from 1 MHz to 10 MHz To obtain the actual residual jitter of the CLC021 a root sum square adjustment of the jitter reading must be made to compensate for the measurement system s jitter floor specification For example if the jitter reading is 250 ps the CLC021 residual jitter is the square root of 250 200 150 ps The accuracy limits of the reading as given above apply Precision SDO21EVK 75Q Coaxial Cable 27MHz CLC021 e E dl TTL Clock Evaluation Kit Video Measu
9. non SMPTE mode The outputs are active HIGH true For composite video these outputs correspond to the line and field ID encoded as input parallel data bits 2 MSB through 0 These outputs are registered for the duration of the applicable field 2 NSP New Sync Position A function and output indicating that a new or out of place TRS character has been detected This output remains active for at least one horizontal line period reset by EAV or unless re activated by a subsequent new or out of place TRS Activation of this function flushes the existing state of the machine reseting the EDH generator SMPTE polynomial generator serializer and NRZ NRZI converter This function is disabled in non SMPTE mode operation The output is active HIGH true 3 ANC Ancilliary data location output Indicates that the ancilliary data header component or flag composite has been detected The output is a pulse having a duration of one Perk period The output is active HIGH true SMPTE POLYNOMIAL GENERATOR AND CONTROLS The SMPTE Mode input allows the CLC021 to function both as a full SMPTE 259M encoder or general purpose 8 or 10 bit serializer SMPTE mode is enabled when this input is LOW Non SMPTE mode is enabled when this pin is HIGH This pin is pulled internally to Vss when unconnected When in SMPTE mode the SMPTE polynomial generator TRS sync detection circuitry EDH control circuitry H V F and NSP outputs and TRS clipping are enabled The S
10. 13 TEXAS INSTRUMENTS www ti com CLC021 SNLS068H MAY 2000 REVISED APRIL 2013 CLC021 SMPTE 259M Digital Video Serializer with EDH Generation and Insertion Check for Samples CLC021 FEATURES e SMPTE 259M Serial Digital Video Standard Compliant e Supports All NTSC and PAL Standard Component and Composite Serial Video Data Rates No External Serial Data Rate Setting or VCO Filtering Components Required e Fast VCO Lock Time lt 75 us at 270 Mbps e Built In Self Test BIST and Video Test Pattern Generator TPG with 16 Internal Patterns Automatic EDH Character and Flag Generation and Insertion per SMPTE RP 165 e Non SMPTE Mode Operation as Parallel to Serial Converter NRZ to NRZI Conversion Control HCMOS LSTTL Compatible Data and Control Inputs and Outputs for CLC021AVGZ 5 0 LVCMOS for CLC021AVGZ 3 3 e 750 ECL Compatible Differential Serial Cable Driver Outputs e Single Power Supply Operation 5V CLC021AVGZ 5 0 or 3 3V CLC021AVGZ 3 3 in TTL or ECL Systems Low Power Typically 235 mW JEDEC 44 Lead Metric PQFP Package Commercial Temperature Range 0 C to 70 C 1 Patents Applications Made or Pending TYPICAL APPLICATION sve CLC021 Data SDV Serializer Cable Driver Input 75Q Coaxial Cable Cable SMPTE 259M Equalizer Serial Data APPLICATIONS e SMPTE 259M Parallel to Serial Digital Video Interfaces for Video Cameras VTRs Telecines Video
11. MPTE polynomial generator accepts the parallel video data and encodes it using the polynomial X X 1 as specified in SMPTE 259M 1997 rev paragraph 5 and Annex C The transmission bit order is LSB first per paragraph 6 Copyright 2000 2013 Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links CLC021 CLC021 OE SNLS068H MAY 2000 REVISED APRIL 2013 www ti com NRZ TO NRZI CONVERTER The NRZ to NRZI converter accepts NRZ serial data from the SMPTE and EDH polynomial genertors and converts it to NRZI using the polynomial X 1 per SMPTE 259M paragraph 5 2 and Annex C The converter s output goes to the output buffer amplifier The NRZ NRZI input enables this conversion function Conversion from NRZ to NRZI is enabled when the input is a logic LOW Conversion to NRZI is disabled when this input is a logic HIGH This function is not affected by the SMPTE mode control input The input pin is pulled internally to Vss NRZI enabled when unconnected EDH SYSTEM OPERATION The CLC021 has EDH character and flag generation and insertion circuitry which operates as proposed in SMPTE RP 165 Inputs and circuitry are provided to control generation and automatic insertion of the EDH check words at proper locations in the serial data output The EDH polynomial generators accept parallel data from the input register and generate 16 bit serial check words using the polynomial X X1 X 1 Separate calculat
12. NDITIONS Supply Voltage Vpp Vss CLCO21AVGZ 5 0 5 0V 10 CLC021AVGZ 3 3 3 3V 10 CMOS TTL Input Voltage Vss to Vop Maximum DC Bias on SDO pins CLCO21AVGZ 5 0 3 0V 10 CLC021AVGZ 3 3 1 3V 10 Perk Frequency Range 10 to 40MHz Peck Duty Cycle 45 to 55 Dn and Pci Rise Fall Time 1 0 to 3 0 ns Operating Free Air Temperature Ta 0 C to 70 4 Submit Documentation Feedback Copyright O 2000 2013 Texas Instruments Incorporated Product Folder Links CLC021 14 Ti INS FRUMENES CLC021 www ti com SNLS068H MAY 2000 REVISED APRIL 2013 DC ELECTRICAL CHARACTERISTICS CLC021AVGZ 5 0 Over Supply Voltage and Operating Temperature ranges unless otherwise specified 12 Symbol Parameter Conditions Reference Min Typ Max Units Vin Input Voltage High Level 2 0 Vop V V Input Voltage Low Level V 0 8 V L p All CMOS Inputs Ss lin Input Current High Level Vin Vpop 40 60 yA lit Input Current Low Level Vit Vss 1 20 uA VoH CMOS Output Voltage High lop 10 mA 24 47 V V Level gt DD All CMOS Outputs VoL CMOS Output Voltage Low lo 10 mA 0 0 0 3 Vos 0 5V V Level Vspo Serial Driver Output Voltage Ri 750 1 Rrer 1 69 KQ 1 SDO SDO 700 800 900 mVp p See Figure 3 lbo Power Supply Current Total RL 750 1 Reger 1 69 KQ 1 Perk 27 MHz NTSC 47 60 mA Colour Bar Pattern See Figure 3 1 Current fl
13. NERATOR POWER ON RESET PAL ay ck NTSC SYNC ANG AND NSP AAA Formar H E DETECTOR v t PLL SYSTEM os L REGISTER per py Tet DET ee R S POLYNOMIAL NRZ NRZI i EDH GENERATOR CONVERTER 0 PROCESSORS is Rrer EDH amp SMPTE MODE Pork CONTROL 2 Submit Documentation Feedback Copyright 2000 2013 Texas Instruments Incorporated Product Folder Links CLC021 14 Ti INS FRUMENES CLC021 www ti com SNLS068H MAY 2000 REVISED APRIL 2013 CONNECTION DIAGRAM _ SMPTE MODE o EDH ENAB NRZI o EDH FORCE f Vop of TEST OUT NE NRZ RESET of Vbo af Vss gt Vss o DO 447 PAL NTSC D1 43 ANC D2 42 NSP D3 41 SYNC DET ENAB D4 401 Voosp D5 CLC021AVGZ 39 _ SDO D6 38 SDO D7 37 _ Vssso D8 36 Vonon D9 35 Ree Pork 34 N C N dal N N F LFb2 H LFbO 7 LOCK DET 7 V LFb1 7 TPG ENAB D Figure 1 44 Pin Metric PQFP See Package Number PGB0044A Copyright O 2000 2013 Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links CLC021 CLC021 SNLS068H MAY 2000 REVISED APRIL 2013 TEXAS INSTRUMENTS www ti com A These devices have limited built in ESD protection The leads should be shorted together or the device placed in conductive foam hid during storage or handling to prevent electrostatic damage to the MOS gates ABSOLUTE MAXIMUM RATINGS 2
14. an annual basis Addendum Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections enhancements improvements and other changes to its semiconductor products and services per JESD46 latest issue and to discontinue any product or service per JESD48 latest issue Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All semiconductor products also referred to herein as components are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment Tl warrants performance of its components to the specifications applicable at the time of sale in accordance with the warranty in Tl s terms and conditions of sale of semiconductor products Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by applicable law testing of all parameters of each component is not necessarily performed Tl assumes no liability for applications assistance or the design of Buyers products Buyers are responsible for their products and applications using TI components To minimize the risks associated with Buyers products and applications Buyers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any paten
15. at RP1 and RP3 when using 500 source loading The board s outputs may be DC interfaced to PECL inputs by first installing 1240 resistors at R1B and R2B changing R1A and R2A to 1870 and replacing C1 and C2 with short circuits The PECL inputs should be directly connected to J1 and J2 without cabling If 75Q cabling is used to connect the CLC021 to the PECL inputs the voltage dividers used on the CLC021 outputs must be removed and re installed on the circuit board where the PECL device is mounted This will provide correct termination for the cable and biasing for both the CLC021 s outputs and the PECL inputs It is most important to note that a 750 or equivalent DC loading measured with respect to the negative supply rail must always be installed at both of the CLCO21 s SDO outputs to obtain proper signal levels from device When using 75Q Thevenin equivalent load circuits the DC bias applied to the SDO outputs should not exceed 3V 1 3V for CLC021AVGZ 3 3 with respect to the negative supply rail Serial output levels should be reduced to 400 mV by changing Rrer to 3 4 KQ This may be done by removing the Output Level shorting jumper on the post header Copyright 2000 2013 Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links CLC021 I TEXAS CLC021 INSTRUMENTS SNLS068H MAY 2000 REVISED APRIL 2013 www ti com The Test Out output is intended for monitoring by equipment having high impedance test loadin
16. e 1 BIST and Test Pattern Generator Control Functions Pin Name Function 12 DO TPG Code Input LSB 13 D1 TPG Code Input 14 D2 TPG Code Input 15 D3 TPG Code Input MSB 29 TPG_EN TPG Enable Active High True 3 Test_Out BIST Pass Fail Output Pass High See text for Timing Requirements Table 2 Component Video Test Pattern Selection Standard Frame Test Pattern D3 D2 D1 DO NTSC 4x3 Flat Field Black 0 0 0 0 NTSC 4x3 PLL Pathological 0 0 0 1 NTSC 4x3 EQ Pathological 0 0 1 0 NTSC 4x3 Colour Bars 75 8 Bars modified see text BIST 0 0 1 1 PAL 4x3 Flat Field Black 0 1 0 0 PAL 4x3 PLL Pathological BIST 0 1 0 1 PAL 4x3 EQ Pathological 0 1 1 0 PAL 4x3 Colour Bars 75 8 Bars modified see text 0 1 1 1 NTSC 16x9 Flat Field Black 1 0 0 0 NTSC 16x9 PLL Pathological 1 0 0 1 NTSC 16x9 EQ Pathological 1 0 1 0 NTSC 16x9 Colour Bars 75 8 bars modified see text 1 0 1 1 PAL 16x9 Flat Field Black 1 1 0 0 PAL 16x9 PLL Pathological 1 1 0 1 PAL 16x9 EQ Pathological 1 1 1 0 PAL 16x9 Colour Bars 75 8 Bars modified see text 1 1 1 1 1 D9 through D4 0 binary Copyright 2000 2013 Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links CLC021 CLC021 SNLS068H MAY 2000 REVISED APRIL 2013 A Texas INSTRUMENTS www ti com PIN DESCRIPTIONS
17. el data clock frequency This system consists of a VCO divider chain phase frequency detector and internal loop filter The VCO free running frequency is internally set The PLL automatically generates the appropriate frequency for the serial clock rate using the parallel data clock Pc x frequency as its reference Loop filtering is internal to the CLC021 The VCO halts when no Pc x signal is present or is inactive Pc xk should be applied after power to the device The VCO has separate Vsso and Vppo power supply feeds pins 27 and 28 which may be supplied power via an external low pass filter if desired The PLL acquisition lock time is less than 75 us 270 Mbps LOCK DETECT The lock detect output pin 26 of the phase frequency detector is a logic HIGH when the loop is locked The output is CMOS TTL compatible and is suitable for driving other CMOS devices or an LED indicator The Lock Detect pin reports the status of the PLL When Pc x is lost it will switch low at the event SERIAL DATA OUTPUT BUFFER The current mode serial data outputs provide low skew complimentary or differential signals The output buffer design can drive 750 coaxial cables AC coupled or 10K 100K ECL PECL compatible devices DC coupled Output levels are 800 MVp p 10 into 750 AC coupled back matched loads The output level is 400 mVp p 10 when DC coupled into 750 See APPLICATION INFORMATION for details The 750 resistors connected to the SDO outputs a
18. erk 0 A e s E s Vos ue rn ka 8 Figure 5 Power On Reset Sequence Vemi enti Vo gt Ons min Vss 90 E 90 RESET E 10 E 10 Vss _ 22222000 pe pe fe Fe 4 mers Pork 0 0 0 0 t 0 i 0 0 0 0 0 0 0 0 0 0 0 0 e 0 0 Ye ef Sah A A A a Figure 6 Power On Reset Sequence with Manual Reset Copyright 2000 2013 Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links CLC021 CLC021 gi eae SNLS068H MAY 2000 REVISED APRIL 2013 www ti com BUILT IN SELF TEST BIST The CLC021 has a built in self test BIST function The BIST performs a comprehensive go no go test of the device The test uses either a full field colour bar for NTSC or a PLL pathological for PAL as the test data pattern Data is input internally in the input data register processed through the device and tested for errors A go no go indication is given at the Test_Output Table 1 gives device pin functions and Table 2 gives the test pattern codes used for this function The signal level at Test_Output pin 3 indicates a pass or fail condition The BIST is initiated by applying the code for the desired BIST to DO through D3 D9 through D4 are 00h anda 27 MHz clock at the Pc x input Since all parallel data inputs are equipped with an internal pull down device only those inputs DO through D3 which require a logic 1 need be pulled high After the Lock_Detect output goes high indicating the VCO is
19. evision H Page e Changed layout of National Data Sheet to Tl format cceeecececceeeeeeeecneeeeaeeeseeeeaeeeeeeeeaeeseaeesaeeseaeeeaeeseaeeseesnaeesieeeeeeeeeees 20 Copyright 2000 2013 Texas Instruments Incorporated Submit Documentation Feedback 21 Product Folder Links CLC021 H PACKAGE OPTION ADDENDUM IA TEXAS INSTRUMENTS www ti com 12 Oct 2014 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Op Temp C Device Marking Samples 0 Drawing Qty 2 6 3 4 5 CLC021AVGZ 3 3 NRND QFP PGB 44 96 TBD Call TI Call TI 0 to 70 CLCO21A VGZ 3 3 CLC021AVGZ 3 3 NOPB ACTIVE QFP PGB 44 96 Green ROHS CU SN Level 3 260C 168 HR 0 to 70 CLCO21A 5 i amp no Sb Br VGZ 3 3 CLC021AVGZ 5 0 NOPB ACTIVE QFP PGB 44 96 Green ROHS CU SN Level 3 260C 168 HR 0 to 70 CLCO21A 5 l amp no Sb Br VGZ 5 0 The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but Tl does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan The planned eco friendly classificati
20. g gt 5000 If the Lock Detect output is to be externally monitored the attached monitoring circuit should present a DC resistance greater than 5 kQ so as not to affect Lock Detect indicator operation RP2 330Q RP1 2209 BB Vop HLMP 4700 LOCK DET H LFbo V LFb1 F LFb2 TEST OUT PAL NTSC 9 R2 J2 SMPTE MODE NRZ NRZI RB 1 69kQ 1 R6 SYNC DET ENAB 1 69kQ TPG ENAB I CLC021AVGZ Sie swt At E BEDS Uke JE NORMAL JUMPERS RESET 51 I lo 1 RP4 3309 lt is is Sole SSS SSS 1 RP3 220 Connect LOCK DETECT to TPG ENABLE for test pattern generator function Remove RP1 8 RP3 and replace RP2 amp RP4 with 500 resistor packs for coax interfacing Install RP1 4 when using ribbon cable for input interfacing This board is designed for use with TTL power supplies only Figure 10 SD021EVK Schematic Diagram 16 Submit Documentation Feedback Copyright 2000 2013 Texas Instruments Incorporated Product Folder Links CLC021 14 Ti INS FRUMENES CLC021 www ti com SNLS068H MAY 2000 REVISED APRIL 2013 MEASURING JITTER The test method used to obtain the timing jitter value given in the AC Electrical Specification table is based on procedures and equipment described in SMPTE RP 192 1996 The recommended practice discusses several methods and indicator devices An FFT method performed by standard video test equipment was used to obtain the data given in this data sheet
21. h Hanning window Specification is ensured by design 5 Measured from rising edge of first Pc x cycle until Lock Detect output goes high true 4 AC ELECTRICAL CHARACTERISTICS CLCO21AVGZ 3 3 Over Supply Voltage and Operating Temperature ranges unless otherwise specified Symbol Parameter Conditions Reference Min Typ Max Units BRspo Serial Data Rate See 2 SDO SDO 100 400 Mbps Pue fiers Cos Pox 0 wi o Clock Duty Pole 45 50 55 tr t Rise Time Fall Time Dn Pork 1 0 1 5 3 0 ns ti Serial Output Jitter 270 Mbps See Figure 3 220 PSp p tit Serial Output Jitter See 4 ae 100 200 PSp p SDO SDO tr Rise Time Fall Time 20 80 2 4 500 800 1500 ps Output Overshoot See 4 1 tLock Lock Time See 215 75 us tsu Setup Time See 4 and Figure 4 Dy to Pork 4 2 ns tut Hold Time See and Figure 4 Dy from Perk 4 2 ns Leen Output duetan See Epa sae 6 nH Raen Output Resistance See 4 25k Q 1 Typical values are stated for Vpp 5 0V CLC021AVGZ 5 0 or 3 3V CLC021AVGZ 3 3 and Ta 25 C 2 Ry 750 AC coupled 270 Mbps Rrer 1 69 KQ 1 See TEST LOADS and Figure 3 3 CLC021 mounted in the SD021EVK board configured in BIST mode NTSC colour bars with Perk 27 MHz derived from Tektronix TG2000 black burst reference Timing jitter measured with Tektronix VM700T using jitter measurement FFT mode frame rate
22. ications related information or support that may be provided by TI Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures monitor failures and their consequences lessen the likelihood of failures that might cause harm and take appropriate remedial actions Buyer will fully indemnify Tl and its representatives against any damages arising out of the use of any TI components in safety critical applications In some cases TI components may be promoted specifically to facilitate safety related applications With such components TI s goal is to help enable customers to design and create their own end product solutions that meet applicable functional safety standards and requirements Nonetheless such components are subject to these terms No Tl components are authorized for use in FDA Class III or similar life critical medical equipment unless authorized officers of the parties have executed a special agreement specifically governing such use Only those TI components which TI has specifically designated as military grade or enhanced plastic are designed and intended for use in military aerospace applications or environments Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer s risk and that Buyer is solely responsible for compliance with all legal and regulator
23. input to video D to A conversion devices unless measures are taken to restrict the production of out of band frequency components The TPG is operated by applying the code for the desired test pattern to DO through D3 D4 through D9 are 00h Since all parallel data inputs are equipped with internal pull down devices only those inputs DO through D3 which require a logic 1 need be pulled high Next apply a 27 MHz or 36 MHz signal appropriate to the raster size desired at the Po input and wait until the Lock_Detect output goes true indicating the VCO is locked on frequency Then take TPG_Enable pin 29 to a logic high The serial test pattern data appears on the SDO outputs The Lock_Detect output may be temporarily connected to TPG_Enable to automate TPG operation The TPG mode is exited by taking TPG_Enable to a logic low Table 1 gives device pin functions for this mode Table 2 gives the available test patterns and selection codes 12 Submit Documentation Feedback Copyright 2000 2013 Texas Instruments Incorporated Product Folder Links CLC021 14 Ti INS FRUMENES CLC021 www ti com SNLS068H MAY 2000 REVISED APRIL 2013 ry TA rr Pclk Ww ww w Lock Detect D 3 0 y X S e Table 3 Data stable TPG Enable Control stable m a a a eaa E E e E e a a yaaran mes E MMU MM Vww SDO SDO I 1 x XX 1 1 X X AA A er a NANANA m o o ee eee eee ee eee ee eee eee e e e Y tw laa td ws ty Figure 8 Test Pattern Generator Control Sequence Tabl
24. ions are made for each video field prior to serialization Separate CRCs for the full field and active picture along with status flags are inserted and serially transmitted with the other data Upon being reset the initial state of all EDH check characters is 00h The EDH control system accepts input from the sync detector and controls the EDH polynomial generator and SMPTE EDH polynomial insertion multiplexer EDH Enable an external TTL compatible low true input enables this circuitry The controller inserts the EDH check words in the serial data stream at the correct positions in the ancilliary data space per SMPTE 259M paragraph 7 3 8 4 4 or 9 4 4 and per SMPTE RP 165 Ancilliary data space is formatted per SMPTE 291M The EDH Force control input causes the insertion of new EDH checkwords and flags into the serial output regardless of the previous condition of EDH checkwords and flags in the input parallel data This function may be used in situations where video content has been editted thus making the previous EDH information invalid The NTSC PAL output indicates the type of component or composite data standard being input to the CLC021 This output is useful for troubleshooting or may be used to drive a panel indicator The output is high when 625 line PAL data is being input and low when 525 line NTSC data is being input PHASE LOCKED LOOP AND VCO The phase locked loop PLL system generates the output serial data clock at 10x the parall
25. locked on frequency TPG_Enable pin 29 is taken to a logic high The Lock_Detect output may be temporarily connected to TPG_Enable to automate BIST operation Test_Output pin 3 is monitored for a pass fail indication If no errors have been detected this output will go to a logic high level approximately 2 field intervals after TPG_Enable is taken high If errors have been detected in the internal circuitry of the CLC021 Test_Output will remain low until the test is terminated The BIST is terminated by taking TPG _Enable to a logic low Continuous serial data output is available during the test rr re Polk AS mA r 1N UN Ty w ts p Lock Detect pake eres NTSC 03h Data stable PAL 05h AAA ae ww wv W v Ww y y SDO 5D0 n A na D n A n Figure 7 Built In Self Test Control Sequence TEST PATTERN GENERATOR The CLC021 includes an on board test pattern generator TPG Four full field component video test patterns for both NTSC and PAL standards and 4x3 and 16x9 raster sizes are produced The test patterns are flat field black PLL pathological equalizer EQ pathological and a modified 75 8 colour vertical bar pattern The pathologicals follow recommendations contained in SMPTE RP 178 1996 regarding the test data used The colour bar pattern does not incorporate bandwidth limiting coding in the chroma and luma data when transitioning between the bars For this reason it may not be suitable for use as a visual test pattern or for
26. nt Line Field ID Composite 26 Lock Detect Lock Detector Output High True 27 Vsso Negative Power Supply Input PLL Supply 28 Vopo Positive Power Supply Input PLL Supply 29 TPG Enable TPG Enable High True 30 Vssop Negative Power Supply Input PLL Digital Supply 31 Vssop Negative Power Supply Input PLL Digital Supply 32 Vppop Positive Power Supply Input PLL Digital Supply 33 Vppop Positive Power Supply Input PLL Digital Supply 34 N C No Connect 35 Rrer Output Level Reference Resistor 1 69 kQ 1 Nominal Value 36 Vppop Positive Power Supply Input PLL Digital Supply 37 Vsssp Negative Power Supply Input Output Driver 38 SDO Serial Data True Output 39 SDO Serial Data Complement Output 40 Vppsp Positive Power Supply Input Output Driver 41 Sync Detect Enable Parallel Data Sync Detection Enable Input Low True 42 NSP New Sync Position Output 43 ANC Ancilliary Data Header Flag Output 44 NTSC PAL NTSC PAL Mode Indicator Output PAL High NTSC Low 1 All CMOS TTL inputs have internal pull down devices 14 Submit Documentation Feedback Copyright O 2000 2013 Texas Instruments Incorporated Product Folder Links CLC021 14 Ti INS FRUMENES CLC021 www ti com SNLS068H MAY 2000 REVISED APRIL 2013 APPLICATION INFORMATION A typical application circuit for the CLC021 is shown in Figure 9 This circuit demonstrates the capabilities of the CLC021 and allows its evaluation in a variety of configurations Assembled demonstra
27. on Pb Free ROHS Pb Free RoHS Exempt or Green RoHS amp no Sb Br please check http www ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 1 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free ROHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free ROHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 1 by weight in homogeneous material 6 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature There may be additional marking which relates to the logo the lot trace code information or the environmental category on the device 6 Multiple Device Markings will be inside parentheses Only
28. one Device Marking contained in parentheses and separated by a will appear on a device If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device 6 Lead Ball Finish Orderable Devices may have multiple material finish options Finish options are separated by a vertical ruled line Lead Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties TI has taken and Addendum Page 1 H A PACKAGE OPTION ADDENDUM IA TEXAS INSTRUMENTS 12 Oct 2014 www ti com continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on
29. ortion The planes should be pulled back from all transmission lines and component mounting pads a distance equal to the width of the widest transmission line or the thickness of the dielectric separating the transmission line from the internal power or ground plane s whichever is greater Doing so minimizes effects on transmission line impedances and reduces unwanted parasitic capacitances at component mounting pads In especially noisy power supply environments such as is often the case when using switching power supplies separate filtering may be used at the CLC021 s VCO and output driver power pins The CLCO21 was designed for this situation The digital section VCO and output driver power supply feeds are independent see and CONNECTION DIAGRAM for details Supply filtering may take the form of L section or pi section L C filters in series with these Vpp inputs Such filters are available in a single package from several manufacturers Despite being independent feeds all device power supplies should be applied simultaneously as from a common source The CLC021 is free from power supply latch up caused by circuit induced delays between the device s three separate power feed systems 20 Submit Documentation Feedback Copyright 2000 2013 Texas Instruments Incorporated Product Folder Links CLC021 14 Ti Inc RUMENTS CLC021 www ti com SNLS068H MAY 2000 REVISED APRIL 2013 REVISION HISTORY Changes from Revision G April 2013 to R
30. ow into device pins is defined as positive Current flow out of device pins is defined as negative All voltages are stated referenced to Vss OV 2 Typical values are stated for Vpp 5 0V CLC021AVGZ 5 0 or 3 3V CLC021AVGZ 3 3 and Ta 25 C DC ELECTRICAL CHARACTERISTICS CLC021 AVGZ 3 3 Over Supply Voltage and Operating Temperature ranges unless otherwise specified 12 Symbol Parameter Conditions Reference Min Typ Max Units Vin Input Voltage High Level 2 0 Vop V V Input Voltage Low Level V 0 6 V i p a All CMOS Inputs SS lin Input Current High Level Vin Vpop 22 60 yA lit Input Current Low Level Vit Vss 1 20 uA VoH CMOS Output Voltage High lop 8 mA 24 3 0 V V Level DD All CMOS Outputs VoL CMOS Output Voltage Low lo 8 mA 0 0 0 3 Vos 0 5V V Level Vspo Serial Driver Output Voltage Ri 750 1 Rrer 1 69 KQ 1 SDO SDO 720 800 880 mVp p See Figure 3 lbo Power Supply Current Total RL 750 1 Rrer 1 69 KQ 1 Perk 27 MHz NTSC 33 55 mA Colour Bar Pattern See Figure 3 1 Current flow into device pins is defined as positive Current flow out of device pins is defined as negative All voltages are stated referenced to Vss OV 2 Typical values are stated for Vpp 5 0V CLC021AVGZ 5 0 or 3 3V CLC021AVGZ 3 3 and Ta 25 C Copyright 2000 2013 Texas Instruments Incorporated Submit Documentation Feedback 5 Product
31. ragraph 8 1 1 or composite PAL per paragraph 9 1 1 Eight bit video data corresponds to the upper 8 bits of the 10 bit video data word and is MSB aligned Output from this register feeds the TRS sync character detector SMPTE polynomial generator serializer and the EDH polynomial generators serializers and control system All parallel data and clock inputs have internal pull down devices The syne detector or TRS character detector receives data from the input register The detection function is controlled by Sync Detect Enable a low true TTL compatible external signal Synchronization words the timing reference signals TRS start of active video SAV and end of active video EAV are defined in SMPTE 125M and 244M The sync detector supplies control signals to the SMPTE polynomial generator to identify the presence of valid video data and to the EDH control block In SMPTE mode TRS character LSB clipping as prescribed in ITU R BT 601 is enabled LSB clipping causes all TRS characters with a value between 000h and 003h to be forced to 000h and all TRS characters with a value between 3FCh and 3FFh to be forced to 3FFh Clipping is done prior to encoding or EDH character generation This function is disabled in non SMPTE mode operation Outputs from the sync detector are 1 H V and F or Line Field ID For component video these are registered outputs corresponding to input TRS data bits 6 7 and 8 respectively These outputs are disabled in
32. re back matching resistors No series back matching resistors should be used Output level is controlled by the value of Reef connected to pin 35 The value of Rrer is normally 1 69 kQ 1 The output buffer is static when the device is in an out of lock condition Separate Vsssp and Vopsp power feeds pins 37 and 40 are provided for the serial output driver 10 Submit Documentation Feedback Copyright O 2000 2013 Texas Instruments Incorporated Product Folder Links CLC021 14 Ti INS FRUMENES CLC021 www ti com SNLS068H MAY 2000 REVISED APRIL 2013 POWER ON RESET AND RESET INPUT The CLCO21 has an internally controlled automatic power on reset circuit Reset clears TRS detection circuitry all latches registers counters and polynomial generators sets the EDH characters to 00h and disables the serial output The SDO outputs are tri stated during power on reset The part will remain in the reset condition until the parallel input clock is applied An active HIGH true manual reset input is available at pin 1 It resets both the digital and PLL blocks The reset input has an internal pull down device and is inactive when unconnected It is recommended that Pex not be asserted until at least 30 us after power has reached Vppmin See Figure 5 If manual reset is used during power on then Pc k may be asserted at any time as long as manual reset is not de asserted until Vppmin is reached See Figure 6 Vopmin Voo Vss 30us min A P
33. rement Set Figure 11 Jitter Test Circuit Tektronix VM700T Copyright 2000 2013 Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links CLC021 CLC021 A cies SNLS068H MAY 2000 REVISED APRIL 2013 www ti com 5V 10uF 5V GND Input trom To SD021EVK Tektronix P1_Pelk pin TG2000 BG1 p module clock To SD021EVK output P1 Pclk Gnd pin All resistances in Ohms Ground all unused inputs Figure 12 ECL to TTL CMOS Level Converter Amplifer 18 Submit Documentation Feedback Copyright 2000 2013 Texas Instruments Incorporated Product Folder Links CLC021 14 Ti INS FRUMENES CLC021 www ti com SNLS068H MAY 2000 REVISED APRIL 2013 UM B8T Video Measurement Set Channel A System Default S SDI Jitter i 270Mb 525 line Auto detect 5008 F1 L17 20 8 46 6 66 8 86 6 190 8 128 0 Microseconds 2 8 4 6 6 8 8 4 18 Frequency MHz FFT Window Hanning Timing p p 2093 ps 1 kHz filter Alignment p p 126 ps Figure 13 Jitter Plots PCB LAYOUT AND POWER SYSTEM BYPASS RECOMMENDATIONS Circuit board layout and stack up for the CLC021 should be designed to provide noise free power to the device Good layout practice also will separate high frequency or high level inputs and outputs to minimize unwanted stray noise pickup feedback and interference Power system performance may be greatly improved by using thin dielectrics 4 to 10 mils for power ground sandwiches This increases
34. t right copyright mask work right or other intellectual property right relating to any combination machine or process in which TI components or services are used Information published by Tl regarding third party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of significant portions of Tl information in Tl data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices TI is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated Tl component or service and is an unfair and deceptive business practice Tl is not responsible or liable for any such statements Buyer acknowledges and agrees that it is solely responsible for compliance with all legal regulatory and safety related requirements concerning its products and any use of TI components in its applications notwithstanding any appl
35. the CLCO21 include parallel to serial data conversion ITU R BT 601 4 input data clipping data encoding using the SMPTE polynomial X X 1 data format conversion from NRZ to NRZI parallel data clock frequency multiplication and encoding with the serial data and differential serial output data driving The CLC021 has circuitry for automatic EDH character and flag generation and insertion per SMPTE RP 165 The CLCO21 has an exclusive built in self test BIST and video test pattern generator TPG with 16 component video test patterns reference black PLL and EQ pathologicals and modified colour bars in 4 3 and 16 9 raster formats for NTSC and PAL formats The CLC021 has inputs for enabling sync detection non SMPTE mode operation enabling the EDH function NRZ NRZI mode control and an external reset control Outputs are provided for H V and F bits new TRS sync character position indication ancilliary data header detection NTSC PAL raster indication and PLL lock detect Separate power pins for the output driver VCO and the serializer improve power supply rejection output jitter and noise performance The CLC021AVGZ 5 0V is powered by a single 5V supply The CLCO21AVGZ 3 3V is powered by a single 3 3V supply Power dissipation is typically 235 mW including two 750 back matched output loads The device is packaged in a JEDEC metric 44 lead PQFP BLOCK DIAGRAM SYNC DET ENAB RESET BUILT IN SELF TEST Us Jae amp TEST PATTERN GE
36. the intrinsic capacitance of the PCB power system which improves power supply filtering especially at high frequencies and makes the value and placement of external bypass capacitors less critical External bypass capacitors should include both RF ceramic and tantalum electrolytic types RF capacitors may use values in the range 0 01 uF to 0 1 uF Tantalum capacitors may be in the range 2 2 uF to 10 uF Voltage rating for tantalum capacitors should be at least 5X the power supply voltage being used It is recommended practice to use two vias at each power pin of the CLC021 as well as all RF bypass capacitor terminals Dual vias reduce the interconnect inductance by up to half thereby reducing interconnect inductance and extending the effective frequency range of the bypass components Copyright 2000 2013 Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links CLC021 I TEXAS CLC021 INSTRUMENTS SNLS068H MAY 2000 REVISED APRIL 2013 www ti com The outer layers of the PCB may be flooded with additional Vss ground plane These planes will improve shielding and isolation as well as increase the intrinsic capacitance of the power supply plane system Naturally to be effective these planes must be tied to the Vss power supply plane at frequent intervals with vias Frequent via placement also improves signal integrity on signal transmission lines by providing short paths for image currents which reduces signal dist
37. tion boards with more comprehensive evaluation options are available part number SD021 5EVK 5V device or SD021 3EVK 3 3V device The boards may be ordered through any of Texas Instruments sales offices Complete circuit board layouts and schematics including Gerber photoplot files for the demonstration boards are available on Texas Instruments website in the application information for this device APPLICATION CIRCUIT PARALLEL DATA 1kQ amp CONTROL INPUTS DO 12100 Lock per 28 5 B i a NA LOCK DET D1 D1 TEST OUT HLMP 14 23 4700 D2 D2 H LFbO 15 24 D3 D3 V LFb1 16 25 FLAG AND D4 D4 F LFb2 INDICATOR 17 44 OUTPUTS SERIAL D5 e D5 PAL NTSC DEG D6 D6 0 1uF OUTPUTS 19 42 D7 D7 O SD D8 2 D8 apo Le D9 D9 0 1 uF 22 35 Pork Pork O SDO 8 EDH FORCE gt E 1 69kQ 759 759 EDH ENAB 33 36 1 1 1 ee SMPTE MODE ee SYNC DET ENAB 27 37 NRZ NRZI 30 31 RESET laz 4 7uF 0 1uF O TPG ENAB CLC021AVGZ Figure 9 Typical Application Circuit The SD021EVK application circuit boards Figure 10 can accommodate different input and output drive and loading options Pin headers are provided for input and control I O signal access Install the appropriate value resistor packs 2200 at RP1 and RP3 and 3300 at RP2 and RP4 for TTL cabled interfaces before applying input signals Install 510 resistor packs at RP2 and RP4 for signal sources requiring such loading Remove any resistor packs
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