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CIC751 User´s Manual

1. Table 8 2 MLI Kernel Registers cont d Register Register Long Name Address Description Short Name see MLI TP1BAR Transmitter Pipe 1 Base Address 0000 0258 Page 4 73 Register MLI TP2BAR Transmitter Pipe 2 Base Address 0000 025C 4 73 Register Transmitter Pipe Base Address 0000 0260 4 73 Register MLI_TCBAR Transmitter Copy Base Address 0000 0264 Page 4 74 Register MLI RCR Receiver Control Register 0000 0268 Page 4 75 MLI RPOBAR Receiver Pipe 0 Base Address 0000 026C Page 4 78 Register MLI RP1BAR Receiver Pipe 1 Base Address 0000 0270 Page 4 78 Register MLI RP2BAR Receiver Pipe 2 Base Address 0000 0274 Page 4 78 Register MLI RP3BAR Receiver Pipe 3 Base Address 0000 0278 Page 4 78 Register MLI RPOSTATR Receiver Pipe 0 Status Register 0000 027C Page 4 79 MLI RP1STATR Receiver Pipe 1 Status Register 0000 0280 Page 4 79 MLI RP2STATR Receiver Pipe 2 Status Register 0000 0284 Page 4 79 MLI RP3STATR Receiver Pipe Status Register 0000 0288 Page 4 79 MLI RADRR Receiver Address Register 0000 028C Page 4 81 MLI RDATAR Receiver Data Register 0000 0290 Page 4 82 MLI SCR Set Clear Register 0000 0294 Page 4 51 MLI TIER Transmitter Interrupt Enable 0000 0298 Page 4 83 Register MLI TISR Transmitter Interrupt Status 0000 029C Page 4 85 Register MLI TINPR Transmit
2. 0 DRAIP 0 0 0 CFRIP 0 NFRIP r rw r rw r rw r rw Field Bits Type Description NFRIP 2 0 rw Normal Frame Received Interrupt Pointer This bit field determines which MLI Request x becomes active when a Normal Frame received interrupt occurs 000 MLI Request 0 is selected 001 MLI Request 1 is selected 010 MLI Request 2 is selected 011 MLI Request 3 is selected 100 Reserved do not use 101 Reserved do not use 110 Reserved do not use 111 Reserved do not use CFRIP 6 4 rw Command Frame Received Interrupt Pointer This bit field determines which MLI Request x becomes active when a Command Frame received interrupt occurs Coding see NFRIP DRAIP 14 12 rw Discarded Read Answer Interrupt Pointer This bit field determines which MLI Request x becomes active when a discarded read answer interrupt occurs Coding see NFRIP Reserved Should be written with 0 0 10 8 User Manual 4 92 V 1 0 2005 11 MLI V1 0 Cinfineon CIC751 Micro Link Interface MLI Field Bits Type Description 0 3 7 11 r Reserved 31 15 Read as 0 should be written with O User Manual 4 93 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI 4 4 MLI Address Map MLI module supports four Small Transfer Windows STW one for each Pipe and four Large Transfer Windows LTW one for each Pi
3. Unit Address Range Reserved 0000 0000 0000 01FF Micro Link Interface MLI 0000 0200 0000 02FF Reserved 0000 0300 0000 Direct Memory Access Controller DMA 0000 0400 0000 O5FF Reserved 0000 0600 0000 07FF System Control Unit SCU 0000 0800 0000 O8FF Synchronous Serial Interface SSC 0000 0900 0000 O9FF Ports 0000 0A00 0000 OAFF Reserved 0000 0B00 0000 OFFF User Manual 8 1 V 1 0 2005 11 Regs V1 0 Cinfineon CIC751 Table 8 1 Block Address Map CIC751 cont d Register Overview Unit Address Range Analog to Digital Converter ADC 0000 1000 0000 11 Reserved 0000 1200 0000 7FFF MLI Small Transfer Windows Pipe 0 0000 8000 0000 9FFF Pipe 1 0000 A000 0000 BFFF Pipe 2 0000 C000 0000 DFFF Pipe 3 0000 E000 0000 FFFF MLI Large Transfer Windows Pipe 0 0001 0000 0001 FFFF Pipe 1 0002 0000 0002 FFFF Pipe 2 0003 0000 0003 FFFF Pipe 3 0004 0000 0004 FFFF Reserved 0005 0000 FFFF FFFF 8 1 1 The following rules apply for all accesses Access Rules User Manual 8 2 Regs V1 0 V 1 0 2005 11 Cinfineon Register Overview All registers read and write conditions can be found in the different module chapters Accesses to reserved marked addresses are forbidd
4. 4 17 Functional Description 4 19 Frame Handling 4 19 Copy Base Address Frame 4 19 Data 2 22 need bee dE 4 22 Read Frames isco cence SU Sees cree EE US Ac iof op dos 4 26 Answer Frame 4 29 Command 4 30 General MLI Features 4 34 Parity Generation and Checking 4 34 L 2 V 1 0 2005 11 Cinfineon eel 4 2 2 2 4 2 2 3 4 2 2 4 4 2 2 5 4 2 3 4 2 4 4 2 5 4 2 5 1 4 2 5 2 4 2 5 3 4 2 6 4 2 6 1 4 2 6 2 4 2 6 3 4 2 6 4 4 2 6 5 4 2 7 4 3 4 3 1 4 3 1 1 4 3 1 2 4 3 1 3 4 3 1 4 4 3 2 4 3 2 1 4 3 2 2 4 3 2 3 4 3 2 4 4 3 2 5 4 3 2 6 4 3 2 7 4 3 2 8 4 3 2 9 4 3 2 10 4 3 3 4 3 3 1 4 3 3 2 4 3 3 3 4 3 3 4 4 3 3 5 4 3 4 4 3 4 1 4 3 4 2 User Manual Table Of Contents Non Acknowledge 4 37 Address 4 38 Automatic Data Mode 4 39 Transmit 4 39 MLI Interface 4 40 MLI Request Generation 4 41 Transmitter Interrup
5. 498 n 20 Reset Value 0000 0000 31 0 SHADR r Field Bits Description SHADR 31 0 rh Shadowed Address This bit field holds the shadowed 32 bit source or destination address of DMA channel On SHADROn is written when source or destination address buffering is selected ADRCROn SHCT 01 or ADRCROn SHCT 10g and a transaction is running While the shadow mechanism is disabled SHADR is set to 0000 0000 The value stored the SHADR is automatically set to 0000 0000 when the shadow transfer takes place The user can read the shadow register in order to detect if the shadow transfer has already taken place If the value in SHADR is 0000 0000 no shadow transfer can take place and the corresponding address register is modified according to the circular buffer rules User Manual 3 49 V 1 0 2005 11 DMA V1 0 Cinfineon Micro Link Interface MLI 4 Micro Link Interface MLI This chapter describes the Micro Link Interface MLI module and the MLI protocol 4 1 MLI Protocol This section describes the MLI protocol and its general usage and defines the terms specific to the MLI 4 1 1 Overview The Micro Link Interface MLI is a fast synchronous serial interface that makes it possible to exchange data between microcontrollers or other devices Figure 4 1 shows how two microcontrollers are typically connected via their MLI interfaces In this example the MLI modules
6. 6 6 Fixed Channel Conversion Modes 6 6 Auto Scan Conversion Modes 6 6 Wait for Read 6 7 Channel Injection Mode 6 8 Arbitration of Conversions 6 10 Automatic 6 11 Multiplexer Test Mode 6 11 Conversion Timing Control 6 12 A D Converter Interrupt Operation 6 15 Interrupt Event Handling 6 15 Trigger DMA Action 6 15 User Manual L 4 V 1 0 2005 11 Cinfineon Table Of Contents 6 6 1 2 Forward to an SRn Pin 6 15 6 7 ADC Buffer Registers 6 16 6 7 1 Overview rm 6 16 6 7 2 Extended Result Registers 6 17 6 7 3 Doorbell Mechanism 6 17 6 7 3 1 Trigger DMA Transfer 6 17 6 7 3 2 Slimulate SRM PINS se ss ss aias die ee eee siw as 6 18 6 8 pedro PT 6 19 6 8 1 ADC Control Registers for Compatibility Mode 6 21 6 8 2 ADC Control Registers for Enhanced Mode 6 24 6 8 3 ADC Result Registers
7. 6 27 6 8 4 ADC Extended Result Registers 6 29 6 8 5 ADC Doorbell Register 6 35 7 Parallel OR EE EE RE REB 7 1 7 1 POW CCCII 7 2 7 1 1 Block Diagram 7 2 7 1 2 IMP t STAJE cO 7 2 7 1 3 Fort O ROUMO s sa aman puasa a area A A 7 3 7 1 4 Port 0 Register Description 7 5 7 1 4 1 Port 0 Control Register 7 5 7 2 Polls a ea E Q 7 13 7 2 1 Block Diagram 7 13 7 2 2 Input Stage 7 13 7 2 3 Port 1 Routing MT TETTE 7 14 7 2 4 Port 1 Register Description 7 15 7 2 4 1 Port Input 5 7 15 7 3 Ports Register Overview 7 15 8 Register Overview 8 1 8 1 Address Map of CIC751 8 1 8 1 1 Access RU eS NEP 8 2 8 2 Registers Tables 8 4 8 3 Memory Registers 8 15 User Manual L 5 V 1 0 2005 11 Cinfineon Table Of Contents User Manual L 6 V 1 0 2005 11 Cinfineon Introduct
8. 31 30 29 28 27 26 25 24 23 22 21 20 9 18 17 16 PR PR PR PR PR PR PR PR PR PR PR PR 12 11 10 9 8 7 6 5 4 3 2 1 0 r w w w w w w w w w w w w w 15 14 13 12 11 10 1 0 PS PS PS PS PS PS PS PS PS PS PS PS PS 12 11 10 9 8 7 6 5 4 3 2 1 0 r w w w w w w Field Bits Type Description PSx x w Port Set Bit x x 0 12 Setting this bit sets or toggles the corresponding bit in the port output register PO_OUT see Table 7 2 On a read access this bit returns 0 PCx x 16 w Port Clear Bit x x 0 12 Setting this bit clears or toggles the corresponding bit in the port output register PO_OUT see Table 7 2 On a read access this bit returns 0 0 15 13 r Reserved 31 29 Read as 0 should be written with 0 Function of the PCx and PSx Bit fields Table 7 2 Function of the Bits and PSx PCx PSx Function 0 or no write access 0 or no write access Bit PO OUT Px is not changed 0 or no write access 1 Bit PO OUT Px is set 1 0 or no write access Bit PO OUT Px is cleared 1 1 Bit PO OUT Px is toggled Note If a bit position is not written one out of two bytes not targeted by a byte write the corresponding value is considered as 0 Toggling a bit requires one 16 bit write User Manual Parallel Ports V1 0 7 7 V 1 0 2005 11 Cinfineon Parallel Ports P0_IOCR0 Port 0 Input Output Control 0 Register 10 Reset Value Table 7
9. ADC_CON ADC Control Register 010 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AD AD AD AD AD ADCTC ADSTC WR BSY ST 0 ADM ADCH rw rw wh rw rw rh rwh r rw rw Field Bits Type Description ADCH 3 0 ADC Analog Channel Input Selection Selects the first ADC channel which is to be converted User Manual 6 21 V 1 0 2005 11 ADC V1 0 Cinfineon CIC751 The Analog Digital Converter Field Bits Type Description ADM 5 4 ADC Mode Selection 00 Fixed Channel Single Conversion 01 Fixed Channel Continuous Conversion 10 A Auto Scan Single Conversion 11 Auto Scan Continuous Conversion ADST 7 rwh ADC Start Bit 0 Stop a running conversion 1 Start conversion s ADBSY 8 rh ADC Busy Flag 0 ADC is idle 1 A conversion is active ADWR 9 rw ADC Wait for Read Control 0 Wait for Read Mode is deactivated 1 Wait for Read Mode is activated ADCIN 10 rw ADC Channel Injection Enable 0 Channel Injection is disabled 1 Channel Injection is enabled ADCRQ 11 rwh ADC Channel Injection Request Flag 0 No Channel Injection request is pending 1 A Channel Injection request is pending This bit is automatically cleared if a Channel Injection conversion is started ADSTC 13 12 rw ADC Sample Time Control Defines the ADC sample time in a certain range 00 tp x8 01 tao x16 10 tag X 32 11 tpg x 64 ADCTC 15 14 ADC Conversion Time Control Defines
10. Figure 4 14 MLI Communication without Error Transmitter View A transmission can be started by an MLI transmitter when the MLI receiver is ready to receive frames which is indicated by TREADY 1 When the MLI transmitter detects TREADY 1 and starts its transmission TVALID is asserted and is held as long as frame data is sent out When the MLI receiver has detected the falling edge of the RVALID signal it will de assert RREADY transmission start acknowledged by receiver At the end of the frame transmission the MLI transmitter de asserts the TVALID signal and checks if the TREADY signal is also de asserted This check is used as the life sign of the receiver and the MLI transmitter can detect whether the receiver is able to react in time to the transmitter actions 4 1 6 1 Ready Delay Time In order to support significant propagation delays the signal TREADY is evaluated with respect to TVALID and TCLK in a time interval called Ready Delay Time see Figure 4 14 When a transmission is finished RVALID becomes 0 the MLI receiver checks the received frame for correct reception parity error In the case of correct reception it asserts RREADY to indicate the correct reception with the next falling edge of RCLK The MLI transmitter checks TREADY with respect to TVALID becoming 0 by counting TCLK periods with a ready delay counter The ready delay counter is started from 0 at the end of a frame transmission TVALID become
11. 5 1 QU UR A ay ruwana 5 1 General Operation 5 2 SPI Communication Basics 5 3 Full Duplex Operation 5 3 Half Duplex Operation 5 6 Operating the SSC 5 8 SSC Transaction Header 5 8 SSC Data Flow Model 5 9 Operating Mode Selection 5 13 Error Detection Mechanisms 5 14 Register Descriptions 5 15 Port Control 5 23 Connecting 2 more CIC751 SSC Slaves to 1 Host 5 23 The Analog Digital Converter 6 1 Mode Selection 6 3 Compatibility Mode 6 3 Enhaneed Mode cu coo bep E uio eor MC 6 3 Operation i Rl ea E QE E ESTA 6 4 Channel Selection 6 4 ADG Stat s Flags vee EE E EE UR 6 4 ADC Start Stop Control 6 4 Conversion Mode Selection 6 5 Conversion Resolution Control 6 6 Conversion Result
12. RB VALUE 0 31 16 r Reserved Read as 0 should be written with 0 SSC_BR SSC Baud Rate Timer Reload Register 14 Reset Value 0000 0063 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BR_VALUE User Manual 5 22 V 1 0 2005 11 SSC 1 0 Cinfineon Synchronous Serial Interface SSC Field Bits Type Description BR_VALUE 15 0 rw Baud Rate Timer Reload Value This bit field has to be set to FFFF by the set up software to ensure a error free communication The reset value is set in way that a communication with a bandwidth greater than 400 KBit s is possible Reserved Read as 0 should be written with O 0 81 16 A 5 4 Port Control If the SSC was selected as the communication interface pin MODE was latched after PORST with 1 for the CIC751 the port control registers of port 0 are automatically configured in a way that a communication via SPI is possible Port 0 control registers PO IOCRO PO PO 8 IOCHR12 are initialized with the following values IOCRO A0202020 4 0020A020 8 20202020 IOCR12 00000020 Port pins that can be used for either SSC MLI communication are automatically configured in way that the MLI part is inactive and does not generate any action that can cause any harm to an SSC communication Using the open drain output feature of port lines
13. cusnontcount XXe CHCROn TREL tc1 tc2 tc3 1 SADROn SHADROn with sa2 0000 0000 CHCROn SHCT 01 tcl transfer count 1 1 3 writing to CHCROn and SADROn 2 transfer count 2 2 start of new DMA transaction with sal source address 1 shadow transfer of source address 2 dd 2 source address MCT06153 Figure 3 6 Shadow Source Address and Transfer Count Update Figure 3 6 shows how the contents of the source address register SADR0n and the transfer count CHSR0n TCOUNT are updated during two DMA transactions with a shadowed source address and transfer count update At reference point 2 the DMA transaction 1 is finished and DMA transaction 2 is started At 1 the DMA channel is reprogrammed with two new parameters for the next DMA transaction Transfer count tc2 and source address sa2 Source address sa2 is buffered in SADR0n and transferred to SADR0n when the new DMA transaction is started at 2 At this time transfer count tc2 is also transferred to CHSR0n TCOUNT User Manual 3 14 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller 3 2 4 2 Channel Request Control Figure 3 7 shows the control logic for DMA requests that is implemented for each DMA channel CHCR0n Suspend Request Suspend Control SUSPMR End of Transaction CH0n_
14. 0 WS id RS r rh m rh Field Bits Type Description MEORS 0 rh Move Engine 0 Read Status 0 Move Engine 0 is not performing a read 1 Move Engine 0 is performing a read CHO 3 1 rh Reading Channel in Move Engine 0 This bit field indicates which channel number is currently being processed by the Move Engine 0 MEOWS 4 rh Move Engine 0 Write Status 0 Move Engine 0 is not performing a write 1 Move Engine 0 is performing a write 0 31 8 r Reserved Read as 0 should be written with O User Manual 3 37 V 1 0 2005 11 DMA V1 0 CIC751 Cinfineon The Move Engine 0 Read Register indicates the value that has just been read by Move Engine 0 Direct Memory Access Controller DMA_MEOR DMA Move Engine 0 Read Register 434 Reset Value 0000 0000 31 24 23 1615 8 7 0 RDO3 RD02 RDO1 RDOO rh l l rh l l rh l l rh l Field Bits Type Description RD00 7 0 rh Read Value for Move Engine 0 RD01 15 8 Contains the 32 bit read data four bytes RDO 3 0 RD02 23 16 that is stored in the Move Engine 0 after each read RD03 31 24 move The content of ME0R is overwritten after each read move of a DMA channel belonging to DMA Sub block 0 User Manual 3 38 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller 3 3 3 Channel Control Status Registers The Channel Control Register for DMA channel 0n contains its configuration and its control bits and b
15. 1 751 The Analog Digital Converter Field Bits Type Description ADCRQ 11 rwh ADC Channel Injection Request Flag 0 No Channel Injection request is pending 1 A Channel Injection request is pending This bit is automatically cleared if a Channel Injection conversion is started ADCTS 13 12 rw Channel Injection Trigger Input Select 00 Channel injection trigger input disabled 01 Trigger input CAPCOM2 selected 10 Trigger input CAPCOM6 selected 11 Reserved Note Reset value of bit field ADCTS is 01g for compatibility purposes SAMPLE 14 rh Sample Phase Status Flag 0 A D Converter is not in sample phase 1 A D Converter in sample phase MD 15 rw Mode Control 0 Compatibility Mode 1 Enhanced Mode Note Any modification of control bit MD is forbidden while a conversion is currently running User software must take care ADC_CTR2 ADC Control 2 Register 020 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RES ADCTC ADSTC r rw rw rw Field Bits Type Description ADSTC 5 0 rw ADC Sample Time Control Defines the ADC sample time 15 X 4 x lt ADSTC gt 1 ADCTC 11 6 ADC Conversion Time Control Defines the ADC basic conversion clock User Manual 6 25 V 1 0 2005 11 ADC V1 0 Cinfineon The Analog Digital Converter Field Bits Type Description RES 13 12 rw Conve
16. 3 1 3 1 DMA Request Generation and Control 3 1 3 1 1 Request 3 1 3 1 1 1 Preselection of the Indirect Requests 3 2 3 1 2 DMA Request Assignment Matrix 3 4 3 2 DMA Controller Kernel Description 3 8 3 2 1 dinie ute ET 3 9 3 2 2 Definition of 5 3 10 User Manual L 1 V 1 0 2005 11 Cinfineon 3 2 3 3 2 4 3 2 4 1 3 2 4 2 3 2 4 3 3 2 4 4 3 2 4 5 3 2 4 6 3 2 5 3 3 3 3 1 3 3 2 3 3 3 3 3 4 4 4 1 4 1 1 4 1 2 4 1 3 4 1 4 4 1 4 1 4 1 4 2 4 1 4 3 4 1 4 4 4 1 4 5 4 1 4 6 4 1 4 7 4 1 5 4 1 6 4 1 6 1 4 1 6 2 4 1 7 4 1 8 4 2 4 2 1 4 2 1 1 4 2 1 2 4 2 1 3 4 2 1 4 4 2 1 5 4 2 2 4 2 2 1 User Manual Table Of Contents DMA Principles ated B 3 11 DMA Channel Functionality 3 12 Shadowed Source or Destination Address 3 12 DMA Channel Request Control 3 15 DMA Channel Operation Modes 3 16 Channel Reset Operation 3 20 Transfer Count and Move Count 3 22 Circular Buffer 3 24 Transaction Control Engine 3 25 DMA Mo
17. Note Note that the entire range between two f columns in the above table is allowed Note For divider factors that cause duty cycles far from 5096 not only the cycle time has to be checked but also the minimum clock pulse width Oscillator Run Detection Oscillator Run Detection monitors the incoming clock from the oscillator and determines whether it is suitable for an operation in Normal Mode with the selected setting for the N Divider Only incoming frequencies that are too low to enable a stable operation of the VCO circuit are detected User Manual 2 9 V 1 0 2005 11 STCU V 1 0 Cinfineon System and Control Unit SCU PLL Configuration and Status Registers The PLL Configuration and Status Registers hold the hardware configuration bits of the PLL and provide the control for the N P and K Dividers as well as the PLL status information The clock generation path is selected via the PLL control register SCU_PLLCON 2 3 23 Clock Control Unit The Clock Control Unit CCU receives the clock that is created by the PLL fpu In Normal Mode the PLL output frequency is always used directly as the system clock 2 4 Power Supply System The power supply system is selected such that it offers maximum flexibility and requires a minimum o pins and system integration cost Features supply for the ADC 5Vor3 3 supply for the I O pads SOI digital module cores Figu
18. 4 85 MLI_TINPR Transmitter Interrupt Node Pointer 00 0 4 86 Register MLI_RIER Receiver Interrupt Enable Register 00A44 Page 4 88 MLI_RISR Receiver Interrupt Status Register 8 4 90 MLI RINPR Receiver Interrupt Node Pointer Register Page 4 92 MLI GINTR Global Interrupt Set Register 00B0 Page 4 53 MLI OICR Output Input Control Register 00B4 Page 4 54 User Manual 4 48 V 1 0 2005 11 MLI V1 0 Cinfineon CIC751 4 3 1 General Registers Micro Link Interface MLI 4 3 1 1 Fractional Divider Register The fractional divider register allows programming of the frequency fy to generate the baud rate of the of the 50 duty cycle transmitter shift clock TCLK MLI FDR MLI Fractional Divider Register 31 30 29 28 27 26 25 20 Reset Value 24 23 22 21 2 19 18 17 16 DIS CLK 0 RESULT rwh r rh 15 14 13 12 11 10 9 Field Bits Type Description STEP 9 0 w Step Value In Normal Divider Mode STEP contains the reload value for RESULT In Fractional Divider Mode this bit field defines the 10 bit value that is added to the RESULT with each input clock cycle DM 15 14 rw Divider Mode 00 01 10 11 This bit field defines the functionality of the fractional divider block Fractional divider is switched off no output clock is generated RESULT is n
19. 5 6 Serial Clock SCLK Phase and Polarity Options User Manual SSC 1 0 5 13 V 1 0 2005 11 Cinfineon Synchronous Serial Interface SSC 5 2 4 Error Detection Mechanisms The SSC is able to detect three different error conditions Receive Error Phase Error and Transmit Error When an error is detected the respective error flag is always set The error flags are not cleared automatically but must be cleared via register SSC_EFM after servicing The error status flags can be set and cleared by software via the error flag modification register SSC_EFM A Receive Error is detected when a new data frame is completely received but the previous data was not read out of the receive buffer register RB This condition sets the error flags STAT RE and SCU_ERRCUM RE The old data in the receive buffer RB will be overwritten with the new value and is unrecoverable lost A Phase Error is detected when the incoming data at pin MTSR Slave Mode sampled with the same frequency as the system clock changes between one cycle before and two cycles after the latching edge of the shift clock signal SCLK This condition sets the error status flags STAT PE and SCU_ERRCUM PE Note When using the setting SSC_ CON PH 1 phase errors can occur due to the fact that the slave select signal change can result in a change of the data signal The slave select signal always changes with the leading clock edge A Transmit Error is detected whe
20. ADC Extended Result 0 View A Register 100 Reset Value 0000 0000 RESA1 ADC Extended Result 1 View A Register 104 Reset Value 0000 1000 ADC RESA2 ADC Extended Result 2 View A Register 108 Reset Value 0000 2000 ADC Extended Result 3 View A Register 10C Reset Value 0000 3000 ADC_RESA4 ADC Extended Result 4 View Register 110 Reset Value 0000 4000 ADC_RESA5 ADC Extended Result 5 View Register 114 Reset Value 0000 5000 ADC_RESA6 ADC Extended Result 6 View A Register 118 Reset Value 0000 6000 ADC_RESA7 ADC Extended Result 7 View A Register 11C Reset Value 0000 7000 ADC_RESA8 ADC Extended Result 8 View A Register 120 Reset Value 0000 8000 ADC RESA9 ADC Extended Result 9 View A Register 124 Reset Value 0000 9000 ADC RESA10 ADC Extended Result 10 View A Register 128 Reset Value 0000 A000 RESA11 ADC Extended Result 11 View A Register 12C Reset Value 0000 B000 ADC RESA12 ADC Extended Result 12 View A Register 130 Reset Value 0000 C000 ADC RESA13 ADC Extended Result 13 View A Register 134 Reset Value 0000 0000 RESA14 ADC Extended Result 14 View A Register 138 Reset Value 0000 E000 ADC RESA15 ADC Extended Result 15 View A Register 13C Reset Value 0000 F000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHNR RESULT r rh User Manual 6 30 V 1 0 2005 11 A
21. 00 Atime out interrupt can be generated if a non ack condition is detected 01 Atime out interrupt can be generated if a non ack condition is detected 10 A time out interrupt can be generated if 2 consecutive non ack conditions are detected 11 Atime out interrupt can be generated if 3 consecutive non ack conditions are detected MDP 13 10 W Maximum Delay for Parity Error This bit field determines a window for the transmitter in number of TCLK clock periods in which a TREADY low to high signal transition signal is considered as correctly received condition 0000 Zero clock periods selected not useful 0001 1 clock period selected 1110 14 clock periods selected 1111 15 clock periods selected NO No Address Prediction This bit field enables disables the address prediction for read or write frames see Page 4 38 0 Address prediction is enabled 1 Address prediction is disabled TP Type of Parity This bit determines the type of parity used in frame transmissions For correct data transfers TP 0 must be programmed The value TP 1 can be selected to force parity errors to analyze the propagation delay see Page 4 17 0 Even parity is selected 1 Odd parity selected User Manual MLI V1 0 4 61 V 1 0 2005 11 Cinfineon CIC751 Micro Link Interface MLI Field Bits Type Description 3 81 16 Reserved Read as 0 should be wr
22. 1 52 x pc 6 x sys 2600 400 150 ns 3 1 5 us Post calibr off 40 x 6 x 2000 400 150 ns 2 55 us Conversion 8 bit With post calibr ts 44 6 x tsys 2200 400 150 ns 2 75 us Post calibr off tog tg 92 x 6 x tsys 1600 400 150 ns 2 15 us Note For the exact specification refer to the data sheet of the selected derivative User Manual 6 14 V 1 0 2005 11 ADC V1 0 Cinfineon The Analog Digital Converter 6 6 A D Converter Interrupt Operation The ADC offers different interrupts request triggers that can occur due to different cases End of conversion interrupt ADC event 0 the result of a conversion is placed into register ADC_DAT Error injection interrupt ADC event 1 a conversion result overwrites a previous value in register ADC_DAT error interrupt in standard mode the result of an injected conversion has been stored into ADC_DAT2 end of injected conversion interrupt e ADC event 2 the OR combination of all valid bits of the ADC_RESBn registers 6 6 1 Interrupt Event Handling Interrupt events can be handled in three different ways Trigger an DMA action Forward the interrupt to pin SRn 6 6 1 1 Trigger DMA Action Both ADC interrupts can be used to trigger a DMA transfer This mechanism can be used to store the conversion result within a extended result regis
23. RREADY map 7 4 o RDATA _ _ _ _ Figure 4 24 MLI Communication without Parity Error Indicator Receiver View RCR DPE eu ITU LIP LE LILI LET RREADY RVALID _ E sm e s gt gt t P RDATA rIA e vv N Parr_error_rec Figure 4 25 MLI Communication with Parity Error Indicator Receiver View 4 2 2 2 Non Acknowledge Error A non acknowledge error condition is detected by the transmitter when at the end of a frame transmission the TREADY signal is still at high level TREADY 1 when TVALID becomes 0 In this case the error flag MLI TSTATR NAE is set and the maximum non acknowledge error counter TCR MNAE is decremented by 1 If a non acknowledge error condition is detected and MLI TCR MNAE is becoming or while it is already 0 a time out interrupt event is generated by setting bit MLI TISR TEI and an MLI Request is generated if enabled by MLI TIER TEIE 1 The non acknowledge error flag User Manual 4 37 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI MLI_TSTATR NAE is cleared when a frame transmission has been acknowledged correctly It can also be cleared by software when writing 1 to bit MLI SCR CNAE The non acknowledge error counter TCR MNAE is automatically set to 11g when frame has been acknowledged correctly It
24. Automatic pad control possible Flexible data format Programmable shift direction LSB or MSB shift first Programmable clock polarity Idle low or idle high state for the shift clock Programmable clock data phase Data shift with leading or trailing edge of the shift clock e Internal Master Function Access to the all addresses Automatic address handling Automatic data handling User Manual 5 1 V 1 0 2005 11 SSC 1 0 Cinfineon Synchronous Serial Interface SSC 5 2 General Operation The SSC supports full duplex half duplex synchronous communication up to 10 5 40 MHz module clock The serial clock signal is received from an external master Slave Mode Data width shift direction clock polarity and phase are programmable This allows communication with SPI compatible devices Transmission and reception of data are double buffered A shift clock generator provides the SSC with a separate serial clock signal Configuration of the high speed synchronous serial interface is very flexible so it can work with other synchronous serial interfaces can serve for master slave or multi master interconnections or can operate compatibly with the popular SPI interface The SSC supports half duplex and full duplex communication Data is transmitted or received on pins MTSR Master Transmit Slave Receive and MRST Master Receive Slave Transmit The clock signal is received via pin SCLK Serial Cl
25. Figure 3 9 Hardware controlled Single Mode Operation Hardware controlled Continuous Mode In hardware controlled Continuous Mode CHCR0n CHMODE 1 the hardware transaction request enable bit is not reset at the end of transaction new transaction of DMA channel 0n with the parameters actually stored in the channel register set of DMA channel 0n is started each time when CHSR0n TCOUNT reaches 000 No software re enable for a hardware request at CHOn_REQ is required User Manual 3 19 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller Combined Software Hardware controlled Mode Figure 3 10 shows how software and hardware controlled modes can be combined In the example the first DMA transfer is triggered by software when setting STREQ SCHOn Hardware requests are still disabled After hardware requests have been enabled by setting HTREQ ECHOn subsequent DMA transfers are triggered now by hardware request coming from the CHOn REQ line In the example channel On operates in Single Mode CHCROn CHMODE 0 In this mode TRSR HTREOn becomes reset by hardware when CHSROn TCOUNT reaches 0 at the end of the transaction TRSR CHOn f Writing Sa STREQ SCHOn 1 Writing 110102 HTREQ ECHOn 1 TRSR HTRE0n _ Transfer TRn 1 CHSR0n TCOUNT 0 475 tc 1 0 INT tc initial transfer count
26. Header ao M 01234 11 12 mI RR E Header M 01234 19 20 12 16 Bit Data d uds 1234 35 36 32 Data d opt write Figure 4 8 Optimized Write Frame Details about the Optimized Write Frame handling of the CIC751 are provided in Chapter 4 2 1 2 User Manual 4 10 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI 4 1 4 4 Discrete Read Frame A Discrete Read Frame is used by the Local Controller to request data to be read from the Remote Window in the Remote Controller If the read data is available the Remote Controller responds to this request by sending an Answer Frame with the requested read data back to the Local Controller The Discrete Read Frame contains the following parts Header The header starts with Frame Code FC 01g followed by the Pipe number PN of the Transfer Window that has been the target of the read operation m Bits of read offset These bits define the read offset The value of m depends on the size of the Remote Window defined by the Copy Base Address Frame m 1 16 Data Width DW The data width DW indicates if the read from the Remote Window was an 8 16 or 32 bit read action It defines how many bytes must be delivered to the Local Controller by the Answer Frame e Parity bit P Header 01234 6 m m Bit Offset Address owl disc_read Figure 4 9 Discrete Read Frame Table 4
27. Micro Link Interface MLI The Receiver Interrupt Enable Register MLI RIER contains the interrupt enable bits and the interrupt request enable flag clear bits for all receiver interrupt request sources The bits marked w are always read as 0 MLI RIER MLI Receiver Interrupt Enable Register 2 4 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 PE ICE CFR CFR IR IR IR3 IR2 IRO IR w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DRA CFR CFR CFR CFR NFR IE 0 PRIE Ice IE3 IE2 IE1 IEO IE r rw rw rw rw rw rw rw rw rw Field Bits Type Description NFRIE 1 0 rw Normal Frame Received Interrupt Enable This bit field defines whether an interrupt is generated when a Normal Frame is correctly received 00 The interrupt generation is disabled 01 Theinterrupt is generated each time a Normal Frame is correctly received 10 interrupt is generated each time a Normal Frame is correctly received that is not handled automatically by the MLI e g an Answer Frame 11 Reserved CFRIEO 2 rw Command Received in Pipe x Interrupt Enable CFRIE1 3 This bit determines whether an interrupt is generated CFRIE2 4 when a Command Frame for Pipe x has been received CFRIE3 5 correctly 0 Command received in Pipe x interrupt is disabled 1 Command rec
28. CHICROn ADRCROn Channel Address Registers SADROn DADROn HTREQ ERRSR CLRE MEOAENR MEOARR SHADROn 06175 M Figure 3 15 DMA Kernel Registers Table 3 2 Registers Address Space DMA Kernel Registers Module Base Address End Address Note DMA 0000 0400 0000 O5FF Table 3 3 Registers Overview DMA Kernel Registers Register Short Register Long Name Address Description Name see CHRSTR DMA Channel Reset Request Register 0410 Page 3 29 DMA TRSR DMA Transaction Request State 0414 Page 3 31 Register DMA_STREQ DMA Software Transaction Request 0418 Page 3 32 Register User Manual 3 26 V 1 0 2005 11 DMA V1 0 Cinfineon CIC751 Direct Memory Access Controller Table 3 3 Registers Overview DMA Kernel Registers cont d Register Short Register Long Name Address Description Name see DMA HTREQ DMA Hardware Transaction Request 0410C Page 3 33 Register ERRSR Error Status Register 0424 Page 3 34 DMA CLRE DMA Clear Error Register 0428 3 36 Move Engine Status Register 0430 3 37 DMA Move Engine 0 Read Register 0434 3 38 CHSROn Channel On Status Register nx 204 Page 3 42 n 0 7 0480 CHCROn Channel Control Register nx 20y Page 3 39 n 0 7 0484
29. INTOn triggered by TCOUNT 0 MCT06155 Figure 3 8 Software Controlled Mode Operation User Manual 3 17 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller Hardware controlled Modes In hardware controlled modes a hardware request signal starts a DMA transaction or a single DMA transfer There are two hardware controlled modes available Single Mode Hardware requests are disabled by hardware after a DMA transaction Continuous Mode Hardware requests are not disabled by hardware after a DMA transaction Hardware controlled Single Mode In hardware controlled Single Modes one hardware request starts one complete DMA transaction or one single DMA transfer The hardware controlled Single Mode that initiates one complete DMA transaction to be executed for DMA channel 0n is selected by the following operations e CHCROn CHMODE 0 e CHCROn RROAT 1 Selecting one of the eight hardware request inputs via CHCROn PRSEL e HTREQ ECHOn 1 Setting HTREQ ECHOn to 1 causes the hardware request CHOn REQ of channel On to be enabled TRSR HTREOn 1 Whenever the hardware request CHOn becomes active the value of CHCROn TREL is loaded into CHSROn TCOUNT and the DMA transaction is started by executing its first DMA transfer After each DMA transfer TCOUNT becomes decremented and next source and destination addresses are calculated When TCOUNT reaches the 0 channel becomes dis
30. Reset Value 0000 0000 ADC_RESB10 ADC Extended Result 10 View B Register 168 Reset Value 0000 0000 ADC_RESB11 ADC Extended Result 11 View B Register 16C Reset Value 0000 0000 ADC_RESB12 ADC Extended Result 12 View Register 170 Reset Value 0000 0000 ADC_RESB13 ADC Extended Result 13 View Register 174 Reset Value 0000 0000 ADC_RESB14 ADC Extended Result 14 View B Register 178 Reset Value 0000 0000 ADC_RESB15 ADC Extended Result 15 View Register 178 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 V 0 RESULT rh r rh User Manual 6 32 V 1 0 2005 11 ADC V1 0 Cinfineon CIC751 The Analog Digital Converter Field Bits Type Description RESULT 11 0 Conversion Result This bit field represents the conversion result for the selected channel If the conversion result is smaller than 10 bits the result always starts with its MSB at bit position 11 and the unused bit positions are filled with 0 rh Valid This bit indicates that the result has been written with a new value since the last read from this location It becomes set with the write action of a new result and cleared when at least the low byte of the result is read out 0 The result is not new has already been read out 1 The result is new has not yet been read out 0 14 12 31 16 A Reserved Read as 0 s
31. ADRCR5 all three registers be updated with a single SSC communication block 5 2 2 2 SSC Data Flow Model As the SSC operates only as slave the master must follow some rules to establish a working communication link Communication Rules e An SSC communication block is composed out of one Transaction Header and several data blocks EN e An SSC communication block is started by the master with an assertion of 515 e An SSC communication block is stopped by the master with de assertion of SLS The duration of a communication block should always be a multiple of 16 SCLK cycles Adata block is the data that is transmitted during the 16 SCLK cycles Only 16 bit data blocks are legal for an SSC communication e The first 16 bit data block is always used as the transaction header All 16 bit data blocks after the transaction header are used as write or read data SSC Write Operation CMD 1 For each SSC transfer that is received via the SSC interface the transaction header information is extracted from the first transmitted halfword which is the command CMD the increment indicator INCE and the address ADDR The following halfwords are then used as data With CMD INCE and ADDR available the data is copied to the destination address according to the setting of INCE and ADDR The pin RDY is provided for additional synchronization between the host and slave This pin or information is required due to the fact that the
32. LOCK rh PLL Lock Status Flag 0 PLL is not locked 1 PLL is locked RESLD rwh Restart Lock Detection Setting this bit will reset bit LOCK and restart the lock detection When set this bit is automatically cleared 0 No effect 1 Reset LOCK and restart lock detection SWRST Software Reset Trigger Setting this bit will automatically request and generate a reset With the reset execution this bit is automatically cleared P1DIDIS Port 1 Digital Input Disable This bit controls the digital input stage for all port 1 pins 0 Digital input stage Schmitt trigger is enabled 1 Digital input stage Schmitt trigger is disabled This is necessary if pins are used as analog input MTM 7 6 Multiplexer Test Mode for Channel 0 This bit enables disables the Multiplexer Test Mode for the input channel 0 This feature is independent of the current mode of the analog part If the Multiplexer Test Mode is enabled the analog input is connected to ADC ground via an internal resistance This structure creates a voltage divider to ground so the measurement result becomes smaller 00 Multiplexer Test Mode is disabled The analog input is not connected to ground and can be used for normal measurements 01 The Multiplexer Test Mode is enabled The internal resistance to ground is in the range of 300 Ohm 10 The Multiplexer Test Mode is enabled The internal resistance to ground is in th
33. MLI RDATAR 10 32 bit relevant data width in MLI RDATAR 11 Reserved TF 12 11 Type of Frame This bit field determines the frame type that has most recently been received by the MLI receiver It is updated whenever the MLI receiver updates MLI RDATAR MLI RADRR or MLI RPxBAR The most recently received frame was a 00 Base Address Frame 01 Discrete Read Frame or Optimized Read Frame 10 Write Offset and Data Frame or Optimized Write Frame 11 Answer Frame PE rh Parity Error PE is set when a parity error is detected by the receiver in a received frame see Page 4 34 PE is cleared by hardware when a frame has been received without parity error can be cleared via bit MLI SCR CRPE RPN 15 14 Received Pipe Number This bit field contains the Pipe Number that was indicated by the Pipe Number bit field of the latest received frame It is updated by any received frame User Manual MLI V1 0 4 76 V 1 0 2005 11 Cinfineon CIC751 Micro Link Interface MLI Field Bits Type Description MPE 19 16 rwh Maximum Parity Errors This bit field indicates the number of receive parity error conditions after which a receiver parity error interrupt event will be generated It is set to a desired value by software and it is decremented down to 0 automatically by the MLI each time it detects a receiver parity error condition If a receiver pari
34. Reset Values Reset Short Name Reset Mode Note SSC Mode Selected 0020 020 Asynchronous MLI Mode Selected 0020 9020 Asynchronous PO IOCR8 Port 0 Input Output Control 8 Register A18 Reset Value Table 7 6 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PC11 0 10 0 r rw r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 9 0 0 r rw r User Manual 7 10 V 1 0 2005 11 Parallel Ports V1 0 Cinfineon CIC751 Parallel Ports Field Bits Type Description PC8 7 4 rw Port Input Output Control Bit 8 see Table 7 4 PC9 15 12 rw Port Input Output Control Bit 9 see Table 7 4 PC10 23 20 rw Port Input Output Control Bit 10 see Table 7 4 PC11 31 28 rw Port Input Output Control Bit 11 see Table 7 4 0 3 0 r Reserved 11 8 Read as 0 should be written with 0 19 16 27 24 Table 7 6 Register Reset Values Register Reset Type Reset Values Reset Short Name Reset Mode Note SSC Mode Selected 2020 2020 Asynchronous MLI Mode Selected 202020204 l Asynchronous PO IOCR12 Port 0 Input Output Control 12 Register A1Cj Reset Value Table 7 7 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 12 0 r rw r Field Bits Type Description PC12 7 4 rw Port Input Output Control Bit 12 see Table 7 4 User Manual 7 11
35. The MLI transmitter can generate the following interrupts User Manual 4 41 V 1 0 2005 11 MLI V1 0 Cinfineon CIC751 Micro Link Interface MLI Table 4 8 MLI Transmitter Interrupts Interrupt Events Interrupt See Parity Error Parity Time out Error Page 4 43 Time out Error Normal Frame Sent in Pipe 0 Normal Frame Sent in Pipe 0 Page 4 43 Normal Frame Sent in Pipe 1 Normal Frame Sent in Pipe 1 Normal Frame Sent in Pipe 2 Normal Frame Sent in Pipe 2 Normal Frame Sent in Pipe 3 Normal Frame Sent in Pipe 3 Command Frame Sent in Pipe 0 Command Frame Sent Page 4 43 Command Frame Sent in Pipe 1 Command Frame Sent in Pipe 2 Command Frame Sent in Pipe 3 User Manual 4 42 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI 4 2 5 1 Parity Time out Error Interrupt A parity time out error interrupt is generated when a programmable maximum number of parity errors or a programmable maximum number of non acknowledge errors has been reached Both interrupt events have separate status control bits but are concatenated to one common error interrupt 4 2 5 2 Normal Frame Sent x Interrupt A Normal Frame sent x x 0 3 interrupt is generated when a Normal Frame has been sent and correctly received in Pipe x 4 2 5 3 Command Frame Sent Interrupt A Command Frame sent interrupt is generated when the MLI transmitter has sent a Command Frame through Pipe x x 0 3
36. User Manual 4 66 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI Field Bits Type Description CMDP1 11 8 rw Command Code for Pipe 1 This bit field contains the command code related to Pipe 1 The Pipe 1 command codes allow to adjust the receiver delay for the parity error condition see MLI_RCR DPE in the MLI receiver of the Remote Controller 0000 Set MLI RCR DPE 0000p 0001 Set MLI RCR DPE 0001 1111 Set MLI RCR DPE 1111p CMDP2 19 16 rw Command Code for Pipe 2 This bit field contains the command code related to Pipe 2 The Pipe 2 command codes allow to control the MLI receiver in the Remote Controller 0001 Select Automatic Data Mode set RCR MOD 1 0010 Automatic Data Mode is disabled set MLI RCR MOD 0 0100 Clear bit MLI TRSTATR RPO 0101 Clear bit MLI TRSTATR RP1 0110 Clear bit MLI TRSTATR RP2 0111 Clear bit MLI TRSTATR RP3 1111 Activate MLI break event else No action CMDP3 27 24 rw Command Code for Pipe 3 This bit field contains the command code related to Pipe 3 The command codes for Pipe 3 are free programmable 0 7 4 Ir Reserved 15 12 Read as 0 should be written with O 23 20 31 28 User Manual 4 67 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI 4 3 2 5 Transmitter Receiver Status Register The Transmitter Receiver Status Register MLI TRSTATR contains read only flags that indicate the status of
37. _ DMA Channel Address Control nx 20 Page 3 43 ADRCROn Register n 0 7 048C SADROn DMA Channel On Source Address nx 20 Page 3 47 Register n 0 7 0490 DMA DADROn Channel Destination Address n x 20 Page 3 48 Register n 0 7 0494 DMA SHADROn DMA Channel Shadow Address nx 20 Page 3 49 Register n 0 7 0498 User Manual 3 27 V 1 0 2005 11 DMA V1 0 Cinfineon 3 3 1 CIC751 Direct Memory Access Controller General Control Status Registers The following registers are used to configure and control the request generation of the DMA from the system point of view SCU ETCTR External Trigger Control Register 850 Reset Value 0000 0000 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 1 1 10 9 8 7 6 5 4 3 2 1 0 HEN 0 INSEL1 FEN 0 INSEL0 1 1 0 0 rw rw r rw x rw rw r rw Field Bits Type Description INSEL0 2 0 rw Input Selection for Pin Trigger 0 This bit field defines the Trigger Source for Pin Trigger 0 000 Pin SRO is selected 001 Pin SR1 is selected 010 Pin SR2 is selected 011 Pin is selected 100 Pin SR4 is selected 101 MLI Break Event is selected 110 Pin AIN4 is selected 111 Pin AIN14 is selected FENO 6 rw Falling Edge Enable for Pin Trigger 0 This bit enables disables the activation of Pin Trigger 0 upon a
38. address is added to the base address of the Pipe x stored in MLI RPXBAR ADDR x 0 3 The result of this addition is stored both MLI RADRR ADDR MLI RPxBAR ADDR and represents the source address of the Remote Controller where data should be read In the case of an Optimized Read Frame The result of the address prediction is taken into account The next address in the Remote Controller where data is read is calculated by adding the detected receiver address prediction value RPXSTATR AP x 0 3 to the actual address stored in RPXBAR ADDR 0 3 The result of this addition is stored MLI RADRR ADDR and MLI RPxBAR ADDR and represents the destination address in the Remote Controller User Manual 4 27 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI The transmitted data width DW is stored in bit field MLI RCR DW The information about the received frame type is stored in bit field RCR TF e Interrupt status flag RISR NFHI is set and MLI Request is generated if enabled by MLI RIER NFRIE 01g or 10g After correct reception of a read frame by the Remote Controller the data requested by the Local Controller can be read by the Remote Controller and sent back to the Local Controller by an Answer Frame This read operation can be executed in two ways MLI RCR MOD 0 Automatic Data Mode is disabled The DMA is requested by an MLI Request generated by the Normal Fram
39. slaves must program their MRST pins to input Therefore only one slave can input its data to the master s receive line Only reception of data from the master is possible The master selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave The selected slave then switches its MRST line to output until it gets a de selection signal or command The slaves use an open drain output on MRST This forms a wired AND connection The receive line needs an external pull up in this case Corruption of the data on the receive line sent by the selected slave is avoided when all slaves not selected for transmission to the master send only 1s Since this high level is not actively driven onto the line but is only held through the pull up device the selected slave can pull this line actively to a low level when transmitting a 0 bit The master User Manual 5 4 V 1 0 2005 11 SSC 1 0 Cinfineon Synchronous Serial Interface SSC selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave After performing all necessary initialization tasks for the SSC the serial interfaces can be enabled For a master device the alternate clock line will now go to its programmed polarity The alternate data line will go to either 0 or 1 until the first transfer starts After a transfer the alternate data line will al
40. 0 31 28 User Manual 4 52 V 1 0 2005 11 MLI V1 0 Cinfineon CIC751 Micro Link Interface MLI 4 3 1 3 Global Interrupt Set Register The Global Interrupt Set Register MLI GINTR is a write only register always reads 0 that allows each of the MLI Requests to be activated under software control MLI GINTR MLI Global Interrupt Set Register 2 0 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 9 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 SI SI SI 5 MLI3 MLI2 MLIO w w w w Field Bits Type Description SIMLIx x w Set MLI Service Request Output Line x x 0 3 0 No action 1 MLI Request x is activated 0 31 4 r Reserved Read as 0 should be written with 0 User Manual 4 53 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI 4 3 1 4 Output Input Control Register The Output Input Control Register MLI_OICR determines the functionality of the MLI transmitter and MLI receiver I O control logic MLI_OICR MLI Output Input Control Register 2B4 Reset Value 1000 8000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RDS RCE RCP RCS RVP RVS 0 0 RRS rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RVE TDP TCP TCE TRE TRP TRS
41. 0 T 0 0 rw rw rw rw rw rw rw rw rw rw rw rw Field Bits Type Description TVEB 1 rw Transmitter Valid Enable This bit enables the MLI transmitter output signal TVALID 0 TVALID is disabled and remains at passive level as selected by TVPB 1 Transmitter output signal TVALID is enabled and driven TVPB 5 rw Transmitter Valid Polarity This bit determines the polarity of the transmitter output signals TVALID 0 Non inverted polarity for TVALID selected TVALID is passive when driving a 0 TVALID is active when driving a 1 1 Inverted polarity for TVALID selected TVALID is passive when driving a 1 TVALID is active when driving a 0 User Manual 4 54 V 1 0 2005 11 MLI V1 0 Cinfineon CIC751 Micro Link Interface MLI Field Bits Type Description TRS 9 8 rw Transmitter Ready Selection This bit field determines the input TREADY that is used as MLI transmitter input 00g TREADY is not connected to the MLI Olg TREADY is selected 106 TREADY is not connected to the MLI 116 TREADY is not connected to the MLI TRP Transmitter Ready Polarity This bit determines the polarity of TREADY 0 Non inverted polarity for TREADY selected TREADY is passive if 0 TREADY is active if 1 1 Inverted polarity for TREADY selected TREADY is passive if 1 TREADY if 0 TRE Transmitter Ready Enable This bit enables the MLI transmitter input signal TREADY 0 TREADY signa
42. 0000 020C Page 4 49 MLI_TCR Transmitter Control Register 0000 0210 Page 4 59 MLI_TSTATR Transmitter Status Register 00000214 Page 4 62 TPOSTATR Transmitter Pipe 0 Status Register 0000 0218 4 64 MLI_TP1STATR Transmitter Pipe 1 Status Register 0000 021 Page 4 64 MLI TP2STATR Transmitter Pipe 2 Status Register 0000 0220 Page 4 64 MLI_TP3STATR Transmitter Pipe Status Register 00000224 Page 4 64 MLI_TCMDR Transmitter Command Register 0000 0228 4 66 MLI TSTATR Transmitter Receiver Status 0000 022C Page 4 62 Register MLI TPOAOFR Transmitter Pipe 0 Address Offset 0000 0230 4 70 Register MLI TP1AOFR Transmitter Pipe 1 Address Offset 0000 0234 4 70 Register MLI TP2AOFR Transmitter Pipe 2 Address Offset 0000 0238 4 70 Register MLI Transmitter Pipe Address Offset 0000 023C Page 4 70 Register MLI TPODATAR Transmitter Pipe 0 Data Register 0000 0240 4 71 MLI TP1DATAR Transmitter Pipe 1 Data Register 0000 0244 4 71 MLI TP2DATAR Transmitter Pipe 2 Data Register 0000 0248 Page 4 71 MLI Transmitter Pipe 3 Data Register 0000 024C Page 4 71 MLI TDRAR Transmitter Data Read Answer 0000 0250 Page 4 72 Register MLI TPOBAR Transmitter Pipe 0 Base Address 00000254 Page 4 73 Register User Manual 8 4 V 1 0 2005 11 Regs V1 0 Cinfineon CIC751 Register Overview
43. 1 View Register 104 Page 6 30 RESA1 ADC ADC Extended Result 2 View A Register 1084 Page 6 30 RESA2 ADC_ ADC Extended Result 3 View Register 10C Page 6 30 RESA3 ADC ADC Extended Result 4 View A Register 110 6 30 RESA4 ADC ADC Extended Result 5 View A Register 114 Page 6 30 RESA5 ADC ADC Extended Result 6 View A Register 118 Page 6 30 RESA6 ADC ADC Extended Result 7 View A Register 11C Page 6 30 RESA7 ADC ADC Extended Result 8 View A Register 120 Page 6 30 RESA8 ADC ADC Extended Result 9 View A Register 1244 Page 6 30 RESA9 User Manual 6 19 V 1 0 2005 11 ADC V1 0 Cinfineon CIC751 The Analog Digital Converter Table 6 5 Registers Overview cont d Register Register Long Name Offset Page Short Name Address Number ADC ADC Extended Result 10 View A Register 128 Page 6 30 RESA10 ADC ADC Extended Result 11 View A Register 126 6 30 RESA11 ADC_ ADC Extended Result 12 View Register 130 Page 6 30 RESA12 ADC ADC Extended Result 13 View A Register 134 Page 6 30 RESA13 ADC ADC Extended Result 14 View A Register 1384 Page 6 30 RESA14 ADC_ ADC Extended Result 15 View A Register 13C Page 6 30 RESA15 ADC ADC Extended Result 0 View B Register 140 6 32 RESB0 ADC_ ADC Extended Result 1 View B Register 144 Page 6 32 RESB1 ADC ADC Extended Result 2 View B Register 1484 Page 6 32 RESB2 ADC_ ADC Extended R
44. 100 0 16 100 0 32 1008 0 64 1 16 1 32 1 64 101 0 32 101 0 64 101 0 128 1 32 1 64 1 128 110 0 64 1108 0 128 1108 0 256 1 64 1 128 1 256 111 0 128 111 0 256 111 0 512 1 128 1 256 1 512 Note CHCR0n CHDW 115 reserved and should be used User Manual 3 46 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller 3 3 4 Channel Address Registers The Source Address Register contains the 32 bit source address If DMA channel is active SADROn is updated continuously if programmed and shows the actual source address that is used for read moves within DMA transfers DMA SADROn 0 7 DMA Channel Source Address Register 490 n 20 Reset Value 0000 0000 2r E SADR mE w 777 Field Bits Type Description SADR 31 0 rwh Source Start Address This bit field holds the actual 32 bit source address of DMA channel 0n that is used for read moves A write to SADROn is executed directly only when the DMA channel On is inactive CHSROn TCOUNT 0 and TRSR CHOn 0 If DMA channel is active when writing to SADROn the source address will not be written into SADROn directly but will be buffered in the shadow register SADROn until the start of the next DMA transaction During this shadowed address register operation bit field ADRCROn SHCT must be set to 01g User Manual 3 47 V 1 0 2005
45. 11 DMA V1 0 Cinfineon Direct Memory Access Controller The Destination Address Register contains the 32 bit destination address If a DMA channel is active DADROn is updated continuously if programmed and shows the actual destination address that is used for write moves within DMA transfers DMA DADROn n 0 7 DMA Channel 0n Destination Address Register 494 n 20 Reset Value 0000 0000 E DADR Field Bits Type Description DADR 31 0 Destination Address This bit field holds the actual 32 bit destination address of DMA channel 0n that is used for write moves A write to DADROn is executed directly only when the DMA channel On is inactive CHSROn TCOUNT 0 and TRSR CHOn 0 If DMA channel is active when writing to DADROn the source address will not be written into DADROn directly but will be buffered in the shadow register SADROn until the start of the next DMA transaction During this shadowed address register operation bit field ADRCROn SHCT must be set to 10g User Manual 3 48 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller The Shadow Address Register holds the shadowed source or destination address before it is written into the source or destination address register SHADROn can be read only SHADROn 0 7 DMA Channel 0n Shadow Address Register
46. 16 0 0 DER r w r w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 07 06 05 04 03 02 01 00 r w w w w w w w w Field Bits Description CTLOn n w Clear Transaction Request Lost for DMA Channel n 0 7 0 action 1 Clear channel transaction request lost flag ERRSR TRL0n CMEOSER 16 w Clear Move Engine 0 Source Error 0 No action 1 Clear source error flag ERRSR ME0SER CMEODER 17 w Clear Move Engine 0 Destination Error 0 No action 1 Clear destination error flag ERRSR ME0DER CLRMLIO 27 w Clear MLI0 Error 0 No action 1 Clear error flag ERRSR MLI0 0 15 8 r Reserved 26 18 Read as 0 should be written with 0 31 28 User Manual 3 36 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller 3 3 2 Move Engine Registers The Move Engine Status Register is a read only register that holds status information about the transaction handled by the Move Engines DMA_MESR DMA Move Engine Status Register 430 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
47. 2 4 This bit has to be cleared by software User Manual 5 20 V 1 0 2005 11 SSC 1 0 Cinfineon Synchronous Serial Interface SSC Field Bits Type Description PE 10 w Phase Error Flag 0 No error 1 Received data changes around the sampling clock edge This bit is set in case of a Phase Error event see Chapter 5 2 4 This bit has to be cleared by software 0 15 rwh Reserved Read as 0 have to be written with 0 0 7 0 r Reserved 31 12 Read as 0 should be written with 0 SSC_TB SSC Transmit Buffer Register 20 Reset Value 0000 0000 31 30 22 28 27 26 25 24 23 22 21 00 19 18 17 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TB VALUE rw Field Bits Type Description TB_VALUE 15 0 rw Transmit Data Register Value Register SSC_TB stores the data value to be transmitted TB_VALUE Reserved Returns 0 if read should be written with 0 0 31 16 The Receive Buffer Register RB contains the receive data value User Manual 5 21 V 1 0 2005 11 SSC 1 0 Cinfineon Synchronous Serial Interface SSC SSC_RB SSC Receive Buffer Register 24 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Field Bits Type Description RB_VALUE 15 0 rh Receive Data Register Value Register RB contains the received data value
48. 2 Embedded Voltage Regulator EVR Reset 2 1 2 2 Mode Selection 2 1 2 2 1 MODE 3 weenie a 2 2 2 2 2 TESIMODE PD 35525555 o eed ened sapa eu qa 2 2 2 3 Clock System 2 2 2 3 1 CT 2 2 2 3 2 Clock Generation Unit 2 2 2 3 2 1 RC Oscillator Circuit RCOSC 2 3 2 3 2 2 Phase Locked Loop PLL Module 2 4 2 3 2 3 Clock Control Unit 2 10 2 4 Power Supply System 2 10 2 4 1 Embedded Voltage Regulator 2 11 2 5 Event Gontol HC a RAEE 2 11 2 5 1 Event Sources 2 11 2 5 2 External Trigger Inputs 2 11 2 5 3 Event Output Structure 2 12 2 5 3 1 Service Request Routing 2 13 2 6 SCU Registers i carae zu a 2 14 2 6 1 Clock Control Registers 2 14 2 6 2 Miscellaneous SCU Registers 2 16 2 7 SCU Register 2 24 3 Direct Memory Access Controller
49. 25 24 23 22 21 20 9 18 17 16 0 C C C C 0 C C NAE TPE RPE AV BAV IMOD W w w w w W w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C C C C C C C C 0 s s s s s 2 CV1 CVO DV2 DV1 DVO MOD CV3 CV2 CV1 CVO w w w w w w w w w w w w w w Field Bits Type Description SCV0 0 w Set Command Valid SCV1 1 0 No effect SCV2 2 1 Bit MLI_TRSTATR CVx is set SCV3 3 SMOD 4 w Set MOD Flag 0 No effect 1 If CMOD 0 MLI RCR is set If CMOD 1 MLI RCR MOD is cleared CDVO 8 w Clear Data Valid x Flag CDV1 9 0 No effect CDV2 10 1 If SCVx 0 bits MLI TRSTATR DVx CDV3 11 MLI_TRSTATR RPx are cleared If SCVx 1 bit MLL TRSTATR DVx is set CCVO 12 w Clear Command Valid x Flag CCV1 13 0 No effect 2 14 1 Bit MLI_TRSTATR CVx is cleared CCV3 15 CMOD 16 w Clear MOD Flag 0 No effect 1 Bit MLI_RCR MOD is cleared User Manual 4 51 V 1 0 2005 11 MLI V1 0 Cinfineon CIC751 Micro Link Interface MLI Field Bits Type Description CBAV 17 w Clear BAV Flag 0 No effect 1 Bit MLI_TRSTATR BAV is cleared CAV 24 w Clear AV Flag 0 No effect 1 Bit MLI_TRSTATR AV is cleared CRPE 25 w Clear Receiver PE Flag 0 No effect 1 Bit MLI_RCR PE is cleared CTPE 26 w Clear Transmitter PE Flag 0 No effect 1 Bit MLI_TSTATR PE is cleared CNAE 27 w Clear NAE Flag 0 No effect 1 Bit MLI_TSTATR NAE is cleared 0 7 5 w Reserved 23 18 Read as 0 should be written with
50. 3 UNE UN 20 CN NE NE VR E D TH MC CUP 2 0 rw r PC1 0 0 rw r rw r Field Bits Type Description PC0 7 4 rw Port Input Output Control Bit 0 see Table 7 4 PC1 15 12 rw Port Input Output Control Bit 1 see Table 7 4 PC2 23 20 rw Port Input Output Control Bit 2 see Table 7 4 PC3A 27 24 rw Port Input Output Control Bit 3 see Table 7 4 PC3 31 28 rw Port Input Output Control Bit 3 see Table 7 4 0 3 0 r Reserved 11 8 Read as 0 should be written with 0 19 16 Table 7 3 Register Reset Values Register Reset Type Reset Values Reset Short Name Reset Mode Note SSC Mode Selected 020 20204 l Asynchronous MLI Mode Selected 9290 0090 Asynchronous Coding of the PCx Bit field The coding of the GPIO port behavior is done by the bit fields in the port control registers PO IOCRx There s a control bit field PCx for each port pin The bit fields PCx are located User Manual 7 8 V 1 0 2005 11 Parallel Ports V1 0 1 751 Parallel Ports in separate control registers in order to allow modifying a port pin without influencing the others with simple move operations Table 7 4 PCx Coding PCx 3 0 Selected Pull up down Selected Output Function 0000 Input Mode No pull device co
51. 3 Data Width DW Coding Data Width DW Number of Data Bits to be transferred 00g 8 bit read access Olg 16 bit read access 10g 32 bit read access 11g Reserved Details about the Discrete Read Frame handling of the CIC751 are provided in Chapter 4 2 1 3 User Manual 4 11 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI 4 1 4 5 Optimized Read Frame An Optimized Read Frame is used by the Local Controller to request 8 bit 16 bit or 32 bit wide data from the Remote Controller without sending any offset address The address for the requested data is predicted and calculated by the MLI receiver of the Remote Controller The Optimized Read Frame contains the following parts Header The header starts with Frame Code FC 11g followed by the Pipe number PN of the Transfer Window that has been the target of the read operation Data Width DW The data width DW indicates if the read from the Transfer Window was an 8 16 or 32 bit read action It defines how many bytes must be delivered to the Local Controller by the Answer Frame Same coding as for the Discrete Read Frame e Parity bit P Header 4 0123456 M 1 PN pw P DW Data Width opt_read Figure 4 10 Optimized Read Frame Table 4 4 Data Width DW Coding Data Width DW Number of Data Bits to be transferred 00 8 bit read access Olg 16 bit read access 10g 32 bit read access 11g Rese
52. Address Description Short Name see 5 7 DMA Channel 7 Shadow Address 0000 0578 Page 3 49 Reserved Reserved 0000 0580 0000 O5FF Table 8 4 SCU Registers Register Short Register Long Name Address Description Name see SCU OSCCON SCU Oscillator Control Register 0000 0800 Page 2 14 SCU PLLCON SCU PLL Control Register 0000 0804 Page 2 15 Reserved Reserved 0000 0808 0000 081C SCU SYSCON SCU System Control Register 0000 0820 Page 2 16 Reserved Reserved 00000824 0000 082C SCU CHTRO SCU Channel Trigger 0 Register 0000 0830 Page 2 22 SCU CHTR1 SCU Channel Trigger 1 Register 0000 0834 Page 2 22 SCU CHTR2 SCU Channel Trigger 2 Register 0000 0838 Page 2 22 SCU CHTR3 SCU Channel Trigger Register 0000 083C 2 22 SCU_CHTR4 SCU Channel Trigger 4 Register 0000 0840 Page 2 22 SCU CHTR5 SCU Channel Trigger 5 Register 0000 0844 Page 2 22 SCU CHTR6 SCU Channel Trigger 6 Register 0000 0848 Page 2 22 SCU CHTR7 SCU Channel Trigger 7 Register 0000 084C Page 2 22 SCU ETCTR SCU External Trigger Control 0000 0850 Page 2 18 Register Reserved Reserved 0000 0854 SCU SRCR SCU Service Request Control 0000 0858 Page 2 19 Register SCU ERRCUM SCU Cumulative Error Register 0000 085C 5 20 User Manual 8 10 V 1 0 2005 11 Regs V1 0 Cinfineon CIC751 Register Overview Table 8 4 S
53. Address Offset Register 4 70 Transmitter Pipe x Data 4 71 Transmitter Data Read Answer Register 4 72 Transmitter Pipe x Base Address Register 4 73 Transmitter Copy Base Address Register 4 74 MLI Receiver Registers 4 75 Receiver Control Register 4 75 Receiver Pipe x Base Address Register 4 78 Receiver Pipe x Status Register 4 79 Receiver Address Register 4 81 Receiver Data Register 4 82 Transmitter Interrupt Registers 4 83 Transmitter Interrupt Enable Register 4 83 Transmitter Interrupt Register 4 85 L 3 V 1 0 2005 11 Cinfineon 4 3 4 3 4 3 5 4 3 51 4 3 5 2 4 3 5 3 4 4 6 2 1 6 2 2 6 6 1 6 6 1 1 Table Contents Transmitter Interrupt Node Pointer Register 4 86 Receiver Interrupt Registers 4 88 Receiver Interrupt Enable Register 4 88 Receiver Interrupt Status Register 4 90 Receiver Interrupt Node Pointer Register 4 92 MLI Address 4 94 Synchronous Serial Interface SSC
54. Enhanced Mode Only one of these register sets may be active at a given time As most of the bits and bit fields of the registers of the two sets control the same functionality or control the functionality in a very similar way the following description is organized according to the functionality not according to the two register sets User Manual 6 2 V 1 0 2005 11 ADC V1 0 Cinfineon The Analog Digital Converter 6 1 Mode Selection It is recommended that the digital input stage should be disabled via register STCU_SYSCON P1DIDIS if the ADC is used This avoids undesired cross currents and switching noise when the analog input signal level is between and The functions of the A D Converter are controlled by two sets of control registers In Compatibility Mode registers CON and ADC are used In Enhanced Mode registers CTR2 and CTR2IN are used Their bit fields specify the analog channel to be acted upon specify the conversion mode and also reflect the status of the converter 6 1 1 Compatibility Mode In Compatibility Mode CTRO MD 0 registers CON 1 select the basic functions 6 1 2 Enhanced Mode In Enhanced Mode ADC CTRO MD 1 registers ADC CTRO ADC CTR2 and CTR2IN select the basic functions The register layout for Enhanced Mode differs from the Compatibility Mode layout but this mode provides more options Conv
55. Offset Width 1 1 Send Discrete Read gt Frame of pipe x Parity check amp acknowledge frame Address Prediction Calculate TPxSTATR AP and TPxSTATR OP yes TPxSTATR OP 0 no RADRR ADDR RPxBAR ADDR RPxBAR modified by Offset Send Optimized Read Frame of pipe x lt Parity check amp acknowledge frame B RADRR ADDR RPxBAR ADDR RREAUY S RPxBAR ADDR RPxSTATR AP lt TRSTATR DVx 0 RCR DW TSTATR APN Send Answer RISR NFRI Frame of pipe x Parity check amp acknowledge frame RDATAR DATA Read Data Normal Frame RCR DW Width 22 Received Interrupt Read Data from Remote Window see separate figure RCR TF TRSTATR RPx RISR NFRI Normal Frame TRSTATR AV 0 Received Interrupt TREADY 1 5891 Figure 4 19 Read Frame Transaction Flow User Manual 4 26 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI Local Controller A read operation from a location within a Transfer Window delivers a dummy value as result of the read action and triggers the transmission of a read frame from the Local to the Remote Controller The 16 least significant address bits of the Transfer Window read access are stored in MLI TPXAOFR AOFF x 0 3 as read offset address The data width of the Transfer Window read
56. Others effect 01g 00008 Set MLI_RCR DPE to 0000 00018 Set RCR DPE to 0001 00108 Set RCR DPE to 0010 1111 Set RCR DPE to 11118 User Manual 4 32 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI Table 4 6 Command Frame Actions for the Remote Controller cont d PN CMD Command Description 10g 0001 Select Automatic Data Mode set MLI RCR MOD 1 00108 Select Manual Remote Data Transfer Mode set RCR MOD 0 0100g Clear bit MLI TRSTATR RP0 0101 Clear bit MLI_TRSTATR RP1 0110g Clear bit TRSTATR RP2 0111g Clear bit MLI_TRSTATR RP3 1111 Generate MLI Break Event if enabled by MLI RCR BEN 1 others No effect 116 Free programmable command stored the remote MLI receiver bit field MLI User Manual 4 33 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI 4 2 2 General MLI Features The following general features comprise the MLI Parity generation and checking see Page 4 34 e Non acknowledge error see Page 4 37 Address prediction see Page 4 38 Automatic data transfers see Page 4 39 Transmit priority see Page 4 39 4 2 2 1 Parity Generation and Checking For parity generation the number of transmitted bits with the value of 1 is counted over the header and the complete data field of a frame For even parity the parity bit
57. V 1 0 2005 11 Parallel Ports V1 0 Cinfineon CIC751 Parallel Ports Field Bits Type Description 0 3 0 r Reserved 31 8 Read as 0 should be written with O Table 7 7 Register Reset Values Register Reset Type Reset Values Reset Short Name Reset Mode Note SSC Mode Selected 0000 0020 Asynchronous MLI Mode Selected 0000 00204 l Asynchronous User Manual 7 12 V 1 0 2005 11 Parallel Ports V1 0 Cinfineon Parallel Ports 7 2 Port 1 This section describes the control mechanisms of all pins used as ADC analog channels 7 2 1 Block Diagram Figure 7 1 shows the different options for the control of port 1 2 ADC Analog Input Schmitt P1_IN Trigger Data Input Register Pad Control Logic Direct Data Input lt Y N enable disable System Control Register Figure7 2 Port 1 Control Structure 7 2 2 Input Stage The input value of each pin can be used in up to three different ways 1 The input value of pin 0 x is always available at bit P0_IN Px 2 The input can be used directly as External Trigger Input a pins P1 4 and P1 14 are usable as trigger inputs 3 The pins are used as analog inputs for the ADG a pin P1 0 is equipped with the Multiplexer Test Mode Feature User Manual 7 13 V 1 0 2005 11 Parallel Ports V1 0 Cinfineon Parallel Ports 7 2 3 Port 1 Routing The following table de
58. access 8 bit 16 bit or 32 bit is stored in bit field MLI TPXSTATR DW x 0 3 Status flag MLI TRSTATR DVXx is set Status flag MLI TRSTATR RPx is set This bit is cleared when an Answer Frame has been received correctly f the address prediction is not enabled MLI TCR NO 1 transmission of a Discrete Read Frame is started If the address prediction is enabled MLI TCR NO 0 a Discrete Read Frame is started only if an address prediction is not possible indicated TPxSTATR OP 0 If TPXSTATR OP 1 an address prediction is possible and an Optimized Read Frame is started e Status TRSTATR DVx is cleared after the read frame has been finished and correctly acknowledged by the MLI receiver of the Remote Controller The number of offset address bits that are transmitted by a Discrete Read Frame is determined by the size of the Remote Window in the Remote Controller that has been previously initialized After the transmission of a read frame the MLI expects the reception of an Answer Frame The Answer Frame is introduced with the highest priority into the data flow of the transmitter of the Remote Controller Remote Controller After a read frame has been correctly received and acknowledged the following actions are executed in the MLI receiver of the Remote Controller Inthe case of a Discrete Read Frame The result of the address prediction is not taken into account The received offset
59. address of the Transfer Window in the Local Controller The access is transferred to the Remote Controller where it is executed at the address location defined by the base address of the Remote Window plus the offset For example a write access to the 10th byte of the Transfer Window is transferred to a write to the 10th byte of the Remote Window The offset of a write action to a Transfer Window is also called a write offset whereas a read offset is related to a read action 4 1 3 MLI Communication Principles The communication principle of the MLI allows data to be transferred between a local and a Remote Controller without intervention by a CPU in the Remote Controller Data transfers are always triggered in the Local Controller by read or write operations to an address location in a Transfer Window control tasks control address and data transmissions that are required for the data transfer request between local and Remote Controller are handled autonomously by the two connected MLI modules User Manual 4 3 V 1 0 2005 11 MLI V1 0 Cinfineon CIC751 Micro Link Interface MLI Address Space Transfer Read window Interrupt lt p Local Controller Transmitter Receiver write data and write offset or read offset Remote Controller Address Space Receiver read data MCA05871_M Figure 4 2 Communication Principles Transfer Window Organization Fig
60. are programmable and should be programmed to an input function in this case The port thus becomes input whenever SLS goes high and the slave is deselected User Manual 5 24 V 1 0 2005 11 SSC 1 0 Cinfineon The Analog Digital Converter 6 The Analog Digital Converter The ClC751 provides an Analog Digital Converter with 8 bit or 10 bit resolution and a sample amp hold circuit on chip An input multiplexer selects from up to 16 analog input channels either via software Fixed Channel Modes or automatically Auto Scan Modes To fulfill most requirements of embedded control applications the ADC supports the following conversion modes Standard Conversions Fixed Channel Single Conversion produces just one result from the selected channel Fixed Channel Continuous Conversion repeatedly converts the selected channel Auto Scan Single Conversion produces one result from each of a selected group of channels Auto Scan Continuous Conversion repeatedly converts the selected group of channels Wait for Read Mode starts a conversion automatically when the previous result has been read Channel Injection Mode can insert the conversion of a specific channel into a group conversion auto scan A set of SFRs provide access to control functions and results of the ADC The Enhanced Mode registers provide more detailed control functions for the ADC The external analog reference voltages Varer and Vagnp are not program
61. bit MLI SCR CDVx User Manual 4 68 V 1 0 2005 11 MLI V1 0 Cinfineon CIC751 Micro Link Interface MLI Field Bits Type Description RPO RP1 RP2 RP3 20 21 22 23 Read Pending Bit is set when the MLI TPOAOFR register of the MLI transmitter is updated after a read access to a Transfer Window of Pipe x RPx is cleared when the MLI receiver in the Local Controller receives an Answer Frame for Pipe x from the Remote Controller RPx can be cleared via bit MLI SCR CDVx PN 25 24 Pipe Number This bit field indicates the Pipe Number x of the base address that has been written into register MLI TPxBAR 00 Register MLI TPOBAR has been written last 01 Register MLI TP1BAR has been written last 01 Register MLI TP2BAR has been written last 11 Register MLI has been written last 3 0 15 10 31 26 Reserved Read as 0 should be written with O User Manual MLI V1 0 4 69 V 1 0 2005 11 Cinfineon CIC751 Micro Link Interface MLI 4 3 2 6 Transmitter Pipe x Address Offset Register The Transmitter Pipe x Address Offset Register MLI TPxAOFR x 0 3 is a read only register that stores the offset address that has been used by the last read or write access to a Transfer Window of Pipe x MLI TPOAOFR MLI Transmitter Pipe 0 Address Offset Reg 230
62. can be read and written by software allowing a limited number of consecutive non acknowledge errors to be defined that can be detected until a non acknowledge error interrupt event is generated If for example the first occurrence of a non acknowledge error should lead to an non acknowledge interrupt bit MLI TCR MNAE has to be written by software with 01g after each correctly received frame 4 2 2 3 Address Prediction Address prediction can be enabled to support communication between the MLI transmitter and MLI receiver without sending address offset information in the frames This feature reduces the required bandwidth for MLI communication Both of the communication partners the MLI transmitter and the receiver are able to detect regular offset differences of consecutive window accesses to the same window The address prediction mechanism operates independently for each Pipe so different prediction values can be handled in parallel for the different Pipes Local Controller If the address prediction mechanism is enabled TCR NO 0 the MLI transmitter compares the offset of each Transfer Window read or write access with the offset of the previous access to the same Transfer Window stored in The result of this comparison is stored in two s complement representation in MLI TPxSTATR AP limited to 9 bits otherwise prediction is not possible Between the accesses to a specific window other windows can
63. channel 0n DMA CHRSTR DMA Channel Reset Request Register 410 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH CH CH CH CH CH 07 06 05 04 03 02 01 00 rwh rwh rwh rwh rwh rwh wh rwh L User Manual 3 29 V 1 0 2005 11 DMA V1 0 Cinfineon CIC751 Direct Memory Access Controller Field Bits Type Description CHOn n rwh Channel On Reset n 0 7 These bits force the DMA channel On to stop its current DMA transaction Once set by software this bit will be automatically cleared when the channel has been reset Writing a 0 to CHOn has no effect 0 No action write or the requested channel reset has been reset read 1 DMA channel is stopped More details see Page 3 20 0 31 8 r Reserved Read as 0 should be written with 0 User Manual 3 30 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller The bits in the Transaction Request State Register indicates which DMA channel is processing a request and which DMA channel has hardware transaction requests enabled TRSR DMA Transaction Request State Register 414 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 x M HT HT HT HT HT HT HT HT
64. channel On to be started and TRSR CHOn to be set At the start of the DMA transaction the value of CHCROn TREL is loaded into CHSROn TCOUNT transfer count or tc and the DMA transfers are executed After each DMA transfer TCOUNT becomes decremented and next source and destination addresses are calculated When TCOUNT reaches the 0 channel becomes disabled and status flag TRSR CHOn is reset Setting STREQ SCHOn again starts a new transaction of DMA channel On with the parameters as actually defined in the channel register set User Manual 3 16 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller The software controlled mode that initiates a single DMA transfer to be executed is selected for DMA channel 0n by the following write operations e CHCROn RROAT 0 e STREQ SCHOn 1 repeated for each DMA transfer When CHCROn RROAT 0 TRSR CHOn becomes reset after each DMA transfer of the DMA transaction and a new software request writing STREQ SCHOn 1 must be generated for starting the next DMA transfer CHCROn RROAT 1 TRSR CHOn Writing STREQ SCHOn 1 Transfer TROKTR1 Tum TRn TROXTR1 CHSR0n TCOUNT _ XXX 1 X X te ey tc initial transfer count INTOn triggered by TCOUNT 0 CHCROn RROAT 0 TRSR CHOn m Writing T STREQ SCHOn 1 CHSROn TCOUNT 0 tc 1 initial transfer count
65. determines the frame type of the transmitted frame The Pipe Number PN indicates the Pipe that is related to the frame content the value of PN is defined as 00 for Pipe 0 01g for Pipe 1 10g for Pipe 2 and 11g for Pipe 3 The FC parameter is coded according to Table 4 1 Table 4 1 Frame Code Definition Frame Code FC Data Field Length Frame Type Description 00g 32 Bits Copy Base Address Frame Page 4 8 01g 8 m 16 m or Write Offset and Data Frame Page 4 9 32 m Bits 6 m Bits Discrete Read Frame Page 4 11 10p 4 Bits Command Frame Page 4 13 8 16 or 32 Bits Answer Frame Page 4 14 11g 8 16 or 32 Bits Optimized Write Frame Page 4 10 2 Bits Optimized Read Frame Page 4 12 User Manual 4 7 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI 4 1 4 1 Copy Base Address Frame With a Copy Base Address Frame the two parameters base address and size of a Remote Window are transferred from the Local Controller to the Remote Controller to initialize or to update the Remote Window The Copy Base Address Frame contains the following parts Header The header starts with Frame Code FC 00g followed by the Pipe number PN of the Pipe to which the transmitted base address bits and the size are assigned e Remote Window base address The 28 most significant bits of the 32 bit base address bits can be programmed by the Local Controller the four LSBs are considered a
66. is set if the result of a modulo 2 division of the elaborated number is 1 For odd parity the parity bit is set if the result of a modulo 2 division of the elaborated number is 0 For a parity error free MLI connection even parity must be selected in the transmitter because the receiver operates only with even parity detection The capability to select odd parity can be used by the transmitter to force a parity error reply from the receiver during the startup procedure of the MLI connection This can be used to measure the propagation delay and to optimize the ready delay time Note There is no protection against frames where more than one bit is corrupted e g shortened frames In such a case unpredicted behavior of the MLI module may occur Local Controller MLI transmitter is able to count parity errors and to generate parity error interrupt when a programmable number max 16 of parity errors has occurred A parity error condition is indicated by Remote Controller after the transmission of a frame see Figure 4 23 The transmitter parity error condition is detected when the TREADY signal is sampled at low level during a programmable number MLI_TCR MDP maximum delay for parity errors of TCLK clock cycles after TVALID is de asserted When a transmitter parity error condition is detected the MLI transmitter sets the parity error flag MLI_TSTATR PE and also decreases the maximum parity error counter MLI TCR MPE 1 The
67. of the pin can be read via Pn IN or a peripheral can use the pin level as an input In Output Mode the output driver is activated and drives the value supplied through the multiplexer to the port pin Switching between Input and Output Mode is accomplished through the Pn_IOCRx registers which enables or disables the output driver If a peripheral unit uses a GPIO port line as a bi directional I O line register Pn IOCR has to be written for input or output selection The Pn IOCRx registers further controls the driver type of the output driver and determines whether an internal weak pull up or pull down device is alternatively connected to the pin when used as an input This offers additional advantages in an application The output multiplexer in front of the output driver selects the source for the GPIO line when used as output If the pin is used as general purpose output the multiplexer is switched by Pn IOCRx register to the Output Data Register Pn OUT If the on chip peripheral units use the pin for output the alternate output lines ALT1 to ALT3 can be switched via the multiplexer to the output driver The data written into the output register Pn OUT can be used as input data to an on chip peripheral When selected as general purpose output line the logic state of each port pin can be changed individually by programming the pin related bits in the Output Modification Register OMR The bits in OMR make it possible to set reset
68. operate in both microcontrollers as bus masters on the internal system bus Controller 1 Controller 2 CPU CPU Peripheral Peripheral Peripheral Peripheral A B D System Bus System Bus MCA05869 Figure 4 1 Typical Micro Link Interface Connection Features Synchronous serial communication between an MLI transmitter and an MLI receiver Different system clock speeds supported in MLI transmitter and MLI receiver due to full handshake protocol 4 lines between a transmitter and a receiver Fully transparent read write access supported 2 remote programming e Complete address range of target device Remote Controller available Specific frame protocol to transfer commands addresses and data Error detection by parity bit e 32 bit 16 bit or 8 bit data transfers supported User Manual 4 1 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI e Programmable baud rate 2 max fui fsys Multiple receiving devices supported 4 1 2 MLI Specific Terms Local and Remote Controller The terms local and remote controller are assigned to the two partners microcontrollers or other devices with MLI modules in a serial MLI connection The controller with an MLI module that operates as a transmitter in the serial MLI connection is defined as a Local Controller A Local Controller handles data operations with Transfer Windows and
69. output line 5 SR5 After latching the initial state with the rising edge of the PORST signal see Chapter 2 5 this pin can be used as an additional general purpose or SR5 output line TESTMODE 27 Test Mode Selection P0 9 0 Reserved do no use 1 Normal Mode After latching the initial state with the rising edge of the PORST signal this pin can be used as an additional general purpose or special function I O line see Chapter 2 5 SRO 28 Event request output line 0 P0 10 SR1 29 External Trigger P0 11 SR2 30 External Trigger P0 12 PORST 31 Power on Reset 34 5 Power Supply supply for ADC module Vppp 18 33 143 3 Power Supply supply for pads or 5 0 V 16 2 5 Power Supply supply for digital module cores Vss 15 32 0V Ground 1 Inaddition to the analog input function of pin P1 x a digital input stage is available This input stage is activated while STCU_SYSCON P1DIDIS 0 The initial logic state on pin MODE is latched while the PORST input is active A weak pull up can be disabled if used as the SR5 pin The initial logic state on pin TESTMODE is latched while the PORST input is active 2 3 Figure 1 2 shows the pin out for a 38 pin package User Manual 1 7 V 1 0 2005 11 Introduction V 1 0 Cinfineon Introduction Modules Ports Pins Function TCLK SR3 TREADY SR4 TVALID SCLK
70. received write data to the Remote Window address and sets interrupt status flag RISR MEI when the access is terminated An MLI Request is generated if enabled by MLI RIER MEIE 1 RCR MOD 1 gt P Write to remote window is executed automatically Write to remote window is not executed RISR NFRI 1 RISR MEI 1 Normal Frame Received Interrupt Y MLI write2remote Figure 4 18 Write Frame Handling on Remote Side Note In Automatic Data Mode write frames lead to a write action executed by the MLI During the move operation only one new MLI frame can be received stored in a waiting position to be executed Then the reception of more frames is blocked by User Manual 4 24 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI non acknowledge errors If the move operation is finished frame execution and reception continue normally If Automatic Data Mode is no selected no blocking mechanism is present User Manual 4 25 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI 4 2 1 3 Read Frames Read frames transmit the read request and optionally the read offset Local MLI Controller MLI Transmitter Ready Read access to transfer window x Offset Width Remote MLI Controller MLI Receiver Ready Pipe x initialized TPxAOFR AOFF TPxSTATR DW TRSTATR DVx TRSTATR RPx TCR NO 1 no
71. run detection Output frequency fp 6 25 to 250 MHz e 2bit input divider P divide by PDIV 1 Sbit feedback divider N multiply by NDIV 1 stability restrictions possible 4bit output divider K divide by KDIV 1 Bypass Mode e Prescaler Mode e Freerunning Mode Normal Mode Glitchless switching between Normal Mode and Prescaler Mode PLL Functional Description The PLL provides the system with a clock generated from one of the various potential clock sources 1 For P 1 otherwise multiplied by P User Manual 2 4 V 1 0 2005 11 STCU V 1 0 Cinfineon System and Control Unit SCU VCO Bypass Bypass P PDIV 1 N NDIV 1 K KDIV 1 Figure 2 2 PLL Block Diagram The PLL uses up to three dividers to manipulate the input frequency in a configurable way Each the three dividers can be bypassed in some way to define an operating mode Bypassing and K divider this defines the Bypass Mode Bypassing N divider this defines the Prescaler Mode Bypassing no divider this defines the Normal Mode Ignoring the P divider this defines the Freerunning Mode Normal Mode In Normal Mode the input clock fosc is divided by a factor multiplied by a factor N and then divided by a factor K So the output frequency is given by fosc 2 1 User Manual 2 5 V 1 0 2005 11 STCU V 1 0 Cinfineon System and Control Unit SCU The Normal is selected
72. the clock signal The baud rate shift clock can be set from 0 15 bit s up to 10 Mbit s 40 MHz module clock These features allow the SSC to be adapted to a wide range of applications that require serial data transfer Regardless of whether the MSB or the LSB is transmitted first the transfer data is always right aligned in registers SSC TB and SSC RB with the LSB of the transfer data in bit 0 of these registers The data bits are rearranged for transfer by the internal shift register logic The Clock Control allows the adaptation of the transmit and receive behavior of the SSC to a variety of serial interfaces A specific clock edge rising or falling is used to shift out transmit data while the other clock edge is used to latch in receive data Bit SSC CON PH selects the leading edge or the trailing edge for each function Bit SSC CON PO selects the level of the clock line in the idle state For an idle high clock the leading edge is a falling one 1 to 0 transition see Figure 5 6 Synchronous Serial Interface SSC Shift Clock SCLK if CON PO 0 CON PH 0 _ LJ LJ L __ Transmit Data CON PO 1 CON PH 1 nu E SSC Pins MTSR MRST First Last Bit 1 Latch Data Bit Shift Data 1 First MRST is replaced 0 in Slave Mode if CON PH 1 MCT04507a_mod
73. to be updated for the next DMA transaction a running DMA transaction for this channel must be finished After that source and destination address registers can be written before the next DMA transaction is started Figure 3 5 shows the actions that take place when a source address register is updated The update of a destination register happens in an equivalent manner When writing a new address to the address of the source or destination address register and no DMA transaction is running the new address value is directly written into the source or destination address register In this case no buffering of the address is required When writing a new address to the address of the source or destination address register and a DMA transaction is running no transfer to an address register can take place and SHADROn holds the new address value that was written For this User Manual 3 12 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller operation bit field ADRCR0n SHCT must be set either to 01 address is a source address 10 new address is a destination address At the start of the next transaction the shadow transfer takes place and the content of SHADROn is written either into SADROn or DADROn ADRCROn SHCT must be set accordingly After the shadow transfer SHADROn is set to 0000 0000 Therefore the software can check by reading the shadow address register whether or not the shadow transfe
74. triggered at the end of a transaction with IRDV 0 06157 Figure 3 10 Transaction Start by Software Continuation by Hardware 3 2 4 4 Channel Reset Operation A DMA transaction of DMA channel On can be stopped channel is reset by setting bit CHRSTR CHOn When CHRST CHOn is set to 1 Bits TRSR HTREOn TRSR CHOn ERRSR TRLOn INTSR ICHOn INTSR IPMOn WRPSR WRPDOn WRPSR WRPSOn CHSROn LXO and bit field CHSROn TCOUNT are reset e If ADRCROn SHCT is 01g or 10g either source or destination address register will be loaded with the value buffered in the shadow address register SHADROn is cleared SHADROn will be cleared afterwards User Manual 3 20 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller All automatic functions are stopped for channel On A user program should execute the following steps for resetting and restarting a DMA channel 1 Writing a 1 to CHRST CHOn 2 Waiting polling until CHRST CHOn 0 3 Optionally re configuring the address and other channel registers 4 Restarting the DMA channel by setting HTREQ ECHOn 1 for hardware requests or STREQ SCHOn 1 for software requests Bit field CHCROn TREL is copied to CHSROn TCOUNT when a new DMA transaction is requested User Manual 3 21 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller 3 2 4 5 Transfer Count and Move Count The move coun
75. 0 CFS CFS CFS CFS NFS NFS NFS NFS IE IE 1E3 IE2 IE1 IEO IE3 IE2 IE1 r rw rw rw rw rw rw rw rw rw rw Field Bits Description NFSIEO 0 rw Normal Frame Sent in Pipe x Interrupt Enable NFSIE1 1 0 Normal Frame sent in Pipe x interrupt source is NFSIE2 2 disabled NFSIE3 3 1 Normal Frame sent in Pipe x interrupt source is enabled CFSIEO 4 rw Command Frame Sent in Pipe x Interrupt Enable CFSIE1 5 0 Command Frame sent in Pipe x interrupt source is CFSIE2 6 disabled CFSIE3 7 1 Command Frame sent in Pipe x interrupt source is enabled PEIE 8 rw Parity Error Interrupt Enable 0 Parity error interrupt source is disabled 1 Parity error interrupt source is enabled TEIE 9 rw Time Out Error Interrupt Enable 0 Time out error interrupt source is disabled 1 Time out error interrupt source is enabled User Manual 4 83 V 1 0 2005 11 MLI V1 0 Cinfineon CIC751 Micro Link Interface MLI Field Bits Type Description NFSIRO 16 w Normal Frame Sent in Pipe x Flag Clear NFSIR1 17 0 No action NFSIR2 18 1 Clear MLI_TISR NFSIx NFSIR3 19 CFSIRO 20 w Command Frame Sent in Pipe x Flag Clear CFSIR1 21 0 No action CFSIR2 22 1 Clear MLI_TISR CFSIx CFSIR3 23 PEIR 24 w Parity or Time Out Error Flag Clear 0 No action 1 Clear MLI TISR PEIx TEIR 25 w Time Out Error Flag C
76. 0 RE RE RE RE RE RE 07 06 05 04 03 02 01 00 r rh rh rh rh rh rh rh rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 CH CH CH 07 06 05 04 03 02 01 00 r rh rh rh rh rh rh rh rh Field Bits Type Description CH0n n rh Transaction Request State of DMA Channel 0n n 0 7 0 No DMA request is pending for channel 0n 1 A DMA request is pending for channel 0n HTRE0n n 16 rh Hardware Transaction Request Enable State of DMA n 0 7 Channel 0n 0 Hardware transaction request for DMA Channel On is disabled An input DMA request will trigger the channel On 1 Hardware transaction request for DMA Channel On is enabled The transfers of a DMA transaction are controlled by the corresponding channel request line of the DMA requesting source HTREOn is set to 0 when CHSROn TCOUNT is decremented and CHSROn TCOUNT 0 HTREOn can be enabled and disabled with HTREQ ECHOn or HTREQ DCHOn 0 31 24 Reserved 15 8 Read as 0 should be written with 0 User Manual 3 31 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller The bits in the Software Transaction Request Register are used to generate a DMA transaction request by software DMA STREQ DMA Software Transaction Request Register 418 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 2 19 18 17 16 0 r 15
77. 1 0 31 9 r Reserved Read as 0 should be written with O User Manual 3 42 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller The Address Control Register controls how source and destination addresses are updated after a DMA move Furthermore it determines whether or not a source or destination address register update is shadowed ADRCROn 0 7 Channel Address Control Register 48C n 20 Reset Value 0000 0000 INE E NE EE RE NE NR NN w 0 SHCT r iW 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CBLD CBLS INCD DMF INCS SMF rw rw rw rw rw rw Field Bits Type Description SMF 2 0 rw Source Address Modification Factor This bit field and the data width as defined in CHCROn CHDW determine an address offset value by which the source address is modified after each DMA move See also Table 3 5 000 Address offset is 1 x CHCROn CHDW 001 55 offset is 2 x CHCROn CHDW 010 Address offset is 4 x CHCROn CHDW 011gAddress offset is 8 x CHCROn CHDW 100 Address offset is 16 x CHCROn CHDW 101 Address offset is 32 x CHCROn CHDW 110 Address offset is 64 x CHCROn CHDW 111 Address offset is 128 x CHCROn CHDW INCS 3 rw Increment of Source Address This bit determines whether the address offset as selected by SMF will be added to or subtracted from the source address after each DMA move The source addre
78. 1 2 MLI The Micro Link Interface MLI is a fast synchronous serial interface that makes it possible to exchange data between microcontrollers or other devices The key features of the MLI are e Synchronous serial communication between MLI transmitter an MLI receiver Different system clock speeds are supported in the MLI transmitter and MLI receiver due to full handshake protocol 4 lines between a transmitter and receiver Fully transparent read write access is supported remote programming Complete address range of target device Remote Controller is available Specific frame protocol to transfer commands addresses and data Error detection by parity bit 32 bit 16 bit or 8 bit data transfers are supported e Programmable baud rate fy 2 max fu fsvs Multiple receiving devices are supported 1 2 1 3 SSC The SSC supports full duplex and half duplex serial synchronous communication up to 10 Mbit s 40 MHz module clock The serial clock signal is received from an external master Slave Mode Data width shift direction clock polarity and phase are programmable This allows communication with SPl compatible devices Transmission and reception of data is double buffered A shift clock generator provides the SSC with a separate serial clock signal This section describes only the use of the SSC module as a slave because the CIC751 always operates as a slave to a host Features Slave M
79. 1 RREADY MLI ALT2 RDY SSC ALT3 Not used 6 Input RVALID MLI SLS SSC Output GPIO Port Output Register PO_OUT P6 ALT1 Not used ALT2 Not used ALT3 Not used P0 7 Input RDATA MLI MTSR SSC Output GPIO Port Output Register PO_OUT P7 ALT1 Not used ALT2 Not used ALT3 Not used 8 Input MODE SCU Output GPIO Port Output Register PO_OUT P8 ALT1 SR5 SCU ALT2 SR5 SCU ALT3 SR5 SCU 9 Input TESTMODE SCU Output GPIO Port Output Register PO OUT P9 ALT1 Not used ALT2 Not used ALT3 Not used User Manual 7 4 V 1 0 2005 11 Parallel Ports V1 0 1 751 Parallel Ports Table 7 1 Port 0 Input Output Functions cont d Port Select Connected Function From to Module Pin P0 10 Input SRO SCU Output GPIO Port Output Register PO_OUT P10 ALT1 SRO SCU ALT2 SRO SCU SR0 SCU P0 11 Input SR1 SCU Output GPIO Port Output Register PO_OUT P11 ALT1 5 1 SCU ALT2 SR1 SCU ALT3 SR1 SCU 0 12 Input SR2 SCU Output GPIO Port Output Register PO OUT P12 ALT1 SR2 SCU ALT2 SR2 SCU ALT3 SR2 SCU 7 1 4 Port 0 Register Description 7 1 41 Port 0 Control Register PO_IN Port 0 Input Register A244 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 15 14 13
80. 12 11 10 9 8 7 6 5 4 3 2 1 0 0 12 P11 10 P9 P8 P7 P6 P5 P2 PO r rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh User Manual 7 5 1 0 2005 11 Parallel Ports V1 0 Cinfineon Parallel Ports Field Bits Type Description Px x rwh Port 0 Input Bit x x 0 12 This bit indicates the level at the input pin of port PO pin x 0 The input level of PO x is 0 1 The input level of PO x is 1 0 31 13 r Reserved Read as 0 should be written with 0 PO OUT Port 0 Output Register A004 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 41 10 9 8 7 6 5 4 3 2 1 0 0 12 11 10 9 P8 P7 P6 P5 P3 P2 P1 r rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description Px x rwh Port Output Bit x x 0 12 This bit defines the level at the output pin of port 0 pin x if the output is selected as GPIO output 0 The output level of P0 x is 0 1 The output level of PO x is 1 0 31 13 r Reserved Read as 0 should be written with O User Manual 7 6 V 1 0 2005 11 Parallel Ports V1 0 Cinfineon Port 0 Output Modification Register A044 CIC751 Parallel Ports Reset Value 0000 0000
81. 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 SCH SCH SCH SCH SCH SCH SCH SCH 07 06 05 04 03 02 01 00 r w w w w w w w w Field Bits Type Description SCH0n n w Set Transaction Request for DMA Channel 0n n 0 7 0 No action 1 A transaction for DMA channel 0n is requested When setting SCH0n TRSR CH0n becomes set to indicate that a DMA request is pending for DMA channel 0n 0 31 8 Reserved Read as 0 should be written with 0 User Manual 3 32 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller The bits in the Hardware Transaction Request Register enable or disable DMA hardware requests DMA_HTREQ DMA Hardware Transaction Request Register 41C Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 DCH DCH DCH DCH DCH DCH DCH DCH 07 06 05 04 03 02 01 00 r w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 ECH ECH ECH 07 06 05 04 03 02 01 00 r w w w w w w w w Field Bits Type Description ECH0n n w Enable Hardware Transfer Request n 0 7 for DMA Channel see table below DCH0n n 16 w Disable Hardware Transfer Request n 0 7 for DMA Channel 0n see table below 0 31 24 Reserved 15 8 Read as 0 sh
82. 148 Page 6 32 Register RESB3 ADC Extended Result 3 View B 0000 114C Page 6 32 Register ADC_RESB4 ADC Extended Result 4 View B 0000 1150 Page 6 32 Register ADC_RESB5 ADC Extended Result 5 View B 0000 1154 6 32 Register RESB6 ADC Extended Result 6 View B 0000 1158 Page 6 32 Register ADC_RESB7 ADC Extended Result 7 View B 0000 115C Page 6 32 Register ADC_RESB8 ADC Extended Result 8 View B 0000 1160 Page 6 32 Register ADC_RESB9 ADC Extended Result 9 View B 0000 1164 Page 6 32 Register ADC_RESB10 ADC Extended Result 10 View B 0000 1168 Page 6 32 Register ADC_RESB11 ADC Extended Result 11 View 0000116C 6 32 Register User Manual 8 14 V 1 0 2005 11 Regs V1 0 Cinfineon Register Overview Table 8 7 ADC Registers cont d Register Short Register Long Name Address Description Name see ADC_RESB12 ADC Extended Result 12 View B 0000 1170 Page 6 32 Register ADC_RESB13 ADC Extended Result 13 View 0000 1174 Page 6 32 Register ADC_RESB14 ADC Extended Result 14 View 0000 1178 Page 6 32 Register ADC_RESB15 ADC Extended Result 15 View B 0000 117C 6 32 Register ADC_INRES ADC Input Result Register 0000 1180 Page 6 33 DBCTR ADC Doorbell Control Register 0000 1184 6 35 ADC RESV ADC Result Valid Register 0000 1188 6 34 Reserved Reserved 0000 118C l 0000 11FF 8 3 Memory Regist
83. 2 is used as source 011 Doorbell event 3 is used as source 100 ADC event 0 is used as source 101 ADC event 1 is used as source 110 Reserved do not use this combination 111 Reserved do not use this combination INV2 11 rw Invert Source for Event 2 0 The source is not inverted 1 The source is inverted User Manual STCU V 1 0 2 20 V 1 0 2005 11 Cinfineon System and Control Unit SCU Field Bits Type Description INSEL3 14 12 Input Selection for Event 3 000 No Event is generated 001 ADC event 2 is used as source 010 Doorbell event 2 is used as source 011 Doorbell event 3 is used as source 100 ADC event 0 is used as source 101 ADC event 1 is used as source 110 Reserved use this combination 111 Reserved do use this combination INV3 15 rw Invert Source for Event 3 0 The source is not inverted 1 The source is inverted 0 31 16 r Reserved Read as 0 should be written with User Manual 2 21 V 1 0 2005 11 STCU V 1 0 Cinfineon CIC751 SCU CHTRO System and Control Unit SCU SCU Channel Trigger 0 Register 830 Reset Value 0000 0000 SCU CHTR1 SCU Channel Trigger 1 Register 834 Reset Value 0000 0000 SCU CHTR2 SCU Channel Trigger 2 Register 838 Reset Value 0000 0000 SCU_CHTR3 SCU Channel Trigger 3 Register 83C Reset Value 0000 0000 SCU_CHTR4 SCU C
84. 2C DMA_MESR DMA Move Engine Status Register 0000 0430 Page 3 37 DMA_MEOR DMA Move Engine 0 Read 0000 0434 Page 3 38 Register Reserved Reserved 0000 0438 l Memory 0 Register 0000 043C User Manual 8 6 V 1 0 2005 11 Regs V1 0 Cinfineon CIC751 Register Overview Table 8 3 DMA Kernel Registers cont d Register Register Long Name Address Description Short Name see MEM DMA Memory 1 Register 00000440 l DMA 2 DMA Memory 2 Register 00000444 l DMA MEM3 DMA Memory 3 Register 0000 0448 Memory 4 Register 0000 044C l DMA_MEM5 DMA Memory 5 Register 0000 0450 l Reserved Reserved 0000 0454 l 0000 0464 14 Memory 14 Register 0000 0468 Reserved Reserved 0000 046C 0000 047C 5 00 Channel 0 Status Register 0000 0480 Page 3 42 0 DMA Channel 0 Control Register 00000484 3 39 MEM6 Memory 6 Register 0000 0488 ADRCROO Channel 0 Address Control 0000 048C Page 3 43 Register SADROO DMA Channel 0 Source Address 0000 0490 Page 3 47 DADROO Channel 0 Destination 0000 0494 3 36 Address Register DMA_SHADROO DMA Channel 0 Shadow Address 0000 0498 Page 3 49 Register DMA_CHSR01 DMA Channel 1 Status Re
85. 3 Overrun Error Interrupt Request MC_ADC0001_AUTOSCAN Figure 6 2 Auto Scan Conversion Mode Example 6 2 8 Wait for Read Mode If a previous conversion result has not been read out of the result register by the time a new conversion is complete the previous result is lost because it is overwritten by the new value and the error injection interrupt request trigger is generated User Manual 6 7 V 1 0 2005 11 ADC V1 0 Cinfineon The Analog Digital Converter In order to avoid error injection interrupts and the loss of conversion results especially when using Continuous Conversion Modes the ADC can be switched to Wait for Read Mode by setting bit ADC_CON ADWR or ADC_CTRO ADWR If the result value has not been read by the time the current conversion is completed the new result is stored in a temporary buffer and the next conversion is suspended ADST ADC_CON ADBSY or ADC_CTRO ADBSY will remain set in the meantime but no interrupt will be generated After reading the previous value the temporary buffer is copied into ADC_DAT generating an interrupt and the suspended conversion is started This mechanism applies to both single and Continuous Conversion Modes Note In Standard Mode continuous conversions are executed at a fixed rate determined by the conversion time but in Wait for Read Mode there may be delays due to suspended conversions cov O OOOO T T of Channel Write ADC_DAT A
86. 4 Reset Value 0000 0000 MLI TP1AOFR MLI Transmitter Pipe 1 Address Offset Reg 2344 Reset Value 0000 0000 MLI TP2AOFR MLI Transmitter Pipe 2 Address Offset Reg 238 Reset Value 0000 0000 MLI TP3AOFR MLI Transmitter Pipe Address Offset Reg 23C Reset Value 0000 0000 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AOFF r Field Bits Type Description AOFF 15 0 rh Address Offset Whenever a location within a Transfer Window is accessed read or written AOFF is loaded with the lowest 16 address bits of the access Also in the case of a small Transfer Window access all AOFF bits are loaded but AOFF 15 13 are not taken into account for further actions 0 31 16 r Reserved Read as 0 should be written with 0 User Manual 4 70 V 1 0 2005 11 MLI V1 0 Cinfineon CIC751 Micro Link Interface MLI 4 3 2 7 Transmitter Pipe x Data Register The Transmitter Pipe x Data Register TPxDATAR x 0 3 is a read only register that stores the data that has been written during the last write access to a Transfer Window of Pipe x MLI TPODATAR MLI Transmitter Pipe 0 Data Register 2404 Reset Value 0000 0000 MLI TP1DATAR MLI Transmitter Pipe 1 Data Register 2444 Reset Value 0000 0000 MLI TP2DATAR MLI Transmitter Pipe 2 Data Register 248 Reset Value 0000 0000 MLI Transmitter Pipe 3 Data Register 24C Reset Val
87. 4 34 Bit PE can be cleared via bit MLI_SCR CTPE NAE rh Non Acknowledge Error Flag This bit is set when a non acknowledge error condition is detected by the MLI transmitter after a frame transmission see Page 4 37 NAE is cleared by hardware if a transmitted frame has been acknowledged correctly Bit NAE can be cleared via bit MLI_SCR CNAE 31 9 Reserved Read as 0 should be written with 0 User Manual MLI V1 0 4 63 V 1 0 2005 11 Cinfineon CIC751 Micro Link Interface MLI 4 3 2 3 Transmitter Pipe x Status Registers The Transmitter Pipe x Status Registers MLI TPxSTATR contain Pipe specific status information related to address optimization and prediction data width for transmit data and Remote Window size MLI TPOSTATR MLI Transmitter Pipe 0 Status Register 218 Reset Value 0000 0000 MLI TP1STATR MLI Transmitter Pipe 1 Status Register 21 Reset Value 0000 0000 MLI TP2STATR MLI Transmitter Pipe 2 Status Register 2204 Reset Value 0000 0000 MLI TP3STATR MLI Transmitter Pipe 3 Status Register 2244 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 OP 15 14 13 12 r rh 10 9 8 7 6 5 4 3 2 1 0 Field Bits Description BS 9 0 Size This bit field indicates the coded size of the Pipe x Remote Window in the Remote Controller BS furthe
88. 6 45 8 06 3 13 4 69 6 25 7 81 1 Values this range are allowed in Freerunning Mode but have no impact there User Manual STCU V 1 0 2 8 V 1 0 2005 11 Cinfineon System and Control Unit SCU Note Of course the entire range between two fvco columns in the above table is allowed N divider output frequency fy is then compared with face in the phase detector logic which is within the VCO logic The phase detector determines the difference between the two clock signals and accordingly controls the output frequency of the VCO Jvco Note Due to this operation the VCO clock of the PLL has a frequency that is a multiple feer The factor for this is controlled through the value applied to the N divider in the feedback path For this reason this factor is often called a multiplier although it actually controls division The output frequency of the VCO fyco is divided by K to provide the final desired output frequency fp Table 2 4 lists the output frequency range depending on the K divisor and the VCO frequency range Table 2 4 K Divisor Table K2 Seu for fvco Duty Cycle K2DIV 1 DIV 100 150 200 250 1 0 100 0 150 0 200 0 250 0 45 55 2 1 50 0 75 0 100 0 125 0 50 3 2 33 3 50 0 66 6 83 3 33 4 3 25 0 37 5 50 0 62 5 50 5 4 20 0 30 0 40 0 50 0 40 6 14 5 13 15 14 6 6 10 0 13 8 16 6 46 6 16 15 6 25 9 38 12 5 18 75 50
89. 8 Port 0 Input Output Control 0000 0418 7 10 Register 8 PO IOCR12 Port 0 Input Output Control 0000 0A1C 7 11 Register 12 Reserved Reserved 00000A20 l PO IN Port 0 Input Register 00000A24 7 5 Reserved Reserved 0000 0A28 _ l 0000 0 60 P1 Port 1 Input Register 00000A64 Page 7 15 Reserved Reserved 0000 0 68 0000 OAFF Table 8 7 ADC Registers Register Short Register Long Name Address Description Name see Reserved Reserved 0000 1000 0000 100E ADC_CON ADC Control Register 0000 1010 Page 6 21 1 ADC Control 1 Register 0000 1012 Page 6 23 Reserved Reserved 0000 1014 0000 101E ADC_CTR2 ADC Control 2 Register 0000 1020 Page 6 25 User Manual 8 12 V 1 0 2005 11 Regs V1 0 Cinfineon Table 8 7 CIC751 ADC Registers cont d Register Overview Register Short Register Long Name Address Description Name see ADC CTR2IN ADC Injection Control 2 Register 0000 1022 Page 6 26 ADC CTRO ADC Control 0 Register 0000 1024 Page 6 24 Reserved Reserved 0000 1026 0000 101E ADC DAT ADC Result Register 0000 1030 Page 6 27 ADC DAT2 ADC Result 2 Register 0000 1032 Page 6 27 Reserved Reserved 0000 1034 0000 10FE 5 0 ADC Extended Result 0 View A 0000 1100 Page 6 30 Register ADC RESA1 ADC Extended Result 1 View A 0000 1104 Page 6 30 Register ADC RESA2 ADC Extended Resul
90. 8 bit Pipe x Remote Window base address of the latest write access to TPOBAR ADDR MLI TCBAR MLI Transmitter Copy Base Address Register 644 Reset Value 0000 0000 31 30 S NE NE SUME UM 18 17 1 ADDR 31 16 15 14 pow u om 7 6 5 4 3 2 1 0 ADDR 15 4 0 rh r Field Bits Type Description ADDR 31 4 rh Address This bit field contains the 28 address bits written to MLI_TPOBAR ADDR This value will be transferred to the Remote Controller to define the base address of the Remote Window for Pipe x Reserved 0 3 0 Read as 0 should be written with 0 User Manual 4 74 MLI V1 0 V 1 0 2005 11 Cinfineon Micro Link Interface MLI 4 3 3 MLI Receiver Registers 4 3 3 1 Receiver Control Register Receiver Control Register MLI_RCR contains control and status bits bit fields that are related to the MLI receiver operation MLI_RCR MLI Receiver Control Register 2681 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 RST 0 BEN MPE T rw T rw rwh RPN PE TF DW MOD CMDP3 DPE rh rh rh rh rh rh rh Field Bits Type Description DPE 9 0 rh Delay for Parity Error DPE determines the number of RCLK clock periods that the MLI receiver waits before the RREADY signal is raised again when it has dete
91. ADDR RPxBAR ADDR RADRR ADDR RPxSTATR AP RREADY 1 lt RDATAR DATA Data TRSTATR DVx RCR DW i Received data 0 TISR NFSIx 1 RCR TF RIER NFRI Normal Frame Sent x Interrupt Normal Frame Received Interrupt Write Data to Remote Window see separate figure MCA05890 M Figure 4 17 Write Frame Transaction Flow User Manual 4 22 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI Local Controller In the Local Controller a write operation to a Transfer Window address defines the address the data and the data size and triggers the following actions in the MLI transmitter The 16 least significant address bits of the Transfer Window write access are stored in MLI TPXAOFR AOFF x 0 3 as write offset address The data of the write access is stored x 0 3 The data width of the Transfer Window write access 8 bit 16 bit or 32 bit is stored in bit field MLI TPXSTATR DW x 0 3 Status flag MLI TRSTATR DVx is set indicating that the Pipe contains valid data for transmission If the address prediction is disabled MLI_TCR NO 1 the transmission of a Write Offset and Data Frame is started as soon as the MLI transmitter is idle If the address prediction is enabled MLI_TCR NO 0 a Write Offset and Data Frame is started only if an address prediction is not possible indicated by MLI TPO
92. CTR2IN Bit field ADCTC conversion time control selects the basic conversion clock fac used for the operation of the A D Converter The sample time is derived from this conversion clock and is controlled by bit field ADC_CTR2 ADSTC The sample time is always a multiple of 4 fac periods Table 6 4 lists the possible combinations Table 6 4 Improved Conversion and Sample Timing Control ADCTC A D Converter ADSTC Sample Time ts Basic Clock fg 00 0000 00 foys 1 00 0000 00 tac X 8 0000015201 2 00 0001 01 fgc x 12 0000105202 1 4 3 00 0010 02 tac 16 T Jsys ADCTC 1 5 fgc X 4 x ADSTC 2 1111115 2 3F 64 111111 tac X 260 User Manual 6 13 V 1 0 2005 11 ADC V1 0 Cinfineon The Analog Digital Converter 1 The limit values for fac see data sheet must not be exceeded when selecting ADC_CTR2 ADCTC fsys Total Conversion Time Examples The time for a complete conversion includes the sample time fs the conversion itself successive approximation and calibration and the time required to transfer the digital value to the result register as shown in the example below Standard Conversion timing The timings refer to module clock cycles where 1 foys e Assumptions fsys 40 MHz 25 ns ADC_CON ADCTC 015 ADC_CON ADSTC 00 e Sample time ts x 8 400 ns Conversion 10 bit With post calibr
93. CU Registers cont d Register Short Register Long Name Address Description Name see IDCHIP Chip Identification Register 0000 0860 Page 2 24 Reserved Reserved 0000 0864 0000 08FF Table 8 5 SSC Registers Register Short Register Long Name Address Description Name see Reserved Reserved 00000900 l 0000 090C SSC CON SSC Control Register 0000 0910 Page 5 15 SSC BR SSC Baud Rate Timer Reload 0000 0914 Page 5 22 Register Reserved Reserved 0000 0918 0000 091C SSC TB SSC Transmit Buffer Register 0000 0920 Page 5 21 55 SSC Receive Buffer Register 0000 0924 5 22 55 5 SSC Status Register 0000 0928 Page 5 18 SSC_EFM SSC Error Flag Modification 0000 092 Page 5 19 Register Reserved Reserved 00000930 l 0000 O9FF Table 8 6 Port Registers Register Short Register Long Name Address Description Name see P0_OUT Port 0 Output Register 0000 0 00 7 6 PO Port 0 Output Modification Register 0000 0A04 7 7 User Manual 8 11 V 1 0 2005 11 Regs V1 0 Cinfineon CIC751 Register Overview Table 8 6 Port Registers cont d Register Short Register Long Name Address Description Name see Reserved Reserved 0000 0 08 l 0000 0A0C Port 0 Input Output Control 0000 0A10 Page 7 8 Register 0 P0_IOCR4 Port 0 Input Output Control 0000 0 14 7 9 Register 4 P0_IOCR
94. DC V1 0 Cinfineon CIC751 The Analog Digital Converter Field Bits Type Description RESULT 11 0 rh Conversion Result This bit field represents the conversion result for the selected channel If the conversion result is smaller than 10 bits the result always starts with its MSB at bit position 11 and the unused bit positions are filled with 0 CHNR 15 12 Channel Number This bit field indicates the channel number 0 31 16 r Reserved Read as 0 should be written with 0 User Manual 6 31 V 1 0 2005 11 ADC V1 0 Cinfineon CIC751 ADC RESBO The Analog Digital Converter ADC Extended Result 0 View B Register 140 Reset Value 0000 0000 ADC_RESB1 ADC Extended Result 1 View B Register 144 Reset Value 0000 0000 ADC_RESB2 ADC Extended Result 2 View Register 148 Reset Value 0000 0000 ADC_RESB3 ADC Extended Result 3 View Register 14C Reset Value 0000 0000 ADC Extended Result 4 View Register 150 Reset Value 0000 0000 ADC_RESB5 ADC Extended Result 5 View Register 154 Reset Value 0000 0000 ADC_RESB6 ADC Extended Result 6 View B Register 158 Reset Value 0000 0000 ADC_RESB7 ADC Extended Result 7 View Register 15C Reset Value 0000 0000 ADC_RESB8 ADC Extended Result 8 View B Register 160 Reset Value 0000 0000 ADC_RESB9 ADC Extended Result 9 View Register 164
95. DC CTRO ADCH may be changed ADC_CON ADM or ADC CTRO ADM will be evaluated after the current conversion CON ADCH or ADC CTRO ADCH will be evaluated after the current conversion Fixed Channel Modes or after the current conversion sequence Auto Scan Modes User Manual 6 5 V 1 0 2005 11 ADC V1 0 Cinfineon The Analog Digital Converter 6 2 5 Conversion Resolution Control The ADC can produce either 10 bit result ADC_CON1 RES 0 2 5 00 or 8 bit result ADC_CON1 RES 1 or CTR2 RES 201g Depending on the application s requirements higher conversion speed an 8 bit conversion requires less conversion time or a higher resolution can be chosen 6 2 5 1 Conversion Result The result of a conversion is stored in the result register ADC_DAT or in register ADC DAT for an injected conversion The position of the result depends on the basic operating mode compatibility or enhanced and on the selected resolution 8 bit or 10 bit Note Bit field CHNR of register ADC DAT is loaded by the ADC to indicate the channel to which the result refers Bit field of register DAT is loaded by software to select the analog channel which is to be injected 6 2 6 Fixed Channel Conversion Modes These modes are selected by programming the mode selection bit field CON ADM or ADC_CTRO ADM to 00 single conversion or to 01 continuous conversion After starting the c
96. DC_DAT Full Temp Latch Full Generate Interrupt equest lt Hold Result in Temp Latch Read of ADC_DAT Result of Channel 3 2 1 0 MC_ADC0002_WAITREAD Figure 6 3 Wait for Read Mode Example 6 2 9 Channel Injection Mode Channel Injection Mode allows the conversion of a specific analog channel also while the ADC is running in a Continuous or Auto Scan Mode without changing the current operating mode After the conversion of this specific channel the ADC continues with the original operating mode Channel Injection Mode is enabled by setting bit ADC CON ADCIN or ADC_CTRO0 ADCIN and requires the Wait for Read Mode ADC_CON ADWR 1 or ADC_CTRO ADWR 1 The channel to be converted in this mode is specified in bit field CHNR of register ADC_DAT2 User Manual 6 8 V 1 0 2005 11 ADC V1 0 Cinfineon The Analog Digital Converter Note Since the channel number for an injected conversion is not buffered bit field CHNR of ADC_DAT2 must never be modified during the sample phase of an injected conversion otherwise the input multiplexer will switch to the new channel It is recommended to change the channel number only when injected conversion is running x1 x 2 x 3 x 4 Conversion of Channel Y Write ADC DAT x 1 x 1 x 2 3 x 4 ADC_DAT Full P L Tl 7701 T1 r1 Read ADC_DAT x 1 x 2 3 x 4 Injected Channel Injection d Conver
97. DMA_CHCR4 PRSEL 100 Set Trigger Flag Request DMA_CHCR4 PRSEL 101 not used no Request DMA_CHCR4 PRSEL 110 DMA_CHCR4 PRSEL 111 5 Channel 4 Request DMA_CHCR5 PRSEL 000 Channel 3 Request DMA_CHCR5 PRSEL 001 MLI Request 2 DMA_CHCR5 PRSEL 010 MLI Request 3 DMA_CHCR5 PRSEL 011 Trigger AND Ready Request CHCR5 PRSEL 100 Set Trigger Flag Request CHCR5 PRSEL 101 not used no Request DMA CHCR5 PRSEL 110 DMA_CHCR5 PRSEL 1115 6 Channel 5 Request DMA_CHCR6 PRSEL 000 Channel 4 Request DMA CHCR6 PRSEL 001 MLI Request 2 DMA_CHCR6 PRSEL 010 MLI Request 3 DMA_CHCR6 PRSEL 011 Trigger AND Ready Request DMA_CHCR6 PRSEL 100 Set Trigger Flag Request DMA_CHCR6 PRSEL 101 not used no Request DMA_CHCR6 PRSEL 110 DMA_CHCR6 PRSEL 111 User Manual 3 6 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller Table 3 1 DMA Request Assignment cont d DMA DMA Request Input Selected by Channel 7 Channel 6 Request DMA_CHCR7 PRSEL 000 Channel 5 Request DMA_CHCR7 PRSEL 001 MLI Request 2 DMA_CHCR7 PRSEL 010 MLI Request 3 DMA_CHCR7 PRSEL 011 Trigger AND Ready Request DMA CHCR7 PRSEL 100 Set Trigger Flag Request DMA CHCR7 PRSEL 101 not used no Request CHCR7 PRSEL 110 DMA_CHCR7 PRSEL 111 Note Not all channel are connected to the exactly same direct channel Request User Manual 3 7 V 1 0 2005 11 DMA V1 0 C
98. DRCR0n Parameters ADRCROn Parameters SMF 0115 DMF 010 INCS 1 INCD 0 06159 Figure 3 12 Programmable Address Modification Example 1 In Figure 3 12 16 bit half words are transferred from a source memory with an incrementing source address offset of 10 to a destination memory with decrementing destination addresses offset of 08 In Figure 3 13 16 bit half words are transferred from a source memory with an incrementing source address offset of 02 to a destination memory with incrementing destination addresses offset of 04 User Manual 3 23 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller Source Memory Destination Memory 31 16 15 0 31 16 15 Moves ADRCROn Parameters ADRCROn Parameters SMF 000 DMF 001 INCS 1 INCD 1 MCA06160 Figure 3 13 Programmable Address Modification Example 2 3 2 4 6 Circular Buffer Destination and source address can be configured to build a circular buffer separately for source and destination data Within this circular buffer addresses are updated as defined in Figure 3 12 and Figure 3 13 with a wrap around at the buffer limits The circular buffer length is determined by bit fields ADRCROn CBLS for the source buffer and ADRCROn CBLD for the destination buffer These 4 bit wide bit fields determine which bits of the 32 bit address remain unchanged at an address update Possible buffer sizes of the ci
99. FRI3 5 received in Pipe x The MLI Request that is activated is defined by MLI_RINPR CFRIP User Manual 4 90 V 1 0 2005 11 MLI V1 0 Cinfineon CIC751 Micro Link Interface MLI Field Bits Type Description IC 6 rh Interrupt Command Flag This flag is set when a Command Frame has been received in Pipe 0 leading to an activation of one of the MLI Requests The MLI Request that is activated is defined by the received command CMD PEI 7 rh Parity Error Interrupt Flag This flag is set when a parity error interrupt event has occurred The MLI Request that is activated is defined by MLI_RINPR MPPEIP DRAI 9 rh Discarded Read Answer Interrupt Flag This flag is set when the discarded read answer interrupt event has occurred This condition occurs if an Answer Frame is received while none of the MLI_TRSTATR RPx bits is set the Answer Frame was not expected The MLI Request that is activated is defined by MLI_RINPR DRAIP 0 8 r Reserved 31 10 Read as 0 should be written with 0 User Manual 4 91 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI 4 3 5 3 Receiver Interrupt Node Pointer Register The Receiver Interrupt Node Pointer Register MLI RINPR contains the interrupt node pointers for the MLI receiver interrupts MLI_RINPR MLI Receiver Interrupt Node Pointer Register 2AC Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
100. I RADRR In case of a Write Offset and Data Frame or a Discrete Read Frame the receiver address registers MLI RADRR MLI RPxBAR are always updated with an address This address is calculated by replacing the offset bit positions in MLI RPxBAR with the received offset value In this case the address delta value stored in MLL RPxSTATR AP is not taken into account The programmed size of the Remote Window and the number of offset bits are given by MLI RPxSTATR BS The non offset bit positions in register MLI RPxBAR are kept constant whereas the offset bit positions are replaced 4 2 2 4 Automatic Data Mode The MLI module supports automatic data transfer for read or write frames in the Remote Controller The Automatic Data Mode in the Remote Controller can be enabled either via setting bit MLI RCR MOD or by a Command Frame sent by the Local Controller The Automatic Data Mode in the Remote Controller can be disabled by clearing bit RCR MCOD If the Automatic Data Mode is disabled the DMA has to execute the requested data transfers Note For the CIC751 the Automatic Data Mode should also be used 4 2 2 5 Transmit Priority In the case that several requests for frame transmission are pending at the same time in the MLI transmitter of the Local Controller the following priority scheme is applied starting with the highest priority e Answer Frame Software driven Command Frames 0 before CCV1 before CCV2 before CCV3 Re
101. MA DMA Request Input Selected by Channel 1 Channel 0 Request DMA_CHCR1 PRSEL 000 Channel 7 Request DMA_CHCR1 PRSEL 001 MLI Request 2 DMA_CHCR1 PRSEL 010 MLI Request 3 DMA_CHCR1 PRSEL 011 Trigger AND Ready Request DMA_CHCR1 PRSEL 100 Set Trigger Flag Request DMA_CHCR1 PRSEL 101 not used no Request DMA_CHCR1 PRSEL 110 DMA_CHCR1 PRSEL 111 2 Channel 1 Request DMA_CHCR2 PRSEL 000 Channel 0 Request DMA_CHCR2 PRSEL 001 MLI Request 2 DMA_CHCR2 PRSEL 010 MLI Request 3 DMA_CHCR2 PRSEL 011 Trigger AND Ready Request DMA_CHCR2 PRSEL 100 Set Trigger Flag Request DMA_CHCR2 PRSEL 101 not used no Request DMA_CHCR2 PRSEL 110 DMA_CHCR2 PRSEL 1115 3 Channel 2 Request DMA_CHCR3 PRSEL 000 Channel 1 Request DMA_CHCR3 PRSEL 001 MLI Request 2 DMA_CHCR3 PRSEL 010 MLI Request 3 DMA_CHCR3 PRSEL 011 Trigger AND Ready Request DMA_CHCR3 PRSEL 100 Set Trigger Flag Request DMA_CHCR3 PRSEL 101 not used no Request DMA_CHCR3 PRSEL 110 DMA_CHCR3 PRSEL 1115 User Manual 3 5 V 1 0 2005 11 DMA V1 0 Cinfineon CIC751 Direct Memory Access Controller Table 3 1 DMA Request Assignment cont d DMA DMA Request Input Selected by Channel 4 Channel 3 Request DMA_CHCR4 PRSEL 000 Channel 2 Request DMA_CHCR4 PRSEL 001 MLI Request 2 DMA_CHCR4 PRSEL 010 MLI Request 3 DMA_CHCR4 PRSEL 011 Trigger AND Ready Request
102. MLI operations MLI TRSTATR MLI Transmitter Receiver Status Register 22 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 RP2 RPO DV3 DV2 DV1 DVO r rh rh rh rh rh rh rh rh rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 BAV AV CV3 CV2 CV1 CVO 0 r rh rh rh rh rh rh r Field Bits Type Description CVO 4 rh Command Valid CV1 5 Bit is set when TCMDR CMDPXx bit field is CV2 6 written It is cleared when the Command Frame has 7 been correctly transmitted CVx be set cleared via bits SCR SCVx MLI_SCR CCVx AV 8 rh Answer Valid Bit is set when the MLI TDRAR register in the MLI transmitter in the Remote Controller is written AV is cleared when the Answer Frame has been correctly sent AV can be cleared via bit MLI SCR CAV BAV 9 rh Base Address Valid Bit is set when the MLI TCBAR register in the MLI transmitter is written BAV is cleared when the Copy Base Address Frame has been correctly sent BAV can be cleared via bit MLI SCR CBAV DVO 16 rh Data Valid DV1 17 Bit is set when the MLI TPODATAR and or the DV2 18 MLI TPOAOFR registers of the MLI transmitter are DV3 19 updated after an access to a Transfer Window of Pipe x DVx is cleared again when the read or write frame has been correctly sent DVx can be cleared via
103. R COMP1 e Doorbell event 2 that monitors the valid bit ADC_RESBn V of the result register selected e Doorbell event that monitors the valid bit ADC_RESBn V of the result register selected e MLI Request 0 of the MLI module e MLI Request 1 of the MLI module MLI Request 2 of the MLI module MLI Request 3 of the MLI module External trigger Input 0 External trigger Input 1 2 5 2 External Trigger Inputs The device supports external trigger sources to start ADC conversions or DMA transfers The device has several input pins SRO 2 for MLI Mode and SRO 4 for SSC Mode capable of delivering a trigger input signal User Manual 2 11 V 1 0 2005 11 STCU V 1 0 Cinfineon SIE System and Control Unit SCU External Trigger Control x X 2 0 1 SCU INSELx SCU SCU FENx Edge Detection Trigger external triggers Figure 2 5 External Triggers The rising edge and falling edge sensitivity of the selected input can be enabled individually If both edge detections are enabled an external trigger event is generated upon each change of the signal level rising edge or falling edge The external trigger control register ETCTR contains the bits defining the behavior of the external trigger inputs 2 5 3 Event Output Structure The CIC751 allows output of internal status or notification events on output pins In order to support different a
104. REQI0 CHOn_REQI1 Transfer CHOn REQI2 oe CHOn_REQI3 Channel CH0n_REQI4 Arbiter CH0n_REQI5 CH0n_REQI6 Transfer CHOn_REQI7 End of Transaction Transfer Set CHCR0n CHCROn CHRSTR ERRSR 06154 Figure3 7 Channel Request Control Two different types of DMA requests are possible Hardware DMA requests Software DMA requests The hardware request CH0n_REQ can be connected to one of eight possible hardware request input lines as selected by bit field CHCR0n PRSEL Hardware requests are enabled disabled by status bit TRSR HTREOn HTREOn be set reset by software by hardware in Single Mode at the end of a DMA transaction A software request can be generated by setting bit STREQ CHOn Status flag TRSR CHOn indicates whether or not a software or hardware generated DMA request for DMA channel On is pending TRSR CHOn can be reset by software or by User Manual 3 15 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller hardware at the end of a DMA transfer RROAT 0 or at the end of a DMA transaction RROAT 1 If a software or a hardware DMA request is detected for channel 0n while TRSR CH0n is set a request lost event occurs This error event indicates that the DMA is already processing a transfer and that another transfer has been requested before the end of the previous one In this case bit ERRSR TRLOn will be set 3 2 4 3 Channel Operation Mo
105. Receiver Pipe 1 Base Address Register 270 MLI RP2BAR MLI Receiver Pipe 2 Base Address Register 2744 MLI RP3BAR MLI Receiver Pipe Base Address Register 2784 CIC751 Micro Link Interface MLI Receiver Pipe x Base Address Register Reset Value 0000 0000 Reset Value 0000 0000 Reset Value 0000 0000 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 31 16 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR 15 0 ho Field Bits Type Description ADDR 31 0 rh Address ADDR indicates the complete target address for the Pipe x Remote Window If a Pipe x Copy Base Address Frame is received ADDR 31 4 becomes loaded with the transmitted 28 bit address and bits 3 0 are cleared If a write or read frame with m bits of address offset is received bits ADDR 31 m are held constant and bits ADDR m 1 0 are replaced by the received offset If an optimized read or data frame is received the address prediction mechanism adds the predicted address offset MLL RPxSTATR AP to ADDR and stores the result in ADDR If an Answer Frame is received ADDR is not changed User Manual 4 78 V 1 0 2005 11 MLI V1 0 1 751 4 3 3 3 Micro Link Interface MLI Receiver Pipe x Status Register The Receiver Pipe x Status Register MLI RPxSTATR x 0 3 indicates the data width 8 16 or 32 bit of the last access to the Pipe x Remote Window and the addre
106. SADR 31 0 is not updated 0001 Source address SADR 31 1 is not updated 0010 Source address SADR 31 2 is not updated 0011 Source address SADR 31 3 is not updated 1110 Source address SADR 31 14 is not updated 1111 Source address SADR 31 15 is not updated User Manual 3 44 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller Field Bits Type Description CBLD 15 12 rw Circular Buffer Length Destination This bit field determines which part of the 32 bit destination address register remains unchanged and is not updated after a DMA move operation see also Page 3 24 Therefore CBLD also determines the size of the circular destination buffer 0000 Destination address DADR 31 0 is not updated 0001 Destination address DADR 31 1 is not updated 0010 Destination address DADR 31 2 is not updated 0011 Destination address DADR 31 3 is not updated 1110 Destination address DADR 31 14 is not updated 1111 Destination address DADR 31 15 is not updated SHCT 17 16 rw Shadow Control This bit field determines whether an address is transferred into the shadow address register when writing to source or destination address register 00 Shadow address register not used Source and destination address register are written directly 01 Shadow address register used for source address buffering When writing to SADROn the address is buffered in SHADROn and transferred to SADROn wit
107. STATR OP 0 If MLI TPOSTATR OP 1 an address prediction is possible in the MLI transmitter and an Optimized Write Frame is started The address prediction is described in Chapter 4 2 2 3 Status flag TRSTATR DVXx is cleared after the Write Offset and Data Frame or the Optimized Write Frame has been finished and correctly acknowledged by the MLI receiver of the Remote Controller Interrupt status flag MLI_TISR NFSIx is set and an MLI Request is generated if enabled MLI_TIER NFSIEx 1 The number of offset address bits that are transmitted at a Write Offset and Data Frame is determined by the size of the Remote Window that has been previously initialized by the transmission of a Copy Base Address Frame Remote Controller After a data frame has been received correctly and acknowledged the following actions are executed in the MLI receiver of the Remote Controller In the case of a Write Offset and Data Frame The result of the internal address prediction is not taken into account The received offset address is added to the base address the x Transfer Window and the result is stored MLI RPXBAR ADDR x 0 3 MLI RADRR ADDR In the case of an Optimized Write Frame The result of the internal address prediction is taken into account The next address in the Remote Controller to that data are written is calculated by adding the detected receiver address prediction value RPxSTATR AP x 0 3 to the ac
108. TDATA MRST RCLK RREADY RDY P0 Port Control RVALID SLS RDATA MTSR MODE SR5 TESTMODE SRO SR1 SR2 PORST VAREF VAGND AINO Figure 1 2 Pins for P PG TSSOP 38 Package User Manual 1 8 V 1 0 2005 11 Introduction V 1 0 Cinfineon Introduction AIN4 17 fas AIN3 AIN5 2 37 AIN2 AIN10 5 36 AIN1 AIN11 4 ras AINO AIN8 5 4 VDDM AIN9 VDDP AING 2 VSS AIN7 31 PORST VAREF SR2 VAGND 29 SR1 AIN12 11 28 SRO AIN13 12 TESTMODE AIN14 MODE AIN15 4 25 RDATA MTSR vss 5 24 RVALID SLS VDDC 23 RREADY RDY TCLK SR3 17 22 RCLK VDDP TDATA MRST TREADY SRA 19 20 TVALID SCLK PACKAGE 38 Figure 1 3 Pin Numbering for P PG TSSOP 38 Package User Manual 1 9 V 1 0 2005 11 Introduction V 1 0 Cinfineon System and Control Unit SCU 2 System and Control Unit SCU The System and Control Unit SCU controls all system relevant tasks The system tasks of the SCU are e Reset operation see Chapter 2 1 System clock control see Chapter 2 3 Power supply system see Chapter 2 4 System Interrupt control see Chapter 2 5 2 1 Reset Control Block The single system reset function initializes the CIC751 into a defined default state and is invoked by any of the following trigger conditions External PORST reset Power on reset indicated by hardware reset input after pow
109. User Manual V 1 0 Nov 2005 CIG751 Companion IC Microcontrollers Cfineon Never stop thinking Edition 2005 11 Published by Infineon Technologies AG St Martin Strasse 53 81669 M nchen Germany Infineon Technologies AG 2005 Rights Reserved Attention please The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics Terms of delivery and rights to technical change reserved We hereby disclaim any and all warranties including but not limited to warranties of non infringement regarding circuits descriptions and charts stated herein Information For further information on technology delivery terms and conditions and prices please contact your nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Infineon Technologies Office Infineon Technologies Components may only be used in life support devices or systems with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect
110. _MEM7 DMA Memory 7 Register 0000 04A8 DMA_MEM8 DMA Memory 8 Register 0000 04 8 DMA 9 DMA Memory 9 Register 0000 04E8 l DMA MEM 10 DMA Memory 10 Register 0000 0508 MEM 1 DMA Memory 11 Register 0000 0528 12 Memory 12 Register 0000 0548 Memory 13 Register 0000 0568 Table 8 10 8 Bit Memory Registers Register Register Long Name Address Description Short Name see 14 DMA Memory 14 Register 0000 0468 l User Manual 8 16 V 1 0 2005 11 Regs V1 0 Cinfineon CIC751 Keyword Index A ADC 6 1 Address map of segment 15 8 1 Analog Digital Converter 6 1 C Calibration 6 1 1 Clock System 2 2 Oscillator run detection 2 9 Clock system PLL see PLL Control reset 2 1 Conversion analog digital 6 1 timing control 6 12 D DMA 3 8 Block diagram 3 8 Channel operation 3 12 Channel operation modes 3 16 Channel request control 3 15 Channel reset operation 3 20 Circular buffer 3 24 Definition of terms 3 10 Features 3 9 Principle 3 2 Transaction control 3 25 M MLI Communication principles 4 3 Frames Answer frame 4 14 Command frame 4 13 Copy base address frame 4 8 Optimized read frame 4 12 Optimized write frame 4 10 Write offset and data frame 4 9 User Manual Keyword Index Interrupts Receiver interrupts 4 43 Transmitter interrupts 4 41 Kernel registers 4 47 MLI Specific Terms 4 2 Registers Overview 4 47 T
111. abled The internal resistance to ground is in the range of 300 Ohm 10 The Multiplexer Test Mode is enabled The internal resistance to ground is in the range of 70 Ohm 11 Reserved like 00 3 2 Reserved Should be written with 1 15 8 Reserved Read as 0 should be written with O User Manual STCU V 1 0 2 17 V 1 0 2005 11 Cinfineon CIC751 System and Control Unit SCU 1 Please refer to the ACDC chapter for the current capability of the grounding resistor especially when using RC input filters at the analog inputs SCU ETCTR SCU External Trigger Control Register 850 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RENTEN 0 INSEL1 RENFEN 0 INSEL0 1 1 0 0 rw rw r rw rw rw r rw Field Bits Type Description INSEL0 2 0 rw External Trigger Input 0 Selection This bit field defines the source for the external trigger input 0 000 Input SRO is selected 001 Input SR1 is selected 010 Input SR2 is selected 011 Input SR3 is selected 100 Input SR4 is selected 101 MLI Break Event is selected 110 Input AIN4 is selected 111 Input AIN14 is selected FENO 6 rw Falling Edge Enable for External Trigger Input 0 This bit enables disables the activation of external trigger input 0 upon a falling edge at the selected input 0 The trigger u
112. abled and status flags TRSR CHOn and TRSR HTREOn are reset In order to start a new hardware controlled DMA transaction hardware requests must be enabled again by setting TRSR HTREOn through HTREQ ECHOn 1 The hardware request disable function in Single Mode is typically needed when a reprogramming of the DMA channel register set addresses transfer count is required before the next hardware triggered DMA transaction is started The hardware controlled Single Mode in which each single DMA transfer has to be requested by a hardware request signal is selected as described above with one difference e CHCROn RROAT 0 In this operation mode TRSR CHOn becomes reset after each DMA transfer of the DMA transaction and a new hardware request at must be generated for starting the next DMA transfer User Manual 3 18 V 1 0 2005 11 DMA V1 0 Cinfineon CIC751 Direct Memory Access Controller CHCR0n RROAT 1 TRSR CH0n 4 5 TRSR HTRE0n m 7777 m Transfer TRO aXe osmowTcouwr o Son INT tc initial transfer count triggered at the end of a transaction with IRDV 0 CHCROn RROAT 0 TRSR CH0n j TRSR HTRE0n l CH0n_REQ INT tc initial transfer KASD triggered at the end of a transaction with IRDV 0 MCT06156
113. ad or Write Frames DVO before DV1 before DV2 before DV3 Base Address Copy Frame BAVO before BAV1 before BAV2 before BAV3 User Manual 4 39 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI 4 2 3 NLI Interface Control Each of the MLI transmitter and MLI receiver communicate with other MLI receivers and MLI transmitters via a four line serial connection Each input output signal used for MLI communication between a transmitter and a receiver can be disabled and inverted in its polarity The control is achieved via register MLI_OICR User Manual 4 40 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI 4 2 4 MLI Request Generation MLI Request generation is based on the interrupt event cases that can be created by the different interrupt sources Each interrupt source is provided with a status flag and an enable bit with software clear capability Several interrupt sources can be combined into one MLI Request using a common interrupt node pointer An interrupt event generated by an interrupt source is always stored in an interrupt status flag that is located in the interrupt status registers MLI TISR for transmitter interrupts MLI RISR for receiver interrupts All interrupt event flags can be cleared individually by write actions to bits located in the interrupt enable registers MLI TIER for transmitter interrupts MLI RIER for receiver interrupts These two registers also c
114. al transmit line which in turn is connected to the slaves shift register input The output of the slaves shift register is connected to the external receive line in order to enable the master to receive the data shifted out of the slave The external connections are hard wired with the function and direction of these pins determined by the master or slave operation of the individual device Note The shift direction shown in Figure 5 2 applies to both MSB first and LSB first operation When initializing the devices in this configuration one device must be selected for master operation while all other devices must be programmed for slave operation Initialization includes the operating mode of the device s SSC and also the function of the respective port lines User Manual 5 3 V 1 0 2005 11 SSC 1 0 Cinfineon Synchronous Serial Interface SSC Master Device 1 Device 2 Slave Shift Register q Transmit q Receive q Clock Device 3 Slave MCA04508 Figure 5 2 SSC Full Duplex Configuration The data output pins MRST of all slave devices are connected to one receive line this configuration During a transfer each slave shifts out data from its shift register There are two ways to avoid collisions on the receive line due to different slave data Only one slave drives the line and enables the driver of its MRST pin All the other
115. also initiates all control tasks control address and data transmissions that are required for the data transfer request between the Local Controller and the Remote Controller The controller with an MLI module that operates as a receiver in the serial MLI connection is defined as a Remote Controller A Remote Controller handles data operations with Remote Windows and executes the tasks that have been assigned requested by the Local Controller Due to the full duplex operation capability of an MLI module two serial MLI connections can be installed simultaneously This means that each microcontroller with an MLI module is able to operate as a Local Controller for transmission as well as a Remote Controller for reception at the same time Transfer Window A Transfer Window is an address space in the address map of the Local Controller Transfer Windows are typically assigned to a fixed address space base address and size in a specific microcontroller The transfers windows are the logical data inputs for the MLI transmitter Data write actions are initiated by a write access to a Transfer Window whereas data read actions are started by a read access from a Transfer Window Each MLI module supports up to eight independent Transfer Windows Each Transfer Window can be accessed at two different address ranges with two different window sizes leading to Four small Transfer Windows each with 8 KByte address range e Four large Tra
116. an Answer Frame MLI RDATAR MLI Receiver Data Register 31 30 29 28 27 26 2901 Reset Value 0000 0000 25 24 23 22 21 20 19 18 17 16 DATA 31 16 r 9 8 7 6 5 4 3 2 1 0 DATA 15 0 r Field Bits Type Description DATA 31 0 Data In the Remote Controller DATA contains the data received by a write frame or an Answer Frame Bit field MLI_RCR DW determines the width of the relevant data that is stored in MLL RDATAR MLI RCR DW 00 7 0 are relevant 8 bit MLI RCR DW 01 MLI RDATAR 15 0 are relevant 16 bit MLI RCR DW 10 MLI RDATAR 31 0 are relevant 32 bit User Manual MLI V1 0 4 82 V 1 0 2005 11 Cinfineon i Micro Link Interface MLI 4 3 4 Transmitter Interrupt Registers 4 3 41 Transmitter Interrupt Enable Register The Transmitter Interrupt Enable Register MLI TIER contains the interrupt enable bits and the interrupt request enable flag clear bits for all transmitter interrupt request events The bits marked w are always read as 0 MLI_TIER MLI Transmitter Interrupt Enable Register 298 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 TE PE CFS CFS CFS CFS NFS NFS NFS NFS IR IR IR3 IR2 IR1 IRO IR3 IR2 IR1 IRO r w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
117. anual 4 80 V 1 0 2005 11 MLI V1 0 Cinfineon CIC751 Micro Link Interface MLI 4 3 3 4 Receiver Address Register The Receiver Address Register MLI RADRR is a read only register storing the complete address of the most recently or currently targeted Remote Window MLI RADRR MLI Receiver Address Register 28 31 30 29 28 27 26 Reset Value 0000 0000 25 24 23 22 21 20 19 18 17 16 ADDR 31 16 r 9 8 7 6 5 4 3 2 1 0 ADDR 15 0 r Field Bits Type Description ADDR 81 0 Address ADDR indicates the complete target address for the most recently or currently targeted Remote Window Pipe x If a Copy Base Address Frame is received ADDR is unchanged If a write or read frame with m bits of address offset is received bits ADDR 31 m replaced by the bits RPOBAR ADDR S1 m and bits ADDR m 1 0 are replaced by the received offset If an optimized read or data frame is received the address prediction mechanism adds the predicted address offset MLI RPOSTATR AP to MLI RPOBAR ADDR and stores the result in ADDR If an Answer Frame is received ADDR becomes invalid User Manual MLI V1 0 4 81 V 1 0 2005 11 Cinfineon CIC751 Micro Link Interface MLI 4 3 3 5 Receiver Data Register The Receiver Data Register MLI RDATAR is a read only register that stores data received by a write frame or
118. at is consumed by the different conversion steps therefore is independent from the general speed of the device This allows the A D converter of the CIC751 to be adjusted to the properties of the system Fast Conversion can be achieved by programming the respective times to their absolute possible minimum This is preferable for scanning high frequency signals The internal resistance of analog source and analog supply must however be sufficiently low High Internal Resistance can be achieved by programming the respective times to a higher value or to the possible maximum This is preferable when using analog sources and supply with a high internal resistance in order to keep the current as low as possible The conversion rate in this case may however be considerably lower Control Bit Fields Two mechanisms are provided for timing control of the conversion and the sample phase Standard timing control uses two 2 bit fields in register ADC CON to select prescaler values for the general conversion timing and the duration of the sample phase This provides compact control while limiting the prescaler factors to a few steps Improved timing control uses two 6 bit fields in register CON1 Compatibility Mode or register ADC_CTR2 ADC_CTR2IN Enhanced Mode This provides a wide range of prescaler factors so the ADC can be better adjusted to the internal and external system circumstances Improved timing control is selected by se
119. be accessed without disturbing the prediction If the offset differences in at least two accesses are identical to the same Transfer Window an address prediction is possible flag MLI TPxSTATR OP is set and optimized frames can be sent to the receiver in the Remote Controller for this Pipe If the offset difference of the next access to the same Transfer Window does not match the calculated value TPxSTATR AP flag TPxSTATR OP is cleared and address prediction is not possible In this case a Normal Frame for writing or reading Write Offset and Data Frame or Discrete Read Frame is started Remote Controller The MLI receiver operates with the same address prediction as the MLI transmitter This means that after receiving at least two consecutive Write Offset and Data Frames and or Discrete Read Frames that include address information the MLI receiver is able to follow the address prediction used by the MLI transmitter Each received offset is compared in the MLI receiver with the offset of the previously received frame of the same Pipe The result of this comparison is stored in two s User Manual 4 38 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI complement representation MLI_RPxSTATR AP limited 9 bits If an optimized frame is received by the MLI receiver it calculates the next address by adding the value stored RPxSTATR AP to the contents of the receiver address register ML
120. by setting SCU_PLLCON PLLCTRL 115 Bypass Mode In Bypass Mode the input clock fosc is directly connected to the PLL output fpu So the output frequency is given by fet fosc 2 2 The Bypass Mode is selected by setting SCU_PLLCON BY 1p Prescaler Mode In Prescaler Mode the input clock fosc is divided down by a factor P So the output frequency is given by fosc 2 3 Prescaler Mode is selected by setting SCU_PLLCON PLLCTRL 00g Freerunning Mode In Freerunning Mode the base frequency output of the Voltage Controlled Oscillator VCO fvcobase iS only divided by a factor K So the output frequency is given by f fycobase PLL 7 K 2 4 The Freerunning Mode is selected by setting SCU_PLLCON PLLCTRL 10g General Configuration Overview All three divider values and all necessary other values can be configured via the PLL configuration register SCU_PLLCON Table 2 1 lists a few possible values for the P factor and gives the valid output frequency range for the P divider dependent on P and the fosc frequency range User Manual 2 6 V 1 0 2005 11 STCU V 1 0 Cinfineon System and Control Unit SCU Table 2 1 P Divider Factors P PDIV 1 PDIV for fosc Note Of course the entire range between two fosc columns in the above table is allowed E g for a range fosc 20 to 25 and P 3 frer 6 66 to 8 33 MHz The P divider output frequenc
121. can be freely moved and located within the complete address space of the Remote Controller They are used to overlay address ranges of peripheral modules or internal memories Remote Window Address Definition A Remote Window is defined for each Pipe Each Remote Window is defined by a programmable base address and a size for each Pipe Frames transfer only the address offset information to define an address within a Remote Window if no prediction is possible A Remote Window can have a size of up to 64 KBytes User Manual 4 5 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI 4 1 4 MLI Frame Types A frame is a message sent by an MLI transmitter to an MLI receiver The fame type depends on the desired behavior The MLI protocol offers seven different frame types for communication e Copy Base Address Frame defines the base address and size of a Remote Window e Write Offset and Data Frame transmits the write offset and the write data Discrete Read Frame transmits read request with the read offset Command Frame transmits a command e g setup information MLI Request generation Optimized Write Frame transmits write data without a write offset in case of an address prediction match Optimized Read Frame transmits the read request without a read offset in case of an address prediction match e Answer Frame transmits the data previously requested by a read frame The local remote str
122. cted a parity error When a Pipe 1 Command Frame is received by the MLI receiver the command code is stored in this bit field see Page 4 30 0000 Zero RCLK clock period delay is selected 0001 One RCLK clock period delay is selected 0010 Two RCLK clock periods delay is selected 1110 Fourteen RCLK clock periods delay is selected 1111 Fifteen RCLK clock periods delay is selected CMDP3 7 4 rh Command From Pipe 3 When a Pipe 3 Command Frame is received by the MLI receiver the command code is stored in this bit field Pipe 3 commands are available for software use User Manual 4 75 V 1 0 2005 11 MLI V1 0 Cinfineon CIC751 Micro Link Interface MLI Field Bits Type Description MOD rh Mode of Operation This bit determines the data transfer operation mode of the MLI receiver Bit MOD can be set with the reception of a Pipe 2 Command Frame see Page 4 67 It can be set or cleared via bits MLI SCR SMOD or MLI SCR CMOD 0 Automatic Data Mode is disabled Data read write operations from to a Remote Window must be executed by the DMA 1 Automatic Data Mode selected Data read write operations from to a Remote Window are executed by the MLI DW 10 9 Data Width This bit field is updated by the MLI receiver whenever new data is received in the MLI RDATAR register It indicates the relevant data width 00 8 bit relevant data width in MLI RDATAR 01 16 bit relevant data width
123. ctional Divider Register 000 4 49 TCR Transmitter Control Register 00104 Page 4 59 MLI_TSTATR Transmitter Status Register 00144 Page 4 62 MLI_TPOSTATR Transmitter Pipe x Status Register 00184 4 64 x 4 MLI TCMDR Transmitter Command Register 0028 4 66 MLI TRSTATR Transmitter Receiver Status Register 002 4 68 MLI TPOAOFR Transmitter Pipe x Address Offset 00304 Page 4 70 Register x 4 MLI_TPODATAR Transmitter Pipe x Data Register 00404 Page 4 71 x 4 MLI_TDRAR Transmitter Data Read Answer Register 00504 Page 4 72 MLI_TPOBAR Transmitter Pipe x Base Address 0054 Page 4 73 Register x 4 MLI_TCBAR Transmitter Copy Base Address 0064 Page 4 74 Register MLI_RCR Receiver Control Register 0068 Page 4 75 MLI RPOBAR Receiver Pipe x Base Address Register 006C 4 78 x 4 RPOSTATR Receiver Pipe x Status Register 007 4 74 x 4 MLI RADRR Receiver Address Register 008C Page 4 81 MLI RDATAR Receiver Data Register 0090 Page 4 82 MLI SCR Set Clear Register 0094 Page 4 51 User Manual 4 47 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI Table4 10 MLI Kernel Registers cont d Register Register Long Name Offset Description Short Name Address see MLI_TIER Transmitter Interrupt Enable Register 0098 4 83 MLI_TISR Transmitter Interrupt Status Register 009
124. ddress that is transmitted to the Remote Controller via a Copy Base Address Frame MLI_TPOBAR MLI Transmitter Pipe 0 Base Address Register 2544 Reset Value 0000 0000 MLI_TP1BAR MLI Transmitter Pipe x Base Address Register 258 Reset Value 0000 0000 MLI TP2BAR MLI Transmitter Pipe x Base Address Register 25 Reset Value 0000 0000 MLI TP3BAR MLI Transmitter Pipe x Base Address Register 260 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADDR 31 16 w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDR 15 4 BS Ww w Field Bits Type Description BS 3 0 w Size This bit field determines the coded size of the Pipe x Remote Window in the Remote Controller When writing MLI_TP0BAR BS is copied into bit field MLI TPOSTATR BS 0000 1 bit offset address of Remote Window 0001 2 bit offset address of Remote Window 0010 3 bit offset address of Remote Window 1111 16 bit offset address of Remote Window ADDR 31 4 Address This bit field determines the most significant 28 bits of the Pipe x Remote Window base address When writing MLI_TPOBAR ADDR is copied into bit field MLI_TCBAR ADDR 31 4 User Manual 4 73 V 1 0 2005 11 MLI V1 0 Cinfineon CIC751 4 3 2 10 Transmitter Copy Base Address Register Micro Link Interface MLI The Transmitter Copy Base Address Register MLI TCBAR contains the 2
125. de the result is placed as follows 8 bit ADRES 9 2 10 bit ADRES 9 0 In Enhanced Mode the result is placed as follows 8 bit ADRES 1 1 4 10 bit ADRES 1 1 2 Note Unused bits of ADRES are always set to 0 CHNR 15 12 rwh Channel Number This bit field identifies the converted analog channel ADC DAT2 ADC Result 2 Register 032 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHNR ADRES rw rwh User Manual 6 27 V 1 0 2005 11 ADC V1 0 Cinfineon CIC751 The Analog Digital Converter Field Bits Type Description ADRES 11 0 A D Conversion Result The digital result of the most recent conversion In Compatibility Mode the result is placed as follows 8 bit ADRES 9 2 10 bit ADRES 9 0 In Enhanced Mode the result is placed as follows 8 bit ADRES 1 1 4 10 bit ADRES 11 2 Note Unused bits of ADRES are always set to 0 CHNR 15 12 rw Channel Number This bit field identifies the converted analog channel User Manual 6 28 V 1 0 2005 11 ADC 1 0 Cinfineon The Analog Digital Converter 6 8 4 ADC Extended Result Registers The following registers be used in the Compatibility Mode and Enhanced Mode for storage of the conversion results User Manual 6 29 V 1 0 2005 11 ADC V1 0 Cinfineon CIC751 RESAO0 The Analog Digital Converter
126. des The operation mode of a DMA channel is individually programmable for each DMA channel On Basically a DMA channel can operate in the following modes Software controlled mode Hardware controlled mode in Single or Continuous Mode In software controlled mode a DMA channel request is generated by setting a control bit In hardware controlled mode a DMA channel request is generated by request signals typically generated by on chip peripheral units In hardware controlled Single Mode a DMA channel On becomes disabled by hardware after the last DMA transfer of its DMA transaction In hardware controlled Continuous Mode a channel remains enabled after the last transfer of its transaction In hardware and software controlled mode a DMA request signal can be configured to trigger a complete DMA transaction or one single transfer Software controlled Modes In software controlled mode one software request starts one complete DMA transaction or one single transfer Software controlled modes are selected by writing HTREQ DCHOn 1 This forces status flag TRSR HTREOn 0 hardware request of DMA channel On is disabled The software controlled mode that initiates one complete DMA transaction to be executed is selected for DMA channel On by the following write operations e CHCROn RROAT 1 e STREQ SCHOn 1 Setting STREQ SCHOn to 1 this is the software request causes the DMA transaction of DMA
127. ding on the type of access to the Transfer Windows different actions take place inside the MLI interface Please refer to the following sections for the handling of specific frame types see the pages indicated e Copy Base Address Frame see Page 4 19 Data frames see Page 4 22 e Read frames see Page 4 26 e Answer Frame see Page 4 29 Command Frame see Page 4 30 4 2 1 1 Copy Base Address Frame A Copy Base Address Frame defines the base address and the size of a Remote Window User Manual 4 19 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI Local NLI Controller Remote MLI Controller MLI Transmitter Ready MLI Receiver Ready TPxBAR is written TPxSTATR BS TPxBAR BS TCBAR ADDR TPxBAR ADDR TRSTATR PN x TRSTATR BAV 1 Send Copy Base Address Frame of pipe x x Base Address buffer size Parity check amp acknowledge frame RREADY 1 TRSTATR BAV TISR NFSIx RPxBAR ADDR Base address 28 bit i RPxSTATR BS Buffer size 4 bit RCR TF RISR NFRI 0 1 Normal Frame Sent x Interrupt Normal Frame Received Interrupt Remote window pipe x is initialized and ready to read write data MCA05888 Figure 4 16 Copy Base Address Frame Transaction Flow Local Controller The transmi
128. do not use 101 Reserved do not use 110 Reserved do not use 111 Reserved do not use NFSIP1 6 4 rw Normal Frame Sent in Pipe 1 Interrupt Pointer This bit field determines which MLI Request x becomes active when a Normal Frame sent in Pipe 1 interrupt occurs Coding see NFSIPO User Manual 4 86 V 1 0 2005 11 MLI V1 0 Cinfineon CIC751 Micro Link Interface MLI Field Bits Type Description NFSIP2 10 8 rw Normal Frame Sent in Pipe 2 Interrupt Pointer This bit field determines which MLI Request x becomes active when a Normal Frame sent in Pipe 2 interrupt occurs Coding see NFSIPO NFSIP3 14 12 Normal Frame Sent in Pipe 3 Interrupt Pointer This bit field determines which MLI Request x becomes active when a Normal Frame sent in Pipe 3 interrupt occurs Coding see NFSIPO CFSIP 18 16 Command Frame Sent Interrupt Pointer This bit field determines which MLI Request x becomes active when a Command Frame sent interrupt occurs Coding see NFSIPO PTEIP 22 20 Parity or Time Out Interrupt Pointer This bit field determines which MLI Request x becomes active when a parity time out interrupt occurs Coding see NFSIPO 3 7 11 15 3 1 23 Reserved Read as 0 should be written with 0 User Manual MLI V1 0 4 87 V 1 0 2005 11 Cinfineon CIC751 4 3 5 Receiver Interrupt Registers 4 3 5 1 Receiver Interrupt Enable Register
129. dress Register SADROn for details see Page 3 47 Channel Destination Address Register DADROn for details see Page 3 48 e Channel Shadow Address Register SHADROn for details see Page 3 49 3 2 4 4 Shadowed Source or Destination Address As a typical application an SSC module that receives data fixed source address has to deliver it to a memory buffer using a DMA transaction variable destination address After a certain amount of data has been transferred a new DMA transaction should be initiated to deliver further SSC data into another memory buffer While the destination address register is updated during a running DMA transaction with the actual destination address a shadow mechanism allows programming of a new destination address without disturbing the content of the destination address register In this case the new destination address is written into a buffer register i e the shadow address register At the start of the next DMA transaction the new address is transferred from this shadow address register to the destination address register The shadow address register can be used also to store a source address However it cannot store source and destination address at the same time This means that the shadow mechanism makes it possible to automatically update either a new source address or a new destination address at the start of a DMA transaction If both address registers for source and destination address have
130. ds that are used for parity acknowledge address optimization TDATA idle polarity retry and transmitter enable disable control MLI_TCR MLI Transmitter Control Register 2104 Reset Value 0000 0110 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TP NO MDP MNAE MPE 0 RTY DNT MOD w rw rw rwh rwh r iW mw Iw Field Bits Type Description MOD 0 rw Mode of Operation This bit enables the MLI transmitter 0 The MLI transmitter is disabled 1 MLI transmitter is enabled DNT 1 rw Data in Not Transmission This bit determines the level of the transmitter data line TDATA when no transmission is in progress 0 TDATA is at low level if no transmission is running 1 TDATA is at high level if no transmission is running User Manual 4 59 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI Field Bits Type Description RTY 2 rw Retry This bit enables the retry mechanism for the Transfer Windows This bit is only relevant for system bus architectures supporting a retry mechanism otherwise it is ignored 0 The retry mechanism is disabled Any access while the transmitter is busy is discarded without additional action 1 The retry mechanism is enabled Any access while the transmitter is busy is acknowledged with a retry In this case the requesting bus master sends the requested access again until the req
131. dule Kernel Registers 3 26 General Control Status Registers 3 28 Move Engine Registers 3 37 Channel Control Status Registers 3 39 Channel Address Registers 3 47 Micro Link Interface 4 1 MLI n iit eee eek owes ace 4 1 AMPLE 4 1 MLI Specific Terms 4 2 MLI Communication Principles 4 3 MLI Frame 4 6 Copy Base Address Frame 4 8 Write Offset and Data 4 9 Optimized Write Frame 4 10 Discrete Read 4 11 Optimized Read Frame 4 12 Command 4 13 Answer Frame 4 14 Naming Conventions 4 15 MLI Communication Examples 4 15 Ready Delay Time 4 16 Non Acknowledge 4 17 Parity 4 17 Address
132. e Description LOCK 0 rh PLL Lock Status Flag 0 PLL is not locked 1 PLL is locked User Manual 2 16 V 1 0 2005 11 STCU V 1 0 Cinfineon CIC751 System and Control Unit SCU Field Bits Type Description RESLD rwh Restart Lock Detection Setting this bit will reset bit LOCK and restart the lock detection When set this bit is automatically cleared 0 No effect 1 Reset LOCK and restart lock detection SWRST Software Reset Trigger Setting this bit will automatically request and generate a reset With the reset execution this bit is automatically cleared P1DIDIS Port 1 Digital Input Disable This bit controls the digital input stage for all port 1 pins 0 Digital input stage Schmitt trigger is enabled 1 Digital input stage Schmitt trigger is disabled This is necessary if pins are used as analog input MTM 7 6 Multiplexer Test Mode for Channel 0 This bit enables disables the Multiplexer Test Mode forthe input channel 0 This feature is independent of the current mode of the analog part If the Multiplexer Test Mode is enabled the analog input is connected to ADC ground via an internal resistance This structure creates a voltage divider to ground so the measurement result becomes smaller 00 The Multiplexer Test Mode is disabled The analog input is not connected to ground and can be used for normal measurements 01 The Multiplexer Test Mode is en
133. e range of 70 Ohm 11 Reserved like 00 User Manual ADC V1 0 6 36 V 1 0 2005 11 Cinfineon CIC751 The Analog Digital Converter Field Bits Type Description 1 3 2 rw Reserved Should be written with 1 0 15 8 Reserved Read as 0 should be written with 0 1 Please refer to the ACDC chapter for the current capability of the grounding resistor especially when using RC input filters at the analog inputs User Manual ADC V1 0 6 37 V 1 0 2005 11 Cinfineon Parallel Ports 7 Parallel Ports The CIC751 has two parallel ports port 0 and port 1 Port 0 controls all pins for the communication MLI SSC Service Requests Port 1 controls 16 inputs of the 16 ADC channels Each port line has a number of control and data bits enabling very flexible usage of the line Each port pin can be configured for input or output operation In Input Mode the output driver is switched off high impedance The actual voltage level present at the port pin is translated into a logical 0 or 1 via a Schmitt Trigger device and can be read via the read only register Pn IN The input can also be connected directly to the various inputs of the peripheral units Alternate Input The function of the input line from the pin to the input register Pn_IN and to the alternate input is independent of whether the port pin operates as input or output This means that when the port is in Output Mode the level
134. e received interrupt to read the requested read data and transfer it to the MLI receiver Therefore it must read data with width MLI RCR DW from the address stored in MLI RADRR and write the data into MLI TDRAR DATA e RCR MOD 1 Automatic Data Mode is enabled In this mode the MLI automatically reads the read data from the Remote Window and sets interrupt status flag MLI RISR MEI An MLI Request is generated if enabled by RIER MEIE 1 After MLI TDRAR DATA has been updated status flag TRSTATR AV of the Remote Controller is set and the transmission of an Answer Frame is started Read Data from Remote Window no RCR MOD 1 S Read from remote window is executed RISR MEI 1 RISR NFRI 1 Normal Frame Received Interrupt Read from remote window is executed Writeto TDRAR DATA iin TRSTATR AV 1 read_from_remote Figure 4 20 Read Frame Handling on Remote Side Note In Automatic Data Mode read frames lead to a read action executed by the MLI During the move operation only one more MLI frame can be received stored in a waiting position to be executed Then the reception of more frames is blocked by User Manual 4 28 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI non acknowledge error If the move operation is finished frame execution and reception continue normally If Automatic Data Mode is disabled no b
135. ected to the SSC c pins P0 3 P0 8 P0 9 10 11 and P0 12 are used for general purpose Note Not all pins are directly connected for functional reasons to a peripheral User Manual 7 2 V 1 0 2005 11 Parallel Ports V1 0 incen CIC751 Parallel Ports 7 1 3 Port 0 Routing The following table describes the mapping of the pins of Port 0 and the related I O functions Table 7 1 Port 0 Input Output Functions Port Select Connected Function From to Module Pin P0 0 Input Not used Output GPIO Port Output Register PO_OUT PO Port ALT1 TCLK MLI ALT2 SR3 SCU 883 SCU PO 1 Input TREADY MLI Output GPIO Port Output Register PO OUT P1 Port ALT1 SR4 SCU ALT2 SR4 SCU ALT3 SR4 SCU 2 Input SCLK SSC Output GPIO Port Output Register OUT P2 ALT1 TVAILD MLI ALT2 Not used ALT3 Not used Input Not used Output GPIO Port Output Register PO_OUT P3 ALT1 TDAT MLI ALT2 MRST SSC ALT3 Not used P0 4 Input RCLK MLI RCLK SCU Output GPIO Port Output Register P0_OUT P4 ALT1 Not used ALT2 Not used ALT3 Not used User Manual 7 3 V 1 0 2005 11 Parallel Ports V1 0 Cinfineon Parallel Ports Table 7 1 Port 0 Input Output Functions Port Select Connected Function From to Module Pin P0 5 Input Not used Output GPIO Port Output Register PO_OUT P5 ALT
136. ed back to the host in a semi automatic way 5 2 2 4 SSC Transaction Header The first halfword that is send by the host is interpreted as the transaction header and is composed of the CMD bit the INCE bit and an address ADDR of 14 bits Therefore the master host must first send the 16 bit header information before sending each communication block A communication block is composed of the transaction header and one or more 16 bit communication data blocks The following table defines the SSC transaction header Table 5 1 Transaction Header Name Description Bit Position CMD Transfer Type Identifier 15 0 A read transfer is selected 1 A write transfer is selected INCE Address Increment Enable 14 0 The destination address is not increment after each transaction 1 The destination address is increment after each transaction ADDR Destination Address 13 0 CMD determines if the following portion of the communication indicates a write or read operation INCE determines whether or not the address is automatically incremented by two after the first data block User Manual 5 8 V 1 0 2005 11 SSC 1 0 Cinfineon Synchronous Serial Interface SSC Example INCE 1 Setup for the source and destination addresses of DMA Channel 5 for additional data transfers must be updated Therefore the DMA channel registers 5 DMA_SADR5 and DMA_DADR5 must be updated Beginning with register
137. ed if enabled by RIER PEIE 1 After a receiver parity error event has occurred RCR MPE can set again by software to a value greater 00015 If for example each receiver parity error condition should generate a receiver parity error interrupt MLI RCR MPE can be set to 0001g after a receiver parity error interrupt has occurred The receiver parity error flag MLI RCR PE is cleared when a correct frame transmission has occurred MLI RCR PE can be cleared by software when writing a 1 to bit MLI SCR CRPE The receiver parity error flag RCR PE is cleared when a correct frame transmission and TREADY has been sampled with 1 within the ready delay time It can be cleared by software by writing a 1 to bit SCR CRPE If for example each receiver parity error condition should generate a receiver parity error event MLI RCR MPE should be set to 0001g The software can check for accumulated parity error conditions by reading MLI RCR MPE or MLI RISR PEI for the status of the latest received frame it can check MLI RCR PE The delay for parity error bit field MLI RCR DPE is a read only bit field in the receiver that can be written only by hardware if a Command Frame for Pipe 1 is received With this frame type the transmitter in the Local Controller transfers a value for MLI RCR DPE to the receiver in the Remote Controller User Manual 4 36 V 1 0 2005 11 MLI V1 0 Cinfineon i Micro Link Interface MLI RCR DPE RCLK
138. eived in Pipe x interrupt is enabled User Manual 4 88 V 1 0 2005 11 MLI V1 0 Cinfineon CIC751 Micro Link Interface MLI Field Bits Type Description ICE 6 rw Interrupt Command Enable This bit determines whether an interrupt is generated when a Command Frame is received in Pipe 0 0 Command Frame received in Pipe 0 interrupt is disabled 1 Command Frame received in Pipe 0 interrupt is enabled PEIE 7 rw Parity Error Interrupt Enable This bit enables the interrupt generated if receiver a parity error event is detected 0 Parity error interrupt is disabled 1 Parity error interrupt is enabled DRAIE 9 rw Discarded Read Answer Interrupt Enable This bit enables the interrupt generated if a discarded read Answer Frame condition is detected 0 Discarded read answer interrupt is disabled 1 Discarded read answer interrupt is enabled NFRIR 16 w Normal Frame Received Interrupt Flag Clear 0 No action 1 Clear MLI RISR NFRI MEIR 17 w MLI Move Engine Interrupt Flag Clear 0 No action 1 Clear MLI RISR MEI CFRIRO 18 w Command Frame Received through Pipe x Interrupt CFRIR1 19 Flag Clear CFRIR2 20 0 No action CFRIR3 21 1 Clear MLI RISR CFRIx ICER 22 w Interrupt Command Flag Clear 0 No action 1 Clear MLI RISR ICE PEIR 23 w Parity Error Interrupt Flag Clear 0 No action 1 Clear MLI_RISR PEI DRAIR 25 w Discarded Read Answer Interrupt Flag Clear 0 No action 1 Clear MLI RISR DRAI 0 8 24 w Rese
139. en and lead to an undefined behavior All port register can only be accesses by 32 bit accesses The MLI master automatically generates 32 bit accesses for 32 bit data transfers The MLI master automatically generates 16 bit accesses for 16 bit data transfers The MLI master automatically generates 8 bit accesses for 8 bit data transfers The SSC master automatically generates 32 bit accesses to all registers beside the ADC register The SSC master automatically generates 16 bit accesses to all ADC registers Accesses to not configured parts of an MLI Remote Window are forbidden and lead to an undefined behavior All registers beside the ADC core register are 32 bit registers The ADC core registers are 16 bit registers 32 bit accesses are forbidden and lead to an undefined behavior The registers are ADC core registers CON ADC Control Register ADC_CON1 ADC Control 1 Register ADC Control 0 Register ADC_CTR2 ADC Control 2 Register ADC_CTR2IN ADC Injection Control 2 Register ADC_DAT ADC Result Register ADC_DAT2 ADC Result 2 Register User Manual 8 3 V 1 0 2005 11 Regs V1 0 CIC751 Cinfineon Register Overview 8 2 Registers Tables Table 8 2 MLI Kernel Registers Register Register Long Name Address Description Short Name see Reserved Reserved 00000200 l 0000 0208 MLI FDR Fractional Divider Register
140. eon System and Control Unit SCU Table 2 5 SCU Registers cont d Register Short Register Long Name Address Description Name see SCU_CHTR4 SCU Channel Trigger 4 Register 840 2 22 SCU CHTR5 SCU Channel Trigger 5 Register 844 Page 2 22 SCU CHTR6 SCU Channel Trigger 6 Register 848 2 22 SCU_CHTR7 SCU Channel Trigger 7 Register 84C Page 2 22 IDCHIP Chip Identification Register 860 Page 2 24 User Manual 2 25 V 1 0 2005 11 STCU V 1 0 Cinfineon Direct Memory Access Controller 3 Direct Memory Access Controller This chapter describes the Direct Memory Access DMA Controller of the CIC751 3 1 DMA Request Generation and Control This section describes how a DMA Move Transfer Transaction is requested The differnet request sources can be controlled to support the adaption for the required application 3 1 1 Request Generation Requests that trigger a DMA Transaction can be generated in several ways This flexible request generation mechanism enables the software to configure the hardware to the exact needs of the application After configuration the DMA handles all requests without further software requirements Each of the eight channels can be requested by one of six possible requests The following request sources can trigger a DMA Transfer of a channel MLI Request 0 indirect e MLI Request 1 indirect MLI Request 2 direct e MLI Request 3 direc
141. er 27 26 28 24 Reset Value 0000 0000 25 23 22 21 20 19 18 17 16 ssl RE TE 2 Field Bits Type Description BC 9 0 Bit Count Status BC indicates the current status of the shift counter The shift counter is updated with every shifted bit TE rh Transmit Error Flag 0 No error 1 Transfer starts with the slave s transmit buffer not being updated RE rh Receive Error Flag 0 No error 1 Reception completed before the receive buffer was read PE rh Phase Error Flag 0 No error 1 Received data changes during the sampling clock edge BSY 12 rh Busy Flag BSY is set while a transfer is in progress 7 4 11 31 13 m Reserved Read as 0 should be written with O The Error Flag Modification Register 55 EFM is required for resetting or setting the four error flags that are located in register 55 STAT User Manual 5 18 SSC 1 0 V 1 0 2005 11 Cinfineon CIC751 Synchronous Serial Interface SSC SSC EFM SSC Error Flag Modification Register 2C Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 9 18 17 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 SET SET 0 CLR CLR CLR 0 RE TE w w w w w w w w Field Bits Type Description CLRTE 8 w Clear Transm
142. er on Internal EVR fail reset The EVR encounters a problem and the required power supply levels are not longer guaranteed Setting bit SCU SYSCON SWRST This generates a software trigger reset The entire CIC751 is reset regardless of the means by which the reset was generated A reset always triggers a new mode selection phase with the exception that a software reset does not trigger a new Mode Selection A software reset retains the mode currently selected 2 1 1 Power On Reset The PORST input pin requests a power on reset Driving the PORST pin low causes a non synchronized reset of the entire device PORST is equipped with a noise suppression filter which suppresses glitches below 10 ns pulse width PORST pulses with a width above 100 ns are safely recognized 2 1 2 Embedded Voltage Regulator EVR Reset If the power supply does not reach the value required for proper functionality a reset is applied This ensures a reproducible behavior after power on or in the case of power fail 2 2 Mode Selection The pins TESTMODE and MODE should supplied with specific voltage levels to ensure correct configuration of the CIC751 User Manual 2 1 V 1 0 2005 11 STCU V 1 0 Cinfineon System and Control Unit SCU 2 2 1 MODE Pin The MODE pin defines whether the MLI interface or the SSC interface is activated for Normal Mode For MODE 0 the MLI interface is activated and configured as the only communication int
143. erences larger than 512 bytes are not supported by the address prediction If in at least two accesses the offset differences are identical an address prediction is possible and Optimized Write Frames or Optimized Read Frames can be sent to the receiver in the Remote Controller for this Pipe If the offset difference of the next access to this Transfer Window does not match the previous ones predicted offset address prediction is not possible In this case a Normal Frame for writing or reading Write Offset and Data Frame or Discrete Read Frame is started Identical address prediction mechanisms are used by both the transmitter and the receiver As a result the receiver can elaborate on the original offset value in the transmitter when receiving an optimized frame for any Pipe Details about the prediction mechanism of the CIC751 are provided in Chapter 4 2 2 3 User Manual 4 18 V 1 0 2005 11 MLI V1 0 Cinfineon i Micro Link Interface MLI 4 2 Functional Description This chapter describes the functionality of the MLI interface and how frame handling can be done by software Frame handling see Page 4 19 MLI features see Page 4 34 e MLI Request structure see Page 4 41 e transmitter interrupts see Page 4 41 MLlreceiver interrupts see Page 4 43 e Baud rate generation see Page 4 45 4 2 1 Frame Handling Frame handling is based on receiver and transmitter registers and the Transfer Windows Depen
144. erface For MODE 1 the SSC interface is activated and configured as the only communication interface The value that is sampled and used for this decision must be held for 400 us after reached 1 5 V 2 2 2 TESTMODE Pin The pin must be tied to 1 2 3 Clock System This section describes the clock system of the CIC751 Topics include clock generation clock domains operation of clock circuitry and clock control registers 2 3 1 Overview The CIC751 clock system performs the following functions Uses the internal free running frequency of the VCO block to create a fast clock frequency feys Uses the internal oscillator of the VCO block to create a fast clock frequency fsys Acquires and buffers the external clock signal RCLK to create a fast clock frequency e Distributes the in phase synchronized clock signal throughout the 751 8 entire clock tree The clock system must be operational before the CIC751 can operate so it contains special logic to handle power up and reset operations Its services are fundamental to the operation of the entire system so it contains a special fail safe logic 2 3 2 Clock Generation Unit The Clock Generation Unit CGU allows very flexible clock generation for CIC751 The CGU in the CIC751 consists of an oscillator circuit RCOSC one Phase Locked Loop PLL module and a Clock Control Unit CCU The CGU can convert a low frequency clock signal to a high speed inte
145. ers Within the DMA and the MLI address area there are some memory register defined in Table 8 2 and Table 8 3 These registers can be used as memory registers if needed All memory registers in Table 8 8 are 32 bit register that can be read and written from all masters All memory registers in Table 8 9 are 16 bit register that can be read and written from all masters Register DMA_MEM14 in Table 8 10 is a 8 bit register that can be read and written from all masters Table 8 8 32 Bit Memory Registers Register Register Long Name Address Description Short Name see MLI MEMO MLI Memory 0 Register 00000288 MLI MLI Memory 1 Register 0000 02BC Memory 0 Register 0000 043C _ Memory 1 Register 00000440 l Memory 2 Register 00000444 l Memory 3 Register 0000 0448 User Manual 8 15 V 1 0 2005 11 Regs V1 0 Cinfineon CIC751 Register Overview Table 8 8 32 Bit Memory Registers cont d Register Register Long Name Address Description Short Name see Memory 4 Register 0000 044C l 5 Memory 5 Register 0000 0450 8 9 16 Bit Memory Registers Register Register Long Name Address Description Short Name see DMA_MEM6 DMA Memory 6 Register 0000 0488 DMA
146. ersion timing is selected via registers CTR2IN where controls standard conversions and CTR2IN controls injected conversions User Manual 6 3 V 1 0 2005 11 ADC V1 0 Cinfineon The Analog Digital Converter 6 2 ADC Operation This section describes the various control mechanisms of the ADC 6 2 1 Channel Selection Bit field ADC_CON ADCH or ADC_CTR0 ADCH controls the input channel multiplexer logic In the Single Channel Modes it specifies the analog input channel which is to be converted In the Auto Scan Modes it specifies the highest channel number to be converted in the auto scan round ADC_CON ADCH or ADC_CTRO ADCH may be changed while a conversion is in progress The new value will go into effect after the current conversion is finished in the Fixed Channel Modes or after the current conversion round is finished in the Auto Scan Modes 6 2 2 ADC Status Flags The ADC busy status flag ADC_CON ADBSY or ADC CTRO ADBSY is set when the ADC is started by setting ADC_CON ADST ADC_CTRO ADST and remains set as long as the ADC performs conversions or calibration cycles ADC_CON ADBSY ADC_CTRO ADBSY are cleared when the ADC is idle meaning there are no conversion or calibration operations in progress Bit ADC_CON1 SAMPLE or ADC_CTRO SAMPLE is set during the sample phase 6 2 3 ADC Start Stop Control Bit ADC_CON ADST or ADC_CTRO ADST is used to start or to stop the ADC A single con
147. esult 3 View B Register 14C Page 6 32 RESB3 ADC ADC Extended Result 4 View B Register 150 Page 6 32 RESB4 ADC ADC Extended Result 5 View B Register 154 Page 6 32 RESB5 ADC ADC Extended Result 6 View B Register 158 6 32 RESB6 ADC_ ADC Extended Result 7 View B Register 15C Page 6 32 RESB7 ADC_ ADC Extended Result 8 View B Register 160 6 32 RESB8 ADC_ ADC Extended Result 9 View B Register 164 6 32 RESB9 ADC_ ADC Extended Result 10 View B Register 168 6 32 RESB10 User Manual 6 20 V 1 0 2005 11 ADC V1 0 Cinfineon CIC751 The Analog Digital Converter Table 6 5 Registers Overview cont d Register Register Long Name Offset Page Short Name Address Number ADC ADC Extended Result 11 View B Register 16C Page 6 32 RESB11 ADC ADC Extended Result 12 View B Register 170 Page 6 32 RESB12 ADC ADC Extended Result 13 View B Register 1744 Page 6 32 RESB13 ADC ADC Extended Result 14 View B Register 178 Page 6 32 RESB14 ADC ADC Extended Result 15 View B Register 17 Page 6 32 RESB15 ADC _ ADC Input Result Register 180 Page 6 33 INRES ADC ADC Result Valid Register 1884 Page 6 34 RESV ADC_ ADC Doorbell Control Register 184 Page 6 35 DBCTR 6 8 1 ADC Control Registers for Compatibility Mode The following registers are used in the Compatibility Mode to configure the ADC module
148. etting of RRP 00 RREADY is at passive level 01 is selected 10 RREADY is at passive level 11 RREADY is at passive level RRPB Receiver Ready Polarity This bit determines the polarity of the receiver output RREADY 0 Non inverted polarity for RREADY selected RREADY is passive if 0 RREADY is active if 1 1 Inverted polarity for RREADYx selected RREADY is passive if 1 RREADY is active if 0 RVS 23 22 rw Receiver Valid Selector This bit field determines whether the MLI is connected to pin RVALID or not 00g RREADY is not connected to the MLI Oig RREADY is connected to the MLI 10g RREADY is not connected to the MLI 11g RREADY is not connected to the MLI User Manual MLI V1 0 4 56 V 1 0 2005 11 Cinfineon CIC751 Micro Link Interface MLI Field Bits Type Description RVP 24 Receiver Valid Polarity This bit determines the polarity of RVALID 0 Non inverted polarity for RVALID selected RVALID is passive if 0 RVALID is active if 1 1 Inverted polarity for RVALID selected RVALID is passive if 1 RVALID is active if O RCS 26 25 rw Receiver Clock Selector This bit field determines whether the MLI is connected to pin RCLK or not 00 RCLK is not connected to the MLI Olg RCLK is connected to the MLI 10 is not connected to the MLI 11g RCLK is not connected to the MLI RCP 27 Receiver Clock Polarity Th
149. falling edge at the selected input 0 The trigger upon a falling edge is disabled 1 The trigger upon a falling edge is enabled RENO 7 rw Rising Edge Enable for Pin Trigger 0 This bit enables disables the activation of Pin Trigger 0 upon a rising edge at the selected input 0 The trigger upon a rising edge is disabled 1 The trigger upon a rising edge is enabled User Manual 3 28 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller Field Bits Type Description INSEL1 10 8 w Input Selection for Pin Trigger 1 This bit field defines the Trigger Source for Pin Trigger 1 000 Pin SRO is selected 001 Pin SR1 is selected 010 Pin SR2 is selected 011 Pin SR3 is selected 100 Pin SR4 is selected 101 MLI Break Event is selected 110 Pin AIN4 is selected 111 Pin AIN14 is selected FEN1 14 rw Falling Edge Enable for Pin Trigger 1 This bit enables disables the activation of Pin Trigger 1 upon a falling edge at the selected input 0 The trigger upon a falling edge is disabled 1 The trigger upon a falling edge is enabled REN1 15 rw Rising Edge Enable for Pin Trigger 1 This bit enables disables the activation of Pin Trigger 1 upon rising edge at the selected input 0 The trigger upon a rising edge is disabled 1 The trigger upon a rising edge is enabled 0 5 3 r Reserved 13 11 Read as 0 should be written with 0 The bits in the Channel Reset Request Register are used to reset DMA
150. fineon CIC751 Introduction Table 1 1 Pin Definitions and Functions cont d Symbol Pin Port I O Function AIN15 14 Analog Input 15 P1 15 VAREF 9 Analog Reference Voltage VAGND 10 Analog Ground TCLK SR3 17 0 P0 0 MLI Transmit Channel Clock Output 1 Event output line 3 TREADY SR4 19 MODE 0 PO 1 MLI Transmit Channel Ready Input MODE 1 Event request output line 4 TVALID SCLK 20 0 2 MLI Transmit Channel Valid Output 1 SPI Serial Channel Clock TDATA MRST 21 MLI Transmit Channel Data Output 1 SPI Master Receive Slave Transmit RCLK 22 0 P0 4 MLI Receive Channel Clock Input 1 GPIO RREADY RDY 23 0 5 MLI Receive Channel Ready Output 1 SSC Ready Signal RVALID SLS 24 P0 6 MLI Receive Channel Valid Input 1 SSC Select Slave RDATA MTSR 25 MODE 0 P0 7 MLI Receive Channel Data Input 1 SPI Master Transmit Slave Receive User Manual 1 6 V 1 0 2005 11 Introduction V 1 0 Cinfineon Introduction Table 1 1 Pin Definitions and Functions cont d Symbol Pin Port I O Function MODE 26 Interface Selection P0 8 Pin MODE selects whether the on chip MLI or SSC are used to access the CIC751 device 0 On chip MLI 1 On chip SSC Event request
151. gInput CHOn_REQI6 selected 111 lnput selected BLKM 18 16 Block Mode BLKM determines the number of DMA moves executed during one DMA transfer 000 DMA transfer has 1 DMA move 001 DMA transfer has 2 DMA moves 010 DMA transfer has 4 DMA moves 011 DMA transfer has 8 DMA moves 100 One DMA transfer has 16 DMA moves OthersReserved do not use these combinations See also Figure 3 11 on Page 3 22 RROAT 19 rw Reset Request Only After Transaction RROAT determines whether or not the TRSR CHOn transfer request state flag is reset after each transfer 0 TRSR CHOn is reset after each transfer A transfer request is required for each transfer 1 TRSR CHOn is reset when TCOUNT 0 after a transfer One transfer request starts a complete DMA transaction User Manual 3 40 V 1 0 2005 11 DMA V1 0 Cinfineon CIC751 Direct Memory Access Controller Field Bits Type Description CHMODE 20 rw Channel Operation Mode CHMODE determines the reset condition for control bit TRSR HTREOn of DMA channel On 0 Single Mode operation is selected for DMA channel On After a transaction DMA channel On is disabled for further hardware requests TRSR HTREOn is reset by hardware TRSR HTREOn must be set again by software for starting a new transaction 1 Continuous Mode operation is selected for DMA channel On After a transaction bit TRSR HTREOn rema
152. gister 0000 04A0 Page 3 42 1 DMA Channel 1 Control Register 0000 04A4 Page 3 39 Memory 7 Register 0000 04A8 l DMA_ADRCRO1 DMA Channel 1 Address Control 0000 04AC Page 3 43 Register SADRO1 DMA Channel 1 Source Address 00000480 Page 3 47 Register DMA_DADR01 DMA Channel 1 Destination 0000 04B4 Page 3 48 Address Register User Manual 8 7 V 1 0 2005 11 Regs V1 0 1 751 Cinfineon Register Overview Table 8 3 DMA Kernel Registers cont d Register Register Long Name Address Description Short Name see 5 DMA Channel 1 Shadow Address 0000 04B8 3 49 Register DMA CHSR02 DMA Channel 2 Status Register 0000 04C0 Page 3 42 CHCRO02 Channel 2 Control Register 0000 04C4 Page 3 39 8 DMA Memory 8 Register 0000 0468 l ADRCRO2 Channel 2 Address Control 0000 04CC 3 43 Register DMA_SADR02 DMA Channel 2 Source Address 0000 0400 Page 3 47 Register DADRO2 DMA Channel 2 Destination 00000404 Page 3 48 Address Register SHADRO2 Channel 2 Shadow Address 0000 04D8 Page 3 49 Register 5 Channel 3 Status Register 0000 04E0 Page 3 42 DMA Channel Control Register 0000 04E4 Page 3 39 9 Memory 9 Regi
153. h channel 0 without requiring software to change the channel number After starting the converter through bit ADC_CON ADST or ADC_CTRO ADST the busy flag ADC_CON ADBSY or ADC_CTRO ADBSY will be set and the channel specified in bit field ADC_CON ADCH or ADC CTRO ADCH will be converted After the conversion is completed an interrupt request trigger ADC event 0 is generated that can be used to trigger the DMA and the converter will automatically start a new conversion of the next lower channel After each completed conversion an interrupt trigger is generated After conversion of channel 0 the current sequence is complete In Single Conversion Mode the converter will automatically stop and clear bits ADC CON ADBSY or CTRO ADBSY and ADC CON ADST or ADC_CTRO ADST In Continuous Conversion Mode the converter will automatically start a new sequence beginning with the conversion of the channel specified in ADC_CON ADCH or ADC_CTRO ADCH When bit ADC_CON ADST or ADC_CTRO ADST is cleared by software while a conversion is in progress the converter will complete the current sequence including conversion of channel 0 and then stop and clear bit ADC_CON ADBSY or ADC_CTRO ADBSY 3 2 1 0 3 2 L T T T T T L Y Ya 1 Write ADC_DAT x 3 2 1 0 3 M P pP LP L T Generate Interrupt Request ADC_DAT Full Read of ADC_DAT Channnel 0 Result of Channel 3 2 1 Result Lost
154. h the start of the next DMA transaction 10 Shadow address register used for destination address buffering When writing to DADROn the address is buffered in SHADROn and transferred to DADROn with the start of the next DMA transaction 11 Reserved In case of SHCT 01g or 105 SHCT must not be changed until the next DMA transaction has been started 0 31 18 Reserved Read as 0 should be written with O wt Table 3 5 shows the offset values that are added or subtracted to from a source or destination address register after a move Bit field SMF and bit INCS determine the offset value for the source address Bit field DMF and bit INCD determine the offset value for the destination address User Manual 3 45 V 1 0 2005 11 DMA V1 0 Cinfineon Table 3 5 CIC751 Direct Memory Access Controller Address Offset Calculation Table CHCROn CHDW 00 8 bit Data Width CHCROn CHDW 01 16 bit Data Width CHCROn CHDW 10 32 bit Data Width SMF INCS Address SMF 5 SMF INCS Address DMF INCD Offset DMF Offset DMF INCD Offset 000 0 1 000 0 2 0000 0 4 1 1 1 2 1 4 0015 0 2 001 0 4 001 0 8 1 2 1 4 1 8 010 0 4 010 O 8 010 0 16 1 4 1 8 1 16 0115 0 8 011 O 16 011 0 32 1 8 1 16 1 32
155. hannel Trigger 4 Register 840 Reset Value 0000 0000 SCU CHTR5 SCU Channel Trigger 5 Register 844p Reset Value 0000 0000 SCU_CHTR6 SCU Channel Trigger 6 Register 848 Reset Value 0000 0000 SCU_CHTR7 SCU Channel Trigger 7 Register 84C Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 8 7 6 5 4 3 2 1 0 0 TF RF 0 TRSEL r rh rh r rw User Manual 2 22 V 1 0 2005 11 STCU V 1 0 Cinfineon CIC751 System and Control Unit SCU Field Bits Type Description TRSEL 2 0 rw Trigger Selection This bit field defines the trigger source for the DMA channel n 000 Aconstant 0 is selected TF and HF are cleared 001 ADC event 0 is selected as trigger source 010 event 1 is selected as trigger source 011 Doorbell event 0 is selected as trigger source 100 Doorbell event 1 is selected as trigger source 101 External trigger input 0 is selected as trigger source 110 External trigger input 0 is selected as trigger source 111 Reserved do not use this combination RF rh Ready Flag This bit indicates if the MLI is ready for the next transfer 0 The MLI is not yet ready for a new transfer former transfer not yet finished 1 The MLI is ready for a new transfer former transfer is finished TF rh Trigger Flag This bit indicates that a channel trigger request is pending 0 No channel trigger request is pending 1 A channel trigger re
156. he Move Engine handles the execution of a DMA transfer that has been detected by the Channel Arbiter to be the next one The Move Engine requests the required buses and loads or stores data according to the parameters of a DMA transfer It is able to wait if a targeted bus is not available the Move Engine transfer transaction cannot be interrupted and always get finished This means that a DMA transfer which can also be composed of several data moves read move and write move cannot be interrupted by a transfer of another DMA channel After a DMA transfer is finished the Move Engine will send back the actualized address register information to the related DMA channel Possible error conditions are also reported DMA Channels 0n of Sub Block 0 DMA Channel Arbiter Move Engine 0 Transaction Control Unit 0 Bus Switch MCA06161 Figure 3 14 Transaction Control Engine User Manual 3 25 V 1 0 2005 11 DMA V1 0 CIC751 3 3 Module Kernel Registers Figure 3 15 and Table 3 2 show all registers associated with the DMA Controller Kernel All DMA kernel register names described in this section are also referenced in other parts of the 751 User Manual by the module name prefix Direct Memory Access Controller DMA Registers Overview Channel Control Status Registers General Control Status Registers Move Engine Registers MESR MEOR MEOPR
157. he control of DMA transfer triggers see Chapter 3 1 This mechanism can be used to create a sensitivity level for the start of the block ADG conversion result data download to the host controller for Auto Scan conversions 6 7 32 Stimulate SRn Pins The status valid bit of the extended result register that is monitored by a doorbell channel can be forwarded to an SRn pin This offers an additional opportunity for supervision of the extended result registers Note For information about routing a valid bit to an SRn pin see Chapter 2 5 3 1 User Manual 6 18 V 1 0 2005 11 ADC V1 0 Cinfineon er The Analog Digital Converter 6 8 ADC Registers Table 6 5 summarizes all ADC registers The base address of the ADC is 0000 1000 A register address is computed by adding the base address to the register offset address Table 6 5 Registers Overview Register Register Long Name Offset Page Short Name Address Number CON Control Register 10 Page 6 21 CON Control 1 Register 12 4 Page 6 23 Control 0 Register 24 Page 6 24 CTR2 Control 2 Register 20 Page 6 25 ADC ADC Injection Control 2 Register 22 Page 6 26 CTR2IN DAT Result Register 30 Page 6 27 DAT2 ADC Result 2 Register 32 Page 6 27 ADC ADC Extended Result 0 View A Register 100 6 30 RESA0 ADC_ ADC Extended Result
158. helps avoid bus contention problems and reduces the need for hard wired hand shaking or slave select lines The open drain output feature can be selected for pin MRST via bit field PO IOCRO PC3 5 4 1 Connecting 2 or more CIC751 SSC Slaves to 1 Host If more than one slave is connected to an SSC master only one of them may be selected at a time The master enables one of the connected slaves with the associated slave select output signals The other output signals of the master MTSR and SCLK are broadcast and connected to each slave The output signals of the slaves MRST and RDY which are inputs of the master must be activated by the selected slave and must be deactivated by all other slaves In this way it is possible to directly connect the incoming signals at the master s input terminal The deactivation of the outputs MRST and RDY of the deselected slaves is accomplished by deactivating the output stage on the associated pads This deactivation takes place if MODE 1 and SLS 1 i e SSC is selected and slave is not selected User Manual 5 23 V 1 0 2005 11 SSC 1 0 Cinfineon Synchronous Serial Interface SSC Two additional bit fields are defined PC3B in register for pin P0 3 and PC5B in register P0_IOCR4 for pin P0 5 If the upper condition is true then the new bit fields PC3B and PC5B define the GPIO port behavior otherwise the regular PC3 and PC5 define the GPIO port behavior These new bit fields
159. hould be written with O ADC INRES ADC Input Result Reg ister 31 30 29 28 27 26 180 Reset Value 0000 0000 25 24 23 22 21 20 19 18 17 16 11 10 9 8 7 6 5 4 3 2 1 0 CHNR RESULT w Ww Field Bits Type Description RESULT 11 0 Conversion Result This bit field updates both bit fields for the registers RESAn RESULT RESBn RESULT n is equal the value written to CHNR User Manual 6 33 V 1 0 2005 11 ADC V1 0 Cinfineon CIC751 The Analog Digital Converter Field Bits Type Description CHNR 15 12 Channel Number This bit field defines the extended result registers that are updated 0 31 15 Reserved Read as 0 should be written with 0 ADC_RESV ADC Result Valid Register 188 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHN CHN CHN CHN CHN CHN CHN CHN CHN CHN CHN CHN 15V 14V 13V 12V 11V 10V 9V 7 5 AV 2V V OV rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh Field Bits Type Description CHNnV n rh Channel n Valid Status n 0 to 15 This bit indicates that the result has been written with a new value since the last read from this location It becomes set wi
160. human life they fail it is reasonable to assume that the health of the user or other persons may be endangered 1 751 Companion Cinfineon Never stop thinking CIC751 CONFIDENTIAL Revision History 2005 11 V 1 0 Previous Version None Page Subjects major changes since last revision We Listen to Your Comments Any information within this document that you feel is wrong unclear or missing at all Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to mcdocu comments infineon com D lt Template mc a5 um tmplt fm 5 2005 10 01 Cinfineon Table Of Contents Table Of Contents 1 Introduction 1 1 1 1 1 1 1 2 Features teen eee wank 1 2 1 2 1 Detailed Features 1 2 1 2 1 1 dg usay uh hb er abe 1 3 1 2 1 2 Dau 1 4 1 2 1 3 SSO Ziya ahua ghi taa un Wa 1 4 1 3 Signal Description 1 5 2 System and Control Unit SCU 2 1 2 1 Reset Control Block 2 1 2 1 1 Power On Reset 2 1 2 1
161. ic calibration of the ADC after a power on reset e Post calibration performs one small calibration step after each conversion Reset Calibration After a reset a thorough power up calibration is performed automatically to correct gain and offset errors of the A D converter To achieve the best calibration results the reference voltages as well as the supply voltages must be stable during the power up calibration During the calibration sequence a series of calibration cycles is executed where the step width for adjustments is reduced gradually The total number of executed calibration cycles depends on the actual properties of the respective ADC module The maximum duration of the power up calibration is 11 696 cycles of the basic clock fac Status flag CON1 CAL is set as long as this power up calibration takes place Post Calibration After each conversion a small calibration step can be executed For 8 bit and 10 bit conversions post calibration is not mandatory in order not to exceed the total unadjusted error TUE specified in the data sheet Post calibration can be disabled by setting bit CALOFF in register When disabled the post calibration cycles are skipped which reduces the total conversion time Note Calibration may be disabled only after the reset calibration is completed 6 4 Multiplexer Test Mode For analog channel 0 a Multiplexer Test Mode MTM is also available This function is controlled
162. infineon Direct Memory Access Controller 3 2 DMA Controller Kernel Description The DMA Controller of the CIC751 transfers data from data source locations to data destination locations without intervention of other on chip devices One data move operation is controlled by one DMA channel Eight DMA channels are provided in one DMA Sub Block DMA Controller DMA Block DMA Channels Transaction Control Unit DMA_BlockDiag Figure 3 3 DMA Block Diagram User Manual 3 8 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller 3 2 1 Features The DMA controller has the following features 8 independent DMA channels 8 DMA channels in the Sub Block Up to 8 selectable request inputs per DMA channel 2 level programmable priority of DMA channels within the DMA Sub Block Software and hardware DMA request Hardware requests by selected on chip peripherals and external inputs Buffer capability for move actions on the buses at least 1 move per bus is buffered Individually programmable operation modes for each DMA channel Single Mode stops and disables DMA channel after a predefined number of DMA transfers Continuous Mode DMA channel remains enabled after a predefined number of DMA transfers DMA transaction can be repeated Programmable address modification Full 32 bit addressing capability of each DMA channel 4 Gbyte address range Support of circu
163. ins set CHDW 22 21 Channel Data Width CHDW determines the data width for the read and write moves of DMA channel On 00 8 bit byte data width for moves selected 01 16 bit half word data width for moves selected 10 32 bit word data width for moves selected 11 Reserved CHPRIO 28 rw Channel Priority CHPRIO determines the priority of DMA channel On for the channel arbitration of Move Engine 0 0 DMA channel has a low channel priority 1 DMA channel has a high channel priority 0 25 24 30 Reserved Read as 0 have to be written with 0 0 12 9 23 27 26 29 31 Reserved Read as 0 should be written with 0 User Manual DMA V1 0 3 41 V 1 0 2005 11 Cinfineon Direct Memory Access Controller The Channel Status Register contains the current transfer count and a pattern detection compare result CHSROn n 0 7 Channel Status Register 480 n 20 Reset Value 0000 0000 30 29 28 27 26 25 24 2 22 21 20 19 18 17 16 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 TCOUNT r rh Field Bits Type Description TCOUNT 8 0 rh Transfer Count Status TCOUNT holds the actual value of the DMA transfer count for DMA channel On TCOUNT is loaded with the value of CHCROn TREL when TRSR CHOn becomes set and TCOUNT 0 After each transfer TCOUNT is decremented by
164. ion 1 Introduction CIC751 is a companion IC for the Infineon AUDO NG family of 32 bit microcontrollers The major function of the 751 is to provide the AUDO NG 32 bit microcontrollers with the capability of a 5 V Analog to Digital Converter ADC The interconnection of the CIC751 and the microcontroller is accomplished via either the Micro Link Interface MLI or the Synchronous Serial Interface SSC Internal operations of the CIC751 are supported by the very flexible on chip DMA controller 1 1 Overview Figure 1 1 provides the block diagram of the CIC751 companion chip This design allows access to the ADC by the host CPU without sacrificing any of the features of the ADC This can be achieved because all registers of the ADC are mapped to the on chip bus This bus can be accessed via one of the two serial interfaces Selection of the interface is made via pin MODE which can be directly connected to the supply voltage or via pull up down resistors The bus domain is completely separated from the address domain on the CPU chip The addresses of all modules on the companion chip are 32 bit addresses Transactions between the CPU and the SSC are executed with the SSC transmission protocol transactions between the MLI and the CPU use the MLI transmission protocol Each transaction via any of the two serial interfaces is defined by address data data width and type of frame The address from which data is read or written to
165. ion User Manual 5 10 V 1 0 2005 11 SSC 1 0 Cinfineon Synchronous Serial Interface SSC The default level of RDY is 0 If a master selects the CIC751 for an SSC communication SLS is asserted 0 and RDY is changed to asserted 1 This allows the master to start with the transmission of the transaction header the first 16 SCLK cycles Meanwhile RDY is de asserted again to be ready for the next use and to signal the master that the first SCLK cycle was received Using the first address the first read data is fetched and is ready for transmission This is indicated by the assertion of RDY again Thereafter the master can generate the next 16 SCLK required for the slave to transmit the 16 bit read data With the first cycle of SCLK RDY is de asserted again to be ready for the next use and to signal the master that the first SCLK cycle was received and the transmission of the first read data is started In parallel with the transmission of the read data the next read is fetched and prepared for transmission either from address ADDR INCE 0 or from address ADDR 2 INCE 1 This sequence is repeated until SLS is de asserted 17 by the master This automatic read process is optimized for several consecutive read data transfers within one communication block Therefore the next to transmit read data is prefetched during the transmission of the currently processed data This leads to a minimum dead time between the transmi
166. ion calculation see Page 4 17 and Page 4 38 0 No address prediction is possible A Write Offset and Data Frame or a Discrete Read Frame are used for transmission 1 Address prediction is possible An Optimized Write Frame or an Optimized Read Frame are used for transmission 31 17 Reserved Read as 0 should be written with 0 User Manual MLI V1 0 4 65 V 1 0 2005 11 Cinfineon Micro Link Interface MLI 4 3 2 4 Transmitter Command Register The Transmitter Command Register MLI TCMDR contains the command codes that are used during Command Frame transmission see Page 4 30 Each time one of the MLI_TCMDR CMDPx bit fields is written a Command Frame transmission is triggered Therefore only byte write accesses may be used when writing to MLI TCMDR only one Command Frame can be sent at a time MLI TCMDR MLI Transmitter Command Register 2284 Reset Value 0000 0000 SMS UNES NC SEA NE C EE NN DUE 0 0 2 7 w r W z 2 Field Bits Type Description CMDPO 3 0 Command Code for Pipe 0 This bit field contains the command code related to Pipe 0 The Pipe 0 command codes allow an activation pulse of one of the MLI Requests in the Remote Controller 0001 Activate MLI Request 0 0010 Activate MLI Request 1 0011 Activate MLI Request 2 0100 Activate MLI Request 3 else no action
167. is bit determines the polarity of RCLK 0 Non inverted polarity for RCLK selected RCLK is at 0 level in passive state 1 Inverted polarity for TCLK selected RCLK is at 1 level in passive state RCE 28 Receiver Clock Enable This bit enables the MLI receiver input clock RCLK 0 RCLK signal is disabled always at 0 level 1 RCLK signal is enabled and driven by RCLK according to the settings of RCS and RCP RDS 30 29 rw Receiver Data Selector This bit field determines whether the MLI is connected to pin RDATA or not 00g is not connected to the MLI Oig RDATA is connected to the MLI 10g RDATA is not connected to the MLI 116 RDATA is not connected to the MLI RDP 31 Receiver Data Polarity This bit determines the polarity of RDATA 0 Non inverted polarity for RDATA selected RDATA is passive if 0 RDATA is active if 1 1 Inverted polarity for RDATA selected RDATA is passive if 1 RDATA is active if O User Manual MLI V1 0 4 57 V 1 0 2005 11 Cinfineon Micro Link Interface Field Bits Type Description 0 4 2 Reserved 7 6 Should be written with 0 18 21 20 User Manual 4 58 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI 4 3 2 MLI Transmitter Registers 4 3 2 1 Transmitter Control Register Transmitter Control Register MLI_TCR includes transmitter related control bits and bit fiel
168. is related to the address domain The data width may be 8 16 or 32 bits for the MLI and 16 bits for the SSC The ADC and the MLI may send request triggers to the DMA Controller User Manual 1 1 V 1 0 2005 11 Introduction V 1 0 Cinfineon Introduction MLI SSC PORTS Bus Switch DMA BLOCK_DIAGRAM Figure 1 1 751 Block Diagram 1 2 Features This section provides a high level description of the features on the CIC751 e 5 Analog to Digital Converter e 16 analog input channels e Internal low power oscillator Slave SPI SSC interface operating on 5 V or 3 3 V e MLI Interface operating on 5 V or 3 3 V Maximum system frequency of 40 MHz Low power design Single power supply concept design for pad and core supply e Seperated ADC supply Input and output pins with 3 3 V and 5 0 V Flexible clocking concept Crossbar bus architecture 1 2 1 Detailed Features The following sections provide detailed information about each of the on chip modules User Manual 1 2 V 1 0 2005 11 Introduction V 1 0 Cinfineon Introduction 1 2 1 1 ADC The CIC751 provides an Analog Digital Converter with 8 bit or 10 bit resolution and sample amp hold circuit on chip An input multiplexer selects between up to 16 analog input channels either via software Fixed Channel Modes or automatically Auto Scan Modes To fulfill most requirements of embedded control applications the ADC suppo
169. it Error Flag 0 No effect 1 Bit SSC_STAT TE is cleared Bit is always read as 0 CLRRE 9 w Clear Receive Error Flag 0 No effect 1 Bit SSC_STAT RE is cleared Bit is always read as 0 CLRPE 10 w Clear Phase Error Flag 0 No effect 1 Bit SSC_STAT PE is cleared Bit is always read as 0 SETTE 12 w Set Transmit Error Flag 0 No effect 1 Bit SSC_STAT TE is set Bit is always read as 0 SETRE 13 w Set Receive Error Flag 0 No effect 1 Bit SSC_STAT RE is set Bit is always read as 0 SETPE 14 w Set Phase Error Flag 0 No effect 1 Bit SSC_STAT PE is set Bit is always read as 0 User Manual 5 19 V 1 0 2005 11 SSC 1 0 Cinfineon Synchronous Serial Interface SSC Field Bits Type Description 0 11 15 w Reserved Read as 0 have to be written with 0 0 7 0 r Reserved 31 16 Read as 0 should be written with 0 SCU_ERRCUM SCU Cumulative Error Register 85C Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rwh rwh rwh rwh Field Bits Type Description TE 8 rwh Transmit Error Flag 0 No error 1 Transfer starts with transmit buffer not being updated This bit is set in case of a Transmit Error event see Chapter 5 2 4 This bit has to be cleared by software RE 9 rwh Receive Error Flag 0 No error 1 Reception completed before the receive buffer was read This bit is set in case of a Receive Error event see Chapter 5
170. it fields n 0 7 DMA Channel Control Register 484 n 20 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CH I 0 0 0 on 0 oL 0 CHDW MO RRD BLKM PRIO AT l l DE l r rw r rw r rw r rw rw rw rw PRSEL 0 TREL rw r rw Field Bits Type Description TREL 8 0 rw Transfer Reload Value This bit field contains the number of DMA transfers for s DMA transaction of DMA channel On This 9 bit transfer count value is loaded into CHSROn TCOUNT atthe start of a transaction when TRSR CHOOn becomes set and CHSROn TCOUNT 0 TREL can be written during a running DMA transaction because TCOUNT will be updated decremented during the DMA transaction If TREL 0 or if TREL 1 TCOUNT will be loaded with 1 when a new transaction is started at least one DMA transfer must be executed per DMA transaction User Manual 3 39 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller Field Bits Type Description PRSEL 15 13 rw Peripheral Request Select This bit field controls the hardware request input multiplexer of DMA channel 0n see Figure 3 7 on Page 3 15 000 Input CHOn_REQIO selected 001glnput selected 010glnput CHOn_REQI2 selected 011glnput REQIS selected 100glnput REQIA selected 1018 CHOn REQIS selected 110
171. itten with O 4 3 2 2 Transmitter Status Register The Transmitter Status Register MLI TSTATR contains transmitter specific status information MLI TSTATR MLI Transmitter Status Register 2144 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 NAE APN RDC r rh rh rh Th Field Bits Type Description RDC 4 0 rh Ready Delay Counter This bit field counts TCLK periods after the end of a frame transmission When the TVALID signal goes to low level RDC is cleared to zero and starts counting up the TCLK clock periods until a TREADY high level is detected APN 6 5 rh Answer Pipe Number This bit field is written by the MLI receiver with the Pipe Number of a received read frame APN is used by an Answer Frame that is transmitted as response to the read frame 00 Pipe 0 is used in Answer Frame 01 Pipe is used in Answer Frame 10 Pipe2is used in Answer Frame 11 Pipe 3 is used in Answer Frame User Manual 4 62 V 1 0 2005 11 MLI V1 0 Cinfineon CIC751 Micro Link Interface MLI Field Bits Type Description PE rh Parity Error Flag This bit is set if a transmitter parity error condition is detected by the transmitter after a frame transmission PE is cleared by hardware when a frame has been transmitted without a parity error see Page
172. itter parity error interrupt event has been detected The service request output that is activated is defined by MLI TINPR PTEIPx TEI 9 rh Time Out Error Flag This flag becomes set if a time out error interrupt event has been detected The service request output that is activated is defined by MLI TINPR PTEIPx User Manual 4 85 V 1 0 2005 11 MLI V1 0 Cinfineon CIC751 Micro Link Interface MLI Field Bits Type Description 0 31 10 A Reserved Read as 0 should be written with O 4 3 4 8 Transmitter Interrupt Node Pointer Register The Transmitter Interrupt Node Pointer Register MLI TINPR contains the interrupt node pointers for the MLI transmitter interrupts events MLI TINPR MLI Transmitter Interrupt Node Pointer Register 2 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 CFSIP r rw r rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O 0 NFSIP3 0 NFSIP2 0 NFSIP1 0 NFSIP0 r rw r rw r rw r rw Field Bits Type Description NFSIP0 2 0 rw Normal Frame Sent in Pipe 0 Interrupt Pointer This bit field determines which MLI Request x becomes active when a Normal Frame sent in Pipe 0 interrupt occurs 000 MLI RequestO is selected 001 MLI Request is selected 010 MLI Request2 is selected 011 MLI Request3 is selected 100 Reserved
173. ived in the Local Controller the software must read it As long as at least one byte of this data has not yet been read out only one more MLI frame can be received stored in a waiting position to be executed Then the reception of more frames is blocked by a non acknowledge error If the received data has been read out frame execution and reception continue normally 4 2 1 5 Command Frame Command Frames transmit a command e g setup information User Manual 4 30 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI Local Controller Remote NLI Controller MLI Transmitter Ready TCMDR CMDPx is written byte write TRSTATR CV 1 MLI Receiver Ready Send Command Frame of pipe x x Code RREADY 1 Parity check amp acknowledge frame Pipe 0 generate interrupt at SR 3 0 RISR IC 1 Pipe 1 write RCR DPE Pipe 2 set dear RCR MOD or clear TRSTATR RP 3 0 or activate BRKOUT Pipe 3 write command code into TRSTATR CV 0 TISR CFSIx 1 Command Frame Sent in Pipe x Interrupt Y 0 Command Frame Code Interrupt Pipe x RISR CFRIx 1 Command Frame Received Interrupt I MCA05889_M Figure 4 21 Command Frame Transaction Flow User Manual 4 31 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI Local Controller The transmission of a Comma
174. l 5 Source Address 0000 0530 Page 3 47 Register DADRO05 DMA Channel 5 Destination 0000 0534 Page 3 48 Address Register SHADRO5 Channel 5 Shadow Address 0000 0538 Page 3 49 Register DMA CHSR06 DMA Channel 6 Status Register 0000 0540 Page 3 42 DMA Channel 6 Control Register 00000544 Page 3 39 MEM 12 Memory 12 Register 0000 0548 l ADRCRO6 Channel 6 Address Control 0000054 Page 3 43 SADRO6 Channel 6 Source Address 0000 0550 Page 3 47 Register DADRO06 DMA Channel 6 Destination 0000 0554 Page 3 48 Address Register SHADRO06 DMA Channel 6 Shadow Address 0000 0558 Page 3 49 Register 5 07 Channel 7 Status Register 0000 0560 Page 3 42 7 DMA Channel 7 Control Register 00000564 3 39 Memory 13 Register 0000 0568 ADRCRO7 Channel 7 Address Control 000056 Page 3 43 SADRO 7 DMA Channel 7 Source Address 0000 0570 3 47 DADRO7 Channel 7 Destination 0000 0574 Page 3 48 Address Register User Manual 8 9 V 1 0 2005 11 Regs V1 0 1 751 Cinfineon Register Overview Table 8 3 DMA Kernel Registers cont d Register Register Long Name
175. l is disabled always at 0 level 1 TREADY signal is enabled and driven by TREADY according to the settings of TRS and TRP TCE Transmitter Clock Enable This bit enables the module output signal TCLK 0 TCLK is disabled and remains at passive level as selected by TCP 1 TCLK is enabled and driven according to the setting of TCP TCP Transmitter Clock Polarity This bit determines the polarity of the module output clock signal TCLK 0 Non inverted polarity for TCLK selected is driving a 0 when it is passive 1 Inverted polarity for TCLK selected TCLK is driving a 1 when it is passive User Manual MLI V1 0 4 55 V 1 0 2005 11 Cinfineon CIC751 Micro Link Interface MLI Field Bits Type Description TDP 14 rw Transmitter Data Polarity This bit determines the polarity of the module output clock signal TDATA 0 TDATA is directly driven by MLI transmitter output signal TDATA non inverted 1 TDATA is directly driven by the inverted MLI transmitter output signal TDATA RVE Receiver Valid Enable This bit enables the MLI receiver input signal RVALID 0 RVALID signal is disabled always at 0 level 1 RVALID signal is enabled and driven by RVALID according to the settings of RVS and RVP RRS 17 16 rw Receiver Ready Selector This bit field determines whether RREADY is driven by the MLI receiver or is tied to passive level according to the s
176. lar buffer addressing mode Programmable data width of DMA transfer transaction 8 bit 16 bit or 32 bit Register set for each channel Source and destination address register Channel control and status register Transfer count register User Manual 3 9 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller 3 2 2 Definition of Terms Some basic terms must be defined for the functional description of the DMA controller DMA Move A DMA move is an operation that always consists of two parts 1 A read move that loads data from a data source into the DMA controller 2 A write move that puts data from the DMA controller to a data destination Within a DMA move data is always moved from the data source via the DMA controller to the data destination Data is temporarily stored in the DMA controller The data widths of read move and write move are always identical 8 bit 16 bit or 32 bit Data assembly or disassembly is not supported DMA Controller Data DMA Data Source j Destination DMA Move MCA06150 Figure 3 4 DMA Definition of Terms DMA Transfer A DMA transfer can be composed of 1 2 4 8 or 16 DMA moves DMA Transaction A DMA transaction is composed of several at least one DMA transfers The Transfer Count determines the number of DMA transfers within one DMA transaction Example 1024 word 32 bit wide transactions can be composed of 256
177. lear 0 No action 1 Clear MLI TISR TEIx 0 15 10 r Reserved 31 26 Read as 0 should be written with O User Manual 4 84 V 1 0 2005 11 MLI V1 0 Cinfineon i Micro Link Interface MLI 4 3 4 2 Transmitter Interrupt Register The Transmitter Interrupt Status Register MLI_TISR contains all of the interrupt request flags of the MLI transmitter These interrupt request flags can be cleared by software when writing the appropriate bits in the MLI_TIER register MLI TISR MLI Transmitter Interrupt Status Register 29Cj Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 41 10 9 8 7 6 5 4 3 2 1 0 CFS CFS 5 5 NFS 5 5 5 3 12 1 0 21 1 10 2 2 2 2 2 Field Bits Type Description NFSI0 0 rh Normal Frame Sent in Pipe x Flag NFSI1 1 This flag becomes set if a write or read frame has been NFSI2 2 correctly sent and acknowledged for Pipe x NFSI3 3 The service request output that is activated is defined by MLI TINPR NFSIPx CFSIO 4 rh Command Frame Sent in Pipe x Flag CFSI1 5 This flag becomes set if a Command Frame has been CFSI2 6 correctly sent and acknowledged for Pipe x CFSI3 7 The service request output that is activated is defined by MLI TINPR CFSIP PEI 8 rh Parity Error Flag This flag becomes set if a transm
178. locking mechanism is present 4 2 1 4 Answer Frame Please note that only one Answer Frame can be handled at a time No additional Read Frame should be requested while any MLI_TRSTATR RPx bit is set To ensure this a certain time out criterion has to be defined and handled by Local Controller software The Remote Controller should take care that no Answer Frame is delivered after the time out criterion has been detected e g by a software triggered Command Frame The lenoth of the time out depends on the application and has to be defined accordingly on a case by case base e g the transfer rates between Local Controller and Remote Controller etc have to be considered In the case a time out has been detected the Local Controller has to clear the TRSTATR RPx bit by writing 1 to MLI SCR CDVx a new Read Frame be started If no time out handling is supported Answer Frame data can be lost or corrupted Remote Controller The Answer Frame is the only frame sent from the Remote Controller to the Local Controller The transmitter part of the Remote Controller is used to generate the Answer Frame Every time the transmitter data read answer register MLI_TDRAR is updated in the Remote Controller the transmission of an Answer Frame is started and the following actions are triggered e StatusflagMLI_TRSTATR AV is set to trigger the transmission of an Answer Frame Status flag MLI TRSTATR AV is cleared after the Answer Frame has been fi
179. mable The separate supply for the ADC reduces interference with other digital signals The reference voltages must be stable during the reset calibration phase and during an entire conversion to achieve maximum accuracy The sample time as well as the conversion time are programmable so the ADC can be adjusted to the internal resistances of the analog sources and or the analog reference voltage supply User Manual 6 1 V 1 0 2005 11 ADC V1 0 Cinfineon The Analog Digital Converter Injection ADC_CIRQ Request ADC_EIRQ ANO MUX 8 10 bit Capacitive Conversion AN15 MCB05416_N Figure 6 1 Analog Digital Converter Block Diagram The ADC is implemented as a capacitive network using successive approximation conversion conversion consists of three phases During the sample phase the capacitive network is connected to the selected analog input and is charged or discharged to the voltage of the analog signal During the actual conversion phase the network is disconnected from the analog input and is repeatedly charged or discharged via V4ger during the steps of successive approximation After the optional post calibration phase to adjust the network to changing conditions such as temperature the result is written to the result register and an interrupt request is generated There are two sets of control data and status registers one set for Compatibility Mode and one set for
180. master does not know how much time system cycles is exactly consumed by the CIC751 to move the transmitted write data to the desired destination The amount of time depends on the frequency of the CIC751 and the currently active CIC751 register accesses performed by the DMA Therefore the RDY pin is introduced to show that the SSC interface is ready for the next part of the transmission RDY is asserted The RDY pin should be used by the master in the following way e f RDY changes from de asserted 0 to asserted 17 the master starts to generate 16 clock cycles for SCLK f RDY changes from asserted 17 to de asserted 07 the master takes no action User Manual 5 9 V 1 0 2005 11 SSC 1 0 Cinfineon Synchronous Serial Interface SSC The default level of RDY is 0 If a master selects the CIC751 for an SSC communication SLS is asserted 0 RDY is changed to asserted 1 This allows the master to start with the transmission of the transaction header the first 16 SCLK cycles Meanwhile RDY is de asserted again to be ready for the next use and to signal the master that the first SCLK cycle was received Using the first address the first write data is forwarded to the destination register This is indicated by the assertion of RDY again Thereafter the master can generate the next 16 SCLK required for the next write data to transmit With the first cycle of SCLK RDY is de asserted again to be ready for
181. maximum parity error counter of the transmitter MLI_TCR MPE determines the number of transmit parity error conditions that can be still detected until a transmitter parity error interrupt event is generated If a transmitter parity error condition is detected MLI TCR MPE is becoming 0 or while it is 0 a transmitter parity error interrupt event is generated by setting bit MLI TISR PEI and an interrupt is generated if enabled by MLI_TIER PEIE 1 After a transmitter parity error event occurred MLI TCR MPE be set again by software to a value greater 00015 Otherwise each additional transmitter parity error condition will generate an MLI Request User Manual 4 34 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI The transmitter parity error flag MLI TSTATR PE is cleared when a correct frame transmission and TREADY has been sampled with 1 within the ready delay time It can be cleared by software by writing a 1 to bit MLI SCR CTPE If for example each transmitter parity error condition should generate a transmitter parity error event should be set to 0001 The software can check for accumulated parity error conditions by reading MLI TCR MPE MLI TISR PEI for the status of the latest received frame it can check MLI TSTATR PE TCR MDP TREADY M Kk I W TVALID TDATA Dn parr error tran Figure 4 22 MLI Co
182. mmunication without Parity Error Indicator Transmitter View TCR MDP TREADY F TVALID n TDATA U Parr_error_trans Figure 4 23 Communication with Parity Error Indicator Transmitter View Remote Controller User Manual 4 35 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI The receiver always checks the parity bit of a received frame for even parity receiver parity condition is detected if the received parity bit does not match with the internally calculated If receiver parity error condition is found after the reception of a frame RREADY is immediately set to 1 otherwise RREADY is kept at 0 until a defined number of cycles as determined by bit field MLI RCR DPE delay for parity error has been elapsed Then RREADY is asserted high If a receiver parity condition is found the MLI receiver sets the parity error flag MLI RCR PE and additionally decreases the maximum parity error counter of the receiver MLI RCR MPE by 1 The maximum parity error counter MLI RCR MPE determines the number of receiver parity error conditions that can be still detected until the next receiver parity error event is generated If a receiver parity error condition is detected and MLI RCR MPE is becoming 0 or while it is already 0 a receiver parity error interrupt event is generated by setting bit MLI RISR PEI and an interrupt is generat
183. mote Controller The value of CMD indicates which function is controlled The coding of CMD and the control mechanisms depend on the product 11 Freely programmable software command Details about the Command Frame handling of the CIC751 are provided in Chapter 4 2 1 5 User Manual 4 13 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI 41 47 Answer Frame An Answer Frame is used by the Remote Controller to send 8 bit 16 bit or 32 bit wide data to the Local Controller The Answer Frame is the only frame that is transmitted within a logic Local Remote Controller assignment from the Remote Controller to the Local Controller It is the answer to Discrete Read Frame or an Optimized Read Frame that has been sent by the Local Controller to request data from the Remote Controller The Answer Frame contains the following parts Header The header starts with Frame Code FC 10g followed by the Pipe number PN The value of PN is taken from the read frame that has triggered the Answer Frame Read data field The read data field can be 8 16 or 32bits wide depending on the data width requested by the read frame that triggered the Answer Frame e Parity bit P Header 01234 1112 Header MM 01234 19 20 16 Bit Data 01234 36 37 32 Bit Data d answer frame Figure 4 12 Answer Frame Details about the Answer Frame handling of
184. n a transfer was initiated by the master shift clock becomes active but the transmit buffer TB of the slave was not updated since the last transfer This condition sets the error status flags STAT TE SCU_ERRCUM TE If a transfer starts while the transmit buffer is not updated the slave will shift out the old contents of the shift register which is normally the data received during the last transfer This may lead to the corruption of the data on the transmit receive line in Half duplex Mode open drain configuration if this slave is not selected for transmission Note A slave with push pull output drivers not selected for transmission will normally have its output drivers switched off However to avoid possible conflicts or misinterpretations it is recommended to always load the slave s transmit buffer prior to any transfer User Manual 5 14 V 1 0 2005 11 SSC 1 0 Cinfineon 5 3 CIC751 Synchronous Serial Interface SSC Register Descriptions Table 5 2 identifies all of the SSC registers The base address of the SSC is 0000 0900 A register address is computed by adding the base address to the register offset address Table 5 2 Registers Overview Register Register Long Name Offset Page Short Name Address Number SSC CON Register 10 Page 5 15 SSC STAT Statu
185. nd Frame is initiated by writing one of the four Pipe x related command code bit fields in register MLI TCMDR CMDPx triggering the following actions Status flag MLI TRSTATR CVx is set and the Command Frame transmission is started using x as Pipe number PN and the command code stored in MLI TCMDR CMDPx as parameter e MLI_TRSTATR CVx is cleared after the Command Frame has been finished and correctly acknowledged by the Remote Controller e Interrupt status flag TISR CFSIx is set and an MLI Request is generated if enabled by MLI TIER CFSIEx 1 Remote Controller Depending on the Pipe x related command code that is transmitted by a Command Frame different actions are triggered in the Remote Controller Table 4 6 describes the actions that are triggered by a Command Frame The received PN value is checked and the corresponding control actions are executed according to Table 4 6 e Independent of the received Pipe Number interrupt status flag MLI_RISR CFRIx is set and an MLI Request is generated if enabled by MLI RIER CFRIEx 1 If a Command Frame is received for Pipe 2 with command code 1111g the MLI Break Event is generated if enabled MLI RCR BEN 1 Table 4 6 Command Frame Actions for the Remote Controller PN CMD Command Description 00 0001 Generate Request 0 0010 Request 1 0011 Generate Request 2 0100 Generate Request 3
186. nd only send 1 s Because the data inputs and outputs are connected together a transmitting device will clock in its own data at the input pin MRST for a master device MTSR for a slave In this way any corruption is detected on the common data exchange line when the received data is not equal to the transmitted data User Manual 5 6 V 1 0 2005 11 SSC 1 0 Cinfineon Synchronous Serial Interface SSC Master Device 1 Transmit Device 2 Slave Shift Register Common Transmit Receive Device 3 Slave 04509 Figure 5 3 SSC Half Duplex Configuration User Manual 5 7 V 1 0 2005 11 SSC 1 0 Cinfineon Synchronous Serial Interface SSC 5 2 2 Operating the SSC The following sections explain how the SSC is best used for operation of the CIC751 The basic task of the SSC is to communicate with a host controller to which the CIC751 is connect Therefore the CIC751 SSC always operates as a slave within the serial communication The communication requirements can be split into two categories Configuration of the CIC751 This requires write access from the host to the CIC751 to update the various control registers Transfer of the conversion result back to the host The conversion results need to be transferred back to the requesting host The CIC751 provides all required hardware support so that the conversion results can be communicat
187. ng to check for new data in view B This view B can be accessed when reading the second set of addresses The input register for the 16 result registers is INRES Any write access to this address will lead to an update of the corresponding result register The bit positions 15 12 of the written data are used as pointer to indicate the targeted result register All 16 valid bits of the different result registers RESBn are additionally accessible by a single status register RESV This enable the host to verify easily which result register has valid date and which not 6 7 3 Doorbell Mechanism The doorbell mechanism offers a monitoring system for the extended result registers Two doorbell channels are implemented each with an individual sensitivity level The sensitivity level can be configured to monitor one of the 16 extended result registers via ADC_DBCTR COMPO0 ADC_DBCTR COMPO The doorbell mechanism can be used to trigger either a DMA transfer or to stimulate an SRn pin 6 7 31 Trigger DMA Transfer If a extended result register that is monitored by a doorbell channel is updated via register INRES the doorbell channel generates a trigger that can be used to request an DMA transfer Note Please note that writing to register ADC INRES updates both views of a extended result register User Manual 6 17 V 1 0 2005 11 ADC V1 0 Cinfineon Analog Digital Converter Note For more information about t
188. nished and correctly acknowledged by the MLI receiver of the Local Controller An Answer Frame is sent through the same Pipe that was used by the read frame Local Controller If an Answer Frame has been received correctly and acknowledged the following actions are executed in the MLI receiver of the Local Controller The MLI TRSTATR RPx flag is cleared The received data is stored into the receiver data register MLI RDATAR If 8 data bits are received they are duplicated to all 4 bytes in MLI RDATAR If 16 data bits are received they are duplicated to both half words in MLI RDATAR The data width of the received data is written to bit field MLI RCR DW Thereceived Pipe Number x represents the answer Pipe Number and is stored in bit field MLI TSTATR APN e The information about the received frame type 11g for an Answer Frame is stored in bit field MLI RCR TF User Manual 4 29 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI Interrupt status flag RISR NFHI is set and an MLI Request is generated if enabled by RIER NFRIE 01g or 10g The data that has been previously requested from the Remote Controller by a read frame is available in MLI RDATAR f an Answer Frame is received while the corresponding MLI TRSTATR RPx bit is cleared the reception is declared as unintended and a discarded read answer event is generated see Page 4 43 Note If an Answer Frame has been correctly rece
189. nnected 0001p Pull down device connected 0010p Pull up device connected 0011p No pull device connected 0100p No pull device connected 0101p Pull down device connected 0110 Pull up device connected 0111 pull device connected 1000 Output Mode General purpose Output 1001p Direct input Output function ALT1 Push pull 10106 Output function ALT2 1011p Output function ALT3 1100p Output Mode General purpose Output 11015 Direct input Output function ALT1 Open drain 1110 Output function ALT2 1111 Output function ALT3 Port 0 Input Output Control 4 Register A14 Reset Value Table 7 5 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 7 0 PC6 0 rw r rw r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 5 PC4 0 rw rw rw r User Manual 7 9 V 1 0 2005 11 Parallel Ports V1 0 Cinfineon CIC751 Parallel Ports Field Bits Type Description PC4 7 4 rw Port Input Output Control Bit 4 see Table 7 4 PC5A 11 8 rw Port Input Output Control Bit 5 see Table 7 4 PC5 15 12 rw Port Input Output Control Bit 5 see Table 7 4 PC6 23 20 rw Port Input Output Control Bit 6 see Table 7 4 PC7 31 28 rw Port Input Output Control Bit 7 see Table 7 4 0 3 0 r Reserved 19 16 Read as 0 should be written with 0 27 24 Table 7 5 Register Reset Values Register Reset Type
190. nsfer Windows each with 64 KByte address range Remote Window A Remote Window defines an area in the address space of the Remote Controller Remote Window parameters base address and window size of the Remote Controller are programmable by the local microcontroller by MLI transfers Each Remote Window of a Remote Controller is related to specific pair of small and large Transfer Windows of the Local Controller via one Pipe User Manual 4 2 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI The Remote Windows are the logical data outputs of the MLI receiver If enabled the MLI module can automatically execute the requested data transfer to from the defined address location in the Remote Window If the automatic data handling is disabled the offset and the data are available in the MLI receiver Pipe A Pipe defines the logical connection between a Transfer Window in the Local Controller and the associated Remote Window in the Remote Controller The MLI module supports up to four Pipes Frame A frame is a contiguous set of bits forming a message sent by an MLI transmitter to an MLI receiver Normal Frame A Normal Frame is the collective term for the following frame types Write Offset and Data Frame Optimized Write Frame Discrete Read Frame Optimized Read Frame Answer Frame Copy Base Address Frame Offset The offset is defined by the accessed address location relative to the base
191. ock Using the RDY the CIC751 signals the master that SCLK can be activated The SSC can be selected from a master via the Slave Select input Line SLS SLS MTSR MRST SCLK SSC Control Block Registers CON STAT EFM Transmit Buffer Register TB 16 Bit Shift Register Receive Buffer Register RB 2 Internal Bus Figure 5 1 Synchronous Serial Channel SSC Block Diagram User Manual 5 2 V 1 0 2005 11 SSC 1 0 Cinfineon Synchronous Serial Interface SSC 5 2 1 SPI Communication Basics There are two principal modes of operation for SPI communication Full Duplex and Half Duplex 5 2 1 1 Full Duplex Operation The description in this section assumes that the SSC is used with software controlled bi directional GPIO port lines that have an open drain capability The various devices are connected through three lines The definition of these lines is always determined by the master The line connected to the master s data output pin MTSR Master Transmit Slave Receive is the transmit line the receive line is connected to its data input line MRST Master Receive Slave Transmit and the clock line is connected to pin SCLK Only the device selected for master operation generates and outputs the serial clock on pin SCLK All slaves receive this clock so their pin SCLK must be switched to input mode The output of the master s shift register is connected to the extern
192. ode operation Full duplex or half duplex operation Automatic pad control possible Flexible data format Programmable shift direction LSB or MSB shift first Programmable clock polarity Idle low or idle high state for the shift clock Programmable clock data phase Data shift with leading or trailing edge of the shift clock e Internal Master Function Access to the all addresses Automatic address handling Automatic data handling User Manual 1 4 V 1 0 2005 11 Introduction V 1 0 Cinfineon Introduction 1 3 Signal Description This section describes signals that connect off chip Table 1 1 gives a summery of the CIC751 external signals pins Table 1 1 Pin Definitions and Functions Symbol Pin Port I O Function AINO 35 Analog Input 0 P1 0 For this pin a Multiplexer Test Mode is available AIN1 36 Analog Input 1 P1 1 AIN2 37 Analog Input 2 P1 2 AIN3 38 Analog Input 3 P1 3 AIN4 1 Analog Input 41 P1 4 AIN5 2 Analog Input 5 P1 5 AIN6 7 Analog Input 6 P1 6 AIN7 8 Analog Input 7 P1 7 AIN8 5 Analog Input 8 P1 8 AIN9 6 Analog Input 9 P1 9 AIN10 3 Analog Input 10 P1 10 AIN11 4 Analog Input 111 P1 11 AIN12 11 Analog Input 121 P1 12 AIN13 12 Analog Input 13 P1 13 AIN14 13 Analog Input 141 P1 14 User Manual 1 5 V 1 0 2005 11 Introduction V 1 0 Cin
193. on and then stops There is no difference to the operation if ADC_CON ADST ADC_CTRO ADST was not cleared by software n Fixed Channel Continuous Conversion Mode the ADC finishes the current conversion and then stops This is the usual way to terminate this conversion mode e n Auto Scan Single Conversion Mode the ADC continues the auto scan round until the conversion of channel 0 is finished then it stops There is no difference to the operation if ADST was not cleared by software In Auto Scan Continuous Conversion Mode the ADC continues the auto scan round until the conversion of channel 0 is finished then it stops This is the usual way to terminate this conversion mode A restart of the ADC can be performed by clearing and then setting bit ADC_CON ADST or ADC_CTRO ADST This sequence will abort the current conversion and restart the ADC with the new parameters given in the control registers 6 2 4 Conversion Mode Selection Bit field ADC_CON ADM or ADC_CTRO ADM selects the conversion mode of the A D Converter as listed in Table 6 1 Table 6 1 A D Converter Conversion Mode ADM Description 00 Fixed Channel Single Conversion Mode 01 Fixed Channel Continuous Conversion Mode 10 Auto Scan Single Conversion Mode 11 Auto Scan Continuous Conversion Mode While a conversion is in progress the mode selection bit field ADC_CON ADM or ADC CTRO ADM and the channel selection bit field ADC CON ADCH A
194. onal Divider Mode The MLI receiver automatically adapts to the incoming receive shift clock signal RCLK The received baud rate is determined by the connected transmitter and has no direct relation to fsys except that it should not exceed fsys The frequency fy 15 generated by the fractional divider FDIV programmable by register MLI FDR receiver RCLK registers docks Figure 4 26 MLI Baud Rate Generation Normal Divider Mode In Normal Divider Mode MLI FDR DM 01g the fractional divider behaves like a reload counter addition of 1 that generates a clock fy on the transition from 3FFy to 000 MLI FDR RESULT represents the counter value FDR STEP defines the reload value In order to achieve fy fsys FDR STEP must be programmed with The output frequency in Normal Divider Mode is defined according the following equation f f x EM M MLI SYS 1024 STEP 4 1 Fractional Divider Mode If the Fractional Divider Mode is selected MLI FDR DM 105 the clock fy is derived from the input clock fsys by division of a fraction of STEP 1024 for any value of STEP from 0 to 1023 In general the Fractional Divider Mode allows to program the average clock frequency with a higher accuracy than in Normal Divider Mode In Fractional Divider Mode a clock pulse fy is generated based on the result of the addition MLI FDR RESULT MLI FDR STEP The frequency fy corresponds to the overflo
195. ontain the enable control bits that allow each interrupt source to be enabled disabled individually Some interrupt events are combined to one common interrupt Each interrupt is connected to exactly one of the four MLI interrupt node pointer One additional register the Global Interrupt Set Register MLI GINTR allows each MLI Request to be activated separately without setting the request flags of the interrupt sources This feature is sometimes helpful for software test purposes Interrupt Registers MLI interrupt sources are controlled by several registers see Table 4 7 and Page 4 83 The register name prefixes and indicate whether an interrupt register is assigned to the MLI transmitter or to the MLI receiver Table 4 7 Interrupt Registers Unit Registers with Request Flags Enable Bits Node Pointer Req Flag Clear Bits MLI Transmitter MLI TISR MLI TIER MLI TINPR MLI Receiver MLI RISR MLI RIER MLI RINPR Interrupt Request Compressor Interrupt control of the MLI uses an interrupt compressing scheme that allows great flexibility in interrupt processing Eleven interrupts six transmitter interrupts and four of the five receiver interrupts are directed via a interrupt node pointer to one of the four MLI Request One receiver interrupt the interrupt Command Frame interrupt has a special characteristic its node pointer is controlled by the received CMD value directly 4 2 5 Transmitter Interrupts
196. onverter through setting bit CON ADST CTRO ADST the busy flag CON ADBSY or CTRO ADBSY will be set and the channel specified in bit field CON ADCH ADC_CTRO ADCH will be converted After the conversion is complete an interrupt request trigger ADC event 0 is generated that can be used to trigger the DMA In Single Conversion Mode the converter will automatically stop and clears bits ADC CON ADBSY or ADC CTRO ADBSY and ADC CON ADST or ADC_CTRO0 ADST In Continuous Conversion Mode the converter will automatically start new conversion of the channel specified in bit field ADC_CON ADCH or ADC_CTRO ADCH An interrupt request trigger ADC event 0 is generated that can be used to trigger the DMA after each completed conversion When bit CON ADST CTRO ADST is cleared by software while conversion is in progress the converter will complete the current conversion and then stop and clear bit CON ADBSY CTRO ADBSY 6 2 7 Auto Scan Conversion Modes These modes are selected by programming the mode selection bit field CON ADM CTRO ADM to 10g single conversion or to 11 continuous conversion Auto Scan Modes automatically convert a sequence of analog channels beginning with the User Manual 6 6 V 1 0 2005 11 ADC V1 0 Cinfineon The Analog Digital Converter channel specified in bit field ADC_CON ADCH or ADC_CTRO ADCH and ending wit
197. ot updated Normal Divider Mode selected Fractional Divider Mode selected Fractional divider is switched off no output clock is generated RESULT is not updated User Manual MLI V1 0 4 49 V 1 0 2005 11 Cinfineon CIC751 Micro Link Interface MLI Field Bits Type Description RESULT 25 16 Result Value In Normal Divider Mode RESULT acts as reload counter addition 1 In Fractional Divider Mode this bit field contains the result of the addition RESULT STEP If DM is written with 01g 10g RESULT is loaded with 3FFH DISCLK rwh Disable Clock 0 Clock generation of fy 15 enabled according to the setting of bit field DM 1 Fractional divider is stopped Signal fy becomes inactive No change except when writing bit field DM 13 10 30 26 Reserved Read as 0 should be written with 0 User Manual MLI V1 0 4 50 V 1 0 2005 11 Cinfineon 4 3 1 2 CIC751 Set Clear Register Micro Link Interface MLI The Set Clear Register MLI SCR is a write only register that makes it possible to set or clear several status flags located in registers MLI TSTATR MLI TRSTATR and MLI RCR under software control Reading register MLI SCR always returns zero MLI SCR MLI Set Clear Register 2944 Reset Value 0000 0000 31 30 29 28 27 26
198. ould be written with 0 Set Reset Bit Conditions Table 3 4 Conditions to Set Reset the Bits TRSR HTRE0n HTREQ ECH0n HTREQ DCHOn Transaction Modification of Finishes for TRSR HTREOn Channel 0 0 0 unchanged 1 0 0 set X 1 X reset X X 1 reset 1 n Single Mode only In Continuous Mode the end of a transaction has no impact User Manual 3 33 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller The Error Status Register indicates if the DMA controller could not answer to a request because the previous request was not terminated ERRSR DMA Error Status Register 424 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 MLI LEC 0 ME0 ME0 0 ME0 DER SER r rh Th r rh rh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 TRL TRL TRL TRL TRL TRL TRL TRL 07 06 05 04 03 02 01 00 r rh rh rh rh rh rh rh rh Field Bits Type Description TRLOn n rh Transaction Transfer Request Lost of DMA n 0 7 Channel On 0 No request lost event has been detected for channel On 1 A new DMA request was detected while TRSR CHOn 1 request lost event This bit is reset by software when writing a 1 to CLRE CTLOn or by a channel reset writing CHRSTR CHOn 1 MEOSER 16 rh Move Engine 0 Source Error This bit is set whenever a Move Engine 0 error occurred during a source read m
199. ove of a DMA transfer ora request could not been serviced due to the access protection 0 No Move Engine 0 source error has occurred 1 A Move Engine 0 source error has occurred MEODER 17 rh Move Engine 0 Destination Error This bit is set whenever a Move Engine 0 error occurred during a destination write move of a DMA transfer request could not been serviced due to the access protection 0 No Move Engine 0 destination error has occurred 1 A Move Engine 0 destination error has occurred User Manual 3 34 V 1 0 2005 11 DMA V1 0 Cinfineon CIC751 Direct Memory Access Controller Field Bits Type Description LECMEO 26 24 rh Last Error Channel Move Engine 0 This bit field indicates the channel number of the last channel of Move Engine 0 leading to an Bus error that has occurred MLIO 27 rh MLI0 Error Source This bit is set whenever an Bus error occurred due to an action of MLI0 0 No bus error occurred due to MLI0 1 An bus error occurred due to MLI0 0 15 8 Ir Reserved 23 18 Read as 0 should be written with 0 31 28 User Manual 3 35 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller The Clear Error contains bits that make it possible to clear the Transaction Request Lost flags or the Move Engine error flags CLRE Clear Error Register 428 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
200. owledge Error TVALID Figure 4 15 Non Acknowledge Error MCT05876_M 4 1 7 Parity Generation For parity generation the number of transmitted bits with the value of 1 is counted over the header and the complete data field of a frame For even parity the parity bit is set if the result of a modulo 2 division of the elaborated number is 1 For error free MLI traffic even parity generation and checking is defined Details about the parity handling of the CIC751 are provided in Chapter 4 2 2 1 4 1 8 Address Prediction An address prediction mechanism supports communication between the MLI transmitter and the MLI receiver without sending address offset information in the frames This feature reduces the required bandwidth for MLI communication Both of the communication partners the MLI transmitter and the receiver are able to detect regular offset differences of consecutive window accesses to the same window The address prediction mechanism operates independently for each Pipe different prediction values can be handled in parallel for the different Pipes The MLI transmitter can compare the offset of each Transfer Window read or write access with the offset of the previous access to the same Transfer Window Between User Manual 4 17 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI accesses to a specific window other windows can be accessed without disturbing the prediction Offset diff
201. pe Transfer Window Areas and NLI Register Address Space Table 4 11 Transfer Window Areas Module Base Address End Address Note STWPipe0 00008000 0000 8 kBytes max STW Pipe 1 0000 A000 0000 8 kBytes max STW Pipe2 0000 C000 0000 DFFFy 8 kBytes max STW Pipe3 0000 E000 0000 8 kBytes max LTW Pipe 0 0001 0000 0001 64 kBytes max LTW Pipe 1 0002 0000 0002 64 kBytes max LTW Pipe 2 0003 0000 0003 64 kBytes max LTW Pipe 3 0004 0000 0004 64 kBytes max User Manual 4 94 V 1 0 2005 11 MLI V1 0 Cinfineon Synchronous Serial Interface SSC 5 Synchronous Serial Interface SSC This chapter describes how the SSC interface is used in the CIC751 5 1 Overview The SSC supports full duplex half duplex serial synchronous communication up to 10 5 40 MHz module clock The serial clock signal is received from an external master Slave Mode Data width shift direction clock polarity and phase are programmable This allows communication with SPI compatible devices Transmission and reception of data is double buffered A shift clock generator provides the SSC with a separate serial clock signal This chapter describes only the use of the SSC module as a slave because the CIC751 always operates as a slave to a host Features Slave Mode operation Full duplex or half duplex operation
202. plex Mode TEN 8 rw Transmit Error Enable 0 Ignore transmit errors 1 Check transmit errors REN 9 rw Receive Error Enable 0 Ignore receive errors 1 Check receive errors PEN 10 rw Phase Error Enable 0 Ignore phase errors 1 Check phase errors MS 14 rw Master Select 0 Slave Mode Operate on shift clock received via SCLK 1 Master Mode This mode should not be selected The module should also operated in Slave Mode only Always set this bit when this register is updated Otherwise the communication is corrupted User Manual 5 16 V 1 0 2005 11 SSC 1 0 Cinfineon CIC751 Synchronous Serial Interface SSC Field Bits Type Description EN 15 rw Enable Bit 0 Transmission and reception are disabled 1 Transmission and reception are enabled The module should also be enabled Always set this bit when this register is updated Otherwise the communication is corrupted 12 11 Reserved Returns if read has to be written with Og Writing something different than 0 could lead to a corruption of the communication 13 31 16 Reserved Read as 0 should be written with 0 User Manual 55 1 0 5 17 V 1 0 2005 11 Cinfineon CIC751 Synchronous Serial Interface SSC The Status Register 55 STAT contains status flags for error identification the busy flag and a bit field that indicates the current shift counter status SSC STAT SSC Status Regist
203. pon a falling edge is disabled 1 The trigger upon a falling edge is enabled RENO 7 rw Rising Edge Enable for External Trigger Input 0 This bit enables disables the activation of external trigger input 0 upon a rising edge at the selected input 0 The trigger upon a rising edge is disabled 1 The trigger upon a rising edge is enabled User Manual 2 18 V 1 0 2005 11 STCU V 1 0 Cinfineon CIC751 System and Control Unit SCU Field Bits Type Description INSEL 1 10 8 External Trigger Input 1 Selection This bit field defines the source for the external trigger input 1 000 Input SRO is selected 001 Input SR1 is selected 010 Input SR2 is selected 011 Input SR3 is selected 100 Input SR4 is selected 101 MLI Break Event is selected 110 Input AIN4 is selected 111 Input AIN14 is selected FEN1 14 rw Falling Edge Enable for External Trigger Input 1 This bit enables disables the activation of external trigger input 1 upon a falling edge at the selected input 0 The trigger upon a falling edge is disabled 1 The trigger upon a falling edge is enabled REN1 15 rw Rising Edge Enable for External Trigger Input 1 This bit enables disables the activation of external trigger input 1 upon a rising edge at the selected input 0 The trigger upon a rising edge is disabled 1 The trigger upon a rising edge is enabled 0 5 3 r Reserved 13 11 Read as 0
204. pplications and pin usage internal events are generated These events are then distributed to the service request pins SRn n 0 5 The following status events can be selected as the source for an output of an SRn pin Doorbell event 2 Doorbell event 3 e ADC event 2 the OR combination of all valid bits of the RESBn registers ADC event 0 ADC event 1 User Manual 2 12 V 1 0 2005 11 STCU V 1 0 Cinfineon System and Control Unit SCU 2 5 3 1 Service Request Routing The service request routing allows the user to combine the various events as output for the pins SRx The alternative data outputs of the SRx pins are connected as shown in Figure 2 6 0 Event Selection 0 ADC 2 Doorbell 2 Doorbell 3 ADC 0 rp ADC 1 Reserved Reserved SCU INSELO SCU INVO Event Selection 1 Event Selection 2 Service request routing Figure 2 6 Service Request Routing User Manual 2 13 V 1 0 2005 11 STCU V 1 0 Cinfineon System Control Unit SCU 2 6 SCU Registers 2 6 1 Clock Control Registers The following register controls the clock system of the CIC751 SCU_OSCCON SCU Oscillator Control Register 800 Reset Value 0000 0020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ORD OSC 0 0 RRC 0 1 0 RES OSCSEL r rw rh r r rw rwh rh rw Field Bits Type Description OSCSEL 1 0 rw Oscillator Selec
205. quest is pending 5 3 31 8 Reserved Read as 0 should be written with O User Manual STCU V 1 0 2 23 V 1 0 2005 11 Cinfineon CIC751 System and Control Unit SCU IDCHIP Chip Identification Register 8604 Reset Value 0000 8EXX 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHIPID REVISION r r Field Bits Type Description REVISION 7 0 r Device Revision Code Identifies the device step CHIPID 15 8 r Device Identification The value 8E identifies the device as CIC751 0 31 16 r Reserved Read as 0 should be written with 0 2 7 SCU Register Overview Table 2 5 SCU Registers Register Short Register Long Name Address Description Name see SCU OSCCON SCU Oscillator Control Register 800 Page 2 14 SCU PLLCON SCU PLL Control Register 804 2 15 SCU_SYSCON SCU System Control Register 820 2 16 SCU_ETCTR SCU External Trigger Control Register 850 Page 2 18 SCU_SRCR SCU Service Request Control Register 858 Page 2 19 SCU_CHTRO SCU Channel Trigger 0 Register 830 2 22 SCU SCU Channel Trigger 1 Register 834 2 22 SCU_CHTR2 SCU Channel Trigger 2 Register 838 2 22 SCU_CHTR3 SCU Channel Trigger 3 Register 83C Page 2 22 User Manual 2 24 V 1 0 2005 11 STCU V 1 0 Cinfin
206. r determines how many address offset bits are transmitted in a Write Offset and Data Frame or in a Discrete Read Frame When register MLI TPxBAR is written for generation of a Copy Base Address Frame BS is updated by the Copy Base Address Frame see Page 4 19 0000 1 bit offset address of Remote Window 0001 2 bit offset address of Remote Window 0010 3 bit offset address of Remote Window 1111 16 bit offset address of Remote Window User Manual MLI V1 0 4 64 V 1 0 2005 11 Cinfineon CIC751 Micro Link Interface MLI Field Bits Type Description DW 5 4 Data Width This bit field indicates the data width that has been detected for a read or write access to a Transfer Window of Pipe x see Page 4 22 and Page 4 26 00 8 bit data width detected 01 16 bit data width detected 10 32 bit data width detected 11 Reserved AP 15 6 Address Prediction Factor This bit field indicates the delta value positive or negative number of offset address used by the MLI transmitter for the next address prediction AP is a signed 9 bit number 10th bit is the sign bit that is written with each transmitter address prediction calculation see Page 4 17 and Page 4 38 OP rh Use Optimized Frame When address optimization is enabled with TCR NO 0 this bit indicates if address prediction is possible in the transmitter OP is written with each transmitter address predict
207. r has already taken place Only one address register can be shadowed while a transaction is running because the shadow register can only be assigned either to the source or to the destination address register Note that the shadow address register transfer has the same behavior in Single and Continuous Mode When the shadow mechanism is disabled ADRCROn SHCT 005 SHADROn is always read as 0000 0000 Write new source address to address of SADROn No transaction running yes CHSROn TCOUNT 0 amp TRSR CHOn 0 Store new source address intermediately in SHADROn New transaction started amp ADRCROn SHCT 015 Content of SHADROn is transferred into SADROn and SHADROn 00000000 New source address is directly transferred into SADROn 6152 Figure 3 5 Source Address Update User Manual 3 13 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller The transfer count of a DMA transaction stored in bit field CHCR0n TREL can also be programmed if the DMA transaction is running At the start of a DMA transaction TREL is transferred to bit field CHSR0n TCOUNT which is then updated during the DMA transaction No reload of address or counter will be done if TCOUNT is not equal to 0 The reprogramming of channel specific values except for the selected address shadow register should be avoided while a DMA channel is active 1 2
208. ransaction flow diagrams Command frame 4 31 Copy base address 4 20 Read frame 4 26 Write frame 4 22 Transmitter Description of frame transmission 4 19 Typical application 4 1 P PLL Features 2 4 Functionality 2 4 Ports Output register OUT 7 5 7 15 Port 0 I O functions 7 3 7 14 R Register overview and address map 8 1 Reset control block 2 1 S Self calibration 6 1 1 SSC Block diagram 5 2 Error detection 5 14 Full duplex operation 5 3 Half duplex operation 5 6 Interrupts 5 14 Module implementation Port control 5 23 L 1 V 1 0 2005 11 Cinfineon Keyword Index User Manual L 2 V 1 0 2005 11
209. rcular buffers can be 29815 or 2 CPP bytes 1 2 4 8 16 up to 32k bytes When source or destination addresses are updated incremented or decremented after a move all upper bits 31 CBL S of source address and 31 CBLD of destination address are frozen and remain unchanged even if a wrap around from the lower address bits CBLS 0 or CBLD 0 occurred This address freezing mechanism always causes the circular buffers to be aligned to a multiple integer value of its size If the circular buffer size is less or equal than the selected address offset see Table 3 5 the same circular buffer address will always be accessed User Manual 3 24 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller 3 2 5 Transaction Control Engine The Transaction Control Unit in the DMA Sub Block as shown in the DMA Controller block diagram in Figure 3 3 contains a Channel Arbiter and a Move Engine The Channel Arbiter arbitrates the transfer requests of the DMA channels and submits the transfers parameters of the DMA channel with the highest channel priority that are needed for a DMA transfer to the Move Engine DMA channels within a DMA Sub Block have a two level programmable channel priority as defined by bit CHCR0n CHPRIO When two transfer requests of two different DMA channels with identical channel priority become active at the same time the DMA channel with the lowest channel number n is serviced first T
210. re information about the MLI Break Event see Chapter 4 2 1 5 Which of the eight possible trigger sources is used can be configured via SCU_ETCTR INSELO for the Pin Trigger Request 0 and SCU_ETCTR INSEL1 for the Pin Trigger Request 1 An edge detection activates the trigger signal upon a event that is configurable via ETCTR FENx and ETCTR RENx User Manual 3 2 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller External Request Trigger Control 0 Edge Detection Pin Request 0 External Request Trigger Control 1 Edge Deica Pin Request 1 Figure 3 2 External Trigger Unit external_triggers The rising edge and falling edge sensitivity of the selected input can be enabled individually If edge detection for both edges is enabled a trigger signal is generated upon each change of the signal level rising edge or falling edge User Manual 3 3 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller Note For MLI Mode only the pins 5 0 SR1 and 2 are available as Request Trigger sources Trigger AND Ready Flag Request This combined request enables the MLI interface and the ADC to quickly establish communication with the help of the DMA and minimal software requirements The Set Trigger Flag part signals that a new ADC conversion result 5 available This be from a standard conversion indicated via ADC event 0 or from a injected conversion indicated via ADC even
211. re 2 4 CIC751 Power Supply System PowerConcept User Manual 2 10 V 1 0 2005 11 STCU V 1 0 Cinfineon System Control Unit SCU 2 4 1 Embedded Voltage Regulator The Embedded Validated Voltage Regulator EVR is used for the reduction of supply interfaces between PCB CIC751 In addition to the I O voltage VDDP the voltage supply for the core VDD is necessary The handling of two different supply voltages can have a large impact on application board design Thus it is highly appreciated to provide the on chip voltage by an on chip voltage regulator This embedded voltage regulator further helps reduce the power consumption of the entire chip 2 5 Event Control Events or interrupts are generated towards the system by the ADC SSC MLI DMA and pins In this chip the term event is used because the term interrupt is normally linked with the interruption of a code execution but a code executing unit is not present within the CIC751 2 5 1 Event Sources There are 13 event sources available for the CIC751 e ADC event 0 injection conversion interrupt of the ADC module e ADC event 1 standard conversion interrupt of the ADC module e ADC event 2 the OR combination of all valid bits of the ADC_RESBn registers Doorbell event 0 that becomes active if the channel number written to INRES equals Doorbell event 1 that becomes active if the channel number written to INRES equals DBCT
212. rnal clock User Manual 2 2 V 1 0 2005 11 STCU V 1 0 Cinfineon System and Control Unit SCU SCU_OSCCON SCU_PLLCON CGU_block Figure 2 1 Clock Generation Unit Block Diagram The following sections describe the various parts of the CGU 2 3 21 RC Oscillator Circuit RCOSC The RC Oscillator Circuit RCOSC is designed to work without an external crystal oscillator or an external stable clock source The RCOSC consists of an Schmitt Trigger RC oscillator core and a standard current reference to provide a VDD independent bias current Internal Clock Mode When operating without an external crystal or clock source the RC oscillator provides a stabile clock frequency of 9 MHz The stability of this clock frequency is influenced by the temperature The system clock for Normal Mode equal to fp is generated from an oscillator clock fosc in one of four selectable ways e Bypass Mode Direct Drive e Prescaler Mode e Normal Mode Free running Mode User Manual 2 3 V 1 0 2005 11 STCU V 1 0 Cinfineon System and Control Unit SCU 2 3 2 2 Phase Locked Loop PLL Module This section describes the PLL module of the CIC751 The PLL supplies the system with a single clock frequency Features Programmable clock generation PLL e Loop filter Input frequency fog 3 1 to 37 5 MHz e VCO frequency fyco 100 to 250 MHz select by range VCO lock detection Oscillator
213. rs The slave device will not wait for the next clock from the shift clock generator as the master does because the first clock edge generated by the master may be already used to clock in the first data bit depending on the selected clock phase So the slave s first data bit must already be valid at this time Note On the SSC a transmission and a reception always takes place at the same time regardless of whether valid data has been transmitted or received User Manual 5 5 V 1 0 2005 11 SSC 1 0 Cinfineon Synchronous Serial Interface SSC 5 2 1 2 Half Duplex Operation The description this section assumes that the SSC is used with software controlled bi directional GPIO port lines that provide an open drain capability In a half duplex configuration only one data line is necessary for both receiving and transmitting data The data exchange line is connected to both pins MTSR and MRST of each device and the clock line is connected to the SCLK pin The master device controls the data transfer by generating the shift clock while the slave devices receive it Due to the fact that all transmit and receive pins are connected to the one data exchange line serial data may be moved between arbitrary stations As in full duplex mode there are two ways to avoid collisions on the data exchange line Only the transmitting device may enable its transmit pin driver The non transmitting devices use open drain output a
214. rter Resolution Control 00 10 bit resolution 01 8 bit resolution 1x Reserved 0 15 14 Reserved Read as 0 should be written with O ADC CTR2IN ADC Injection Control 2 Register 022 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 RES ADCTC ADSTC r rw rw rw Field Bits Type Description ADSTC 5 0 rw ADC Sample Time Control Defines the ADC sample time ts fgc X 4 x lt ADSTC gt 1 ADCTC 11 6 ADC Conversion Time Control Defines the ADC basic conversion clock fac fsvs lt ADCTC gt 1 RES 13 12 rw Converter Resolution Control 00 10 bit resolution 01 8 bit resolution 1x Reserved 0 15 14 Reserved Read as 0 should be written with 0 Note The limit values for see data sheet must not be exceeded when selecting ADCTC and fsys User Manual 6 26 V 1 0 2005 11 ADC V1 0 Cinfineon eel The Analog Digital Converter 6 8 3 ADC Result Registers The following registers are used in the Compatibility Mode and Enhanced Mode for storage of the last conversion result ADC_DAT ADC Result Register 030 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHNR ADRES rwh rwh Field Bits Type Description ADRES 11 0 A D Conversion Result The digital result of the most recent conversion In Compatibility Mo
215. rts the following conversion modes Standard Conversions Fixed Channel Single Conversion produces just one result from the selected channel Fixed Channel Continuous Conversion repeatedly converts the selected channel Auto Scan Single Conversion produces one result from each of a selected group of channels Auto Scan Continuous Conversion repeatedly converts the selected group of channels Wait for Read Mode start a conversion automatically when the previous result was read Channel Injection Mode can insert the conversion of a specific channel into a group conversion auto scan The key features of the ADC are Use of Successive Approximation Method e Integrated sample and hold functionality e Analog Input Voltage Range from OV to 5V e 16 Analog Input Channels e 16 ADC result registers Resolution 8 Bit 10 Bit in Compatibility Mode Minimum Conversion Time 2 55 us 10 Bit Total Unadjusted Error TUE 1 LSB 8 Bit 2 LSB 10 Bit Support of several Conversion Modes Fixed Channel Single Conversion Fixed Channel Continuous Conversion Auto Scan Single Conversion Auto Scan Continuous Conversion Wait for Result Read and Start Next Conversion Channel Injection during Group Conversion Programmable Conversion and Sample Timing Scheme Automatic Self Calibration to changing temperatures or process variations User Manual 1 3 V 1 0 2005 11 Introduction V 1 0 Cinfineon Introduction 1 2
216. rupt A Normal Frame received interrupt is generated when the MLI receiver has correctly received a Normal Frame a read or a write frame not a Command Frame or Copy Base Address Frame correctly or when the MLI has terminated its read or write access Both interrupt sources have separate status control bits but are concatenated to one common frame receive interrupt 4 2 6 4 Interrupt Command Frame Interrupt An interrupt command frame interrupt is generated when a Command Frame is received correctly on Pipe 0 with a valid command code for remote interrupt generation CMD 0000g to 0011p The received command code determines which of the service request output lines SR 3 0 should be activated 4 2 6 5 Command Frame Received Interrupt A command frame received interrupt is generated when the MLI receiver has correctly received a Command Frame through Pipe Number x x 0 3 Separate interrupt status control bits are assigned to each Pipe All four Pipe related Command Frame received in Pipe x interrupt events are concatenated to one common Command Frame received interrupt User Manual 4 44 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI 4 2 7 Baud Rate Generation The MLI transmitter baud rate is given by fy 2 The MLI shift clock output signal TCLK of the transmitter toggles with each clock cycle of fy in order to obtain a 50 duty cycle the 50 duty cycle can vary to one clock cycle of fsys in Fracti
217. rved Details about the Optimized Read Frame handling of the CIC751 are provided in Chapter 4 2 1 2 User Manual 4 12 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI 4 1 4 6 Command Frame The Local Controller is able to initiate control actions to be executed by the Remote Controller by sending a Command Frame The Command Frame contains the following parts Header The header starts with Frame Code FC 10g followed by the Pipe number PN The Pipe number defines the type of command to be executed Command Code CMD Pipe number PN and a 4 bit CMD field are used for command coding The command coding of some control actions is fixed but free programmable software commands can also be defined with PN 11g The coding of the command bit field is Pipe specific and depends on the transmitted Pipe Number n e Parity bit P 01234 78 1 0 PN CMD P CMD Command Code Header Command frame Figure 4 11 Command Frame Table 4 5 PN for Command Coding Pipe Number 00g Activate MLI Request generation or other control signal s of the Remote Controller The identity of which signal becomes activated is defined by CMD The use of these lines depends on the product 01 Define delay for parity error indication the Remote Controller The delay in RCLK cycles is defined by the value of CMD 10 Control of internal functions of the Re
218. rved Read as 0 should be written with O User Manual 4 89 V 1 0 2005 11 MLI V1 0 CIC751 Cinfineon Micro Link Interface MLI Field Bits Type Description 0 15 10 Reserved 31 26 Read as 0 should be written with 0 4 3 5 2 Receiver Interrupt Status Register The Receiver Interrupt Status Register MLI_RISR contains all of the interrupt request flags of the MLI receiver These interrupt request flags can be cleared by software when writing the appropriate bits in the MLI_RIER register MLI_RISR MLI Receiver Interrupt Status Register 2A8 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 l l T l l l 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CFR CFR 0 DRAI 0 IC 2 1 10 r rh r rh rh rh rh rh rh rh rh Field Bits Description NFRI 0 rh Normal Frame Received Interrupt Flag This flag is set when a write or a read frame has been received The MLI Request that is activated is defined by MLI RINPR NFRIP MEI 1 rh MLI Move Engine Interrupt Flag This flag is set when the MLI has finished an operation read or write depending on received frame The MLI Request that is activated is defined by MLI RINPR MPPEIP CFRIO 2 rh Command Frame Received through Pipe x Interrupt 3 Flag 2 4 This flag is set when Command Frame has been C
219. s 0 If the TREADY 1 is detected and the ready delay counter value is less than a programmed value it is assumed that the MLI receiver has received the frame without a parity error and a new frame can be transmitted by the MLI transmitter An MLI transfer without a parity error condition is shown in Figure 4 14 Figure 4 23 shows a transfer with a parity error detected by the MLI receiver In this case the receiver waits a programmed number of RCLK clock cycles before setting RREADY to 1 If TREADY 1 is detected by the transmitter and the ready delay counter User Manual 4 16 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI value is greater than the programmed value an reception error condition has been signalled For this case it is assumed that the MLI receiver has received the frame with a parity error and has discarded the frame In this case the transmitter automatically sends the last frame again 4 1 6 2 Error The transmitter of the Local Controller is able to detect an inoperable receiver in the Remote Controller Such non acknowledge error condition is detected by the transmitter when at the end of a frame transmission the TREADY signal is still at high level TREADY 21 when TVALID becomes 0 Figure 4 15 shows the acknowledge error case In this case the transmitter automatically sends the last frame again TCLK TREADY Non ackn
220. s 0 The base address of a Remote Window must be aligned to its size e g a window of 1 KByte to start at 1 KByte address boundaries e Remote Window size The size is defined by the 4 bit coded size BS The maximum size is 64 KBytes Parity bit P Header 01234 3132 3536 0 0 PN Base Address 28 bit Bs copy baseaddr Figure 4 6 Copy Base Address Frame Table 4 2 Size Coding BS Remote Window Size Number of Offset Bits 0000 2 bytes 1 0001p 4 bytes 2 11106 32 KBytes 15 1111p 64 KBytes 16 Details about the Copy Base Address Frame handling of the CIC751 are provided in Chapter 4 2 1 1 User Manual 4 8 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI 4 1 4 2 Write Offset and Data Frame A Write Offset and Data Frame are used by the Local Controller to send an address offset and data to the Remote Controller The Write Offset and Data Frame contains the following parts Header The header starts with Frame Code FC 00 followed by the Pipe number PN of the Transfer Window that has been the target of the write operation m Bits of write offset These bits define the write offset The value of m depends on the size of the Remote Window defined by the Copy Base Address Frame m 1 16 Write data field The write data field can be 8 16 or 32 bit wide depending on the data width of the write access to the Transfer Window e Pari
221. s Register 28 Page 5 18 SSC EFM Error Flag Modification Register 2C Page 5 19 SSC TB Transmit Buffer Register 20 Page 5 21 SSC RB Receive Buffer Register 24 Page 5 22 SSC BR Baud Rate Timer Reload Register 14 Page 5 22 SSC CON SSC Control Register 104 Reset Value 0000 875F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EN MS 0 0 PEN REN TEN LB HB BM rw rw r rw rw rw rw rw rw rw rw rw Field Bits Type Description BM 3 0 rw Data Width Selection BM determines the number of data bits of the serial frame The data width is set to 16 bit and should never be changed Always write 1111 to this bit field when this register is updated Otherwise the communication is corrupted User Manual 5 15 V 1 0 2005 11 SSC 1 0 Cinfineon CIC751 Synchronous Serial Interface SSC Field Bits Type Description HB 4 rw Heading Bit Control 0 Transmit Receive LSB First 1 Transmit Receive MSB First PH 5 rw Clock Phase Control 0 Shift transmit data on the leading clock edge latch on trailing edge 1 Latch receive data on leading clock shift on trailing edge PO 6 rw Clock Polarity Control 0 Idle clock line is low the leading clock edge is low to high transition 1 Idle clock line is high the leading clock edge is high to low transition LB 7 rw Loop Back Control 0 Normal output 1 Receive input is connected to transmit output Half du
222. scribes the mapping of the pins of Port 0 and the related I O functions Table 7 8 Port 1 Input Output Functions Port Connected Function From to Module Pin P1 0 Input Mode Analog Input 0 ADC P1 1 Analog Input 1 ADC P1 2 Analog Input 2 ADC P1 3 Analog Input 3 ADC P1 4 Analog Input 4 ADC Trigger SCU DMA P1 5 Analog Input 5 ADC P1 6 Analog Input 6 ADC P1 7 Analog Input 7 ADC P1 8 Analog Input 8 ADC P1 9 Analog Input 9 ADC P1 10 Analog Input 10 ADC P1 11 Analog Input 11 ADC P1 12 Analog Input 12 ADC P1 13 Analog Input 13 ADC P1 14 Analog Input 14 ADC Trigger SCU DMA P1 15 Analog Input 15 ADC User Manual 7 14 V 1 0 2005 11 Parallel Ports V1 0 Cinfineon Parallel Ports 7 2 4 Port 1 Register Description 7 2 4 4 Port Input Register P1 IN Port 1 Input Register A644 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P15 P14 P13 P12 P11 P10 9 P8 P7 P6 P5 P3 P2 1 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Field Bits Type Description Px x rwh 1 Input Bit x x 15 0 This bit indicates the level at the input pin of port P1 pin x 0 The input level of P1 x is 0 1 The input level of P1 x is 1 0 31 16 r Reserved Read as 0 should be
223. should be written with 0 31 16 SCU_SRCR SCU Service Request Control Register 858 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INV3 INSEL3 INV2 INSEL2 INV1 INSEL1 INV0 INSEL0 rw rw rw rw rw rw rw rw User Manual 2 19 V 1 0 2005 11 STCU V 1 0 Cinfineon CIC751 System and Control Unit SCU Field Bits Type Description INSELO 2 0 Input Selection for Event 0 000 Event is generated 001 ADC event 2 is used as source 010 Doorbell event 2 is used as source 011 Doorbell event 3 is used as source 100 ADC event 0 is used as source 101 ADC event 1 is used as source 110 Reserved do not use this combination 111 Reserved do not use this combination INVO 3 rw Invert Source for Event 0 0 The source is not inverted 1 The source is inverted INSEL1 6 4 w Input Selection for Event 1 000 No Event is generated 001 ADC event 2 is used as source 010 Doorbell event 2 is used as source 011 Doorbell event is used as source 100 ADC event 0 is used as source 101 ADC event 1 is used as source 110 Reserved do not use this combination 111 Reserved do not use this combination INV1 7 rw Invert Source for Event 1 0 The source is not inverted 1 The source is inverted INSEL2 10 8 rw Input Selection for Event 2 000 No Event is generated 001 ADC event 2 is used as source 010 Doorbell event
224. sion Request of Channel y wie ADC DAT2 ADC_DAT2 Full Int Request ADEINT Y Read ADC_DAT2 MC_ADC0003_INJECT Figure 6 4 Channel Injection Example A Channel Injection can be triggered in the following way setting of the Channel Injection Request bit ADC CON ADCHRQ or CTRO ADCRQ via software Note The channel injection request bit ADC_CON ADCRQ or ADC CTRO ADCRQ will be set regardless of whether or not the Channel Injection Mode is enabled It is recommended to always clear bit CON ADCRQ CTRO ADCRQ before enabling the Channel Injection Mode After the completion of the current conversion if any is in progress the converter will start inject the conversion of the specified channel When the conversion of this channel is completed the result will be placed into the alternate result register ADC DAT2 and a Channel Injection Complete interrupt request trigger ADC event 1 is generated that can be used to trigger the DMA Note The result of an injected conversion is directly written to 2 If the previous result has not been read in the meantime it is overwritten User Manual 6 9 V 1 0 2005 11 ADC V1 0 Cinfineon oj The Analog Digital Converter 6 2 10 Arbitration of Conversions Conversion requests that are activated while the ADC is idle immediately trigger the respective conversion If a conversion is requested while another conversion is currently in progre
225. ss prediction factor that has been calculated for Pipe x in the receiver of the Remote Controller MLI RPOSTATR MLI Receiver Pipe 0 Status Register 27C MLI RP1STATR MLI Receiver Pipe 1 Status Register 280 MLI RP2STATR MLI Receiver Pipe 2 Status Register 2844 MLI RP3STATR MLI Receiver Pipe 3 Status Register 2884 31 30 29 28 27 26 Reset Value 0000 0000 Reset Value 0000 0000 Reset Value 0000 0000 Reset Value 0000 0000 25 24 23 22 21 20 19 18 17 16 0 r 2 Field Bits Type Description BS 3 0 rh Size This bit field indicates the size of Pipe x Remote Window in the Remote Controller It is updated by hardware when a Copy Base Address Frame has been received see Page 4 19 0000 1 bit offset address of Remote Window 0001 2 bit offset address of Remote Window 0010 3 bit offset address of Remote Window 1111 16 bit offset address of Remote Window User Manual MLI V1 0 4 79 V 1 0 2005 11 Cinfineon CIC751 Micro Link Interface MLI Field Bits Type Description AP 15 6 Address Prediction Factor AP contains the address prediction factor that has been calculated for Pipe x in the receiver of the Remote Controller It is a signed 9 bit number with the sign in its most significant bit see Page 4 38 0 5 4 Ir Reserved 31 16 Read as 0 should be written with 0 User M
226. ss the operation of the A D converter depends on the type of conversions involved standard or injected Note A conversion request is activated if the respective control bit ADC_CON ADST ADC CTRO ADST or ADC CON ADCRQ CTRO ADCRQ is toggled from 0 to 1 i e the bit must have been zero before being set Table 6 2 summarizes the ADC operation in the possible situations Table 6 2 Conversion Arbitration Conversion New Requested Conversion in Progress Standard Injected Standard Abort running conversion Complete running conversion and start requested new start requested conversion after that conversion Injected Complete running conversion Complete running conversion start requested conversion after start requested conversion after that that Bit ADC CON ADCRQ ADC CTRO ADCRQ will be 0 for the second conversion however 1 If an injected conversion is pending when a Standard Conversion is re started the injected conversion is executed before the newly started Standard Conversion User Manual 6 10 V 1 0 2005 11 ADC V1 0 Cinfineon The Analog Digital Converter 6 3 Automatic Calibration The ADC ofthe CIC751 features automatic self calibration This calibration corrects gain errors which are mainly due to process variation and offset errors which are mainly due to temperature changes Two types calibration are supported e Reset calibration performs a thorough bas
227. ss is not modified if CBLS 00005 0 Address offset will be subtracted 1 Address offset will be added User Manual 3 43 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller Field Bits Type Description DMF 6 4 Destination Address Modification Factor This bit field and the data width as defined in CHCROn CHDW determines an address offset value by which the destination address is modified after each DMA move The destination address is not modified if CBLD 00005 See also Table 3 5 000 Adadress offset is 1 x CHDW 001 55 offset is 2 x CHDW 010 Adadress offset is 4 CHDW 011 Address offset is 8 x CHDW 100 Address offset is 16 x CHDW 101 Address offset is 32 x CHDW 110 Address offset is 64 x CHDW 111 Address offset is 128 x CHDW INCD 7 rw Increment of Destination Address This bit determines whether the address offset as selected by DMF will be added to or subtracted from the destination address after each DMA move destination address is not modified if 0000 0 Address offset will be subtracted 1 Address offset will be added CBLS 11 8 rw Circular Buffer Length Source This bit field determines which part of the 32 bit source address register remains unchanged and is not updated after a DMA move operation see also Section 3 2 4 6 Therefore CBLS also determines the size of the circular source buffer 0000 Source address
228. ssion of a Copy Base Address Frame is started each time a transmitter Pipe x base address register MLI TPxBAR x 0 3 is written triggering the following actions for Pipe x Bit field MLI_TPxBAR BS x 0 3 is written to bit field MLI TPXSTATR BS x 0 3 Bit field MLI TPXBAR ADDR x 0 3 is written to bit field MLI TCBAR ADDR Status bit field MLI TRSTATR PN is updated with Pipe Number x for example x 2 when MLI_TP2BAR has been written Status flag MLI TRSTATR BAV base address valid is set The transmission of a Copy Base Address Frame with the two parameters MLI TCBAR ADDR MLI TPxSTATR BS is started for Pipe x User Manual 4 20 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI e Status MLI TRSTATR BAV in the Local Controller is cleared after the Base Address Frame has been finished and correctly acknowledged by the MLI receiver of the Remote Controller e Interrupt status flag MLI TISR NFSIx is set and MLI Request is generated if enabled by MLI_TIER NFSIEx 1 Note After the transfer of a Copy Base Address Frame the optimized mode will be suppressed automatically for the next two data frames This ensures a correct offset prediction afterwards Remote Controller When a Copy Base Address Frame for Pipe x has been received correctly and acknowledged the following actions are executed in the MLI receiver of the Remote Controller The received address bits are s
229. ssion of two 16 bit read data parts and an increase of the maximum usable bandwidth for communication But on the other hand this mechanism has a negative impact for starting a read access After the first read access to the CIC751 the last read data that was prefetched is still read for transmission and will be automatically transmitted in parallel with the reception of the next transaction header Automatically during the transmission of this prefetched data a new prefetch is started before the new transaction header is taken into account Therefore the following rules must be considered for read accesses by the master The read data that is received in parallel with sending the transaction header should be ignored The first read data that is received after sending the transaction header should be ignored The above mentioned rules does not apply to the first read access after a reset PORST or SW reset or a write access User Manual 5 11 V 1 0 2005 11 SSC 1 0 Cinfineon Synchronous Serial Interface SSC 515 Transaction RDY READ_FLOW Figure 5 5 Consecutive Reads User Manual 5 12 V 1 0 2005 11 SSC 1 0 1 751 Cinfineon 5 2 3 Operating Mode Selection The following features of the serial data bit transfer can be programmed e transfer may start with the LSB or the MSB The shift clock may be idle low or idle high The data bits may be shifted with the leading or trailing edge of
230. ster 0000 04E8 l Channel Address Control 0000 O4EC Page 3 43 Register SADROS DMA Channel Source Address 0000 04 0 Page 3 47 Register DADROS3 DMA Channel 3 Destination 0000 04F4 Page 3 48 Address Register SHADRO03 DMA Channel 3 Shadow Address 0000 04F8 Page 3 49 Register DMA_CHSR04 DMA Channel 4 Status Register 0000 0500 Page 3 42 4 DMA Channel 4 Control Register 0000 0504 Page 3 39 10 Memory 10 Register 0000 0508 ADRCRO4 Channel 4 Address Control 0000 050C Page 3 43 Register DMA_SADR04 DMA Channel 4 Source Address 0000 0510 3 47 Register DMA_DADR04 DMA Channel 4 Destination 0000 0514 Page 3 48 Address Register User Manual 8 8 V 1 0 2005 11 Regs V1 0 1 751 Cinfineon Register Overview Table 8 3 DMA Kernel Registers cont d Register Register Long Name Address Description Short Name see DMA_SHADR04 DMA Channel 4 Shadow Address 0000 0518 3 49 Register DMA CHSR05 DMA Channel 5 Status Register 0000 0520 3 42 5 DMA Channel 5 Control Register 00000524 3 39 11 Memory 11 Register 0000 0528 5 DMA Channel 5 Address Control 0000 052C Page 3 43 SADRO05 DMA Channe
231. sts the oscillator frequency to the defined input frequency range of the PLL Jin 7 fosc PDIV 1 Valid values 11 00 PLLVB 7 6 PLL VCO Band Select ValueVCO output frequencyBase frequency 00 100 150 MHz 20 80 MHz 01 150 200 MHz 40 130 MHz 10 200 250 MHz 60 180 MHz 11Reserved NDIV 12 8 PLL N Divider by which the PLL multiplies its input frequency Juco NDIV 1 Valid values 11111 00111 User Manual STCU V 1 0 2 15 V 1 0 2005 11 Cinfineon System and Control Unit SCU Field Bits Type Description PLLCTRL 14 13 rw PLL Operation Control 00 Bypass PLL clock mult the VCO is off Prescaler Mode 01 Reserved do not use this combination 10 clock used input clock switched off Freerunning Mode 11 VCO clock used input clock connected Normal Mode BY 15 rw PLL Bypass Control 0 PLL operates as defined by bit field CTRL 1 PLL operates in Bypass Mode 0 31 16 Reserved Read as 0 should be written with 0 1 Operation in the upper VCO band cannot be guaranteed because of a possible malfunction of the K divider 2 6 2 Miscellaneous SCU Registers SCU_SYSCON SCU System Control Register 820 Reset Value 0000 000C 31 30 22 28 27 26 25 24 23 22 21 20 19 18 17 16 P1DI SW RES g MTM DIS RST 1 LD K r rw rw rw rw rwh Field Bits Typ
232. t e ADC event 0 indirect e ADC event 1 indirect e Doorbell event 0 indirect e Doorbell event 1 indirect e Channel 0 Request direct Channel 1 Request direct Channel 2 Request direct Channel 3 Request direct Channel 4 Request direct Channel 5 Request direct Channel 6 Request direct Channel 7 Request direct There are two classes of requests that are connected to the DMA direct and indirect Indirect requests need to be preselected on a system level in order to be mapped to the two additional direct requests Set Trigger Flag Request direct Trigger AND Ready Flag Request direct User Manual 3 1 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller DMA Controller Request 2 mu Trigger AND Ready Flag Request Request Selection Pin Trigger 0 Pin Trigger 1 Doorbell Trigger 0 i Set Trigger Flag Request Doorbell Trigger 1 ADC Trigger 0 ADC Trigger 1 Channel Request 0 7 DMA Channels 0 7 Figure 3 1 DMA Request Principle 3 1 1 1 Preselection of the Indirect Requests There are two options for the requests Set Trigger Flag Request The following requests can be mapped to the Set Trigger Request Pins SRO SR1 SR2 SR3 SR4 AIN4 and AIN14 MLI Break Event These eight sources are combined into two Pin Trigger Request sources at a first level These eight sources represent all possible external Request Triggers for mo
233. t must not be exceeded when selecting ADCTC and fsys User Manual 6 23 V 1 0 2005 11 ADC V1 0 Cinfineon CIC751 The Analog Digital Converter 6 8 2 ADC Control Registers for Enhanced Mode The following registers are used in the Enhanced Mode to configure the ADC module ADC_CTRO ADC Control 0 Register 024 Reset Value 1000 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 SAM AD AD AD AD AD CAL PLE pcs CRQ WR BSY ST ADM OFF ADCN w rh rw wh rw rw rh rwh rw rw rw Field Bits Type Description ADCH 3 0 Analog Input Channel Selection Selects the first ADC channel which is to be converted CALOFF 4 rw Calibration Disable Control 0 Calibration cycles are executed 1 Calibration is disabled off Note This control bit is active in both compatibility and Enhanced Mode ADM 6 5 Mode Selection Control 00 Fixed Channel Single Conversion 01 Fixed Channel Continuous Conversion 10 Auto Scan Single Conversion 11 Auto Scan Continuous Conversion ADST 7 rwh ADC Start Stop Control 0 Stop a running conversion 1 Start conversion s ADBSY 8 rh Busy Flag 0 ADC is idle 1 A conversion is active ADWR 9 rw ADC Wait for Read Control 0 Wait for Read Mode is deactivated 1 Wait for Read Mode is activated ADCIN 10 rw ADC Channel Injection Enable 0 Channel Injection is disabled 1 Channel Injection is enabled User Manual 6 24 V 1 0 2005 11 ADC V1 0
234. t 1 If the ADC conversion result was stored in the ADC extended result registers the doorbell mechanism can be used indicated via Doorbell event 0 or Doorbell event 1 for the communication Note The Doorbell mechanism requires the use of at least one additional channel Typical Use Case Example This is combined with the MLI Request trigger 0 and 1 Both MLI Request triggers be used to indicate when the MLI interface is ready to send the next data ADC conversion result to the host controller Therefore the combination indicates that a new ADC conversion result is available and the MLI interface is ready to transmit the result to the host controller 3 1 2 DMA Request Assignment Matrix The DMA requests input lines of the DMA are assigned as indicated in Table 3 1 Table 3 1 DMA Request Assignment DMA DMA Request Input Selected by Channel 0 Channel 7 Request CHCRO PRSEL 000 Channel 6 Request CHCRO PRSEL 001 MLI Request 2 DMA CHCRO PRSEL 010 MLI Request 3 DMA CHCRO PRSEL 011 Trigger AND Ready Request DMA CHCRO PRSEL 100 Set Trigger Flag Request DMA CHCRO PRSEL 101 not used no Request DMA CHCRO PRSEL 110 DMA CHCRO PRSEL 1115 User Manual 3 4 V 1 0 2005 11 DMA V1 0 Cinfineon CIC751 Direct Memory Access Controller Table 3 1 DMA Request Assignment cont d D
235. t 2 View A 0000 1108 Page 6 30 Register ADC Extended Result 3 View 0000 110C 6 30 Register ADC_RESA4 ADC Extended Result 4 View A 0000 1110 Page 6 30 Register ADC_RESA5 ADC Extended Result 5 View A 0000 1114 Page 6 30 Register 5 6 ADC Extended Result 6 View A 0000 1118 Page 6 30 Register ADC_RESA7 ADC Extended Result 7 View A 0000 111C Page 6 30 Register RESA8 ADC Extended Result 8 View A 0000 1120 Page 6 30 Register ADC RESA9 ADC Extended Result 9 View A 0000 1124 Page 6 30 Register ADC RESA10 ADC Extended Result 10 View 0000 1128 Page 6 30 Register User Manual 8 13 V 1 0 2005 11 Regs V1 0 CIC751 Cinfineon Register Overview Table 8 7 ADC Registers cont d Register Short Register Long Name Address Description Name see ADC RESA11 ADC Extended Result 11 View A 0000 112C 6 30 Register ADC RESA12 ADC Extended Result 12 View 0000 1130 Page 6 30 Register ADC RESA13 ADC Extended Result 13 View A 0000 1134 Page 6 30 Register RESA14 ADC Extended Result 14 View 0000 1138 Page 6 30 Register ADC RESA15 ADC Extended Result 15 View 10000 113C 6 30 Register ADC RESBO ADC Extended Result 0 View B 0000 1140 Page 6 32 Register ADC RESB1 ADC Extended Result 1 View B 0000 1144 Page 6 32 Register ADC RESB2 ADC Extended Result 2 View B 0000 1
236. t Configuration This bit field selects the oscillator or clock input for the PLL 00 The RC oscillator is used 01 Reserved do not use 10 RCLK is directly used 11 RCLKis directly used same setting as 10g OSCR 2 rh Oscillator Run Status Bit This bit shows the state of the oscillator run state 0 The oscillator is not running 1 The oscillator is running ORDRES 3 rwh Oscillator Run Detection Reset 0 No operation 1 The oscillator run detection logic is reset and restarted When set this bit is automatically cleared RRCOSC 7 rh RC Oscillator Status 0 Nominal bias voltages is not reached 1 Nominal bias voltages is reached 0 4 8 rw Reserved Read as 0 should be written with User Manual 2 14 V 1 0 2005 11 STCU V 1 0 Cinfineon CIC751 System and Control Unit SCU Field Bits Type Description Reserved Read as 1 should be written with 1 6 31 9 Reserved Read as 0 should be written with O SCU PLLCON SCU PLL Control Register 31 30 29 28 27 26 804 24 Reset Value 0000 6B02 25 23 22 21 20 19 18 17 16 13 12 11 PLLCTRL PDIV KDIV Field Bits Description KDIV 9 0 PLL K Divider Scales the PLL output frequency to the desired CPU frequency fvco KDIV 1 PDIV 5 4 PLL P Divider Adju
237. t determines the number of moves consisting of one read and one write each to be done in each transfer It allows the user to indicate to the DMA the number of moves to be done after one request The number of moves per transfer is selected by the block mode settings CHCROn BLKM a Transaction Transfer 0 Transfer 1 Transfer n M CHOn CHSROn i tc initial transfer count MCT06158 Figure 3 11 Transfer and Move Count After a DMA move the next source and destination addresses are calculated Source and destination addresses are calculated independently of each other The following address calculation parameters can be selected e The address offset which is a multiple of the selected data width e The offset direction addition subtraction or none unchanged address Control bits in address control register ADRCROn determine how the addresses are incremented decremented Further the data width as defined in CHCR0n CHDW is taken into account for the address calculation Figure 3 12 and Figure 3 13 show two examples of address calculation In both examples data width of 16 bit CHCROn CHDW 015 is assumed User Manual 3 22 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller Source Memory Destination Memory 31 16 15 0 31 16 15 0 x r r n C H4 e 1 A
238. tandard ADC pointer to target data location copy data result registers S CHNR 0010 RESULT 11 0 V 0 Door bell ADC_result_buffer Figure 6 5 Extended ADC Result Registers User Manual 6 16 V 1 0 2005 11 ADC V1 0 Cinfineon The Analog Digital Converter Each of the 16 extended result registers contains a RESULT bit field with the conversion result delivered by the ADC The ADC extended result registers also indicate the channel number belonging to the result 6 7 2 Extended Result Registers After being triggered the DMA reads a 16 bit data word from the register DAT in the ADC and writes it to the input result register INRES A 16 bit data word written to this register is transferred automatically to one of the 16 result registers The upper 4 bits written to INRES indicate the number of the target result register Each result register has an associated valid bit RESBn V The valid bit of a result register is automatically set if data is transferred to it The valid bit is automatically cleared if the result register is read out As a result the valid bit indicates that new data is available that has not yet been read out In order to allow different read modes two different 16 bit read views exist selected by two different read address one view view A shows the same bit positions as the original ADC register the other view view B shows the valid bit instead of the channel number so the user can do polli
239. ter Note For more information about triggering a DMA transfer see Chapter 3 1 6 6 1 2 Forward to an SRn Pin ADC interrupt can be forwarded to a host controller via SRn pin of the CIC751 The following events can be selected as the source for an output of an SRn pin e end of conversion interrupt was triggered An error injection interrupt was triggered Note For information about routing an interrupt to an SRn pin see Chapter 2 5 3 1 User Manual 6 15 V 1 0 2005 11 ADC V1 0 Cinfineon The Analog Digital Converter 6 7 ADC Buffer Registers This section describes the extended result register including the control and input register and the doorbell mechanism 6 7 1 Overview The ADC module offers the possibility of storing two results in its data registers The result of the injected conversion is stored in register DAT2 whereas all other results auto scan or single programmed conversions are stored in register DAT In order to make all results available at the same time additional result registers are added As the ADC has 16 analog input channels the same number of result registers is necessary to store the results of each single channel The data transfer between the standard ADC result registers and the extended result registers is performed by an interrupt request to the DMA RESULT 11 0 V RES2 RES1 CHNR 0001 RESULT 11 0 V RES0 CHNR 0000 RESULT 11 0 V s
240. ter Interrupt Node Pointer 0000 02A0 4 86 Register MLI RIER Receiver Interrupt Enable Register 0000 02A4 Page 4 88 MLI RISR Receiver Interrupt Status Register 0000 02A8 Page 4 90 User Manual 8 5 V 1 0 2005 11 Regs V1 0 Cinfineon CIC751 Register Overview Table 8 2 MLI Kernel Registers cont d Register Register Long Name Address Description Short Name see MLI RINPR Receiver Interrupt Node Pointer 0000 02AC Page 4 92 Register MLI GINTR Global Interrupt Set Register 0000 02B0 Page 4 53 MLI_OICR Output Input Control Register 0000 02B4 Page 4 54 MLI MEMO MLI Memory 0 Register 00000288 MLI Memory 1 Register 0000 02BC Reserved Reserved 0000 02C0 l 0000 02FF Table 8 3 Registers Register Register Long Name Address Description Short Name see Reserved Reserved 0000 0400 0000 040C DMA CHRSTR DMA Channel Request Register 0000 0410 3 29 DMA TRSR DMA Transaction Request State 0000 0414 3 31 Register DMA STREQ DMA Software Transaction 0000 0418 Page 3 32 Request Register DMA Hardware Transaction 0000 041C Page 3 33 Request Register Reserved Reserved 0000 0420 DMA_ERRSR DMA Error Status Register 0000 0424 3 34 DMA_CLRE DMA Clear Error Register 0000 0428 3 36 Reserved Reserved 0000 04
241. th the write action of a new result and cleared when at least the low byte of the result is read out 0 The result is not new has already been read out 1 The result is new has not yet been read out 0 31 16 r Reserved Read as 0 should be written with 0 User Manual 6 34 V 1 0 2005 11 ADC V1 0 Cinfineon The Analog Digital Converter 6 8 5 ADC Doorbell Register The following register control the doorbell mechanism of the extended result registers ADC_DBCTR ADC Doorbell Control Register 184 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 COMP1 0 COMPO r rw rw Field Bits Type Description COMP0 3 0 Compare Value 0 This bit field defines the compare value for the doorbell mechanism channel 0 COMP1 11 8 rw Compare Value 1 This bit field defines the compare value for the doorbell mechanism channel 1 0 7 4 r Reserved 31 12 Read as 0 should be written with 0 SCU_SYSCON SCU System Control Register 820 Reset Value 0000 000C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 T P1DI SW RES ILOC LD K rw rw rw rw rwh rh User Manual 6 35 V 1 0 2005 11 ADC V1 0 Cinfineon CIC751 The Analog Digital Converter Field Bits Type Description
242. that has been correctly received Separate status control bits are assigned to each Pipe All four Pipe related Command Frame sent interrupt events are concatenated to one common Command Frame sent interrupt 4 2 6 Receiver Interrupts The MLI receiver can generate the following interrupts Table 4 9 MLI Receiver Interrupts Interrupt Events Interrupt See Discarded Read Answer Discarded Read Answer Page 4 43 Parity Error Parity Error Page 4 44 Normal Frame Correctly Received Normal Frame Received Page 4 44 Move Engine Access Terminated Interrupt Command Frame Interrupt Command Frame Page 4 44 Command Frame Received on Pipe 0 Command Frame Received Page 4 44 Command Frame Received on Pipe 1 Command Frame Received on Pipe 2 Command Frame Received on Pipe 3 4 2 6 1 Discarded Read Answer Interrupt A discarded read answer received interrupt is generated when an Answer Frame has been received and the read pending flag MLI TRSTATR RPx of its correspondent Pipe is 0 Although named discarded the received data is available in the receiver data register until it is overwritten by the next incoming data User Manual 4 43 V 1 0 2005 11 MLI V1 0 Cinfineon i Micro Link Interface MLI 4 2 6 2 Parity Error Interrupt A parity error interrupt is generated when a programmable maximum number of receiver parity errors is reached 4 2 6 3 Normal Frame Received Move Engine Terminated Inter
243. the 751 are provided in Chapter 4 2 1 4 User Manual 4 14 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI 4 1 5 Naming Conventions MLI module transmitter signals are indicated with the prefix and MLI receiver signals are indicated with the prefix R The 4 line MLI Bus between a transmitter and a receiver outside the controllers uses signal names without any prefix as referred to in the timing diagrams of this section In order to emphasize where a signal is generated or sampled actions taken by the transmitter are described by referring to signals with the prefix T whereas receiver actions are referred to by signals with the prefix R Controller 1 Controller 2 Local Controller Remote Controller TREADY RREADY TVALID RVALID MLI TDATA RDATA Receiver TCLK RCLK Remote Controller Local Controller RREADY TREADY lt TVALID MLI Receiver P RDATA TDATA Transmitter RCLK TCLK Signal Naming Figure 4 13 Transmitter Receiver Signal Definitions 4 1 6 MLI Communication Examples The following section provides some basic example of the MLI communication from the point of view of the transmitter User Manual MLI V1 0 V 1 0 2005 11 Cinfineon i Micro Link Interface MLI Ready Delay Time LI TREADY TVALID P T EO 05874 M
244. the ADC basic conversion clock fac 00 fac Ssys 4 01 fac Ssys 2 10 fac fsys 16 11 fac fsvs 8 0 6 r Reserved Read as 0 should be written with O User Manual 6 22 V 1 0 2005 11 ADC V1 0 Cinfineon The Analog Digital Converter ADC Control 1 Register 012 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ICST S M CAL RES ADCTC ADSTC PLE w rh rh rw rw rw Field Bits Type Description ADSTC 5 0 rw ADC Sample Time Control Defines the ADC sample time 15 X 4 x lt ADSTC gt 1 ADCTC 11 6 rw ADC Conversion Time Control Defines the ADC basic conversion clock fac favs lt ADCTC gt 1 RES 12 rw Conversion Resolution Control 0 10 bit resolution default after reset 1 8 bit resolution CAL 13 rh Reset Calibration Phase Status Flag 0 A D Converter is not in calibration phase 1 A D Converter is in calibration phase SAMPLE 14 rh Sample Phase Status Flag 0 A D Converter is not in sampling 1 A D Converter is currently in the sample phase ICST 15 rw Improved Conversion and Sample Timing Selects the active timing control bit fields 0 Standard Conversion and sample time control controlled by the two bit fields ADC_CON ADCH and ADC_CON ADM 1 Improved conversion and sample time control controlled by the two bit fields ADC_CON1 ADSTC and ADC_CON1 ADCTC Note The limit values for fsc see data shee
245. the next use and to signal the master that the first SCLK cycle was received This sequence is repeated until 515 is de asserted 1 by the master after was asserted 515 MTSR Write Data 1 Write Data 2 Write Data n Header WRITE_FLOW Figure 5 4 Consecutive Writes SSC Read Operation CMD 0 For each SSC transfer that is received via the SSC interface the transaction header information is extracted from the first transmitted halfword which is the command CMD the increment indicator INCE and the address ADDR With this header the data from the source address on the CIC751 reads automatically and sends them back to the host via the SSC transmit buffer 55 The pin RDY is provided for additional synchronization between the host and slave This pin or information is required due to the fact that the master does not know how much time system cycles is exactly consumed by the CIC751 for fetching the requested read data This depends on the frequency of the 751 and the currently active 751 register accesses performed by the DMA Therefore the RDY pin is introduced to ensure that the read data is ready for transmission RDY is asserted The RDY pin should be used by the master in the following way e f RDY changes from de asserted 0 to asserted 1 the master starts to generate 16 clock cycles for SCLK e f RDY changes from asserted 1 to de asserted 07 the master takes no act
246. toggle or leave the bits in the OUT register unchanged When selected as general purpose output line the actual logic level at the pin can be examined through reading latch Pn IN and compared against the applied output level This can be used to detect some electrical failures at the pin caused through external circuitry Collisions on the external communication lines can be detected when a high level 1 is output but a low level 0 is seen when reading the pin value via the input register Pn IN User Manual 7 1 V 1 0 2005 11 Parallel Ports V1 0 Cinfineon Parallel Ports 7 1 Port 0 This section describes the control mechanisms of all pins other than the ADC analog channels and the reset pin PORST 7 1 1 Block Diagram Figure 7 1 shows the different options for the control of port 0 Input Output Control Register Pul up Pul down OMR Control Output Modification Reg PO OUT Data Output Register Output Driver Schmitt PO IN Trigger Data Input lt Register Pad Control Logic P Direct Data Input Figure 7 1 Port 0 Control Structure 7 1 2 Input Stage The input value of each pin can be used in two different ways 1 The input value of pin 0 x is always available at bit PO_IN Px 2 The input can be used directly by peripheral if connected a pins P0 1 P0 3 P0 6 and 7 are connected to the MLI b pins P0 2 P0 6 and P0 7 are conn
247. tored in the receiver Pipe x base address register bit field MLI RPOBAR ADDR This bit field determines the base address of the Pipe x Remote Window The received size is stored in the receiver Pipe x status register bit field MLI RPOSTATR BS This bit field determines the number of offset address bits of the Pipe x Remote Window The information about the received frame type 2 00g for Copy Base Address Frame is stored in the receiver control register bit field MLI RCR TF Interrupt status flag RISR NFRI Normal Frame received is set and an MLI Request is generated if enabled by MLI RIER NFRIE 01g or 10g User Manual 4 21 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI 4 2 1 2 Data Frames Data frames transmit the write data and optionally the write offset Local NLI Controller MLI Transmitter Ready Transfer window x is written Offset Data Width TPxAOFR AOFF Offset TPxDATAR DATA Data TPxSTATR DW Width TRSTATR DVx 1 TCR NO 1 Address Prediction Calculate TPxSTATR AP and TPxSTATR OP yes TPxSTATR OP 0 no Remote NLI Controller MLI Receiver Ready Pipe x initialized Send Write Offset and Data Frame of pipe x Parity check amp acknowledge frame RADRR ADDR RPxBAR ADDR RPxBAR modified by Offset Send Optimized Write Frame of pipe x lt Parity check amp acknowledge frame RADRR
248. transfers of four DMA word moves or 128 transfers of eight DMA word moves User Manual 3 10 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller 3 2 3 DMA Principles The DMA controller supports DMA moves from one address location to another one DMA moves can be requested either by hardware or by software DMA hardware requests are triggered by specific request lines from the peripheral modules or from other DMA channels The number of available DMA request lines from a peripheral module varies depending on the module functionality Typically the occurrence of a receive or transmit data interrupts in a peripheral module are able to generate a DMA request User Manual 3 11 V 1 0 2005 11 DMA V1 0 Cinfineon Direct Memory Access Controller 3 2 4 DMA Channel Functionality Each of the 8 DMA channels has one associated register set containing six 32 bit registers These registers are numbered by one index to indicate the related DMA channel Index n refers to the channel number n 0 7 within the DMA Sub Block Example CHCR04 is the Control Register of DMA channel 4 in Sub Block 0 The register set of a DMA channel register contains the following registers e Channel Control Register CHCROn for details see Page 3 39 e Channel Status Register CHSROn for details see Page 3 42 e Channel On Address Control Register ADRCROn for details see Page 3 43 Channel Source Ad
249. ts 4 41 Parity Time out Error Interrupt 4 43 Normal Frame Sent x Interrupt 4 43 Command Frame Sent Interrupt 4 43 Receiver Interrupts 4 43 Discarded Read Answer Interrupt 4 43 Parity Error Interrupt 4 44 Normal Frame Received Move Engine Terminated Interrupt 4 44 Interrupt Command Frame Interrupt 4 44 Command Frame Received Interrupt 4 44 Rate Generation 4 45 MLI Kernel Registers 4 47 General Registers 4 49 Fractional Divider Register 4 49 Set Clear Register 4 51 Global Interrupt Set Register 4 53 Output Input Control Register 4 54 MLI Transmitter Registers 4 59 Transmitter Control Register 4 59 Transmitter Status 4 62 Transmitter Pipe x Status Registers 4 64 Transmitter Command Register 4 66 Transmitter Receiver Status Register 4 68 Transmitter Pipe x
250. tting bit ICST in register CON 1 in Compatibility Mode or by selecting Enhanced Mode Note The conversion clock fgg must not exceed 20 MHz User Manual 6 12 V 1 0 2005 11 ADC V1 0 Cinfineon The Analog Digital Converter Standard Timing Control Standard timing control is performed by using two 2 bit fields in register ADC_CON Bit field ADCTC conversion time control selects the basic conversion clock fac used for the operation of the A D Converter The sample time is derived from this conversion clock and controlled by bit field ADSTC The sample time is always a multiple of 8 fac periods Table 6 3 lists the possible combinations Table 6 3 Standard Conversion and Sample Timing Control ADC_CON ADCTC Converter ADC CON ADSTC Sample Time Basic Clock fac 00 fapc 4 00 X 8 01g Taoc 2 01g fgc X 16 10 fapc 16 10 fgc X 32 11g fapc 8 11g taco X 64 Improved Timing Control To provide a finer resolution for programming of the timing parameters wider bit fields have been implemented for timing control the 2 bit bit fields in register are disregarded in all cases In Compatibility Mode with bit ADC_CON1 ICST 1 the bit fields in register are used for all conversions In Enhanced Mode bit ADC_CTRO MD 1 the bit fields in register ADC_CTR2 are used for Standard Conversions Injected conversions use the bit fields in register ADC_
251. tual address RPxBAR ADDR 0 3 and the result is stored MLI RPXBAR ADDR x 0 3 and in MLI RADRR ADDR The received data is stored in the receiver data register MLI RDATAR right aligned unused bits are 0 User Manual 4 23 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI The data width of the received data is stored in bit field MLI RCR DW The information about the received frame type 10g for a write frame is stored into bit field MLI RCR TF Interrupt status flag MLI RISR NFHI is set and an MLI Request is generated if enabled by RIER NFRIE 01g or 10g After all these actions related to the reception of a write frame by the remote receiver are performed the data that has been received from the Local Controller is ready to be written into the Remote Window related to the receiving Pipe This write operation can be executed in two ways MLI RCR MOD 0 Automatic Data Mode is disabled In this mode the DMA is request by an MLI Request generated for the Normal Frame received interrupt RISR NFRI if enabled by RIER NFRIE 10 to transfer the received write data from the MLI receiver to the Remote Window address Therefore it must read the data from RDATAR together with width MLI RCR DW and the address stored in MLI RADRR and write it to the indicated address location MLI RCR MOD 1 Automatic Data Mode is selected In this mode the MLI automatically writes the
252. ty bit P Header 01234 12 20 m m Bit Offset Address 16 Bit Data mp 36 m m Bit Offset Address 32 Bit Data d write offs data Figure 4 7 Write Offset and Data Frame Details about the Write Offset and Data Frame handling of the CIC751 are provided in Chapter 4 2 1 2 User Manual 4 9 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI 4 1 4 3 Optimized Write Frame An Optimized Write Frame is used by the Local Controller to send 8 bit 16 bit or 32 bit wide data to the Remote Controller In contrast to a Write Offset and Data Frame no write offset is transmitted because the offset address for the write data is predicted and calculated by the MLI receiver of the Remote Controller An Optimized Write Frame allows a higher data bandwidth than Write Offset and Data Frames An optimized frame is only send if the predicted address matches with the actually written address within the Local Controller Otherwise an Write Offset and Data Frame is generated The Write Offset and Data Frame contains the following parts Header The header starts with Frame Code FC 11g followed by the Pipe number PN of the Transfer Window that has been the target of the write operation Write data field The write data field can be 8 16 or 32 bit wide depending on the data width of the write access to the Transfer Window e Parity bit P
253. ty error condition is detected and MPE becomes 0 or is already 0 a receiver parity error event is generated see Page 4 34 0000 A receiver parity event is generated if a receiver error condition is detected 0001 A receiver parity event is generated if a receiver error condition is detected 0010 A receiver parity event is generated if two receiver error conditions are detected 1111 A receiver parity event is generated if 15 receiver error conditions are detected BEN 20 rw Break Out Enable When setting BEN 1 the MLI receiver generates an MLI Break Event when a Pipe Command Frame with command code CMD 1111 is received 0 MLI Break Event generation is disabled 1 MLI Break Event is enabled RCVRST rw Receiver Reset This bit forces the receiver to be reset in order to be able to change MLI OICR settings without affecting the receiver registers 0 The MLI receiver is in operating mode 1 The MLI receiver is held in reset state and OICR can be modified without unintentional actions in the receiver 23 21 31 25 A Reserved Read as 0 should be written with O User Manual MLI V1 0 4 77 V 1 0 2005 11 Cinfineon 4 3 3 2 The Receiver Pipe x Base Address Register RPxBAR x 0 3 is a read only register that contains the complete target address in the Remote Window of Pipe x MLI RPOBAR MLI Receiver Pipe 0 Base Address Register 26C MLI RP1BAR MLI
254. ucture of an MLI connection between two microcontrollers requires a transmitter unit and a receiver unit in both MLI modules local and remote for communication Physically the communication is performed via two separate serial MLI buses Logically the information flow of each MLI frame can be assigned to one of the MLI Buses see Figure 4 4 Remote Controller Local Controller MLI Module MLI Module Copy Base Address Frame Write Offset and Data Frame Discrete Read Frame Transmitter Command Frame Optimized Write Frame Optimized Read Frame Answer Frame Receiver Transmitter MCA05877 M Receiver Figure 4 4 Logic Frame Assignment to Local Remote Controller The general layout of a frame is shown in Figure 4 5 It contains the following parts User Manual 4 6 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI frame starts with 4 bit header field that contains 2 bit Frame Code FC anda 2 bit Pipe Number PN The data field can contain address data or control information The length of the data field depends on the frame type The frame is terminated by a parity bit P with even parity see Page 4 17 which is calculated over header and data field bits Header Data Field Frame Code PN Pipe Number P Parity MCA05878 Figure 4 5 General Frame Layout The Frame Code FC and the length of the data field
255. ue 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DATA 31 16 15 14 13 12 11 r 10 9 8 7 6 5 4 3 2 1 0 DATA 15 0 T Field Bits Type Description DATA 31 0 rh Data Whenever a location within a Transfer Window is written the data is loaded in this bit field User Manual 4 71 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI 4 3 2 8 Transmitter Data Read Answer Register The Transmitter Data Read Answer Register MLI_TDRAR contains the read data for the transmission of an Answer Frame MLI_TDRAR MLI Transmitter Data Read Answer Register 250 Reset Value 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DATA 31 16 rwh 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATA 15 0 rwh Field Bits Type Description DATA 31 0 wh Data This bit field is loaded with data that is read from the address requested by a read frame An update of this bit field triggers the start of an Answer Frame with DATA used as content of the Answer Frame User Manual 4 72 V 1 0 2005 11 MLI V1 0 Cinfineon i Micro Link Interface MLI 4 3 2 0 Transmitter Pipe x Base Address Register write only Transmitter Pipe x Base Address Register MLI TPxBAR x 0 3 represents the 28 bit Pipe x Remote Window base a
256. uest is accepted MPE 7 4 rwh Maximum Parity Errors This bit field determines the maximum number of transmitter parity error conditions that can be still detected until a transmitter parity error event is generated see Page 4 34 With each condition detected MPE is decremented down to 0 0000 A parity error interrupt event can be generated if a transmitter parity error condition is detected 0001 A parity error interrupt event can be generated if a transmitter parity error condition is detected 0010 A parity error interrupt event can be generated if 2 transmitter parity error conditions are detected 0011 A parity error interrupt event can be generated if 3 transmitter parity error conditions are detected 1111 A parity error interrupt event can be generated if 15 transmitter parity error conditions are detected User Manual 4 60 V 1 0 2005 11 MLI V1 0 Cinfineon CIC751 Micro Link Interface MLI Field Bits Type Description MNAE 9 8 rwh Maximum Non Acknowledge Errors This bit field determines the maximum number of consecutive non acknowledge error conditions that can be still detected in the transmitter until a time out interrupt is generated MNAE is decremented down to 0 at each non acknowledge error condition When MNAE 0 or becoming 0 a time out interrupt event is generated MNAE is automatically set to 11g after a successful frame transmission see Page 4 37
257. ure 4 3 shows the organization of Transfer Windows and Remote Windows with a possible assignment in the Local and Remote Controller Each of the four Pipes assigns one Transfer Window to one Remote Window with its base address and window size User Manual MLI V1 0 4 4 V 1 0 2005 11 Cinfineon Micro Link Interface MLI Local Controller Remote Controller Address Map Address Map Large Transfer Window O _ gt O 002 Remote Window 0 Large Transfer Window 1 n Large Transfer lt Windows Pipe 2 Remote Window 2 Large Transfer Window 2 p Large Transfer Window 3 Pipe d Remote Window 3 7 di d 7 Small Transfer Window 0 lt Small Small Transfer Window 1 Transfer 26 EP Windows Small Transfer Window2 2 Pipe 1 Remote Window 1 Small Transfer Window 3 9 i 5872 Figure 4 3 Transfer Remote Window Assignment Example During initialization the Pipes the base addresses sizes the Remote Windows are transmitted from the Local Controller to the Remote Controller In the example of Figure 4 3 two large Transfer Windows and two small Transfer Windows are assigned to Remote Windows Pipe 1 and Pipe 2 cover the full range of their transfer and Remote Windows Pipe 0 and Pipe 3 address only sub areas of the related Transfer Windows Remote Windows
258. version or a conversion sequence is started by setting bit ADC_CON ADST or ADC_CTRO ADST The busy flag ADC_CON ADBSY or ADC CTRO ADBSY will be set and the converter then selects and samples the input channel which is specified by the channel selection bit field ADC_CON ADCH or ADC CTRO ADCH The sampled level will then be held internally during the conversion When the conversion of this channel is complete the result is transferred into the result register together with the number of the converted channel and the interrupt request is generated The conversion result is placed into bit field ADC_DAT ADRES ADC_CON ADST or ADC_CTRO ADST remains set until cleared either by hardware or by software Hardware clears the bit dependent on the conversion mode In Fixed Channel Single Conversion Mode ADC_CON ADST or ADC_CTRO ADST is cleared after the conversion of the specified channel is finished In Auto Scan Single Conversion Mode ADC_CON ADST ADC_CTRO ADST is cleared after the conversion of channel 0 is finished User Manual 6 4 V 1 0 2005 11 ADC V1 0 Cinfineon The Analog Digital Converter Note In the Continuous Conversion Modes ADC_CON ADST or ADC CTRO ADST is never cleared by hardware Stopping the ADC via software is performed by clearing bit ADC_CON ADST or bit ADC_CTRO ADST The reaction of the ADC depends the conversion mode Fixed Channel Single Conversion Mode the ADC finishes the conversi
259. via bit field SCU SYSCON MTM This feature is independent of the currently selected conversion mode If the MTM is enabled the analog input is connected to ADC ground via an internal resistor This structure creates a voltage divider to ground Therefore conversion delivers a smaller result if MTM is enabled User Manual 6 11 V 1 0 2005 11 ADC V1 0 Cinfineon The Analog Digital Converter 6 5 Conversion Timing Control When conversion is started first the capacitances of the converter are loaded via the respective analog input pin to the current analog input voltage The time to load the capacitances is referred to as sample time Next the sampled voltage is converted to a digital value in successive steps which correspond to the resolution of the ADC During these phases except for the sample time the internal capacitances are repeatedly charged and discharged via pins Varer and Vagnp The current that must be drawn from the sources for sampling and changing charges depends on the time required for each respective step because the capacitors must reach their final voltage level within the given time at least with a certain approximation The maximum current however that a source can deliver depends on its internal resistance The time that the two different actions during conversion take sampling and converting can be programmed within a certain range in the CIC751 relative to the system clock The absolute time th
260. ways remain at the logic level of the last transmitted data bit When the serial interfaces are enabled the master device can initiate the first data transfer This value is copied into the shift register assumed to be empty at this time and the selected first bit of the transmit data will be placed onto the MTSR line on the next clock from the shift clock generator Depending on the selected clock phase a clock pulse is generated on the SCLK line With the opposite clock edge the master simultaneously latches and shifts in the data detected at its input line MRST This exchanges the transmit data with the receive data Because the clock line is connected to all slaves their shift registers will be shifted synchronously with the master s shift register shifting out the data contained in the registers and shifting in the data detected at the input line After the pre programmed number of clock pulses via the data width selection the data transmitted by the master is contained in all slaves shift registers while the master s shift register holds the data of the selected slave In the master and all slaves the content of the shift register is copied into the Receive Buffer 55 A slave device will immediately output the selected first bit MSB or LSB of the transfer data at pin MRST when the contents of the transmit buffer is copied into the slave s shift register Bit SSC_STAT BSY is not set until the first clock edge at SCLK appea
261. written with O 7 3 Ports Register Overview All port register can only be accessed by 32 bit accesses 8 bit or 16 bit accesses are not allowed and lead to errors Table 7 9 Port 0 Registers Register Register Long Name Address Description Short Name see PO_OUT Port 0 Output Register 7 6 P0_OMR Port 0 Output Modification Register A044 Page 7 7 PO IOCRO Port 0 Input Output Control Register 0 A104 Page 7 8 PO Port 0 Input Output Control Register 4 A144 Page 7 9 PO_IOCR8 0 Input Output Control Register 8 A184 Page 7 10 User Manual 7 15 V 1 0 2005 11 Parallel Ports V1 0 Cinfineon CIC751 Parallel Ports Table 7 9 Port 0 Registers cont d Register Register Long Name Address Description Short Name see P0_IOCR12 Port 0 Input Output Control Register 12 A1CH Page 7 11 P0_IN Port 0 Input Register A244 Page 7 5 Table 7 10 Port 1 Registers Register Register Long Name Address Description Short Name see P1_IN Port 1 Input Register A644 Page 7 15 User Manual 7 16 V 1 0 2005 11 Parallel Ports V1 0 Cinfineon Register Overview 8 Register Overview This chapter describes all registers of the CIC751 It also describes the read write access rights of the specific address ranges registers 8 1 Address Map of CIC751 Table 8 1 shows the block address map of CIC751 Table 8 1 Block Address Map of CIC751
262. ws User Manual 4 45 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI over 3FFy Note that in Fractional Divider Mode the clock fy have a maximum period jitter of one fsys clock period This jitter is not accumulated over several cycles and does not exceed one cycle of fsys The frequency in Fractional Divider Mode is defined according to the following equation Pee STEP MLI 7 SYS 1024 4 2 The baud rate of MLI transmissions equals frc k which is defined by the frequency of clock signal fu divided by 2 to create the 50 duty cycle of the shift clock signal TCLK The signal TCLK toggling with each period of a jitter due to fractional dividing is propagated to TCLK f 72 4 3 User Manual 4 46 V 1 0 2005 11 MLI V1 0 Cinfineon Micro Link Interface MLI 4 3 MLI Kernel Registers Table 4 10 lists all of the registers associated with the MLI All registers can be accessed with 8 bit 16 bit or 32 bit write or read operations Accesses to address locations inside the MLI address range not targeting the indicated registers are not allowed The base address the MLI is 0000 0200 A register address is computed by adding the base address to the register offset address Table 4 10 MLI Kernel Registers Register Register Long Name Offset Description Short Name Address see MLI_FDR Fra
263. y is fed to a Voltage Controlled Oscillator VCO The VCO is part of the PLL with a feedback path A divider in the feedback path N divider divides the VCO frequency As well as N the correct range of fco must be chosen by configuring SCU_PLLCON PLLVB Table 2 2 VCO Ranges PLLVB 1 0 i Jvcomax 0 1 fvcobase IS the free running operation frequency of the PLL when no input clock is available These values are only preliminary and are later updated with more exact simulation and measurement results from the PLL The VCO band 100 150 MHz 150 200 MHz 200 250 MHz must be selected according to the desired VCO output frequency 100 250 2 Figure 2 3 illustrates how this output frequency depends on the input frequency and the multiplication factor User Manual 2 7 V 1 0 2005 11 STCU V 1 0 CIC751 Cinfineon System and Control Unit SCU 8 0 6 0 4 0 8 10 12 14 16 18 20 22 24 26 28 30 32 NDIV 1 e 100 9 150 200 250 Figure 2 3 VCO Band Selection Table 2 3 lists the possible N loop division rates and gives the valid output frequency range for face depending on N and the VCO frequency range Table 2 3 N Loop Division Rates N NDIV 1 NDIV frer for fvco 100 150 200 250 not allowed 12 5 18 75 25 00 31 25 11 11 16 66 22 22 27 77 10 00 15 00 20 00 25 00 3 22 4 84

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CIC751 User´s Manual