Errata to R32C/153 Group User`s Manual: Hardware
Contents
1. When the EID bit is 0 the corresponding EID bit in a received message is not compared When this bit is 1 the corresponding EID bit in a received message is compared Page 467 of 656 description in 25 1 4 2 is corrected as follows When the SID bit is 0 the corresponding SID bit in a received message is not compared When this bit is 1 the corresponding SID bit in a received message is compared Page 477 of 656 expression fCAN CAN system clock in line 5 of 25 1 9 5 is corrected as follows the peripheral bus clock Page 480 of 656 expression fCAN in line 6 of 25 1 10 3 is corrected as follows the peripheral bus clock Page 486 of 656 description of function of b7 in Figure 25 17 is corrected as follows b7 No register bit the read value is 0 Page 490 of 656 description of function of b6 b5 in Figure 25 19 is corrected as follows b6 b5 No register bits the read value is 0 Page 498 of 656 description in 25 1 20 8 is corrected as follows refer to TN 16C A229A E The BLIF bit becomes 1 if 32 consecutive dominant bits are detected on the CAN bus while the CAN module is in CAN operation mode After the BLIF bit becomes 1 bus lock can be detected again after either of the following conditions is satisfied After this bit is set to 0 from 1 recessive bits are detected bus lock is resolved After this bit is set to 0 from 1 the CAN module enters CAN reset mode and then ent2. Halt Mode Table 25 9 Receiver CAN module enters CAN reset mode without waiting for the end of message reception CAN module enters CAN halt mode after waiting for the end of Transmitter CAN module enters CAN reset mode after waiting for the end of message transmission 1 4 CAN module enters CAN halt mode after waiting for the end of CAN module enters CAN reset mode without waiting for the end of bus off recovery When the BOM bit is 00b A halt request from a program n 1 2 4 will be acknowledged only after bus off recovery When the BOM bit is 01b CAN module automatically enters CAN halt mode without waiting for the end of bus off recovery regardless of a halt request from a program When the BOM bit is 10b CAN module automatically enters CAN halt mode after waiting for the end of bus off recovery regardless of a halt request from a program When the BOM bit is 11b CAN module enters CAN halt mode without waiting for the end of bus off recovery if a halt is requested by a program during bus off message reception 2 3 message transmissio BOM bit Bit in the CiICTLR register i 0 to 3 Notes 1 If several messages are requested to be transmitted mode transition occurs after the completion of the first message transmission When CAN reset mode is being requested during suspend transmission mode transition occurs when the bus is idle the next transmission ends or the CAN module becomes
3. Table 10 7 is corrected as follows These are the values when the interrupt vectors are aligned to the addresses in multiples of 4 in the internal ROM However the condition does not apply to the fast interrupt Page 172 of 656 description in lines 4 to 5 and 7 to 8 of 10 8 as follows For maskable interrupts peripheral interrupts the interrupt request level select bits bits ILVL2 to ILVLO select a request level If two or more interrupt requests have the same request level the interrupt with higher priority predetermined by hardware is accepted The priorities of the reset and special interrupts such as the watchdog timer interrupt are determined by the hardware Note that the reset has the highest priority The following is the priority order determined by the hardware Page 179 of 656 register symbol IIOiE in line 16 of 10 13 is corrected as follows HOWE Page 183 of 656 description in lines 4 to 6 of 11 Watchdog Timer is corrected as follows Select either an interrupt request or a reset with the CMO6 bit in the CMO register for when the watchdog timer underflows Once the CMO6 bit is set to 1 reset it cannot be changed to 0 watchdog timer interrupt by a program It can be set to 0 only by a reset Page 183 of 656 register symbol WKD of 11 Watchdog Timer is corrected as follows WDK ePage 188 of 656 expression a value more than 00000001h in the Specification of DMA tr
4. again the VMF bit becomes 1 VCC gt Vdet and the LVDF bit becomes 1 At this point an interrupt request is generated when the LVDIEN bit is 1 2013 Renesas Electronics Corporation All rights reserved stENESAS Page 1 of 12 RENESAS TECHNICAL UPDATE TN 16C A233A E Date Sep 24 2013 Page 119 of 656 Figure 7 1 is corrected as follows WAIT instruction wait mode wait_mode STOP instruction stop mode stop_mode S Low speed clock o4 a Low voltage detection interrupt f8 1015 O CLKOUT Output signal from priority resolver f32 k aay CM01 and CM00 Main clock oscillator Detection enabled XIN AOUT Oscillator stop Peripheral clock source detection interrupt Peripheral clocks Main clock request stop detector gt fAD gt Main clock gt f PLL clock TEG DoH atei e f32 EAE eH tn BCS PM26 ee CM10 PLL oscillator BCD CM02 ees Ra d EEAS n Base o i Clock CCD wait_mode gt iim CPU stop_mode e aS clock Sub clock oscillator cm3o PCD l XCIN XCOUT Peripheral 5 1 q oA Note 5 CPSR 1 i Divider d Sub clock fC reset CM04 D Ln 0 1 32 stop_mode bus clock fOCO4 1 4 On chip oscillator On chip oscillator clock fOCO 125 kHz CMO0 to CM02 CM04 and CMO05 Bits in the CMO register PM26 Bit in the PM2 register CM10 Bit in the CM1 register CST Bit in the TCSPR register CM20 Bit in the CM2 register CPSR Bit in the CP
5. 3 2 is changed as follows timer Bj interrupt handler Page 251 of 656 description of Note 1 in Figure 16 3 is modified as follows Set this register after setting the PRC1 bit in the PRCR register to 1 write enabled Also rewrite this register while timers A1 A2 A4 and B2 are stopped Page 258 of 656 description The sum of setting values for registers TAi and TAi1 should be identical to the setting value of the TB2 register in this mode is deleted from lines 8 to 9 of 16 3 Page 258 of 656 description in line 11 of 16 3 is corrected as follows Figure 16 11 shows registers TA1M TA2M TA4M TA11M TA21M and TA41M in this function Page 263 of 656 bit symbol INV06 in Note 3 of Figure 16 16 is corrected as follows INV16 Page 264 of 656 register symbol INV1 in Note 2 of Figure 16 18 is corrected as follows INVC1 ePages 272 and 273 of 656 descriptions for the CRD bit in Figures 17 5 and 17 6 are modified as follows 0 CTS function enabled ae ies Function Disable Bit 4 CTS function disabled on Page 274 of 656 description of function of the UiIRS bit in Figure 17 7 is modified as follows 0 Transmit buffer is empty TI 1 1 Transmission is completed TXEPT 1 stENESAS Page 5 of 12 RENESAS TECHNICAL UPDATE TN 16C A233A E Date Sep 24 2013 Page 274 of 656 bit name Logical Inversion Select Bit in Figure 17 7 is modified as follows Logic I
6. Date Sep 24 2013 RENESAS TECHNICAL UPDATE 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan Renesas Electronics Corporation Product MPU amp MCU Document TN 16C A233A E Category No Errata to R32C 153 Group User s Manual Information Hardware Category Technical Notification Title Applicable Ref renc R32C 153 Group User s Manual ae R32C 153 Group Document Hardware Rev 1 10 REJO9B0505 0110 This document describes corrections to the R32C 153 Group User s Manual Hardware Rev 1 10 The corrections are indicated in red in the list below Page 16 of 656 register symbol R3RO in line 3 of 2 1 1 is corrected as follows R3R1 Page 34 of 656 register name Increment Decrement Counting Select Register in Table 4 15 is corrected as follows Increment Decrement Select Register ePages 61 62 75 76 89 90 103 and 104 of 656 register name CAN3 2 1 0 Acceptance Mask Register 0 1 2 3 4 5 6 7 in Tables 4 42 4 43 4 56 4 57 4 70 4 71 4 84 and 4 85 is corrected as follows CAN3 2 1 0 Mask Register 0 1 2 3 4 5 6 7 ePages 64 78 92 and 106 of 656 reset value XXXX XX00b for registers C3MSMR C2MSMR C1MSMR and COMSMR in Tables 4 45 4 59 4 73 and 4 87 is corrected as follows 0000 0000b Page 116 of 656 description of the third paragraph of 6 2 1 is modified as follows When the voltage rises to or above Vdet R
7. SRF register CM30 and CM31 Bits in the CM3 register BCS Bit in the CCR register Notes 1 The value of p can be selected by setting bits PM36 and PM35 in the PM3 register p 2 4 6 8 2 The value of n can be selected by setting bits CNT3 to CNTO in the TCSPR register n 0 to 15 When n is 0 the clock is not divided 3 The value of b can be selected by setting bits BCD1 and BCDO in the CCR register b 2 3 4 6 4 The value of m can be selected by setting bits CCD1 and CCDO in the CCR register m 1 to 4 5 The value of q can be selected by setting bits PCD1 and PCDO in the CCR register q 2 to 4 Figure 7 1 Clock Generation Circuitry Page 121 of 656 bit name XCIN XCOUT Drive Power Select Bit in Figure 7 3 is modified as follows XCIN XCOUT Drive Strength Select Bit stENESAS Page 2 of 12 RENESAS TECHNICAL UPDATE TN 16C A233A E Date Sep 24 2013 Page 122 of 656 bit name XIN XOUT Drive Power Select Bit in Figure 7 4 is modified as follows XIN XOUT Drive Strength Select Bit Page 122 of 656 description of Note 2 in Figure 7 4 is modified as follows When the BCS bit in the CCR register is 0 PLL clock selected as base clock source the PLL frequency synthesizer does not stop oscillating even if the CM10 bit is set to 1 Page 122 of 656 bit symbol CM02 in Note 3 of Figure 7 5 is corrected as follows CM20 Page 132 of 656 description of the last paragr
8. a receiver If the CAN bus is locked in dominant state the program can detect this state by monitoring the BLIF bit in the CiEIFR register The CAN module does not enter CAN Halt mode while the CAN bus is locked in dominant state Enter CAN reset mode instead If a CAN bus error occurs during reception after CAN halt mode is requested the CAN module enters CAN halt mode However the CAN module does not enter CAN Halt mode when the CAN bus is locked in dominant state If a CAN bus error or arbitration lost occurs during transmission after CAN reset mode or CAN halt mode is requested the CAN module enters the requested operating mode However the CAN module does not enter CAN Halt mode when the CAN bus is locked in dominant state Page 510 of 656 description of the first paragraph in 25 2 3 is modified as follows CAN sleep mode is used for reducing current consumption by stopping the clock supply to the CAN module After a MCU reset the CAN module starts from CAN sleep mode Page 513 of 656 q value q 1 2 3 4 in Figure 25 36 is corrected as follows q 2 3 4 Page 525 of 656 description of the first and second paragraphs in 26 I O Pins is corrected as follows refer to TN 16C A200A E Each pin of the MCU functions as a programmable I O port or an I O pin for integrated peripherals These functions can be switched by the function select registers The pull up resistors are enabled for every group of four pins Howev
9. ansfer start up in Table 12 1 is corrected as follows a value other than 00000000h Page 196 of 656 description of the first paragraph in 12 1 is corrected as follows The transfer cycle is composed of bus cycles to read data from source read or to write data to destination write memory or an SFR Page 202 of 656 source address FFFFFFFh in Note 1 of Table 13 1 is corrected as follows FFFFFFFFh Page 202 of 656 bit symbol IIRLT in the fifth bullet point of 13 1 is corrected as follows RLT ePages 204 and 205 of 656 expression DMA II transfer complete interrupt vector address in lines 3 to 4 and the seventh bullet point of 13 1 2 and Figure 13 2 is corrected as follows jump address for the DMA II transfer complete interrupt handler ePages 204 and 207 of 656 expression interrupt vector in Figure 13 2 and 13 1 4 is corrected as follows interrupt vector space Page 205 of 656 expression jump address in the seventh bullet point of 13 1 2 is corrected as follows start address Page 206 of 656 bit names of the OPER bit and bits CNTO to CNT2 in Figure 13 3 are modified as follows OPER Calculation Result Transfer Select Bit CNTO to CNT2 Number of Transfers Setting Bit Page 216 of 656 description of the third bullet point of 15 1 is corrected as follows One shot timer mode The timer outputs pulses after a trigger input until the counter
10. aph of 7 1 4 is modified as follows It starts running when setting any of the following bits to 1 the CM31 bit in the CM3 register or the PM22 bit in the PM2 register It is not necessary to wait for stabilization because the on chip oscillator instantly starts oscillating Page 133 of 656 description Refer to Figure 7 18 State Transition when the sub clock is used is deleted from 7 2 Page 142 of 656 description of 7 7 2 is modified as follows The base clock stops in wait mode so clocks generated by the base clock the CPU clock and peripheral bus clock stop running as well Thus the CPU and watchdog timer operated by these two clocks also stop Page 151 of 656 IOBC is added to description in Function of the PRC1 bit in Figure 9 1 as follows Enable writing to registers PMO PM2 INVCO INVC1 and IOBC Page 151 of 656 description Bits PRCO and PRC1 do not automatically become 0 They should be set to 0 by a program is deleted from Note 1 of Figure 9 1 Page 155 of 656 description of Note 1 in Figure 10 1 is modified as follows The peripheral interrupts are generated by the corresponding peripherals in the MCU Page 156 of 656 the second paragraph of 5 in 10 2 is modified as follows The stack pointer SP used for this interrupt differs depending on the software interrupt numbers For software interrupt numbers 0 to 127 when an interrupt request is accepted the U fla
11. ected pins including one to four prioritized pins is repeatedly converted into a digital code The prioritized pins are selected by setting bits SCAN1 and SCANDO in the ADOCON 1 register and bits APS1 and APSO in the ADOCON2 register stENESAS Page 6 of 12 RENESAS TECHNICAL UPDATE TN 16C A233A E Date Sep 24 2013 Page 341 of 656 Figure 20 1 is corrected as follows gt Upper byte of data bus 7 2 Lower byte of data bus Li Upper byte E Lower byte CRCD register CRC generator CRCIN register Figure 20 1 CRC Calculator Block Diagram Page 355 of 656 descriptions for bits UDO and UD1 in Figure 22 7 are modified as follows Bit Symbol Bit Name Function UDO Increment mode Increment decrement mode Increment Decrement Control Bit Two phase pulse signal processing mode Do not use this combination Page 356 of 656 Note 3 The GOC bit becomes 0 after gating is cleared is deleted from Figure 22 8 Page 363 of 656 description in the second bullet point of the reset conditions in Table 22 2 is modified as follows An input of low signal into the external interrupt pin INTO or INT1 as follows Page 363 of 656 description of the first bullet point of the selectable functions in Table 22 2 is corrected as follows The base timer starts counting when the BTS or BTiS bit is set to 1 When the base timer reaches FFFFh it starts decrementing When the RST1 bit
12. er when a pin functions as an output pin a pull up resistor is disabled regardless of the register settings stENESAS Page 10 of 12 RENESAS TECHNICAL UPDATE TN 16C A233A E Date Sep 24 2013 Page 525 of 656 Figure 256 1 is corrected as follows refer to TN 16C A200A E The use of pull up resistor selection PDi_j Port output Peripheral function 1 output Peripheral function 2 output Peripheral function 3 output Peripheral function 4 output Peripheral function 5 output Peripheral function 6 output Peripheral function 7 output PSEL2 PSEL1 PSELO ASEL Port input Peripheral functions 1 to 7 input Analog I O Figure 26 1 Typical I O Pin Block Diagram i 0 to 15 j 0 to 7 Page 525 of 656 description in the last paragraph of 26 I O Pins is corrected as follows The input only port P8_5 shares a pin with NMI and has neither function select register nor the corresponding direction bit Port P14_1 also functions as an input only port The function select register and bit 1 in the PD14 register are reserved Port P9 is protected from unexpected write accesses by the PRC2 bit in the PRCR register Ports P3 P7 and P8 are protected from unexpected write accesses by the PRC30 bit in the PRCR3 register refer to 9 Protection ePages 529 532 and 533 of 656 expressions IIO0 output and IIO1 output in Figures 26 4 26 7 and 26 8 are changed as follows 1I00_i output and I
13. ers CAN operation mode again internal reset stENESAS Page 8 of 12 RENESAS TECHNICAL UPDATE TN 16C A233A E Date Sep 24 2013 Page 507 of 656 Note 3 is added to Figure 25 34 as follows refer to TN 16C A229A E CPU reset i SLPM 0 when CANM 01b CANM 00b CAN sleep mode CAN reset mode CAN operation mode CANM 01b When the BOM bit is SLPM 0 when 00b or 11b no halt CANM 10b request and 11 consecutive recessive bits are detected 128 times or the RBOC bit is 1 CAN operation mode CAN halt mode bus off state CANM 10b CANM SLPM BOM and RBOC Bits in the CiCTLR register Notes 1 The transition timing from the bus off state to CAN halt mode depends on the setting of the BOM bit When the BOM bit is 01b the state transition timing is immediately after entering the bus off state When the BOM bit is 10b the state transition timing is at the end of the bus off state When the BOM bit is 11b the state transition timing is at the setting of the CANM bit to 10b CAN halt mode Write only to the SLPM bit to exit set CAN sleep mode The CAN module does not enter CAN Halt mode while the CAN bus is locked in dominant state Enter CAN reset mode instead stENESAS Page 9 of 12 RENESAS TECHNICAL UPDATE TN 16C A233A E Date Sep 24 2013 Page 509 of 656 Table 25 9 is corrected as follows refer to TN 16C A229A E Operation in CAN Reset Mode and CAN
14. g is saved and set to 0 to select the interrupt stack pointer ISP during the interrupt sequence The saved data of the U flag is restored upon returning from the interrupt handler For software interrupt numbers 128 to 255 the stack pointer does not change during the interrupt sequence Page 158 of 656 description of 10 5 is corrected as follows Each interrupt vector has a 4 byte memory space in which the start address of the associated interrupt handler is stored When an interrupt request is accepted a jump to the address set in the interrupt vector takes place Figure 10 2 shows an interrupt vector Page 159 of 656 description in the Remarks for the BRK instruction in Table 10 1 is corrected as follows If address FFFFFFE h is FFh a jump to the interrupt vector of software interrupt number 0 in the relocatable vector table takes place Page 166 of 656 description for the IR bit below Figure 10 4 is corrected as follows The IR bit becomes 1 interrupt requested when an interrupt request is generated this bit setting is retained until the interrupt request is accepted When the request is accepted and a jump to the corresponding interrupt vector takes place the IR bit becomes 0 no interrupt requested The IR bit can be set to 0 by a program This bit should not be set to 1 stENESAS Page 3 of 12 RENESAS TECHNICAL UPDATE TN 16C A233A E Date Sep 24 2013 Page 170 of 656 description of Note 1 in
15. h is read while reloading is in progress When a value is set to the TBj register while the timer counter is stopped if the TBj register is read before the count starts the set value is read Page 642 of 656 expression TBj interrupt handler in the eighth bullet point of 30 6 3 2 is changed as follows timer Bj interrupt handler Page 644 of 656 expression restart condition in 30 8 3 is changed as follows repeated START condition Page 650 of 656 description in 30 11 7 is corrected as follows The time to execute software commands program block erase lock bit program and protect bit program increases as the number of program erase cycles increases If the number of program erase cycles exceeds the endurance value specified in the electrical characteristics it may take an unpredictable amount of time to execute the software commands The wait time for executing software commands should be set much longer than the execution time specified in the electrical characteristics Page 650 of 656 description in the first bullet point of 30 11 8 is corrected as follows The minimum values of program erase cycles specified in the electrical characteristics are the maximum values that can guarantee the initial performance of the flash memory The program erase operation may still be performed even if the number of program erase cycles exceeds the guaranteed values stENESAS Page 12 of 12
16. in the GiBCR1 register is 1 the base timer is reset by matching with the GiPOO register the timer counter starts decrementing two counts after the base timer value matches the GiPOO register setting When the timer counter reaches 0000h it starts incrementing again refer to Figure 22 20 ePages 374 376 and 379 of 656 expression Input to the IlOi_j pin in Figures 22 24 to 22 26 is corrected as follows IlOi_j pin Page 390 of 656 expression b6 b5 b4 in Figures 23 3 is corrected as follows b2 b1 b0 stENESAS Page 7 of 12 RENESAS TECHNICAL UPDATE TN 16C A233A E Date Sep 24 2013 Page 397 of 656 description write to this register in 16 bit units in Figures 23 11 is corrected as follows read this register in 16 bit units Page 398 of 656 description with bits CKS2 to CKSO to the first paragraph of 23 1 1 is added as follows When the MSS bit in the SSICRH register is 1 master mode select a transmit receive clock from among seven internal clocks f BCLK divided by 4 8 16 32 64 128 and 256 with bits CKS2 to CKSO Page 412 of 656 bit symbol MSL in line 14 of 23 1 7 is corrected as follows MLS Page 460 of 656 descriptions for the RBOC bit in Figure 25 2 are modified as follows 0 Nothing occurred RBOC Forced Recovery From Bus off Bit 1 Forced recovery from bus off Page 467 of 656 description in 25 1 4 1 is corrected as follows
17. lO1_i output Page 531 of 656 PD3_i register in line 4 of the paragraph below Figure 26 6 is corrected as follows PD3_i bit Page 573 of 656 Note 2 of Table 27 12 is corrected as follows The program is performed in 64 bit 4 word units A sequence of commands consists of commands from the second to fifth The upper 29 bits of the address WA should be fixed and the lower 3 bits of respective commands from the second to fifth should be set to 000b 010b 100b and 110b for the addresses Oh 2h 4h and 6h or 8h Ah Ch and Eh Page 579 of 656 description in 27 3 4 7 is corrected as follows Execute this command to verify if a specified block in the flash memory is locked This command can be used when the LBM bit in the FMRO register is 1 read by the LBS bit The LBS bit in the FMSRO register reflects the lock bit status of the specified block when the following is performed first write 0071h to address FFFFF800h and verify that the FCA bit in the FMRO register becomes 0 Then write OODOh to an even address of the corresponding block Read the LBS bit after the RDY bit in the FMSRO register becomes 1 ready stENESAS Page 11 of 12 RENESAS TECHNICAL UPDATE TN 16C A233A E Date Sep 24 2013 Page 587 of 656 description in 27 6 7 is corrected as follows The time to execute software commands program block erase lock bit program and protect bit program increases as the number of program erase c
18. nversion Select Bit Page 276 of 656 bit name Clock Synchronous Bit in Figure 17 11 is modified as follows Clock Synchronization Bit Page 277 of 656 expression UIBRG count source in the function of bits DLO to DL2 in Figure 17 12 is corrected as follows baud rate generator count source Page 278 of 656 bit name of the RSTAREQ bit in Figure 17 13 is modified as follows Repeated START Condition Generate Bit Page 284 of 656 TXEPT flag in Figure 17 18 is corrected as follows TXEPT bit Page 284 of 656 description in the fourth dash of Figure 17 18 is corrected as follows The UiIRS bit in registers UiC1 and U34CON is 0 an interrupt request is generated when the transmit buffer is empty ePages 292 and 293 of 656 descriptions of function of the UiIRS bit in Figures 17 23 and 17 24 are corrected as follows 1 an interrupt request is generated when transmission is completed 0 an interrupt request is generated when the transmit buffer is empty Page 329 of 656 description of 18 1 5 is modified as follows In repeat sweep mode 1 the analog voltage applied to eight selected pins including one to four prioritized pins is repeatedly converted into a digital code Table 18 6 lists specifications of repeat sweep mode 1 Page 329 of 656 description in the specification of the function in Table 18 6 is modified as follows The analog voltage applied to eight sel
19. reaches 0000h stENESAS Page 4 of 12 RENESAS TECHNICAL UPDATE TN 16C A233A E Date Sep 24 2013 Page 219 of 656 Counting is deleted from bit names of bits TAOUD to TA4UD Timer A0 1 2 3 4 Increment Decrement Counting Select Bit and the register name Increment Decrement Counting Select Register in Figure 15 7 Page 221 of 656 descriptions b2 b3 b4 b5 and b6 b7 in Figure 15 9 are corrected as follows b3 b2 b5 b4 and b7 b6 Page 227 of 656 bit name of the MR2 bit in Figure 15 12 is modified as follows Increment Decrement Switching Source Select Bit Page 227 of 656 bit symbols TAITGH and TAiTGL in Note 5 of Figure 15 12 are corrected as follows TAJTGH and TAjTGL Page 228 of 656 pin name INT2 in Figures 15 13 and 15 14 is corrected as follows Page 232 of 656 bit symbol TAIS in Function of the MR2 bit in Figures 15 16 is corrected as follows TAIOS Page 247 of 656 description of 15 3 3 1 is corrected as follows While the timer counter is running the TBj register indicates a counter value at any given time j 0 to 5 However FFFFh is read while reloading is in progress When a value is set to the TBj register while the timer counter is stopped if the TBj register is read before the count starts the set value is read Page 247 of 656 expression TBj interrupt handler in the eighth bullet point of 15 3
20. ycles increases If the number of program erase cycles exceeds the endurance value specified in the electrical characteristics it may take an unpredictable amount of time to execute the software commands The wait time for executing software commands should be set much longer than the execution time specified in the electrical characteristics Page 587 of 656 description in the first bullet point of 27 6 8 is corrected as follows The minimum values of program erase cycles specified in the electrical characteristics are the maximum values that can guarantee the initial performance of the flash memory The program erase operation may still be performed even if the number of program erase cycles exceeds the guaranteed values ePages 604 and 605 of 656 Programming and erasure endurance of flash memory in Tables 29 8 and 29 9 is changed as follows Program erase cycles ePages 604 and 605 of 656 unit times in Tables 29 8 and 29 9 is corrected as follows Cycles ePages 611 and 622 of 656 expression Driver power in Tables 29 18 and 29 38 is modified as follows Drive strength Page 635 of 656 counting is deleted from the UDF register name Increment decrement counting select register in Table 30 1 Page 642 of 656 description of 30 6 3 1 is corrected as follows While the timer counter is running the TBj register indicates a counter value at any given time j 0 to 5 However FFFF
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