Application Note
Contents
1. 3 3v AD 31 0 A 24 2 z l ll l kl l 2 g u1 uz CS0 b CS0 b Tors ie SE Toes uz SE gfelefefefefefef x IPRATP cs 9E TPRW _ cs OE i515 Kio e o o o Tm 64 WE mno 64 WE REY 7 RviBY A2 ADO A2 AD16 A 2 ao Dao E T 2 ao _ Dao HRS x USA 21 EM GO 2A re Ar EJA wg A C2 s Ha ADS C2 s H4 D cso xm pos A3 m pos E RE D2 is K5 AE D2 is K5 Dz v19 cSt A r3 g DO ros D5 Fal 4 o gt 004 es D Yig ATA INTRO Csz AE E g pos He A t 2 005 S 122 css AU czas ma 006 He 07 AU 2349 q 006 He D V17 ATA IOCHDRY cs a SS bar A SS bar pasa OR Css wir A10 06 ot A10 D6 ot Fry ATA OW ATI cs 148 Alt cs 9 v16 ATA Di iP OE A ne 49 A Hs 49 184 ATA ISOLATION iP TS E6 A10 A Ee A10 LP ACK Fe Att ATA F6 Att IPAE D7 12 57 A12 RA LP_RIW Sr A13 Sr 13 D RzPCLGNT Er A14 Er A14 PCI RESET PCI CLOCK 15 45 ADO A18 A18 Bz ss pam ao LY ET BA are PCI AD u5 A17 A17 Y2 VI2 ADZ 0 D3 Z0 D3 pe PCLC BE 3 AD2 yz ADT Ge A18 Ge 18 zye PCLC BE 2 AD3 ADI E 7 1 A19 x J7 19 Owo PCLC BE 1 ADA Faas cP K A20 x k 20 o gi cH ul D5 Pur ADS AD2 M AZ Es A21 AZ E5 21 ws PCI FRAME AD6 yi ADT 00 N go A A22 A22 ve ECLTRDY DT Bi pa a ANZSLVOGSD ANZ9TV065D Y6 BEHIRDY pe HA 2 5 A0 PCL RD2. 104 591915 HEM S 7 5 124 41 81 5114 2907 Figure 6 Large Flash VVrite Access MPC5200 Local Plus Bus Interface Rev 3 19 Freescale Semiconductor Non Multiplexed Mode 3 7 5 Large Flash Short Burst Read Access q dt ped qma dt ped q eo dr ped q xoe dt ped q sa dr ped v qs ped dddd VVdc 91 16 se3eq4 8700010 8700010 SS IDDV x oo o rod ped RAPID UU UL I TUUM UU dT AE SONTdTeoot dnoz su 8Zt L9E LBS I 9E6 118 9881 su 92 162 1 89 2 081 2 Su 807710Z728S 1 1 0821 peeu Ising 4 yse 4 002504 O1NVS G ZHIN 104 591215 HEM S L p t I9d dl g TX Snid 2907 Figure 7 Large Flash Short Burst Read MPC5200 Local Plus Bus Interface Rev 3 Freescale Semiconductor 20 Multiplexed Mode 4 Multiplexed Mode Opposed to the previous mode the multiplexed mode implements the address and data lines multiplexed on the same physical pins using dual tenure or time multiplexing First the address is driven on the shared address data bus and LP ALE b is asserted Then the data is either vvritten or read during the assertion of chip select Table 12 Multiplexed Address Data Size Options Muxed Modes first address tenure follovved by the data tenure Memory Size
3. MPC5200 Local Plus Bus Interface Rev 3 32 Freescale Semiconductor BestComm Interface to the Local Plus Bus 5 7 Writing the Packet Size Register Now it is the proper time to write the SCLPC Packet size register MBAR 0x3C00 This register has 24 bits allocated to indicate the size in bytes of the complete transfer A single packet can then be as large as 65536 bytes It is important than the Packet Size and the PBT divide evenly if the PBT is set to 8 then only multiple of 8 bytes are allowed as Packet Size As long as the transaction is ongoing the next address can be read on the SCLPC NextAddress Status register MBAR 0x3C10 while the number of bytes transmitted are read from the SCLPC Bytes Done Status Register lower 24 bits Resetting the FIFO does NOT alter the Packet Size register 5 8 Writing the Restart Bit Kick Off Bit number 7 RESTART bit of the Packet Size register kicks off the transaction It is part of the Packet Size register to allow a new packet to be written and started at the same time but the two operations can be performed independently The RESTART bit always auto clear itself and reads back as zero As a complementary information to avoid stale data during READS due to the fact that a non zero Granularity would stop the BsstComm before emptying totally the FIFO a bit is provided FLUSH bit in the SCLPC Control register to ignore the granularity level when the last transaction of a packet is per
4. 002SOdiA OLNVS G ZHIN 66 124 S9 181S HEM 8 1 2 124 41 81 snid 12907 0 Dead Cycles 8 Wait States Figure 11 Write Access MPC5200 Local Plus Bus Interface Rev 3 29 Freescale Semiconductor Multiplexed Mode 4 6 3 Read Access 8 Wait States 2 Dead Cycles ST TYTOTST SU 986 296 02 COT STL 621 sn q Te dti ped qM dT ped q o dr ped q xoe di ped q sa dr ped v qso ped u 0 16180 xoo o rod ped ATO dt ATO ATX TdTeooT dnoz5 qvat 2 eoa yoy ou ly apo p xniy 0029041 OLNVS G ZHIN 104 591215 HEM ZZ L Z t IOd dl 81X snig 2907 Figure 12 Read Access 8 Wait States 2 Dead Cycles MPC5200 Local Plus Bus Interface Rev 3 Freescale Semiconductor 30 BestComm Interface to the Local Plus Bus 5 BestComm interface to the Local Plus Bus The MPC5200 processor has integrated a DMA engine called BestComm It allows to move data from different peripherals PSC PCI ATA LP I2C ETHERNET to and from the main memory SDRAM memory via FIFOs used as buffers Each internally supported peripheral has a specific set of registers to su
5. 0 TSIZE_1 TSIZE1 TSIZE1 TEST_SEL_1 TSIZE2 TSIZE2 PCI_CLK PCI CLK PCI CLK PCI CLK PCI CLK PCI CLK PCI CLK PCI PAR AO AO PCI C BE 0 A1 A1 PCI C BE 1 A2 A2 PCI C BE 2 A3 A3 PCI C BE 3 A4 A4 PCI_TRDY A5 A5 PCI_IRDY A6 A6 PCI_STOP A7 A7 PCI_DEVSEL A8 A8 PCI_FRAME A9 A9 PCI_SERR A10 A10 PCI_PERR A11 A11 PCI_IDSEL A12 A12 PCI_REQ A13 A13 PCI_GNT A14 A14 PCI RESET A15 A15 ATA DRQ A16 A16 ATA DACK A17 A17 ATA IOR A18 A18 ATA IOW A19 A19 ATA IOCHDRY A20 A20 ATA INTRQ A21 A21 ATA ISOLATION A22 A22 3 4 Special Dedicated Local Plus Signals 3 1 1 Transfer Acknowledge LP ACK b The use of LP ACK b for termination is software programmable The LP ACK b when input can only reduce the maximum programmed duration of the chip select transaction but never prolong it The same pin can be used as an output in the Most Graphics and Large Flash interface indicating the burst advance of a burst access MPC5200 Local Plus Bus Interface Rev 3 Freescale Semiconductor 9 Non Multiplexed Mode NOTE Acknovvledge active during boot The LP ACK bfunctionality is enabled during boot and therefore requires a pull up resistor to disable the acknovvledge input in case the peripheral from vvhich the boot code is fetched does not support the acknovvledge feature 3 1 2 Address Latch Enable LP ALE b This signal serves as the additional address line A23 when MOST Graphics mode is selected 3 1 3 Transfer Start LP TS b
6. 0x12 0 1 0 1 0x34 0 1 1 0 OxAB 0 1 1 1 OxCD 2 5 4 Write Transaction This example details a 32 bit write transaction As before the value 0x1234ABCD is used to demonstrate a 32 bit two 16 bit or four 8 bits write accesses of the MPC5200 to a peripheral Table 7 Single 32 bit access TSIZ1 TSIZ2 A1 AO AD 31 24 AD 23 16 AD 15 8 ADI7 01 0 0 0 0 0x12 0x34 OxAB OxCD Table 8 Two 16 bit access TSIZ1 TSIZ2 A1 AO AD 31 24 AD 23 16 AD 15 8 ADI7 01 1 0 0 0 0x12 0x34 1 0 1 0 OxAB OXCD OxAB OXCD MPC5200 Local Plus Bus Interface Rev 3 Freescale Semiconductor General Features of the Local Plus Bus Table 9 Four 8 bit access TSIZ1 TSIZ2 A1 A0 AD 31 24 AD 23 16 AD 15 8 ADI7 01 0 1 0 0 0x12 0 1 0 1 0x34 0x34 0 1 1 0 OxAB OxAB 0 1 1 1 OxCD 2 6 Boot Chip Select For booting the MPC5200 uses a special chip select called Chip Select Boot CSBOOT This signal is physically tied to the same ball as chip select 0 CS0 CSBOOT and CS0 also share the configuration register located at offset 0x0300 from the module base address MBAR The only difference between the two virtual chip selects CSBOOT and CS0 lies in the fact that CSBOOT is enabled after reset during boot and CS0 must first be enabled by software before it can be used as a CS line NOTE Code Execution Code can be executed
7. 0x34 OxAB OxCD Table 2 Two 16 bit access TSIZ1 TSIZ2 A1 AO AD 31 24 AD 23 16 AD 15 8 AD 7 0 1 0 0 0 0x12 0x34 1 0 1 0 OxAB OXCD Table 3 Four 8 bit access TSIZ1 TSIZ2 A1 A0 AD 31 24 AD 23 16 AD 15 8 ADI7 01 0 1 0 0 0x12 0 1 0 1 0x34 0 1 1 0 OxAB 0 1 1 1 OxCD 2 5 2 Reading from a 16 bit port If reading from a 16 bit port then either a 16 bit access or two 8 bit accesses are used To configure the port size the Configuration Register ofthe used chip select must be written Note that in a 16 bit chip select the valid data byte lanes are the upper two ones i e AD 31 24 MSB and AD 23 16 LSB Table 4 Single 16 bit access TSIZ1 TSIZ2 Ai AO AD 31 24 AD 23 16 AD 15 8 ADI7 01 1 0 0 0 0x12 0x34 1 0 1 0 OxAB OXCD MPC5200 Local Plus Bus Interface Rev 3 Freescale Semiconductor General Features of the Local Plus Bus Table 5 Two 8 bit access TSIZ1 TSIZ2 A1 AO AD 31 24 AD 23 16 AD 15 8 AD 7 0 0 1 0 0 0x12 0 1 0 1 0x34 0 1 1 0 OxAB 0 1 1 1 OxCD 2 5 3 Reading from a 8 bit port With data contents as before now the chip select is configured as a single byte located on AD 31 24 Therefore only four consecutive accesses are used It must be noted that this is transparent to the user Table 6 Four 8 bit access TSIZ1 TSIZ2 A1 AO AD 31 24 AD 23 16 AD 15 8 ADI7 0 0 1 0 0
8. 3 Dynamic Bus Size Read 14 Wait States 0 DC MPC5200 Local Plus Bus Interface Rev 3 Freescale Semiconductor 16 Non Multiplexed Mode 3 7 2 32 bit Write Access to an 16 bit Address and Data Port Wait States 14 Dead Cycles 0 This waveform shows a dynamic bus sizing accesses performed by the LPC Notice that there is no XLB related PCI clock penalties as the LPC collects the data necessary to complete the XLB data tenure however the XLB data tenure now consumes 2 LPC transactions to obtain the necessary data to complete its tenure 34 053 068 ns 3FF0026 Cursor2 RTL x 3FF0024 n S e co N e I H O n H 0 1 h 23 clk h 3FF002 pad lp ale b 16 pad csb 4 ack b xlb clk ipg pad pci clock 1 LocalPLUS pad lp rwb ddress Data 31 pad lp ts b pad lp oe b Local Plus XLB IP PCl 4 2 1 14 Wait States PCI 33 MHz pad lp D SANTO MPC5200 16 16 Not Muxed Mode Dynamic Access 32 bit WRITE Group A Figure 4 Dynamic Bus Size Write 14 Wait States 0 DC MPC5200 Local Plus Bus Interface Rev 3 Freescale Semiconductor 17 Non Multiplexed Mode 3 7 3 Large Flash Read Access q
9. Dead Cycles 0 Non muxed 32 bit XLB write transaction to 16 bit address and 16 bit data port resulting in dynamic Local Plus Controller accesses Wait States 4 Dead Cycles 0 Non muxed 16 bit read transaction to 26 bit address and 16 bit data port Wait States 5 Dead Cycles 0 Non muxed 16 bit write transaction to 26 bit address and 16 bit data port Wait States 5 Dead Cycles 0 Non muxed 16 bit short burst read transaction to 26 bit address and 16 bit data port Wait States 5 Dead Cycles 0 The simulations were run under the following conditions allowing for maximum performance on the Local Plus Bus Clock ratio as indicated in the figures E g clock ratio 4 2 1 133MHz 66MHz 33MHz No other XLB traffic is present so XLB arbitration is dedicated to Zeppo core read write access to from the Local Plus Controller No other Local Plus Bus traffic is present so the PCI arbiter remains parked on the Local Plus Controller These simulated conditions are characteristic of the conditions that would exist during boot operations where pipelined read read and read write XLB transactions are not pipelined 3 7 1 32 bit Read Access to an 16 bit Address and Data Port Wait State 14 Dead Cycle 0 Eqn 2 This transaction shovvs a back to back LPC read access The visible LPC transactions correspond to the first two XLB bus tenures The second XLB address data bus tenure is pipelined with respect to the first ad
10. Total Address Data TSIZE BANK per Bank Memory Size Boot Burst Size Size Bits Bits Bytes MBytes Option Support LegacyMuxed 8 25 8 3 2 33554432 128 no no LegacyMuxed 8 24 8 3 2 16777216 64 no no LegacyMuxed 8 16 8 3 2 65536 0 25 no no LegacyMuxed 8 8 8 3 2 256 0 000976563 no no LegacyMuxed 16 25 16 3 2 33554432 128 yes no LegacyMuxed 16 24 16 3 2 16777216 64 no no LegacyMuxed 16 16 16 3 2 65536 0 25 no no LegacyMuxed 16 8 16 3 2 256 0 000976563 no no LegacyMuxed 32 25 32 3 2 33554432 128 yes no LegacyMuxed 32 24 32 3 2 16777216 64 no no LegacyMuxed 32 16 32 3 2 65536 0 25 no no LegacyMuxed 32 8 32 3 2 256 0 000976563 no no This approach is slower in comparison to the not multiplexed mode as it multiplexes the bus functions in time At least two PCI clocks more than in the non multiplexed case are needed for each bus access However the multiplexed mode has the advantage of a bigger address space up to 128 MBytes divided in 4 Banks It also always needs external logic to latch the address in case this function is not provided by the peripheral The latch gate must be active low meaning the latch is transparent when its gating signal is kept asserted to a logic low value NOTE Address Latch Enable Attention must be paid to the fact that the LP ALE b signals deasserts at the same time as the CSx b will assert see MPC5200 Hardware Specification for more details about the Local Plus timing A board trace delay then might cause the LP AL
11. available at the same time On the same data bus several PCI devices 1f more than one external PCI device with bus master capabilities is intended to be used an external Priority Encoder for the single build in GNT REQ pair needs to be added an ATA device and up to eight generic memory mapped peripherals like Flash FPGAs SRAM E2PROM etc could coexist and each of these devices may need a different kind of transaction For example PCI uses dual tenure first the address then the data are driven on the bus while Flash might need address and data lines driven at the same time Another example is ATA which uses a 16 bit wide bus while external UART controllers usually come with an 8 bit wide bus Other time a specific peripheral implements a subset of a PowerPC 60x like interface using the LP TS b LP R W b and LP ACK signals for instance the EPSON SEIKO LCD controller SD13806 or they might need a separate Read and Write bar with also an Output Enable e g AMD Flash devices as AM29LV065 2 1 Nev Local Plus Bus Features of the MPC5200 Two new operating modes called Large Flash and Most Graphic have been implemented in the Local Plus interface They both can be used to BOOT MPC5200 using normal off the shelf ROM memory devices without the need for external glue logic The Large Flash interface supports up to 64 Mbytes it has 26 address lines A25 A0 and 16 bit data lines D16 D0 where the higher ordered number indicates always the
12. bit wide data bus configurations are supported Normally a slow device such as Flash ROM memory may need some waits states and therefore at the very boot it might be necessary to start the MPC5200 with the longest wait state default 48 PCI 727 ns at maximum allowed PCI speed of 66 MHz 4 3 Connecting an LCD Controller This example shows how a typical LCD controller the SD 13806 by Epson Seiko can be connected to the Local Plus Bus in the Muxed Mode This peripheral has 21 address lines and 16 separate data lines It also implements an E Bus like interface which makes use of the Transfer Size bits as the control registers are MPC5200 Local Plus Bus Interface Rev 3 Freescale Semiconductor 23 Multiplexed Mode 8 bit wide while graphic data is 16 bits the Transfer Start LP TS b Acknowledge LP ACK b and LP R VV b signals 3 3V zelo xen o 2505 fofofofofoftofo x Sees U2 cs Yi BUSCLK Vig ATA INTR
13. of 32 MBytes each In fact there are 25 address line AD 24 0 and two bank select lines AD 26 25 addressing words 32 bits 4 4 1 Write Access 1 Setup 1 Address Tenure e 2 Data Tenures CS asserted W number of waits states 0 to 127 4 pci xlb clock ratio 1 LPC processing 2 4 pci xlb clock ratio I For an internal clock ratio of the XLB IPBI PCI 4 2 1 a minimum of 6 pci clocks W per bus tenure is needed for back to back vvrites 4 4 2 Read Access 1 Setup 1 Address Tenure 2 data tenures CS asserted W number of waits states 0 to 127 programmable dead cycles 0 to 3 to allow peripheral time to 3 state bus after read 1 LPC Processing this may be masked by dead cycles if set to 1 or greater 1 Do not add this cycle if the transaction is a dynamic LPC bus tenure 2 Assumes the PCI Arbiter is parked on the LPC else this number is dependent upon Local Plus Bus traffic 3 Add these cycle s to the count if XLB pipelining is turned off MPC5200 Local Plus Bus Interface Rev 3 Freescale Semiconductor 25 Multiplexed Mode 4 pci xlb clock ratio 1 1 LPC processing 2 4 pci xlb clock ratio 3 For an internal clock ratio of the XLB IPBI PCI 4 2 1 a minimum of 7 pci clocks W D per bus tenure is needed for back to back reads The main difference between the non muxed and the muxed mode lies in the fact that an address tenure 1s needed The data tenure minimum
14. time is 2 PCI clocks 4 5 External Glue Logic In case of the muxed mode of the Local Plus Bus it is necessary to add external logic to generate control signals needed by a peripheral but not supplied by the Local Plus Bus As mentioned above an external logic is needed to latch or register the address during the address tenure NOTE LP OE b and Write Enable Not always a pair of signals like LP OE b and a Write Enable is needed Some device simply support a direct connection with the LP R W b Some peripherals might also take a particularly long time before releasing the bus after a read access is completed The Local Plus Bus has a maximum of three dead cycles at the end of a transaction which can be reduced for a READ only access to 0 via SW programming where the bus remains tri stated allowing such peripherals to detach from the bus without the risk of a bus contention 1 Do not add this cycle if the transaction is a dynamic LPC bus tenure 2 Assumes the PCI Arbiter is parked on the LPC else this number is dependent upon Local Plus Bus traffic 3 Add these cycle s to the count if XLB pipelining is turned off MPC5200 Local Plus Bus Interface Rev 3 26 Freescale Semiconductor Multiplexed Mode
15. 6 06 22 22 5 GIs x AMZSLVOSSD AMZSLVOGSD Figure 9 Multiplexed mode address latching Figure 9 shows how external logic can be used to interface a bank of four 8 bit Flashed devices using the Muxed Mode 4 6 Waveforms Snapshots The following pages contain snapshots of simulation waveforms for the following Local Plus port configurations Muxed 32 bit XLB read transaction to 32 bit address and 32 bit data port ALE 1 Wait States 8 Dead Cycles 0 Muxed 32 bit XLB write transaction to 32 bit address and 32 bit data port ALE 1 Wait States 8 Dead Cycles 0 Muxed 32 bit XLB read transaction to 32 bit address and 32 bit data port ALE 1 Wait States 8 Dead Cycles 2 The simulations were run under the following conditions allowing for maximum performance on the Local Plus Bus No other XLB traffic is present so XLB arbitration is dedicated to Zeppo core read write access to from the Local Plus Controller No other Local Plus Bus traffic is present so the PCI arbiter remains parked on the Local Plus Controller These simulated conditions are characteristic of the conditions that could exist during boot operations MPC5200 Local Plus Bus Interface Rev 3 Freescale Semiconductor 27 Multiplexed Mode Read Access 8 VVait States 0 Dead Cycles 4 6 1 q ete 4 ped qma dq ped q oo dT ped q yoe dti ped q sa dT ped v qs ped v Uu 10 16l1 av T
16. E b to deassert later than the CS falling edge thus causing Data to be latched instead of an Address To avoid this problem a register driven by the PCI CLK with LP ALE b gating the clock itself can be used Please refer to the latest Errata sheet of the MPC5200 regarding limitations of the LP ALE b signal implementation and its workarounds The following table shows the Local Plus bus signals available in the Muxed Mode MPC5200 Local Plus Bus Interface Rev 3 Freescale Semiconductor 21 Multiplexed Mode Table 13 LocalPlus Signals in Muxed Mode Muxed Modes first address tenure followed by the data tenure SignalName MSB LSB Local Plus Bus Signal Functionality Dedending On Mode Configured MPC5200 Signal Name LegacyMuxed 8 LegacyMuxed 16 LegacyMuxed 32 Address Phase Data Phase Address Phase Data Phase Address Phase Data Phase LP R W b Read Write Read Write Read Write Read Write Read Write Read Write LP ALE b Address Latch Enable Address Latch Enable Address Latch Enable Address Latch Enable Address Latch Enable Address Latch Enable LP ACK Transfer Acknowledge Transfer Acknowledge Transfer Acknowledge Transfer Acknowledge Transfer Acknowledge Transfer Acknowledge LP TS b Transfer Start Transfer Start Transfer Start Transfer Start Transfer Start Transfer Start LP OE b Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable CS 7 0 CS 7 0 CS 7 0 CS 7 0 LP AD 31 0 0 0 L
17. Freescale Semiconductor 7 Application Note Rev 3 04 2005 MPC5200 Local Plus Bus interface by Davide Santo and Oliver Bibel 1 Introduction Table of Contents Introduction essnee ax e RR sl iba p Oed qu 1 General Features of the Local Plus Bus 1 Non Multiplexed Mode 9 Multiplexed Mode 22 BestComm Interface to the Local Plus Bus 32 The Local Plus Bus is the external bus system of the MPC5200 processor which can be used in conjunction with Flash ROM SRAM and memory mapped peripherals sharing data bus pins with ATA and PCI devices This application note gives a brief explanation how to use this interface with memory mapped peripherals like Flash or SRAM This application note does not cover any workarounds required for potential bugs of the MPC5200 processor Please refer to the latest Errata list of the MPC5200 available from the Freescale web page O Q N 2 General Features of the Local Plus Bus The Local Plus Bus has a total of eight Independent chip selects 32 Address Data lines AD lines and nine control lines LP R VV b LP ALE b LP TS b LP ACK BANK SEL 1 0 and TSIZ 1 0 and LP OE b The same physical pins can be used for ey oe f I TM Freescale Semiconductor Inc 2005 All rights reserved reescaie semiconductor General Features of the Local Plus Bus different functions depending on the interface type and they might not all
18. Most Significant bit while the Most Graphic interface covers up to 16 Mbytes 24 Address by 32 Data bus width Both have TSIZ signals and LP OE b directly available The MPC5200 processor has been designed using the same package PBGA 272 pins as its predecessor Therefore the two newly introduced interfaces share now some pins with the PCI ATA interface preventing them from being simultaneously used at any moment during MPC5200 operations not only during BOOT The basic rule is that PCI is mutually exclusive with the Large Flash or Most Graphic but not with the legacy modes of the Local Plus while ATA can be used with all the legacy modes plus the Large Flash Interface but not with the MOST graphic one At power on the PCI controller is in a reset state to avoid possible contention on the Local Plus Bus thus preventing a correct boot process from happening The PCI controller is taken out of reset via a control bit bit 16 of the GPIO Port Configuration Register located at MBAR x0B00 ATA is a chip select controlled interface then it will not interfere during Boot It is important to recall that the MPC5200 ATA controller does NOT provide for a reset line to be connected to the SW RESET pin 1 of the standard 40 pin ATA connector this line must be implemented via a GPIO Two new Power On Reset Configuration Pins large flash sel connected to ball K02 and most graphic sel connected to ball K01 allow the user to select one o
19. O 18 ATA DACK BSB YT ATA IOCHDRY RDATE Xr ATA IOW MREG Y16 ATA D8 gt A ATA ISOLATION LP OE HRX IPTS Aja RD IP ACK Lig u3 WEO IPAE gt BY PELGNT LP RAN PS ed 1 1 PCI RESET PCI CLOCKq 4 cP M gt r Pcr DSEL apo Ae DO KM Q0 ao yz PCLREQ AD Las Di 3 a At cO ES AE 2 PALE PCI C BE 1 ADA z pa En A4 SY EGI C BE O aps HR 05 RM Q5 As 00 ws AD6 i D6 Q6 A6 eo ve PCICTRDY AD7 D7 Q7 A Y PCLSTOP v7 PCIIRDY US Xw PC LPAR YT PCLDEVSEL IE PCI PERR 4 cp WB aps H T DO is Qo A8 o 101 zE 550 g AD11 Lye D3 2 Q3 AM AD12 Lye 04 a4 A12 LLI AD13 Live D5 N Q5 A13 215 AD14 ja D6 Q6 A14 E i AD15 D7 a7 A15 ki x o Y CP wA M AD16 Lye Y DO N Qo A16 AD17 vg R Di C at A17 AD18 yz 4 p oz A18 019 Tyo D3 gt Q3 A19 o AD20 R 04 04 A20 1021 Ha 75 W3 Q AD23 D7 07 n AD24 Hus DO AD25 T D1 AD26 4 D2 AD27 Fy D3 AD28 r D4 AD29 FR D5 AD30 Hpi D6 AD31 D7 PC5200 s D9 D10 D11 D12 D13 D14 D15 STDT3806 Figure 8 LCD Controller in 16 Bit Local Plus Multiplexed Mode It is self evident that a legacy non multiplexed mode is not viable as there would be either not enough address line 16 data lines 16 address lines or not enough data lines 24 data lines 8 address lines In this case either an external logic is required to latch the address during the address tenure or the Large Flash in
20. P AD 30 TSIZEO TSIZEO TSIZEO LP AD 29 TSIZE1 TSIZE1 TSIZE1 LP AD 28 TSIZE2 TSIZE2 TSIZE2 LP AD 27 0 0 0 LP AD 26 Bank Select Bit 1 Bank Select Bit 1 Bank Select Bit 1 LP AD 25 Bank Select Bit 0 Bank Select Bit 0 Bank Select Bit 0 LP AD 24 A24 A24 A24 LP AD 23 A23 A23 A23 LP AD 22 A22 0 A22 A22 LP AD 21 A21 0 A21 A21 LP AD 20 A20 0 A20 A20 LP AD 19 A19 0 A19 A19 LP AD 18 0 A18 LP AD 17 0 A17 LP AD 16 0 A16 LP AD 15 0 A15 LP AD 14 0 A14 0 LP AD 13 0 A13 0 LP AD 12 0 A12 0 LP AD 11 0 0 LP AD 10 0 0 LP AD 9 0 0 LP AD 8 0 0 LP_AD 7 0 0 LP ADI61 0 0 LP ADI51 0 0 LP AD 4 0 0 LP AD 3 0 0 LP AD 2 0 0 LP AD 1 0 0 LP ADI01 0 0 PCI CLK PCI CLK PCI CLK PCI PCI CLK 4 1 Special Dedicated Local Plus signals NOTE Bursting Bursting is not available in any of the Muxed Modes 4 1 1 Transfer Acknowledge LP ACK b The use of LP ACK b for termination is software programmable The LP ACK b when input can only reduce the maximum programmed duration of the chip select transaction but never prolong it The same pin can be used as an output in the Most Graphics and Large Flash interface indicating the burst advance of a burst access MPC5200 Local Plus Bus Interface Rev 3 22 Freescale Semiconductor Multiplexed Mode NOTE Acknovvledge active during boot The LP ACK bfunctionality is enabled during boot and therefore requires a pull up resistor to disable the ackno
21. This pin can be used as an output in the Most Graphics mode burst mode only and Large Flash mode burst mode only indicating a valid start address for the next burst transfer 3 2 Configuration options 3 2 Wait States The numbers for read and write wait states can be set independently The wait states are counted in PCI clock cycles 3 2 2 Dead Cycles Dead cycles after a read access can be inserted up to three as chosen by the user via software to provide for proper peripheral hold time Some dead cycles might be hidden by arbitration In either case the data and control signals will be maintained one clock cycle beyond CSx negation to assure hold time 3 3 Booting At boot by default via the Hardware Reset Word the wait states inserted can be either 4 PCI clock cycles or 48 PCI clock cycles This value can be changed by software to anything from 0 to 127 or even more when a prescaler is used once the boot process has successfully started Normally a slow device such as Flash ROM memory may need some waits states and therefore at the very boot it might be necessary to start the MPC5200 with the longest wait state default 48 PCI Clocks 727 ns at the maximum allowed Local Plus speed of 66 MHz 3 4 How to connect a Flash device in a legacy mode This example assumes the use of a byte wide Flash device with an address space of 8 MBytes In this case the 24 address 8 bit data non multiplexed mode can be used The AD pins are sp
22. core in case of a Normal Termination of a packet NIE or an abnormal i e erred termination ATE If an interrupt will be received the core can read the SCLPC Bytes Status Register MBAR 0x3C14 to determine whether it was a normal or abnormal termination interrupt signalled 5 6 Writing the FIFO Watermarks The Fifo has two watermarks called Granularity and Alarm They can be set now to their desired value Granularity indicates the level of data in the FIFO at which BestComm will stop operating on it either filling or emptying it The Alarm is the level of data in the FIFO at which BestComm must resume operation and start moving data The Alarm level can be set to any value by writing the SCLPC LPC RX TX FIFO Alarm register MBAR 0x3C4C The Granularity can be set by writing to the SCPLC LPC RX TX FIFO Control register MBAR 0x3C48 Granularity is measured in 32 bit words and can be set from 0 to 7 It is important to remember that BestComm will wait before transmitting to have enough data in the FIFO to cover an entire transaction whose number of bytes is fixed by the PBT field in the control register Therefore the Alarm level shall be always be set greater than the PBT size to avoid stalling the DMA engine NOTE DMA request Line There is no DMA request line available it is thus NOT possible for an external device to directly initiate a BestComm transfer It is always the internal core which starts the task
23. d ped ATO Bdr YI qIX Sn aTeoor 4 012 x dad ST TOTST 444444 I 0 I I I I I I I I Su GqG8 vCL CG 007 26 008 S 68c 80 ZS ava 0 bp Oq yoy ou 1v poui p xniy 00zSOdW OLNVS G ZHIN 124 S WIS HEM 8 2 124 1 8 snid 2907 Figure 10 Read Access 8 Wait States 0 Dead Cycles MPC5200 Local Plus Bus Interface Rev 3 Freescale Semiconductor 28 Multiplexed Mode 4 6 2 Write Access 8 Wait States 0 Dead Cycles q eq dq ped qu 41 ped q eo dT ped q xoe dt ped q sa dr ped v qs ped y 4 10 16 av YTVTOYT ST T TST XOOT T d ped JT bdr XTO GTX 91141800 dnoz5 T 0 T T I I I I I I Su T 961 67 006 8v 008 87 S99 7SS 87 SU 16Z 961 6P zioszno SU G99YSS 8 T TIOSIND ALIYM 0 81949 v ou e1v p xniy
24. dress data bus tenure As a result XLB arbitration cycles do not impact the LPC as it goes from a write 1 Do not add this cycle if the transaction is a dynamic LPC bus tenure 2 Assumes the PCI arbiter is parked on the LPC else this number is dependent upon Local Plus Bus traffic 3 Add these cycle s to the count if XLB pipelining is turned off MPC5200 Local Plus Bus Interface Rev 3 Freescale Semiconductor 15 Non Multiplexed Mode to a read transaction There is a XLB clock cycle necessary for the XLB data bus tenure to complete and start the next tenure q eie 41 ped qma 41 ped q eo dT ped q xoe dT ped q S3 dT ped p qso ped 8212 Ek 9282 144 c Uu 191 1619822394 9200442 200246 0044 U Ssodppv T d ped l MT c c c4 CN O m m O rm en XIO qIX S yIdl 2oT dnou5 9 UES9 CE 000 2v v99 t6t TH 9 189 zy ZIOSINJ x SU 99 66 I4OSJnOD avat q z sseooy ottueu q 9poW p xniy ION 91391 002904 O1NVS G ZHIN 66 124 591215 HEM vL 1 2 7 124 4181 5 14 2907 Figure
25. e LSB of the address section of the Local Plus interface and D 0 is the LSB of the data byte lane MPC5200 Local Plus Bus Interface Rev 3 12 Freescale Semiconductor Cus Non Multiplexed Mode U1A aan W14 Y14 V15 ATA INTRQ CS2 W15 ATA DACK CS3 y45 ATA IOCHDRY C84 ag ATA IOR 55 n ATA IOW ATA DRQ bs ATA_ISOLATION LP OE Fyag LP ACK n LP ALE wig PCL_GNT LP RW PCI RESET vid elge Alo 10K R10 10K R11 10K 12 10K R13 10K 14 10K R15 10K R16 b Q I Q o e A PCI IDSEL AD1 12 PCI REQ AD2 742 PCI C BE 3 AD3 14 AD4 vel PCL FRAME AD w11 PCI PAR PCI C BE 0 we PCI C BE 1 Mwe PCI C BE 2 Q N Q co m o N lt lt 0 LL m a s AD16 AD17 v AD18 y AD19 AD20 AD21 v AD22 wa AD23 AD24 AD25 we AD26 y1 AD27 13 AD28 w AD29 783 AD30 AD31 IRQ 0 0 ET IRQ 1 Bz IRQ 2 IRQ 3 RI AM29BL802C MPC5200 Figure 2 Large Flash Mode 3 6 Timing To calculate how many clock cycles are involved in a Local Plus transaction the following data will be useful For detailed values like data and address set up and hold times please refer to the MPC5200 Hardware Specification and the MPC5200 User Manual MPC5200 Local Plus Bus Interface Rev 3 Freescale Semiconductor 13 Non Multiplexed Mode The number of clock eycles given be
26. e use On the Large Flash and Most graphic mode only TSIZ 1 2 have been pinned out The meaning of the TSIZ 1 2 is in any case the same for the muxed mode and the Large Flash or Most graphic modes 2 5 Transfer alignment To illustrate transfer alignments on the bus the follovving example assumes that the processor performs a transaction where a 32 bit word e g 0x1234A BCD is read in one 32 bit two 16 bit or four 8 bit accesses respectively MPC5200 Local Plus Bus Interface Rev 3 4 Freescale Semiconductor General Features of the Local Plus Bus 2 5 1 Reading From a 32 Bit Port When reading from a 32 bit port dynamic bus sizing allows the transfer to take place in a single word access in tvvo half vvord accesses or in four consecutive byte accesses The follovving tables shovv the position of the data byte lanes expected by the MPC5200 and the value of the TSIZ bits driven by the MPC5200 Please refer to Table 11 on page 9 or Table 13 on page 22 for the pins where the TSIZ signals vvill be available depending on the Local Plus mode selected Note that in the following tables AD 31 24 is the most significant byte lane while AD 7 0 is the least significant byte lane and that AQ is the least significant bit of the address Table 1 Single 32 bit access TSIZ1 TSIZ2 A1 AO AD 31 24 AD 23 16 AD 15 8 AD 7 0 0 0 0 0 0x12
27. ection 9 7 3 The following is the description of a typical sequence used to program the Local Plus Bus BestComm interface 5 1 Reset of the FIFO Before starting any BestComm access a reset of the FIFO and ofthe FIFO controller should be performed This is achieved by setting to 1 the RF and RC bits of the SCLPC Enable register MBAR 0x3CO0C As long as any of these bits are set high no external BestComm driven operation on the bus is possible Software must release these bits to allow start of operation see Clear of reset state later on 5 2 Write Start Address Register The starting address for the transaction must then be set in the SCLPC Start Address Register MBAR 0x3C04 This can be written even before the reset of the FIFO or FIFO controller without being affected by the latter The written address is the same one which will appear on the Local Plus Bus on the very first BestComm initiated transfer There are two possibilities then either the address will be automatically incremented in case a memory like device is accessed or can be fixed to the initial value in case a FIFO like device is accessed This can be set by the user by setting the DAI Disable Auto Increment bit of the SCLPC Control register MPC5200 Local Plus Bus Interface Rev 3 Freescale Semiconductor 31 BestComm Interface to the Local Plus Bus 5 3 Write Control Register The Control register MBAR 0x3C08 is then programmed to indica
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29. ete dr ped qma dT ped q eo dT ped q woe 4 ped q S3 di ped p qs ped 1221211000016 6 u 91 16 l e4eq 9910010 44 9910010 ssexppv T d ped HM HM ATO BdT SNTdTeoOT sdnoz SU EEE GIZ ZOL T 178067T61 1 su 96872617Z64 1 zaosun SU 6 291 26 peoy lbuls 4 use 4 96127 002SOdiN OLNVS G ZHIN 124 S WIS HEM S 124 41281 Snid 12907 Figure 5 Large Flash Read Access MPC5200 Local Plus Bus Interface Rev 3 Freescale Semiconductor 18 Non Multiplexed Mode 3 7 4 Large Flash Write Access q 41 ped quz dt ped q o dT ped q xoe dq ped q S4 dT ped qso ped n 001 00110000 u 91 16199390 010 446 96000101 461 10000246 Y SSe3ppv I XOOT tod ped XI Bdr S n IdTe2oT dnoz EE M M OIIII OIIIIIIIIIIKIIIIIIIIIIIIIIIIIIIIOIIIIIOIIOMI MI IOGIIXII IIEIIIR Su t G LvZ 66v 1 LZL 9887867 T su 80 LTZ 669 T zzosznO SU 9ST A481 667 1 TIOSIND 3 I 4981 9617 002904 1 1 9 4 ZHIN 66
30. f the 2 modes for booting Only one of the two new modes can be selected at the time if both POR Configuration pins are set to a logic 1 the LPC will not boot properly or as expected If none of them is selected then one of the legacy booting mode either not muxed or muxed is automatically used MPC5200 Local Plus Bus Interface Rev 3 2 Freescale Semiconductor General Features of the Local Plus Bus As a second new feature for the MPC5200 processor there is the support for today most common burst flash see as reference the Intel 28F160F3 or AMD29BL802C or ST Microelectronic M58BVV016 to reduce the total booting time Full Bursting is supported for Read only no write by the Local Plus controller on the Large Flash Most Graphic operating modes If the bursting controlled device supports Critical Double Word First CDVVF wrapping order then a complete cache line 32 Words can be read in at the time When this is not the case the Local Plus controller can downgrade an internal XLB request to a cache word size 64 bits per beat All of this happens dynamically in the LPC hardware if an 8 byte XLB fetch happens 1 e instruction fetch then a 64 bit Burst will occur at the peripheral If an XLB 32 byte cache line fetch happens then a cache Line burst will occur at the peripheral It is not possible to burst using an access less that the port size Bursting mode 64 bit versus CDWF mode must programmed via SW be
31. f up to 128 bit data width a Cache line is allowed and performed transparently to the user Dynamic Bus Access refers to any XLB transaction size that is different larger or shorter than the LPC data port size thus forcing the LPC to dynamically break the transactions down into multiple LPC bus tenures in order to assemble disassemble the XLB data transfer onto the LPC bus As an example an instruction fetch beat 64 bit long is supported by the Local Plus controller which translates it into the correct number of external access either 2 for the Most Graphic interface or 4 for the Large Flash The Local Plus controller supports XLB cache line bursting 32 byte long assuming that the memory device also supports the Critical Double Word First ordering scheme These modes of the Local Plus are software programmable please refer to the PowerPC user manual e g refer to MPC603e amp EC603e Risc Microprocessor User Manual and to the MPC5200 User Manual for further details During a Local Plus access using either the legacy multiplexed or the Large Flash or the Most Graphic mode Transfer Size bits and the address line AO LSB and A1 are put on the bus to reflect the specified transaction similar to the usual dynamic bus access of PowerPC family microprocessors Specifically in the Muxed Mode three Transfer Size bits TSIZ 0 2 are available on AD 30 28 during the address tenure where the most significant one TSIZ 0 is reserved for futur
32. fore first burst transaction can be performed Up to three dead cycles can be inserted in a read Not in a write access to better adapt to different peripheral s hold time requirements Dead cycles are at boot set to the maximum possible 3 and are programmed via SW The dead cycles when set to 0 or 1 can be hidden by arbitration cycles and do not add to them The Local Plus in the MPC5200 is also hooked to the internal DMA engine BestComm allowing data movement to be generated independently from CPU The interface has been implemented by using a single FIFO 512 bytes deep which means that the data movement can only happen in a single direction TX or RX at the time i e only Half Duplex communication is possible Last the Local Plus being shared among different controllers PCI ATA LPC is arbitrated by a dedicated arbiter which adds Bus Parking as new feature in the MPC5200 Bus Parking is not available for an external Master such as an external PCI Initiator device The Local Plus Bus interface being so flexible can be adjusted to meet all its different operating modes by means of software configuration and in some cases minimal external logic in the multiplexed mode precisely NOTE Multiplexed versus Non Multiplexed Mode The most important concept to understand are the Local Plus two main modes of operation multiplexed mode and non multiplexed mode Bursting can happen ONLY in a non multiplexed mode
33. formed FIFO status registers are available to gain information about the FIFO state Overflow underrun etc in case of errors and during debug phase MPC5200 Local Plus Bus Interface Rev 3 Freescale Semiconductor 33 How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com AN2458 Rev 3 04 2005 Informati
34. from any chip select CSBOOT CSO through CS7 Also the two virtual chip select have different mapping registers CS0 start and stop virtual address values are mapped at MBAR 0x04 and MBAR 0x08 while CSBOOT is mapped at MBAR 0x4C and MBAR 0x50 It is essential to avoid to have both of them enabled using the enabling control register at MBAR 0x54 at the same time 2 7 Local Plus Performance The Local Plus interface has been originally designed to be an easy to use interface not specifically focused on high speed performance For this reason arbitration of the bus there can be different masters on the Local Plus as the processor core an external PCI master and different targets could be accessed such as ATA PCI or an external memory mapped device may be performed at every new access This of course adds some overhead time which should be taken into consideration when trying to evaluate the speed characteristics and performances of this interface As already mentioned Bus Parking is available but only for internal Masters LP controller PCI controller and ATA controller This feature improves performances allowing a Master to have immediate access to the bus without having to re arbitrate as long as no other requests are pending NOTE Local Plus Bus Reference Clock MPC5200 is using the PCI clock as the internal reference clock As a result all clock counts are with respect to the PCI clock All transitions are sy
35. lit in two groups the following way AD 23 0 are used as address lines A 23 0 and AD 31 24 are used as data lines D 7 0 MPC5200 Local Plus Bus Interface Rev 3 10 Freescale Semiconductor Non Multiplexed Mode With this convention the Address and the Data bus can be directly connected to the device In fact A0 is the least significant bit of the address section of the Local Plus interface while D 0 connected to AD 24 on the processor is the least significant bit of the data byte lane ATA INTRQ ATA DACK ATA IOCHDRY ATA ATA ISOLATION PCI GNT PCI RESET ap PCI CLOCK PCI IDSEL PCI REQ PCI C BE PCI C BE PCI C BE PCI D S o CN lt a 0 ae o q eo MPC5200 Figure 1 Legacy Non Multiplexed Mode MPC5200 Local Plus Bus Interface Rev 3 Freescale Semiconductor 11 Non Multiplexed Mode 3 5 How to connect a Flash device in the Large Flash Mode This example assumes the use ofa synchronous 16 Bit wide Flash device with an address space of 1 MByte that supports burst reads Figure 2 shows how the Local Plus pins have to be connected to the flash device It should be noted that also some PCI signals are used to extend the address range of the Local Plus Bus during Local Plus transfers A maximum of 26 address lines A 25 0 is available in the Large Flash mode In this example only A 19 1 are required to cover the whole address range of the flash device connected A 0 is th
36. ller than the physical connection to the peripheral In such case a direct connection from A 1 0 processor to A 1 0 device is possible or necessary MPC5200 Local Plus Bus Interface Rev 3 8 Freescale Semiconductor Non Multiplexed Mode The Non Multiplexed Mode is able to interface gluelessly vvith memory mapped external devices like Flash ROM E2PROM or SRAM It is also faster than the multiplexed mode as it provides both data and address in a single tenure The following table shows the Local Plus bus signals of the most important Non muxed Modes Table 11 Local Plus Signals of the most important Non muxed Modes Non Muxed Modes address and data at the same time SignalName MSB LSB Local Plus Bus Signal Functionality Dedending On Mode Configured MOST Graphics MPC5200 Signal Name LegacyNonMuxed8 LegacyNonMuxed16 Large Flash16 Burst Enabled 32 32 LP R W b Read Write Read Write Read Write Read Write Read Write Read Write LP ALE b A23 A23 LP ACK b Transfer Acknowledge Transfer Acknowledge Transfer Acknowledge Burst Advance Transfer Burst Advance Acknowledge LP TS b Transfer Start Start Address for Transfer Start Start Address for Burst Burst LP OE b Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable CS 7 0 CS 7 0 CS 7 0 517 0 CS 7 0 LP AD 31 24 D 31 24 D 31 24 LP AD 23 16 D 23 16 D 23 16 LP AD 15 8 D 15 8 D 15 8 LP ADI7 0 E D 7 0 D 7
37. lovv vvill be per data beat vvhich is based on the port size it could be 8 bit or 16 bit or 32 bit The reference clock is the PCI clock These numbers provide the best case timing where it is assumed that the PCI arbiter is parked on the Local Plus controller there is no other traffic on the internal Bus XLB and pipelining of the XLB is enabled The XLB for future reference is the processor core s bus PPC 60X Local Bus Again the Wait states must be computed in terms of PCI clock cycles XLB pipeline can be turned on off via SW control the control register belongs to the XLB Arbiter register group Pipelining refers to the possibility to start internally on the XLB bus a second address tenure while the data tenure corresponding to the previous address has not yet terminated either with a TA or a TEA It might increases performances depending on the application With Dynamic Bus Sizing is important to remember that when a wider piece of data is decomposed in smaller chunks to adapt to the peripheral size no additional overhead is added Nonetheless any time a new data 32 or 64 bit long is to be read written from the core a turnaround overhead clock is needed This is calculated by the formula Overhead Clock 4 x PCI XLB clock ratio Eqn 1 Last is to note that while a normal PowerPC data or instruction can be maximum be 32 bit wide an instruction fetch has always a size of 64 bit to make full usage of the internal instructio
38. n pipeline Write Access 3 6 1 Write Access 1 Setup e 1 CS assertion W number of waits states 0 to 127 e 4 pci xlb clock ratio 1 2 1 LPC processing 2 4 pci xlb clock ratio For an internal clock ratio of the XLB IPBI PCI 4 2 1 a minimum of 4 pci clocks W per bus tenure is needed for back to back writes 3 6 2 Read Access non burst 1 Setup e 1 CS assertion W number of waits states 0 to 127 e programmable dead cycles 0 to 3 to allow peripheral time to 3 state bus after read 1 LPC processing this may be masked by dead cycles if set to 1 or greater 1 Do not add this cycle if the transaction is a dynamic LPC bus tenure 2 Assumes the PCI arbiter is parked on the LPC else this number is dependent upon Local Plus Bus traffic 3 Add these cycle s to the count if XLB pipelining is turned off MPC5200 Local Plus Bus Interface Rev 3 14 Freescale Semiconductor Non Multiplexed Mode 4 pci xlb clock ratio 1 1 LPC processing 2 4 pci xlb clock ratio 3 For an internal clock ratio of the XLB IPBE PCI 4 2 1 a minimum of 5 PCI clocks W D per bus tenure is needed for back to back reads 3 7 Waveform Snapshots The following pages contain snapshots of simulation waveforms for the following Local Plus port configurations Non muxed 32 bit XLB read transaction to 16 bit address and 16 bit data port resulting in dynamic Local Plus Controller accesses Wait States 14
39. nchronized to the rising edge of the PCI clock The Local Plus has a BestComm hook Therefore Local Plus can directly transfer in a DMA fashion data from the target to BestComm s FIFOs thus increasing performance The BestComm interface is a Half Duplex only designed on a 512 deep FIFO Alarm and granularity level can be set via SW and any CS can MPC5200 Local Plus Bus Interface Rev 3 Freescale Semiconductor 7 Non Multiplexed Mode be supported by the internal DMA engine See lt st blue gt Chapter 5 lt st blue gt lt st italic gt BestComm Interface to the Local Plus Bus for more details XLB bus processing and arbitration cycles are removed from the Local Plus Controller transaction timing clock counts when the BestComm interface is used 3 Non Multiplexed Mode In non multiplexed mode the 32 physical AD pins of the MPC5200 are divided into two separate non multiplexed groups precisely the address and data partitions This allows data and address to be driven at the same time on separate pins Eight different configurations of address and data lines are supported Table 10 Non Multiplexed Address Data Size Options Non Muxed Modes address and data at the same time Total Address Data TSIZE BANK Memory Size Memory Size Boot Burst ATA PCI Mode Name Size Size Bits Bits Bytes MBytes Option Support Support Support LegacyNonMuxed 8 24 8 16777216 16 yes no yes yes LegacyNonMuxed 8 16 8 65536 0 0625 no no yes yes LegacyN
40. of the Local Plus 2 2 How to connect a peripheral to the Local Plus Bus MPC5200 supports the PCI bus naming convention on the Local Plus Bus This means that the byte ordering of the external pins conforms to the little endianess rule typical for PCI Having a PowerPC core inside the MPC5200 s internal registers the internal memory and peripherals bus XLB and IPBI bus adhere instead to the big endian ordering rule Please refer to the MPC5200 User Manual for more details about the XLBus and the IPBI The swap is automatically done in the Local Plus module and it is completely transparent to the user MPC5200 Local Plus Bus Interface Rev 3 Freescale Semiconductor 3 General Features of the Local Plus Bus 2 3 MSBs and LSBs To connect an external device to the Local Plus Bus a couple of simple rules can be used regardless of the mode the bus vvill use to control the device itself A lower bit number in the pin name indicates lower importance of the line in terms of the bit ordering 0 is always the least significant bit MPC5200 s Local Plus Bus pins are called AD 31 0 where bit 31 is the most significant bit and bit 0 is the least significant bit PCI mode All 32 bits AD 31 0 are used ATA mode Data is connected to AD 15 0 and address to AD 18 16 2 4 Dynamic Bus Access The Transfer Size Bits The Local Plus bus allows dynamic bus sizing in the terms that on any chip select a transaction o
41. on in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Fr
42. onMuxed 8 8 8 256 0 000244141 no no yes yes LegacyNonMuxed 16 16 16 65536 0 0625 yes no yes yes LegacyNonMuxed 16 8 16 256 0 000244141 no no yes yes Large Flash 16 26 16 67108864 64 yes yes yes no Large Flash8 26 8 67108864 64 yes yes yes no MOST Graphics 32 24 32 2 16777216 16 yes yes no no For example a possible booting configuration uses 24 address and 8 data lines and is thus able to address 27 data bytes or a total of 16 Mbytes A second configuration uses 16 address and 16 data lines Here 215 address lines point at a half word each for at a total of 64 kBytes NOTE Byte Addressing is used in all modes 16 Bit wide data connection to the peripheral Any two short addresses 16 bit data are separated by an 0x02 address offset which clearly indicates that AO lines is never asserted or used thus it shall not be connected to the device The pin A 0 of the controlled device is usually connected to A 1 of the processor 32 Bit wide data connection to the peripheral Any two vvord addresses 32 bit data are separated by an 0x04 address offset which clearly indicates that A 1 0 lines are never asserted or used thus they shall not be connected to the device The pins A 1 0 ofthe controlled device are usually connected to A 3 2 of the processor The TSIZ 1 2 pins can sometimes be used in conjunction with A 1 0 to select which byte or short is actually used during the transfer and allow transfers sma
43. pport the DMA process in addition to those needed by the DMA engine to operate to read about the BestComm Programmer Model please refer to the User Manual section 11 The Local Plus interface is supported by the DMA engine via a specific interface called in the User Manual SCLPC using a single 512 byte deep FIFO This allows the user to implement data transfer either from memory to the Local Plus Bus or from the Local Plus Bus in an half duplex fashion For sake of completeness the PCI interface is also supported by BestComm but with 2 FIFOs one for RX and one for TX thus enabling a full duplex transfer while the ATA interface has an half duplex interface to BestComm Each peripheral has his own FIFO with associated FIFO controller allowing all three modules PCI ATA and LP to be used at the same time The same internal arbiter called PCI arbiter which arbitrates the PCI Local Plus and ATA core originated access manages the BestComm initiated request for either PCI Local plus and ATA How to write a BestComm s task supporting the Local Plus is not treated in this application note The focus will be more on the steps needed to prepare the Local Plus controller to use the BestComm assuming a proper task capable of moving data to from the LP bus is available and that the user knows how to enable a task see User Manual Section 11 The complete description for the SCLPC register can be found in the User Manual at s
44. te which chip select 0 through 7 will be used by the BestComm and how many bytes will be moved per transaction PBT field The bus port mode Muxed Mode versus not muxed data address width ale ack number of wait states etc of the bus are still set using the usual control and configuration registers as for the not BestComm initiated accesses The BPT field can be set from 0 to 7 where 0 means 8 bytes per transaction 1 then meaning 1 byte and so on In general the BPT field can be larger than the bus port s size example 8 bytes on a 16 bit data port except in the case where the DAI bit is set 1 e when writing to an external FIFO the BPT must be of the same size as the FIFO s port The BPT can never be less than the bus port s size The control register RWb field indicates if a WRITE to the Local Plus or a READ from the Local Plus will be executed Also the Control register is unaffected by a RESET of the FIFO 5 4 Clear the FIFO Reset State It is possible if not done before to clear write to 0 the RF and CF bits in the SCLPC enable register allowing the FIFO to exit the reset state 5 5 Write the Interrupt and Master Enable bits There is a Master enable bit and two interrupt enabling bits in the SCLPC Enable register MBAR 0x3CO0C The Master bit must be set to 1 to permit any operation and before the first packet is kicked off The two interrupts bits enable the SCLPC interface to send an interrupt to the
45. terface could be used which then would not allow the usage of PCI on the same design The external registers will also store the TSIZ bits on AD 28 the least significant TSIZ bit and on AD 29 the most significant TSIZ bit for the legacy mode For the Large Flash and Most Graphics interfaces these bits are directly available from two separated pins MPC5200 Local Plus Bus Interface Rev 3 24 Freescale Semiconductor Multiplexed Mode To connect the device properly the latched address lines A 20 0 must directly be connected to the A 20 0 pins of the slave device while for the data part the lines AD 31 16 will be connected to the pins named D 15 0 on the LCD controller AD 16 again being the least significant bit 4 4 Timing Please refer to the Hardware Specification of the MPC5200 for detailed timing values of the Local Plus interface This chapter shows how to calculate the number of clock cycles one access in the muxed mode would take Note that during data tenure the decision between data being driven or the AD bit being tri stated is dependent on whether the transaction is a Read or a Write and what the programmed data size is Unused bits in the data tenure i e those in excess of the programmed data size will be driven to zero by the Local Plus Bus controller as a precaution to avoid floating bus condition The maximum address space per each single chip select in multiplexed mode is 128 MBytes divided into four banks
46. vvledge input in case the peripheral from vvhich the boot code is fetched does not support the acknovvledge feature 4 1 2 Address Latch Enable LP ALE b This signal serves as the a control signal for an external address latch in all muxed modes Please note that there is no hold time left between the release of the LP ALE b signal an the assertion of the CS signal This might impact some peripherals and must be carefully taken into consideration when designing an external address register 4 1 3 Transfer Start LP TS b This signal is driven low during the first LP clock the Local Plus bus is based on the PCI clock when CS has been asserted to indicate the data phase of the transfer 4 1 4 Transfer Size TSIZ 0 2 The multiplexed mode also provides the three Transfer Size bits TSIZ 0 2 They are available on AD 30 28 during the address phase of a transfer and are used to signal the size of the current transfer NOTE TSIZ Naming Convention AD 30 represents TSIZ 0 and it is reserved for future use This bit 1s driven to 0 when a 8 bit or 16 bit transaction is performed and to 1 ifa 32 bit transaction is executed AD 29 represents TSIZ 1 and AD 28 represents TSIZ 2 during the address phase In the Multiplexed Mode the data bus width can be either 8 16 or 32 The boot modes are limited to 16 or 32 bit data width 4 2 Booting At boot 8 bit wide multiplexed mode configuration is not supported Only 16 bit or 32
47. y Vio ADS ADE i A6 us uz wr 1 ADS Y10 4010 04 04 T CS0 b H CS0 b Y7 TEL DEVSEE AD10 yg ADTI D5 N Q5 AF IPOEP J2 5E TPOEb J2 SE Ws FCI PERR ADIT YS T ADS D6 Q6 PRW b cs OE IP RW T cs SE PRANS ADI2 Vs ADTS er ar ca WE TRE cg WE AD13 WS ADIT nvr8Y 58 siz ADI ua ADT ua A2 G2 G3 AD8 A2 G2 Ga 2 AD15 F A0 Dao ADU K F2 A0 000 w4 AD16 TE E2 lt 001 feg DT AT E DQ dq AD16 cP A2 O 002 D 2 iD 002 Ys C2 SG H4 TT C2 OB H4 xe 1 DiS AD10 A10 D2 3 iL e or D AE 6248 ESS Ed AD18 DS D DO N ao 7 A4 gt Da 7 A4 vas 74 TT T F3 o G5 D F3 G5 AD19 D a A5 S 3 pos AB pos V2 ADU ADT AT E E LO J6 4014 E E3 LO J amp AD2U Ve 4021 Dis n g TT S c3 26 qaq 006 ke D gl GJ qaq 006 ke D AD21 027 ADU D3 ii AT 007 007 AD22 Hye pa d as zz EE WS 2025 Dis 2 T5 A10 06 4 A10 06 4 AD23 KOTE 05 N Q5 ATE ce A8 A Cg 8 u3 AD24 DIT D6 w ud T H6 9 H6 AD24 Fw 02 07 ar TT E6 A10 EG 10 AD25 AD26 Aid F6 Att Aid F6 11 AD26 Yi D27 ug A 57 A12 D7 A12 AD27 rs DI 5 Sr A13 er AD28 Twi AD29 E E7 A14 ET A14 AD29 3 E CP A15 A15 VT AD3T AD18 A18 A18 ET A18 E7 AD31 ADTT Do M ao T GP A16 Gr 16 ADZU Di M at TOU ZU D3 A17 XU Da A17 P3 1800 DZT 2 9o AZT T Ge 1518 AZ Ge 18 RO 0 127 2 a3 77 j7 19 v SH Ate IPCS200 AD23 DS sp Gt A23 223 xa 1420 A23 Ka 220 ADU 05 KR 05 T XOT Es A21 Es 221 122 0
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