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ModelSim SE Tutorial - Electrical and Computer Engineering

1. 2a 20 3a Figure 20 The structure tab for the counter design unit Workspace HAX Transcript HA Loading project test E EHI test counte FRERE Compile of tcounter v was successful psi coume pa COTS CU Compile of counter v was successful M dut Counter Module 2 compiles failed with no errors ModelSim gt vsim work test counter 3 vsim work test counter Loading work test counter BIMPLICITAWIRE res test counter Process HIMPLJCIT WIRE clk test counter Process INITIAL T lest counter Process Loading work counter HINITIALHI7 test_counter Process HINITIANHZS test_counter Process VSIM 3 4a J Teea Organizing projects with folders If you have a lot of files to add to a project you may want to organize them in folders You can create folders either before or after adding your files If you create a folder before adding files you can specify in which folder you want a file placed at the time you add the file see Folder field in Figure 16 If you create a folder after adding files you edit the file properties to move it to that folder Adding folders As shown previously in Figure 15 the Add items to the Project dialog has an option for adding folders If you have already closed that dialog you can use a menu command to add a folder 1 Add a new folder Select File gt Add to Project gt Folder b Type Design Files in the Fo
2. ler 2004 06 Jun 420 Save List Compiling module Compiling module POS Coverage P End Simulation l 2 3 4 Rightmodule test counter 5 6 Top level modules reg clk reset Figure 9 Waves being drawn in the Wave window wave default File Edit View Insert Format Tools Window 4 test_counter clk 4 jest counter reset test_counter count e m RR FRSC RE RD D D D RU E LA fA Lf A A A tn O Li hi hs Cursor 1 D ns to 630 ns Now 600 ns Delta 2 ModelSim SE Tutorial T 26 Lesson 2 Basic simulation c Click the Run All icon on the Main or Wave window toolbar The simulation continues running until you execute a break command or it hits a statement in your code e g a Verilog stop statement that halts the simulation d Click the Break icon The simulation stops running ModelSim SE Tutorial Setting breakpoints and stepping in the Source window Next you will take a brief look at one interactive debugging feature of the ModelSim environment You will set a breakpoint in the Source window run the simulation and then step through the design under test Breakpoints can be set only on lines with red line numbers 1 Open counter v in the Source window a Select the Files tab in the Main window Workspace b Double click counter v to add it to the Source window Set a breakpoint on line 31 of counter v if you are simulating the VHDL files use line 30 inste
3. Now IKI Mow S00ns Delta 2 Ons to 1008 ns Lesson 6 Viewing simulations in the Wave window Topics The following topics are covered in this lesson Introduction Related reading Loading a design Adding objects to the Wave window Using cursors in the Wave window Working with a single cursor Working with multiple cursors Saving the window format Lesson wrap up T 66 T 66 T 67 T 68 T 70 T 70 T 71 T 73 T 74 T 65 ModelSim SE Tutorial T 66 Lesson 6 Viewing simulations in the Wave window Introduction The Wave window allows you to view the results of your simulation as HDL waveforms and their values The Wave window is divided into a number of window panes Figure 47 All window panes in the Wave window can be resized by clicking and dragging the bar between any two panes Related reading ModelSim GUI Reference Wave window GR 211 ModelSim User s Manual Chapter 8 WLF files datasets and virtuals UM 225 ModelSim SE Tutorial pathname Ted wave default File Edit iew Insert Format Tools value Window Figure 47 The Wave window and its many panes waveform zem xj smag me A h XIe I8 m ae A D test_ringbuf ring_INST block test_ringbuf ring_INST bloc test_ringbuf ring_INST bloc Ztest ringbuf ring
4. View file is selected by default when you select Write to file Leave it selected Click OK The calltree rpt report file will open automatically in Notepad Figure 108 You can also output this report from the command line using the profile report command See the ModelSim Command Reference for details ModelSim SE Tutorial Figure 105 The Profiler toolbar F Unex 23600 e 1a 1b 2a Figure 106 The filtered profile data Page __ Ueer intan Une rix ras EF sm B7 Tcl Flush L Tcl Close Tcl DoOneEvent test sm v 86 Call Tree Structural Figure 107 The Profile Report dialog x Profile Report x r Type Performance Memory data Call Tree 2b C Ranked 2c Default data collected C Structural C Performance only Root opt E C Memory only Include function call hierarchy Performance and memory Specify structure level 1 E Cutoff percent Function to instance 2d Function C Default 0 Instances using same definition Specify 2 Instance Dutput C write to transcript white to file calltres rpt Browse M View file 2e DK Cancel Lesson wrap up T 121 Le sson wrap u p Figure 108 The calltree rpt report This concludes this lesson Before continuing we need to end the current File Edt Window simulation calltree rpt A Model Technology ModelSim SE PLUS vsim 6 0 Bet
5. Design Unit Name KE SAN S S Job a S OS Ww om es File Name m Browse Overwrite Existing Files OK Cancel Running the simulation Once you have finished editing the waveforms you can run the simulation straight away 1 Add a design signal a Inthe Objects pane right click count and select Add to Wave gt Selected Signals The signal is added to the Wave window 2 Run the simulation a Click the Run All icon The simulation runs for 1000 ns and the waveform is drawn for sim counter count Figure 65 Look at the signal transitions for count from 300 ns to 500 ns The transitions occur when clk goes high and you can see that count follows the pattern you created when you edited clk by deleting an edge 3 Quit the simulation a Inthe Main window select Simulate gt End Simulation and click Yes to confirm you want to quit simulating Running the simulation T 85 Figure 65 The counter waveform reacts to the created stimulus pattern wave default File Edit View Insert Format Tools Window 4 Edit counter clk 4 Edit counter reset E 4 sim counter count Now 1000 ns Cursor 1 l0 x ModelSim SE Tutorial T 86 Lesson 7 Creating stimulus with Waveform Editor Si mu lati ng with the testbench fi le Figure 66 The testbench design unit compiled into the work library Earlier in the lesson you exported the created waveforms to a testbench file In this TOR
6. Extended mode enabled Keep 1 top p ASSIGNH 9 x ModelSim SE Tutorial Tracing an X unknown The Dataflow window lets you easily track an unknown value X as it propagates through the design The Dataflow window is linked to the stand alone Wave window so you can view signals in the Wave window and then use the Dataflow window to track the source of a problem As you traverse your design in the Dataflow window appropriate signals are added automatically to the Wave window 1 View t out in the Wave and Dataflow windows a Scroll in the Wave window until you can see top p t out t out goes to an unknown state at 2065 ns and continues transitioning between 1 and unknown for the rest of the run Figure 74 The red color of the waveform indicates an unknown value b Double click the last transition of signal t out at 2785 ns This automatically opens the Dataflow window and displays t out its associated process and its waveform You may need to increase the size of the Dataflow window and scroll the panes to see everything c Move the cursor in the Wave window As previously mentioned the Wave and Dataflow windows are designed to work together As you move the cursor in the Wave the value of t out changes in the Dataflow window d Move the cursor to a time when f out is unknown e g 2724 ns 2 Tracethe unknown a Inthe Dataflow window make sure f out is selected and then select Trace ChaseX
7. Index A aCC T 53 add dataflow command T 96 add wave command T 68 Assertions add to dataflow T 142 debugging failures T 141 ignore assertions during simulation T 138 nopsl argument to vsim T 138 speeding debugging T 139 using assertions for debugging T 135 B break icon T 26 breakpoints in SystemC modules T 61 setting T 27 stepping T 28 C C Debug T 61 Code Coverage excluding lines and files T 132 reports T 133 Source window T 129 command line mode T 163 comparisons Waveform Compare T 147 compile order changing T 35 compiling your design T 13 T 23 cover argument T 125 coverage argument T 126 coverage report command T 133 cursors Wave window T 70 T 85 D Dataflow window T 89 displaying hierarchy T 96 expanding to drivers readers T 92 options T 96 tracing events T 93 tracing unknowns T 95 dataset close command T 157 design library working type T 16 DO files T 159 documentation T 7 drivers expanding to T 92 E error messages more information T 46 external libraries linking to T 46 F folders in projects T 37 format saving for Wave window T 73 G gcc T 53 ModelSim SE Tutorial T 176 Index H hierarchy displaying in Dataflow window T 96 L libraries design library types T 16 linking to external libraries T 46 mapping to permanently T 49 resource libraries T 16 working libraries T 16 working creating T 21 linking to external libraries T 46 M macros T 15
8. Module Module Module HS c clock ScModule C Modeltech_6 0 Module C MTI examples ScModule C MTI examples Library MODEL_TECH Library MODEL_TECH I modelsim lib Library MODEL TECH mM std Libarv MODEL TECH test_ringbuf ScModule m delta 184467440737 clock sc clock ScModule m_cur_val true M ring INST ringbuf Module m negedge lime reset generator test ringbuf ScMethod m posedge time r generate dala test ringbuf ScMethod m start time compare data test ringbuf ScMethod m duty cycle p nt eror test ringbuf ScMethod m period print restore test_ringbuf ScMethod Active Processes Ready IMPLICIT WIRE outstrobe 28 Ready IMPLICIT WIRE oeenable 27 Ready IMPLICIT WIRE ramadrs 26 7 Ready HASSIGNHES test ringbuf ring Ready SIMPLICIT wIRE buffer H23 te Readu HASSIGNI3S test rinabuf rina ModelSim SE Tutorial T 62 Lesson 5 Simulating designs with SystemC b Click the Step icon on the Source window toolbar m This steps the simulation to the next statement Because the next statement is a function call ModelSim steps into the function which is in a separate file Figure 44 c Click the Continue Run icon on the Source window toolbar Hii The breakpoint in fest ringbuf h is hit again Examining SystemC objects and variables To examine the value of a SystemC object or variable you can us
9. b Save the file as basic h Now you have made all the edits that are required for preparing the design for compilation Preparing an OSCI SystemC design Figure 36 Basic example excerpts before and after modifications T 55 ModelSim SE Tutorial T 56 Lesson 5 Simulating designs with SystemC Compiling a SystemC only design Now you are ready to compile the design whose sources you have just edited With designs that contain SystemC objects you compile SystemC files using the sccom compiler and HDL files using vlog or vcom Our first example design basic contains only SystemC code Thus you only need to run the SystemC compiler sccom CR 254 to compile the design 1 Set the working library a Type vlib work in the ModelSim Transcript window to create the working library 2 Compile and link all SystemC files a Type sccom g basic cpp at the ModelSim gt prompt The g argument compiles the design for debug Upon successfully compiling the design the following message is issued to the screen Model Technology ModelSim sccom compiler 2003 05 May 25 2004 Exported modules top b Type sccom link at the ModelSim gt prompt to perform the final link on the SystemC objects You have successfully completed the compilation of the design The successful compilation verifies that all the necessary file modifications have been entered correctly ModelSim SE Tutorial basic orig cpp original file include ba
10. dow You can display connectivity in the Dataflow window using hierarchical instances You enable this by modifying the options prior to adding objects to the window Change options to display hierarchy a Select Tools Options from the Dataflow window menu bar b Check Show Hierarchy and then click OK Figure 76 2 Add signal t_out to the Dataflow window a Typeadd dataflow top p t out at the VSIM prompt The Dataflow window will display t out and all hierarchical instances Figure 77 ModelSim SE Tutorial Figure 76 The Dataflow options dialog Dataflow Options E x General options Warning options Keep previous contents when adding new nets or instances to the Dataflow window z dataflow IV Hide cells V Keep Dataflow Show Hierarchy FM Bottom inout pins Disable Sprout Select equivalent nets Lognets IV Select Environment IV Automatic Add to Wave Figure 77 Dataflow window displaying with hierarchy et 3 File Edit View Navigate Trace Tools Window Si Ras X IB OO FA le HHH 61 E E201 amp B m gt Extended mode enabled Hier Keep 1 ftop p t out Z Lesson Wrap up T 97 Lesson Wrap up This concludes this lesson Before continuing we need to end the current simulation 1 Type quit sim at the VSIM gt prompt ModelSim SE Tutorial T 98 Lesson 8 Debugging with the Dataflow window ModelSim SE Tutorial Lesson 9
11. m Default Library Name work Creating a new project T 33 2b 2G 2d ModelSim SE Tutorial T 34 Lesson 3 ModelSim projects Adding objects to the project Once you click OK to accept the new project settings you will see a blank Project tab in the workspace area of the Main window and the Add items to the Project dialog will appear Figure 15 From this dialog you can create a new design file add an existing file add a folder for organization purposes or create a simulation configuration discussed below 1 Add two existing files a Click Add Existing File This opens the Add file to Project dialog Figure 16 This dialog lets you browse to find files specify the file type specify which folder to add the file to and identify whether to leave the file in its current location or to copy it to the project directory b Click Browse c Open the examples directory in your ModelSim installation tree d Verilog Select counter v hold the Ctrl key down and then select tcounter v VHDL Select counter vhd hold the Ctrl key down and then select tcounter vhd e Click Open and then OK f Click Close to dismiss the Add items to the Project dialog ModelSim SE Tutorial Figure 15 Adding new items to a project x ModelSim File Edit View Format Compile Simulate Add Tools Window Help lue Se c id Sa gti i amp SR amp s Contains t ini x i
12. 0 add button num list bookmark goto wave bk num These commands do the following e Create a new procedure called add wave zoom that has two arguments stime and num e Create a bookmark with a zoom range from the current simulation time minus 50 time units to the current simulation time plus 100 time units e Add a button to the Main window that calls the bookmark b Now add these lines to the bottom of the script add wave r when clk event and clk 1 echo Count is exa count if exa count 00100111 add_wave_zoom Snow 1 elseif exa count 01000111 add_wave_zoom Snow 2 ModelSim SE Tutorial These commands do the following e Add all signals to the Wave window e Use a when statement to identify when clk transitions to 1 Examine the value of count at those transitions and add a bookmark if it is a certain value Save the script with the name add_bkmrk do Save it into the directory you created in Lesson 2 Basic simulation 2 Load the test counter design unit a b Start ModelSim Select File gt Change Directory and change to the directory you saved the DO file to in step 1c above In the Library tab of the Main window expand the work library and double click the test counter design unit 3 Execute the DO file and run the design a b Type do add bkmrk do at the VSIM gt prompt Type run 1500 ns at the VSIM gt prompt The simulation runs and
13. REF states a Expand assert check refresh to reveal all signals referenced by the assertion Resize and scroll the Wave window so you can see we n under the Assertions divider and the mem state signal in the Memory Controller section above the assertions Figure 126 Zoom in on the last 600 ns of the simulation using the Zoom in 2x icon or the View Zoom menu selections It is easy to see that we n is high only during the REF state It is low during REF2 Let s examine we n further Debugging the assertion failure T 141 Figure 125 Source code for failed assertion C PSL Tutorial DRAM cntrlr extemal vlog dram cntrl psi 16 1 18 19 20 21 22 23 declare refresh sequence check sequence refresh sequence cas_n amp ras n amp ve n 1 cas n amp ras n amp wen property check refresh always roseirefresh gt mem state IDLE 0 14 mem state abort fellireset n 24 assert check refresh 2s 26 2 28 29 30 31 dramcon sim v dram cntrl psl Figure 126 Examining we n with respect to mem state declare refresh rate check sequence signal refresh 24 rose refresh property refresh rate always rose reset_n roset signal refresh abort assert refresh rate ii File Edit View Insert Format Tools Window sas 4 mem state S CAS ACK IDLE JREFI JREF2 tefresh Asser
14. Radix to Binary Click OK to accept the changes and close the dialog Fi d Select File gt Save to bring up the Save Memory dialog box E Le e Specify a Start address of 0 and End address of 250 EN oo mem mem Browse f For Address Radix select Decimal and for Data Radix select Binary ok ES g Click No addresses to create a memory pattern that you can use to relocate somewhere else in the memory or in another memory Te h Enter the file name as reloc mem then click OK to save the memory contents and close the dialog ModelSim SE Tutorial You will use this file for initialization in the next section Initializing a memory In ModelSim it is possible to initialize a memory using one of three methods from a saved memory file from a fill pattern or from both First let s initialize a memory from a file only You will use one you saved previously data mem mem View instance ram tb spram3 mem a Double click the ram_tb spram3 mem instance in the Memories tab This will open a new tab mem 2 in the MDI frame to display the contents of ram tb spram3 mem Scan these contents so you can identify changes once the initialization is complete Right click and select Properties to bring up the Properties dialog Change the Address Radix to Decimal and Data Radix to Binary and click OK 2 Initialize spram3 from a file a b C Right click anywhere in the data column and sel
15. T 106 Lesson 9 Viewing and initializing memories Saving memory contents to a file Figure Suconye MEET MINE KOX x You can save memory contents to a file that can be loaded at some later point in mE xl simulation Instance Name Aram tb spram1 mem 1 Save a memory pattern from the ram tb spram1 mem instance to a file a Make sure ram_tb spraml mem is open and selected in the MDI frame Address Range b Select File gt Save to bring up the Save Memory dialog box Figure 86 Al c Forthe Address Radix select Decimal Addresses in decimal d For the Data Radix select Binary start 0 End 4035 e Typedata mem mem into the Filename field f Click OK m File Format You can view the saved file in any editor C Verilog Hex No addresses r B Memory pattern files can be saved as relocatable files simply by leaving out the vers Econ Compress address information Relocatable memory files can be loaded anywhere in a f MTI memory because no addresses are specified r Address Radix Data Radix 6 B r pe 2 Save a relocatable memory pattern file from the ram_tb spram2 mem Mn ee instance Decimal Binary a Select the mem 1 tab in the MDI pane to see the data for the ram tb S 2 kis spram2 mem instance ic 1d C Decimal b Right click on the memory contents to open a popup menu and select C Unsigned Properties Hexadecimal c Inthe Properties dialog set the Address Radix to Decimal and the Data
16. T 90 Lesson 8 Debugging with the Dataflow window Introduction The Dataflow window allows you to explore the physical connectivity of your design to trace events that propagate through the design and to identify the cause of unexpected outputs The window displays processes signals nets and registers and interconnect Design files for this lesson The sample design for this lesson is a testbench that verifies a cache module and how it works with primary memory A processor design unit provides read and write requests The pathnames to the files are as follows Verilog install dir modeltech examples dataflow verilog VHDL install dir modeltech examples dataflow vhdl This lesson uses the Verilog version in the examples If you have a VHDL license use the VHDL version instead When necessary we distinguish between the Verilog and VHDL versions of the design Related reading ModelSim User s Manual Tracing signals with the Dataflow window UM 299 ModelSim GUI Reference Dataflow window GR 128 ModelSim SE Tutorial Compiling and loading the design In this exercise you will use a DO file to compile and load the design 1 Create a new directory and copy the tutorial files into it Start by creating a new directory for this exercise in case other users will be working with these lessons Create the directory and copy all files from lt install_dir gt examples dataflow verilog to the new direct
17. Using cursors in the Wave window T 71 2 Rename the cursor Figure 52 Renaming a cursor a Right click Cursor 1 in the cursor name pane and select and delete the Ini x text Figure 52 File Edit View Insert Format Tools Window aK b Type A and press Enter E EE 5 Bas RM le BR aL aL x a 1 QQ Bcoe The cursor name changes to A 4 Jtest_counter clk 4 jest counter reset E4 test counter count 3 Jump the cursor to the next or previous transition a Click signal count in the pathname pane a Click the Find Next Transition icon on the Wave window toolbar The cursor jumps to the next transition on the currently selected signal b Click the Find Previous Transition icon on the Wave window toolbar 177 ris to 448 ns Figure 53 Interval measurement between two cursors The cursor jumps to the previous transition on the currently selected LT ax signal File Edit View Insert Format Tools Window IR a Q ax Working with multiple cursors 4 jest counter clk 0 1 Add a second cursor m 4 jest counter reset 0 I a Click the Add Cursor icon on the Wave window toolbar EE OMM MR MT Oe ee ee ee EE GEN END EUR UR NIE 14 b Right click the name of the new cursor and delete the text Type B and press Enter d Drag cursor B and watch the interval measurement change dynamically Figure 53 cu Now 1 us Delta 2 72 1d ModelSim SE Tutorial Mo
18. Viewing and initializing memories Topics The following topics are covered in this lesson Introduction Related reading Compiling and loading the design Viewing a memory Navigating within the memory Saving memory contents to a file Initializing a memory Interactive debugging commands Lesson Wrap up T 100 T 100 T 101 T 102 T 104 T 106 T 107 T 109 T 111 T 99 ModelSim SE Tutorial T 100 Lesson 9 Viewing and initializing memories Introduction In this lesson you will learn how to view and initialize memories in ModelSim ModelSim defines and lists as memories any of the following e reg wire and std logic arrays e Integer arrays e Single dimensional arrays of VHDL enumerated types other than std_logic Design files for this lesson The ModelSim installation comes with Verilog and VHDL versions of the example design The files are located in the following directories Verilog install dir modeltech examples memory verilog VHDL install dir modeltech examples memory vhdl This lesson uses the Verilog version for the exercises If you have a VHDL license use the VHDL version instead Related reading ModelSim GUI Reference Memory windows GR 169 ModelSim Command Reference mem display CR 196 mem load CR 199 mem save CR 202 radix CR 241 commands ModelSim SE Tutorial Compiling and loading the design 1 Create a n
19. modeltech examples systemc sc basic into the new directory 2 Start ModelSim and change to the exercise directory If you just finished the previous lesson ModelSim should already be running If not start ModelSim a Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows If the Welcome to ModelSim dialog appears click Close b Select File Change Directory and change to the directory you created in step 1 ModelSim SE Tutorial 3 Useatexteditor to view and edit the basic orig cpp file To use ModelSim s editor from the Main Menu select File gt Open Change the files of type to C C files then double click basic orig cpp The red highlighted code in the orig files Figure 36 indicates the section of the code that needs modification a Using the ifdef MTI SYSTEMC preprocessor directive add the SC MODULE EXPORT top to the design see Figure 36 Close the preprocessing directive with else The original code in the cpp file follows directly after else Of course that section the file must end with endif b Save the file as basic cpp 4 View and edit the basic orig h header file a Add a ModelSim specific SC MODULE top see Figure 36 The declarations that were in sc main are placed here in the header file in SC MODULE top This creates a top level module above mod a which allows the tool s automatic name binding feature to properly associate the primitive channels with their names
20. paper shipped with ModelSim PDF select Help Documentation also available from the Support page of our web site www model com ModelSim Tutorial PDF HTML select Help Documentation also available from the Support page of our web site www model com ModelSim User s Manual PDF HTML select Help Documentation ModelSim Command Reference PDF HTML select Help Documentation ModelSim GUI Reference PDF HTML select Help Documentation Foreign Language Interface Reference PDF HTML select Help Documentation Std DevelopersKit User s Manual PDF www model com support documentation BOOK sdk um pdf The Standard Developer s Kit is for use with Mentor Graphics QuickHDL Command Help type help command name at the prompt in the Transcript pane Error message help type verror lt msgNum gt at the Transcript or shell prompt Tcl Man Pages Tcl manual select Help Tcl Man Pages or find contents htm in VnodeltechNdocsNcl help html Technotes select Technotes dropdown on www model com support Where to find our documentation T 7 ModelSim SE Tutorial T 8 Introduction Technical support and updates Support Model Technology online and email technical support options maintenance renewal and links to international support contacts www model com support default asp Mentor Graphics support www mentor com supp
21. vhd 1 Copyright Model Technology a Mentor Graphics zi z Corporation company 2004 All rights reserved 3 4 LIBRARY parts lib 5 USE parts _lib ALL 6 entity test counter is 8 PORT count BUFFER bit vector 98 downto 1 9 end 10 11 architecture only of test counter is 12 13 COMPONENT counter l4 PORT count BUFFER bit vector 8 downto 1 15 clk IN bit 16 reset IN bit fi tcounter vhd Ej Permanently mapping resource libraries If you reference particular resource libraries in every project or simulation you may want to permanently map the libraries Doing this requires that you edit the master modelsim ini file in the installation directory Though you won t actually practice it in this tutorial here are the steps for editing the file 1 Locate the modelsim ini file in the ModelSim installation directory install dir2 modeltech modelsim ini 2 IMPORTANT Make a backup copy of the file 3 Change the file attributes of modelsim ini so it is no longer read only 4 Open the file and enter your library mappings in the Library section For example parts lib C libraries parts lib 5 Save the file 6 Change the file attributes so the file is read only again Permanently mapping resource libraries T 49 ModelSim SE Tutorial T 50 Lesson 4 Working with multiple libraries Lesson wrap up This concludes this lesson Before continuing we need to end the current simulation and clo
22. 01101001 01101110 01101111 01110100 01110101 11336536 331734131 mem f mem 1 ram 1t5 v Figure 81 Changing the address radix HITTCENEENSST x Address Radis Hexadecimal Decimal e Cc C Cc C C Data Radix Symbolic Binary Octal Decimal Unsigned Hexadecimal Line Wrap C Fit in Window Words per Line fi OK Cancel ModelSim SE Tutorial T 104 Lesson 9 Viewing and initializing memories Navigating within the memory You can navigate to specific memory address locations or to locations containing particular data patterns First you will go to a specific address Use Goto to find a specific address a Right click anywhere in address column and select Goto Figure 83 The Goto dialog box opens in the data pane b Type 30 in the dialog box c Click OK The requested address appears in the top line of the window ModelSim SE Tutorial Figure 82 Memory window new address radix and line length E ram_tb spram1 mem 00101000 00101001 00101010 00101011 00101100 00101101 00101110 00101111 00110000 00110001 00110010 00110011 00110100 annn 0 1 2 3 4 5 6 7 8 a M Ot J Figure 83 The Goto dialog box E ACO mem 00101000 00101001 00101010 00101011 00101100 yi Goto Memory X 00101101 Goto Address 00101110 00101111 a0 00110000 00110001 00110010 00110011 00110100 1a Edit
23. 116 ModelSim SE Tutorial Figure 109 Coverage columns in the Main window Workspace Workspace Stmt Branch Count Branch Hits Branch Branch Graph Cc 22 21 95455 DEN 14 13 892857 EE 30 27 90 000 SN 20 17 85000 SSSR 10 3 90000 EE 8 7 8500 DS 83 75 90361 a af age ETE Missed Statements test sm v X 25 5 Details E i FE X 25 into 4 b0001 28 b0 Instance test sm sram 0 i Signal dat r X 2e posedge clk Node count 32 X 27 g X 27 into data gt 0 12525 gt 1 12499 X icc Toggle Coverage 25 X 128 i 0 1 Coverage 62 5 X 128 stop Current Exclusions Full Coverage 62 5 sm v entire file X Z Coverage 62 5 4 test sm v test sm v pragma EF Lines 25 29 Line 25 Line 26 Line 27 Line 28 Instance Coverage RE wmnsance Designunit Designunttype Stmeount Stmthis Stmtmisses Stmt Stmtgraph M test sm sram 0 beh sram Module 10 3 1 90 RET M est sm sm seq sm O0 sm Module 30 2 3 90 EET M test sm sm seq sm seq Module 22 21 1 955 E M test_sm 83 test_sm Module Viewing statistics in the Main window T 127 Viewing stati stics in the Mai n wi ndow Figure 111 Right click a column heading to hide or show columns Workspace Branch Count Branch Hits Imt Count Stmt Hits Stmt Stmt Graph _ Fullpath 30 27 90000 EM Type 10 3 90 000 i v StmtCou
24. Add items to the Project xj Statul T ao i 3 R Name mm creel ed Click on the icon to add items of that type Create New File Add Existing File ui FSS SSS EEE a Project Library TER EE Create Simulation Create New Folder Loading project test ModelSim gt Project test No Design Loaded gt Figure 16 The Add file to Project dialog y Add file to Project File Name counter vcounter v Browse m Add file as type Folder default zz files vi Reference from current location Copy to project directory You should now see two files listed in the Project tab of the Workspace pane Figure 17 Question mark icons in the Status column mean the file hasn t been compiled or the source file has changed since the last successful compile The other columns identify file type e g Verilog or VHDL compilation order and modified date Changing compile order VHDL Compilation order is important in VHDL designs Follow these steps to change compilation order within a project 1 Change the compile order a Select Compile Compile Order This opens the Compile Order dialog box Figure 18 Click the Auto Generate button ModelSim determines the compile order by making multiple passes over the files It starts compiling from the top if a file fails to compile due to dependencies it moves that file to the bottom an
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26. INST block Ztest ringbuf ring INST block Ztest ringbuf ring INST block test rinabuf ring INST block test_tingbuf ring_INST block 7test ringbuf ring INST block Ztest ringbuf ring INST block test ringbufZring INST block 7test ringbuf ring INST block 00000 62300 463000 ns 2 es CI sf d eal 461988 ns to 463241 ns cursor name Now 500 us cursor value Delta 2 cursor Loading a design For the examples in this lesson we have used the design simulated in Lesson 2 Basic simulation 1 If you just finished the previous lesson ModelSim should already be running If not start ModelSim a Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows If the Welcome to ModelSim dialog appears click Close 2 Loadthe design a Select File gt Change Directory and open the directory you created in Lesson 2 The work library should already exist b Click the icon next to the work library and double click test counter ModelSim loads the design and adds sim and Files tabs to the Workspace Loading a design T 67 ModelSim SE Tutorial T 68 Lesson 6 Viewing simulations in the Wave window Adding objects to the Wave Wi ndow Figure 48 A Wave window docked in the Main window ModelSim offers several methods for adding objects to the Wave window In this SE 4 jest counter clk exercise you
27. Lesson 11 Simulating with Code Coverage Introduction ModelSim Code Coverage gives you graphical and report file feedback on which executable statements branches conditions and expressions in your source code have been executed It also measures bits of logic that have been toggled during execution Design files for this lesson The sample design for this lesson consists of a finite state machine which controls a behavioral memory The testbench fest sm provides stimulus The ModelSim installation comes with Verilog and VHDL versions of this design The files are located in the following directories Verilog install dir modeltech examples coverage verilog VHDL install dir modeltech examples coverage vhdl This lesson uses the Verilog version in the examples If you have a VHDL license use the VHDL version instead When necessary we distinguish between the Verilog and VHDL versions of the design Related reading ModelSim User s Manual Chapter 13 Measuring code coverage UM 333 ModelSim SE Tutorial Compiling the design Enabling Code Coverage is a two step process first you compile the files and identify which coverage statistics you want second you load the design and tell ModelSim to produce those statistics 1 Create a new directory and copy the tutorial files into it Start by creating a new directory for this exercise in case other users will be working with these lessons Create the dire
28. Loading work control Loading work store Loading work retrieve Now Ons Delta 0 sim test_ringbuf Setting breakpoints and stepping in the Source window As with HDL files you can set breakpoints and step through SystemC files in the Source window In the case of SystemC ModelSim uses C Debug an interface to the open source gdb debugger Please see C Debug UM 399 for complete details 1 Set a breakpoint a Double click on test_ringbuf in the Main window workspace to bring up the Source window b Inthe Source window scroll to near line 148 of test_ringbuf h c Click on or just to the right of the line number next to the line shown in Figure 42 containing Verilog bool var dataerror newval actual read VHDL SC logic var dataerror newval acutal read ModelSim recognizes that the file contains SystemC code so it automatically launches C Debug Once the debugger is running ModelSim places a solid red sphere next to the line number Figure 42 2 Run and step through the code a Type run 500 at the VSIM gt prompt When the simulation hits the breakpoint it stops running highlights the line with an arrow in the Source window Figure 43 and issues the following message in the Main window C breakpoint c 1 test_ringbuf compare_data this 0x842f658 at test ringbuf h line number Viewing SystemC objects in the GUI T 61 Figure 40 SystemC objects in the work library Library
29. ModelSim uses libraries in two ways 1 as a local working library that contains the compiled version of your design 2 as a resource library The contents of your working library will change as you update your design and recompile A resource library is typically static and serves as a parts source for your design You can create your own resource libraries or they may be supplied by another design team or a third party e g a silicon vendor You specify which resource libraries will be used when the design is compiled and there are rules to specify in which order they are searched A common example of using both a working library and a resource library is one where your gate level design and testbench are compiled into the working library and the design references gate level models in a separate resource library The diagram below shows the basic steps for simulating with multiple libraries You can also link to resource libraries from within a project If you are using a project you would replace the first step above with these two steps create the project and add the testbench to the project ModelSim SE Tutorial Debugging tools T 17 Debugging tools ModelSim offers numerous tools for debugging and analyzing your design Several of these tools are covered in subsequent lessons including Setting breakpoints and stepping through the source code Viewing waveforms and measuring time Exploring the physical connectivity of
30. USE OF SOFTWARE INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH IN THIS AGREEMENT If you do not agree to these terms and conditions promptly return or if received electronically certify destruction of Software and all accompanying items within five days after receipt of Software and receive a full refund of any license fee paid END USER LICENSE AGREEMENT GRANT OF LICENSE The software programs you are installing downloading or have acquired with this Agreement including any updates modifications revisions copies documentation and design data Software are copyrighted trade secret and confidential information of Mentor Graphics or its licensors who maintain exclusive title to all Software and retain all rights not expressly granted by this Agreement Mentor Graphics grants to you subject to payment of appropriate license fees a nontransferable nonexclusive license to use Software solely a in machine readable object code form b for your internal business purposes and c on the computer hardware or at the site for which an applicable license fee is paid or as authorized by Mentor Graphics A site is restricted to a one half mile 800 meter radius Mentor Graphics standard policies and programs which vary depending on Software license fees paid or service plan purchased apply to the following and are subject to change a relocation of Software b use of Software which may be
31. and expected data 145 ff 146 inline void test ringbuf compare data 147 148 bool var dataerror newval actual read expected read 143 dataerror write var_dataerror_newval 150 1516 if reset read 0 400X49 152 153 storage write 0 154 expected write 0 155 actual write 0 156 counter 157 158 else 1 FI Ja Viewing SystemC objects in the GUI T 63 2 Click the Continue Run button again Figure 44 ModelSim steps into a function in a separate file The simulation runs for 500 ns and waves are drawn in the Wave window Figure 46 ES uimtiextra builds mainline modeltech nclude systemc sc sianal h POuNMC EE RETI C Cen n 523 ff get the negative edge event window transcript These warnings are related to VHDL value 530 virtual const sc event negedge event const 531 return m negedge event conversion routines and can be ignored 532 533 534 535 virtual const bool amp read const 536 mb return m cur val 53 538 If you are using the VHDL version you might see warnings in the Main 533 virtual const bool amp get data ref const 540 return m cur wal 541 542 543 Was there a value changed event Gd4 wirtnal hanl ewent nnnct He D C test ringbuf h Che_signal h Figure 45 Output of show command 3 ptype this 3 type class test ringbuf public sc module 1 public struct sc clock clock sc
32. bar Figure 61 c Inthe Edit Stretch Edge dialog enter 50 for Duration make sure the Time field shows 350 and then click OK Figure 62 The wave edge stretches so it s high until 400 ns Note the difference between stretching and moving an edge the Stretch command moves an edge by moving other edges on the waveform either increasing waveform duration or deleting edges at the beginning of simulation time the Move command moves an edge but does not move other edges on the waveform If you scroll the Wave window to the right you will see that the waveform for signal c k now extends to 1050 ns Editing waveforms in the Wave window T 81 Figure 61 The Edit Stretch Edge dialog uJ Edit Stretch Edge E x Signal Name Edit counter clk Direction Forward Backward Duration Time Time Unit o po rs Figure 62 Stretching an edge on signal clk E woe deraue File Edit View Insert Format Tools Window SLE x mjs QQ e Bc LES UL i ag Edit counter clk sto 4 Edit counter reset Now Cursor t 1 KJ I Eb El Ons to 1023 ns Now ns Delta 0 A ModelSim SE Tutorial T 82 Lesson 7 Creating stimulus with Waveform Editor 3 Delete an edge Figure 63 Deleting an edge on signal clk a Click signal clk just to the right of the transition at 350 ns IT ax ARE jf amp Q a File Edit View Insert Format Tools Window The cursor should snap to 350 ns b Click the Delet
33. compiles both files and changes the symbol in the Status column to a check mark A check mark means the compile succeeded If the compile had failed the symbol would be a red X and you would see an error message in the Transcript pane 2 View the design units Click the Library tab in the workspace b Click the icon next to the work library You should see two compiled design units their types modules in this case and the path to the underlying source files Figure 19 3 Load the fest counter design unit a Double click the test counter design unit You should see a new tab named sim that displays the structure of the test counter design unit Figure 20 A fourth tab named Files contains information about the underlying source files At this point you would generally run the simulation and analyze or debug your design like you did in the previous lesson For now you ll continue working with the project However first you need to end the simulation that started when you loaded test counter 4 End the simulation a Select Simulate End Simulation b Click Yes ModelSim SE Tutorial Figure 19 The Library tab with an expanded library Library C modeltech examples w Module C modeltech examples c1 Module C modeltech examples te Library MODEL TECH vital20 Library MODEL TECH ieee Library MODEL TECH models Library MODEL_TECH std Library MODEL TECH std de Library MODEL TECH synop
34. count and select Add to Wave gt Selected Signals 2 Import the VCD file a Inthe Wave window select File gt Import EVCD b Double click export vcd The created waveforms draw in the Wave window c Click the Run All icon The simulation runs for 1000 ns and the waveform is drawn for sim counter count When you import an EVOD file signal mapping happens automatically if signal names and widths match If they do not you have to manually map the signals See Signal mapping and importing EVCD files GR 295 for more information Importing an EVCD file T 87 ModelSim SE Tutorial T 88 Lesson 7 Creating stimulus with Waveform Editor Lesson wrap up This concludes this lesson Before continuing we need to end the current simulation 1 Select Simulate gt End Simulation Click Yes ModelSim SE Tutorial Lesson 8 Debugging with the Dataflow window Topics The following topics are covered in this lesson Introduction Related reading Compiling and loading the design Exploring connectivity Tracing events Tracing an X unknown Displaying hierarchy in the Dataflow window Lesson Wrap up gt Note The functionality described in this tutorial requires a dataflow license feature in your ModelSim license file Please contact your Mentor Graphics sales representative if you currently do not have such a feature T 90 T 90 T 91 T 92 T 93 T 95 T 96 T 97 T 89 ModelSim SE Tutorial
35. examples compare verilo g gold wi opened as dataset gold compare start gold sim compare options track compare add recursive all wave Created 11 comparisons compare run Computing waveform differences from ti me Ops to 750 ns Found 12 differences Figure 134 Comparison objects in the Wave window wave default E E File Edit View Insert Format Tools Window ete fe s bt sim test sm rd sim test_sm wr_ compare test_sm i compare test_sm compare test_sm r compare test_sm compare test_sm EX compare test_sm compare test sm compare test sm A compare test_sm i compare test sm r Now 750000 ps 748800 ps 454800 ps to 455600 ps Now 750 ns Delta 2 Figure 135 The compare icons Ie ie EEE T 153 ModelSim SE Tutorial T 154 Lesson 13 Waveform Compare Viewing comparison data in the List window You can also view the results of your waveform comparison in the List window 1 Add comparison data to the List window Select View gt Debug Windows gt List from the Main window menu bar b Drag the test sm comparison object from the compare tab of the Main window to the List window c Scroll down the window Differences are noted with yellow highlighting Figure 136 Differences that have been annotated have red highlighting Mod
36. i amp carry 26 end 2 end 23 endfunction 29 30 always posedge clk or posedge reset if reset cogunt ftpd reset to count 8 h00 else count rement count ftest counter dut count f hr XXXXXXXX 6 AAA A QJ counter v Figure 13 Values shown in the Objects window count clk reset tpd_reset_to_count 3 Parameter Internal tpd clk to count 2 Parameter Internal NMNRMNMM Reg Out Sto Net In SH Net In Lesson wrap up T 29 Lesson wrap up This concludes this lesson Before continuing we need to end the current simulation 1 Select Simulate gt End Simulation 2 Click Yes when prompted to confirm that you wish to quit simulating ModelSim SE Tutorial T 30 Lesson 2 Basic simulation ModelSim SE Tutorial Lesson 3 ModelSim projects Topics The following topics are covered in this lesson Introduction Related reading Creating anew project Adding objects to the project Changing compile order VHDL Compiling and loading a design Organizing projects with folders Adding folders Moving files to folders Simulation Configurations Lesson wrap up T 32 T 32 T 33 T 34 T 35 T 36 T 37 T 37 T 38 T 39 T 40 T 31 ModelSim SE Tutorial T 32 Lesson 3 ModelSim projects Introduction In this lesson you will practice creating a project At a minimum projects have a work library and a session state that is stored in a mpf
37. less a reasonable allowance for use 9 3 Mentor Graphics has no liability to you if infringement is based upon a the combination of Software with any product not furnished by Mentor Graphics b the modification of Software other than by Mentor Graphics c the T 171 ModelSim SE Tutorial T 172 License Agreement 10 11 12 13 14 15 use of other than a current unaltered release of Software d the use of Software as part of an infringing process e a product that you make use or sell f any Beta Code contained in Software g any Software provided by Mentor Graphics licensors who do not provide such indemnification to Mentor Graphics customers or h infringement by you that is deemed willful In the case of h you shall reimburse Mentor Graphics for its attorney fees and other costs related to the action upon a final judgment 9 4 THIS SECTION 9 STATES THE ENTIRE LIABILITY OF MENTOR GRAPHICS AND ITS LICENSORS AND YOUR SOLE AND EXCLUSIVE REMEDY WITH RESPECT TO ANY ALLEGED PATENT OR COPYRIGHT INFRINGEMENT OR TRADE SECRET MISAPPROPRIATION BY ANY SOFTWARE LICENSED UNDER THIS AGREEMENT TERM This Agreement remains effective until expiration or termination This Agreement will immediately terminate upon notice if you exceed the scope of license granted or otherwise fail to comply with the provisions of Sections 1 2 or 4 For any other material breach under this Agreement Mentor Graphics may terminate this
38. mouse location You can also add additional cursors name lock and delete cursors use cursors to measure time intervals and use cursors to find transitions Working with a single cursor 1 Position the cursor by clicking and dragging a Click the Select Mode icon on the Wave window toolbar b Click anywhere in the waveform pane A cursor is inserted at the time where you clicked Figure 51 c Drag the cursor and observe the value pane The signal values change as you move the cursor This is perhaps the easiest way to examine the value of a signal at a particular time d Inthe waveform pane drag the cursor to the right of a transition with the mouse positioned over a waveform The cursor snaps to the transition Cursors snap to a waveform edge if you click or drag a cursor to within ten pixels of a waveform edge You can set the snap distance in the Window Preferences dialog select Tools Window Preferences e Inthe cursor pane drag the cursor to the right of a transition Figure 51 The cursor doesn t snap to a transition if you drag in the cursor pane ModelSim SE Tutorial Figure 51 Working with a single cursor in the Wave window wave default El x File Edit View Insert Format Tools Window sue x ema nores st 4 jest counter clk Er 4 test counter count 00010011 wat wat 4 jest counter reset Now 177 ns to 448 ns Now 1 us Delta 2 1e
39. on Contracts for the International Sale of Goods does not apply to this Agreement SEVERABILITY If any provision of this Agreement is held by a court of competent jurisdiction to be void invalid unenforceable or illegal such provision shall be severed from this Agreement and the remaining provisions will remain in full force and effect PAYMENT TERMS AND MISCELLANEOUS You will pay amounts invoiced in the currency specified on the applicable invoice within 30 days from the date of such invoice This Agreement contains the parties entire understanding relating to its subject matter and supersedes all prior or contemporaneous agreements including but not limited to any purchase order terms and conditions except valid license agreements related to the subject matter of this Agreement which are physically signed by you and an authorized agent of Mentor Graphics either referenced in the purchase order or otherwise governing this subject matter This Agreement may only be modified in writing by authorized representatives of the parties Waiver of terms or excuse of breach must be in writing and shall not constitute subsequent consent waiver or excuse The prevailing party in any legal action regarding the subject matter of this Agreement shall be entitled to recover in addition to other relief reasonable attorneys fees and expenses Rev 040401 Part Number 221417 T 173 ModelSim SE Tutorial T 174 License Agreement ModelSim SE Tutorial
40. process or signal caused the unexpected output 1 Add an object to the Dataflow window Make sure instance p is selected in the sim tab of the Main window b Drag signal t out from the Objects pane into the Dataflow window c Select View Show Wave in the Dataflow window to open the wave viewer Figure 70 You may need to increase the size of the Dataflow window and scroll the panes to see everything 2 Tracethe inputs of the nand gate a Select process NAND 44 labeled line 62 in the VHDL version in the dataflow pane All input and output signals of the process are displayed automatically in the wave viewer b Inthe wave view scroll to time 2785 ns the last transition of signal t out c Click on the last transition of signal t out to set a cursor Figure 71 Tracing events T 93 Figure 70 The embedded wave viewer pane EET NN ini x File Edit View Navigate Trace Tools Window SiR m 4M BOAO Mi Je 9 X 3e 3 9 E2 EZ 01 amp Bo mi test NAND 44 3l t out strb 3 js8 954 xem R ec TX mj ae R amp Bx 3e ia CRE Ons Fr FT TH Extended mode enabled Keep 1 Atop p t out SA Figure 71 Signals added to the wave viewer automatically datanom MT File Edit View Navigate Trace Tools Window Sikap X Ba I 20 7 M Je e X 3e 3 AMAA B m jS edd rmea
41. the comparison configuration rules to a separate file When you reload the data you must have the reference dataset open 1 Save the comparison data to a text file Select Tools Waveform Compare Differences Write Report b Click Save This saved compare txt to the current directory Figure 137 c Type notepad compare txt at the VSIM gt prompt d Close Notepad when you are done reviewing the report 2 Save the comparison data in files that can be reloaded into ModelSim Select Tools gt Waveform Compare gt Differences gt Save b Click Save This saved compare dif to the current directory Select Tools Waveform Compare Rules Save d Click Save This saved compare rul to the current directory e Select Tools Waveform Compare End Comparison Saving and reloading comparison data Figure 137 Coverage data saved to a text file ini xi File Edi Window E compare tst Total signals compared 11 Total primary differences 6 Total secondary differences 6 Number of primary signals with differences 4 Diff number 1 From time 135 ns delta O0 to time 155 ns gold test sm into 00000000000000000000000010101010 sim test sm into 00000000000000000000000010101011 Diff number 2 From time 135 ns delta O0 to time 155 ns gold test sm into 0 O sim test sm into 0 1 Diff number 3 From time 171 ns delta 1 to time 191 ns gold test sm dat 00000000000000000000000010101010 sim test_sm dat 00000000
42. the view argument a Type vsim view counter wlf at the DOS UNIX prompt The GUI opens and a dataset tab named counter is displayed in the Workspace Figure 140 b Right click the counter instance and select Add gt Add to Wave The waveforms display in the Wave window When you finish viewing the results select File Quit to close ModelSim Running ModelSim in command line mode T 165 Figure 140 A dataset in the Main window Workspace M counter counter Madule HSE rmm counter gt ModelSim SE Tutorial T 166 Lesson 14 Automating ModelSim Using Tcl with ModelSim The DO files used in previous exercises contained only ModelSim commands However DO files are really just Tcl scripts This means you can include a whole variety of Tcl constructs such as procedures conditional operators math and trig functions regular expressions and so forth In this exercise you ll create a simple Tcl script that tests for certain values on a signal and then adds bookmarks that zoom the Wave window when that value exists Bookmarks allow you to save a particular zoom range and scroll position in the Wave window The Tcl script also creates buttons in the Main window that call these bookmarks 1 Create the script a Ina text editor open a new file and enter the following lines proc add wave zoom stime num echo Bookmarking wave num bookmark add wave bk num expr stime 50 expr stime 100
43. the DO file creates two bookmarks It also creates buttons labeled 1 and 2 on the Main window toolbar that jump to the bookmarks Figure 141 Click the buttons and watch the Wave window zoom on and scroll to the time when count is the value specified in the DO file Using Tcl with ModelSim T 167 ModelSim SE Tutorial T 168 Lesson 14 Automating ModelSim Lesson Wra p u p Figure 141 Buttons added to the Main window toolbar x ModelSim This concludes this lesson Fie Edit View Format Compile Simulate Add Tools Window Help 1 Select File gt Quit to close ModelSim EHE test counter test counter Module M dut counter Module SIMPLICIT wWIRE res test counter Process E count 01001011 HIMPLICIT WIRE clk test counter Process RINITIALET lest counter Process D HINITIALH23 lest counter Process HINITIBLE3O lest counter Process SEWN SS QEL ModelSim SE Tutorial End User License Agreement IMPORTANT USE OF THIS SOFTWARE IS SUBJECT TO LICENSE RESTRICTIONS CAREFULLY READ THIS LICENSE AGREEMENT BEFORE USING THE SOFTWARE This license is a legal Agreement concerning the use of Software between you the end user either individually or as an authorized representative of the company acquiring the license and Mentor Graphics Corporation and Mentor Graphics Ireland Limited acting directly or through their subsidiaries or authorized distributors collectively Mentor Graphics
44. the address location directly To quickly move to a particular address do the following a Double click any address in the address column b Enter any desired address Figure 84 C Press Enter on your keyboard The pane scrolls to that address Now let s find a particular data entry a Right click anywhere in the data column and select Find The Find in dialog box opens Figure 85 Type 11111010 in the Find data field and click Find Next The data scrolls to the first occurrence of that address Click Find Next a few more times to search through the list Click Close to close the dialog box Figure 84 Edit the address directly Viewing a memory T 105 ram_tb sp ram mem 01000110 01000111 01001000 01001001 01001010 01001011 01001100 01001101 01001110 37 100 39 40 41 01001111 01010000 01010001 01010010 42 83000331 x H mem mem 1 ram 15 v Figure 85 Find in searching for data value ram tb spram1 mem 92 10000100 El 33 10000111 ond p ES A 94 1OOC WRLC ELLE CURE EU PETS 35 100 36 100 A a ae acai Find data 11111010 Find Next 38 100 jh Repl a Jobi Replace with eplace 100 100 Replace Al 101 100 102 1000 J Find backwards 103 100 104 100 Example Find Patterns Close mem mem T ram t5 v 1234 101 011 05 hfa38 ModelSim SE Tutorial
45. 000000000000000010101011 Diff number 4 From time 171 ns delta 1 to time 191 ns gold test sm dat 0 StO sim test sm dat 0 Sti Diff number 5 From time 409 ns delta 1 to time 411 ns gold test sm dat 00000000000000000000000010101010 sim test sm dat 00000000000000000000000010101011 Diff number 6 From time 409 ns delta 1 to time 411 ns gold test sm dat 0 sto sim test sm dat 0 Sti Diff number 7 From time 431 ns delta 1 to time 491 ns delta MA l4 enne cw ese wien nnnnnnnnnnnnnnnnnnnnnnnnsnin303n T 155 ModelSim SE Tutorial T 156 Lesson 13 Waveform Compare 3 Reload the comparison data Figure 138 Displaying log files in the Open dialog a Select Pile gt Open and opem b Change the Files of Type to Log Files wlf p Ovis e e Fe c Double click gold wlf to open the dataset Pe d Select Tools gt Waveform Compare gt Reload My Recent i vsim w Since you saved the data using default file names the dialog should ca already have the correct files specified Figure 139 e Click OK eee The comparison reloads My Documents Sr My Computer om T My Network Places Log Files wif 3b Figure 139 Reloading saved comparison data Reload and Redisplay Compare Differences OI X Waveform Rules file name compare ru Browse Waveform Difference file name compare df Browse ModelSim SE Tutorial Lesson wrap up This concl
46. 9 manuals T 7 mapping libraries permanently T 49 memories changing values T 109 initializing T 107 viewing T 99 memory contents saving to a file T 106 Memory window T 99 N notepad command T 155 O options simulation T 39 ModelSim SE Tutorial P Performance Analyzer T 113 filtering data T 120 physical connectivity T 92 Profiler profile details T 118 view profile data T 119 viewing profile details T 118 projects T 31 adding items to T 34 creating T 33 flow overview T 15 organizing with folders T 37 simulation configurations T 39 Q quit command T 46 R radix command T 102 reference dataset Waveform Compare T 149 reference signals T 148 run all T 26 run command T 25 S saving simulation options T 39 simulation basic flow overview T 13 comparing runs T 147 restarting T 27 running T 25 simulation configurations T 39 Standard Developer s Kit User Manual T 7 stepping after a breakpoint T 28 Support T 8 SystemC T 51 setting up the environment T 53 supported platforms T 53 viewing in the GUI T 60 T Tcl using in ModelSim T 166 Technical support and updates T 8 test dataset Waveform Compare T 150 test signals T 148 time measuring in Wave window T 70 T 85 toggle statistics Signals window T 131 tracing events T 93 tracing unknowns T 95 U unknowns tracing T 95 V vcom command T 101 verror command T 46 vlib command T 101 vlog command T 101 vsim command T 21 W Wave
47. 92 40 00000006 04 31 0000000 0000000 lt 24 25 0000000 lt e 26 27 sl J WENNE DER Y Jes OM 2b 26 ed ModelSim SE Tutorial T 110 Lesson 9 Viewing and initializing memories 3 Change contents by highlighting Figure 94 Changing contents by highlighting You can also change data by highlighting them in the Address Data pane amp l ram tb dprami mem 00000000 a Highlight the data for the addresses 0x0000000c 0x0000000e as shown 00000002 E 00000004 in Figure 94 00000006 00000008 ieht cli iehli 0000000 b Right click the highlighted data and select Change ee This brings up the Change dialog box Figure 95 Note that the aad Addresses field is already populated with the range you highlighted c Select Value as the Fill Type d Enter the data values into the Fill Data field as follow 34 35 36 F4 12 e Click OK nram tb v amp mem The data in the address locations change to the values you entered Figure g 96 Figure 95 Entering data to change 4 Edit data in place eel ea ane ram tb dpram1 mem To edit only one value at a time do the following Address Range Fill Type m a Double click any value in the Data column FA Vae b Enter the desired value and press Enter Qt bs send Start p000000c End D000000e S c When you are finished editing all values press the Enter key on your etl keyboard
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49. CT TO A SERVICES B SOFTWARE WHICH IS LICENSED TO YOU FOR A LIMITED TERM OR LICENSED AT NO COST OR C EXPERIMENTAL BETA CODE ALL OF WHICH ARE PROVIDED AS IS ModelSim SE Tutorial 5 2 THE WARRANTIES SET FORTH IN THIS SECTION 5 ARE EXCLUSIVE NEITHER MENTOR GRAPHICS NOR ITS LICENSORS MAKE ANY OTHER WARRANTIES EXPRESS IMPLIED OR STATUTORY WITH RESPECT TO SOFTWARE OR OTHER MATERIAL PROVIDED UNDER THIS AGREEMENT MENTOR GRAPHICS AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND NON INFRINGEMENT OF INTELLECTUAL PROPERTY LIMITATION OF LIABILITY EXCEPT WHERE THIS EXCLUSION OR RESTRICTION OF LIABILITY WOULD BE VOID OR INEFFECTIVE UNDER APPLICABLE LAW IN NO EVENT SHALL MENTOR GRAPHICS OR ITS LICENSORS BE LIABLE FOR INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES INCLUDING LOST PROFITS OR SAVINGS WHETHER BASED ON CONTRACT TORT OR ANY OTHER LEGAL THEORY EVEN IF MENTOR GRAPHICS OR ITS LICENSORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES IN NO EVENT SHALL MENTOR GRAPHICS OR ITS LICENSORS LIABILITY UNDER THIS AGREEMENT EXCEED THE AMOUNT PAID BY YOU FOR THE SOFTWARE OR SERVICE GIVING RISE TO THE CLAIM IN THE CASE WHERE NO AMOUNT WAS PAID MENTOR GRAPHICS AND ITS LICENSORS SHALL HAVE NO LIABILITY FOR ANY DAMAGES WHATSOEVER LIFE ENDANGERING ACTIVITIES NEITHER MENTOR GRAPHICS NOR ITS LICENSORS SHALL BE LIABLE FOR ANY DAMAGES RESULTING FROM OR IN CONNE
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51. Execute the lesson DO file a Type do gold sim do at the ModelSim gt prompt The DO file does the following e Creates and maps the work library Compiles the Verilog and VHDL files e Runsthe simulation and saves the results to a dataset named gold wlf Quits the simulation Feel free to open the DO file and look at its contents Creating the reference dataset T 149 ModelSim SE Tutorial T 150 Lesson 13 Waveform Compare Creating the test dataset The test dataset is the w f file that will be compared against the reference dataset Like the reference dataset the test dataset can be a saved dataset the current simulation dataset or any part of the current simulation dataset To simplify matters you will create the test dataset from the simulation you just ran However you will edit the testbench to create differences between the two runs Verilog Editthe testbench a Select File gt Open and open fest sm v b Scroll to line 122 which looks like this posedge clk wt wd h10 haa c Change the data pattern aa to ab posedge clk wt wd hl10 hab d Select File Save to save the file 2 Compile the revised file and rerun the simulation a Type do sec sim do at the ModelSim gt prompt The DO file does the following e Re compiles the testbench e Adds waves to the Wave window e Runs the simulation ModelSim SE Tutorial VHDL Editthe testbench a b d a Select F
52. ModelSim GUI a CEN EC E 1 Open a Memory instance M am tb sprami mem 0 4095 4036 a Select View Debug Windows Memory M ram tb spram2 mem 0 2047 2048 7 M ram tb spram3 mem 0 65535 65536 32 The Memories tab opens in the Workspace pane Figure 78 and lists the a am_tb spram4 mem 0 3 4 16 memories in the current design context ram tb with the range depth M ram_tb dpram1 mem 0 15 16 9 and width of each memory b VHDL The radix for enumerated types is Symbolic To change the radix to binary for the purposes of this lesson type the following command at the vsim prompt VSIM gt radix bin EB Memories iL c Double click the ram_tb spraml mem instance in the memories list to view its contents Figure 79 The mem tab in the MDI pane shows instance A mem tab is created in the MDI frame to display the memory contents ram_tb spram1 mem The data are all X 0 in VHDL since you have not yet simulated the design The first column blue hex characters lists the addresses Figure ram_tb spraml mem F x 79 and the remaining columns show the data values 00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX B d Double click instance ram tb spram2 mem in the Memories tab of the 00000006 xxxxxxxx XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0000000c xxxxxxxx XXXXXXxX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Workspace 00000012 xxxxxxxx XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX X
53. NI with the correct assignment immediately below line 65 that will hold we n high through both states of the refresh cycle ModelSim SE Tutorial Display cover directives in count mode You can change the functional coverage waveform so it displays in a decimal integer format the count mode 1 Right click a functional coverage waveform and select Cover Directive View gt Count Mode Figure 129 The cover directives count mode can be useful for gauging the effectiveness of stimulus over time If all cover directive counts are static for a long period of time it may be that the stimulus is acting in a wasteful manner and can be improved Display cover directives in count mode T 143 Figure 129 Display a cover directive in count mode wave default File Edit View Insert Format Tools Window QQQhx alpha cover 1 alpha cover 4 2 alpha clk 4 1 alpha a 4 0 alpha b 50 ns to 1035 ns Now 1 us Delta 2 ModelSim SE Tutorial T 144 Lesson 12 Debugging with PSL assertions Repo rting functional coverage statistics Figure 130 Create a text file of the functional coverage Save an ASCII file of the functional coverage statistics k Functional coverage report E xl Report on 1 Select Tools Functional Coverage Reports Main window to open the EX Functional coverage report dialog Figure 130 C Specific instance Instance Name sim alpha Browse 2 Selectth
54. No Design Loaded lt No Conte Project Library xt ModelSim SE Tutorial T 40 Lesson 3 ModelSim projects Lesson wrap up This concludes this lesson Before continuing you need to end the current simulation and close the current project 1 Select Simulate End Simulation Click Yes 2 Select the Project tab in the Main window Workspace 3 Right click the test project to open a context popup menu and select Close Project If you do not close the project it will open automatically the next time you start ModelSim ModelSim SE Tutorial Figure 28 Transcript shows options used for Simulation Configuration HA Transcript project open C 6 0 Tutorial examples test Loading project test ModelSim gt wm title ModelSim Compile of tcounter y was successful Compile of counter v was successful amp I CQ with n vsim hazards t ps work test counter vsim hazards t ps work test counter j Ua Wo 5 OLI Loading work cd unter command line switches Lesson 4 Working with multiple libraries Topics The following topics are covered in this lesson Introduction Related reading Creating the resource library Creating the project Linking to the resource library Permanently mapping resource libraries Lesson wrap up T 42 T 42 T 43 T 45 T 46 T 49 T 50 T 41 ModelSim SE Tutorial T 42 Lesson 4 Working with multiple li
55. Properties c Change the Data Radix to Hexadecimal d Select Words per line and enter 2 e Click OK 2 Initialize a range of memory addresses from a fill pattern a Right click in the data column of ram_tb dpraml mem contents pane and select Change to open the Change Memory dialog Figure 92 b Click the Addresses radio button and enter the start address as 0x00000006 and the end address as 0x00000009 The Ox hex notation is optional c Select Random as the Fill Type d Enter 0 as the Fill Data setting the seed for the Random pattern e Click OK The data in the specified range are replaced with a generated random fill pattern Figure 93 Interactive debugging commands Figure 91 Original memory contents BS ram tb dprami mem 00000000 06 03 00000002 7a 1b 00000004 00000006 1e 1f 00000008 20 21 0000000a 0000000c 24 25 0000000e 26 27 b ihram tb v Elmem T 109 Figure 92 Changing memory contents for a range of addresses Change Memory x Instance Name Aram tbidpram mem Address Range CAI 4 Addresses E End 0x00000009 Start 0x00000006 Fill C Value Increment C Decrement Random Fill Data 0 Skip 0 word s OK Cancel Apply Figure 93 Random contents of a range of addresses BE9S ram tb dprami mem 00000000 06 03 00000002 7a 1b 00000004 1c 1d 00000006
56. Sim Advanced Verification and Debugging SE Tutorial Version 6 0b Published November 15 2004 T 2 This document is for information and instruction purposes Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice and the reader should in all cases consult Mentor Graphics to determine whether any changes have been made The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in written agreements between Mentor Graphics and its customers No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL INDIRECT SPECIAL OR CONSEQUENTIAL DAMAGES WHATSOEVER INCLUDING BUT NOT LIMITED TO LOST PROFITS ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THEINFORMATION CONTAINED IN IT EVEN IF MENTOR GRAPHICS CORPORATION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES RESTRICTED RIGHTS LEGEND 03 97 U S Government Restricted Rights The SOFTWARE and documentation have been developed entirely at private expense and are commercial computer software provided with
57. The design expands to show the source of the unknown Figure 75 In this case there is a HiZ U in the VHDL version on input signal test in and a 0 on input signal rw bar rw in the VHDL version so output signal test2 resolves to an unknown Scroll to the bottom of the Wave window and you will see that all of the signals contributing to the unknown value have been added 3 Clear the Dataflow window before continuing Tracing an X unknown T 95 Figure 74 A signal with unknown values wave default File Edit View Insert Format Tools Window SHS eea no ex top p clk top p rdy 4top p addr top p nw top p stib top p data 0000000000000000 top p addr r 00000000 ji top p data_r 2222222222222222 top p rw r top p strb_r top p verbose top p t_out top p t set 4 Jjop p rw out sim top p t_out 8 2785 ns db top p test SEX Figure 75 ChaseX identifies the cause of the unknown on f out igi xd File Edit View Navigate Trace Tools Window Sik ad X B3 I amp O 2 A ke HILL AMA a Bb mi RAND T NETTE BUFHE e test b bl bl testin ML St E 4 top p t_out top p tes 4 hende 2785 ns gt 4 Kl Cw iur Extended mode enabled Keep 1 top p test2 P ModelSim SE Tutorial T 96 Lesson 8 Debugging with the Dataflow window Displaying hierarchy in the Dataflow win
58. XXXXXXX This creates a new tab in the MDI frame called mem 1 that contains the 00000018 xxxxxxxx XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 2 0000001e xxxxxxxx XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX addresses and data for the spram2 instance Each time you double click DOUUDDSN Xeuxxckx IXGXZXXX XXXXXiXX XXXXZXXX XXXXXXXX XXXXZXXX a new memory instance in the Workspace a new tab is created for that 0000002a xxxxxxxx XXXXxXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX instance in the MDI frame 00000030 xxxxxxxxX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00000036 xxxxxxxx XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0000003c xxxxxXxx XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00000042 xxxxxXxx XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ARNAR A a coerce TE IRI IT ECCLE me se dunes au ciao ju 2e an on ai au an 20 II TORODIIIBIECIIIII 00000048 xxxxxxxx XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ModelSim SE Tutorial Simulate the design a Click the run all icon in the Main window b Click the mem tab of the MDI frame to bring the ram_tb spram1 mem instance to the foreground Figure 80 VHDL In the Transcript pane you will see NUMERIC STD warnings that can be ignored and an assertion failure that is functioning to stop the simulation The simulation itself has not failed Let s change the address radix and the number of words per line for instance ram_tb spraml mem a Right click anywhere in the Memory C
59. _deasserts asset check refresh assetl refresh rate assert_check_write asset check read TIIIIT ertions A HOC vinane u amp zm Pass Faiure Coun Pass Count tb cntrl a 6n E enabled ELA b ontil assert_reftesh_rate disabled 1 EKA tb cntr assert check write enabled disabled D 1 EKA tb cntil assert check read enabled enabled 0 0 Debugging the assertion failure 1 View the source code of the failed assertion Verilog The current line arrow points to the failed assertion on line 24 of the dram cntrl psl file Figure 125 This assertion consists of checking the check refresh property which is defined on lines 20 22 The property states that when the refresh signal is active then we will wait until the memory controller state goes to IDLE The longest a read or write should take is 14 cycles If the controller is already IDLE then the wait is 0 cycles Once the controller is in IDLE state then the refresh sequence should start in the next cycle The refresh sequence second line of the property is defined on line 18 The key part of the refresh protocol is that we_n must be held high write enable not active for the entire refresh cycle VHDL The current line arrow points to the failed assertion on line 24 of the dram_cntrl psl file The refresh sequence second line of the property is defined on line 20 2 Check the Wave window to see if we n was held high through both REF and
60. a 2 Simulator 2004 06 Jun 16 2004 1 Select Simulate End Simulation Click Yes Platform win32 Calltree profile generated Thu Jun 17 17 25 07 2004 Number of samples 13795 Net memory allocated 73714 Number of samples in user code 1993 14 Cutoff percentage 2 PERFORMANCE MEMOF Name Under raw In raw Under In 5Parent Under b In b nct 1993 t 14 4 0 0 73714 692 6 sm v 67 661 329 4 8 2 4 33 0 t test sm v 86 308 303 2 2 2 2 15 0 beh sram v 33 17 17 0 1 0 1 1 4400 4400 calltree rptf ModelSim SE Tutorial T 122 Lesson 10 Analyzing performance with the Profiler ModelSim SE Tutorial Lesson 11 Simulating with Code Coverage Topics The following topics are covered in this lesson Introduction Lx x 3 Design files for this lesson Related reading Compiling the design Loading and running the design Viewing statistics in the Main window Viewing statistics in the Source window Viewing toggle statistics in the Objects pane Excluding lines and files from coverage statistics Creating Code Coverage reports Lesson wrap up gt Note The functionality described in this tutorial requires a coverage license feature in your ModelSim license file Please contact your Mentor Graphics sales representative if you currently do not have such a feature T 124 T 124 T 124 T 125 T 126 T 127 T 129 T 131 T 132 T 132 T 134 T 123 ModelSim SE Tutorial T 124
61. ad a Scroll to line 31 and click on the line number A red ball appears next to the line Figure 10 indicating that a breakpoint has been set Disable enable and delete the breakpoint a Click the red ball to disable the breakpoint It will become a black circle b Click the black circle to re enable the breakpoint It will become a red ball c Click the red ball with your right mouse button and select Remove Breakpoint 31 d Click on line number 31 again to re create the breakpoint Restart the simulation a Click the Restart icon to reload the design elements and reset the simulation time to zero The Restart dialog that appears gives you options on what to retain during the restart Figure 11 b Click Restart in the Restart dialog Setting breakpoints and stepping in the Source window T 27 Figure 10 A breakpoint in the Source window C 6 0 Tutorial examples counter v 22 for i 4 b0 carry 4 bl 66 i lt 7 i it 4 1 4 23 begin 24 increment i val i carry 2s carry val i amp carry 26 end 2 end 28 endfunction 29 30 always posedge clk or posedge reset 319 if reset 32 count ftpd reset to count S h00 33 else 34 count lt ftpd clk to count increment count 35 gt PT 2 tcounter v counter v Figure 11 The Restart dialog D lt Restart eles Keep v List Format v Wave Format v Breakpoints v Logged Signals v Virtual Definitions v Assertions and Funct
62. age enabled ModelSim adds several columns to the Files and sim tabs in the Workspace Figure 109 ModelSim also displays three Code Coverage panes in the Main window Figure 110 Missed Coverage Displays the selected file s un executed statements branches conditions and expressions and signals that have not toggled Instance Coverage Displays statement branch condition expression and toggle coverage statistics for each instance in a flat non hierarchical view Details Shows details of missed coverage such as truth tables or toggle details Another coverage related pane is the Current Exclusions pane Select View gt Code Coverage gt Current Exclusions to display that pane Current Exclusions Lists all files and lines that are excluded from coverage statistics see Excluding lines and files from coverage statistics T 132 for more information These panes can be re sized rearranged and undocked to make the data more easily viewable To resize a pane click and drag on the top or bottom border To move a pane click and drag on the double line to the right of the pane name To undock a pane you can select it then drag it out of the Main window or you can click the Dock Undock Pane button in the header bar top right To redock the pane click the Dock Undock Pane button again We will look at these panes more closely in the next exercise For complete details on each pane see Code coverage panes GR
63. ailures Action section select Break This causes the simulation to break stop on any failed assertion e Click the OK button to accept your selections and close the dialog Using assertions to speed debugging T 139 Figure 122 Change assertions dialog M Change assertions m Change on Specific instance Instance Name sim tb I Recursive All assertions Failures Passes Assertions Assertions Enable C Enable C Disable Disable m Logging Logging On On C of C Off Limit Limit Limited Limited a Times a Times C Unlimited C Unlimited Action C Continue Break Exit OK Cancel Apply ModelSim SE Tutorial T 140 Lesson 12 Debugging with PSL assertions 4 Add assertions and cover directives to the Wave window Select the Assertions pane if necessary b Select Add Wave Assertions in Design Scroll to the bottom of the Wave window and you will see the assertions denoted by magenta triangles c Select View gt Debug Windows gt Functional Coverage Main window to see cover directives in the Functional Coverage window d Select the Functional Coverage pane e Select Add Wave Functional Coverages in Design Scroll to the bottom of the Wave window and you will see the cover directives denoted by magenta arrowheads 5 Runthe simulation a Typerun all at the VSIM gt prompt Veri
64. al 5j amp Q Be 3 jtop p test top p stb Outputs top p t out eo 2820 ns 2785 ns 2 al KI SST ES Extended mode enabled Keep 1 ftop pAgNANDS 44 2 ModelSim SE Tutorial T 94 Lesson 8 Debugging with the Dataflow window d Select Trace Trace next event to trace the first contributing event Figure 72 Cursor in wave viewer marking last event ModelSim adds a cursor marking the last event the transition of the strobe to 0 at 2745 ns which caused the output of 1 on t out Figure 72 a uad xoa Xs IR ta Fe QQ Be 3 e Select Trace gt Trace next event two more times f Select Trace Trace event set The dataflow pane sprouts to the preceding process and shows the input driver of signal strb Figure 73 Notice too that the wave viewer now shows the input and output signals of the newly selected process You can continue tracing events through the design in this manner select Trace next event until you get to a transition of interest in the wave viewer and then select Trace event set to update the dataflow pane Figure 73 Tracing the event set fez aatto MIT File Edit View Navigate Trace Tools Window SKAH 3 8S amp 2 A he 3x LE E218 Bb nj 3 Select File Close to close the Dataflow window NAND 44 t out test strbj 4 Jton n sth 2820 ns 2665 ns k Hj Kl RS
65. and copy all files from lt install_dir gt examples profiler verilog to the new directory If you have a VHDL license copy the files in lt install_dir gt examples profiler vhdl instead Start ModelSim and change to the exercise directory If you just finished the previous lesson ModelSim should already be running If not start ModelSim a Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows If the Welcome to ModelSim dialog appears click Close b Select File gt Change Directory and change to the directory you created in step 1 Create the work library a Type vlib work at the ModelSim gt prompt Compile the design files a Verilog Type vlog test sm v sm seq v sm v beh sram v at the ModelSim gt prompt VHDL Type vcom 93 sm vhd sm seq vhd sm sram vhd test sm vhd at the ModelSim prompt Load the design unit with memory allocation profiling enabled a Type vsim test sm at the ModelSim gt prompt Compiling and loading the design T 115 ModelSim SE Tutorial T 116 Lesson 10 Analyzing performance with the Profiler Ru nni ng the sim u ation Figure 97 Note the run time reported in the Transcript Transcript Throughout this lesson you will run the simulation via a DO file DO files are macros you create that automatically run several ModelSim commands The DO file in this lesson uses the seconds Tcl command to time each simulation run Feel free to open the DO file and look
66. are written in HDL The pathnames to the files are as follows SystemC install dir modeltech examples systemc sc basic SystemC Verilog install dir modeltech examples systemc sc vlog SystemC VHDL install dir modeltech examples systemc sc vhdl This lesson uses the SystemC Verilog version of the ringbuf design in the examples If you have a VHDL license use the VHDL version instead There is also a mixed version of the design but the instructions here do not account for the slight differences in that version Related reading ModelSim User s Manual Chapter 6 SystemC simulation UM 159 Chapter 7 Mixed language simulation UM 187 Chapter 16 C Debug UM 399 ModelSim Command Reference sccom command CR 254 ModelSim SE Tutorial Setting up the environment T 53 Setting up the environment SystemC is a licensed feature You need the systemc license feature in your ModelSim license file to simulate SystemC designs Please contact your Mentor Graphics sales representatives if you currently do not have such a feature The table below shows the supported operating systems for SystemC and the corresponding required versions of a C compiler Platform Supported compiler versions HP UX 11 0 or later aCC 3 45 with associated patches RedHat Linux 7 2 and 7 3 gcc 3 2 3 RedHat Linux Enterprise version 2 1 SunOS 5 6 or later gcc 3 2 Windows NT and other NT based Minimalist GNU for Window
67. at its contents 23999431 illegal op received 23999475 outof 000000cf 23999815 outof O00000aa 23999875 outof OO0000bb 23999935 outof 000000cc 23999995 outof 000000cd Profiling paused 2513 samples taken 72 in user code H H H H H H 1 Enable the statistical sampling profiler a Select Tools gt Profile gt Performance or simply click the P Performance Profiling icon in the toolbar a This must be done prior to running the simulation ModelSim is now ready to collect performance data and memory allocation data when the simulation is run 2 Run the simulation via the DO file Figure 98 The Profile window a Typedo profile run do at the VSIM gt prompt Profile A A The status bar at the bottom of the Main window reports the number of rame Undedraw Intaw Unde Int Profile Samples collected T Tt Close Make note of the run time reported in the Transcript Figure 97 You test sm v 99 will use it later to compare how much you have increased simulation BIMBI speed by tweaking the design Your times may differ from those shown ere here due to differing system configurations OLAI OEN test_sm v 86 test sm v 130 Tcl DoOneEvent a Select View Profile View Tcl DeleteTimerHandler Tcl Flush 3 Display the statistical performance data in the Profile pane The Profile pane displays three tab selectable views of the profile data Ranked Call Tree a
68. ayed whenever there are multiple statements on the line Hover 23 task nop the mouse pointer over a statement to see the count for that statement 1562 24 EEE eee op wor 25 endtask f Select Tools Code Coverage Hide coverage numbers to return to 26 2 the ctrl op Icon display 28 task ctrl 29 input 7 0 data 30 begin X 31 5 into 4 b0001 28 b0 ctrl X 32 8 tposedge clk X 33 f5 into data 34 end X 35 endtask Ae T EYE NET zj SE E E El Ihltest_sm v E ModelSim SE Tutorial Viewing toggle statistics in the Objects pane T 131 Viewing togg le statistics in the Ob Jects Figure 118 Toggle coverage columns in the Source window pane Objects 1H 0L HToggled Toggle coverage counts each time a logic node transitions from one state to Le m s e another Earlier in the lesson you enabled two state toggle coverage 0 gt 1 and 1 poppe rige E gt 0 with the cover t argument Alternatively you can enable six state toggle ERES n 1 1 coverage using the cover x argument See Toggle coverage UM 343 for more 12525 12499 2 9 information 395271 85922 2 8 0 15631 15624 G3 QJ GO N oO e 1 View toggle data in the Objects pane of the Main window Select test sm in the sim tab of the Main window 100 100 b Ifthe Objects pane isn t open already select View gt Debug Windows gt 100 100 Objects Scroll to the right and you will see the various tog
69. been executed zero hits indicates a line that has been excluded from code coverage statistics green E red XT or Xp indicates that a true or false branch respectively of a conditional statement has not been executed EE T 129 1b 46 0 Tutorial ex Mh ha Sh hn Ta Yo Ta Ba lt n J mples Ff repeat 40000 begin ff posedge posedge posedge posedge posedge posedge posedge posedge posedge posedge posedge posedge clk clk clk clk clk clk clk clk clk clk clk clk fe fe end 100 stop end for loop 0 loop lt 2000 ctrl h5 wt vd hl0 haa wt wd h20 hbb wt blk h30 hcc rd vwd hl0 rd wdi h20 rd vd h30 rd vdi h31 rd wdi h32 rd vdi h33 ill op nop ModelSim SE Tutorial T 130 Lesson 11 Simulating with Code Coverage d Hover your mouse pointer over a line of code with a green checkmark Figure 117 Coverage numbers shown by hovering the mouse pointer The icons change to numbers that indicate how many times the statements and branches in that line were executed Figure 117 In this case line 24 was executed 1562 times 18 reg rst clk 19 ire 31 0 ire dat e Select Tools gt Code Coverage gt Show coverage numbers So ee l ee The icons are replaced by execution counts on every line An ellipsis nr es il 22 nop is displ
70. braries Introduction In this lesson you will practice working with multiple libraries As discussed in Lesson 1 ModelSim conceptual overview you might have multiple libraries to organize your design to access IP from a third party source or to share common parts between simulations You will start the lesson by creating a resource library that contains the counter design unit Next you will create a project and compile the testbench into it Finally you will link to the library containing the counter and then run the simulation Design files for this lesson The sample design for this lesson is a simple 8 bit binary up counter with an associated testbench The pathnames are as follows Verilog install dir modeltech examples counter v and tcounter v VHDL install dir modeltech examples counter vhd and tcounter vhd This lesson uses the Verilog files tcounter v and counter v in the examples If you have a VHDL license use tcounter vhd and counter vhd instead Related reading ModelSim User s Manual 3 Design libraries UM 57 ModelSim SE Tutorial Creating the resource library 1 Create a directory for the resource library Create a new directory called resource_library Copy counter v from lt install_dir gt modeltech examples to the new directory Create a directory for the testbench Create a new directory called testbench that will hold the testbench and project files Copy tcounter v from lt
71. breach of this Agreement and may at Mentor Graphics option result in the immediate termination of the Agreement and licenses granted under this Agreement The terms of this Agreement including without limitation the licensing and assignment provisions shall be binding upon your heirs successors in interest and assigns The provisions of this section 4 shall survive the termination or expiration of this Agreement 5 LIMITED WARRANTY 5 1 Mentor Graphics warrants that during the warranty period Software when properly installed will substantially conform to the functional specifications set forth in the applicable user manual Mentor Graphics does not warrant that Software will meet your requirements or that operation of Software will be uninterrupted or error free The warranty period is 90 days starting on the 15th day after delivery or upon installation whichever first occurs You must notify Mentor Graphics in writing of any nonconformity within the warranty period This warranty shall not be valid if Software has been subject to misuse unauthorized modification or installation MENTOR GRAPHICS ENTIRE LIABILITY AND YOUR EXCLUSIVE REMEDY SHALL BE AT MENTOR GRAPHICS OPTION EITHER A REFUND OF THE PRICE PAID UPON RETURN OF SOFTWARE TO MENTOR GRAPHICS OR B MODIFICATION OR REPLACEMENT OF SOFTWARE THAT DOES NOT MEET THIS LIMITED WARRANTY PROVIDED YOU HAVE OTHERWISE COMPLIED WITH THIS AGREEMENT MENTOR GRAPHICS MAKES NO WARRANTIES WITH RESPE
72. ccom link 1 Create a new directory and copy the tutorial files into it Start by creating a new directory for this exercise in case other users will be working with these lessons Create the directory then copy all files from lt install_dir gt modeltech examples systemc sc_vlog into the new directory If you have a VHDL license copy the files in lt install_dir gt modeltech examples systemc sc_vhdl instead Start ModelSim and change to the exercise directory If you just finished the previous lesson ModelSim should already be running If not start ModelSim a Type vsim at a command shell prompt If the Welcome to ModelSim dialog appears click Close b Select File gt Change Directory and change to the directory you created in step 1 Set the working library a Type vlib work in the ModelSim Transcript window to create the working library Compile the design a Verilog Type vlog v in the ModelSim Transcript window to compile all Verilog source files VHDL Type vcom 93 vhd in the ModelSim Transcript window to compile all VHDL source files Mixed SystemC and HDL example T 57 ModelSim SE Tutorial T 58 Lesson 5 Simulating designs with SystemC Upon successful compilation the following message Verilog version shown appears in the Transcript window Model Technology ModelSim vlog compiler Compiling module control Compiling module retrieve Compiling module ringbuf Compiling
73. counter os vi le P y p y P to see what s available You can consult the ModelSim User s Manual to Optimization get a description of each option Enable optimization Optimization Options b Type counter in the Simulation Configuration Name field OK Cancel c Select HDL from the Place in Folder drop down d Click the icon next to the work library and select test counter Figure 27 A Similation Comme uranen the Project D e Click the Resolution drop down and select ps ModelSim f File Edit View Format Compile Simulate Add Tools Window Help f For Verilog click the Verilog tab and check Enable Hazard Checking g Click OK Transcript The Project tab now shows a Simulation Configuration named counter R ITS LICENSORS Figure 27 8 8 Folder project open C 6 0 Tutorial exa Folder mples test 2 Load the Simulation Configuration countetv yf Verilog vede digi suh odelSim wm title ModelSim a Double click the counter Simulation Configuration in the Project tab tcounter v Verlog Compile of tcounter v was succ counter Simulation l cessful Compile of counter v was succe ssful 2 compiles 0 failed with no error In the Transcript pane of the Main window the vsim the ModelSim simulator invocation shows the hazards and t ps switches Figure 28 These are the command line equivalents of the options you specified in the Simulate dialog ModelSim gt Project test
74. ctory and copy all files from lt install_dir gt modeltech examples coverage verilog to the new directory If you have a VHDL license copy the files in lt install_dir gt modeltech examples coverage vhdl instead Start ModelSim and change to the exercise directory If you just finished the previous lesson ModelSim should already be running If not start ModelSim a Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows If the Welcome to ModelSim dialog appears click Close b Select File gt Change Directory and change to the directory you created in step 1 Create the working library a Type vlib work at the ModelSim prompt Compile the design files a For Verilog Type vlog cover bct sm v sm seq v beh sram v test sm v at the ModelSim prompt For VHDL Type vcom cover bct sm vhd sm seq vhd sm sram vhd test sm vhd at the ModelSim prompt The cover bct argument instructs ModelSim that you want branch condition and toggle coverage statistics statement coverage is included by default See Enabling code coverage UM 337 for more information on the available coverage types Compiling the design T 125 ModelSim SE Tutorial T 126 Lesson 11 Simulating with Code Coverage Loading and running the design 1 Load the design a Type vsim coverage test sm at the ModelSim gt prompt 2 Run the simulation b Type run 1 ms at the VSIM gt prompt When you load a design with Code Cover
75. d The view expands to display the processes that are connected to strb Figure 69 b Select signal test on process NAND 44 labeled line 62 in the VHDL version and click the Expand net to all drivers icon Notice that after the display expands the signal line for strb is highlighted in green This highlighting indicates the path you have traversed in the design c Select signal oen on process ALWAYS 149 labeled line 75 in the VHDL version and click the Expand net to all readers icon Continue exploring if you wish When you are done click the Erase All icon p 8 a ModelSim SE Tutorial Figure 68 A signal in the Dataflow window Tn Lex File Edit View Navigate Trace Tools Window SiM api BBQ M foe 5 Ye 3e 3 AMA amp i ni RASSIGNIM 9i stb gt Extended mode enabled Keep 1 Aop p strb gt Figure 69 Expanding the view to display connected processes inix File Edit View Navigate Trace Tools Window amp i x m4 BEN Ai he 9 36x E AAA Ib nj ASSIGNI est NAND 44 RASSIGNI 941 ou BSALWAYSIH 49 strb S EJ elk M ds oen Ti a prdy_r p wen paddr gt Extended mode enabled Keep 1 Atop p strb A Tracing events Another useful debugging feature is tracing events that contribute to an unexpected output value Using the Dataflow window s embedded wave viewer you can trace backward from a transition to see which
76. d then recompiles it after compiling the rest of the files It continues in this manner until all files compile successfully or until a file s can t be compiled for reasons other than dependency Alternatively you can select a file and use the Move Up and Move Down buttons to put the files in the correct order Click OK to close the Compile Order dialog Creating a new project T 35 Figure 17 Newly added project files display a for status x ModelSim File Edit View Format Compile Simulate Add Tools Window Help amp s Contains em f UE PS 551 i 3 EL SH ame vw iz Workspace Ha x rName Status Type Order Mi t 7 PROPERTY OF MEN 06 TOR GRAPHICS CORPORATI Verilog 1 ON OR ITS LICENSORS Verilog 0 05 ft ModelSim wm title ModelSim counter v tcounter v D cd C 6 0 Tutorial examples reading modelsim ini Loading project test 4 Project Library ModelSim Project test No Design Loaded No Context Figure 18 The Compile Order dialog box Compile Order xj Current Order n counter vhd tcounter vhd move up down buttons Auto Generate ModelSim SE Tutorial T 36 Lesson 3 ModelSim projects Compiling and loading a design Compile the files a Right click anywhere in the Project tab and select Compile Compile All from the pop up menu ModelSim
77. debug the error you might first examine the simulation waveforms and look for all writes to the memory location You might also check the data on the bus and the actual memory contents at the location after each write If that didn t identify the problem you might then check all refresh cycles to determine if a refresh corrupted the memory location Quite possibly all of these debugging activities would be required depending on one s skill or luck in determining the most likely cause of the error Any way you look at it it s a tedious exercise 3 Endthe simulation a Type quit sim at the VSIM prompt to end this simulation ModelSim SE Tutorial Using assertions to speed debugging To show how assertions help with debugging we ll reload the design with assertions 1 Reload the design a Type vsim tb at the ModelSim gt prompt 2 Execute the lesson DO file a Typedo sim do at the ModelSim gt prompt The DO file does the following e Opens the Assertions pane and displays all assertions e Opens a Source window e Adds signals to the Wave window Feel free to open the DO file and look at its contents 3 Set all assertions to Break on Failures a Make sure the Assertions pane is selected a Select Edit Advanced Change Main window This opens the Change assertions dialog Figure 122 b Inthe Change on section select All assertions c Inthe Failures Assertions section select Enable if necessary d Inthe F
78. delSim SE Tutorial T 72 Lesson 6 Viewing simulations in the Wave window 2 Lock cursor B a Right click cursor B in the cursor pane and select Lock B The cursor color changes to red and you can no longer drag the cursor Figure 54 3 Delete cursor B a Right click cursor B and select Delete B Figure 54 A locked cursor in the Wave window ELTE HEN File Edit pom Format Tools Window CRETE loj xl SPIRI SERE Ry a Q coe ii i s ee 4 test_counter clk 1 4 test_counter reset 0 E4 test counter count p Ife qe pp EE mE E 0 1 Saving the window format If you close the Wave window any configurations you made to the window e g signals added cursors set etc are discarded However you can use the Save Format command to capture the current Wave window display and signal preferences to a DO file You open the DO file later to recreate the Wave window as it appeared when the file was created Format files are design specific use them only with the design you were simulating when they were created 1 Save a format file a Select File gt Save gt Format b Leave the file name set to wave do and click Save c Close the Wave window 2 Load a format file a In the Main window select View gt Debug Windows gt Wave All signals and cursor s that you had set are gone b Inthe Wave window select File gt Open gt Format c Select wave do and click Open Mod
79. duced by almost 50 Transcript 23336231 illegal op received 23996871 illegal op received 23897511 illegal op received 23338151 illegal op received 23998791 illegal op received 23999431 illegal op received Profiling paused 1214 samples taken 43 in user code Figure 104 Source edit removes the performance bottleneck Profile EF sm v 73 4 Tcl Flush E Tcl DoOneEvent Tcl DeleteTimerHandler Tcl WaitFarEvent test sm v 82 beh sram v 22 test sm v 136 test sm v 103 Ranked Call Tree Structural ModelSim SE Tutorial T 120 Lesson 10 Analyzing performance with the Profiler Filtering and saving the data As a last step you will filter out lines that take less than 296 of the simulation time using the Profiler toolbar and then save the report data to a text file 1 Filter lines that take less than 2 of the simulation time a b c Make sure the Profile pane is selected Change the Under field to 2 Figure 105 Click the Refresh Profile Data button ModelSim filters the list to show only those lines that take 2 or more of the simulation time Figure 106 2 Save the report a b Click the save icon in the Profiler toolbar In the Profile Report dialog Figure 107 select the Call Tree Type In the Performance Memory data section select Default data collected Specify the Cutoff percent as 296 Select Write to file and type calltree rpt in the file name field
80. e AIl cover directives radio button Io anxie 3 Select None in the Filtering options f All cover directives 4 Select Include aggregated results and Include detailed results from the Filtering Contents Contents options 7 None M Include aggregated results 5 Select Write to File from the Other Options You can use the default C Zero coverage only M Include detailed results filename fcover report txt or rename the file C Range Include config info Above Percent 25 Include comments 6 Click OK to create the report T AE SR elow Percen 75 The new report will appear automatically in the Notepad viewer You can Below Percent view the report at any time by entering notepad fcover report txt at the command line Dther Options Use XML format JV Write to file Filename fcover_report txt Browse Append to existing file OK Cancel ModelSim SE Tutorial Lesson wrap up T 145 Lesson wrap up This concludes this lesson Before continuing we need to end the current simulation 1 Select Simulate gt End Simulation Click Yes ModelSim SE Tutorial T 146 Lesson 12 Debugging with PSL assertions ModelSim SE Tutorial Lesson 13 Waveform Compare Topics The following topics are covered in this lesson Introduction Design files for this lesson Related reading Creating the test dataset Verilog VHDL Comparing the simulation runs Viewing comparis
81. e Coverage T 123 Lesson 12 Debugging with PSL assertions 1 135 Lesson 13 Waveform Compare T 147 T 3 ModelSim SE Tutorial T 4 ModelSim SE Tutorial Introduction Topics The following topics are covered in this chapter Assumptions Where to find our documentation Technical support and updates Before you begin Example designs T 6 T 7 T 8 T 9 T 9 ModelSim SE Tutorial T 6 Introduction Assumptions We assume that you are familiar with the use of your operating system You should be familiar with the window management functions of your graphic interface either OpenWindows OSF Motif CDE KDE GNOME or Microsoft Windows 98 Me NT 2000 XP We also assume that you have a working knowledge of VHDL Verilog and or SystemC Although ModelSim is an excellent tool to use while learning HDL concepts and practices this document is not written to support that goal ModelSim SE Tutorial Where to find our documentation ModelSim documentation is available from our website at www model com support or in the following formats and locations Document Format How to get it ModelSim Installation amp Licensing Guide paper shipped with ModelSim PDF select Help Documentation also available from the Support page of our web site www model com ModelSim Quick Guide command and feature quick reference
82. e Edge icon Edit counter clk st 17 4 Edit counter reset The edge is deleted and c k now stays high until 400 ns Figure 63 4 Undo and redo an edit a Click the Wave Undo icon Ons to 675 ns Now Ons Delta 0 2 The deleted edge reappears b Click the Wave Redo icon The edge is deleted again You can undo and redo any number of editing operations except extending all waves and changing drive types Those two edits cannot be undone ModelSim SE Tutorial Saving and reusing the wave commands You can save the commands that ModelSim used to create the waveforms You can load this format file at a later time to re create the waves In this exercise we will save the commands quit and reload the simulation and then open the format file 1 Save the wave commands to a format file a Select File Close in the Wave window and you will be prompted to save the wave commands Click Yes Type waveedit do in the File name field and then click Save This saves a DO file named waveedit do to the current directory 2 Quitand then reload the simulation a In the Main window select Simulate End Simulation and click Yes to confirm you want to quit simulating Double click the counter design unit on the Library tab to reload the simulation 3 Open the format file a a b Select View Debug Windows Wave to open the Wave window In the Wave window select File Open Format Doubl
83. e Main window SystemC objects have a green S next to their names Figure 40 2 Observe window linkages Click on the Sim tab in the Workspace pane of the Main window b Select the clock instance in the sim tab Figure 41 The Locals and Objects windows update to show the associated SystemC or HDL objects 3 Addobjects to the Wave window a Right click test ringbuf in the sim tab and select Add gt Add to Wave ModelSim SE Tutorial Figure 39 test ringbuf design in ModelSim Osua teL AE Workspace Design unit type EH test_ringbuf test_ringbuf ScModule clock sc clock ScModule M rina INST ringbuf Module reset generator test_ringbuf ScMethod generate_data test_ringbuf ScMethod B compare data test ringbuf ScMethod print error test_ringbuf ScMethod print restore test ringbuf ScMethod zog x Active Processes lt Ready gt lt Ready gt lt Ready gt lt Ready gt Ready lt Ready gt HIMPLICIT WIRE outstrobe tt IMPLICIT WIRE oeenable t H IMPLICIT WIRE ramadrs 2 HASSIGNHES test ringbuf ri HIMPLICIT W IRE buffer t23 HASSIGNH33S test ringbuf ri ModelSim gt sccom link Model Technology ModelSim SE sccom 6 0 Beta 3 compiler 2004 07 Jul 9 2004 ModelSim gt vsim test ringbuf vsim test ringbuf Loading work systemc so Loading work test_ringbuf Loading work ringbuf
84. e Main window The Dataflow List and Wave windows will open as separate windows You may need to move or resize the windows to your liking Panes within the Main window can be undocked to stand alone 2 Add signals to the Wave window In the Workspace pane select the sim tab Right click test counter to open a popup context menu Select Add Add to Wave Figure 8 Three signals are added to the Wave window 3 Runthe simulation a Click the Run icon in the Main or Wave window toolbar The simulation runs for 100 ns the default simulation length and waves are drawn in the Wave window Type run 500 at the VSIM gt prompt in the Main window The simulation advances another 500 ns for a total of 600 ns Figure 9 Running the simulation T 25 Figure 8 Adding signals to the Wave window File Edit View Format Compile Simulate Add Tools Window Help Active Processes Ready HIMPLICIT wI Ready IMPLICIT wI Ready IMPLICIT Wi Ready INITIALHI1 Ready HINITIALH17 test counter dit View Declaration SIMPLIC View Instantiation 2 mmr BE ETSI INITIAL Copy Add to Dataflow D HINITIAL Find Add ta List D HINITIAL Ready HINITIALH24 Expand Selected Collapse Selected sim Expand All Collapse All Copyright Model Technology al Corporation company 2004 Al Transcript
85. e ModelSim prompt The DO file does the following e Creates the working library e Compiles the design files assertions and cover directives Feel free to open the DO file and look at its contents Compile the example design T 137 ModelSim SE Tutorial T 138 Lesson 12 Debugging with PSL assertions Load an d run with out asse rtio ns Figure 121 Transcript after running the simulation without assertions Transcript 1 Load the design without assertions Optimized design name is sim nopsl ModelSim gt vsim nopsl sim nopsl vsim nopsl sim nopsl Loading work tb fast Loading work dram control fast Loading work dram fast VSIM 5 run all Reset is working a Type vsim tb nopsl at the VSIM gt prompt The nopsl argument instructs the compiler to ignore PSL assertions 2 Run the simulation a Type run all at the VSIM gt prompt or click the Run All icon Verilog The simulation reports an error at 267400 ns and stops on line 266 of the dramcon_sim v module A ERROR at time 267400 Controller is not working data written 01 RK dataread 80 VHDL The simulation reports an error at 246800 ns and stops on line 135 of the dramcon_sim vhd entity H The ERROR message indicates that the controller is not working because Break at dame mv line 266 a value read from memory does not match the expected value Figure VSIM 6 gt 121 To
86. e click wave do to open the file The waves you created earlier in the lesson reappear If waves do not appear you probably did not load the counter design unit Saving and reusing the wave commands T 83 ModelSim SE Tutorial T 84 Lesson 7 Creating stimulus with Waveform Editor Exporting the created waveforms At this point you can run the simulation or you can export the created waveforms to one of four stimulus file formats You will run the simulation in a minute but first let s export the created waveforms so we can use them later in the lesson Export the created waveforms in an HDL testbench format a Inthe Wave window select File gt Export Waveform b Select Verilog Testbench or VHDL Testbench if you are using the VHDL sample files c Enter 1000 Figure 64 for End Time if necessary and click OK ModelSim creates a file named export v or export vhd in the current directory Later in the lesson we will compile and simulate the file 2 Exportthe created waveforms in an extended VCD format a Select File Export Waveform b Select EVCD File c Enter 1000 for End Time if necessary and click OK ModelSim creates an extended VCD file named export vcd We will import this file later in the lesson ModelSim SE Tutorial Figure 64 The Export Waveform dialog y Export Waveform E Xj Save As C Force File C EVCD File VHDL Testbench Verilog Testbench 1b Start Time End Time Time Unit 0
87. e clicking on any address in the OK EET Address column and entering 250 You can see the specified range of addresses overwritten with the new data Also Figure 90 Overwritten values in memory instance you can see the incrementing data beginning at address 251 Figure 90 Now before you leave this section go ahead and clear the instances already being ES ram_tb spram3 mem viewed 246 00000000000000000010010000011110 247 00000000000000000010010000011111 248 00000000000000000010010000100000 4 Right click somewhere in the mem 2 pane and select Close All 249 00000000000000000010010000100001 250 00000000000000000010010000100010 251 00000000000000000000000000000000 252 00000000000000000000000000000001 253 00000000000000000000000000000010 254 00000000000000000000000000000011 255 00000000000000000000000000000100 256 00000000000000000000000000000101 257 00000000000000000000000000000110 258 00000000000000000000000000000111 259 00000000000000000000000000001000 ncn mnannnnannnnnnnnnnnmnnmnmnnnmnnmnmnnnnmnm nnA1n NAM LEA ModelSim SE Tutorial Interactive debugging commands The memory panes can also be used interactively for a variety of debugging purposes The features described in this section are useful for this purpose 1 Open a memory instance and change its display characteristics a Double click instance ram tb dpram1 mem in the Memories tab b Right click in the memory contents pane and select
88. e selected file Figure 112 18 reg rst clk r s 5 13 wire 31 0 out wire dat b Select any entry in the Statement tab to display that line in the Source 20 wire 9 0 addr window 21 reg 31 0 loop 22 nop 23 task nop PA 24 5 into 4 b0000 28 h0 op wor X zs endtask 26 27 the ctrl op 28 task ctrl 29 input 7 0 data 30 begin X 31 5 into 4 b0001 28 b0 ctrl X 32 G posedge clk X 33 5 into data 34 end X 35 endtask 36 EX era OO EIN a OIRNE a OTE AN SPIO A ModelSim SE Tutorial T 128 Lesson 11 Simulating with Code Coverage 3 View statistics in the Details pane Figure 113 Details pane showing toggle coverage statistics a Select the Toggle tab in the Missed Coverage pane TET AM X If the Toggle tab isn t visible you can do one of two things 1 widen the Instance test sm pane by clicking and dragging on the pane border 2 if your mouse has Signal into a middle button click and drag the tabs with the middle mouse button Noda count g2 b Select any object in the Toggle tab to see details in the Details pane gt 0 76 Figure 113 1 46 Toggle Coverage 34 35 0 1 Coverage 57 1955 Full Coverage 67 19 The Instance Coverage pane displays coverage statistics for each instance in X Z Coverage 67 19 a flat non hierarchical view Figure 114 Select any instance in the Instance Coverage pane to see its source code displayed in the Source window 4 View in
89. e the examine command or view the value in the Objects window View the value and type of an sc signal a Typeshow at the CDBG prompt to display a list of all the objects in the design including their types Inspect the list to discover that the type for dataerror is boolean sc logic for VHDL and counter is integer Figure 45 b Typeexamine dataerror at the CDBG prompt The value returned is true 2 View the value of a SystemC variable a Typeexamine counter at the CDBG prompt to view the value of this variable The value returned is 1 Removing a breakpoint 1 Right click the breakpoint on the red sphere and select Remove Breakpoint ModelSim SE Tutorial Figure 42 An active breakpoint in a SystemC file iujddale MTVexamples sysc_tutorial sc_vlog test test_ringbuf h 143 ff 144 vi On every negedge of the clock compare actual and expected data 145 146 inline void test ringbuf compare data 147 1499 bool var dataerror newval actual read lexpected read 143 dataerror write var dataerror newval 150 151 if reset read 0 152 153 storage write 0 154 expected write 0 J 155 actual write 0 156 counter 157 FI J Figure 43 Simulation stopped at the breakpoint E Ju ddale MTl examples sysc tutorialisc vlog test test ringbuf h In 143 ff 144 ff On every negedge of the clock compare actual
90. eated waveform RTE RT TE File Edit View Insert Format Tools Window FLEE eB ay QQ Bx Specify the Clock Pattern attributes ModelSim SE Tutorial T 80 Lesson 7 Creating stimulus with Waveform Editor Editing waveforms in the Wave window F ge sn ThE Tonart Pulse dale s Insert Pulse E xj Waveform Editor gives you numerous commands for interactively editing waveforms e g invert mirror stretch edge cut paste etc You can access these Signal Name commands via the menus toolbar buttons or via keyboard and mouse shortcuts Edit counter teset You will try out several commands in this part of the exercise 3 S Duration Time Time Unit 1 Inserta pulse on signal reset 100 rod ns vi x Cancel Figure 60 Signal reset with an inserted pulse a Click the Edit Mode icon on the Wave window toolbar wave default b Click signal reset so it is selected File Edit View Insert Format Tools Window c Inthe waveform pane right click on signal reset and select Edit Wave Insert Pulse d Inthe Insert Pulse dialog enter 100 for duration and 100 for time Figure 59 and click OK Signal reset now goes high from 100 ns to 200 ns Figure 62 Now 0 ns to 1 us Now Ons Delta 0 S ModelSim SE Tutorial 2 Stretch an edge on signal clk Click signal clk on the transition at 350 ns b Select Edit gt Edit Wave gt Stretch Edge from the menu
91. ect Load to bring up the Load Memory dialog box Figure 87 The default Load Type is File Only Type data mem mem in the Filename field Click OK The addresses in instance ram tb spram3 mem are updated with the data from data mem mem Figure 88 Figure 87 Load Memory dialog box jy Load Memory x or UE Se Figure 88 Initialized memory from file and fill pattern Instance Name Initializing a memory T 107 ram_tb spram3 mem Load Type Address Range File Only All C Data Ony C Addresses in decimal C Both File and Data Start o End 65535 File Load File Format Verilog Hex Verilog Binary MTI Filename data mem mem m Data Load LUE Fil Data Value Ime C Increment C Decrement Skip C Random o word s 2b 1 mem mem 1 ram tb v mem 2 J 00000000000000000000000000101000 00000000000000000000000000101001 00000000000000000000000000101010 00000000000000000000000000101011 00000000000000000000000000101100 00000000000000000000000000101101 00000000000000000000000000101110 00000000000000000000000000101111 00000000000000000000000000110000 00000000000000000000000000110001 00000000000000000000000000110010 00000000000000000000000000110011 00000000000000000000000000110100 sl Iz ModelSim SE Tutorial T 108 Lesson 9 Viewing and initializing memories In this next step you will exper
92. elSim SE Tutorial Figure 136 Compare differences in the List window LEE ulnis File Edit View Tools Window psy deltay 30000 35000 100000 110000 115000 120000 130000 135000 140000 150000 151000 155000 160000 170000 171000 compare test_su into lt into E 0 00000000000000000000000000000000 00000000000000000000000000000000 ooooc 0 00100000000000000000000000000000 00100000000000000000000000000000 0000 0 00100000000000000000000000000000 00100000000000000000000000000000 0000 0 00100000000000000000000000000000 00100000000000000000000000000000 0000C 0 00000000000000000000000000010000 00000000000000000000000000010000 0000 0 00000000000000000000000000010000 00000000000000000000000000010000 0 00000000000000000000000000010000 00000000000000000000000000010000 0 0 0 1 0 00100000000000000000000000000000 00100000000000000000000000000000 0 00100000000000000000000000000000 00100000000000000000000000000000 0 00100000000000000000000000000000 00100000000000000000000000000000 0000 1 00100000000000000000000000000000 00100000000000000000000000000000 0000 SS Saving and reloading comparison data You can save comparison data for later viewing either in a text file or in files that can be reloaded into ModelSim To save comparison data so it can be reloaded into ModelSim you must save two files First you save the computed differences to one file next you save
93. elSim restores the window to its previous state d Close the Wave window when you are finished by selecting File gt Close Saving the window format T 73 ModelSim SE Tutorial T 74 Lesson 6 Viewing simulations in the Wave window Lesson wrap up This concludes this lesson Before continuing we need to end the current simulation 1 Select Simulate gt End Simulation Click Yes ModelSim SE Tutorial Lesson 7 Creating stimulus with Waveform Editor Topics The following topics are covered in this lesson Introduction Related reading Loading a design unit Creating waves with a wizard Editing waveforms in the Wave window Saving and reusing the wave commands Exporting the created waveforms Running the simulation Simulating with the testbench file Importing an EVCD file Lesson wrap up T 76 T 76 T 77 T 78 T 80 T 83 T 84 T 85 T 86 T 87 T 88 T 75 ModelSim SE Tutorial T 76 Lesson 7 Creating stimulus with Waveform Editor Introduction The Waveform Editor creates stimulus for your design via interactive manipulation of waveforms You can then run the simulation with these edited waveforms or export them to a stimulus file for later use In this lesson you will do the following Load the counter design unit without a testbench Create waves via a wizard Edit waves interactively in the Wave window Export the waves to an HDL testbench and extended VCD file Run t
94. elect Create Wave Figure 55 This opens the Create Pattern Wizard dialog where you specify the type of pattern Clock Repeater etc and a start and end time b The default pattern is Clock which is what we need so click Next Figure 56 ModelSim SE Tutorial Figure 55 Creating waves from the Objects pane Parameter tpd clk to count Parameter count x Reg Signal Declaration Insert Breakpoint Add to Wave id Add to List gt Log Signal d Toggle Coverage gt Force NoForce Clock 1a Figure 56 The Create Pattern Wizard Signal Name sim counter clk Start Time End Time Time Unit c Inthe second dialog of the wizard enter 0 for Initial Value leave everything else as is and click Finish Figure 57 A generated waveform appears in the Wave window Figure 58 Notice the small red dot on the waveform icon that denotes an editable wave 2 Create a second wave using the wizard a Right click signal reset in the Objects pane and select Create Wave b Select Constant for the pattern type and click Next c Enter 0 for the Value and click Finish A second generated waveform appears in the Wave window Creating waves with a wizard T 79 Figure 57 Specifying clock pattern attributes uJ sim counter clk lt Pattern clock gt b x m Clock Attributes Initial Value d ESSAN Clock Period Time Unit 100 s yi Duty Cycle 50 lt Previous Finish Cancel Figure 58 The cr
95. ent command line entry is vsim test ringbuf entered at the ModelSim gt prompt If necessary you may close the Locals Profile and Watch panes of the main window Please make sure the Objects and Active Processes windows are open as shown in Figure 39 Mixed SystemC and HDL example T 59 Figure 37 ringbuf h include systemc h class ringbuf public sc_foreign_module public sc_in lt bool gt clock sc_in lt bool gt reset sc_in lt bool gt txda sc out bool rxda Sc out bool txc Sc out bool outstrobe ringbuf sc module name nm const char hdl name int num generics const char generic list sc foreign module nm hdl name num generics generic list clock clock reset reset txda txda rxda rxda RO TEXOM M outstrobe outstrobe t ringbuf Figure 38 test_ringbuf cpp file test_ringbuf cpp Copyright Model Technology a Mentor Graphics Corporation company 2004 All rights reserved include test ringbuf h include lt iostream gt SC_MODULE_EXPORT test_ringbuf ModelSim SE Tutorial T 60 Lesson 5 Simulating designs with SystemC Viewing SystemC objects in the GUI SystemC objects are denoted in the ModelSim GUI with a green S on the Library tab a green C on the Files tab and a green square circle or diamond icon elsewhere View Workspace and objects a Click on the Library tab in the Workspace pane of th
96. erties dialog 1 Move tcounter v and counter v to the HDL folder Select counter v hold the Ctrl key down and then select tcounter v b Right click either file and select Properties This opens the Project Compiler Settings dialog Figure 25 which lets you set a variety of options on your design files c Click the Place In Folder drop down arrow and select HDL d Click OK The two files are moved into the HDL folder Click the icons on the folders to see the files The files are now marked with a icon Because you moved the files the project no longer knows if the previous compilation is still valid ModelSim SE Tutorial Figure 24 A folder with a sub folder Workspace EAE Name Status Type Order Modified counter v LS Verilog 1 06 03 04 07 36 00 PM tcounter v X Verilog 0 06 03 04 07 36 26 PM ES Design Files Folder LCJ HDL Folder 2e fe Project Compiler Settings x General Verilog Coverage General Settings Do Not Compile Compile to library wok vi Place in Folder Top Level vt File Properties File sm v Location C 6 0 Tutorial examples coverage verilog sm v MS DOS name C 6 0 Tutorial examples coverage werllog sm Type Verilog Change T ype Size 2459 2KB Simulation Configurations T 39 H H H H Figure 26 T
97. essage tells you that a component dut in this case has not been explicitly bound and no default binding can be found c Type quit sim to quit the simulation ModelSim SE Tutorial Figure 31 Verilog simulation error reported in the Main window Transcript Top level modules counter cd C 6 0 Tutorial testbench Loading project counter Compile of tcounter v was successful ModelSim gt vsim work test counter vsim work test counter Loading work test counter Error vsim 3033 C 6 0 Tutorial testbench tcounter v 9 Instantiation of counter failed The design unit was not found Region test counter Searched libraries work Error loading design 4 ModelSim gt Figure 32 VHDL simulation warning reported in Main window Transcript cd C 6 0 Tutorial testbench Loading project counter Compile of tcounter vhd was successful ModelSim gt vsim work test counter vsim work test counter Loading C Modeltech 6 0 win32 std standard Loading work test_counter only Warning vsim 3473 Component dut is not bound Time Ons Iteration 0 Region test counter File C 6 0 Tutorial testbench tcounter vhd VSIM 9 gt The process for linking to a resource library differs between Verilog and VHDL If you are using Verilog follow the steps in Linking in Verilog T 47 If you are using VHDL follow the steps in L
98. event reset deactivation event sc signal bool reset sc signal bool txda sc signal bool rxda sc signal bool txc sc signal bool outstrobe sc signal sc dt sc uint 20 gt pseudo sc signal sc dt sc uint 20 gt storage sc signal bool expected sc signal bool dataerror sc signal bool actual class ringbuf ring INST test ringbuf sc module name void reset generator y void generate data void compare data y void print error y void print restore y virtual void sc bind mti obi name char y Ak dE dp dp dp dp dp dp dp dp dp dp dp dp dp dp dp dp dp dp dp db ModelSim SE Tutorial T 64 Lesson 5 Simulating designs with SystemC Lesson Wrap up This concludes the lesson Before continuing we need to quit the C debugger and end the current simulation 1 Select Tools gt C Debug gt Quit C Debug 2 Select Simulate gt End Simulation Click Yes when prompted to confirm that you wish to quit simulating ModelSim SE Tutorial Figure 46 SystemC primitive channels in the Wave window wave default LS DI x File Edit View Insert Format Tools Window susslieenlaxes L FIRCUTU ETES ftest_ringbuf counter ftest_ringbufireset test ringbuf txda test ringbuf rxda Jtest ringbuf txc test ringbuf outstrobe test ringbufipseudo test ringbuf storage Itest ringbuf expected Jtest ringbufidataerror ftest_ringbuf actual e Ld
99. ew directory and copy the tutorial files into it Start by creating a new directory for this exercise in case other users will be working with these lessons Create the directory and copy all files from lt install_dir gt examples memory verilog to the new directory If you have a VHDL license copy the files in lt install_dir gt examples memory vhdl instead Start ModelSim and change to the exercise directory If you just finished the previous lesson ModelSim should already be running If not start ModelSim a Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows If the Welcome to ModelSim dialog appears click Close b Select File gt Change Directory and change to the directory you created in step 1 Create the working library and compile the design a Type vlib work at the ModelSim gt prompt b Verilog Type vlog sp syn ram v dp syn ram v ram tb v at the ModelSim gt prompt VHDL Type vcom 93 sp syn ram vhd dp syn ram vhd ram tb vhd at the ModelSim gt prompt Load the design a On the Library tab of the Main window Workspace click the icon next to the work library b Double click the ram tb design unit to load the design Compiling and loading the design T 101 ModelSim SE Tutorial T 102 Lesson 9 Viewing and initializing memories Viewi ng a memory Figure 78 Viewing the memories tab in the Main window workspace Haw Workspace Memories can be viewed via the
100. exercise you will compile and load the testbench and then run the simulation Library C modeltech exe 1 Compile and load the testbench 11 counter Module C modeltechsexz Module vital2000 C modeltech ex MODEL TECH a Atthe ModelSim prompt enter vlog export v or vcom export vhd if you are working with VHDL files Library ieee Library MODEL_TECH You should see a design unit named EditorTestbench appear in the modelsim_ib Library MODEL_TECH Library tab Figure 66 std Library MODEL_TECH b Double click EditorTestbench on the Library tab to load the design std developerskit Library MODEL TECH synopsys Library MODEL TECH 2 Add waves and run the design verilog Library M DEL TECH a Atthe VSIM gt prompt type add wave b Next type run all The waveforms in the Wave window match those you saw in the last exercise Figure 67 3 Quit the simulation a Inthe Main window select Simulate gt End Simulation and click Yes to confirm you want to quit simulating 4 EditorTestbench clk 0 EditorTestbench re Cursor 1 ModelSim SE Tutorial Importing an EVCD file Earlier in the lesson you exported the created waveforms to an extended VCD file In this exercise you will use that file to stimulate the counter design unit Loadthe counter design unit and add waves a Double click counter on the Library tab b Inthe Objects pane right click
101. file A project may also consist of e HDL source files or references to source files e Other files such as READMES or other project documentation e local libraries e references to global libraries This lesson uses the Verilog files tcounter v and counter v in the examples If you have a VHDL license use tcounter vhd and counter vhd instead Related reading ModelSim User s Manual Chapter 2 Projects UM 37 ModelSim SE Tutorial Creating a new project 1 If you just finished the previous lesson ModelSim should already be running If not start ModelSim a Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows Create a new project a Select Create a Project from the Welcome dialog or File gt New gt Project Main window from the menu bar This opens a dialog where you enter a Project Name Project Location i e directory and Default Library Name Figure 14 The default library is where compiled design units will reside Type test in the Project Name field Click Browse to select a directory where the project file will be stored Leave the Default Library Name set to work Click OK If you see the Select Initial Ini dialog asking which modelsim ini file you would like the project to be created from select the Use Default Ini button Figure 14 The Create Project dialog Create Project M m Project Name test I m Project Location C modeltech examples Browse
102. gle coverage columns Figure 118 The blank columns show data when you have extended toggle coverage enabled ModelSim SE Tutorial T 132 Lesson 11 Simulating with Code Coverage Excluding lines and files from coverage statistics ModelSim allows you to exclude lines and files from code coverage statistics You can set exclusions with the GUI with a text file called an exclusion filter file or with pragmas in your source code Pragmas are statements that instruct ModelSim to not collect statistics for the bracketed code See Excluding objects from coverage UM 347 for more details on exclusion filter files and pragmas 1 Exclude a line via the Missed Coverage pane a Right click a line in the Missed Coverage pane and select Exclude Selection You can also exclude the selection for the current instance only by selecting Exclude Selection For Instance inst name 2 Exclude an entire file a Inthe Files tab of the Workspace locate sm v or sm vhd if you are using the VHDL example b Right click the file name and select Coverage Exclude Selected File Figure 119 The file is added to the Current Exclusions pane 3 Cancel the exclusion of sm v a Right click sm v in the Current Exclusions pane and select Cancel Selected Exclusions ModelSim SE Tutorial Figure 119 Excluding an entire file via the GUI Wi or k space Filename Fullpath Type StmtCount Stmt Hits Stmt _ Stmt Gra
103. h section of your code as well as the amount of memory allocated to each function and instance With this information you can identify bottlenecks and reduce simulation time by optimizing your code Users have reported up to 7596 reductions in simulation time after using the Profiler This lesson introduces the Profiler and shows you how to use the main Profiler commands to identify performance bottlenecks It will guide you through a simple code change that improves performance in the example design Design files for this lesson The example design for this lesson consists of a finite state machine which controls a behavioral memory The testbench test sm provides stimulus The ModelSim installation comes with Verilog and VHDL versions of this design The files are located in the following directories Verilog install dir modeltech examples profiler verilog VHDL install dir modeltech examples profiler vhdl This lesson uses the Verilog version for the exercises If you have a VHDL license use the VHDL version instead Related reading ModelSim User s Manual Chapter 12 Profiling performance and memory use UM 317 Chapter 20 Tcl and macros DO files UM 471 ModelSim SE Tutorial Compiling and loading the design 1 Create a new directory and copy the tutorial files into it Start by creating a new directory for this exercise in case other users will be working with these lessons Create the directory
104. he Main window Transcript pane vlib work vmap work work 4 Modifying modelsim ini The first two lines are the command line equivalent of the menu commands you invoked Most menu driven functions will echo their command line equivalents in this fashion The third line notifies you that the mapping has been recorded in the ModelSim initialization file ModelSim SE Tutorial Figure 3 The newly created work library v ModelSim File Edit View Format Compile Simulate Add Tools Window ias ieee Library modelsim_lib Library std Library std developerskit Library synopsys Library ModelSim gt wm title ModelSim vlib work vmap work work Copying C Modeltech 6 0 win32 mo delsim ini to modelsim ini Modifying modelsim ini H Warning Copied C Modeltech 6 0 w in32 modelsim ini to modelsim ini Updated modelsim ini ModelSim gt No Design Loaded Compiling the design T 23 Com pi li ng the desig n Figure 4 The Compile HDL Source Files dialog Compile Source files ZS n Tm Library work x You can compile by using the menus and dialogs of the graphic interface as in the Verilog example below or by entering a command at the ModelSim gt prompt as Look in tutorial er Ea in the VHDL example below With the working library created you are ready to compile your source files counter v 1 Verilog Compile counter v and tcounter v tcounter v a Se
105. he Simulation Configuration dialo imuiation Contigurations 8 y Add Simulation Configuration A Simulation Configuration associates a design unit s and its simulation options Simulation Configuration Name Place in Folder For example say every time you load fcounter v you want to set the simulator los ic resolution to picoseconds ps and enable event order hazard checking Ordinarily you would have to specify those options each time you load the design With a Design VHDL Veiog Libraries SDE others if Simulation Configuration you specify options for a design and then save a Type Path on JE Li Ctmedetech examples work configuration that associates the design and its options The configuration is aod M RS m then listed in the Project tab and you can double click it to load counter v along iB test counter Mods EAEE with its options vital2000 Library MODEL TECH vital2000 I ice Library MODEL_TECH ieee E Il modelsim lib Library MODEL_TECH modelsim_lib 1 Create a new Simulation Configuration std Library MODEL TECH std P z std_developerskit Library MODEL_TECH std_developerskit a Select File gt Add to Project gt Simulation Configuration Library MODEL TECH syropsjs A z 5 mona ed bibens 4kAQDE TOCU tinilan This opens the Simulate dialog Figure 26 The tabs in this dialog ETT PUR resent a myriad of simulation options You may want to explore the tabs Jwork test_
106. he simulation Re simulate using the exported testbench and VCD file Related reading ModelSim User s Manual 10 Generating stimulus with Waveform Editor UM 225 ModelSim GUI Reference Wave window GR 211 ModelSim SE Tutorial Loading a design unit For the examples in this lesson we will use part of the design simulated in Lesson 2 Basic simulation D Note You can also use Waveform Editor prior to loading a design See Using Waveform Editor prior to loading a design GR 287 for more information 1 Ifyou just finished the previous lesson ModelSim should already be running If not start ModelSim a Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows If the Welcome to ModelSim dialog appears click Close 2 Loadthe counter design unit a Select File gt Change Directory and open the directory you created in Lesson 2 The work library should already exist b Click the icon next to the work library and double click counter ModelSim loads the counter design unit and adds sim and Files tabs to the Workspace Loading a design unit T 77 ModelSim SE Tutorial T 78 Lesson 7 Creating stimulus with Waveform Editor Creating waves with a wizard Waveform Editor includes a Create Pattern wizard that walks you through the process of creating editable waveforms Use the Create Pattern wizard to create a clock pattern a Inthe Objects pane right click signal clk and s
107. hics authorization Mentor Graphics grants to you a temporary nontransferable nonexclusive license for experimental use to test and evaluate the Beta Code without charge for a limited period of time specified by Mentor Graphics This grant and your use T 169 ModelSim SE Tutorial T 170 License Agreement of the Beta Code shall not be construed as marketing or offering to sell a license to the Beta Code which Mentor Graphics may choose not to release commercially in any form If Mentor Graphics authorizes you to use the Beta Code you agree to evaluate and test the Beta Code under normal conditions as directed by Mentor Graphics You will contact Mentor Graphics periodically during your use of the Beta Code to discuss any malfunctions or suggested improvements Upon completion of your evaluation and testing you will send to Mentor Graphics a written evaluation of the Beta Code including its strengths weaknesses and recommended improvements You agree that any written evaluations and all inventions product improvements modifications or developments that Mentor Graphics conceived or made during or subsequent to this Agreement including those based partly or wholly on your feedback will be the exclusive property of Mentor Graphics Mentor Graphics will have exclusive rights title and interest in all such property The provisions of this subsection shall survive termination or expiration of this Agreement 4 RESTRICTIONS ON USE You may copy Sof
108. ial Zooming the waveform display Zooming lets you change the display range in the waveform pane There are numerous methods for zooming the display 1 Zoom the display using various techniques a Click the Zoom Mode icon on the Wave window toolbar In the waveform pane click and drag down and to the right You should see blue vertical lines and numbers defining an area to zoom in Figure 49 Select View Zoom Zoom Last The waveform pane returns to the previous display range Click the Zoom In 2x icon a few times In the waveform pane click and drag up and to the right You should see a blue line and numbers defining an area to zoom out Figure 50 Select View Zoom Zoom Full Zooming the waveform display T 69 Figure 49 Zooming in with the mouse pointer LT ins File Edit View Insert Format Tools Window sued r eBa hx essi uuum IEC i E 4 itest counter clk 4 lest counter reset E 4 test_counter count fa ti Q ax 4 test_counter clk 4 jest counter reset Er test_counter count 258 ns to 367 ns Now 1 us Delta 2 ModelSim SE Tutorial T 70 Lesson 6 Viewing simulations in the Wave window Using cursors in the Wave window Cursors mark simulation time in the Wave window When ModelSim first draws the Wave window it places one cursor at time zero Clicking anywhere in the waveform pane brings that cursor to the
109. ile gt Open and open test sm vhd Scroll to line 151 which looks like this wt wd 164104 16 aa clk into Change the data pattern aa to ab wt wd 164104 16 ab clk into Select File Save to save the file Compile the revised file and rerun the simulation Type do sec sim do at the ModelSim gt prompt The DO file does the following e Re compiles the testbench e Adds waves to the Wave window Runs the simulation Creating the test dataset T 151 ModelSim SE Tutorial T 152 Lesson 13 Waveform Compare Comparing the simulation runs ModelSim includes a Comparison Wizard that walks you through the process You can also configure the comparison manually with menu or command line commands Create a comparison using the Comparison Wizard a Select Tools Waveform Compare Comparison Wizard b Click the Browse button and select gold wif as the reference dataset Figure 131 Recall that gold wif is from the first simulation run Leaving the test dataset set to Use Current Simulation click Next d Select Compare All Signals in the second dialog and click Next Figure 132 e Inthe next three dialogs click Next Compute Differences Now and Finish respectively ModelSim performs the comparison and displays the compared signals in the Wave window ModelSim SE Tutorial Figure 131 First dialog of the Comparison Wizard Comparison Wizard The first step in crea
110. ilog simulation UM 111 Chapter 4 VHDL simulation UM 71 ModelSim Command Reference vlib CR 356 vmap CR 370 vlog CR 358 vcom CR 311 vopt CR 371 view CR 332 and right CR 250 commands ModelSim SE Tutorial Creating the working design library T 21 Creati ng the worki ng desig n library Figure 1 The Welcome to ModelSim dialog 4 IMPORTANT Information Ini xi Before you can simulate a design you must first create a library and compile the W i Model Welcome to ModelSim 6 0 ev source code into that library IM IMPORTANT Information 1 Create a new directory and copy the tutorial files into it Key Information Start by creating a new directory for this exercise in case other users will be ModelSim platform changes working with these lessons Product Changes Fro a Verilog Copy counter v and tcounter v files from lt install_dir gt examples Changes in ModelSim functionality to the new directory New Features VHDL Copy counter vhd and tcounter vhd files from lt install_dir gt The latest ModelSim features examples to the new directory ModelSim 6 0 Application Notes 2 Start ModelSim if necessary Performance Guidelines Y n Taking Advantage of SystemVerilog a Type vsim at a UNIX shell prompt or use the ModelSim icon in The ModelSim Debue GUI Windows SystemC Verification Comparing PSL and OVL Upon opening ModelSim for the first time
111. iment with loading from both a file and a fill Figure 89 Loading a relocatable memory file pattern You will initialize spram3 with the 250 addresses of data you saved S lt Load memory previously into the relocatable file reloc mem You will also initialize 50 Instance Name additional address entries with a fill pattern fram tb spramS mem is r Load Type Address Range 3 Load the ram_tb spram3 mem instance with a relocatable memory pattern Le Elle on ee reloc mem and a fill pattern Bate Only Addresses in decimal a Right click in the data column of the mem 2 tab and select Load to Both File and Data Start O End 300 bring up the Load Memory dialog box Figure 89 3d m File Load b For Load Type select Both File and Data Eat c For Address Range select Addresses and enter as the Start address and Verilog Hex 3e 300 as the End address s belly Binary This means that you will be loading the file from 0 to 300 However the 3f reloc mem file contains only 251 addresses of data Addresses 251 to 300 will be loaded with the fill data you specify next Filename reloc mem Browse Data Load d For File Load enter reloc mem in the Filename field Fil Type e For Data Load select a Fill Type of Increment value Increment f Inthe Fill Data field set the seed value of 0 for the incrementing data Decrement Skip P 0 word s g Click OK Random s h View the data near address 250 by doubl
112. in step 1 a Type vlib work at the DOS UNIX prompt b For Verilog type vlog counter v at the DOS UNIX prompt For VHDL type vcom counter vhd Running ModelSim in command line mode T 163 ModelSim SE Tutorial T 164 3 Lesson 14 Automating ModelSim Create a DO file Open a text editor Type the following lines into a new file list all signals in decimal format add list decimal read in stimulus do stim do output results write list counter lst quit the simulation quit f Save the file with the name sim do and place it in the current directory 4 Runthe batch mode simulation 5 a Type vsim c do sim do counter wlf counter wlf at the DOS UNIX prompt The c argument instructs ModelSim not to invoke the GUI The wlf argument saves the simulation results in a WLF file This allows you to view the simulation results in the GUI for debugging purposes View the list output a Open counter lst and view the simulation results ns counter count delta counter clk counter reset O0 0 x Zz 1 0 uz 50 0 Qr ime o 100 0 gg 100 1 000 150 0 0 g 151 0 1 0 200 0 1 0 0 250 0 q 0 ModelSim SE Tutorial This is the output produced by the Verilog version of the design It may appear slightly different if you used the VHDL version View the results in the GUI Since you saved the simulation results in counter wlf you can view them in the GUI by invoking VSIM with
113. inking in VHDL T 48 one page later Linking in Verilog Linking in Verilog requires that you specify a search library when you invoke the simulator 1 Specify a search library during simulation a b Click the Simulate icon on the Main window toolbar Click the icon next to the work library and select PER test counter Click the Libraries tab Click the Add button next to the Search Libraries field and browse to parts lib in the first directory you created earlier in the lesson Click OK The dialog should have parts lib listed in the Search Libraries field Figure 33 Click OK The design loads without errors Linking to the resource library T 47 Figure 33 Specifying a search library in the Simulate dialog RATES Design VHDL Verilog Libraries SDF Options m Search Libraries L C 6 0 Tutorial resource library parts lib Add Modify Delete Search Libraries First Lf Add Modify c LEE LE ModelSim SE Tutorial T 48 Lesson 4 Working with multiple libraries Linking in VHDL To link to a resource library in VHDL you have to create a logical mapping to the physical library and then add LIBRARY and USE statements to the source file 1 Create a logical mapping to parts lib Select File gt New gt Library a b Inthe Create a New Library dialog select a map to an existing library c Type parts lib i
114. install dir modeltech platform directory to your PATH If you did not you will need to specify full paths to the tools i e vlib vmap vlog vcom and vsim that are used in the lesson Related reading ModelSim User s Manual 20 Tcl and macros DO files UM 225 Practical Programming in Tcl and Tk Brent B Welch Copyright 1997 ModelSim SE Tutorial Creating a simple DO file Creating DO files is as simple as typing the commands in a text file Alternatively you can save the Main window transcript as a DO file In this exercise you will use the transcript to create a DO file that adds signals to the Wave window provides stimulus to those signals and then advances the simulation 1 Loadthe fest counter design unit a b c If necessary start ModelSim Change to the directory you created in Lesson 2 Basic simulation In the Library tab of the Workspace pane double click the test_counter design unit to load it 2 Enter commands to add signals to the Wave window force signals and run the simulation a a Select File gt New gt Source gt Do to create a new DO file Enter the following commands into the source window add wave count add wave clk add wave reset force freeze clk 00 1 50 ns r 100 force reset 1 run 100 force reset 0 run 300 force reset 1 run 400 force reset 0 run 200 3 Save the file a b Select File Save As Type sim do in the File name field and sa
115. install_dir gt modeltech examples to the new directory You are creating two directories in this lesson to mimic the situation where you receive a resource library from a third party As noted earlier we will link to the resource library in the first directory later in the lesson Start ModelSim and change to the exercise directory If you just finished the previous lesson ModelSim should already be running If not start ModelSim a Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows If the Welcome to ModelSim dialog appears click Close b Select File gt Change Directory and change to the resource library directory you created in step 1 Create the resource library a Select File New Library b Type parts lib in the Library Name field Figure 29 The Library Physical Name field is filled out automatically Once you click OK ModelSim creates a directory for the library lists it in the Library tab of the Workspace and modifies the modelsim ini file to record this new library for the future Creating the resource library T 43 Figure 29 Creating the new resource library Create a New Library E x Create anew library and a logical mapping to it C a map to an existing library m Library Name parts lit m Library Physical Name parts_lib OK Cancel ModelSim SE Tutorial T 44 Lesson 4 Working with multiple libraries 5 Compile the co
116. ional Coverage Restart Cancel ModelSim SE Tutorial T 28 Lesson 2 Basic simulation c Click the Run All icon The simulation runs until the breakpoint is hit When the simulation hits the breakpoint it stops running highlights the line with a blue arrow in the Source view Figure 12 and issues a Break message in the Transcript pane When a breakpoint is reached typically you want to know one or more signal values You have several options for checking values e look at the values shown in the Objects window Figure 13 set your mouse pointer over the count variable in the Source window and a balloon will pop up with the value Figure 12 e highlight the count variable in the Source window right click it and select Examine from the pop up menu e use the examine command to output the value to the Main window Transcript i e examine count 5 Try out the step commands a Click the Step icon on the Main window toolbar This single steps the debugger Experiment on your own Set and clear breakpoints and use the Step Step Over and Continue Run commands until you feel comfortable with their operation ModelSim SE Tutorial Figure 12 Resting the mouse pointer on a variable in the Source view 31 32 33 34 35 C 6 0 Tutorial examp 22 for i 4 bO carry 4 bl 466 i lt 7 i it 23 begin 24 increment i val i carry 25 carry val
117. lay cover directives in count mode Reporting functional coverage statistics Lesson wrap up T 136 T 136 T 136 T 137 T 138 T 139 T 141 T 143 T 144 T 145 T 135 ModelSim SE Tutorial T 136 Lesson 12 Debugging with PSL assertions Introduction Using assertions in your HDL code increases visibility into your design and improves verification productivity ModelSim supports Property Specification Language PSL assertions for use in dynamic simulation verification These assertions are simple statements of design intent that declare design or interface assumptions This lesson will familiarize you with the use of PSL assertions in ModelSim You will run a simulation with and without assertions enabled so you can see how much easier it is to debug with assertions After running the simulation with assertions you will use the ModelSim debugging environment to locate a problem with the design Design files for this lesson The sample design for this lesson uses a DRAM behavioral model and a self checking testbench The DRAM controller interfaces between the system processor and the DRAM and must be periodically refreshed in order to provide read write and refresh memory operations Refresh operations have priority over other operations but a refresh will not preempt an in process operation The ModelSim installation comes with Verilog and VHDL versions of this design The files are located in the fol
118. lder Name field Figure 21 c Click OK You ll now see a folder in the Project tab Figure 22 2 Adda sub folder a Right click anywhere in the Project tab and select Add to Project gt Folder b Type HDL in the Folder Name field Figure 23 c Click the Folder Location drop down arrow and select Design Files d Click OK Organizing projects with folders T 37 Figure 21 Adding a new folder to the project f Add Folder xj Folder Name z Files 1b Folder Location E Level vij OK Cancel Figure 22 A folder in a project Workspace Name Steus Type rder Modfed countery vy Verilog 1 06 03 04 07 36 00 PM tcounter X Verlog O 06 03 04 07 36 26 PM M Design Files Folder Project Library Figure 23 Creating a subfolder y Add Folder x m Folder Name HDL 2b Folder Location Design Files a 2c Top Level ma incel ModelSim SE Tutorial T 38 Lesson 3 ModelSim projects You ll now see a amp icon next to the Design Files folder in the Project tab Figure 24 e Click the icon to see the HDL sub folder Moving files to folders Now that you have folders you can move the files into them If you are running on a Windows platform you can simply drag and drop the files into the folder On Unix platforms you either have to place the files in a folder when you add the files to the project or you have to move them using the prop
119. le click test sm v 105 The Source window opens in the MDI frame with line 105 displayed Figure 100 VHDL Double click test sm vhd 203 The Source window opens in the MDI frame with line 203 displayed Running the simulation T 117 Figure 99 Expand the hierarchical function call tree Profile Tcl Flush L Tcl Close Tcl DoOneEvent Tcl DeleteTimerHandler L Tcl GetTime Tcl WaitForEvent sm 73 test_sm v 92 Call Tree Structural 99 end 100 101 102 always posedge clk 103 outof 5 out wire put output in register 104 105 always outof any change of outof 106 display time BRoutofV een outof 107 108 integer i f 103 110 111 112 tests 4l zi h test_sm yv KE ModelSim SE Tutorial T 118 Lesson 10 Analyzing performance with the Profiler View Profile Details The Profile Details pane increases visibility into simulation performance and memory usage Right clicking any function in the Ranked or Call Tree views opens a popup menu that includes a Function Usage selection When Function Usage is selected the Profile Details pane opens in the Main window and displays all instances using the selected function 1 View the Profile Details of a function in the Call Tree view a Right click the Tc Close function and select Function Usage from the popup menu The Profile Details pane displays all instances using function Tcl_Close Figure 101 The statis
120. lect Compile Compile This opens the Compile Source Files dialog Figure 4 If the Compile menu option is not available you probably have a project open If so close the project by selecting File Close when the S File t mm t C 1 Workspace pane is selected at PM EL EE EL b Select counter v hold the Ctrl key down and then select tcounter v Files of type HDL Files v v1 vhd vhdl vho hdl v x me c With the two files selected click Compile Default Options Edit Source Figure 5 Verilog modules compiled into the work library VHDL Compile counter vhd and counter vhd File Edit View Format Compile Simulate Add Tools Window Help ELESSE a Contains Transcript Hg Compiling module test counter E The files are compiled into the work library d Click Done a Type vcom counter vhd tcounter vhd at the ModelSim gt prompt and press lt Enter gt on your keyboard 2 View the compiled design units a On the Library tab click the icon next to the work library and you will see two design units Figure 5 You can also see their types Modules Entities etc and the path to the underlying source files if you scroll to the right Top level modules H test counter vlog reportprogress 300 work work C 6 0 Mi uy ij counter Module E test counter Module 1 Tutorial examples counter v 7 Model Technology ModelSim SE vl
121. limited for example to execution of a single session by a single user on the authorized hardware or for a restricted period of time such limitations may be communicated and technically implemented through the use of authorization codes or similar devices c support services provided including eligibility to receive telephone support updates modifications and revisions Current standard policies and programs are available upon request ESD SOFTWARE If you purchased a license to use embedded software development ESD Software Mentor Graphics grants to you a nontransferable nonexclusive license to reproduce and distribute executable files created using ESD compilers including the ESD run time libraries distributed with ESD C and C compiler Software that are linked into a composite program as an integral part of your compiled computer program provided that you distribute these files only in conjunction with your compiled computer program Mentor Graphics does NOT grant you any right to duplicate or incorporate copies of Mentor Graphics real time operating systems or other ESD Software except those explicitly granted in this section into your products without first signing a separate agreement with Mentor Graphics for such purpose BETA CODE Portions or all of certain Software may contain code for experimental testing and evaluation Beta Code which may not be used without Mentor Graphics explicit authorization Upon Mentor Grap
122. ling your design Running the simulation Debugging your results Project flow Multiple library flow Debugging tools T 12 T 13 T 13 T 13 T 13 T 14 T 15 T 16 T 17 ModelSim SE Tutorial T 12 Lesson 1 ModelSim conceptual overview Introduction ModelSim is a simulation and debugging tool for VHDL Verilog SystemC and mixed language designs This lesson provides a brief conceptual overview of the ModelSim simulation environment It is divided into four topics which you will learn more about in subsequent lessons Topic Additional information and practice Basic simulation flow Lesson 2 Basic simulation Project flow Lesson 3 ModelSim projects Multiple library flow Lesson 4 Working with multiple libraries Debugging tools Remaining lessons ModelSim SE Tutorial Basic simulation flow T 13 Basic simulation flow The following diagram shows the basic steps for simulating a design in ModelSim Creating the working library In ModelSim all designs be they VHDL Verilog SystemC or some combination thereof are compiled into a library You typically start a new simulation in ModelSim by creating a working library called work Work is the library name used by the compiler as the default destination for compiled design units Compiling your design After creating the working library you compile your design units into it The ModelSim library format is compatible across a
123. ll supported platforms You can simulate your design on any platform without having to recompile your design Running the simulation With the design compiled you invoke the simulator on a top level module Verilog or a configuration or entity architecture pair VHDL Assuming the design loads successfully the simulation time is set to zero and you enter a run command to begin simulation ModelSim SE Tutorial T 14 Lesson 1 ModelSim conceptual overview Debugging your results If you don t get the results you expect you can use ModelSim s robust debugging environment to track down the cause of the problem ModelSim SE Tutorial Project flow T 15 Project flow A project is a collection mechanism for an HDL design under specification or test Even though you don t have to use projects in ModelSim they may ease interaction with the tool and are useful for organizing files and specifying simulation settings The following diagram shows the basic steps for simulating a design within a ModelSim project As you can see the flow is similar to the basic simulation flow However there are two important differences You do not have to create a working library in the project flow it is done for you automatically Projects are persistent In other words they will open every time you invoke ModelSim unless you specifically close them ModelSim SE Tutorial T 16 Lesson 1 ModelSim conceptual overview Multiple library flow
124. log The Main window transcript shows that the assert check refresh assertion in the dram cntrl psl file failed at 3100 ns The simulation is stopped at that time Note that with no assertions the testbench did not report a failure until 267 400 ns over 80x the simulation time required for a failure to be reported with assertions VHDL The Main window transcript shows that the assert check refresh assertion in the dram cntrl psl file failed at 3800 ns The simulation is stopped at that time Note that with no assertions the testbench did not report a failure until 246 800 ns over 60x the simulation time required for a failure to be reported with assertions The Wave window displays a red triangle at the point of the simulation break and shows FAIL in the values column of the assert check refresh assertion Figure 123 The blue sections of the assertion waveforms indicate inactive assertions green indicates active assertions The Assertions pane also indicates a failure of assert check refresh in the Failure Count column Figure 124 You ll notice in the Functional Coverage window that the cover directives have not been executed ModelSim SE Tutorial Figure 123 Assertion failure indicated in the Wave window mave deaur MET File Edit View Insert Format Tools Window OO ON TOOL NF ref_count CLEITE LITIY refresh Assertions assert__test_read_response assert_test_write_response assert__check_as
125. lowing directories Verilog install dir modeltech examples psl verilog VHDL install dir modeltech examples psl vhdl This lesson uses the Verilog version for the exercises If you have a VHDL license use the VHDL version instead You can embed assertions within your code or supply them in a separate file This example design uses an external file Related reading ModelSim User s Manual Chapter 14 PSL Assertions Chapter 15 Functional coverage with PSL and ModelSim ModelSim SE Tutorial Compile the example design In this exercise you will use a DO file to compile the design 1 Create a new directory and copy the lesson files into it Start by creating a new directory for this exercise in case other users will be working with these lessons Create the directory and copy all files from lt install_dir gt examples psl verilog to the new directory If you have a VHDL license copy the files in lt install_dir gt examples psl vhdl instead Start ModelSim and change to the exercise directory you created If you just finished the previous lesson ModelSim should already be running If not start ModelSim a To start ModelSim type vsim at a UNIX shell prompt or use the ModelSim icon in Windows If the Welcome to ModelSim dialog appears click Close Select File gt Change Directory and change to the directory you created in step 1 Execute the lesson DO file a Type do compile do at th
126. module store Top level modules ringbuf 5 Create the foreign module declaration SystemC stub for the Verilog module ringbuf a Verilog Type scgenmod bool ringbuf gt ringbuf h at the ModelSim gt prompt The bool argument is used to generate boolean scalar port types inside the foreign module declaration See scgenmod CR 258 for more information VHDL Type scgenmod ringbuf gt ringbuf h at the ModelSim gt prompt The output is redirected to a file ringbuf h Figure 37 This file is included in the test_ringbuf cpp file Figure 38 6 Compile and link all SystemC files including the generated ringbuf h a Type sccom g test ringbuf cpp at the ModelSim gt prompt Thetest ringbuf cpp file contains an include statement for test_ringbuf h and a a necessary SC_MODULE_EXPORT top statement which informs ModelSim that the top level module is SystemC Upon successfully compiling the design following message appears in the Transcript window Model Technology ModelSim sccom compiler 2003 05 May 25 2004 Exported modules test_ringbuf b Type sccom link at the ModelSim gt prompt to perform the final link on the SystemC objects ModelSim SE Tutorial Load the design Click on the Library tab in the Workspace pane of the Main window b Clickthe icon next to the work library in the Main window to expand the work library c Double click the test ringbuf design unit in the Workspace pane The equival
127. n the Library Name field Qa Click Browse to open the Select Library dialog and browse to parts_lib in the resource_library directory you created earlier in the lesson Click OK to select the library and close the Select Library dialog e The Create a New Library dialog should look similar to the one shown in Figure 34 Click OK to close the dialog 2 Add LIBRARY and USE statements to tcounter vhd a Inthe Library tab of the Main window click the icon next to the work library b Right click test counter in the work library and select Edit This opens the file in the Source window c Add these two lines to the top of the file LIBRARY parts lib USE parts lib ALL The testbench source code should now look similar to that shown in Figure 33 d Select File Save 3 Recompile and simulate a Inthe Project tab of the Main window right click tcounter vhd and select Compile Compile Selected b In the Library tab double click test counter to load the design The design loads without errors ModelSim SE Tutorial Figure 34 Mapping to the parts lib library fu Create a New Library Create C anew library and a logical mapping to it amapto an existing library Library Name ge Library Maps to x Tutorial resource_library parts_ vi Browse DK Cancel Figure 35 Adding LIBRARY and USE statements to the testbench E C 6 0 Tutorial testbench tcounter
128. nd Structural Figure 98 Data in the Ranked view anked is sorted by default from highest to lowest percentage in the In column In the Call Tree and Structural views data is sorted by default Glick here to hide or according to the Under column You can click the heading of any display columns column to sort data by that column ModelSim SE Tutorial b Click the Call Tree tab to view the profile data in a hierarchical function call tree display The results differ between the Verilog and VHDL versions of the design In Verilog line 105 test sm v 105 is taking the majority of simulation time In VHDL test sm vhd 203 and sm vhd 93 are taking the majority of the time P Note Your results may look slightly different as a result of the computer you re using and different system calls that occur during the simulation Also the line number reported may be one or two lines off the actual source file This happens due to how the stacktrace is decoded on different platforms Verilog Right click test sm v 105 and select Expand All from the popup menu This expands the hierarchy of test sm v 105 and allows you to see the functions that call it Figure 99 VHDL Right click test sm vhd 203 and select Expand All from the popup menu This expands the hierarchy of test sm vhd 203 and allows you to see the functions that call it 4 View the source code of a line that is using a lot of simulation time a Verilog Doub
129. ng the project T 45 ModelSim SE Tutorial T 46 Lesson 4 Working with multiple libraries Linking to the resource library To wrap up this part of the lesson you will link to the parts lib library you created earlier But first try simulating the testbench without the link and see what happens ModelSim responds differently for Verilog and VHDL in this situation Verilog 1 Simulate a Verilog design with a missing resource library a In the Library tab click the icon next to the work library and double click test counter The Main window Transcript reports an error Figure 31 When you see a message that contains text like Error vsim 3033 you can view more detail by using the verror command b Type verror 3033 at the ModelSim gt prompt The expanded error message tells you that a design unit could not be found for instantiation It also tells you that the original error message should list which libraries ModelSim searched In this case the original message says ModelSim searched only work VHDL 1 Simulate a VHDL design with a missing resource library a Inthe Library tab click the icon next to the work library and double click test counter The Main window Transcript reports a warning Figure 32 When you see a message that contains text like Warning vsim 3473 you can view more detail by using the verror command b Type verror 3473 at the ModelSim gt prompt The expanded error m
130. nt 83 70 94337 D StmtHits wv Stmt v Stmt Graph v Branch Count Let s take a look at the data in these various panes Branch Branch Graph 1 View statistics in the Workspace pane a Selectthe sim tab in the Workspace and scroll to the right Coverage statistics are shown for each object in the design b Select the Files tab in the Workspace and scroll to the right DESEE ea v Branch Hits Each file in the design shows summary statistics for statements Files iu wv Branch branches conditions and expressions v Branch Graph v Condition Count 5 illegal op received 35 outof 00000000 mu 455 outof O00000aa v Condition 515 outof 000000bb v Condition Graph E35 outol DODODDcd v Expression Count 695 outof 000000ce v Expression Hits wv Expression Transcript c Click the right mouse button on any column name and select an object from the list Figure 111 Whichever column you selected is hidden To redisplay the column right click again and select that column name The status of which columns are displayed or hidden is persistent between invocations of HHHHHHH ModelSim i VSIM 6 gt w Expression Graph 2 View statistics in the Missed Coverage pane Figure 112 Statement statistics in the Missed Coverage pane a Select different files from the Files tab of the Workspace The Missed Coverage pane updates to show statistics for th
131. og 6 0 Library Beta Compiler 2004 06 Jun 4 2004 modelsim lib Library Compiling module counter g std Library ZA Top level modules gt counter Library ModelSim gt No Design Loaded No Context ModelSim SE Tutorial T 24 Lesson 2 Basic simulation Loading the design into the simulator 1 Load the test counter module into the simulator a Double click test counter in the Main window Workspace to load the design You can also load the design by selecting Simulate Start Simulation in the menu bar This opens the Start Simulation dialog With the Design tab selected click the sign next to the work library to see the counter and test counter modules Select the test counter module and click OK Figure 6 When the design is loaded you will see a new tab named sim that displays the hierarchical structure of the design Figure 7 You can navigate within the hierarchy by clicking on any line with a expand contract icon You will also see a tab named Files that displays all files included in the design ModelSim SE Tutorial test counter vital2000 ieee Il modelsim lib std std developerskit m mM sean 4 Library Module Module Library Library Library Library Library 1 ibrar Figure 6 Loading the design with the Start Simulation dialog C 6 0 Tutorial examples work C 46 0 Tutorial examples counter v C 46 0 Tutorial example
132. on data es ae Viewing comparison data in the Main window Viewing comparison data in the Wave window Viewing comparison data in the List window Saving and reloading comparison data Lesson wrap up D Note The functionality described in this tutorial requires a compare license feature in your ModelSim license file Please contact your Mentor Graphics sales representative if you currently do not have such a feature T 148 T 148 T 148 T 150 T 150 T 151 T 152 T 153 T 153 T 153 T 154 T 155 T 157 T 147 ModelSim SE Tutorial T 148 Lesson 13 Waveform Compare Introduction Waveform Compare computes timing differences between test signals and reference signals The general procedure for comparing waveforms has four main steps 1 Selecting the simulations or datasets to compare 2 Specifying the signals or regions to compare 3 Running the comparison 4 Viewing the comparison results In this exercise you will run and save a simulation edit one of the source files run the simulation again and finally compare the two runs Design files for this lesson The sample design for this lesson consists of a finite state machine which controls a behavioral memory The testbench fest sm provides stimulus The ModelSim installation comes with Verilog and VHDL versions of this design The files are located in the following directories Verilog install dir modeltech examples compare ve
133. ontents pane and select Properties The Properties dialog box opens Figure 81 b Forthe Address Radix select Decimal This changes the radix for the addresses only c Select Words per line and type 1 in the field d Click OK You can see the results of the settings in Figure 82 If the figure doesn t match what you have in your ModelSim session check to make sure you set the Address Radix rather than the Data Radix Data Radix should still be set to Symbolic the default Viewing a memory T 103 Figure 80 Memory display updates with simulation 00000000 00000006 0000000c 00000012 00000018 0000001e 00000024 00000022 00000030 00000036 0000003c 00000042 00000048 AAA NN A K m1 mem 00101000 00101110 00110100 00111010 01000000 01000110 01001100 01010010 01011000 01011110 01100100 01101010 01110000 marinn 00101001 00101010 00101111 00110000 00110101 00110110 00111011 00111100 01000001 01000010 01000111 01001000 01001101 01001110 01010011 01010100 01011001 01011010 01011111 01100000 01100101 01100110 01101011 01101100 01110001 01110010 333633535 AIIAN 00101011 00110001 00110111 00111101 01000011 01001001 01001111 01010101 01011011 01100001 01100111 01101101 01110011 1111360601 00101100 00101101 00110010 00110011 00111000 00111001 00111110 00111111 01000100 01000101 01001010 01001011 01010000 01010001 01010110 01010111 01011100 01011101 01100010 01100011 01101000
134. ortnet Updates Access to the most current version of ModelSim www model com downloads default asp Latest version email Place your name on our list for email notification of news and updates www model com products informant asp ModelSim SE Tutorial Before you begin T 9 Before you begin Preparation for some of the lessons leaves certain details up to you You will decide the best way to create directories copy files and execute programs within your operating system When you are operating the simulator within ModelSim s GUI the interface is consistent for all platforms Examples show Windows path separators use separators appropriate for your operating system when trying the examples Example designs ModelSim comes with Verilog and VHDL versions of the designs used in these lessons This allows you to do the tutorial regardless of which license type you have Though we have tried to minimize the differences between the Verilog and VHDL versions we could not do so in all cases In cases where the designs differ e g line numbers or syntax you will find language specific instructions Follow the instructions that are appropriate for the language that you are using ModelSim SE Tutorial T 10 Introduction ModelSim SE Tutorial Lesson 1 ModelSim conceptual overview Topics The following topics are covered in this chapter Introduction Basic simulation flow Creating the working library Compi
135. ory If you have a VHDL license copy the files in lt install_dir gt examples dataflow vhdl instead Start ModelSim and change to the exercise directory If you just finished the previous lesson ModelSim should already be running If not start ModelSim a Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows If the Welcome to ModelSim dialog appears click Close b Select File gt Change Directory and change to the directory you created in step 1 Execute the lesson DO file a Typedo run do at the ModelSim gt prompt The DO file does the following e Creates the working library e Compiles the design files e Opens the Dataflow and Wave windows Adds signals to the Wave window e Logs all signals in the design e Runs the simulation Feel free to open the DO file and look at its contents Compiling and loading the design T 91 ModelSim SE Tutorial T 92 Lesson 8 Debugging with the Dataflow window Exploring connectivity A primary use of the Dataflow window is exploring the physical connectivity of your design You do this by expanding the view from process to process This allows you to see the drivers receivers of a particular signal net or register 1 Adda signal to the Dataflow window a Make sure instance p is selected in the sim tab of the Workspace pane b Drag signal strb from the Objects pane to the Dataflow window Figure 68 2 Explore the design a Double click the net highlighted in re
136. ph sm seq v sm seqv vfile 22 21 95 455 DO sm v em file 30 27 90 000 DEN beh sramv View Source file 10 9 90 000 DEN Save List fila ga Coverage Coverage Reports Exclude ted File 7 lest sm v 30 361 DR Copy i Clear Coverage Data Properties Creating Code Coverage reports You can create reports on the coverage statistics using either the menus or by entering commands in the Transcript pane The reports are output to a text file regardless of which method you use To create coverage reports via the menus do one of the following select Tools Code Coverage Reports from the Main window menu right click any object in the sim or Files tab of the Workspace and select Code Coverage Coverage Reports right click any object in the Instance Coverage pane and select Code coverage reports from the context menu 1 Create a report on all instances a Select Tools Coverage Reports from the Main window toolbar This opens the Coverage Report dialog Figure 120 b Make sure Report on all instances and No Filtering are selected and then click OK ModelSim creates a file report txt in the current directory and displays the report in Notepad c Close Notepad when you are done looking at the report 2 Create a summary report on all design files from the Transcript pane a Type coverage report file cover txt at the VSIM gt prompt b Type notepad cover txt at the VSIM gt prompt to view
137. restricted rights Use duplication or disclosure by the U S Government or a U S Government subcontractor is subject to the restrictions set forth in the license agreement provided with the software pursuant to DFARS 227 7202 3 a or as set forth in subparagraph c 1 and 2 of the Commercial Computer Software Restricted Rights clause at FAR 52 227 19 as applicable Contractor manufacturer is Mentor Graphics Corporation 8005 S W Boeckman Road Wilsonville Oregon 97070 7777 This is an unpublished work of Mentor Graphics Corporation Contacting ModelSim Support Telephone 503 685 0820 Toll Free Telephone 877 744 6699 Website www model com Support www model com support ModelSim SE Tutorial Table of Contents irit iil CT T 5 Lesson 1 ModelSim conceptual overview T 11 Lesson 2 Basic simulation Liu dues ERROR see Y gne eee T 19 Lesson 3 ModelSim projects sse RR ER emn T 31 Lesson 4 Working with multiple libraries T 41 Lesson 5 Simulating designs with SystemC T 51 Lesson 6 Viewing simulations in the Wave window T 65 Lesson 7 Creating stimulus with Waveform Editor T 75 Lesson 8 Debugging with the Dataflow window T 89 Lesson 9 Viewing and initializing memories T 99 Lesson 10 Analyzing performance with the Profiler T 113 Lesson 11 Simulating with Cod
138. rilog VHDL install dir modeltech examples compare vhdl This lesson uses the Verilog version in the examples If you have a VHDL license use the VHDL version instead When necessary we distinguish between the Verilog and VHDL versions of the design Related reading Waveform Compare UM 270 Chapter 8 WLF files datasets and virtuals UM 225 ModelSim SE Tutorial Creating the reference dataset The reference dataset is the w f file that the test dataset will be compared against It can be a saved dataset the current simulation dataset or any part of the current simulation dataset In this exercise you will use a DO file to create the reference dataset 1 Create a new directory and copy the tutorial files into it Start by creating a new directory for this exercise in case other users will be working with these lessons Create the directory and copy all files from install dir modeltech examples compare verilog to the new directory If you have a VHDL license copy the files in install dir modeltech examples compare vhdl instead 2 Start ModelSim and change to the exercise directory If you just finished the previous lesson ModelSim should already be running If not start ModelSim a Type vsim at a UNIX shell prompt or use the ModelSim icon in Windows If the Welcome to ModelSim dialog appears click Close b Select File gt Change Directory and change to the directory you created in step 1 3
139. s platforms win2K XP etc MinGW gcc 3 2 3 See SystemC simulation in the ModelSim User s Manual for further details ModelSim SE Tutorial T 54 Lesson 5 Simulating designs with SystemC Preparing an OSCI SystemC design When you first bring up an OpenSystemC Initiative OSCI compliant design in ModelSim you must make a few minor modifications to the SystemC code to prepare it for running in ModelSim For a SystemC design to run on ModelSim you must first Replace sc main with an SC MODULE potentially adding a process to contain any testbench code Replace sc start by using the run CR 252 command in the GUI Remove calls to sc initialize Export the top level SystemC design unit s using the SC MODULE EXPORT macro In order to maintain portability between OSCI and ModelSim simulations we recommend that you preserve the original code by using ifdef to add the ModelSim specific information When the design is analyzed sccom CR 254 recognizes the MTI SYSTEMC preprocessing directive and handles the code appropriately For more information on the minor modifications to OSCI SystemC files necessary for simulation in ModelSim see Modifying SystemC source code UM 164 1 Create a new directory and copy the tutorial files into it Start by creating a new directory for this exercise in case other users will be working with these lessons Create the directory then copy all files from install dir
140. s tcounter v MODEL_TECH vital2000 MODEL_TECH ieee MODEL_TECH modelsim_lib MODEL TECH std MODEL TECH std developerskit thONEL TECH tomancne Design Unit s E Ld osa x Optimization 5 Enable optimization Optimization Options OK Cancel Figure 7 Workspace tab showing a Verilog design x ModelSim File Edit View Format Compile Simulate Add Tools Window ad Workspace EM test_counter M dut SIMPLICI SIMPLICI d INITIAL FINITIAL d OHINITIAL instance _ Design unit_ Design unit type test_counter counter test_counter test_counter test_counter test_counter test_counter 6 0 Beta Compiler 2004 06 Jun 4 2004 Compiling module counter meelis Compiling module test counter Module Process Top level modules H test counter Dieses ModelSim gt vsim work test counter Process vsim work test counter Process Loading work test counter Process Loading work counter Bee e e p Now Ons Delta 0 sim test_counter VSIM 19 gt Running the simulation Now you will run the simulation 1 Set the graphic user interface to view all debugging windows a Select View gt Debug Windows gt All Windows This opens all ModelSim windows giving you different views of your design data and a variety of debugging tools Most windows will open as panes within th
141. se the project 1 Select Simulate gt End Simulation Click Yes 2 Select the Project tab of the Main window Workspace 3 Select File gt Close Click OK ModelSim SE Tutorial Lesson 5 Simulating designs with SystemC Topics The following topics are covered in this lesson Introduction Lx x 3 Design files for this lesson Related reading Setting up the environment Preparing an OSCI SystemC design Compiling a SystemC only design Mixed SystemC and HDL example Viewing SystemC objects in the GUI Setting breakpoints and stepping in the Source window Lesson Wrap up gt Note The functionality described in this tutorial requires a systemc license feature in your ModelSim license file Please contact your Mentor Graphics sales representative if you currently do not have such a feature T 52 T 52 T 52 T 53 T 56 T 56 T 56 T 60 T 61 T 64 T 51 ModelSim SE Tutorial T 52 Lesson 5 Simulating designs with SystemC Introduction ModelSim treats SystemC as just another design language With only a few exceptions in the current release you can simulate and debug your SystemC designs the same way you do HDL designs Design files for this lesson There are two sample designs for this lesson The firstis a very basic design called basic containing only SystemC code The second design is a ring buffer where the testbench and top level chip are implemented in SystemC and the lower level modules
142. sic h int se maini int char Sc clock clk mod a a a Jj gg de yg sc initialize return 0 basic orig h ifndef INCLUDED TEST define INCLUDED TEST include systemc h SC MODULE mod a SC in clk clk void main action method cout lt lt simcontext gt delta_count lt lt main action method called endl void main action thread while true cout lt lt simcontext gt delta_count lt lt main action thread called endl SC CTOR mod a SC METHOD main action method SC THREAD main action thread dendif basic cpp modified file Existing contents of basic orig cpp and adds include basic h ifdef MTI SYSTEMC SC MODULE EXPORT top else OSCI sc_main code here endif basic h Includes everything in basic_orig h and adds the ollowing OSCI SC MODULE code here ifdef MTI SYSTEMC SC MODULE top ee clock clik mod_a a SC_CTOR top re a a clk elk J3 endif Mixed SystemC and HDL example In this next example you have a SystemC testbench that instantiates an HDL module In order for the SystemC testbench to interface properly with the HDL module you must create a stub module a foreign module declaration You will use the scgenmod CR 258 utility to create the foreign module declaration Finally you will link the created C object files using s
143. ssertion Extended mode enabled Keep 1 Ab cntrlwe n failure c Select the process that drives we 7n in order to display its source code in Figure 128 Finding ihe hug ithe source code the Source window BI C PSL Tutorial DRAM cntrlr extemal vlog dramcon rtl sv Verilog Looking at the Source window you ll see that the current line 99 assign col out mem state 3 arrow points to line 104 of the dramcon rtl sv file Figure 128 In this 100 assign ras n mem_state Z line you can see that the logic assigning we_n is wrong it does not 101 assign cas n mem state l account for the REF2 state pel ASSUES MER NN state tl The code shows that the incorrect assignment is used for the example 104 Deassert we n high during refresh with the correct assignment immediately below lines 106 107 that will 105 ifdef BUG hold we_n high through both states of the refresh cycle ree c rri DEL we n rw mem state REF1 else VHDL Looking at the Source window you can see that the current line 108 assign DEL we n rw mem state REFl arrow points to line 61 of the dramcon rtl vhd file In this line you can 103 i mem state REFZ see that the logic assigning we_n is wrong it does not account for the 110 endif REF state 111 112 Give the row address or column address to the DRAM The code shows that the incorrect assignment is used for the example 112 medion 4 NTT adde aee anl eee 2 dde def ANTTI
144. stance coverage statistics Figure 114 The Instance Coverage pane Instance Coy erage NI Stmt graph Berch sont Broreh is Franchises ranch Branch gegh Doe ModelSim SE Tutorial Viewing statistics in the Source window In the previous section you saw that the Source window and the Main window coverage panes are linked You can select objects in the Main window panes to view the underlying source code in the Source window Furthermore the Source window contains statistics of its own 1 View coverage statistics for test sm in the Source window Make sure fest sm is selected in the sim tab of the Workspace b Inthe Statement tab of the Missed Coverage pane expand test sm v if necessary and select any line Figure 115 The Source window opens in the MDI frame with the line you selected highlighted Figure 116 c Switch to the Source window The table below describes the various icons Icon Description Viewing statistics in the Source window Figure 115 Selecting a line in the Missed Coverage pane Missed Coverage Ir Missed Statements wL test sm v X 18 c X 18 into 4 b0000 h0 X 19 endtask X 25 s X 25 into 4 b0001 28 b0 X 26 8 posedge clk X 27 5 X 2 into data X 29 endtask 113 repeat X 126 nop X 128 100 X 128 stop sn green checkmark indicates a statement that has been executed red X indicates that a statement in that line has not
145. statistical sampling profiler can be used to speed up the simulation In this example the repeated printing of data values to the screen is a significant burden to simulation A more efficient approach would be to print only fail messages when they occur and a single pass message at the end of a data block or the entire simulation run Editthe source code to remove the repeated screen printing a Right click the source code and uncheck the Read Only selection in the popup menu b Comment out the repeated screen printing Verilog Change lines 105 106 so they look like this always outof any change of outof A display Stime outof h outof VHDL Change lines 198 201 so they look like this write msg_line NOW field gt 10 write msg line msgl hwrite msg line rd data writeline OUTPUT msg line 2 Save the file and re compile a Select File Save b Verilog Type vlog test sm v at the VSIM prompt VHDL Type vcom test sm vhd at the VSIM gt prompt 3 Recstart and re run the design a Typerestart f at the VSIM prompt b Typedo profile run do at the VSIM prompt The simulation time is reduced by almost 5046 Figure 103 4 Look at the performance data again a Ifnecessary select Tools Profile View then the Call Tree tab The problem with repeated screen printing has been removed Figure 104 Using the data to improve performance T 119 Figure 103 Simulation time re
146. the report c Close Notepad when you are done reviewing the report Creating Code Coverage reports T 133 Figure 120 The Coverage Report dialog igi xi C Report on all files C Report on all instances Report on a specific instance Instance Name sim test_sm Browse C Report on a source file File Name Report on a specific package Package Name xj Coverage Type IV Statement Coverage Expression Coverage Branch Coverage Toggle Coverage Condition Coverage Extended Toggle Coverage Other Options Filter 3 Zero Coverage Only No Filtering IV Include Line Details Filter Above Percent Coverage Totals Only C Filter Below Percent Disable Source Annotation Percent 75 IV Recursive Write XML Format Report Pathname reportat Browse Append to file OK Cancel ModelSim SE Tutorial T 134 Lesson 11 Simulating with Code Coverage Lesson wrap up This concludes this lesson Before continuing we need to end the current simulation 1 Type quit sim at the VSIM prompt ModelSim SE Tutorial Lesson 12 Debugging with PSL assertions Topics The following topics are covered in this lesson Introduction B x x 4 Design files for this lesson Related reading Compile the example design Load and run without assertions Using assertions to speed debugging Debugging the assertion failure Disp
147. tical performance and memory allocation data shows how much simulation time and memory is used by Tcl Close in each instance When you right click a selected function or instance in the Structural pane the popup menu displays either a Function Usage selection or an Instance Usage selection depending on the object selected 2 View the Profile Details of an instance in the Structural view a Select the Structural tab to change to the Structural view b Right click test sm and select Expand All from the popup menu c Verilog Right click the sm_0 instance and select Instance Usage from the popup menu The Profile Details shows all instances with the same definition as est_sm sm_seqO sm_0 Figure 102 VHDL Right click the dut instance and select Instance Usage from the popup menu The Profile Details shows all instances with the same definition as test_sm dut ModelSim SE Tutorial Figure 101 Profile Details of function Tc Close Profile Details d ad xi Instances using function Tcl Close Name Underfraw Infraw Underl In 7z test sm 590 590 23 5 23 5 test_sm sm_seq0 sm_O 96 96 3 8 3 8 Figure 102 Profile Details of instance sm_0 Profile Details 4 i xi Instances with same definition as test_sm sm_seq0 sm_0 Name Underfraw Infraw Underl In test_sm sm_seq0 sm_O 279 279 11 1 11 1 Using the data to improve performance Information provided by the
148. ting a CD comparison is to open the reference Reference Dataset and test datasets wlf files Joold wif Browse 1b m Test Dataset Either dataset can be a saved wif file or a dataset that is already opened Use the Browse buttons to browse for a saved dataset or click the down arrow to select a file from the dataset selection history Use Current Simulation 1c IV Update comparison after each run C Specify Dataset E lt Previous Next gt Cancel Figure 132 Second dialog of the Comparison Wizard Comparison Wizard With the reference and test datasets selected the next step is to select a MES comparison method CD ARD MENO 1d Compare All Signals compares all signals in the test dataset against the signals in the reference dataset Compare Top Level Ports Compare Top Level Ports compares Specify Comparison by Signal the top level ports of the selected gt datasets C Specify Comparison by Region Specify Comparison by Signal opens the structure browser to allow you to select specific signals for comparison Specify Comparison by Region opens the Add Comparison by Region dialog to allow selection of a specific reference region lt Previous Next gt Cancel Viewing comparison data Comparison data displays in three places within the ModelSim GUI the Workspace pane of the Main window the Wa
149. tions Ex EH asserit check refresh 4 clkeclk refresh refresh mem state mem state S ane AS ACK JIDLE REF1 we_n we_n as nezras n cas necas n reset_n reset n assert test read response Now Cursor 1 ModelSim SE Tutorial T 142 Lesson 12 Debugging with PSL assertions 3 Examine we n in the Dataflow and Source windows Figure 127 Viewing we n in the Dataflow window E irren i CoD d SS ___ Dataflow Main window dataflow i 2 0 File Edit View Navigate Trace Tools Window b Drag we_n from the Wave window to the Dataflow window Verilog The Dataflow window shows that we n is driven by the e x a i amp e 222 4 Je e m Ke 3e SE 9 ASSIGN 106 process with inputs rw and mem state Figure 127 The E EZ 4 Gl Q e i Bo r values shown in yellow are the values for each signal at the point at which the simulation stopped 3100 ns We see that we n is StO when ASSIGN 106 mem state is REF2 As noted above we n should be St1 This is the reason for the assertion failure nw TNT VHDL The Dataflow window shows that we n is driven by the process mem state at line 61 which has inputs rw and mem state The values shown in yellow are the values for each signal at the point at which the simulation B stopped 3800 ns We see that we n is St0 when mem state is REF2 As Extended mode enabled Abentwen noted above we n should be St1 This is the reason for the a
150. to exit the editing mode Fill Data Skip Ee If you needed to cancel the edit function press the lt Esc gt key on your o word s keyboard OK _ Cancel App 00000000 00000002 00000004 00000006 00000008 0000000a 0000000c 0000000e 27 Fa iz Cama NN ModelSim SE Tutorial Lesson Wrap up T 111 Lesson Wrap up This concludes this lesson Before continuing we need to end the current simulation 1 Select Simulate gt End Simulation Click Yes ModelSim SE Tutorial T 112 Lesson 9 Viewing and initializing memories ModelSim SE Tutorial Lesson 10 Analyzing performance with the Profiler Topics The following topics are covered in this lesson Introduction Lx x 3 Design files for this lesson Related reading Compiling and loading the design Running the simulation View Profile Details Using the data to improve performance Filtering and saving the data Lesson wrap up gt Note The functionality described in this tutorial requires a profile license feature in your ModelSim license file Please contact your Mentor Graphics sales representative if you currently do not have such a feature T 114 T 114 T 114 T 115 T 116 T 118 T 119 T 120 T 121 T 113 ModelSim SE Tutorial T 114 Lesson 10 Analyzing performance with the Profiler Introduction The Profiler identifies the percentage of simulation time spent in eac
151. tware only as reasonably necessary to support the authorized use Each copy must include all notices and legends embedded in Software and affixed to its medium and container as received from Mentor Graphics All copies shall remain the property of Mentor Graphics or its licensors You shall maintain a record of the number and primary location of all copies of Software including copies merged with other software and shall make those records available to Mentor Graphics upon request You shall not make Software available in any form to any person other than employees and contractors excluding Mentor Graphics competitors whose job performance requires access You shall take appropriate action to protect the confidentiality of Software and ensure that any person permitted access to Software does not disclose it or use it except as permitted by this Agreement Except as otherwise permitted for purposes of interoperability as specified by applicable and mandatory local law you shall not reverse assemble reverse compile reverse engineer or in any way derive from Software any source code You may not sublicense assign or otherwise transfer Software this Agreement or the rights under it whether by operation of law or otherwise attempted transfer without Mentor Graphics prior written consent and payment of Mentor Graphics then current applicable transfer charges Any attempted transfer without Mentor Graphics prior written consent shall be a material
152. udes this lesson Before continuing we need to end the current simulation and close the gold wif dataset 1 Type quit sim at the VSIM gt prompt 2 Type dataset close gold at the ModelSim gt prompt Lesson wrap up T 157 ModelSim SE Tutorial T 158 Lesson 13 Waveform Compare ModelSim SE Tutorial Lesson 14 Automating ModelSim Topics The following topics are covered in this lesson Introduction Related reading Creating a simple DO file Running ModelSim in command line mode Using Tcl with ModelSim Lesson Wrap up T 160 T 160 T 161 T 163 T 166 T 168 T 159 ModelSim SE Tutorial T 160 Lesson 14 Automating ModelSim Introduction Aside from executing a couple of pre existing DO files the previous lessons focused on using ModelSim in interactive mode executing single commands one after another via the GUI menus or Main window command line In situations where you have repetitive tasks to complete you can increase your productivity with DO files DO files are scripts that allow you to execute many commands at once The scripts can be as simple as a series of ModelSim commands with associated arguments or they can be full blown Tcl programs with variables conditional execution and so forth You can execute DO files from within the GUI or you can run them from the system command prompt without ever invoking the GUI A Important This lesson assumes that you have added the
153. unter into the resource library a Click the Compile icon on the Main window toolbar b Select the parts lib library from the Library list Figure 30 c Double click counter v to compile it d Click Done You now have a resource library containing a compiled version of the counter design unit 6 Change to the testbench directory a Select File Change Directory and change to the testbench directory you created in step 2 ModelSim SE Tutorial Figure 30 Compiling into the resource library Library parts ib 5b Look in O resource library e ex EE File name counter v Files of type HDL Files v vL vhd vhdl vho hdi Y Done Default Options Edit Source Creating the project Now you will create a project that contains fcounter v the counter s testbench 1 Create the project a b c d Select File New Project Type counter in the Project Name field Click OK If a dialog appears asking about which modelsim ini file to use click Use Default Ini Add the testbench to the project a b c d Click Add Existing File in the Add items to the Project dialog Click the Browse button and select tcounter v Click Open and then OK Click Close to dismiss the Add items to the Project dialog The fcounter v file is listed in the Project tab of the Main window Compile the testbench a Right click tcounter v and select Compile gt Compile Selected Creati
154. ve it to the current directory Creating a simple DO file T 161 ModelSim SE Tutorial T 162 Lesson 14 Automating ModelSim 4 Load the simulation again and use the DO file a Type quit sim at the VSIM gt prompt b Type vsim test counter at the ModelSim gt prompt c Type do sim do at the VSIM gt prompt ModelSim executes the saved commands and draws the waves in the Wave window 5 When you are done with this exercise select File gt Quit to quit ModelSim ModelSim SE Tutorial Running ModelSim in command line mode We use the term command line mode to refer to simulations that are run from a DOS UNIX prompt without invoking the GUI Several ModelSim commands e g vsim vlib vlog etc are actually stand alone executables that can be invoked at the system command prompt Additionally you can create a DO file that contains other ModelSim commands and specify that file when you invoke the simulator 1 Create a new directory and copy the tutorial files into it Start by creating a new directory for this exercise Create the directory and copy these files into it lt install dir gt modeltech examples counter v e lt install_dir gt modeltech examples stim do We have used the Verilog file counter v in this example If you have a VHDL license use counter vhd instead 2 Create a new design library and compile the source file Again enter these commands at a DOS UNIX prompt in the new directory you created
155. ve window and the List window Viewing comparison data in the Main window Comparison information displays in three places in the Main window the Compare tab in the Workspace pane shows the region that was compared the Transcript shows the number of differences found between the reference and test datasets and the Objects pane shows comparison differences if you select the object on the Compare tab Figure 133 Viewing comparison data in the Wave window In the pathnames pane of the Wave window a timing difference is denoted by a red X Figure 134 Red areas in the waveform pane show the location of the timing differences as do the red lines in the scrollbars Annotated differences are highlighted in blue The Wave window includes six compare icons that let you quickly jump between differences Figure 135 From left to right the icons do the following find first difference find previous annotated difference find previous difference find next difference find next annotated difference find last difference Use these icons to move the selected cursor The compare icons cycle through differences on all signals To view differences for just the selected signal use tab and shift tab Viewing comparison data Figure 133 Comparison information in the Main window ae Dinu Transcript 711 illegal op received dataset open C modeltech examples co mpare verilog gold wif gold C madeltech
156. will try different methods 4 test_counter reset E4 test counter count wxxxxxxx 1 Addobjects from the Objects pane a Selectan item in the Objects pane of the Main window right click and then select Add to Wave Signals in Region ModelSim adds several signals to the Wave window 2 Undock the Wave window By default ModelSim opens Wave windows as a tab in the MDI frame of the Main window You can change the default via the Preferences dialog Tools a gt Edit Preferences See ModelSim GUI preferences GR 266 in the ModelSim GUI amp Interface Reference for more information EL a Click the undock icon on the Wave pane Figure 48 The Wave pane becomes a standalone un docked window 3 Add objects using drag and drop You can drag an object to the Wave window from many other windows and panes e g Workspace Objects and Locals a Inthe Wave window select Edit gt Select All and then Edit gt Delete b Dragan instance from the sim tab of the Main window to the Wave window ModelSim adds the objects for that instance to the Wave window c Drag a signal from the Objects pane to the Wave window d Inthe Wave window select Edit gt Select All and then Edit gt Delete 4 Add objects using a command a Type add wave at the VSIM gt prompt ModelSim adds all objects from the current region b Run the simulation for awhile so you can see waveforms ModelSim SE Tutor
157. window T 65 T 75 adding items to T 68 T 78 cursors T 70 T 85 measuring time with cursors T 70 T 85 saving format T 73 zooming T 69 T 80 Waveform Compare T 147 reference signals T 148 saving and reloading T 155 test signals T 148 working library creating T 13 T 21 X X values tracing T 95 Z zooming Wave window T 69 T 80 T 177 ModelSim SE Tutorial T 178 Index ModelSim SE Tutorial
158. you will see the Welcome to Verilog 2001 Ready For Use P ModelSim dialog Figure 1 Click Close Np 5 Select Jumpstart to Don t show this dialog again SES MSIE NOM Jumpstart M Close b Select File gt Change Directory and change to the directory you created in step 1 Figure 2 The Create a New Library dialog 3 Create the working library Create a New Library E Create This opens a dialog where you specify physical and logical names for the f a library Figure 2 You can create a new library or map to an existing C a map to an existing library library We ll be doing the former a Select File New Library b Type work in the Library Name field if it isn t entered automatically Library Name work i 3b Library Physical Name work A Cancel ModelSim SE Tutorial T 22 Lesson 2 Basic simulation c Click OK ModelSim creates a directory called work and writes a specially formatted file named info into that directory The info file must remain in the directory to distinguish it as a ModelSim library Do not edit the folder contents from your operating system all changes should be made from within ModelSim ModelSim also adds the library to the list in the Workspace Figure 3 and records the library mapping for future reference in the ModelSim initialization file modelsim ini When you pressed OK in step c above three lines were printed to t
159. your design Viewing and initializing memories Analyzing simulation performance Testing code coverage Comparing waveforms ModelSim SE Tutorial T 18 Lesson 1 ModelSim conceptual overview ModelSim SE Tutorial Lesson 2 Basic simulation Topics The following topics are covered in this lesson Introduction b x5 Design files for this lesson Related reading Creating the working design library Compiling the design Loading the design into the simulator Running the simulation Setting breakpoints and stepping in the Source window Lesson wrap up T 20 T 20 T 20 T 21 T 23 T 24 T 25 T 27 T 29 ModelSim SE Tutorial T 20 Lesson 2 Basic simulation Introduction In this lesson you will go step by step through the basic simulation flow Design files for this lesson The sample design for this lesson is a simple 8 bit binary up counter with an associated testbench The pathnames are as follows Verilog install dir modeltech examples counter v and tcounter v VHDL install dir modeltech examples counter vhd and tcounter vhd This lesson uses the Verilog files counter v and tcounter v in the examples If you have a VHDL license use counter vhd and tcounter vhd instead Or if you have a mixed license feel free to use the Verilog testbench with the VHDL counter or vice versa Related reading ModelSim User s Manual Chapter 3 Design libraries UM 57 Chapter 5 Ver

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