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USER`S MANUAL ERRATA

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1. 17 12 S3C84E5 C84E9 P84E9 MICROCONTROLLER xv List of Tables continued Table Title Page Number Number 19 1 Descriptions of Pins Used to Read Write the OTP 19 3 19 2 Comparison of 53 84 9 and S3C84E5 C84E9 Fealures 19 3 19 3 Operating Mode Selection 19 3 20 1 Power Selection Settings for 4 5 84 9 20 4 20 2 Using Single Header Pins as the Input Path for External Trigger Sources 20 4 20 3 The Port 0 0 and Port 0 1 selection Setting a 20 5 Xvi S3C84E5 C84E9 P84E9 MICROCONTROLLER List of Programming Tips Description Page Number Chapter 2 Address Spaces Using the Page Pointer for RAM clear Page 0 1 2 6 Setting the Register Pointers esras niipea ee ie a ieee ieee ne V NaN 2 10 Using the RPs to Calculate the Sum of a Series of Registers a 2 11 Addressing the Common Working Register 2 15 Standard Stack Operations Using PUSH and 2 20 Chapter 11 8 bit Timer A B To Generate 38 kHz 1 3duty signal through 3
2. 4 27 PP Register Page Pointer DFH Set 1 4 28 RPO Register Pointer 0 D6H Set 1 eene 4 29 RP1 Register Pointer 1 D7H Set 1 4 29 SPH Stack Pointer High Byte D8H Set 1 4 30 SPL Stack Pointer Low Byte DOH Set 1 4 30 STPCON Stop Control Register E5H Set 1 Bank 0 a 4 31 SYM System Mode Register DEH Set 1 a 4 32 T1CONO Timer 1 0 Control Register E8H Set 1 Bank 1 a 4 33 T1CON1 Timer 1 1 Control Register E9H Set 1 Bank 1 4 34 TACON Timer A Control Register E1H Set 1 Bank 1 a 4 35 TBCON Timer B Control Register DOH Set 1 a a 4 36 TINTPND Timer A Timer 1 Interrupt Pending Register EOH Set 1 Bank 1 4 37 UARTCON UART Control Register F6H Set 1 Bank 0 02 4 38 UARTPND UART Pending and parity control Set 1 Bank 0 4 40 WTCON Watch Timer Control Register Set 1 Bank 0 4 41 S3C84E5 C84E9 P84E9 MICROCONTROLLER xix Instruction Mnemonic ADC ADD AND BAND BCP BITC BITR BITS BOR BTJR
3. 6 57 Load WONG aie eine 6 58 Multiply Unsigned ye RR 6 59 6 60 b eyare rcu ME 6 61 L gica OR 6 62 Pop irom Stack cete uh NE ed E a REN ee 6 63 Pop User Stack 6 64 Pop User Stack 6 65 Pushto a 6 66 Push User Stack 6 67 Push User Stack Incrementing a 6 68 Reset Carry Flag isc n Sau do uay 6 69 acu 6 70 Fotate Left ou E RERO ie RE ERN Beene 6 71 Rotate Left through Carry 2 aaa a eria 6 72 Rotate Rights uu u bak asa yy 6 73 Rotate Right through 6 74 Select Bank ecc ete A 6 75 Select er 6 76 Subtract a 6 77 Set vies beeen ie Pen cy anderen eee Ee eee 6 78 Shift Right Arithmetic ere y umu u 6 79 Set Register Pointer u us ui dives ae Su de ele eae HE dte dads 6 80 Stop Operations uy u Sua shee 6 81 ee eee ee 6 82
4. R6 10H R7 34H LDEI R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is incremented by one RR6 lt RR6 1 R8 ODDH R6 10H R7 34H LDEI instruction can be used to read write the data of 64 Kbyte data memory ELECTRONICS 6 55 INSTRUCTION SET S3C84E5 C84E9 P84E9 LDCPD LDEPD Load Memory with Pre Decrement LDCPD LDEPD Operation Flags Format Examples NOTE dst src dst src rr m 1 dst src These instructions are used for block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair and is first decremented The contents of the source location are then loaded into the destination location The contents of the source are unaffected LDCPD refers to program memory and LDEPD refers to external data memory The assembler makes an even number for program memory and an odd number for external data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 2 14 F2 r Given RO 77H R6 30H and R7 OOH LDCPD RR6 RO RR6 lt RR6 1 77H the contents of RO is loaded into program memory location 2FFFH 3000H RO 77H R6 2FH R7 OFFH LDEPD RR6 RO RR6 lt 6 1 77H the contents of RO is loaded into external data memory location 2FFFH 3000H 1H LDEPD instruction can be u
5. eTe Te Foroa rose P aoo regse Pe es Pons saa regse Pa em o Pona oara regse Pa es STOP soon 29 o o o o o o olo or 0 contol eister aah be ex e o o o o o olo Pot 0 conte reger tw ove Focon r emo o o o mew ae we o Pon contol eisterfow by PIOONL 23s en o o o o o Pon 2 contol eiter igh byte Pacon a4 em o o o o o o For 2 contol eiterfow by Pacon so em o o o o o o olo Fort 2intruptconvergier Pant ew o o o For 2 iterupipending egs Femrewo ey o o o o o o contol bye racow ex ee o o o o o o olo contol register ow Pacon aaa err o eoo For contol egister igh byte ao o o o olo contol eiterfow by Pacon an rw o o o o o convoi Pant 264 o o Porta meruptpenano egs PanrTend o o o o o UART pendngvegster oante aa o o o o o UART contolregiter o o o o o ND convener
6. 4 Interrupt Level 1 IRQ1 Request Pending Bit Not pending Pending je 0 Inte rupt Level 0 IRQ0 Request Pending Bit Not pending Pending S3C84E5 C84E9 P84E9 CONTROL REGISTER OSCCON oscillator Control Register FBH Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write _ _ _ R W R W R W _ R W Addressing Mode Register addressing mode only 7 5 Not used for the S3C84E5 C84E9 P84E9 must keep always 0 4 Sub system Oscillator Driving Ability Control Bit Strong driving ability 1 Normal driving ability 3 Main System Oscillator Control Bit Main System Oscillator RUN 1 Main System Oscillator STOP 2 Sub System Oscillator Control Bit Sub system oscillator RUN Sub system oscillator STOP 4 Not used for the S3C84E5 C84E9 P84E9 must keep always 0 0 System Clock Selection Bit Main oscillator select Subsystem oscillator select ELECTRONICS 4 1 CONTROL REGISTERS S3C84E5 C84E9 P84E9 POCONH Port 0 control Register High Byte E6H Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode 7 6 Register addressing mode only P0 7 TACAP Configuration Bits o Input mode with pull up TACAP input 0 1 Input mode input Push pull output mode P0 6 TACK Configuration Bits o Input mode with pull up TACK input fo 1 Input mode TACK input Push pull output mode P0 5 T1CAPO Con
7. cese dr tut 19 1 Operating Mode 19 3 Chapter 20 Development Tools e Cl kas AS ka us dy ts 20 1 Ih rre 20 1 qme aber TIBERI UE tee platte tates RR VERE e DER DRIN P De aes 20 1 Sama Assemble esri e 20 1 552 LEBER eee PO ME ac eR entered 20 1 Target Boards ER 20 2 a tae ee e BERE UE Dea E AE enn t da roten nde 20 2 Programming Socket 20 2 TB84E5 84E9 Target Boarders 20 3 LOG oe we 20 4 SOP E o EDT 20 4 Port P0 0 P0 1 Selection SUB OSC or normal 20 4 S3C84E5 C84E9 P84E9 MICROCONTROLLER List of Figures Figure Title Page Number Number 1 1 S3C84E5 C84E9 P84E9 Block 1 3 1 2 S3C84E5 C84E9 P84E9 Pin Assignment 44 pin QFP 1 4 1 3 S3C84E5 C84E9 P84E9 Pin Assignment 42 pin SDIP 1 5 1 4 Pin Circuit RESETB uu L 1 8 1 5 Pim Circuit Type Gu cde dede edere bue vie deve ec pde 1 8 1 6 Pin Circuit Type D 0 2 0 7 P1 4 3 4 5 1 9 1 7
8. SP SP SP 2 The RET instruction is normally used to return to the previously executed procedure at the end of the procedure entered by a CALL instruction The contents of the location addressed by the stack pointer are popped into the program counter The next statement to be executed is the one that is addressed by the new program counter value No flags are affected Bytes Cycles Opcode Hex 1 10 Given SP OOFCH SP 101AH and 1234 RET PC 101AH SP OOFEH The RET instruction pops the contents of the stack pointer location OOFCH 10H into the high byte of the program counter The stack pointer then pops the value in the location OOFEH 1AH into the PC s low byte and the instruction at the location 101AH is executed The stack pointer now points to the memory location OOFEH ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET RL Rotate Left RL Operation Flags Format Examples dst C lt dst 7 dst 0 lt dst 7 dst 1 lt dst n n 0 6 The contents of the destination operand are rotated left one bit position The initial value of bit 7 is moved to the bit zero LSB position and also replaces the carry flag as shown in the figure below 2H 3 Set if the bit rotated from the most significant bit position bit 7 was 1 Set if the result is 0 cleared otherwise Set if the result bit 7 is set cleared otherwise Unaffected 2 5 V Se
9. 1 Inte Level 1 IRQ1 Enable Bit Disable mask Je Enable un mask 0 Inte rupt Level 0 IRQO Enable Bit Disable mask 1 Enable un mask NOTE When an interrupt level is masked any interrupt requests that may be issued are not recognized by the CPU ELECTRONICS 4 CONTROL REGISTERS S3C84E5 C84E9 P84E9 IPH Instruction Pointer High Byte DAH Set 1 Reset Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address High Byte The high byte instruction pointer value is the upper eight bits of the 16 bit instruction pointer address 15 8 The lower byte of the IP address is located in the IPL register DBH IPL Instruction Pointer Low Byte DBH Set1 Reset Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address Low Byte The low byte instruction pointer value is the lower eight bits of the 16 bit instruction pointer address IP7 IPO The upper byte of the IP address is located in the IPH register DAH 4 10 ELECTRONICS S3C84E5 C84E9 P84E9 CONTROL REGISTER IPR Interrupt Priority Register FFH Set 1 Bank 0 Reset Value X x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 and 1 Priority Control Bits for Interrupt
10. Push User Stack Incrementing PUSHUI Operation Flags Format Example dst src IR lt IR 1 dst src This instruction is used for user defined stacks in the register file PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dst src 3 8 83 IR R Given Register 03H register 01 05H and register 04H 2AH PUSHUI 00H 01H gt Register OOH 04H register 01H 05H register 04H 05H If the user stack pointer the register 00H for example contains the value 03H the statement PUSHUI 00H 01H increments the user stack pointer by one leaving the value 04H The 01H register value 05H is then loaded into the location addressed by the incremented user stack pointer ELECTRONICS S3C84E5 C84E9 P84E9 RCF Reset Carry Flag RCF Operation Flags Format Example RCF C 0 The carry flag is cleared to logic zero regardless of its previous value C Cleared to 0 No other flags are affected Bytes Cycles 1 4 Given C 1 or 0 The instruction RCF clears the carry flag C to logic zero ELECTRONICS INSTRUCTION SET Opcode Hex CF INSTRUCTION SET S3C84E5 C84E9 P84E9 RET Return RET Operation Flags Format Example 6 70
11. ms ms STOR r orto ester gh Bye 729 contol reiter Low Bye Poco 724 Pon 1 contol register Hoh Bye Piconi 2 Pon contol register Low Bye Froon 9 Fort 2 294 Fort 2 contlreiter Low Bye Pacon 2 Fort 2 2 mr 7 me me Ca 24 ms me Port 2 data register e AD caa eer nay aooaa ND convener oara regier Low Bye AW me R Location FCH is factory use only Location FEH is not mapped Interrupt priority register 255 4 2 ELECTRONICS S3C84E5 C84E9 P84E9 CONTROL REGISTER Table 4 3 Set 1 Bank 1 Registers RegstrName mnemonic Timer A Timer interupt pending register RW Timer Acontolregister meon RW _ Tmora rosor RW FTimerAcounierresister 1 0 data register High Bye 228 RW Timer 0 data register Low Byte TIDATMO aw Timer 101 register High Bye aw Timer 101 data register Low Byte moata RW Timer 10 sontot register moomo RW Timer 101 regse moon RW _ Timer 1 0 counter re
12. GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM 00H FFH contains the addresses of interrupt service routines that correspond to each level in the interrupt structure Vectored interrupt processing follows this sequence o ON d t mm Push the program counter s low byte value to the stack Push the program counter s high byte value to the stack Push the FLAG register values to the stack Fetch the service routine s high byte address from the vector location Fetch the service routine s low byte address from the vector location Branch to the service routine specified by the concatenated 16 bit vector address NOTE 16 bit vector address always begins at an even numbered ROM address within the range of OOH FFH NESTING OF VECTORED INTERRUPTS It is possible to nest a higher priority interrupt request while a lower priority request is being serviced do this you must follow these steps 1 Push the current 8 bit interrupt mask register IMR value to the stack PUSH IMR Load the IMR register with a new mask value that enables only the higher priority interrupt Execute an El instruction to enable interrupt processing a higher priority interrupt will be processed if it occurs When the lower priority interrupt service routine ends restore the IMR to its original value by returning the previous mask value from the stack POP IMR Execute an IRET Depending on the application you m
13. cc Oto F NOTE In the first byte of the two byte instruction format the condition code and the opcode are each four bits in length Given The carry flag 1 and LABEL_X 1FF7H JR C LABEL_X gt PC 1FF7H If the carry flag is set that is if the condition code is true the statement JR C LABEL_X will pass control to the statement whose address is currently in the program counter Otherwise the program instruction following the JR will be executed ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET LD Load LD dst src Operation dst lt src The contents of the source are loaded into the destination The source s contents are unaffected Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src r8 r R r 0toF 4 D7 Ir r opc src dst 3 6 E4 R R 6 5 R IR 6 D6 IR IM 8006006 r ELECTRONICS 6 49 INSTRUCTION SET LD Load LD Examples 6 50 Continued S3C84E5 C84E9 P84E9 Given RO 01H R1 OAH register OOH 01H register 01 20H register 02H 02H LOOP 30H and register OFFH R0 H 0H R0 01H 01H RO R1 RO RO R1 00H 01H 02H 00H 00H 0AH 00H 10H gt 00H 02H RO LOOP R1 LOOP RO R1 24 Lt RO 10H RO 20H register 01H 20H Register 01H 01H RO 01H R1 20H RO 01H RO 01H R1 OAH register 01H OAH Register OOH 20H register 01 20H Register
14. 0 o 1 Push pull output mode Alternative function mode TXD output 1 0 P1 4 RXD Configuration Bits 0 o Input mode with pull up RXD input fo 1 Input mode RXD input Push pull output mode Alternative function mode RXD output 4 16 ELECTRONICS S3C84E5 C84E9 P84E9 CONTROL REGISTER P1CONL Port 1 Control Register Low Byte E9H Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P1 3 BZOUT Configuration Bits Input mode with pull up Input mode 0 Push pull output mode Alternative function mode T1OUTO output 3 2 P1 1 T1CK0 Configuration Bits o 0 Input mode with pull up T1CK0 input Input mode input Push pull output mode 1 0 P1 0 TAOUT Configuration Bits 0 0 Input mode with pully S O LO t ERES Push pull output mode Alternative function mode TAOUT output ELECTRONICS 4 17 CONTROL REGISTERS S3C84E5 C84E9 P84E9 P2CONH Port 2 Control Register High Byte EAH Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P2 7 INT7 0 Input mode with pull up falling edge interrupt INT7 Input mode falling edge interrupt INT7 Input mode with pull up falling edge interrupt INT6 Inpu
15. 1 In mode 2 if the UARTCON 5 bit is set to 1 then the receive interrupt will not be activated if the received 9th data bit is 0 In mode 1 if UARTCON 5 1 then the receive interrut will not be activated if a valid stop bit was not received The descriptions for 8 bit and 9 bit UART mode do not include start and stop bits for serial data receive and transmit Parity enable bits PEN is located in the UARTPND register at address F4H Parity enable and parity error check can be available in 9 bit UART mode Mode 2 only Figure 13 1 UART Control Register UARTCON ELECTRONICS 13 3 UART S3C84E5 C84E9 P84E9 UART INTERRUPT PENDING REGISTER UARTPND UART interrupt pending register UARTPND is located at address It contains the UART data transmit interrupt pending bit UARTPND 0 and the receive interrupt pending bit UARTPND 1 In mode 0 of the UART module the receive interrupt pending flag UARTPND 1 is set to 1 when the 8th receive data bit has been shifted In mode 1 or 2 the UARTPND 1 bit is set to 1 at the halfway point of the stop bit s shift time When the CPU has acknowledged the receive interrupt pending condition the UARTPND 1 flag must be cleared by software in the interrupt service routine In mode 0 of the UART module the transmit interrupt pending flag UARTPND O is set to 1 when the 8th transmit data bit has been shifted In mode 1 or 2 the UARTPND O bit is set at the start of the stop bi
16. 5 5 Enable Disable Interrupt Instructions El Hmmm 5 7 System Level Interrupt Control Registers u a 5 7 Interrupt Processing Control 5 8 Peripheral Interrupt Control Registers 5 9 System Mode Register SYM 5 10 Interrupt Mask Register asao nnne apuyaya a nnne enhn nnne 5 11 Interrupt Priority Register 5 12 Interrupt Request 22 2 1 2 8 Idee iieri Sd ede ee Date ee Oo VT Te OD YE MN aO ee OUR da Oe 5 14 Interrupt Pending Function Hee nnne 5 15 Interrupt Source Polling Sequence eene nnne nnne nnn nnne 5 16 Interrupt Service Routines cree nee eI ds eerte e Pre IR rne En DP Eee on E Rene sQ 5 16 Generating Interrupt Vector Addresses 5 17 Nesting of Vectored 5 17 Chapter 6 Instruction Set EE 6 1 Data Types bee ieee eet eee ed 6 1 6 1 Addressing Modes ee
17. G 85 C Vpp Vi vn to 5 5 V 9 Table 17 7 Sub Oscillator Frequency PAGE 17 7 25 G 85 C Vpp Vi vn to 5 5 V Oscar Clock Cireut Test Condition min Max Unit Crystal Crystal oscillation frequency 32 32 768 34 kHz B L 100 pF C2 100 pF R 330 0 XT xy and XTour are connected J C1 Ji C2 with R and C by soldering ELECTRONICS 5 USER S MANUAL ERRATA S3C84E5 C84E9 P84E9 10 Table 17 8 Subsystem Oscillator crystal Stabilization Time PAGE 17 7 TA 25 L TL Tel Moo Wn sy e 11 Table 17 9 Data Retention Supply Voltage in Stop Mode PAGE 17 8 TA 25 C to 85 G Vpp Vi vR to 5 5 V 12 Table 17 10 UART Timing Characteristics in Mode 0 PAGE 17 10 Ta 25 to 85 Vpp Vi vn to 5 5 V Load capacitance 80 pF 6 ELECTRONICS S3C84E5 C84E9 P84E9 USER S MANUAL ERRATA 13 Table 17 11 A D Converter Electrical Characteristics PAGE 17 11 TA 25 C to 85 to 5 5 V Vgs OV 14 Table 17 12 LVR Low Voltage Reset Circuit Characteristics PAGE 17 12 TA 25 C 15 Figure 17 8 Operating Voltage Range PAGE 17 12 Main Oscillator Frequency CPU Clock 1 2 3 4 5 6 7 VivR 5 5 V Supply Voltage V Minimum instruction clock 1 4 Oscillator clock 16 Table 19 2 Comparison of S3P84E9 and S3C84E5 C84E9 Features PAGE 17 12 S3P84E9 S
18. disabling interrupt processing ELECTRONICS 6 37 INSTRUCTION SET S3C84E5 C84E9 P84E9 DIV pivide Unsigned DIV Operation Flags Format Examples 6 38 dst src dst src dst UPPER REMAINDER dst LOWER QUOTIENT The destination operand 16 bits is divided by the source operand 8 bits The quotient 8 bits is stored in the lower half of the destination The remainder 8 bits is stored in the upper half of the destination When the quotient is gt 28 the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect Both operands are treated as unsigned integers C Set if the V flag is set and the quotient is between 28 and 29 1 cleared otherwise Set if the divisor or the quotient 0 cleared otherwise Set if MSB of the quotient 1 cleared otherwise Unaffected 2 s V Set if the quotient is gt 28 or if the divisor 0 cleared otherwise D H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 26 10 94 RR R 26 10 95 RR IR 26 10 96 RR IM Execution takes 10 cycles if the divide by zero is attempted otherwise it takes 26 cycles Given RO 10H R1 03H R2 40H register 40H 80H DIV RRO R2 gt RO R1 40H DIV RR0 R2 gt RO R1 20H DIV RRO 20H gt RO 03H R1 80H In the first example the destination working register pair RRO contains the values 10H
19. into R8 and RR6 is decremented by one R8 R6 10H R7 32H RR6 lt RR6 1 LDED R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is decremented by one RR6 lt 6 1 R8 ODDH R6 10H R7 32H LDED instruction can be used to read write the data of 64 Kbyte data memory ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET LDCI LDEI Load Memory and Increment LDCI LDEI Operation Flags Format Examples NOTE dst src dst src dst src m rr 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then incremented automatically The contents of the source are unaffected LDCI refers to program memory and LDEI refers to external data memory The assembler makes an even number for program memory and odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given R6 10H R7 33H R8 12H program memory locations 1033H and 1034H external data memory locations 1033H ODDH and 1034H 0D5H LDCI R8 RR6 OCDH contents of program memory location 1033H is loaded into R8 and RR6 is incremented by one RR6 lt RR6 1 R8
20. vA DPSODE Register in Register One Operand A O File Instruction Example Value used in Instruction Execution Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Figure 3 1 Register Addressing Register File MSB Point to RPO ot RP1 RPO or Selected RP points to start of working register Program Memory 4 bit TERN dst EET IS block E OPCODE Working Register OPERAND Two Operand 7 J ht Instruction Example Sample Instruction ADD R1 R2 Where R1 and R2 are registers in the currently selected working register area Figure 3 2 Working Register Addressing 3 2 ELECTRONICS S3C84E5 C84E9 P84E9 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE IR In Indirect Register IR addressing mode the content of the specified register or register pair is the address of the operand Depending on the instruction used the actual address may point to a register in the register file to program memory ROM or to an external memory space see Figures 3 3 through 3 6 You can use any 8 bit register to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location Please note however that you cannot access locations in set 1 using the Indirect Register addressing mode Program Memory Register File Register ADDRESS P OPCODE Point to
21. 11 9 To generate a one pulse signal through 3 11 10 IU euge tsay Shee deena 11 11 Using the Timer B col ter ue ed URN LATER SERRE 11 12 Chapter 12 16 bit Timer 1 0 1 Using thieTimer 1 0 5 iiio pakakushasqa senate Oo Pena ut b e COE PH RTL RE COL eda buds 12 7 Chapter 14 Watch Timer Using the Watch Tier E 14 4 Chapter 15 A D Converter Configuring A D Converter 15 6 S3C84E5 C84E9 P84E9 MICROCONTROLLER xvii List of Register Descriptions Register Full Register Name Page Identifier Number ADCON A D Converter Control Register F7H Set 1 Bank 0 4 5 BTCON Basic Timer Control Register H Set 1 a 4 6 CLKCON System Clock Control Register D4H 1 4 7 FLAGS System Flags Register D5H Set 1 a 4 8 IMR Interrupt Mask Register DDH 1 4 9 IPH Instruction Pointer High Byte DAH 1 4 10 IPL Instruction Pointer Low Byte DBH 1 4 10 IPR Interrupt Priority Register FFH Set 1 Bank 0 a 4 11 IRQ Interrupt Request Register DCH 1 4 12 OSCCON Oscillator Control Register FBH Set 1 Bank 0 4 13 POCONH Port 0 Control
22. 2 In the 53 84 5 84 9 84 9 implementation interrupt types 1 and are used Figure 5 1 S3C8 Series Interrupt Types 5 2 ELECTRONICS S3C84E5 C84E9 P84E9 INTERRUPT STRUCTURE S3C84E5 C84E9 P84E9 INTERRUPT STRUCTURE The S3C84E5 C84E9 P84E9 microcontroller supports twenty one interrupt sources All of the interrupt sources have a corresponding interrupt vector address Eight interrupt levels are recognized by the CPU in this device specific interrupt structure as shown in Figure 5 2 When multiple interrupt levels are active the interrupt priority register IPR determines the order in which contending interrupts are to be serviced If multiple interrupts occur within the same interrupt level the interrupt with the lowest vector address is usually processed first The relative priorities of multiple interrupts within a single level are fixed in hardware When the CPU grants an interrupt request interrupt processing starts All other interrupts are disabled and the program counter value and status flags are pushed to stack The starting address of the service routine is fetched from the appropriate vector address plus the next 8 bit value to concatenate the full 16 bit address and the service routine is executed ELECTRONICS 5 3 INTERRUPT STRUCTURE S3C84E5 C84E9 P84E9 Levels Vectors Sources Reset Clear IRQ0 n Timer B underflow H W IRQ1 Timer A match
23. CPU Control Instructions CCF DI El IDLE NOP RCF SB0 SB1 SCF SRP src SRP0 src SRP1 src STOP ELECTRONICS INSTRUCTION SET Table 6 1 Instruction Group Summary Concluded Instruction Rotate left Rotate left through carry Rotate right Rotate right through carry Shift right arithmetic Swap nibbles Complement carry flag Disable interrupts Enable interrupts Enter mode No operation Reset carry flag Set bank 0 Set bank 1 Set carry flag Set register pointers Set register pointer 0 Set register pointer 1 Enter Stop mode 6 5 INSTRUCTION SET S3C84E5 C84E9 P84E9 FLAGS REGISTER FLAGS The flags register FLAGS contains eight bits which describe the current status of CPU operations Four of these bits FLAGS 7 FLAGS 4 can be tested and used with conditional jump instructions Two other flag bits FLAGS 3 and FLAGS 2 are used for BCD arithmetic The FLAGS register also contains a bit to indicate the status of fast interrupt processing FLAGS 1 and a bank address status bit FLAGS 0 to indicate whether register bank 0 or bank 1 is currently being addressed FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags such as Load instruction Logical and Arithmetic instructions such as AND OR XOR ADD and SUB can affect the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND
24. INT9 1 1 Push pull output mode 1 0 P4 0 INT8 Configuration Bits 0 0 Input mode with pull up falling edge interrupt INT8 0 1 Input mode falling edge interrupt 8 1 0 Input mode rising edge interrupt INT8 1 1 Push pull output mode Figure 9 12 Port 4 Low Byte Control Register PACONL ELECTRONICS 9 15 PORTS S3C84E5 C84E9 P84E9 Port 4 Interrupt Pending Register P4INTPND Set1 R W Reset value 00 7 3 Not used must keep always 0 2 P4 2 PND10 Interrupt Pending Bit 0 No interrupt pending when read Pending bit clear when write 1 Interrupt is pending when read No effect when write 1 P4 1 PND9 Interrupt Pending Bit 0 No interrupt pending when read Pending bit clear when write 1 Interrupt is pending when read No effect when write 0 P4 0 PND8 Interrupt Pending Bit 0 No interrupt pending when read Pending bit clear when write 1 Interrupt is pending when read No effect when write Figure 9 13 Port 4 Interrupt Pending Register PAINTPND Port 4 Interrupt Control Register PAINT F2H Set1 Bank0 R W Reset value 00 7 3 Not used must keep always 0 2 P4 2 External Interrupt INT10 Enable Bit 0 Disable interrupt 1 Enable interrupt 1 P4 1 External Interrupt INT9 Enable Bit 0 Disable interrupt 1 Enable interrupt 0 P4 0 External Interrupt INT8 Enable Bit 0 Disable int
25. Input mode with pull up Input mode Push pull output mode Alternative function mode ADC2 input Input mode with pull up Input mode Push pull output mode Alternative function mode ADC1 input Input mode Push pull output mode Alternative function mode ADC0 input ELECTRONICS 4 23 CONTROL REGISTERS S3C84E5 C84E9 P84E9 P4CONH Port 4 control Register High Byte FOH Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write _ _ _ _ R W R W R W R W Addressing Mode Register addressing mode only 7 4 Not used for the S3C84E5 C84E9 P84E9 must keep always 0 3 2 ES Input mode with pull up Input mode with pull up KOEN C 4 24 ELECTRONICS S3C84E5 C84E9 P84E9 CONTROL REGISTER P4CONL Port 4 Control Register Low Byte F1H Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P4 3 TBPWM Input mode with pull up Input mode with pull up falling edge interrupt INT 10 Input mode falling edge interrupt INT10 Input mode rising edge interrupt INT10 Push pull output mode Input mode with pull up falling edge interrupt INT9 Input mode falling edge interrupt INT9 o Input mode with pull up falling edge interrupt INT8 Input mode falling edge interrupt INT8 Push pull output mode ELECTRONICS 4 25 CONTROL REGISTERS S3C84E5 C84E9 P84E9 PAINT Port4 Interrupt Contro
26. Interrrupt pending Timer 1 1 overflow interrupt Timer A overflow pending bit errupt Timer A match capture interrupt pending Bit 0 No interrupt pending 0 No interrupt pending 1 Interrrupt pending 1 Interrrupt pending Timer 1 1 match capture interrupt Timer 1 0 match capture interrupt pending bit pending bit 0 No interrupt pending 0 No interrupt pending 1 Interrrupt pending 1 Interrrupt pending Timer 1 0 overflow interrupt pending bit 0 No interrupt pending 1 Interrrupt pending Figure 12 2 Timer A Timer 1 0 1 Pending Register TINTPND ELECTRONICS 12 5 16 BIT TIMER 1 0 1 S3C84E5 C84E9 P84E9 BLOCK DIAGRAM fxx 1024 fxx 256 gt xx 64 gt 8 M fxx 1 gt U 16 bit Up Counter Read Only 16 bit BH M U X T1CON 4 3 U Ky TINTPND 16 bit Timer Buffer T1OUT T1PWM 16 bit Timer Data Register T1DATAH L T1CON 4 3 Data Bus NOTES 1 When PWM mode match signal cannot clear counter 2 Pending bit is located at TINTPND register Figure 12 3 Timer 1 0 1 Functional Block Diagram 12 6 ELECTRONICS S3C84E5 C84E9 P84E9 16 BIT TIMER 1 0 1 59 PROGRAMMING TIP Using the Timer 1 0 ORG 0000h VECTOR OCAh TIM1 INT ORG 0100h INITIAL LD SYM 00h Disable Global Fast interrupt LD IMR 00001000b Enable IRQ2 interrupt LD SPH 00000000b Set stack area LD SPL 00000000b LD BTCON 1010001 1b Dis
27. RO and 03H R1 and the register R2 contains the value 40H The statement DIV RRO R2 divides the 16 bit RRO value by the 8 bit value of the R2 source register After the DIV instruction RO contains the value 03H and R1 contains 40H The 8 bit remainder is stored in the upper half of the destination register RRO RO and the quotient in the lower half R1 ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET DJNZ Decrement Jumpiif Non Zero DJNZ Operation NOTE Flags Format Example r dst rer 1 If r z 0 PC dst The working register being used as a counter is decremented If the contents of the register are not logic zero after decrementing the relative address is added to the program counter and control passes to the statement whose address is now in the PC The range of the relative address is 127 to 128 and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement In case of using DJNZ instruction the working register being used as a counter should be set at the one of location to OCFH with SRP SRPO or SRP 1 instruction No flags are affected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 jump taken rA RA 8 no jump r 0toF Given R1 02H and LOOP is the label of a relative address SRP 0C0H DJNZ R1 LOOP DJNZ is typically used to control a loop of instructions In many cases a label is used as the de
28. Shift Register fxx 16 x 16 bit BRDATA 1 Po fo o Mode r sot UART Dy Mode 2 9 bit UART fxx 16 16 bit BRDATA 1 Multiprocessor Communication 1 Enable Bit for mode 2 only Disable Enable Serial Data Receive Enable Bit Disable 1 Enable If Parity disable mode PEN 0 location of the 9th data bit to be transmitted in UART mode 2 0 or 1 If Parity enable mode PEN 1 even odd parity selection bit for transmit data in UART mode 2 0 Even parity bit generation for transmit data 1 Odd parity bit generation for transmit data If Parity disable PEN 0 location of the 9th data bit that was received in UART mode 2 0 or 1 If Parity enable mode PEN 1 even odd parity selection bit for receive data in UART mode 2 0 Even parity check for the received data 1 Odd parity check for the received data A result of parity error will be saved in RPE bit of the UARTPND register after parity checking of the received data Receive Interrupt Enable Bit Disable receive interrupt Enable receive interrupt Transmit Interrupt Enable Bit E Disable transmit interrupt Enable transmit Interrupt S3C84E5 C84E9 P84E9 CONTROL REGISTER NOTES 1 In mode 2 if the MCE UARTCON 5 bit is set to 1 then the receive interrupt will not be activated if the received 9th data bit is 0 In mode 1 if MCE 1 then the receive interrupt w
29. address the bit 1 bit 4 bit or 8 bit Bit number MSB Bit 7 LSB Bit 0 Figure 4 1 Register Description Format 4 4 ELECTRONICS S3C84E5 C84E9 P84E9 CONTROL REGISTER ADCON A D Converter Control Register F7H Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write _ R W R W R W R R W R W R W Addressing Mode Register addressing mode only 7 Not used for the S3C84E5 C84E9 P84E9 must keep always 0 6 4 A D Input Pin Selection Bits 3 End of Conversion Bit Read only ES A D conversion operation is in progress A D conversion operation is complete 2 1 Clock Source Selection Bits cops fee SSCS popa OSC 0 Start or Enable Bit ES Disable operation Start operation ELEGTRONIGS 4 5 CONTROL REGISTERS S3C84E5 C84E9 P84E9 BTCON Basic Timer Control Register D3H Set 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Watchdog Timer Function Disable Code for System Reset L1 Disable watchdog timer function Other Values Enable watchdog timer function 3 2 Basic Timer Input Clock Selection Bits Basic Timer Counter Clear Bit 1 No effect 1 Clear the basic timer counter value 0 Clock Frequency Divider Clear Bit for Basic Timer 2 o No effect 1 Clear both clock frequency dividers NOTES 1 When you write a 1 to BTCON 1 the basic timer counter v
30. rising edge interrupt INT2 1 1 Push pull output mode 3 2 P2 1 INT1 Configuration Bits 0 Input mode with pull up falling edge interrupt INT1 1 Input mode falling edge interrupt INT1 0 Input mode rising edge interrupt INT1 1 Push pull output mode 0 0 1 1 1 0 P2 0 INT0 Configuration Bits 0 0 Input mode with pull up falling edge interrupt INT0 0 1 Input mode falling edge interrupt INT0 1 0 Input mode rising edge interrupt INT0 1 1 Push pull output mode Figure 9 6 Port 2 Low Byte Control Register P2CONL ELECTRONICS 9 9 1 0 PORTS 9 10 Port 2 Interrupt Pending Register P2INTPND EDH Set1 Bank0 R W Reset value 00 7 P2 7 PND7 Interrupt Pending Bit 0 No interrupt pending when read Pending bit clear when write 1 Interrupt is pending when read No effect when write 6 P2 6 PND6 Interrupt Pending Bit 0 No interrupt pending when read Pending bit clear when write 1 Interrupt is pending when read No effect when write 5 P2 5 PND5 Interrupt Pending Bit 0 No interrupt pending when read Pending bit clear when write 1 Interrupt is pending when read No effect when write 4 P2 4 PND4 Interrupt Pending Bit 0 No interrupt pending when read Pending bit clear when write 1 Interrupt is pending when read No effect when write 3 P2 3 PND3 Interrupt Pending Bit 0 No interrupt pending when read
31. the T1CAPO pin You select the capture input by setting the value of the timer 1 0 capture input selection bit in the port 0 control register high POCONH set 1 bankO E6H Both kinds of timer 1 0 interrupts T1OVFO T1INT0 can be used in capture mode the timer 1 0 overflow interrupt is generated whenever a counter overflow occurs the timer 1 0 capture interrupt is generated whenever the counter value is loaded into the timer 1 data register By reading the captured data value T1DATAHO T1DATALO and assuming a specific value for the timer 1 0 clock frequency you can calculate the pulse width duration of the signal that is being input at the T1CAPO pin In capture mode for Timer 1 1 a signal edge that is detected at the T1CAP1 pin opens a gate and loads the current counter value into the timer 1 data register T1DATAH1 T1DATAL1 for rising edge or falling edge You can select rising or falling edges to trigger this operation The timer 1 1 also gives you capture input source the signal edge at the T1CAP1 pin You select the capture input by setting the value of the timer 1 1 capture input selection bit in the port 0 control register low POCONL set 1 bank0 E7H Both kinds of timer 1 1 interrupts T1OVF1 T1INT1 can be used in capture mode the timer 1 1 overflow interrupt is generated whenever a counter overflow occurs the timer 1 1 capture interrupt is generated whenever the counter value is loaded into the timer 1 data
32. 0 P3 7 ADCO ADC7 P1 2 710UTO lt P1 1 T1CKO gt 0 5 1 POA TIOUT1 lt Timer Counter 3 1 gt 2 1 gt P1 5 TxD 16K 32K Byte 528 Byte P1 4 RxD ROM RAM P1 3 BZOUT Watch Timer P4 0 P4 5 INT8 INT10 ADCO ADC7 P3 0 P3 7 AVREF AVss lt Eid lt lt gt 4 gt lt gt lt gt gt gt lt gt 4 lt e lt gt 4 lt gt lt gt lt lt gt 4 Figure 1 1 S3C84E5 C84E9 P84E9 Block Diagram ELECTRONICS 1 3 PRODUCT OVERVIEW PIN ASSIGNMENT XTout P0 1 XTin P0 0 TBPWM P4 3 INT10 P4 2 VDD vss Xout Xin TEST INT9 P4 1 INT8 P4 0 Figure 1 2 SSC84E5 C84E9 P84E9 Pin Assignment 44 pin QFP 1 2 3 4 5 6 7 8 9 1 1 i N 43 P0 2 T1CAP1 42 P0 3 T1CK1 41 1 P0 4 T1OUT1 40 P0 5 T1CAP0 39 L3 P0 6 TACK 38 L3 7 37 L3 P1 0 TAOUT 36 1 P1 1 T1CKO 35 P1 2 T10UTO 34 P1 3 BZOUT a 63 84 5 S3C84E9 S3P84E9 Top View 44 QFP AVref 22 P1 4 RXD P1 5 TXD P3 7 ADC7 P3 6 ADC6 P3 5 ADC5 P3 4 ADC4 P3 3 ADC3 P3 2 ADC2 P3 1 ADC1 P3 0 ADCO AVss S3C84E5 C84E9 P84E9 S3C84E5 C84E9 P84E9 PRODUCT OVERVIEW PIN ASSIGNMENT P1 0 TAOUT P1 1 T1CKO P1 2 T10UTO P1 3 BZOUT P1 4 RXD P1 5 TXD S3C84E5 P3 7 ADC7 0 0 P3 6 ADC6 TBPWM P4 3 S3C84E9
33. 02H 20H register 00H 01H Register 00H gister 00H 01H register 01H 10H Register 00H 01H register 01H register 02H 02H RO OFFH OAH Register 31H OAH RO 01H R1 OAH 02 ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET LDB Load Bit LDB LDB Operation Flags Format Examples dst src b dst b src dst 0 lt src b or dst b lt src 0 The specified bit of the source is loaded into bit zero LSB of the destination or bit zero of the source is loaded into the specified bit of the destination No other bits of the destination are affected The source is unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 47 Rb r NOTE n the second byte of the instruction format the destination or the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given RO 06H and general register OOH 05H LDB R0 00H 2 gt RO register OOH 05 LDB 00H 0 RO gt RO 06H register OOH 04H In the first example the destination working register RO contains the value 06H and the source general register OOH the value 05H The statement LD 0 00 2 loads the bit two value of the 00H register into bit zero of the RO register leaving the value 07H in the register RO In the second example is the destination register The statement LD 00H 0 RO0 loads bit zer
34. 1 RRC 01H gt Register 01H 02H register 02H 1 In the first example if the general register 00H contains the value 55H 01010101B the statement RRC rotates this value one bit position to the right The initial value of bit zero 1 replaces the carry flag and the initial value of the C flag 1 replaces bit 7 This leaves the new value 2AH 00101010 in the destination register OOH The sign flag and the overflow flag are both cleared to 0 ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET SB0 Select Bank 0 SB0 Operation Flags Format Example BANK lt 0 The SBO instruction clears the bank address flag in the FLAGS register FLAGS 0 to logic zero selecting the bank 0 register addressing in the set 1 area of the register file No flags are affected Bytes Cycles Opcode Hex 1 4 4F The statement SBO clears FLAGS 0 to 0 selecting the bank 0 register addressing ELECTRONICS 6 75 INSTRUCTION SET S3C84E5 C84E9 P84E9 SB1 Select Bank 1 SB1 Operation Flags Format Example 6 76 BANK lt 1 SB1 instruction sets the bank address flag in the FLAGS register FLAGS 0 to logic one selecting the bank 1 register addressing in the set 1 area of the register file NOTE Bank 1 is not implemented in some KS88 series microcontrollers No flags are affected Bytes Cycles Opcode Hex 1 4 The statement SB1 sets
35. 1 Register Values After RESET 8 4 9 1 S3C84E5 C84E9 P84E9 Port Configuration Overview 9 1 9 2 Port Data Register 9 2 14 1 Watch Timer Control Register WTCON Set 1 Bank 0 FAH 14 2 17 1 Absolute Maximum 17 2 17 2 Input Output 17 2 17 3 D C Electrical Characteristics 2 0080 17 3 17 4 A C Electrical 17 5 17 2 Input TIMING Tor RES EM teu tii te peine t tih 17 5 17 5 Main Oscillator Frequency 06 1 17 6 17 6 Main Oscillator Clock Stabilization Time teT4 mI 17 6 17 7 Sub Oscillator Frequency 17 7 17 8 Subsystem Oscillator crystal Stabilization Time 17 7 17 9 Data Retention Supply Voltage in Stop 17 8 17 10 UART Timing Characteristics in Mode 0 10 2 17 10 17 11 A D Converter Electrical Characteristics 17 11 17 12 LVR Low Voltage Reset Circuit
36. 12 shows a typical example of 4 bit working register addressing The high order bit of the instruction INC R6 is 0 which selects RPO The five high order bits stored in RPO 01110B are concatenated with the three low order bits of the instruction s 4 bit address 110B to produce the register address 76H 01110110B ELECTRONICS 2 15 ADDRESS SPACES S3C84E5 C84E9 P84E9 Selects RPO or RP1 Address OPCODE SER 4 bit address Register pointer provides three provides five low order bits high order bits INC Together they create an 8 bit register address Figure 2 11 4 Bit Working Register Addressing RPO RP1 Selects RPO R6 OPCODE Register Instruction 01110 address 0110 1110 INCRE 76H Figure 2 12 4 Bit Working Register Addressing Example 2 16 ELECTRONICS S3C84E5 C84E9 P84E9 ADDRESS SPACES 8 BIT WORKING REGISTER ADDRESSING You can also use 8 bit working register addressing to access registers in a selected working register area To initiate 8 bit working register addressing the upper four bits of the instruction address must contain the value 1100B This 4 bit value 1100B indicates that the remaining four bits have the same effect as 4 bit working register addressing As shown in Figure 2 13 the lower nibble of the 8 bit address is concatenated in much the same way as for 4 bit addressing Bit 3 selects either RP0 or RP1 which then supplies the five high order bits of the final address T
37. 3 6 06 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register 03H OAH ADD R1 R2 gt R1 15H R2 03H ADD R1 R2 gt R1 1CH R2 08H ADD 01H 02H gt Register 01H 24H register 02H 03H ADD 01H 02H gt Register 01H 2BH register 02H ADD 01H 25H gt Register 01H 46H In the first example the destination working register R1 contains 12H and the source working register R2 contains The statement ADD R1 R2 adds to 12H leaving the value 15H in the register R1 ELECTRONICS 6 15 INSTRUCTION SET S3C84E5 C84E9 P84E9 AND Logical AND AND dst src Operation dst lt dst AND src The source operand is logically ANDed with the destination operand The result is stored in the destination The AND operation causes a 1 bit to be stored whenever the corresponding bits in the two operands are both logic ones otherwise a 0 bit value is stored The contents of the source are unaffected Flags C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src 6 53 r Ir src dst 3 6 54 R R 55 R IR opc dst src 3 6 56 R IM Examples Given 1 12H R2 register 01H 21H register 02H register OAH AND R1 R2 gt R1 02H R2 03H AND R1 R2 gt R1 02H R2 0
38. 4 A C Electrical Characteristics 25 C to 85 C Vi to 5 5 V Parameter Symbol bol Conditions NC I 2 EE CXNI EX S Interrupt input tiNTH 5 high low width tINTL Ports 4 nRESET input Input low width NOTE User must keep more large value then min value tnt lINTH Figure 17 1 Input Timing for External Interrupts Ports 4 and 6 Figure 17 2 Input Timing for RESET ELECTRONICS 17 5 ELECTRICAL DATA S3C84E5 C84E9 P84E9 Table 17 5 Main Oscillator Frequency fosc TA 25 G 85 C Vpp 5 5 Oscilator Clock Circuit Test Condition min Max Uni 12 MHz Main crystal or Vpp to 5 5 V 1 ceramic XIN XOUT External clock main system Table 17 6 Main Oscillator Clock Stabilization Time ts74 TA 25 G 85 Vpp Vi vn to 5 5 V Oscillator Test Condition Min Typ Max Unit Main crystal fosc 400 kHz Oscillation stabilization occurs when Vpp is equal to the minimum oscillator voltage range Main ceramic External clock Xy input High and Low width ty ty main system Oscillator twarr when released by a reset 1 stabilization wait time NOTES 1 fosc is the oscillator frequency 2 The duration of the oscillator stabilization wait time when it is released by an interrupt is determined by the settings in the bas
39. 6 82 dst src dst dst src The source operand is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand C Setif a borrow occurred cleared otherwise Z Setif the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V Setif arithmetic overflow occurred that is if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Bytes Cycles Opcode Addr Mode Hex dst src 6 23 r Ir src dst 3 6 24 R R 25 R IR opc dst src 3 6 26 R IM Given R1 12H R2 03H register 01 21H register 02H 03H register O3H OAH SUB R1 R2 gt R1 R2 03H SUB R1 R2 gt R1 08H R2 03H SUB 01H 02H gt Register 01H register 02H SUB 01H 02H gt Register 01H 17H register 02H 03H SUB 01H 90H gt Register 01H 91H C S and V 1 SUB 01H 65H gt Register 01H 0BCH C and S 1 0 In the first example if he working register R1 contains the value 12H and if the register R2 contains the value 03H the statement SUB R1 R2 subtracts the sour
40. 7 Bit programmable port input or output mode ADC0 ADC7 selected by software input or push pull output Software assignable pull up Alternately can be used as analog inputs for A D converter modules 0 7 4 0 4 5 NOTE Pin numbers shown parentheses are for the 42 pin SDIP package Bit programmable port input or output mode INT8 INT10 selected by software input or push pull output TBPWM Software assignable pull up Alternatively can be used as Timer B inputs for external interrupts INT8 INT10 with noise filters and interrupt controller 1 6 ELECTRONICS S3C84E5 C84E9 P84E9 PRODUCT OVERVIEW Table 1 1 S3C84E5 C84E9 P84E9 Pin Descriptions Continued Pin Pin Pin Circuit Pin Share Name Type Description Type Number Pins INTO INT10 ADCO ADC7 AVREF 55 RxD xD BUZ Input pins for external interrupt 2 0 2 7 Alternatively used as general purpose digital P4 0 P4 2 input output port 2 4 Analog input pins for A D converter module Alternatively used as general purpose digital input output port 3 A D converter reference voltage and ground Serial data RxD pin for receive input and transmit output mode 0 Serial data TxD pin for transmit output and shift clock output mode 0 TACK TACAP TAOUT TBPWM T1CKO T1CAPO T1OUTO T1CK1 T1CAP1 T1OUT1 nRESET TEST VDD VSS XTOUT Xin Xout External clock input pins for timer 1 0 Capture in
41. ARCHITECTURE In the S8C84E5 C84E9 P84E9 implementation the upper 64 byte area of register files is expanded two 64 byte areas called set 1 and set 2 The upper 32 byte area of set 1 is further expanded two 32 byte register banks bank 0 and bank 1 and the lower 32 byte area is a single 32 byte common area set 2 is logically expanded 2 separately addressable register pages page 0 1 In case of S3C84E5 C84E9 P84E9 the total number of addressable 8 bit registers is 590 Of these 590 registers 16 bytes are for CPU and system control registers 46 bytes are for peripheral control and data registers 16 bytes are used as a shared working registers and 512 registers are for general purpose use You can always address set 1 register location regardless of which of the 2 register pages is currently selected The set 1 locations however can only be addressed using direct addressing modes The extension of register space into separately addressable areas sets banks and pages is supported by various addressing mode restrictions the select bank instructions SBO and SB1 and the register page pointer PP Specific register types and the area in bytes that they occupy in the register file are summarized in Table 2 1 Table 2 1 S3C84E5 C84E9 P84E9 Register Type Summary Register Type i Number of Bytes is aS UR ER RR ERE Sa u General purpose registers including 16 byte common working register area
42. C NOT C The carry flag C is complemented If C 1 the value of the carry flag is changed to logic zero If C 0 the value of the carry flag is changed to logic one C Complemented No other flags are affected Bytes Cycles Opcode Hex 1 4 EF Given The carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register OD5H changing its value from logic zero to logic one ELECTRONICS 6 27 INSTRUCTION SET CLR clear CLR dst Operation dst 0 Flags Format Examples 6 28 The destination location is cleared to O No flags are affected Bytes Cycles Opcode Hex dst 2 4 B0 B1 Given Register 00H 4FH register 01H 02H and register 02 CLR 00H gt Register OOH CLR 01H gt Register 01H 02H register 02H OOH S3C84E5 C84E9 P84E9 Addr Mode dst R IR In Register R addressing mode the statement CLR clears the destination register 00H value to 00 In the second example the statement 01H uses Indirect Register IR addressing mode to clear the 02H register value to ELECTRONICS S3C84E5 C84E9 P84E9 COM Complement COM Operation Flags Format Examples dst dst NOT dst INSTRUCTION SET The contents of the destination location are complemented one s complement All 15 are changed to 05 and vice versa Unaf
43. C P2 3 INT3 INT4 P2 4 P2 5 INT5 INT6 P2 6 P2 7 INT7 P4 5 AVREF AVSS P3 0 ADCO P3 1 ADC1 P3 2 ADC2 P3 3 ADC3 P3 4 ADC4 P3 5 ADC5 P3 6 ADC6 P3 7 ADC7 P1 5 TXD P1 4 RXD P1 3 BZOUT 1 2 1100 0 4 P1 1 T1CKO P1 0 TAOUT 7 0 6 P0 5 T1CAPO T1OUT1 PO 4 C3 PO S T1CK1 0 2 C3 4 4 1439065 did Figure 20 3 44 Connector Pin Assignment for 84 5 84 9 ELECTRONICS 20 5 DEVELOPMENT TOOLS S3C84E5 C84E9 P84E9 Target Board Target System J101 10 99uuoo A 5 O o 5 lt Figure 20 4 TB84E5 84E9 Adapter Cable for 44pin Connector Package 20 6 ELECTRONICS
44. ELECTRONICS 11 3 8 BIT TIMER A B S3C84E5 C84E9 P84E9 BLOCK DIAGRAM TACON 2 Overflow TACON 7 6 Data Bus TACON 0 TINTPND 1 f xx 1024 gt f xx 256 M 8 bit Up Counter TACON 3 fxx 64 U Read Only x TACK TACON 1 TAINT 8 bit Comparator Pending M x P TINTPND 0 X Timer A Buffer Reg M TAOUT TAPWM U N X Timer A Data Register TACON 5 4 Read Write Data Bus TACON 5 4 NOTES 1 When PWM mode match signal cannot clear counter 2 Pending bit is located at TINTPND register Figure 11 2 Timer A Functional Block Diagram 11 4 ELECTRONICS S3C84E5 C84E9 P84E9 8 BIT TIMER A B 8 BIT TIMER B OVERVIEW The S3C84E5 C84E9 P84E9 micro controller has an 8 bit timer called timer Timer B which can be used to generate the carrier frequency of a remote controller signal Also it can be used as the programmable buzz signal generator that makes a sound with a various frequency from 200Hz to 20kHz These various frequencies can be used to generate a melody sound Timer B has two functions Asanormal interval timer generating a timer B interrupt at programmed time intervals generate a programmable carrier pulse for a remote control signal at P4 3 BLOCK DIAGRAM TBCON 6 7 TBCON 2 PG trigger signal 0 fxx 4 f xx 8 gt fxx 64 gt TB Underflow fxx 256 gt TBUF TBPWM P4 3 TBCON 3 Repeat Control Data
45. General purpose digital I O Alternative function INT8 INT10 TBPWM Port 4 is accessed directly by writing or reading the port 4 data register P4 at location E4H in set 1 bank 0 Port 4 Control Register P4CONH P4CONL Port 4 pins are configured individually by bit pair settings in two control registers located in set 1 bank 0 P4CONL low byte F1H and P4CONH high byte FOH When you select output mode a push pull circuit is configured In input mode three different selections are available Schmitt trigger input and interrupt generation on falling signal edges Schmitt trigger input and interrupt generation on rising signal edges Schmitt trigger input with pull up resister and interrupt generation on falling signal edges Port 4 Interrupt Enable and Pending Registers P4INT P4INTPND To process external interrupts at the port 4 pins two additional control registers are provided the port 4 interrupt enable register P4INT F2H set 1 bank 0 and the port 4 interrupt pending register P4INTPND F3H set 1 bank 0 The port 4 interrupt pending register P4INTPND lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated The application program detects interrupt requests by polling the P4INTPND register at regular intervals When the interrupt enable bit of any port 4 pin is 1 a rising or falling signal edge at that pin will gener
46. LDC R0 1104H RO lt contents of program memory location 1104H RO 88H LDE R0 1104H RO e contents of external data memory location 1104H RO 98H LDC 1105H RO 11H contents of RO is loaded into program memory location 1105H 1105H 11H LDE 1105H RO 11H contents of RO is loaded into external data memory location 1105H 1105H lt 11H NOTE The LDC and the LDE instructions are not supported by masked ROM type devices ELECTRONICS 6 53 INSTRUCTION SET S3C84E5 C84E9 P84E9 LDCD LDED Load Memory and Decrement LDCD LDED Operation Flags Format Examples NOTE dst src dst src dst src r lt r i These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then decremented The contents of the source are unaffected LDCD refers to program memory and LDED refers to external data memory The assembler makes Irr an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given R6 10H R7 33H R8 12H program memory location 1033H 0CDH and external data memory location 1033H 0DDH LDCD R8 RR6 contents of program memory location 1033H is loaded
47. Lv Table 14 1 Watch Timer Control Register WTCON Set 1 Bank 0 FAH R W vs aan WTCON7 Saelect fx 256 as the watch timer clock fx Main clock Select subsystem clock as watch timer clock WTCON 6 0 Disable watch timer interrupt Enable watch timer interrupt WTCON 5 4 0 0 5 kHz buzzer BZOUT signal output o 1 1 kHz buzzer BZOUT signal output 1 0 2kHz buzzer BZOUT signal output 4 kHz buzzer BZOUT signal output WTCON 3 2 fo Set watch timer interrupt to 0 5 s fo 1 Set watch timer interrupt to 0 25 s Set watch timer interrupt 0 125 s Set watch timer interrupt to 1 955 ms WTCON 1 Disable watch timer clear frequency dividing circuits Enable watch timer WTCON 0 Interrupt is not pending clear pending bit when write Interrupt is pending NOTE Main system clock frequency fx is assumed to be 9 8304 MHz 14 2 ELECTRONICS S3C84E5 C84E9 P84E9 WATCH TIMER WATCH TIMER CIRCUIT DIAGRAM BUZZER Output BZOUT WTCON 6 WICONS WTCON 4 fW64 0 5 kHz WTINT fw32 1 kHz WTCON 3 fw16 2 kHz WTCON 2 fwa 4 kHz Enable Disable WTCON 1 WTCON 0 Circuit Frequency Clock aus WTCON 7 Selector Dividing 32768 Hz Circuit fxr fx 256 fx Main System Clock 9 8304 2 fxr Subsystem Clock 32768 Hz fw Watch timer Figure 14 1 Watch Timer Circuit Diagram ELECTRONICS 14 3 WATCH TIMER 59 PROGRAMMING TIP Using the Wat
48. P3 5 ADC5 INT10 P4 2 S3P84E9 P3 4 ADC4 VDD P3 3 ADC3 VSS P3 2 ADC2 Xout Top View P3 1 ADC1 Xin 42 SDIP P3 0 ADC0 TEST AVss INT9 P4 1 AVref INT8 P4 0 P2 7 INT7 nRESET P2 6 INT6 INTO P2 0 P2 5 INT5 INT1 P2 1 P2 4 INT4 INT2 P2 2 P2 3 INT3 TACAP PO0 7 TACK PO 6 T1CAPO P0 5 T10UT1 P0 4 T1CK1 P0 3 T1CAP1 P0 2 XTout PO 1 O1 Q Figure 1 3 S3C84E5 C84E9 P84E9 Pin Assignment 42 pin SDIP ELECTRONICS 1 5 PRODUCT OVERVIEW S3C84E5 C84E9 P84E9 PIN DESCRIPTIONS Table 1 1 S3C84E5 C84E9 P84E9 Pin Descriptions Pin Pin Circuit Type Description Type F 1 2 0 7 IO Bit programmable port input or output mode XTOUT selected by software input or push pull output D 3 TACAP Software assignable pull up resistor TACK Alternately can be used as I O for Timer T1CAPO Timer 1 0 1 P0 0 and P0 1 can alternately be T1OUT1 used for subsystem oscillator in out mode T1CK1 selected by software T1CAP1 1 0 1 5 Bit programmable port input output mode selected by software input or push pull output Software assignable pull up resistor Alternatively can be used as Timer A Timer 1 0 UART Watch Timer Buzzer output Bit programmable port input output mode INTO INT7 selected by software input or push pull output Software assignable pull up Alternately can be used as inputs for external interrupts INTO INT7 with noise filters and interrupt controller 2 0 2
49. Page Selection Bits Destination page 0 Other values Don t care 91919121 Lo o o u o 3 0 Source Register Page Selection Bits Source page 0 91919121 ro fo fo sureme SSCS Dome oo Other values Don t care NOTE In the S3C84E5 C84E9 P84E9 microcontroller the internal register file is configured as two pages Pages 0 1 The pages 0 1 are used for the general purpose register file and data register 4 28 ELECTRONICS S3C84E5 C84E9 P84E9 CONTROL REGISTER RPO Register Pointer 0 D6H Set 1 Reset Value 1 1 0 0 0 _ _ Read Write R W R W R W R W R W _ _ _ Addressing Mode Register addressing only 7 3 Register Pointer 0 Address Value Register pointer 0 can independently point to one of the 256 byte working register areas in the register file Using the register pointers RP0 and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RP0 points to address C0H in register set 1 selecting the 8 byte working register slice COH C7H 2 0 Not used for the S3C84E5 C84E9 P84E9 RP1 Register Pointer 1 D7H Set 1 Reset Value 1 1 0 0 1 _ _ _ Read Write R W R W R W R W R W _ _ _ Addressing Mode Register addressing only 7 3 Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 256 byte working register areas in the register file Using the register pointers RP0 and RP1 you can select two 8 byte
50. Pin Circuit Type D 1 P2 and 0 42 1 9 1 8 Pin Circuit Type FIPS eare eerte heehee OBS 1 10 1 9 Pin Circuit Type F P0 0 1 10 2 1 Program Memory Address Space a 2 2 2 2 Internal Register File 2 4 2 3 Register Page Pointer PP a 2 5 2 4 Set 1 Set 2 Prime Area 2 8 2 5 8 Byte Working Register Areas 2 9 2 6 Contiguous 16 Byte Working Register 2 10 2 7 Non Contiguous 16 Byte Working Register 2 11 2 8 16 Bit Register Pait dedita exe dettes u pude it 2 12 2 9 Register File 000 sao A 2 13 2 10 Common Working Register 2 14 2 11 4 Bit Working Register 2 16 2 12 4 Bit Working Register Addressing 2 16 2 13 8 Bit Working Register Addressing a 2 17 2 14 8 Bit Working Register Addressing 2 18 2 15 Stack Operations 2 5 eie ee udine 2 19 3 1 Register Addressing onere re n ann ve 3 2 3 2 Working Register Addre
51. R R A5 R IR opc dst src 3 6 A6 R IM 1 Given R1 02H and R2 03H CP R1 R2 gt Set the C and S flags The destination working register R1 contains the value 02H and the source register R2 contains the value The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occurs and the difference is negative the C and the S flag values are 1 2 Given R1 05H and R2 OAH CP R1 R2 JP UGE SKIP INC R1 SKIP LD R3 R1 In this example the destination working register R1 contains the value 05H which is less than the contents of the source working register R2 OAH The statement CP R1 R2 generates C 1 and the JP instruction does not jump to the SKIP location After the statement LD R3 R1 executes the value 06H remains in the working register R3 ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET Compare Increment and Jump on Equal Operation Flags Format Example dst src RA If dst src 0 PC RA Ir 1 The source operand is compared to subtracted from the destination operand If the result is 0 the relative address is added to the program counter and control passes to the statement whose address is now in the program counter Otherwise the instruction immediately following the CPIJE instruction is executed In either case the source pointer is incremented by one before the next i
52. Register 00H 98H 1 RR 01H gt Register 01H 02H register 02 8BH C 1 In the first example if the general register 00H contains the value 31H 00110001B the statement RR 00H rotates this value one bit position to the right The initial value of bit zero is moved to bit 7 leaving the new value 98H 10011000B in the destination register The initial bit zero also resets the C flag to 1 and the sign flag and the overflow flag are also set to 1 ELECTRONICS 6 73 INSTRUCTION SET S3C84E5 C84E9 P84E9 RRC Rotate Right through Carry RRC Operation Flags Format Examples 6 74 dst dst 7 C lt dst 0 dst n dst n 1 n 0 6 The contents of the destination operand and the carry flag are rotated right one bit position The initial value of bit zero LSB replaces the carry flag and the initial value of the carry flag replaces bit 7 MSB C Set if the bit rotated from the least significant bit position bit zero was 1 Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination is changed during the rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst Opc dst 2 4 CO R C1 IR Given Register 55H register 01H 02H register 02H 17H and C 0 RRC 00H gt Register OOH 2AH C
53. Register addressing mode You can read test the contents of the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels After a reset all IRQ status bits are cleared to 0 You can poll IRQ register values even if a DI instruction has been executed that is if global interrupt processing is disabled If an interrupt occurs while the interrupt structure is disabled the CPU will not service it You can however still detect the interrupt request by polling the IRQ register In this way you can determine which events occurred while the interrupt structure was globally disabled Interrupt Request Register IRQ DCH Set 1 R wo 5 IRQ1 RQO IRQ2 IRQ3 IRQ5 IRQ4 Interrupt level request pending bit 0 IRQ interrupt is not pending 1 IRQ interrupt is pending Figure 5 9 Interrupt Request Register IRQ 5 14 ELECTRONICS S3C84E5 C84E9 P84E9 INTERRUPT STRUCTURE INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the other that must be cleared in the interrupt service routine Pending Bits Cleared Automatically by Hardware For interrupt pending bits that are cleared automatically by hardware interrupt logic sets the corresponding pending bit to 1 when a request
54. Serial data pin Output port when reading and input port when writing Can be assigned as a input or push pull output port SCLK pen Serial clock pin Input only pin TEST Power supply for EPROM cell writing indicates that OTP enters into the writing mode When 12 5 V is applied OTP is in writing mode and when 5 V is applied OTP is in reading mode Option nRESET nRESET 18 12 Chip Initialization Vpp Vss Vpp Vss 11 12 5 6 Logic power supply pin should be tied to 5 V during programming NOTE means 44 QFP package Table 19 2 Comparison of S3P84E9 and S3C84E5 C84E9 Features OTP programming mode Vpp 5 V Vpp TEST 12 5 V LLL OPERATING MODE CHARACTERISTICS When 12 5 V is supplied to the TEST pin of the S3P84E9 the EPROM programming mode is entered The operating mode read write or read protection is selected according to the input signals to the pins listed in Table 19 3 below Table 19 3 Operating Mode Selection Criteria Vpp Vpp REG Address R W TEST MEM 14 0 5v oESFH o EPROM read protection NOTE 0 means Low level 1 means High level ELECTRONICS 19 3 S3C84E5 C84E9 P84E9 DEVELOPMENT TOOLS DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy to use development support system on a turnkey basis The development support system is composed of a host system debugging tools and supporting software For a hos
55. T1OUTO output 3 2 P1 1 T1CK0 Configuration Bits 0 0 Input mode with pull up T1CKO input 0 1 Input mode T1CKO input 1 X Push pull output mode 1 0 P1 0 TAOUT Configuration Bits 0 0 Input mode with pull up 0 1 Input mode 1 0 Push pull output mode 1 1 Alternative function mode TAOUT output Figure 9 4 Port 1 Low Byte Control Register P1CONL 9 6 ELECTRONICS S3C84E5 C84E9 P84E9 VO PORTS PORT 2 Port 2 is 8 bit I O port with individually configurable pins Port 2 pins are accessed directly by writing or reading the port 2 data register P2 at location E2H in set 1 bank 0 P2 0 P2 7 can serve as digital inputs outputs push pull or you can configure the following alternative functions General purpose digital I O Alternative function INTO INT7 Port 2 Control Register P2CONH P2CONL Port 2 has two 8 bit control registers P2CONH for 2 4 2 7 and P2CONL for 2 0 2 3 A reset clears the P2CONH and P2CONL registers to OOH configuring all pins to input mode You use control registers settings to select input or output mode push pull and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 2 control registers must also be enabled in the associated peripheral module When you select output mode a push pull circuit is configured In input mode three different selections ar
56. accessed Figure 3 8 Indexed Addressing to Program or Data Memory with Short Offset 3 8 ELECTRONICS S3C84E5 C84E9 P84E9 ADDRESSING MODES INDEXED ADDRESSING MODE Continued Register File 5 1 gt RPO or RP1 Selected block RP points Program Memory to 9 of working OFFSET register OFFSET NEXT 2 Bits aninion gt Register Register Address Point to Working Pair OPCODE Register Pair a tesi address added to p Program Memory offset LSB Selects or Data Memory 16 Bits 16 Bits OPERAND Value used in 16 Bits Instruction Sample Instructions LDG R4 1000H RR2 The values in the program address RR2 1000H are loaded into register R4 LDE R4 1000H RR2 Identical operation to LDC example except that external program memory is accessed Figure 3 9 Indexed Addressing to Program or Data Memory ELECTRONICS 3 9 ADDRESSING MODES DIRECT ADDRESS MODE DA S3C84E5 C84E9 P84E9 In Direct Address DA mode the instruction provides the operand s 16 bit memory address Jump JP and Call CALL instructions use this addressing mode to specify the 16 bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory LDC or to external data memory LDE if implemented 3 10 Program or Dat
57. as necessary Part II hardware Descriptions has detailed information about specific hardware components of the S3C84E5 C84E9 P84E9 microcontroller Also included in Part Il are electrical mechanical and development tools data It has 14 chapters Chapter 7 Clock Circuit Chapter 14 Watch Timer Chapter 8 RESET and Power Down Chapter 15 A D Converter Chapter 9 Ports Chapter 16 Low Voltage Reset Chapter 10 Basic Timer Chapter 17 Electrical Data Chapter 11 8 bit Timer A B Chapter 18 Mechanical Data Chapter 12 16 bit Timer 1 0 1 Chapter 19 53 84 9 OTP version Chapter 13 UART Chapter 20 Development Tools Two order forms are included at the back of this manual to facilitate customer order for S3C84E5 C84E9 P84E9 microcontrollers the Mask ROM Order Form and the Mask Option Selection Form You can photocopy these forms fill them out and then forward them to your local Samsung Sales Representative S3C84E5 C84E9 P84E9 MICROCONTROLLER iii Table of Contents Part Programming Model Chapter 1 Product Overview S3C8 SERIES nen ene nenne se S3C84E5 C84E9 P84E9 Microcontroller MU RERO Block Diagram obiecto oot deitas Porte a sut dh Pin Assignment decedere cobi eder aaa qaku k aa Qua RN Pin Descriptions Pin Circuits Chapter 2 Address Space
58. can also program the duration of the oscillation stabilization interval To do this you must make the appropriate control and clock settings before entering Stop mode When the Stop mode is released by external interrupt the CLKCON 4 and CLKCON 3 bit pair setting remains unchanged and the currently selected clock value is used The external interrupt is serviced when the Stop mode release occurs Following the IRET from the service routine the instruction immediately following the one that initiated Stop mode is executed Using an internal Interrupt to Release Stop Mode Activate any enabled interrupt causing stop mode to be released Other things are same as using external interrupt ELECTRONICS 8 5 RESET and POWER DOWN S3C84E5 C84E9 P84E9 How to Enter into Stop Mode There are two steps to enter into Stop mode 1 Handling OSCCON register 2 Handling STPCON register then writing Stop instruction keep the order IDLE MODE Idle mode is invoked by the instruction IDLE opcode 6FH In idle mode CPU operations are halted while some peripherals remain active During idle mode the internal clock signal is gated away from the CPU but all peripherals timers remain active Port pins retain the mode input or output they had at the time idle mode was entered There are two ways to release idle mode 1 Execute a reset All system and peripheral control registers are reset to their default values and the contents of all
59. clock This brings the S3C84E5 C84E9 P84E9 into a known operating status To ensure correct start up the user should take that Reset signal is not released before the VDD level is sufficient to allow MCU operation at the chosen frequency The nRESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance in order to allow time for internal CPU clock oscillation to stabilize The minimum required oscillation stabilization time for a Reset is approximately 6 55 ms 2 fosc fosc 10MHz When a Reset occurs during normal operation with both VDD and nRESET at High level the signal at the nRESET pin is forced Low and the reset operation starts All system and peripheral control registers are then set to their default hardware Reset values see Table 8 1 The MCU provides a watchdog timer function in order to ensure graceful recovery from software malfunction If watchdog timer is not refreshed before an end of counter condition overflow is reached the internal Reset will be activated The S3C84E5 C84E9 P84E9 has a built in low voltage Reset circuit that allows detection of power voltage drop of external VDD input level to prevent a MCU from malfunctioning in an unstable MCU power level This voltage detector works for the Reset operation of MCU This Low Voltage reset includes an analog compactor and Vref circuit The value of a detection voltage is set internally by hardware The on chip Low Voltag
60. contains detailed descriptions of the addressing modes that are supported by the S3C8 series CPU Chapter 4 Control Registers contains overview tables for all mapped system and peripheral control register values as well as detailed one page descriptions in a standardized format You can use these easy to read alphabetically organized register descriptions as a quick reference source when writing programs Chapter 5 Interrupt Structure describes the S3C84E5 C84E9 P84E9 interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part Il Chapter 6 Instruction Set describes the features and conventions of the instruction set used for all S3C8 series microcontrollers Several summary tables are presented for orientation and reference Detailed descriptions of each instruction are presented in a standard format Each instruction description includes one or more practical examples of how to use the instruction when writing an application program A basic familiarity with the information in Part will help you to understand the hardware module descriptions in Part II If you are not yet familiar with the S3C8 series microcontroller family and are reading this manual for the first time we recommend that you first read Chapters 1 3 carefully Then briefly look over the detailed information in Chapters 4 5 and 6 Later you can reference the information in Part
61. data registers are retained The reset automatically selects the slow clock fxx 16 because CLKCON 4 and CLKCON 3 are cleared to 00B If interrupts are masked a reset is the only way to release idle mode 2 Activate any enabled interrupt causing idle mode to be released When you use an interrupt to release idle mode the CLKCON 4 and CLKCON 3 register values remain unchanged and the currently selected clock value is used The interrupt is then serviced When the return from interrupt IRET occurs the instruction immediately following the one that initiated idle mode is executed 8 6 ELECTRONICS S3C84E5 C84E9 P84E9 VO PORTS I O PORTS OVERVIEW The S3C84E5 C84E9 P84E9 microcontroller has seven bit programmable I O ports PO P4 This gives total of 36 I O pins Each port can be flexibly configured to meet application design requirements The CPU accesses ports by directly writing or reading port registers No special I O instructions are required Table 9 1 gives you a general overview of the S3C84E5 C84E9 P84E9 port functions Table 9 1 S3C84E5 C84E9 P84E9 Port Configuration Overview Configuration Options Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up resistor Alternately P0 0 P0 7 can be used as I O for Timer A Timer 1 0 1 0 and P0 1 can alternately be used for subsystem oscillator in out mode selected by software Bit programmable p
62. dst 2 14 D4 IA Given RO 85H R1 21H PC 1A47H and SP 0002H CALL 3521H gt SP 0000H Memory locations OOOOH 1AH 0001H 4AH where 4AH is the address that follows the instruction CALL RRO gt SP 0000 0000 1AH 0001H 49H CALL 40H gt SP 0000H 0000H 0001H 49H In the first example if the program counter value is 1 47 and the stack pointer contains the value 0002H the statement CALL 3521H pushes the current PC value onto the top of the stack The stack pointer now points to the memory location 0000H The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed If the contents of the program counter and the stack pointer are the same as in the first example the statement CALL QRRO produces the same result except that the 49H is stored in stack location 0001H because the two byte instruction format was used The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed Assuming that the contents of the program counter and the stack pointer are the same as in the first example if the program address 0040H contains 35H and the program address 0041H contains 21H the statement CALL 40H produces the same result as in the second example ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET CCF Complement Carry Flag CCF Operation Flags Format Example
63. eue aq 11 3 METTE 11 4 BE TIMET 11 5 e CU S EEUU 11 5 BIOCK Diagram c MES 11 5 Timer B Control Register 000 000 11 6 Timer B Pulse Width 11 7 Chapter 12 16 bit Timer 1 0 1 OVOIVIOW ya ee 12 1 Function Description 2 2 deco e petes n reete astute payka T En tae kav 12 2 Timer 1 0 1 Control Register T1 CONO T1CON1 12 3 Block PIT To Va seeria Qua w i bandas pinaattia 12 6 13 UART GEM 13 1 rece eee Ie eb De ee amb au ue Peg tovc Eg eee eg iov ER 13 1 Uart Control Register 444444 0 13 2 Uart Interrupt Pending Register 13 4 Data Register UDATA cisi sec on A a rur dtd pel nex x UU eaves 13 5 Uart Baud Rate Data Register BRDATAH BRDATAL em me eee 13 6 Baud Rate Calc latioris pt E ee 13 6 Block Diagram S u u te pt Penta eee c ee iE D Pec Poche o dake 13 8 Uart Mode 0 Function 1
64. expanded 2 separately addressable register pages 1Page occupies 192 byte prime register area and the 64 byte set 2 area CPU and system control registers Mapped clock peripheral control and data registers Total Addressable Bytes ELECTRONICS 2 3 ADDRESS SPACES 2 4 Bank 0 System and Peripheral Control Registers Register Addressing Mode System and Peripheral Control Registers Register Addressing Mode General Purpose Register Register Addressing Mode S3C84E5 C84E9 P84E9 Page 0 Set 2 General Purpose Data Registers Indirect Register Indexed Mode and Stack Operations Prime Data Registers All Addressing Modes Figure 2 2 Internal Register File Organization ELECTRONICS S3C84E5 C84E9 P84E9 ADDRESS SPACES REGISTER PAGE POINTER PP The S3C8 series architecture supports the logical expansion of the physical 512 byte internal register file using an 8 bit data bus into as many as 2 separately addressable register pages Page addressing is controlled by the register page pointer PP DFH In the S3C84E5 C84E9 P84E9 microcontroller a paged register file expansion is implemented for data registers and the register page pointer must be changed to address other pages After a reset the page pointer s source value lower nibble and the destination value upper nibble are always 0000 automatically selecting page 0 as the source and destination page for register addressing Regi
65. implementing threaded code languages contents of the instruction pointer are pushed to the stack The program counter PC value is then written to the instruction pointer The program memory word that is pointed to by the instruction pointer is loaded into the PC and the instruction pointer is incremented by two No flags are affected Bytes Cycles Opcode Hex opc 1 14 1F The diagram below shows an example of how to use an ENTER statement Before After Address Data 0043 Dat pum Address Address 40 Enter Address H 41 Address H Address L 42 Address L 0022 Address H 0020 43 Address 110 i 20 IPH 00 Routine 21 IPL 50 22 Data 22 Data Memory Stack Stack ELECTRONICS 6 41 INSTRUCTION SET S3C84E5 C84E9 P84E9 EXIT Exit EXIT Operation IP lt SP SP lt SP 2 PC P lt IP 2 This instruction is useful when implementing threaded code languages The stack value is popped and loaded into the instruction pointer The program memory word that is pointed to by the instruction pointer is then loaded into the program counter and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 16 2F Example The diagram below shows an example of how to use an EXIT statement Before After Address Data Address Data IP 0050 IP Address Address Data 6 42 v 60 Main 140 IPL 50 22 Data Memory Sta
66. instruction If the AND instruction uses the Flags register as the destination then two write will simultaneously occur to the Flags register producing an unpredictable result System Flags Register FLAGS D5H Set 1 R W vs z s s 2 2 Bank address status flag BA Carry flag C _ Fast interrupt Zero flag Z status flag FS Sign flag S Half carry flag H Overflow flag V Decimal adjust flag D Figure 6 1 System Flags Register FLAGS 6 6 ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET FLAG DESCRIPTIONS C FIS BA Carry Flag FLAGS 7 C flag is set to 1 if the result from an arithmetic operation generates a carry out from or a borrow to the bit 7 position MSB After rotate and shift operations have been performed it contains the last value shifted out of the specified register Program instructions can set clear or complement the carry flag Zero Flag FLAGS 6 For arithmetic and logic operations the Z flag is set to 1 if the result of the operation is zero In operations that test register bits and in shift and rotate operations the Z flag is set to 1 if the result is logic zero Sign Flag FLAGS 5 Following arithmetic logic rotate or shift operations the sign bit identifies the state of the MSB of the result A logic zero indicates a positive number and a logic one indicates a negative number Overflow Flag FLAGS 4 The V flag is set to 1 when the r
67. is 400 ns 4 fxx If each bit conversion requires 4 clocks the conversion rate is calculated as follows 4 clocks bit x 10 bits step up time 10 clock 50 clocks 50 clock x 400 ns 20 us at 10 MHz 1 clock time 4 fxx ADCON 0 I I 50 ADC Clock Conversion Start I I l CCC OC OC I Previous ADDATAH 8 Bit ADDATAL 2 84 1 Valid I I Value lt Set up Data 40 Clock time 10 clock Figure 15 4 A D Converter Timing Diagram 15 4 ELECTRONICS S3C84E5 C84E9 P84E9 A D CONVERTER INTERNAL A D CONVERSION PROCEDURE 15 2 Analog input must remain between voltage range of 55 AVREF Configure 0 7 for analog input before A D conversions To do this you load the appropriate value to the P3CONH and P3CONL for ADCO ADC7 registers Before the conversion operation starts you must first select one of the eight input pins ADC0 ADC7 by writing the appropriate value to the ADCON register When conversion has been completed 50 clocks have elapsed the EOC ADCON 3 flag is set to 1 so that a check can be made to verify that the conversion was successful The converted digital value is loaded to the output register ADDATAH 8 bit and ADDATAL 2 bit then the ADC module enters an idle state The digital conversion result can now be read from the ADDATAH and ADDATAL register Reference Voltage Input Analog Input
68. occurs It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced The CPU acknowledges the interrupt source by sending an IACK executes the service routine and clears the pending bit to 0 This type of pending bit is not mapped and cannot therefore be read or written by application software Inthe S3C84E5 C84E9 P84E9 interrupt structure the timer B underflow interrupt IRQ0 belongs to this category of interrupts in which pending condition is cleared automatically by hardware Pending Bits Cleared by the Service Routine The second type of pending bit is the one that should be cleared by program software The service routine must clear the appropriate pending bit before a return from interrupt subroutine IRET occurs To do this a 0 must be written to the corresponding pending bit location in the source s mode or control register In the S3C84E5 C84E9 P84E9 interrupt structure pending conditions for IRQ3 IRQ4 IRQ5 IRQ6 and IRQ7 must be cleared in the interrupt service routine ELECTRONICS 5 15 INTERRUPT STRUCTURE S3C84E5 C84E9 P84E9 INTERRUPT SOURCE POLLING SEQUENCE The gt dme interrupt request polling and servicing sequence is as follows A source generates an interrupt request by setting the interrupt request bit to 1 The CPU polling procedure identifies a pending condition for that source The CPU checks the interrupt level of source The CPU generates an inte
69. pin goes to low level ELEGTRONIGS 13 11 UART S3C84E5 C84E9 P84E9 Tx Clock Write to Shift Register UARTDATA Shift Transmit TIP TB8 or Parity bit RB8 or Parity bit Start Bit Bit Detect Sample Time Shift I RIP Figure 13 8 Timing Diagram for UART Mode 2 Operation 13 12 ELECTRONICS S3C84E5 C84E9 P84E9 UART SERIAL COMMUNICATION FOR MULTIPROCESSOR CONFIGURATIONS The S3C9 series multiprocessor communication features let a master S3C84E5 C84E9 P84E9 send a multiple frame serial message to a slave device in a multi SSC84E5 C84E9 P84E9 configuration It does this without interrupting other slave devices that may be on the same serial line This feature can be used only in UART mode 2 with the parity disable mode In mode 2 9 data bits are received The 9th bit value is written to RB8 UARTCON 2 The data receive operation is concluded with a stop bit You can program this function so that when the stop bit is received the serial interrupt will be generated only if RB8 1 To enable this feature you set the MCE bit in the UARTCON registers When the MCE bit is 1 serial data frames that are received with the 9th bit 0 do not generate an interrupt In this case the 9th bit simply separates the address from the serial data Sample Protocol for Master Slave Interaction When the master device wants to transmit a block of data to one of several slaves on a serial line it firs
70. register By reading the captured data value in T1DATAH1 T1DATAL1 and assuming a specific value for the timer 1 1 clock frequency you can calculate the pulse width duration of the signal that is being input at the T1CAP1 pin 12 2 ELECTRONICS S3C84E5 C84E9 P84E9 16 BIT TIMER 1 0 1 PWM Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the T1OUTO T1OUT1 pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the timer 1 0 1 data registers In PWM mode however the match signal does not clear the counter but can generate a match interrupt Instead it runs continuously overflowing at FFFFH and then continuous increasing from 0000H Whenever an overflow occur an overflow T1OVF0 1 interrupt can be generated Although you can use the match or overflow interrupts in the PWM mode these interrupts are not typically used in PWM type applications Instead the pulse at the 10070 T1OUT1 pin is held to low level as long as the reference data value is less than or equal to lt the counter value and then the pulse is held to high level for as long as the data value is greater than gt the counter value One pulse width is equal to TIMER 1 0 1 CONTROL REGISTER T1CONO 1 You use the timer 1 0 1 control register TT CONO T1CON1 to Select the timer 1 0 1 operating mode Interval timer Ca
71. register slices at one time as active working register space After a reset RP1 points to address C8H in register set 1 selecting the 8 byte working register slice C8H CFH 2 0 Not used for the S3C84E5 C84E9 P84E9 ELECTRONICS 4 29 CONTROL REGISTERS S3C84E5 C84E9 P84E9 SPH stack Pointer High Byte D8H Set 1 Reset Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address High Byte The high byte stack pointer value is the upper eight bits of the 16 bit stack pointer address 5 15 5 8 The lower byte of the stack pointer value is located in register SPL D9H The SP value is undefined following a reset SPL stack Pointer Low Byte D9H Set 1 Reset Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address Low Byte The low byte stack pointer value is the lower eight bits of the 16 bit stack pointer address SP7 SP0 The upper byte of the stack pointer value is located in register SPH D8H The SP value is undefined following a reset 4 30 ELECTRONICS S3C84E5 C84E9 P84E9 CONTROL REGISTER STPCON Stop Control Register E5H Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 STOP Control Bits 10100101 Enable stop instruction Other values Disabl
72. resumes Pulse Width Modulation Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the TAOUT pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the Timer A data register TADATA In PWM mode however the match signal does not clear the counter Instead it runs continuously overflowing at FFH and then continues incrementing from OOH Although you can use the match signal to generate a timer A overflow interrupt interrupts are not typically used in PWM type applications Instead the pulse at the TAOUT is held to Low level as long as the reference data value is less than or equal to lt the counter value and then the pulse is held to High level for as long as the data value is greater than gt the counter value One pulse width is equal to 256 Capture Mode In capture mode a signal edge that is detected at the TACAP pin opens a gate and loads the current counter value into the Timer A data register You can select rising or falling edges to trigger this operation Timer A also gives you capture input source the signal edge at the TACAP pin You select the capture input by setting the value of the Timer A capture input selection bit in the port 0 control register POCONH set 1 bank 0 E6H When POCONH 7 6 is 00 or 01 the TACAP input or normal input is selected When
73. sources In the S3C84E5 C84E9 P84E9 interrupt structure there are twenty one possible interrupt sources When a service routine starts the respective pending bit should be either cleared automatically by hardware or cleared manually by program software The characteristics of the source s pending mechanism determine which method would be used to clear its respective pending bit ELECTRONICS 5 1 INTERRUPT STRUCTURE S3C84E5 C84E9 P84E9 INTERRUPT TYPES The three components of the S3C8 interrupt structure described before levels vectors and sources are combined to determine the interrupt structure of an individual device and to make use of its available interrupt logic There are three possible combinations of interrupt structure components called interrupt types 1 2 and 3 The types differ in the number of vectors and interrupt sources assigned to each level see Figure 5 1 Type 1 One level IRQn one vector V1 one source S1 Type 2 One level IRQn one vector V1 multiple sources S1 Sn Type 3 One level IRQn multiple vectors V1 Vn multiple sources 81 Sn Sn 1 Sn m In the S3C84E5 C84E9 P84E9 microcontroller two interrupt types are implemented Levels Vectors Sources Type 1 IRQn V1 Si 1 2 IRQn S2 S3 Sn 51 3 IRQn 52 53 NOTES 1 The number of Sn and Vn value is expandable
74. 0 3 1 DA R1 2 R1 lt 31 0 leave the value 31 BCD in the address 27H R1 ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET DEC DEC Operation Flags Format Examples Decrement dst dst dst 1 The contents of the destination operand are decremented by one C Unaffected 7 Set if the result is 0 cleared otherwise S Set if result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 00 R 01 IR Given R1 and register 10H DEC R1 gt R1 02H DEC R1 gt Register 03H OFH In the first example if the working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DEC R1 decrements the value 10H contained in the destination register by one leaving the value OFH ELECTRONICS 6 35 INSTRUCTION SET S3C84E5 C84E9 P84E9 DECW Decrement Word DECW dst Operation dst dst 1 The contents of the destination location which must be an even address and the operand following that location are treated as a single 16 bit value that is decremented by one Flags Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared ot
75. 01H 20H register 02H 03H and register 03H OAH SBC R1 R2 gt R1 OCH R2 03H SBC R1 R2 gt R1 05H R2 03H register O3H OAH SBC 01H 02H gt Register 01H 1CH register 02H SBC 01H 02H gt Register 01H 15H register 02H register O3H OAH SBC 01H 8AH gt Register 01H 95H S and V 1 In the first example if the working register R1 contains the value 10H and the register R2 the value 03H the statement SBC R1 R2 subtracts the source value 03H and the C flag value 1 from the destination 10H and then stores the result OCH in the register R1 ELECTRONICS 6 77 INSTRUCTION SET S3C84E5 C84E9 P84E9 SCF set Carry Flag SCF Operation C lt 1 The carry flag C is set to logic one regardless of its previous value Flags Setto 1 No other flags are affected Format Bytes Cycles Opcode Hex 1 4 DF Example The statement SCF sets the carry flag to 1 6 78 ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET SRA shift Right Arithmetic SRA Operation Flags Format Examples dst dst 7 lt dst 7 lt dst 0 dst n dst n 1 n 0 6 An arithmetic shift right of one bit position is performed on the destination operand Bit zero the LSB replaces the carry flag The value of bit 7 the sign bit is unchanged and is shifted into the bit position 6 C Set if the bit shifted from the LSB position bit zer
76. 1 To clear the frequency dividers write a 1 to 0 ELECTRONICS 10 1 BASIC TIMER Basic Timer Control Register BTCON D3H Set 1 R W ws 7 5 2 T2 Watchdog timer enable bit 1010B Disable watchdog function Other value Enable watchdog function Divider clear bit 0 No effect 1 Clear divider Basic timer counter clear bit 0 No effect 1 Clear BTCNT Basic timer input clock selection bit 00 fxx 4096 01 fxx 1024 10 fxx 128 11 fxx 1 Not used Figure 10 1 Basic Timer Control Register BTCON S3C84E5 C84E9 P84E9 ELEGTRONIGS S3C84E5 C84E9 P84E9 BASIC TIMER BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal BTOVF to generate a reset by setting BTCON 7 BTCON 4 to any value other than 1010B The 1010B value disables the watchdog function A reset clears BTCON to 00H automatically enabling the watchdog timer function A reset also selects the CPU clock as determined by the current CLKCON register setting divided by 4096 as the BT clock The CPU is reset whenever a basic timer counter overflow occurs During normal operation the application program must prevent the overflow and the accompanying reset operation from occurring To do this the BTCNT value must be cleared by writing a 1 to BTCON 1 at regular intervals If a system malfunction occurs due to circuit noise or some other error condit
77. 1 1 match capture interrupt T1INT1 pending condition is also cleared by hardware when it has been serviced Interval Mode match The timer 1 0 module can generate an interrupt the timer 1 0 match interrupt T1INTO T1INTO belongs to interrupt level IRQ2 and is assigned the separate vector address In interval timer mode a match signal is generated and T1OUTO is toggled when the counter value is identical to the value written to the Timer 1 reference data registers TTDATAHO and T1DATALO The match signal generates a timer 1 0 match interrupt T1INTO vector and clears the counter value The timer 1 1 module can generate an interrupt the timer 1 1 match interrupt T1INT1 belongs to interrupt level IRQ2 and is assigned the separate vector address C8H In interval timer mode a match signal is generated and T10UT1 is toggled when the counter value is identical to the value written to the Timer 1 reference data register T1DATAH1 and T1DATAL1 The match signal generates a timer 1 1 match interrupt T1INT1 vector and clears the counter value Capture Mode In capture mode for timer 1 0 a signal edge that is detected at the T1CAPO pin opens a gate and loads the current counter value into the timer 1 data registers T1DATAHO T1DATALO for rising edge or falling edge You can select rising or falling edge to trigger this operation The timer 1 0 also gives you capture input source the signal edge at
78. 1 12 ORG 0000h VECTOR OBEh TBUN_INT ORG 0100h LD SYM 00h LD IMR 00000001b LD SPH 00000000b LD SPL 00000000b LD BTCON 10100011b LD P4CONL 00000011b LD TBDATAH 80h LD TBDATAL 80h LD TBCON 11101110b El MAIN ROUTINE JR T MAIN e e e Interrupt service routine IRET END S3C84E5 C84E9 P84E9 Disable Global Fast interrupt Enable IRQO interrupt Set stack area Disable Watch dog Enable TBPWM output Enable interrupt fxx 256 Repeat Duration 6 605ms 10 MHz x tal ELECTRONICS S3C84E5 C84E9 P84E9 16 BIT 1 0 1 16 BIT TIMER 1 0 1 OVERVIEW The S3C84E5 C84E9 P84E9 has two 16 bit timer counters The 16 bit timer 1 0 1 is an 16 bit general purpose timer counter Timer 1 0 1 has three operating modes one of which you select using the appropriate T1CONO T1CON1 setting is Interval timer mode Toggle output at 0 100 1 pin Capture input mode with a rising or falling edge trigger at the T1CAPO T1CAP1 pin PWM mode T1PWMO T1PWM1 PWM output shares their output port with TT OUTO T1OUT1 pin Timer 1 0 1 has the following functional components Clock frequency divider fxx divided by 1024 256 64 8 1 with multiplexer External clock input pin T1CKO T1CK1 16 bit counter T1CNTHO LO 1 a 16 bit comparator and two 16 bit reference data register T1DATAHO LO T1DATAH1 L1 I O pins for capture input T1CAPO T1CAP1 or match output T1OUTO
79. 1 IM rO Rb 7 PUSH PUSH TM TM TM TM TM BIT R2 IR2 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b DECW DECW PUSHUD PUSHUI MULT MULT MULT LD RR1 IR1 IR1 R2 IR1 R2 R2 RR1 IR2 RR1 IM RR1 r1 x r2 RL RL POPUD POPUI DIV DIV DIV LD R1 IR1 IR2 R1 IR2 R1 R2 RR1 IR2 RR1 IM RR1 r2 x r1 A INCW INCW CP CP CP CP CP LDC RR1 IR1 r1 r2 r1 lr2 R2 R1 IR2 R1 R1 IM r1 Irr2 xL CLR CLR XOR XOR XOR XOR XOR LDC R1 IR1 r1 r2 12 R2 R1 IR2 R1 R1 IM r2 Irr2 xL C RRC RRC CPIJE LDC LDW LDW LDW LD R1 IR1 Ir r2 RA r1 Irr2 RR2 RR1 IR2 RR1 RR1 IML r1 Ir2 SRA SRA CPIJNE LDC CALL LD LD R1 IR1 Irrr2 RA r2 Irr1 IA1 IR1 IM Ir1 r2 E RR RR LDCD LDCI LD LD LD LDC R1 IR1 r1 lrr2 r1 Irr2 R2 R1 R2 IR1 R1 IM r1 Irr2 xs F SWAP SWAP LDCPD LDCPI CALL LD CALL LDC R1 IR1 r2 Irr1 r2 lrr1 IRR1 IR2 R1 DA1 r2 Irr1 xs 6 10 ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET Table 6 5 OPCODE Quick Reference Continued OPCODE MAP LOWER NIBBLE HEX ELECTRONICS 6 11 INSTRUCTION SET S3C84E5 C84E9 P84E9 CONDITION CODES The opcode of a conditional jump always contains a 4 bit field called the condition code cc This specifies under which conditions it is to execute the jump For example a conditional jump with the condition code for equal after a compare operation only jumps if the two operands are equal Condition codes are listed in Table 6 6 The carry C zero Z sign S and overflow V flags are used to control the operation of conditional jump instructio
80. 17 1 Input Timing for External Interrupts Ports 4 and 6 17 5 17 3 Clock Timing Measurement at Xy usuario 17 7 17 4 Stop Mode Release Timing Initiated by 17 8 17 5 Stop Mode Main Release Timing Initiated by Interrupts 17 8 17 6 Stop Mode Sub Release Timing Initiated by 17 9 17 7 Waveform for UART Timing Characteristics 17 10 17 8 Operating Voltage Raga u l u Dy pa 17 12 17 9 The Circuit Diagram to Improve EFT 17 12 18 1 42 SDIP 600 Package 18 1 18 2 44 QFP 1010 Package Dimensions 18 2 19 1 S3P84E9 Pin Assignments 42 SDIP 19 1 19 2 S3P84E9 Pin Assignments 44 QFP 19 2 20 1 SMDS or SK 1000 Product Configuration a 20 2 20 2 S3C84E5 S3C84E9 S3P84E9 Target Board Configuration 20 3 20 3 44 Pin Connector assignment for 4 5 84 9 20 5 20 4 TB84E5 84E9 Adapter
81. 1H read write ELECTRONICS 11 1 8 BIT TIMER A B S3C84E5 C84E9 P84E9 FUNCTION DESCRIPTION Timer A Interrupts IRQ1 Vectors C0H and C2H The timer A module can generate two interrupts the timer A overflow interrupt TAOVF and the timer A match capture interrupt TAINT TAOVF is interrupt level IRQ1 vector C2H TAINT also belongs to interrupt level IRQ1 but is assigned the separate vector address C0H A timer A overflow interrupt pending condition is automatically cleared by hardware when it has been serviced A timer A match capture interrupt TAINT pending condition is also cleared by hardware when it has been serviced Interval Timer Function The timer A module can generate an interrupt the timer A match interrupt TAINT TAINT belongs to interrupt level IRQ1 and is assigned the separate vector address C0H When the timer A match interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware In interval timer mode a match signal is generated and TAOUT is toggled when the counter value is identical to the value written to the timer A reference data register TADATA The match signal generates a timer A match interrupt TAINT vector COH and clears the counter If for example you write the value 10H to and OAH to TACON the counter will increment until it reaches 10H At this point the Timer A interrupt request is generated the counter value is reset and counting
82. 2H 23H XOR RO R1 XOR RO R1 RO R1 02H XOR 00H 01H register 02H 23H XOR 00H 54H gt Register OOH 7FH In the first example if the working register RO contains the value 0C7H and if the register R1 gt RO 0E4H R1 02H register 02H 23H XOR 00H 01H gt Register 29H register 01H 02H gt Register 08H register 01H 02H Addr Mode dst src r r r Ir R R R IR R IM contains the value 02H the statement RO0 R1 logically exclusive ORs the R1 value with the RO value and stores the result OC5H in the destination register RO ELECTRONICS S3C84E5 C84E9 P84E9 CLOCK CIRCUIT CLOCK CIRCUIT OVERVIEW The clock frequency generated for the Main clock of S3C84E5 C84E9 P84E9 by an external crystal can range from 1 MHz to 12 MHz The maximum CPU clock frequency is 12 MHz The XIN and XOUT pins connect the external oscillator or clock source to the on chip clock circuit Also the subsystem clock frequency for the Watch timer by an external crystal can range from 30 kHz to 35 kHz The XTIN and XTOUT pins connect the external oscillator or clock source to the on chip clock circuit The sub system oscillation pins XT IN and XTOUT can be used for normal digital I O pins P0 0 P0 1 if they are not used for oscillation pins SYSTEM CLOCK CIRCUIT The system clock circuit has the following components External crystal or ceramic resonator oscillation source or an exter
83. 3 84 9 there are SA 44QFP and SA 42SDIP socket adapters for it s 44QFP and 42SDIP packages respectively IBM PC AT or Compatible RS 232C Emulator SMDS2 or SK 1000 PROM OTP Writer Target gt RAM Break Display Unit System Probe Adapter Unit TB84E5 84E9 SAM8 Base Unit Target Board EVA lt gt Power Supply Unit Chip Figure 20 1 SMDS or SK 1000 Product Configuration 20 2 ELECTRONICS S3C84E5 C84E9 P84E9 DEVELOPMENT TOOLS TB84E5 84E9 TARGET BOARD TB84E5 84E9 target board is used for the S3C84E5 C84E9 and the S3P84E9 microcontroller It is supported by the SMDS2 or SK 1000 development system In Circuit Emulator Figure 20 2 TB84E5 84E9 Target Board Configuration TB84E5 84E9 To User_Vcc Idle Stop RESET e e 144 S3E84E0 EVA Chip 2 o c 0 44 Pin Connector External P0 0 P0 1 Triggers USE PORT CH1 o USE SUB OSC SM13XXA Figure 20 2 S3C84E5 S3C84E9 S3P84E9 Target Board Configuration ELECTRONICS 20 3 DEVELOPMENT TOOLS S3C84E5 C84E9 P84E9 Table 20 1 Power Selection Settings for TB84E5 84E9 To User Vcc Settings Operating Mode To User SMDS2 or SK 1000 supplies 3 TB84ES E9 Vpp to the target board evaluation chip and the target System VDD SMDS2 or SK 1000 To User SMDS2 or SK 1000 supplies Vpp only to the target board evaluation chi
84. 3 9 Uart Mode 1 Function eene n emen nhe qa yq 13 10 Mode 2 Function 1 13 11 Serial Communication for Multiprocessor Configurations 13 13 Chapter 14 Watch Timer e eres 14 1 Watch Timer Control Register WTCON 14 2 Watch Timer Circuit iu mene 14 3 viii S3C84E5 C84E9 P84E9 MICROCONTROLLER Table of Contents Continued Chapter 15 8 bit Analog to Digital Converter vette 15 1 Function 15 1 A D Converter Control Register 15 2 Internal Reference Voltage 15 4 GONVErSION Sam upay bie aaa LER ERES 15 4 Internal A D Conversion Procedure 15 5 Chapter 16 Low Voltage RESET av MR eL 16 1 Chapter 17 Electrical Data MM MER T T EM 17 1 Chapter 18 Mechanical Data o tots Bah aa e Site eh raa A e Lar cn was Loa Sh ae Ake S Tal 18 1 Chapter 19 S3P84E9 OTP Version OVOIVIGW
85. 3C84E5 C84E9 Operating voltage Viyg to 5 5 V to 5 5 V ELECTRONICS 7 S3C84E5 C84E9 P84E9 8 BIT CMOS MICROCONTROLLERS USER S MANUAL Revision 1 1 ELECTRONICS Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages S3C84E5 C84E9 P84E9 8 Bit CMOS Microcontrollers User s Manual Revision 1 1 Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each custom
86. 3H AND 01H 02H gt Register 01H 01H register 02H 03H AND 01H 02H gt Register 01H register 02H 03H AND 01H 25H gt Register 01H 21H In the first example the destination working register R1 contains the value 12H and the source working register R2 contains 03H The statement AND R1 R2 logically ANDs the source operand 03H with the destination operand value 12H leaving the value 02H in the register R1 6 16 ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET BAND Bit AND BAND BAND Operation Flags Format Examples dst src b dst b src dst 0 lt dst 0 AND src b or dst b lt dst b AND src 0 The specified bit of the source or the destination is logically ANDed with the zero bit LSB of the destination or the source The resultant bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected C Unaffected Z Setif the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src dst 3 6 67 Rb ro NOTE Inthe second byte of the 3 byte instruction formats the destination or the source address is four bits the bit address b is three bits and the LSB address value is one bitin length Given H1 07H and register 01H 05H BAND R1 01H 1 gt R1 06H register 01H 05H BAND 01H 1 R1 gt Register 01H 05H
87. 4 12 2 Timer A Timer 1 0 1 Pending Register TINTPND 12 5 12 3 Timer 1 0 1 Functional Block 12 6 13 1 UART Control Register 13 3 13 2 UART Interrupt Pending Register UARTPND seem 13 4 13 3 UART Data Register 13 5 13 4 UART Baud Rate Data Register BRDATAH BRDATAL 13 6 13 5 UART Functional Block eee 13 8 13 6 Timing Diagram for UART Mode 0 Operation 13 9 13 7 Timing Diagram for UART Mode 1 Operation 13 10 13 8 Timing Diagram for UART Mode 2 Operation 13 12 13 9 Connection Example for Multiprocessor Serial Data Communications 13 14 14 1 Watch Timer Circuit 14 3 15 1 A D Converter Control Register ADCON 15 2 15 2 A D Converter Data Register ADDATAH 15 3 15 3 A D Converter Circuit 15 3 15 4 A D Converter Timing Diagram 15 4 15 5 Recommended A D Converter Circuit for Highest Absolute 15 5 16 1 Low Voltage Reset 16 2
88. 5 4 Interrupt Function 5 8 5 5 System Mode Register 5 5 10 5 6 Interrupt Mask Register IMR 5 11 5 7 Interrupt Request Priority 5 12 5 8 Interrupt Priority Register 5 13 5 9 Interrupt Request Register 5 14 6 1 System Flags Register FLAGS a 6 6 7 1 Main Oscillator Circuit Crystal or Ceramic Oscillator 7 1 7 2 Sub System Oscillator Circuit Crystal 7 1 7 3 System Clock Circuit Diagrami es u n aS OA m ee een 7 2 7 4 System Clock Control Register 7 3 7 5 Oscillator Control Register 05 7 4 7 6 STOP Control Register 7 4 9 1 Port 0 High Byte Control Register 9 3 9 2 Port 0 Low Byte Control Register POCONL a 9 4 9 3 Port 1 High Byte Control Register 9 5 9 4 Port 1 Low Byte Control Register 9 6 9 5 Port 2 High Byte Control Register P2CONH a 9 8 9 6 Port 2 Low Byte Control Register 2 9 9 9 7 Port 2 Interrupt Pending
89. 53 84 5 84 9 84 9 microcontroller pages 0 1 are implemented Pages 0 1 contain all of the addressable registers in the internal register file Page 0 1 Page 0 1 Register Addressing Only All Indirect Register Addressing Indexed Addressing Modes Modes Can be pointed by Register Pointer Figure 2 9 Register File Addressing ELECTRONICS 2 13 ADDRESS SPACES S3C84E5 C84E9 P84E9 COMMON WORKING REGISTER AREA COH CFH After a reset register pointers RPO and automatically select two 8 byte register slices in set 1 locations CFH as the active 16 byte working register block RPO COH C7H RP1 C8H CFH This 16 byte address range is called common area That is locations in this area can be used as working registers by operations that address any location on any page in the register file Typically these working registers serve as temporary buffers for data operations between different pages Following a hardware reset register pointers RPO and point to the common working register area locations COH CFH APO RP1 Figure 2 10 Common Working Register Area 2 14 ELECTRONICS S3C84E5 C84E9 P84E9 ADDRESS SPACES PROGRAMMING TIP Addressing the Common Working Register Area As the following examples show you should access working registers in the common area locations COH CFH using working register addressing mode only Examples 1 1 LD 0C2H 40H Invalid a
90. 7 6 is set to 1X normal push pull output is selected Both kinds of timer A interrupts can be used in capture mode the timer A overflow interrupt is generated whenever a counter overflow occurs the timer A match capture interrupt is generated whenever the counter value is loaded into the Timer A data register By reading the captured data value in TADATA and assuming a specific value for the timer A clock frequency you can calculate the pulse width duration of the signal that is being input at the TACAP pin 11 2 ELECTRONK S S3C84E5 C84E9 P84E9 8 BIT TIMER A B TIMER A CONTROL REGISTER TACON You use the timer A control register TACON to Select the timer A operating mode interval timer capture mode and PWM mode Select the timer A input clock frequency Clear the timer A counter TACNT Enable the timer A overflow interrupt or timer A match capture interrupt Clear timer A match capture interrupt pending conditions TACON is located in set 1 Bank 1 at address E1H and is read write addressable using Register addressing mode A reset clears TACON to 00H This sets timer A to normal interval timer mode selects an input clock frequency of fxx 1024 and disables all timer A interrupts You can clear the timer A counter at any time during normal operation by writing a 1 to TACON 3 The timer A overflow interrupt TAOVF is interrupt level IRQ1 and has the vector address C2H When a timer A overflow interru
91. A F5H The start and stop bits are generated automatically by hardware Mode 1 Receive Procedure 1 Select the baud rate to be generated by 16 bit BRDATA 2 Select mode 1 and set the RE Receive Enable bit in the UARTCON register to 1 3 The start bit low 0 condition at the RxD P1 4 will cause the UART module to start the serial data receive operation Tx pan nnnmnnmnnsnsnnnmn Write to Shift Register UDATA gange Do y re X os X ps X 07 y Transmit TIP URUS C D c Ge Di AU suoma sensors TTL TTTLTTTLTTTLTTTLTTTLITTLITTL TITLITTI Ln nm nn RIP Figure 13 7 Timing Diagram for UART Mode 1 Operation 13 10 ELECTRONICS S3C84E5 C84E9 P84E9 UART UART MODE 2 FUNCTION DESCRIPTION In mode 2 11 bits are transmitted through the TxD pin or received through the RxD pin Each data frame has four components Start bit 0 8 data bits LSB first Programmable 9th data bit or parity bit Stop bit 1 lt In parity disable mode PEN 0 gt The 9th data bit to be transmitted be assigned a value of 0 or 1 by writing the TB8 bit UARTCON 3 When receiving the 9th data bit that is received is written to the RB8 bit UARTCON 2 while the stop bit is ignored The baud rate for mode 2 is fosc 16 x 16 bit BRDATA 1 clock frequency lt In parity enable mode PEN 1 gt The 9th data bit to be transmitted can be
92. AGS 6 result together with an INCW instruction To avoid this problem it is recommended to use the INCW instruction as shown in the following example LOOP INCW RRO LD R2 R1 OR R2 R0 JR NZ LOOP ELECTRONICS 6 45 INSTRUCTION SET S3C84E5 C84E9 P84E9 IRET Interrupt Return IRET Operation Flags Format Example NOTE 6 46 IRET Normal RET Fast FLAGS SP PC IP SP SP 1 FLAGS lt FLAGS PC SP FIS 0 SP SP 2 SYM 0 lt 1 This instruction is used at the end of an interrupt service routine It restores the flag register and the program counter It also re enables global interrupts A normal IRET is executed only if the fast interrupt status bit FIS bit one of the FLAGS register OD5H is cleared 0 If a fast interrupt occurred IRET clears the FIS bit that was set at the beginning of the service routine All flags are restored to their original settings that is the settings before the interrupt occurred IRET Bytes Cycles Opcode Normal Hex 1 12 IRET Bytes Cycles Opcode Fast Hex 1 6 BF In the figure below the instruction pointer is initially loaded with 100H in the main program before interrupt are enabled When an interrupt occurs the program counter and the instruction pointer are swapped This causes the PC to jump to the address 100H and the IP to keep the return address The last instruction in the service routine is normally a ju
93. AOUT P1 1 T1CKO P1 2 T1OUTO P1 3 BZOUT P1 4 RXD P1 5 TXD P3 7 ADC7 XTin P0 0 P3 6 ADC6 SDAT TBPWM P4 3 P3 5 ADC5 SCLK INT10 P4 2 1 S3P84E9 3 P3 4 ADC4 VDD P3 3 ADC3 vss Top View P3 2 ADC2 Xout 42 SDIP P3 1 ADC1 Xin 2 P3 0 ADCO VPP TEST AVss INT9 P4 1 AVref INT8 P4 0 P2 7 INT7 nRESET P2 6 INT6 2 0 P2 5 INT5 INT1 P2 1 P2 4 INT4 INT2 P2 2 P2 3 INT3 TACAP PO 7 TACK P0 6 T1CAPO P0 5 T10UT1 P0 4 T1CK1 P0 3 T1CAP1 P0 2 XTout PO 1 O G N Figure 19 1 S3P84E9 Pin Assignments 42 SDIP Package ELECTRONICS 19 1 OTP VERSION S3C84E5 C84E9 P84E9 43 PO 2 T1CAP1 42 P0 3 T1CK1 41 P0 4 T1OUT1 40 L3 P0 5 T1CAP0 39 1 6 38 1 PO 7 TACAP 37 P1 0 TAOUT 36 1 P1 1 T1CKO 35 1 21100 0 34 Fa P1 3 BZOUT XTout PO 1 0 0 SDAT TBPWM P4 3 SCLK INT10 P4 2 VDD P1 4 RXD P1 5 TXD P3 7 ADC7 P3 6 ADC6 S3P84E9 P3 5 ADC5 P3 4 ADC4 Top View P3 3 ADC3 44 QFP P3 2 ADC2 P3 1 ADC1 P3 0 ADCO AVss O vss Xout Xin VPP TEST INT9 P4 1 INT8 P4 0 GQ N nRESET Cj 12 NTO P2 0 C3 13 NT1 P2 1 C3 14 NT2 P2 2 15 NT3 P2 3 C3 16 NT4 P2 4 17 NT5 P2 5 C3 18 NT6 P2 6 C3 19 NT7 P2 7 C3 20 AVref C 22 Figure 19 2 S3P84E9 Pin Assignments 44 QFP Package 19 2 ELECTRONICS S3C84E5 C84E9 P84E9 OTP VERSION Table 19 1 Descriptions of Pins Used to Read Write the OTP Main Chip During Programming Pin E
94. ATAH F8H Set 1 Bank 0 Read only Conversion Data Register Low Byte ADDATAL F9H Set 1 Bank 0 Read only Figure 15 2 A D Converter Data Register ADDATAH ADDATAL ADCON 4 6 Select one input pin of the assigned i EN ADCON 2 1 To ADCON 3 i EOC Flag Clock 8 hod lt Selector fxx ADCON 0 ADC Enable Analog Comparator Successive Approximation Logic Input Pins ADCO ADC7 P3 0 P3 7 ADCON 0 A D Conversion enable 10 bit result is loaded into A D Conversion Data Register xs hi Conversion Result 10 bit D A ADDATAH Converter ADDATAL To Data bus Figure 15 3 A D Converter Circuit Diagram ELECTRONICS 15 3 A D CONVERTER S3C84E5 C84E9 P84E9 INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block the analog input voltage level is compared to the reference voltage The analog input level must remain within the range AVSS to AVREF AVREF VDD Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step The reference voltage level for the first bit conversion is always 1 2 AVREF CONVERSION TIMING The A D conversion process requires 4 steps 4 clock edges to convert each bit and 10 clocks to step up A D conversion Therefore total of 50 clocks is required to complete a 10 bit conversion With a 10 MHz CPU clock frequency one clock cycle
95. BDATAL 7FH TBDATAH 7FH Figure 11 6 Timer B Output Flip Flop Waveforms in Repeat Mode 11 8 ELECTRONK S S3C84E5 C84E9 P84E9 8 BIT TIMER A B PROGRAMMING TIP To Generate 38 kHz 1 3duty signal through P4 3 This example sets Timer B to the repeat mode sets the oscillation frequency as the Timer B clock source and TBDATAH and TBDATAL to make a 38 kHz 1 3 Duty carrier frequency The program parameters are 8 795 us 17 59 us lt O 37 9 kHz 1 3 Duty is used in repeat mode Oscillation frequency is 16 MHz 0 0625 us fx fxx 4 4MHz 0 25 us TBDATAH 8 795 us 0 25 us 35 18 TBDATAL 17 59 us 0 25 us 70 36 Set P4 3 to TBPWM mode ORG 0100H Reset address START DI LD TBDATAL 35 1 Set 17 5us LD TBDATAH 70 1 Set 8 75 us LD TBCON 00100111B Clock Source fxx 4 Disable Timer B interrupt Select repeat mode for Timer B Start Timer B operation Set Timer B Output flip flop T FF high LD P4CONLH 03H Set P4 3 to TBPWM mode This command generates 38 kHz 1 3 duty pulse signal through P4 3 ELECTRONICS 11 9 8 BIT TIMER A B S3C84E5 C84E9 P84E9 PROGRAMMING TIP generate one pulse signal through P4 3 This example sets Timer B to the one shot mode sets the oscillation frequency as the Timer B clock source and TBDATAH and TBDATAL to make a 40us width pulse The program parameters are Timer is used on
96. Bus Data Bus NOTE In case of setting TBCON 5 4 at 10 the value of the TBDATAL register is loaded into the 8 bit counter when the operation of the timer B starts And then if a underflow occurs in the counter the value of the TBDATAH register is loaded into the value of the 8 bit counter However if the next borrow occurs the value of the TBDATAL register is loaded into the value of the 8 bit counter To output TBPWM as carrier wave you have to set P4CONL 7 6 as 11 Figure 11 3 Timer B Functional Block Diagram ELECTRONICS 11 5 8 BIT TIMER A B S3C84E5 C84E9 P84E9 TIMER B CONTROL REGISTER TBCON Timer B Control Register TBCON DOH Set 1 Bank 0 R W input clock selection bit Timer B output flip flop 00 fxx 4 control bit 01 fxx 8 0 T FF is low 10 fxx 64 1 T FF is high 11 fxx 256 Timer B mode selection bit Timer B interrupt time selection bit 0 One shot mode 00 Elapsed time for low data value 1 Repeating mode 01 Elapsed time for high data value 10 Elapsed time for low and high data value Timer B start stop bit 11 Invaild setting 0 Stop timer B 1 Start timer B Timer B interrupt enable bit 0 Disable interrupt 1 Enable interrupt Figure 11 4 Timer B Control Register TBCON Timer B Data High Byte Register TBDATAH D1H Set 1 Bank 0 R W Reset Value FFh Timer B Data Low Byte Register TBDATAL D2H Set 1 Bank 0 R W Reset Valu
97. Bytes Cycles Opcode Addr Mode Hex dst src 6 43 r Ir src dst 3 6 44 R R 45 R IR opc dst src 3 6 46 R IM Given RO 15H R1 2AH R2 01H register OOH 08H register 01 37H and register 08H 8AH OR RO R1 gt RO SFH R1 2AH OR RO R2 gt RO 37H R2 01H register 01H 37H OR 00H 01H gt Register 00H register 01H 37H OR 01H 00H gt Register OOH 08H register 01 OBFH OR 00H 02H gt Register OOH OAH In the first example if the working register RO contains the value 15H and the register R1 the value 2AH the statement OR RO R1 logical ORs the RO and R1 register contents and stores the result in the destination register RO Other examples show the use of the logical OR instruction with various addressing modes and formats ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET POP Pop from Stack POP Operation Flags Format Examples dst dst SP SP SP 1 The contents of the location addressed by the stack pointer are loaded into the destination The stack pointer is then incremented by one No flags are affected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 50 R 51 IR Given Register 01H register 01 1BH SPH 0D8H SPL 0D9H OFBH and stack register 0FBH 55H POP 00H gt Register OOH 55H SP OOFCH POP 00H gt Register OOH 01H register 01H 55H SP OOFCH In the first example th
98. C dst The specified bit within the source operand is tested If it is a 0 the relative address is added to the program counter and control passes to the statement whose address is currently in the program counter Otherwise the instruction following the BTJRF instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode note Hex dst src dst 3 10 37 RA NOTE Inthe second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 O7H BTJRF SKIP R1 3 gt PC jumps to SKIP location If the working register R1 contains the value 07H 00000111 the statement BTJRF SKIP R1 3 tests bit 3 Because it is 0 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 23 INSTRUCTION SET S3C84E5 C84E9 P84E9 BTJRT Bit Test Jump Relative on True BTJRT Operation Flags Format Example dst src b If src b is a 1 then PC PC dst The specified bit within the source operand is tested If it is a 1 the relative address is added to the program counter and control passes to the statement whose address is now in the PC Otherwise the instruction following the BTJRT instruction is executed No flags are affected Bytes Cycles Op
99. C84E9 P84E9 VO PORTS PORT 0 Port 0 is 8 bit I O port that you can use two ways General purpose digital I O Alternative function TACAP TACK TICAP0 T1OUT1 T1CK1 T1CAP1 XTIN XTOUT Port 0 is accessed directly by writing or reading the port 0 data register PO at location E0H in set 1 bank 0 Port 0 Control Register POCONH POCONL Port 0 has two 8 bit control registers POCONH for PO 4 P0 7 and POCONL for 0 0 3 A reset clears the POCONH and POCONL registers to and configuring all pins to input modes You use control registers settings to select input or output mode push pull and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 0 control registers must also be enabled in the associated peripheral module Port 0 Control Register High Byte POCONH E6H Seti R W Reset value 00 7 6 7 Configuration Bits 0 0 Input mode with pull up TACAP input 0 1 Input mode TACAP input 1 X Push pull output mode 5 4 PO 6 TACK Configuration Bits 0 0 Input mode with pull up TACK input 0 1 Input mode TACK input 1 X Push pull output mode 3 2 P0 5 T1CAP0 Configuration Bits 0 0 Input mode with pull up T1CAPO input 0 1 Input mode T1CAPO input 1 X Push pull output mode 1 0 PO 4 T1OUT1 Configuration Bits 0 0 Input mode wi
100. Cable for 44pin Connector Package 20 6 S3C84E5 C84E9 P84E9 MICROCONTROLLER xiii List of Tables Table Title Page Number Number 1 1 S3C84E5 C84E9 P84E9 Pin 1 6 2 1 S3C84E5 C84E9 P84E9 Register Type Summary 2 3 4 1 an hero be a ten aa u etie 4 1 4 2 Set l Bank 0 R gisters u e e eee eae cade te teer etu tee ERE eee TR 4 2 4 3 Set 1 Bank T Registers uti Saga akawa Qasa a aea baa 4 3 5 1 lt i md 5 6 5 2 Interrupt Control Register Overview 5 7 5 3 Interrupt Source Control and Data 5 9 6 1 Instruction Group Summary 6 2 6 2 Flag Notation 6 8 6 3 Instruction Set SYMONS rn ree 6 8 6 4 Instruction Notation Conventions 6 9 6 5 OPCODE Quick 2100099 nennen nnne 6 10 6 6 Condition C O6des 6 12 8 1 S3C84E5 C84E9 P84E9 Set 1 Register Values After RESET 8 2 8 2 S3C84E5 C84E9 P84E9 Set 1 Bank 0 Register Values After RESET 8 3 8 3 S3C84E5 C84E9 P84E9 Set 1 Bank
101. E9 P84E9 Table 6 2 Flag Notation Conventions Flag Deseription C 2 5 V D H 0 1 6 8 Carry flag Zero flag Sign flag Overflow flag Decimal adjust flag Half carry flag Cleared to logic zero Set to logic one Set or cleared according to operation Value is unaffected Value is undefined Table 6 3 Instruction Set Symbols Destination operand Source operand Indirect register address prefix Program counter Instruction pointer Flags register D5H Register pointer Immediate operand or register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET Table 6 4 Instruction Notation Conventions Condition code Working register only Bit b of working register Bit 0 LSB of working register Working register pair Register or working register Bit b of register or working register Register pair or working register pair Indirect addressing mode Indirect working register only Indirect register or indirect working register Indirect working register pair only Indirect register pair or indirect working register pair Indexed addressing mode Indexed short offset addressing mode Indexed long offset addressing mode Direct addressing mode Relative addressing mode Immediate addressing mode Immediate long addressing mode ELECTRONICS See list of condition codes in Table 6 6
102. ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET LDC LDE Load Memory LDC LDE Continued Examples Given RO 11H R1 34H R2 01H R3 04H Program memory locations 0103H 0104H 0105 6DH and 1104H 88H External data memory locations 0103H 5FH 0104H 2 0105 7DH and 1104H 98H LDC RO RR2 RO lt contents of program memory location 0104H RO R2 01H 04H LDE RO RR2 RO lt contents of external data memory location 0104H RO 2 R2 01H R3 04H LDC RR2 RO 11H contents of RO is loaded into program memory location 0104H RR2 RO R2 change LDE RR2 RO 11H contents of RO is loaded into external data memory location 0104H RR2 RO R2 R3 change LDC RO 01H RR2 RO lt contents of program memory location 0105H 01H RR2 RO 6DH R2 01H R3 04H LDE RO 01H RR2 RO lt contents of external data memory location 0105H 01H RR2 RO 7DH R2 01H 04H LDC 01H RR2 RO 11H contents of RO is loaded into program memory location 0105H 01H 0104H LDE 01H RR2 R0 11H contents of RO is loaded into external data memory location 0105H 01H 0104H LDC R0 4 1000H RR2 RO lt contents of program memory location 1104H 1000H 0104H RO 88H R2 01H R3 04H LDE R0 1000H RR2 RO lt contents of external data memory location 1104H 1000H 0104H RO 98H R2 01H R3 04H
103. ELECTRONICS USER S MANUAL ERRATA This document contains the corrections of errors typos and omissions in the following document Samsung 8 bit CMOS S3C84E5 C84E9 P84E9 Microprocessor User s Manual Document Number 21 1 S3 C84E5 C84E9 P84E9 082005 Publication August 2005 S3C84E5 C84E9 P84E9 USER S MANUAL ERRATA ERRATA VER 1 1 Samsung 8 bit CMOS S3C84E5 C84E9 P84E9 Microprocessor User s Manual Document Number 21 1 S3 C84E5 C84E9 P84E9 082005 Publication August 2005 1 Features PAGE 1 2 Built in RESET circuit LVR e Low Voltage reset LVR value 2 9 V Operating Voltage Range e Vi yg to 5 5V 2 Low Voltage Reset PAGE 16 1 The on chip Low Voltage Reset features static reset when supply voltage is below a reference voltage value Typical 2 9 V ELECTRONICS 1 USER S MANUAL ERRATA S3C84E5 C84E9 P84E9 3 Low Voltage Reset PAGE 16 2 Watchdog RESET nRESET Internal System RESET When the Von level is lower than 2 9V NOTES 1 The target of voltage detection level is 2 9 V at VDD 5 V 2 BGR is Band Gap voltage Reference Figure 16 1 Low Voltage Reset Circuit 2 ELECTRONICS S3C84E5 C84E9 P84E9 USER S MANUAL ERRATA 4 Table 17 3 D C Electrical Characteristics PAGE 17 3 TA 25 C to 85 C Vop to 5 5 V Input high voltage Viri Vpp Vi vn to 55V 0 8 NNNM All port and nRESET 1 a Input low voltage Via Vpp Viyg to 55V 0 2Vpp All ports and nRESE
104. Examples Given flag C 1 register 00 01H and register 01 20H Secs JP C LABEL W gt LABEL_W 1000H PC 1000H JP 00H gt PC 0120H The first example shows a conditional JP Assuming that the carry flag is set to 1 the statement C LABEL W replaces the contents of the PC with the value 1000H and transfers control to that location Had the carry flag not been set control would then have passed to the statement immediately following the JP instruction The second example shows an unconditional JP The statement JP 00 replaces the contents of the PC with the contents of the register pair 00H and 01H leaving the value 0120H ELECTRONICS 6 47 INSTRUCTION SET S3C84E5 C84E9 P84E9 JR Jump Relative JR Operation Flags Format Example 6 48 cc dst If cc is true PC dst If the condition specified by the condition code cc is true the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the JR instruction is executed See the list of condition codes at the beginning of this chapter The range of the relative address is 127 128 and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement No flags are affected Bytes Cycles Opcode Addr Mode note Hex dst dst 2 6
105. Examples Given R1 10H R2 C flag 1 register 01H 20H register 02H and register 03H OAH ADC R1 R2 gt R1 14H R2 03H ADC R1 R2 gt R1 1BH R2 03H ADC 01H 02H gt Register 01H 24H register 02H 03H ADC 01H 02H gt Register 01H 2BH register 02H ADC 01H 11H gt Register 01H 32H In the first example the destination register R1 contains the value 10H the carry flag is set to 1 and the source working register R2 contains the value The statement ADC R1 R2 adds and the carry flag value 1 to the destination value 10H leaving 14H in the register R1 6 14 ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET ADD ADD dst src Operation dst dst src The source operand is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed Flags C Setif there is a carry from the most significant bit of the result cleared otherwise Z Setif the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V Setif arithmetic overflow occurred that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to O H Setif a carry from the low order nibble occurred Format Bytes Cycles Opcode Addr Mode Hex dst src 6 03 r Ir opc src dst 3 6 04 R R 05 R IR opc dst src
106. F BTJRT BXOR CALL CCF List of Instruction Descriptions Full Register Name N Bit Compare sorena i r e uides Bit C mplement 7 tem bes rA BILR68817 aeos tee eel ane aaa as rr Sau Lm u aqa su Compare Increment and Jump 0 Compare Increment and Jump on hee MEE Decimal Adjust niece ciue y ti Dee ka Rer EPI Idle Operation siess errare Leere Deere e Late eL ee tte ee Lb te rau us s INCH MSN ee AA E RS erae eee eae duo s ev T Ee s Pau d DUAE Du avant S3C84E5 C84E9 P84E9 MICROCONTROLLER Page umber xxi Instruction Mnemonic LDC LDE LDC LDE LDCD LDED LDCI LDEI LDCPD LDEPD LDCPI LDEPI LDW MULT NEXT NOP OR POP POPUD POPUI PUSH PUSHUD SRP SRP0 SRP1 STOP SUB SWAP TCM TM WEI XOR xxii List of Instruction Descriptions Continued Full Register Name Page Number Load Memory E 6 52 Load Memory y 1 eem a uy Sts dde etu ae suway uya Kx e PE DH ukap 6 53 Load Memory 6 54 Load Memory and Increment 6 55 Load Memory with Pre Decrement 6 56 Load Memory with
107. FFH is used to set the relative priorities of the interrupt levels in the microcontroller s interrupt structure After a reset all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine When more than one interrupt sources are active the source with the highest priority level is serviced first If two sources belong to the same interrupt level the source with the lower vector address usually has the priority This priority is fixed in hardware To support programming of the relative interrupt level priorities they are organized into groups and subgroups by the interrupt logic Please note that these groups and subgroups are used only by IPR logic for the IPR register priority definitions see Figure 5 7 Group A IRQ0 IRQ1 Group B IRQ2 IRQ3 IRQ4 Group C IRQ5 IRQ6 IRQ7 IPR Group C B21 B22 C21 IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5 8 IPR 7 IPR 4 and IPR 1 control the relative priority of interrupt groups A B and C For example the setting 001B for these bits would select the group relationship B gt C gt A The setting 101B would select the relationship C gt B gt A The functions of the other IPR bit settings are as follows IPR 5 controls the relative priorities of group C interrupts Interrupt group C includes a subgroup that has an additional priority rel
108. FLAGS 0 to 1 selectin the bank 1 register addressing if bank 1 is implemented in the microcontrooler s internla register file ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET SBC subtract with Carry SBC Operation Flags Format Examples dst src dst dst src c The source operand along with the current value of the carry flag is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand In multiple precision arithmetic this instruction permits the carry borrow from the subtraction of the low order operands to be subtracted from the subtraction of high order operands C Setifa borrow occurred src gt dst cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Bytes Cycles Opcode Addr Mode Hex dst src 6 33 r Ir src dst 3 6 34 R R 6 35 R IR opc dst src 3 6 36 R IM Given R1 10H R2 08H C 1 register
109. Groups A B and C Group priority undefined gt gt gt gt 6 B gt A gt C C gt A gt B gt gt gt gt Group priority undefined o 0 Group prionty undefined O 0 t B CoA S OS ee 7 EC 7 r o o osasB 0 OE 2 2 7 1 1 1 Group priority undefined 0 6 Interrupt Subgroup C Priority Control Bit 0 IRQ6 gt IRQ7 IRQ7 gt IRQ6 5 Interrupt Group C Priority Control Bit IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQS 3 Interrupt Subgroup B Priority Control Bit IRQ3 gt IRQ4 IRQ4 gt IRQ3 je 2 Interrupt Group B Priority Control Bit IRQ2 gt IRQ3 IRQ4 1 IRQ3 IRQ4 gt IRQ2 0 Interrupt Group A Priority Control Bit IRQ0 gt IRQ1 IRQ1 gt IRQ0 RB ELECTRONICS 4 1 CONTROL REGISTERS S3C84E5 C84E9 P84E9 IRQ Interrupt Request Register DCH Set 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R R R R Addressing Mode Register addressing mode only 7 Interrupt Level 7 IRQ7 Request Pending Not pending je Pending 6 Interrupt Level 6 IRQ6 Request Pending Bit Not pending Pending je 5 Interrupt Level 5 IRQ5 Request Pending Not pending 1 Pending 4 Interrupt Level 4 IRQ4 Request Pending Bit Not pending Pending 3 Interrupt Level 3 IRQ3 Request Pending Bit Not pending Pending je 2 Interrupt Level 2 IRQ2 Request Pending Bit Not pending Pending
110. H SPL OFFH PUSH 40H gt Register 40H 4FH register 4FH OAAH stack register OFFH SPH OFFH SPL OFFH In the first example if the stack pointer contains the value OOOOH and the general register 40H the value 4FH the statement PUSH 40H decrements the stack pointer from 0000 to OFFFFH It then loads the contents of the register 40H into the location OFFFFH and adds this new value to the top of the stack ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET PUSHUD Push user Stack Decrementing PUSHUD Operation Flags Format Example dst src IR IR 1 dst src This instruction is used to address user defined stacks in the register file PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dst src 3 8 82 IR R Given Register 00H register 01H 05H and register 02H PUSHUD O00H 01H gt Register OOH 02H register 01H O5H register 02H 05H If the user stack pointer the register OOH for example contains the value 03H the statement PUSHUD 00H 01H decrements the user stack pointer by one leaving the value 02H The 01H register value 05H is then loaded into the register addressed by the decremented user stack pointer ELECTRONICS 6 67 INSTRUCTION SET S3C84E5 C84E9 P84E9 PUSHUI
111. One Ex File Address Register in Register One Operand Fle Instruction Example Address of Operand used by Instruction Value used in OPERAND Instruction Execution Sample Instruction RL SHIFT Where SHIFT is the label of an 8 bit register address Figure 3 3 Indirect Register Addressing to Register File ELECTRONICS 3 3 ADDRESSING MODES S3C84E5 C84E9 P84E9 INDIRECT REGISTER ADDRESSING MODE Continued Register File REGISTER Example Instruction References OPCODE Points to Address Points to Program Memory Program Memory Sample Instructions Value used in OPERAND CALL RR2 Instruction JP RR2 Figure 3 4 Indirect Register Addressing to Program Memory 3 4 ELECTRONICS S3C84E5 C84E9 P84E9 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE Continued Register File MSB Points to RPO or RP1 RPO or Selected RP points Program Memory to start fo 4 bit working register 56 block Working Register Pointtothe ADDRESS ej Address a Working Register ADDRESS 1 of 8 Value used OPERAND A Sample Instruction Figure 3 5 Indirect Working Register Addressing to Register File ELECTRONICS 3 5 ADDRESSING MODES S3C84E5 C84E9 P84E9 INDIRECT REGISTER ADDRESSING MODE Continued Register File C C RP0 or RP1 RP0 or RP1 Selected RP points to start of working register pee Program Mem
112. Pending bit clear when write 1 Interrupt is pending when read No effect when write 2 P2 2 PND2 Interrupt Pending Bit 0 No interrupt pending when read Pending bit clear when write 1 Interrupt is pending when read No effect when write 1 P2 1 PND1 Interrupt Pending Bit 0 No interrupt pending when read Pending bit clear when write 1 Interrupt is pending when read No effect when write 0 P2 0 PNDO Interrupt Pending Bit 0 No interrupt pending when read Pending bit clear when write 1 Interrupt is pending when read No effect when write Figure 9 7 Port 2 Interrupt Pending Register P2INTPND S3C84E5 C84E9 P84E9 ELECTRONKIS S3C84E5 C84E9 P84E9 VO PORTS Port 2 Interrupt Control Register P2INT ECH Set1 Bank0 R W Reset value 00 7 P2 7 External Interrupt INT7 Enable Bit 0 Disable interrupt 1 Enable interrupt 6 P2 6 External Interrupt INT6 Enable Bit 0 Disable interrupt 1 Enable interrupt 5 P2 5 External Interrupt INT5 Enable Bit 0 Disable interrupt 1 Enable interrupt 4 P2 4 External Interrupt INT4 Enable Bit 0 Disable interrupt 1 Enable interrupt 3 P2 3 External Interrupt INT3 Enable Bit 0 Disable interrupt 1 Enable interrupt 2 P2 2 External Interrupt INT2 Enable Bit 0 Disable interrupt 1 Enable interrupt 1 P2 1 External Interrupt INT1 Enable Bit 0 Disable interrupt 1 Enable interru
113. Pin ADCO ADC7 S3C84E5 S3C84E9 S3P84E9 AVss Vss NOTE The symbol R signifies an offset resistor with a value of from 50 to 1000 Figure 15 5 Recommended A D Converter Circuit for Highest Absolute Accuracy ELECTRONICS 15 5 A D CONVERTER S3C84E5 C84E9 P84E9 59 PROGRAMMING TIP Configuring A D Converter ADO_CHK AD3_CHK 15 6 LD LD LD TM JR LD LD LD TM JR LD LD P3CONH 11111111B 11111111B ADCON 00000001B ADCON 00001000B Z ADO_CHK AD0BUFH ADDATAH AD0BUFL ADDATAL ADCON 00110001B ADCON 00001000B Z AD3 AD3BUFH ADDATAH AD3BUFL ADDATAL P3 7 P3 4 A D Input MODE P3 3 P3 0 A D Input MODE Channel ADCO fxx Conversion start A D conversion end EOC check No 8 bit conversion data 2 bit conversion data Channel ADC3 fxx Conversion start A D conversion end EOC check No 8 bit conversion data 2 bit conversion data ELECTRONICS S3C84E5 C84E9 P84E9 LOW VOLTAGE RESET LOW VOLTAGE RESET OVERVIEW The S3C84E5 C84E9 P84E9 can be reset in four ways external power on Reset by the external nReset input pin pulled low by the digital watchdog timing out by the Low Voltage reset circuit LVR During an external power on reset the voltage VDD is High level and the nRESET pin is forced Low level The RESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU
114. R1 07H In the first example the source register 01H contains the value 05H 00000101B and the destination working register R1 contains 07H 000001 11B The statement BAND R1 01H 1 ANDs the bit 1 value of the source register 0 with the bit 0 value of the register R1 destination leaving the value 06H 000001 10B in the register R1 ELECTRONICS 6 17 INSTRUCTION SET S3C84E5 C84E9 P84E9 BCP _ Bit Compare BCP Operation Flags Format Example dst src b dst 0 src b The specified bit of the source is compared to subtracted from bit zero LSB of the destination The zero flag is set if the bits are the same otherwise it is cleared The contents of both operands are unaffected by the comparison Unaffected Set if the two bits are the same cleared otherwise Cleared to 0 Undefined Unaffected Unaffected f OS oo Bytes Cycles Opcode Addr Mode Hex dst src NOTE Inthe second byte of the instruction format the destination address is four bits the bit address 0 is three bits and the LSB address value is one bit in length Given R1 07H and register 01H 01H BCP R1 01H 1 gt R1 O7H register 01H 01H If the destination working register R1 contains the value 07H 00000111B and the source register 01H contains the value 01H 00000001 the statement BCP R1 01H 1 compares bit one of the source register 01H and bit zero of the destination register R1 Because the bit val
115. RQ5 IRQ6 IRQ7 0 0 1 1 0 0 1 1 O O Figure 5 5 System Mode Register SYM 5 10 ELECTRONICS S3C84E5 C84E9 P84E9 INTERRUPT STRUCTURE INTERRUPT MASK REGISTER IMR The interrupt mask register IMR set 1 DDH is used to enable or disable interrupt processing for individual interrupt levels After a reset all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine Each IMR bit corresponds to a specific interrupt level bit 1 to IRQ1 bit 2 to IRQ2 and so on When the IMR bit of an interrupt level is cleared to 0 interrupt processing for that level is disabled masked When you set a level s IMR bit to 1 interrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH in set 1 Bit values can be read and written by instructions using the Register addressing mode Interrupt Mask Register IMR DDH Set 1 R W we IRQ2 4 IRQ3 IRQ IRQ5 RQ6 Interrupt level enable bit 0 Disable IRQ interrupt 1 Enable IRQ interrupt NOTE Before IMR register is changed to any value all interrupts must be disable Using DI instruction is recommended Figure 5 6 Interrupt Mask Register IMR ELECTRONICS 5 11 INTERRUPT STRUCTURE S3C84E5 C84E9 P84E9 INTERRUPT PRIORITY REGISTER IPR The interrupt priority register IPR set 1 bank 0
116. RUPT VECTOR ADDRESSES All interrupt vector addresses for the S3C84E5 C84E9 P84E9 interrupt structure are stored in the vector address area of the internal 16 32 Kbyte ROM OH 3FFFH OH 7FFFH see Figure 5 3 You can allocate unused locations in the vector address area as normal program memory If you do so please be careful not to overwrite any of the stored vector addresses Table 5 1 lists all vector addresses The program reset address in the ROM is 0100H Decimal 32 767 32 Kbyte Memory Area 16 Kbyte Memory Area 0100H 4 RESET Address FFH Interrupt Vector Area Figure 5 3 ROM Vector Address Area ELECTRONICS 5 5 INTERRUPT STRUCTURE S3C84E5 C84E9 P84E9 Table 5 1 Interrupt Vectors Vector Address Interrupt Source Request Reset Clear Decimal Interrupt Priorityin H W S W Value Value 2 Level Level 100H Basic timer WDT overflow nRESET UART transmit IRQ7 UART receive 0 2 1 1 3 2 1 1 1 E6 E4 E2 0 DE DC DA 3 2 H H H H H H H CAH Timer 1 1 overflow IRQ2 C8H Timer 1 1 match capture C6H Timer 1 0 overflow C4H Timer 1 0 match capture C2H Timer A overflow IRQ1 COH Timer A match capture EH Timer B underflow EM 1 Interrupt priorities are identified in inverse order 0 is the highest priority 1 is the next highest and so on 2 If two or more interrupts within the same level contend the interrupt with the lowest vector addres
117. Register High Byte E6H Set 1 Bank 0 4 14 POCONL Port 0 Control Register Low Byte E7H Set 1 Bank 0 4 15 P1CONH Port 1 Control Register High Byte E8H Set 1 Bank 0 4 16 P1CONL Port 1 Control Register Low Byte E9H Set 1 Bank 0 4 17 P2CONH Port 2 Control Register High Byte EAH Set 1 Bank 0 4 18 P2CONL Port 2 Control Register Low Byte EBH Set 1 Bank 0 4 19 2 Port 2 Interrupt Control Register ECH Set 1 Bank 0 4 20 P2INTPND Port 2 Interrupt Pending Register EDH Set 1 Bank 0 4 21 P3CONH Port Control Register High Byte Set 1 Bank 0 4 22 P3CONL Port Control Register Low Byte Set 1 Bank 0 4 23 Port 4 Control Register High Byte FOH Set 1 Bank 0 4 24 P4CONL Port 4 Control Register Low Byte F1H Set 1 Bank 0 4 25 P4INT Port 4 Interrupt Control Register F2H Set 1 Bank 0 4 26 P4INTPND Port 4 Interrupt Pending Register F3H Set 1 Bank 0
118. Register P2INTPND a HH 9 10 9 8 Port 2 Interrupt Control Register P2INT He 9 11 9 9 Port High Byte Control Register 9 12 9 10 Port Low Byte Control Register 9 13 9 11 Port 4 High Byte Control Register 9 15 9 12 Port 4 Low Byte Control Register 9 15 9 13 Port 4 Interrupt Pending Register P4INTPND a a 9 16 9 14 Port 4 Interrupt Control Register 9 16 10 1 Basic Timer Control Register 10 2 10 2 Basic Timer Block meer 10 4 11 1 Timer A Control Register 11 3 11 2 Timer A Functional Block 11 4 11 3 Timer B Functional Block 8 11 5 11 4 Timer B Control Register 11 6 11 5 Timer B Data Registers TBDATAH 11 6 11 6 Timer B Output Flip Flop Waveforms in Repeat 11 8 xii S3C84E5 C84E9 P84E9 MICROCONTROLLER List of Figures Concluded Page Title Page Number Number 12 1 Timer 1 0 1 Control Register T1CON0 T1CON1 a 12
119. Rn n 0 15 Rn b n 0 15 b 0 7 Rn n 0 15 RRp 0 2 4 14 reg or Rn reg 0 255 n 0 15 reg b reg 0 255 b 0 7 reg or RRp reg 0 254 even number only where p 0 2 14 addr addr 0 254 even number only Rn n 0 15 Rn or reg reg 0 255 n 0 15 RRp p 0 2 14 RRp or reg reg 0 254 even only where p 0 2 14 reg Rn reg 0 255 n 0 15 addr RRp addr range 128 to 127 where p 0 2 14 addr RRp addr range 0 65535 where p 2 14 addr addr range 0 65535 addr addr a number from 127 to 128 that is an offset relative to the address of the next instruction data data 0 255 data data 0 65535 6 9 INSTRUCTION SET S3C84E5 C84E9 P84E9 Table 6 5 OPCODE Quick Reference OPCODE MAP LOWER NIBBLE HEX is Pee T s i esis J 5 21 2 DEC DEC ADD ADD ADD ADD ADD BOR R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM rO Rb 1 RLC RLC ADC ADC ADC ADC ADC BCP R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b R2 2 INC INC SUB SUB SUB SUB SUB BXOR R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM rO Rb 3 JP SRP 0 1 SBC SBC SBC SBC SBC BTJR IRR1 IM r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r2 b RA 4 DA DA OR OR OR OR OR LDB R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM rO Rb 5 POP POP AND AND AND AND AND BITC R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b COM COM TCM TCM TCM TCM TCM BAND R1 IR1 r1 r2 r1 lr2 R2 R1 IR2 R1 R
120. T Vito Vpp Vivr_ to 55V 0 4 Xin and XTIN ELECTRONICS 3 USER S MANUAL ERRATA S3C84E5 C84E9 P84E9 5 Table 17 3 D C Electrical Characteristics PAGE 17 4 TA 25 C to 85 C Vpp Vi vn to 5 5 V Pull up resistor Voo 5 V Vy 20V TA 25 G All I O pins except nRESET Vpp 3 V Vin 0 V TA 25 C All I O pins except nRESET Rpo Vpp 5 V Vin 0 V Ta 25 C 50 250 nRESET only Vpp 3 V Vin 0 V TA 25 C 100 500 nRESET only Supply current 1 Vpp 4 5V to 5 5V RUN mode 12 MHz CPU clock 8 MHz CPU clock Idle mode 12 MHz CPU clock 8 MHz CPU clock Sub operating main osc stop 32768 Hz crystal oscillator N e e C1 e 0 2 5 150 A Sub idle mode main osc stop 32768 Hz crystal oscillator Vpp 4 5 V to 5 5 V Ty 25 Stop mode Vpp Vi vn to 3 3 V Ta 25 G Stop mode e 4 ELECTRONICS S3C84E5 C84E9 P84E9 USER S MANUAL ERRATA 6 Table 17 4 A C Electrical Characteristics PAGE 17 5 TA 25 C to 85 C Vpp Vi vn to 5 5 V 7 Table 17 5 Main Oscillator Frequency PAGE 17 6 TA 25 C 85 C Vpp 5 5 V Oscillator Clock Circuit Test Condition Min Typ Max Unit Main crystal or Vpp to 55V ceramic External clock VLypg to 5 5 V main system 8 Table 17 6 Main Oscillator Clock Stabilization Time PAGE 17 6 TA 25
121. T1OUT1 Timer 1 0 overflow interrupt IRQ2 vector C6H and match capture interrupt IRQ2 vector generation Timer 1 1 Timer 1 0 control register T1 CONO set 1 E8H Bank 1 read write Timer 1 1 control register T1 CON1 set 1 E9H Bank 1 read write overflow interrupt IRQ2 vector CAH and match capture interrupt IRQ2 vector C8H generation ELECTRONICS 12 1 16 BIT TIMER 1 0 1 S3C84E5 C84E9 P84E9 FUNCTION DESCRIPTION Timer 1 0 1 Interrupts IRQ2 Vectors The timer 1 0 module can generate two interrupts the timer 1 0 overflow interrupt T1OVFO and the timer 1 0 match capture interrupt T1INTO T1OVFO is interrupt level IRQ2 vector C6H T1INTO also belongs to interrupt level 2 but is assigned the separate vector address A timer 1 0 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced A timer 1 0 match capture interrupt T1INTO pending condition is also cleared by hardware when it has been serviced The timer 1 1 module can generate two interrupts the timer 1 1 overflow interrupt T1OVF1 and the timer 1 1 match capture interrupt T1OVF1 is interrupt level IRQ2 vector T1INT1 also belongs to interrupt level IRQ2 but is assigned the separate vector address C8H A timer 1 1 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced A timer
122. TCON 6 and 7 to 00B Write transmission data to the shift register UDATA F5H to start the transmission operation Mode 0 Receive Procedure gt Select mode 0 by setting UATCON 6 and 7 to 00B Clear the receive interrupt pending bit UARTPND 1 by writing a 0 to UARTPND 1 Set the UART receive enable bit UARTCON 4 to 1 The shift clock will now be output to the TxD P1 5 pin and will read the data at the RxD P1 4 pin A UART receive interrupt vector E4H occurs when UARTCON 1 is set to 1 Write to Shift Register UDATA Shift N m X ow X p X m X m X m X X m TxD Shift Clock _ _ ___ 1 Write to UARTPND Clear RIP and set RE Transmit Shift RxD Data In DO DI D2 D3 D4 D5 D6 D7 TxD Shift Clock Figure 13 6 Timing Diagram for UART Mode 0 Operation ELECTRONICS 13 9 UART S3C84E5 C84E9 P84E9 UART MODE 1 FUNCTION DESCRIPTION In mode 1 10 bits are transmitted through the TxD P1 5 pin or received through the RxD P1 4 pin Each data frame has three components Start bit 0 8 data bits LSB first Stop bit 1 When receiving the stop bit is written to the RB8 bit in the UARTCON register The baud rate for mode 1 is variable Mode 1 Transmit Procedure 1 Select the baud rate generated by 16bit BRDATA Select mode 1 8 bit UART by setting UARTCON bits 7 and 6 to 01 Write transmission data to the shift register UDAT
123. a Memory Memory Address Program Memory Used Upper Address Byte Lower Address Byte 0 or 1 4 LSB Selects Program OPCODE Memory or Data Memory 0 Program Memory 1 Data Memory Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded into register R5 LDE R5 1234H Identical operation to LDC example except that external program memory is accessed Figure 3 10 Direct Addressing for Load Instructions ELECTRONICS S3C84E5 C84E9 P84E9 ADDRESSING MODES DIRECT ADDRESS MODE Continued Program Memory Next OPCODE Address Used Memory Upper Address Byte Lower Address Byte OPCODE Sample Instructions JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Figure 3 11 Direct Addressing for Call and Jump Instructions ELECTRONICS 3 11 ADDRESSING MODES S3C84E5 C84E9 P84E9 INDIRECT ADDRESS MODE IA In Indirect Address IA mode the instruction specifies an address located in the lowest 256 bytes of the program memory The selected pair of memory locations contains the actual address of the next instruction to be executed Only the CALL instruction can use the Indirect Address mode Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory only an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed
124. able Watch dog SB1 LD T1CONO 01000110b Enable interrupt fxx 64 Interval Interval 1 536 ms 10 MHz x tal LDW T1DATAHO 00F0Oh 00 T1DATALO FOh SBO El MAIN MAIN ROUTINE JR T MIAN TIM1_INT Interrupt service routine IRET END ELECTRONICS 12 7 S3C84E5 C84E9 P84E9 UART UART OVERVIEW The UART block has a full duplex serial port with programmable operating modes There is one synchronous mode and three UART Universal Asynchronous Receiver Transmitter modes Shift Register I O with baud rate of fxx 16 x 16 bit BRDATA 1 8 bit UART mode variable baud rate fxx 16 x 16 bit BRDATA 1 9 bit UART mode variable baud rate fxx 16 x 16 bit BRDATA 1 UART receive and transmit buffers are both accessed via the data register UDATA is at address F5H Writing to the UART data register loads the transmit buffer reading the UART data register accesses a physically separate receive buffer When accessing a receive data buffer shift register reception of the next byte can begin before the previously received byte has been read from the receive register However if the first byte has not been read by the time the next byte has been completely received the first data byte will be lost Overrun error In all operating modes transmission is started when any instruction usually a write operation uses the UDATA register as its destination address In mode 0 serial data rece
125. alue is cleared to 00H Immediately following the write operation the BTCON 1 value is automatically cleared to 0 2 When you write a 1 to BTCON 0 the corresponding frequency divider is cleared to 00H Immediately following the write operation the BTCON O value is automatically cleared to 0 3 The fxx is selected clock for system main OSC or sub OSC 4 6 ELECTRONICS S3C84E5 C84E9 P84E9 CONTROL REGISTER System Clock Control Register D4H Set1 Reset Value 0 0 0 0 0 0 0 0 Read Write _ _ _ R W R W _ _ _ Addressing Mode Register addressing mode only 7 5 Not used for the S3C84E5 C84E9 P84E9 must keep always 0 4 3 CPU Clock System Clock Selection Bits note fxx 1 non divided 2 0 Not used for the S3C84E5 C84E9 P84E9 must keep always 0 NOTE After a reset the slowest clock divided by 16 is selected as the system clock To select faster clock speeds load the appropriate values to CLKCON 3 and CLKCON 4 ELECTRONICS 4 7 CONTROL REGISTERS S3C84E5 C84E9 P84E9 FLAGS System Flags Register D5H Set 1 Reset Value x x x x x x 0 0 Read Write R W R W R W R W R W R W R R W Addressing Mode Register addressing mode only 7 Carry Flag C Operation does not generate a carry or underflow condition 1 Operation generates a carry out or underflow into high order bit 7 6 Zero Flag Z Operation result is a non zero value Operation result is zero 1 5 Sign Flag S Operation generate
126. alue is the content of a specific register or register pair you can access any location in the register file except for set 2 With working register addressing you use a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space Registers are addressed either as a single 8 bit register or as a paired 16 bit register space In a 16 bit register pair the address of the first 8 bit register is always an even number and the address of the next register is always odd number The most significant byte of the 16 bit data is always stored in the even numbered register and the least significant byte is always stored in the next 1 odd numbered register Working register addressing differs from Register addressing as it uses a register pointer to identify a specific 8 byte working register space in the internal register file and a specific 8 bit register within that space LSB n Even address Figure 2 8 16 Bit Register Pair 2 12 ELECTRONICS S3C84E5 C84E9 P84E9 ADDRESS SPACES Special Purpose Registers General Purpose Register Bank 1 Bank 0 Control Registers System Registers CFH Register Pointers Each register pointer RP can independently point to one of the 24 8 byte slices of the register file other than set 2 After a reset RPO points to locations COH C7H and to locations C8H CFH that is to the common working register area NOTE In the
127. an automatically generated parity of 0 or 1 depending on a parity generation by means of TB8 bit UARTCON 3 When receiving the received 9th data bit is treated as a parity for checking receive data by means of the RB8 bit UARTCON 2 while the stop bit is ignored The baud rate for mode 2 is fosc 16 x 16 bit BRDATA 1 clock frequency Mode 2 Transmit Procedure 1 Select the baud rate generated by 16 bit BRDATA 2 Select mode 2 9 bit UART by setting UARTCON bits 6 and 7 to 10B Also select the 9th data bit to be transmitted by writing TB8 to 0 or 1 and set PEN bit of UARTPND register to 0 if you don t use a parity mode If you want to use the parity enable mode select the parity bit to be transmitted by writing TB8 to 0 or 1 and set PEN bit of UARTPND register to 1 3 Write transmission data to the shift register UDATA F5H to start the transmit operation Mode 2 Receive Procedure Select the baud rate to be generated by 16 bit BRDATA Select mode 2 and set the receive enable bit RE in the UARTCON register to 1 N 3 If you don t use a parity mode set PEN bit of UARTPND register to 0 to disable parity mode If you want to use the parity enable mode select the parity type to be check by writing TB8 to 0 or 1 and set PEN bit of UARTPND register to 1 Only 8 bits BitO to Bit7 of received data are available for data value 4 The receive operation starts when the signal at the RxD
128. are used to control system stack operations The S3C84E5 C84E9 P84E architecture supports stack operations in the internal register file Stack Operations Return addresses for procedure calls interrupts and data are stored on the stack The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction When an interrupt occurs the contents of the PC and the FLAGS register are pushed to the stack The IRET instruction then pops these values back to their original locations The stack address value is always decreased by one before a push operation and increased by one after a pop operation The stack pointer SP always points to the stack frame stored on the top of the stack as shown in Figure 2 15 High Address Top of stack Stack contents Stack contents after a call after an instruction interrupt Low Address Figure 2 15 Stack Operations User Defined Stacks You can freely define stacks in the internal register file as data storage locations The instructions PUSHUI PUSHUD POPUI and POPUD support user defined stack operations Stack Pointers SPL SPH Register locations D8H and D9H contain the 16 bit stack pointer SP that is used for system stack operations The most significant byte of the SP address SP15 SP8 is stored in the SPH register D8H and the least significant byte SP7 SP0 is stored in the SPL register After a reset the SP value is undetermined Because
129. at handles interrupt processing be sure to include the necessary register file address register pointer information El Interrupt Request Register Polling nRESET Read only Cycle IRQ0 IRQ7 Interrupts Interrupt Priority Vector Register Interrupt Cycle Interrupt Mask Register Global Interrupt Control El DI or SYM 0 manipulation Figure 5 4 Interrupt Function Diagram 5 8 ELECTRONICS S3C84E5 C84E9 P84E9 INTERRUPT STRUCTURE PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral see Table 5 3 Table 5 3 Interrupt Source Control and Data Registers Interrupt Source Interrupt Level Register s Location s in set1 Timer B undertow mao x Timer Amatchicapture omon Embnt x Embn x ow Timer 1 0 overfow TIDATAHITIDATALI _E6H E7H bank Timer 1 1 matohieapture TICONO TICONI _EGH EQH bank _THGNTHo TIONTLO_ bank Pd TIONTHITICNILI EDH x CTP Pact extemalinterupt OH Pazetemaimemp Panno ako P2 3 external interrupt P24 extemal interu mas PACONH IRQ5 P2INT ECH bank 0 P2INTPND EDH bank 0 P2 7 external in
130. ate an interrupt request The corresponding P4INTPND bit is then automatically set to 1 and the IRQ level goes low to signal the CPU that an interrupt request is waiting When the CPU acknowledges the interrupt request application software must clear the pending condition by writing a 0 to the corresponding P4INTPND bit 9 14 ELECTRONICS S3C84E5 C84E9 P84E9 VO PORTS Port 4 Control Register High Byte P4CONH FOH Set1 Bank0 R W Reset value 00 7 4 Not used must keep always 0 3 2 P4 5 Configuration Bits 0 0 Input mode with pull up 0 1 Input mode 1 X Push pull output mode 1 0 P4 4 Configuration Bits 0 0 Input mode with pull up 0 1 Input mode 1 X Push pull output mode Figure 9 11 Port 4 High Byte Control Register P4CONH Port 4 Control Register Low Byte P4CONL F1H Set1 Bank0 R W Reset value 00 7 6 P4 3 TBPWM Configuration Bits 0 0 Input mode with pull up 0 1 Input mode 1 0 Push pull output mode 1 1 Alternative function mode TBPWM output 5 4 P4 2 INT10 Configuration Bits 0 0 Input mode with pull up falling edge interrupt INT 10 0 1 Input mode falling edge interrupt INT 10 1 0 Input mode rising edge interrupt INT 10 1 1 Push pull output mode 3 2 P4 1 INT9 Configuration Bits 0 0 Input mode with pull up falling edge interrupt INT9 0 1 2 Input mode falling edge interrupt INT9 1 0 Input mode rising edge interrupt
131. ationship among the interrupt levels 5 6 and 7 IPR 6 defines the subgroup C relationship IPR 5 controls the interrupt group C IPR 0 controls the relative priority setting of IRQ0 and IRQ1 interrupts 5 12 ELECTRONICS S3C84E5 C84E9 P84E9 INTERRUPT STRUCTURE Interrupt Priority Register IPR FFH Set 1 Bank 0 R W ve 7 e s 2 9 us I Group priority SMS MEME REM RES 1 D7 D4 D1 0 IRQ0 gt IRQ1 Undefined 1 IRQ1 gt IRQ0 B gt C gt A Group B A gt B gt C 0 IRQ2 gt IRQ3 IRQ4 gt gt 1 IRQ3 IRQ4 gt IRQ2 C gt A gt B Subgroup B C gt B gt A 0 IRQ3 gt IRQ4 gt gt 1 IRQ4 gt IRQ3 Undefined Group 0 IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQ5 Subgroup C 0 IRQ6 gt IRQ7 1 IRQ7 gt IRQ6 0 0 0 0 1 1 1 1 Figure 5 8 Interrupt Priority Register ELECTRONICS 5 13 INTERRUPT STRUCTURE S3C84E5 C84E9 P84E9 INTERRUPT REQUEST REGISTER IRQ You can poll bit values in the interrupt request register IRQ set 1 DCH to monitor interrupt request status for all levels in the microcontroller s interrupt structure Each bit corresponds to the interrupt level of the same number bit 0 to IRQO bit 1 to IRQ1 and so on A 0 indicates that no interrupt request is currently being issued for that level A 1 indicates that an interrupt request has been generated for that level IRQ bit values are read only addressable using
132. ay be able to simplify the procedure above to some extent ELECTRONICS 5 17 S3C84E5 C84E9 P84E9 INSTRUCTION SET INSTRUCTION SET OVERVIEW The instruction set is specifically designed to support large register files that are typical of most S3C8 series microcontrollers There are 78 instructions The powerful data manipulation capabilities and features of the instruction set include A full complement of 8 bit arithmetic and logic operations including multiply and divide No special I O instructions I O control data registers are mapped directly into the register file Decimal adjustment included in binary coded decimal BCD operations 16 bit word data can be incremented and decremented Flexible instructions for bit addressing rotate and shift operations DATA TYPES The CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be set cleared complemented and tested Bits within a byte are numbered from 7 to 0 where bit 0 is the least significant right most bit REGISTER ADDRESSING To access an individual register 8 bit address the range 0 255 or the 4 bit address of a working register is specified Paired registers can be used to construct 16 bit data 16 bit program memory or data memory addresses For detailed information about register addressing please refer to Chapter 2 Address Spaces ADDRESSING MODES There are seven explicit addres
133. c The contents of the source a word are loaded into the destination The contents of the source are unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 8 C4 RR RR 5 RR IR opc dst src 4 8 C6 RR IML Given R4 06H R5 1CH R6 05H R7 02H register 00H register 01H 02H register 02H 03H and register 03H OFH LDW RR6 RR4 gt R6 O6H R7 1CH R4 O6H R5 1CH LDW 00H 02H gt Register OOH register 01H OFH register 02H 03H register 03H OFH LDW RR2 R7 gt R2 03H R3 OFH LDW 04H 01H gt Register 04H 03H register 05H OFH LDW RR6 1234H R6 12H R7 34H LDW 02H 0FEDH Register 02H OFH register OEDH In the second example please note that the statement LDW 00H 02H loads the contents of the source word 02H and into the destination word 00H and 01H This leaves the value in the general register 00H and the value OFH in the register 01H Other examples show how to use the LDW instruction with various addressing modes and formats ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET MULT Multiply Unsigned MULT dst src Operation dst lt dst x src The 8 bit destination operand the even numbered register of the register pair is multiplied by the Source operand 8 bits and the product 16 bits is stored in the register pair specified by the destination address Both operands are trea
134. capture H W S W C2H Timer A overflow H W S W n Timer 1 0 match capture S W C6H Timer 1 0 overflow H W S W Timer 1 1 1 match capture S W CAH Timer 1 1 overflow H W S W CCH _ Watch timer S W P2 0 external interrupt S W DOH T P2 1 external interrupt S W D2H 2 2 external interrupt S W D4H TL P2 3 external interrupt S W D6H P2 4 external interrupt S W D8H P2 5 external interrupt S W DAH P2 6 external interrupt S W DCH P2 7 external interrupt S W DEH P4 0 external interrupt S W EOH T P4 1 external interrupt S W E2H P4 2 external interrupt S W E4H o UART data receive S W i E6H UART data transmit S W NOTES 1 Within a given interrupt level the lower vector address has high priority For example DCH has higher priority than DEH within the level IRQ5 the priorities within each level are set at the factory 2 External interrupts are triggered by a rising or falling edge depending on the corresponding control register setting Figure 5 2 S3C84E5 C84E9 P84E9 Interrupt Structure 5 4 ELECTRONICS S3C84E5 C84E9 P84E9 INTERRUPT STRUCTURE INTER
135. ce value 03H from the destination value 12H and stores the result OFH in the destination register R1 ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET SWAP swap Nibbles SWAP Operation Flags Format Examples dst dst 0 3 e dst 4 7 The contents of the lower four bits and the upper four bits of the destination operand are swapped 7 43 0 Undefined Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 FO R F1 IR Given Register 00H register 02H and register OA4H SWAP 00H gt Register OOH OE3H SWAP 02H gt Register 02H register 4AH In the first example if the general register 00H contains the value 3EH 00111110B the statement SWAP 00H swaps the lower and the upper four bits nibbles in the OOH register leaving the value 11100011B ELECTRONICS 6 83 INSTRUCTION SET S3C84E5 C84E9 P84E9 TCM rest Complement under Mask TCM Operation Flags Format Examples 6 84 dst src NOT dst AND src This instruction tests selected bits in the destination operand for a logic one value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask The TCM statement complements the destination operan
136. ch Timer INITIAL MAIN WT_INT 14 4 ORG 0000h VECTOR OCCh WT INT ORG 0100h LD SYM 00h i LD IMR 00010000b i LD SPH 00000000b LD SPL 0FFh LD BTCON 10100011b LD WTCON 11001110b i El MAIN ROUTINE JR T MIAN AND WTCON 11111110b IRET END Disable Global Fast interrupt Enable IRQ3 interrupt Set stack area Disable Watch dog S3C84E5 C84E9 P84E9 0 5 kHz buzzer 1 955 ms duration interrupt Interrupt enable fxt 32 768Hz pending clear ELEGTRONIGS S3C84E5 C84E9 P84E9 A D CONVERTER A D CONVERTER OVERVIEW The 10 bit A D converter ADC module uses successive approximation logic to convert analog levels entering at one of the eight input channels to equivalent 10 bit digital values The analog input level must lie between the and AVss values The A D converter has the following components Analog compactor with successive approximation logic D A converter logic resistor string type ADC control register ADCON set 1 bank 0 F7H read write but ADCON 3 is read only Eight multiplexed analog data input pins ADCO ADC7 10 bit A D conversion data output register ADDATAH ADDATAL Internal AVREF and AVSS FUNCTION DESCRIPTION To initiate an analog to digital conversion procedure at first you must configure P3 0 P3 7 to analog input before A D conversions because the P3 0 P3 7 pins can be used alternatively as normal data I O or analog input
137. ck Stack ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET IDLE Operation IDLE Operation Flags Format Example See description The IDLE instruction stops the CPU clock while allowing the system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 1 4 6F instruction IDLE stops the CPU clock but it does not stop the system clock ELECTRONICS 6 43 INSTRUCTION SET S3C84E5 C84E9 P84E9 INC Increment INC Operation Flags Format Examples 6 44 dst dst dst 1 The contents of the destination operand are incremented by one C Unaffected 2 Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst r OtoF dst 2 4 20 R 21 IR Given RO 1BH register 00H OCH and register 1BH OFH INC RO RO 1CH INC 00H Register 00H RO 1BH register 01H 10H In the first example if the destination working register RO contains the value 1BH the statement INC RO leaves the value 1CH in that same register The second example shows the effect an INC instruction has on the register at the location assum
138. ck address RPO lt Stack address OFDH lt Stack address ELECTRONICS S3C84E5 C84E9 P84E9 ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter Instructions indicate the operation to be performed and the data to be operated on Addressing mode is the method used to determine the location of the data operand The operands specified in SAM88RC instructions be condition codes immediate data or a location in the register file program memory or data memory The S3C8 series instruction set supports seven explicit addressing modes Not all of these addressing modes are available for each instruction The seven addressing modes and their symbols are Register R Indirect Register Indexed X Direct Address DA Indirect Address IA Relative Address RA Immediate IM ELECTRONICS 3 1 ADDRESSING MODES S3C84E5 C84E9 P84E9 REGISTER ADDRESSING MODE R In Register addressing mode R the operand value is the content of a specified register or register pair see Figure 3 1 Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space see Figure 3 2 Program Memory Register File _ 200 ame OPERAND P
139. code Addr Mode note Hex dst src opc dst 3 10 37 RA NOTE Inthe second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRT SKIP R1 1 If the working register R1 contains the value 07H 00000111B the statement BTJRT SKIP R1 1 tests bit one in the source register R1 Because it is a 1 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location addressed by the BTJRT instruction must be within the allowed range of 127 to 128 ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET BXOR Bit xoR BXOR BXOR Operation Flags Format Examples dst src b dst b src dst 0 lt dst 0 src b or dst b lt dst b src 0 The specified bit of the source or the destination is logically exclusive ORed with bit zero LSB of the destination or the source The result bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected C Unaffected Z Setif the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 27 Rb r NOTE Inthe second byte of the 3 byte instruction format the destination or the source address is fo
140. conor acon 27 converter data regerar ovej ADDATAH aaa ran ND convener data reiterfow bye ADDATAL ws ron o o o o oto waron imer conor regier wrcon aso re o o o o o osccon es o o o o o e Basic ner courier roser ron 919191515191919 Location is not mapped merun mory eose I T7 ELECTRONICS 8 3 RESET and POWER DOWN S3C84E5 C84E9 P84E9 Table 8 3 S3C84E5 C84E9 P84E9 Set 1 Bank 1 Register Values After RESET Timer A 1 interrupt pending register TINTPND Timer A control register TACON Timer A data register TADATA Dee Hex Timer 1 0 counter register low byte Timer 1 1 counter register high byte Timer 1 1 counter register low byte 8 4 ELEGTRONIGS S3C84E5 C84E9 P84E9 RESET and POWER DOWN POWER DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP opcode 7FH In Stop mode the operation of the CPU and all peripherals is halted That is the on chip main oscillator stops and the supply current is reduced to less than pA except for the current consumption of LVR Low voltage Reset circuit All system functions stop when the clock freezes but data stored in the internal register file is retained Stop mode can be released in one of two ways by a reset o
141. ction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then incremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 8 93 R IR Given Register 00 01H and register 01 70H POPUI 02H 00H gt Register OOH 02H register 01H 70H register 02H 70H If the general register OOH contains the value 01H and the register 01H the value 70H the statement POPUI 02H O0OH loads the value 70H into the destination general register 02H The user stack pointer the register 00H is then incremented by one changing its value from 01H to 02H ELECTRONICS 6 65 INSTRUCTION SET S3C84E5 C84E9 P84E9 PUSH Push to Stack PUSH Operation Flags Format Examples 6 66 src SP SP 1 SP lt src A PUSH instruction decrements the stack pointer value and loads the contents of the source src into the location addressed by the decremented stack pointer The operation then adds the new value to the top of the stack No flags are affected Bytes Cycles Opcode Addr Mode Hex dst Opc SIC 2 8 internal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Given Register 40H 4FH register 4FH SPH and SPL OOH PUSH 40H gt Register 40H 4FH stack register OFFH 4FH SPH OFF
142. d which is then ANDed with the source mask The zero Z flag can then be checked to determine the result The destination and the source operands are unaffected C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 63 r Ir src dst 3 6 64 R R 65 R IR opc dst src 3 6 66 R IM Given RO 0C7H R1 02H R2 12H register 2BH register 01H 02H and register 02H 23H TCM RO R1 gt RO OC7H R1 02H Z 1 TCM RO R1 gt RO OC7H R1 02H register 02H 23H Z TCM 00H 01H gt Register OOH 2BH register 01 02H Z 1 TCM 00H 01H gt Register OOH 2BH register 01H 02H register 02H 23H Z 1 TCM 00H 34 gt Register OOH 2BH Z 0 In the first example if the working register RO contains the value 0C7H 11000111B and the register R1 the value 02H 00000010B the statement TCM RO R1 tests bit one in the destination register for a 1 value Because the mask value corresponds to the test bit the Z flag is set to logic one and can be tested to determine the result of the TCM operation ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET TM Test under Mask TM Operation Flags Format Examples dst src dst AND src This instruction tests selected bits in the destination operand for a logic zer
143. d clock for system S3C84E5 C84E9 P84E9 CONTROL REGISTER TINTPND Timer A Timer 1 Interrupt Pending Register EOH Set 1 Bank 1 Bit Identifier _ 4 3 2 fo 0 0 0 0 0 0 0 Reset Value 0 Read Write _ _ R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Not used for the S3C84E5 C84E9 P84E9 must keep always 0 5 Timer 1 1 Overflow Interrupt Pending Bit No interrupt pending Clear pending bit when write Interrupt pending 4 Timer 1 1 Match Capture Interrupt Pending Bit No interrupt pending Clear pending bit when write Interrupt pending 3 Timer 1 0 Overflow Interrupt Pending Bit No interrupt pending Clear pending bit when write Interrupt pending 2 Timer 1 0 Match Capture Interrupt Pending Bit No interrupt pending E Clear pending bit when write Interrupt pending 4 A Overflow Interrupt Pending Bit No interrupt pending ES Clear pending bit when write Interrupt pending 0 Timer Match Capture Interrupt Pending Bit No interrupt pending EJ Clear pending bit when write Interrupt pending ELECTRONICS 4 37 CONTROL REGISTERS S3C84E5 C84E9 P84E9 UARTCON UART Control Register F6H Set 1 Bank 0 Bit Identifier Reset Value Read Write 7 6 p 7 6 s a 3 2 9 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Operating Mode and Baud Rate Selection Bits Mode 0
144. ddressing mode Use working register addressing instead SRP 0COH LD R2 40H R2 C2H lt the value in location 40H Example 2 ADD 0C3H 45H Invalid addressing mode Use working register addressing instead SRP 0C0H ADD R3 45H R3 C3H R3 45H 4 BIT WORKING REGISTER ADDRESSING Each register pointer defines a movable 8 byte slice of working register space The address information stored in a register pointer serves as an addressing window that makes it possible for instructions to access working registers very efficiently using short 4 bit addresses When an instruction addresses a location in the selected working register area the address bits are concatenated in the following way to form a complete 8 bit address The high order bit of the 4 bit address selects one of the register pointers 0 selects RPO 1 selects RP1 The five high order bits in the register pointer select 8 byte slice of the register space The three low order bits of the 4 bit address select one of the eight registers in the slice As shown in Figure 2 11 the result of this operation is that the five high order bits from the register pointer are concatenated with the three low order bits from the instruction address to form the complete address As long as the address stored in the register pointer remains unchanged the three bits from the address will always point to an address in the same 8 byte register slice Figure 2
145. e 6 1 Flags Register FLAGS for codec romeo tede tette et Laien ett een d nn eR tus ee LR Pn 6 6 Flag Descriptions einna EE 6 7 Mstuction Ser or o n 6 8 Condition D 6 12 Instr ction Descriptioris u u L w uuu coe tea te PRI u Saa w asa ue RR 6 13 vi S3C84E5 C84E9 P84E9 MICROCONTROLLER Table of Contents Continued Part Hardware Descriptions Chapter 7 Clock Circuit Overview System Clock Circuit Clock Status During Power Down Modes System Clock Control Register CLKCON Chapter 8 RESET and Power Down System Reset ev eer aha Normal Mode RESET Operation Hardware RESET Values Power Down Modes Stop Mode Idle Mode Chapter 9 I O Ports Chapter 10 Basic Timer pecias Bas Timer ic uum EET Basic Timer Control Register BTCON Basic Timer Function Description S3C84E5 C84E9 P84E9 MICROCONTROLLER vii Table of Contents Continued Chapter 11 8 bit Timer A B BB MMS A chr tcn e yee eva se xv E Ee set Ree 11 1 gu C 11 1 Function 11 2 Time A Control Register ooi cte na edu emen puente de ecu k a au Qs
146. e FFh Figure 11 5 Timer B Data Registers TBDATAH TBDATAL ELECTRONICS S3C84E5 C84E9 P84E9 8 BIT TIMER A B TIMER B PULSE WIDTH CALCULATIONS To generate the above repeated waveform consisted of low period time t and high period time When T FF 0 ti ow TBDATAL 1 x 1 fx lt TBDATAL lt 100H where fx The selected clock TBDATAH 1 x 1 fx OH lt TBDATAH lt 100H where fx The selected clock When T FF 1 ti ow TBDATAH 1 x 1 fx OH lt TBDATAH lt 100H where fx The selected clock TBDATAL 1 x 1 fx lt TBDATAL lt 100H where fx The selected clock To make ti ow 24 us and THIGH 15 us fosc 4 MHz fx 4 MHz 4 1 MHz When T FF 0 ti gw 24 us TBDATAL 1 fx TBDATAL 1 x tus TBDATAL 23 tijg 15 us TBDATAH 1 TBDATAH 1 x 1 5 TBDATAH 14 When T FF 1 tijg 15 us TBDATAL 1 fx TBDATAL 1 x tus TBDATAL 14 ti ow 24 us TBDATAH 1 TBDATAH 1 x ius TBDATAH 23 ELECTRONICS 11 7 8 BIT TIMER A B S3C84E5 C84E9 P84E9 Timer B Clock T FF 0 TBDATAL 01 FFH TBDATAH 00H T FF 0 TBDATAL 00H TBDATAH 01 FFH T FF 0 TBDATAL 00H TBDATAH 00H T FF 1 TBDATAL 00H TBDATAH 00H Timer B Clock T FF 1 TBDATAL DFH TBDATAH 1FH T FF 0 TBDATAL DFH TBDATAH 1FH T FF 1 TBDATAL 7FH TBDATAH 7FH T FF 0 T
147. e available Schmitt trigger input and interrupt generation on falling signal edges Schmitt trigger input and interrupt generation on rising signal edges Schmitt trigger input with pull up resister and interrupt generation on falling signal edges Port 2 Interrupt Enable and Pending Registers P2INT P2INTPND To process external interrupts at the port 2 pins two additional control registers are provided the port 2 interrupt enable register P2INT set 1 bank 0 and the port 2 interrupt pending register P2INTPND EDH set 1 bank 0 The port 2 interrupt pending register P2INTPND lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated The application program detects interrupt requests by polling the P2INTPND register at regular intervals When the interrupt enable bit of any port 4 pin is 1 a rising or falling signal edge at that pin will generate an interrupt request The corresponding P2INTPND bit is then automatically set to 1 and the IRQ level goes low to signal the CPU that an interrupt request is waiting When the CPU acknowledges the interrupt request application software must clear the pending condition by writing a 0 to the corresponding P2INTPND bit ELECTRONICS 9 7 PORTS S3C84E5 C84E9 P84E9 Port 2 Control Register High Byte P2CONH EAH Set1 Bank0 R W Reset value 00 7 6 P2 7 INT7 Configurati
148. e 1 9 Pin Circuit Type F PO 0 P0 1 ELECTRONICS S3C84E5 C84E9 P84E9 ADDRESS SPACES ADDRESS SPACES OVERVIEW The S3C84E5 C84E9 P84E9 microcontroller has two types of address space Internal program memory ROM Internal register file RAM A 16 bit address bus supports program memory operations A separate 8 bit register bus carries addresses and data between the CPU and the register file The S3C84E5 C84E9 P84E9 has an internal 16 32 Kbyte mask programmable ROM 32 Kbyte OTP ROM and 528 byte RAM ELECTRONICS 2 1 ADDRESS SPACES S3C84E5 C84E9 P84E9 PROGRAM MEMORY ROM Program memory ROM stores program codes or table data The S3C84E5 84E9 has 16Kbytes and 32Kbytes of internal mask programmable program memory The program memory address range is therefore OH 3FFFH and 0H 7FFFH see Figure 2 1 The first 256 bytes of the ROM 0H 0FFH are reserved for interrupt vector addresses Unused locations in this address range can be used as normal program memory If you use the vector address area to store a program code be carelul not to overwrite the vector addresses stored in these locations The ROM address at which a program execution starts after a reset is 0100H Decimal HEX 32 767 32 KByte 7FFFH S3C84E9 P84E9 Decimal HEX 16 383 3FFFH S3C84E5 16 KByte Interrupt Vector Area Figure 2 1 Program Memory Address Space 2 2 ELECTRONK S S3C84E5 C84E9 P84E9 ADDRESS SPACES REGISTER
149. e Reset features static reset when supply voltage is below a reference voltage value Typical 2 9 V Thanks to this feature external reset circuit can be removed while keeping the application safety As long as the supply voltage is below the reference value there is an internal and static RESET The MCU can start only when the supply voltage rises over the reference voltage When you calculate power consumption please remember that a static current of LVR circuit should be added a CPU operating current in any operating modes such as Stop Idle and normal RUN mode ELECTRONICS 16 1 LOW VOLTAGE RESET S3C84E5 C84E9 P84E9 Watchdog RESET nRESET Internal System RESET When the Voo level is lower than 2 9V NOTES 1 The target of voltage detection level is 2 9 V at VoD 5 V 2 BGR is Band Gap voltage Reference Figure 16 1 Low Voltage Reset Circuit NOTE To program the duration of the oscillation stabilization interval you make the appropriate settings to the basic timer control register BTCON before entering Stop mode Also if you do not want to use the basic timer watchdog function which causes a system reset if a basic timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of BTCON 16 2 ELECTRONICS S3C84E5 C84E9 P84E9 ELECTRICAL DATA OVERVIEW ELECTRICAL DATA In this chapter S3C84E5 C84E9 P84E9 electrical characteristics are presented in tables and graphs The informat
150. e general register 00H contains the value 01H The statement POP 00H loads the contents of the location 00FBH 55H into the destination register 00H and then increments the stack pointer by one The register 00H then contains the value 55H and the SP points to the location 00FCH ELECTRONICS 6 63 INSTRUCTION SET S3C84E5 C84E9 P84E9 POPUD Pop User Stack Decrementing POPUD Operation Flags Format Example dst src dst src IR IR 1 This instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then decremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 8 92 R IR Given Register 42H user stack pointer register register 42H 6FH and register 02H 70H POPUD 02H 00H gt Register OOH 41H register 02H 6FH register 42H 6FH 02H If the general register 00H contains the value 42H and the register 42H the value 6FH the statement POPUD 02H 00H loads the contents of the register 42H into the destination register The user stack pointer is then decremented by one leaving the value 41H ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET POPUI Pop User Stack Incrementing POPUI Operation Flags Format Example dst src dst src IR lt IR 1 The POPUI instru
151. e lower 32 byte area contains 16 system registers DOH DFH and a 16 byte common working register area You can use the common working register area as a scratch area for data operations being performed in other areas of the register file Registers in set 1 locations are directly accessible at all times using Register addressing mode The 16 byte working register area can only be accessed using working register addressing For more information about working register addressing please refer to Chapter 3 Addressing Modes REGISTER SET 2 The same 64 byte physical space that is used for set 1 locations COH FFH is logically duplicated to add another 64 bytes of register space This expanded area of the register file is called set 2 For S8C84E5 C84E9 P84E9 the set 2 address range COH FFH is accessible on pages 0 1 The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions You can use only Register addressing mode to access set 1 locations In order to access registers in set 2 you must use Register Indirect addressing mode or Indexed addressing mode The set 2 register area is commonly used for stack operations ELECTRONICS 2 7 ADDRESS SPACES S3C84E5 C84E9 P84E9 PRIME REGISTER SPACE The lower 192 bytes OOH BFH of the S8C84E5 C84E9 P84E9 s two 256 byte register pages is called prime register area Prime registers can be accessed using any of the seven addressing modes
152. e shot mode Oscillation frequency is 4 MHz fx 1 4 clock 1 us TBDATAH 40 us 1 us 40 TBDATAL 1 Set P4 3 to TBPWM mode ORG 0100H I START DI LD TBDATAH 40 1 LD TBDATAL 1 LD TBCON 00010001B I LD P4CONL 03H PULSE OUT LD TBCON 00000101B 11 10 Reset address Set 40 us Set any value except 00H Clock Source lt fxx 4 Disable Timer B interrupt Select one shot mode for Timer B Stop Timer B operation Set Timer B output flip flop T FF high Set P4 3 to TBPWM mode Start Timer B operation to make the pulse at this point After the instruction is executed 0 75 us is required before the falling edge of the pulse starts ELECTRONICS S3C84E5 C84E9 P84E9 8 BIT TIMER A B 59 PROGRAMMING TIP Using the Timer A ORG 0000h VECTOR OCOh TAMC INT VECTOR OC2h TAOV INT ORG 0100h INITIAL LD SYM z00h Disable Global Fast interrupt SYM LD IMR 00000010b Enable IRQ1 interrupt LD SPH 00000000b Set stack area LD SPL 00000000b LD BTCON 1010001 1b Disable watch dog LD POCONH Z0COH Enable TAOUT output SB1 LD TADATA 80h LD TACON 01001010b Match interrupt enable 6 55 ms duration 10 MHz x tal SB0 El MAIN MAIN ROUTINE JR T MAIN TAMC_INT Interrupt service routine IRET INT Interrupt service routine IRET END ELECTRONICS 11 11 8 BIT TIMER A B 59 PROGRAMMING TIP Using the Timer B INITIAL MAIN TBUN_INT 1
153. e stop instruction NOTE Before execute the STOP instruction You must set this STPCON register as 10100101b Otherwise the STOP instruction will not be executed ELEGTRONIGS CONTROL REGISTERS S3C84E5 C84E9 P84E9 SYM System Mode Register DEH Set 1 Reset Value 0 0 0 x x x 0 0 Read Write _ _ _ R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 Not used But you must keep always 0 4 2 Fast Interrupt Level Selection Bits 4 Fast Interrupt Enable Bit o Disable fast interrupt processing Enable fast interrupt processing 0 Global Interrupt Enable Bit note E Disable global interrupt processing Enable global interrupt processing NOTE Following a reset you enable global interrupt processing by executing an El instruction not by writing a 1 to SYM 0 S3C84E5 C84E9 P84E9 CONTROL REGISTER T1CONO Timer 1 0 Control Register E8H Set 1 Bank 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode 7 5 ELEGTRONIGS Register addressing mode only Timer 1 0 Input Clock Selection Bits Polo fo 1112 711 1 0 Operating Mode Selection Bits olo Interval mode 1 Capture mode Capture rising edge OVF occur K Capture mode Capture falling edge OVF occur PWM mode Timer 1 0 C
154. er application by the customer s technical experts Samsung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product Publication Number 21 1 S3 C84E5 C84E9 P84E9 082005 2005 Samsung Electronics All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics Samsung Electronics microcontroller business has been awarded full ISO 14001 certification BSI Certificate No FM24653 All semiconductor products are d
155. errupt 1 Enable interrupt Figure 9 14 Port 4 Interrupt Control Register PAINT 9 16 ELECTRONICS S3C84E5 C84E9 P84E9 BASIC TIMER BASIC TIMER OVERVIEW BASIC TIMER BT You can use the basic timer BT in two different ways As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction signal the end of the required oscillation stabilization interval after a reset or a Stop mode release The functional components of the basic timer block are Clock frequency divider divided by 4096 1024 or 128 with multiplexer 8 bit basic timer counter BTCNT set 1 bank 0 FDH read only Basic timer control register BTCON set 1 D3H read write BASIC TIMER CONTROL REGISTER BTCON The basic timer control register BTCON is used to select the input clock frequency to clear the basic timer counter and frequency dividers and to enable or disable the watchdog timer function It is located in set 1 address D3H and is read write addressable using register addressing mode A reset clears BTCON to 00H This enables the watchdog function and selects a basic timer clock frequency of 4096 To disable the watchdog function write the signature code 1010B to the basic timer register control bits 7 4 8 bit basic timer counter set 1 bank 0 FDH can be cleared at any time during normal operation by writing a 1 to BTCON
156. eset Value FFH Brud rate data Figure 13 4 UART Baud Rate Data Register BRDATAH BRDATAL BAUD RATE CALCULATIONS The baud rate is determined by the baud rate data register 16 bit BRDATA Mode 0 baud rate fxx 16 x 16 bit BRDATA 1 Mode 1 baud rate fxx 16 x 16 bit BRDATA 1 Mode 2 baud rate fxx 16 x 16 bit BRDATA 1 13 6 ELECTRONICS S3C84E5 C84E9 P84E9 UART Table 13 1 Commonly Used Baud Rates Generated by 16 bit BRDATA Oscillation Clock BRDATAH BRDATAL o o ew o o 9 nou o o mao nom o o v Hemom o o 3 o o o o v ELECTRONICS 13 7 UART S3C84E5 C84E9 P84E9 BLOCK DIAGRAM SAMB88 Internal Data Bus Write to UDATA gt Start TxD 1 5 Tx Control TxClock TIP Rx Clock Receive Rx Control me Shift Transition Detector aal Shift Bit Detector Value a Shift 2 puo ee RxD P1 4 SAM88 Internal Data Bus Figure 13 5 UART Functional Block Diagram 13 8 ELECTRONICS S3C84E5 C84E9 P84E9 UART UART MODE 0 FUNCTION DESCRIPTION In mode 0 UART is input and output through the RxD P1 4 pin and TxD P1 5 pin outputs the shift clock Data is transmitted or received in 8 bit units only The LSB of the 8 bit value is transmitted or received first Mode 0 Transmit Procedure 1 2 Select mode 0 by setting UAR
157. esigned and manufactured in accordance with the highest quality standards and objectives Samsung Electronics Co Ltd San 424 Nongseo Dong Giheung Gu Yongin City Gyeonggi Do Korea C P O Box 37 Suwon 446 711 TEL 82 31 209 5238 FAX 82 31 209 6494 Home Page http www samsung com Printed in the Republic of Korea Preface The S3C84E5 C84E9 P84E9 Microcontroller User s Manual is designed for application designers and programmers who are using the S3C84E5 C84E9 P84E9 microcontroller for application development It is organized in two main parts Part Programming Model Part 11 Hardware Descriptions Part contains software related information to familiarize you with the microcontroller s architecture programming model instruction set and interrupt structure It has six chapters Chapter 1 Product Overview Chapter 4 Control Registers Chapter 2 Address Spaces Chapter 5 Interrupt Structure Chapter 3 Addressing Modes Chapter 6 Instruction Set Chapter 1 Product Overview is a high level introduction to S3C84E5 C84E9 P84E9 with general product descriptions as well as detailed information about individual pin characteristics and pin circuit types Chapter 2 Address Spaces describes program and data memory spaces the internal register file and register addressing Chapter 2 also describes working register addressing as well as system stack and user defined stack operations Chapter 3 Addressing Modes
158. esult of a two s complement operation is greater than 127 or less than 128 It is cleared to 0 after a logic operation has been performed Decimal Adjust Flag FLAGS 3 The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute correctly The DA bit is not usually accessed by programmers and it cannot be addressed as a test condition Half Carry Flag FLAGS 2 The H bit is set to 1 whenever an addition generates a carry out of bit 3 or when a subtraction borrows out of bit 4 It is used by the Decimal Adjust DA instruction to convert the binary result of a previous addition or subtraction into the correct decimal BCD result The H flag is normally not accessed directly by a program Fast Interrupt Status Flag FLAGS 1 The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing When set it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed Bank Address Flag FLAGS 0 The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected bank 0 or bank 1 The BA flag is cleared to 0 select bank 0 when the SBO instruction is executed and is set to 1 select bank 1 when the SB1 instruction is executed ELECTRONICS 6 7 INSTRUCTION SET INSTRUCTION SET NOTATION S3C84E5 C84
159. et 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Watch Clock Selection Bit 0 Main system clock divided by 256 fxx 256 Sub system clock fxt 6 Watch Timer Interrupt Enable Bit Disable watch timer interrupt 1 Enable watch timer interrupt 5 4 Buzzer Signal Selection Bits 0 0 5 kHz buzzer BZOUT signal output 1 kHz buzzer BZOUT signal output 0 2 kHz buzzer BZOUT signal output 1 4 kHz buzzer BZOUT signal output 3 2 Watch Timer Speed Selection Bits 41 Watch Enable Bit Disable watch timer Clear frequency dividing circuits Enable watch timer 0 Watch Interrupt Pending Bit Interrupt is not pending Clear pending bit when write Interrupt is pending ELECTRONICS 4 41 S3C84E5 C84E9 P84E9 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The S3C8 series interrupt structure has three basic components levels vectors and sources The SAM8 CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors When a specific interrupt level has more than one vector address the vector priorities are established in hardware A vector address can be assigned to one or more sources Levels Interrupt levels are the main unit for interrupt priority assignment and recognition All peripherals and blocks can
160. fected Set if the result is 0 cleared otherwise Always reset to 0 Unaffected 2 S Set if the result bit 7 is set cleared otherwise V D H Unaffected Bytes Cycles Given R1 07H and register 07H OF1H COM R1 gt R1 OF8H COM R1 gt R1 07H register 07H OEH Opcode Hex 60 61 Addr Mode dst R IR In the first example the destination working register R1 contains the value 07H 00000111B The statement COM R1 complements all the bits in R1 all logic ones are changed to logic zeros and logic zeros to logic ones leaving the value 0F8H 11111000B In the second example Indirect Register IR addressing mode is used to complement the value of the destination register 07H 11110001B leaving the new value OEH 00001110B ELECTRONICS INSTRUCTION SET S3C84E5 C84E9 P84E9 CP Compare CP Operation Flags Format Examples dst src dst src The source operand is compared to subtracted from the destination operand and the appropriate flags are set accordingly The contents of both operands are unaffected by the comparison Set if a borrow occurred src gt dst cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 A3 r Ir opc src dst 3 6 A4
161. figuration Bits o o Input mode with pull up T1CAPO input ofa Input mode T1CAPO input Push pull output mode P0 4 T1OUT1 Configuration Bits Push pull output mode Alternative function mode T1OUT1 output ELECTRONICS S3C84E5 C84E9 P84E9 CONTROL REGISTER POCONL Port 0 Control Register Low Byte E7H Set 1 Bank 0 Reset Value 0 0 0 0 1 1 1 1 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P0 3 T1CK1 Configuration Bits Input mode with pull up T1CK1 input ESEJ Input mode T1CK1 input Push pull output mode 5 4 P0 2 T1CAP1 Configuration Bits o o Input mode with pull up T1CAP1 input Input mode T1CAP1 input Push pull output mode 3 2 P0 1 XTout Configuration Bits o o _ o r mume 1 0 P0 0 XTin Configuration Bits OO Imutmodewthpulup 011 iim 0 K EEN Push pull output mode Alternative function mode Sub oscillator input XTin ELECTRONICS 4 15 CONTROL REGISTERS S3C84E5 C84E9 P84E9 P1CONH Port 1 Control Register High Byte E8H Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write _ _ _ _ R W R W R W R W Addressing Mode Register addressing mode only 7 4 Not used for the S3C84E5 C84E9 P84E9 must keep always 0 3 2 P1 5 TXD Configuration Bits 0
162. format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Flag settings that may be affected by the instruction Detailed description of the instruction s format execution time and addressing mode s Programming example s explaining how to use the instruction ELECTRONICS 6 13 INSTRUCTION SET S3C84E5 C84E9 P84E9 ADC Add with Carry ADC dst src Operation dst dst src The source operand along with the carry flag setting is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed In multiple precision arithmetic this instruction lets the carry value from the addition of low order operands be carried into the addition of high order operands Flags C Setif there is a carry from the most significant bit of the result cleared otherwise Z Setif the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V Setif arithmetic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to O H Setif there is a carry from the most significant bit of the low order four bits of the result cleared otherwise Format Bytes Cycles Opcode Addr Mode Hex dst src 6 13 r Ir opc src dst 3 6 14 R R 15 R IR opc dst src 3 6 16 R IM
163. gister pointers are selected RP0 3 is then cleared to logic zero and RP1 3 is set to logic one No flags are affected Bytes Cycles Opcode Addr Mode Hex src src 2 4 31 IM The statement SRP 40H sets the register pointer 0 RP0 at the location 0D6H to 40H and the register pointer 1 RP1 at the location 0D7H to 48 H The statement SRP0 50H would set RPO to 50H and the statement SRP1 68H would set RP1 to 68H Before execute the STOP instruction You must set the STPCON register 101001010 Otherwise the STOP instruction will not execute ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET STOP Stop Operation STOP Operation Flags Format Example The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode During Stop mode the contents of on chip CPU registers peripheral registers and port control and data registers are retained Stop mode be released by an external reset operation or by external interrupts For the reset operation the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 7F statement STOP halts all microcontroller operations ELECTRONICS 6 81 INSTRUCTION SET S3C84E5 C84E9 P84E9 SU B subtract SUB Operation Flags Format Examples
164. gister High Byte mono 2 R 0 counter register Low Byte menno 5 rR Timer 101 counter resister Hion Byte Timm ze R Timer 5 counter register Low 29 27 EH R UART baud rate data register High Byte es MEME MUNERE UM UART baud rate data register Low Byte BRDATAL 239 Location FOH FFH are not mapped ELECTRONICS 4 3 CONTROL REGISTERS S3C84E5 C84E9 P84E9 Bit number s that is are appended to Name of individual the register name for bit addressing bit or related bits Register location Register address in the internal Register ID Register name hexadecimal register file FLAGS System Flags Register Bit Identifier ES 4 RESET Value x x x x x x 0 0 Read Write R W R W R W R W R W R W R R W Bit Addressing Register addressing mode only Mode 7 Carry Flag C Operation does not generate a carry or borrow conditio Operation generates carry out or borrow into high order bit 7 Zero Flag Z Operation result is a non zero value Operation result is zero ign Flag S Operation generates positive number MSB 0 Operation generates negative number MSB 1 R Read only Description of the W Write only effect of specific RAN Read write bit settings RESET value notation Not used Not used x Undetermined value Type of addressing 0 Logic zero that must be used to 1 Logic one
165. h pull up 0 1 Input mode 1 0 Push pull output mode 1 1 Alternative function mode ADC6 input 3 2 P3 5 ADC5 Configuration Bits 0 0 Input mode with pull up 0 1 Input mode 1 0 Push pull output mode 1 1 Alternative function mode ADC5 input 1 0 P3 4 ADCA Configuration Bits 0 0 Input mode with pull up 0 1 2 Input mode 1 0 Push pull output mode 1 1 Alternative function mode ADCA input Figure 9 9 Port 3 High Byte Control Register P3CONH 9 12 ELECTRONK S S3C84E5 C84E9 P84E9 VO PORTS Port 3 Control Register Low Byte P3CONL Set1 R W Reset value 00 7 6 P3 3 ADC3 Configuration Bits 0 0 Input mode with pull up 0 1 Input mode 1 0 Push pull output mode 1 1 Alternative function mode ADC3 input 5 4 P3 2 ADC2 Configuration Bits 0 0 Input mode with pull up 0 1 2 Input mode 1 0 Push pull output mode 1 1 Alternative function mode ADC2 input 3 2 P3 1 ADC1 Configuration Bits 0 0 Input mode with pull up 0 1 Input mode 1 0 Push pull output mode 1 1 Alternative function mode ADC1 input 1 0 P3 0 ADCO Configuration Bits 0 0 Input mode with pull up 0 1 2 Input mode 1 0 Push pull output mode 1 1 Alternative function mode ADCO input Figure 9 10 Port 3 Low Byte Control Register PSCONL ELECTRONICS 9 13 PORTS S3C84E5 C84E9 P84E9 PORT 4 Port 4 is a 6 bit I O port that you can use two ways
166. he three low order bits of the complete address are provided by the original instruction Figure 2 14 shows an example of 8 bit working register addressing The four high order bits of the instruction address 1100B specify 8 bit working register addressing Bit 3 1 selects RP1 and the five high order bits in RP1 10101B become the five high order bits of the register address The three low order bits of the register address 011 are provided by the three low order bits of the 8 bit instruction address The five address bits from RP1 and the three address bits from the instruction are concatenated to form the complete register address 10101011 Selects RPO Address These address bits indicate 8 bit 8 bit logical working register address addressing Register pointer Three low order bits provides five high order bits 8 bit physical address Figure 2 13 8 Bit Working Register Addressing ELECTRONICS 2 17 ADDRESS SPACES RP0 Selects RP1 R11 8 bit address 1100 11 011 form instruction LD R11 R2 Specifies working register addressing Figure 2 14 8 Bit Working Register Addressing Example S3C84E5 C84E9 P84E9 Register address OABH ELECTRONICS S3C84E5 C84E9 P84E9 ADDRESS SPACES SYSTEM AND USER STACK The S3C8 series microcontrollers use the system stack for data storage subroutine calls and returns The PUSH and POP instructions
167. herwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 80 RR 81 IR Examples Given RO 12H R1 R2 30H register 30H and register 21H DECW RRO gt RO 12H R1 33H DECW R2 gt Register OFH register 31H 20H In the first example the destination register RO contains the value 12H and the register R1 the value The statement DECW RRO addresses RO and the following operand R1 as a 16 bit word and decrements the value of R1 by one leaving the value 33H NOTE Asystem malfunction may occur if you use a Zero flag FLAGS 6 result together with a DECW instruction To avoid this problem it is recommended to use DECW as shown in the following example LOOP DECW RRO LD R2 R1 OR R2 RO JR NZ LOOP 6 36 ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET DI Disable Interrupts DI Operation Flags Format Example SYM 0 0 Bit zero of the system mode control register SYM 0 is cleared to 0 globally disabling all interrupt processing Interrupt requests will continue to set their respective interrupt pending bits but the CPU will not service them while interrupt processing is disabled No flags are affected Bytes Cycles Opcode Hex 1 4 8F Given SYM 01H DI If the value of the SYM register is 01H the statement DI leaves the new value 00H in the register and clears SYM 0 to 0
168. ic timer control register BTCON 17 6 ELECTRONICS S3C84E5 C84E9 P84E9 ELECTRICAL DATA t tosc Vo F q LIXH Figure 17 3 Clock Timing Measurement at X Table 17 7 Sub Oscillator Frequency fosco TA 25 85 Vpp Vi vn to 5 5 V clock rout Test Condition Win Max Umi Crystal Crystal oscillation frequency 32 32 768 34 kHz C1 100 pF C2 100 pF R R 330 XTn and XTour are connected J C1 J C2 with R and C by soldering Table 17 8 Subsystem Oscillator crystal Stabilization Time Ta 25 C Test Condition Normal mode Vpp 4 5 V to 5 5 V Vpp to 3 3 V Strong mode Vpp 4 5 V to 5 5 V Urera s s NOTE Oscillation stabilization time ts is the time required for the oscillator to it s normal oscillation when stop mode is released by interrupts The value Typ and Max are measured by buzzer output signal after stop release For example in voltage range of 4 5 V to 5 5 V of normal mode we can see the buzzer output signal within 400 ms at our test condition ELECTRONICS 17 7 ELECTRICAL DATA S3C84E5 C84E9 P84E9 Table 17 9 Data Retention Supply Voltage in Stop Mode TA 25 C to 85 G Vpp Vi vn to 5 5 V Data retention Vpppn Stop mode 2 5 5 supply voltage Data retention IpppR Stop mode Vpppg 2 0 V supply current NOTE Supply current doe
169. ill not be activated if a valid stop bit was not received In mode 0 the MCE UARTCON 5 bit should be 2 The descriptions for 8 bit and 9 bit UART mode do not include start and stop bits for serial data receive and transmit Parity enable bits PEN are located in the UARTPND register at address F4H bank 0 4 Parity enable and parity error check can be available in 9 bit UART mode Mode 2 only eT ELECTRONICS 4 39 CONTROL REGISTERS S3C84E5 C84E9 P84E9 UARTPND uanT Pending and parity control F4H Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write _ _ R W R W _ _ R W R W 7 6 Not used for the S83C84E5 C84E9 P84E9 must keep always 0 5 UART Parity Enable Disable PEN 4 UART Receive Parity Error RPE opjoen 3 2 Not used for the S83C84E5 C84E9 P84E9 must keep always 0 41 UART Receive Interrupt Pending Flag 0 Not pending Clear pending bit when write Interrupt pending NOTES 1 In order to clear a data transmit or receive interrupt pending flag you must write a 0 to the appropriate pending bit 2 To avoid programming errors we recommend using load instruction except for LDB when manipulating UARTPND values 3 Parity enable and parity error check can be available in 9 bit UART mode Mode 2 only 4 Parity error bit RPE will be refreshed whenever 8th receive data bit has been shifted 4 40 ELEGTRONIGS S3C84E5 C84E9 P84E9 CONTROL REGISTER WTCON Watch Timer Control Register FAH S
170. ing that it contains the value OCH In the third example INC is used in Indirect Register IR addressing mode to increment the value of the register 1BH from OFH to 10H ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET INCW Increment Word INCW Operation Flags Format Examples NOTE dst dst dst 1 The contents of the destination which must be an even address and the byte following that location are treated as a single 16 bit value that is incremented by one C Unaffected Set if the result is 0 cleared otherwise Set if the result is negative cleared otherwise Unaffected Z s V Set if arithmetic overflow occurred cleared otherwise D H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 A0 RR 8 A1 IR Given RO R1 02H register 02H OFH and register INCW RR0 gt RO 1AH R1 INCW R1 gt Register 02H 10H register 03H OOH In the first example the working register pair RRO contains the value 1AH in the register RO and 02H in the register R1 The statement INCW RRO increments the 16 bit destination by one leaving the value 03H in the register R1 In the second example the statement INCW R1 uses Indirect Register IR addressing mode to increment the contents of the general register from to OOH and the register 02H from OFH to 10H A system malfunction may occur if you use a Zero Z flag FL
171. ion the BT counter clear operation will not be executed and a basic timer overflow will occur initiating a reset In other words during the normal operation the basic timer overflow loop a bit 7 overflow of the 8 bit basic timer counter BTCNT is always broken by a BTCNT clear instruction If a malfunction does occur a reset is triggered automatically Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when Stop mode has been released by an external interrupt In Stop mode whenever a reset or an external interrupt occurs the oscillator starts The BTCNT value then starts increasing at the rate of fxx 4096 for reset or at the rate of the preset clock source for an external interrupt When BTCNT 4 overflows a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation In summary the following events occur when stop mode is released 1 During stop mode a power on reset or an interrupt occurs to trigger the Stop mode release and oscillation starts 2 If a power on reset occurred the basic timer counter will increase at the rate of fxx 4096 If an external interrupt is used to release stop mode the BTCNT value increases at the rate of the preset clock source Clock oscillation stabilization interval begins and continues until bi
172. ion is arranged in the following order Absolute maximum ratings Input output capacitance D C electrical characteristics A C electrical characteristics Oscillation characteristics Oscillation stabilization time Data retention supply voltage in stop mode UART timing characteristics in mode 0 A D converter electrical characteristics ELECTRONICS ELECTRICAL DATA S3C84E5 C84E9 P84E9 Table 17 1 Absolute Maximum Ratings TA 25 Parameter Um Supply voltage Yoo 30465 Output voltage All output ports 0 3 to VDD 0 3 Output current high One active mA AIL I O pins active 2 06 Output current low One I O pin active Operating 25 to 85 temperature Storage temperature 6510 150 to 6510 150 150 Table 17 2 Input Output Capacitance Ta 25 C to 85 Vpg OV Input capacitance f 1 MHz unmeasured pins are tied to Output capacitance 17 2 ELECTRONICS S3C84E5 C84E9 P84E9 ELECTRICAL DATA Table 17 3 D C Electrical Characteristics TA 25 C to 85 C Vpp Vi to 5 5 V WI mar is ua All port nRESET Ex I x and XT All ports and nRESET Dm eem Sf XIN and XTIN Output high voltage Vpp 5 5 V fre 1 All ports Output low voltage Vou Vpp 5 5 V lo 15 mA i Ports 0 and 4 Ports 1 2 and 3 current All input pins except i
173. ircuit Diagram to Improve EFT Characteristics NOTE To improve EFT characteristics we recommend using power capacitor near S3C84E5 C84E9 P84E9 like Figure 17 9 17 12 ELECTRONICS S3C84E5 C84E9 P84E9 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3C84E5 C84E9 P84E9 microcontrollers are available in a 42 SDIP 600 44 QFP 1010 package 14 00 0 20 39 50 MAX 39 10 0 20 T IT LI TT LI LI LI LI LI I 0 50 20 10 1 00 20 10 3 50 0 20 5 08 WAKA AA 3 30 70 30 NOTE Dimensions are in millimeters Figure 18 1 42 SDIP 600 Package Dimensions ELECTRONICS 18 1 MECHANICAL DATA S3C84E5 C84E9 P84E9 13 20 0 3 0 80 0 20 44 QFP 1010 0 10 MAX OO SO Hy a S 2 o 0 05 MIN 2 05 0 10 2 30 MAX NOTE Dimensions are in millimeters Figure 18 2 44 QFP 1010 Package Dimensions 18 2 ELECTRONICS S3C84E5 C84E9 P84E9 OTP VERSION S3P84E9 OTP VERSION OVERVIEW S3P84E9 single chip CMOS microcontroller is the OTP One Time Programmable version of the S3C84E5 C84E9 microcontroller It has an on chip EPROM instead of a masked ROM The EPROM is accessed by serial data format The S3P84E9 is fully compatible with the S3C84E5 C84Eg9 both in function in D C electrical characteristics and in pin configuration Because of its simple programming requirements the S3P84E9 is ideal as an evaluation chip for the S8C84E5 C84E9 P1 0 T
174. ircuit UART A D Converter 12 1 8 1 16 3 Selector 2 System CPU IDLE Instruction Figure 7 3 System Clock Circuit Diagram 7 2 ELECTRONICS S3C84E5 C84E9 P84E9 REV 0 CLOCK CIRCUIT SYSTEM CLOCK CONTROL REGISTER CLKCON The system clock control register CLKCON is located in set 1 address It is read write addressable and has the following functions Oscillator frequency divide by value After the main oscillator is activated and the fxx 16 the slowest clock speed is selected as the CPU clock If necessary you can then increase the CPU clock speed fxx 8 fxx 2 or fxx 1 System Clock Control Register CLKCON Set 1 RW 7 e s o i o Not used must keep always 0 Not used must keep always 0 Divide by selection bits for CPU clock frequency 00 fxx 16 01 5 8 10 fxx 2 11 fxx 1 non divided NOTE The fxx can be generated by both main system and sub system oscillator therefore while main system stops peripherals can be operated by sub system Figure 7 4 System Clock Control Register CLKCON ELECTRONICS 7 8 CLOCK CIRCUIT S3C84E5 C84E9 P84E9 Oscillator Control Register OSCCON FBH Set 1 Bank 0 R W Not used must keep always 0 Not used must keep always 0 System clock selection bit 0 Main oscillator select 1 Subsystem oscillator select Subsystem oscillator driving ability control bi
175. issue interrupt requests In other words peripheral and operations interrupt driven There are eight possible interrupt levels IRQ0 IRQ7 also called level 0 level 7 Each interrupt level directly corresponds to interrupt request number IRQn The total number of interrupt levels used in the interrupt structure varies from device to device The S3C84E5 C84E9 P84E9 interrupt structure recognizes eight interrupt levels The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels They are just identifiers for the interrupt levels that are recognized by the CPU The relative priority of different interrupt levels is determined by settings in the interrupt priority register IPR Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels Vectors Each interrupt level can have one or more interrupt vectors or it may have no vector address assigned at all The maximum number of vectors that can be supported for a given level is 128 The actual number of vectors used for S3C8 series devices is always much smaller If an interrupt level has more than one vector address the vector priorities are set in hardware S3C84E5 C84E9 P84E9 uses twenty one vectors Sources A source is any peripheral that generates an interrupt A source can be an external pin or a counter overflow Each vector can have several interrupt
176. it for checking the received data In parity enable mode PEN 1 UARTCON 3 TB8 UARTCON 2 RB8 will be a parity selection bit for transmit and receive data respectively The UARTCON 3 8 is for settings of the even parity generation TB8 0 or the odd parity generation TB8 0 in the transmit mode The UARTCON 2 RB8 is also for settings of the even parity checking RB8 0 or the odd parity checking RB8 1 in the receive mode The parity enable generation checking functions are not available in UART mode 0 and 1 If you don t want to use a parity mode UARTCON 2 RB8 and UARTCON 3 8 are a normal control bit as the 9 data bit in this case PEN must be disable 0 in mode 2 Also it is needed to select the 9th data bit to be transmitted by writing TB8 to 0 or 1 The receive parity error flag RPE will be set to 0 or 1 depending on parity error whenever the 8 data bit of the receive data has been shifted UART DATA REGISTER UDATA UART Data Register UDATA F5H Set1 Bank 0 R W Reset Value FFH Transmit or Receive data Figure 13 3 UART Data Register UDATA ELECTRONICS 13 5 UART S3C84E5 C84E9 P84E9 UART BAUD RATE DATA REGISTER BRDATAH BRDATAL The value stored in the UART baud rate register BRDATAH BRDATAL lets you determine the UART clock rate baud rate UART Baud Rate Data Register BRDATAH EEH Set1 Bank 0 R W Reset Value FFH BRDATAL EFH Set1 Bank 0 R W R
177. jo s Xin Xour and XTi XTour current All input pins except and 12 0 20 Ne NN All output pins 1 Output low leakage lo Vour 0V current All output pins ELECTRONICS 17 3 ELECTRICAL DATA S3C84E5 C84E9 P84E9 Table 17 3 D C Electrical Characteristics Continued TA 25 to 85 G Vpp Vi vn to 5 5 V Vpp 5 V Vn 0 V TA 25 C All I O pins except nRESET Vpp 3 V Vin 0 V Ta 25 C All I O pins except nRESET Vpp 5 V Vin 0 V Ta 25 C nRESET only Vpp 3 V Vin 0 V 25 C nRESET only Supply current 1 Vpp 4 5 V to 5 5V RUN mode 12 MHz CPU clock Idle mode 12 MHz CPU clock Sub operating main osc stop 32768 Hz crystal oscillator Sub idle mode main osc stop Vyr to 3 3 V 32768 Hz crystal oscillator Vpp 4 5 V to 5 5 V Ta 25 C Stop mode Vpp Vivn to 3 3 V 25 C Stop mode NOTES 1 Supply current does not include current drawn through internal pull up resistors or external output current loads Ippi and Ippo include a power consumption of subsystem oscillator 2 and Ipp are the current when the main system clock oscillation stop and the subsystem clock is used 4 is the current when the main and subsystem clock oscillation stop 5 All currents Ipp4 pps include the current consumption of LVR circuit 17 4 ELECTRONICS S3C84E5 C84E9 P84E9 ELECTRICAL DATA Table 17
178. l Register F2H Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W Addressing Mode Register addressing mode only 7 3 Not used for the S3C84E5 C84E9 P84E9 must keep always 0 2 P4 2 External Interrupt INT10 Enable Bit Disable interrupt 1 Enable interrupt 1 P4 1 External Interrupt INT9 Enable Bit Disable interrupt Enable interrupt 0 P4 0 External Interrupt INT8 Enable Bit Disable interrupt Enable interrupt S3C84E5 C84E9 P84E9 CONTROL REGISTER PAINTPND Port 4 Interrupt Pending Register F3H Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write _ R W R W R W Addressing Mode Register addressing mode only 7 3 Not used for the S3C84E5 C84E9 P84E9 must keep always 0 2 P4 2 PND10 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 4 P4 1 PND9 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 0 P4 0 PND8 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending ELECTRONICS 4 2 N CONTROL REGISTERS S3C84E5 C84E9 P84E9 PP _ Register Page Pointer DFH Set1 Bit Identifier 7 6 s 4 3 2 o 0 0 0 0 0 0 0 0 Reset Value Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Destination Register
179. mbedded Using a proven modular design approach Samsung engineers have successfully developed the S3C84E5 C84E9 P84E9 by integrating the following peripheral modules with the powerful SAM8 core Five programmable I O ports 42SDIP 34pins 44QFP 36pins Eleven bit programmable pins for external interrupts One 8 bit basic timer for oscillation stabilization and watchdog function system reset Two 8 bit timer counter and Two 16 bit timer counter with selectable operating modes One asynchronous UART 10 bit 8 channel A D converter The S3C84E5 C84E9 P84E9 is versatile microcontroller for home appliances and ADC applications etc They are currently available in 44 pin QFP and 42 pin SDIP package ELECTRONICS 1 1 PRODUCT OVERVIEW FEATURES CPU e SAMB88RC CPU core Memory e 528 bytes internal register file e 16K 32Kbytes internal program memory S3C84E5 C84E9 Mask ROM S3P84E9 OTP Oscillation Sources e Main clock oscillator Crystal Ceramic e CPU clock divider 1 1 1 2 1 8 1 16 e 32 768 2 Sub oscillator for watch timer Instruction Set e 78 instructions IDLE and STOP instructions added for power down modes Instruction Execution Time e 333 ns at 12 MHz fOSC minimum Interrupts e 21 interrupt sources with 21 vectors e 8 level 21 vector interrupt structure I O Ports e Total 36 bit programmable pins 44QFP Total 34 bit programmable pins 42SDIP Timers and Timer Cou
180. mp to IRET at the address FFH This loads the instruction pointer with 100H again and causes the program counter to jump back to the main program Now the next interrupt can occur and the is still correct at 100H 0H FFH 100H Interrupt Service Routine JP to FFH FFFFH In the fast interrupt example above if the last instruction is not a jump to IRET you must pay attention to the order of the last tow instruction The IRET cannot be immediately proceeded by an instruction which clears the interrupt status as with a reset of the IPR register ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET JP Jump JP cc dst Conditional JP dst Unconditional Operation If cc istrue PC dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code cc is true otherwise the instruction following the JP instruction is executed The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair Control then passes to the statement addressed by the PC Flags No flags are affected Format 1 Bytes Cycles Opcode Addr Mode 2 Hex dst cc 0to F opc dst 2 8 30 IRR NOTES 1 The 3 byte format is used for a conditional jump and the 2 byte format for an unconditional jump 2 In the first byte of the 3 byte instruction format conditional jump the condition code and the OPCODE are both four bits
181. n operand is not the result of a valid H Flag Before DA O O O O o Bits 0 3 Number Added Value Hex to Byte 0 9 00 A F 06 0 3 06 0 9 60 A F 66 0 3 66 0 9 60 A F 66 0 3 66 0 9 00 00 6 F 06 0 9 A0 60 6 F 9A 66 Carry After DA 0 0 O Setifthere was carry from the most significant bit cleared otherwise see table S Set if result bit 7 is set cleared otherwise ELECTRONICS dst Bytes Cycles Opcode Hex 40 41 Addr Mode dst R IR 6 33 INSTRUCTION SET S3C84E5 C84E9 P84E9 DA Decimal Adjust DA Example Continued Given The working register RO contains the value 15 BCD the working register R1 contains 27 BCD and the address 27H contains 46 BCD ADD R1 RO e lt 0 Bits 4 7 3 bits 0 3 C R1 lt DA R1 R1 lt 06 If addition is performed using the values 15 27 the result should 42 sum is incorrect however when the binary representations are added in the destination location using the standard binary arithmetic 0001 0101 15 0010 0111 27 0011 1100 The DA instruction adjusts this result so that the correct BCD representation is obtained 0011 1100 0000 0110 0100 0010 42 Assuming the same values given above the statements SUB 27H R0 C lt 0 Bits 4 7 3 bits
182. nal clock source Oscillator stop and wake up functions Programmable frequency divider for the CPU clock fxx divided by 1 2 8 or 16 System clock control register CLKCON Oscillator control register OSCCON and STOP control register STPCON XTINP0 0 S3C84E5 S3C84E9 S3P84E9 XTour PO 1 XIN S3C84E5 S3C84E9 S3P84E9 Xour 32 768 kHz Figure 7 1 Main Oscillator Circuit Figure 7 2 Sub System Oscillator Circuit Crystal or Ceramic Oscillator Crystal Oscillator ELECTRONICS 7 1 CLOCK CIRCUIT S3C84E5 C84E9 P84E9 CLOCK STATUS DURING POWER DOWN MODES The two power down modes Stop mode and Idle mode affect the system clock as follows In Stop mode the main oscillator is halted Stop mode is released and the oscillator is started by a reset operation or an external interrupt with RC delay noise filter and can be released by internal interrupt too when the sub system oscillator is running and watch timer is operating with sub system clock In Idle mode the internal clock signal is gated to the CPU but not to interrupt structure timers timer counters Idle mode is released by a reset or by an external or internal interrupt Stop Release 9 Driving Ability OSCCON 4 Main System Sub system Watch Timer Oscillator Oscillator Circuit Circuit Selector 1 OSCCON 3 OSCCON 0 OSCCON 2 STOP OSC 1 8 1 4096 Basic Timer inst Timer Counter Watch Timer fxx 256 STPCON icu C
183. ng register slice have the same binary value for their five most significant address bits This makes it possible for each register pointer to point to one of the 24 slices in the register file other than set 2 The base addresses for the two selected 8 byte register slices are contained in register pointers RP0 and RP1 After a reset RPO RP1 always point to the 16 byte common area in set 1 Slice 32 11111XXX Slice 31 RP1 Registers R8 R15 Each register pointer points to one 8 byte slice of the register space selecting a total 16 byte working register block 00000XXX RPO Registers RO R7 Figure 2 5 8 Byte Working Register Areas Slices ELECTRONICS 2 9 ADDRESS SPACES S3C84E5 C84E9 P84E9 USING THE REGISTER POINTERS Register pointers RPO and RP1 mapped to addresses D6H and D7H in set 1 are used to select two movable 8 byte working register slices in the register file After a reset RP point to the working register common area RP0 points to addresses COH C7H and RP1 points to addresses C8H CFH To change a register pointer value you load a new value to RPO and or RP1 using an SRP or LD instruction see Figures 2 6 and 2 7 With working register addressing you can only access those two 8 bit slices of the register file that are currently pointed to by RPO and RP1 You cannot however use the register pointers to select a working register space in set 2 because these locati
184. ns Table 6 6 Condition Codes Wa mnm mis _ Always false Always true II Carry II II Zero Not zero Plus Minus Overflow No overflow 0 0 1 1 0 1 Equal II Not equal gt Greater than or equal Less than Greater than Less than or equal Unsigned greater than or equal Unsigned less than Unsigned greater than OR V 0 OR V 1 S V 0 XOR V 1 O qq m N II 0 AND Z 0 1 Unsigned less than or equal C OR Z 1 NOTES 1 Itindicate condition codes which are related to two different mnemonics but which test the same flag For example Z and EQ are both true if the zero flag Z is set but after an ADD instruction Z would probably be used Following a CP instruction you would probably want to use the instruction EQ 2 Foroperations using unsigned numbers the special condition codes UGE ULT UGT and ULE must be used 6 12 ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET INSTRUCTION DESCRIPTIONS This Chapter contains detailed information and programming examples for each instruction in the S3C8 series instruction set Information is arranged in a consistent format for improved readability and for quick reference The following information is included in each instruction description Instruction name mnemonic Full instruction name Source destination
185. ns ADC dst src Add with carry ADD dst src Add CP dst src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst src Divide INC dst Increment INCW dst Increment word MULT dst src Multiply SBC dst src Subtract with carry SUB dst src Subtract Logic Instructions AND dst src Logical AND COM dst Complement OR dst src Logical OR XOR dst src Logical exclusive OR ELECTRONICS 6 3 INSTRUCTION SET S3C84E5 C84E9 P84E9 Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Program Control Instructions BTJRF dst src Bit test and jump relative on false BTJRT dst src Bit test and jump relative on true CALL dst Call procedure dst src Compare increment and jump on equal dst src Compare increment and jump on non equal DJNZ r dst Decrement register and jump on non zero ENTER Enter EXIT Exit IRET Interrupt return JP cc dst Jump on condition code JP dst Jump unconditional JR cc dst Jump relative on condition code NEXT Next RET Return WFI Wait for interrupt Bit Manipulation Instructions BAND dst src Bit AND BCP dst src Bit compare BITC dst Bit complement BITR dst Bit reset BITS dst Bit set BOR dst src Bit OR BXOR dst src Bit XOR TCM dst src Test complement under mask TM dst src Test under mask 6 4 ELECTRONICS S3C84E5 C84E9 P84E9 Mnemonic Rotate and Shift Instructions RL dst RLC dst RR dst RRC dst SRA dst SWAP dst
186. nstruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src SE 3 2 G r h Given R1 02H R2 and register 02H CPIJE R1 R2 SKIP gt R2 04H PC jumps to SKIP location In this example the working register R1 contains the value 02H the working register R2 the value 03H and the register 03 contains 02H The statement CPIJE R1 R2 SKIP compares the R2 value 02H 00000010B to 02H 00000010B Because the result of the comparison is equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source register R2 is incremented by one leaving a value of 04H Remember that the memory location addressed by the CPIJE instruction must be within the allowed range of 127 to 128 ELECTRONICS 6 31 INSTRUCTION SET S3C84E5 C84E9 P84E9 CPIJNE Compare Increment and Jump on Non Equal CPIJNE Operation Flags Format Example dst src RA If dst src j 0 PC PC RA Ir Ir 1 The source operand is compared to subtracted from the destination operand If the result is not 0 the relative address is added to the program counter and control passes to the statement whose address is now in the program counter Otherwise the instruction following the CPIJNE instruction is executed In either case the source pointer is incremented by one before the next instruction No flags are affected Bytes Cycle
187. nters programmable 8 bit basic timer BT for oscillation stabilization control or watchdog timer function e 8 bit timer counter Timer A with three operating modes Interval mode capture mode and PWM mode 8 bit timer Timer B with carrier frequency or PWM generator e Two 16 bit timer counter Timer 10 11 with three operating modes Interval mode Capture mode and PWM mode S3C84E5 C84E9 P84E9 Watch timer e Real time and interval time measurement e Four frequency outputs for buzzer sound A D Converter e 10 bit resolution e Eight analog input channels 20us conversion speed at 10 2 fang clock Asynchronous UART e One Asynchronous UART e Programmable baud rate generator e Supports serial data transmit receive operations with 8 bit 9 bit in UART Built in RESET Circuit LVR e Low Voltage reset LVR value 2 9V Oscillation Frequency e 1MHz to 12MHz external crystal oscillator Operating Temperature Range e 25 C to 85 C Operating Voltage Range to 5 5V Package Type 42 pin SDIP 44 pin QFP ELECTRONICS S3C84E5 C84E9 P84E9 PRODUCT OVERVIEW BLOCK DIAGRAM P0 0 P0 7 P1 0 P1 5 55252242 99997 Port 0 Port 1 Xin Xout XTout OSC nRESET nRESET gt 8 Bit I O Port and Interrupt Control Basic Timer P1 0 TAOUT none PRO B TACK lt P4 3 TBPWM CPU 2 0 2 7 INTO INT7 P3
188. o of the register RO to the specified bit bit zero of the destination register leaving 04H in the general register 00H ELECTRONICS 6 51 INSTRUCTION SET S3C84E5 C84E9 P84E9 LDC LDE Load Memory LDC dst src LDE dst src Operation dst src This instruction loads a byte from program or data memory into a working register or vice versa The source values are unaffected LDC refers to program memory and LDE to data memory The assembler makes Irr or rr values an even number for program memory and an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src C3 r Irr i N E dst src 2 10 D3 Irr r 7 dst 0000 DA 4 14 A7 r DA 8 opc src 0000 DAL DAY 4 14 B7 DA r 9 dst 0001 DA 4 14 7 DA 10 src 0001 DA DAY 4 14 B7 DA r NOTES 1 The source src or the working register pair rr for formats 5 and 6 cannot use the register pair 0 1 2 Forthe formats 3 and 4 the destination XS rr and the source address XS rr are both one byte 3 Forthe formats 5 and 6 the destination XL rr and the source address XL rr are both two bytes 4 The DA and ther source values for the formats 7 and 8 are used to address program memory The second set of values used in the formats 9 and 10 are used to address data memory 5 LDE instruction can be used to read write the data of 64 Kbyte data memory 6 52
189. o was 1 Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 D0 R D1 IR Given Register 9AH register 02H 03H register 03H OBCH and 1 SRA 00H gt Register OOH OCD C 0 SRA 02H gt Register 02H 03H register 03H ODEH C 0 In the first example if the general register OOH contains the value 10011010 the statement SRA OOH shifts the bit values in the register right one bit position Bit zero 0 clears the C flag and bit 7 1 is then shifted into the bit 6 position bit 7 remains unchanged This leaves the value 11001101B in the destination register OOH ELECTRONICS 6 79 INSTRUCTION SET S3C84E5 C84E9 P84E9 SRP SRP0 SRP1 set Register Pointer SRP SRP0 SRP1 Operation Flags Format Examples NOTE 6 80 src src src If src 1 1 and src 0 O then RPO 3 7 lt src 3 7 If src 1 0 and src 0 1then RP1 3 7 lt src 3 7 If src 1 0 and src 0 Othen RPO 4 7 lt src 4 7 RPO 3 lt 0 RP1 4 7 lt src 4 7 3 lt 1 The source data bits zero LSB determine whether write both of the register pointers RP0 and RP1 Bits 3 7 of the selected register pointer are written unless both re
190. o value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask which is ANDed with the destination operand The zero Z flag can then be checked to determine the result The destination and the source operands are unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always reset to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 73 r Ir src dst 3 6 74 R R 6 75 R IR opc dst src 3 6 76 R IM Given RO R1 02H R2 18H register 00H 2BH register 01H 02H register 02H 23H TM RO R1 gt RO OC7H R1 02H 2 0 RO R1 gt RO OC7H R1 02H register 02H 23H 2 TM 00H 01H gt Register OOH 2BH register 01H 02H Z 0 TM 00H 01H gt Register OOH 2BH register 01H 02H register 02H 23H Z TM 00H 54H gt Register 00H 2BH Z 1 In the first example if the working register RO contains the value 0C7H 11000111B and the register R1 the value 02H 00000010B the statement TM RO R1 tests bit one in the destination register for a 0 value Because the mask value does not match the test bit the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation ELECTRONICS 6 85 INSTRUCTION SET S3C84E5 C84E9 P84E9 WEI wate for Interrupt WFI Operati
191. on Before After Address Data 1P PC 0130 Data Address Data Address H Address L Address H Address Data 43 Address H 01 7 Address L 30 45 Address H Routine 120 Memory Memory ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET Operation NOP Operation Flags Format Example No action is performed when the CPU executes this instruction Typically or more NOPs are executed in sequence in order to affect a timing delay of variable duration No flags are affected Bytes Cycles Opcode Hex 1 4 FF When the instruction is executed in a program no operation occurs Instead there happens a delay in instruction execution time which is of approximately one machine cycle per each NOP instruction encountered ELECTRONICS 6 61 INSTRUCTION SET S3C84E5 C84E9 P84E9 OR Logical OR OR Operation Flags Format Examples dst src dst dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination The contents of the source are unaffected The OR operation results in a 1 being stored whenever either of the corresponding bits in the two operands is a 1 otherwise a 0 is stored C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected
192. on Flags Format Example 6 86 The CPU is effectively halted before an interrupt occurs except that DMA transfers can still take place during this wait state The WFI status can be released by an internal interrupt including a fast interrupt No flags are affected Bytes Cycles Opcode Hex 1 4n 3F 1 2 3 The following sample program structure shows the sequence of operations that follow a WFI statement Main program El Enable global interrupt WFI Wait for interrupt Next instruction Interrupt occurs Interrupt service routine Clear interrupt flag IRET Service routine completed ELECTRONICS S3C84E5 C84E9 P84E9 XOR Logical Exclusive OR XOR Operation Flags Format Examples dst src dst dst XOR src INSTRUCTION SET The source operand is logically exclusive ORed with the destination operand and the result is stored in the destination The exclusive OR operation results in a 1 bit being stored whenever the corresponding bits in the operands are different Otherwise a 0 bit is stored C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always reset to 0 D Unaffected H Unaffected Bytes Cycles Opcode Hex 6 B3 src dst 3 6 B4 6 B5 opc dst src 3 6 B6 Given RO R1 02H R2 18H register 00H 2BH register 01H 02H and register 0
193. on The 8 bit or 16 bit offset given in the instruction is then added to that base address see Figure 3 9 The only instruction that supports indexed addressing mode for the internal register file is the Load instruction LD The LDC and LDE instructions support indexed addressing mode for internal program memory and for external data memory when implemented Register File or RP1 Value used in points to Instruction y OPERAND start of working register block Program Memory usd Base Address wo Operan dst src x INDEX Instruction Point to One of the 211 Example Woking Register 1 048 Sample Instruction LD RO BASE R1 Where BASE is an 8 bit immediate value Figure 3 7 Indexed Addressing to Register File ELECTRONICS 3 7 ADDRESSING MODES S3C84E5 C84E9 P84E9 INDEXED ADDRESSING MODE Continued Register File c ices C al RPO or RP1 RPO or RP1 Selected RP points to start of ki Program Memory eae block OFFSET NEXT2Bits L gt Register Register Address Point to Working Pair Register Pair x Jal tesi adress added to p Program Memory offset LSB Selects or Data Memory 8 Bits 16 Bits OPERAND Value used in Sample Instructions LDC R4 04H RR2 The values in the program address RR2 04H are loaded into register R4 LDE R4 04H RR2 Identical operation to LDC example except that external program memory is
194. on Bits 0 0 Input mode with pull up falling edge interrupt INT7 0 1 Input mode falling edge interrupt INT7 1 0 Input mode rising edge interrupt INT7 1 1 Push pull output mode 5 4 P2 6 INT6 Configuration Bits 0 0 Input mode with pull up falling edge interrupt INT6 0 1 Input mode falling edge interrupt INT6 1 0 Input mode rising edge interrupt INT6 1 1 Push pull output mode 3 2 P2 5 INT5 Configuration Bits 0 Input mode with pull up falling edge interrupt INT5 1 Input mode falling edge interrupt INT5 0 Input mode rising edge interrupt INT5 1 Push pull output mode 0 0 1 1 1 0 P2 4 INT4 Configuration Bits 0 0 Input mode with pull up falling edge interrupt INT4 0 1 Input mode falling edge interrupt INT4 1 0 Input mode rising edge interrupt INT4 1 1 Push pull output mode Figure 9 5 Port 2 High Byte Control Register P2CONH 9 8 ELECTRONICS S3C84E5 C84E9 P84E9 VO PORTS Port 2 Control Register Low Byte P2CONL EBH Set1 Bank0 R W Reset value 00 7 6 P2 3 INT3 Configuration Bits 0 0 Input mode with pull up falling edge interrupt INT3 0 1 Input mode falling edge interrupt INT3 1 0 Input mode rising edge interrupt INT3 1 1 Push pull output mode 5 4 P2 2 INT2 Configuration Bits 0 0 Input mode with pull up falling edge interrupt INT2 0 1 Input mode falling edge interrupt INT2 1 0 Input mode
195. only internal memory space is implemented in the S3C84E5 C84E9 P84E the SPL must be initialized to 8 bit value in the range The SPH register is not needed and can be used as a general purpose register if necessary When the SPL register contains the only stack pointer value that is when it points to a system stack in the register file you can use the SPH register as a general purpose data register However if an overflow or underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register during normal stack operations the value in the SPL register will overflow or underflow to the SPH register overwriting any other data that is currently stored there To avoid overwriting data in the SPH register you can initialize the SPL value to FFH instead of OOH ELECTRONICS 2 19 ADDRESS SPACES S3C84E5 C84E9 P84E9 PROGRAMMING TIP Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions LD PUSH PUSH PUSH PUSH POP POP POP POP 2 20 SPL 0FFH PP RP0 RP1 R3 R3 RP1 RP0 PP SPL lt Normally the SPL is set to 0FFH by the initialization routine Stack address lt PP Stack address lt RPO Stack address lt RP1 Stack address OFBH lt R3 R3 lt Stack address OFBH lt Sta
196. ons can be accessed only using the Indirect Register or Indexed addressing modes The selected 16 byte working register block usually consists of two contiguous 8 byte slices As a general programming guideline it is recommended that RPO point to the lower slice and RP1 point to the upper slice see Figure 2 6 In some cases it may be necessary to define working register areas in different non contiguous areas of the register file In Figure 2 7 RPO points to the upper slice and RP1 to the lower slice Because a register pointer can point to either of the two 8 byte slices in the working register block you can flexibly define the working register area to support program requirements PROGRAMMING TIP Setting the Register Pointers SRP 70H RPO lt 70H RP1 lt 78H SRP1 48H RPO lt nochange lt 48H SRPO 0A0H RPO lt lt nochange CLR RPO RPO lt OOH lt nochange LD RP1 0F8H RPO lt nochange lt OF8H Register File Contains 32 8 Byte Slices 8 Byte Slice 16 Byte Contiguous 00001X XxX Working Register 00000XXX 8 Byte Slice Figure 2 6 Contiguous 16 Byte Working Register Block 2 10 ELECTRONICS S3C84E5 C84E9 P84E9 ADDRESS SPACES Register File Contains 32 aie Gs 11110 8 Byte Slices j register block RPO 00000XXX Figure 2 7 Non Contiguous 16 Byte Working Register Block 59 PROGRAMMING TIP Using the RPs to Calc
197. ort input or output mode selected by software input or push pull output Software assignable pull up resistor Alternatively 1 0 1 5 be used as Timer A Timer 1 0 UART Watch Timer Buzzer output Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up Alternately P2 0 P2 7 can be used as inputs for external interrupts INTO INT7 with noise filters and interrupt controller Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up Alternately 0 7 be used as analog inputs for A D converter modules Bit programmable port input or output mode selected by software input or push pull output Software assignable pull up Alternatively P4 0 P4 5 can be used as Timer B inputs for external interrupts INT8 INT 10 with noise filters and interrupt controller ELECTRONICS 9 1 5 S3C84E5 C84E9 P84E9 PORT DATA REGISTERS Table 9 2 gives you an overview of the register locations of all seven S3C84E5 C84E9 P84E9 I O port data registers Data registers for ports 0 1 2 3 and 4 have the general format shown in Table 9 2 Table 9 2 Port Data Register Summary Port 0 data register Set 1 Bank 0 Se Port 2 data register t 1 Bank 0 Port 3 data register Set 1 Bank 0 Port 1 data register Set 1 Bank 0 Port 4 data register 9 2 ELECTRONICS S3C84E5
198. ory Register Next 2 bit Point Pair Example Instruction p to Working ww References either Register Pair Program Memory or 1 of 4 Data Memory 4 bit Working Register Address 16 Bit address LSB Selects Program Memory points to or program Data Memory memory or data memory Value used in OPERAND Instruction Sample Instructions LCD R5 RR6 Program memory access LDE R3 RR14 External data memory access LDE RR4 R8 External data memory access Figure 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 ELECTRONICS S3C84E5 C84E9 P84E9 ADDRESSING MODES INDEXED ADDRESSING MODE X Indexed X addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address see Figure 3 7 You can use Indexed addressing mode to access locations in the internal register file or in external memory Please note however that you cannot access locations COH FFH in set 1 using indexed addressing mode In short offset Indexed addressing mode the 8 bit displacement is treated as a signed integer in the range 128 to 127 This applies to external memory accesses only see Figure 3 8 For register file addressing an 8 bit base address provided by the instruction is added to an 8 bit offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instructi
199. ounter Enable Bit No effect 1 Clear the timer 1 0 counter Auto clear bit Timer 1 0 Match Capture Interrupt Enable Bit Disable interrupt Enable interrupt Timer 1 0 Overflow Interrupt Enable Disable overflow interrupt 1 Enable overflow interrupt 4 3 CONTROL REGISTERS S3C84E5 C84E9 P84E9 T1CON1 rimer 1 1 Control Register E9H Set 1 Bank 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 Timer 1 1 Input Clock Selection Bits 1 1 extemal 711 4 3 1 1 Operating Mode Selection Bits Interval mode ofa Capture mode Capture on rising edge OVF can occur ESES Capture mode Capture on falling edge OVF can occur PWM mode 2 Timer 1 1 Counter Enable Bit No effect 1 Clear the timer 1 1 counter Auto clear bit 4 Timer 1 1 Match Capture Interrupt Enable Bit Disable interrupt 1 Enable interrupt 0 Timer 1 1 Overflow Interrupt Enable Disable overflow interrupt 1 Enable overflow interrupt 4 34 ELECTRONICS S3C84E5 C84E9 P84E9 CONTROL REGISTER TACON Timer A Control Register E1H Set 1 Bank 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode 7 6 ELEGTRONIGS Register addressing mode only Timer A Input Clock Selec
200. ow level for a minimum time interval after the power supply comes within tolerance The minimum required oscillation stabilization time for a reset operation is 1 millisecond Whenever a reset occurs during normal operation that is when both VDD and nRESET are High level the nRESET pin is forced Low and the Reset operation starts All system and peripheral control registers are then Reset to their default hardware values In summary the following sequence of events occurs during a Reset operation Interrupt is disabled The watchdog function basic timer is enabled Ports 0 4 are set to input mode with pull up resistor PO 0 and 0 1 are set to XTin and XTout respectively Peripheral control and data registers are disabled and reset to their default hardware values The program counter is loaded with the program reset address in the ROM 0100H When the programmed oscillation stabilization time interval has elapsed the instruction stored in ROM location 0100H and 0101H is fetched and executed NORMAL MODE RESET OPERATION In normal masked ROM mode the TEST pin is tied to VSS A reset enables access to the 32 Kbyte on chip ROM NOTE To program the duration of the oscillation stabilization interval you make the appropriate settings to the basic timer control register BTCON before entering Stop mode Also if you do not want to use the basic timer watchdog function which causes a system reset if a ba
201. p The target system must have a power ly of i supply of its own SMDS2 or SK 1000 Table 20 2 Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part Comments Connector from External Trigger External Sources of the Triggers Application System om You can connect an external trigger source to one of the two external trigger channels CH1 or CH2 for the SMDS2 breakpoint and trace functions IDLE LED This LED is ON when the evaluation chip S3E84E0 is in idle mode STOP LED This LED is ON when the evaluation chip S3E84E0 is in stop mode PORT P0 0 P0 1 SELECTION SUB OSC OR NORMAL INPUT In the debugging your program by using SMDS2 or SK 1000 you can select the subsystem oscillator 32 768Hz crystal or normal input port 0 0 and 0 1 20 4 ELEGTRONIGS S3C84E5 C84E9 P84E9 DEVELOPMENT TOOLS Table 20 3 The Port 0 0 and Port 0 1 selection setting If you set the Sub OSC to the XTin and XTout side 32 768Hz subsystem crystal will be connected to P0 0 and P0 1 pins and these pins are isolated to the user system If you set the Sub OSC to the P0 0 and P0 1 side 32 768Hz subsystem crystal will be disconnected to P0 0 and P0 1 pins and these pins are connected to the user system through J101 XTout P0 1 XTin P0 0 TBPWM P4 3 4 INT10 P4 2 VDD C VSS XOUT C XIN TEST P4 1 INT9 P4 0 INT8 nRESET 2 0 P2 1 INT1 INT2 P2 2
202. p means one CPU clock period Figure 17 7 Waveform for UART Timing Characteristics 17 10 ELECTRONICS S3C84E5 C84E9 P84E9 ELECTRICAL DATA Table 17 11 A D Converter Electrical Characteristics TA 25 C to 85 G Vpp VLvR to 5 5 V vss 0 V Total accuracy 5 12 V Integral linearity CPU clock 10 MHz error AVggr 5 12 V Differential AVss linearity error one error of bottom Conversion time 10 bit 2 1 50 4 fosc 3 fosc 10 MHz Analog input VIAN voltage Analog input impedance Analog AVREF reference voltage Analog ground AVSS Analog input Vpp 5 current conversion time 20 us Analog block IADC AVper OOO SN 3 V conversion time 20 us AVgge 5V when power down mode NOTES 1 Conversion time is the time required from the moment a conversion operation starts until it ends 2 lapc is operating current during A D conversion 3 is the main oscillator clock ELECTRONICS 17 11 ELECTRICAL DATA S3C84E5 C84E9 P84E9 Table 17 12 LVR Low Voltage Reset Circuit Characteristics TA 25 C Parameter Symbol TestCondition Min Typ Max Unit Main Oscillator Frequency CPU Clock Supply Voltage V Minimum instruction clock 1 4 Oscillator clock Figure 17 8 Operating Voltage Range S3C84E5 C84E9 P84E9 Figure 17 9 The C
203. pending When the sub routine has been serviced the pending condition must be cleared by software by writing a 0 to the interrupt pending bit If interrupts match capture or overflow are enabled the pending bit is cleared automatically by hardware ELECTRONICS 12 3 16 BIT TIMER 1 0 1 S3C84E5 C84E9 P84E9 Timer 1 Control Register T1CON0 E8H Set 1 Bank 1 RW T1CON1 E9H Set 1 Bank 1 RW ue B Timer 1 clock source selection bit Timer 1 overflow interrupt enable bit 000 fxx 1024 001 fxx 256 0 Disable overflow interrupt 010 fxx 64 1 Enable overflow interrrupt 011 fxx 8 100 fxx Timer 1 match capture interrupt enable bit 101 External clock falling edge 0 Disable interrupt 110 External clock rising edge 1 Enable interrrupt 111 Counter stop Timer 1 counter clear bit 0 No effect 1 Clear counter Auto clear bit Timer 1 operating mode selection bit 00 Interval mode 01 Capture mode capture on rising edge OVF can occur 10 Capture mode capture on falling edge OVF can occur 11 PWM mode NOTE Interrupt pending bits are located in TINTPND register Figure 12 1 Timer 1 0 1 Control Register T1CONO 1 ELEGTRONIGS S3C84E5 C84E9 P84E9 16 BIT TIMER 1 0 1 Timer A Timer 1 Pending Register TINTPND EOH Set 1 Bank 1 R W woe Not used must keep always 0 pending bit 0 No interrupt pending 1
204. pins To do this you load the appropriate value to the and P3CONL for ADCO ADC7 register And you write the channel selection data in the A D converter control register ADCON to select one of the eight analog input pins ADCn n 0 7 and set the conversion start or enable bit ADCON O A 10 bit conversion operation can be performed for only one analog input channel at a time The read write ADCON register is located in set 1 bank 0 at address F7H During a normal conversion ADC logic initially sets the successive approximation register to 200H the approximate half way point of an 10 bit register This register is then updated automatically during each conversion step The successive approximation block performs 10 bit conversions for one input channel at a time You can dynamically select different channels by manipulating the channel selection bit value ADCON 6 4 in the ADCON register To start the A D conversion you should set the enable bit ADCON 0 When a conversion is completed ADCON 3 the end of conversion EOC bit is automatically set to 1 and the result is dumped into the ADDATAH ADDATAL registers where it can be read The ADC module enters an idle state Remember to read the contents of ADDATAH and ADDATAL before another conversion starts Otherwise the previous result will be overwritten by the next conversion result NOTE Because the ADC does not use sample and hold circuitry it is important that any fl
205. pt 0 P2 0 External Interrupt INT0 Enable Bit 0 Disable interrupt 1 Enable interrupt Figure 9 8 Port 2 Interrupt Control Register P2INT ELECTRONICS 9 11 PORTS S3C84E5 C84E9 P84E9 PORT 3 Port is 8 bit I O port that can be used for general purpose digital I O The pins are accessed directly by writing or reading the port 3 data register P3 at location in set 1 bank 0 P3 0 P3 7 can serve as inputs outputs push pull or you can configure the following alternative functions General purpose digital I O Alternative function ADCO ADC7 Port Control Register P3CONL Port has two 8 bit control registers for P3 4 P3 7 and PSCONL for P3 0 P3 3 A reset clears the P2CONH and P2CONL registers to configuring all pins to input mode You use control registers settings to select input or output mode push pull and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 3 control registers must also be enabled in the associated peripheral module Port 3 Control Register High Byte EEH Set1 Bank0 R W Reset value 00 7 6 P3 7 ADC7 Configuration Bits 0 0 Input mode with pull up 0 1 Input mode 1 0 Push pull output mode 1 1 Alternative function mode ADC7 input 5 4 P3 6 ADC6 Configuration Bits 0 0 Input mode wit
206. pt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware To enable the timer A match capture interrupt IRQ1 vector COH you must write TACON 1 to 1 To generate the exact time interval you should write TACON 3 and 0 to 1 which cleared counter and interrupt pending bit When interrupt service routine is served the pending condition must be cleared by software by writing a 0 to the interrupt pending bit TINTPND O or TINTPND 1 Timer A Control Register E1H Set 1 Bank 1 R W Reset 00H ell Timer A input clock selection bit Timer A start stop bit 00 fxx 1024 0 Stop timer A 01 fxx 256 1 Start timer 10 fxx 64 11 External clock TACK Timer A match capture interrupt Timer A operating mode selection bit enable bit 00 Interval mode TAOUT mode 0 Disable interrupt 01 Capture mode capture on rising edge 1 Enable interrupt counter running OVF can occur 10 Capture mode capture on falling edge Timer A overflow interrupt enable bit counter running OVF can occur 0 Disable overflow interrupt 11 PWM mode OVF interrupt and match 1 Enable overflow interrrupt interrupt can occur Timer A counter clear bit 0 No effect 1 Clear the timer A counter when write When th counter clear bit 3 is set the 8 bit counter is cleared and it also is cleared automatically Figure 11 1 Timer A Control Register TACON
207. ption starts when the receive interrupt pending bit UARTPND 1 is 0 and the receive enable bit UARTCON 4 is 1 In mode 1 and 2 reception starts whenever an incoming start bit 0 is received and the receive enable bit UARTCON 4 is set to 1 PROGRAMMING PROCEDURE To program the UART modules follow these basic steps 1 Configure P1 4 and P1 5 to alternative function RXD P1 4 TXD P1 5 for UART module by setting the P1CONL register to appropriatly value Load an 8 bit value to the UARTCON control register to properly configure the UART I O module For parity generation and check in UART mode 2 set parity enable bit UARTPND 5 to 1 For interrupt generation set the UART interrupt enable bit UARTCON 1 or UARTCON O to 1 When you transmit data to the UART buffer write transmit data to UDATA the shift operation starts When the shift operation transmit receive is completed UART pending bit UARTPND 1 or UARTPND O is set to 1 and an UART interrupt request is generated ELECTRONICS 13 1 UART UART CONTROL REGISTER UARTCON S3C84E5 C84E9 P84E9 The control register for the UART is called UARTCON at address F6H It has the following control functions Operating mode and baud rate selection Multiprocessor communication and interrupt control Serial receive enable disable control 9th data bit location for transmit and receive operations mode 2 Parity generation and check for transmi
208. pture mode PWM mode Select the timer 1 0 1 input clock frequency Clear the timer 1 0 1 counter T1CNTHO LO T1CNTH1 L1 Enable the timer 1 0 1 overflow interrupt Enable the timer 1 0 1 match capture interrupt T1CONO is located in set 1 and Bank 1 at address E8H and is read write addressable using Register addressing mode T1CON1 is located in set 1 and Bank 1 at address E9H and is read write addressable using Register addressing mode A reset clears T1 CONO T1CON1 to OOH This sets timer 1 0 1 to normal interval timer mode selects an input clock frequency of fxx 1024 and disables all timer 1 0 1 interrupts To disable the counter operation please set T1CON 0 1 7 5 to 111B You can clear the timer 1 0 1 counter at any time during normal operation by writing a 1 to 0 1 3 The timer 1 0 overflow interrupt T1OVFO is interrupt level IRQ2 and has the vector address C6H And the timer 1 1 overflow interrupt T1OVF1 is interrupt level IRQ2 and has the vector address CAH To generate the exact time interval you should write 1 to 0 1 2 and clear appropriate pending bits of the TINTPND register To detect a match capture or overflow interrupt pending condition when T1INTO T1INT1 or TTOVFO T1OVF1 is disabled the application program should poll the pending bit TINTPND register bank 1 address EOH When a 1 is detected a timer 1 0 1 match capture or overflow interrupt is
209. put pins for timer 1 0 Timer 1 0 16 bit PWM mode output or counter match toggle output pins External clock input pins for timer 1 1 Capture input pins for timer 1 1 Timer 1 1 16 bit PWM mode output or counter match toggle output pins System reset pin Pull down resistor connected internally Power input pins Subsystem oscillator pins 1 2 7 8 Main oscillator pins 7 8 13 14 NOTE Pin numbers shown in parentheses are for the 42 pin SDIP package ELECTRONICS 1 7 PRODUCT OVERVIEW PIN CIRCUITS 1 8 Pull Up Resistor Schmitt Trigger Figure 1 4 Pin Circuit Type B nRESET P Channel Data Out Output N Channel Disable Figure 1 5 Pin Circuit Type C S3C84E5 C84E9 P84E9 ELECTRONICS S3C84E5 C84E9 P84E9 PRODUCT OVERVIEW Pull up Enable Data 15 Pin Circuit Output Type C Disable Figure 1 6 Pin Circuit D 0 2 0 7 P1 P4 3 P4 5 Pull up Data Pin Circuit Enable in Circui lO Output Type C Disable Noise Ext INT amp Filter Input Normal Figure 1 7 Pin Circuit Type D 1 P2 and 4 0 4 2 ELECTRONICS 1 9 PRODUCT OVERVIEW S3C84E5 C84E9 P84E9 Pull up Resistor Typical Value 47 In Out Output Disable Figure 1 8 Pin Circuit Type E P3 Output Data o Output Disable Input Mode Digital Input Alternative I O Enable XTin XTout Oscillation circuit Figur
210. r OAAH register 01H 02H and register 02 17H C 0 RLC 00H gt Register OOH 54H C 1 RLC 01H gt Register 01H 02H register 02H 2EH C In the first example if the general register OOH has the value OAAH 10101010 the statement RLC OOH rotates OAAH one bit position to the left The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of the register leaving the value 55H 01010101 The MSB of the register OOH resets the carry flag to 1 and sets the overflow flag ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET RR Rotate Right RR Operation Flags Format Examples dst lt dst 0 dst 7 lt dst 0 dst dst n 1 n 0 6 The contents of the destination operand are rotated right one bit position The initial value of bit zero LSB is moved to bit 7 MSB and also replaces the carry flag C sC Set if the bit rotated from the least significant bit position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination is changed during the rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 0 R E1 IR Given Register 00H 31H register 01 02H and register 02 17H RR 00H gt
211. r by interrupts NOTE Do not use stop mode if you are using an external clock source because XIN input must be restricted internally to VSS to reduce current leakage Using RESET to Release Stop Mode Stop mode is released when the nRESET signal is released and returns to high level all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained A reset operation automatically selects a slow clock 1 16 because CLKCON 3 and CLKCON 4 are cleared to 00B After the programmed oscillation stabilization interval has elapsed the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H and 0101H Using an External Interrupt to Release Stop Mode External interrupts with an RC delay noise filter circuit can be used to release Stop mode Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller s current internal operating mode The external interrupts in the S3C84E5 C84E9 P84E9 interrupt structure that can be used to release Stop mode are External interrupts 2 0 2 7 INTO INT7 and 4 0 4 2 8 10 Please note the following conditions for Stop mode release f you release Stop mode using an external interrupt the current values in system and peripheral control registers are unchanged lf you use an external interrupt for Stop mode release you
212. registers P1CONH for 1 4 1 5 and P1CONL for 1 0 1 3 A reset clears the P1CONH and registers to OOH configuring all pins to input modes You use control registers settings to select input or output mode push pull and enable the alternative functions When programming the port please remember that any alternative peripheral I O function you configure using the port 1 control registers must also be enabled in the associated peripheral module Port 1 Control Register High Byte P1 CONH E8H Set1 R W Reset value 00 7 4 Not used must keep always 0 3 2 P1 5 TXD Configuration Bits 0 0 2 Input mode with pull up 0 1 Input mode 1 0 Push pull output mode 1 1 Alternative function mode TXD output 1 0 P1 4 RXD Configuration Bits 0 0 Input mode with pull up RXD input 0 1 Input mode RXD input 1 0 Push pull output mode 1 1 Alternative function mode RXD output Figure 9 3 Port 1 High Byte Control Register P1CONH ELECTRONICS 9 5 PORTS S3C84E5 C84E9 P84E9 Port 1 Control Register Low Byte P1CONL E9H Set1 Bank0 R W Reset value 00H 7 6 P1 3 BZOUT Configuration Bits 0 0 Input mode with pull up 0 1 Input mode 1 0 Push pull output mode 1 1 Alternative function mode BZOUT output 5 4 P1 2 T1OUTO Configuration Bits 0 0 Input mode with pull up 0 1 Input mode 1 0 Push pull output mode 1 1 Alternative function mode
213. remiss 6 83 Test Complement under Mask a a 6 84 MaSK Lm 6 85 Wate 6 86 Logical Exclusive OR 22 de 6 87 S3C84E5 C84E9 P84E9 MICROCONTROLLER S3C84E5 C84E9 P84E9 PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8 SERIES MICROCONTROLLERS Samsung s S3C8 series of 8 bit single chip CMOS microcontrollers offers a fast and efficient CPU a wide range of integrated peripherals and various mask programmable ROM sizes The major CPU features are Efficient register oriented architecture Selectable CPU clock sources Idle and Stop power down mode released by interrupt or reset Built in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels Each level can have one or more interrupt sources and vectors Fast interrupt processing within a minimum of four CPU clocks can be assigned to specific interrupt levels S3C84E5 C84E9 P84E9 MICROCONTROLLER The S8C84E5 C84E9 P84E9 single chip CMOS microcontrollers are fabricated using the highly advanced CMOS process technology based on Samsung s latest CPU architecture The S3C84E5 is a microcontroller with a 16K byte mask programmable ROM embedded The S3C84E9 is a microcontroller with a 32K byte mask programmable ROM embedded The S3P84E9 is a microcontroller with a 32K byte OTP ROM e
214. rite 0 1 Interrupt request is pending 2 P2 2 PND2 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 1 P2 1 PND1 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 0 P2 0 PNDO Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending ELECTRONICS 4 2 CONTROL REGISTERS S3C84E5 C84E9 P84E9 P3CONH Port 3 Control Register High Byte EEH Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P3 7 ADC7 Input mode with pull up Input mode Push pull output mode Alternative function mode ADC7 input Input mode with pull up Input mode Push pull output mode Alternative function mode ADC6 input Input mode with pull up Input mode Push pull output mode Alternative function mode ADC5 input Input mode Push pull output mode Alternative function mode ADC4 input 4 22 ELECTRONICS S3C84E5 C84E9 P84E9 CONTROL REGISTER P3CONL Port 3 Control Register Low Byte EFH Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P3 3 ADC3 Input mode with pull up Input mode Push pull output mode Alternative function mode ADC3 input
215. rmation SAMA ASSEMBLER The Samsung Arrangeable Microcontroller SAM Assembler SAMA is a universal assembler and generating an object code in the standard hexadecimal format Assembled program codes include the object code used for ROM data and required In circuit emulators program control data To assemble programs SAMA requires a source file and an auxiliary definition device_name def file with device specific information HEX2ROM HEX2ROM file generates a ROM code from a HEX file which is produced by the assembler A ROM code is needed to fabricate a microcontroller which has a mask ROM When generating a ROM code file by HEX2ROM the value FF is automatically filled into the unused ROM area up to the maximum ROM size of the target device ELECTRONICS 20 1 DEVELOPMENT TOOLS S3C84E5 C84E9 P84E9 TARGET BOARDS Target boards are available for all the S3C8 series microcontrollers All the required target system cables and adapters are included on the device specific target board TB84E5 84E9 is a specific target board for the S3C84E5 C84E9 and S3P84E9 development OTP One time programmable microcontrollers OTP for the S3C84E5 C84E9 OTP programmers SPW2plus Single socket programmer GW PRO2 Gang programmer are now available OTP PROGRAMMING SOCKET ADAPTER When you program S3P84E9 OTPs by using ICE or SPW2plus programmers you need OTP socket adapter to mount OTP devices on the programmers In case of 5
216. rrupt acknowledge signal Interrupt logic determines the interrupt s vector address The service routine starts and the source s pending bit is cleared to 0 by hardware or by software The CPU continues polling for interrupt requests INTERRUPT SERVICE ROUTINES Before an interrupt request is serviced the following conditions must be met Interrupt processing must be globally enabled El SYM 0 1 The interrupt level must be enabled IMR register The interrupt level must have the highest priority if more than one level is currently requesting service The interrupt must be enabled at the interrupt s source peripheral control register When all the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle The 1 2 3 4 CPU then initiates interrupt machine cycle that completes the following processing sequence Reset clear to 0 the interrupt enable bit in the SYM register SYM 0 to disable all subsequent interrupts Save the program counter PC and status flags to the system stack Branch to the interrupt vector to fetch the address of the service routine Pass control to the interrupt service routine When the interrupt service routine is completed the CPU issues an Interrupt Return IRET The IRET restores the and status flags setting SYM O to 1 It allows the CPU to process the next interrupt request ELECTRONICS S3C84E5 C84E9 P84E9 INTERRUPT STRUCTURE
217. s S cL Program Memory ROM Register Register Pointer Register Set 1 niece Prime Register Space Working Registers eee deed ette obl e n t t E beh eed een etta c eb Rd iege ER Eu d Using the Register Pointers Register Addressing Common Working Register Area 2 14 4 Bit Working Register Addressing 8 Bit Working Register Addressing System and JSer Stack oie aha ed HORE unay aa Ea 2 19 Chapter 3 Addressing Modes OVGIVIGW ied toe tree gem te I Du Dr NU o m BE Me cd E Mer e ut 3 1 Register Addressing Mode R Indirect Register Addressing Mode IR Indexed Addressing Mode nnn E ernst 3 7 Direct Address Mode DA Indirect Address Mode IA Relative Address Mode RA 1 3 14 S3C84E5 C84E9 P84E9 MICROCONTROLLER Table of Contents Continued Chapter 4 Control Registers UE LM MET 4 1 Chapter 5 Interrupt Structure 5 1 niic el ore 5 2 S3C84E5 C84E9 P84E9 Interrupt 5 3 interrupt Vector Addresses ien cede rece dave day E dee
218. s Opcode Addr Mode Hex dst src 3 12 D2 r Ir Given R1 02H R2 and register 04H R1 R2 SKIP gt R2 04H PC jumps to SKIP location The working register R1 contains the value 02H the working register R2 the source pointer the value 03H and the general register 03 the value 04H The statement CPIJNE R1 R2 SKIP subtracts 04H 00000100B from 02H 00000010B Because the result of the comparison is non equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source pointer register R2 is also incremented by one leaving a value of 04H Remember that the memory location addressed by the CPIJNE instruction must be within the allowed range of 127 to 128 ELECTRONICS S3C84E5 C84E9 P84E9 DA Decimal Adjust DA dst Operation dst lt DA dst addition or subtraction of BCD digits Instruction Carry Bits 4 7 Before DA Value Hex 0 0 9 0 0 8 0 0 9 ADD 0 A F ADC 0 9 F 0 A F 1 0 2 1 0 2 1 0 3 0 0 9 SUB 0 0 8 SBC 1 7 1 6 Flags Z Set if result is 0 cleared otherwise V Undefined D Unaffected H Unaffected Format INSTRUCTION SET The destination operand is adjusted to form two 4 bit BCD digits following an addition or subtraction operation For addition ADD ADC or subtraction SUB SBC the following table indicates the operation performed The operation is undefined if the destinatio
219. s a positive number MSB 0 1 Operation generates a negative number MSB 1 4 Overflow Flag V Operation result is lt 127 or gt 128 1 Operation result is gt 127 or lt 128 3 Decimal Adjust Flag D A dd operation completed 1 Subtraction operation completed 2 Half Carry Flag H No carry out of bit 3 or no underflow into bit 3 by addition or subtraction 1 Addition generated carry out of bit 3 or subtraction generated underflow into bit 3 4 Fast Interrupt Status Flag FIS Interrupt return IRET in progress when read Fast interrupt service routine in progress when read 0 Bank Address Selection Flag BA Bank 0 is selected je 1 Bank 1 is selected 4 8 ELECTRONICS S3C84E5 C84E9 P84E9 CONTROL REGISTER IMR Interrupt Mask Register DDH Set 1 Reset Value x x x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only T Interrupt Level 7 IRQ7 Enable Bit Disable mask Je Enable un mask 6 Inte rupt Level 6 IRQ6 Enable Bit Disable mask 1 Enable un mask 5 Inte rupt Level 5 IRQ5 Enable Bit Disable mask 1 Enable un mask 4 Inte rupt Level 4 IRQ4 Enable Bit Disable mask Je Enable un mask Inte Level 3 Enable Bit Disable mask 1 Enable un mask 2 Inte rupt Level 2 IRQ2 Enable Bit Disable mask 1 Enable un mask
220. s not include current drawn through internal pull up resistors or external output current loads RESET Oscillation occurs Stabilzation 4 311 StopMode 4 lt Data Retention Mode gt Executionof STOPInstrction nRESET NOTE twait isthe same as4096 x 16 x 1 fosc Figure 17 4 Stop Mode Release Timing Initiated by RESET Oscillation Stabilization Time lt Stop Mode Idle Mode lt Data Retention Mode A Normal Execution of Operating Mode STOP Instruction Interrupt 0 2 VDD lt gt NOTE is the same as 4096 x 16 x BT clock Figure 17 5 Stop Mode Main Release Timing Initiated by Interrupts 17 8 ELECTRONICS S3C84E5 C84E9 P84E9 31 Stop Execution of STOP Instruction Interrupt Data Retention Mode Oscillation Stabilization Time NOTE When the case of select the fxx 128 for basic timer input clock before enter the stop mode tWAIT 128 x 16 x 1 32768 62 5 ms ELECTRICAL DATA Idle Mode Normal Operating Mode Figure 17 6 Stop Mode Sub Release Timing Initiated by Interrupts ELECTRONICS ELECTRICAL DATA S3C84E5 C84E9 P84E9 Table 17 10 UART Timing Characteristics in Mode 0 10 MHz Serial port clock High Low level width NOTES 1 Alltimings are in nanoseconds ns and assume a 10 MHz CPU clock frequency 2 The unit tc
221. s usually has priority over one with a higher vector address The priorities within a given level are fixed in hardware a 3 2 a L EA __ Lje L B 5 6 ELECTRONICS S3C84E5 C84E9 P84E9 INTERRUPT STRUCTURE ENABLE DISABLE INTERRUPT INSTRUCTIONS El Dl Executing the Enable Interrupts El instruction globally enables the interrupt structure All interrupts are then serviced as they occur according to the established priorities NOTE The system initialization routine executed after a reset must always contain an El instruction to globally enable the interrupt structure During the normal operation you can execute the DI Disable Interrupt instruction at any time to globally disable interrupt processing The El and DI instructions change the value of bit 0 in the SYM register SYSTEM LEVEL INTERRUPT CONTROL REGISTERS In addition to the control registers for specific interrupt sources four system level registers control interrupt processing The interrupt mask register IMR enables un masks or disables masks interrupt levels The interrupt priority register IPR controls the relative priorities of interrupt levels The interrupt request register IRQ contains interrupt pending flags for each interrupt level as opposed to each interrupt source system mode register SYM enables or disables global interrupt processing SYM settings also enable fast interrupts and con
222. sed to read write the data of 64 Kbyte data memory ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET LDCPI LDEPI Load Memory with Pre Increment LDCPI LDEPI Operation Flags Format Examples NOTE dst src dst src m rr 1 dst src These instructions are used for block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair and is first incremented The contents of the source location are loaded into the destination location The contents of the source are unaffected LDCPI refers to program memory and LDEPI refers to external data memory The assembler makes Irr an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 2 14 F3 r Given RO 7FH R6 21H and R7 OFFH LDCPI RR6 RO RR6 bRR6 1 the contents of RO is loaded into program memory location 2200H 21FFH 1H RO 7FH R6 22H R7 00H LDEPI RR6 RO RR6 bRR6 1 the contents of RO is loaded into external data memory location 2200H 21FFH 1H RO 7FH R6 22H R7 00H LDEPI instruction can be used to read write the data of 64 Kbyte data memory ELECTRONICS 6 57 INSTRUCTION SET S3C84E5 C84E9 P84E9 LDW Load word LDW Operation Flags Format Examples 6 58 dst src dst sr
223. see Chapter 3 Addressing Modes The prime register area on page 0 is immediately addressable following a reset In order to address prime registers on pages 0 or 1 you must set the register page pointer PP to the appropriate source and destination values 1 Bank 1 CPU system control General purpose Peripheral and I O Figure 2 4 Set 1 Set 2 Prime Area Register 2 8 ELECTRONICS S3C84E5 C84E9 P84E9 ADDRESS SPACES WORKING REGISTERS Instructions can access specific 8 bit registers or 16 bit register pairs using either 4 bit or 8 bit address fields When 4 bit working register addressing is used the 256 byte register file can be seen by the programmer as one that consists of 32 8 byte register groups or slices Each slice comprises of eight 8 bit registers Using the two 8 bit register pointers RP1 and RPO two working register slices be selected at any one time to form a 16 byte working register block Using the register pointers you can move this 16 byte register block anywhere in the addressable register file except for the set 2 area The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces working register slice is 8 bytes eight 8 bit working registers RO R7 or R8 R15 One working register block is 16 bytes sixteen 8 bit working registers R0 R15 All the registers in an 8 byte worki
224. sic timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of BTCON ELECTRONICS 8 1 RESET and POWER DOWN S3C84E5 C84E9 P84E9 HARDWARE RESET VALUES Table 8 1 8 2 and 8 3 list the reset values for CPU and system registers peripheral control registers and peripheral data registers following a reset operation The following notation is used to represent reset values 1 a 0 shows the reset bit value as logic one or logic zero respectively means that the bit value is undefined after a reset Adash means that the bit is either not used or not mapped but read 0 is the bit value Table 8 1 S3C84E5 C84E9 P84E9 Set 1 Register Values After RESET rex s Timer contoivegiter ava Basc imer convoi regster ero 24 m o o clock conreegiter ou o o o o o o oto system fags register Fus eo osa x x x lt me ew Joio olo lol een mr es ow o o ma s system x Register page poner 8 2 ELECTRONICS S3C84E5 C84E9 P84E9 RESET and POWER DOWN Table 8 2 S3C84E5 C84E9 P84E9 Set 1 Bank 0 Register Values After RESET oe nsn Boe
225. sing modes Register R Indirect Register IR Indexed X Direct DA Relative RA Immediate IM and Indirect IA For detailed descriptions of these addressing modes please refer to Chapter 3 Addressing Modes ELECTRONICS 6 1 INSTRUCTION SET S3C84E5 C84E9 P84E9 Table 6 1 Instruction Group Summary Mnemonic Operands Instruction Load Instructions CLR dst Clear LD dst src Load LDB dst src Load bit LDE dst src Load external data memory LDC dst src Load program memory LDED dst src Load external data memory and decrement LDCD dst src Load program memory and decrement LDEI dst src Load external data memory and increment LDCI dst src Load program memory and increment LDEPD dst src Load external data memory with pre decrement LDCPD dst src Load program memory with pre decrement LDEPI dst src Load external data memory with pre increment LDCPI dst src Load program memory with pre increment LDW dst src Load word POP dst Pop from stack POPUD dst src Pop user stack decrementing POPUI dst src Pop user stack incrementing PUSH src Push to stack PUSHUD dst src Push user stack decrementing PUSHUI dst src Push user stack incrementing NOTE LDE LDED LDEI LDEPP and LDEPI instructions can be used to read write the data from the 64 Kbyte data memory 6 2 ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Arithmetic Instructio
226. ssing 3 2 3 3 Indirect Register Addressing to Register File a 3 3 3 4 Indirect Register Addressing to Program Memory 3 4 3 5 Indirect Working Register Addressing to Register File 3 5 3 6 Indirect Working Register Addressing to Program Data 3 6 3 7 Indexed Addressing to Register File _ a 3 7 3 8 Indexed Addressing to Program or Data Memory with Short Offset 3 8 3 9 Indexed Addressing to Program or Data 3 9 3 10 Direct Addressing for Load Instructions 3 10 3 11 Direct Addressing for Call and Jump Instructions 3 11 3 12 Indirect Addressing vaya a 3 12 3 13 Relative Addressing u oen desee decere aes 3 13 3 14 Immediate Addressing 5 yu elisa ces hatin REOR c UH Ree ees 3 14 4 1 Register Description Format ene mener 4 4 S3C84E5 C84E9 P84E9 MICROCONTROLLER xi List of Figures continued Figure Title Page Number Number 5 1 S3C8 Series Interrupt 5 2 5 2 S3C84E5 C84E9 P84E9 Interrupt Structure 5 4 5 3 ROM Vector Address Afa na uu u s 5 5
227. ster Page Pointer PP DFH Set 1 R W ws 7 s 5 TS T2 T4 es Destination register page selection bits Source register page selection bits 0000 Destination Page 0 0000 Source Page 0 0001 Destination Page 1 0001 Source Page 1 NOTE A hardware reset operation writes the 4 bit destination and source values shown above to the register page pointer These values should be modified to other pages Figure 2 3 Register Page Pointer PP ELECTRONICS 2 5 ADDRESS SPACES S3C84E5 C84E9 P84E9 PROGRAMMING TIP Using the Page Pointer for RAM clear Page 0 Page 1 LD SRP LD RAMCLO CLR DJNZ CLR LD LD RAMCL1 CLR DJNZ CLR 2 6 PP 00H 0C0H RO 0FFH RO RO RAMCLO RO 0H R0 0FFH R0 RO RAMCL1 RO Destination 0 Source 0 Page 0 RAM clear starts RO 00H Destination 1 Source 0 Page 1 RAM clear starts RO 00H ELECTRONICS S3C84E5 C84E9 P84E9 ADDRESS SPACES REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file locations COH FFH The upper 32 byte area of this 64 byte space EOH FFH is expanded two 32 byte register banks bank 0 and bank 1 The set register bank instructions SB0 or SB1 are used to address one bank or the other A hardware reset operation always selects bank 0 addressing The upper two 32 byte areas bank 0 and bank 1 of set 1 EOH FFH contains 64 mapped system and peripheral control registers Th
228. stination operand instead of a numeric relative address value In the example the working register R1 contains the value 02H and LOOP is the label for a relative address The statement DJNZ R1 LOOP decrements the register R1 by one leaving the value 01H Because the contents of R1 after the decrement are non zero the jump is taken to the relative address specified by the LOOP label ELECTRONICS 6 39 INSTRUCTION SET S3C84E5 C84E9 P84E9 E Enable Interrupts El Operation Flags Format Example 6 40 SYM 0 1 The El instruction sets bit zero of the system mode register SYM 0 to 1 This allows interrupts to be serviced as they occur assuming they have the highest priority If an interrupt s pending bit was set while interrupt processing was disabled by executing a DI instruction it will be serviced when the El instruction is executed No flags are affected Bytes Cycles Opcode Hex 1 4 Given SYM OOH El If the SYM register contains the value OOH that is if interrupts are currently disabled the statement El sets the SYM register to 01H enabling all interrupts SYM 0 is the enable bit for global interrupt processing ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET ENTER Enter ENTER Operation Flags Format Example Address IP PC Enter PC SP lt 5 2 SP lt IP IP PC PC lt IP lt IP 2 This instruction is useful when
229. struction is the value supplied in the operand field itself The operand may be one byte or one word in length depending on the instruction used Immediate addressing mode is useful for loading constant values into registers Program Memory OPERAND OPCODE The Operand value is in the instruction Sample Instruction LD RO0O 0AAH Figure 3 14 Immediate Addressing ELECTRONICS S3C84E5 C84E9 P84E9 CONTROL REGISTER CONTROL REGISTERS OVERVIEW Control register descriptions are arranged in alphabetical order according to register mnemonic More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part II of this manual The locations and read write characteristics of all mapped registers in the S3C84E5 C84E9 P84E9 register file are listed in Table 4 1 The hardware Reset value for each mapped register is described in Chapter 8 RESET and Power Down Table 4 1 Set 1 Registers Register name Mnemonic F a Seok on stack poner s Instruction poner igh sy nstucton pomer ow Byte enna me m ww a 2 ow AW eisterpage porter PP nw ELECTRONICS 4 1 CONTROL REGISTERS S3C84E5 C84E9 P84E9 Table 4 2 Set 1 Bank 0 Registers Port 0 data register Port 1 data register 2 ms
230. t INT6 Enable Bit Disable interrupt Enable interrupt je 5 2 5 External Interrupt 5 Enable Bit Disable interrupt Enable interrupt ae 4 P2 4 External Interrupt INT4 Enable Bit Disable interrupt Enable interrupt je 3 P2 3 External Interrupt INT3 Enable Bit Disable interrupt Enable interrupt je 2 P2 2 External Interrupt INT2 Enable Disable interrupt 1 Enable interrupt 1 P2 1 External Interrupt INT1 Enable Bit Disable interrupt 1 Enable interrupt 0 P2 0 External Interrupt INT0 Enable Bit Disable interrupt Enable interrupt S3C84E5 C84E9 P84E9 CONTROL REGISTER P2INTPND Port 2 Interrupt Pending Register EDH Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P2 7 PND7 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 6 P2 6 PND6 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 5 P2 5 PND5 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 4 P2 4 PND4 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 3 P2 3 PND3 Interrupt Pending Bit Interrupt request is not pending pending bit clear when w
231. t Subsystem oscillator control bit 0 Strong driving ability 0 Subsystem oscillator RUN 1 Normal driving ability 1 Subsystem oscillator STOP Mainsystem oscillator control bit 0 Mainsystem oscillator RUN 1 Mainsystem oscillator STOP In strong mode the warm up time is less than 100 ms When the CPU is operated with fxt sub oscillation clock it is possible to use the stop instruction but in this case before using stop instruction you must select fxx 128 for basic timer counter clock input Then the oscillation stabilization time is 62 5 1 32768 x 128 x 16 ms 100 ms Here the warm up time is from the time that the stop release signal activates to the time that basic timer starts counting Figure 7 5 Oscillator Control Register OSCCON STOP Control Register STPCON E5H Set 1 Bank 0 R W STOP Control bits Other values Disable STOP instruction 10100101 Enable STOP instruction Figure 7 6 STOP Control Register STPCON ELECTRONICS S3C84E5 C84E9 P84E9 RESET and POWER DOWN RESET and POWER DOWN SYSTEM RESET OVERVIEW During a power on Reset the voltage at VDD goes to High level and the nRESET pin is forced to Low level The nRESET signal is input through a Schmitt trigger circuit where it is then synchronized with the CPU clock This procedure brings S3C84E5 C84E9 P84E9 into a known operating status To allow time for internal CPU clock oscillation to stabilize the nRESET pin must be held to L
232. t When the CPU has acknowledged the transmit interrupt pending condition the UARTPND 0 flag must be cleared by software in the interrupt service routine UART Pending Register UARTPND Set1 Bank 0 R W Reset Value 00H wool rene 2 me se Not used Not used UART transmit interrupt pending flag must keep always 0 must keep 0 Not pending always 0 0 Clear pending bit when write UART parity enable disable 1 Interrupt pending 0 Disable L Enable UART receive parity error UART receive interrupt pending flag 0 No error 0 Not pending 1 Parity error 0 Clear pending bit when write 1 Interrupt pending NOTES In order to clear a data transmit or receive interrupt pendingflag you must write a to the appropriate pending bit 0 has no effect To avoid errors we recommend using load instruction except for LDB when manipulating UARTPND values Parity enable and parity error check can be available 9 bit UART mode Mode 2 only Parity error bit RPE will be refreshed whenever 8th receive data bit has been shifted Figure 13 2 UART Interrupt Pending Register UARTPND 13 4 ELECTRONICS S3C84E5 C84E9 P84E9 UART In mode 2 9 bit UART data by setting the parity enable bit PEN of UARTPND register to 1 the 9 data bit of transmit data will be an automatically generated parity bit Also the 9 data bit of the received data will be treated as a parity b
233. t 4 of the basic timer counter overflows When a BTCNT 4 overflow occurs normal CPU operation resumes ELECTRONICS 10 3 BASIC TIMER S3C84E5 C84E9 P84E9 RESET or STOP Basic Timer Control Register y Write 1010xxxxB to disable Data Bus 4096 Clear 8 Bit Up Counter BTCNT Read Only fxx 128 R NOTE During a power on reset operation the CPU is idle during the required oscillation stabilization interval until bit 4 of the basic timer counter overflows Start the CPU note Figure 10 2 Basic Timer Block Diagram ELEGTRONIGS S3C84E5 C84E9 P84E9 8 BIT TIMER A B 8 BIT TIMER A B 8 BIT TIMER A OVERVIEW The 8 bit timer is an 8 bit general purpose timer counter Timer A has three operating modes you can select of them using the appropriate TACON setting Interval timer mode Toggle output at TAOUT Capture input mode with a rising or falling edge trigger at the TACAP pin PWM mode TAPWM Timer A has the following functional components Clock frequency divider fxx divided by 1024 256 or 64 with multiplexer External clock input pin TACK 8 bit counter TACNT 8 bit comparator and 8 bit reference data register TADATA O pins for capture input TACAP PWM or match output TAOUT Timer A overflow interrupt IRQ1 vector C2H and match capture interrupt IRQ1 vector COH generation Timer A control register TACON set 1 bank1 E
234. t and receive operations mode 2 UART transmit and receive interrupt control A reset clears the UARTCON value to OOH So if you want to use UART module you must write appropriate value to UARTCON ELEGTRONIGS S3C84E5 C84E9 P84E9 UART UART Control Register UARTCON F6H Set1 Bank 0 R W Reset Value 00H vo ve wee s Operating mode and Transmit interrupt enable bit baud rate selection bits 0 Disable see table below 1 Enable Multiprocessor communication 1 Received interrupt enable bit enable bit mode 2 only 0 Disable 0 Disable 1 Enable 1 Enable If parity disable mode PEN 0 Serial data receive enable bit location of the 9th data bit that was received in 0 Disable UART mode 2 0 or 1 1 Enable If parity enable mode PEN 1 If parity disable mode REN 0 Even odd parity selection bit for receive data in location of the 9th data bit to be transmitted in UART mode 2 UART moge 2 UO 0 Even parity check for the received data If parity enable mode PEN 1 1 Odd parity check for the received data Even odd parity selection bit for transmit data in UART mode 2 0 Even parity bit generation for transmit data 1 Odd parity bit generation for transmit data 2 MS1 MSO Mode Description Baud Rate 0 Shift register fxx 16 x 16bit BRDATA 1 1 8 bit UART fxx 16 x 16bit BRDATA 1 2 9 bit UART 16 16bit BRDATA 1 NOTES
235. t if arithmetic overflow occurred cleared otherwise D H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 90 R 91 IR Given Register 00H OAAH register 01H 02H and register 02H 17H RL 00H gt Register OOH 55H C 1 RL 01H gt Register 01H 02H register 02 2bEH C 0 In the first example if the general register OOH contains the value OAAH 10101010B the statement RL OOH rotates the OAAH value left one bit position leaving the new value 55H 01010101B and setting the carry C and the overflow V flags ELECTRONICS 6 71 INSTRUCTION SET S3C84E5 C84E9 P84E9 RLC Rotate Lett through Carry RLC Operation Flags Format Examples 6 72 dst dst 0 C lt dst 7 dst n 1 lt dst 0 6 The contents of the destination operand with the carry flag are rotated left one bit position The initial value of bit 7 replaces the carry flag C and the initial value of the carry flag replaces bit zero 7 0 F ee C Set if the bit rotated from the most significant bit position bit 7 was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination is changed during the rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 10 R 11 IR Given Registe
236. t mode falling edge interrupt INT6 Input mode rising edge interrupt INT6 Push pull output mode Input mode with pull up falling edge interrupt INT5 Input mode falling edge interrupt INT5 0 Input mode with pull up falling edge interrupt INT4 Input mode falling edge interrupt INT4 Push pull output mode 4 18 ELECTRONICS S3C84E5 C84E9 P84E9 CONTROL REGISTER P2CONL Port 2 Control Register Low Byte EBH Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P2 3 INT3 Input mode with pull up falling edge interrupt INT3 Input mode falling edge interrupt INT3 Input mode with pull up falling edge interrupt INT2 Input mode falling edge interrupt INT2 Input mode rising edge interrupt INT2 Push pull output mode Input mode with pull up falling edge interrupt INT1 Input mode falling edge interrupt INT1 lo Input mode with pull up falling edge interrupt INTO Input mode falling edge interrupt INTO Push pull output mode ELECTRONICS 4 19 CONTROL REGISTERS S3C84E5 C84E9 P84E9 P2INT Port 2 Interrupt Control Register ECH Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 2 7 External Interrupt INT7 Enable Disable interrupt 1 Enable interrupt 6 P2 6 External Interrup
237. t of the destination No other bits of the destination are affected The source is unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Cleared to 0 Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 07 Rb r0 NOTE Inthe second byte of the 3 byte instruction format the destination or the source address is four bits the bit address b is three bits and the LSB address value is one bit Given R1 07H register 01H 03H BOR R1 01H 1 gt R1 07H register 01H BOR 01H 2 R1 gt Register 01H 07H R1 07H In the first example the destination working register R1 contains the value 07H 00000111B and the source register 01H the value 03H 00000011B The statement BOR R1 01H 1 logically ORs bit one of the register 01H source with bit zero of R1 destination This leaves the same value 07H in the working register R1 In the second example the destination register 01H contains the value 03H 00000011B and the source working register R1 the value 07H 00000111B The statement BOR 01H 2 R1 logically ORs bit two of the register 01H destination with bit zero of R1 source This leaves the value 07H in the register 01H ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET BTJRF sit Test Jump Relative on False BTJRF Operation Flags Format Example dst src b If src b is a 0 then PC P
238. t sends out an address byte to identify the target slave Note that in this case an address byte differs from a data byte In an address byte the 9th bit is 1 and in a data byte it is 0 The address byte interrupts all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave then clears its MCE bit and prepares to receive incoming data bytes bits of slaves that were not addressed remain set and they continue operating normally while ignoring the incoming data bytes While the MCE bit setting has no effect in mode 0 it can be used in mode 1 to check the validity of the stop bit For mode 1 reception if MCE is 1 the receive interrupt will be issue unless a valid stop bit is received ELECTRONICS 13 13 UART S3C84E5 C84E9 P84E9 Setup Procedure for Multiprocessor Communications Follow these steps to configure multiprocessor communications 1 Set all S8C84E5 C84E9 P84E9 devices masters and slaves to UART mode 2 with parity disable Write the MCE bit of all the slave devices to 1 The master device s transmission protocol is First byte the address identifying the target slave device 9th bit 1 Next bytes data 9th bit 0 When the target slave receives the first byte all of the slaves are interrupted because the 9th data bit is 1 The targeted slave compares the address byte to its own address and then clears its MCE bit in order
239. t system any standard computer that employs Win95 98 2000 as its operating system can be used A sophisticated debugging tool is provided both in hardware and software the powerful in circuit emulator SMDS2 or SK 1000 for the S3C7 S3C9 and S3C8 microcontroller families SMDS2 is a newly improved version of SMDS2 and SK 1000 is supported by a third party tool vendor Samsung also offers supporting software that includes debugger an assembler and a program for setting options SHINE Samsung Host Interface for In Circuit Emulator SHINE is a multi window based debugger for SMDS2 SHINE provides pull down and pop up menus mouse support function hot keys and context sensitive hyper linked help It has an advanced multiple windowed user interface that emphasizes ease of use Each window can be easily sized moved scrolled highlighted added or removed SASM The SASM is a re locatable assembler for Samsung s S3C8 series microcontrollers The SASM takes a source file containing assembly language statements and translates them into a corresponding source code an object code and comments The SASM supports macros and conditional assembly It runs on the MS DOS operating system As it produces the re locatable object codes only the user should link object files Object files can be linked with other object files and loaded into memory SASM requires a source file and an auxiliary register file device_name reg with device specific info
240. ted as unsigned integers Flags C Set if the result is gt 255 cleared otherwise Z Setif the result is 0 cleared otherwise S Set if MSB of the result is a 1 cleared otherwise V Cleared D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 22 84 RR R 22 85 RR IR 22 86 RR IM Examples Given Register 00H 20H register 01H 03H register 02H 09H register 03H 06H MULT 00H 02H gt Register OOH 01H register 01H 20H register 02H 09H MULT 00H 01H gt Register 00H 00H register 01H OCOH MULT 00H 30H gt Register 00H 06H register 01H OOH In the first example the statement MULT 00H 02H multiplies the 8 bit destination operand in the register OOH of the register pair 01H by the source register 02H operand 09H The 16 bit product 0120H is stored in the register pair OOH 01H ELECTRONICS 6 59 INSTRUCTION SET S3C84E5 C84E9 P84E9 NEXT Next NEXT Operation Flags Format Example Address 1P PC 0120 44 6 60 PC IP IP IP 2 The NEXT instruction is useful when implementing threaded code languages The program memory word that is pointed to by the instruction pointer is loaded into the program counter The instruction pointer is then incremented by two No flags are affected Bytes Cycles Opcode Hex opc 1 10 OF The following diagram shows an example of how to use the NEXT instructi
241. terrupt P4 0 external interrupt Oo P4CONL F1H bank 0 P4 1 external interrupt PAINT F2H bank 0 P4 2 external interrupt PAINTPND F3H bank 0 UART receive transmit IRQ7 UARTCON F6H bank 0 NOTE If a interrupt is un mask Enable interrupt level in the IMR register the pending bit and enable bit of the interrupt should be written after a DI instruction is executed ELECTRONICS 5 9 INTERRUPT STRUCTURE S3C84E5 C84E9 P84E9 SYSTEM MODE REGISTER SYM The system mode register SYM set 1 DEH is used to globally enable and disable interrupt processing see Figure 5 5 A reset clears SYM 0 to 0 The instructions El and DI enable and disable global interrupt processing respectively by modifying the bit 0 value of the SYM register In order to enable interrupt processing an Enable Interrupt El instruction must be included in the initialization routine which follows a reset operation Although you can manipulate 5 0 directly to enable and disable interrupts during the normal operation it is recommended to use the El and DI instructions for this purpose System Mode Register SYM DEH Set 1 R W Not used for the S3C84E5 C84E9 Global interrupt enable bit P84E9 0 Disable all interrupts processing 1 Enable all interrupts processing Fast interrupt level selection bits Fast interrupt enable bit 0 Disable fast interrupts processing IRQO 1 Enable fast interrupts processing IRQ1 IRQ2 IRQ4 I
242. th pull up 0 1 Input mode 1 0 Push pull output mode 1 1 Alternative function mode T1OUT1 output Figure 9 1 Port 0 High Byte Control Register POCONH ELECTRONICS 9 3 PORTS S3C84E5 C84E9 P84E9 Port 0 Control Register Low Byte POCONL E7H Seti R W Reset value 0FH 7 6 PO 3 T1CK1 Configuration Bits 0 0 Input mode with pull up T1CK1 input 0 1 Input mode T1CK1 input 1 X Push pull output mode 5 4 PO 2 T1CAP1 Configuration Bits 0 0 Input mode with pull up T1CAP1 input 0 1 Input mode T1CAP1 input 1 X Push pull output mode 3 2 1 Configuration Bits 0 0 2 Input mode with pull up 0 1 2 Input mode 1 0 Push pull output mode 1 1 Alternative function mode Sub oscillator output XTout 1 0 PO 0 XTin Configuration Bits 0 0 Input mode with pull up 0 1 Input mode 1 0 Push pull output mode 1 1 Alternative function mode Sub oscillator input XTin Figure 9 2 Port 0 Low Byte Control Register POCONL 9 4 ELECTRONICS S3C84E5 C84E9 P84E9 VO PORTS PORT1 Port 1 is a 6 bit I O port with individually configurable pins that can use two ways General purpose digital I O Alternative function TAOUT 10070 1 0 BZOUT TXD RXD Port 1 is accessed directly by writing or reading the port 1 data register P1 at location E1H in set 1 bank 0 Port 1 Control Register P1CONH P1CONL Port 1 has two 6 bit control
243. tination address is four bits the bit address 0 is three bits and the LSB address value is one bit in length Given R1 O7H BITR R1 1 R1 05H If the value of the working register R1 is 07H 00000111B the statement BITR R1 1 clears bit one of the destination register R1 leaving the value 05H 00000101B ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET BITS Bit Set BITS Operation Flags Format Example dst b dst b 1 The BITS instruction sets the specified bit within the destination without affecting any other bit in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 O7H BITS R1 3 gt OFH If the working register R1 contains the value 07H 00000111B the statement BITS R1 3 sets bit three of the destination register R1 to 1 leaving the value OFH 00001111B ELECTRONICS 6 21 INSTRUCTION SET S3C84E5 C84E9 P84E9 BOR Bit or BOR BOR Operation Flags Format Examples dst src b dst b src dst 0 lt dst 0 OR src b or dst b lt dst b OR src 0 The specified bit of the source or the destination is logically ORed with bit zero LSB of the destination or the source The resulting bit value is stored in the specified bi
244. tion Bits Operating Mode Selection o 0 Interval mode TAOUT mode fo 1 Capture mode capture on rising edge counter running OVF can occur oo Capture mode capture on falling edge counter running OVF can occur PWM mode OVF interrupt can occur Timer A Counter Clear Bit No effect 1 Clear the timer A counter Auto clear bit Timer A Overflow Interrupt Enable Bit Disable overflow interrupt 1 Enable overflow interrupt Timer A Match Capture Interrupt Enable Bit Disable interrupt 1 Enable interrupt Timer A Start Stop Bit Stop timer A 1 Start timer A 4 3 CONTROL REGISTERS S3C84E5 C84E9 P84E9 TBCON Timer B Control Register DOH Set 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Timer Input Clock Selection Bits 5 4 Interrupt Time Selection Bits ofo Elapsed time for low data value ofa Elapsed time for high data value alo Elapsed time for low and high data values Not Used 3 Timer B Interrupt Enable Bit Disable interrupt 1 Enable interrupt 2 Timer B Start Stop Bit Stop timer B 1 Start timer B Selection One shot mode 1 Repeating mode 0 Output flip flop Control T FF is low T FF is high EB NOTE is selecte
245. to be all zeros Program Memory Next Instruction LSB Must be Zero dst Current Instruction gt OPCODE Lower Address Byte Program Memory Upper Address Byte Locations 0 255 Sample Instruction CALL 40H The 16 bit value in program memory addresses 40H and 41H is the subroutine start address Figure 3 12 Indirect Addressing 3 12 ELECTRONK S S3C84E5 C84E9 P84E9 RELATIVE ADDRESS MODE RA ADDRESSING MODES In Relative Address RA mode a twos complement signed displacement between 128 and 127 is specified the instruction The displacement value is then added to the current PC value The result is the address of the next instruction to be executed Before this addition occurs the PC contains the address of the instruction immediately following the current instruction Several program control instructions use the Relative Address mode to perform conditional jumps The instructions that support RA addressing BTJRF BTJRT DJNZ CPIJE CPIJNE and JR Program Memory Next OPCODE Displacement Current Instruction OPCODE Sample Instructions Program Memory Address Used Current PC Value Signed Displacement Value JR ULT OFFSET Where OFFSET is a value in the range 127 to 128 Figure 3 13 Relative Addressing ELECTRONICS 3 13 ADDRESSING MODES IMMEDIATE MODE IM S3C84E5 C84E9 P84E9 In Immediate IM addressing mode the operand value used in the in
246. to receive incoming data The other slaves continue operating normally Full Duplex Multi S3C84E5 C84E9 P84E9 Interconnect RxD RxD TxD RxD RxD Master Slave 1 Slave 2 Slave n S3C84E5 S3C84E5 S3C84E5 S3C84E5 C84E9 C84E9 C84E9 C84E9 P84E9 P84E9 P84E9 P84E9 Figure 13 9 Connection Example for Multiprocessor Serial Data Communications 13 14 ELECTRONICS S3C84E5 C84E9 P84E9 WATCH TIMER WATCH TIMER OVERVIEW Watch timer functions include real time and watch time measurement and interval timing for the system clock To start watch timer operation set bit1 and bit 6 of the watch timer mode register WTCON 1and 6 to 1 After the watch timer starts and elapses a time the watch timer interrupt is automatically set to 1 and interrupt requests commence in 1 955 ms or 0 125 0 25 and 0 5 second intervals The watch timer can generate a steady 0 5 kHz 1 kHz 2 kHz or 4 kHz signal to the BUZZER output BZOUT pin By setting WTCON 3 and WTCON 2 to 11b the watch timer will function in high speed mode generating an interrupt every 1 955 ms High speed mode is useful for timing events for program debugging sequences Real time and Watch time measurement Using a main system or subsystem clock source Buzzer output frequency generator Timing tests in high speed mode ELEGTRONIGS 14 1 WATCH TIMER S3C84E5 C84E9 P84E9 WATCH TIMER CONTROL REGISTER WTCON R W me v v 9 9
247. trol the activity of external interface if implemented Table 5 2 Interrupt Control Register Overview Control Register i RW Function Description Interrupt mask register IMR R W _ Bit settings in the IMR register enable or disable interrupt processing for each of the eight interrupt levels IRQ0 IRQ7 Interrupt priority register R W Controls the relative processing priorities of the interrupt levels The seven levels of S3C84E5 C84E9 P84E9 are organized into three groups A B and C Group A is IRQO and IRQ1 group B is IRQ2 IRQ3 and IRQ4 and group C is IRQ5 IRQ6 and IRQ7 Interrupt request register This register contains a request pending bit for each interrupt level System mode register SYM R W This register enables disables fast interrupt processing dynamic global interrupt processing ELECTRONICS 5 7 INTERRUPT STRUCTURE S3C84E5 C84E9 P84E9 INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways globally or by specific interrupt level and source The system level control points in the interrupt structure are Global interrupt enable and disable by El and DI instructions or by direct manipulation of SYM 0 Interrupt level enable disable settings IMR register Interrupt level priority settings IPR register Interrupt source enable disable settings in the corresponding peripheral control registers NOTE When writing an application program th
248. uctuations in the analog level at the ADCO ADCT7 input pins during a conversion procedure be kept to an absolute minimum change in the input level perhaps due to circuit noise will invalidate the result ELECTRONICS 15 1 A D CONVERTER S3C84E5 C84E9 P84E9 A D CONVERTER CONTROL REGISTER ADCON A D converter control register ADCON is located in set1 bank 0 at address F7H ADCON is read write addressable using 8 bit instructions only But the EOC bit ADCON 3 is read only ADCON has four functions Bits 6 4 select an analog input pin ADCO ADC7 Bit 3 indicates the end of conversion status of the A D conversion Bits 2 1 select a conversion speed Bit 0 starts the A D conversion Only one analog input channel can be selected at a time You can dynamically select any one of the eight analog input pins ADCO ADC7 by manipulating the 3 bit value for ADCON 6 ADCON 4 A D Converter Control Register ADCON F7H Set 1 Bank 0 R W ADCON 3 bit is read only Not used Start or Enable bit must keep always 0 0 Disable Operation 1 Start Operation A D Input Pin Selection bits A D Input pin Clock Selection bit Conversion Clock fxx 16 fxx 8 fxx 4 End of Conversion bit only 0 Conversion not complete 1 Conversion complete Figure 15 1 A D Converter Control Register ADCON 15 2 ELECTRONICS S3C84E5 C84E9 P84E9 A D CONVERTER Conversion Data Register High Byte ADD
249. ues are not identical the zero flag bit Z is cleared in the FLAGS register OD5H ELECTRONICS S3C84E5 C84E9 P84E9 INSTRUCTION SET BITC Bit Complement BITC Operation Flags Format Example dst b dst b NOT dst b This instruction complements the specified bit within the destination without affecting any other bit in the destination C Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected Bytes Cycles Opcode Addr Mode Hex dst NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITC R1 1 R1 05H If the working register R1 contains the value 07H 00000111B the statement BITC R1 1 complements bit one of the destination and leaves the value 05H 00000101B in the register R1 Because the result of the complement is not the zero flag Z in the FLAGS register OD5H is cleared ELECTRONICS 6 19 INSTRUCTION SET S3C84E5 C84E9 P84E9 BITR Bit Reset BITR Operation Flags Format Example dst b dst b 0 The BITR instruction clears the specified bit within the destination without affecting any other bit in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst NOTE Inthe second byte of the instruction format the des
250. ulate the Sum of a Series of Registers Calculate the sum of registers 80H 85H using the register pointer The register addresses from 80H through 85H contain the values 10H 11H 12H 13H 14H and 15 H respectively SRP0 80H RPO lt 80H ADD RO R1 RO lt RO ADC RO R2 RO lt RO R2 C ADC RO R3 RO lt RO ADC RO R4 RO lt RO R4 C ADC RO R5 RO lt RO R5 C The sum of these six registers 6FH is located in the register RO 80H The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles If the register pointer is not used to calculate the sum of these registers the following instruction sequence would have to be used ADD 80H 81H 80H lt 80H 81H ADC 80H 82H 80H lt 80H 82H C ADC 80H 83H 80H lt 80H 83H C ADC 80H 84H 80H lt 84H C ADC 80H 85H 80H lt 80H 85H C Now the sum of the six registers is also located in register 80H However this instruction string takes 15 bytes of instruction code rather than 12 bytes and its execution time is 50 cycles rather than 36 cycles ELECTRONICS 2 11 ADDRESS SPACES S3C84E5 C84E9 P84E9 REGISTER ADDRESSING The S3C8 series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time With Register R addressing mode in which the operand v
251. ur bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H 00000111B and register 01H 03H 00000011B BXOR R1 01H 1 gt R1 06H register 01H 03H BXOR 01H 2 R1 gt Register 01H 07H R1 07H In the first example the destination working register R1 has the value 07H 00000111B and the source register 01H has the value 03H 00000011B The statement BXOR R1 01H 1 exclusive ORs bit one of the register 01H the source with bit zero of R1 the destination The result bit value is stored in bit zero of R1 changing its value from 07H to 06H The value of the source register 01H is unaffected ELECTRONICS 6 25 INSTRUCTION SET S3C84E5 C84E9 P84E9 CALL Call Procedure CALL Operation Flags Format Examples dst SP lt SP 1 SP lt PCL SP lt SP 1 SP lt PCH PC lt ast The contents of the program counter are pushed onto the top of the stack The program counter value used is the address of the first instruction following the CALL instruction The specified destination address is then loaded into the program counter and points to the first instruction of a procedure At the end of the procedure the return instruction RET can be used to return to the original program flow RET pops the top of the stack back into the program counter No flags are affected Bytes Cycles Opcode Addr Mode Hex dst dst 3 14 F6 DA opc dst 2 12 F4 IRR

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