Home

Describing Synthesizable RTL in SystemC™

Contents

1. Fk SC_METHOD comb_logic X finds a singular run of zeros and counts them kd void count_zeros_seq comb_logic set_defaults if read read if seenTrailing amp amp data read 0 new_is_legal false new_zeros 0 new_data_ready true else if seenZero amp amp data read 1 new_seenTrailing true else if data read 0 new_seenZero true new_zeros zeros_s read 1 if bits_seen read MAX_BIT_READ new_data_ready true else new_bits_seen bits_seen read 1 SC_METHOD seq_logic All registers have asynchronous resets Si void count_zeros_seq seq_logic if reset zeros_s 0 bits_seen 0 seenZero false seenTrailing false is_legal_s true data_ready_s false else zeros_S new_zeros bits_seen new_bits_seen sS nZero new_s nZero seenTrailing new_seenTrailing is_legal_s new_is_legal Creating SystemC Modules for RTL Synthesis Creating a Module With Multiple SC_METHOD Processes 2 24 data_ready_s new_data_ready SC_METHOD assign_outputs Zero time assignments of signals to their associated outputs ay void count_zeros_seq assign_outputs zeros zeros_s is_legal is_legal_s data_ready data_ready_s k method set_defaults sets the default values of the new_ signals for the comb_logic A process ay void count_z
2. SC_MODULE d_latch6a sc_in lt bool gt in_data set reset RTL Coding Guidelines Register Inference 4 25 sc_in lt bool gt clock sc_out lt bool gt out_q void d_latch_fen infer_latch if reset read 0 out_q write 0 else if set read 0 out_q write 1 else if clock read out_gq write in_data read Constructor SC_CTOR d_latch6a SC_METHOD d_latch_fcn sensitive lt lt in_data lt lt clock lt lt set lt lt reset Figure 4 17 Latch With Active Low Set and Reset in_data set outg reset elac Active High Set and Reset To instruct RTL synthesis to implement all signals in the group as active high add a check to the SystemC code to ensure that the group of signals has only one active high signal at a given time RTL synthesis does not produce any logic to check this assertion RTL Coding Guidelines Register Inference 4 26 Example 4 18 shows a latch with the set and reset specified as active high Figure 4 18 shows the resulting schematic Example 4 18 Latch With Active High Set and Reset include systemc h SC_MODULE d_latch7a sc_in lt bool gt in_data set reset sc_in lt bool gt clock sc_out lt bool gt out oO void d Latch Cen infer_latch if reset read out_q write 0 else if set read out_q write 1 Jelse if clock read out_q write in_data read
3. Constructor SC_CTOR d_latch7a SC_METHOD d_latch_fcn sensitive lt lt in_data lt lt clock lt lt set lt lt reset Figure 4 18 Latch With Active High Set and Reset in_data outq set reset clock RTL Coding Guidelines Register Inference 4 27 D Latch With an Asynchronous Set and Reset Example 4 19 is a SystemC description for a D latch with an active low asynchronous set and reset Figure 4 19 shows the inferred latch Example 4 19 Latch With Asynchronous Set and Reset include systemc h SC_MODULE d_latch6 sc_in lt bool gt in data set reset sc_in lt bool gt clock sc_out lt bool gt out oO void d Latch Cen if reset read 0 out_q write 0 else if set read 0 out_q write 1 Jelse if clock read out_q write in_data read ff Constructor SC_CTOR d_latch6 SC_METHOD d_latch_fcn sensitive lt lt in_data lt lt clock lt lt set lt lt reset Figure 4 19 Latch With Asynchronous Set and Reset in_data set outq reset elac RTL Coding Guidelines Register Inference 4 28 D Latch With an Asynchronous Set Example 4 20 is a SystemC description for a D latch with an asynchronous set Figure 4 20 shows the inferred latch Example 4 20 Latch With Asynchronous Set include systemc h SC_MODULE d_latch4 sc_in lt bool gt in_data set sc_in lt bool gt clock sc_out
4. default value if in_sela read out_l write in_a read Jelse if in_selb read out_l write in_b read Constructor SC_CTOR tristate_ex2 SC_METHOD tristate_fcn sensitive lt lt in_sela lt lt in_selb lt lt in_a lt lt in_b RTL Coding Guidelines Three State Inference 4 32 Figure 4 23 Three State Driver With Gated Data in_selb In_sela In_b outi n_a Three State Driver for Bus To infer a three state driver to resolve bus contention use a port of type sc_out_rv as shown in Example 4 24 Figure 4 24 shows the resulting schematic Example 4 24 Three State Driver for Bus Thr state buffer inferenc with resolved logic output include systemc h SC_MODULE tristate_ex3 sc_in lt bool gt in_sela in_selb sc_in lt sc_logic gt in_a in_b sc_out_rv lt 1 gt out_1 Method for first thr state driver void tristate_a Method for second thr state driver void tristate_b Constructor SC_CTOR tristate_ex3 SC_METHOD tristate_a sensitive lt lt in_sela lt lt in_a SC_METHOD tristate_b sensitive lt lt in_selb lt lt in_b i void tristate_ex3 tristate_a if in_sela read out_l write in_a read RTL Coding Guidelines Three State Inference 4 33 else out_l write 2 void tristate_ex3 tristate_b if in_selb read out_l write in_b rea
5. Behavioral Modeling and Synthesis RTL and Behavioral Coding Style Examples 5 12 Example 5 1 RTL Coding fifo_rtl h header file define BUFSIZE 4 define LOGBUFSIZI define LOGBUFSIZEP 1 El ON T USONE Kal LA SC_MODULE circ_buf Same I O as behavioral sc_in lt bool gt clk sc_in lt bool gt read_fifo sc_in lt bool gt write_fifo sc_in lt int gt data_in sc_in lt bool gt reset sc_out lt int gt data_out sc_out lt bool gt full sc_out lt bool gt empty Internal signals sc_signal lt int gt buf0 Dutt next sc_signal lt int gt bufl bufl_next sc_signal lt int gt buf2 buf2_next sc_signal lt int gt buf3 buf3_next sc_signal lt sc_uint lt LOGBUFSIZEPLUSONE gt gt num_in_buf num_in_buf_next sc_signal lt bool gt full_next empty_next sc_signal lt int gt data_out_next Declare processes void ns_logic Next state logic void update_regs Update all registers void gen_full Generate a full signal void gen_empty Generate an empty signal Constructor SC_CTOR circ_buf SC_METHOD ns_logic sensitive lt lt read_fifo lt lt write_fifo lt lt data_in lt lt num_in_buf SC_METHOD update_regs sensitive_pos lt lt clk SC_METHOD gen_full sensitive lt lt num_in_buf_next Behavioral Modeling and Synthesis RTL and Behavioral Coding Style Examples 5 13 SC_METHOD gen_em
6. buf2_next data_in read num_in_buf_next num_in_buf read 1 break case 3 buf3_next data_in read num_in_buf_next num_in_buf read 1 default ignore the write command break Behavioral Modeling and Synthesis RTL and Behavioral Coding Style Examples 5 15 Behavioral Coding Style The general characteristics of the behavioral coding style for synthesis are the following e The behavior is described like an algorithm a software program and functions can be used to manage complexity e Although the initial model may have float or integer data types you need to change these types to synthesizable SystemC types e You specify the I O protocol of the design by defining in which clock cycle the I O happens Note that only the I O not the operations described in the algorithm is bound to clock cycles e Ituses the synthesizable subset of the SystemC language Example 5 2 is a behavioral description of a FIFO Example 5 2 FIFO Behavioral Coding fifo_bhv h header file define BUFSIZE 4 define LOGBUFSIZE 2 define LOGBUFSIZEPLUSONE 3 SC_MODULE circ_buf sc_in_clk clk The clock sc_in lt bool gt read_fifo Indicate read from FIFO sc_in lt bool gt write_fifo Indicate write to FIFO sc_in lt int gt data_in Data written to FIFO sc_in lt bool gt reset Reset the FIFO sc_out lt int gt data_out Data read from the FIFO sc_out lt bool gt full In
7. output_data_ready sc_out lt int gt result sc_signal lt unsigned gt state_out fir_fsm fir_fsml fir_data fir_datal SC_CTOR fir_rtl fir_fsml new fir_fsm FirFSM fir_fsml gt clock clk fir_fsml gt reset reset Creating SystemC Modules for RTL Synthesis Creating a Hierarchical RTL Module 2 29 fir _fsml gt in_valid in_valid fir_fsml gt state_out state_out fir_datal 1 gt state_out state_out 1 gt sample sample 1 gt clock clk 1 gt result result 1 gt output_data_ready output_data_ready fir_data fir_data fir_data fir_data fir_data new fir _data FirData Example 2 14 FIR FSM Module Creating SystemC Modules for RTL Synthesis Creating a Hierarchical RTL Module 2 30 ZE EY fem A file SC_MODULE fir_fsm sc_in lt bool gt sc_in lt bool gt sc_in lt bool gt clock reset in_ valid sc_out lt unsigned gt state_out defining the states of the ste machine enum reset_s first_s second_s third_s wait_s state SC_CTOR fir_fsm SC_METHOI D entry sensitive_pos clock void entry 1 D fRFeA ELL Zem opp File include lt systemc h gt include fir fam bi output_s void fir_fsm entry sc_uint lt 3 gt state_tmp reset behavior if reset read true state reset_s main state machine switch
8. state case reset_s state wait_s state_tmp 0 state_out write state_tmp break case first_s state second_s state_tmp 1 state_out write state_tmp break case second_s state third_s state_tmp 2 state_out write state_tmp break case third_s state output_s state_tmp 3 state_out write state_tmp break case output_s state wait_s state_tmp 4 state_out write state_tmp break default if in_valid read true state first_s hi state_tmp 5 state_out write state_tmp Creating SystemC Modules for RTL Synthesis Creating a Hierarchical RTL Module 2 31 break Example 2 15 FIR Data Module fReKPE IY Catach Liler dese SC_MODU sc_in sc_in SC Ou SC Ou SC nm sc_in sc_in sc_in SC_CTOR fir_data SC_METHOI LE fir_data lt unsigned gt lt int gt t lt int gt t lt bool gt lt bool gt t lt 19 gt acc t lt 8 gt shift t lt 9 gt coefs state_out sample result output_data_ready clock Lol L6 D entry sensitive_pos clock void entry JeeRe EL Y datavcpp filex include lt systemc h gt include Wear data h void fir_data entry include Weir const rel sh sc_int lt 8 gt sample_tmp sc_uint lt 3 gt sta
9. R T Les zs 1 gt Do wait gt i FSM Behavioral Modeling and Synthesis What is Behavioral Synthesis 5 8 Choosing the Right Abstraction for Synthesis You can implement a hardware module by using RTL synthesis or behavioral level synthesis Evaluate each design module by module and consider each modules attributes described in the following sections to determine whether RTL or behavioral synthesis is applicable Identifying Attributes Suitable for RTL Synthesis Look for the following design attributes when identifying a hardware module that is suitable for RTL synthesis e Itis easier to conceive the design as an FSM and a data path than as an algorithm for example a microprocessor e The design is very high performance and the designer therefore needs complete control over the architecture e The design contains complex memory such as SDRAM or RAMBUS e The design is asynchronous Behavioral Modeling and Synthesis Choosing the Right Abstraction for Synthesis 5 9 Identifying Attributes Suitable for Behavioral Synthesis Look for the following design attributes when identifying a hardware module that is suitable for behavioral synthesis e It is easier to conceive the design as an algorithm than as an FSM and a data path for example a fast Fourier transform filter inverse quantization or digital signal processor e The design has a c
10. SC_MODULE jkffl sc_in lt bool gt j k sc_inout lt bool gt q inout to read q for toggle sc_in lt bool gt c Method for k clock port D flip flop void jk_flop Constructor RTL Coding Guidelines Register Inference 4 10 SC_CTOR jkff1 SC_METHOD jk_flop sensitive_pos lt lt clk void jkff 1 jk_flop sc_uint lt 2 gt temp temp to create vector temp 1 j read temp 0 k read switch temp case 0x1 q write 0 write a zero break case 0x2 qg write 1 write al break case 0x3 toggle qg write q read break default break no change Figure 4 6 JK Flip Flop cl RTL Coding Guidelines Register Inference 4 11 JK Flip Flop With Asynchronous Set and Reset Example 4 7 is a SystemC description for a JK flip flop with an active low asynchronous set and reset To specify an asynchronous set or reset specify the signal in the sensit Example 4 7 Figure 4 7 shows the i ivity list as shown in nferred flip flop Example 4 7 JK Flip Flop With Asynchronous Set and Reset Rising edge triggered JKFF include systemc h SC_MODULE jkff2 sc_in lt bool gt j k set reset sc_inout lt bool gt q inout to read q for toggle sc_in lt bool gt clk clock port Method for D flip flop void jk_flop Constructor SC_CTOR jk 2 SC_METHOD jk
11. SystemC SystemC is the foundation for design tools and methodologies that address the above mentioned system level design challenges of tool interoperability team Communication and component model creation and distribution SystemC is based on C the most popular language with system designers and software engineers The SystemC classes add the necessary constructs to C for modeling systems and hardware at various levels of abstraction from the abstract untimed models to cycle accurate RTL models The software content of the system can be written in C without the need for additional constructs SystemC by itself solves only a few of the system level design challenges You can use SystemC for creating an executable specification to verify the system functionality and architecture but analysis and architecture design tools are needed and IP vendors need to provide SystemC models The power of SystemC is that it can be used as a common language by system designers software engineers and hardware designers SystemC allows exchange of IP models creation of an interoperable tool infrastructure and development of a concept to implementation design methodology The same benefits derived from the standardization of Verilog and VHDL in RTL design can now be achieved in the system design space with SystemC SystemC RTL Synthesis Overview SystemC 1 4 Why Synthesis From SystemC Hardware design has the well established Verilog
12. SystemC code to detect this condition during simulation RTL synthesis does not support these checks RTL Coding Guidelines Register Inference 4 17 Table 4 2 Truth Table for the SR Latch NAND Type set reset Q 0 0 Not stable 0 1 1 1 0 0 1 1 Q Example 4 11 SR Latch SR_LATCH latch include systemc h SC_MODULE sr_latch sc_in lt bool gt RESET SET sc_out lt bool gt Q void sr_latch_fen synopsys async_set_reset SET RESET if RESET read 0 Q write 0 else if SET read 0 O write 1 SC_CTOR sr_latch SC_METHOD sr_latch_fcn sensitive lt lt RESET lt lt SET RTL Coding Guidelines Register Inference 4 18 Figure 4 1 1 SR Latch Avoiding Latch Inference To avoid latch inference assign a value to a signal for all cases in a conditional statement Example 4 13 shows addition of an else clause to avoid the latch inferred by the if statement in Example 4 10 and Figure 4 12 shows the resulting schematic Example 4 12 Adding an Else Clause to Avoid Latch Inference include systemc h SC_MODULE d_latchla IL sc_in lt bool gt An data sc_in lt bool gt clock sc_out lt bool gt out_q Method process void d_latch_fcn if clock read out_q write in_data read else out_q write false Constructor SC_CTOR d_latchla SC_METHOD d_latch_fcn sensitive lt lt in data lt l
13. e What is Behavioral Synthesis e Choosing the Right Abstraction for Synthesis e RTL and Behavioral Coding Style Examples e Getting More Information About Behavioral Synthesis 5 1 Comparing RTL and Behavioral Modeling An RTL model describes registers in your design and the combinational logic between the registers You specify the functionality of your system as an finite state machine FSM and a data path Because register updates are tied to a clock the model is cycle accurate both at the interfaces and internally Internal cycle accuracy means you specify the clock cycle in which each operation is performed A behavioral model is a higher level algorithmic description You describe your design functionality when inputs are read the operations performed on the input data and when the results are written to the outputs You do not specify a finite state machine FSM for controlling your design or the clock cycle when each operation or I O is executed behavioral synthesis decides these based on constraints you provide for the design Your behavioral description is independent from the technology and implementation architecture For behavioral synthesis you can change the target technology library or constrain the implementation architecture without modifying the behavioral description This allows you to quickly explore various architectures for your design Behavioral descriptions are smaller make it easier to capture compl
14. engineers can achieve greater productivity by modifying a SystemC executable specification Design teams can fully deploy the productivity of system level design by using a SystemC synthesis tool that supports both behavioral and RTL styles This designer productivity improvement can reduce time to market About This Manual As with VHDL and Verilog SystemC has modeling rules and a synthesizable subset of those rules This manual describes the modeling rules and synthesizable subset for describing RTL in SystemC and it introduces you to behavioral modeling and synthesis SystemC RTL Synthesis Overview About This Manual 1 7 SystemC RTL Synthesis Overview About This Manual 1 8 2 Creating SystemC Modules for RTL Synthesis This chapter explains the SystemC and C C language elements that are important for RTL synthesis It contains the following sections Defining Modules and Processes Creating a Module Creating a Module With a Single SC_METHOD Process Creating a Module With Multiple SC_METHOD Processes Creating a Hierarchical RTL Module 2 1 Defining Modules and Processes This modeling guide explains how to develop SystemC RTL modules for synthesis It assumes that you are knowledgeable about the C C language and the SystemC Class Library available from the Open SystemC Community Web site at http www systemc org Modules The basic building block in SystemC is the module A SystemC module is a container in whic
15. output logic and the next state logic are separate in this diagram you can merge them into one logic block where gates can be shared for a smaller design area The output logic is always a function of the current state state vector and optionally a function of the inputs If inputs are included in the output logic it is a Mealy state machine If inputs are not included it is a Moore state machine The next state logic is always a function of the current state state vector and optionally a function of the inputs The common implementations of state machines are e An GC METHOD process for updating the state vector and a single common SC_METHOD process for computing both the output and next state logic RTL Coding Guidelines State Machines 4 38 s An SC METHOD process for updating the state vector an SC_METHOD process for the computing the output logic anda separate SC_METHOD process for computing the next state logic e A Moore machine with a single process for computing and updating the next state vector and outputs Figure 4 28 shows a state diagram that represents an example state machine where a and b represent the outputs Figure 4 28 Finite State Machine State Diagram input a i input2 0 input2 RTL Coding Guidelines State Machines 4 39 State Machine With a Common Computation Process Example 4 27 shows the state machine represented in Figure 4 28 with acommon SC_METHOD process for computing th
16. platform dependent widths which are often not the correct width for efficient hardware For example you might need only a 6 bit integer for a particular operation instead of the native C 32 bit integer In addition C does not support four valued logic vectors operations such as concatenation and other features that are needed to efficiently describe hardware operations SystemC provides a set of limited precision and arbitrary precision data types that allows you to create integers bit vectors and logic vectors of any length SystemC also supports all common operations on these data types Using the Synthesizable Subset Modifying Data for Synthesis 3 7 To modify a SystemC model for RTL synthesis you need to evaluate all variable declarations formal parameters and return types of all functions to determine the appropriate data type and the appropriate widths of each data type Selecting the data widths is a design decision and it is typically a tradeoff between the cost of hardware and the required precision This decision is therefore left to you Synthesizable Data Types C is a strongly typed language Every constant port signal variable function return type and parameter is declared as a data type such as bool or sc_int lt n gt and can hold or return a value of that type Therefore it is important that you use the correct data types in expressions Nonsynthesizable Data Types All SystemC and C data t
17. practice to describe a module by using a separate header file module_name h and an implementation file module_name cpp or module_name cc Module Header File Each module header file contains e Port declarations e Internal signal variable declarations e Internal data variable declarations e Process declarations e Member function declarations e Module constructor Creating SystemC Modules for RTL Synthesis Creating a Module 2 5 Module Syntax Declare a module using the syntax shown in bold in the following example include systemc h SC_MODULE module_name Module port declarations Signal variable declarations Data variable declarations Member function declarations Method process declarations Module constructor SC_CTOR module_name Register processes Declare sensitivity list GC _ MODULE and SC_CTOR are C macros defined in the SystemC Class library Module Ports Each module has any number of input outputs and inout ports see Figure 2 2 which determine the direction of data into or out of the module Creating SystemC Modules for RTL Synthesis Creating a Module 2 6 Figure 2 2 Module Ports Module Ports A port is a data member of SC_MODULE You can declare any number of sc_in sc_out and sc_inout ports To read from an output port declare it as an sc_inout rather than an sc_out port Port Syntax Declare ports by using the syntax sh
18. sc_uint lt 4 gt count_zeros_comb zeros sc_uint lt 8 gt x int count 0 for int i 0 i lt 7 i if x il 0 count return count Creating SystemC Modules for RTL Synthesis Creating a Module With a Single SC_METHOD Process 2 21 Creating a Module With Multiple SC_METHOD Processes Example 2 11 on page 2 23 shows a sequential description of the same count zeros circuit described in Creating a Module With a Single SC_METHOD Process on page 2 20 In this sequential version there are three SC_METHOD processes and several signals for communication between the processes as shown in Figure 2 7 The comb_logic and output_assign processes are level sensitive and the seq_logic process is sensitive to the positive edge of the clk and reset inputs The set_defaults member function is called at the beginning of the comb_logic process This example does not show typical simulation specific code that you might include for debugging purposes Figure 2 7 Count Zeros Sequential Module count_zeros data Panik read gt logic Signal output ignals gt assign is_legal_s gt zeros gt data_ready __ gt is_legal on i reset Se scentralling clk logic Signals seenZero data ready_ bits seen is _legal_s zeros s new_zeros new_data_ready new_is_legal new_seenZero new_seenTrailing new_bits_seen Creating SystemC Mo
19. use the sensitive sensitive_pos or sensitive_neg functions or the sensitive sensitive_pos or sensitive_neg streams in the sensitivity declaration list Defining a Level Sensitive Process For combinational logic define a sensitivity list that includes all input ports inout ports and signals used as inputs to the process Use the sensitive method to define the level sensitive inputs Example 2 2 shows in bold a stream type declaration and a function type declaration Specify any number of sensitive inputs for the stream type declaration and specify only one sensitive input for the function type declaration You can call the sensitive function multiple times with different inputs Example 2 2 Defining a Level Sensitive Sensitivity List SC_MODULE my_module Ports sc_in lt int gt a sc_in lt bool gt b sc_out lt int gt x sc_out lt int gt y Internal signals sc_signal sc_signal sc_signal lt in l lt in l lt bool gt c t gt di t gt e process declaration void my_meth module constructor SC_CTOR my_m od_proc odule register process SC_METHOD my_method_proc declare level sensitive sensitivity list sensitive lt lt a lt lt c lt lt d Stream declaration Creating SystemC Modules for RTL Synthesis Creating a Module 2 12 sensitive b Function declaration sensitive e Function declaration Incomple
20. 10101 Tr i 2 SO 0100 0011111010101011 1100 0010101011111001 0010 1101010111010101 Output 1010 0000000011010101 0110 0111111110010111 Clk Enable Timing Behavioral Modeling and Synthesis What is Behavioral Synthesis 5 4 During timing behavioral synthesis decides which component from the synthetic library it can use to implement each operation in your behavioral description and the delay through each component Behavioral synthesis uses the basic components the wire load models and the operating conditions from the ASIC or FPGA vendor technology library to compute the timing Behavioral synthesis uses the timing estimates during scheduling and allocation to synthesize the most efficient implementation for your design Scheduling During scheduling behavioral synthesis decides in which clock cycle each I O and operation will occur during execution Scheduling is illustrated in Figure 5 2 Figure 5 2 Scheduling Into a Specific Clock Cycle Behavioral code wait_until start delayed true A portl read port2 read B port3 read port4 read C A B if C lt 0 VO Arithmetic operations porti port2 Schedule port3 port4 Scheduled operations Cycle Operation 1 read inputs Em O 4 a Behavioral Modeling and Synthesis What is Behavioral Synthesis 5 5 Behavioral synthesis objectives during scheduling are to Satisfy the data f
21. CoCentric SystemC Compiler SystemC RTL Synthesis Overview This chapter describes how RTL synthesis from SystemC fits into the system level design flow It contains the following sections e System Level Design e System Level Design Challenges e SystemC e Why Synthesis From SystemC System Level Design System level design involves specifying the system verifying its functionality and determining optimum system architecture by evaluating design alternatives Today s complex systems have significant software content and are integrated into a system on a chip SoC System level design can help with the growing complexity of both the hardware and software An effective system level design strategy minimizes late design iterations and increases design team productivity which enables you to deliver a high quality product on time System Level Design Challenges Developing an effective system level design strategy presents several challenges that can be solved by using SystemC Component Integration Component reuse is a widely implemented strategy for handling complexity but many of the components are provided from various sources Because component models are written in different languages and styles integrating the models into the system design is often so difficult the system designers avoid doing it eliminating the important task of specification and functional verification SystemC RTL Synthesis Overview System
22. Describing Synthesizable RTL in SystemC Version 1 2 November 2002 Trademarks and Copyright Synopsys and CoCentric are a registered trademarks of Synopsys Inc with further information at http synopsys com SystemC is a trademark of Synopsys Inc All other product or company names may be trademarks of their respective owners Copyright 2001 2002 Synopsys Inc Printed in the U S A Describing Synthesizable RTL in SystemC v1 2 Contents About TAIS GUAE ee ns ra doce de eel EINE SESS ee De X SystemC Training EE xi Information About Synopsys SystemC Synthesis Products xii 1 SystemC RTL Synthesis Overview System Level Design nnana E AEN de edd 1 2 System Level Design Challenges 1 2 Component Integration EE 1 2 Beie e UE 1 3 Design Team Collaboration 20000 eee eee 1 3 E eae at Ge ante eh anette CM Aude eee here 1 4 Why Synthesis From Gwvstemt eee ee 1 5 Interpretation Errors er 4s24 4 4 281 ned he eee ey ees 1 5 Verification ROUSE 22e cc ons 2 2120 0 erregt 1 6 Increased Productivity dase dee eke eee EE 1 6 About This Manual 225 e anne et a 1 7 2 Creating SystemC Modules for RTL Synthesis Defining Modules and Processes 0000 ee eeees 2 2 lee UE 2 2 eler 2 3 Registering a Process 2 3 Triggering Execution of a Process aaaa nonae 2 4 Reading and Writing Processes 222222222 2 4 Types of Processes seele ee 2 4 Creating a
23. Hierarchical RTL Module 2 26 sc_out lt bool gt OUTPUT_DATA_ READY sc_out lt int gt RESULT sc_signal lt unsigned gt state_out Communication between two peer modules Create data members pointers to instantiated modules fir Cem fir_fsml fir data fir_datal SC_CTOR fir_top Create new instance of fir_fsm module fir_fsml new fir_fsm FirFSM Binding by name fir_fsml gt clock CLK fir_fsml gt reset RESET fir _fsml gt in_valid IN_VALID fir_fsml gt state_out state_out Binding by position alternative fir_fsml CLK RESET IN_VALID state_out Create new instance of fir_data module and bind by name fir_datal new fir_data FirData fir_datal gt reset RESET fir_datal gt state_out state_out fir_datal gt sample SAMPLE fir_datal gt result RESULT fir_datal gt output_data_ready OUTPUT_DATA READY fir_datal gt clk CLK F fir_fsm h SC_MODULE fir_fsm sc_in lt bool gt clock sc_in lt bool gt reset sc_in lt bool gt in_valid Creating SystemC Modules for RTL Synthesis Creating a Hierarchical RTL Module 2 27 sc_out lt unsigned gt state_out fRrerti data h SC_MODULE fir_data sc_in lt bool gt clk sc_in lt bool gt reset sc_in lt unsigned gt state_out sc_in lt int gt sample sc_out lt int gt result sc_out lt bool gt output_data_ready Hierarchical RTL Module Exam
24. Level Design 1 2 Tool Interoperability Although system modeling tools are available each tool uses a proprietary model format which makes a model developed for one tool unsuitable for use with another tool This lack of tool interoperability and model compatibility also prevents using more than one tool in a design flow Design Team Collaboration During system architecture design designers choose the processor s bus and peripherals and decide what to implement in hardware and software Effective architecture design requires participation of the hardware and software design teams for creating models and influencing architectural decisions which is called hardware software co design Furthermore as the hardware and software design teams participate in architecture design concurrently communication and consensus is reached early in the design cycle The results of this collaboration must be validated and corrections can be made early in the design cycle This prevents surprises when the hardware and software are integrated much later in the design cycle To further complicate the situation the system designers hardware designers and software engineers often apply different design languages A common design language is needed to increase understanding communication and productivity and to bring these teams together during the system architecture design phase SystemC RTL Synthesis Overview System Level Design Challenges 1 3
25. Module asaan EEN 2 5 Module Header Flle u tiber 2 5 Module Syntax Hauer Bereit 2 6 Mod le SEN 2 6 Port SYNTAX area 2 7 Port Data Ke EE 2 8 SODASS EE ee cee N 2 8 elt EE 2 9 Signal Data TREIE bk ME rb ek ii 2 9 Data Member Variables 000 seen 2 10 Creating a Process ina Module 2 11 Defining the Sensitivity si 2 12 Defining a Level Sensitive Process 2 12 Incomplete Sensitivity sis 2 13 Defining an Edge Sensitive Process 2 13 Limitations for Sensitivity iers 2 14 Member Functions ocecescectuceeevige este ee 2 15 Module G nstr cierss ser sce ake enna reese el 2 15 Implementing the Module 2 15 Reading and Writing Ports and Signals 2 16 Reading and Writing Bits of Ports and Signals 2 16 Signal and Port Assignments 00000 eee eee 2 17 Variable Assignment 222 00 seen nennen 2 18 Creating a Module With a Single SC_METHOD Process 2 20 Creating a Module With Multiple SC_METHOD Processes 2 22 Creating a Hierarchical RTL Module 2 26 The Basics of Hierarchical Module Creation 2 26 Hierarchical RTL Module Example 2 28 Using the Synthesizable Subset Converting to a Synthesizable Subset 005 3 2 SystemC and C Synthesizable Subsets 3 2 Nonsynthesizable SystemC Constructs 3 3 Nonsynthesizable C C Constructs asn ann
26. TOR module_name Register processes Declare sensitivity list Note Do not use data variables for peer to peer communication in a module This can cause pre and post synthesis simulation mismatches and nondeterminism order dependency in your design Creating SystemC Modules for RTL Synthesis Creating a Module 2 10 Creating a Process in a Module SystemC processes are declared in the module body and registered as processes inside the constructor of the module as shown in bold in Example 2 1 You must declare a process with a return type of void and no arguments which is also shown in bold in Example 2 1 To register a function as an SC_METHOD process you need to use the SC_METHOD macro that is defined in the SystemC class library The SC_METHOD macro takes one argument the name of the process Example 2 1 Creating a Method Process in a Module SC_MODULE my_module Ports sc_in lt int gt a sc_in lt bool gt b sc_out lt int gt x sc_out lt int gt y Internal signals sc_signal lt bool gt c sc_signal lt int gt d process declaration void my_method_proc module constructor SC_CTOR my_module register process SC_METHOD my_method_proc Define the sensitivity list Creating SystemC Modules for RTL Synthesis Creating a Module 2 11 Defining the Sensitivity List An SC_METHOD process reacts to a set of signals called its sensitivity list You can
27. _CTOR counter SC_METHOD do_count sensitive_pos lt lt clk sensitive_neg lt lt reset_z SC_METHOD outregs sensitive_pos lt lt clk sensitive_neg lt lt reset_z Using the Synthesizable Subset Modifying Data for Synthesis 3 15 void do_count if reset read 0 count 0 else count void outregs if reset read 0 count_out write 0 else count_out write count hi To eliminate the nondeterminism of count in Example 3 3 change count to an sc_signal as shown in bold in Example 3 4 Notice that the only change in the code is the type declaration of count Example 3 4 Correct Use of a Signal for Interprocess Communication mem_var_good h include systemc h SC_MODULE counter sc_in lt bool gt clk sc_in lt bool gt reset_z sc_out lt sc_uint lt 4 gt gt count_out Signal for interprocess communication sc_signal lt sc_uint lt 4 gt gt count SC_CTOR counter SC_METHOD do_count sensitive_pos lt lt clk sensitive_neg lt lt reset_z SC_METHOD outregs sensitive_pos lt lt clk sensitive_neg lt lt reset_z Using the Synthesizable Subset Modifying Data for Synthesis 3 16 void do_count if reset read 0 count 0 else count void outregs if reset read 0 count_out write 0 else count_out write count Recommendations About Modificat
28. _flop sensitive_pos lt lt clk sensitive_neg lt lt set lt lt reset hi void jkff2 jk_ flop sc_uint lt 2 gt temp temp if reset read 0 q write 0 reset else if set read 0 q write 1 set Jelse temp 1 j read temp 0 k read switch temp to create vector case 0x1 q write 0 write zero break case 0x2 q write 1 write al break RTL Coding Guidelines Register Inference 4 12 case 0x3 toggle q write q read break default break no change Figure 4 7 JK Flip Flop With Asynchronous Set and Reset set clk reset Inferring Toggle Flip Flops This section describes the toggle flip flop with an asynchronous set and the toggle flip flop with an asynchronous reset Toggle Flip Flop With Asynchronous Set Example 4 8 is a description for a toggle flip flop with asynchronous set The asynchronous set signal is specified in the sensitivity list Figure 4 8 shows the flip flop Example 4 8 Toggle Flip Flop With Asynchronous Set include systemc h SC_MODULE tffl sc_in lt bool gt set clk sc_inout lt bool gt q inout to read q for toggle void t_async_set_fen RTL Coding Guidelines Register Inference 4 13 SC_CTOR tff1 SC_METHOD t_async_set_fcn sensitive_pos lt lt clk lt lt set void tffl t_async_set_fen if set read q write 1 Jelsef
29. a char is 8 bits wide a short is 16 bits wide and both an int and long are 32 bits wide An int however can be 16 32 or 64 bits wide Using the Synthesizable Subset Modifying Data for Synthesis 3 9 To restrict bit size for synthesis use the recommended SystemC data types summarized in Table 3 3 in place of the equivalent C native type For example change an int type to an sc_int lt n gt type Table 3 3 Synthesizable Data Types SystemC and C type Description sc_bit A single bit true or false value Supported but not recommended Use the bool data type sc_bv lt n gt Arbitrary length bit vector Use sc_uint lt n gt when possible sc_logic A single bit 0 1 X or Z sc_lv lt n gt Arbitrary length logic vector sc_int lt n gt Fixed precision integers restricted in size up to 64 bits and 64 bits of precision during operations sc_uint lt n gt Fixed precision integers restricted in size up to 64 bits and 64 bits of precision during operations unsigned sc_bigint lt n gt Arbitrary precision integers recommended for sizes over 64 bits and unlimited precision sc_biguint lt n gt Arbitrary precision integers recommended for sizes over 64 bits and unlimited precision unsigned bool A single bit true or false value int A signed integer typically 32 or 64 bits depending on the platform unsigned int An unsigned integer typically 32 or 64 bits depending on the platform long A signed integer t
30. and sc_uint lt 8 gt address sc_uint lt 12 gt data Using C Data Types The native C data types such as bool char int long short unsigned char unsigned int unsigned long and unsigned short have a platform specific size which will be used during synthesis Using the Synthesizable Subset Modifying Data for Synthesis 3 14 Data Members of a Module Do not use data members for interprocess communication because it can lead to nondeterminism order dependencies during simulation and it can cause mismatches between the results of pre and post synthesis simulation Instead of a data member for interprocess communication use an sc_signal for this purpose Example 3 3 shows in bold a data member variable named count that is incorrectly used to communicate between the do_count and outregs processes A value is written to the count variable in the do_count process and a value is read from the same variable in the outregs process The order in which the two processes execute cannot be predicted therefore you cannot determine whether writing to the count variable is happening before or after count Is incremented Example 3 3 Incorrect Use of a Data Member Variable for Interprocess Communication mem_var_bad h include systemc h SC_MODULE counter sc_in lt bool gt clk sc_in lt bool gt reset_z sc_out lt sc_uint lt 4 gt gt count_out sc_uint lt 4 gt count Member Variable SC
31. and VHDL hardware description languages with tools and design flows based on them Why should you bother to understand how to use SystemC a system design language for hardware design and synthesis Consider a scenario where a system designer has created an architectural model of a SoC in SystemC and you are a hardware designer The architectural model contains a variety of models including processor models abstract bus models and peripheral models The peripheral models capture the full functionality and interface of the peripherals although at a high level of abstraction This allows the system designer to hand you the peripheral models as an executable specification along with written requirements for the area speed and power consumption for the peripherals Interpretation Errors You need to implement the peripherals and verify the implementation in the context of the entire system If you use a Verilog or VHDL synthesis tool you need to rewrite the peripheral models in Verilog or VHDL which is a time consuming and error prone process Or you can synthesize the peripheral models from SystemC Instead of throwing away the work done at the system level and recoding the design you can take the abstract non synthesizable peripheral models and change them into synthesizable models SystemC RTL Synthesis Overview Why Synthesis From SystemC 1 5 Verification Reuse As an added advantage you can use the system level verification e
32. assing Replace in all other parameters to functions cases Reference Reference conversion is Replace in all other conversion supported for implicit cases conversion of signals only Static variable Not allowed in functions User defined Only SystemC templates Replace template class classes such as sc_int lt gt are supported Explicit The C built in types and Replace in all other user defined SystemC types are supported cases type conversion only for explicit conversion Type casting at Not allowed Replace runtime Type Not allowed Replace identification at runtime Unconditional goto Not allowed Replace branching Using the Synthesizable Subset Converting to a Synthesizable Subset 3 6 Table 3 2 Nonsynthesizable C C Constructs Continued Category Construct Comment Corrective action Unions Not allowed Replace with structs Global variable Not supported for synthesis Replace with local variables Member Member variables accessed by Use signals instead of variable two or more SC_METHOD variables for processes are not supported communication However access to member between processes variables by only one process is supported Volatile variable Not allowed Use only nonvolatile variables Modifying Data for Synthesis A pure C C model or a high level SystemC model typically uses native C types or aggregates structures of such types Native C types such as int char bool and long have fixed
33. ate logic Example 4 28 State Machine With Separate Computation Processes SC_MODULE fsm_b sc_in_clk clk sc_in lt bool gt rst inputi input2 sc_out lt bool gt a b sc_signal lt state_t gt state next_state void ns_op_logic void output_logic void update_state SC_CTOR fsm_b SC_METHOD update_state sensitive_pos lt lt clk SC_METHOD ns_logic sensitive lt lt state lt lt inputl lt lt input2 SC_METHOD output_logic sensitive lt lt state lt lt inputl lt lt input2 enum state_t enumerate states SO Sl S2 void fsm_b update_state if rst read true state S0 else state next_state void fsm_b ns_logic Determine next state RTL Coding Guidelines State Machines 4 42 switch state case SOQ if inputl read 1 next_state Sl else next_state SO break case Sl if input2 read 1 next_state S2 else next_state SO break case S2 next_state S0 break default next_state S0 break void fsm_b output_logic determine outputs a write s tate SO amp amp inputl read input2 read tate Sl b write s RTL Coding Guidelines State Machines 4 43 Moore State Machine Example 4 28 shows a Moore state machine with a single SC_METHOD process for computing and updating the output and next s
34. ch in_i read case 0 out write 0x01 break case 1 out write 0x02 break case 2 out write 0x04 break case 3 out write 0x10 break case 4 out write 0x20 break case 5 out write 0x40 break Constructor SC_CTOR d_latch2 SC_METHOD d_latch_fcn sensitive in_i RTL Coding Guidelines Register Inference 4 21 Figure 4 14 Latch Inference From a switch Statement ee mdapts F To avoid latch inference caused by the incomplete switch statement in Example 4 14 add a default case statement as shown in Example 4 15 Figure 4 15 shows the resulting schematic Example 4 15 Avoiding Latch Inference From a switch Statement include systemc h SC_MODULE d_latch2a sc_in lt unsigned char gt in_i sc_out lt unsigned char gt out Method process void d_latch_fen RTL Coding Guidelines Register Inference 4 22 switch in_i read case 0 out write 0x01 break case 1 out write 0x02 break case 2 out write 0x04 break case 3 out write 0x10 break case 4 out write 0x20 break case 5 out write 0x40 break default out write 0x01 Constructor SC_CTOR d_latch2a SC_METHOD d_latch_fen sensitive in_i hi Figure 4 15 Avoiding Latch Inference by Adding a Default Case to a switch Statement oul 7 0 in_i GE RTL Coding Guidelines Register Inference 4 23 You ca
35. d else out_l write Z Figure 4 24 Three State Bus Driver Schematic In_selb In_b 0 0 In_sela in_a 0 0 out_1 0r0 Registered Three State Drivers When a variable is registered in the same process in which it is ina three state condition RTL synthesis also registers the enable pin of the three state gate Example 4 25 is an example of this type of code Figure 4 25 shows the schematic generated by the code Example 4 25 Three State Driver With Registered Enable simple thr state buffer inference include systemc h SC_MODULE tristate_ex4 sc_in lt bool gt control sc_in lt sc_logic gt data sc_out lt sc_logic gt ts_out sc_in_clk clk Method for three state driver RTL Coding Guidelines Three State Inference 4 34 void tristate_fen if control read ts_out write data read else ts_out write Z Constructor SC_CTOR tristate_ex4 SC_METHOD tristate_fcn sensitive_pos lt lt clk note inferred seq logic IL Figure 4 25 Three State Driver With Registered Enable clk control date ts_out To avoid registering the enable pin separate the three state driver inference from the sequential logic inference using two SC_METHOD processes Example 4 26 uses two methods to instantiate a three state gate with a flip flop only on the input Note that the sc_signal temp is used to communicate between the two SC_METHOD proc
36. d data inputs to the registers can be directly controlled from the ports of the design This ensures that you can initialize your design easily during simulation as well as in the actual circuit You can of course infer registers with set and reset which makes the task of register initialization easier and is highly recommended Flip Flop Inference RTL synthesis can infer D flip flops JK flip flops and toggle flip flops The following sections provide details about each of these flip flop types Simple D Flip flop To infer a simple D flip flop make the SC_METHOD process sensitive to only one edge of the clock signal To infer a positive edge triggered flip flop make the process sensitive to the positive edge of the clock and make the process sensitive to the negative edge to infer a negative edge triggered flip flop RTL Coding Guidelines Register Inference 4 2 RTL synthesis creates flip flops for all the variables that are assigned values in the process Example 4 1 is acommon SC_METHOD process description that infers a flip flop Figure 4 1 shows the inferred flip flop Example 4 1 Inferring a Positive Edge Triggered Flip Flop Rising edge triggered DFF include systemc h SC_MODULE dffl sc_in lt bool gt in_data sc_out lt bool gt out oO sc_in lt bool gt clock clock port Method for D flip flop void do_dff_pos Constructor SC_CTOR dff1 SC_METHOD do_dff_pos
37. dicate FIFO is full sc_out lt bool gt empty Indicate FIFO is empty int buffer BUFSIZE FIFO buffer sc_uint lt LOGBUFSIZE gt headp Pointer to FIFO head sc_uint lt LOGBUFSIZE gt tailp Pointer to FIFO tail Counter for number of elements sc_uint lt LOGBUFSIZEPLUSONE gt num_in_buf wu Behavioral Modeling and Synthesis RTL and Behavioral Coding Style Examples 5 16 void read_write FIFO process SC_CTOR circ_buf SC_CTHREAD read_write clk pos watching reset delayed true tt fifo_bhv cc implementation file include systemc h include fifo_bhv h void circ_buf read_write Reset operations headp 0 tailp 0 num_in_buf 0 full false empty true data_out 0 for int i 0 i lt BUFSIZE i synopsys unroll buffer i 0 wait Main loop while true if read_fifo read Check if FIFO is not empty if num_in_buf 0 num_in_buf data_out buffer headpt t full false if num_in_buf 0 empty true Ignore read request otherwise else if write_fifo read Check if FIFO is not full if num_in_buf BUFSIZE Behavioral Modeling and Synthesis RTL and Behavioral Coding Style Examples 5 17 buffer tailp data_in num_in_buf mpty false if num_in_buf BUFSIZE full true Ignore write reques
38. duces two outputs the number of zeros found and an error indication Figure 2 6 illustrates the module and its ports Figure 2 6 Count Zeros Combinational Module count_zeros_combo in control out proc error Example 2 10 Count Zeros Combinational Version count_zeros_comb h file include systemc h SC_MODULE count_zeros_comb sc_in lt sc_uint lt 8 gt gt in sc_out lt sc_uint lt 4 gt gt out sc_out lt bool gt error bool legal sc_uint lt 8 gt x sc_uint lt 4 gt zeros sc_uint lt 8 gt x void control_proc SC_CTOR count_zeros_comb SC_METHOD control_proc sensitive lt lt in D Creating SystemC Modules for RTL Synthesis Creating a Module With a Single SC_METHOD Process 2 20 count_zeros_comb cpp file include count_zeros_comb h void count_zeros_comb control_proc sc_uint lt 4 gt tmp_out bool is_legal legal in read error write is_legal 1 is_legal tmp_out zeros in read tmp_out 0 out write tmp_out bool count_zeros_comb legal sc_uint lt 8 gt x bool is_legal 1 bool seenZero 0 bool seenTrailing 0 for int i 0 i lt 7 i if seenTrailing 1 amp amp x i 0 is_legal 0 break else if seenZero 1 amp amp x i 1 seenTrailing 1 else if x i 0 seenZero 1 return is_legal
39. dules for RTL Synthesis Creating a Module With Multiple SC_METHOD Processes 2 22 Example 2 11 Count Zeros Sequential Version count_zeros_seq h file include systemc h define ZEROS WIDTH 4 define MAX BIT READ 7 SC_MODULE count_zeros_seq sc_signal lt bool gt new_data_ready new_is_legal new_s sc_in lt bool gt data reset read clk sc_out lt bool gt is_legal data_ready sc_out lt sc_uint lt ZEROS_WIDTH gt gt zeros sc_signal lt bool gt seenZero seenTrailing sc_signal lt bool gt is_legal_s data_ready_s sc_signal lt sc_uint lt ZEROS_WIDTH gt gt new_zeros zeros_s sc_signal lt sc_uint lt ZEROS_WIDTH 1 gt gt bits_seen new_bits_seen Processes void comb_logic void seq_logic void assign_outputs Helper functions void set_defaults SC_CTOR count_zeros_seq SC_METHOD comb_logic sensitive lt lt data lt lt read lt lt is_legal_s lt lt data_ready_s sensitive lt lt seenTrailing lt lt seenZero lt lt zeros_s lt lt bits_seen SC_METHOD seq_logic sensitive_pos lt lt clk lt lt reset SC_METHOD assign_outputs sensitive lt lt is_legal_s lt lt data_ready_s lt lt zeros_s nZero nTrailing Creating SystemC Modules for RTL Synthesis Creating a Module With Multiple SC_METHOD Processes 2 23 count_zeros_seq cpp file include count_zeros_seq h
40. e output and next state logic Example 4 27 State Machine With a Common Computation Process SC_MODULE ex_fsm_a sc_in_clk clk sc_in lt bool gt rst inputi input2 sc_out lt bool gt a b sc_signal lt state_t gt state next_state void ns_op_logic void update_state SC_CTOR ex_fsm_a SC_METHOD update_state sensitive_pos lt lt clk SC_METHOD ns_op_logic sensitive lt lt state lt lt inputl lt lt input2 enum state_t enumerate states S0 SL 2 hi void ex_fsm_a update_state if rst read true state S0 else state next_state void ex_fsm_a ns_op_logic Determine next state and output logic switch state case SO RTL Coding Guidelines State Machines 4 40 b write 0 if inputl read input2 read a write 1 else a write 0 if inputl read 1 next_state Sl else next_state SO break case Sl a write 0 b write 1 if input2 read 1 next_state S2 else next_state SO break case S2 a write 0 b write 0 next_state S0 break default a write 0 b write 0 next_state S0 break RTL Coding Guidelines State Machines 4 41 State Machine With Separate Computation Processes Example 4 28 shows the state machine represented in Figure 4 28 with separate SC_METHOD processes for computing the output and next st
41. elect on the temporary variable Example 2 7 shows in bold how to write a bit by using a temporary variable Creating SystemC Modules for RTL Synthesis Creating a Module 2 16 Example 2 7 Reading and Writing Bits of a Variable e exis sc_signal lt sc_int lt 8 gt gt a sc_int lt 8 gt b bool c b a read c b 0 c a 0 Does not work in SystemC Example 2 7 reads the value of signal a into temporary variable b and bit 0 of b is assigned to c You cannot read a bit from signal a because this operation is not allowed in SystemC Signal and Port Assignments When you assign a value to a signal or port the value on the right side is not transferred to the left side until the process ends This means the signal value as seen by other processes is not updated immediately but it is deferred Example 2 8 shows a serial register implementation with signal assignment and Figure 2 4 shows the resulting schematic Example 2 8 Signal Assignment include systemc h SC_MODULE rtl_nb sc_in lt bool gt clk sc_in lt bool gt data sc_inout lt bool gt regc regd void reg_proc regc write data read regd write regc read Creating SystemC Modules for RTL Synthesis Creating a Module 2 17 SC_CTOR rtl_nb SC_METHOD reg_proc sensitive_pos lt lt clk Figure 2 4 Signal Assignment Schematic rege data reqd clk Variable Assignment When you assign a val
42. eros_seq set_defaults new_is_legal is_legal_s new_s nZero sS nZero new_seenTrailing seenTrailing new_zeros zeros_s new_bits_seen bits_seen new_data_ready data_ready_s Creating SystemC Modules for RTL Synthesis Creating a Module With Multiple SC_METHOD Processes 2 25 Creating a Hierarchical RTL Module You can create a hierarchical module with multiple instantiated modules The Basics of Hierarchical Module Creation To create a hierarchical module 1 Create data members in the top level module that are pointers to the instantiated modules 2 Allocate the instantiated modules inside the constructor of the top level module giving each instance a unique name 3 Bind the ports of the instantiated modules to the ports or signals of the top level module Use either binding by position or binding by name coding style which is illustrated in bold in Example 2 12 Example 2 12 shows the partial source code of two modules fir_fsm and fir_data instantiated within the fir_top module The relevant code is highlighted in bold Example 2 12 Hierarchical Module With Multiple RTL Modules PREECE IL COP Att include lt systemc h gt fir fam bi fir data bi include include SC_MODULE fir_top sc_in sc_in sc_in sc_in _clk lt bool gt lt bool gt lt int gt CLK RESET SAMPLE IN_VALID Creating SystemC Modules for RTL Synthesis Creating a
43. esizable Subset This chapter explains the subset of the SystemC and C C language elements and data types that are used for RTL synthesis It contains the following sections e Converting to a Synthesizable Subset e Modifying Data for Synthesis e Recommendations About Modification for Synthesis 3 1 Converting to a Synthesizable Subset To prepare for synthesis you need to convert all nonsynthesizable code into synthesizable code This is required only for functionality that is to be synthesized Although you can use any SystemC class or C construct for simulation and other stages of the design process only a subset of the language can be used for synthesis You can use ifdef and endif to comment out code that is needed only for simulation For example you can exclude trace and print statements with these compiler directives SystemC and C Synthesizable Subsets The synthesizable subsets of SystemC and C are provided in the sections that follow Wherever possible a recommended corrective action is indicated for converting nonsynthesizable constructs into synthesizable constructs For many nonsynthesizable constructs there is no obvious recommendation for converting them into synthesizable constructs or there are numerous ways to convert them In such cases a recommended corrective action is not indicated Familiarize yourself with the synthesizable subset and use it as much as possible in your pure C C or high level S
44. esses Figure 4 26 shows the schematic the code generates RTL Coding Guidelines Three State Inference 4 35 Example 4 26 Three State Driver Without Registered Enable simple thr state buffer inference include systemc h SC_MODULE tristate_ex5 sc_in lt bool gt control sc_in lt sc_logic gt data sc_out lt sc_logic gt ts_out sc_in_clk clk sc_signal lt sc_logic gt temp Method for three state driver void tristate_fen if control read ts_out write temp else ts_out write 2 Method for sequential logic void flop temp data read Constructor SC_CTOR tristate_ex5 SC_METHOD tristate_fcn sensitive lt lt control lt lt temp SC_METHOD flop sensitive_pos lt lt clk RTL Coding Guidelines Three State Inference 4 36 Figure 4 26 Three State Driver Without Registered Enable control data ts_out clk RTL Coding Guidelines Three State Inference 4 37 State Machines Explicitly describe state machines for RTL synthesis Figure 4 27 shows a Mealy state machine structure Figure 4 27 Mealy State Machine Inputs Outputs 3 gt p Next state State Output logic logic m vector _ clk The diagram in Figure 4 27 has one sequential element he state vector and two combinational elements the output logic and the next state logic Although the
45. ex algorithms are faster to simulate because of the higher level of abstraction accommodate late specification changes and are more intuitive to write and understand and therefore maintain than RTL descriptions Behavioral Modeling and Synthesis Comparing RTL and Behavioral Modeling 5 2 What is Behavioral Synthesis Behavioral synthesis performs the following with a SystemC behavioral description Times all operations according to a technology library Schedules each operation input read and output write to occur at a specified clock cycle Allocates synthetic components to execute the operations in your design Allocates registers to store the values of variables signals and intermediate operation results Creates a data path with the allocated synthetic components and registers by inserting multiplexers and interconnects as needed Creates a finite state machine FSM and memory interface control logic The synthesized design consists of an FSM a data path and memory as shown in Figure 5 1 Behavioral Modeling and Synthesis What is Behavioral Synthesis 5 3 Figure 5 1 Structure of the Circuit Generated During Behavioral Synthesis Control FSM External _ gt input Si Logic Memory State bo optional Status Control v Input p 0000 0110110010110101 Data 1000 01111000010
46. gnal_name c_signal lt signal_type gt signall signal Data variable declarations Process declarations Member function declarations Module constructor C_CTOR module_name Register processes Declare sensitivity list Signal Data Types A sign Specif al s bit width is determined by its corresponding data type y the data type as any of the synthesizable SystemC or C data types listed in Converting to a Synthesizable Subset on page 3 2 Signals and the ports they connect must have the same data types Creating SystemC Modules for RTL Synthesis Creating a Module 2 9 Data Member Variables Inside a module you can define data member variables of any synthesizable SystemC or C type These variables can be used for internal storage in the module Recommendations about using data member variables for synthesis are provided in Data Members of a Module on page 3 15 Declare internal data variables by using the syntax shown in bold in the following example SC_MODULE module_name Module port declarations sc_in lt port_type gt port_name sc_out lt port_type gt port_name sc_in port_name Internal signal variable declarations sc_signal lt signal_type gt signal_name Data member variable declarations int count_val Internal counter sc_int lt 8 gt mem 1024 Array of sc_int Process declarations Member function declaration Module constructor SC_C
47. gq write q read Figure 4 8 Toggle Flip Flop With Asynchronous Set set clk RTL Coding Guidelines Register Inference 4 14 Toggle Flip Flop With Asynchronous Reset Example 4 9 is a SystemC description for a toggle flip flop with asynchronous reset The asynchronous reset signal is specified in the sensitivity list Figure 4 9 shows the inferred flip flop Example 4 9 Toggle Flip Flop With Asynchronous Reset include systemc h SC_MODULE tff2 sc_in lt bool gt reset clk sc_inout lt bool gt q to read q for toggle void t_async_reset_fen SC_CTOR tff2 SC_METHOD t_async_reset_fcn sensitive_pos lt lt clk lt lt reset IL void tff2 t_async_reset_fen if reset read q write 0 jelsef q write q read Figure 4 9 Toggle Flip Flop With Asynchronous Reset clk reset RTL Coding Guidelines Register Inference 4 15 Latch Inference In simulation a signal or variable holds its value until that value is reassigned A latch implements the ability to hold a state in hardware RTL synthesis supports inference of set reset SR and delay D latches You can unintentionally infer latches from your SystemC code which can add unnecessary hardware RTL synthesis infers a D latch when your description has an incomplete assignment in an if else or switch case statement To avoid creating a latch specify all conditions in if else and switch case s
48. h processes and other modules are instantiated A typical module can have e Single or multiple RTL processes to specify combinational or sequential logic e Multiple RTL modules to specify hierarchy e One or more member functions that are called from within an instantiated process or module Figure 2 1 shows a module with several RTL processes The processes within a module are concurrent and they execute whenever one of their sensitive inputs changes Creating SystemC Modules for RTL Synthesis Defining Modules and Processes 2 2 Figure 2 1 Module Module Ports p Koi process Signals gt process RTL process Processes SystemC provides processes to describe the parallel behavior of hardware systems This means processes execute concurrently rather than sequentially like C functions The code within a process however executes sequentially Registering a Process Defining a process is similar to defining a C function A process is declared as a member function of a module class and registered as a process in the module s constructor Registering a process means that it is recognized as a SystemC process rather than as an ordinary member function You can register multiple different processes but it is an error to register more than one instance of the same process To create multiple instances of the same process enclose the process ina module and instantiate
49. ignals sc_signal lt bool gt c sc_signal lt int gt d process declaration void my_method_proc module constructor SC_CTOR my_module register process SC_METHOD my_method_proc declare sensitivity list sensitive_pos clock Function delaration sensitive_neg lt lt b lt lt reset Stream declaration Limitations for Sensitivity Lists When you define a sensitivity list adhere to the following limitations e You cannot specify both edge sensitive and level sensitive inputs in the same process for synthesis e You cannot declare an sc_logic type for the clock or other edge sensitive inputs You can declare only an sc_in lt bool gt data type Creating SystemC Modules for RTL Synthesis Creating a Module 2 14 Member Functions You can declare member functions in a module that are not processes This type of member function is not registered as a process in the modules constructor It can be called from a process Member functions can contain any synthesizable C or SystemC statement allowed ina SC_METHOD process A member function that is not a process can return any synthesizable data type Module Constructor For each module you need to create a constructor which is used to e Register processes e Define a sensitivity list for an SC_METHOD process For synthesis other statements are not allowed in the constructor See Example 2 4 Implementing the Module I
50. ion for Synthesis The following practices are recommended during modification for synthesis After each modification step reverify your design to ensure that you did not introduce errors during that step Although it is recommended that you thoroughly define at each modification stage it is not necessary For example during data modification you can change one data type at a time and evaluate the impact on synthesizability and the quality of results Similarly you might want to replace one nonsynthesizable construct with a synthesizable construct and reverify the design before replacing the next nonsynthesizable construct Using the Synthesizable Subset Recommendations About Modification for Synthesis 3 17 Using the Synthesizable Subset Recommendations About Modification for Synthesis 3 18 4 RTL Coding Guidelines This chapter provides SystemC RTL coding guidelines It contains the following sections e Register Inference e Three State Inference e State Machines 4 1 Register Inference Register inference allows you to use sequential logic in your designs and keep your designs technology independent A register is an array of 1 bit memory devices A latch is a level sensitive memory device and a flip flop is an edge triggered memory device Use the coding guidelines in this section to control flip flop and latch inference As a recommended design practice whenever you infer registers ensure that the clock an
51. is Guide The Describing Synthesizable RTL in SystemC describes how to develop a SystemC RTL model for synthesis and introduces behavioral modeling and synthesis For information about SystemC see the Open SystemC Community web site at http www systemc org Related Publications For information about the SystemC language and syntax see the SystemC User s Manual available from the Open SystemC Community web site at http www systemc org Comments About This Document E mail your comments about this document to techpubs sld synopsys com Typographical Conventions Courier font is used in this document to distinguish SystemC code examples SystemC Training For information about SystemC training and private workshops contact Willamette HDL http www whdl com Three day SystemC for High Level Synthesis Three day Modeling With SystemC Transfer http www transfer nt Three day Modeling With SystemC Fraunhofer IIS A http www lis fhg de Three day SystemC Training Classes Doulos Five day Comprehensive SystemC Training Class http www doulos com Blue Pacific Computing http www bluepc com Three Day SystemC Workshop xi xii Information About Synopsys SystemC Synthesis Products For information about Synopsys SystemC synthesis products contact your local Synopsys sales representative or 1 Go to the Synopsys Web page at http www synopsys com 2 In the Synopsys Products field choose
52. izes the implementation area by sharing components between operations and by sharing registers between values Figure 5 3 shows hardware allocation that uses one multiplier one adder and one comparator to execute the operations Note the use of the same multiplier to execute the two multiply operations which is an example of resource sharing Figure 5 3 Allocation of Resources Scheduled operations Hardware resources Cycle Operation Allocation Multiplier Adder Comparator 1 read inputs 2 OOOO Behavioral Modeling and Synthesis What is Behavioral Synthesis 5 7 Creating the Data Path and Finite State Machine Scheduling and allocation fully define the architecture of your design Behavioral synthesis creates the data path of the architecture by connecting the allocated components and registers to each other with wires and multiplexers and it generates a finite state machine FSM to control the data path The FSM configures the data path during circuit execution to ensure that operations are executed and data is correctly stored and routed through the data path The FSM also implements control constructs such as loop if and while statements from your behavioral description Figure 5 4 shows a simple algorithm and the data path and FSM created by behavioral synthesis Figure 5 4 An Algorithm With the Created Data Path and FSM R 1 while I gt 1 ED a R
53. loration of alternative architectures Automatically creates the control FSM and data path Pipelines critical parts of the design such as loops Shares components and registers Automatically synthesizes synchronous memory accesses Behavioral Modeling and Synthesis Choosing the Right Abstraction for Synthesis 5 11 RTL and Behavioral Coding Style Examples This section provides an RTL description and a behavioral description for a FIFO The FIFO is a circular buffer that accepts a 32 bit integer value from the input and writes an integer to the output The reset port clears all data in the buffer The RTL description shows the level of detail you need in order to describe an RTL model which is automatically created during behavioral synthesis from the behavioral description RTL Coding Style The general characteristics of the RTL coding style for synthesis are the following e Implements the design as combinational logic between registers The finite state machine and the data path are explicitly specified e Uses only the synthesizable SystemC data types e Uses the synthesizable subset of the C language Example 5 1 is an RTL version of the FIFO behavioral model in Example 5 2 The RTL coding style has separate processes for the FSM control and data path Notice that the RTL version of the FIFO is much longer and more detailed than the equivalent behavioral version and that it is harder to follow than the behavioral description
54. low and control dependencies described in the behavioral description Satisfy any scheduling constraints of latency throughput and clock period specified Minimize the number of clock cycles needed by the implementation to execute the specified functionality Facilitate resource sharing by distributing operations over the available clock cycles to minimize the implementation area Facilitate register sharing by intelligently producing and using data to minimize the number of registers needed I O between the implementation synthesized by behavioral synthesis and the external environment usually has a predefined protocol The I O protocol typically specifies either a fully synchronous interface with a fixed clock cycle for each input and output or a handshake driven interface where the relative order of inputs and outputs is specified but the clock cycle when each input and output occurs can vary You define whether behavioral synthesis uses a fixed clock cycle or handshake driven interface Behavioral Modeling and Synthesis What is Behavioral Synthesis 5 6 Allocating Hardware After the design is scheduled into clock cycles behavioral synthesis allocates the hardware It adds synthetic components to the implementation to execute the operations in the behavioral description and it adds registers to hold the values of variables signals and intermediate data produced by operations When it is beneficial behavioral synthesis minim
55. lt bool gt out_q void d_latch_fen if set read 0 out_q write 1 Jelse if clock read out_q write in_data read Constructor SC_CTOR d_latch4 SC_METHOD d_latch_fcn sensitive lt lt in data lt lt clock lt lt set Figure 4 20 Latch With Asynchronous Set ndata out_q clo set RTL Coding Guidelines Register Inference 4 29 D Latch With an Asynchronous Reset Example 4 21 is a SystemC description for a D latch with an asynchronous reset Figure 4 21 shows the inferred latch Example 4 21 Latch With Asynchronous Reset include systemc h SC_MODULE d_latch5 sc_in lt bool gt in_data reset sc_in lt bool gt clock sc_out lt bool gt out oO void d_latch_fcn if reset read out_q write 0 Jelse if clock read out_q write in_data read Constructor SC_CTOR d_latch5 SC_METHOD d_latch_fcn sensitive lt lt in_data lt lt clock lt lt reset 0 Figure 4 21 Latch With Asynchronous Reset indata out_q cloc rese RTL Coding Guidelines Register Inference 4 30 Three State Inference A three state driver is inferred when you assign the value Z to a variable The value Z represents the high impedance state You can assign high impedance values to single bit or bused variables The assignment must occur in a conditional statement if or switch or with the conditional operato
56. n Active High Asynchronous Reset in_data out_q clock reset D Flip Flop With an Active Low Asynchronous Set or Reset Example 4 3 is a SystemC description for a D flip flop with an active low asynchronous reset Figure 4 3 shows the inferred flip flop Example 4 3 D Flip Flop With an Active Low Asynchronous Reset Rising edge triggered DFF with active low reset include systemc h SC_MODULE dff3a sc_in lt bool gt in_data reset sc_out lt bool gt out oO sc_in lt bool gt clock clock port void do dff pos Constructor SC_CTOR dff3a SC_METHOD do_dff_pos sensitive_pos lt lt clock RTL Coding Guidelines Register Inference 4 5 sensitive_neg lt lt reset void dff3a do_dff_pos if reset read 0 out_g write 0 Jelsef out_q write in_data read Figure 4 3 D Flip Flop With an Active Low Asynchronous Reset In_data out_q cloc rese RTL Coding Guidelines Register Inference 4 6 D Flip Flop With Active High Asynchronous Set and Reset Example 4 4 is a SystemC description for a D flip flop with active high asynchronous set and reset ports Figure 4 4 shows the inferred flip flop An implied priority exists between set and reset and reset has priority This priority is not guaranteed because it can be implemented differently in various technology libraries To ensure the correct behavior assign a high value to either the se
57. n also avoid latch inference caused by the incomplete switch statement in Example 4 14 by writing a default value to the output port as shown in Example 4 16 Figure 4 16 shows the resulting schematic Example 4 16 Seta Default Value to Avoid Latch Inference From a switch Statement include systemc h SC_MODULE d_latch2b sc_in lt unsigned char gt in_i sc_out lt unsigned char gt out Method process void d_latch_fcn out write 1 Set default value switch in_i read case 0 out write 0x01 break case 1 out write 0x02 break case 2 out write 0x04 break case 3 out write 0x10 break case 4 out write 0x20 break case 5 out write 0x40 break Constructor SC_CTOR d_latch2b SC_METHOD d_latch_fcn sensitive in_i RTL Coding Guidelines Register Inference 4 24 Figure 4 16 Avoiding Latch Inference by Setting a Default Case Before a switch Statement oul 7 0 in_i GES Active Low Set and Reset To instruct RTL synthesis to implement all signals in the group as active low add a check to the SystemC code to ensure that the group of signals has only one active low signal at a given time RTL synthesis does not produce any logic to check this assertion Example 4 17 shows a latch with an active low set and reset Figure 4 17 shows the resulting schematic Example 4 17 Latch With Active Low Set and Reset include systemc h
58. n nna 3 4 Modifying Data for Synthesis 3 7 Synthesizable Data fvpes 0 000 eee 3 8 Nonsynthesizable Data Iwvpes nenn 3 8 Recommended Data Types for Synthesis 3 8 Using SystemC Data Ivpes eee eee 3 12 Bit Vector Data Type Operators annann n annn nna 3 12 Fixed and Arbitrary Precision Data Type Operators 3 13 Using Enumerated Data Types 000020 00s 3 14 Using Aggregate Data Ivpes nunaa aana 3 14 Using C Data Types Re EE ENEE E A an 3 14 Data Members of a Module 3 15 Recommendations About Modification for Synthesis 3 17 4 RTL Coding Guidelines Ee EE 4 2 Flip Flop MNterenice aere abe tet ea eee eee eee ea eds 4 2 Simple D Flip flop Karina ee 4 2 D Flip Flop With an Active High Asynchronous Set Or RESEN ee Eee 4 4 D Flip Flop With an Active Low Asynchronous Set DEE ana EE 4 5 D Flip Flop With Synchronous Set or Reset 4 8 Inferring JK Flip Flops 4 10 Inferring Toggle Flip Flops 22222 muessen 4 13 Lateh Inference eek Sees pee e dee id deed ain 4 16 Inferring a D Latch From an If Statement 4 16 Inferring an SR L leh EE 4 17 Avoiding Latch Inference NN ENN rn Eee 4 19 Inferring a Latch From a Switch Statement 4 21 Active Low Set and Reset 2 200054 4 25 Active High Set and Reset 0 000 cece eee 4 26 D Latch With an Asynchronous Set and Reset 4 28 D Latch With an Asynchronou
59. n the module implementation file define the functionality of each SC_METHOD process and member function Example 2 5 shows a minimal implementation file Example 2 5 Module Implementation File include systemc h include my_module h void my_module my_method_proc describe process functionality as C code Creating SystemC Modules for RTL Synthesis Creating a Module 2 15 Reading and Writing Ports and Signals In the module implementation description you can read from or write to a port or signal by using the read and write methods or by assignment When you read or write a port as a recommended coding practice use the read and write methods Use the assignment operator for variables Example 2 6 shows in bold how to use the read and write methods for ports and signals and it shows assignment operators for variables Example 2 6 Using Assignment and read and write Methods inet read method address into read get address assignment templ address save address data_tmp memory address get data from memory write method outof write data_tmp write out assignment temp2 data_tmp save data_tmp oer Reading and Writing Bits of Ports and Signals You read or write all bits of a port or signal You cannot read or write the individual bits regardless of the type To do a bit select on a port or signal read the value into a temporary variable and do a bit s
60. nvironment to check the correctness of your implementation as you modify it Increased Productivity If a hardware designer receives a SystemC executable specification implementation from SystemC gives higher designer productivity than recoding it in Verilog or VHDL Higher designer productivity comes from two sources modifying the design is faster than recoding and verifying a modified design is faster than verifying a recoded HDL design Modifying is faster than recoding because hardware functionality is envisioned as either an algorithm or a finite state machine and data path even if the description is abstract Algorithmic models can be synthesized using behavioral synthesis techniques and finite state machines and data paths can be synthesized by using RTL synthesis techniques The primary modification tasks are staying within the synthesizable subset and adding the implementation details and the hardware structure that were not included in the abstract model You can reduce the modification effort by ensuring that the system designer minimizes violations in the abstract model Verifying a modified SystemC design is faster than verifying a recoded HDL design because modification changes fewer lines of code and has fewer opportunities to introduce interpretation mistakes Therefore you typically spend less time debugging and verifying the hardware design SystemC RTL Synthesis Overview Why Synthesis From SystemC 1 6 Design
61. omplex control flow for example a network processor e The design has memory accesses and you need to synthesize access to synchronous memory Applications that are suitable for behavioral modeling and synthesis are e Digital communication applications such as cable modems cellular phones cordless phones two way pagers wireless LANs satellite DSPs and XDSL modems e Image and video processing applications such as digital cameras printers set top boxes 3 D graphic devices and video capture devices e Networking applications such as ATM switches fast networking switches and packet routers e Digital signal processing applications such as filters codecs IQ IDCT and channel equalizers e Computer applications such as cache controllers hardware accelerators and fixed point arithmetic units Behavioral Modeling and Synthesis Choosing the Right Abstraction for Synthesis 5 10 Benefits of Behavioral Synthesis The following are benefits of behavioral synthesis compared to RTL synthesis A behavioral description Promotes communication of design intent Is smaller than RTL code Promotes greater design reuse because the design is technology and architecture independent Accommodates late design specification changes because the code is architecture independent Cuts implementation time significantly increasing designer productivity Increases verification speed and decreases verification time Promotes exp
62. ous set or reset test and action in an if statement Example 4 5 is a SystemC description for a D flip flop with synchronous reset Figure 4 5 shows the inferred flip flop RTL Coding Guidelines Register Inference 4 8 Example 4 5 D Flip Flop With Synchronous Reset Rising edge triggered DFF include systemc h SC_MODULE dff5 sc_in lt bool gt in_data reset sc_out lt bool gt out oO sc_in lt bool gt clock clock port Method for D flip flop void dff Constructor SC_CTOR dff5 SC_METHOD dff sensitive_pos lt lt clock void dff5 dff if reset read f out_g write 0 jelsef out_q write in_data read Figure 4 5 D Flip Flop With Synchronous Reset in_data out_q clock reset RTL Coding Guidelines Register Inference 4 9 Inferring JK Flip Flops Use a switch case statement to infer JK flip flops JK Flip Flop With Synchronous Set and Reset Example 4 6 is the SystemC code that implements the JK flip flop truth table described in Table 4 1 In the JK flip flop the J and K signals are similar to active high synchronous set and reset Figure 4 6 shows the inferred flip flop Table 4 1 Positive Edge Triggered JK Flip Flop Truth Table J K CLK Qn 1 0 0 Rising Qn 0 1 Rising 0 1 0 Rising 1 1 1 Rising an x x Falling Qn Example 4 6 JK Flip Flop Rising edge triggered JK FF include systemc h
63. own in bold in the following example SC_MODULE module_name Module port declarations sc_in lt port_data_type gt port_name sc_out lt port_data_type gt port_name sc_inout lt port_data_type gt port_name sc_in lt port_data_type gt port_name Module constructor SC_CTOR module_name Register processes Declare sensitivity list Creating SystemC Modules for RTL Synthesis Creating a Module 2 7 Port Data Types Ports connect to signals and have a data type associated with them For synthesis declare each port as one of the synthesizable data types described in Converting to a Synthesizable Subset on page 3 2 Signals Modules use ports to communicate with other modules In hierarchical modules use signals to communicate between the ports of instantiated modules Use internal signals for peer to peer communication between processes within the same module as shown in Figure 2 3 Figure 2 3 Processes and Signals Module Ports Signals Creating SystemC Modules for RTL Synthesis Creating a Module 2 8 Signal Syntax Declare signals by using the syntax shown in bold in the following example SC_MODULE module_name s s s s s S Module port declarations c_in lt port_type gt port_name c_out lt port_type gt port_name c_in lt port_type gt port_name Internal signal variable declarations c_signal lt signal_type gt si
64. ple Example 2 13 on page 2 29 shows a complete example of the hierarchical RTL finite impulse response FIR filter description This is atypical sequential logic description that separates the controlling FSM Example 2 14 on page 2 30 and the data path Example 2 15 on page 2 32 into two separate modules Figure 2 8 illustrates the modules the port binding and their interconnecting signals In the top level fir_rtl module data member pointers to the fir_fsm and fir data modules are declared new instances of the two modules fir_fsm1 and fir_data1 are created and the port bindings are defined A signal state_out is defined to connect the fir_fsm1 and fir_data1 state_out ports Coding guidelines for state machines are described in State Machines on page 4 38 Creating SystemC Modules for RTL Synthesis Creating a Hierarchical RTL Module 2 28 Figure 2 8 FIR RTL Modules fir_rtl SAMPLE sample result RESULT RESET reset fir data output_data_ready IN VALID in_valid OUTPUT_DATA_READY CLK clk I 5 fir_fsm1 ZS Example 2 13 FIR Top Level Module fir_rtl h file include lt systemc h gt include fir fam bi include fir data bin SC_MODULE fir_rtl sc_in lt bool gt clk sc_in lt bool gt reset sc_in lt bool gt in_valid sc_in lt int gt sample sc_out lt bool gt
65. pty sensitive lt lt num_in_buf_next i tt fifo_rtl cc implementation file include systemc h include fifo_rtl h void circ_buf gen_full if num_in_buf_next read BUFSIZE full_next 1 else full_next 0 void circ_buf gen_empty if num_in_buf_next read 0 empty_next 1 else empty_next 0 void circ_buf update_regs if reset read 1 full 0 empty 1 num_in_buf 0 buf0 0 bufl 0 buf2 0 buf3 0 data_out 0 else full ful empty empty_next num_in_bu num_in_buf_next _next buf0 buf0_next bufl bufl_next buf2 buf2_next buf3 buf3_next data_out data_out_next Behavioral Modeling and Synthesis RTL and Behavioral Coding Style Examples 5 14 void circ_buf ns_logic Default assignments buf0_next buf0 bufl_next bufl buf2_next buf2 buf3_next buf3 num_in_buf_next num_in_buf data_out_next 0 if read_fifo read 1 if num_in_buf read 0 data_out_next buf0 bufO_next bufl bufl_next buf2 buf2_next buf3 num_in_buf_next num_in_buf read 1 else if write_fifo read 1 switch int num_in_buf read case 0 buf0_next data_in read num_in_buf_next num_in_buf read 1 break case 1 bufl_next data_in read num_in_buf_next num_in_buf read 1 break case 2
66. r Note that only the sc_logic and sc_lv data types support the value Z Simple Three State Inference Example 4 22 is a SystemC description for a simple three state driver Figure 4 22 shows the schematic the code generates Example 4 22 Three State Buffer Inference From a Block of Code simple thr state buffer inference include systemc h SC_MODULE tristate_exl sc_in lt bool gt control sc_in lt sc_logic gt data sc_out lt sc_logic gt ts_out Method for three state driver void tristate_fen if control read ts_out write data read Jelsef ts_out write 2 Constructor SC_CTOR tristate_exl SC_METHOD tristate_fcn sensitive lt lt control lt lt data RTL Coding Guidelines Three State Inference 4 31 Figure 4 22 Schematic of a Simple Three State Driver control data ts_out Example 4 23 is a different instance of three state inference In this case the output is computed and RTL synthesis infers a single three state driver Figure 4 23 shows the schematic the code generates Example 4 23 Inferring One Three State Driver simple thr state buffer inference include systemc h SC_MODULE tristate_ex2 sc_in lt bool gt in_sela in_selb sc_in lt sc_logic gt in_a in_b sc_out lt sc_logic gt out IL Method for single thr state driver void tristate_fen out_l write Z
67. ructs The C and C constructs listed in Table 3 2 are not supported for RTL synthesis Table 3 2 Nonsynthesizable C C Constructs Category Construct Comment Corrective action Local class Not allowed Replace declaration Nested class Not allowed Replace declaration Derived class Only SystemC modules and Replace processes supported Dynamic malloc malloc free new new Use static memory storage free new delete and delete are not allocation allocation new supported The new construct is delete allowed only to instantiate a delete module to create hierarchy Exception try catch Not allowed Comment out handling throw Recursive Not allowed Replace with function call iteration Function Not allowed except the classes Replace with unique overloading overloaded by SystemC function calls C built in Math library I O library file I O Replace with functions and similar built in C synthesizable Virtual function functions not allowed Not allowed Using the Synthesizable Subset Converting to a Synthesizable Subset 3 4 functions or remove Replace with a nonvirtual function Table 3 2 Nonsynthesizable C C Constructs Continued Category Construct Comment Corrective action Inheritance Not allowed Create an independent SC_MODULE Multiple Not allowed Create independent inheritance modules Member access public Allowed in code but ignored for control protected
68. s Set 05 4 29 D Latch With an Asynchronous Reset 4 30 Three State Inference 2 0 0 0 es 4 31 Simple Three State Inference 000 ee eee 4 31 Three State Driver for Bus 4 33 Registered Three State Divers 4 34 State Wachines lt lt x 2s2 255 03 646 212 nn 4 38 State Machine With a Common Computation Process 4 40 State Machine With Separate Computation Processes 4 42 Moore State Machine 4 44 5 Behavioral Modeling and Synthesis Comparing RTL and Behavioral Modeling 5 2 What is Behavioral Synthesis 00 0c eee eee ees 5 3 Lawl ale lene sete ea Grane we eee gee E eee sa 5 4 SCHCOUING sa see ees be ee arte 5 5 Allocating HardW re 2 026 2224 44 2 5 7 Creating the Data Path and Finite State Machine 5 8 Choosing the Right Abstraction for Synthesis 5 9 Identifying Attributes Suitable for RTL Synthesis 5 9 Identifying Attributes Suitable for Behavioral Synthesis 5 10 Benefits of Behavioral Synthesis nnana nananana 5 11 RTL and Behavioral Coding Style Examples 5 12 RTL Coding Style re 5 12 Behavioral Coding Style 5 16 Getting More Information About Behavioral Synthesis 5 18 vii viii Preface This preface includes the following sections e About This Guide e SystemC Training e Information About Synopsys SystemC Synthesis Products About Th
69. sensitive_pos lt lt clock void dffl do_dff_pos out_g write in_data read Figure 4 1 Inferred Positive Edge Triggered Flip Flop in_data out_q cloc RTL Coding Guidelines Register Inference 4 3 D Flip Flop With an Active High Asynchronous Set or Reset To infer a D flip flop with an asynchronous set or reset include edge expressions for the clock and the asynchronous signals in the sensitivity list of the SC_METHOD process constructor Specify the asynchronous signal conditions with an if statement in the SC_METHOD process definition Example 4 2 shows a typical asynchronous specification Specify the asynchronous branch conditions before you specify the synchronous branch conditions Example 4 2 is a the SystemC description for a D flip flop with an active high asynchronous reset Figure 4 2 shows the inferred flip flop Example 4 2 D Flip Flop With an Active High Asynchronous Reset Rising edge triggered DFF include systemc h SC_MODULE dff3 sc_in lt bool gt in_data reset sc_out lt bool gt out oO sc_in lt bool gt clock clock port void da dff pos OD Constructor SC_CTOR dff3 SC_METHOD do_dff_pos sensitive_pos lt lt clock lt lt reset void dff3 do_dff_pos if reset read out_g write 0 jelse RTL Coding Guidelines Register Inference 4 4 out_g write in_data read Figure 4 2 D Flip Flop With a
70. synthesis All member access is specifiers private public friend Accessing struct gt operator Not allowed except for module Replace with access members with instantiation using the period the gt operator operator Static member Not allowed Replace with nonstatic member variable Dereference and amp Not allowed Replace operator operators dereferencing with array accessing for loop comma operator The comma operator is not Remove the comma operator Unbounded loop Out of bound array access Operator overloading allowed in a for loop definition Not allowed Not allowed Not allowed except the classes overloaded by SystemC operators Replace with a bounded loop such as a for loop Replace with in bound array access Replace overloading with unique function calls Using the Synthesizable Subset Converting to a Synthesizable Subset 3 5 Table 3 2 Nonsynthesizable C C Constructs Continued Category Construct Comment Corrective action Operator sizeof sizeof Not allowed Determine size statically for use in synthesis Pointer u Pointers are allowed only in Replace all other hierarchical modules to pointers with access instantiate other modules to array elements or individual elements Pointer type Not allowed Do not use pointers conversions Use explicit variable reference this pointer this Not allowed Replace Reference C amp Allowed only for p
71. t clock RTL Coding Guidelines Register Inference 4 19 Figure 4 12 Avoiding Latch Inference by Adding Else Clause clock na Pota You can also avoid latch inference by assigning a default value to the output port Example 4 13 shows setting a default value to avoid the latch inferred by the if statement in Example 4 10 and Figure 4 13 shows the resulting schematic Example 4 13 Setting a Default Value to Avoid Latch Inference include systemc h SC_MODULE d_latchl sc_in lt bool gt in_data sc_in lt bool gt clock sc_out lt bool gt out o Method process void d_latch_fen out_q write 1 set a default if clock read out_g write in_data read Constructor SC_CTOR d_latchl SC_METHOD d_latch_fcn sensitive lt lt in_data lt lt clock Figure 4 13 Avoiding Latch Inference by a Default Value clock out_q In_data RTL Coding Guidelines Register Inference 4 20 Inferring a Latch From a Switch Statement Example 4 14 shows a switch statement that infers D latches because the switch statement does not provide assignments to the out port for all possible values of the in_i input Figure 4 14 shows the inferred latches Example 4 14 Latch Inference From a switch Statement include systemc h SC_MODULE d_latch2 sc_in lt unsigned char gt in_i sc_out lt unsigned char gt out Method process void d_latch_fcen swit
72. t or reset at one time but not to both at the same time Example 4 4 Flip Flop With Asynchronous Set and Reset Rising edge triggered DFF include systemc h SC_MODULE dff4 sc_in lt bool gt in_data reset set sc_out lt bool gt out oO sc_in lt bool gt clock clock port void do_dff pos Constructor SC_CTOR dff4 SC_METHOD do_dff_pos sensitive_pos lt lt clock lt lt reset lt lt set void dff4 do_dff_pos if reset read out_g write 0 else if set read out_g write 1 jelse out_g write in_data read RTL Coding Guidelines Register Inference 4 7 Figure 4 4 Flip Flop With Asynchronous Set and Reset set in_data out_q clock reset D Flip Flop With Synchronous Set or Reset The previous examples illustrated how to infer a D flip flop with asynchronous controls one way to initialize or control the state of a sequential device You can also synchronously reset or set a flip flop If the target technology library does not have a D flip flop with a synchronous reset a D flip flop with synchronous reset logic as the input to the D pin of the flip flop is inferred If the reset or set logic is not directly in front of the D pin of the flip flop initialization problems can occur during gate level simulation of the design To specify a synchronous set or reset input do not include it in the sensitivity list Describe the synchron
73. t otherwise else wait Notice that the behavioral description is much more compact and easier to understand compared to the RTL description Getting More Information About Behavioral Synthesis To find out more about SystemC behavioral synthesis contact your local Synopsys sales representative Behavioral Modeling and Synthesis Getting More Information About Behavioral Synthesis 5 18
74. tate logic Example 4 29 Moore State Machine ex_fsm_c h SC_MODULE ex_fsm_c SC SC SC SC in_clk clk in lt bool gt rst inputl input2 out lt bool gt a b signal lt state_t gt state void update_state SG CTOR ex_fsm_c SC_METHOD update_state sensitive_pos lt lt clk ex fsm_c cpp incl incl incl incl void LE ude lt iostream h gt ude systemc h ude fsm_types h ude ex_fsm_c h ex_fsm_c update_state rst read true b write 0 a write 0 state S0 else switch state case SO b write 0 if inputl read input2 read RTL Coding Guidelines State Machines 4 44 a write 1 else a write 0 if inputl read 1 state S1 break case Sl a write 0 b write 1 if input2 read 1 state S2 break case S2 a write 0 b write 0 state S0 break RTL Coding Guidelines State Machines 4 45 RTL Coding Guidelines State Machines 4 46 Behavioral Modeling and Synthesis In addition to the RTL modeling style described in the previous chapters you can use the behavioral modeling style to model synthesizable circuits at a higher level of abstraction than RTL This chapter provides a brief introduction to SystemC behavioral modeling and behavioral synthesis It contains the following sections e Comparing RTL and Behavioral Modeling
75. tatements and assign all variables in all branches Inferring a D Latch From an If Statement An if statement infers a D latch when there is no else clause as shown in Example 4 10 The SystemC code specifies a value for output out_q only when the clock has a logic 1 value and it does not specify a value when the clock has a logic 0 value As a result output out_q becomes a latched value Figure 4 10 shows the schematic of the inferred D latch Example 4 10 Latch Inference Using an if Statement include systemc h SC_MODULE d_latchl sc_in lt bool gt in_data sc_in lt bool gt clock sc_out lt bool gt out oO Method process void d_latch_fen if clock read out_g write in_data read RTL Coding Guidelines Register Inference 4 16 Constructor SC_CTOR d_latchl SC_METHOD d_latch_fcn sensitive lt lt in_data lt lt clock hi Figure 4 10 D Latch Inferred From an if Statement in_data out_q cloc Inferring an SR Latch SR latches are difficult to test so use them with caution If you use SR latches verify that the inputs are hazard free and do not generate glitches RTL synthesis does not ensure that the logic driving the inputs is hazard free Example 4 11 is the SystemC code that implements the truth table in Table 4 2 Figure 4 11 shows the inferred SR latch Output y is unstable when both inputs are at a logic 0 value so you need to include a check in the
76. te state_out read Creating SystemC Modules for RTL Synthesis Creating a Hierarchical RTL Module 2 32 switch state case 0 sample_tmp 0 acc 0 for int 1 0 i lt 15 i shift i 0 result write 0 output_data_ready write false break case 1 sample_tmp sample read acc sample_tmp coefs 0 acc shift 14 coefs 15 acc shift 13 coefs 14 acc shift 12 coefs 13 acc shift 11 coefs 12 output_data_ready write false break case 2 acc shift 10 coefs 11 acc shift 9 coefs 10 acc shift 83 coefs 9 acc shift 7 coefs 8 output_data_ready write false break case 3 acc shift 6 coefs 7 acc shift 5 coefs 6 acc shift 4 coefs 5 acc shift 3 coefs 4 output_data_ready write false break case 4 acc shift 2 coefs 3 acc shift 1 coefs 2 acc shift 0 coefs 1 for int i 14 i gt 0 i shift itl shift i hi shift 0 sample read result write acc Creating SystemC Modules for RTL Synthesis Creating a Hierarchical RTL Module 2 33 output_data_ready write true break case 5 This state waits for valid input output_data_ready write false break default output_data_ready write false result write 0 Creating SystemC Modules for RTL Synthesis Creating a Hierarchical RTL Module 2 34 Using the Synth
77. te Sensitivity Lists To eliminate the risk of pre and post synthesis simulation mismatches include all the inputs to the combinational logic process in the sensitivity list of the method process Example 2 3 shows an incomplete sensitivity list Example 2 3 Incomplete Sensitivity List method process void comb_proc out_x in_a amp in_b amp inc SC_CTOR comb_logic_complete Register method process SC_METHOD comb_proc sensitive lt lt in_a lt lt in_b missing in_c Defining an Edge Sensitive Process For sequential logic define a sensitivity list of the input ports and signals that trigger the process Use the sensitive_pos sensitive_neg or both the sensitive_pos and sensitive_neg methods to define the edge sensitive inputs that trigger the process Declare ports and the edge sensitive inputs as type sc_in lt bool gt You can define any number of sc_in lt bool gt inputs Creating SystemC Modules for RTL Synthesis Creating a Module 2 13 Define the sensitivity list by using either the function or the stream syntax Example 2 4 shows in bold an example of a stream type declaration for two inputs and a function type declaration for the clock input Example 2 4 Defining an Edge Sensitive Sensitivity List SC_MODULE my_module Ports sc_in lt int gt a sc_in lt bool gt b sc_in lt bool gt clock sc_out lt int gt x sc_out lt int gt y sc_in lt bool gt reset Internal s
78. the module multiple times Creating SystemC Modules for RTL Synthesis Defining Modules and Processes 2 3 Triggering Execution of a Process You define a sensitivity list that identifies which input ports and signals trigger execution of the code within a process You can define level sensitive inputs to specify combinational logic or edge sensitive inputs to specify sequential logic Reading and Writing Processes A process can read from and write to ports internal signals and internal variables Processes use signals to communicate with each other One process can cause another process to execute by assigning a new value to a signal that interconnects them Do not use data variables for communication between processes because the processes execute in random order and it can cause nondeterminism order dependencies during simulation Types of Processes SystemC provides three process types SC_METHOD SC_CTHREAD and SC_THREAD that execute whenever their sensitive inputs change For simulation you can use any of the process types For RTL synthesis you can use only the SC_METHOD process The SC_METHOD process is sensitive to either changes in signal values level sensitive or to particular transitions edges of the signal edge sensitive and executes when one of its sensitive inputs changes Creating SystemC Modules for RTL Synthesis Defining Modules and Processes 2 4 Creating a Module It is a recommended coding
79. ue to a variable the value on the right side is immediately transferred to the left side of the assignment statement Example 2 9 uses a variable assignment where the implementation assigns the value of data to rega and regb as the resulting schematic in Figure 2 5 indicates Note This example is only an illustration of variable assignment You can write the same behavior more efficiently by removing the rega_v and regb_v variables and writing the ports directly Creating SystemC Modules for RTL Synthesis Creating a Module 2 18 Example 2 9 Variable Assignment include systemc h SC_MODULE rtl_b sc_in lt bool gt clk sc_in lt bool gt data sc_out lt bool gt rega regb bool rega_v regb_v void reg_proc rega_v data read regb_v rega_v rega write rega_v regb write regb_v SC_CTOR rtl_b SC_METHOD reg_proc sensitive_pos lt lt clk Figure 2 5 Variable Assignment Schematic rega data reqb elki Creating SystemC Modules for RTL Synthesis Creating a Module 2 19 Creating a Module With a Single SC_METHOD Process Example 2 10 is a complete example of an RTL description of a count zeros circuit that contains one SC_METHOD process control_proc and two member functions legal and zeros The circuit determines in one cycle if an 8 bit value on the input port is valid no more than one sequence of zeros and how many zeros the value contains The circuit pro
80. ynthesis 3 12 Fixed and Arbitrary Precision Data Type Operators Table 3 5 lists the operators available for the SystemC sc_int and sc_uint fixed precision and sc_bigint and sc_biguint arbitrary precision integer data types Table 3 5 SystemC Integer Data Type Operators Operators Bitwise amp and or Asor and not Bitwise lt lt shift left and gt gt shift right Assignment amp and Equality Relational lt lt gt and gt Autoincrement and autodecrement Bit selection x Part selection range x y Concatenation x y Type conversion to_uint and to_int Note The reduction and_reduce or_reduce and xor_reduce operators are not supported for the fixed and arbitrary precision data types Using the Synthesizable Subset Modifying Data for Synthesis 3 13 Using Enumerated Data Types Systemc supports enumerated enum data types and interprets an enum data type the same was a C compiler interprets it Example 3 1 shows an enum definition Example 3 1 Enumerated Data Type enum command_t NONE RED GREEN YELLOW Using Aggregate Data Types To group data types into a convenient aggregate type define them as a Struct type similar to Example 3 2 You need to use all synthesizable data types in a struct for the struct to be synthesizable Example 3 2 Aggregate Data Type struct package sc_uint lt 8 gt comm
81. ypes can be used for RTL synthesis except the following types e Floating point types such as float and double e Fixed point types sc_fixed sc_ufixed sc_fix and sc_ufix e Access types such as pointers e File types such as FILE e O streams such as stdout and cout Using the Synthesizable Subset Modifying Data for Synthesis 3 8 Recommended Data Types for Synthesis For best synthesis use appropriate data types and bit widths so unnecessary hardware is not built during RTL synthesis The following are some general recommendations about data type selections e Fora single bit variable use the native C type bool e For variables with a width of 64 bits or less use sc_int or sc_uint data types Use sc_uint for all logic and unsigned arithmetic operations Use sc_int for signed arithmetic operations as well as for logic operations These types produce the fastest simulation runtimes of the SystemC types e For variables larger than 64 bits use sc_bigint or sc_biguint if you want to do arithmetic operations with these variables e Use sc_logic or sc_lv only when you need to model three state signals or buses When you use these data types avoid comparison with X and Z values in your synthesizable code because such comparisons are not synthesizable e Use native C integer types for loop counters e Use the native C data types with caution because their size is platform dependent For example on most platforms
82. ypically 32 bits or longer depending on the platform unsigned long An unsigned integer typically 32 bits or longer depending on the platform Using the Synthesizable Subset Modifying Data for Synthesis 3 10 Table 3 3 Synthesizable Data Types Continued SystemC and C type Description char 8 bits signed character platform dependent unsigned char 8 bits unsigned character platform dependent short A signed short integer typically 16 bits depending on the platform unsigned short An unsigned short integer typically 16 bits depending on the platform struct A user defined aggregate of synthesizable data types enum A user defined enumerated data type associated with an integer constant Using the Synthesizable Subset Modifying Data for Synthesis 3 11 Using SystemC Data Types Use the SystemC data type operators to access individual bits of a value Bit Vector Data Type Operators Table 3 4 lists the operators available for the SystemC sc_bv data type Table 3 4 SystemC Bit Vector Data Type Operators Operators Bitwise amp and or Asor and not Bitwise lt lt shift left and gt gt shift right Assignment amp and Equality Bit selection x Part selection range x y Concatenation x y Reduction and_reduce or_reduce and xor_reduce Type conversion to_uint and to_int Using the Synthesizable Subset Modifying Data for S
83. ystemC models to minimize the modification effort for synthesis You can use any SystemC or C construct for a testbench You do not need to restrict your code to the synthesizable subset in the testbench Using the Synthesizable Subset Converting to a Synthesizable Subset 3 2 Nonsynthesizable SystemC Constructs The SystemC constructs listed in Table 3 1 are not supported for RTL synthesis Table 3 1 Nonsynthesizable SystemC Constructs for RTL Synthesis Category Construct Comment Corrective action Thread process SC_THREAD Used for modeling a testbench but not supported for synthesis CTHREAD SC_CTHREAD Used for simulation and process modeling at the behavioral level Main function sc_main Used for simulation Clock sc_start Used for simulation Use only in generators sc_main Communication Global watching Local watching Synchronization Tracing sc_interface sc_port sc_mutex sc_fifo watching W_BEGIN W_END W_DO W_ESCAPE Master slave library of SystemC sc_trace sc_create trace_file Used for modeling communication Not supported for RTL synthesis Not supported Used for synchronization of events Creates waveforms of signals channels and variables for simulation Comment out for synthesis Comment out for synthesis Comment out for synthesis Using the Synthesizable Subset Converting to a Synthesizable Subset 3 3 Nonsynthesizable C C Const

Download Pdf Manuals

Related Search

Related Contents

User Manual - Lord Civil  TOTO Clean Dry High Speed Concealed Hand Dryer  USB-6008/6009 User Manual and Specifications  Navilock NL-6003P  e-PDR User Guide Employee Guide 4  Split York Cassete Supreme  Supervision System  Life Fitness TR91/95/97 User's Manual    Hamilton Beach 33464 User's Manual  

Copyright © All rights reserved. Failed to retrieve file