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DAQ 6711/6713/6715 User Manual

1. TTL Signal o DIO lt 0 3 gt 5V VW gt Switch ye DGND I O Connector 6711 6713 Device Figure 4 4 Digital 1 0 Connections Figure 4 4 shows DIO lt 0 3 gt configured for digital input and DIO lt 4 7 gt configured for digital output Digital input applications include receiving TTL signals and sensing external device states such as the switch state shown in Figure 4 4 Digital output applications include sending TTL signals and driving external devices such as the LED shown in Figure 4 4 The hardware up down control for general purpose counters 0 and 1 are connected onboard to DIO6 and DIO7 respectively Thus you can use DIO6 and DIO7 to control the general purpose counters The up down control signals are input only and do not affect the operation of the DIO lines 6711 6713 6715 User Manual 4 10 www ni com Chapter 4 Signal Connections Power Connections Two pins on the I O connector supply 5 V from the computer power supply through a self resetting fuse The fuse will reset automatically within a few seconds after the overcurrent condition is removed You can use these pins referenced to DGND to power external digital circuitry e Power rating 4 65 to 5 25 VDC at 1 A 0 75 A DAQCard 6723 VAN Caution Under no circumstances should you connect these 5 V power pins directly to analog or digital ground or to any other voltage source on the 671X d
2. y CH6 Amp CHS 12 CH6 12 Bit DAC Latch Amp i i i i y CH7 1 i i i CHO Latch CH1 Latch CH2 Latch CH3 Latch CH4 Latch CH5 Latch CH7 12 CH7 12 Bit DAC 7 Latch COGIGICIGIL Data Data TE DAC FIFO AO Control Calibration 24 DACs p Calibration A Mux ADC 1 0 Connector PFI Trigger Timing Digital 1 O 8 Generic Bu IS Interface DAQPad 6713 only 400 Mbps 1394 PHY NI Firephli Data f AO Control Calibration Control 1 D D Analog Output Bus 1 Timing Control 1 Interface erron EEPROM Register Control Decode 1 1 FPGA DMA IRQ IDAQ STC Bus Interface Data IRQ Address Counter Timing vo DAQ STC Digital YO Analog Input 1 RTSI Bus Timing Control Interface Note CH4 through CH7 on 6713 only PCI PXI 6711 6713 6715 User Manual Figure 3 1 6711 6713 Block Diagram 3 2 www ni com Chapter 3 Hardware Overview I O Connector Calibration DACs 24 Calibration Calibration 8 Mux ADC Control Data DAC Control AO Control FIFO Data DAC FIFO 1 1 Bus 1 1 Interface DAQ STC Calibration Data in Interface Control I 1 Data Control Analog O
3. Chapter 3 Hardware Overview The seven RTSI trigger lines on the RTSI bus provide a very flexible interconnection scheme for the 6711 6713 device sharing the RTSI bus These bidirectional lines can drive any of five timing signals onto the RTSI bus and can receive any of these timing signals This signal connection scheme is shown in Figure 3 4 Po RTSI Bus Connector 5 Trigger lt _ _ 2 7 7 fe Clock switch Ss DAQ STC UPDATE WFTRIG GPCTRO_SOURCE GPCTRO_GATE GPCTRO_OUT UISOURCE GPCTR1_SOURCE GPCTR1_GATE RTSI_OSC 20 MHz Figure 3 4 RTS Bus Signal Connection Refer to the Timing Connections section of Chapter 4 Signal Connections for a description of the signals National Instruments Corporation 6711 6713 6715 User Manual Signal Connections 1 0 Connector This chapter describes how to make input and output signal connections to your 671X device through the device I O connector PCI PXI 67 11 6713 DAQCard 6715 The I O connector for the 6711 6713 device has 68 pins that you can connect to 68 pin accessories with the SH68 68 EP or similar 68 pin shielded cable DAQPad 67 13 The DAQPad 6713 allows connection to all analog and some digital signals through BNC connectors You can access the remaining digital signals using the removable screw terminal block on the front panel Figure 4 1 shows the pin assignments
4. UI UISOURCE unipolar UPDATE V y VDC National Instruments Corporation G 9 Glossary terminal count the ending value of a counter gate hold time gate setup time gate pulse width output delay time total harmonic distortion the ratio of the total rms signal due to harmonic distortion to the overall rms signal in decibel or a percentage a temperature sensor created by joining two dissimilar metals The junction produces a small voltage as a function of the temperature trigger signal source clock period source pulse width transistor transistor logic update interval update interval counter clock signal a signal range that is always positive for example 0 to 10 V update signal volts volts direct current 6711 6713 6715 User Manual Glossary VI virtual instrument 1 a combination of hardware and or software elements typically used with a PC that has the functionality of a classic stand alone instrument 2 a LabVIEW software module VI which consists of a front panel user interface and a block diagram program Vin volts input high Vit volts input low Vin volts in Vin measured voltage Von volts output high VoL volts output low V ief reference voltage Viis volts root mean square WFTRIG waveform generation trigger signal 6711 6713 6715 User Manual G 10 www ni com Index Numbers 5 V signal description table 4 4 power connections 4 11 self resetting fu
5. externally generated by another PFI This output is set to tri state at startup 6711 6713 6715 User Manual 4 20 www ni com Chapter 4 Signal Connections Figure 4 15 shows the timing requirements for the GPCTR1_GATE signal Rising edge polarity 1 Falling edge polarity tw 10ns minimum Figure 4 15 GPCTR1_GATE Signal Timing in Edge Detection Mode GPCTR1_OUT Signal This signal is available only as an output on the GPCTR1_OUT pin The GPCTR1_OUT signal monitors the TC device general purpose counter 1 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to tri state at startup Figure 4 16 shows the timing requirements for the GPCTR1_OUT signal GPCTR1_SOURCE GPCTR1_OUT Pulse on TC GPCTR1_OUT Toggle output on TC Figure 4 16 GPCTR1_OUT Signal Timing National Instruments Corporation 4 21 6711 6713 6715 User Manual Chapter 4 Signal Connections GPCTR1_UP_DOWN Signal You can externally input this signal on the DIO7 pin and is not available as an output on the I O connector General purpose counter counts down when this pin is at a logic low and counts up at a logic high You can disable this input so that software can control the up down functionality and leave the DIO7 pin free for general use Figure 4 1
6. or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation Trademarks ComponentWorks CVI DAQCard DAQPad DAQ STC LabVIEW MITE National Instruments ni com NI DAQ NI PGIA PXI RTSI SCXI and VirtualBench are trademarks of National Instruments Corporation Product and company names mentioned herein are trademarks or trade names of their respective companies WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS 1 NATIONAL INSTRUMENTS PRODUCTS ARE NOT DESIGNED WITH COMPONENTS AND TESTING FOR A LEVEL OF RELIABILITY SUITABLE FOR USE IN OR IN CONNECTION WITH SURGICAL IMPLANTS OR AS CRITICAL COMPONENTS IN ANY LIFE SUPPORT SYSTEMS WHOSE FAILURE TO PERFORM CAN REASONABLY BE EXPECTED TO CAUSE SIGNIFICANT INJURY TO A HUMAN 2 IN ANY APPLICATION INCLUDING THE ABOVE RELIABILITY OF OPERATION OF THE SOFTWARE PRODUCTS CAN BE IMPAIRED BY ADVERSE FACTORS INCLUDING BUT NOT LIMITED TO FLUCTUATIONS IN ELECTRICAL POWER SUPPLY COMPUTER HARDWARE MALFUNCTIONS COMPUTER OPERATING SYSTEM SOFTWARE FITNESS FITNESS
7. 0 5 gt PXI Trigger lt 0 5 gt B16 A16 A17 A18 B18 C18 RTSI Trigger 6 PXI Star Trigger D17 RTSI Clock PXI Trigger 7 E16 Serial LBR 6 7 8 9 10 EIS A3 C3 D3 E3 Communication 11 12 A2 B2 What You Need to Get Started To set up and use the 671X device you will need the following Q Q for DAQCard 6715 Either the 6711 6713 or 6715 device 6711 6713 6715 User Manual LabVIEW for Windows LabWindows CVI for Windows ComponentWorks VirtualBench C language compiler Q Your computer National Instruments Corporation DAQPad 6713 NI DAQ driver for PC compatibles version 6 5 or higher 6 7 or higher One of the following software packages and documentation SH68 68 EP cable PCI PX1I CompactPCI 671 1 13 and 6711 6713 6715 User Manual Chapter 1 Introduction Unpacking Q SHC68 68EP cable DAQCard 6715 UL One of the following BNC 2110 signal connector block SCB 68 shielded terminal block CB 68LP terminal block The 671X device is shipped in an antistatic package to prevent electrostatic damage to the device Electrostatic discharge can damage several components on the device To avoid such damage in handling the device take the following precautions e Ground yourself using a grounding strap or by holding a grounded object e Touch the antistatic package to a metal part of your computer chassis before removing the device
8. 2 online problem solving and diagnostic resources C 1 software related resources C 2 WFTRIG signal input signal timing figure 4 14 output signal timing figure 4 15 timing connections 4 14 to 4 15 wiring considerations 4 23 Worldwide technical support C 2 6711 6713 6715 User Manual l 6 www ni com
9. 3 5 at 5at0 4 1 5 50 kQ pu Vec 0 4 PFI2 DI Vec 0 5 3 5 at 5at0 4 1 5 50 kQ pu Vec 0 4 PFI3 GPCTRI_SOURCE DIO Vec 0 5 3 5 at 5at0 4 1 5 50 kQ pu Vec 0 4 PFI4 GPCTR1_GATE DIO Vec 0 5 3 5 at 5at0 4 1 5 50 kQ pu Vec 0 4 GPCTR1_OUT DO 3 5 at 5at0 4 1 5 50 KQ pu Vec 0 4 6711 6713 6715 User Manual 4 6 www ni com Chapter 4 Signal Connections Table 4 2 1 0 Signal Summary for the 6711 6713 Device Continued Rise Time Signal Impedance Protection Sink ns Type and Input Volts Source mA Slew Signal Name Direction Output On Off mA at V at V Rate Bias PFIS UPDATE DIO Vec 0 5 3 5 at 5at0 4 1 5 50 kQ pu Vec 0 4 PFI6 WFTRIG DIO Vec 0 5 3 5 at 5at0 4 1 5 50 kQ pu Vec 0 4 PFI7 DI Vec 0 5 3 5 at 5at0 4 1 5 50 kQ pu Vec 0 4 PFI8 GPCTRO_SOURCE DIO Vec 0 5 3 5 at 5at0 4 1 5 50 kQ pu Vec 0 4 PFI9 GPCTRO_GATE DIO Vec 0 5 3 5 at 5at0 4 1 5 50 kQ pu Vec 0 4 GPCTRO_OUT DO 3 5 at 5at0 4 1 5 50 kQ pu Vec 0 4 FREQ_OUT DO 3 5 at 5at0 4 1 5 50 kQ pu Vec 0 4 1 The 5 V line on the connector of the DAQCard 6715 is fused at 0 75 A however the actual current available can be limited below this value by the host computer National Instruments recommends limiting current from this line to 250 mA AI Analog Input DIO Digital Input Output pu pull up AO Analog Output DO Digit
10. Manual Chapter 2 Installation and Configuration Device Configuration 6711 6713 6715 User Manual Due to the National Instruments standard architecture for data acquisition the PCI bus specification the IEEE 1394 1995 specification the PCMCIA PC Card specification and the 671X device is completely software configurable There are two types of configuration on the 671X device bus related and data acquisition related configuration The PCI PXI 671 1 6713 device is fully compatible with the industry standard PCI Local Bus Specification Revision 2 0 This specification allows the PCI system to automatically perform all bus related configurations and requires no user interaction Bus related configuration includes setting the device base memory address and interrupt channel Data acquisition related configuration includes such settings as analog output range reference selection and others You can modify these settings using NI DAQ C language API or application level software such as ComponentWorks LabVIEW LabWindows CVI and VirtualBench 2 4 www ni com Hardware Overview This chapter presents an overview of the hardware functions on your PCI PXI 67 11 6713 and DAQPad 6713 device Figure 3 1 shows a block diagram of the 6711 6713 device Figure 3 2 shows a block diagram of the 6715 device National Instruments Corporation 3 1 6711 6713 6715 User Manual Chapter 3 Hardware Overview
11. Output Channels 0 through 7 These pins supply the voltage output of the respective channel DGND Digital Ground This pin supplies the reference for the digital signals at the I O connector as well as the 5 VDC supply DIO lt 0 7 gt DGND Input or Digital I O signals DIO6 and 7 can control the up down Output signal of general purpose counters 0 and 1 respectively 5 V DGND Output 5 VDC Source These pins are fused for up to 1 A 0 75 A DAQCard 6715 of 5 V supply The fuse is self resetting EXTREF AOGND Input External Reference This is the external reference input for the analog output circuitry EXTSTROBE DGND Output External Strobe This output is used for controlling SCXI devices PFIO DGND Input PFIO As an input this is one of the Programmable Function Inputs PFIs PFI signals are explained in the Timing Connections section later in this chapter PFIO cannot be an output PFI1 DGND Input PFI1 As an input this is one of the PFIs PFI1 cannot be an output PFI2 DGND Input PFI2 As an input this is one of the PFIs PFI2 cannot be an output PFI3 GPCTR1_SOURCE DGND Input PFI3 Counter 1 Source As an input this is one of the PFIs Output As an output this is the GPCTR1_SOURCE signal This signal reflects the actual source connected to the general purpose counter 1 6711 6713 6715 User Manual 4 4 www ni com Chapter 4 Signal Connections Table 4 1 Signa
12. User Manual The final option for programming any National Instruments DAQ hardware is to write register level software Writing register level programming software can be very time consuming and inefficient and is not recommended for most users Even if you are an experienced register level programmer using NI DAQ or application software to program your National Instruments DAQ hardware is easier than and as flexible as register level programming and can save weeks of development time 1 6 www ni com Chapter 1 Introduction Optional Equipment National Instruments offers a variety of products to use with the 671X device including cables connector blocks and other accessories as follows e Cables and cable assemblies e Connector blocks shielded and unshielded 50 and 68 pin screw terminals e RTSI bus cables e Low channel count digital signal conditioning modules devices and accessories For more specific information about these products refer to your National Instruments catalogue or call the office nearest you Custom Cabling National Instruments offers cables and accessories for you to prototype your application or to use if you frequently change device interconnections If you want to develop your own cable however the following guidelines can be useful e Route the analog lines separately from the digital lines e When using a cable shield use separate shields for the analog and digital halves
13. appendix describes the comprehensive resources available to you in the Technical Support section of the National Instruments Web site and provides technical support telephone numbers for you to use if you have trouble connecting to our Web site or if you do not have internet access NI Web Support To provide you with immediate answers and solutions 24 hours a day 365 days a year National Instruments maintains extensive online technical support resources They are available to you at no cost are updated daily and can be found in the Technical Support section of our Web site at www ni com support Online Problem Solving and Diagnostic Resources e KnowledgeBase A searchable database containing thousands of frequently asked questions FAQs and their corresponding answers or solutions including special sections devoted to our newest products The database is updated daily in response to new customer experiences and feedback e Troubleshooting Wizards Step by step guides lead you through common problems and answer questions about our entire product line Wizards include screen shots that illustrate the steps being described and provide detailed information ranging from simple getting started instructions to advanced topics e Product Manuals A comprehensive searchable library of the latest editions of National Instruments hardware and software product manuals e Hardware Reference Database A searchable database containing bri
14. connections 4 23 signal summary table 4 7 frequently asked questions See questions and answers fuse self resetting 4 11 B 2 G general purpose timing signal connections 4 17 to 4 23 FREQ_OUT signal 4 23 GPCTRO_GATE signal 4 18 GPCTRO_OUT signal 4 18 to 4 19 GPCTRO_SOURCE signal 4 17 to 4 18 GPCTRO_UP_DOWN signal 4 19 GPCTR1_GATE signal 4 20 to 4 21 GPCTR1_OUT signal 4 21 GPCTR1_SOURCE signal 4 19 to 4 20 GPCTR1_UP_DOWN signal 4 22 to 4 23 questions about B 3 glitches 3 4 B 2 GPCTRO_GATE signal 4 18 GPCTRO_OUT signal description table 4 5 general purpose timing connections 4 18 to 4 19 signal summary table 4 7 GPCTRO_SOURCE signal 4 17 to 4 18 GPCTRO_UP_DOWN signal 4 19 GPCTR1_GATE signal 4 20 to 4 21 GPCTR1_OUT signal description table 4 5 general purpose timing connections 4 21 signal summary table 4 6 GPCTR1_SOURCE signal 4 19 to 4 20 GPCTR1_UP_DOWN signal 4 22 to 4 23 www ni com H hardware installation steps for 2 1 to 2 3 unpacking PCI PXI 671 1 6713 1 4 hardware overview analog output 3 4 reference selection 3 4 reglitch selection 3 4 block diagrams 6711 6713 3 2 6715 3 3 digital I O 3 4 timing signal routing 3 5 to 3 7 device and RTSI clocks 3 6 programmable function inputs 3 6 RTSI triggers 3 7 installation DAQCard 6715 2 3 DAQPad 67 13 2 3 PCI 6711 6713 2 2 to 2 3 PXI 6711 6713 2 1 to 2 2 questions about B 2 software 2 1 unpacking 671X dev
15. for the 68 pin I O connector on the 671X device Figure 4 2 shows the pin assignments for the 50 pin I O cable connector when used with the 671X device A signal description follows the connector pinouts National Instruments Corporation 4 1 6711 6713 6715 User Manual Chapter 4 Signal Connections AOGND 34 68 NC NC 33 67 AOGND AOGND 32 66 AOGND AOGND 31 65 DAC7OUT DAC6OUT 30 64 AOGND AOGND 29 63 AOGND DAC50UT 28 62 NC AOGND 27 61 AOGND AOGND 26 60 DAC4OUT DAC30UT 25 59 AOGND AOGND 24 58 AOGND AOGND 23 57 DAC2OUT DACOOUT 22 56 AOGND DAC1OUT 21 55 AOGND EXTREF 20 54 AOGND DIO4 19 53 DGND DGND 18 52 DIOO DIO1 17 51 DIO5 DIO6 16 50 DGND DGND 15 49 DIO2 5V 14 48 DIO7 DGND 13 47 DIO3 DGND 12 46 NC PFIO 11 45 EXTSTROBE PFI1 10 44 DGND DGND 9 43 PFI2 5 V 8 42 PFI3 GPCTR1_SOURCE DGND 7 41 PFl4 GPCTR1_GATE PFI5 UPDATE 6 40 GPCTR1_OUT PFI6 WFTRIG 5 39 DGND DGND 4 38 PFI7 PFI9 GPCTRO_GATE 3 37 PFI8 GPCTRO_SOURCE GPCTRO_OUT 2 36 DGND FREQ_OUT 1 35 DGND 1 No Connect on PCI PXI 6711 Figure 4 1 68 Pin I O Connector Pin Assignment for the 671X Device 6711 6713 6715 User Manual 4 2 www ni com Chapter 4 Signal Connections AOGND NC NC DAC7OUT1 DAC6OUT DAC50UT1 DAC40UT DAC30UT DAC2OUT NC DAC10O
16. however the actual current available can be limited below this value by the host computer National Instruments recommends limiting current from this line to 250 mA National Instruments Corporation 4 11 6711 6713 6715 User Manual Chapter 4 Signal Connections All digital timing connections are referenced to DGND This reference is demonstrated in Figure 4 5 which shows how to connect an external PFIO source and an external PFI2 source to two 671X device PFI pins PFIO PFl2 PFIO Source PFl2 Source DGND Z 1 O Connector 6711 6713 Device 6711 6713 6715 User Manual Figure 4 5 Timing I O Connections 4 12 www ni com Chapter 4 Signal Connections Programmable Function Input Connections There are a total of seven internal timing signals that you can externally control from the PFI pins The source for each of these signals is software selectable from any of the PFIs when you want external control This flexible routing scheme reduces the need to change the physical wiring to the device I O connector for different applications requiring alternative wiring You can individually enable six of the PFI pins to output a specific internal timing signal For example if you need the UPDATE signal as an output on the I O connector software can turn on the output driver for the PFI5 UPDATE pin Be careful not to driv
17. is not required to be held after the active edge of the source signal If you use an internal timebase clock you cannot synchronize the gate signal with the clock In this case gates applied close to a source edge take effect either on that source edge or on the next one This arrangement results in an uncertainty of one source clock period with respect to unsynchronized gating sources The OUT output timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated clock signals on the 671X device Figure 4 17 shows the OUT signal referenced to the rising edge of a source signal Any OUT signal state changes occur within 80 ns after the rising or falling edge of the source signal FREQ_OUT Signal This signal is available only as an output on the FREQ OUT pin The frequency generator for the 671X device outputs the FREQ_OUT pin The frequency generator is a 4 bit counter that can divide its input clock by the numbers 1 through 16 The input clock of the frequency generator is software selectable from the internal 10 MHz and 100 kHz timebases The output polarity is software selectable This output is set to tri state at startup Field Wiring Considerations The following recommendations apply for all signal connections to the 671X device e Separate the 671X device signal lines from high current or high voltage lines These lines can induce currents in or voltages on the 671X device signal line
18. memory for waveform generation Max update rate in FIFO mode will not change irrespective of the number of devices in the system 2 These results were measured using one PCI 671 1 6713 device with a 90 MHz Pentium machine These numbers may change when using more devices or when other CPU or bus activity is taking place 3 These results were measured using one DAQCard 6715 with a 266 MHz Pentium II machine These numbers may change when using more devices or when other CPU or bus activity is taking place 6711 6713 6715 User Manual Type of DAC 3 4 iss eierens FIFO buffer size A 2 Deita Double buffered multiplying 6711 6713 Serial multiplying 6715 staves 8 192 samples seve 16 384 samples estes 8 192 samples TEN DMA 6711 6713 only interrupts programmed I O asis Scatter gather 6711 6713 only www ni com Appendix A Specifications Accuracy Information Absolute Accuracy Nominal Range V of Reading Offset Temp Drift Positive Negative FS FS 24 Hours 90 Days 1 Year mV C 10 10 0 0177 0 0197 0 0219 5 933 0 0005 Absolute accuracy of Reading x Voltage Offset Temp Drift x Voltage Note Temp drift applies only if ambient is greater than 10 C of previous external calibration Transfer Characteristics Relative accuracy INL After calibration eee 0 3 LSB typ 0 5 LSB max Before calibration eeeeeeeeeees 4 LSB max
19. of the cable Failure to do so results in noise coupling into the analog signals from transient digital signals Mating connectors and a backshell kit for making custom 68 pin cables are available from National Instruments The following list gives recommended connectors that mate to the I O connector on the 6711 6713 device e Honda 68 position solder cup female connector e Honda backshell The following list gives recommended connectors that mate to the I O connector on the 6715 device e Amp 68 position VHDCI e Amp backshell National Instruments Corporation 1 7 6711 6713 6715 User Manual Installation and Configuration This chapter explains how to install and configure your 671X device Software Installation Install your software before you install the 671X device Refer to the appropriate release notes indicated below for specific instructions on the software installation sequence 1 Install your application software If you are using LabVIEW LabWindows CVI or other National Instruments application software packages refer to the appropriate release notes 2 Install the NI DAQ driver software Refer to your NI DAQ release notes and follow the instructions given there for your operating system and application software package You can now install your hardware Hardware Installation You can install the PCI PXI 6711 6713 device in any available PXI PCI expansion slot in your computer You can connect
20. polarity Rising edge ty 10ns minimum Figure 4 12 GPCTRO_GATE Signal Timing in Edge Detection Mode GPCTRO_OUT Signal This signal is available only as an output on the GPCTRO_OUT pin The GPCTRO_OUT signal reflects the terminal count TC of general purpose counter 0 You have two software selectable output options pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options This output is set to tri state at startup Figure 4 13 shows the timing of the GPCTRO_OUT signal 4 18 www ni com Chapter 4 Signal Connections GPCTRO_SOURCE GPCTRO_OUT Pulse on TC GPCTRO_OUT Toggle output on TC Figure 4 13 GPCTRO_OUT Signal Timing GPCTRO_UP_DOWN Signal You can externally input this signal on the DIO6 pin and is not available as an output on the I O connector The general purpose counter 0 will count down when this pin is at a logic low and count up when it is at a logic high You can disable this input so that software can control the up down functionality and leave the DIO6 pin free for general use GPCTR1_SOURCE Signal Any PFI pin can externally input the GPCTR1_SOURCE signal which is available as an output on the PFI3 GPCTR1_SOURCE pin As an input the GPCTR1_SOURCE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTR1_SOURCE and configure the polarity s
21. software for PC compatible computers unless otherwise noted Refers to all PC AT series computers with PCI bus unless otherwise noted SCXI stands for Signal Conditioning eXentsions for Instrumentation and is a National Instruments product line designed to perform front end signal conditioning for National instruments plug in DAQ devices National Instruments Documentation 6711 6713 6715 User Manual The 671X User Manual is one piece of the documentation set for your DAQ system You could have any of several types of documentation depending on the hardware and software in your system Use the documentation you have as follows e Getting Started with SCXI If you are using SCXI this is the first manual you should read It gives an overview of the SCXI system and contains the most commonly needed information for the modules chassis and software e Your SCXI hardware user manuals If you are using SCX read these manuals next for detailed information about signal connections and module configuration They also explain in greater detail how the module works and contain application hints e Your DAQ hardware documentation This documentation has detailed information about the DAQ hardware that plugs into or is connected to your computer Use this documentation for hardware installation and configuration instructions specification information about your DAQ hardware and application hints e Software documentation You may hav
22. the DAQPad 6713 to any available 1394 port on your PC or another 1394 device You can install the DAQCard 6715 in any available 5 V PC Card slot in your computer However to achieve best noise performance leave as much room as possible between the 671X device and other devices and hardware The following are general installation instructions but consult your computer user manual or technical reference manual for specific instructions and warnings PXI 6711 6713 You can install the PXI 671 1 6713 in any available PXI slot in your PXI or CompactPCI chassis National Instruments Corporation 2 1 6711 6713 6715 User Manual Chapter 2 Installation and Configuration B Note The PXI 6711 6713 has connections to several reserved lines on the CompactPCI J2 connector Before installing the PXI 6711 6713 in a CompactPCI system that uses J2 connector lines for a purpose other than PXI see Using PXI with CompactPCI in Chapter 1 Introduction 7 8 Turn off and unplug your PXI or CompactPCI chassis Choose an unused PXI or CompactPCI peripheral slot For maximum performance install the PXI 6711 6713 in a slot that supports bus arbitration or bus master cards The PXI 6711 6713 contains onboard bus master DMA logic that can operate only in such a slot If you choose a slot that does not support bus masters you will have to disable the onboard DMA controller using your software PXI compliant chassis must have bus arbitration for all slot
23. to 4 21 GPCTR1_OUT signal 4 21 GPCTR1_SOURCE signal 4 19 to 4 20 GPCTR1_UP_DOWN signal 4 22 to 4 23 I O connector 4 1 to 4 7 exceeding maximum ratings warning 4 4 www ni com T O signal summary table 4 6 to 4 7 pin assignments figures 4 2 to 4 3 signal descriptions table 4 4 to 4 5 power connections 4 11 programmable function input connections 4 13 timing connections 4 11 to 4 23 waveform generation timing connections 4 14 to 4 17 UISOURCE signal 4 16 to 4 17 UPDATE signal 4 15 to 4 16 WFTRIG signal 4 14 to 4 15 software installation 2 1 software programming choices 1 4 to 1 6 National Instruments application software 1 4 to 1 5 NI DAQ driver software 1 5 to 1 6 register level programming 1 6 software related resources C 2 specifications analog output A 1 to A 5 accuracy information A 3 dynamic characteristics A 4 to A 5 external reference input A 4 output characteristics A 1 to A 2 stability A 5 transfer characteristics A 3 voltage output A 4 bus interface A 7 digital I O A 5 to A 6 digital trigger A 7 environment A 8 physical A 8 power requirements A 8 RTSI and PXI trigger lines A 7 timing I O A 6 to A 7 stability specifications A 5 National Instruments Corporation l 5 Index T technical support resources C 1 to C 2 theory of operation See hardware overview timing connections 4 11 to 4 23 general purpose timing signal connections 4 17 to 4 23 FREQ_OU
24. wall outlet and the DAQPad device 3 Flip the rocker switch to turn on the power for the DAQPad 6713 Your computer should detect your DAQPad device immediately and when the computer recognizes your DAQPad device the COM LED on the front panel will blink once The power LED should be on 4 Configure your DAQPad device and any accessories with the Measurement amp Automation Explorer DAQCard 6715 1 Insert the DAQCard and attach the I O cable The DAQCard has two connectors a 68 pin PCMCIA bus connector on one end and a 68 pin T O connector on the other end Insert the PCMCIA bus connector into any available Type If PCMCIA slot until the connector is seated firmly The DAQCard and I O cable are both keyed so that you can attach the cable only one way ays Note Becareful not to put strain on the I O cable when inserting it into and removing it from the DAQCard Always grasp the cable by the connector you are plugging or unplugging Never pull directly on the I O cable to unplug it from the DAQCard You can connect your DAQCard to 68 and 50 pin accessories You can use either a 68 pin female cable to plug into the PSHR68 68M with your DAQCard or a 50 pin male cable and the PSHR68 68M and SH6850 with your DAQCard 2 Tighten the jackscrews to secure the cable to the DAQCard 3 Configure your DAQPad device and any accessories with Measurement amp Automation Explorer National Instruments Corporation 2 3 6711 6713 6715 User
25. warranted against defects in materials and workmanship for a period of one year from the date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this document is accurate The document has been carefully reviewed for technical accuracy In the event that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent edi
26. 671X device General Information What is the 671X device The 671X device is a switchless and jumperless analog output device that uses the DAQ STC for timing What is the DAQ STC The DAQ STC is the system timing control application specific integrated circuit ASIC designed by National Instruments and is the backbone of the 6711 6713 device The DAQ STC contains seven 24 bit counters and three 16 bit counters The counters are divided into the following three groups e Analog input two 24 bit two 16 bit counters not used on 6711 6713 e Analog output three 24 bit one 16 bit counters e General purpose counter timer functions two 24 bit counters The groups can be configured independently with timing resolutions of 50 ns or 10 us With the DAQ STC you can interconnect a wide variety of internal timing signals to other internal blocks The interconnection scheme is quite flexible and completely software configurable New capabilities such as buffered pulse generation and seamlessly changing the sampling rate are possible What does update rate mean to me It means that this is the fastest you can output data from your device and still achieve accurate results The 6711 6713 device has an update rate of 1 MS s at up to 4 channels and the DAQCard 6715 device has an update rate of 1 MS s on 1 channel and 480 kS s on all eight channels simultaneously However the outputs of the DAQCard 6715 settle to within 1 2 LSB of
27. 7 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the 6711 6713 device OUT output signals V 1 i o V gt tgsu lt gt ton lt GATE IH X i b m tow Lt tout V i OUT OH i V 1 OL Source Clock Period tes 50 ns minimum Source Pulse Width ten 23 ns minimum Gate Setup Time tgsu 10 ns minimum Gate Hold Time tgh Ons minimum Gate Pulse Width tow 10 ns minimum Output Delay Time tout 80 ns maximum 6711 6713 6715 User Manual Figure 4 17 GPCTR Timing Summary The GATE and OUT signal transitions shown in Figure 4 17 are referenced to the rising edge of the SOURCE signal This timing diagram assumes that the counters are programmed to count rising edges The same timing diagram but with the source signal inverted and referenced to the falling edge of the source signal would apply when the counter is programmed to count falling edges The GATE input timing parameters are referenced to the signal at the SOURCE input or to one of the internally generated signals on the 6711 6713 device Figure 4 17 shows the GATE signal referenced to the rising edge of a source signal The gate must be valid either high or low for at least 10 ns before the rising or falling edge of a source signal for the gate to take effect at that source edge as shown by t and tgn in 4 22 www ni com Chapter 4 Signal Connections Figure 4 17 The gate signal
28. DAQ 6711 6713 6715 User Manual Analog Voltage Output Device for PCI PXI CompactPCl PCMCIA 1394 Bus Computers Qr NATIONAL December 1999 Edition gt INSTRUMENTS Part Number 322080B 01 Worldwide Technical Support and Product Information www ni com National Instruments Corporate Headquarters 11500 North Mopac Expressway Austin Texas 78759 3504 USA Tel 512 7940100 Worldwide Offices Australia 03 9879 5166 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Brazil 011 284 5011 Canada Calgary 403 274 9391 Canada Ontario 905 785 0085 Canada Qu bec 514 694 8521 China 0755 3904939 Denmark 45 76 26 00 Finland 09 725 725 11 France 01 48 14 24 24 Germany 089 741 31 30 Greece 30 1 42 96 427 Hong Kong 2645 3186 India 91805275406 Israel 03 6120092 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico D F 5 280 7625 Mexico Monterrey 8 357 7695 Netherlands 0348 433466 Norway 32 27 73 00 Poland 48 22 528 94 06 Portugal 351 1 726 9011 Singapore 2265886 Spain 91 640 0085 Sweden 08 587 895 00 Switzerland 056 200 51 51 Taiwan 02 2377 1200 United Kingdom 01635 523545 For further support information see the Technical Support Resources appendix To comment on the documentation send e mail to techpubs ni com Copyright 1998 1999 National Instruments Corporation All rights reserved Important Information Warranty The PCI 6711 PCI 6713 PXI 6711 PXI 6713 DAQPad 6713 and DAQCard 6715 devices are
29. DNL After calibration eee 0 3 LSB typ 1 0 LSB max Before calibration eeseeeeeeees 3 LSB max MOMNOtonicity 0 ce eeeeceeeeeeeeecsecenceceeeeees 12 bits guaranteed after calibration Offset error After calibration eee 1 0 mV typ 5 9 mV max Before calibration cccccseeeeeeeee 200 mV max Gain error relative to internal reference After calibration cee 0 01 of output max Before calibration 0 00 0 5 of output max Gain error relative to external reference 0 to 0 5 of output max not adjustable National Instruments Corporation A 3 6711 6713 6715 User Manual Appendix A Specifications Voltage Output RANGES nne an eE S A 10 V EXTREF Output coupling sseseeeessseeeesererrererrereeeee DC Output impedance eens 0 1 Q max Current drive ccccccccccceeesssecececessaeeceees 5 mA max total not to exceed 20 mA for all 8 outputs combined DAQCard 6715 Output stability 00 eects Any passive load up to 1500 pF Protection n mnano ii Short circuit to ground Power on state seeesseeeeeeeeeeeeerereeeerree OV External Reference Input Rangesiicci ein etein a 11 V Overvoltage protection 0 0 eee 25 V powered on 15 V powered off Input impedance 0 eee cee eeeeeeeeeeee 10 KQ Bandwidth 3 dB 1 MHz Dynamic Characteristics Slew rat e inini 20 V us Noise OPLTIGT AS eare nene 200 UV ms DC to 1 MHz DAQCard 6715 oo eeeeeeeeeeee 400 uVi
30. H SYSTEM OR APPLICATION Contents About This Manual Conventions Used in This Manual cceesesscecereecseceeeecesecesaeceececereeeneeeeeeeaeeeseeceneees ix National Instruments Documentation cessceececseeeeceesecesecesceceseecsaeeeeeeeseeeeneceseee X Related Doc ment tion ceee ereen aea E E EN E xi Chapter 1 Introduction About the 671 X DeVICeS 5 2 feiss i a e A RRE 1 1 Using PXI with CompactPCl eee cece cseseecseessececeseeseceseeseceeeeseseneseeecaeesaesaeeaesaees 1 2 What You Need to Get Started oreas n e e i ea 1 3 Unpacking 52 sh e eat eh cer a eee HAAR A AERA rhe Reva eh heh ee 1 4 Software Programming Choices 20 00 eee eseeeceseeeeceeceeeeeeeeeeecaeeseecaecsaecaeceaeesesnseeeeneeeaes 1 4 National Instruments Application Software 0 eee eeeeceseeeeceeeeeeeeseeeeeees 1 4 NI DAQ Driver Software enren e e Taha ea ens 1 5 Register Level Programming ssseesssseeessstesssresesrssrsresrrresreersreerrsenresrererresere 1 6 Optional Equipment ni sesir joasbessnegh steeds getsecee sees cspeesssededassbshsssssotvens senstesees sees 1 7 Custom Cabling ssri eree er cb ieee oie eet notes haee lade digs outa eee tees 1 7 Chapter 2 Installation and Configuration Software Installation s2 ccc s 33 oso sielses ee Saha ea ea Es 2 1 Hardware Ins tallation ws s ccscesccssvcseetetdawccevte aise ucbiod sen nentenet A E EARS 2 1 Device Configuration eee ceceseecesseeeceeeeeecseeesecseesaecseceaecsecsseeesns
31. Manual Appendix A Specifications Power Requirement PCI PXI 6711 5 VDE 45 ws ccccstices deed cine Power available at I O connector PCI PX1 6713 0 80 A typ 1 0 A max 4 65 to 5 25 VDC at 1 A 5 VDE 45 arnein a 1 25 A typ 1 5 A max Power available at I O connector 4 65 to 5 25 VDC at 1 A DAQPad 6713 ooo eeceeeesecseceteceeeeteeereee 14 W typ 20 W max internal DA QCard 67 15 v ccssccescecccecsecssessseetssentes dissipation add up to 1 A at 5 VDC available at the I O connection 160 mA typ 250 mA max plus any current used from the I O connector Physical Dimensions not including connectors PCT 6711 6713 reee dees cxis ths 17 5 by 10 7 cm 6 87 by 4 2 in PXI 671 1 6713 prieina 16 by 10 cm 6 3 by 3 9 in DAQPad 6713 oeiee 30 5 by 24 4 by 4 45 cm 12 by 10 by 1 75 in DAQCard 6715 ooeec Type II PC Card T O connector PCI PXI 671 1 6713 oo eee 68 pin male SCSI I type DAQPad 67 l3 ceci BNC s for analog I O and screw terminals for digital and counter I O DAQCard 6715 Loeser 68 pin female Honda connector Environment Operating temperature eseeseeeee eese Storage temperature 0 eee Relative humidity 0 0 0 ee eeeeeeeeeeeeeee 6711 6713 6715 User Manual A 8 0 to 50 C 55 to 150 C 5 to 90 noncondensing www ni com Common Questions This appendix contains a list of commonly asked questions and their answers relating to usage and special features of your
32. OF COMPILERS AND DEVELOPMENT SOFTWARE USED TO DEVELOP AN APPLICATION INSTALLATION ERRORS SOFTWARE AND HARDWARE COMPATIBILITY PROBLEMS MALFUNCTIONS OR FAILURES OF ELECTRONIC MONITORING OR CONTROL DEVICES TRANSIENT FAILURES OF ELECTRONIC SYSTEMS HARDWARE AND OR SOFTWARE UNANTICIPATED USES OR MISUSES OR ERRORS ON THE PART OF THE USER OR APPLICATIONS DESIGNER ADVERSE FACTORS SUCH AS THESE ARE HEREAFTER COLLECTIVELY TERMED SYSTEM FAILURES ANY APPLICATION WHERE A SYSTEM FAILURE WOULD CREATE A RISK OF HARM TO PROPERTY OR PERSONS INCLUDING THE RISK OF BODILY INJURY AND DEATH SHOULD NOT BE RELIANT SOLELY UPON ONE FORM OF ELECTRONIC SYSTEM DUE TO THE RISK OF SYSTEM FAILURE TO AVOID DAMAGE INJURY OR DEATH THE USER OR APPLICATION DESIGNER MUST TAKE REASONABLY PRUDENT STEPS TO PROTECT AGAINST SYSTEM FAILURES INCLUDING BUT NOT LIMITED TO BACK UP OR SHUT DOWN MECHANISMS BECAUSE EACH END USER SYSTEM IS CUSTOMIZED AND DIFFERS FROM NATIONAL INSTRUMENTS TESTING PLATFORMS AND BECAUSE A USER OR APPLICATION DESIGNER MAY USE NATIONAL INSTRUMENTS PRODUCTS IN COMBINATION WITH OTHER PRODUCTS IN A MANNER NOT EVALUATED OR CONTEMPLATED BY NATIONAL INSTRUMENTS THE USER OR APPLICATION DESIGNER IS ULTIMATELY RESPONSIBLE FOR VERIFYING AND VALIDATING THE SUITABILITY OF NATIONAL INSTRUMENTS PRODUCTS WHENEVER NATIONAL INSTRUMENTS PRODUCTS ARE INCORPORATED IN A SYSTEM OR APPLICATION INCLUDING WITHOUT LIMITATION THE APPROPRIATE DESIGN PROCESS AND SAFETY LEVEL OF SUC
33. T signal 4 23 GPCTRO_GATE signal 4 18 GPCTRO_OUT signal 4 18 to 4 19 GPCTRO_SOURCE signal 4 17 to 4 18 GPCTRO_UP_DOWN signal 4 19 GPCTR1_GATE signal 4 20 to 4 21 GPCTR1_OUT signal 4 21 GPCTR1_SOURCE signal 4 19 to 4 20 GPCTR1_UP_DOWN signal 4 22 to 4 23 overview 4 11 to 4 12 programmable function input connections 4 13 questions about B 2 to B 3 timing I O connections figure 4 12 waveform generation timing connections 4 14 to 4 17 UISOURCE signal 4 16 to 4 17 UPDATE signal 4 15 to 4 16 WFTRIG signal 4 14 to 4 15 timing I O specifications A 6 to A 7 timing signal routing 3 5 to 3 7 device and RTSI clocks 3 6 internal timing signals 3 5 programmable function inputs 3 6 RTSI triggers 3 7 UPDATE signal routing figure 3 5 transfer characteristic specifications A 3 triggers digital trigger specifications A 7 questions about B 2 to B 3 6711 6713 6715 User Manual Index U UISOURCE signal 4 16 to 4 17 unpacking 671X devices 1 4 UPDATE signal input signal timing figure 4 15 output signal timing figure 4 16 signal routing 3 5 timing connections 4 15 to 4 16 V VCC signal table 4 6 VirtualBench software 1 5 voltage output specifications A 4 W waveform generation questions about B 2 waveform generation timing connections 4 14 to 4 17 UISOURCE signal 4 16 to 4 17 UPDATE signal 4 15 to 4 16 WFTRIG signal 4 14 to 4 15 Web support from National Instruments C 1 to C
34. UPDATE signal reflects the actual update pulse that is connected to the DACs This is true even if the updates are externally generated by another PFI The output is an active low pulse with a pulse width of 50 to 75 ns This output is set to tri state at startup Figures 4 8 and 4 9 show the input and output timing requirements for the UPDATE signal Rising edge polarity Falling edge polarity tw 10ns minimum Figure 4 8 UPDATE Input Signal Timing National Instruments Corporation 4 15 6711 6713 6715 User Manual Chapter 4 Signal Connections ty 50 75 ns Figure 4 9 UPDATE Output Signal Timing The DACs are updated within 100 ns of the leading edge Separate the UPDATE pulses with enough time that new data can be written to the DAC latches The UI counter for the 67 LX device normally generates the UPDATE signal unless you select some external source The UI counter is started by the WFTRIG signal and can be stopped by software or the internal Buffer Counter D A conversions generated by either an internal or external UPDATE signal do not occur when gated by the software command register gate UISOURCE Signal Any PFI pin can externally input the UISOURCE signal which is not available as an output on the I O connector The UI counter uses the UISOURCE signal as a clock to time the generation of the UPDATE signal You must configure the PFI pin you select as the
35. UT AOGND DIOO DIO1 DIO2 DIO3 DGND 5 V EXTSTROBE PFI1 TRIG2 PFI3 GPCTR1_SOURCE GPCTR1_OUT PFI6 WFTRIG PFI8 GPCTRO_SOURCE GPCTRO_OUT 1No Connect on PCI PXI 6711 Ni cn wo 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 AOGND AOGND AOGND AOGND AOGND AOGND AOGND AOGND AOGND DACOOUT EXTREF DGND DIO4 DIO5 DIO6 DIO7 5 V SCANCLK PFIO TRIG1 PFI2 CONVERT PFI4 GPCTR1_GATE PFI5 UPDATE PFI7 STARTSCAN PFI9 GPCTRO_GATE FREQ_OUT National Instruments Corporation Figure 4 2 50 Pin I O Connector Pin Assignment for the 671X Device When Using the SH68 50 Cable 4 3 6711 6713 6715 User Manual Chapter 4 Signal Connections Caution Connections that exceed any of the maximum ratings of input or output signals A on the 671X device can damage the 671X device and the computer Maximum input ratings for each signal are given in the Protection column of Table 4 2 National Instruments is not liable for any damages resulting from such signal connections 1 0 Connector Signal Descriptions Table 4 1 Signal Descriptions for I O Connector Pins Signal Name Reference Direction Description AOGND Analog Output Ground The analog output voltages are referenced to this node DAC lt 0 7 gt OUT AOGND Output Analog
36. ack your 671X device About the 671X Devices Thank you for buying a National Instruments 671X device Your 671X device is a completely Plug and Play analog output digital and timing I O device for PXI PCI CompactPCI 1394 or PCMCIA PC Card bus The 671X device features a 12 bit digital to analog converter DAC per channel with update rates up to 1 MS s channel for voltage outputs eight lines of TTL compatible digital I O and two 24 bit counter timers for timing I O The 6711 device features four voltage output channels while the 6713 and 6715 devices feature eight voltage output channels Because the 671X device has no DIP switches jumpers or potentiometers it is easily software configured and calibrated The 6711 6713 device is a completely switchless and jumperless data acquisition DAQ device for the PXI PCI CompactPCI or 1394 bus This feature is made possible by the National Instruments MITE bus interface chip that connects the device to the PCI I O bus The MITE implements the PCI Local Bus Specification so that the interrupts and base memory addresses are all software configured The 6715 device is acompletely switchless and jumperless data acquisition DAQ device for the PCMCIA PC Card bus and is Plug and Play software configurable The 671X device uses the National Instruments DAQ STC system timing controller for time related functions The DAQ STC consists of three timing groups that control analog input analog o
37. al Output The tolerance on the 50 KQ pull up and pull down resistors is very large Actual value may range between 17 and 100 KQ Analog Output Signal Connections The analog output signals are DAC lt 0 7 gt OUT AOGND and EXTREF DACOOUT is the voltage output signal for analog output channel 0 EXTREF is the external reference input for all analog output channels You can use this input to reduce the voltage swing on the DAC outputs while preserving the dynamic range For example with internal reference the minimum change LSB on a voltage output is 20V _ 498 mV 4096 National Instruments Corporation 4 7 6711 6713 6715 User Manual Chapter 4 Signal Connections 6711 6713 6715 User Manual For an external reference at 5 V you can output 5 V with the LSB ona voltage output reduced to 2 44 mV This gives you a higher resolution at lower voltage You must configure each analog output channel individually for external reference selection in order for the signal applied at the external reference input to be used by that channel If you do not specify an external reference the channel will use the internal reference Analog output configuration options are explained in the Analog Output section in Chapter 3 Hardware Overview The following ranges and ratings apply to the EXTREF input e Usable input voltage range 11 V peak with respect to AOGND e Absolute maximum ratings 15 V peak with respect to AOGND AOGND is th
38. all measurements are made with respect to a common NRSE measurement system reference but the voltage at this reference can vary with respect to the measurement system ground G 6 www ni com OUT PCI PFI PFI3 GPCTRI1_ SOURCE PFI4 GPCTR1_GATE PFI5 UPDATE PFI6 WFTRIG PFI8 GPCTRO_ SOURCE PFI9 GPCTRO_GATE PGIA port ppm pu rms National Instruments Corporation G 7 Glossary output pin a counter output pin where the counter can generate various TTL pulse waveforms Peripheral Component Interconnect a high performance expansion bus architecture originally developed by Intel to replace ISA and EISA It is achieving widespread acceptance as a standard for PCs and work stations it offers a theoretical maximum transfer rate of 132 MB s Programmable Function Input PFI3 general purpose counter source PFI4 general purpose counter 1 gate PFI5 update PFI6 waveform trigger PFI8 general purpose counter 0 source PFI9 general purpose counter 0 gate Programmable Gain Instrumentation Amplifier 1 acommunications connection on a computer or a remote controller 2 a digital port consisting of four or eight lines of digital input and or output parts per million pull up random access memory root mean square 6711 6713 6715 User Manual Glossary RSE RTD RTSIbus RTSI_OSC S s S SCANCLK SCXI SE settling time signal conditioning SISOURCE SOURCE S s system no
39. ble to calibrate the analog output gain error when using an external reference In this case it is advisable to account for the nominal gain error of the analog output channel either in software or with external hardware See Appendix A Specifications for analog output gain error information National Instruments Corporation 5 3 6711 6713 6715 User Manual Specifications This appendix lists the specifications of your 671X device These specifications are typical at 25 C unless otherwise noted 6711 6713 Device Analog Output Output Characteristics Number of channels 00 0 0 8 voltage outputs 6713 6715 devices 4 voltage outputs 6711 devices Resolution vices cise nei 12 bits 1 in 4 096 National Instruments Corporation A 1 6711 6713 6715 User Manual Appendix A Specifications Max update rate Max Update Rate 6711 6713 Max Update Rate 6715 Number of Using Local Using Host PC Using Local Using Host PC Channels FIFO kS s Memory kS s FIFO kS s Memory kS s 1 1000 1000 1000 800 2 1000 1000 850 400 3 1000 1000 750 266 4 1000 1000 650 200 5 1000 1000 600 160 6 952 1000 550 133 7 833 869 510 114 8 740 769 480 100 1 These numbers apply to continuous waveform generation which allows for the time it takes to reset the FIFO to the beginning when cycling through it This additional time about 200 ns is not incurred when using host PC
40. channels for IEEE 1394 Firewire e DAQCard 6715 with eight AO channels two counters and eight DIO channels for PCMCIA PC Card Your PCI PXI 67 11 6713 DAQPad 6713 and DAQCard 6715 device is a multifunction analog output DIO and timing input output I O device for PCI PXI CompactPCI 1394 and PCMCIA PC Card buses Conventions Used in This Manual lt gt 3 A italic The following conventions are used in this manual Angle brackets enclose the name of a key on the keyboard for example lt option gt Angle brackets containing numbers separated by an ellipsis represent a range of values associated with a bit or signal name for example DIO lt 3 0 gt The indicates that the text following it applies to only to a specific PCI PXI CompactPCI DAQCard and 1394 device This icon denotes a note which alerts you to important information This icon denotes a caution which advises you of precautions to take to avoid injury data loss or a system crash Italic text denotes emphasis a cross reference or an introduction to a key concept This font also denotes text from which you supply the appropriate word or value as in NI DAQ 6 X National Instruments Corporation ix 6711 6713 6715 User Manual About This Manual 671X NI DAQ PC SCXI 671X refers to the National Instruments PCI PXI 6711 6713 DAQPad 6713 and DAQCard 6715 devices unless otherwise noted NI DAQ refers to the NI DAQ driver
41. connector to connect the device to external circuitry These connections are designed to enable the 6711 6713 device to both control and be controlled by other devices and circuits There are a total of 13 timing signals internal to the DAQ STC that you can control by an external source You can also control these timing signals control by signals generated internally to the DAQ STC and these selections are fully software configurable For example the signal routing multiplexer for controlling the UPDATE signal is shown in Figure 3 3 ioe RTSI Trigger lt 0 6 gt gt gt gt UPDATE PFI lt 0 9 gt lt Update Interval Counter TC gt GPCTRO_OUT ee Figure 3 3 UPDATE Signal Routing National Instruments Corporation 3 5 6711 6713 6715 User Manual Chapter 3 Hardware Overview Figure 3 3 shows that you can generate UPDATE from a number of sources including the external signals RTSI lt 0 6 gt and PFI lt 0 9 gt and the internal signals Sample Interval Counter TC and GPCTRO_OUT Many of these timing signals are also available as outputs on the RTSI pins as indicated in the RTSI Triggers section later in this chapter and on the PFI pins as indicated in Chapter 4 Signal Connections Programmable Function Inputs 6711 6713 The 10 PFIs are connected to the signal routing multiplexer for each timing signal and software can select one of the PFIs as the external
42. e Data transfers esines ian Number of channels c c0c00eeeeeeee Resolution Counter timers cccccseeeeeeeeees Frequency scaler eeesceeeeeees Compatibility 0 eeeeeseeeeeees Base clocks available Counter timers ccceseeeeeeeeees Frequency scaler eeeseeseeeerees Base clock accuracy Max source frequency Min source pulse duration Min gate pulse duration eee A 6 Input High Z Programmed I O 2 up down counter timers 1 frequency scaler 24 bits 4 bits TTL CMOS 20 MHz 100 kHz 10 MHz 100 kHz 0 01 over operating temperature 10 ns edge detect mode 10 ns edge detect mode www ni com Triggers Data transfers cccccceceeseseeesescseseeeeens DMA modes cccceceseseseeeseseseceseeeeece Digital Trigger Compatibility 000 eee eeeeeeereeees RESPONSE ninne i Pulse width sananne nna RTSI and PXI Trigger Lines Bus Interface National Instruments Corporation PCI 6711 6713 and DAQPad 6713 Trigger lines lt 0 6 gt cece eeeeeeee RTSI clock enneren PXI 6711 6713 A 7 Appendix A Specifications DMA 6711 6713 only interrupts programmed I O Scatter gather 6711 6713 only Rising or falling edge 10 ns min 5 V PCI master slave PXI CompactPCI master slave IEEE 1394 1995 16 bit PC Card PCMCIA 6711 6713 6715 User
43. e a PFI signal externally when it is configured as an output As an input you can individually configure each PFI for edge or level detection and for polarity selection as well You can use the polarity selection for any of the seven timing signals but the edge or level detection will depend upon the particular timing signal being controlled The detection requirements for each timing signal are listed within the section that discusses that individual signal In edge detection mode the minimum pulse width required is 10 ns This applies for both rising edge and falling edge polarity settings There is no maximum pulse width requirement in edge detect mode In level detection mode there are no minimum or maximum pulse width requirements imposed by the PFIs themselves but there can be limits imposed by the particular timing signal being controlled These requirements are listed later in this chapter EXTSTROBE Signal EXTSTROBE is an output only signal that is used for controlling SCXI devices National Instruments Corporation 4 13 6711 6713 6715 User Manual Chapter 4 Signal Connections Waveform Generation Timing Connections 6711 6713 6715 User Manual The analog group defined for the 6711 6713 device is controlled by WFTRIG UPDATE and UISOURCE WFTRIG Signal Any PFI pin can externally input the WFTRIG signal which is available as an output on the PFI6 WFTRIG pin As an input the WFTRIG signal is configured in t
44. e both application software and NI DAQ software documentation National Instruments application software includes ComponentWorks LabVIEW LabWindows CVI and VirtualBench After you set up your hardware system use either your application software documentation or the NI DAQ documentation to help you write your application If you have a large complicated system it is worthwhile to look through the software documentation before you configure your hardware X www ni com About This Manual Accessory installation guides or manuals If you are using accessory products read the terminal block and cable assembly installation guides They explain how to physically connect the relevant pieces of the system Consult these guides when you are making your connections SCXI chassis manuals If you are using SCXI read these manuals for maintenance information on the chassis and installation instructions Related Documentation The following documents contain information you may find helpful National Instruments Corporation DAQ STC Technical Reference Manual National Instruments Application Note 025 Field Wiring and Noise Considerations for Analog Signals PCI Local Bus Specification Revision 2 0 TEEE 1394 1995 specification xi 6711 6713 6715 User Manual Introduction This chapter describes your 671X device lists what you need to get started describes the optional software and optional equipment and explains how to unp
45. e ground reference signal for the analog output channels DAC lt 0 7 gt OUT as well as EXTREF is referenced to AOGND The external reference signal can be either a DC or an AC signal The device multiplies this reference signal by the DAC code divided by the full scale DAC code to generate the output voltage 4 8 www ni com Chapter 4 Signal Connections Figure 4 3 shows how to make analog output connections to the 671X device External Reference Signal Optional Ce EXTREF DACOOUT Lol Channel 0 Load AOGND Load DAC10OUT Lol lt Channel 1 Analog Output Channels 6711 6713 Device Figure 4 3 Analog Output Connections Digital 1 0 Signal Connections The digital I O signals are DIO lt 0 7 gt and DGND DIO lt 0 7 gt are the signals making up the DIO port and DGND is the ground reference signal for the DIO port You can program all lines individually as inputs or outputs UN Caution Exceeding the maximum input voltage ratings which are listed in Table 4 2 can damage the 671X device and the computer National Instruments is not liable for any damages resulting from such signal connections National Instruments Corporation 4 9 6711 6713 6715 User Manual Chapter 4 Signal Connections Figure 4 4 shows signal connections for three typical digital I O applications LED 7 1 DIO lt 4 7 gt
46. ef hardware descriptions mechanical drawings and helpful images of jumper settings and connector pinouts e Application Notes A library with more than 100 short papers addressing specific topics such as creating and calling DLLs developing your own instrument driver software and porting applications between platforms and operating systems National Instruments Corporation C 1 6711 6713 6715 User Manual Appendix C Technical Support Resources Software Related Resources e Instrument Driver Network A library with hundreds of instrument drivers for control of standalone instruments via GPIB VXI or serial interfaces You also can submit a request for a particular instrument driver if it does not already appear in the library e Example Programs Database A database with numerous non shipping example programs for National Instruments programming environments You can use them to complement the example programs that are already included with National Instruments products e Software Library A library with updates and patches to application software links to the latest versions of driver software for National Instruments hardware products and utility routines Worldwide Support 6711 6713 6715 User Manual National Instruments has offices located around the globe Many branch offices maintain a Web site to provide information on local services You can access these Web sites from www ni com worldwide If you have troub
47. election for either rising or falling edge As an output the GPCTR1_SOURCE monitors the actual clock connected to general purpose counter 1 This is true even if the source clock is externally generated by another PFI This output is set to tri state at startup National Instruments Corporation 4 19 6711 6713 6715 User Manual Chapter 4 Signal Connections Figure 4 14 shows the timing requirements for the GPCTR1_SOURCE signal tp 50 ns minimum ty 10ns minimum Figure 4 14 GPCTR1_SOURCE Signal Timing The maximum allowed frequency is 20 MHz with a minimum pulse width of 10 ns high or low There is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates the GPCTR1_SOURCE unless you select some external source GPCTR1_GATE Signal Any PFI pin can externally input the GPCTR1_GATE signal which is available as an output on the PFI4 GPCTR1_GATE pin As an input the GPCTR1_GATE signal is configured in edge detection mode You can select any PFI pin as the source for GPCTR1_GATE and configure the polarity selection for either rising or falling edge You can use the gate signal in a variety of different applications to perform such actions as starting and stopping the counter generating interrupts saving the counter contents and so on As an output the GPCTR1_GATE signal monitors the actual gate signal connected to general purpose counter 1 This is true even if the gate is
48. eseeseseeeeseaeeaaeeaes 2 4 Chapter 3 Hardware Overview Analogs OUtpUb iis cc ececieccseydisaseeieAcevecserevics scp enaar aap a EE o EE E IRS RES 3 4 Analog Output Reference Selection eseseeesseeessrsrerrseeererrererrsrerrereresseeeesee 3 4 Analog Output Reglitch Selection eee eseessecneceseceeceseeeenseneeeneeeees 3 4 Digital WO ocuse SS Re eae oe ee E E a E 3 4 Timing Signal ROUND rena epeei oe O E E ER 3 5 Programmable Function Inputs 00 0 0 cece ceessessesessecssesesseseeseesseseeseeseeees 3 6 De viceand RTSI Clocks scariest i n aaoi E ETR 3 6 RISI Tne gers osetia Aone RS aS 3 7 National Instruments Corporation v 6711 6713 6715 User Manual Contents Chapter 4 Signal Connections VO Comme ctr niroot ieri essa ue EEE E deeds cbs es EENE orii EE a ETE EEEE 4 1 T O Connector Signal Descriptions sseeeesseeeseeeseseseerrsetrrsreerereererreseereseee 4 4 Analog Output Signal Connections seeeessesesessesrssseerestestrtesrsrteseerssertnseeesreeesrrnrereset 4 7 Digital VO Signal Connections 000 cece eeeeceeeeeeceseeeeecaeeeaecaeesaecseesaecsecsseereneeeeeenes 4 9 Power Connections 2 cic te eee eel Asa eh Bia eae 4 11 Timing Connections 5s esessessee shee E E ieee EE E E boris E 4 11 Programmable Function Input Connections esesssseeeeesseesesreereererrereseerrseree 4 13 EXTSTROBE S1gtial rr a Eee E EEE AEE NE E 4 13 Waveform Generation Timing Connections sessseeeeseeeesrerrersree
49. evice or any other device Doing so can damage the 671X device and the computer National Instruments is not liable for damages resulting from such a connection Timing Connections UN Caution Exceeding the maximum input voltage ratings which are listed in Table 4 2 can damage the 671X device and the computer National Instruments is not liable for any damages resulting from such signal connections All external control over the timing of the 671X device is routed through the 10 programmable function inputs labeled PFIO through PFI9 These signals are explained in detail in the next section Programmable Function Input Connections These PFIs are bidirectional as outputs they are not programmable and reflect the state of many DAQ waveform generation and general purpose timing signals On 671X device six PFIs are bidirectional and four PFIs are input only PFIO PFI1 PFI2 PFI7 There are four other dedicated outputs for the remainder of the timing signals on the 671X SCANCLK is not used As inputs the PFI signals are programmable and can control any DAQ waveform generation and general purpose timing signals The waveform generation signals are explained in the Waveform Generation Timing Connections section later in this chapter The general purpose timing signals are explained in the General Purpose Timing Signal Connections section later in this chapter The 5 V line on the connector of the DAQCard 6715 is fused at 0 75 A
50. expressed in decibels dB convert signal a circuit that counts external pulses or clock pulses timing counter digital to analog digital to analog converter an electronic device often an integrated circuit that converts a digital number into a corresponding analog voltage or current data acquisition a system that uses the computer to collect receive and generate electrical signals Data acquisition system timing controller An application specific integrated circuit ASIC for the system timing requirements of a general A D and D A system such as a system containing the National Instruments E Series devices decibel the unit for expressing a logarithmic measure of the ratio of two signal levels dB 20log10 V1 V2 for signals in volts direct current digital ground signal digital input differential mode digital input output dual inline package the addition of Gaussian noise to an analog input signal 6711 6713 6715 User Manual Glossary DMA DNL DO E EEPROM EXTSTROBE FIFO FREQ OUT ft G GATE GPCTR 6711 6713 6715 User Manual direct memory access a method by which data can be transferred to from computer memory from to a device or memory on the bus while the processor does something else DMA is the fastest method of transferring data to from computer memory differential nonlinearity a measure in least significant bit of the worst case deviation of code widths from their
51. from the package e Remove the device from the package and inspect the device for loose components or any other sign of damage Notify National Instruments if the device appears damaged in any way Do not install a damaged device into your computer e Never touch the exposed pins of connectors Software Programming Choices You have several options to choose from when programming your National Instruments DAQ and SCXI hardware You can use National Instruments application software NI DAQ or register level programming National Instruments Application Software 6711 6713 6715 User Manual LabVIEW features interactive graphics a state of the art user interface and a powerful graphical programming language The LabVIEW Data Acquisition VI Library a series of VIs for using LabVIEW with National Instruments DAQ hardware is included with LabVIEW The LabVIEW Data Acquisition VI Library is functionally equivalent to NI DAQ software 1 4 www ni com Chapter 1 Introduction LabWindows CVI features interactive graphics state of the art user interface and uses the ANSI standard C programming language The LabWindows CVI Data Acquisition Library a series of functions for using LabWindows CVI with National Instruments DAQ hardware is included with the NI DAQ software kit The LabWindows CVI Data Acquisition Library is functionally equivalent to the NI DAQ software ComponentWorks contains tools for data acquisition and instrument co
52. he edge detection mode You can select any PFI pin as the source for WFTRIG and configure the polarity selection for either rising or falling edge The selected edge of the WFTRIG signal starts the waveform generation for the DACs The update interval UD counter is started if you select internally generated UPDATE As an output the WFTRIG signal reflects the trigger that initiates waveform generation This is true even if the waveform generation is externally triggered by another PFI The output is an active high pulse with a pulse width of 25 to 50 ns This output is set to tri state at startup Figures 4 6 and 4 7 show the input and output timing requirements for the WFTRIG signal Rising edge polarity aaa Falling edge polarity tw 10 ns minimum Figure 4 6 WFTRIG Input Signal Timing 4 14 www ni com Chapter 4 Signal Connections tw 25 50 ns 1 Figure 4 7 WFTRIG Output Signal Timing UPDATE Signal Any PFI pin can externally input the UPDATE signal which is available as an output on the PFIS UPDATE pin As an input the UPDATE signal is configured in the edge detection mode You can select any PFI pin as the source for UPDATE and configure the polarity selection for either rising or falling edge The selected edge of the UPDATE signal updates the outputs of the DACs In order to use UPDATE you must set the DACs to posted update mode As an output the
53. ices 1 4 I O connector 4 1 to 4 7 exceeding maximum ratings warning 4 4 T O signal summary table 4 6 to 4 7 optional equipment 1 7 pin assignments figure 671X device 4 2 671X device with SH68 50 cable 4 3 signal descriptions table 4 4 to 4 5 J J2 pin assignments for PXI 671 1 6713 table 1 3 National Instruments Corporation l 3 Index L LabVIEW and LabWindows CVI application software 1 4 to 1 5 manual See documentation MITE bus interface chip 1 1 National Instruments Web support C 1 to C 2 NI DAQ driver software 1 5 to 1 6 0 online problem solving and diagnostic resources C 1 optional equipment 1 7 P PFIO signal description table 4 4 signal summary table 4 6 PFI1 signal description table 4 4 signal summary table 4 6 PFI2 signal description table 4 4 signal summary table 4 6 PFI3 GPCTR1_SOURCE signal description table 4 4 signal summary table 4 6 PFI4 GPCTR1_GATE signal description table 4 5 signal summary table 4 6 PFI5 UPDATE signal description table 4 5 signal summary table 4 7 PFI6 WFTRIG signal 6711 6713 6715 User Manual Index description table 4 5 signal summary table 4 7 PFI7 signal description table 4 5 signal summary table 4 7 PFI8 GPCTRO_SOURCE signal description table 4 5 signal summary table 4 7 PFI9 GPCTRO_GATE signal description table 4 5 signal summary table 4 7 PFIs programmable functi
54. ideal value of 1 LSB digital output electrically erasable programmable read only memory ROM that can be erased with an electrical signal and reprogrammed external strobe signal first in first out memory buffer FIFOs are often used on DAQ devices to temporarily store incoming or outgoing data until that data can be read or written For example an analog input FIFO stores the results of A D conversions until the data can be read into system memory Programming the DMA controller and servicing interrupts can take several milliseconds in some cases During this time data accumulates in the FIFO for future retrieval With a larger FIFO longer latencies can be tolerated In the case of analog output a FIFO permits faster update rates because the waveform data can be stored in the FIFO ahead of time This again reduces the effect of latencies associated with getting the data from system memory to the DAQ device frequency output signal feet gate signal general purpose counter signal G 4 www ni com GPCTRO_GATE GPCTRO_OUT GPCTRO_SOURCE GPCTRO_UP_DOWN GPCTR1_GATE GPCTR1_OUT GPCTR1_SOURCE GPCTR1_UP_DOWN INL T O National Instruments Corporation G 5 Glossary general purpose counter 0 gate signal general purpose counter 0 output signal general purpose counter 0 clock source signal general purpose counter 0 up down signal general purpose counter gate signal general purpose counter output signal general pu
55. iest and least accurate whereas the last level is the slowest most difficult and most accurate Loading Calibration Constants The 671X device is factory calibrated before shipment at approximately 25 C to the levels indicated in Appendix A Specifications The associated calibration constants the values that were written to the CalDACs to achieve calibration in the factory are stored in the onboard nonvolatile memory EEPROM Because the CalDACs have no memory capability they do not retain calibration information when the device is unpowered Loading calibration constants refers to the process of loading the CalDACs with the values stored in the EEPROM NI DAQ software determines when this is necessary and does it automatically If you are not using NI DAQ you must load these values yourself In the EEPROM there is a user modifiable calibration area in addition to the permanent factory calibration area This means that you can load the CalDACs with values either from the original factory calibration or from a calibration that you subsequently performed National Instruments Corporation 5 1 6711 6713 6715 User Manual Chapter 5 Calibration The loading factory calibration constants method of calibration is not very accurate because it does not take into account the fact that the device measurement and output voltage errors can vary with time and temperature It is better to self calibrate when the device is installed in the e
56. ing 0 000 eee eeeeeeteceecneeeeeeees 4 17 Figure 4 12 GPCTRO_GATE Signal Timing in Edge Detection Mode 0 4 18 Figure 4 13 GPCTRO_OUT Signal Timing oo eee eseeceeseeeseeeeneeneeenes 4 19 Figure 4 14 GPCTR1_SOURCE Signal Timing 0 0 ee eeeeseeecneceeeneeeees 4 20 Figure 4 15 GPCTR1_GATE Signal Timing in Edge Detection Mode 4 21 Figure 4 16 GPCTR1_OUT Signal Timing eee eseeceeneesaeeteceeeneeenes 4 21 Figure 4 17 GPCTR Timing Summary ccc ceceeeeeeeeeeceeesseaececeseeeeeeaeenes 4 22 Tables Table 1 1 PXI 6711 6713 J2 Pin Assignment ccc eecesseserceeseeeseeceeeceeeeneeeenees 1 3 Table 4 1 Signal Descriptions for I O Connector Pins 0 0 00 eeeeeseeeseeereesteceeeeee 4 4 Table 4 2 VO Signal Summary for the 6711 6713 Device eee eeeeeeeeeeees 4 6 National Instruments Corporation vil 6711 6713 6715 User Manual About This Manual This manual describes the electrical and mechanical aspects of the PCI PXI 67 11 6713 DAQPad 6713 and DAQCard 6715 devices and contains information concerning their operation and programming The 6711 6713 6715 devices include e PXI 6711 with four or PXI 6713 with eight analog output AO channels two counters and eight digital input output DIO channels for PXI CompactPCI e PCI 6711 with four or PCI 6713 with eight AO channels two counters and eight DIO channels for PCI e DAQPad 6713 with eight AO channels two counters and eight DIO
57. ise 6711 6713 6715 User Manual referenced single ended mode all measurements are made with respect to a common reference measurement system or a ground Also called a grounded measurement system resistive temperature detector a metallic probe that measures temperature based upon its coefficient of resistivity Real Time System Integration bus the National Instruments timing bus that connects DAQ devices directly by means of connectors on top of the devices for precise timing synchronization between multiple devices RTSI Oscillator RTSI bus master clock seconds samples scan clock signal Signal Conditioning eXtensions for Instrumentation the National Instruments product line for conditioning low level signals within an external chassis near sensors so only high level signals are sent to DAQ devices in the noisy computer environment single ended a term used to describe an analog input that is measured with respect to a common ground the amount of time required for a voltage to reach its final value within specified limits the manipulation of signals to prepare them for digitizing SI counter clock signal source signal samples per second used to express the rate at which a DAQ device samples an analog signal a measure of the amount of noise seen by an analog circuit or an ADC when the analog inputs are grounded G 8 www ni com TC ty tes ew tout THD thermocouple TRIG tsc is TTL U
58. l Descriptions for I O Connector Pins Continued Signal Name Reference Direction Description PFI4 GPCTR1_GATE DGND Input PFI4 Counter 1 Gate As an input this is one of the PFIs Output As an output this is the GPCTR1_GATE signal This signal reflects the actual gate signal connected to the general purpose counter 1 GPCTR1_OUT DGND Output Counter 1 Output This output is from the general purpose counter output PFIS5 UPDATE DGND Input PFI5 Update As an input this is one of the PFIs Output As an output this is the UPDATE signal A high to low edge on UPDATE indicates that the analog output waveform generation group is being updated PFI6 WFTRIG DGND Input PFI6 Waveform Trigger As an input this is one of the PFIs Output As an output this is the WFTRIG signal In timed analog output sequences a low to high transition indicates the initiation of the waveform generation PFI7 DGND Input PFI7 As an input this is one of the PFIs PFI7 cannot be an output PFI8 GPCTRO_SOURCE DGND Input PFI8 Counter 0 Source As an input this is one of the PFIs Output As an output this is the GPCTRO_SOURCE signal This signal reflects the actual source connected to the general purpose counter 0 PFI9 GPCTRO_GATE DGND Input PFI9 Counter 0 Gate As an input this is one of the PFIs Output As an output this is the GPCTRO_GATE signal This signal reflects the actual gate signal connected to the ge
59. le connecting to our Web site please contact your local National Instruments office or the source from which you purchased your National Instruments product s to obtain support For telephone support in the United States dial 512 795 8248 For telephone support outside the United States contact your local branch office Australia 03 9879 5166 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Brazil 011 284 5011 Canada Calgary 403 274 9391 Canada Ontario 905 785 0085 Canada Qu bec 514 694 8521 China 0755 3904939 Denmark 45 76 26 00 Finland 09 725 725 11 France 01 48 14 24 24 Germany 089 741 31 30 Greece 30 1 42 96 427 Hong Kong 2645 3186 India 91805275406 Israel 03 6120092 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico D F 5 280 7625 Mexico Monterrey 8 357 7695 Netherlands 0348 433466 Norway 32 27 73 00 Poland 48 22 528 94 06 Portugal 351 1 726 9011 Singapore 2265886 Spain 91 640 0085 Sweden 08 587 895 00 Switzerland 056 200 51 51 Taiwan 02 2377 1200 United Kingdom 01635 523545 C 2 www ni com Glossary Prefix Meanings Value p pico 10 2 n nano 10 9 u micro 10 6 m milli 10 3 k kilo 103 M mega 106 G giga 10 t tera 10 Numbers Symbols 2 degrees gt greater than gt greater than or equal to lt less than lt less than or equal to per percent plus or minus positive of or plus negative
60. mponentWorks software 1 5 configuration 671X devices 2 4 questions about B 2 connector See I O connector counter timers questions about B 3 D DAC lt 0 7 gt OUT signal analog output signal connections 4 7 to 4 9 description table 4 4 6711 6713 6715 User Manual Index signal summary table 4 6 DAQ STC system timing controller 1 1 B 1 to B 3 deglitching filter B 2 DGND signal description table 4 4 digital I O connections 4 9 signal summary table 4 6 diagnostic resources online C 1 digital I O operation 3 4 questions about B 2 to B 3 signal connections 4 9 to 4 10 specifications A 5 to A 6 digital trigger specifications A 7 DIO lt 0 7 gt signal description table 4 4 digital I O connections 4 9 to 4 10 signal summary table 4 6 documentation conventions used in manual ix x National Instruments documentation x xi related documentation xi E EEPROM storage of calibration constants 5 1 environment specifications A 8 equipment optional 1 7 external reference input specifications A 4 EXTREF signal analog output reference selection 3 4 analog output signal connections 4 7 to 4 9 description table 4 4 signal summary table 4 6 EXTSTROBE signal controlling SCXI devices 4 13 description table 4 4 signal summary table 4 6 6711 6713 6715 User Manual l 2 F field wiring considerations 4 23 FREQ_OUT signal description table 4 5 general purpose timing
61. ms DC to 1 MHz 6711 6713 6715 User Manual A 4 www ni com Appendix A Specifications Channel crosstalk 6711 6713 riras 70 dB with SH6868EP cable generating a 10 V 10 pt sinusoidal at 100 KHz on the reference channel DAQCard 6715 cecceceessceeseeeeees 60 dB generating a 10 V 10 pt sinusoidal at 100 KHz on the reference channel Total harmonic distortion 60 dB typ generating a 10 V 100 points 10 kHz sine wave summing 9 harmonics Stability Offset temperature coefficient 50 uV C Gain temperature coefficient Internal reference 0 0 0 0 eee 25 ppm C External reference n 25 ppm C Onboard calibration reference EA os cccetiwsosnvestoeconna yeoman 5 000 V 2 5 mV actual value stored in EEPROM Temperature coefficient 5 0 ppm C max Long term stability oe 15 ppm 41 000 h Digital 1 0 Number of channels 000 000 cece 8 input output Compatibility 00 eee cee eeeeeeeee TTL CMOS National Instruments Corporation A 5 6711 6713 6715 User Manual Appendix A Timing 1 0 6711 6713 6715 User Manual Specifications Digital logic levels Level Min Max Input low voltage 0 0 V 0 8 V Input high voltage 2 0 V 5 0 V Input low current V 0 V 320 uA Input high current V 5 V 10 pA Output low voltage I 24 mA 0 4 V Output high voltage 13 mA 4 35 V Power on state ssoseseseseseeeeeeeeeeereersess
62. neral purpose counter 0 GPCTRO_OUT DGND Output Counter 0 Output This output is from the general purpose counter 0 output FREQ_OUT DGND Output Frequency Output This output is from the frequency generator output 1 The 5 V line on the connector of the DAQCard 67 15 is fused at 0 75 A however the actual current available can be limited below this value by the host computer National Instruments recommends limiting current from this line to 250 mA National Instruments Corporation 4 5 6711 6713 6715 User Manual Chapter 4 Signal Connections Table 4 2 shows the I O signal summary for the 6711 6713 devices Table 4 2 1 0 Signal Summary for the 6711 6713 Device Rise Time Signal Impedance Protection Sink ns Type and Input Volts Source mA Slew Signal Name Direction Output On Off mA at V at V Rate Bias DAC lt 0 7 gt OUT AO 0 1 Q Short circuit 5 at 10 5 at 10 20 V to ground total not us to exceed 20 mA total for all 8 outputs combined DAQCard 6715 AOGND AO DGND DIO VCC DO 0 1 Q Short circuit 1A to ground 0 75 A DAQCard 6715 DIO lt 0 7 gt DIO Vec 0 5 13 at 24 at 1 1 50 KQ pu Vec 0 4 0 4 EXTSTROBE DO 3 5 at 5at0 4 1 5 50 kQ pu Vec 0 4 EXTREF AI 10 kQ 25 15 PFIO DI Vec 0 5 3 5 at 5at0 4 1 5 50 kQ pd Vec 0 4 PFI1 DI Vec 0 5
63. nship Between the Programming Environment NI DAQ and Your Hardware ccccescccsssecesceceesseecesececseeeeessseeennaes 1 6 Figure 3 1 6711 6713 Block Diagram esssseesssrerseesreeseesesreresresrrrrererrsseerssreeesee 3 2 Figure 3 2 6715 Block Diagram oe eee ceeeee ce cnee cee ceseeseceeeeseceeeseeeeeeseeneeeaes 3 3 Figure 3 3 UPDATE Signal Routing 0 ce ceeeseceeceseceeeeseeeeeeeeeeeeeseeees 3 5 Figure 3 4 RTSI Bus Signal Connection eee ceeceseceeeeseeeeceeeeeeeeeeeeeeens 3 7 Figure 4 1 68 Pin I O Connector Pin Assignment for the 671X Device 4 2 Figure 4 2 50 Pin I O Connector Pin Assignment for the 67 1X Device When Using the SH68 50 Cable oo cece cre cneceeeeeeeeeeeneeneeenees 4 3 Figure 4 3 Analog Output Connections 0 0 eee eseecseceeeesecneceeeeseeseseseeneeeaes 4 9 Figure 4 4 Digital I O Connections eee ce ceceeeeeseeeeeeseeceecssceseceeceeeesesenseaeenaes 4 10 Figure 4 5 Timing T O Connections issin ses cbenescsoscoesedvsdessssgetenensnsce 4 12 Figure 4 6 WFTRIG Input Signal Timing 200 eee ceeeee cee ceseeseeeeeeeeeneeeaes 4 14 Figure 4 7 WFTRIG Output Signal Timing cece ce cneceseeeeeeeeeeeeneeeaes 4 15 Figure 4 8 UPDATE Input Signal Timing eee ce cneceseeeecneeeeeeeeeenes 4 15 Figure 4 9 UPDATE Output Signal Timing oo cece eee ceeeeeeeeeceeneees 4 16 Figure 4 10 UISOURCE Signal Timing oe eceeeeeeeseeenececeseeeeeseeeseeaee 4 16 Figure 4 11 GPCTRO_SOURCE Signal Tim
64. ntrol built on NI DAQ driver software ComponentWorks provides a higher level programming interface for building virtual instruments through standard OLE controls and DLLs With ComponentWorks you can use all of the configuration tools resource management utilities and interactive control utilities included with NI DAQ VirtualBench features virtual instruments that combine DAQ products software and your computer to create a stand alone instrument with the added benefit of the processing display and storage capabilities of your computer VirtualBench instruments load and save waveform data to disk in the same forms that used in popular spreadsheet programs and word processors Using ComponentWorks Lab VIEW LabWindows CVI or VirtualBench software will greatly reduce the development time for your data acquisition and control application NI DAQ Driver Software The NI DAQ driver software is included at no charge with all National Instruments DAQ hardware NI DAQ is not packaged with SCXI or accessory products except for the SCXI 1200 NI DAQ has an extensive library of functions that you can call from your application programming environment These functions include routines for analog input A D conversion buffered data acquisition high speed A D conversion analog output D A conversion waveform generation timed D A conversion digital I O counter timer operations SCXI RTSI self calibration messaging and acquiring data t
65. nvironment in which it will be used Self Calibration The 671X device can measure and correct for almost all of its calibration related errors without any external signal connections Your National Instruments software provides a self calibration method This self calibration process which generally takes less than two minutes is the preferred method of assuring accuracy in your application Initiate self calibration to minimize the effects of any offset gain and linearity drifts particularly those due to warmup Immediately after self calibration the only significant residual calibration error could be gain error due to time or temperature drift of the onboard voltage reference This error is addressed by external calibration which is discussed in the following section If you are interested primarily in relative measurements and you can ignore a small amount of gain error self calibration should be sufficient External Calibration The 671X device has an onboard calibration reference to ensure the accuracy of self calibration Its specifications are listed in Appendix A Specifications The reference voltage is measured at the factory and stored in the EEPROM for subsequent self calibrations This voltage is stable enough for most applications but if you are using your device at an extreme temperature or if the onboard reference has not been measured for a year or more you may wish to externally calibrate your device An ex
66. o extended memory NI DAQ has both high level DAQ I O functions for maximum ease of use and low level DAQ I O functions for maximum flexibility and performance Examples of high level functions are streaming data to disk or acquiring a certain number of data points An example of a low level function is writing directly to registers on the DAQ device NI DAQ does not sacrifice the performance of National Instruments DAQ devices because it lets multiple devices operate at their peak National Instruments Corporation 1 5 6711 6713 6715 User Manual Chapter 1 Introduction NI DAQ also internally addresses many of the complex issues between the computer and the DAQ hardware such as programming interrupts and DMA controllers NI DAQ maintains a consistent software interface among its different versions so that you can change platforms with minimal modifications to your code Whether you are using conventional programming languages or National Instruments application software your application uses the NI DAQ driver software as illustrated in Figure 1 1 Conventional ComponentWorks Programming LabVIEW LabWindows CVI Environment NI DAQ Driver Software L DAQ or Personal Computer SCXI Hardware or Workstation or VirtualBench Figure 1 1 The Relationship Between the Programming Environment NI DAQ and Your Hardware Register Level Programming 6711 6713 6715
67. of or minus Q ohms National Instruments Corporation G 1 6711 6713 6715 User Manual Glossary r 5 V AC A D ADC ANSI AO AOGND ASIC bipolar C C CalDAC CH cm 6711 6713 6715 User Manual square root of 5 VDC source signal amperes alternating current analog to digital analog to digital converter an electronic device often an integrated circuit that converts an analog voltage to a digital number American National Standards Institute analog output analog output ground signal Application Specific Integrated Circuit a proprietary semiconductor component designed and manufactured to perform a set of specific functions a signal range that includes both positive and negative values for example 5 V to 5 V Celsius calibration DAC channel pin or wire lead to which you apply or from which you read the analog or digital signal Analog signals can be single ended or differential For digital signals you group channels to form ports Ports usually consist of either four or eight digital channels centimeter G 2 www ni com CMOS CMRR CONVERT counter timer CTR D D A DAC DAQ DAQ STC dB DC DGND DI DIFF DIO DIP dithering National Instruments Corporation G 3 Glossary complementary metal oxide semiconductor common mode rejection ratio a measure of an instrument s ability to reject interference from a common mode signal usually
68. on inputs connecting to external signal source warning B 3 overview 4 13 questions about B 3 signal routing 3 6 timing connections 4 13 physical specifications A 8 pin assignments 671X device figure 4 2 671X device with SH68 50 cable figure 4 3 J2 pin assignments for PXI 6711 6713 table 1 3 power connections 4 11 5 V power pins 4 11 power on states of PFI and DIO lines B 3 self resetting fuse 4 11 power requirement specifications A 8 problem solving and diagnostic resources online C 1 programmable function inputs PFIs See PFIs programmable function inputs PXI using with CompactPCI 1 2 to 1 3 PXI trigger line specifications A 7 6711 6713 6715 User Manual l 4 Q questions and answers general information B 1 to B 2 installation and configuration B 2 timing and digital I O B 2 to B 3 R reference selection analog output 3 4 register level programming 1 6 reglitch selection analog output 3 4 requirements for getting started 1 3 to 1 4 RTSI clocks 3 6 RTSI triggers 3 7 RTSI bus signal connections figure 3 7 specifications A 7 S signal connections analog output signal connections 4 7 to 4 9 digital T O 4 9 to 4 10 field wiring considerations 4 23 general purpose timing signal connections 4 17 to 4 23 FREQ_OUT signal 4 23 GPCTRO_GATE signal 4 18 GPCTRO_OUT signal 4 18 to 4 19 GPCTRO_SOURCE signal 4 17 to 4 18 GPCTRO_UP_DOWN signal 4 19 GPCTR1_GATE signal 4 20
69. p Figure 4 11 shows the timing requirements for the GPCTRO_SOURCE signal tp 50 ns minimum ty 10 ns minimum Figure 4 11 GPCTRO_SOURCE Signal Timing National Instruments Corporation 4 17 6711 6713 6715 User Manual Chapter 4 Signal Connections 6711 6713 6715 User Manual The maximum allowed frequency is 20 MHz with a minimum pulse width of 10 ns high or low There is no minimum frequency limitation The 20 MHz or 100 kHz timebase normally generates the GPCTRO_SOURCE signal unless you select some external source GPCTRO_GATE Signal Any PFI pin can externally input the GPCTRO_GATE signal which is available as an output on the PFI9 GPCTRO_GATE pin As an input the GPCTRO_GATE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTRO_GATE and configure the polarity selection for either rising or falling edge You can use the gate signal in a variety of different applications to perform actions such as starting and stopping the counter generating interrupts saving the counter contents and so on As an output the GPCTRO_GATE signal reflects the actual gate signal connected to general purpose counter 0 This is true even if the gate is externally generated by another PFI This output is set to tri state at startup Figure 4 12 shows the timing requirements for the GPCTRO_GATE signal tw 4 gt polarity Falling edge
70. route internal signals to the I O connector route external signals to internal timing sources or tie internal timing signals together If you are using NI DAQ with LabVIEW and you want to connect external signal sources to the PFI lines you can use AO Clock Config AO Trigger and Gate Config CTR Mode Config and CTR Pulse Config advanced level VIs to indicate which function the connected signal will serve Use the Route Signal VI to enable the PFI lines to output internal signals as Caution If you enable a PFI line for output do not connect any external signal source to it if you do you can damage the device the computer and the connected equipment What are the power on states of the PFI and DIO lines on the I O connector At system power on and reset both the PFI and DIO lines are set to high impedance by the hardware This means that the device circuitry is not actively driving the output either high or low However these lines may have pull up or pull down resistors connected to them as shown in Table 4 2 These resistors weakly pull the output to either a logic high or logic low state For example DIO 0 will be in the high impedance state after power on and Table 4 2 shows that there is a 50 kQ pull up resistor This pull up resistor will set the DIO O pin to a logic high when the output is in a high impedance state National Instruments Corporation B 3 6711 6713 6715 User Manual Technical Support Resources This
71. rpose counter clock source signal general purpose counter up down signal hour hexadecimal hertz integral nonlinearity For an ADC deviation of codes of the actual transfer function from a straight line input output the transfer of data to from a computer system involving communications channels operator interface devices and or data acquisition and control interfaces current output high current output low kilohertz 6711 6713 6715 User Manual Glossary LED LSB MB MHz MIO MITE MSB mux mV NC NI DAQ noise NRSE 6711 6713 6715 User Manual light emitting diode least significant bit meter megabytes of memory megahertz multifunction I O MXI Interface to Everything most significant bit multiplexer a switching device with multiple inputs that sequentially connects each of its inputs to its output typically at high speeds in order to measure several signals with a single analog input channel millivolts normally closed or not connected National Instruments driver software for DAQ hardware an undesirable electrical signal Noise comes from external sources such as the AC power line motors generators transformers fluorescent lights CRT displays computers electrical storms welders radio transmitters and internal sources such as semiconductors resistors and capacitors Noise corrupts signals you are trying to send or receive nonreferenced single ended mode
72. rsrrerrereresesee 4 14 WETRIG S anal E E EEEE E des pee tien etiscad 4 14 UPDATE Signal is 2 0s seston eal Mae ee Ne a 4 15 WISOQURCE S etna spay soe csfeseesests aa dl evecsesndet len eein E 4 16 General Purpose Timing Signal Connections 0 cece eeseeeceseeeeeeeeeeeeeeeees 4 17 GPCTRO_SOURCE Signal 0 0 00 ccssssscsssessseoesensenesocesneeveesseeseens 4 17 GPCTRO_GATE Signal niseni eher a reia 4 18 GPCTROVOUT Signal arne sopeopie ienee e aeai ne ap enia 4 18 GPCTRO_UP_DOWN Signal sseeesseeeeseeeseeresesseresereerrsrrserrrsreeresese 4 19 GPCTRI SOURCE Sipak sis avin e e 4 19 GPCTRI_GATE Signalons ee e i ereak nna 4 20 GPCTRI OUT Signalne aee o aana ira aptesa 4 21 GPCTR1_UP_DOWN Signal eseseeeeeeeeeeeseseeresrerrersrsresrsrseereeeseee 4 22 FREQ OUT Signal anene ease en a ARN 4 23 Field Wiring Considerations eseseeeeseeeesesresesresrsrsstereseeersresrereereenresteseeresrenerrrsereset 4 23 Chapter 5 Calibration Loading Calibration Constant 0 ccc cesceceseeeeceeeeeeeeeeeeeeeaeeaeecaecsaecaecsacsnecesenseensenes 5 1 Self Cali bration ena aa eenen eE ee ain i ne eee 5 2 External Calibration aeien us taut Bh Aue eee DO A Sahota save etd E 5 2 Other Considerations a o e EE pae poneo an a sa 5 3 Appendix A Specifications Appendix B Common Questions 6711 6713 6715 User Manual vi www ni com Contents Appendix C Technical Support Resources Glossary Index Figures Figure 1 1 The Relatio
73. s Remove the filter panel for the peripheral slot that you have chosen Touch a metal part on the chassis to discharge any static electricity that might be on your clothes or body Insert the PXI 6711 6713 device in the 5 V slot Use the injector ejector handle to fully inject the device into place Screw the front panel of the PXI 6711 6713 to the front panel mounting rails of the PXI or CompactPCI chassis Visually verify the installation Plug in and turn on the PXI or CompactPCI chassis The PXI 6711 6713 is now installed PCI 6711 6713 1 2 3 4 6711 6713 6715 User Manual Turn off and unplug your computer Remove the top cover or access port to the I O channel Remove the expansion slot cover on the back panel of the computer Insert the 6711 6713 device into a 5 V PCI slot Gently rock the device to ease it into place It can be a tight fit but do not force the device into place If required screw the mounting bracket of the 6711 6713 device to the back panel rail of the computer Replace the cover Plug in and turn on your computer 2 2 www ni com Chapter 2 Installation and Configuration The PCI 671 1 6713 device is installed You are now ready to configure your software Refer to your software documentation for configuration instructions DAQPad 6713 1 Connect the 1394 cable from the computer or any other 1394 device to the port on your DAQPad device 2 Connect the power cord to the
74. s output as a source to a system that has low bandwidth characteristics the glitches are ignored by the system Timing and Digital 1 0 6711 6713 6715 User Manual What types of triggering can be hardware implemented on my 671X device Hardware digital triggering is supported on the 671X device What functionality does the DAQ STC make possible The DAQ STC has the complexity of more than 24 chips The DAQ STC makes possible PFI lines selectable logic level and frequency shift keying B 2 www ni com Appendix B Common Questions The DAQ STC also makes buffered operations possible such as direct up down control single pulse or pulse train generation equivalent time sampling buffered period and buffered semiperiod measurement I m using one of the general purpose counter timers on my 671X device but I do not see the counter timer output on the I O connector What am I doing wrong If you are using the NI DAQ language interface or LabWindows CVI you must configure the output line to output the signal to the I O connector Use the Select_Signal call in NI DAQ to configure the output line By default all timing I O lines except EXTSTROBE are tri stated What are the PFIs and how do I configure these lines PFIs are Programmable Function Inputs These lines serve as connections to virtually all internal timing signals If you are using the NI DAQ language interface or LabWindows CVI use the Select_Signal function to
75. s if they run in parallel paths at a close distance To reduce the magnetic coupling between lines separate them by a reasonable distance if they run in parallel or run the lines at right angles to each other e Do not run signal lines through conduits that also contain power lines e Protect signal lines from magnetic fields caused by electric motors welding equipment breakers or transformers by running them through special metal conduits For more information refer to the application note Field Wiring and Noise Consideration for Analog Signals available from National Instruments National Instruments Corporation 4 23 6711 6713 6715 User Manual Calibration This chapter discusses calibration procedures for your 671X device If you are using the NI DAQ device driver that software includes calibration functions for performing all of the steps in the calibration process Calibration refers to the process of minimizing measurement and output voltage errors by making small circuit adjustments On the 671X device these adjustments take the form of writing values to onboard calibration DACs CalDACs Some form of device calibration is required for all but the most forgiving applications If you do not calibrate your device your signals and measurements could have very large offset gain and linearity errors Three levels of calibration are available to you and described in this chapter The first level is the fastest eas
76. se 4 11 B 2 6711 6713 6715 devices See also hardware overview custom cabling 1 7 optional equipment 1 7 overview l 1 to 1 2 questions about B 1 to B 3 general information B 1 to B 2 installation and configuration B 2 timing and digital I O B 2 to B 3 requirements for getting started 1 3 to 1 4 software programming choices 1 4 to 1 6 National Instruments application statement 1 4 to 1 5 NI DAQ driver software 1 5 to 1 6 register level programming 1 6 unpacking 1 4 using PXI with CompactPCI 1 2 to 1 3 A analog output 3 4 questions about B 2 reference selection 3 4 reglitch selection 3 4 analog output specifications A 1 to A 5 accuracy information A 3 dynamic characteristics A 4 to A 5 external reference input A 4 output characteristics A 1 to A 2 stability A 5 transfer characteristics A 3 voltage output A 4 National Instruments Corporation AOGND signal analog output signal connections 4 7 to 4 9 description table 4 4 signal summary table 4 6 block diagrams 6711 6713 3 2 6715 3 3 bus interface specifications A 7 C cables custom cabling 1 7 field wiring considerations 4 23 optional equipment 1 7 calibration 5 1 to 5 3 adjusting for gain error 5 3 external calibration 5 2 to 5 3 loading calibration constants 5 1 to 5 2 self calibration 5 2 clocks device and RTSI 3 6 common questions See questions and answers CompactPCI using with PXI 1 2 to 1 3 Co
77. source for a given timing signal It is important to note that you can use any of the PFIs as an input by any of the timing signals and that multiple timing signals can use the same PFI simultaneously This flexible routing scheme reduces the need to change physical connections to the I O connector for different applications You can also individually enable each of the PFI pins to output a specific internal timing signal For example if you need the UPDATE signal as an output on the I O connector software can turn on the output driver for the PFIS UPDATE pin Device and RTSI Clocks 6711 6713 6715 User Manual 6711 6713 Many functions performed by the 6711 6713 device require a frequency timebase to generate the necessary timing signals for controlling DAC updates or general purpose signals at the I O connector The 6711 6713 device can use either its internal 20 MHz timebase or a timebase received over the RTSI bus In addition if you configure the device to use the internal timebase you can also program the device to drive its internal timebase over the RTSI bus to another device that is programmed to receive this timebase signal This clock source whether local or from the RTSI bus is used directly by the device as the primary frequency source The default configuration at startup is to use the internal timebase without driving the RTSI bus timebase signal This timebase is software selectable 3 6 www ni com RTSI Triggers
78. source for the UISOURCE signal in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low Figure 4 10 shows the timing requirements for the UISOURCE signal tp 50 ns minimum ty 10 ns minimum Figure 4 10 UISOURCE Signal Timing 6711 6713 6715 User Manual 4 16 www ni com Chapter 4 Signal Connections The maximum allowed frequency is 20 MHz with a minimum pulse width of 10 ns high or low There is no minimum frequency limitation Either the 20 MHz or 100 kHz internal timebase normally generates the UISOURCE signal unless you select some external source General Purpose Timing Signal Connections The general purpose timing signals are GPCTRO_SOURCE GPCTRO_GATE GPCTRO_OUT GPCTRO_UP_DOWN GPCTR1_SOURCE GPCTR1_GATE GPCTR1_OUT GPCTR1_UP_DOWN and FREQ_OUT GPCTRO_SOURCE Signal Any PFI pin can externally input the GPCTRO_SOURCE signal which is available as an output on the PFI8 GPCTRO_SOURCE pin As an input the GPCTRO_SOURCE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTRO_SOURCE and configure the polarity selection for either rising or falling edge As an output the GPCTRO_SOURCE signal reflects the actual clock connected to general purpose counter 0 This is true even if another PFI is externally inputting the source clock This output is set to tri state at startu
79. ternal calibration refers to calibrating your device with a known external reference rather than relying on the onboard reference Redetermining the value of the onboard reference is part of this process and you can save the results in the EEPROM so you should not have to perform an external calibration very often You can externally calibrate your device by calling the NI DAQ calibration function The onboard voltage reference has a temperature coefficient of 5 ppm C max 25 uV C Therefore if the temperature difference between the factory calibration and the service environment is less than 10 C the maximum gain error is less than 50 ppm 0 005 percent at full scale output after performing self calibration 6711 6713 6715 User Manual 5 2 www ni com Chapter 5 Calibration To externally calibrate your device be sure to use a very accurate external reference The reference should be several times more accurate than the device itself For example to calibrate a 12 bit device the external reference should be at least 0 0062 62 ppm accurate 3 Note National Instruments recommends using a 5 V external reference voltage when performing calibration Other Considerations The CalDACs adjust the gain error of each analog output channel by adjusting the value of the reference voltage supplied to that channel This calibration mechanism is designed to work only with the internal 10 V reference Thus in general it is not possi
80. their final value within about 5 us restricting large scale accurate outputs to 200 kS s channel National Instruments Corporation B 1 6711 6713 6715 User Manual Appendix B Common Questions What type of 5 V protection does the 671X device have The 6711 6713 device has 5 V lines equipped with a self resetting 1 A fuse The 6715 device has 5 V lines equipped with a self resetting 0 75 A fuse Installation and Configuration Analog Output How do you set the base address for the 671X device The base address of the 67 LX device is assigned automatically through the bus protocol This assignment is completely transparent to you What jumpers should I be aware of when configuring my 671X device The 671X device is jumperless and switchless Which National Instruments document should I read first to get started using DAQ software Your NI DAQ or application software release notes documentation is always the best starting place I m using the DACs to generate a waveform but I discovered with a digital oscilloscope that there are glitches on the output signal Is this normal When it switches from one voltage to another any DAC produces glitches due to released charges The largest glitches occur when the most significant bit MSB of the D A code switches You can use a lowpass deglitching filter to remove some of these glitches depending on the frequency and nature of your output signal In addition if you are using thi
81. tions of this document without prior notice to holders of this edition The reader should consult National Instruments if errors are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse
82. to code and appears as distortion in the frequency spectrum Each analog output channel contains a reglitch circuit that generates uniform glitch energy at every code rather than large glitches at the major code transitions This uniform glitch energy appears as a multiple of the update rate in the frequency spectrum Notice that this reglitch circuit does not eliminate the glitches it only makes them more uniform in size By default reglitching is disabled for all channels however you can use NI DAQ to independently enable reglitching for each channel 6711 6713 6715 User Manual The 671X device contains eight lines of digital I O for general purpose use You can individually software configure each line for either input or output At system startup and reset the digital I O ports are all high impedance The hardware up down control for general purpose counters 0 and 1 are connected onboard to DIO6 and DIO7 respectively Thus you can use DIO6 and DIO7 to control the general purpose counters The up down control signals are input only and do not affect the operation of the DIO lines 3 4 www ni com Chapter 3 Hardware Overview Timing Signal Routing The DAQ STC provides a very flexible interface for connecting timing signals to other devices or external circuitry The 6711 6713 device uses the RTSI bus to interconnect timing signals between devices PCI PX1I CompactPCI and the Programmable Function Input PFI pins on the I O
83. u use a PXI compatible plug in device in a standard CompactPCI chassis you cannot use PX I specific functions but you can still use the basic plug in device functions For example the PXI trigger bus on your 6711 6713 device is available in a PXI chassis but not in a CompactPCI chassis The CompactPCI specification permits vendors to develop sub buses that coexist with the basic PCI interface on the CompactPCI bus Compatible operation is not guaranteed between CompactPCI devices with different sub buses nor between CompactPCI devices with sub buses and PXI The standard implementation for CompactPCI does not include these sub buses Your 6711 6713 device will work in any standard CompactPCI chassis adhering to the PICMG CompactPCI 2 0 R2 1 document PXI specific features RTSI bus trigger RTSI Clock and Serial Communication are implemented on the J2 connector of the CompactPCI bus Table 1 1 lists the J2 pins used by your PXI CompactPCI 671 1 6713 1 2 www ni com Chapter 1 Introduction which is compatible with any CompactPCI chassis with a sub bus that does not drive these lines Even if the sub bus is capable of driving these lines the 6711 6713 is still compatible as long as those pins on the sub bus are disabled by default and are never enabled Damage can result if these lines are driven by the sub bus Table 1 1 PXI 6711 6713 J2 Pin Assignment 6711 6713 Signal PXI Pin Name PXI J2 Pin Number RTSI Trigger lt
84. utput and general purpose counter timer functions These groups include a total of seven 24 bit and three 16 bit counters and a maximum timing resolution of 50 ns The analog input section of the DAQ STC is unused by the 671X National Instruments Corporation 1 1 6711 6713 6715 User Manual Chapter 1 Introduction PCI PX1 Compact PCI 6711 6713 only Often with other DAQ devices you cannot easily synchronize several measurement functions to a common trigger or timing event The PXI CompactPCI 67 1 1 6713 device has the Real Time System Integration RTSI bus to solve this problem The RTSI bus consists of our RTSI bus interface and a ribbon cable to route timing and trigger signals between several functions on as many as five DAQ devices in your computer If you are using the PXI 6711 6713 in a PXI chassis RTSI lines known as the PXI trigger bus are part of the backplane therefore you do not need the RTSI cable for system triggering and timing on the PXI DAQCard 6715 only The DAQCard 6715 provides access to timing and triggering signals through the I O connector for synchronization to other DAQ devices or timing signals Detailed specifications of the 671X device are in Appendix A Specifications Using PXI with CompactPCI 6711 6713 6715 User Manual PXI CompactPCI 67 11 6713 Only Using PXI compatible products with standard CompactPCI products is an important feature provided by the PXI Specification revision 1 0 If yo
85. utput i Timing Control Bus Analog Input Timing Control Interface DAQ STC Digital VO i PFI Trigger Timing Counter Timing O Digital 1 O 8 Bus FPGA interface Address Control Digital Thermometer RTSI Bus Interface National Instruments Corporation Figure 3 2 6715 Block Diagram 3 3 6711 6713 6715 User Manual Chapter 3 Hardware Overview Analog Output The 6711 has four channels and the 6713 6715 has eight channels of voltage output at the I O connector The reference for the analog output circuitry is software selectable per channel The reference can be either internal or external whereas the range is always bipolar This means that you can output signals up to 10 V with internal reference selected or EXTREF voltage with external reference selected Analog Output Reference Selection You can connect each D A converter DAC to the internal reference of 10 V or to the external reference signal connected to the external reference EXTREF pin on the I O connector This signal applied to EXTREF should be within 11 V of AOGND You can configure each channel to use either internal or external reference The default reference value selection is internal reference Analog Output Reglitch Selection Digital 1 0 In normal operation a DAC output will glitch whenever it is updated with a new value The glitch energy differs from code

DAQ 6711/6713/6715 User Manual

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