Multi-Protocol PCI Board Instructions
Contents
1. 1T DDC Data Device Corporation Multi Protocol PCI Board Instructions Version 1 0 May 1999 The information provided in this document is believed to be accurate however no responsibility is assumed by for its use and no license or rights are granted by implication or otherwise in connection therewith Specifications are subject to change without notice TABLE OF CONTENTS Paragraph INDEX Page 1 0 Package Contents 2 1 1 Features 3 1 2 Description 3 2 0 Installation 4 2 1 Inspection 4 22 System Requirements 4 2 3 Coupling Transformer Jumpers 4 2 4 Hardwired RT Address Jumpers 5 3 0 Address Map 6 4 0 Hardware Description 7 4 1 Clock t 8 4 2 Pci To Local Bus Bridge 8 4 3 NHi 15382ET Terminals 8 5 0 On Line Help 8 1 0 Package Contents One PCI board Instructions Software Disks WindowsNT 95 98 Filght Deck Software Qukstart doc New1582 doc Flight Deck is menu driven GUI software which controls the PCI board and all the functions of the multi protocol terminal s on the board Qukstart doc is a WORD97 document which demonstrates the use of Flight Deck New1582 doc is the manual for the NHi 15382et terminal s which are on the PCI board This isa WORD97 document 1 1 FEATURES e Mil Std 1553 and Multi protocol PCI Interface Card e One or Two Independent Dual redundant Multi protocol BC RT MTs on a PCI card e 1553B Notice 2 STANAG 3838 1760 3818 EFA etc e 64K x 16 Shared RAM for each dual BC RT MT e Prog2. e design and manufacture of high reliability data interface products motion control and solid state power controllers for aerospace defense and industrial automation Inside the U S Call Toll Free 1 800 DDC 5757 Headquarters and Main Plant 105 Wilbur Place Bohemia NY 11716 2426 Tel 631 567 5600 Fax 631 567 7358 Toll Free Customer Service 1 800 DDC 5757 Web site www ddc web com Outside the U S Call 1 631 567 5600 United Kingdom DDC U K LTD Mill Reef House 9 14 Cheap Street Newbury Berkshire RG14 5DD England Tel 44 1635 811140 Fax 44 1635 32264 France DDC Electronique 10 Rue Carle Hebert 92400 Courbevoie France Tel 33 1 41 16 3424 Fax 33 1 41 16 3425 Germany DDC Elektronik GmbH Triebstrasse 3 D 80993 Munchen Germany Tel 49 0 89 15 00 12 11 Fax 49 0 89 15 00 12 22 Japan DDC Electronics K K Dai ichi Magami Bldg 8F 1 5 Koraku 1 chome Bunkyo ku Tokyo 112 0004 Japan Tel 81 3 3814 7688 Fax 81 3 3814 7689 Web site www ddcjapan co jp Asia Data Device Corporation RO Registered in Singapore Blk 327 Hougang Ave 5 05 164 Singapore 530327 Tel 65 6489 4801 The information in this Manual is believed to be accurate however no responsibility is assumed by Data Device Corporation for its use and no license or rights are granted by implication or otherwise in connection therewith Specifications are subject to change without notice
3. ng container may be utilized in the event that the card has to be returned due to failure or damage 2 2 System Requirements SYSTEM REQUIREMENTS PC with PCI Bus Windows95 98 NT Hard disk Color Monitor Follow these precautions before installing the card inside your PC Remove power to the PC before opening the top cover Make the necessary switch and jumper selections for your application as detailed in this manual and then plug the card into an available slot on the motherboard The card has been delivered from the factory with the folowwing default settings IRQ from the terminals are software disabled Buses are jumpered for Stub coupling via jumper blocks Hardwire RT address 01 and 02 for terminals 1 and 2 respectively via jumper blocks Follow the installation instructions in file LOAD95 TXT or LOADNT TXT REMOVE POWER TO THE PC WHEN REMOVING OR INSERTING THE CARD INTO THE PC 2 3 Coupling Transformer Jumpers The card can be configured for either direct or transformer coupling via jumpers JP13 JP20 For terminal 1 jumpers JP13 and JP14 are for Bus A jumpers JP15 and JP16 are for Bus B For terminal 2 jumpers JP17 and JP18 are for Bus A jumpers JP19 and JP20 are for Bus B The jumper configuration for the coupling transformer for each terminal is shown below Jumper Transformer Coupling Direct Coupling JP13 e e o o spi e 4 E e IPAS 3 JP16 e olj e o o JP17 e gt e ele JP18 e olj e
4. o o JP19 e o ejo JP20 e olj e o o Note In the above illustration position the PCI card with the component side up and the Bus connectors are on your left Both Bus A and Bus B of each terminal should be configured the same way to avoid any potential bus mismatch 2 4 Hardwired RT Address Jumpers Each of the Terminals can be given a unique Remote Terminal RT hardwire address via jumper selection The configuration for terminal 1 with an RT address of 1 and odd parity is shown below JP3 JP2 JP1 JP12 JP11 JP10 Parity A4 A3 A2 Al AO wy E eogaos The configuration for terminal 2 with an RT address of 2 and odd parity is shown below JP9 JP8 JP7 JP6 JP5 JP4 Parity A4 A3 A2 Al AO se a e e e e t e al on a e e Note In the above illustration position the PCI card with the component side up and the Bus connectors are on your left 1 is at the top of the jumper block 3 0 ADDRESS MAP The following memory map information is not generally required by a user unless custom software is being developed for the NHi PCI card The NHi Filght Deck Windows software handles all memory allocation and accesses Each terminal on the 15503 card appears to the host as 64K words of contiguous memory The address map for each terminal is shown below ADDRESS in words 0 29 Internal Control and Status registers 30 External RT address Command outpin pins 31 Not Used 32 35 Not Used 64 65535 Shared RAM accessed
5. on the Host I O bus The following address map table defines all addresses relevant to the user The addresses are offsets from the base address as selected by the user ADDRESS Base 0 Base 1 Base 2 Base 3 Base 3 Base 3 Base 4 Base 4 Base 4 Base 5 Base 6 Base 7 Base 8 Base 8 Base 9 Base 10 Base 11 Base 12 Base 13 Base 14 Base 15 Base 16 Base 17 Base 18 Base 19 Base 20 Base 21 Base 22 Base 23 Base 24 Base 25 Base 26 Base 27 Base 28 Base 29 Base 30 Base 30 Base 31 CONTENTS OPERATION Control Register Pointer Table Address Register Basic Status Register IMR lower byte IVR upper byte IRR upper byte IVR lower byte AVR upper byte Configuration Register 2 upper byte BC MT only RTC_ High RTC_ Low RTC Control Register FIFO Read FIFO Reset both bytes Configuration Register 1 Reserved Last Command Register Last Status Register Frame A Msg List Addr Block A Start Address Frame A Length Msg List Len Block A End Addr Reset RT both bytes Frame B Msg List Addr Block B Start Address Frame B Length Block B End Encoder Status Register Condition Register BC Frame Gap Word Monitor End of Frame Options Configuration Register 3 Message Monitor Address Filter 1 0 15 Encoder Data Register Encoder Data TX Request both bytes Encoder CMD TX Req
6. rammable BC Gap Times e BC Frame Auto Repeat e RT Data Buffering e RT Separate Broadcast Data Tables e Monitor Command Filtering e Simultaneous RT Monitor e Programmable Interrupts e Low cost solution for 1553B protocol based testing e On board watchdog timer e Time tag with programmable resolution e Programmable real time clock e Switch selectable interrupt levels e Low power consumption 1 2 Description The NHI 15503 is a PCI card which contains one or two completely independent 1553 interfaces Each interface is an NHi 15382ET multi protocol MCM which can operate as an RT BC or MT Each ET includes two monolithic transceivers a protocol asic and 64K wordsof shared RAM Double buffering of the shared RAM enables simultaneous message preparation and 1553 bus transfers All modes of operation access data tables via pointers residing in RAM which facilitates multiple buffering This allows buffers to change without moving data and promotes efficient use of RAM space The data tables have programmable sizes and locations The invisibility of memory when the card is not active prevents inadvertent access during power on self test of the PC or by any other process 2 0 INSTALLATION 2 1 Inspection The card has been thoroughly tested and inspected before shipment After removing the card from the packing container please retain the container as it may be used to store the card when not installed in the computer The packi
7. uest both bytes Message Monitor Address Filter 2 16 31 Word Monitor Last Address Block A Word Monitor Last Address Block B Reserved External RT Address Buffer lower byte Command Output Pins VO Tag Register Tn order to write to addresses 23 24 and 25 the ET must be in loopback in the RT mode see Control Register in the Enhanced Terminal Products User s Manual for details 2 lt 7 meg esegas ss R W R W R W 4 0 HARDWARE DESCRIPTION 4 1 Clock A 20 Mhz oscillator U4 is used to provide the required clocks for the NHi 15503 PCI Card 4 2 PCI To Local Bus Bridge A PLX9050 chip is used as the PCI to local bus bridge It interfaces with the two NHi ET s and and Altera EPM7064 pld The EPM7064 connects the local bus and control signals to each NHi ET 4 3 NHi 15382ET Terminals The PCI card contains two NHi 15382ET terminals which function as a BC MT RT or an MT RT See the NHi Enhanced Terminals Manual for a full description 5 0 On Line Help On Line help is available for all menu items and dialog boxes Use the left mouse button to drag the Question Mark to the item requiring help then release the button over that item The help dialog will appesr in the upper left screen area DATA DEVICE CORPORATION REGISTERED TO ISO 9001 2008 AS9100C 2009 01 EN9100 2009 JIS Q9100 2009 FILE NO 10001296 ASH09 The first choice for more than 45 years DDC DDC is the world leader in th
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