Digital PFC and dual FOC MC integration
Contents
1. p U0 scrlsLccal ION cun En ERE zi Control Secton Jp cov beuuoiun2m222j 2s02z i AD ADC ADC 1 channel channel channel Mew Duty ee 1 pc I I r n AC AC I Y uu Pl Regulator Seno PI Regulator Vocrer N Verr Vpr gt N gt D IN gt Voltage Error TV La fM Current Error i Compensator Compensator 2 2 2 cccccll 2 2 2 2 c z AMO6672v1 The voltage error compensator regulates the output DC voltage at the target reference VDCREF Its output is then used as a scaling factor for the input Vac This product constitutes the current reference input IACREF for the current error compensator operating at 40 kHz The output of this last PI is the actual duty cycle applied at the gate of the power MOSFET transistor Q The voltage error compensator uses a frequency of 100 Hz in line with the Vdc ripple that has this frequency The current error compensator uses a frequency of 40 kHz which is the frequency at which the system gets the new converted values of all the necessary signals STM32 peripheral utilization The following peripherals are used to implement the digital PFC e TIMG its frequency is fixed at 80 kHz CH4 is used to drive the PFC MOSFET whereas CH3 is used as the start trigger for ADC1 2 e ADC1 converts the output DC voltage V2. OR ADC1 2 SUB PRIORITY 0 TY 2 In the private define of the stm32f10x_Timebase c module ifndef define else define endif define PFC_ENABLE SYSTICK_PRE_EMPTION_PR ORITY 3 SYSTICK_PRE_EMPTION_PR SYSTICK_SUB_PRIORITY 0 ORITY 4 The other IRQ priorities related to the dual FOC MC are not changed Application example This section lists the software and hardware requirements for the system to run correctly and also describes the connection topology and performances obtained Doc ID 17180 Rev 1 25 31 www BDTIC com ST Integration principles and description AN3165 4 4 1 Software and hardware requirements The integrated firmware has been tested with the following software and hardware elements e Software requirements IAR embedded workbench IDE v 5 20 STM32 standard library FWLib v 2 0 1 STM32 Dual FOC MC Digital PFC Demo v 1 0 e Hardware requirements MB459 3 ph inverter board for main motor STEVAL IHM021V1 modified for single shunt as 3 ph inverter board for sub motor Two 3 ph motors STEVAL ISF002V1 as PFC power board Three 34 pin flat cables for MC connectors AC power source able to provide 185 230 Vrms at 50 Hz with 1000 VAC Dual motor control demonstration board STEVAL IHMO22V 1 DC power supply 5 V 2 A J Link ARM dongle USB cable type A B plugs 20 pin flat cable for JTAG PC e Forthe main moto
3. Integration principles and description AN3165 4 4 1 4 2 4 2 1 4 2 2 18 31 Integration principles and description Aim The goal of this integration firmware is to merge the two sets of firmware described previously into one single set that will manage both the dual FOC MC and the digital PFC through one single STM32 MCU Figure 10 Integrated firmware elements Digital PFC Part STM32 Dual FOC MC plus Digital PFC Integrated FW Demo AMO6680v1 Resource constraints Several elements must be checked before the firmware can be integrated e Availability of CPU load e Conflicts between peripherals e Conflicts between ports e IRQ priorities CPU load From the findings described in Section 2 6 and Section 3 5 it has been demonstrated that there is sufficient CPU load available The STM32 Digital PFC has a CPU load of 17 at 40 kHz while it is of 58 at 12 kHz for the STM32 dual FOC MC software demonstrator Conflicts between peripherals From Section 2 4 and Section 3 3 it is deduced that both firmware sets use ADC1 and ADC2 Table 4 explains their use Doc ID 17180 Rev 1 ky www BDTIC com ST AN3165 Integration principles and description Table 4 Use of A D converters by both firmware sets Digital PFC Dual FOC MC Control loop 40 kHz 6 kHz frequency Regular conversions Injected conversions 13 conversion group 21d conversion group Every conversion A
4. Ti AN3165 Sf Application note Digital PFC and dual FOC MC integration July 2010 Introduction This application note explains how to integrate two sets of firmware to manage a digital PFC and a dual field oriented control FOC motor control driver by means of a high density STM32 The purpose is to evaluate the potentiality of an STM32 to control a high power PFC with performances comparable to a standard continuous mode PFC monolithic IC while allotting sufficient micro resources such as program memory and CPU computational capabilities to make other complex operations such as the simultaneous driving of two 3 phase field oriented control motors in sensorless and single shunt mode Section 2 and Section 3 briefly describe the implementation of a digital PFC and dual motor control FOC with an STM32 while Section 4 describes how to integrate these two parts in a single firmware with the main focus on the use of the STM32 resources and constraints Doc ID 17180 Rev 1 1 31 www st com www BDTIC com ST Contents AN3165 Contents 1 Safety and operating instructions leeessse 6 1 1 General sauce UR c arte aae E a d arcas Ro PRORA EUR a Meade 6 1 2 Intended use of the demonstration board l l ills 6 1 3 Installation of the demonstration board llllllllllsun 6 1 4 Electronic connection l lililililelelele ees 6 1 5 Board operation a isa cost d by SER Sad yee edhe eh
5. STM32 digital PFC connections for the boost and control stages 10 Use of peripherals for STM32 digital PFC 20 0 ccc eens 11 Digital PFC timing 2 0 0 0 62 cee 12 STM32 dual FOC MC topology 0 00 teens 13 Control strategy block diagram for STM32 dual FOC MC 0 annann 14 STM32 peripherals used by dual FOC MC 0 00 cee 15 ADC and FOC execution timing diagram 000 cece 16 Free MCU time vs PWM frequency in dual FOC MC 000 0c cee eee 16 Integrated firmware elements 000 eee 18 Voltage management timing in STM32 dual FOC MC 0000 eee eee 19 Voltage management timing in integrated firmware 0000 c eee ee 20 Triggers for STM32 ADC3 1 tte 20 Connection topology for integration of dual FOC MC and digital PFC 27 System running a a aa teas 27 Modified input stage for 3 ph inverter boards 000 0 cee ee 28 Doc ID 17180 Rev 1 5 31 www BDTIC com ST Safety and operating instructions AN3165 1 1 1 2 1 3 1 4 6 31 Safety and operating instructions General During assembly and operation the PFC power board poses several inherent hazards including bare wires moving or rotating parts and hot surfaces Serious personal injury and damage to property may occur if the kit or its components are used or installed incorrectly All operations involving transportation i
6. O pins 23 2 31 Doc ID 17180 Rev 1 Ti www BDTIC com ST AN3165 Contents 4 3 3 Firmware modifications to set IRQ priorities 04 24 4 4 Application example 02 ee 25 4 4 1 Software and hardware requirements llle 26 4 4 2 Running of the system 0 0 0c eee ee 26 4 4 3 3 ph inverter board input stage modification 0 28 5 ipn eI ATTI 29 5 1 4 TNIOU CIE crTmUTST 29 6 Revision history ciao deine prio RARCACRCR CH CE ae RR de ea eee ad e 30 y Doc ID 17180 Rev 1 3 31 www BDTIC com ST List of tables AN3165 List of tables Table 1 STM32F103ZE pin description 0 0 00 cet ae 11 Table 2 STM32 digital PFC module summary liliis 12 Table 3 STM32 dual FOC MC module data summary ees 17 Table 4 Use of A D converters by both firmware sets 19 Table 5 Used interrupts and their priorities for integrated firmware llle 21 Table 6 System performances llssisleeee eee 28 Table 7 Document revision history llseleeleeee e mr 30 4 31 Doc ID 17180 Rev 1 ky www BDTIC com ST AN3165 List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Block representation of STM32 digital PFC concept 000 eee eee 9
7. PE Em ERES 7 2 STM32 digital PFC 5 ss rk kyRr e RR mms x eben E X ETE 8 2 1 IMtMOGUCTION Tc Sa ieee ca hips ere nae Sa aes 8 2 2 System OVBIVIGW cen weweesietdseceeetedn ERES RU RUNG deere teehee da 8 2 3 System architecture vo cei ceca cd es eS aee eH Res ews eee ee ne AG TE 9 2 4 STM32 peripheral utilization llle 10 2 5 uo coe eats obs Be aE ee aa ee eee ok aes E 11 2 6 CPU load and memory size 000 eee 12 3 STM32 dual motor field oriented control 13 3 1 s u 7 AT 13 3 2 Dual field oriented control motor driver strategy Lune 13 3 3 PenpheralS SUC sta aan Dub aw eaa Se danke Pee M tuni diera de 15 3 4 lun 02203 6cxee yea tne enrees Se eceh cee Ges e eee AE EAA anaes 16 3 5 GPU load and memory Size iis sss suo waked bas bee ee eee eee ees 16 4 Integration principles and description 18 4 1 PAN stink Seer eke eS a ee Rh eke aa ee baw Wee aed Se x at hed Ak ok 18 4 2 Resource constraints 0 000 c ces 18 4 2 1 CPU load ind oe Se rhe eRe tace ut do p he SOR dnte deg eda 18 4 2 2 Conflicts between peripherals 0 000 e eee eee 18 4 2 3 Conflicts between I O pins liliis 20 4 2 4 IRQ priorities 22 aiaia aa a ee 21 4 3 Brief overview of firmware integration 000 eee 21 4 3 1 Firmware modifications to resolve conflicts between peripherals 22 4 3 2 Firmware modifications to resolve conflicts between I
8. SelectSlaveMode TIM5 TIM SlaveMode Trigger TIM2 is used by the dual FOC MC part to synchronize all timers In the main c module int main void ifdef PFC ENABLE TIM5 Configuration dendif SVPWM 1ShuntInit TIM5_Configuration must be called before any initializations performed by SVPWM_1ShuntInit In the stm32f10x_svpwm_1shunt c module void SVPWMUpdateEvent_TIM8 void ifdef PFC_ENABLE TIM5 gt CCMR2 amp OxFF8F TIM5 gt CCMR2 TIM8 gt CCMR2 gt gt 8 endif ifdef PFC_ENABLE TIM5 gt CCR3 TIM8 gt CCR4 endif ifndef PFC_ENABLE ADC3 gt CR2 ADC_ExternalTrigInjecConv_T8_CC4 else ADC3 gt CR2 ADC_ExternalTrigInjecConv_T5_TRGO endif Firmware modifications to set IRQ priorities The following is the code to resolve the conflicts outlined in Section 4 2 4 In the private define of the stm32f10x_svpwm_ishunt c module ifndef PFC_ENABLE define ADC3 PRE EMPTION PRIORITY 1 else define ADC3 PRE EMPTION PRIORITY 2 4 Doc ID 17180 Rev 1 www BDTIC com ST AN3165 Integration principles and description 4 4 endif define ifndef define else define endif define ADC3_SUB_PRIORITY 0 PFC_ENABLE ADC1 2 PRE EMPTION PR OR TY 1 ADC1 2 PRE EMPTION PR
9. connection scheme between the STEVAL IHMO22V1 board and two inverter stage boards for performing simultaneous two motor FOC control Note For more information refer to UM0683 UM0686 and UMO0688 user manuals Figure 5 STM32 dual FOC MC topology Main Motor STEVAL IHM022V1 Control Board In Iw n wc 3 ph Motor Sub Motor AMO06675v1 3 2 Dual field oriented control motor driver strategy Figure 6 shows the block diagram of the dual motor FOC mechanism The phase currents of the main and sub motor are sampled during each FOC cycle The strategy adopted for the current sampling and execution of the FOC algorithm is to dedicate one PWM period to each motor halving in this way the execution rate of the FOC with respect to single motor driving a See Chapter 5 References ki Doc ID 17180 Rev 1 13 31 www BDTIC com ST STM32 dual motor field oriented control AN3165 Dual motor driving is possible by way of two advanced PWM timers TIM1 and TIM8 inside the high density version of the STM32 microcontroller STM32F103xC D E These two timers are kept synchronous using the master slave feature of each timer peripheral present in the microcontroller The timers must be synchronized to ensure that the current sampling occurs during the proper PWM period The single shunt solution implemented with the ST patented method expects two ADC conversions for each motor to sample the phase currents These t
10. in Section 4 2 2 and demonstrates how the dual FOC MC part reads the bus voltages by means of the PFC part In the stm32f10x_svpwm_1shunt c module void SVPWMGetBusSampling void pMotor _GET_MOTOR_POINTER MAIN_MOTOR ifndef PFC_ENABLE pMotor gt pPowerStage_Vars gt h_ADCBusvolt ADC_GetInjectedConversionValue pMotor pBusVoltageADC ADC InjectedChannel 1 else pMotor gt pPowerStage_Vars gt h_ADCBusvolt Get_Vdc_main lt lt 3 to fit ADC injected configuration endif pMotor GET MOTOR POINTER SUB MOTOR ifndef PFC ENABLE pMotor pPowerStage Vars h ADCBusvolt ADC GetInjectedConversionValue pMotor pBusVoltageADC ADC InjectedChannel 1 pMotor pPowerStage Vars h ADCTemp z ADC_GetConversionValue pMotor gt pTemperatureADC gt gt 1 else pMotor gt pPowerStage_Vars gt h_ADCBusvolt Get_Vdc_sub lt lt 3 to fit ADC injected configuration endif The function Get Vdc main exports the converted VDC value which is also the value of the main motor bus voltage The function Get Vdc sub exports the converted value of the sub motor bus voltage Both are managed through the PFC part q Doc ID 17180 Rev 1 www BDTIC com ST AN3165 Integration principles and description Below is t
11. 80 Rev 1 7 31 www BDTIC com ST STM32 digital PFC AN3165 2 2 1 2 2 Note 8 31 STM32 digital PFC Introduction A power factor correction PFC also known as a power factor controller is a feature that reduces the amount of reactive power generated by a non linear load Loads such as electrical motors distort the current drawn from the system and in such cases a power factor correction may be used to counteract the distortion and raise the power factor Reactive power operates at right angles to true power and energizes the magnetic field Reactive power has no real value for an electronic device but electric companies charge for both true and reactive power resulting in unnecessary charges PFC is a required feature for power supplies shipped to or within Europe In a PFC the power factor is the ratio of the true power divided by the reactive power The value of the power factor is between 0 and 1 If the power factor is above 0 8 the device is using power efficiently A standard power supply has a power factor of 0 70 to 0 75 and a power supply with PFC has a power factor of 0 95 to 0 99 PFC equipment is used to reduce the reactive power produced by fluorescent and high bay lighting arc furnaces induction welders and equipment that uses electrical motors System overview This demonstration board implements a digital control for a high power PFC controlled by an STM32 It has been designed to offer high
12. DC1 VDC IAC Vinmain_motor ADC2 Dummy VAC Vinsub motor The data in Table 4 suggests maintaining the PFC firmware sampling strategy and adding the sub motor voltage bus conversion in the first group in place of the dummy value It is necessary to specify when the firmware of the MC part has to use these values Figure 11 Voltage management timing in STM32 dual FOC MC TIM1 UP ADC1 2 IRQ Service Routine ADGEDE Voltage Management ADC IRQ gt ADC1 start ADC2 start 6 kHz AMO6681v1 As shown in Figure 11 with the dual MC firmware the TIM1 UP event triggers the starts for ADC1 and ADC2 At the end of the conversion the related ADC1 2 IRQ routine processes the acquired bus voltages of the main and sub motor stages In the integrated firmware since the two bus voltages are already converted by the firmware of the PFC part they have to be passed to the MC part at the correct moment like the dual MC firmware has done that is immediately after the TIM1 update event To replicate this behavior an auxiliary timer TIM4 is used that processes the bus voltages after the TIM1 UP event In practice the code executed in the ADC1 2 IRQ routine in the dual FOC MC part is now executed inside the TIM4 IRQ routine ki Doc ID 17180 Rev 1 19 31 www BDTIC com ST Integration principles and description AN3165 4 2 3 20 31 Figure 12 Voltage management timing in integrated firmwa
13. O06685v1 ky Doc ID 17180 Rev 1 27 31 www BDTIC com ST Integration principles and description AN3165 4 4 3 28 31 The following table shows the performances obtained Table 6 System performances Input voltage Output voltage Input power P F Current T H D 185 Vrms 50 Hz 350 Vdc 850 W 0 996 2 7 3 ph inverter board input stage modification When all boards are connected as shown in Figure 14 the 3 ph inverter boards are supplied by a regulated DC voltage and are intended as parts of a whole interconnected system Therefore their input stage must be modified as shown in Figure 16 Figure 16 Modified input stage for 3 ph inverter boards Diode Bridge ial amp 4 AMO6686v1 Doc ID 17180 Rev 1 ky www BDTIC com ST AN3165 References 5 References e UM0877 e UM0683 e UMO686 e UMO688 5 1 Useful links e STEVAL ISF002V1 1 4 kW Digital PFC power board based on STW23NM60N and TD352 Can be found at http www st com stonline products literature bd 1 7282 steval isf002v1 htm e STEVAL IHMO22V1 High density dual motor control demonstration board based on the STM32F103ZE microcontroller Can be found at http www st com stonline products literature bd 16072 steval ihm022v1 htm ki Doc ID 17180 Rev 1 29 31 www BDTIC com ST Revision history AN3165 6 Revision history Table 7 Document revision history Date Revi
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15. at 72 MHz takes 4 27 us to execute the code of the PFC Routine By referring this time to a PFC control loop time of 25 us 40 kHz the CPU load can be computed as Equation 1 CPU load 4 27 us 1796 25 us Table 2 reports the size of the PFC o object module in terms of Flash and RAM memory sizes Table 2 STM32 digital PFC module summary Read only code Flash Read only data Flash Read write data RAM 2088 214 100 Doc ID 17180 Rev 1 ky www BDTIC com ST AN3165 STM32 dual motor field oriented control 3 STM32 dual motor field oriented control 3 1 Overview The firmware running on the STEVAL IHMO22V1 demonstration board performs dual motor control operations in simultaneous mode Up to two motors can be driven in field oriented control FOC single shunt resistor and in sensorless mode To begin with the dual motor control firmware uses the FOC routines of the STM32 PMSM library version 2 0 firmware package and hence shares the same principles as when the motor drive is configured with user parameters The software architecture has been extended to treat each motor as an independent instance splitting the controls for each one in a completely independent manner To emphasize this concept an embedded UI LCD TFT 320 x 240 display and 5 position joystick allows the user to adjust the motor control parameters in real time during the motors operation The following figure shows a typical
16. cted group AMO6683v1 Figure 13 shows the trigger sources for the injected conversion of ADC3 Signals from TIM1 and TIM8 are already used TIMA4 CHS is mapped to pins used by the dual FOC MC TIM5 CHA is mapped to PAS which is used by the digital PFC see Table 1 Doc ID 17180 Rev 1 ky www BDTIC com ST AN3165 Integration principles and description Therefore TIM5_TRGO has to be selected as the start trigger source for the injected conversion of ADC3 TIM5_CC3 is mapped to TIM5_TRGO for internal purposes only In the integrated firmware TIM5 CC3 therefore replaces the function of TIM8_CH4 in the dual FOC MC part 4 2 4 IRQ priorities To set the IRQ priorities when the two parts are merged it must be taken into account that the execution time of the FOC routine lasts longer than that of the PFC routine Therefore this last routine has to be able to interrupt the FOC routine As such priority must be given to IRQs used for managing protection conditions or synchronizations Table 5 shows the interrupts and their priorities for the integrated firmware with O being the highest priority Table 5 Used interrupts and their priorities for integrated firmware Peripheral IRQ use Pre emption Sub priority priority EXTI Line1 Overcurrent protection 0 0 TIM1 BRK Emergency condition for main motor 0 0 TIM8 BRK Emergency condition for sub motor 0 0 TIM1 UP Synchronization for ma
17. ction 27 PD 10 Drives the relay to bypass the resistor when there is in rush 21 current at start up PE 01 PFC hardware overcurrent detection 2 2 5 Timing The signal output from TIM3_CH4 is applied to the power MOSFET gate and its frequency is fixed at 80 kHz its duty cycle varies and is linked to the control strategy of the digital PFC TIM3_CHS is used to trigger ADC1 a conversion is started at the end of each ON period The duty cycle of TIM3_CHS is equal to half that of TIM3_CH4 but never lower than 1 us to avoid invalid conversions due to noise generated by the switching of the power MOSFET Figure 4 shows the triggering mechanism of TIM3 ADC and DMA1 ky Doc ID 17180 Rev 1 11 31 www BDTIC com ST STM32 digital PFC AN3165 2 6 12 31 Figure 4 Digital PFC timing DCA n DCA n DCA n 1 DCA n 1 TIM3 CH4 PFC MOSFET PWM fixed frequency of 80 kHz DC3 n DC3 n DC3 n 1 DC3 n 1 TIM3 CH3 to trigger ADC1 fixed frequency of 80 kHz A D Conversion ADCs End ADCs End ADCs End ADCs End ADC1 Vdc ADC1 lac ADC1 Vdc ADC1 lac ADC2 ADC2 Vac ADC2 ADC2 Vac DMA1_CH1 IRQ DMA1_CH1 IRQ ADCs Start ADCs Start ADCs Start ADCs Start DMA1_CH1 Service Routine PFC Routine New Duty Cycle New Duty Cycle Legend DC3 duty cycle of TIM3_CH3 range 1us DC4 2 DC4 duty cycle of TIM3 CHA AMO06674v1 CPU load and memory size Through experimental measurements the CPU operating
18. dc and inductor current lac alternatively e ADC2 converts a dummy value and input AC voltage Vac alternatively ADC2 is set as the slave of ADC1 for simultaneous conversions The dummy value is replaced with the sub motor bus voltage when this firmware is merged with the MC firmware e DMAt stores the converted values by means of its CH1 As soon as all values have been converted with a frequency of 40 kHz an IRQ is generated and the PFC routine is executed e EXTI LINE1 retrieves overcurrent information from the power section An IRQ is generated and the digital PFC is stopped if an overcurrent condition is detected Doc ID 17180 Rev 1 ky www BDTIC com ST AN3165 STM32 digital PFC Figure 3 Use of peripherals for STM32 digital PFC PFC MOSFET Driver New Check J Duty Cycle Protections OC3REF IRQ generation as is soon as the buffers are filled 40 KHz Trigger Output 32 bit buffer 1 ADC2 is slave of ADC1 for simultaneous conversions Over Current lngm w dummy Signal uw LINE1 AMO06673v1 Table 1 describes the STM32 pins and their purpose Table 1 STM32F103ZE pin description MCU pin Description MC PFC connector PAO3 Vdc PFCouputDCvolagg 14 PA 04 lac PFC current 24 PA 05 Vac input AC voltage 22 PC 09 PFC power MOSFET driver 29 PD 02 Vac zero crossing dete
19. de for PFC Switching frequency of 80 kHz Control loop frequency of 40 kHz Hardware overcurrent protection 14 3 A Software current limitation 13 A Software overvoltage protection 460 Vdc Software voltage limitation 435 Vdc Regulated DC output voltage with zero load Adjustable target value of output DC voltage by firmware Adjustable proportional and integral parameters for voltage and current by firmware Figure 1 Block representation of STM32 digital PFC concept 185 265 Vrms STEVAL ISF002V1 50Hz Digital PFC Board 415 Vdc MC Connector STEVAL IHMO22V1 Control Board 5 Vdc AMO6671v1 System architecture To perform a digital power factor correction the MCU of the control stage needs three input signals e Output DC voltage e Input AC voltage e Inductor current From these inputs the MCU control software modulates the duty cycle of the switching signal applied to the gate of the MOSFET transistor so that the AC input current is in phase with the input AC voltage Moreover the control strategy keeps the output DC voltage regulated at a stable value target output reference voltage Doc ID 17180 Rev 1 9 31 www BDTIC com ST STM32 digital PFC AN3165 2 4 10 31 Figure 2 STM32 digital PFC connections for the boost and control stages Power Section ro 11 U AC input 2 Cin jj lt S Y
20. e two synchronized timer counters The update points for each timer are indicated with a U The update point is the moment at which the computed values of the duty cycle registers become active To allow dual motor control each timer is updated every two PWM periods REP RATE 3 but not at the same time each update is shifted by one PWM period The trigger point for the ADC conversion occurs during the ACD triggering interval depicted by a red bar in Figure 8 The ADC s triggering interval related to a specific timer does not overlap the other so the samplings can be performed using the same ADC peripheral ADC3 Space for both FOC instructions must be guaranteed and the routines completed before the next corresponding update event 3 5 CPU load and memory size Figure 9 Free MCU time vs PWM frequency in dual FOC MC Real 2x1SH RP _ e Real 2x1SH RP Free uC Time m 8 16 PWM Freq kHz AMO06679v1 16 31 Doc ID 17180 Rev 1 ki www BDTIC com ST STM32 dual motor field oriented control AN3165 In the released code for the STM32 dual FOC MC software demonstrator the frequency of the PWM is set to 12 kHz Therefore according to Figure 9 the CPU load is approximately 52 Table 3 STM32 dual FOC MC module data summary Read only code Read only data Read write data 20932 1356 826 ky Doc ID 17180 Rev 1 17 31 www BDTIC com ST
21. el Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com Ly Doc ID 17180 Rev 1 31 31 www BDTIC com ST
22. he code for synchronizing TIM4 with TIM1 In the pfc c module void TIM4 Configuration void Selects TIM1 Output Trigger as input trigger for TIM4 TIM SelectInputTrigger TIM4 TIM TS ITRO Selects the Trigger Mode as Slave Mode for TIMA TIM_SelectSlaveMode TIM4 TIM SlaveMode Trigger As such the code executed in the ADC1_2 IRQ routine in the dual FOC MC part is now executed inside the TIM4_IRQ routine In the stm32f10x it c module void ADC1 2 IRQHandler void ifndef PFC_ENABLE i ADC1 gt SR amp ADC FLAG JEOC ADC FLAG JEOC Test if ADC3 JEOC is set It clear JEOC flag ADC1 gt SR u32 ADC FLAG JEOC SVPWMGetBusSampling j else endif void TIMA IRQHandler void SVPWMGetBusSampling 4 3 2 Firmware modifications to resolve conflicts between I O pins The following is the code to resolve the conflicts outlined in Section 4 2 3 and demonstrates how TIM5_CC3 replaces the function of TIM8_CH4 of the dual FOC MC part In the pfc c module void TIM5_Configuration void Selects TIM5 Output Trigger as OC3REF TIM SelectOutputTrigger TIM5 TIM_TRGOSource_OC3Ref Selects TIM2 Output Trigger as input trigger fot TIM5 ky Doc ID 17180 Rev 1 23 31 www BDTIC com ST Integration principles and description AN3165 Note Note 4 3 3 24 31 TIM SelectInputTrigger TIM5 TIM TS ITRO Selects the Trigger Mode as Slave Mode for TIM5 TIM
23. naging main motor 0 0 TIM8 UP Synchronization for managing sub motor 0 0 DMA1_CH1 PFC routine 1 0 TIM4 Manages bus voltages for MC 2 0 ADC 1 2 Optionally manages brake resistor 2 0 ADC3 FOC implementation for both main and sub motor 2 0 SYSTICK Timer for delays 4 0 4 3 Brief overview of firmware integration In this application the STM32 dual FOC MC demonstration software is intended as the host firmware The modules pfc c and pfc h of the STM32 digital PFC must be integrated into the host firmware Additionally all the modifications described in the previous sections must be added to the new code To initialize the PFC the following function has to be added PFC Initialization PFC_INIT In particular this function call has been added in the main c file of the host firmware and is called after each initialization of the dual FOC MC Likewise all modifications to the host firmware have been inserted inside control structures characterized by the key word PFC_ENABLE defined in the module pfc h Global define ky Doc ID 17180 Rev 1 21 31 www BDTIC com ST Integration principles and description AN3165 4 3 1 Note 22 31 define PFC_ENABLE When this function is enabled the built firmware will be the integration between the dual FOC MC and the digital PFC Firmware modifications to resolve conflicts between peripherals The following is the code to resolve the conflicts outlined
24. nd contacts e The board contains electro statically sensitive components that are prone to damage through improper use To avoid potential health risks ensure that the electrical components are not damaged in any way Electronic connection National accident prevention rules must be followed when working on the main power supply with another power supply or power board in general The electrical installation must be carried out in accordance with the appropriate requirements cross sectional areas of conductors fusing PE connections etc Doc ID 17180 Rev 1 ky www BDTIC com ST AN3165 Safety and operating instructions 1 5 Note Board operation It is advised to use an AC insulated and protected against overloads and short circuits during the evaluation test of the system compliance with technical equipment and accident prevention rules A correct load able to dissipate or in any case absorb and reuse the power delivered by the system must be used In the case of a resistive and dissipative dummy load attention should be given to the temperature that the load could reach Ensure the necessary equipment is provided to avoid hot surfaces and risk of fire during the tests fan water cooled load etc Do not touch the board or its components after disconnection from the voltage supply as several parts and power terminals which contain possibly energized capacitors need to be given time to discharge Doc ID 171
25. nstallation use and maintenance should be carried out by skilled technical personnel national accident prevention rules must be observed Skilled technical personnel refers to suitably qualified persons who are familiar with the installation use and maintenance of power electronic systems Warning The board operates directly from the mains is not galvanic insulated and provides high voltage DC levels at the output that can cause serious electric shock burns or death Hot surfaces on the board can also cause burns This board must only be used in a power laboratory by engineers and technicians who are experienced in power electronics technology and with adequate protection STMicroelectronics shall not be considered responsible for damages to equipment or persons Intended use of the demonstration board The system is designed for demonstration purposes only and must not be used for electrical installations or machinery Technical data and information concerning the supply conditions must be taken from the documentation provided and strictly observed Installation of the demonstration board The system s installation and cooling must be in accordance with the specifications and targeted application e Excessive strain on the board must be avoided In particular no components are to be bent or isolating distances altered during the course of transportation or handling e Nocontact must be made with other electronic components a
26. oltage of the sub motor ADC3 converts the currents and temperature of the main or sub motor DMA1 performs the single shunt for the main motor DMA2 performs the single shunt for the sub motor TIM8 generates the PWMs for controlling the sub motor currents Also triggers the The following figure shows the STM32 peripherals used by the dual FOC MC firmware Figure 7 STM32 peripherals used by dual FOC MC Main motor inverter VBus Main ttt d 3 5 streams DMA1 gt TIM1 VBus Sub ADC2 Trig 1 TRGO CH3 DAC Ff Trig 8 J Injected ostream TIM8 Current Main DMA2 Current Sub ADCS IT U1 EN Sub motor Roue y inverter a s Temp Main Bus voltage samplings Current and Temperature samplings en Sub AMO06677v1 Doc ID 17180 Rev 1 15 31 www BDTIC com ST STM32 dual motor field oriented control AN3165 3 4 Timing Figure 8 ADC and FOC execution timing diagram Pd d d Mi Mot fo ie iets Go Find or we SN S d Sy le Sel sy N A2 NENNEN Oo o zy Sk Pa Se Pi EN Second Motor N NA Z N Pd Noo TIM8 Single shunt P NS uU AN P d T U NUT i 4 Ain HL 355 1 li ADC Triggering interval E FOC Execution time Update ISR O ADC Setup Li AMO6678v1 The two triangular shaped signals represent th
27. performances in terms of PF THD and DC output voltage ripple Contrarily to monolithic ICs this digital approach facilitates the application of a sophisticated control algorithm and makes it easier to adjust system parameters to meet customer requirements The STM32 digital PFC hardware system is composed of two boards a digital PFC board STEVAL ISF002V1 that implements the boost stage of the PFC and a control board STEVAL IHMO22V1 based on the STM32F103ZE microcontroller that implements the control stage of the PFC The digital PFC board can be connected through an MC connector to several evaluation kits available from STMicroelectronics in particular those designed for motor control An on board OFF line switched mode power supply SMPS based on the VIPER12 is used to generate the 15 VDC voltages necessary to supply the drivers inside the power board This board provides 5 volts to any control stage supplied via the MC connector Refer to user manual UM0877 for a description of the STM32 digital PFC and an application example e Main system features Maximum output power 1400 W nput voltage range 185 230 Vrms 50 Hz Output voltage 415 Vdc 5 ripple PF up to 0 998 at nominal rated power Doc ID 17180 Rev 1 ky www BDTIC com ST AN3165 STM32 digital PFC 2 3 THD between 0 9 and 9 within entire operating range Boost topology for DC to DC converter Continuous conduction mo
28. r a 3 ph motor with the following specifications Type permanent magnet 3 ph motor Number of polar couples 2 Target speed 4000 rpm Target power 600 W Rg 2 85 Q Ls 18 mH e Forthe sub motor a 3 ph motor with the following specifications Type permanent magnet 3 ph motor Number of polar couples 3 Target speed 3200 rpm Target power 100 W Rs 1109 Ls 100 mH 4 4 2 Running of the system This section describes how to connect together the various hardware elements Figure 14 and shows the system performance 26 31 Doc ID 17180 Rev 1 ky www BDTIC com ST AN3165 Integration principles and description Figure 14 Connection topology for integration of dual FOC MC and digital PFC Main Motor Digital PFC Board STEVAL ISFOO2V1 Vac AC Power Source DC Power Supply Sub Motor USB cable AM06684v1 The regulated output DC voltage of the PFC is the input voltage for both 3 ph inverter boards For this reason Vdc has to be fixed to 350 V to be compliant with the input stage of the 3 ph inverter boards This Vdc value forces Vac to be within the range 185 230 Vrms so as to obtain a good PF Figure 15 is a screenshot of the system when it is running It shows e the bus voltage Vdc controlled by the PFC part e the input current lac e the main motors phase current e the sub motors phase current Figure 15 System running Main Motor Phase Current Mil AM
29. re TIM1 UP TIM4 IRQ Service Routine Voltage Management TIM4 UP TIM4 IRQ 6 kHz AMO6682v1 The dual FOC MC uses left aligned data for the injected group while the digital PFC uses right aligned data for the regular group Therefore the converted values coming from the code written for the digital PFC part have to be adjusted to fit the format of data used by the dual FOC MC part Conflicts between I O pins As described in Section 3 3 the dual FOC MC uses a DAC for debugging purposes Because the DAC takes control of PA4 DAC_OUT_1 and PA5 DAC OUT 2 it is not possible to use it the same pins are used by the digital PFC to read the PFC current and input AC voltage Another conflict is generated on the PC9 pin which represents both the TIM8_CH4 and TIM3_CH4 signal outputs for the dual FOC MC and digital PFC respectively TIM3_CH4 is used to drive the power MOSFET gate while TIM8_CH4 or better an edge commutation on it is used internally as the trigger input for the ADC3 start conversion Although TIM8_CH4 is used as an internal trigger for ADC3 disabling its output on the PC9 pin also disables its triggering functionality As such it is necessary to use another start trigger source for the injected conversion of ADC3 Figure 13 Triggers for STM32 ADC3 JEXTSEL 2 0 bits TIM1 TRGO TIM1_CH4 TIM4 CHS3 TIM8 CH2 TIM8 CH4 TIM5 TRGO TIMS CH4 Start trigger inje
30. sion Changes 27 Jul 2010 1 Initial release 30 31 Doc ID 17180 Rev 1 ky www BDTIC com ST AN3165 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRAN
31. wo conversions are normally performed within the first half of the PWM period or at most 3 5 us after that time During each FOC execution rate two PWM periods the values of the phase currents are sampled for one motor and the FOC algorithm related to that motor is executed The currents are therefore transformed with Clark and Park transformations torque and flux PID are executed and the voltage demand vector is computed using the reverse park transformations and circle limitation The value of the three duty cycles to be applied to the inverter and the sampling points for the current s conversion are computed from the voltage demand vector using the space vector modulation Depending on the selected firmware options the state observer can be used to estimate the rotor s position and speed The MTPA flux weakening and feed forward can also be executed Figure 6 Control strategy block diagram for STM32 dual FOC MC Power converter MAIN Target speed AMO06676v1 14 31 Doc ID 17180 Rev 1 ky www BDTIC com ST AN3165 STM32 dual motor field oriented control 3 3 Peripherals The following peripherals are used to implement the dual FOC MC e TIM1 generates the PWMs for controlling the main motor currents Also triggers the start of ADC1 ADC2 and ADC3 start of ADC3 DAC used for debugging ADC1 converts the bus voltage of the main motor ADC2 converts the bus v
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