EVBUM2282 - KLI-2113/KLI-8023 Image Sensors Evaluation Kit
Contents
1. 1 Green Gain 1 Blue 1 Red Offset 0 Green Offset 0 mv Blue Offset 0 mv Although the Red and Blue A D converter channels are not used these registers are still initialized to these default settings Adjustments Adjustments can be made to each A D s registers during operation of the board by utilizing the DATA Dipswitch SW7 the ADDRESS switch SW6 and the ADJ AD button After setting SW6 to the desired Address and SW7 to the desired Data pressing the AD button will load the new value into the Timing generator PLD and a state machine inside the PLD will then serial load the new data into the A D s register Each AD9816 uses the Green Input channel pin for its video input This is done to ease the default programming of all three A D s on power up and reset When the AD INT EXT jumper is set to INT each channel can be manually adjusted independently of the others by selecting which channel s to adjust using the channel select jumpers 2 JMP3 JMP4 When the AD INT EXT jumper is set to EXT each channel can be remotely adjusted independently of the others by selecting which channel to adjust using the three independent SLOAD signals SLOAD R SLOAD G SLOAD B See Figure 1 for more information on the AD9816 s registers CCD Modes The CCD Select switch SW5 setting determines the line length timing This switch should be set according to which CCD sensor boa2. EVBUM2282 D Table 11 INPUT CONNECTOR J10 continued 37 N C 38 GND 39 BOARD RESET 40 GND Table 12 GREEN OUTPUT CONNECTOR J6 GND G8 G8 G9 G9 GND J6 34 LINE RS422 a CENE E NEU www onsemi com 17 EVBUM2282 D Table 13 RED OUTPUT CONNECTOR J7 m Cmm m m R2 RS422 R3 RS422 R3 RS422 GND R4 RS422 R5 lt 4 1 tC J J v k C J E lt 4 MI 7 N gt o 12 0 ____ ____ 03 ____ ____ J7 29 R11 RS422 o 9 LL www onsemi com 18 EVBUM2282 D Table 14 BLUE OUTPUT CONNECTOR J4 ee Te m m B2 RS422 B3 RS422 B3 RS422 GND B4 RS422 B5 lt lt _ e GIG AIR 28 c e clc MI 7 N gt o 12 0 ____ ____ ____ ____ J4 29 B11 RS422 ow UU UNE UL 4 www onsemi com 19 EVBUM2282 D Table 15 POWER CONNECTOR J11 CLAMP CLAMP SAMPLE SAMPLE AD_CLK AD_CLK LINE_START LINE START GND www onsemi com 20 EVBUM2282
3. 8 3000 3500 4000 4500 5000 1 5500 12 6000 13 6500 14 7000 www onsemi com 8 EVBUM2282 D Frame Timing 1X Integration Time 2X Integration Time 21e 26e TG1 TG2 10e 8e LINE FRAME H1 H2 Sample 1 system clock X 10 e Figure 4 Line Rate Timing Vdark Vsat o S gt Reset 10t gt H1 H2 Clamp Sample A D Clock PIX t 1 System Clock Figure 5 Pixel Rate Timing for Devices KLI 8023 KLI 2113 www onsemi com EVBUM2282 D Vpixbinned 1 Count 10 bin mode t t 1 System Clock Video Reset H1 H2 Clamp Sample A D Clock PI Figure 6 Pixel Summing 2 Pixel Summing Shown charge to accumulate on the output node of the CCD before being reset In Binning Modes the Frequency of the Reset clamp sample A D and PIX clocks are decreased in order to allow www onsemi com 10 EVBUM2282 D AD9816 REGISTER CONFIGURATION Table 8 AD9816 REGISTER CONFIGURATION Configuration Register Bit 7 MSB Test Mode Bit Always 0 Test Mode Bit Always 0 CDS Mode Bit High for CDS Default Programming Channel Mode High for 3 Channel Channel Mode mum 39 ea 0 ee Le 9 Channel Select High for Blue Test Mode Bit Always 0 Red PGA Register 1X to 6X 0 1X Note 1 3 Green PGA Register 1X to 6X 0 1X Note 1 Blue PGA Regis
4. Jumper vnb VOG VDD TG1 TG Driver gt gt EL7202 gt Line pau Emitter SMA R Follower Driver LOGr gt LOG Driver gt LOGg gt EL7202 KLI Series Vout G 50ohm i i i H1 Driver Linear Emitter gt dd EL7156 Sensor Follower Driver SMA H2 2 Driver 50ohm EL7156 Emitter Vout B Line Follower Driver SMA RESET gt Relk Driver VPLUS VPLUS ST LOG_Peak TG_Peak Sensor Board Interface Connector V VPLUS CCD Sensor Board 10K VPEAK H_Peak POT regulator R Peak Figure 2 CCD Imager Board Block Diagram 3E8206 Sensor Board Interface Connector VPEAK regulator VMINUS VPLUS GND VDD VIG VID VLS Jumper TG1 TG2 3 Driver EL7202 50ohm Line SMA Emitter Vout R gt R Follower Driver LOG Driver KLI 2113 EL7202 Linear Image Sensor Vout_G Line H1 Driver Follower Driver 74 11244 H2 Driver 50ohm Vout B Line 74AC11244 gt Emitter i Rclk Driver 74AC11244 VSUB Sensor Board Interface Connector Figure 3 CCD Imager Board Block Diagram 3E8207 www onsemi com 3 EVBUM2282 D ARCHITECTURE HIGH LEVEL DESIGN Timing Generator Board See Figure 1 for reference Master Clock The Pixel clock frequency is one tenth the Master Clock frequency The maxim
5. implementation can be made quickly and easily to via the JTAG programming interface provided by this connector CONFIGURATION MODES Line Switches Modes The Line Switches Jumper JMP6 Selects whether some of the board settings will be controlled externally through the Digital I O connector J10 or via the on board switches If this switch is set to Line then the integration time and the Binning mode must be set remotely via digital I O AD INT EXT Modes The board comes with three Analog Devices AD9816 12 bit A D converters on board one for each color channel This A D has several features such as multiple configurations programmable gain and offset registers which require initialization and or programming on power up The programming of these registers is done via a three wire serial interface EXT A three wire serial interface is provided on the J10 connector of the board and the AD9816 s registers can be controlled remotely via these when the A D IN EX Jumper JMP5 is set to EXT See Figure 1 for the AD9816 serial timing diagrams and information INT If it is not desired to control the programming of the A D s registers remotely set jumper 5 to INT The Timing generator PLD contains a state machine that serially loads in the following default values to these registers upon power up or board reset A D Default Register Settings channels 1 CDS Mode Input Span Channel Selected Green Red
6. necessary CCD bias voltages from the positive regulated power supply input For digital output operation each of the three CCD VOUT signals are buffered by emitter follower circuits and then routed back to the Timing Generator Board to be processed by an Analog Front End AFE integrated circuit The AFE chip contains a correlated double sampling CDS circuit an 8 bit programmable DC offset compensation circuit an 8 bit programmable gain amplifier and a 12 bit A D converter For analog output operation each of the three CCD VOUT signals are A C coupled to remove the large DC component of the waveform and then routed to a non inverting operational amplifier configured with a gain of two The output of the amplifier is then driven off the Sensor board via a 50 Q coaxial cable SPECIFICATIONS Digital Output Data Rate Maximum 6 MHz Analog Output Data Rate CCD Dependent Maximum 10 MHz Resolution 12 Bits per Channel Digital Line Rate Depends on Data rate Integration time and CCD Outputs R 11 0 Red Output Channel Differential TTL G 11 0 Green Output Channel Differential TTL B 11 0 Blue Output Channel Differential TTL Frame Grabber Syncs Differential TTL External Syncs Differential TTL Semiconductor Components Industries LLC 2014 1 November 2014 Rev 2 Inputs TTL Serial Clock 10 MHz Maximum PGA Gain Range 1X to 6X PGA Gain Resolution 256 Steps Offset Range 100 mV to 100 mV Offset Resolutio
7. or its subsidiaries in the United States and or other countries SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or us
8. to VDD VIG This Input Gate test pin bias is connected to VSUB On the L24 sensor board this pin is biased to VDD via CCD Image Sensor This evaluation board supports the KLI 8023 Linear CCD sensor Emitter Follower The video out of the CCD is buffered using a bipolar junction transistor in the emitter follower configuration CCD Imager Board 3E8207 See Figure 3 for reference Power Supplies Power is supplied to the CCD Sensor Board via the Timing Board interface connector In order to operate the CCD Sensor board requires a 12 V 1000 mA external power supply If it is desired to utilize the analog output mode of operation an additional 15 V 200 mA external power supply is required for the video line drivers CCD Clock Drivers 2 CMOS clock drivers are used to generate the clocks These devices take TTL inputs from the Timing Board and output the voltage levels required by the CCD The supply voltage of these drivers is regulated and adjustable via a potentiometer V PEAK 1 TG2 Elantec clock drivers designed to drive large capacitance clock gates of a CCD image sensor are used to generate the TG clocks These drivers take TTL inputs from the Timing Board and output the voltage levels required by the CCD The drivers can source up to 2 A per channel of drive current The drivers peak output voltage is adjustable via potentiometer V_PEAK LOGr LOGg Elantec clock drivers designed to dri
9. D WARNINGS AND ADVISORIES ON Semiconductor is not responsible for customer damage to the Timing Board or Imager Board electronics The customer assumes responsibility and care must be taken when probing modifying or integrating the Truesense Imaging Evaluation Board Kits When programming the Timing Board the Imager Board must be disconnected from the Timing Board before power is applied If the Imager Board is connected to the Timing Board during the reprogramming of the Altera PLD damage to the Imager Board will occur Purchasers of a Truesense Imaging Evaluation Board Kit may at their discretion make changes to the Timing Generator Board firmware ON Semiconductor can only support firmware developed by and supplied by Truesense Imaging Changes to the firmware are at the risk of the customer ORDERING INFORMATION Please address all inquiries and purchase orders to Truesense Imaging Inc 1964 Lake Avenue Rochester New York 14615 ON Semiconductor reserves the right to change any information contained herein without notice All information furnished by ON Semiconductor is believed to be accurate Phone 585 784 5500 E mail info truesenseimaging com REFERENCES 1 KLI 2113 and KLI 8023 Device Specifications 2 KLI 2113 KLI 8023 Evaluation Board Schematics 3 Analog Devices AD9816 Product Data Sheet ON Semiconductor and the are registered trademarks of Semiconductor Components Industries LLC SCILLC
10. EVBUM2282 D KLI 2113 KLI 8023 Image Sensors Evaluation Kit User s Manual Purpose Scope The purpose of the KLI 2113 KLI 8023 Evaluation Board is to allow ON Semiconductor customers to quickly and easily operate and evaluate the performance of these image sensors The Evaluation Board provides a complete Tri linear CCD imaging acquisition sub system for the following devices KLI 2113 Image Sensor KLI 8023 Image Sensor ON Semiconductor www onsemi com EVAL BOARD USER S MANUAL OVERVIEW The Evaluation Board set consists of two circuit boards a Timing Generator Board and a CCD specific Sensor Imager Board Note The KLI 2113 requires the 3E8207 imager board and KLI 8023 requires the 3E8206 imager board The Timing Generator Board generates the digital clock signals necessary to operate the CCD the digital signals needed to operate the three A D converters and the Frame Grabber and External sync signals The positive and negative DC power supply inputs are regulated on the Timing Generator Board The outputs of the voltage regulators are routed from the Timing Generator Board to the CCD Sensor Board Inputs to the CCD Sensor Board include the TTL timing signals from the Timing Generator Board and the regulated positive and negative DC power supplies Clock drivers on the CCD Sensor Board generate the clock voltages necessary to operate the KLI series CCD The CCD Sensor Board also generates the
11. e SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT Literature Distribution Center for ON Semiconductor Box 5163 Denver Colorado 80217 USA Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Email orderlit onsemi com N American Technical Support 800 282 9855 Toll Free Semiconductor Website www onsemi com USA Canada Europe Middle East and Africa Technical Support Phone 421 33 790 2910 Japan Customer Focus Center Phone 81 3 5817 1050 Order Literature http www onsemi com orderlit For additional information please contact your local Sales Representative EVBUM2282 D
12. ernal serial interface or by manually setting the address and data switches on the board and pressing the Adjust A D button Power on Clear Reset Resets and initializes the board on power up or when the Board Reset button in pressed JTAG Header 10 pin header provides the user with the ability to reprogram the Altera 70005 PLDs in system via Altera s ByteBlaster programming hardware Input Connector This connector provides digital input control signals to the evaluation board This is an optional feature all control lines can be set via on board switches No external digital inputs are needed to operate the evaluation board Digital Output Connectors For each channel Red Green and Blue 12 bits of digital information are output in RS422 differential TTL Additionally three frame grabber sync signals are provided in RS422 differential TTL EXT SYNC Connector This connector provides the Clamp Sample A D clock and Line Start signals These signals can be used to sync up digital conversion of the Analog output of the CCD Sensor Board Board Interface Connectors Provides interface between timing board and sensor boards The sensor boards route the clock traces from the timing Board to the CCD clock drivers Power Supplies The Timing board is designed to require only 5 V 2 A external power supply Power connector The power connector is a 5 pin connector with 5 V 20 V 20 V and two AGND connections Althoug
13. h the Timing board only requires the 5 V supply all the necessary supplies are brought into the Timing board via this single connector The power supplies are then regulated and routed up to the Sensor board via the board interface connector CCD Imager Board 8206 See Figure 2 for reference Power Supplies Power is supplied to the CCD Sensor Board via the Timing Board interface connector In order to operate the CCD Sensor board requires a 13 V 1000 mA external power supply If it is desired to utilize the analog output mode of operation an additional 15 V 200 mA external power supply is required for the video line drivers Horizontal Clock Delay Pots The and 2 TTL signals can be delayed slightly by adjusting the delay pots on the Sensor board This allows the 1 and 2 signals to be adjusted with respect to one another to achieve better crossover points in and 2 CCD clocks signals CCD Clock Drivers 1 2 Elantec clock drivers are used to generate the clocks These devices take TTL inputs from the Timing Board and output the voltage levels required by the CCD The supply voltage of these drivers is regulated and adjustable via a potentiometer V PEAK 1 TG2 Elantec clock drivers designed to drive large capacitance clock gates of a CCD image sensor are used to www onsemi com 4 EVBUM2282 D generate the TG clocks These drivers take TTL inputs from the Timing Board and ou
14. l settings switch Red channel exposure control settings switch Register select switch for programming of AD9816 s AD INT EXT INT Data dipswitch for programming of AD9816 s register AD INT EXT INT Enables loading of blue channel A D converter AD INT EXT INT Enables loading of red channel A D converter AD INT EXT INT Enables loading of green channel A D converter AD INT EXT INT 10X Pixel clock 100 MHz maximum DIO Integration timing control lines DIO Binning mode control lines DIO Green channel exposure control lines DIO Red channel exposure control lines Serial clock for external programming of AD9816 s registers Serial Data for external programming of AD9816 s registers Serial load enable of red channel AD9816 Serial load enable of green channel AD9816 Serial load enable of blue channel AD9816 10 pin header for ISP 12 Bits Differential TTL Digital information 12 Bits Differential TTL Digital information 12 Bits Differential TTL Digital information Differential TTL frame grabber frame sync signal Differential TTL frame grabber line sync signal Differential TTL frame grabber pixel sync signal Differential TTL sync signal Differential TTL sync signal Differential TTL sync signal Differential TTL sync signal Table 9 DYNAMIC RANGE Maximum Sys tem Noise KLI Series CCD Electrons Floor Well Dynamic Range vs KLI Series CCD Frequency 5 MHz System Dynamic Range Electrons dB S
15. lowing sections Fixed Bias Voltages Table 2 FIXED BIAS VOLTAGES Variable Clock and Bias Voltages see Table 3 TMNSROMD __ 8 SEGORBOND _ HCLK PEAK 5V 6 5 V SENSOR BOARD NOTE These voltages are optimized for the particular CCD being used and are fixed at the factory Adjustments should not be made to them without consultation with ON Semiconductor Timing Fixed Timing Other Variable Parameters TG1 TG2 LINE FRAME See Figure 4 for additional information Pixel Frequency The pixel rate frequency can be varied by changing the Master clock oscillator or by utilizing the Variable Timing external clock feature 2 Depending on CCD Select Switch Line Length Depends on CCD switch setting Binning Modes Width Depends on pixel frequency 21 pixel counts CLAMP Binning Modes wide SAMPLE Binning Modes TG2 Width Depends on pixel frequency 26 pixel counts A D Clock Binning modes wide See Figure 5 and Figure 6 for additional information www onsemi com 7 EVBUM2282 D Table 4 CCD MODES CCD Switch Setting CCD Pixels Line 0 Test 0 2872 1 Test 5 6372 KLI 8013 8572 KLI 2113 2472 Test 4 14972 Test 1 172 Table 5 BINNING MODES Table 6 INTEGRATION TIMING MODES i i 3 x Line Time 2 Table 7 LOG MODES LOG Switch Setting Number of Pixels per Line Sw SH 0 Never ON Always LOW 500 1000 1500 2000 2 3 4 7
16. m power the regulator can dissipate without a heatsink R 0 and with a heatsink with heatsink to ambient thermal resistance equal to 20 per Watt 20 www onsemi com 14 EVBUM2282 D Power Dissipation of VPEAK Regulator Ambient Temperature 25 C KLI 8023 KLI 2113 Pdiss Max R 0 Pdiss Max R 12 Pdiss Max R 20 Pixel Dissipation W 4 6 Pixel Frequency MHz Power Dissipation of VPEAK Regulator Ambient Temperature 70 C KLI 8023 KLI 2113 Pdiss Max R 0 Pdiss Max R 12 Pdiss Max R 10 Pixel Dissipation W 4 6 Pixel Frequency MHz Figure 10 VPEAK Regulator Heatsinking Requirements NOTE Depending on the Operating rate and ambient temperature a heatsink may be required for the VPEAK positive voltage regulator on the CCD Sensor Board Figure 10 shows the maximum power the regulator can dissipate without a heatsink R 0 and with heatsinks with heatsink to ambient thermal resistance equal to 10 and 12 C per Watt R 10 R 12 www onsemi com 15 EVBUM2282 D CONNECTOR PINOUTS Table 10 BOARD INTERFACE CONNECTORS 12 15 12 VSUB J15 VSUB TG2 OUT J15 N C J12 J12 21 VIDEO OUTR J15 21 VMINUS Table 11 INPUT CONNECTOR J10 Pinsent mem 1 RLOGO 2 Rog 8 mos 8 J12 10 VSUB J15 10 VSUB J12 11 N C J15 11 N C E 7 n 23 INT1 24 27 SDATA 28 www onsemi com 16
17. n 256 Steps Temperature Range Board 0 70 C Temperature Range 50 to 70 C Publication Order Number EVBUM2282 D EVBUM2282 D Power Supplies Table 1 POWER SUPPLIES REQUIREMENTS Supply Minimum Nominal Maximum Typical Maximum 5 V 44 9 V 45V 45 1 V 1000 mA 2000 mA 20 V 17 V 18 V 20 V 500 mA 1000 mA BLOCK DIAGRAMS Output Connecter Vout R 1200pf i RED 9 09816 Diff Drivers 24 1200pf GREEN Vout G gt AD9816 Diff Drivers 24 1200pf Vout_B OT gt AD9816 _12 Diff Drivers BLUE 24 Interface Connector Power on Clear Diff Drivers SYNC GU I EE Apok j L EN Frame i Input Connecter TG2 a Diff Drivers zia Remote DIO control Timing Generator Altera 70005 ISP PLD lt VMINUS 3 Bit Switch GND Master VPLUS Clock Positive Regulator ISP 10 pin JTAG Data Switch m Negative Regulator GND 4 5V 5V h O Integration PGND inni Binning ocp select Control Red LOG Green LOG V Select 1X 4X i Switch Switch Timing Board Power Supply i i i i i Connecter a dini i Figure 1 Timing Board Block Diagram 3E8205 www onsemi com 2 EVBUM2282 D Sensor Board Interface Connector VMINUS VPLUS GND 10K 10K POT POT V V ma
18. o the board must be quiet and stable in order to achieve the best performance possible www onsemi com 5 EVBUM2282 D Inputs Upon power up the evaluation board is free running and requires no input signals to begin operating See CCD Imager Board 3E8206 section for information on additional optional inputs Outputs R 11 0 12 bits of Differential TTL Digital information G 11 0 12 bits of Differential TTL Digital information B 11 0 12 bits of Differential TTL Digital information FRAME Differential TTL frame grabber vertical synchronization signal LINE Differential TTL frame grabber horizontal synchronization signal PIX Differential synchronization signal CLAMP Differential TTL signal in sync with the reset level of the CCD output waveform TTL frame grabber PIX SAMPLE Differential TTL signal in sync with the settled Vout portion of the CCD output waveform A D CLOCK 3 Differential TTL signal that can be used by external A D to digitize the analog output of the CCD Sensor Board LINE START Differential TTL signal that indicates the start of a CCD line JTAG Programming An Altera 70008 In System Programmable ISP PLD is used on this board A ten pin header J8 is provided to allow for the programming of these PLD s Because these parts are re programmable custom digital logic can be implemented for timing and mode adjustments or additions Any custom
19. rd is being used See Table 4 for additional information www onsemi com 6 EVBUM2282 D Binning Modes The BIN Select jumper JMP7 setting determines the Binning mode operation See Table5 for additional information When no jumper is installed in JMP7 the Timing Generator board will operate according to the CCD device specification sheet timing diagram When JMP7 is configured in BIN2 mode the timing will be modified to allow two pixels worth of charge to accumulate on the CCD s floating diffusion before being reset When JMP7 is configured in BIN4 mode the timing will be modified to allow four pixels worth of charge to accumulate on the CCD s floating diffusion before being reset Integration Modes The INT Select switch SW4 settings determine the Integration time See Table 6 for additional information The INT Select switch determines how many line times worth of charge will accumulate in the photodiode before being transferred into the CCD register and clocked out of the CCD Table 3 VARIABLE CLOCK AND BIAS VOLTAGES Exposure Control Modes The GREEN_LOG switch SW3 settings determine the green channel exposure control duration The RED_LOG switch settings determine the red channel exposure control duration The LOG switches determine how long the LOG signal will be turned on See Table 7 for additional information Adjustments Adjustments that may be made to the circuit boards are addressed in the fol
20. ter 1X to 6X 0 1X Note 1 Red Offset Register 100 mv to 100 mv 0 0 mV Note 2 Green Offset Register 100 mv to 100 mv Note 2 Blue Offset Register 100 mv to 100 mv Note 2 1 PGA Gain 1 Gain Code 51 2 2 01111111 100 mV 00000000 0 mV 11111111 100 mV R W A2 D7 DO 3 Wire Serial Interface Timing R W Low for Write High for Read Figure 7 AD9816 Register Configuration www onsemi com 11 Switches LINE SW A D INT EXT INT EXT CLK DIGITAL OUTPUTS CCD 2 0 INT SEL 1 0 SW BIN2 SW BINA GREEN LOG 3 0 RED LOG 3 0 ADDR 2 0 DATA 7 0 BLUE SEL RED SEL GREEN SEL Inputs Master clk INT 1 0 BIN2 BIN4 GLOG 3 0 RLOG 3 0 SCLOCK SDATA SLOAD R SLOAD G SLOAD B JTAG Header Outputs R11 0 G11 0 11 0 FRAME LINE PIX CLAMP SAMPLE A D CLOCK 3 LINE START EVBUM2282 D BOARD INPUTS OUTPUTS SWITCHES Selects whether operating modes are controlled via DIO or switches on the board Selects whether A D programming is controlled via DIO or switches on the board Selects whether Master clock is input via the on board clock IC or external clock source ON enables outputs of AD9816 s OFF tri states outputs and output drivers Sets line length timing for the CCD selected Integration timing control settings switch Binning mode control settings jumper Green channel exposure contro
21. tput the voltage levels required by the CCD The drivers can source up to 2 A per channel of drive current The drivers peak output voltage is adjustable via potentiometer LOGr LOGg Elantec clock drivers designed to drive large capacitance clock gates of a CCD image sensor are used to generate the LOG clocks These drivers take TTL inputs from the Timing Board and output the voltage levels required by the CCD The drivers can source up to 2 A per channel of drive current The drivers peak output voltage is adjustable via potentiometer The reset clock driver is a pair of fast switching transistors that can drive the lower capacitance reset gate The drivers supply voltage is regulated and is adjustable via a potentiometer V PEAK CCD Bias Voltages VDD The VDD bias is de coupled at the device pin VRD The Reset Drain CCD bias voltage is adjustable via a potentiometer 15 de coupled at the device pin Access is provided to this bias via a jumper This allows measurement of the current IRD from which the number of electrons flowing through the Reset Drain can be calculated Output Gate bias is adjustable a potentiometer VOG is de coupled at the device pin VSS This CCD bias voltage is fixed to be a diode drop above VSUB about 0 7 V VLS The Light Shield bias voltage is fixed by a resistor divider The voltage varies depending on which CCD is being operated VID The Input Diode test pin is biased
22. um pixel clock frequency is 10 MHz therefore the maximum master clock frequency is 100 MHz For slower Pixel clock frequencies decrease the master clock frequency The source of the master clock can be an on board oscillator or the clock can be provided via an external timing generator hooked up to the Timing Generator Board via the clock input SMA connector The default setting of the evaluation board is an on board 50 MHz master clock with a pixel clock frequency of 5 MHz Timing Generator PLD The Timing Generator PLD controls the operational flow of the evaluation board This PLD generates the CCD clock timing A D converter timing and frame grabber sync signals timing The PLD controls the image line length depending on the CCD switch settings The PLD controls the pixel rate signal generation depending on the binning mode BIN jumper settings The PLD controls the Transfer Gate timing depending on the integration mode INT switch setting The PLD also controls the programming of the A D converters A D Converter Analog Devices AD9816 The AD9816 is a 12 bit 6 MSPS CCD analog signal processor The IC provides on board correlated double sampling CDS 8 bit programmable gain and 8 bit DC offset adjust The necessary timing signals for the AD9816 are provided by the Timing Generator PLD Default serial programming of the A D s registers is provided by the PLD at power up Alternate programming of its registers can be achieved via ext
23. ve large capacitance clock gates of a CCD image sensor are used to generate the LOG clocks These drivers take TTL inputs from the Timing Board and output the voltage levels required by the CCD The drivers can source up to 2 A per channel of drive current The drivers peak output voltage is adjustable via potentiometer _ A CMOS clock driver is used to drive the lower capacitance reset gate The drivers supply voltage is adjustable via a potentiometer V_PEAK CCD Bias Voltages VDD The VDD bias is de coupled at the device pin VID The Input Diode test pin is biased to VDD VIG The Input Gate test pin is biased to VDD VRD VRD is de coupled at the device pin Access is provided to this bias via a jumper This allows measurement of the current IRD from which the number of electrons flowing through the Reset Drain can be calculated CCD Image Sensor This evaluation board supports the KLI 2113 Linear CCD sensor Emitter Follower The video out of the CCD is buffered using a bipolar junction transistor in the emitter follower configuration Board Requirements Power Supply The Timing board operates from a 5 V 2 A or greater power supply The Sensor board requires a 20 V 1000 mA or greater power supply to operate If analog output is desired an additional 20 V 200 mA external power supply is required for the video line drivers Although extensive filtering is done on board the power supplied t
24. ystem Dynamic Range Bits Typical Full System Gain KLI 2113 170000 66 88 11 11 KLI 8023 185000 69 5 11 54 www onsemi com 12 Electrons per A D Unit Units Incremental Gain Measured Gain NO 700 600 500 400 300 200 100 0 95 0 90 EVBUM2282 D PGA Gain 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 255 Programmable Gain Code Linearity of Programmable Analog Gain 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 255 Programmable Gain Code Ideal Delta 1 019 Measured 0 15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240 255 Programmable Gain Code Figure 8 Measured Performance A D Programmable Gain www onsemi com 13 NOTE EVBUM2282 D Power Dissipation of VPLUS Regulator Ambient Temperature 25 C wo gt m f an aw KLI 8023 KLI 2113 Pdiss Max R 0 Pdiss Max R 20 E Pixel Dissipation W e 4 6 Pixel Frequency MHz Power Dissipation of VPLUS Regulator Ambient Temperature 70 KLI 8023 KLI 2113 Pdiss Max R 0 Pdiss Max R 20 Pixel Dissipation W 4 6 Pixel Frequency MHz Figure 9 VPLUS Regulator Heatsinking Requirements Depending on the Operating rate and ambient temperature heatsink may be required for the VPLUS positive voltage regulator U3 Figure 9 shows the maximu
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