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S3FN429

1. a e PPDCLK 2 PRESCALEA Counter Synchronous Clear Bit 0 Do not clear a speed capture timer whenever position SCSYNCHCL 19 RW counter is changed up or down 1 Clear a speed capture timer whenever position counter is changed up or down Speed Counter Clear This bit clears the content of speed counter register SCCL 18 RW 0 No effect 1 Clears counter register NOTE This bit is automatically cleared after clear Speed Capture Timer Clear Bit 0 No effect Senge 2 1 Clears speed capture timer bit NOTE This bit is automatically cleared after clear Speed Capture Timer Enable 1 RW This enables or disables speed capture timer Speed Capture Timer Pre scale Bits SCTPRESCALE 27 24 RW This bit sets the pre scale value for Phase A 0000 b SAMSUNG ELECTRONICS 7 13 S3FN429_UM_REV1 20 7 Pulse Position Decoder Name Desorption ResetValue 0 Disables speed capture timer Stop 1 Enables speed capture timer Start R Position Capture Timer Pre scale Bits PCTPRESCALE 11 8 RW This bit sets the pre scale value for Phase a PCTCLK PPDCLK 2 PRESCALEA a Resend SSS Position Counter Synchronous Clear Bit 0 Do not clear position capture timer whenever position PCSYNCHCL 3 RW counter is changed up or down 1 Clear positio
2. 19 2 19 4 O 5 rete Peri rre dra rure rr e enden T e a de dd 19 3 19 5 AC Electrical 19 4 19 6 Reset Input Characteristics ucc pe abe es LR e tee NEL ud dada 19 5 19 7 External Interrupt Input Characteristics 19 6 19 8 Oscillator rcr eer de db 19 7 19 8 1 External Main Oscillator 19 7 19 8 2 Internal Main Oscillator Characteristics ccccccccccccecsessesecesceeceesssaeaececeeecsessaaeaeceeeeeceeseaseeeeesens 19 8 19 9 Current COMSUMPTION 19 9 19 10 PLE CharacleriSti6S a eee ccr recede rb e sa rede ria er wea eue dera Ede s T 19 10 19 11 EVD GharacteriStiCS centri kr ri rere enn nk drin 19 11 19 12 12 bit ADC Electrical nnne 19 12 19 13 Comparator Electrical Characteristics esses enne enne ns 19 13 19 14 OP AMP Electrical Characteristics 19 14 19 15 Flash Memory Characteristics
3. 7 4 Counter Operation Type 1 7 5 Counter Operation 2 entrent rrt ned b et eiae rebate Luna zo tea xe ua 7 5 Flash Block Diagram 9 2 Flash Block Diagram Pre F eteh ient nni tonat tna ruban tenes 9 2 Physical Configuratio 9 3 Normal Program Flowcliart iiti ett atten eerte edente tes ee didus 9 16 Page Erase s t te Cento a 9 17 Sector Erase EFloWChart i cerent eee tec ba e ce 9 18 Entire Erase Flowchialt ott E pues 9 19 Smart Option Program FlowchaLrt tnr Eee nex DOE 9 20 Smart Option Erase sinere ns 9 21 Erroro Conditio 9 22 Error Conditio N 9 23 Errori Conditio mU 9 24 Error2 Conditio 9 25 Block Dic 10 2 Tri Angular Wave Signal Generation sse ener nnne 10 3 Saw Tooth Wave Signal Generation esent 10 4 Tri Angular Wave No SWAP Low Start PWMxUy and High Start
4. 2 5 to 5 5 V Symbol Conditions Operating voltage Xin 1 to 12 MHz PLLCLK 40 MHz 2 5 Input high volt All input pins except 0 855 nput voltage diis l XIN MODE 1 0 nRESET Vis 0 3 induti All input pins except Vi nput low voltage i XIN MODE 1 0 nRESET 1 6 mA 5 0 V Voo 0 4 Output high voltage lo 20 mA 6 IMC pads Vop 5 0V 40 PWMU 2 0 PN MD 2 0 cis Vos 1 6 MA Voo 5 0 V Output low voltage lo 20 mA 6 IMC pads Vpp 5 0 V 9 PWMU 2 0 PWMD 2 0 Input high leakage All input pins except Vin current XIN Vn Voo Input low leakage All input pins except Vin 0 current XIN 0 Output high leakage 2 i Vout Von All output pins Output low leakage _ VO pull up resistor 10 Feedback resistor XIN Pin Vin and 5 V 500 1000 1500 NOTE All pins are of Schmitt trigger type Typ SAMSUNG ELECTRONICS 19 3 x S3FN429_UM_REV1 20 19 Electrical Data 19 5 I O AC Electrical Characteristics Table 19 5 describes the reset input characteristics for the semiconducting device Table 19 4 Reset Input Characteristics 40 to 105 C VppcoreE Vppio 2 5to 5 5 V eese usen GERE input maximum operating requency tr Output maximum operating frequency All
5. PPD MISR PCMAT Position Counter Reference 01 IMC Zero UK PCRR HOLDTRIG 02 IMC Top MC 03 IMC Zero and Top TIMERx 04 TIMERO Match CRO 05 TIMER1 Match 06 TIMER2 Match Analyzer LH PPD_CR 4 00 No Trigger Disconnect Pulse Position Decoder Type PHASEZ x Speed Capture Timer Hold SCTHR X PPD SCTCL PPD_IMSCR clear 16 bit Speed Capture PPD_RISR PPD_MISR SCTOVF E v PPD CRO PPDTYPE PPDCLK 4 Up Timer SCTR clear 4 Prescaler gt 14 SCTCL PPD_CR1 SCTEN PPD_ORT PPD_IMSCR SCSYNCHGI PPD_RISR PPD_MISR SCAPT Speed Capture Timer Value SCTVR Speed Capture Timer Value Hold SCTVHR Speed Counter Hold SCHR PPD_IMSCR PPD_CRO SCDCTRL PPD_MISR 5 16 bit Up Down SCUNF Speed Counter SCR PPD_CR1 SCCL PPD_IMSCR 16 bit Comparator PPD_RISR PPD_MISR SCMAT Spe
6. IMC_SR 1 UPDOWN IMC CRO 14 PWMOUTE I Clear Clear 8 bit gt 16 bit Up Down Counte Prescaler CNTR 15 0 CV 1 NC We PWMOUTOFFEN IMC CR0 18 16 IMCLKSE CR1 5 0 IMC SR 0 FAULTSTAT IMC PACRR15 0 PACMPRDAT PWMxUD IMC PACFR15 0 PACMPFDAT Mode PWMxDD 1 _ 15 0 PBCMPRDAT 16 bit poscis aa XI 01 PBCFR15 0 PBCMPFDAT controller IMG PCCRR15 0 PCCMPRDAT PWMxce IMC PCCFH15 0 PCCMPFDAT DTCR15 0 TCR15 0 TOPCMPDAT IMC_CR0 1 IMMODE IMC CR0 3 PWMSWAP CR0 4 PWMPOLU IMC CR0 5 PWMPOLD IMC_ASTSR1 0SEL IMC_ASCRRJ 15 0 ADCMPR DAT INTMASK ASCFR 15 0 ADCMP DAT E 01 ASCRR 15 0 ADCMPR DAT 16 bit Interrupt INTPND INT IMC_ASCFR 15 0 ADCMPR DAT Comparator Controller 8 ea ADCO start Signal gt To ADCO block 5 15 0 ADCMPR DAT IMC_ASCFR 15 0 ADCMPR DAT CRO 24 20 NUMSKIF IMC ASTSH71 Figure 10 1 Block Diagram SAMSUNG ELECTRONICS 10 2 ex S3FN429_UM_REV1 20 10 Inverter Motor Cont
7. in SAMSUNG ELECTRONICS 11 15 x S3FN429_UM_REV1 20 11 Interrupt Controller INTC 11 3 1 10 NVIC_IPR5 e Base Address 0xE000_0000 e Address Base Address 0xE414 Reset Value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 14 13 12 11 10 9 8 7 6 5 4 23 RSVD PRI_N22 RSVD PRI N21 RSVD N20 RSVD N e RIR R RIR R R R RIJRI IR R R RI R R R R R R R R R WINIW W W W W W W W W W W W W W W W W W W NW W RW The pron ofthe mterupt vectornumber23 RW The prioriy ofthe vectornumber22 o wo ___ AW Reses 0 oriy oft 77 es 0 al zaj Mame Bk SAMSUNG ELECTRONICS 11 16 27 S3FN429_UM_REV1 20 11 Interrupt Controller INTC 11 3 1 11 NVIC_IPR6 e Base Address 0xE000_0000 Address Base Address 0xE418 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 14 13 12 11 10 9 8 7 6 5 4 PRI_N27 RSVD PRI_N26 RSVD PRI N25 RSVD PRI N24 RSVD RIR R RIR R R R RIJRI IR R R RIJRI R R R R R R R R WINIW W W W W W W W W W W W W W W W W W W W W PRI N27 31 30 The priority of the interrupt vector number 27 RSVD 29 24 al zaj
8. Table 2 5 Function Pin Description Table 2 6 Debug Interface Pin Description Table 2 7 Flash Serial Program Pin Table 3 1 53 429 Memory Table 3 2 Core Special Function Register Table 3 3 Peripheral Memory Table 4 1 ADC Pin 2 2 Table 4 2 ADC Input and Digital Table 4 3 CONT Values and the Number of Conversions Table 4 4 Value and Selected nee Table 5 1 Clock 1 eene Table 5 2 Summary of Smart Option for Clock Table 5 3 Clock Status at Reset and Wake Up Table 5 4 Clock Monitor Control Bit sese Table 5 5 Operation Mode Table 5 6 IDLE on Sleep Now Table 5 7 IDLE on Sleep on Exit Table 5 8 Clock Status on STOP and 0 Table 5 9 External Event Table 5 10 Reset ID ette terere tete nr eerte beet Table 5 11 256 Counting Time 4
9. nennen 17 20 17 6 8 USART Configuration in Smart Card 17 20 17 7 Programming Examples deduces 17 21 17 8 Register cents eed eed 17 22 17 8 1 Register Map 17 22 17 9 4 to 40 MHz Asynchronous nennen nnne i 17 46 18 WATCHDOG 18 1 ee 18 1 18 1 eee kt a telat dees ade 18 1 18 2 Functional BI roo Em 18 2 18 2 1 Block Diagram i deberet 18 2 18 2 2 Watchdog Timer 18 3 18 2 3 Watchdog Timer 18 4 18 3 Register DescriptiOn cena eg eae 18 5 18 3 1 Register Map entente nsns intres 18 5 19 ELECTRICAL 19 1 SAMSUNG ELECTRONICS ex 19 1 19 1 19 2 Absolute Maximum Ratings 19 1 19 3 Recommended Operating
10. WwiW IN IW WIWI IW W W W W W W W W W W W W W W W W W W W W W W W W W Writing 1 to a bit removes the associated interrupt from its pending state under the software control Each bit represents an interrupt pin number from IRQO to IRQ31 Writing 0 to a bit has no effect on the associated interrupt The register reads back from the pending state CLRREND 31 0 RW 0x0000 0000 Bit 0 for IRQO Bit 2 for IRQ1 Bit x for IRQx SAMSUNG ELECTRONICS 11 10 ex S3FN429_UM_REV1 20 11 Interrupt Controller INTC 11 3 1 5 NVIC_IPRO e Base Address 0xE000_0000 Address Base Address 0 400 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 R RI R RIJR R R R R IRI IR R RI R R R R RIJRI R RIR RIRIR R R R R R R R WwiW IWN IW WIW IW W W W W W W W W W W W W W W W W W W W W W W W W W C name nw Descrpion Resei value Paino RW Tepiyormemempwetrmmbers mewo e rw Paina 125221 Rw The proriy ofthe interuptvectornumber 00 vo rte Rw Reewd Paini Rw Tepiyormememprvesormmeri vo res ire Rw The proriy ofthe vecornameero 0 Reserved SAMSUNG ELECTRONICS 11 11 S3FN429_UM_REV1 20 11 Interrupt Controller INTC 11 3 1 6 NVIC_IPR1 Base Address 0 000 0000 Address Base Address
11. 4 swo cowse _ Puce Puce Puce Puce SAMSUNG ELECTRONICS 2 4 27 S3FN429_UM_REV1 20 2 Pin Configuration 2 4 Mirror Pins Several pins have mirror pins This helps in flexibility in arranging These pins are however defined for one instance IP only Table 2 2 describes the summary of mirror pins Table 2 2 Summary of Mirror Pins Pius P0 31 EXI23 USARTRXO PWMO PWMO PO 3 AIN2 PWMO EXI2 PO 7 AING PWMO TPWM 1 P0 4 AIN3 PWM1 EXI3 PWM1 P0 8 AIN7 PWM1 TCAP1 P0 23 COMPO P MOSIO PWM1 PO 5 AINA4 PWM 2 EXIA PWM2 P0 9 AIN8 PWM2 TCLK1 P0 24 COMP1 N SCLKO PWM2 P0 6 AIN5 PWM3 EXI5 P0 10 AIN9 PWM3 EXIG P0 30 USARTTXO EXI22 P0 31 EXI23 USARTRXO PWMO P0 11 AIN10 USARTCLK0 ADTRG USARTO P0 19 PHASEA USARTRXO EXI14 P0 20 PHASEB USARTTXO Exl15 P0 21 PHASEZ USARTCLKO EXI16 P0 26 COMP2 N USARTRXO EXI18 P0 27 COMP2 P USARTTXO EXI19 SAMSUNG ELECTRONICS 2 5 ex S3FN429_UM_REV1 20 2 Pin Configuration 2 5 Pin Description The pin description section describes e Power Pins e System Pins e Function Pins e Debug Interface Pins e Flash Serial Program Pins NOTE 1 D A Digital or Analog D Digital A Analog 2 I O Input or Output I Input O Output 3 PIN Z A The same function pin group PIN A PIN B to PIN Z 2 5 1 Power Pins Table 2 3 describes the power pin description Tabl
12. mw R Red Compare Data for Phase B Falling time PBCMPFDAT 15 0 RW This field determines the Phase B compare register value 0x0000 at falling NOTE If you use ADC compare interrupt you should set IMC_PxCRR F from 1 to TCR 1 0 lt PXCRR FR lt TCR SAMSUNG ELECTRONICS 10 57 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 3 1 19 IMC_PCCFR Base Address 0 400 0000 e Address Base Address 0x0048 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24123 22 21 20 19 18 17 16 15 14 13 12 11 10 a B A PCCMPFDAT ele es RIR R R R R R R R R Rvo ema R Rese Compare Data for Phase C Falling time PCCMPFDAT 15 0 RW This field determines the Phase C compare register value 0x0000 at falling NOTE If you use ADC compare interrupt you should set IMC_PxCRR F from 1 to TCR 1 0 lt IMC_PxCRR FR lt TCR SAMSUNG ELECTRONICS 10 58 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 3 1 20 IMC_ASTSR Base Address 0 400 0000 e Address Base Address 0x004C Reset Value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 515 aja 2 lt lt R R ADC Start Trigger
13. 8 2 8 2 3 Output Configuration careret aaan 8 3 8 2 4 Operation her a sesta Hr rad A 8 3 8 2 5 X 8 4 8 3 8 5 8 3 1 Register Map ettet ea ate caes Lu ets 8 5 9 INTERNAL FLASH CONTROLLER eese 9 1 meu 9 1 IPEF OOS 9 1 9 2 Functional EN 9 2 elt 9 3 9 22 ER 9 6 9 10 9 24 FOW EMT 9 16 Teo ENO mto niet tette 9 22 9 3 Register DESCHIPUON m 9 26 9 3 1 Register Map 9 26 10 INVERTER MOTOR CONTROLLER IMC 10 1 10 1 OVGMWIOW m E Uu 10 1 rc 10 1 108 Pin elie dee a ees 10 1 10 2 Functional DescriptiOn 10 2 10 2 1 Block Diagram Ee 10 2 10
14. CHKSRCSEL2 COMP3PPDEN 2 e CHKSRCSEL3 COMP2PPDEN gt COMP2IMCEN a gt m gt zm zm zm gt E zall a ue CERES and PHASEZ Others Invalid COMP3IMCEN COMP2IMCEN COMP1IMCEN COMPOIMCEN IMC Output Signal Floating By Comparator Enable 0 Disables 1 Enables Edge Detect Status Check Source Selection Bit 000 Selects COMPCLK bit 001 Selects PWMUO signal 010 Selects opposite inverted PWMUO signal 011 Selects PWMU1 signal 100 Selects opposite inverted PWMU1 signal 101 Selects PWMU2 signal 110 Selects opposite inverted PWMU2 signal 111 Not used CHKSRCSEL3 26 24 CHKSRCSEL2 18 16 CHKSRCSEL1 10 8 CHKSRCSELO 2 0 Comparator x and PPD Connect Selection 000 Disconnects to PPD 001 Connects a comparator output to PPD PHASEA COMPSPPDEN 010 Connects a comparator output to PPD PHASEB COMP2PPDEN pw 011 Connects a comparator output to PPD PHASEZ COMP1PPDEN 100 Connects a comparator output to PPD PHASEA COMPOPPDEN i and PHASEZ 101 Connects a comparator output to PPD PHASEB NOTE PPD stands for Pulse Position Decoder block IMC stands for Inverter Motor Controller block SAMSUNG ELECTRONICS 6
15. __ S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 1 7 CM_PCKSR e Base Address 0 4002 0000 Address Base Address 0x0020 Reset Value 0x0000 0002 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 WDTCLK gt gt ___ SPIOCLK gt gt ___ gt gt ___ _ gt ___ _ IMCCLK DOMT gt gt ___ gt gt ___ gt gt ___ fe gt gt ___ gt Peripheral Clock Status 0 Disables each peripheral clock disconnected It is impossible to control Write SFR register of a target peripheral 1 Enables each peripheral clock connected It is possible to control Write SFR register of a target peripheral Peripheral Clock Status 0 Disables each peripheral clock disconnected SPIOCLK It is impossible to control Write SFR register of a target COMPCLK peripheral ADCCLK 1 Enables each peripheral clock connected It is possible to control Write SFR register of a target peripheral mewo ein A Peripheral Clock Status 0 Disables each peripheral clock disconnected It is impossible to control Write SFR register of a target USARTOCLK 16 peripheral 1 Enables each peripheral clock connected It is possible to control Write SFR re
16. 1KQ 0 1uF SAMSUNG ELECTRONICS 2 8 ex S3FN429_UM_REV1 20 2 Pin Configuration 2 5 3 Function Pins Table 2 5 describes pin description Table 2 5 Function Pin Description Fato ___ Module emo Generat purpose VO mutipterea D __ 16 bit timer PWM IMC USART OP AMP comparator Compan Comparator Ss SAMSUNG ELECTRONICS 2 9 en S3FN429_UM_REV1 20 2 Pin Configuration 2 5 4 Debug Interface Pins Table 2 6 Debug Interface Pin Description PmName Function Comments DEBUG aue eo Select serial wire data input output D vo Internal pull up 55 kQ SWDOLK DCLK Serial wire clock 2 5 5 Flash Serial Program Pins Table 2 6 describes pin description Refer to 9 2 3 2 Tool Program Mode for more details Table 2 7 Flash Serial Pin Description F Serial Clock Clock Data pin Input and push pull F_SDAT FLASH when reading input when writing SAMSUNG ELECTRONICS 2 10 ex S3FN429_UM_REV1 20 2 Pin Configuration 2 6 Pin Circuit Type 2 6 1 Block Diagram Figure 2 2 Figure 2 3 Figure 2 4 and Figure 2 5 illustrate the Type A Type B MODEx and nRESET pin circuits respectively 2 6 1 1 Type A Bi directional buffer with B4 NOTE output driver and enables schmitt trigger cmos input with control
17. nnne 3 2 3 3 2 Peripheral Special Function Register 3 3 4 ANALOG TO DIGITAL CONVERTER ADC 4 1 AN M 4 1 41 1 Features ER 4 1 4 1 2 E 4 1 4 1 3 Block Diagram 1 4 2 4 4 4 Input and repe rte titi ned ute Rad cenare d der pode 4 3 4 1 5 Clock Frequency and Conversion Time sss eene enne nennen nennen 4 4 EN Ree iibi 4 5 4 1 7 Conversion Start Trigger 4 9 4 1 8 Conversion 4 10 4 1 9 Interrupt and Flag 4 10 Calibration luerit dei e rera Pendet e ud Rea daos dea d aga 4 11 4 1 11 Operation Sequence iecit Eres oddest eee 4 14 4 2 Register Description eee irie cel eet 4 16 4 2 1 Register Map sessi nass assa tasa astra nnns 4 16 5 CLOCK AND POWER 2 2 5 1 5 5 1 mde
18. 16 3 16 2 2 COUNTER SIZC 16 3 16 2 3 dedi ee ee dd ania ae 16 4 SAMSUNG ELECTRONICS ex 16 24 svi 16 4 16 2 5 Trigger rui haee doa ete ae Eee aO Te ees tud e duae eod 16 4 16 2 6 Overflow MOQe tincnt erae neret ta devas se rab edat ev daa c vaL uUi ia 16 5 16 2 7 Pernod 16 8 16 2 9 1 S 16 17 16 3 Register DescriptiOn tcrra et tee eed ede et cate Sea ean 16 18 16 3 1 Register Map 16 18 17 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMIT T BP cetenasncctenatarssbenscnndtneddcntenecancccsnarenebacences 17 1 Aer Um 17 1 E 17 2 17 2 17 2 17 2 Functional Description tenance 17 3 172271 Block Diagram 17 3 17 2 2 Ba dRate Generalor atri
19. PWMUO PWMU1 PWMU2 COMP CR2 CHKSRCSEL2 1 _ 1 INTREFSEL3 _ COMP3PSEL _ COMP3EN COMP_SR COMPOUTSTATUS3 0 45VDD 0 50VDD 0 80VDD _ gt n To IMC gt v COMPCLK COMP SR EDGEDETSTATUS2 COMP COMP2PPDEN Not use for PPD 01 To PPD PHASEA _ 9 10 To PPD gt 9 11 To PPD PHASEZ 2 COMP IMSCR EDGEDET3 COMP3EDGESEL COMP_RISR COMP_MISR COMP COMPSIMCEN comp3 Filter 5 COMP CRt OP amp output To 0 gt COMP_SR EDGEDETSTATUS3 COMPCLK COMP3FILTER N gt 1 COMP 0 COMP3NSEL PWMUO PWMU1 PWMU2 2 CHKSRCSEL3 To IMC A To B To IMC C To IMC IMC Inverter Motor Controller Figure 6 1 SAMSUNG ELECTRONICS CRO0 COMP3PPDEN Not use for PPD 01 To PPD 10 To PPD gt 9 11 To PPD PHASEZ 3 gt To PPD PHASEZ 0 4 To PPD PHASEZ a PPD To PPD PHASEZ 9 7 PHASEZ To
20. R 15 0 Indicates the current counter value EE EN Caution CVR register is available only when the clock source is PCLK SAMSUNG ELECTRONICS 16 44 27 S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 1 Universal Synchronous Asynchronous Receiver Transmitter 17 1 Overview The Universal Synchronous Asynchronous Receiver Transmitter USART controller is used to communicate between micro controllers The USART at the transmitting end takes bytes of data and transmits the individual bits sequentially starting from the Least Significant Bit LSB The USART at the receiving end re assembles the bits into the originally transmitted byte Serial transmission is commonly used with modems and for non networked communication between computers terminals and other devices The two primary forms of serial transmissions are e Synchronous serial transmission e Asynchronous serial transmission The Asynchronous mode uses two lines for data transfer They are e Rx for the reception e Tx for the transmission of the bits The Synchronous mode uses an additional clock signal to strobe the input and output data SAMSUNG ELECTRONICS 17 1 ex S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 1 1 Feature The features of USART are e Programmable BaudRate generator e Parity framing and overrun error detection e idle
21. RXEV bit in CM MRO Event Reg Figure 5 11 Interrupt and Event SAMSUNG ELECTRONICS 5 22 ex S3FN429_UM_REV1 20 5 Clock and Power Manager Figure 5 12 illustrates the different handling process for interrupt and event in IDLE or STOP mode Disable Interrupt event in peripheral external interrupt controller Disable interrupt in peripheral external NVIC Clear pending signal in Clear pending signal in peripheral external interrupt peripheral external interrupt controller and NVIC controller Enable interrupt in Enable interrupt in peripheral external interrupt peripheral external interrupt controller and NVIC controller Copy NVIC interrupt Set Enable Execute WFE register into CM_NISR event Execute WFI Resume code execution Interrupt clear pending signal in peripheral external interrupt controller Serve an interrupt clear pending signal in peripheral external interrupt controller and NVIC Resume code execution Figure 5 12 Different Handling Process for Interrupt and Event in IDLE or Stop Mode SAMSUNG ELECTRONICS 5 23 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 5 External Events External Interrupts and Wake up Event S3FN429 supports 26 external input events including external interrupts Refer to Table 5 14 except other internal peripheral and core event interrupts You can use these as a specific event trigger in an operating mode or wake up trigg
22. 17 4 17 2 9 General est nie 17 4 17 3 Asynchronous Mode eie tt tae eens den Rab a 17 5 17 3 1 Synchronous Mode CUR Te eed Depp 17 5 17 4 M 17 12 17 4 1 22 iuter atten 17 12 17 4 2 Synchronous Receiver 424 0 tena 17 13 17 5 Transmite EUM 17 15 17 5 1 General Description iiie dades eae Fei be aed x aeiia iiai 17 15 17 522 Time Guard eset eee Te eee 17 16 1725 3 M lti Brop MOGE 17 16 17 6 EP 17 17 17 61 Transmit Break 17 17 17 6 2 Receive Break A 17 17 ywesesniguscm 17 17 17 6 4 Test 8 E 17 18 17 6 5 Smart Protocol 5 aera n eit TEE Ee de 17 18 17 6 6 Character Transmission to Smart 17 19 17 6 7 Character Reception from Smart
23. Loop Counter lt lt Pre Loop Counter 1 lt lt Command START Clear END A arget Address i protected Error2 END Bit Set Loop Counter 0 Command NP Normal Program 001 b Figure 9 4 Normal Program Flowchart SAMSUNG ELECTRONICS 9 16 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 2 4 2 Page Erase Figure 9 5 illustrates the Page Erase flowchart Loop Counter lt lt The number of page to erase KEY lt lt 0x5A5A5A5A Y ADDR Page Address Loop Counter lt lt Pre Loop Counter 1 CR lt lt Command START Clear END Page is protected Error2 END Bit Set No Loop Counter 0 Yes Command PE Page Erase 010 b Figure 9 5 Page Erase Flowchart SAMSUNG ELECTRONICS 9 17 x S3FN429_UM_REV1 20 9 2 4 3 Sector Erase 9 Internal Flash Controller IFC Figure 9 6 illustrates the Sector Erase flowchart Loop Counter The number of sector to erase v KEY lt lt Y ADDR Sector Address Loop Counter lt lt Pre Loop Counter 1 CR lt lt Command START Clear END Error2 Sector is protected END Bit Set Loop Counter 0 Yes
24. o0 o3 o9 The count length determines the time out period Loading PCV field of WDT MR register controls the time out period The time out period in seconds is e PCV 15 0 1 WDTCLK freq When the counter reaches the value programmed in the pending windows PWL 15 0 of WDT_PWR register the Watchdog generates a Watchdog pending interrupt The pending interrupt occurs after PCV 15 0 PWL 15 0 WDTCLK freq If PWL 15 0 is greater than PCV 15 0 the previous time is negative then do not use the WDT pending interrupt To prevent an internal chip reset if RSTEN bit is set in the or interrupt if bit WDTOVE is set in the IMSCR the software should be able to reset the counter before it reaches 0 by writing the correct key in the CR register 0 071 The time difference in seconds between the WDT pending interrupt and the WDT overflow is e PWL 15 0 WDTCLK freq When the counter reaches 0 it triggers the programmed action internal chip reset or overflow interrupt If WDT reset is not programmed after reaching 0 it is reset to the programmed value and continues to down count This down count will continue till it disables the WDT Use this to generate periodic interrupts SAMSUNG ELECTRONICS 18 3 ex S3FN429_UM_REV1 20 18 Watchdog Timer 18 2 3 Watchdog Timer Events Watchdog timer events consist of e Internal Chip Reset Pulse Generation
25. Calibration Reference Voltage Source 0 Selects external input voltage sources 1 4 AVpp and 3 4 to determine calibration constants through ADC input channel In this case it is same as normal operation mode The difference is that the input voltage for conversion is 1 4 AVpp and 3 4 AVpp 1 Selects internal reference voltage sources 1 4 AVpp and 3 4 AVpp to determine the calibration constants NOTE If you cannot use ADC without calibration then the CALEN bit is 0 In normal operation EICR is 0 ___ ____ Remark You can use any ADC channel AINx to obtain external reference voltage You can get the conversion data by 1 4 reference voltage with AINx Use the same channel or other channels for conversion data of 3 4 reference voltage Use 1 4 3 4 or both reference voltage supplied externally Use 1 4 reference voltage supplied internally Do not use ADC channel AINx Use 3 4 reference voltage supplied internally Do not use ADC channel AINx X means don t care ICRV 25 Internal Calibration Reference Voltage Value SAMSUNG ELECTRONICS 4 24 S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 0 Selects internal voltage source 1 4 AVpp to determine calibration constants 1 Selects internal voltage source 3 4 AVpp to determine calibration constants Calibration Enable Disable Control Bit 0 Disables calibration bit The conversion data of
26. game 277 g Scwsm Rue meememe Fea 4 s Fm o 2 me chip erasetime Fea 3 EUM Fnwe 10 000 times number of writing erasing Fk A3 SAMSUNG ELECTRONICS 19 15 ex S3FN429_UM_REV1 20 19 Electrical Data 19 16 SPI SSP Timing Characteristics Table 19 16 SPI Timing Characteristics SPI MOSI slave input setup time tSPISIS 1 4 x Tspictkin 2 ese SPI MOSI slave input hold time tSPISIH 1 4 x 2 SPI MISO slave output delay time tSPISOD L 200 SPI MISO master input setup time tSPIMIS 1 4 x Tspictkout 2 Led n SPI MISO master input hold time tSPIMIH 14 2 n NOTE 1 Clock cycle time 1 Fscik Fspictk Min gt 2 x Fspictkout Max for master mode Min gt 12 x Max for slave mode Fsp CLK Max lt 254 x 256 x FspicLKOUT Min for master mode Fspictk Max lt 254 x 256 x Fspictxin Min for slave mode Fspictkout lt 12 Mbps for master mode lt 3 3 Mbps for slave mode 2 Clock rise fall time n Max 12 ns with CL 30 pF 3 The SPI timing characteristics is not tested during mass production o e Figure
27. 14 4 14 2 6 nPULSE uit re 14 4 1422 7 IDLE ETE 14 5 14 2 8 Parameter 14 5 14 2 DEKOS ON 14 8 14 3 Register DescriptiOnmeas no ed 14 13 14 371 Register Map Summary ecce rene ntt te heat ten een edd Fe tae 14 13 15 SERIAL PERIPHERAL INTERFACE SPI 15 1 151 T 15 1 15 11 Features m 15 1 15 1 2 Bree E 15 2 15 2 Functional DescriptiOoni ueteri a a 15 3 15 2 1 Block Diagram oett cotta 15 3 15 2 2 Operation vic m 15 4 15 3 Register DOSCIIDUOM ssc irt tee e t 15 18 15 3 1 Register Map dede en coe e BE etn cre Ee Lade 15 18 15 HMEH COUNTEH 16 1 uev prc 16 1 VOT FOAUUICS E 16 1 16 1 2 Pin 5 16 2 16 2 Functional DescriptlOri enar qe edat ar NEMUS Fai 16 3 16 2 1 Block Diagram iini etate dale denne Eee
28. END END Interrupt Mask Control Bit END HW 0 Interrupt is masked Disables an Interrupt 1 Interrupt is not masked Enables an Interrupt NOTE Ona Read the IFC_IMSCR register gives the current value of the mask on the relevant interrupt A Write of 1 to a particular bit sets the mask and enables the interrupt to be read A Write of 0 clears the corresponding mask 9 ERRn ERR Interrupt Mask Control Bit Error1 Write undefined value CMD 2 0 111b into ERR1 RW CMD field of a control register during operation flow 0 Interrupt is masked Disables an Interrupt 1 Interrupt is not masked Enables an Interrupt SAMSUNG ELECTRONICS 9 33 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 3 1 7 IFC_RISR e Base Address 0x4001_0000 e Address Base Address 0x0018 Reset Value 0x0000 0000 ERR Interrupt Raw Status Gives the raw interrupt state prior to masking of the ERRn interrupts Error2 Writes or erases to the protected memory region ERR Interrupt Raw Status Gives the raw interrupt state prior to masking of the ERRn interrupts Error1 Writes undefined value CMD 2 0 111b into CMD field of a control register during operation flow interrupts ErrorO Tries to execute other operation program erase while executing normal program command operation vo END Interrupt Raw Status Gives the raw interrupt state prior to masking of the
29. PEND gt ___ __ Pulse Match Masked Interrupt State Gives the masked interrupt state prior to masking of PMATCH interrupt Period End Masked Interrupt State Gives the masked interrupt state prior to masking of PEND interrupt RSVD Period Start Masked Interrupt State PSTART Gives the masked interrupt state prior to masking of PSTART interrupt PWM Stop Masked Interrupt State Gives the masked interrupt state prior to masking of PWMSTOP interrupt PWM Start Masked Interrupt State Gives the masked interrupt state prior to masking of PWMSTART interrupt PWMSTOP PWMSTART NOTE On a Read PWM MISR register gives current masked status value of the corresponding interrupt A Write has no effect SAMSUNG ELECTRONICS 14 24 S3FN429_UM_REV1 20 14 Pulse Width Modulation 14 3 1 10 PWM_ICR e Base Address 0x4007_0000 0x4007_ 1000 e Address Base Address 0x0024 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 e e s e pwastarr s e PEND gt ___ 0 effect 1 Clear pulse match interrupt PWM Period End Interrupt clear PEND 0 No effect 1 Clears PWM Period Ended interrupt PWM Period Start Interrupt clear PSTART 0 No effect 1 Clears PWM period started interrupt PWM Stop Interrupt clear PWMSTOP 0 No effect 1 Clears PWM stopped in
30. S3FN429_UM_REV1 20 13 Operational Amplifier 13 1 4 Gain Generation Circuit You can select an external gain control circuit with appropriate pins as OPA_N OPA_P and OPA_O or an internal gain control In this case you should configure OPAG bit that corresponds to each mode Table 13 2 describes the gain specification of OP AMP Table 13 2 Gain Configuration Table OPAGVx Gain Specification of OP AMP SAMSUNG ELECTRONICS 13 3 en S3FN429_UM_REV1 20 13 Operational Amplifier 13 2 Register Description 13 2 1 Register Map Summary e Base Address 0 4004 1000 OPA_IDR 0x000 OP AMP ID register 0x0001_001D OPA_CEDR 0x004 OP AMP clock enable disable register 0x0000_0000 OPA_SRR 0x008 OP AMP software reset register 0x0000 0000 OPA CR 0 00 control register 0x0000_0000 OPA_GCR 0x010 OP AMP gain control register 0x0000_0000 SAMSUNG ELECTRONICS 13 4 ex S3FN429_UM_REV1 20 13 Operational Amplifier 13 2 1 1 OPA_IDR e Base Address 0 4004 1000 e Address Base Address 0x0000 Reset Value 0x0001_001D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 o a Reserved Lug ID Code Register E 0x0001 001D This field stores the ID code for the corresponding IP i E SAMSUNG ELECTRONICS 13 5 ex S3FN429_UM_REV1 20 13 Operational Amplifier 13 2 1 2 OPA_CEDR e Base Address 0 4004 1000 e Address Bas
31. 17 3 USART BaudRate Generator Block Diagram sessi 17 5 Asynchronous Mode Start Bit 17 12 Asynchronous Mode Character 17 12 Synchronous Mode Character 17 13 IDLE Flag at 17 14 Synchronous and Asynchronous Modes Character 17 15 Figure 17 8 Figure 17 9 Figure 18 1 Figure 19 1 Figure 19 2 Figure 19 3 Figure 20 1 Smart Card Transmission 17 19 Error Signaling on 17 20 Watchdog Timer Block 18 2 Input Timing Tor a aaa 19 5 Input Timing for External nenna naa ea a a 19 6 SPI Interface Transmit Receive 7 19 16 44 QFP 1010 Package Dimension esses entere nnne 20 2 SAMSUNG ELECTRONICS ex Table Title Number Table 2 1 Pin Assignment by Pin Number Table 2 2 Summary of Mirror Pins 1 essere nennen Table 2 3 Power Pin Table 2 4 System Pin 5
32. 5 25 FRESE SOUICOS PER 5 26 LVD Block Diagiam Em 5 28 G 5 31 Start Up with Basic Timer 2 5 31 Fast Luo 5 32 Basic Timer and Exit of Stop Mode when FWAKE is 0 5 32 Basic Timer and Exit of Stop Mode when FWAKE is 1 SYSCLK 5 33 Clock Initialization when Reset Value of SYSCLK is 5 76 Clock Initialization when Reset Value of SYSCLK is IMCLK eee 5 77 SAMSUNG ELECTRONICS 227 Figure 6 1 Figure 7 1 Figure 7 2 Figure 7 3 Figure 7 4 Figure 7 5 Figure 9 1 Figure 9 2 Figure 9 3 Figure 9 4 Figure 9 5 Figure 9 6 Figure 9 7 Figure 9 8 Figure 9 9 Figure 9 10 Figure 9 11 Figure 9 12 Figure 9 13 Figure 10 1 Figure 10 2 Figure 10 3 Figure 10 4 Figure 10 5 Figure 10 6 Figure 10 7 Figure 10 8 Figure 10 9 Figure 10 10 Figure 10 11 Figure 10 12 Figure 10 13 Figure 10 14 Figure 10 15 Figure 10 16 Figure 10 17 Figure 10 18 Figure 10 19 Figure 10 20 Figure 10 21 Figure 10 22 Figure 10 23 Figure 10 24 Figure 10 25 Figure 10 26 Figure 10 27 Figure 10 28 Figure 10 29 Comparator Block gt 6 3 PPD Block Diag raTa iessen 7 2 Counter Operation 4 Multiplication Mode enne nennen 7 3 Counter Operation 1 Multiplication
33. Caution The UPDATE bit in the CSR PWM register allows the configuration of new parameters only if the PWM channel disables or associates at the end cycle period SAMSUNG ELECTRONICS 14 3 ex S3FN429_UM_REV1 20 14 Pulse Width Modulation 14 2 3 Clock and Operation Frequency The Clock Source FIN is PCLK Peripheral Clock The divider value M and pre scale value N in the PWM_CDR Clock Divider register decides the frequency of PWM operation clock Defines the PWM counter clock as e PWM Counter Clock Frequency PWMCLK PCLK 2N M 1 e 0 lt lt 16 0 lt lt 27 14 2 4 Period The PERIOD cycle represents periodic PWM output The PERIOD field in the PWM_PRDR register controls the number of down counter cycles to fix the period PERIOD 15 0 for the 16 bit PWM period width If you configure the PERIOD field at 0 then the logical level configured by IDLESL Idle Level bit drives the PWM output The PWM channel automatically disables after setting the UPDATE bit 14 2 5 PULSE Level OUTSL bit controls the level of active width to fix the PWM output device The OUTSL bit affects the PWM output start level When the OUTSL bit is set to 0 then the PULSE width level is low and the nPULSE width level is high On the other hand when the OUTSL bit is set to 1 then the PULSE width level is high and the nPULSE width becomes low 14 2 6 nPULSE Width PWM output starts with PULSE when you enable PWM cha
34. RW 9 ms resena oriy oft w INE UN SAMSUNG ELECTRONICS 11 17 en S3FN429_UM_REV1 20 11 Interrupt Controller INTC 11 3 1 12 NVIC_IPR7 e Base Address 0xE000_0000 e Address Base Address 0xE41C Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 PRI N31 RSVD PRI N30 RSVD PRI N29 RSVD N28 RSVD N e RIR R RIR R R R RIJRI IR R R RIJRI R R R R R R R R WINIW W W W W W W W W W W W W W W W W W W W W al zaj ES en Bt PRI N31 PRI N30 30 24 22 16 PRI_N29 RSVD PRI_N28 5 0 The priority of the interrupt vector number 28 The priority of the interrupt vector number 29 7 w INE UN SAMSUNG ELECTRONICS 11 18 27 S3FN429_UM_REV1 20 I O Configuration 12 1 Overview 12 I O Configuration The I O Configuration chapter describes the configuration of specific function pins mapped to each I O pin 12 1 1 Features The features of IOCONF are e Configuration of function pin Select one among four functions Function 0 GPIO Function 1 Function 2 Function 3 e Configuration of Pull Up Resistor PUCR e Configuration of Open Drain Control Resistor ODCR SAMSUNG ELECTRONICS
35. S3FN429_UM_REV1 20 16 Timer Counter 16 2 Functional Description The TC supports up to 16 bit counter increased by PCLK or the external clock input through TCLK pin The TC operates as Overflow mode or Period mode to generate periodical time event TC can output the PWM signal through TPWM pin You can capture the counter value by an external trigger signal on TCAP pin 16 2 1 Block Diagram Figure 16 1 illustrates the block diagram for TC TC_CSSR CKSRC gt 1777 DIVM 1 Diva n bit Up Counter L E TC CVR COUNT TC CEDR CLKEN Start Interrupt TC SR PWMEN Stop Interrupt TC CCSMR PWM Generator SIZE Overflow Interrupt TC_CPULSE PULSE C_SR PWMIM PWMEX Pulse Match IDELSL OUTSL KEEP Interrupt gt TC_CPERIOD PERIOD Period End Interrupt TC_CDCR COUNT Period Start Interrupt TC SR CAPT_F TC CUCR COUNT Capture gt Interrupt TIMER COUNTER Figure 16 1 Block Diagram NOTE You can assert the external clock source on the TCLK Pin The external clock frequency TCLK should be equal to or lesser
36. SAMSUNG ELECTRONICS 9 6 S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 2 2 1 1 Power On CPU system Clock Configuration Bit When chip reset occurs CPU runs with the clock to be defined by this smart option bit The initial value to be programmed on factory is IMCLK Internal Main Clock If it is changed from IMCLK to EMCLK external clock pin configuration XIN or XIN XOUT should be done together 9 2 2 1 2 External Main Clock Input and Output Pin Configuration Bits Pin7 and Pin8 are decided between the system pin XOUT XIN and the function pin PO 30 USARTTXO EXI22 PO 31 EXI23 USARTRXO PWMO by smart option That means they are selected by hardware configuration at reset time If they are defined as function pins at reset time you can use these pines as one function among 4 functions by software register control after reset If they are defined as system pins at reset time it can be used for the external clock only The initial value to be programmed on factory is the system pin XOUT XIN 9 2 2 1 3 Basic Timer Divider Configuration Bits Internal reset generation circuit uses the basic timer to obtain the stabilization time of system The time comprised by basic timer in reset time is the 256 counts by basic timer If the basic timer divider value is increased the reset time will be longer The default divider value 4096 is enough to make the chip reset under the stabilization for internal logic If you need to
37. es RIR R R R R R R R R Rvo 000021000 Compare Data for Phase A Rising time PACMPRDAT 15 0 RW This field determines the Phase A compare register value 0x0000 at rising NOTE If you use ADC compare interrupt you should set IMC_PxCRR F from 1 to IMC_TCR 1 0 lt IMC_PxCRR FR lt IMC_TCR SAMSUNG ELECTRONICS 10 53 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 3 1 15 IMC_PBCRR Base Address 0 400 0000 Address Base Address 0x0038 Reset Value 0 0000 0000 31 30 29 28 27 26 25 24123 22 21 20 19 18 17 16 15 14 13 12 11 10 a B A PBCMPRDAT ele es RIR R R R R R R R R mw Compare Data for Phase Rising time PBCMPRDAT 15 0 RW This field determines the Phase B compare register value 0x0000 at rising NOTE If you use ADC compare interrupt you should set IMC_PxCRR F from 1 to TCR 1 0 lt IMC_PxCRR FR lt TCR SAMSUNG ELECTRONICS 10 54 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 3 1 16 IMC_PCCRR Base Address 0 400 0000 e Address Base Address 0x003C Reset Value 0 0000 0000 31 30 29 28 27 26 25 24123 22 21 20 19 18 17 16 15 14 13 12 11 10 a B A PCCMPRDAT ele es
38. 15 12 Motorola SPI Frame Format Single Transfer with SPO 1 and SPH 0 15 13 Motorola SPI Frame Format Continuous Transfer with SPO 1 SPH 0 15 13 Motorola SPI Frame Format with SPO 1 SPH 1 15 14 PrimeCell SSP Master Coupled to Two 5 5 15 15 SPI Master Coupled to two PrimeCell SSP Slaves 15 16 TO SBIETe Ir porc 16 3 Match and Overflow Operation eene nennen nnn nennen 16 5 Counter Values According to START STOPCLEAR and STOPHOLD 16 6 Capture Operation Timing i e reris otn pete trita parla pan eda ob ea Md aged EYE apa br da a 16 7 Period Timing e 16 8 Interval Operati 16 9 PWM Operation 16 10 PWM Extension 16 11 PWM Waveform with OUTSL 0 16 13 PWM Waveform with OUTSL enne 16 13 PWM Waveform Under IDLE State 16 15 PWM Waveform with STOPHOLD 1 STOPCLEAR 0 sse 16 15 PWM Waveform with STOPCLEAR 1 16 16 USART Block DIagftamy 1 rir rotundi ior natu dol nn re aite Rede ungui
39. Clock Divider This register has no effect if the synchronous mode is selected with an external clock e ASYNC Mode CD FLOOR FcIk BaudRate x 16 1 e SYNC Mode CD FLOOR Fclk BaudRate 1 imum FRACTION Bypasses clock divider e BaudRate Asynchronous Mode Fclk 16 x CD FRACTION 16 2 to 65535 e BaudRate Synchronous Mode Felk CD FRACTION 16 Fractional Correction Value This register has no effect if the synchronous mode is selected with an external clock e ASYNC Mode FRACTION ROUND Fclk BaudRate x 16 CD 16 0 e SYNC Mode FRACTION ROUND Fclk BaudRate CD x 16 0 0x0000 BaudRate Asynchronous Mode Fclk 16 x CD FRACTION 16 BaudRate Synchronous Mode Felk CD FRACTION 16 SAMSUNG ELECTRONICS 17 42 Cewenmmas 700 5040 S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter NOTE FCLK is the USART input clock and BaudRate is the desired communication speed In the synchronous mode the programmed value should be even to ensure a 50 50 mark space ratio You should enable the clock that is CD is different to zero after configuring the BaudRate clock using the US register You should not use CD 1 when selecting the internal clock PCLK that is USCLKS 1 0 0 Caution SAMSUNG ELECTRONICS 17 43 S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 8 1 14 US_RTOR e Base Address 0 4008
40. LVD reset level After Power on Reset the PORSTS bit in the CM SR register sets to 1 Although a reset by other reset sources occur it does not clear the status 1 or 0 of this bit and the status remains the same Only you can clear this bit by software 5 6 3 LVD Reset LVDRST By default it enables the LVD Reset at reset see the LVDRSTEN bit in the CM MR register After a reset you can configure the LVD reset by using the LVDRST bit in the CM SR register You can also configure the level of the LVD reset by using the LVDRL 2 0 fields in the CM MR register After the LVD reset the LVDRSTS bit in the CM SR register sets to 1 Although a reset by other reset sources occurs it does not clear the status 1 or 0 of this bit and the status remains the same Only you can clear this bit by software SAMSUNG ELECTRONICS 5 27 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 6 3 1 LVD Interrupt You can enable or disable the LVD interrupt level detection by controlling the LVDINTEN bit in CM_MR register You can mask or unmask the LVD interrupt by controlling the LVDINT bit in CM_IMSCR register If LVD detects the interrupt level after LVDINT bit in CM_IMSCR register is set to 1 LVDINT in CM_MISR register is set to 1 You can configure the level of LVD interrupt using LVDIL 2 0 fields in CM_MR register To clear the pending interrupt first clear the status bit LVDINT in CM_ICR and then the corresponding pending bit in NVIC
41. POCCS O0 Reset Value CM MR SYSCLK 1 0 b SYSCLK O CM MR SYSCLK 1 0 by user S W IMCLK PLLCLK gt SYSCLK SYSCLK Figure 5 2 System Clock Selection SAMSUNG ELECTRONICS 5 5 ex S3FN429_UM_REV1 20 5 Clock and Power Manager Table 5 2 describes the summary of smart option for clock manager To have the configuration for your system you should use this configuration smart option They decide the reset value of SYSCLK Pin8 XIN P0 31 Pin7 XOUT PO 30 and BTDIV Table 5 2 Summary of Smart Option for Clock Manager SO CSR Bit name and value The result after reset POCCS 0 SYSCLK EMCLK POCCS 0 SYSCLK IMCLK 0 GPIO P0 31 pin 1 XIN 0 GPIO P0 30 pin 1 XOUT pin BTDIV 3 0 3 BT DIVIDER 1 BTDIV 3 0 2 4 BT DIVIDER 2 BTDIV 3 0 5 BT DIVIDER 2 4 BTDIV 3 0 15 BT DIVIDER 4096 NOTE 1 SO_CSR Smart Option Configuration Status Register 2 When you program on flash operation other bits except the upper control bits field should be 1 For more information refer to the IFC Internal Flash Controller chapters 3 Smart option should be programmed before the operation Table 5 3 describes the clock status at reset and Wake Up Table 5 3 Clock Status at Reset and Wake Up It depends on smart option Status before STOP RUN If FWAKE is 0 status before STOP If FWAKE is 1 RUN PLLCLK STOP Disable Status before STOP
42. Table 7 1 Pin Description PHASEB Phase B input PHASEZ Phase Z input pope SAMSUNG ELECTRONICS 7 1 ex S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 2 Functional Description This section describes the functional description of PPD 7 2 1 Block Diagram Figure 7 1 illustrates the block diagram for PPD Position Capture Timer Hold PPD_CR1 PCTCL PCTHR A PPD_IMSCR clear 16 bit Position Capture gt PPD_RISR PPD_MISR PCTOVF gt Up Timer PCTR clear PPDCLK 4 bit e Prescaler PPD_CR1 PPD_CR1 PPD_IMSCR PCSYNCHCL PPD_CR1 PCTEN PPD_RISR PPD_MISR PCAPT Position Capture Timer Value PCTVR o Position Capture Timer Value Hold PCTVHR Position Counter Hold PCHR PPD_IMSCR PPD_CRO PPDFILTER um PPD MISR PCOVF DIRECTION Up or Down Counting 16 bit Up Down gt PPD_RISR PPDIMISREEOUNE Position Counter PPD CRO PHASEA PPD ESELA PCR clear PPD_CR1 PCCL IPHASEA he ES PPD_IMSCR S U 16 bit Comparator PPD_RISR L PPD_CRO PHASEB gt 5 COMP PPD CRO PHASEZ
43. WE d uas a ad PACFR IMC ASCFRO PWMXUO PWMXxU1 PWMxU2 0 PWMxD1 PWMxD2 Interrupt Can be used by ADC trigger signal Figure 10 10 Tri Angular Wave No SWAP a High Start PWMXUy and Low Start PWMxDy NOTE 1 Both the switches of upside and down side are low active 2 For 100 duty of upside you should set the rising falling compare register to 0 For 0 duty of upside you should set the rising compare register to equal to TOPCMP value SAMSUNG ELECTRONICS 10 11 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC Figure 10 11 illustrates the signal of PWM Assumption Duration of dead time is 2 percent duty Upside Upside 0 duty 33 duty T Setting Upside Upside 1 100 duty 3396 duty T x setting IE gt Upside Upside 1 duty 33 duty gi gi ng Upside 33 duty setting Upside 99 duty T Figure 10 11 Tri Angular Wave Duty No SWAP a High Start PWMxUy and Low Start PWMxDy SAMSUNG ELECTRONICS 10 12 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 2 3 6 Tri Angular Wave IMMODE 0 PWMSWAP 1 PWMPOLU 1 High Start and PWMPOLD 0 Low Start Figure 10 12 illustrates the Tri Angular wave SWAP a High Start PWMxUy Low Start PWMxDy IMC_TCR a Ade mn ASCRR2 s ds on IMG ASCRRT me RE
44. FINMH P M S 1 8 P M s LFPass __2 2 s 4 2 0 3 a o 6 o o 0 __2 6 o s o 0 6 o 0 6 s o 2 SAMSUNG ELECTRONICS 5 64 en S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 1 19 CM_BTCDR e Base Address 0 4002 0000 Address Base Address 0 0070 Reset Value 0x0000 000X 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 BTCDKEY BE Key for Write Access into the CM_BTCDR Register BTCDKEY 31 16 W Any write in CM_BTCDR register bits is only effective if the BTCDKEY is equal to 0x3569 RSVD A Remd Firstly in bear chip status all bits in the SO_CSR refer Program Flash Controller PFC section 1 That means the BT clock is IMCLK 40 MHz and BT Clock Divider is 4096 At reset BT counting time is 26 214 ms 256 count with 40 MHz 4096 The clock manager block runs BT when chip resets or wakes up from stop mode BT counts the defined time to stabilize the internal system logic BT counting clock source is SYSCLK SYSCLK can be IMCLK EMCLK or P
45. Figure 5 15 illustrates the L VD block diagram CM_MR LVDRLI2 0 Er SR Er LVDRST comparator LVD Reset p LVD Reset Register String LVD Interrupt mene LVDI mene nd B 2 p EE LVDINT LVD LVDINTEN E Interrupt CM_IMSCR CM_MR LVDINT LVDIL 2 0 VREF BANDGAP Figure 5 15 LVD Block Diagram The level for LVD reset should be less than the level of LVD interrupt If LVD detect the target level when those levels are the same LVD generates the reset That means the priority of LVD reset is higher than LVD interrupt SAMSUNG ELECTRONICS 5 28 lt x S3FN429_UM_REV1 20 5 Clock and Power Manager 5 6 4 External Main Clock Monitor Reset EMCMRST For more information Refer to Chapter 5 2 5 Clock Monitor 5 6 5 Watchdog Timer Reset WDTRST Watchdog Timer Reset occurs when Watchdog Timer counter value reaches 0 overflow event under the condition that both watchdog timer and reset are enabled After Watchdog Timer Reset WDTRSTS bit in CM SR register sets to 1 The user software or other resets hardware can clear this bit 5 6 6 Software Reset SWRST Software reset occurs when it writes 1 to CM SRR register After the software reset the SWRSTS bit in CM SR register sets to 1 The user software or other resets hardware can clear this bit 5 6 7 CPU Request Reset SYSRST CPU initializes the device state itself when it writes 1 to SYSR
46. NOTE The RUN is explained in the Clock Manager view SAMSUNG ELECTRONICS 5 6 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 2 2 IMCLK The IMCLK means an Internal Main Clock 40 MHz After any reset this clock is always enabled by default While chip operates you can enable or disable the IMCLK by controlling the IMCLK bit in the CM_CCR CM_CSR register The IMCLK is the SYSCLK with reset value by manufacture IMCLK can become SYSCLK by the POCCS bit of the SO_CSR register at reset time Refer to IFC chapter for more details After reset the IMCLK supplies clock to the SYSCLK when the SYSCLK field in the CM_MR register is 01 b The IMCLK is used as the reference clock for the EMCLK monitor function If you want to check the functionality clocking or not of the EMCLK then you should enable the IMCLK and the associated Clock Monitor function If an enabled clock monitor function detects EMCLK clock fail and EMCMRST External Main Clock Monitor Reset occurs the IMCLK runs as the SYSCLK after reset When the clock monitor function is enabled enabled IMCLK can t be disabled although you write 1 b to IMCLK bit in CM_CCR register 5 2 3 EMCLK EMCLK means an External Main Clock The acceptable frequency range of External Clock Oscillator is from 1 to 12 MHz EMCLK can be generated the crystal ceramic resonator or the external clock When you use the resonators and load capacitors as components of an External Oscillator Circ
47. On a Write of 1 it clears the corresponding interrupt A Write of 0 has no effect SAMSUNG ELECTRONICS 15 27 ex S3FN429_UM_REV1 20 16 Timer Counter Timer Counter 16 1 Overview The Timer Counter TC chapter describes TIMER COUNTER module that operates in match and overflow capture interval or in PWM operation The TC can also generate PWM signals through the dedicated pin and supports an external clock as its source clock 16 1 1 Features The features of TC are e Programmable clock source for timer including an external clock e Programmable n bit up counter with up to 16 bit One shot operation or Repeated operation e Match and Overflow operation e Capture operation Capture on rising edge falling edge or both edges Two capture registers for each edge e Interval operation e Pulse Width Modulation PWM operation Programmable duty cycle and frequency Programmable active level and idle level Upto 22 bit resolution including extension function e Debug option e Analog to Digital Converter ADC trigger source SAMSUNG ELECTRONICS 16 1 ex S3FN429_UM_REV1 20 16 Timer Counter 16 1 2 Pin Description Table 16 1 describes the pin description of TC Table 16 1 Pin Description PinName Function VO Type TCLKn External clock input pin 4 3 NOTE n means the channel number of TC For example they will be TCLKO TCAPO and TPWMO where n is 0 SAMSUNG ELECTRONICS 16 2 ex
48. S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter LE See 50 m m E SAMSUNG ELECTRONICS 17 8 27 S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter Table 17 3 describes the synchronous mode SYNC 1 Table 17 3 Synchronous Mode SYNC 1 Error 0 02 95 0 03 0 03 0 16 0 22 0 16 0 16 96 0 01 96 0 04 0 06 96 0 06 96 0 15 95 0 06 96 0 06 96 0 00 0 05 0 05 0 16 96 0 16 96 0 16 96 0 16 96 0 03 0 03 96 0 10 0 16 96 0 16 0 35 96 0 35 0 03 0 03 0 16 0 16 96 0 22 0 16 96 SAMSUNG ELECTRONICS 17 9 S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter PCLK MHz US BRGR CD 15 0 96 Error 977 x 16 1200 0 04 488 x 16 2400 0 06 244 16 4800 0 06 18 75 488 16 1200 0 06 244 16 2400 0 06 9 375 18 16 15 10 122 16 4800 0 06 61 16 9600 0 06 417 x 16 1200 0 08 208 x 16 2400 0 16 104 16 4800 0 16 52 x 16 9600 0 16 26 x 16 19200 0 16 SAMSUNG ELECTRONICS 17 10 S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 15 se SAMSUNG ELECTRONICS 1224 27 S3FN429_UM_REV1 20 17 Universal Synchronous Asy
49. SAMSUNG ELECTRONICS 4 4 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 1 6 Conversion Mode This section describes Conversion Mode and Sequence of ADC 4 1 6 1 Conversion Sequence A conversion sequence is a sequence of conversion of analog inputs You can configure ADC block to make conversions of some of the 10 inputs and an input by OP AMP in its own order The setting of the CCNT field in the ADC Mode Register ADC_MR defines the length of the sequence the number of conversions Table 4 3 describes the relation between the CCNT field and the number of conversion performed in a sequence Table 4 3 CCNT Values and the Number of Conversions 6 times conversion operation rom IONUMOIS 0 10 NUNES StmescomersonopertonfomiCNUMOROICNUM EO 10 o times conversion operation rom SAMSUNG ELECTRONICS 4 5 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC When configured in one shot mode the ADC performs the specified number of conversion after a start request At the end of each conversion sequence the data register gets updated with the conversion result You can program the conversion of a sequence in CCSRO CCSR1 Conversion Channel Sequence Register The ICNUMO field defines the first input conversion in sequence The ICNUM field defines the second input conversion and this sequence continues Table 4 4 descri
50. TC RISR PSTARTI TC_RISR PENDI TC_RISR MATI TC_RISR OVFI Interrupts are cleared by writing a 1 to corresponding bits in Figure 16 2 Match and Overflow Operation Timing SAMSUNG ELECTRONICS 16 5 ex S3FN429_UM_REV1 20 16 Timer Counter To stop the timer you should clear the START bit in TC_SR register by writing 1 to START bit in TC_CCR register The timer stops according to the STOPHOLD bit and STOPCLEAR bit in TC_SR register Figure 16 3 illustrates the counter values according to START STOPCLEAR and STOPHOLD TC_SR START STOP after Overflow TC_CVR COUNT STOPCLEAR 0 STOPHOLD 0 STOP immediately STOPCLEAR 1 STOPHOLD X STOPCLEAR 0 STOPHOLD 1 PAUSE and RESUME Figure 16 3 Counter Values According to START STOPCLEAR and STOPHOLD To stop the timer right after the counter overflows you should clear both STOPHOLD bit and STOPCLEAR bit in TC_SR register before clearing START bit The counter value is cleared to 0 To stop the timer immediately you should set the STOPCLEAR bit in TC_SR register before clearing START bit The timer is stopped immediately and the counter value is cleared to 0 To pause the timer immediately you should set the STOPHOLD bit but you should clear the STOPCLEAR bit in TC_SR register before clearing START bit The timer is stopped immediately but the timer holds the counter value Therefore when the timer is resumed by setting ST
51. The common Receive FIFO is a 16 bit wide 8 locations deep FIFO memory buffer Received data from the serial interface are stored in the buffer until read out by the CPU across the AMBA APB interface When configured as a master or a slave the serial data received through the SSPRXD pin is registered prior to parallel loading into the attached slave or master Receive FIFO respectively SAMSUNG ELECTRONICS 15 5 ex S3FN429_UM_REV1 20 15 Serial Peripheral Interface SPI 15 2 2 1 2 6 Transmit and Receive Logic When configured as a master the clock to the attached slaves is derived from a divided down version of FSSPCLK through the pre scaler operations The master transmit logic successively reads a value from its Transmit FIFO and performs a parallel to serial conversion on it Then the serial data stream and frame control signal synchronized to SSPCLKOUT are output through the SSPTXD pin to the attached slaves The master receive logic performs a serial to parallel conversion on the incoming synchronous SSPRXD data stream extracting and storing values into its Receive FIFO for subsequent reading through the APB interface When configured as a slave the SSPCLKIN clock is provided by an attached master and used to time its transmission and reception sequences The slave transmits logic that is e Under the control of the master clock e Successively reads a value from its Transmit FIFO e Performs parallel to serial conversion e
52. 158 XQ 4 4 to 16 bits 1 SSPRXD Figure 15 4 Motorola SPI Frame Format with SPO 0 and SPH 1 In this configuration during idle periods e The SSPCLKOUT signal is forced LOW e SSPFSSOUT is forced HIGH e The transmit data line SSPTXD is arbitrarily forced LOW e When the PrimeCell SSP is configured as a master the SSPCLKOUT is enabled e When the PrimeCell SSP is configured as a slave the SSPCLKOUT is disabled If the PrimeCell SSP is enabled and there is valid data within the Transmit FIFO the start of transmission is signified by the SSPFSSOUT master signal being driven LOW The master SSPTXD output pas is enabled After a further one half of the SSPCLKOUT period both master and slave valid data is enabled onto their respective transmission lines At the same time the SSPCLKOUT is enabled with a rising edge transition Data is then captured on the falling edges and propagated on the rising edges of the SSPCLKOUT signal In the case of a single word transfer after all bits have been transferred the SSPFSSOUT line is returned to its idle HIGH state one SSPCLKOUT period after the last bit has been captured For continuous back to back transfers the SSPFSSOUT pin is held LOW between successive data words and termination is the same as that of the single word transfer SAMSUNG ELECTRONICS 15 12 ex S3FN429_UM_REV1 20 15 Serial Peripheral Interface SPI 15
53. S3FN429_UM_REV1 20 16 Timer Counter 16 3 1 16 TC_CCDR e Base Address 0 4006 0000 4006 1000 0 4006 2000 e Address Base Address 0x003C Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 Reserved CT Indicates current DIVM Indicates current DIVN __ NOTE The equation to define the Counter Clock is Counter Clock Clock Source DIVM 1 2 DIVN SAMSUNG ELECTRONICS 16 38 ex S3FN429_UM_REV1 20 16 Timer Counter 16 3 1 17 TC_CCSMR e Base Address 0 4006 0000 0x4006_1000 0 4006 2000 Address Base Address 0x0040 Reset Value 0x0000 000F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 Indicates current Counter Size The counter can count from 1 to 2579 1 SAMSUNG ELECTRONICS 16 39 ex S3FN429_UM_REV1 20 16 Timer Counter 16 3 1 18 TC_CPRDR e Base Address 0 4006 0000 4006 1000 0 4006 2000 e Address Base Address 0x0044 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 1 0 PERIOD 15 0 Indicates current PERIOD value D n o lt SAMSUNG ELECTRONICS 16 40 S3FN429_UM_REV1 20 16 Timer Counter 16 3 1 19 TC_CPULR e Base Address 0 4006 0000 4006 1000 0 4006 2000 e Address Base Address 0x0048 Reset Value 0x0000 0000 31 30 2
54. SAMSUNG ELECTRONICS Command SE Sector Erase 011 b Figure 9 6 Sector Erase Flowchart 9 18 S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 2 4 4 Entire Erase Figure 9 7 illustrates the Entire Erase flowchart KEY lt lt 0x5A5A5A5A CR lt lt Command START Flash has a protected area Yes Error2 END Bit Set Command CE Entire Erase 100 b Figure 9 7 Entire Erase Flowchart SAMSUNG ELECTRONICS 9 19 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 2 4 5 Smart Option Program Figure 9 8 illustrates the Smart Option flowchart KEY lt lt 0x5A5A5A5A ADDR lt lt target smart option address 0x000000C0 Protection Smart Option 0x000000C4 Chip Configuration Smart Option Y DATA Smart Option Value v CR lt lt Command START END Bit Set Command SOP Smart Option Program 101 b Figure 9 8 Smart Option Program Flowchart SAMSUNG ELECTRONICS 9 20 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 2 4 6 Smart Option Erase Figure 9 9 illustrates the Smart Option Erase flowchart Start KEY lt lt 0x5A5A5A5A lt lt 5 Smart option erase includes both protection and configuration smart option If user need to change partial value user should read and stor
55. Stops the counter IDLE State Level 0 No effect 1 The output signal level will be LOW in Idle state Reserved SAMSUNG ELECTRONICS 16 26 ex S3FN429_UM_REV1 20 16 Timer Counter 16 3 1 7 TC_SR e Base Address 0 4006 0000 4006 1000 0 4006 2000 e Address Base Address 0x0018 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 re s s 5 wes ss wee fe sorrow ss wen s s f REPEAT 5 storom Bit Description Reset Value 81 30 31 30 Reserved RSVD 2 10 14 18 22 26 30 34 38 42 46 50 54 58 62 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 PWMEXS 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 RSVD 23 19 Reserved Capture by Rising Edge Trigger 0 External rising edge capture is disabled 1 External rising edge capture is enabled When the TC detects rising edge of external input signal on TCAP pin it stores the current counter value into the capture up register Capture by Falling Edge Trigger 0 External falling edge capture is disabled 1 External falling edge capture is enabled When the TC detects falling edge of external input signal on TCAP pin it stores the current counter value into the capture down register mv ta A SAMSUNG ELECTRONICS 16 27
56. select the level for reset and interrupt voltage using LVDRL 2 0 and LVDIL 2 0 in the MRO register 2 LVD hysteresis is only characterization data and not tested in the mass production The minimum value of hysteresis is the simulation data SAMSUNG ELECTRONICS 19 11 ex S3FN429_UM_REV1 20 19 Electrical Data 19 12 12 bit ADC Electrical Characteristics Table 19 12 describes the electrical characteristic parameters of a 12 bit ADC Table 19 12 ADC Characteristics Ta 40 to 105 VppcorE 2 5to 5 5 V AVpp 2 5 0 5 5 V Resolution posee Reference voltage Ped Input voltage range LOW Clock frequency 50 duty cycle Maximum conversion time Max Fanc AVpp AVrer 2 5V Differential nonlinearity i qued 5 to 5 5 2 51055 INL ntegral nonlinearity AVss 0 0 V AVrer 4 0 V to 5 5 V aid AV 2 5 V to 4 0 V REF 04 Offset error unadjusted NOTE AVrer 4 0 V to 5 5 V BOTOFF AVner 2 5Vto4 0V NOTE The values are the characteristic data and not tested during mass production SAMSUNG ELECTRONICS 19 12 ex S3FN429_UM_REV1 20 19 Electrical Data 19 13 Comparator Electrical Characteristics Table 19 13 describes the electrical characteristic parameters of a comparator Table 19 13 Comparator Electrical Characteristics Ta 40 to 105 2 5 to 5 5 V AVpp 2 5 to 5 5 V
57. 0xE404 Reset Value 0 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 R RI R RIJR R R R R IRI IR R RI R R R R RIJRI R RIR RIRIR R R R R R R R WwiW INI IW WIWI IW W W W W W W W W W W W W W W W W W W W W W W W W W PRI N7 31 30 Type 51 30 RW The priority ofthe interrupt vector number _ Re _____ 924 RW Reed 23 22 RW Tre priority of the interrupt vector number Revo RW Reed PRINS 0514 Rw The priority ofthe interrupt vector numbers Rv RW Remd 09 RW Tre priority of the interrupt vector number ww AW Reseved SAMSUNG ELECTRONICS 11 12 en S3FN429_UM_REV1 20 11 Interrupt Controller INTC 11 3 1 7 NVIC_IPR2 Base Address 0 000 0000 Address Base Address 0xE408 Reset Value 0 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 PRI N11 B PRI N10 PRI 9 B PRI 8 ale EXT EXIT zm RIR R RIR R I R R RIR IR RI R RIR R R R R R R R Bit Type 9 9 RSVD __ feri Rw Reseved ae 9 PRI N11 31 30 15 13 7 rou NN PRI 8 RSVD 5 0 30 24 22 16 141 8 6 SAMSUNG ELECTRONICS 11
58. 1 Enables debug mode ADC is halted during processor debug mode v eon a aeea ADC Controller Clock Enable Disable Bit 0 Disables ADC Clock CLKEN 1 Enables ADC Clock ADC software reset does not affect CLKEN bit status SAMSUNG ELECTRONICS 4 19 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 2 1 3 ADC_SRR e Base Address 0 4004 0000 e Address Base Address 0x0008 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 sur Software Reset W 0 No effect 1 Performs ADC software reset operation SAMSUNG ELECTRONICS 4 20 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 2 1 4 ADC_CSR e Base Address 0 4004 0000 e Address Base Address 0x000C Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 14 13 12 11 10987 6 5 4 3 gt ___ gt sme ADC Continuous Conversion Stop 0 No effect 1 Stops the continuous conversion NOTE Before starting the conversion you should ensure that ADC is ready for conversion Ready bit is set to 1 in ADC_SR WE NEN ADC Conversion Start Bit 0 No effect 1 Starts ADC conversion This is one of the ADC trigger sources software trigger ADC Core Enable Bit 0 No effect 1 Enables ADC core bit NOTE After enabling ADC block ADCEN 1 ADC block converts analog value after stabilizatio
59. ADC 4 2 1 11 ADC_SR e Base Address 0 4004 0000 e Address Base Address 0x0060 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 1 Overrun Status 0 No overrun 1 Overrun occurs Reserved Conversion Mode Status 0 Selects One Shot mode with the help of microprocessor 1 Selects Continuous mode the peripheral is stand alone Initialize this bit to 0 and the bit changes when there is change of mode This bit never generates any interrupts mv ia A ADC Status Monitoring Bit This bit notifies the status of ADC BUSY 1 0 ADC 5 notona conversion operation 1 ADC is on a conversion operation NOTE To change the configuration of ADC you should check ADC Status Register ADC_SR or R SAMSUNG ELECTRONICS 4 30 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 0 Disables ADC Core or ADC is not stabilized even if ADC Core is enabled 1 ADC is stabilized This bit is set after initialization time When this bit is 1 ADC can convert data SAMSUNG ELECTRONICS 4 31 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 2 1 12 ADC_IMSCR e Base Address 0 4004 0000 e Address Base Address 0x0064 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 81 7 Overrun Interrupt Mask 0 OVR interrupt is masked Disables
60. ASCRR2 2 4 te ee es IMC PCCRR ei ie a te et eae ae ae we fo ar 2 5 2 aut alent eer meal ue emo her asia cates RE ei vee IMC_ASCRRO IMC_PACRR PWMXxUO PWMXxU1 PWMxU2 PWMxDO PWMxD1 PWMxD2 Interrupt Can be used by ADC trigger signal Figure 10 17 Saw Tooth Wave SWAP Low Start PWMxUy and High Start PWMxDy NOTE 1 Both the switches of upside and down side are high active 2 For 0 96 duty of upside you should set the rising falling compare register to For 100 96 duty of upside you should set the rising compare register to equal to TOPCMP value SAMSUNG ELECTRONICS 10 18 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 2 3 11 Saw Tooth Wave IMMODE 1 PWMSWAP 0 PWMPOLU 0 Low Start and PWMPOLD 0 Low Start Figure 10 18 illustrates the Saw Tooth wave No SWAP a Low Start PWMxUy and Low Start PWMxDy IMC_TCR fo ct ct n m n IMC_ASCRR2 PCCRR ASCRR1 IMG PBORH ae t rte as IMC_ASCRRO IMC_PACRR PWMXxUO PWMXU1 PWMxU2 PWMxDO PWMxD1 PWMxD2 Interrupt Can be used by ADC trigger signal Figure 10 18 Saw Tooth Wave No SWAP
61. Enables Pull Up resistor on pin IOO y NOTE SWD pins Port 28 and 29 of PIOO multiplexed with GPIO have the internal Pull Up resistor enabled by default When these ports are not used for SWD we strongly recommend to disable the internal Pull Up resistors by the software after reset pem 5 SAMSUNG ELECTRONICS 12 7 ex S3FN429_UM_REV1 20 12 Configuration 12 3 1 4 IO ODCRO Base Address 0x4005 8000 e Address Base Address 0x000C Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 100_30_ODEN 29 ODEN 28 ODEN 27 ODEN 0 26 ODEN 0 25 ODEN 24 ODEN 100_23_ODEN 22 ODEN 21 ODEN 20 19 ODEN 0 18 ODEN 17 ODEN 0 16 15 ODEN 14 ODEN 0 13 100_12_ODEN 100_7_ODEN 00 6 ODEN IO0 5 ODEN 00 4 ODEN 100 3 ODEN 00 2 ODEN 00 1 ODEN 00 0 ODEN 0 11 0 10 ODEN 00 9 ODEN 31 ODEN 100 8 za za sar Exe RIR R R R R R R JRI IR R R JR R R R IRIR R R R R R R R WwiW IW W IN W W W W W W W W W W W W W W W W W W W W 00 y Open Drain Enable Disable 0 Disables Open Drain output mode on pin IOO y D i Push Pull Output mode 1 Enables Open Drain Output mode on pin IOO y SAMSUNG ELECTRONICS 12 8 ex S3FN429_UM_REV1 20 13 Opera
62. If the SPH clock phase control bit is HIGH data is captured on the second clock edge transition 15 2 2 1 3 9 Motorola SPI Format with SPO 0 SPH 0 Figure 15 2 and Figure 15 3 illustrates the single and continuous transmission signal sequences for Motorola SPI format with SPO 0 and SPH 0 respectively sspcLK 4 NY NT NN SSPFSS E E RE MC MEME SSPRXD OG C 58 0 e a 4 to 16 bits Le SSPTXD C X LSB Figure 15 2 Motorola SPI Frame Format Single Transfer with SPO 0 and SPH 0 SAMSUNG ELECTRONICS 15 10 ex S3FN429_UM_REV1 20 15 Serial Peripheral Interface SPI SSPCLK pua 2 2 47 SSPFSS CMSBY gt TS MSE 1 1 1 E 1 1 1 1 Figure 15 3 Motorola SPI Frame Format Continuous Transfer with SPO 0 and SPH 0 In this configuration during idle periods e The SSPCLKOUT signal is forced LOW e SSPFSSOUT is forced HIGH e The transmit data line SSPTXD is arbitrarily forced LOW e When the PrimeCell SSP is configured as a master the SSPCLK pin is enabled e When the PrimeCell SSP is configured as a slave SSPCLK pin is disabled If the PrimeCell SSP is enabled and there is valid data within the Transmit FIFO the start of transmission is signified by the SSPFSSOUT master signal being driven LOW This causes the slave data to be enabled onto the SSPRXD input line of the master
63. R R R RI IR RJ R R R R R mw R Red Compare Data for 15 TOP EMER AT This field determines the TOP compare register value NOTE The update of TCR can be executed only when IMC is disabled 0 0 0 Caution IMC_PACRR FR PBCRR FR and PCCRR FR should be less than or equal to TCR PXCRR FR lt TCR SAMSUNG ELECTRONICS 10 51 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 3 1 13 IMC_DTCR Base Address 0 400 0000 e Address Base Address 0 0030 Reset Value 0 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 DTCMPDAT es RIR R R R R R R R R R mw _ DTCMPDAT 15 0 Compare Data for Dead Time 0 0000 This field determines the dead time compare register value NOTE If you use ADC compare interrupt you should set ADCCMPR Fx from 1 to TOPCMP 1 0 lt ADCCMPR Fx lt TOPCMP SAMSUNG ELECTRONICS 10 52 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 3 1 14 IMC_PACRR Base Address 0 400 0000 Address Base Address 0x0034 Reset Value 0 0000 0000 31 30 29 28 27 26 25 24123 22 21 20 19 18 17 16 15 14 13 12 11 10 a B A PACMPRDAT ele
64. Rag Uk FDC Supply Votage for Voncone Ve 02060 Do Supply Votage toro Vn 03 60 Supply VotageforAVoe Avo 03989 DC Supply Votage tor Ame 2060 VO Input Votage 03 03 1 2 NOTE Do not operate the device above the Absolute Maximum Ratings Samsung cannot guarantee that the device will operate as desired SAMSUNG ELECTRONICS 19 1 ex S3FN429 UM REV1 20 19 Electrical Data 19 3 Recommended Operating Conditions This semiconductor device will require recommended operating conditions to ensure normal operation The warranty on electrical characteristics of 53 429 is valid as long as you operate it according to the recommended operating conditions If you operate the device beyond the recommended electrical parameter then it might adversely affect reliability of the device and can lead to a device failure Table 19 2 describes the recommended operating conditions at which the device will operate as desired Table 19 2 Recommended Operating Conditions DC supply voltage for I O Vmo 2 5 to 5 5 DC supply voltage for AVrer 502 2 5 to AVpp 25558 Operating emprar 1 491 SAMSUNG ELECTRONICS 19 2 ex S3FN429_UM_REV1 20 19 Electrical Data 19 4 Characteristics Table 19 3 describes the I O characteristics for semiconducting device Table 19 3 Characteristics Ta 40 to 105 C
65. S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 3 1 12 IFC_DR e Base Address 0x4001_0000 e Address Base Address 0x002C Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 1 0 RI RI R RIJR R R R R I RI IR R RI R R R R RIRI R RIR R IR R R R R R R R R wiw iWw Ww W W W W W W W W W W W W W W W W W W W W W W W W W W W W Data to Write on the Target Address Register AR of the Internal Flash Memory e DATA 31 0 lt You select specific word data 4B to be written into the flash memory DATA 31 0 RW DATA 31 0 lt Trimming data in case of Configuration Smart Option If you program with target value to change a Configuration Option other bits except control bits field is set to 1 DATA 31 0 Protection option data in case of Protection Smart Option NOTE The DR register is auto cleared after finishing command operation SAMSUNG ELECTRONICS 9 39 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 3 1 13 IFC_KR e Base Address 0x4001_0000 e Address Base Address 0x0030 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 1 0 Key Register Value for Program and Erase Operation You can program any data into the flash memory or erase the data in the program mode A specific register key register is used to prevent flash data from getting destroyed accidentally You
66. SAMSUNG ELECTRONICS 5 35 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 1 1 CM_IDR e Base Address 0 4002 0000 e Address Base Address 0x0000 Reset Value 0x0001_001C Identification Code Register Mn 0 0001_001 This field stores the ID code for the corresponding IP SAMSUNG ELECTRONICS 5 36 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 1 2 CM_SRR e Base Address 0 4002 0000 e Address Base Address 0x0004 Reset Value 0x0000 0000 Software Reset Key This is the key for Write access into the CM_SRR register Writing in CM_SRR register is only effective if SWRSTKEY 31 16 W the SWRSTKEY is equal to 0xA66A In other words to generate a software chip reset you should write the SWRST bit with SWRSTKEY value OxA66A mv a Reseed CM Software Reset 0 No effect SWRST W 1 Performs software ol operation and auto clears This reset generates chip reset It is one of the reset sources When the software reset occurs SWRSTS bit in CM SR register will be set to 1 after reset SAMSUNG ELECTRONICS 5 37 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 1 3 CM_CSR e Base Address 0 4002 0000 e Address Base Address 0x0008 Reset Value 0x0000 0000 31 24 Reserved External Main Clock Monitor Function Enable Control Bit 2 EMCM 23 W 1 Enables the Main Clock Monitor function This function is to d
67. The value of NUMSKIP affects interrupt also If IMC_ASCRRx FRx is set to interrupt source and the value of NUMSKIP is 1 then the interrupt does not occur in the second and fourth pulse SAMSUNG ELECTRONICS 10 36 S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC Figure 10 31 illustrates the skip control of ADC trigger signal interrupt IMC TCR IMC ASCRRO IMC ASCFRO Interrupt Can be used by ADC trigger signal Figure 10 31 Skip Control of ADC Trigger Signal Interrupt SAMSUNG ELECTRONICS 10 37 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 3 1 5 IMC_CR1 Base Address 0 400 0000 Address Base Address 0x0010 Reset Value 0 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 7 6 LEVEL PWMxU1 LEVEL PwwxUaEVEL PWMxDOLEVEL Pwmp eve Eom Pwmuon Pwmuen gt 2 Pwmu n PWWwotN PWMxD2EN R R R 2 5 x n R gt gt gt gt RSVD 81 22 PWMXxUO Dead Time Insert Bit This bit determines whether dead time is inserted or not PWMXxUODT 21 before PWM output disable by setting PWMxUOEN 0 Does not insert dead time
68. Time Guard configuration field oe 7 0 Disables the transmitter time Disables the transmitter time guard function function 0x00 of each character for the time duration Time guard duration Time guard duration 0 7 0 x bit period 0 x bit period SAMSUNG ELECTRONICS 17 45 ex S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 9 4 to 40 MHz Asynchronous Mode Table 17 4 Asynchronous Mode SYNC 0 SYSCLK PDIV PCLK US BRGR CD 15 0 Baud Rate 1200 2400 4800 9600 19200 1200 2400 4800 9600 1200 2400 4800 1200 2400 1200 1200 2400 4800 9600 19200 38400 1200 2400 4800 9600 19200 1200 2400 4800 9600 1200 2400 4800 1200 1201 92 2403 85 4807 69 9615 38 19230 77 1201 92 2403 85 4807 69 9615 38 1201 92 2403 85 4807 69 1201 92 2403 85 1201 92 1199 04 2403 85 4807 69 9615 38 19230 77 38461 54 1201 92 2403 85 4807 69 9615 38 19230 77 1201 92 2403 85 4807 69 9615 38 1201 92 2403 85 4807 69 1201 92 SAMSUNG ELECTRONICS 17 46 27 S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter SYSCLK PDIV PCLK US BRGR CD 15 0 Baud Rate 96 Error 0 16 96 0 04 96 0 08 0 16 96 0 16 96 0 16 96 0 16 96 0 08 0 16 96 0 16 96 0 16 96 0 16 96 0 16 96 0 16 96 0 16 96 0 16 96 0 16 96 0 16 96 0 16 96 0
69. ay de 2 A rt ASCFR2 ASCRRO PBCFR s s on n n _ e 0 11 IMC_ASCFR1 IMC_PACFR IMC_ASCFRO Interrupt Can be used by ADC trigger signal Figure 10 12 Tri Angular Wave SWAP High Start PWMxUy and Low Start PWMxDy NOTE 1 Both the switches of upside and down side are low active 2 For 0 duty of upside you should set the rising falling compare register to 0 For 100 duty of upside you should set the rising compare register to equal to TOPCMP value SAMSUNG ELECTRONICS 10 13 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 2 3 7 Tri Angular Wave IMMODE 0 PWMSWAP 0 PWMPOLU 1 High Start and PWMPOLD 1 High Start Figure 10 13 illustrates the Tri Angular wave No SWAP High Start PWMxUy and High Start PWMxDy IMC_ASCRR2 4 04 0 IMG PCCHR sem ASORAT RR Spem o ee 2E PCCFR nn II nl aa IMC_ASCFR2 IMC_ASCRRO IMG 3e lt a es Ge ted a _ y IMC_ASCFRI ct tt on e d Re Rn mei EN ASCFRO 4 Interrupt Can be used by ADC trigger signal Figure 10 13 Tri Angular Wave No SWAP a High Start PWMxUy and High Start PWMxDy NOTE 1 The switch of upside is low active and the swit
70. the CM WRISR register gives the current raw status value of the corresponding interrupt prior to unmasking A Write has no effect SAMSUNG ELECTRONICS 5 71 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 1 25 CM_EEMISR e Base Address 0 4002 0000 e Address Base Address 0x0090 Reset Value 0x0000 0000 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 External Event Masked Interrupt Status Bit CM WMISR CM WIMSCR and CM WRISR 0 Source X interrupt does not occur 1 Source X interrupt occurs NOTE On a Read the CM WRISR register gives the current unmasked status value of the corresponding interrupt A Write has no effect SAMSUNG ELECTRONICS 5 72 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 1 26 CM_EEICR e Base Address 0 4002 0000 Address Base Address 0x0094 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 O Om NI uj Lj Lj Ll Inin n n n njn njnjn n n a n n n n n n n n n n n w w w w w w w w External Event Interrupt Clear Bit 0 No Effect 1 Clears the external event interrupt NOTE Ona Write of 1 it clears the corresponding interrupt A Write of 0 has no effect SAMSUNG ELECTRONICS 5 73 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 1 27 CM_NISR e Base Address 0 4002 0000 e Address Base Addre
71. tn Voo 50v 200 soo 40 NOTE The noise filter for external signal has the distribution like as from 200 ns to 400 ns If the external signal width is smaller than minimum value 200 ns it is always recognized as an invalid signal If the external signal width is greater than maximum value 400 ns it is always recognized as a valid signal Figure 19 2 illustrates the input timing diagram for an external interrupt External Interrupt Figure 19 2 Input Timing for External Interrupt SAMSUNG ELECTRONICS 19 6 ex S3FN429_UM_REV1 20 19 Electrical Data 19 8 Oscillator Characteristics The two kinds of oscillators are e External Main Oscillator e Internal Main Oscillator 19 8 1 External Main Oscillator Characteristics Table 19 7 describes the external main oscillator characteristics Table 19 7 External Main Oscillator Characteristics 40 to 105 C Vpp Vppcone Vppio 2 5 to 5 5 V Fence ERR Vac Vea sd External Clock External clock Open Pin Crystal resonator ceramic B Caution If you don t the external main oscillator when and pin8 are defined XOUT and XIN function you should tie XIN to ground XOUT should be opened SAMSUNG ELECTRONICS 19 7 x S3FN429_UM_REV1 20 19 8 2 Internal Main Oscillator Characteristics Table 19 8 describes the internal ma
72. wo ft amp gt ___ 1_ je wee je e RSVD 31 30 PWM Extension Control Bit rie No effect Includes the corresponding stretched cycle number Stretched Cycle Number PWMEXS w OOOO OU 4 12 20 2 44 52 PWMEX2 PWMEX3 0 28 36 52 60 SMEG 18 22 26 30 34 38 42 46 50 PWMEXO 1 3 5 7 9 11 13 15 17 19 21 23 25 27 PWMEX5 29 31 33 35 37 39 41 43 45 47 49 51 58 55 57 59 61 63 If PNMEXO and PWMEXG3 are set to 1 then the PWM inserts extra 1 cycle at 32 and 4 12 20 28 36 44 52 60 Svo ____ PWM Interval Mode PWMIM 11 0 No effect KEEP 10 1 Specifies PWM Interval Mode PWM phase toggles when a period matches SAMSUNG ELECTRONICS 14 17 Keep Last Period State 0 No effect 1 Keep the PWM output level when PWM stops When PWM is restarted PWM output level begins at the kept PWM output level regardless of IDLE level S3FN429_UM_REV1 20 14 Pulse Width Modulation PWM Output Start Level 0 No effect ost 1 Starts PWM output level from high Logic 1 for the specified PERIOD IDLE State Level IDLESL W 0 No effect 1 Idle State PWM Output Level is High Logic 1 mv a a mew Update PWM Parameter 0 No effect UPDATE 1 Updates PWM Parameter Period Pulse and Clock Divider Start PWM START W 0 Noeffect 1 Starts PWM Ope
73. 0 9 bit Character Length MODE9 17 0 The CHRL field defines the character length 1 9 bit character length Smart Card Protocol SMCARDPT 16 0 Disables smart card protocol on USART 1 Enables smart card protocol on USART Channel Mode e Channel mode field 1 0 Mode Description Normal Mode The USART channel operates as an Rx Tx CHMODE 15 14 USART Automatic Echo Receiver data input connects to the USARTTX pin Local Loop back Transmitter output signal connects to the receiver input signal SAMSUNG ELECTRONICS 17 28 ex S3FN429_UM_REV1 20 NBSTOP 13 12 11 9 RW SYNC CLKS SAMSUNG ELECTRONICS 17 Universal Synchronous Asynchronous Receiver Transmitter Description Remote Loop back USARTRX pin connects internally to the USARTTX pin Number of Stop Bits The interpretation of the number of stop bits depends on SYNC e NBSTOP configuration field Synchronous c yhoo NENNEN INNEN C NN i i e Parity type field PARI2 0 Multi drop mode X X NOTE For LIN PAR 2 0 should be set to 10X Synchronous Mode Select 0 USART operates in Asynchronous Mode 1 USART operates in Synchronous Mode EN IN EN EX Character Length Start stop and parity bits are added to the character length e Character length field CHL REN Clock selection BaudRate generator input clock e CLKS clock selection field CLKS 1 0 Selected Clock
74. 0 field in the SSPCRO register can be programmed as zero Similarly the ratio of the SSPCLK maximum frequency to SSPCLKOUT minimum frequency is 254 x 256 The minimum frequency of SSPCLK is governed by the following equations both of which have to be satisfied F gspcik Minimum 2 x Fsspcikout Maximum for Master Mode FssPcik Minimum 12x FssPCLKkIN Maximum for Slave Mode The maximum frequency of SSPCLK is governed by the following equations both of which have to be satisfied e Fsspci Maximum lt 254 x 256 x Fsspcikour Minimum for Master Mode Maximum lt 254 x 256 x Minimum for Slave Mode 15 2 2 1 3 5 Programming the SSPCRO Control Register The SSPCRO register is used to e Program the Serial Clock Rate SCR e Select one of the three protocols e Select the data word size where applicable The SCR value in conjunction with the SSPCPSR Clock Prescale Divisor Value CPSDVSR is used to derive the PrimeCell SSP transmit and receive bit rate from the external SSPCLK The frame format is programmed through the FRF bits and the data word size through the DSS bits Bit phase and polarity applicable to Motorola SPI format only are programmed through the SPH and SPO bits SAMSUNG ELECTRONICS 15 8 ex S3FN429_UM_REV1 20 15 Serial Peripheral Interface SPI 15 2 2 1 3 6 Programming the SSPCR1 Control Register The SSPCR1 register is used to e Select ma
75. 1 duty Upside 67 duty setting Upside i 5 Upside 9995 duty 67 duty setting setting Figure 10 7 _ Wave Duty SWAP a Low Start PWMxUy and High Start PWMxDy SAMSUNG ELECTRONICS 10 8 x S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 2 3 3 Tri Angular Wave IMMODE 0 PWMSWAP 0 PWMPOLU 0 Low Start and PWMPOLD 0 Low Start Figure 10 8 illustrates the Tri Angular wave No SWAP Low Start PWMxUy Low Start PWMxDy oe ee ne i ak a ves ate IMC_ASCRR2 7 IMC_PCCRR IMC_ASCRR1 PONO ates IMC_PCCFR IMCPBCRR t Tuc bride Rue ok ROS IMC_PBCFR IMC_ASCFR2 IMC_ASCRRO IMC PACRR s oan E IMC_ASCFR1 IMC_PACFR IMC_ASCFRO PWMXxUO PWMXxU1 PWMxU2 PWMxDO PWMxD1 PWMxD2 Interrupt Can be used by trigger signal Figure 10 8 Tri Angular Wave No SWAP Low Start PWMxUy Low Start PWMxDy NOTE 1 The switch of upside is high active and the switch of down side is low active 2 For 100 95 duty of upside you should set the rising falling compare register For 0 95 duty of upside you should set the rising compare register to equal to TOPCMP value SAMSUNG ELECTRONICS 10 9 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 2 3 4 Tri Angular Wave IMMODE 0 PWMSWAP 1 PWMPOLU 0 Low Start and PWMP
76. 1 99999 SAMSUNG ELECTRONICS 4 37 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 2 1 18 ADC_OCR e Base Address 0 4004 0000 e Address Base Address 0x00BO Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 ADCOCC EXER es WIN WI IW WI W W W RSVD ma R reser 109 ADC Offset Calibration Constant Value ADCOCC 13 0 BW ADEOCCE field is signed value 0 0000 Negative values should be expressed using the 2 s complement SAMSUNG ELECTRONICS 4 38 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 2 1 19 ADC_CBRn e Base Address 0x4004_0000 e Address Base Address 0x0100 Reset Value 0x0000_0000 e Address Base Address 0x0104 Reset Value 0x0000_0000 e Address Base Address 0x0108 Reset Value 0x0000_0000 e Address Base Address 0x010C Reset Value 0x0000_0000 e Address Base Address 0x0110 Reset Value 0x0000_0000 e Address Base Address 0x0114 Reset Value 0x0000_0000 e Address Base Address 0x0118 Reset Value 0x0000_0000 e Address Base Address 0x011C Reset Value 0x0000_0000 e Address Base Address 0x0120 Reset Value 0x0000_0000 e Address Base Address 0x0124 Reset Value 0x0000_0000 Address Base Address 0x0128 Reset Value 0x0000_0000 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
77. 10 Inverter Motor Controller IMC Inverter Motor Controller IMC 10 1 Overview You can use the Inverter Motor Controller IMC for three phase inverter motor 10 1 1 Features The features of IMC are e 3 phase Pulse Width Modulation PWM signal outputs PWMxUO and PWMxDO PWMXxU1 and PWMxD1 PWMXxU2 PWMxD2 e Dead time insertion e Eight compare registers for IMC start trigger signal generation and interrupt e High Z output generation 10 1 2 Pin Description Table 10 1 describes the pin description of IMC Table 10 1 IMC Pin Description PWMU 2 0 PWM Up Side Output for Inverter Motor i PWMDI 2 0 PWM Down Side Output for Inverter Motor OF PWMOFF Input Pin for PWM Output Off a 3 SAMSUNG ELECTRONICS 10 1 x S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 2 Functional Description Functional description section includes Block diagram of IMC e Operations e Phase Signal Generation 10 2 1 Block Diagram Figure 10 1 illustrates the block diagram for IMC INTMASK ie INTPND gt INT FAULT IMC CR0 12 PWMOFFE IMC CR0 10 8 IMFILTER CRO 13 PWMOUTOFFEI Pwwxorli Filter mu IMC CRO 15 PWMoFFENBYCOMP CRO 7 6 ESELPWMOFF From comparator block IMC SR COMPEDGEDET CR0 0
78. 11 9 8 7 6 5 4 3 2 1 0 RSVD R Conversion Buffer Data of ADC DATA 11 0 Data will be from 0x000 to OxFFF After conversion starts you can watch converting data before the end of conversion SAMSUNG ELECTRONICS 4 39 ex S3FN429_UM_REV1 20 5 Clock and Power Manager Clock and Power Manager 5 1 Overview The Clock and Power Manager CM chapter describes the management for system clock and power according to the operation mode The System Clock tree consists of two clock sources they are External Main Clock you can select the frequency range from 1 to 12 MHz e IMCLK Internal Main Clock 40 MHz The Clock Control Logic generates the required clock signals including the HCLK FCLK for CPU The HCLK generates the required clock signals for the AHB bus peripherals and the PCLK for the APB bus peripherals and so on The Clock Manager has a Phase Locked Loop PLL for a System Clock By using the software the Clock Control Logic connects or disconnects the clock to each peripheral block which reduces the power consumption The Power Control Logic has several power management schemes to maintain an optimal power consumption for a given task The Power Management Block activates several modes SAMSUNG ELECTRONICS 5 1 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 1 1 Features The features section includes Clock Management Core Clock Sources PLL Reset Sources Power Management
79. 12 1 S3FN429_UM_REV1 20 12 Configuration 12 2 Functional Description The Functional Description section describes the general description and peripheral configuration of IOCONF 12 2 1 General Description The peripherals have their own dedicated pins multiplexed with General Purpose IO GPIO pin and other peripheral pins User should configure the corresponding pin for the function of the target peripheral Define the pin as one function pin among maximum four functions GPIO will be the first function of pin IOCONF block controls Enable Disable for each pins Pull Up Resistor and Open Drain Control Resistor 12 2 2 Peripheral Configuration Table 12 1 describes the I O function mode configuration Table 12 1 I O Function Mode Configuration WoGowo FunetionNumber Ff m e f Pin Number 100xy ore i Poo Exo oron 5 Pos ans exs Pos SAMSUNG ELECTRONICS 12 2 27 S3FN429_UM_REV1 20 12 I O Configuration io Groupd FunctionNumber f a e f Pin Number 100xy ore wb i s XINUSARTAKO SAMSUNG ELECTRONICS 12 3 27 S3FN429_UM_REV1 20 12 I O Configuration 12 3 Register Description 12 3 1 Register Map Summary e Base Address 0x4005 8000 IOCONF MLRO 0x0000 Mode low
80. 13 ex S3FN429_UM_REV1 20 6 Comparator 6 3 1 7 COMP_SR e Base Address 0 4004 2000 Address Base Address 0x0018 Reset Value 0x000F 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 COMPOUTSTATUS3 COMPOUTSTATUS2 COMPOUTSTATUS1 COMPOUTSTATUSO EDGEDETSTATUS3 EDGEDETSTATUS2 EDGEDETSTATUS1 EDGEDETSTATUSO COMPOUTSTATUS3 Comparator Output Real Time Status COMPOUTSTATUS1 9 put 1 Specifies Voltage of comparator P input gt COMPOUTSTATUSO Voltage of comparator N input Comparator Output Edge Detect Status at Edge EDGEDETSTATUSS Detection EDGEDETSTATUS2 0 Voltage of comparator N input gt Voltage of EDGEDETSTATUS 1 comparator P input EDGEDETSTATUSO 1 Voltage of comparator P input gt Voltage of comparator N input SAMSUNG ELECTRONICS 6 14 x S3FN429_UM_REV1 20 6 Comparator 6 3 1 8 COMP_IMSCR e Base Address 0 4004 2000 e Address Base Address 0x001C Reset Value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 Edge Detection Interrupt Mask 0 Specifies Edge Detection interrupt is masked Disables the interrupt 1 Specifies Edge Detection interrupt is not masked Enables the interrupt 2 ___ evaevere gt ___ s gt EDGEDET3 Edge Detection Interrupt Mask 0 Specifies Edge Detec
81. 13 x S3FN429_UM_REV1 20 11 Interrupt Controller INTC 11 3 1 8 NVIC_IPR3 Base Address 0 000 0000 e Address Base Address 0 40 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 PRI N15 RSVD PRI N14 RSVD PRI N13 RSVD PRI N12 RSVD RIR R RIR R R R RIJRI IR R R RIJRI R R R R R R R R WINIW W W W W W W W W W W W W W W W W W W W W PRI N15 31 30 The priority of the interrupt vector number 15 zaj RW The pony ofthe nterupt vector number 4 o wo rte RW Resena 0 E 0 SAMSUNG ELECTRONICS 11 14 en S3FN429_UM_REV1 20 11 Interrupt Controller INTC 11 3 1 9 NVIC_IPR4 e Base Address 0xE000_0000 Address Base Address 0xE410 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 PRI N19 RSVD PRI N18 RSVD PRI N17 RSVD PRI N16 RSVD N e RIR R RIR R R R RIJRI IR R R RIJRI R R R R R R R R WINIW W W W W W W W W W W W W W W W W W W W W Mme 8139 Rw The priority ofthe interrupt vector numero sv g RW Rese Pai Nre 12122 Rw priority ofthe nterupl vector numere o vo erie RW mew 9 9 al zaj
82. 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 ASV pray R Overrun Masked Interrupt State Provides masked interrupt status after masking of OVR interrupt End of Conversion Masked Interrupt State Provides masked interrupt status after masking of EOC interrupt NOTE Ona Read the ADC_MISR register gives the current masked status value of the corresponding interrupt A Write has no effect SAMSUNG ELECTRONICS 4 34 en S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 2 1 15 ADC_ICR e Base Address 0 4004 0000 e Address Base Address 0x0070 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 81 7 ASV pray R Reed OOOO Overrun Interrupt Clear 0 No effect 1 Clears the OVR interrupt End of Conversion Interrupt Clear 0 No effect 1 Clears the EOC interrupt NOTE On a Write of 1 the corresponding interrupt is cleared A Write of 0 makes no effect SAMSUNG ELECTRONICS 4 35 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 2 1 16 ADC_CRRn e Base Address 0x4004_0000 e Address Base Address 0x0080 Reset Value 0x0000_0000 e Address Base Address 0x0084 Reset Value 0x0000_0000 e Address Base Address 0x0088 Reset Value 0x0000_0000 e Address Base Address 0x008C Reset Value 0x0000_0000 e Address Base Address 0x0090 Reset Value 0x0000_0000 e Address Base Address 0x0094 Reset Value 0x000
83. 17 48 27 S3FN429_UM_REV1 20 18 Watchdog Timer Watchdog Timer 18 1 Overview Use Watchdog Timer to prevent the system from locking up For example you can stop the software program running in an infinite loop by setting interrupts If the software does not write to the Watchdog during the programmed time it can either generate an interrupt WDTOVF or an internal reset 18 1 1 Feature The Watchdog Timer has a programmable 16 bit down counter The software can decide what to do when the counter reaches 0 overflows fthe RSTEN bit is set in the OMR register then it generates an internal reset e fthe WDTOVF bit is set in the IMSCR register then it generates an interrupt on the Interrupt Controller The Input Frequency Clock FIN is a clock source EMCLK IMCLK PLLCLK from the clock manager It supplies the Watchdog counter through the WDTPDIV programmable divider It is possible to set a programmable pending window where you can restart the Watchdog counter only within this window 1 This protection is set with the RSTALW bit If this protection is not there then you can restart the Watchdog counter whenever it is required When it reaches the pending window the WDTPEND bit is set before the PENDING The WDTPDIV 2 0 divider divides the supplied clock FIN and provides to the down counter input WDTCLK To prevent corruption of the Watchdog control access key protects all write acces
84. 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 E Software Reset 0 No effect 1 Performs Flash Controller Software Reset operation You can initialize all registers except Smart Option Clock Enable Disable and internal OSC trimming registers SAMSUNG ELECTRONICS 9 29 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 3 1 4 IFC_CR e Base Address 0x4001_0000 e Address Base Address 0x000C Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 14 13 12 1 R R Lm rye ssi Tra va mv ern n Reewd Flash Program Erase Command Field 000 No effect 001 Selects Normal Program Command 010 Selects Page Erase Command 011 Selects Sector Erase Command 100 Selects Entire Erase Command 6 4 RW 101 Selects Smart Option Program Command 110 Selects Smart Option Erase Command 111 Prohibited Smart Option Erase operation clears protection and configuration Smart Option The smart option has the several options in one register If you change partial option you should program new value to change and prior value not to change at a time Operation 1 Start Bit This bit clears automatically at the end of command operation 0 No effect 1 Starts When you write 1 while executing the command normal START Rw Program page sector entire erase Smart Option program erase it does not have an effect But this bec
85. 19 15 19 16 SPI SSP Timing Characteristics enne nnne nnn nnne enn 19 16 19 17 ESD Characteristics reci rk eren tr ek inr P Rr cn dra 19 17 20 PACKAGE 20 1 OP 20 1 SAMSUNG ELECTRONICS ex Figure Number Figure 1 1 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure 3 1 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 Figure 4 7 Figure 4 8 Figure 4 9 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figure 5 6 Figure 5 7 Figure 5 8 Figure 5 9 Figure 5 10 Figure 5 11 Figure 5 12 Figure 5 13 Figure 5 14 Figure 5 15 Figure 5 16 Figure 5 17 Figure 5 18 Figure 5 19 Figure 5 20 Figure 5 21 Figure 5 22 List of Figures Title Page Number ERR 1 9 Pin erum Emm 2 2 Pin Circuit A P0 0 to 11 and P0 18 to 3 1 22 2 11 Circuit Type 1240 PO 17 eterne tnde 2 12 Pin Circuit C MODE1 and 1 2 12 Pin Circuit Type D nRESET uiae ceteri ect ere an ett des e eR edt tuae den a eet 2 13 SSFN429 Memory 3 1 Block T 4 2 ADC Operation Timing D
86. 19 3 SPI Interface Transmit Receive Timing SAMSUNG ELECTRONICS 19 16 ex S3FN429_UM_REV1 20 19 Electrical Data 19 17 ESD Characteristics Table 19 17 ESD Characteristics Symbo Condions Typ max Unit Electrostatic discharge SAMSUNG ELECTRONICS 19 17 ex S3FN429_UM_REV1 20 20 Package Specification Package Specification 20 1 Overview The Package Specification chapter describes the package information available in a 44 QFP 1010 package type Table 20 1 describes the package specification information Table 20 1 Package Specification Information Package Number 44 QFP 1010 Package Width x Package Length 10 0 x 10 0 mm SAMSUNG ELECTRONICS 20 1 ex S3FN429_UM_REV1 20 20 Package Specification Figure 20 1 illustrates the package outline 13 20 0 30 13 20 20 30 x e in 23 N o g E 0 80 0 20 Figure 20 1 44 1010 Package Dimension SAMSUNG ELECTRONICS 20 2 i
87. 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 SCTVHDAT saj zaj SCTVHDAT 15 0 Speed Capture Timer Hold Data 0x0000 Hold data register for speed capture timer value SAMSUNG ELECTRONICS 7 37 ex S3FN429_UM_REV1 20 8 General Purpose I O GPIO General Purpose I O GPIO 8 1 Overview General Purpose I O chapter describes the configuration of General Purpose I O GPIO such as input and output S3FN429 has 32 ports as the GPIO Each port is one of Port 0 group PO 31 0 All I O lines in the microcontroller are unified in GPIO controller This GPIO controller module controls all I O lines GPIO controller also provides interrupt signals to the interrupt controller You can configure each port by software to fulfill various configuration requirements of target system and design You should define the functionality of the port before starting an application program If you do not want to use the function for multiplexed pins you can configure these pins as simple I O ports 8 1 1 Features e Clock Supply Enable Disable Configuration of GPIO requires a clock supply Youcan disable the clock supply to optimize the power consumption Output Data Direction Enable Disable Status Monitoring Output Data Set Clear Data Status Monitoring Software Reset SWRST Function Setto default
88. 28 27 26 25 24123 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 OO o Clock Enable Disable 0 Disables GPIO Clock 1 Enables GPIO Clock GPIO_SRR does not affect CLKEN SAMSUNG ELECTRONICS 8 7 ex S3FN429_UM_REV1 20 8 General Purpose I O GPIO 8 3 1 3 GPIO_SRR e Base Address 0x4005 0000 e Address Base Address 0x0008 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 ert Software Reset W 0 Noeffect 1 Performs GPIO Software Reset and auto clears SAMSUNG ELECTRONICS 8 8 ex S3FN429_UM_REV1 20 8 General Purpose I O GPIO 8 3 1 4 GPIO_IMSCR e Base Address 0x4005 0000 e Address Base Address 0x000C Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 29 28 27 26 25 24 23 22 21 20 19 18 17 16 22 21 20 19 18 R R R R R IR R RI RI R I R R RIRIRIRIRIRIR R IRI IRIRIRIRIR I R I R I IRI IR RI R WIWIWIWIWIWIWIWIWIWIWIWIWIWIWIWIWIWIWIWIWIWIWIWIWIWIWIWIWIWIWIW Port y Interrupt Mask 0 This interrupt is masked Disables the interrupt Py y RW 4 This interrupt is not masked Enables the interrupt Interrupt occurs when a logic level change is detected on the corresponding pin NOTE On a Read GPIO_IMSCR register gives the current value of the mask on the relevant interrupt A Write of 1 to the particular bit sets the mask enabling the interrupt to be read A Write of 0 clears the corresponding mask SAMSUNG ELE
89. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 WwW W gt evcevers s e s e spen Edge Detection Interrupt Clear Gives the raw interrupt state prior to masking of EDGEDETS interrupt Edge Detection Interrupt Clear Gives the raw interrupt state prior to masking of EDGEDET2 interrupt RSVD EDGEDET3 Edge Detection Interrupt Clear Gives the raw interrupt state prior to masking of EDGEDETI1 interrupt Edge Detection Interrupt Clear Gives the raw interrupt state prior to masking of EDGEDETO interrupt EDGEDET 1 EDGEDETO NOTE A Write of 1 clears the corresponding interrupt A Write of 0 has no effect SAMSUNG ELECTRONICS 6 18 ex S3FN429_UM_REV1 20 7 Pulse Position Decoder Pulse Position Decoder 7 1 Overview The Pulse Position Decoder PPD chapter describes the PPD that you can use for measuring the position and speed 7 1 1 Features The features of PPD are e The three input signals of PPD are PHASEZ e The two 16 bit up down counters of PPD are Position Counter PCR Speed Counter SPCR e The two 16 bit capture timers of PPD are Position Capture Timer PCT Speed Capture Timer SCT e PPD has filter in the PHASEZ and edge selector for PHASEZ 7 1 2 Pin Description Table 7 1 describes the functions of each pin on the PPD
90. 5 1 1 1 Clock Management The features of Clock Management are External Oscillator 1 to 12 MHz EMCLK External Main Clock Programmable PLL with operational frequency from 12 to 40 MHz Programmable Clock Divider SDIV and PDIV for SYSCLK and PCLK EMCLK failure detection with an Internal Main Clock Clock Monitor function Clock Out Port COP 4 0 5 1 1 2 Core Clock Sources The features of Core Clock sources are EMCLK External Main Clock External 1 to 12 MHz Oscillator IMCLK Internal Main Clock Internal 40 MHz RC Oscillator PLLCLK From 12 to 40 MHz 5 1 1 3 PLL The features of PLL are Obtain an Input Clock from the EMCLK 1 to 12 MHz Configurable output frequency from 12 to 40 MHz Configurable counter for the PLL stabilization time SAMSUNG ELECTRONICS 5 2 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 1 1 4 Reset Sources The features of Reset Sources are NRST External Input Pin Reset nRESET EMCMRST External Main Clock Monitor Fail Reset e LVDRST LVD Reset also called as an LVR e WDTRST Watchdog Timer Reset e SWHRST Software Reset e PORST Power On Reset e SYSRST Reset by CPU Request 5 1 1 5 Power Management The features of Power Management are e NORMAL MODE CPU runs by one of the clock sources EMCLK or IMCLK except the PLLCLK e PLL MODE The CPU runs by the PLLCLK e IDLE MODE The CPU halts the operations of Stop Configure STCLK or PCLK by enabling or
91. 50 010 0 55 INTREFSEL2 18 16 RW 014 20 60 Vpp 100 0 65 Vpp 101 2 0 70 Vpp 110 2 0 75 Vpp 111 2 0 80 Vpp 1s R feme X Comparator 1 Edge Detection Filter Selection Bit 000 bypass 001 PCLK 1 010 PCLK 16 COMP1FILTER 14 12 RW 011 PCLK 64 100 PCLK 128 101 PCLK 256 110 PCLK 512 111 PCLK 1024 181 Comparator 1 Reference Level Selection Bit 000 0 45 001 0 50 010 0 55 INTREFSEL1 10 8 RW 014 20 60 Vpp 100 0 65 Vpp 101 0 70 110 0 75 111 2 0 80 Vpp mo 70018 S 9 Comparator 0 Edge Detection Filter Selection Bit 000 bypass 001 PCLK 1 010 PCLK 16 COMPOFILTER 6 4 RW 011 PCLK 64 100 PCLK 128 101 PCLK 256 110 PCLK 512 111 PCLK 1024 RSVD I R JReevd 0 Comparator 0 Reference Level Selection Bit INTREFSELO 2 0 Rw 000 0 45 Vpp 001 0 50 010 0 55 SAMSUNG ELECTRONICS 6 11 ex S3FN429_UM_REV1 20 6 Comparator 011 0 60 100 0 65 Vpp 101 0 70 Vpp 110 0 75 111 0 80 Vpp SAMSUNG ELECTRONICS 6 12 ex S3FN429_UM_REV1 20 6 Comparator 6 3 1 6 COMP_CR2 e Base Address 0 4004 2000 e Address Base Address 0x0014 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 o gt ED COMP1PPDEN CHKSRCSEL1 CHKSRCSELO comprmcen
92. 6 5 4 3 2 41 0 RIR R RIR RI R R IR R R R R R R R Positi Ti Val PCAPTV 15 0 osition Capture Timer Value 0x0000 This field contains the current value of position timer SAMSUNG ELECTRONICS 7 26 ex S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 3 1 14 PPD_PCTVR e Base Address 0x400C_0000 e Address Base Address 0x0034 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 RIR R RIR RI R R IR R R R R R R R WINIWIWN IWIW W W W W W W W W W W RSVD R 109 Position Capture Timer Value PCTV 15 0 RW This field contains the captured value of position capture 0x0000 timer SAMSUNG ELECTRONICS 7 27 ex S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 3 1 15 PPD_SCR e Base Address 0x400C_0000 e Address Base Address 0x0038 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 o N RIR R RIR RI R R IR R R R R R R R Reserved Speed Counter Value 0x0000 This field contains the current speed counter value SAMSUNG ELECTRONICS 7 28 ex S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 3 1 16 PPD_SCRR e Base Address 0x400C_0000 e Address Base Address 0x003C Reset Value 0x0000_0000 31 30 29 28 27 26 25 24123 22 21 20 19 18 17 16 15 14 13 12 11 10 o a gt
93. 8 describes the clock status on STOP and wake up Table 5 8 Clock Status on STOP and Wake Up DENNIS Normal or PLL Mode STOP EMCLK STOP STOP STOP FWAKE 0 SAMSUNG ELECTRONICS 5 21 Lp S3FN429_UM_REV1 20 5 Clock and Power Manager Figure 5 1 1 illustrates the interrupt and event diagram Peripheral 1 Enable IMSCR ON Interrupt 1 RISR NISR bit in Pending SEVONPEND Enable Peripheral 2 IMSCR N Interrupt 2 RISR NISR bit in Pending wakeup WFE SEVONPEND Peripheral n Enable Pending IMSCR N Interrupt n RISR J NISR 1 bit in CSR External SEVONPEND Interrupt Wakeup Enable IMSCR UN Interrupt x RISR Pending NISR 1 WFE bit in WFE SEVONPEND SEV inst RXEV event
94. A e SREFDAT zae RIR R R R R R R R R RSVD n 0109 Speed Counter Reference Data Value SREFDAT 15 0 RW This field determines the reference value for speed 0x0000 counter SAMSUNG ELECTRONICS 7 29 ex S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 3 1 17 PPD_SCTR e Base Address 0x400C_0000 e Address Base Address 0x0040 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 SCAPTV saj zaj SCAPTV 15 0 Speed Capture Timer Value 0 0000 This field contains the current speed capture timer value SAMSUNG ELECTRONICS 7 30 ex S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 3 1 18 PPD_SCTVR e Base Address 0x400C_0000 e Address Base Address 0x0044 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 RIR R RIR RI R R IR R R R R R R R WINIWIWN IWIW W W W W W W W W W W RSVD 109 Speed Capture Timer Value SCTV 15 0 RW This field contains the captured value of speed capture 0x0000 timer SAMSUNG ELECTRONICS 7 31 ex S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 3 1 19 PPD_PCHR e Base Address 0x400C_0000 e Address Base Address 0x0048 Reset Value 0x0000 0000 31 30 2
95. ADC is generated without calibration CALEN 1 Enables calibration bit 24 RW The conversion data of ADC is adjusted To use calibration you should initialize before enabling calibration For initialization you should obtain conversion data of 1 4 and 3 4 reference voltage That is used to predefine configuration ICRV or CRVS control bits avo aese _ Conversion Count Field NOTE Even in One Shot mode ADC will run multiple conversions if the CCNT is greater than 0000 b 0000 1 time conversion operation 0001 2 times conversion operation 0010 3 times conversion operation 0011 4 times conversion operation 11 8 RW 0100 5 times conversion operation 0101 6 times conversion operation 0110 7 times conversion operation 0111 8 times conversion operation 1000 9 times conversion operation 1001 10 times conversion operation 1010 11 times conversion operation Others Not used Conversion Mode Bit 0 Selects One Shot mode ADC converts as much inputs as specified by the ICNUMx 3 0 in the order specified in the ADC_CCSR and stops 1 Selects Continuous mode CMODE 7 RW ses ADC converts as much inputs as specified by the ICNUMx 3 0 in the order specified in the ADC_CCSR and repeats This bit is initialized to 0 In Continuous mode after a Stop command ADC finishes the on going conversion and this looks like an extra conversion is R Rese O ADC Start Trigger Signal
96. ADcrMe Apo aocrvo Reserved a i ADC Falling Match Interrupt Clear 0 No effect 1 Clears the ADCFMe interrupt ADC 2 Rising Match Interrupt Clear 0 No effect 1 Clears the ADCRM2 interrupt ADC 1 Falling Match Interrupt Clear 0 No effect 1 Clears the ADCFM1 interrupt ADC Compare Rising Match Interrupt Clear 0 No effect 1 Clears the ADCRM1 interrupt ADC Compared Falling Match Interrupt Clear 0 No effect 1 Clears the ADCFMO interrupt ADC Compare Rising Match Interrupt Clear 0 No effect 1 Clears the ADCRMO interrupt TOP Match Interrupt Clear 0 No effect 1 Clears the TOP interrupt ZERO Match Interrupt Clear 0 No effect 1 Clears the ZERO interrupt RSVD FAULT W FAULT Interrupt Clear SAMSUNG ELECTRONICS 10 49 27 S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 0 No effect 1 Clears the FAULT interrupt NOTE Write of 1 clears the corresponding interrupt A Write of 0 has no effect SAMSUNG ELECTRONICS 10 50 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 3 1 12 IMC_TCR Base Address 0 400 0000 e Address Base Address 0x002C Reset Value 0 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 TOPCMPDAT EX za zaja
97. COMP1PSEL 0 50VDD 0 80VDD COMP COMP1EN COMP SR COMPOUTSTATUS1 COMPi P gt comp1 Filter To gt gt COMP_SR EDGEDETSTATUSO 0 COMPOPPDEN Not use for PPD 9 01 To PPD PHASEA 9 10 PPD gt 11 To PPD PHASEZ 0 COMP IMSCR EDGEDET1 COMP CRO coMPiEDGESEL RISR a COMP MISR COMP1IMCEN output COMP1 N gt H CRO0 COMP1NSEL _ 1 COMPOFILTER COMPCLK 1 PWMUO PWMU1 PWMU2 COMP_CR2 CHKSRCSEL1 _ COMP CR1 INTREFSEL2 0 COMP2PSEL COMP CR0 COMP2EN SR COMPOUTSTATUS2 0 45VDD 0 50VDD 0 80VDD _ coMP2P gt 2 comp2 Filter To IMC B COMP_SR EDGEDETSTATUS1 COMP1PPDEN Not use for PPD 01 To PPD PHASEA _ 9 10 To PPD gt 11 To PPD PHASEZ 1 COMP_IMSCR EDGEDET2 _ COMP2EDGESEL COMP_RISR COMP_MISR COMP COMP2IMCEN OP amp output coMP2N 1 COMP2NSEL CR1 COMP2FILTER
98. Description The BaudRate generator provides a periodic clock for the receiver and the transmitter The BaudRate generator can select the internal or external clock sources The external clock source is asserted on the USARTCLK pin The internal clock sources are either PCLK or PCLK 8 clock sources See Receiver and Transmitter in Figure 17 1 NOTE The duration of the external clock source period should be longer than the period of PCLK The external clock source frequency USARTCLK should be less than 40 percent of the PCLK frequency SAMSUNG ELECTRONICS 17 4 ex S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 3 Asynchronous Mode When the USART is programmed to operate in asynchronous mode SYNC 0 in the Mode Register US_ MR then the selected clock is divided by 16 times the value CD written in US BRGR BaudRate Generator Register If the CD 15 4 field in the US BRGR is set to 0 then the BaudRate clock is disabled e BaudRate Selected Clock 16 x CD where the selected clock is PCLK 8 or USARTCLK 17 3 1 Synchronous Mode When the USART is programmed to operate in synchronous mode SYNC 1 in the Mode Register US MR and the selected clock is internal CLKS 1 0 in the Mode Register US MR then the BaudRate clock is the internal selected clock divided by the value written in US BRGR If the CD 15 4 field in the 05 BRGR is set to 0 then the BaudRate clock is disabled e B
99. EESRC5 12 8 EESRC4 4 0 External Event Source x External Event Source Selection Field Refer to Table 5 14 NOTE You should do any configuration in the register before the entry of STOP IDLE mode You should configure either of the corresponding edge or level to enable an event or interrupt SAMSUNG ELECTRONICS 5 68 x S3FN429_UM_REV1 20 5 Clock and Power Manager Table 5 14 The External Event Sources and Pin Assignment 41000 SPIO 0 22 N MISOO EXI17 2Master Mode P0 23 COMP0_P MOSI0 PWM1 Slave Mode P0 19 PHASEA USARTRXO EXI14 i P0 26 COMP2 N USARTRXO EXI18 SAMSUNG ELECTRONICS 5 69 27 S3FN429_UM_REV1 20 5 Clock and Power Manager R R R R R R R WIN WIW W W W External Event Interrupt Mask Set Clear Bit 0 Mask each interrupt Disables an interrupt 1 Unmask each interrupt Enables an interrupt 5 9 1 23 CM_EEIMSCR e Base Address 0 4002 0000 e Address Base Address 0x0088 Reset Value 0x0000 0000 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 SAMSUNG ELECTRONICS 5 70 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 1 24 CM_EERISR e Base Address 0 4002 0000 e Address Base Address 0x008C Reset Value 0x0000 0000 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 External Event Raw Interrupt Status Bit 0 Each interrupt does not occur Prior to unmasking 1 Each interrupt occurs Prior to unmasking NOTE On a Read
100. ELECTRONICS 10 42 ex 10 3 1 8 IMC_IMSCR Base Address 0 400 0000 e Address Base Address 0x001C Reset Value 0 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 N Qa lt lt S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC fofolofolololofololofolololololololola BE ADC Compare Falling Match Interrupt Mask ADCFM2 0 This interrupt is masked Disables the interrupt 1 This interrupt is not masked Enables the interrupt ADCRM2 ADCFM1 ADCRM1 ADCFMO ADCRMO ZERO RSVD FAULT gt avom __ e ADC Rising Match Interrupt Mask 0 This interrupt is masked Disables the interrupt 1 This interrupt is not masked Enables the interrupt ADC Compare Falling Match Interrupt Mask 0 This interrupt is masked Disables the interrupt 1 This interrupt is not masked Enables the interrupt ADC Compare Rising Match Interrupt Mask 0 This interrupt is masked Disables the interrupt 1 This interrupt is not masked Enables the interrupt ADC Compared Falling Match Interrupt Mask 0 This interrupt is masked Disables the interrupt 1 This interrupt is not masked Enables the interrupt 2 ADC Rising Match Interrupt Mask 0 This interrupt is masked Disables the interrupt 1 This interrupt is not masked Enables the int
101. EMCLK fails the SYSCLK does not have any problem Therefore the chip runs continuously except WDT block WDT block can work normally or not Because WDT clock source is independent of SYCLK Table 5 4 describes the clock monitor control bit Table 5 4 Clock Monitor Control Bit Clock Monitor Control Bit Clock monitor fail function enable disable EMCM Clock monitor fail reset function enable disable EMCMRST Clock fail detection flag EMCKFAIL Clock recovery flag EMCKFAIL END SAMSUNG ELECTRONICS 5 11 x S3FN429_UM_REV1 20 5 Clock and Power Manager 5 2 5 1 Clock Fail The Clock Monitor circuit samples the External Main Clock Oscillator using Internal Main Clock IMCLK If the sampled value is identical during the three consecutive times then the Clock Monitor circuit decides the external oscillator failure is detected After detecting the failure the operation updates the EMCMRST or EMCKFAIL status If SYSCLK is EMCLK or PLLCLK then the clock manager can reset when the Clock Monitor circuit detects the EMCLK failure After EMCMRST reset system clock becomes IMCLK and clock manager updates the reset status register System runs by IMCLK and the reset status register is updated by the hardware Figure 5 6 illustrates the external main oscillator fail and reset diagram EMCM Enabled Internal Oscillator Stabilization mm Clock fail EMCLK Reset by It changes to IMCLK EMCMFAIL am
102. IO configuration The clock out ports are as follows e COPO External Main Clock divided by 8 EMCLK 8 e Internal Main Clock divided by 8 IMCLK 8 2 PLL Clock divided by 8 PLLCLK 8 COP3 Core Clock divided by 8 CORECLK 8 e Peripheral Clock divided by 8 PCLK 8 SAMSUNG ELECTRONICS 5 13 x S3FN429_UM_REV1 20 5 Clock and Power Manager 5 3 Clock Change 5 3 1 Clock State Machine Figure 5 8 illustrates the clock control state machine diagram V bw N w Dien STOP Sleep S NS Wakeup except AnyReset Wakeup except N AnyReset N S W Deep Sleep N AnyReset Reset Release Wakeup Interrupt AnyReset except AnyReset SW Sleep d Ts Wakeup Interrupt IDLE Mode except AnyReset AnyReset Figure 5 8 Clock Control State Machine The SYSCLK defines the Operation Mode The Watchdog Timer Clock is optional Table 5 5 describes the operation mode definition Table 5 5 Operation Mode Definition IMCLK Alive HCLK FCLK STCLK PCLK EMCLK EMCLK Alive HCLK FCLK STCLK PCLK IMCLK PLLCLK Alive EMCLK before PLL enable FEHLER FCLK HCLK STCLK PCLK DIR 2 Alive FCLK EMCLK IMCLK STCLK PCLK Dead HCLK PLLCLK 2 Dead HCLK FCLK PCLK STCLK PLLCLK EMCLK IMCLK NOTE 1 clock sources are and IMCLK 2 The Core Cortex MO cannot take the CO
103. O to 3 Edge Type Selection Bit 30 29 00 Selects rising edge trigger for external event 22 21 01 Selects falling edge trigger for external event 14 13 10 Selects both Rising Falling edge trigger for external 6 5 event 11 Invalid value EESRC3 28 24 EESRC2 20 16 EESRC1 12 8 EESRCO 4 0 External Event Source x External Event Source Selection Field Refer to Table 5 14 NOTE You should do any configuration in the register before the entry of STOP IDLE mode You should configure either of the corresponding edge or level to enable an event or interrupt SAMSUNG ELECTRONICS 5 67 x S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 1 22 CM EECR1 e Base Address 0x4002 0000 e Address Base Address 0x007C Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 EESRC7 RIR R RIJR R IR R JRIR R RIR RI R R R R R R R R External Event Enable Disable Control Bit 0 Disables the target external event source 1 Enable the target external event source x means each number from 4 to 7 R R R R WIW W W Edge Type Selection Bit 30 29 00 Selects rising edge trigger for external event 22 21 01 Selects falling edge trigger for external event 14 13 10 Selects both Rising Falling edge trigger for external 6 5 event 11 2 Invalid value EESRC7 28 24 EESRC6 20 16
104. Output Level Status IDLESL 0 Idle state PWM output level is low Logic 0 1 Idle state PWM output level is high Logic 1 asvo Reeves SSC PWM Start Stop Status START 0 0 Stops PWM 1 Starts PWM SAMSUNG ELECTRONICS 14 21 x S3FN429_UM_REV1 20 14 Pulse Width Modulation 14 3 1 7 PWM_IMSCR e Base Address 0 4007 0000 0x4007_ 1000 Address Base Address 0x0018 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 e ene _ gt enm zm G PEND gt a Pulse Match Interrupt Mask PMATCH 0 Mask the interrupt disables the interrupt 1 Unmask the interrupt disables the interrupt Period End Interrupt Mask PEND 0 Mask the interrupt disables the interrupt 1 Unmask the interrupt disables the interrupt Period Start Interrupt Mask PSTART 0 Mask the interrupt disables the interrupt 1 Unmask the interrupt disables the interrupt PWM Stop Interrupt Mask PWMSTOP 0 Mask the interrupt disables the interrupt 1 Unmask the interrupt disables the interrupt PWM Start Interrupt Mask PWMSTART 0 Mask the interrupt disables the interrupt 1 Unmask the interrupt disables the interrupt NOTE Read PWM_IMSCR register gives current value of mask on the relevant interrupt A Write of 1 to a particular bit sets the mask and enables the interrupt to be read A Write of 0 clears the corres
105. Outputs the serial data stream and frame control signal through the slave SSPTXD pin The slave receives logic to perform e Serial to parallel conversion on the incoming SSPRXD data stream e Extracting and storing values into its Receive FIFO for subsequent reading through the APB interface 15 2 2 1 2 7 Interrupt Generation Logic Four individual maskable active high interrupts are generated by the PrimeCell SSP The individual interrupt requests could also be used with a system interrupt controller that provides masking for the outputs of each peripheral In this way a global interrupt controller service routine will be able to read the entire set of sources from one wide register in the system interrupt controller This is attractive where the time to read from the peripheral registers is significant compared to the CPU clock speed in a real time system This peripheral supports both the methods The transmit and receive dynamic data flow interrupts SSPTXINTR and SSPRXINTR are separated from the status interrupts so that data can be read or written in response to the FIFO trigger levels SAMSUNG ELECTRONICS 15 6 ex S3FN429_UM_REV1 20 15 Serial Peripheral Interface SPI 15 2 2 1 3 PrimeCell SSP Operation PrimeCell SSP Operation section includes e Interface Reset e Configuring the SSP e Enabling PrimeCell SSP Operation e Clock Ratio e Programming the SSPCRO Control Register 15 2 2 1 3 1 Interface Reset The PrimeCell
106. PH 5 2 5 1 2 eio 5 4 SAMSUNG ELECTRONICS ex 5 5 21 SY SCUK ender 5 5 Seu 5 7 5 2 3 EMCLEK du 5 7 2 Jj sears 5 8 suele E 5 11 5 2 6 qe PET 5 13 Sel Serie I 5 14 5 3 1 Clock State Machine te reddo a 5 14 5 3 2 5 ern cm EE 5 16 5 3 3 WDTGEK Source Change 5 16 5 4 Power Management cic cae erii eel veered 5 17 5 4 1 Operation Modes tiia sad Le 5 17 5 4 2 Low Power Modes and 5 18 5 5 External Events External Interrupts and Wake Up Event seen 5 24 5 5 1 Operating eto i eode EE A ie eee Ea 5 24 5 5 2 MOES rete rende cette a Ede p tete aba e eve Fland e 5 25 5 5 9 Stop MOOS iss EL 5 25 5 6 Reset Management Em 5 26 5 6 1 nRESET Pin Reset ae eee ei ed ee ese 5 27 5 6 2 Power On Reset PORST 5 27 5 6 3 LVD UE 5 27 5 6 4 External Main Clock Mon
107. PPD PHASEZ 3 1 PPD Pulse Position Decoder Comparator Block Diagram S3FN429_UM_REV1 20 6 Comparator 6 2 2 Comparator Input The function of comparator is to compare two input signals The input signals are e Reference for signal value to compare e Target signal Comparator supports internal or external reference Set COMPxPSEL bit to 1 in register to use an internal reference value Range is 0 45 Vppto 0 80 Vpp 6 2 3 Comparator Output e The output is in two states The two states are 0 Voltage of comparator input gt Voltage of comparator P input 1 Voltage of comparator P input gt Voltage of comparator input 6 2 4 IMC Output Off Control The output of comparator is used to cut off IMC output signal 6 2 5 Interrupt There is an edge detection interrupt EDGEDETx Use selected interrupt mode edge detection to generate an interrupt 6 2 5 1 Interruption Handling The procedure for interrupt handling is 1 Interrupt Service Routine ISR Entry and call C function 2 Read COMP IMSR and verify the source of interrupt 3 Clear the corresponding interrupt at peripheral level by writing in 4 Interrupt treatment 5 Exit ISR SAMSUNG ELECTRONICS 6 4 ex S3FN429_UM_REV1 20 6 Comparator 6 3 Register Description 6 3 1 Register Map Summary e Base Address 0 4004 2000 ___________ Reset value S
108. Parameter Symbol min Typ Unit Input common mode Vos GND VDD 0 1 V voltage range NOTE The parameters are characterized and not tested SAMSUNG ELECTRONICS 19 13 ex S3FN429_UM_REV1 20 19 Electrical Data 19 14 OP AMP Electrical Characteristics Table 19 14 describes the electrical characteristic parameters of an OP AMP Table 19 14 OP AMP Electrical Characteristics Ta 40 to 105 95 VppcorE 2 5to 5 5 V AVpp 2 5 0 5 5 V Symbol Gonditions Wi Tw Unit 0 040AVp Gain 2 500 Do gt DO 4 DO 4 DO gt DO gt DO DO DO DO DO DO 0 360AVp Do 0 0 0 0 0 0 0 0 200AVpp Gain 5 000 0 020AVp Input voltage range Gain 12 00 0 010AVp Vi 0 075AVpp Gain 15 00 0 010AVp 0 060AVpp Gain 2 5 to 4 5 Gain 5 to 6 667 6 Gain 8 10 12 and 15 SO UE 4 12 1 These characteristic data are only for IP itself 2 Sr Slew Rate parameter is characterized not tested SAMSUNG ELECTRONICS 19 14 ex S3FN429_UM_REV1 20 19 Electrical Data 19 15 Flash Memory Characteristics Table 19 15 describes the flash memory characteristic parameters Table 19 15 Flash Memory Characteristics Ta 40 to 105 C VppcorE AVpp 2 5 to 5 5 V Parameter Symbol Conditions Mi Max uni 0
109. SSP is reset by the global reset signal PRESETn and block specific reset signal nSSPRST external reset controller should use PRESETn to assert nSSPRST asynchronously and negate it synchronously to SSPCLK PRESETn should be asserted LOW for a period long enough to reset the slowest block in the on chip system and then taken HIGH again The PrimeCell SSP requires PRESETn to be asserted LOW for at least one period of PCLK 15 2 2 1 3 2 Configuring the SSP Following reset the PrimeCell SSP logic is disabled and must be configured when in this state Control registers SSPCRO and SSPCR1 need to be programmed to configure the peripheral as a master or a slave operating under Motorola SPI The bit rate derived from the external SSPCLK requires the programming of the clock pre scale register SSPCPSR 15 2 2 1 3 3 Enable PrimeCell SSP Operation The Transmit FIFO can either be primed by writing up to eight 16 bit values when the PrimeCell SSP is disabled or allow the transmit FIFO service request to interrupt the CPU Once enabled the transmission or reception of data begins on the transmit SSPTXD and receive SSPRXD pins SAMSUNG ELECTRONICS 15 7 x S3FN429_UM_REV1 20 15 Serial Peripheral Interface SPI 15 2 2 1 3 4 Clock Ratios The clock ratio is defined as the ratio of the frequencies of PCLK to SSPCLK The frequency of SSPCLK must be less than or equal to that of PCLK This ensures that control signals from the SSPCLK domain to
110. Selection Bits This field determines the trigger signal for ADC TRIG 000 Selects Software START bit in ADC CR 2 0 RW 001 Selects ADTRG Rising 010 Selects ADTRG Falling 011 Selects ADTRG Rising or Falling Both 100 Selects TCx Timer Counter Match SAMSUNG ELECTRONICS 4 25 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 101 Selects IMCO ADC Trigger Value Other Reserved ADC conversion by one or several timer period match can be started SAMSUNG ELECTRONICS 4 26 S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 2 1 8 5 0 Base Address 0 4004 0000 Address Base Address 0x0040 Reset Value 0 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 WwiW INI IW WIWI IW W W W W W W W W W W W W W W W W W W W W W W W W W Analog Input Channel Number Selection Field 0000 AINO an input channel for OP AMP ICNUM7 31 28 0001 AIN1 ICNUM6 27 24 0010 AIN2 ICNUM5 23 20 0011 AIN3 ICNUM4 19 16 m MINE ICNUM3 15 12 TD ANE ICNUM2 11 8 0111 AIN7 ICNUM1 7 4 1000 AIN8 ICNUMO 3 0 1001 AIN9 1010 AIN10 Others Invalid SAMSUNG ELECTRONICS 4 27 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 2 1 9 ADC_CCSR1 e Base Address 0 4004 0000 e Address Base Address 0
111. Signal by ADCCMPF2 Match This bit determines whether ADCMPF2 match of IMCNT is used for ADC trigger signal or not 0 Does not select 1 Selects ADC Start Trigger Signal by ADCCMPR2 Match This bit determines whether ADCMPR2 match of IMCNT is used for ADC trigger signal or not 0 Does not select 1 Selects ADC Start Trigger Signal by ADCCMPF1 Match This bit determines whether ADCMPF1 match of IMCNT is used for ADC trigger signal or not 0 Does not select 1 Selects ex 5 5 e ADCMPF2SEL ADCMPR2SEL D 20 D 20 D 20 zi ADCMPF1SEL ADCMPR1SEL ADCMPFOSEL 1 Selects ADCMPROSEL 2 206 Trigger Signal ADCCMPRO Match This bit determines whether ADCCMPRO match of IMCNT SAMSUNG ELECTRONICS 10 59 ADC Start Trigger Signal by ADCCMPR1 Match This bit determines whether ADCCMPR1 match of IMCNT is used for ADC trigger signal or not 0 Does not select 1 Selects ADC Start Trigger Signal by ADCCMPFO Match This bit determines whether ADCCMPFO match of IMCNT is used for ADC trigger signal or not 0 Does not select S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC is used for ADC trigger signal or not 0 Does not select 1 Selects ADC Start Trigger Signal by Counter Zero Match This bit determines whether 0 mat
112. Table 5 12 SYSCLK Divider Value essent Table 5 13 PMS Value Table 5 14 External Event Sources and Pin Table6 1 Description cidem inerenti esa te Table 7 1 PPD Pin Description 2 Table 8 1 GPIO Pin Description sse Table 9 1 Flash Configuration Table 9 2 Base Address of Each SAMSUNG ELECTRONICS List of Tables Page Number Table 9 3 Table 9 4 Table 9 5 Table 9 6 Table 9 7 Table 10 1 Table 11 1 Table 11 2 Table 12 1 Table 13 1 Table 13 2 Table 14 1 Table 14 2 Table 14 3 Table 15 1 Table 16 1 Table 16 2 Table 16 3 Table 17 1 Table 17 2 Table 17 3 Table 17 4 Table 19 1 Table 19 2 Table 19 3 Table 19 4 Table 19 5 Table 19 6 Table 19 7 Table 19 8 Table 19 9 Table 19 10 Table 19 11 Table 19 12 Table 19 13 Table 19 14 Table 19 15 Base Address of Each 9 5 Configuration Smart Option Address and Control 9 6 Protection Smart Option Address and Control Bits sss 9 8 Description of Interrupt Sources enne en nennen 9 14 Pins Used to Read Write Erase the Flash ROM in Tool Program 9 15 Lies deem 10 1 GCore Intert pt
113. The transmit data line SSPTXD is arbitrarily forced LOW e When the PrimeCell SSP is configured as a master the SSPCLKOUT is enabled e When the PrimeCell SSP is configured as a slave the SSPCLKOUT is disabled If the PrimeCell SSP is enabled and there is valid data within the Transmit FIFO the start of transmission is signified by the SSPFSSOUT master signal being driven LOW The master SSPTXD output pin is enabled After a further one half SSPCLKOUT period both master and slave data are enabled onto their respective transmission lines At the same time the SSPCLK is enabled with a falling edge transition Data is then captured on the rising edges and propagated on the falling edges of the SSPCLKOUT signal After all bits have been transferred in the case of a single word transmission the SSPFSSOUT line is returned to its idle HIGH state one SSPCLKOUT period after the last bit has been captured For continuous back to back transfers the SSPFSSOUT pin is held LOW between successive data words and termination is the same as that of the single word transfer SAMSUNG ELECTRONICS 15 14 ex S3FN429_UM_REV1 20 15 Serial Peripheral Interface SPI 15 2 2 1 3 13 Examples of Master and Slave Configurations PrimeCell SSP 1022 peripheral can be connected to other synchronous serial peripherals when it is configured as a master or a slave NOTE The SSP PL022 does not support dynamic switching between master and slave in a system Each in
114. Upside Upside 100 duty 33 duty setting Setting Upside 196 duty Upside 33 duty setting setting Upside 99 duty T Figure 10 5 Tri Angular Wave Duty No SWAP a Low Start PWMxUy and High Start PWMxDy SAMSUNG ELECTRONICS 10 6 27 S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 2 3 2 Tri Angular Wave IMMODE 0 PWMSWAP 1 PWMPOLU 0 Low Start and PWMPOLD 1 High Start Figure 10 6 illustrates the Tri Angular wave SWAP a Low Start PWMxUy and High Start PWMxDy ct on n n n n t n n M ASCRR2 coco os on IMC PCCRR m IMC_ASCRR1 IMC_ASCRRO D tos E n n nn Denm n ee LN PAORA IMC_PACFR IMC_ASCFRO PWMXxUO PWMxU1 PWMxU2 PWMxDO PWMxD1 PWMxD2 Interrupt Can be used by ADC trigger signal Figure 10 6 Tri Angular Wave SWAP Low Start PWMxUy and High Start PWMxDy NOTE 1 Both the switches of upside and down side are high active 2 For 0 duty of upside you should set the rising falling compare register to 0 For 100 95 duty of upside you should set the rising compare register to equal to TOPCMP value SAMSUNG ELECTRONICS 10 7 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC Figure 10 7 illustrates the signal of PWM Assumption Duration of dead time is 2 percent duty Upside 67 duty setting z setting Upside
115. Value Hold Data 0 0000 Hold data register for position capture timer value SAMSUNG ELECTRONICS 7 34 ex S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 3 1 22 PPD_SCHR e Base Address 0x400C_0000 e Address Base Address 0x0054 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24123 22 21 20 19 18 17 16 15 14 13 12 11 10 a gt A e SCHDAT zae RIR R R R R R R R R RSVD R reser 109 Speed Counter Hold Data SCHDAT 15 0 RW This field contains the speed counter value copies it by 0x0000 holding the event trigger SAMSUNG ELECTRONICS 7 35 ex S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 3 1 23 PPD_SCTHR e Base Address 0x400C_0000 e Address Base Address 0x0058 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24123 22 21 20 19 18 17 16 15 14 13 12 11 10 o a gt A e SCTHDAT zae RIR R R R R R R R R RSVD n Speed Capture Timer Hold Data SCTHDAT 15 0 RW This field contains the speed capture timer value copies it 0x0000 by holding the event trigger SAMSUNG ELECTRONICS 7 36 ex S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 3 1 24 PPD_SCTVHR e Base Address 0x400C_0000 e Address Base Address 0x005C Reset Value 0x0000_0000 31 30 29 28 27
116. WDTCLK d a EXER R R gt mewo R Remd SYSCLK Selection Select one among different clock for SYSCLK 00 EMCLK 01 IMCLK SYSCLK 1 0 RW 10 PLLCLK 11 Prohibits NOTE 1 If you modify the SYSCLK it changes your system clock Be cautious while changing SYSCLK If you try to SAMSUNG ELECTRONICS 5 48 S3FN429_UM_REV1 20 5 Clock and Power Manager write 11 b to SYSCLK then the SYSCLK does not change and the CMDERR bit is 1 2 When the clock change completes the STABLE bit in CM_SR register becomes 1 3 The SYSCLK 0 reset value depends on the POCCS 0 in smart option configuration status register refer to the Program Flash chapter SAMSUNG ELECTRONICS 5 49 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 1 10 CM_IMSCR e Base Address 0 4002 0000 e Address Base Address 0x0030 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 4 n R R Ww Ww gt wow 2 ENCKFAILEND i resen 16 Tm n EE PLL stable interrupt SYSCLK clock switching stable interrupt R Reserved IMCLK Internal main clock stable interrupt External main clock stable interrupt EMCLK RW 0 Mask the stable interrupt Disables an interrupt 1 Unmask the stable interrupt Enables an interrupt Interrupt
117. allowed This bit does not disable the bit WDTPEND in the RSTALW RW interrupt register 0 Restart allowed every time 1 Restart allowed only within pending window 1 SAMSUNG ELECTRONICS 18 15 ex S3FN429_UM_REV1 20 18 Watchdog Timer 18 3 1 11 WDT_CTR e Base Address 0 4003 0000 e Address Base Address 0x0028 Reset Value 0x0000_FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 SAMSUNG ELECTRONICS 18 16 ex S3FN429_UM_REV1 20 19 Electrical Data Electrical Data 19 1 Overview The Electrical Data chapter describes all the electrical parameters for SSFN429 19 2 Absolute Maximum Ratings Every electrical device will have a rating on its electrical data at which the device will safely operate The maximum stress that you can apply on the device in terms of voltage and current above which the device will not operate as desired is called the Absolute Maximum Rating Samsung does not define the functional operations of the device at the absolute maximum rating conditions The document does not explain the functional operations of the device at these conditions Exposing the device to operate at maximum rating conditions for extended periods will affect the reliability of the device Table 19 1 describes the Absolute Maximum Ratings Table 19 1 Absolute Maximum Ratings Conditions
118. bit address is also 00b e AR ADDR 81 0 ADDRESS amp OxFFFFFFFC 9 2 1 2 2 Sector Erase When erasing a sector you should set lower 13 bits of address to 0 because the size of a sector is 8 KB You can select a value from 0 to 3 as the SECTOR ORDER from 4 sectors e FC AR ADDR 81 0 SECTOR ORDER lt lt 13 Sector 0 0 0000 0000 to 0x0000 ADDR S1 0 0x00000000 0 b lt lt 13 Sector 12 0 0000 2000 to 0x0000 ADDR S31 0 0x00002000 1 b lt lt 13 Sector 2 0 0000 4000 to 0x0000 5FFF ADDR 31 0 0x00004000 2 b lt lt 13 Sector 32 0 0000 6000 to 0x0000 7FFF ADDR 31 0 0x00006000 lt lt 13 Table 9 2 describes the base address of each sector Table 9 2 Base Address of Each Sector Sector Number Base Address SAMSUNG ELECTRONICS 9 4 en S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 2 1 2 3 Page Erase When erasing a page you should set lower 8 bits of address to 0 because the size of a page is 256 B You can select a value from 0 to 127 as the PAGE ORDER from 128 pages Table 9 3 describes the base address of each page Table 9 3 Base Address of Each Page o0 t 90010 ox 5 SAMSUNG ELECTRONICS 9 5 S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 2 2 Smart Option There are two kinds of Smart Options One is Protection Smart Option Another is Configuration Smart Option The flash
119. bit to 0 that disables all incoming clocks Then digital consumption is reduced close to 0 SAMSUNG ELECTRONICS 4 13 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 1 11 Operation Sequence Figure 4 9 illustrates ADC flowchart Configuration for ADC Clock Configuration Start Trigger Source Selection Conversion Channel Selection Y ADCEN 1 Enable ADC ADC Engine Stabled TBD us Ready Status ud Not BUSY Y ADC Conversion Operation 1us ADC CRRx Conversion Data Stored12 bit Data NOTE User should configure ADC start conversion by only one trigger Signal among ADTRG input signal START bit or IMC ADC trigger signal Figure 4 9 ADC Flowchart SAMSUNG ELECTRONICS 4 14 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 1 11 1 Software Sequence for Conversion The basic sequences of operations after reset for using ADC peripheral are e Enable ADC clock CLKEN in ADC_CEDR e Enable ADC engine for ADC operation e Configure ADC clock in the ADC_CDR Program CDIV fields to have analog frequency clock less than 5 MHz e Configure conversion channel ADC_CCSRx e Select the conversion start trigger source TRIG in ADC_MR e Check BUSY bit in ADC_SR If flag is 0 then ADC is ready to start conversion e Start conversion by writing START b
120. e Control signal for IMC output or input signal for PPD General Purpose IO GPIO The General Purpose IO GPIO contains e Input or Output configuration e Output open drain push pull configuration e interrupt Low Power Modes The Two Low Power Mode supports e IDLE Only CPU clock stops e STOP All clocks stop e Fast wake up with internal main oscillator from stop mode to normal mode e Programmable external event interrupt sources for wake up Power On Reset POR The Power On Reset POR contains e Built in circuit SAMSUNG ELECTRONICS 1 6 1 Product Overview S3FN429_UM_REV1 20 Low Voltage Detection LVD The Low Voltage Detection LVD contains e LVD for reset with configurable voltage levels e LVD for interrupt with configurable voltage levels e LVDreset interrupt enable disable can be controllable Phase Locked Loop PLL The Phase Locked Loop PLL contains e Input clock source EMCLK e Input frequency 1 to 12 MHz e Output frequency 12 to 40 MHz Operating Voltage Range The Operating Voltage Range contains 2 5 0 5 5V Operating Frequency Range The Operating Frequency Range contains e Up to 40 MHz EMCLK 1 to 12 MHz e I MCLK 40 MHz e PLL clock 12 to 40 MHz Operating Temperature Range The Operating Temperature Range contains e 40 C to 105 C SAMSUNG ELECTRONICS 1 7 1 Product Overview S3FN429_UM_REV1 20 Package The Package contains e Availa
121. equal 20 MHz 1 Selects high speed flash mode Use this when the system clock frequency is greater than 20 MHz RSVD al A gt Boot Area Configuration Enable Disable Control Bit You can enable or disable boot area Enabled boot area is protected You can not erase it by entire erase operation To erase this area you will have to perform Sector Erase or 32 times page erase operation 0 Disables boot sector area You can erase entire area by performing entire erase in user mode 1 Enables boot sector area 8 KB from 0x0000_0000 Flash area except sector 0 You can erase this using entire erase in user mode SAMSUNG ELECTRONICS 9 32 x S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 3 1 6 IFC_IMSCR e Base Address 0x4001_0000 e Address Base Address 0x0014 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 41 10 9 8 7 6 5 R R R mw R ERRn ERR Interrupt Mask Control Bit ERR 10 Error2 Write or erase to protected memory region 0 Interrupt is masked Disables an Interrupt 1 Interrupt is not masked Enables an Interrupt ERRn ERR Interrupt Mask Control Bit ErrorO Tries to execute other operation program ERRO 8 BW erase during normal user program command operation 0 Interrupt is masked Disables an Interrupt 1 Interrupt is not masked Enables an Interrupt wo C
122. except lOFour p 8 Output maximum operating frequency PO 18 12 20 MHz SAMSUNG ELECTRONICS 19 4 ex S3FN429_UM_REV1 20 19 Electrical Data 19 6 Reset Input Characteristics Table 19 5 describes the reset input characteristics for the semiconducting device Table 19 5 Reset Input Characteristics 40 to 105 C VppcoreE Vppio 2 5to 5 5 V __ cantons We V Viv 0V 100 250 400 nRESET schmitt trigger NOTE The noise filter for reset input signal has the distribution like as from 0 8 us to 2 us If the reset input signal width is smaller than minimum value 0 8 us it is always recognized as an invalid signal non reset If the reset input signal width is greater than maximum value 2 us it is always recognized as a valid signal reset Figure 19 1 illustrates the input timing diagram for the nRESET pin nRESET Figure 19 1 Input Timing for nRESET SAMSUNG ELECTRONICS 19 5 iD S3FN429 UM REV1 20 19 Electrical Data 19 7 External Interrupt Input Characteristics Table 19 6 describes the external interrupt input characteristics Table 19 6 External interrupt Input Characteristics 40 to 105 e Vpp Vppio 2 5to 5 5 V CORE QUNM Interrupt input high width twm 50 200 300 400 memupinputiowwith
123. from IRQO to IRQ3 Writing 1 disables the associated interrupt Writing 0 has no effect Th ist ds back with th t enable state CLRENA 31 0 RW register reads back wi e current e 00000 0000 Bit 0 for IRQO Bit 2 for IRQ1 Bit x for IRQx SAMSUNG ELECTRONICS 11 8 ex S3FN429_UM_REV1 20 11 Interrupt Controller INTC 11 3 1 3 NVIC_ISPR e Base Address 0xE000_0000 Address Base Address OxE200 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 a z n WwiWwW IW W WIW IW W W W W W W W W W W W W W W W W W W W W W W W W W Writing 1 to a bit insert the associated interrupt under the software control to a pending state Each bit represents an interrupt pin number from IRQO to IRQ31 Writing 0 to a bit has no effect on the associated interrupt The register reads back from the pending state SETPEND 31 0 RW 0x0000 0000 Bit 0 for IRQO Bit 2 for IRQ1 Bit x for IRQx SAMSUNG ELECTRONICS 11 9 ex S3FN429_UM_REV1 20 11 Interrupt Controller INTC 11 3 1 4 NVIC_ICPR e Base Address 0xE000_0000 e Address Base Address OxE280 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 a z Lu tc tc
124. g Clear pending interrupt You can clear when you write 1 to EEO bit in CM register EEO bit in EEMISR and CM EERISR register should be 0 clear 20 6 000 ISR Interrupt handler for EEO EEIA vector a CM EEMISR EEO and EERISR EEO should 1 set status CM EEICR 1 Clear interrupt pending bit g UserDefinedOperation Handling code for EEO interrupt IOCONF MLRO 3 FSEL 11 b EXI2 defined as third function of pinl2 b CM EECRO 1 b lt lt 7 1 lt lt 5 000010 b lt lt 0 Enable Edge Type Source NVIC ISERO 1 b lt lt 16 NVIC INT16 CM EEIMSCR gt EEO 1 b lt lt 0 SAMSUNG ELECTRONICS 5 24 x S3FN429_UM_REV1 20 5 Clock and Power Manager 5 5 2 Idle Modes IDLE mode halts the core clock So instruction in user code is not executed any more But the peripherals such like a timer can either operate or stops by PCLK status in CM_SR register To wake up from IDLE mode can be done by internal interrupts such like a timer interrupt or external event interrupts 5 5 3 Stop Modes In case of STOP mode all clocks for device logic halt Only 26 external event interrupts can wake up device from STOP mode Figure 5 13 is the simple diagram for external interrupt It shows information about registers and corresponding vector to configure and control external int
125. information provided is for reference purpose only Samsung assumes no responsibility for possible errors or omissions or for any consequences resulting from the use of the information contained herein This publication on its own does not convey any license either express or implied relating to any Samsung and or third party products under the intellectual property rights of Samsung and or any third parties Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages Customers are responsible for their own products and applications Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by the customer s technical experts Samsung products are not designed intended or authorized for use in applications intended to support or sustain life or for any other application in which the failure of the Samsung product could reasonably be expected to create a situation where personal injury or death may occur Customers acknowledge and agree that they are solely responsible to meet all other legal and regulatory requirements regarding their applications usin
126. interrupt clears A Write of 0 has no effect SAMSUNG ELECTRONICS 8 12 ex S3FN429_UM_REV1 20 8 General Purpose I O GPIO 8 3 1 8 GPIO_OER e Base Address 0x4005 0000 e Address Base Address 0x001C Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 29 28 27 26 25 24 23 22 21 20 19 18 17 16 22 21 20 19 18 17 16 15 14 13 12 11 10 14 13 12 1 Bonam ES Port y Output Enable Bit 0 No effect P W 1 Enables the GPIO output data direction on the corresponding pin SAMSUNG ELECTRONICS 8 13 27 S3FN429_UM_REV1 20 8 General Purpose I O GPIO 8 3 1 9 GPIO_ODR e Base Address 0x4005 0000 Address Base Address 0x0020 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 29 28 27 26 25 24 23 22 21 20 19 18 17 16 22 21 20 19 18 17 16 15 14 13 12 11 10 14 13 12 1 Bee eee ee ee a Port y Output Disable Bit Input Enable 0 No effect 1 Disables the GPIO output data direction on the Py A 2 en In other words GPIO_ODR enables GPIO input on the corresponding pin SAMSUNG ELECTRONICS 8 14 ex S3FN429_UM_REV1 20 8 General Purpose I O GPIO 8 3 1 10 GPIO_OSR e Base Address 0x4005 0000 e Address Base Address 0x0024 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 Port y Data Direction Input or Output Status Py y 0 The corresponding GPIO is input on this line 1 The
127. is kept for the debug purpose ony Rem Clock Enable Disable Control Bit CLKEN RW 0 Disables the USART Clock 1 Enables the USART Clock SAMSUNG ELECTRONICS 17 24 x S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 8 1 3 US_SRR e Base Address 0 4008 0000 e Address Base Address 0x0008 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 Software Reset 0 No effect 1 USART software reset SAMSUNG ELECTRONICS 17 25 ex S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 8 1 4 US_CR e Base Address 0 4008 0000 e Address Base Address 0x000C Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 81 7 WIW W smo s s sm 30 13 Start Time out 0 No effect 1 Starts waiting for a character before clocking the time out Send Address 0 No effect ENDA 12 W 2 1 In Multi drop mode only the next character written to the US_THR register is sent with the address bit set STTTO 11 counter value Stop Break 0 No effect STPBRK 10 W 1 If a break is being transmitted then it stops after a minimum of one character length and a high level is transmitted during 12 bit periods Start Break 0 No effect STTBRK 1 If break is not being transmitted then the
128. is a counter clock longer than the normal Period PWMEX bit in TC_SR register determines which Period is Extension Period Since PWMEX bit is 6 bit long the PWM output has approximately up to 22 bit resolution though the counter is 16 bit long Table 16 2 describes the PWM extension bits Table 16 2 PWM Extension Bits PWMEXO PWMEX PWMEXS 4 12 20 28 36 44 52 60 PWMEX4 2 6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 PWMEXS 55 57 59 61 63 Figure 16 8 illustrates the PWM output signals according to PWMEX bits N Normal Period E Extension Period PERIOD 64 PULSE 2 PWMEXO 1 32nd 64 periods PWMEX1 1 PWMEXO0 1 PWMEX1 1 Figure 16 8 PWM Extension Waveform SAMSUNG ELECTRONICS 16 11 ex S3FN429_UM_REV1 20 16 Timer Counter The equation to calculate the duty of PWM signal is PULSE E T ee PERIOD x PERIOD x 64 Duty PULSE x 64 E PULSE 1 x where E is number of Extension Periods in every 64 periods For example the PWM output has normally 50 percent duty when PERIOD is 100 and PULSE is 50 If PWMEXO is only set in this case then the pulse cycle of the 32 period in 64 periods has 51 counter clocks Therefore the PWM output has 50 015625 percent duty because 1 64 is 0 015625 If PW
129. non calibrated results for these input voltages are obtained by converting these channels with conversion commands when CALEN bit is 0 The transfer equations when sampling these reference voltages are DAT_CAL 3 4VREF ADC_GCC x DAT_NCAL 3 4VREF ADC_OCC 2 DAT_CAL 1 4VREF ADC_GCC x DAT_NCAL 1 4VREF ADC_OCC 2 Thus ADC_GCC DAT_CAL 3 4VREF DAT_CAL 1 4VREF DAT_NCAL 3 4VREF DAT_NCAL 1 4VREF ADC_OCC DAT_CAL 3 4VREF ADC_GCC x DAT_NCAL 3 4VREF 2 Or ADC_OCC DAT_CAL 1 4VREF ADC_GCC x DAT_NCAL 1 4VREF 2 After calculating above equation the ADC_GCC and ADC_OCC values are written to ADC_GCCR and ADC OCCR register respectively When you set CALEN bit the ADC automatically calibrates the results using the ADCGCC and ADCOCC values stored in ADC calibration registers To configure the calibration hardware the steps are e Determine the values of the gain and offset calibration constants e Write these constants to the calibration registers 4 1 10 3 Power Management To minimize power consumption ADC peripheral contains power management features Power can be saved on two sides Analog and Digital e Analog Power Saving To reduce analog power consumption CPU disables ADC module ADCDIS bit in SR register should be 1 by writing 1 to ADCDIS bit in control register that sets analog cell to standby mode e Digital Power Saving To reduce digital power consumption CPU disables ADC clock write CLKEN
130. out Overflow Mode 0 No effect 1 Enables Overflow mode The counter value increases until it overflows Repeat Mode 0 No effect 1 Enables Repeat mode PWM Enable 0 No effect 1 Enables the signal output Interval Mode 0 No effect 1 Enables Interval mode to toggle PWM output at the end of period Keep Stop Level 0 No effect 1 Enables Keep State Mode Output Start Level 0 No effect 1 The output signal level will be HIGH when starting IDLE State Level 0 No effect 1 The output signal level will be HIGH in Idle state Reserved Stop Count Clear 0 No effect 1 Enables Stop Clear mode Stop Count Hold 0 No effect 1 Enables Stop Hold mode Update Parameters 0 No effect 1 Updates TC_CCDR TC_CCSMR TC_CPRDR and TC_CPULR registers immediately to new values specified by TC_CDR TC_CSMR TC PRDR and TC_PULR respectively Start the TC 0 No effect 1 Starts the counter SAMSUNG ELECTRONICS 16 24 S3FN429_UM_REV1 20 16 Timer Counter 16 3 1 6 TC_CCR e Base Address 0x4006 0000 0x4006 1000 0 4006 2000 e Address Base Address 0x0014 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 Pwes s 19 sro ERI e Pwes Pwe e REPEAT EXT EL e Reserved O 0 PWM output exten
131. reduce the reset time you can do it by changing BT divider value of smart option Refer to the CM Clock Manager chapter about basic timer related to the reset time SAMSUNG ELECTRONICS 9 7 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 2 2 2 Protection Smart Option In some cases you might need to protect the data or code programmed in the flash memory You should protect the data or code programmed in flash memory The internal flash memory controller supports three kinds of protection mechanism to protect data You can control it by programming the Protection Smart Option bit The Protection Smart Option value should be configured at address 0x0000_00C4 The three kinds of protection mechanism are e HARDWARE HARDLOCK Protection Protection for selected regions among four regions or full region e READ Protection Flash Read protection for serial interface e SWD Protection Flash Read protection through SWD interface Table 9 5 describes the Protection Smart Option address and the protection bits Table 9 5 Protection Smart Option Address and Control Bits IFC AR Bit Description Description Reset Value Bit 8 Enables SWD Protection 1 Disables SWD Protection an Enables Hardware Protection Disables Hardware Protection Bit 27 Enables Read Protection Disables Read Protection Bit 4 Hardware Protection Region Selection Bits Sector 0 Bit 5 Each of these bits is mapped to a corr
132. register 0x0000 0000 MHRO 0x0004 Mode high register 0 0 00 0000 PUCRO 0x0008 Pull up control register 0x3000 0000 ODCRO 0x000C Open drain control register 0x0000 0000 SAMSUNG ELECTRONICS 12 4 ex S3FN429_UM_REV1 20 12 Configuration 12 3 1 1 IOCONF_MLRO e Base Address 0x4005 8000 e Address Base Address 0x0000 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 0 2 5 0 14 FSEL 100_15_FSEL 100_13_FSE 100_12_FSEL 100_11_FSEL 100_10_FSEL 100_9_FSEL 100_8_FSEL 00 7 FSEL 0 6 FSEL 0 5 FSEL 4 FSEL 100_3_FSEL 100_1_FSEL 100_0_FSEL RIR R R R R R R RI R R RI IR R I R R R R JR R R R I R R R R R R R R R R 15 FSEL 81 30 14 FSEL 29 28 13 FSEL 27 26 12 FSEL 25 24 11 FSEL 23 22 00 10 FSEL 21 201 9 FSEL 19 18 100 y Function Selection 00 8 FSEL 17 16 00 b Function 0 GPIO 07 FSEL 15 14 100 6 FSEL 13 12 11 b Function 5 FSEL 11 10 4 FSEL 9 8 3 FSEL 7 6 2 FSEL 5 4 00 1 FSEL 3 2 0 FSEL 1 0 NOTE If you write undefined function value to xFSEL 1 0 Fx Function x then x FSEL 1 0 will not change and will remain as the valid pre configuration Table 12 1 Function Mode Configu
133. smart option program twice When you program the new smart option value all other bits except the smart option control bits field should be 1 To perform the smart option program the steps are 1 2 Write the value Ox5A5A5A5A into the IFC_KEY register Write the address to be written into the Address Register IFC_AR In case of Configuration Smart Option the address is 0 000000 0 In case of Protection Smart Option the address is 0 000000 4 Write the smart option value into the Data Register DR Write the smart option program command and start control bit in Control Register CR Check whether the operation of smart option program is completed or not You can use one ways between polling and interrupt check If you monitor the status bit of END check END bit in Raw Interrupt Status Register RISR SAMSUNG ELECTRONICS 9 13 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 2 3 1 8 Interrupt There are four interrupt sources related to the flash operation Table 9 6 describes the interrupt sources Table 9 6 Description of Interrupt Sources Occurs when the command operation is completed END CMD 2 0 filed in control register has the selected command Occurs when trying to execute other operation program erase during operating normal program EARD command BUSY 1 during operation sequence ERR2 Occurs when writing or erasing to the protected memory region 1 O
134. source is dependent on both the smart option value which controls the start up clock source and the Basic Timer clock division ratio and the reset source The most optimized Ts Tbt value can be obtained with the IMCLK as start up clock source and 1 1 as Basic Timer clock division ratio With minimum setting of clock division ratio using smart option the Tbt value can be less than 20us and Ts value is the most important value to affect the start up time The Most Optimized Ts Tbt value Max 1 ms Reset source POR or LVD Reset Start up clock source IMCLK The Most Optimized Ts Tbt value Max 200 us Reset source Others Start up clock source IMCLK SAMSUNG ELECTRONICS 5 31 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 8 Fast Wake up For fast Wake Up from STOP mode you can use the FWAKE control bit You should enable the FWAKE bit before the STOP mode When fast Wake Up releases the system from STOP mode the SYSCLK is the IMCLK regardless of enable disable status before the STOP mode It is not required to use the fast Wake Up when the SYSCLK is the IMCLK before the STOP mode Figure 5 78 illustrates the fast wake up SYSCLK Fast Wakeup Enable Wakeup FWAKE 1 PLLCLK SYSCLK Figure 5 18 Fast Wake Up Figure 5 19 illustrates the BT and exit of stop mode when FWAKE is 0 Asserted Wakeup Event Interrupt System Wakeup MODE NORMAL STOP Mode Transition NORMAL Mode 1 SYSCLK IMCLK case IMCLK St
135. the PCLK domain are certain to get synchronized before one frame duration e lt In the slave mode of operation the SSPCLKIN signal from the external master is double synchronized and then delayed to detect an edge It takes three SSPCLKs to detect an edge on SSPCLKIN The SSPTXD pin has less setup time to the falling edge of SSPCLKIN on which the master is sampling the line The setup and hold times on SSPRXD with reference to SSPCLKIN must be more conservative to ensure that it is at the right value when the actual sampling occurs within the SSPMS To ensure correct device operation SSPCLK must be at least 12 times faster than the maximum expected frequency of the SSPCLKIN The frequency selected for SSPCLK must accommodate the desired range of bit clock rates The ratio of minimum SSPCLK frequency to the SSPCLKOUT maximum frequency in the case of slave mode is 12 and for the master mode it is two To generate a maximum bit rate of 1 8432 Mbps in the master mode the frequency of SSPCLK must be at least 3 6864 MHz With an SSPCLK frequency of 3 6864 MHz the SSPCPSR register has to be programmed with a value of two and the SCR 7 0 field in the SSPCRO register needs to be programmed as zero To work with a maximum bit rate of 1 8432 Mbps in the slave mode the frequency of SSPCLK must be at least 22 12 MHz With an SSPCLK frequency of 22 12 MHz the SSPCPSR register can be programmed with a value of 12 and the SCR 7
136. the PrimeCell SSP slave is not supposed to drive the SSPTXD line SAMSUNG ELECTRONICS 15 20 ex S3FN429_UM_REV1 20 15 Serial Peripheral Interface SPI 15 3 1 3 SSP_DR e Base Address 0x4009 0000 0x4009 1000 e Address Base Address 0x0008 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 WINIWIW IW W W W W W W W W W W W RSVD aia n 0109 Transmit Receive FIFO Read Receives FIFO Write Transmits FIFO DATA 15 0 RW The user should right justify the data when the PrimeCell 0x0000 SSP is programmed for a data size that is less than 16 bits Unused bits at the top are ignored by the transmit logic The receive logic will automatically right justify When SSPDR is read the entry in the Receive FIFO that is pointed to by the current FIFO read pointer is accessible As data values are removed by the PrimeCell SSP receive logic from the incoming data frame they are placed into the entry in the Receive FIFO that is pointed to by the current FIFO write pointer When SSPDR is written to the entry in the Transmit FIFO that is pointed to by the write pointer is accessible The data values are removed from the Transmit FIFO one value at a time by the transmit logic It is loaded to the transmit serial shifter serially shifted out onto the SSPTXD pin at the programmed bit rate When a data size of less than 16 bit is selected the u
137. the interrupt 1 OVR interrupt is not masked Enables the interrupt OVR includes from OVRO to OVR10 End of Conversion Interrupt Mask 0 EOC interrupt is masked Disables the interrupt 1 EOC interrupt is not masked Enables the interrupt Hardware sets this bit and software clears it NOTE On a Read the ADC_IMSCR register gives current value of mask on the relevant interrupt A Write of 1 to a particular bit sets mask and enables the interrupt to be read A Write of 0 to a particular bit clears the corresponding mask SAMSUNG ELECTRONICS 4 32 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 2 1 13 ADC_RISR e Base Address 0 4004 0000 e Address Base Address 0x0068 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 ASV pray R Overrun Raw Interrupt Status Provides raw interrupt state prior to masking of OVR interrupt End of Conversion Raw Interrupt Status Provides raw interrupt state prior to masking of EOC interrupt NOTE On a Read the ADC_RISR register gives the current raw status value of the corresponding interrupt prior to masking A Write makes no effect SAMSUNG ELECTRONICS 4 33 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 2 1 14 ADC_MISR e Base Address 0 4004 0000 e Address Base Address 0x006C Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
138. third party Samsung reserves its right to take any and all measures both in equity and law available to it and claim full damages against any party that misappropriates Samsung s trade secrets and or confidential information BE Rie RARE B E L T RS T8 AG fo SCPE EE AIT TG BSB SRP PRS tt A IETS it CLEAN NI k Trademarks All brand names trademarks and registered trademarks belong to their respective owners Exynos Exynos4210 FlexOneNAND and OneNAND are trademarks of Samsung Electronics e Jazelle TrustZone and Thumb are registered trademarks of ARM Limited Cortex ETM ETB Coresight ISA and Neon are trademarks of ARM Limited e is a trademark of Sun Microsystems Inc e SD is a registered trademark of Toshiba Corporation e MMC and are trademarks of MultiMediaCard Association e JTAG is registered trademark of JTAG Technologies Inc e Synopsys is a registered trademark of Synopsys Inc
139. tool program mode When you enable this function then reading flash data with serial interface results in zero read out SAMSUNG ELECTRONICS 9 9 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 2 3 Modes This section describes User Mode and Tool Mode e User Mode Read Operation Page Erase Operation Sector Erase Operation Entire Erase Operation Normal Program Operation Smart Option Erase Operation Smart Option Program Operation e Tool Mode Also called as Serial Program Mode SPGM Flash Program Tool 9 2 3 1 User Mode You can program or erase normal flash and smart option area in User Program Mode You can configure User Program Mode by MODE1 and MODE 0 Refer to Pin Configuration chapter To write any data to normal flash area you should clear the target address before program There are three ways page sector and entire erase to clear the normal flash area The flash area to be erased becomes all 1 9 2 3 1 1 Read Operation You can read and access 8 bit 16 bit or 32 bit 9 2 3 1 2 Page Erase Operation The size of a page is 256 B The page erase operation erases one page to include address written into Address Register AR To perform page erase the steps are 1 Write the value Ox5A5A5A5A into the IFC KEY register 2 Write the address for target page to the Address Register AR The address should be one in range of target page Simply u
140. transmission of a break starts transmission of a break after the characters present in the Transmit Shift Register is transmitted mv B R reseve Transmitter Disabled TXDIS 7 W 0 No effect 1 Disables the transmitter Transmitter Enable TXEN W 0 No effect 1 Enables the transmitter if TXDIS is 0 SAMSUNG ELECTRONICS 17 26 x S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 0 No effect 1 Disables the receiver Receiver Enable 0 No effect 1 Enables the receiver if RXDIS is 0 Reset Receiver 0 No effect 1 Resets the receiver logic mv mo R Reset Transmitter 0 No effect 1 Resets the transmitter logic SAMSUNG ELECTRONICS 17 27 ex S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 8 1 5 US_MR e Base Address 0x4008_0000 e Address Base Address 0x0010 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 1 817 6 5 4 3 0 9 lt n RIR R R R R R WIN W W EET N SENDTIME FESSES CHMODE NBSTOP Data Start Bit Selection 20 0 Data transmission starts from LSB and ends at MSB 1 Data transmission starts from MSB and ends at LSB a Clock Output Select CLKO 18 0 The USART does not drive the USARTCLK pin 1 The USART drives the USARTCLK pin if CLKS 1 is
141. transmitted e ISR Exit SAMSUNG ELECTRONICS 17 21 ex S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 8 Register Description 17 8 1 Register Map Summary e Base Address 0x4008_0000 messer Resevaue SAMSUNG ELECTRONICS 17 22 ex S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 8 1 1 US_IDR e Base Address 0 4008 0000 e Address Base Address 0x0000 Reset Value 0x0011_001B 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 IDCODE 25 0 ID Code Register 0x0011_001B This field stores the ID code for the corresponding IP SAMSUNG ELECTRONICS 17 23 ex S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 8 1 2 US_CEDR e Base Address 0 4008 0000 e Address Base Address 0x0004 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 R WwW Debug Mode Enable 0 Disables debug mode 1 Enables debug mode Read 0 The debug acknowledge generated by the debug DBGEN 31 RW interface dbgack_sclk input signal has no influence on the USART function 1 The debug acknowledge freezes the USART function when the debug interface is activated high level on input pin However Read Write access to internal register
142. when values are written to the register Either GPIO ODSR or GPIO PDSR can read the current data value of each pin 8 2 4 Operation Mode GPIO has different configurations and behaviors according to the operation modes 8 2 4 1 Normal Mode In a normal mode the GPIO is powered operational and configurable The GPIO control block is clocked by PCLK 8 2 4 2 Low Power Modes In an idle mode the GPIO is powered on and clocked by PCLK It is configurable The PCLK is also allowed to disconnect the clock to reduce the power consumption After exiting from an idle mode the configuration and states of I Os are not changed In a stop mode the clock is disconnected but the power is still maintained Therefore the configuration and states of I Os are preserved by itself After exiting from stop mode the configuration and states of I Os do not change SAMSUNG ELECTRONICS 8 3 ex S3FN429_UM_REV1 20 8 General Purpose I O GPIO 8 2 5 Interrupt Each GPIO controller block also provides an internal interrupt signal When a rising edge or falling edge level change occurs you can program each GPIO to generate an interrupt The interrupt occurs regardless of the port configuration and data direction It occurs when an edge transition occurs on a pin while the port is configured for the peripherals or output The interrupt detects any edge transition The GPIO interrupt registers are e Interrupt Mask Set and Clear Register GPIO_IMSCR
143. 0 4002 0000 e Address Base Address 0x0058 Reset Value 0x0000 0154 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 PLLSKEY 8 WIN WIW WI W W W W Bit Type Description Reset Value Key for Write access into the CM PSTR register PLLSKEY 31 16 Any Write in the PSTR register bits will only be effective if the PLLSKEY field is equal to 0x59C1 wo nen resem 9 PLL Stabilization Time PST 10 0 RW PST register value PLL stabilization time EMCLK period x 256 NOTE When you disable the PLL then the Stabilization Time Register will have Write access If you enable the PLL then the register will have Read access SAMSUNG ELECTRONICS 5 62 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 1 18 CM_PDPR e Base Address 0 4002 0000 e Address Base Address 0x005C Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 s 7 6 5 43 210 PLLPOST PLLPRE PLLMUL R R R R R JRI IR R IR R R R R R R PLL Parameter Control Register Key Value Key for Write access into the CM_PSTR register Any Write in CM_PDPR register bits is only effective if the PLLKEY is equal to OxC1 Low Frequency Pass Control Bit 0 is the same or greater than 4 MHz Fi gt 4 M
144. 0 bit is set to 1 then all odd numbered cycles are one pulse longer If all extension bits PWMEX 5 0 is set to 1 then all cycles stretches by one pulse except the 64 cycle Thus you can obtain high output resolution at high frequencies SAMSUNG ELECTRONICS 14 8 ex S3FN429_UM_REV1 20 14 Pulse Width Modulation Figure 14 5 illustrates the extended PWM waveform PWM Period 0x40 Pulse PWMEXO 0x0 0x40 PERIOD 15 0 0x40 PULSE 15 0 Ox3E PWMEX 1 0 0x0 gt Extension PERIOD 15 0 0x40 PULSE 15 0 0x3E stretch Figure 14 5 Extended PWM Waveform PWM Period 0x40 Pulse PWMEXO SAMSUNG ELECTRONICS 14 9 27 S3FN429_UM_REV1 20 14 Pulse Width Modulation Figure 14 6 illustrates the extended PWM Waveform PWM Period 0x40 Pulse PWMEX 1 0 0 0x40 PERIOD 15 0 0x40 PULSE 15 0 Ox3E 4 x Extension PWMEX 1 0 0x1 PERIOD 15 0 0x40 PULSE 15 0 0x3E stretch Figure 14 6 Extended PWM Waveform PWM Period 0x40 Pulse 0x3E PWMEX1 SAMSUNG ELECTRONICS 14 10 en S3FN429_UM_REV1 20 14 Pulse Width Modulation Figure 14 7 illustrates the extended PWM Waveform PWM Period 0x40 Pulse PWMEX1 and N Normal Period E Extension Period PERIOD 64 PULSE 2 PWMEXO 1 H P 64th 64 periods
145. 0 001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 s 7 6 5 43 210 no s een a EMCKFAIL EMCKFAIL_END PLL ek e E se we sre WDTCLKS RSVD P wx Desorption Reset Value SysReset Status SYSRST is System Chip Reset by CPU request 0 CPU reset request does not occur 31 1 CPU request causes the last reset This bit is cleared when NRSTS PORRSTS or LVDRSTS occurs or you write this bit to 1 External Clock Monitor Reset Status System Chip reset from external main clock monitor fail 0 External Main Clock Monitor fail reset does not occur EMCMRSTS 30 R 1 External main clock monitor fail reset causes the last reset When nReset POR reset or LVR reset occur it clears this bit by hardware To clear by software writes this bit to 1 RED R Power On Reset Status PORRST is System Chip Reset by Power On Reset circuit POS aS 28 iu 0 Power on reset does not occur 1 Power on reset occurs To clear this bit write to 1 Watchdog Timer Reset Status WDTRST is System Chip Reset by watchdog timer 0 Watchdog timer reset is not occurred TRST 27 RW WISIS 27 1 The last reset is caused by Watchdog timer reset When nReset POR reset or LVR reset occur it clears this bit by hardware To clear by software writes this bit to 1 LVD Reset Status 2 RW LVDRSTS DEAE LVDRST is System Chip Reset by LVD SAMSUNG E
146. 0000 e Address Base Address 0x0034 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 WINIWIW IW W W W W W W W W W W W Description Reset Value Time Out Value When a value is written to this register a time out start command is automatically performed Time Out configuration field rons Disables the receiver time out function 15 0 RW The time out counter is loaded with TO 15 0 0x0000 when the time out start command is given or when each new data character is received after reception has started 1 to 65565 e n asynchronous mode Time out duration TO 15 0 x Bit period synchronous mode Time out duration 2 TO 15 0 x 16 x Bit period Caution When the receiver is disabled by setting the RXDIS bit in the US CR register the time out is stopped If the receiver is re enabled by setting the RXEN bit in the US register then the time out restarts from where it was stopped it is not reset SAMSUNG ELECTRONICS 17 44 en S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 8 1 15 US_TTGR e Base Address 0x4008_0000 e Address Base Address 0x0038 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 WIN WIW I W W W W feral
147. 00000 b The compare registers ASCRRx ASCFRx IMC_PACR FR PBCR FR PCCR FR are written in the rising falling time All real update of written compare registers is executed at the 0 time simultaneously IMG TCR Figure 10 26 Synchronous Write at Zero Match SYNCSEL 01 b NUMSKIP 00000 b SAMSUNG ELECTRONICS 10 34 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC Figure 10 27 illustrates the synchronous write at IMC_TCR match All real update of The compare registers IMC_ASCRRx ASCFRx written compare IMC PACR FR PBCR FR PCCR FR registers is executed at are written in the rising falling time the IMC TCR time simultaneously TCR The compare registers ASCRRx IMC ASCFRx IMC PACR FR PBCR FR IMC_PCCR FR are written in the rising time All real update of written compare registers is executed at the TCR time simultaneously Figure 10 27 Synchronous Write at IMC TCR Match SYNCSEL 10 b NUMSKIP 00000 b NOTE If WMODE is equal to 1 and NUMSKIP is equal to 1 then the update of compare registers look like the illustration in Figure 10 28 If NUMSKIP is 1 then the written compare registers are updated once per two TCR and 0 time Second and fourth pulse is the skipped pulse Figure 10 28 illustrates the synchronous Write at Zero and IMC TCR Match SYNCSEL 00 b NUMSKIP 00001 b Real update t
148. 0_0000 e Address Base Address 0x0098 Reset Value 0x0000_0000 e Address Base Address 0x009C Reset Value 0x0000 0000 Address Base Address 0 Reset Value 0x0000_0000 e Address Base Address 0 00 4 Reset Value 0x0000_0000 Address Base Address 0x00A8 Reset Value 0x0000_0000 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 9 8 7 6 5 4 3 2 1 0 me m Conversion Result Data of ADC A D converter Output Data Result 0x000 OxFFF DATA 11 0 When A D sequence conversion is finished the conversion result can be read from the ADC_CRR register SAMSUNG ELECTRONICS 4 36 x S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 2 1 17 ADC_GCR e Base Address 0 4004 0000 e Address Base Address Reset Value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 GCC_FRAC GCC_INT RIR R R R R I R R R R R R R R R Revo ea R Red econ tq ADC Gain Calibration Constant Value ADCGCC field is fixed point unsigned value ADCGCC 14 0 Fixed point unsigned value GCC x 2 The fix int unsigned value GCC gets from the followin i For o ed Refer Section 4 0 1 Calibration Unit ae GCC IDLE75 25 IDLE25 RAW75 95 RAW25 The calculated result GCC should be limited from 0 5 to
149. 1 Inserts dead time PWMXU 1 Dead Time Insert Bit This bit determines whether dead time is inserted or not before PWM output disable by setting PWMxU1EN 0 Does not insert dead time 1 2 Inserts dead time PWMxU2 Dead Time Insert Bit This bit determines whether dead time is inserted or not before PWM output disable by setting PWMxU2EN 0 Does not insert dead time 1 Inserts dead time 27 2 2 PWMxU2DT PWMxDODT PWMXxDO Dead Time Insert Bit This bit determines whether dead time is inserted or not before PWM output disable by setting PWMxDOEN 0 Does not insert dead time 1 Inserts dead time PWMXxD1 Dead Time Insert Bit This bit determines whether dead time is inserted or not before PWM output disable by setting PWMxD1EN PWMxD1DT 0 Does not insert dead time 1 2 Inserts dead time PWMxD2DT 16 RW Mb Time Insert Bit mM This bit determines whether dead time is inserted or not SAMSUNG ELECTRONICS 10 38 z D 20 S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC Bit TL PWMxD2LEVEL m RSVD 7 14 6 1 before PWM output disable by setting PWMxD2EN 0 Does not insert dead time 1 Inserts dead time Reserved PWMXxUO Output Level Selection Bit 0 Low Level 1 High Level PWMxU1 Output Level Selection Bit 0 Low Level 1 High Level PWMXU Output Level Selection Bit 0 Low Level 1 High Level PWMXxDO Output Level Selectio
150. 1 2 2 Speed Counter Sign Carry Overflow SCSOVF SCCOVF and Speed Counter Sign Carry Underflow SCSUNF SCCUNF will be cleared automatically by SCCL CR1 18 SAMSUNG ELECTRONICS 7 23 ex S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 3 1 11 PPD_PCR e Base Address 0x400C_0000 e Address Base Address 0x0028 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 WINIWIW IW W W W W W W W W W W W Position Counter Value aes 0x0000 This field contains the current position counter value SAMSUNG ELECTRONICS 7 24 ex S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 3 1 12 PPD_PCRR e Base Address 0x400C_0000 e Address Base Address 0x002C Reset Value 0x0000_0000 31 30 29 28 27 26 25 24123 22 21 20 19 18 17 16 15 14 13 12 11 10 a gt A e PREFDAT zae RIR R R R R R R R R RSVD Position Counter Reference Data Value PREFDAT 15 0 RW This field determines the reference value for position 0x0000 counter SAMSUNG ELECTRONICS 7 25 ex S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 3 1 13 PPD_PCTR e Base Address 0x400C_0000 e Address Base Address 0x0030 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987
151. 1 20 16 Timer Counter 16 2 6 Overflow Mode When OVFM bit is set in the TC_SR register the timer operates as Overflow Mode The TC increases the counter value in this mode until it reaches 25 1 where SIZE is specified in TC_CCSMR Current Counter Size Mask Register After that if REPEAT bit is set to clear in TC_SR register then the counter value will be cleared to 0 and generates Stop interrupt and Overflow interrupt You should set PERIOD to greater than 0 in the PRDR register before starting the timer even though PERIOD is not used 16 2 6 1 Match and Overflow Operation In the match and overflow operation the TC generates e Start interrupt and Period Start interrupt when the timer starts e Pulse Match interrupt when the counter value is identical to PULSE bits in CPULR register e Period End interrupt when the counter value is identical to PERIOD bits in CPRDR register e Overflow interrupt when the counter overflows If REPEAT bit SR register is set on overflow then the counter value will be changed to 1 and the timer restarts automatically Figure 16 2 illustrates the match and overflow operation timing Conditions TC SR OVFM 1 REPEAT 1 CCSMR SIZE 3 CPULR PULSE 4 CPRDR PERIOD 8 LI LILI UT UU UU UU UU UU EEUU UU LU UU L TC_CVR COUNT ok 242 415 59 546 SR START TC RISR STARTI
152. 12 2 12 3 Register 12 4 12 31 Register Map Sumnmlaly 5 tette tette ed Laden 12 4 13 OPERATIONAL AMPLIFIER 13 1 13 HO 13 1 MS Ad FoU S 13 1 131 2 Pini DEOSCHPUON m 13 1 13 1 8 Block Diagram I X 13 2 1314 Gain Generation Circuit nazi 13 3 13 2 13 4 13 21 Register Map SUM Many iasence inaia 13 4 14 PULSE WIDTH MODULATION cscscsssdestcnsscscecssctonstccutecccsnacesreccscesasssssnnsscce 14 1 TAA M EE A A E 14 1 ausu ERES 14 1 14 EAR 14 1 14 2 Functional Description obe ret tereti 14 2 T4 2 1 Block 14 2 14 2 2 General 14 3 14 2 3 Clock and Operation 14 4 14 24 14 4 1425 PULSE Level
153. 16 96 0 16 96 0 16 96 0 16 96 0 16 96 0 16 96 0 03 0 03 0 16 96 0 16 96 0 22 96 0 16 96 0 03 0 16 96 0 16 96 0 16 96 0 16 96 0 16 96 2403 85 1200 48 2398 08 4807 69 9615 38 19230 77 38461 54 1199 04 2403 85 4807 69 9615 38 19230 77 38461 54 1201 92 2403 85 4807 69 9615 38 19230 77 1201 92 2403 85 4807 69 9615 38 1201 92 2403 85 4807 69 1199 62 2399 23 4807 69 9615 38 14367 82 19230 77 1199 62 2403 85 4807 69 9615 38 1201 92 2403 85 1200 104 9600 104 4800 833 16 52 26 08 52 26 13 08 52 2400 26 4800 13 9600 52 1 26 13 521 20 87 65 521 10 2 65 2 2400 4800 1042 1200 2400 9600 1200 2 20 MHz 1 2 4 16 1 2 4 130 5 9600 SAMSUNG ELECTRONICS 17 47 S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter US 0 15 0 BaudRate Result 130 1200 0 16 2400 0 16 1 1200 0 16 1200 0 02 2400 0 03 96 4800 0 03 9600 0 16 14400 0 22 19200 0 16 38400 0 16 o 1200 0 03 2400 0 03 25 4800 0 16 9600 0 16 14400 0 22 19200 0 16 1200 0 03 2400 0 16 n 4800 0 16 9600 0 16 1200 0 16 5 2400 0 16 4800 0 16 6 25 1200 1201 92 0 16 2400 2403 85 0 16 95 SAMSUNG ELECTRONICS
154. 18 ex S3FN429_UM_REV1 20 15 Serial Peripheral Interface SPI 15 3 1 1 SSP_CRO e Base Address 0x4009 0000 0x4009 1000 e Address Base Address 0x0000 Reset Value 0x0000 0000 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1 6 5 4 3 21 0 WIN WIW W W WIN IW W W mw R _ Serial Clock Rate Field Use the SCR value to generate the transmit and receive bit SCR 15 8 RW rate The Bit Rate FPCLK CPSDVR 1 SCR The CPSDVSR is an even value from 2 to 254 you can program this through the SSP_CPSR register and SCR is a value from 0 to 255 SSPCLKOUT Phase SPH 7 RW 0 Captures data on the first clock edge transition 1 Captures data on the second clock edge transition SSPCLK Polarity Bit SPO RW 0 Captures data on the first clock edge transition 1 Captures data on the second clock edge transition Frame Format Selection Field FRF 4 RW rer _ Should be 00 for Motorola SPI frame format Data Size Selection Field 0000 to 0010 Reserved 0011 4 bit data 0100 5 bit data 0101 6 bit data 0110 7 bit data 0111 8 bit data DSS 3 0 RW 1000 9 bit data 0000 b 1001 10 bit data 1010 11 bit data 1011 12 bit data 1100 13 bit data 1101 14 bit data 1110 15 bit data 1111 16 bit data SAMSUNG ELECTRONICS 15 19 15 3 1 2 SSP_CR1 e Base Address 0x4009 0000 0x4009 1000 e Address
155. 19 18 17 16 15 14 13 12 11 10 a B A ADCMPR1DAT ele es RIR R R R R R R R R RSVD ma R Red ADC Compare Data 1 for Rising time ADCMPR1DAT 15 0 RW This field determines the ADC compare register value 0x0000 at rising SAMSUNG ELECTRONICS 10 62 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 3 1 23 IMC_ASCRR2 Base Address 0 400 0000 Address Base Address 0x0058 Reset Value 0 0000 0000 31 30 29 28 27 26 25 24123 22 21 20 19 18 17 16 15 14 13 12 11 10 a B A ADCMPR2DAT ele es RIR R R R R R R R R RSVD ADC Compare Data 2 for Rising time ADCMPR2DAT 15 0 RW This field determines the ADC compare register value at 0x0000 rising SAMSUNG ELECTRONICS 10 63 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 3 1 24 IMC_ASCFRO Base Address 0 400 0000 e Address Base Address 0x005C Reset Value 0 0000 0000 31 30 29 28 27 26 25 24123 22 21 20 19 18 17 16 15 14 13 12 11 10 o gt o ADCMPFODAT EXER es RIR R R R R R R R R RSVD ADC Compare Data 0 for Falling time ADCMPFODAT 15 0 RW This
156. 2 11 10 9 8 7 6 5 4 3 2 41 0 ASV ery R Received Character Last character received if RXRDY is set The register RXCHR maintains the value until it receives a new byte When number of data bits is less than 9 bit the bits are right aligned Caution Read the US_RHR register clears the RXRDY bit During the debug mode you should use the ghost registers to avoid clearing RXRDY bit SAMSUNG ELECTRONICS 17 40 ex S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 8 1 12 US_THR e Base Address 0x4008_0000 e Address Base Address 0x002C Reset Value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 Character to be Transmitted If TXRDY is at a logical 1 then this is the next character to be transmitted after a current one if already a character is present in the transmit shift register If TXRDY is at a logical 0 then the current character in the US_THR register is overwritten When number of data bits is less than 9 bit then the bits are right aligned SAMSUNG ELECTRONICS 17 41 ex S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 8 1 13 US_BRGR e Base Address 0x4008_0000 e Address Base Address 0x0030 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 RIR R RI JR R R RIRIR R R R R R R
157. 2 2 RE 10 3 10 2 3 Phase Signal 4 4 10000 10 5 10 3 Register eut pase co pa tede gue dan waned bade dereud ed 10 25 10 3 1 Register Map entente 10 25 11 INTERRUPT CONTROLLER 11 1 ue cc 11 1 iul 11 1 11 2 Functional Description PAPER 11 2 11 24 INtSrrupt 1 79 E aes 11 2 11 2 2 m 11 4 11 3 Register Description iicet teet RE E e E ede Flap De deg 11 6 11 3 1 Register Map SUMMANY BRE e nae ERO 11 6 12 O CONFIGURATION UE 12 1 ev p 12 1 SAMSUNG ELECTRONICS T2 12 1 12 2 Functional DeSCriptiOn eterne ev ecu ee eee eee eee ee 12 2 12 271 General Description aes erdt e rd etat ensue ce tanc aL a amie ia 12 2 12 2 2 Peripheral Configuration isst
158. 2 2 1 3 11 Motorola SPI Format with SPO 1 SPH 0 Figure 15 5 and Figure 15 6 illustrates the single and continuous transmission signal sequences for Motorola SPI format with SPO 1 SPH 0 respectively a ka W am SSPRXD oes 40 16 bits SSPTXD E Figure 15 5 Motorola SPI Frame Format Single Transfer with SPO 1 and SPH 0 SSPCLK Xu Xu as CON SSPFSS sq E As Ru SSPTXD i i SSPRXD 410 16 bits 31 3 Figure 15 6 Motorola SPI Frame Format Continuous Transfer with SPO 1 and SPH 0 In this configuration during the idle periods e The SSPCLKOUT signal is forced HIGH e SSPFSSOUT is forced HIGH e The transmit data line SSPTXD is arbitrarily forced LOW e When the PrimeCell SSP is configured as a master the SSPCLKOUT is enabled e When the PrimeCell SSP is configured as a slave the SSPCLKOUT is disabled If the PrimeCell SSP is enabled and there is valid data within the Transmit FIFO the start of transmission is signified by the SSPFSSOUT master signal being driven LOW which causes slave data to be immediately transferred onto the SSPRXD line of the master The master SSPTXD output pin is enabled One half period later valid master data is transferred to the SSPTXD line Now that both the master and slave data have been set the SSPCLKOUT master clock pin becomes LOW after one further half SSPCLKOUT period This mean
159. 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 ASV n IDCODE 25 0 ID Code Register 0x0011 000A This field stores the ID code for the corresponding IP SAMSUNG ELECTRONICS 16 19 ex S3FN429_UM_REV1 20 16 Timer Counter 16 3 1 2 TC_CSSR e Base Address 0 4006 0000 4006 1000 0 4006 2000 e Address Base Address 0x0004 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RSV 07 Clock Source Selection Field 0 Counter Clock Source is PCLK LKSR 1 Counter Clock Source is external clock which is provided through TCLK pin Caution The frequency of external clock TCLK should be lesser than the internal clock PCLK 0 N R After enabling the TC clock you cannot change the clock source Therefore before changing the clock source CLKSRC you should clear the CLKEN bit of the TC_CSSR register SAMSUNG ELECTRONICS 16 20 ex S3FN429_UM_REV1 20 16 Timer Counter 16 3 1 3 TC_CEDR e Base Address 0 4006 0000 0x4006_1000 0 4006 2000 e Address Base Address 0x0008 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 R Debug Mode Enable Disable Control Bit 0 Disables Debug Mode DBGEN 31 RW 1 Enables Debug Mode If DBGEN is set then the count
160. 3 Phase Inverter Motor Controller IMC 1 x USART 1 x SPI 12 bit Analog to Digital Converter ADC with external input AINx 10 Channel 1 x Operational Amplifier OP AMP 4 x Comparator COMP Supports idle and stop mode for reducing current SAMSUNG ELECTRONICS 1 1 ex S3FN429_UM_REV1 20 1 2 Features S3FN429 device contains CPU Memory Interrupt Controller Clock Manager CM Watchdog Timer WDT 16 bit Timer Counter TC Pulse Width Modulation PWM Pulse Position Decoder PPD Inverter Motor Controller IMC Universal Synchronous Asynchronous Receiver Transmitter USART Serial Peripheral Interface SPI Analog to Digital Converter ADC Operational Amplifier OP AMP Comparator COMP General Purpose IO GPIO Two Low Power Modes Power On Reset POR Low Voltage Detection LVD Phase Locked Loop PLL Operating Voltage Range Operating Frequency Range Operating Temperature Range Available in 44 QFP Package SAMSUNG ELECTRONICS 1 2 1 Product Overview S3FN429_UM_REV1 20 CPU The CPU contains e 32 bit RISC ARM Cortex MO Core e Serial Wire Debug SWD Memory The Memory supports e 32 KB internal program full flash e 2 KB internal SRAM e Only little endian Interrupt Controller The Interrupt Controller supports e of Cortex MO e Dynamically reconfigurable interrupt priority four priority levels e 32 device interrupt vectors e Selectable eight External Interrupts n e
161. 32 KB 9 1 1 Features The features of the flash memory are e Flash memory size 32 KB e Program size word 32 bit e size 256 Bytes e Sector size 8 KB e Erase unit Page or Sector e Number of sectors 4 sectors e Number of pages 128 pages Program Ease Cycle Endurance 10 000 e Protection supports Serial Wire Debug SWD interface protection Hardware protection and Read protection Table 9 1 describes flash configuration Table 9 1 Flash Configuration ee SAMSUNG ELECTRONICS 9 1 x S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 2 Functional Description Figure 9 1 illustrates the non pre fetch flash block diagram HADDR Addro Addr4 Addr8 Addr10 EZ Addr18 HREADY Flash ADDR Addro Addr4 Addr8 Addr10 Addri4 RR Figure 9 1 Flash Block Diagram Non Pre Fetch Figure 9 2 illustrates the pre fetch flash block diagram Addr4 Addr8 AddrC Addr10 HADDR NSEQ even SEQ odd SEQ even SEQ odd SEQ even HREADY Flash ADDR Flash RDB Flash DOUT HRDATA Figure 9 2 Flash Block Diagram Pre Fetch SAMSUNG ELECTRONICS 9 2 x S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 2 1 Organization This section describes Flash Configuration and Address Alignment in detail 9 2 1 1 Flash Configuration The flash ROM consists of four sectors Each sector consist
162. 6 5 6 3 1 Register Map 4 6 5 7 PULSE POSITION DECODER srssecicscassctiaceseacsnascnsscacsseccassssscacacaseanssetcnacexceses 7 1 7 1 QV CIVIOW 7 1 PAV Em 7 1 721 2 Pin DeSCrIplIOn iot Oe nitent 7 1 7 2 Functional DescriptiOl oua coc ett rentre pe toc v eter 7 2 T2 l 4 situe 7 2 7 2 2 Operating tee bo e ean 7 3 SAMSUNG ELECTRONICS ex 7 9 Register Description ident em cette eti eid ettet edem esc EEE 7 6 7 3 1 Register Map Sumrmary inocente 7 6 8 GENERAL PURPOSE YO orar saa unisn soa 8 1 Eu E 8 1 8 1 8 1 2 xiii M 8 1 8 2 Funcional re esos cs 8 2 8 2 GPIO GonflIgUraltlOn 8 2 8 2 2 Inp t ConfigUratiOn Pen FR
163. 8 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 Busy Status Flag 0 Specifies flag not in operation Programming or Erasing 1 Specifies reported flag when flash is programming or erasing NOTE This bit is changed from 0 to 1 at the real time A to start flash IP operation after START bit with command sets to 1 There will be some delay between and So you should not write new IFC_CR IFC_KR IFC_DR and AR values before BUSY bit SR 0 sets to 1 Clear is performed automatically when END bit is set to 1 SAMSUNG ELECTRONICS 9 37 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 3 1 11 IFC_AR e Base Address 0x4001_0000 e Address Base Address 0x0028 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 RI RI R RIJR R R R R I RI IR R RI R R R R RIRI R RIR R IR R R R R R R R R wiw iw wiW IW W W W W W W W W W W W W W W W W W W W W W W W W W W Internal Flash Memory Address to Program Normal Smart Option or Erase Page Sector AR 31 0 lt You can select address in flash memory range ADDR 31 0 RW AR 31 0 lt 0x0000_00C0 for Configuration Smart Option AR 31 0 lt 0 0000 00 4 for Protection Smart Option Sector 8 KB Unit 0x2000 Page 256B Unit 0x100 NOTE The AR register is auto cleared when command operation is completed SAMSUNG ELECTRONICS 9 38 ex
164. 9 18 17 16 5 14 13 12 11 10987 6 5 4 3 COMP1EDGESEL COMPOEDGESEL gt __ gt compen COMP2EDGESEL COMPS3EDGESEL cows corens coman conpownser comense gt _ compoen e eae 2008 BEBE L Wm 31 29 Reserved 23 21 Comparator x Edge Detection Enable 15 13 00 Selects falling edge 7 5 01 Selects rising edge 10 Selects falling rising edge COMPOEDGESEL 4 3 11 effect E m COMPS3NINSEL E E COMP2NINSEL En 2 i Selects external pin x N 1 Selects OP AMP 0 output COMPONINSEL EN EN a zaj COMP3EDGESEL 28 27 COMP2EDGESEL 20 19 COMP3PINSEL COMP2PINSEL COMP1PINSEL COMPOPINSEL COMP3EN COMP2EN COMP1EN COMPOEN Comparator x Positive Input Selection Bit 0 Selects external pin COMPx_P 1 Selects internal reference Comparator x Enable Bit 0 Disables Comparator x 1 Enables Comparator x NOTE Value of x from 0 to 3 represents channel of a comparator For example COMPx_P have channels represented as COMP1_P COMP2_P and SAMSUNG ELECTRONICS 6 9 ex S3FN429_UM_REV1 20 6 Comparator 6 3 1 5 COMP_CR1 e B
165. 9 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 PULSE 15 0 Indicates current PULSE value D n o lt SAMSUNG ELECTRONICS 16 41 S3FN429_UM_REV1 20 16 Timer Counter 16 3 1 20 TC_CUCR e Base Address 0 4006 0000 4006 1000 0 4006 2000 e Address Base Address 0x004C Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 1 0 R Ree COUNT 15 0 Indicates the counter value captured when the last rising edge is detected Caution The TC supports the capture function only when the clock source is PCLK SAMSUNG ELECTRONICS 16 42 ex S3FN429_UM_REV1 20 16 Timer Counter 16 3 1 21 TC_CDCR e Base Address 0 4006 0000 0x4006_1000 0 4006 2000 e Address Base Address 0x0050 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 31 16 Reserved 91 36 COUNT 15 0 Indicates the counter value captured when the last falling edge is detected Caution The TC supports the capture function only when the clock source is PCLK SAMSUNG ELECTRONICS 16 43 ex S3FN429_UM_REV1 20 16 Timer Counter 16 3 1 22 TC_CVR e Base Address 0x4006 0000 0x4006 1000 0 4006 2000 e Address Base Address 0x0054 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
166. 9 28 27 26 25 24123 22 21 20 19 18 17 16 15 14 13 12 11 10 a gt A e PCHDAT zae RIR R R R R R R R R RSVD n 109 Position Counter Hold Data PCHDAT 15 0 RW This field contains the position counter value which will be 0x0000 copied by holding the event trigger SAMSUNG ELECTRONICS 7 32 ex S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 3 1 20 PPD_PCTHR e Base Address 0x400C_0000 e Address Base Address 0x004C Reset Value 0x0000_0000 31 30 29 28 27 26 25 24123 22 21 20 19 18 17 16 15 14 13 12 11 10 o a gt A e PCTVHDAT zae RIR R R R R R R R R RSVD Position Capture Timer Hold Data PCTVHDAT 15 0 RW This field contains the position capture timer value which 0x0000 will be copied by holding the event trigger SAMSUNG ELECTRONICS 7 33 ex S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 3 1 21 PPD_PCTVHR e Base Address 0x400C_0000 e Address Base Address 0x0050 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 PCTVDAT saj zaj Positi Ti Value Hold D PCVTVDAT 15 0 osition Capture Timer
167. 9_UM_REV1 20 15 Serial Peripheral Interface SPI 15 2 2 1 4 Interrupt There are five interrupts generated by the PrimeCell SSP Four of these are individual maskable active HIGH interrupts e SSPRXINTR PrimeCell SSP Receive FIFO service interrupt request SSPTXINTR PrimeCell SSP Transmit FIFO service interrupt request SSPRORINTR PrimeCell SSP receive overrun interrupt request e SSPRTINTR PrimeCell SSP time out interrupt request The four individual maskable interrupts by setting the appropriate bits in the SSPIMSC register Setting the appropriate mask bit HIGH enables the interrupt Provision of the individual outputs as well as a combined interrupt output allows use of either a global interrupt service routine or a modular device drivers to handle interrupts The transmit and receive dynamic data flow interrupts SSPTXINTR and SSPRXINTR have been separated from the status interrupts so that data can be read or written in response to just the FIFO trigger levels The status of the individual interrupt sources can be read from SSPRIS and SSPMIS registers e SSPRXINTR The receive interrupt is asserted when there are four or more valid entries in the Receive FIFO e SSPTXINTR The transmit interrupt is asserted when there are four or less valid entries in the Transmit FIFO The transmit interrupt SSPTXINTR is not qualified with the PrimeCell SSP enable signal which allows operation in one of two ways Data can be writt
168. ABLE bit in register to be clear Change SYSCLK 1 0 field in MR1 register Read CM STABLE bin in CM RISR register to check the change is completed or not Write 1 to CM STABEL bit in CM ICR register to be clear When you use the interrupt method the sequence for SYSCLK change is the followings Check the destination clock to change is stabled or not PLL IMCLK or EMCLK status bits in SR register If STABLE bit in MISR register is 1 write 1 to STABLE bit in CM ICR register to be clear Register the interrupt handler and enable STABLE interrupt Change SYSCLK 1 0 field in MR1 register The STABLE interrupt will occur when the change is completed Check STABLE bin in CM MISR register in ISR Interrupt Service Routine Write 1 to STABEL bit in CM ICR register to be clear in ISR 5 3 3 WDTCLK Source Change e The sequence for WDTCLK change is the followings Check the destination clock to change is enabled and stabled or not If target clock is disabled enable that PLL IMCLK or EMCLK status bits in SR register Change WDTCLK 1 0 field in CM_MR1 register Read WDTCLKS bin in CM SR register to check the change is completed or not The time for switching is 3 x current source clock 4 x next destination clock SAMSUNG ELECTRONICS 5 16 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 4 Power Management There are four operation modes Two modes among them are the low power mode One i
169. AMSUNG ELECTRONICS 6 5 ex S3FN429_UM_REV1 20 6 Comparator 6 3 1 1 COMP_IDR e Base Address 0 4004 2000 e Address Base Address 0x0000 Reset Value 0x0001 0038 ID Code Register 0x00010038 This field stores ID code for the corresponding IP SAMSUNG ELECTRONICS T 27 S3FN429_UM_REV1 20 6 Comparator 6 3 1 2 COMP_CEDR e Base Address 0 4004 2000 e Address Base Address 0x0004 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Debug Mode Enable Disable Control Bit 0 Disables debug mode In debug mode Timer Counter 21 TC is not halted No influence the function 1 Enables debug mode revo a Clock Enable Disable Control Bit CLKEN RW 0 Disables Counter Clock 1 Enables Counter Clock SAMSUNG ELECTRONICS T 27 S3FN429_UM_REV1 20 6 Comparator 6 3 1 3 COMP_SRR e Base Address 0 4004 2000 e Address Base Address 0x0008 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 ert Software Reset W 0 Noeffect 1 Resets Software Comparator IP Block SAMSUNG ELECTRONICS 6 8 ex S3FN429_UM_REV1 20 6 Comparator 6 3 1 4 COMP_CRO e Base Address 0 4004 2000 e Address Base Address 0x000C Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 1
170. ART bit again the counter value will be increased continuously from the last value it has kept SAMSUNG ELECTRONICS 16 6 ex S3FN429_UM_REV1 20 16 Timer Counter 16 2 6 2 Capture Operation The TC can perform the capturing operation wherein the counter value is transferred into the capture registers namely the TC_CUCR Capture Up Counter Register and TC_CDCR Capture Down Counter Register in synchronization with an external trigger signal After the completing the capture operation you can determine the time difference between the external events The external triggering signal for the capturing operation is a pre defined valid edge on the capture input pin TCAP If CAPT_F bit is set in TC_SR register then the counter value in process is copied into TC_CDCR register when a falling edge signal is detected on TCAP pin If CAPT_R bit is set in TC_SR register then the counter value in process is copied into TC_CUCR register when a rising edge signal is detected on TCAP pin You should keep the external trigger signal on TCAP pin at least three times longer than PCLK to distinguish from glitch signals When either CAPT_R or CAPT_F is set the capture function always operates regardless of whether the timer is running or not Figure 16 4 illustrates the capture operation timing Condition TC_SR CAPT_R 1 Condition TC_SR CAPT_F 1 TCAP i 3x PCLK 3 gt Tecucr count CCT TC_CDCR COUNT X TC RI
171. ART signals only a parity error by setting the PARE bit in the US SR register Figure 17 9 illustrates the error signaling on reception diagram SCTX 5 8 Bit Data PAR STO STA 8 Bit Data re transmitted 10 10 625 0 0 0625 bits 1 0625 bits USARTT TX Error signal generated by the USART STA 8 Bit Data PAR STA 8 Bit Data re transmitted 1 e 1 5 Figure 17 9 Error Signaling on Reception If a DMA transfer is used to receive data byte from the smart card then the DMA counter will be decremented and the DMA memory pointer will be incremented even when a parity error is detected You should reconfigure the DMA memory pointer decrement by 1 and counter increment by 1 to receive all the remaining bytes 17 6 8 USART Configuration in Smart Card Mode The USART should be set in normal mode and the number of stop bits should be programmed at two to work in smart card mode Refer to the MODE register for more information SAMSUNG ELECTRONICS 17 20 ex S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 7 Programming Examples Interruption Handling e SR Interrupt Service Routine Entry and call C function e Read the US MISR register and verify the source of the interrupt e Clear the corresponding interrupt at peripheral level by writing in the US_ICR register e Interrupt treatment informs the background software that header or message is
172. Base Address 0x0004 Reset Value 0x0000 0010 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 RXIFLSEL S3FN429_UM_REV1 20 15 Serial Peripheral Interface SPI ojoofojojo olojo e ojo o o o o ojo e o o o o o o jo o vfo o o c evr ___ Receive Interrupt FIFO Level Selection Field 001 Trigger points Receive FIFO becomes gt 1 8 010 Trigger points Receive FIFO becomes gt 1 4 100 Trigger points Receive FIFO becomes gt 1 2 Others Reserved RXIFLSEL Slave mode Output Disable Bit 0 SSP can drive the SSPTXD output in slave mode 1 SSP should not drive the SSPTXD output in slave mode Master or Slave Mode Selection Bit RW 0 Configures device as master 1 Configures device as slave Synchronous Serial Port Enable Bit 0 Disables SSP operation 1 Enables SSP operation Loop Back Mode Bit 0 Enables normal serial port operation 1 Output of transmit serial shifter is connected to input of receive serial shifter internally NOTE SOD bit is relevant only in the slave mode MS 1 In multiple slave systems it is possible for a PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line In such systems the RXD lines from multiple slaves could be tied together To operate in such systems the SOD bit can be set if
173. CCOVF 13 Speed Capture Timer Overflow Interrupt Mask 0 Mask the interrupt disables the interrupt 1 Unmask the interrupt enables the interrupt Speed Capture Interrupt Mask EM SCTOVF 12 11 0 Mask the interrupt disables the interrupt 1 Unmask the interrupt enables the interrupt Speed Counter Sign Underflow Interrupt Mask 0 Mask the interrupt disables the interrupt 1 2 Unmask the interrupt enables the interrupt SCSUNF 10 Speed Counter Sign Overflow Interrupt Mask 0 Mask the interrupt disables the interrupt 1 2 Unmask the interrupt enables the interrupt SCSOVF Speed Counter Match Interrupt Mask 0 Mask the interrupt disables the interrupt 1 Unmask the interrupt enables the interrupt Reserved SAMSUNG ELECTRONICS 7 16 S3FN429_UM_REV1 20 7 Pulse Position Decoder Position Counter Carry Underflow Interrupt Mask 0 Mask the interrupt disables the interrupt 1 Unmask the interrupt enables the interrupt Position Counter Carry Overflow Interrupt Mask PCCOVF 0 Mask the interrupt disables the interrupt 1 Unmask the interrupt enables the interrupt Position Capture Timer Overflow Interrupt Mask PCTOVF 0 Mask the interrupt disables the interrupt 1 Unmask the interrupt enables the interrupt Position Counter Sign Underflow Interrupt Mask PCSUNF 2 0 Mask the interrupt disables the interrupt 1 Unmask the interrupt enables the interrup
174. CFRO IMC_ASCFR1 IMC_ASCFR2 SAMSUNG ELECTRONICS 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 10 25 S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 3 1 1 IMC_IDR e Base Address 0 400 0000 Address Base Address 0 0000 Reset Value 0 0001 0012 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 ASV n IDCODE 25 0 ID Code Register E 0 0001_0012 This field stores the ID code for the corresponding x SAMSUNG ELECTRONICS 10 26 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 3 1 2 IMC_CEDR Base Address 0 400 0000 Address Base Address 0x0004 Reset Value 0 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 R Debug Enable Bit DBGEN 31 RW 0 is not halted during the processor debug mode 1 IMC is halted during the processor debug mode mw eon Clock Enable Disable Control Bit CLKEN RW 0 Disables IMC Clock 1 Enables IMC Clock SAMSUNG ELECTRONICS 10 27 ex S3FN429_
175. CH 1 RW 1 Glitch occurs Write 0 Clears glitch bit 1 No effect NOTE Detects the Glitch bit after verifying whether five times in a row in the same level recognizes as effective signal Direction of Motor Rotation Bit 0 Clockwise Increases the value of PCNT 1 Counter clockwise Decreases the value of PCNT NOTE This bit is a read only bit DIRECTION 0 SAMSUNG ELECTRONICS 7 15 ex S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 3 1 7 PPD_IMSCR e Base Address 0x400C_0000 e Address Base Address 0x0018 Reset Value 0x0000 0000 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 e N o lt I o n R R 151 gt gt sosur scsove gt sw EN gt gt reor gt gt gt gt __ zaj PHASEZ Interrupt Mask 0 Mask the interrupt disables the interrupt 1 Unmask the interrupt enables the interrupt Reserved 31 17 PHASEZ 16 RSVD 15 Speed Counter Carry Underflow Interrupt Mask 0 Mask the interrupt disables the interrupt 1 Unmask the interrupt enables the interrupt SCCUNF 14 Speed Counter Carry Overflow Interrupt Mask 0 Mask the interrupt disables the interrupt 1 Unmask the interrupt enables the interrupt S
176. CLKEN 10 RW 0 Disables 1 Enables RXEV Receive Event Enable Disable Control Bit 0 Disables RXEV 1 Enables RXEV RXEV Rw This bit causes the Event register defined processor Cortex MO to be set This causes WFE instruction to complete It also awakens the processor if it is in sleep mode by the result of encountering a WFE instruction when the Event Register is clear vo mR Reseed LVD Interrupt Enable Disable Control Bit 0 Disables LVD Interrupt 1 Enables LVD Interrupt LVDINTEN 7 RW LVD detects the configured voltage level At this time interrupt may or may not occur with LVDINTEN value LVD detects the target voltage and LVDIL 2 0 field decides the target voltage LVDIL 6 4 LVD Interrupt Threshold Level refer to the Electrical Data SAMSUNG ELECTRONICS 5 46 S3FN429_UM_REV1 20 5 Clock and Power Manager LVDRL 2 0 SAMSUNG ELECTRONICS chapter 000 LVD LEVELS Typical 2 4 V 001 LVD LEVELA Typical 2 6 V 010 LVD LEVEL3 Typical 2 8 V 011 LVD_LEVEL2 Typical 3 8 V 100 2LVD LEVEL1 Typical 4 3 V Others You should not set other values NOTE If the LVDRL and LVDIL field have the same value and LVD detects the voltage then LVD Reset occurs Before LVD detects the voltage LVRSTEN bit should be set to 1 If LVDIL 2 0 and LVDRI 2 0 have the same value LVD reset occurs when LVD detects the configured level LVD Reset Enable Disable Control Bit 0 Disa
177. CTRONICS 8 9 ex S3FN429_UM_REV1 20 8 General Purpose I O GPIO 8 3 1 5 GPIO_RISR e Base Address 0x4005 0000 e Address Base Address 0x0010 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 Port y Raw Interrupt State Py y Gives the raw interrupt state prior to masking of the Py interrupt NOTE Ona Read GPIO_RISR register gives the current raw status value of the corresponding interrupt prior to masking SAMSUNG ELECTRONICS 8 10 ex S3FN429_UM_REV1 20 8 General Purpose I O GPIO 8 3 1 6 GPIO_MISR e Base Address 0x4005 0000 Address Base Address 0x0014 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 Port y Masked Interrupt State Py y Gives the masked interrupt status after masking of the Py interrupt NOTE Ona Read GPIO_MISR register gives the current masked status value of the corresponding interrupt A Write has no effect SAMSUNG ELECTRONICS 8 11 ex S3FN429_UM_REV1 20 8 General Purpose I O GPIO 8 3 1 7 GPIO_ICR e Base Address 0x4005 0000 e Address Base Address 0x0018 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 29 28 27 26 25 24 23 22 21 20 19 18 17 16 22 21 20 19 18 17 15 14 13 12 11 10 11 Port Interrupt Clear Py W 0 Noeffect 1 Clears Py interrupt NOTE On a Write of 1 the corresponding
178. Clear 0 Stop Clear mode is disabled STOPCLEAR 3 1 Stop Clear MAAG 8 enabled If you clear START bit when STOPCLEAR is set then the counter stops and clears to zero In this state IDLESL determines the output signal level Stop Count Hold 0 Stop Hold mode is disabled STOPHOLD 2 1 Stop Hold mode is enabled If you clear START bit when STOPHOLD is set and STOPCLEAR is clear then the counter stops but keeps SAMSUNG ELECTRONICS 16 28 ex PWM Enable PWMEN 12 0 The signal output is disabled 1 The signal output is enabled S3FN429_UM_REV1 20 16 Timer Counter the current counter value and the output signal level Later the counter resumes when START is set again Reserved Start Stop the TC 0 The counter is stopped 1 The counter is started SAMSUNG ELECTRONICS 16 29 ex S3FN429_UM_REV1 20 16 Timer Counter 16 3 1 8 TC_IMSCR e Base Address 0 4006 0000 4006 1000 0 4006 2000 e Address Base Address 0x001C Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 81 7 on 1 lt lt __ 1 xp saff so Capture Interrupt Mask 0 Mask the interrupt Disables this interrupt 1 Unmask the interrupt Enables this interrupt Overflow Interrupt Mask 0 Mask the interrupt Disables this interrupt 1 Unmask the interrupt Enables this interrupt Pulse Match Interrupt Mask 0 M
179. Control Register CR 5 Check whether the operation of normal program is completed or not You can use one ways between polling and interrupt check If you monitor the status bit of END check END bit in Raw Interrupt Status Register RISR 9 2 3 1 6 Smart Option Erase Operation You can change the Smart Option You have to program the Smart Option with new option value To change the smart option value Configuration Smart Option or Protection Smart Option you should clear the smart option area before program Smart Option Erase erases and clears both Configuration Smart Option and Protection Smart Option So you need to store the smart option value not to be changed and program again To perform the smart option erase the steps are 1 Write the value Ox5A5A5A5A into the IFC KEY register 2 Write the smart option erase command and start control bit to Control Register CR 3 Check whether the operation of smart option erase is completed or not You can use one ways between polling and interrupt check If you monitor the status bit of END check END bit in Raw Interrupt Status Register RISR SAMSUNG ELECTRONICS 9 12 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 2 3 1 7 Smart Option Program Operation All smart option is cleared by smart option erase If both Configuration Smart option and Protection Smart Option don t have the initial value as the new value you should do
180. DUTY The duty means the ratio between PERIOD and PULSE e DUTY PULSE 15 0 PERIOD 1 5 0 PERIOD should not be 0 When PULSE 15 0 is 0 the duty is 0 percent If PULSE 15 0 is greater than PERIOD 15 0 then the duty is 100 percent This PWM supports 0 percent and 100 percent duty Table 14 2 describes the PERIOD and PULSE field relationship in normal mode Table 14 2 PERIOD and PULSE Field Relationship in Normal Mode Duty Ratio Configuration Normal Mode gt n 96 e PERIOD X 0x1 Normal PWM Wave e PULSE Value Y 0x1 OXFFFF lt 100 e PERIOD 0x1 OxFFFF OUTPUTL bit value Level e PULSE Value 5 0x1 NOTE Incase of an interval mode if the value of PERIOD is not zero regardless of PULSE value PWM output will toggle with every PERIOD In PWM operation if the PERIOD 15 0 value is 0 it is invalid SAMSUNG ELECTRONICS 14 5 ex S3FN429_UM_REV1 20 14 Pulse Width Modulation Table 14 3 describes the PWM output Table 14 3 PWM Output Figure 14 3 illustrates the PWM basic waveform OUTSL 1 diagram OUTSL 1 High 0 0 PERIOD 15 0 0x40 PULSE 15 0 0x0 PULSE 15 0 0 1 PULSE 15 0 0x20 PULSE 15 0 0x3F PULSE 15 0 0x40 Figure 14 3 PWM Basic Waveform OUTSL 1 PWM Period 0x40 Pulse 0 0 0x1 0x20 0x40 SAMSUNG ELECTRONICS 14 6 S3FN429_UM_REV1 20 14 Pulse Width Modulation Figu
181. END END interrupt When operation defined by CMD 2 0 is finished then END bit is set to 1 a command field in control register NOTE On a Read the IFC_RISR register gives the current raw status value of the corresponding interrupt prior to masking ERR Interrupt Raw Status Gives the raw interrupt state prior to masking of the ERRn Caution When ERRn occurs in operation to continue flash operation after clear ERRn bit is recommended You can clear ERRn interrupt status by ICR register SAMSUNG ELECTRONICS 9 34 227 S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 3 1 8 IFC_MISR e Base Address 0x4001_0000 e Address Base Address 0x001C Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 1 0 ERR Interrupt Status Error2 Writes or erases to protected memory region 0 Interrupt does not occur 1 Interrupt occurs ERR Interrupt Status Error1 Writes undefined value CMD 2 0 111b into CMD field of a control register during operation flow 0 Interrupt does not occur 1 Interrupt occurs ERR Interrupt Status ErrorO Try to execute other operation program erase while executing normal program command operation 0 Interrupt does not occur 1 Interrupt occurs END Interrupt Status Gives the masked interrupt status after masking of the END interrupt 0 Interrupt does not occur 1 Interrupt occurs NOTE On
182. ESETREQ bit in Application Interrupt and Reset Control Register of Cortex MO After system reset SYSRSTS bit in CM SR register sets to 1 The user software or other resets hardware can clear this bit SAMSUNG ELECTRONICS 5 29 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 7 Basic Timer The Basic Timer BT is a release timer at reset or the Wake Up from the STOP mode It blocks the clock supply to system and controls the reset STOP release time for the predefined time While the power and clock supply becomes unstable as soon as you power on the processor or the oscillator starts to run The reference clock for timer is the SYSCLK Smart option defines the SYSCLK The smart option generates the source clock for the BT with clock divider The BT counts with a different clock divider Smart option defines the reset value of the clock divider After a reset you can control the divider value by changing the BTCDIV 3 0 field in the CM_BTCDR register For instance to shorten the Wake Up latency in the exit of the STOP mode the software can configure the number of BT divider or count value before the entry of STOP mode The reset count value of the BT is 0x100 In other words when the 8th bit on the BT is sets to 1 it releases System reset or Wake Up signals When the BT count value is 256 and each divider value splits from 1 to 4096 then the frequency of the BT input clock splits into 1 MHz 4 MHz 8 MHz 16 MHz 20 MHz an
183. ET1 Gives the raw interrupt state prior to masking of EDGEDET1 interrupt Edge Detection Raw Interrupt Status EDGEDETO Gives the raw interrupt state prior to masking of EDGEDETO interrupt NOTE On a Read the COMP_RISR register gives the current raw status value of the corresponding interrupt prior to masking A Write has no effect SAMSUNG ELECTRONICS 6 16 ex S3FN429_UM_REV1 20 6 Comparator 6 3 1 10 COMP_MISR e Base Address 0 4004 2000 Address Base Address 0x0024 Reset Value 0x0000 000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 gt gt ___ gt gt ___ gt ecever e EbGEDETo Edge Detection Masked Interrupt State EDGEDETS Provides masked interrupt status of EDGEDET3 interrupt Edge Detection Masked Interrupt State EDGEDET1 Provides masked interrupt status of EDGEDET1 interrupt Edge Detection Masked Interrupt State EDGEDETO Provides masked interrupt status of EDGEDETO interrupt NOTE On a Read the MISR register gives the current masked status value of the corresponding interrupt A Write has no effect Edge Detection Masked Interrupt State EDGEDET2 Provides masked interrupt status of EDGEDET2 interrupt SAMSUNG ELECTRONICS 17 x S3FN429_UM_REV1 20 6 Comparator 6 3 1 11 COMP_ICR e Base Address 0 4004 2000 e Address Base Address 0x0028 Reset Value 0x0000 0000 31 30
184. EV1 20 9 Internal Flash Controller IFC 9 2 5 2 Error Case 1 This error occurs when writing the undefined value CMD 2 0 111 b into CMD field of a control register during operation sequence Figure 9 12 illustrates the Error Case 1 Stay status before START and Error occurs by undefined flash program erase command A Write data K or Erase A sector CODEO START by undefined command P N CODEO START by undefined command Figure 9 12 Condition SAMSUNG ELECTRONICS 9 24 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 2 5 3 Error Case 2 If the operation is not allowed because of protection while executing normal program operation that operation is executed and an abort signal is generated on the internal bus along with an interrupt error Figure 9 13 illustrates the Error Case 2 Stay memory data before START and Error occurs by access protected area SRAM CODEO Protected Area START program or erase Program Fash BE FLASH CODE 0 START program or erase Figure 9 13 Error2 Condition SAMSUNG ELECTRONICS 9 25 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 3 Register Description 9 3 1 Register Map Summary e Base Address 0x4001_0000 Regser Reservaue SO PSR 0x0034 Smart option protection status register ui dg SO CSR 0x0038 Smart option configuration status register IFC_IOTR 0x003C Internal OSC trimmin
185. Figure 16 13 Figure 17 1 Figure 17 2 Figure 17 3 Figure 17 4 Figure 17 5 Figure 17 6 Figure 17 7 SAMSUNG ELECTRONICS Synchronous Write at IMC_TCR Match SYNCSEL 10 b NUMSKIP 00001 5 10 36 Skip Control of ADC Trigger Signal 10 37 Interrupt Block Diagram eerie detiene ostia ep ME 11 4 edu 13 2 Pulse Width Modulation PWM Block Diagram nemen 14 2 PWM m 14 3 PWM Basic Waveform OUTSL 1 PWM Period 0x40 Pulse 0x0 0x1 0x20 0x40 14 6 PWM Basic Waveform OUTSL 0 PWM Period 0x40 Pulse 0x0 0x1 0x20 Ox3F 0x40 14 7 Extended PWM Waveform PWM Period 0x40 Pulse PWMEXO 14 9 Extended PWM Waveform PWM Period 0x40 Pulse 1 14 10 Extended PWM Waveform PWM Period 0x40 Pulse PWMEX1 and PWMEXO 14 11 Extended PWM Waveform High Start esee 14 12 Extended PWM Waveform Low Start enne 14 12 SSP Block Lo e in 15 3 Motorola SPI Frame Format Single Transfer with SPO 0 and SPH 0 15 10 Motorola SPI Frame Format Continuous Transfer with SPO 0 and SPH 0 15 11 Motorola SPI Frame Format with SPO 0 SPH 1
186. Figure 7 3 illustrates the counter operation for 1 Multiplication mode PHASEA ENCSTATUSO DIRECTION 0 1 Figure 7 3 Counter Operation 1 Multiplication Mode Direction of Rotation When the DIRECTION bit is 0 the counter value of PCR increases and when the DIRECTION bit is 1 the counter value of PCR decreases PCR is an up down counter The leading phase signal between PHASEA and PHASEB decides the DIRECTION bit status and counting direction NOTE Although the PBEN and PAEN bit are 0 disable if inserted any signal into PHASE A or PHASE B input port and A0 A1 or BO B1 interrupt are unmask those interrupts occur SAMSUNG ELECTRONICS 7 4 en S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 2 2 2 Type 1 If the input pulse is applied into PHASEA the PCR increases up counting If the input pulse is applied into PHASEB the PCR decreases down counting Figure 7 4 illustrates the counter operation for Type 1 Direction SR CNT Figure 7 4 Counter Operation Type 1 7 2 2 3 Type 2 If the high input is applied into PHASEA the PCR increases up counting If the low input is applied into PHASEB the PCR decreases according to direction signal down counting Figure 7 5 illustrates the counter operation for Type 2 Type 2 A Drection Z Pulse Direction SR Figure 7 5 Counter Operation Type 2 SAMSUNG ELECTRONICS 7 5 ex S3F
187. Hz LFPASS RW 1 2Fwisless than 4 MHz Fin lt 4 MHz The pre divider value P 5 0 does not effect to output frequency for PLL PLLPRE 13 8 PLLMUL 7 0 PLL Post Scaler Value NOTE S 1 0 0x0 to 0x3 0 to 3 1 If you disable the PLL then the register will have the Write access If you enable the PLL then the register will have Read Reserved access PLL Pre Divider Value P 5 0 0x01 to Ox3F 1 to 63 PLL Multiplier Value M 7 0 0x10 to OxFF 16 to 255 The FIN is input frequency of the PLL and becomes the EMCLK m M 7 0 p P 5 0 s S 1 0 At the LFPASS 0 FOUT m 8 x FIN p 2 x 25 At the LFPASS 1 FOUT m 8 x FIN 2 18 Bit is reserved That has no effect regardless of the value O or 1 PLLKEY 31 24 W Or m Four PLL output frequency Fin PLL input frequency EMCLK SAMSUNG ELECTRONICS 5 63 ex S3FN429_UM_REV1 20 5 Clock and Power Manager Table 5 13 PMS Value Table e w S e S ias 9 2 4 __ 2 o 2 1 6 1 P m S P S Pss AR gt NININI AJOJN __ 2 2 __ _ __2 2 gt __ 2 __ 2
188. Interface SPI Serial Peripheral Interface SPI 15 1 Overview The PrimeCell Synchronous Serial Port SSP PL022 is used for Serial Peripheral Interface Serial communication is the process of sequentially sending data one bit at a time About the ARM PrimeCell SSP PL022 The PrimeCell Synchronous Serial Port SSP is an Advanced Microcontroller Bus Architecture AMBA slave block that connects to the Advanced Peripheral Bus APB The PrimeCell SSP is an AMBA compliant System on Chip SoC peripheral That is developed tested and is licensed by ARM 15 1 1 Features This section describes the features of SPI The PrimeCell SSP is a master or slave interface that enables synchronous serial communication with slave or master peripherals having e Motorola SPI compatible interface In both the master and slave configurations the PrimeCell SSP performs A parallel to serial conversion on the data written to an internal 16 bit wide and 8 location deep transmit First In First Out FIFO Aserial to parallel conversion on the received data buffering it in a similar 16 bit wide and 8 location deep receive FIFO Interrupts are generated to e Request servicing for transmit and receive FIFO e Inform the system that a receive FIFO over run has occurred e Inform the system that the data is present in the receive FIFO after an idle period has expired SAMSUNG ELECTRONICS 15 1 ex S3FN429_UM_REV1 20 15 Serial Peri
189. K frequency a A resen WDT Clock Divider Field This field determines the clock frequency of Watchdog Timer m t o o we NOTE FIN is an input clock asserted into Watchdog Timer supplied by clock manager SAMSUNG ELECTRONICS 18 8 en S3FN429_UM_REV1 20 18 Watchdog Timer 18 3 1 4 WDT_OMR e Base Address 0 4003 0000 e Address Base Address 0x000C Reset Value 0x0000 0003 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 14 13 12 11 10 987 6 5 4 3 0 N RSVD R Overflow Access Key Field Used only when writing OMR OKEY is read as 0 OKEY 15 4 W 0x234 Allows Write access Other values Does not allow Write access in WDT OMR 78 8 Resend RSVD Lockrsten gt mw wmn System Chip Reset Enable Disable Control Bit 0 Disables the generation of a system chip reset by RSTEN 1 RW the Watchdog 1 Watchdog generates the system chip reset on overflow Watchdog Enable Disable Control Bit WDTEN RW 0 Disables Watchdog Timer 1 Enables Watchdog Timer CPU Lock up Reset Enable Disable Control Bit 0 Disables the generation of an internal reset on CPU Lock up LOCKRSTEN 2 RW 1 Enables the generation of an internal reset on CPU L
190. LECTRONICS Table of Contents TPRODUCT OVERVIEW 1 1 AST WPM CU CUO MN 1 1 RC ALU S 1 2 1 3 EE 1 9 2 PIN CONFIGURATION CES Ec 2 1 OVGIVIOW mE dentin eet dinates det cari nd slag ei dames dente 2 1 2 2 duci p E 2 2 23 ede ei ede Gee Wl een eee 2 3 mega 2 5 2 5 Pin DESCriPtlONs Em 2 6 251 Power 2 6 252 System TM 2 7 2 5 3 Function PINS E tdi 2 9 2 5 4 Debug Interface Pins eite eee dre tee pec 2 10 2 5 5 Flash Program Pins oii riter i erred Rate uite ee ea coved nera na p 2 10 2 6 Pin Circuit Type ie de en au en v da ced dd ee 2 11 2 641 Block 2 11 3 SYSTEM MEMORY 2 2 1 3 1 31 OVORVIOW 3 1 3 2 Default Memory Map m 3 1 3 3 Special Function Register 1 sse en nennen entrer nsns inneren ns 3 2 3 3 1 Core Special Function Register
191. LECTRONICS 5 56 S3FN429_UM_REV1 20 5 Clock and Power Manager NRSTS For LVD reset condition you should enable the LVDRST bit in CM_MR register 0 LVD reset is not occurred 1 LVD reset is occurred To clear this bit write to 1 _ nRESET Status NRST is System Chip Reset by external reset pin This bit instructs the reset source that generates reset 25 signal pin 0 External pin reset is not occurred 1 External pin reset AnRESET is occurred To clear this bit write to 1 Software Reset Status System Chip reset from the software reset SWRST in CM SRR register SWRSTS 24 0 Software reset is not occurred 1 The last reset is caused by software reset When nReset POR reset or LVR reset occur it clears this bit by hardware To clear by software writes this bit to 1 External Main Clock Monitor Fail Function Enable Disable Status EMEM 158 0 Disables 1 Enables External Main Clock Monitor Reset Function Enable Disable Status EMCMRST 22 22 0 Disables reset function by clock fail mode 1 Enables reset function by clock fail mode RSVD 21 19 18 0 Does not occur CMDERR event 1 Occurs CMDERR event LVD Reset Level Detect Status Same as LVDRS in CM RISR register aii UA 0 Does not detect LVD Reset voltage level 1 Detects LVD Reset voltage level LVD Interrupt Status LVDINT 16 0 Does not detect LVD Interrupt voltage level 1 Detects LVD In
192. LLCLK BTCDIV decides the clock frequency of BT count with the clock source At reset time smart option value decides SYSCLK and BT clock divider In wake up time the condition before entering the stop mode decides SYSCLK and BTCDIV value in CM_BTCDR register decide BT clock divider When 8 bit of BT Timer is set to 1 it releases system reset or Wake Up signal BTCDIV 3 0 Divider Ratio BTCDIV 3 0 Divider Ratio z s ert T 1101 0110 8 3 1 4 2 SAMSUNG ELECTRONICS 5 65 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 1 20 CM_BTR e Base Address 0 4002 0000 e Address Base Address 0x0074 Reset Value 0x0000 0100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 RIR R RIR R R RIRIR R R R R R R Basic Timer Count Value 0x0100 SAMSUNG ELECTRONICS 5 66 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 1 21 CM_EECRO e Base Address 0 4002 0000 e Address Base Address 0x0078 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 EESRC3 R R R R R R R R R R R R Ww WIW W WINIWIWIW W W W W External Event Enable Disable Control Bit 0 Disables the target external event source 1 Enable the target external event source X means each number from
193. MC package do not expose semiconductor IC to bright light Exposure to bright light causes malfunctioning of the devices However a few special products that utilize light or with security functions are exempted from this guide Radioactive Cosmic and X ray Radioactive substances cosmic ray or X ray may influence semiconductor devices These substances or rays may cause a soft error during a device operation Therefore ensure to shield the semiconductor devices under environment that may be exposed to radioactive substances cosmic ray or X ray EMS Electromagnetic Susceptibility Strong electromagnetic wave or magnetic field may affect the characteristic of semiconductor devices during the operation under insufficient PCB circuit design for Electromagnetic Susceptibility EMS SAMSUNG ELECTRONICS 227 Revision History Revision No Date Description Author s 1 00 Jan 17 2012 e Promoted from preliminary to V1 0 and released YH Jin e Added guide notes caution related to the pin XIN and XOUT connection for unused external oscillator 1 10 Feb 22 2012 e Page 2 7 5 8 5 21 5 41 5 59 and 19 7 MCU solution e Corrected the errata part e The offset address of PPD_SCTVHR register in page 7 37 was fixed from 0 006 to 0 005 e Added guide notes related to the pin OPAMP output MCU solution 1 20 May 16 2012 pin configuration when OPAMP is enabled 12 5 13 8 SAMSUNG E
194. MCLK interrupt 0 Each interrupt does not occur 1 Each interrupt occurs NOTE Ona Read CM_MISR register gives the current masked status value of the corresponding interrupt A Write has no effect SAMSUNG ELECTRONICS 5 54 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 1 13 CM_ICR e Base Address 0 4002 0000 Address Base Address 0x003C Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 e N k o EMCKFAIL END RSVD gt ___ s e RSVD 31 RSVD 13 8 RSVD STABLE RSVD 1 Clears the CMDERR interrupt 1 Clears the LVDRS flag 1 Clears the LVDINT Interrupt 1 Clears the EMCKFAIL interrupt 1 Clears the EMCKFAIL_END interrupt 4 Reserved PLL Stable Interrupt Clears the PLL stable interrupt Reserved 1 Clears the Switching stable interrupt 1 Clears the IMCLK stable interrupt External Main Clock Stable Interrupt NOTE On a Write of 1 it clears the corresponding interrupt the RISR register A Write of 0 has no effect 7 4 4 5 2 6 3 9 SAMSUNG ELECTRONICS 5 55 S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 1 14 CM_SR e Base Address 0x4002 0000 e Address Base Address 0x0040 Reset Value 0 8
195. MEXG5 is only set then the 32 periods in every 64 periods are Extension Periods and the duty would be 50 5 percent SAMSUNG ELECTRONICS 16 12 27 S3FN429_UM_REV1 20 16 Timer Counter 16 2 7 2 2 PWM Waveform Figure 16 9 and Figure 16 10 illustrates PWM waveforms according to the relationship between PERIOD and PULSE in the PWM operation In Normal Period when PULSE is 0 the duty is 0 percent and when PULSE is equal to PERIOD the duty is 100 percent The OUTSL bit in TC_SR register determines the output level on TPWM pin when the timer is running The TPWM signal starts from LOW when OUTSL bit is clear Conditions SR OVFM 0 REPEAT 1 PWMEN 1 PWMIM 0 OUTSL 0 TC CPRDR PERIOD Counter Clock TC_CVR COUNT TC_CPULR PULSE 0 TC CPULR PULSE 0 N M TC CPULR PULSE M Normal Period Extension Period Figure 16 9 PWM Waveform with OUTSL 0 If OUTSL bit is set then the TPWM signal starts from HIGH Conditions SR OVFM 0 REPEAT 1 PWMEN 1 PWMIM 0 OUTSL 1 CPRDR PERIOD M Counter Clock CVR COUNT CPULR PULSE 0 TC CPULR PULSE 0 lt N lt M TC CPULR PULSE M Normal Period Extension Period Figure 16 10 PWM Waveform with OUTSL z 1 SAMSUNG ELECTRONICS 16 13 ex S3FN429_UM_REV1 20 16 Timer Counter 16 2 7 2 3 PWM Output Polarity When the timer stops the PWM output polarity on TPWM pin will have different states according to STOPCLEAR S
196. N429_UM_REV1 20 7 Pulse Position Decoder 7 3 Register Description 7 3 1 Register Map Summary e Base Address 0x400C_0000 onsa Desorption NOTE PCR SCR are 2 s complement The range of PCR and SCR is 2 to 27571 SAMSUNG ELECTRONICS 7 6 x S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 3 1 1 PPD_IDR e Base Address 0x400C_0000 Address Base Address 0x0000 Reset Value 0x0001 8703 Identification Code Register 0x0001_ 8703 This field stores the ID code for the corresponding IP 2 F SAMSUNG ELECTRONICS 7 7 ex S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 3 1 2 PPD_CEDR e Base Address 0x400C_0000 e Address Base Address 0x0004 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Debug Enable Bit 0 Disables debug mode bit DBGEN 31 RW PPD is not halted during processor debug mode 1 Enables debug mode bit PPD is halted during processor debug mode sv Clock Enable CLKEN RW 0 Disables PPD Clock 1 Enables PPD Clock SAMSUNG ELECTRONICS 7 8 ex S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 3 1 3 PPD_SRR e Base Address 0x400C_0000 e Address Base Address 0x0008 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 ert Software Reset W 0 Noe
197. OLD 0 Low Start Figure 10 9 illustrates the Tri Angular wave SWAP a Low Start PWMxUy and Low Start PWMxDy s er ss ss s ss 5 Ro keen IMC_ASCRR2 IMC_PCCRR IMC_ASCRR1 IMC_PCCFR E IMCPBeRR omo Daa aie Bete Ce Ee a IMC PBCFR IMC ASCFR2 IMC_ASCRRO IMC_PACRR IMC_ASCFR1 n n m m n m DC m m m E Tt IMC_PACFR IMC_ASCFRO PWMXxUO PWMxU1 PWMxU2 PWMxDO PWMxD1 PWMxD2 Interrupt Can be used by ADC trigger signal Figure 10 9 Tri Angular Wave SWAP a Low Start PWMxUy and Low Start PWMxDy NOTE 1 The switch of upside is low active and the switch of down side is high active 2 For 0 duty of upside you should set the rising falling compare register to 0 For 100 96 duty of upside you should set the rising compare register to equal to TOPCMP value SAMSUNG ELECTRONICS 10 10 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 2 3 5 Tri Angular Wave IMMODE 0 PWMSWAP 0 PWMPOLU 1 High Start and PWMPOLD 0 Low Start Figure 10 10 illustrates the Tri Angular wave No SWAP High Start PWMxUy and Low Start PWMxDy IMC TGR 45058 IMC_ASCRR2 IMC_PCCRR IMC_ASCRR1 IMC_PCCFR E PBCFR IMC_ASCFR2 IMC_ASCRRO IMC_PACRR ASCFR1 ewe ww apes dew CLR aa
198. One half SSPCLKOUT period later valid master data is transferred to the SSPTXD pin Now that both the master and slave data have been set the SSPCLKOUT master clock pin goes HIGH after one further half SSPCLKOUT period The data is now captured on the rising and propagated on the falling edges of the SSPCLKOUT signal In the case of a single word transmission after all bits of the data word have been transferred the SSPFSSOUT line is returned to its idle HIGH state one SSPCLKOUT period after the last bit has been captured However in case of continuous back to back transmissions the SSPFSSOUT signal should be pulsed HIGH between each data word transfer This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the SPH bit is logic zero Therefore the master device must raise the SSPFSSIN pin of the slave device between each data transfer to enable the serial peripheral data write On completion of the continuous transfer the SSPFSSOUT pin is returned to its idle state one SSPCLKOUT period after the last bit has been captured SAMSUNG ELECTRONICS 15 11 x S3FN429_UM_REV1 20 15 Serial Peripheral Interface SPI 15 2 2 1 3 10 Motorola SPI Format with SPO 0 SPH 1 Figure 15 4 illustrates the transfer signal sequence for Motorola SPI format with SPO 0 SPH 1 SSPFSS 5 COXMSB X
199. PCLK You can specify which clock is used as the clock source by setting CLKSRC in TC_CSSR register 16 2 3 2 Counter Clock You can determine the frequency of the counter clock TCCLK using the frequency of the clock source FIN and the internal clock dividers DIVM 10 0 and DIVN 3 0 in CCDR register e TCCLK FIN 2PS DIVM 1 You can determine the counter resolution using the TCCLK value e Counter Resolution 1 TCCLK Since TC_CCDR is read only you should modify the DIVM and DIVN in TC_CDR Clock Divider Register When the timer starts or UPDATE bit is set in the TC_CSR register the TC copies the DIVM and DIVN in the TC_CDR register into the TC_CCDR register Caution Do not set DIVM to zero when DIVN is not zero For example If the counter clock is 4 four times slower than the clock source then the allowed settings are DIVN 0 and DIVM 3 DIVN 1 and DIVM 1 But following is forbidden DIVN 2 and DIVM 0 16 2 4 Debug Option When the debugger halts the CPU DBGEN bit in the TC_CEDR register determines whether the TC freezes the counter or not You can set DBGEN bit to 1 in order to easily check and verify the states of the TC for debug purpose under the development 16 2 5 ADC Trigger Source You can use TC as a trigger source of ADC conversion when ADTRIG bit is set in the TC_SR register You can start the ADC conversion by using Pulse Match event SAMSUNG ELECTRONICS 16 4 ex S3FN429_UM_REV
200. PWMDO COP2 EXI12 P0 16 PWMD1 COP1 EXI11 40 QFP P0 15 PWMD2 COPO EXI10 MODE1 MODEO nRESET VSSCORE VDDCORE VDDCOREOUT XOUT P0 30 USARTTXO EXI22 XIN P0 31 EX123 USARTRX0 PWMO P0 0 EXIO TPWMO OPO P0 14 PWMUO TCLK2 EXI9 F SDAT P0 13 PWMU1 TCAP2 EXI8 F_SCLK P0 1 EXH TCAPO OPO P0 12 PWMU2 TPWM2 EXI7 2 AVDD P0 10 AIN9 PWM3 EXI6 P0 9 AINS PWM2 TCLK1 P0 11 AINTO USARTCLKO ADTRG PO 7 AING PWMO TPWM 1 P0 8 AIN7 PWM1 TCAP1 Figure 21 Pin Map Diagram NOTE If you use OP amp AIN1 should not be used for ADC input SAMSUNG ELECTRONICS 2 2 ex S3FN429_UM_REV1 20 2 Pin Configuration 2 3 Pin Assignment Table 2 1 describes the pin assignment details Table 2 1 Pin Assignment by Pin Number Order exo ms we 55 ms s we 19 20 21 22 23 24 25 26 27 28 29 30 31 32 8 E EN o9 NE EN EF 2 NEM EES 5 EES SAMSUNG ELECTRONICS 2 3 S3FN429_UM_REV1 20 2 Pin Configuration m mus usano _ as Fa Paz Ext a mso ar rz mw a ma cowrw suo ewe 3 Pos cowre co 4 a cowee
201. PWMEX1 1 PWMEX0 1 PWMEX121 Figure 14 7 Extended PWM Waveform PWM Period 0x40 Pulse PWMEX1 and PWMEXO SAMSUNG ELECTRONICS 14 11 lt S3FN429_UM_REV1 20 14 Pulse Width Modulation Figure 14 8 illustrates the extended PWM waveform high start PWM Mte Extension period PWM Pulse 0 0 Duty PWM OUT Extension period Figure 14 8 Extended PWM Waveform High Start Figure 14 9 illustrates the extended PWM waveform low start PWM OUT Extension period PWM Pulse 0 0 Duty Extension period PWM Pulse Period 100 Duty Figure 14 9 Extended PWM Waveform Low Start SAMSUNG ELECTRONICS 14 12 ex S3FN429_UM_REV1 20 14 Pulse Width Modulation 14 3 Register Description 14 3 1 Register Map Summary Base Address 0x4007 0000 0x4007 1000 0x4007 2000 0 4007 3000 esetvalue PWM CSR 0 000 Control set register 0x0000 0000 PWM CCR 0x0010 Control clear register 0x0000 0000 PWM CPULR 0 003 Current pulse register 0x0000 0000 SAMSUNG ELECTRONICS 14 13 ex S3FN429_UM_REV1 20 14 Pulse Width Modulation 14 3 1 1 PWM_ID e Base Address 0x4007 0000 0x4007 1000 e Address Base Address 0x0000 Reset Value 0x0001 0009 o s ID Code Register 0x0001_ 0009 This field stores the ID code for the corresponding IP m SAMSUNG ELECTRONICS 14 14 27 S3FN429_UM
202. PWMxDy 10 5 Tri Angular Wave Duty No SWAP a Low Start PWMxUy and High Start 10 6 Tri Angular Wave SWAP a Low Start PWMxUy and High Start PWMXDYy 10 7 Tri Angular Wave Duty SWAP a Low Start PWMxUy and High Start PWMXDYy 10 8 Tri Angular Wave No SWAP Low Start PWMxUy Low Start PWMXDy 10 9 Tri Angular Wave SWAP a Low Start PWMxUy and Low Start PWMXDYy 10 10 Tri Angular Wave No SWAP a High Start PWMxUy and Low Start PWMxDy 10 11 Tri Angular Wave Duty No SWAP a High Start PWMxUy Low Start PWMXDy 10 12 Tri Angular Wave SWAP a High Start PWMxUy and Low Start PWMXxDy 10 13 Tri Angular Wave No SWAP a High Start PWMxUy and High Start PWMXDy 10 14 Tri Angular Wave SWAP a High Start PWMxUy and High Start PWMXxDy 10 15 Saw Tooth Wave No SWAP Low Start PWMxUy and High Start PWMXDy 10 16 Saw Tooth Wave Duty No SWAP a Low Start PWMxUy and High Start PWMxDy 10 17 Saw Tooth Wave SWAP a Low Start PWMxUy and High Start PWMXDy 10 18 Saw Tooth Wave No SWAP a Low Start PWMxUy and Low Start 10 19 Saw Tooth Wave SWAP a Low Start PWMxUy and Low St
203. Programmable eight wake up sources from stop Clock Manager CM The Clock Manager CM supports e External Main Oscillator Clock EMCLK 1 to 12 MHz e Internal Main Oscillator Clock IMCLK 40 MHz e Phase Locked Loop PLL control from 12 to 40 MHz e Clock monitor to detect an external main oscillator failure e Low power mode IDLE STOP by clock gating control e Programmable clock dividers SDIV and PDIV e Reset management e Basic timer for reset generation SAMSUNG ELECTRONICS 1 3 1 Product Overview S3FN429_UM_REV1 20 Watchdog Timer WDT The Watchdog Timer WDT contains e Configurable microcontroller reset event e Programmable 16 bit down counter 16 bit Timer Counter TC The 16 bit Timer Counter TC contains e Operation in an interval capture match and overflow or PWM mode e Match and overflow interrupt e Selectable an internal or external clock Pulse Width Modulation PWM The Pulse Width Modulation PWM supports e 16 bit PWM signal generation e Interval mode e Programmable idle level e Extension PWM function Pulse Position Decoder PPD The Pulse Position Decoder PPD contains 3 input signals are PHASEA PHASEB PHASEZ e Position counter and position capture timer e Speed counter and speed capture timer e Up Down counter SAMSUNG ELECTRONICS 1 4 1 Product Overview S3FN429_UM_REV1 20 1 Product Overview Inverter Motor Controller IMC The Inverter Motor Co
204. R RI IR RI R R IR R R R R R R R WIN IWIWN IWIW W W W W W W W W W W avo ema R Rev PWM Pulse Val PULSE 15 0 o RM Refer to Section 14 2 8 Parameter Relationship 9605 SAMSUNG ELECTRONICS 14 28 ex S3FN429_UM_REV1 20 14 3 1 14 PWM_CCDR 14 Pulse Width Modulation e Base Address 0x4007_0000 0x4007_ 1000 Address Base Address 0x0034 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 SAMSUNG ELECTRONICS Current Clock Divider Value PWMCLK M 1 where 0 lt M lt 2 Current Pre scale Value PWMCLK 2 where 0 lt N lt 16 r 14 29 ex S3FN429_UM_REV1 20 14 Pulse Width Modulation 14 3 1 15 PWM_CPRDR e Base Address 0 4007 0000 0x4007_ 1000 Address Base Address 0x0038 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 1 0 PWM Current Period Value 0x0000 This field shows operating PWMs current period value SAMSUNG ELECTRONICS 14 30 ex S3FN429_UM_REV1 20 14 Pulse Width Modulation 14 3 1 16 PWM_CPULR e Base Address 0 4007 0000 0x4007_ 1000 e Address Base Address 0x003C Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 PWM Pulse Value 0x0000 This field shows operating PWMs current pulse value SAMSUNG ELECTRONICS 14 31 ex S3FN429_UM_REV1 20 15 Serial Peripheral
205. RECLK because the IDLE and the STOP modes disconnect the CORECLK SAMSUNG ELECTRONICS 5 14 ex S3FN429_UM_REV1 20 5 Clock and Power Manager The System Clock SYSCLK input source can use PLLCLK EMCLK or IMCLK as its clock source by setting SYSCLK fields in CM MR register If you change the System Clock then the both source and destination clock should be stabled Otherwise you can put microcontroller in an unexpected status It might generate a command error also Figure 5 9 illustrates the case that changes the clock source for the SYSCLK diagram The operation of the other case remains the same External Oscillator Stabilization time Enabled Stabled Enabled Disabled Enabled Stabled Stabled IMCLK MEM ME od h SYSCLK Freezed Freezed During times EMCLK During 3 times IMCLK Internal Oscillator Stabilization time 10clocks Check EMCLK stable Check IMCLK stable It changes to EMCLK It changes to IMCLK Figure 5 9 The Change Clock Source of SYSCLK SAMSUNG ELECTRONICS 5 15 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 3 2 SYSCLK Change SYSCLK uses for core and peripherals except the watchdog timer e When you use the status polling method the sequence for SYSCLK change is the followings Check the destination clock to change is stabled or not PLL IMCLK or EMCLK status bits in SR register If STABLE bit in register is 1 write 1 to ST
206. RIR R R R R R R R R mw Compare Data for Phase Rising time PCCMPRDAT 15 0 RW This field determines the Phase C compare register value 0x0000 at rising NOTE If you use ADC compare interrupt you should set IMC_PxCRR F from 1 to IMC_TCR 1 0 lt IMC_PxCRR FR lt IMC_TCR SAMSUNG ELECTRONICS 10 55 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 3 1 17 IMC_PACFR Base Address 0 400 0000 Address Base Address 0x0040 Reset Value 0 0000 0000 31 30 29 28 27 26 25 24123 22 21 20 19 18 17 16 15 14 13 12 11 10 a B A PACMPFDAT ele es RIR R R R R R R R R Rvo Compare Data for Phase A Falling time PACMPFDAT 15 0 RW This field determines the Phase A compare register value 0x0000 at falling NOTE If you use ADC compare interrupt you should set IMC_PxCRR F from 1 to IMC_TCR 1 0 lt IMC_PxCRR FR lt IMC_TCR SAMSUNG ELECTRONICS 10 56 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 3 1 18 IMC_PBCFR Base Address 0 400 0000 Address Base Address 0x0044 Reset Value 0 0000 0000 31 30 29 28 27 26 25 24123 22 21 20 19 18 17 16 15 14 13 12 11 10 a B A PBCMPFDAT ele es RIR R R R R R R R R
207. Register Map Reed DWT SAMSUNG ELECTRONICS 3 2 ex S3FN429_UM_REV1 20 3 System Memory Management 3 3 2 Peripheral Special Function Register Map Table 3 3 describes the peripheral special function register map Table 3 3 Peripheral Memory Base Address Peripheral Description PPD 0 400 0000 PPD Pulse Position Decoder IMC IMC Pulse Width Modulation 3 16 bit oi Timer Counter 2 16 bit TC TC1 Timer Counter 1 16 bit TCO Timer Counter 0 16 bit ADC ADC WDT WDT Watchdog Timer 16 bit IFC SAMSUNG ELECTRONICS 3 3 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC Analog to Digital Converter ADC 4 1 Overview This chapter describes the complete functional description of the Analog to Digital Converter ADC controller and the operation of design from the end user perspective 4 1 1 Features The distinctive features of ADC are e Resolution 12 bit e One input channel AINO is assigned to Operational Amplifier OP AMP 10 external input channels AIN 10 1 e Conversion start sources Software start External trigger input ADTRG Internal peripheral trigger signals Inverter Motor Controller IMC and Timer Counter TC e Maximum conversion rate 5 MHz clock e Analog input voltage range 0 to Vayaer e Differential linearity error 1 5 LSB Max at 2 5 to 5 5 V e I
208. S3FN429 32 bit CMOS Microcontrollers Revision 1 20 May 2012 User s Manual SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS INFORMATION AND SPECIFICATIONS WITHOUT NOTICE Products and specifications discussed herein are for reference purposes only All informa tion discussed herein is provided on an AS IS basis without warranties of any kind This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics No license of any patent copyright mask work trademark or any other intellectual property right is granted by one party to the other party under this document by implication estoppel or otherwise Samsung products are not intended for use in life support critical care medical safety equipment or similar applications where product failure could result in loss of life or personal or physical harm or any military or defense application or any governmental procurement to which special terms or provisions may apply For updates or additional information about Samsung products contact your nearest Samsung office All brand names trademarks and registered trademarks belong to their respective owners 2012 Samsung Electronics Co Ltd All rights reserved SAMSUNG ELECTRONICS 7 Important Notice Samsung Electronics Co Ltd Samsung reserves the right to make changes to the information in this publication at any time without prior notice All
209. SR CAPI Interrupts are cleared by writing 1 to corresponding bits in Figure 16 4 Capture Operation Timing Caution The TC supports the capture operation only when the clock source is PCLK SAMSUNG ELECTRONICS 16 7 ex S3FN429_UM_REV1 20 16 Timer Counter 16 2 7 Period Mode The TC operates in Period Mode when OVFM bit in TC_SR register is clear In this mode the counter value increases from 1 to PERIOD bits in TC_CPRDR register When the counter value reaches PERIOD value Period End event is generated If REPEAT bit in TC SR register is set then the counter value restarts from 1 If REPEAT bit is clear then the timer stops and the counter value is cleared to O During operation CPRDR and CPULR represent the current configured values When the timer starts or UPDATE bit in CSR register is set the TC changes the values of PERIOD in CPRDR and PULSE in CPULR to new values specified by PRDR and PULR register respectively You should set PERIOD to greater than 1 before starting the timer Figure 16 5 illustrates the period mode timing Condition TC SR OVFM 0 REPEAT 1 CCSMR SIZE gt 3 TC CPULR PULSE 4 CPRDR PERIOD 8 Counter Clock TC CVR COUNT TC SR START TC RISR STARTI TC RISR STOPI TC RISR PSTARTI TC RISR PENDI TC RISR MATI Interrupts are cleared by writing 1 to corresponding bits in Figure 16 5 Per
210. STS WDTRSTS LVDRSTS NRSTS or SWRSTS 01 b Check SYSCLK initial value M MR1 amp 0x3 IMCLK Y EMCLK No N 8 hange SYSCLK divider Yes N lt 2 Figure 5 21 from 8 to N 1 7 CM PCSR gt IFCCLK 1 Enable Flash Gate Clock Yes 3 zN 7 IFC gt CLKEN 1 Enable Flash Clock IFC MR gt FSMODE 1 Enable Fast Mode v CM SCDR SDIVKEY SDIV Yes EMCLK SYSGE Yes PLLCLK K to other Check EMCLK Check EMCLK CM SR2EMCLK 1 No v Setting P M S value CM PDPR value Setting Stabilization Time CM PSTR value Clear STABLE bit Y CM_ICR gt STABLE 1 Enable PLL CM_CSR Y Change SYSCLK CM MR1 _ 1 amp 0x3 10 0 Check PLL status 7 CM SROPLL LLCLK SDIV gt 20MHz an IFC_MR gt FSMODE 1 CM_SR CM_RISR SSTABLE 1 a CM_PCSR gt IFCCLK 1 Y IFC_CEDR gt CLKEN 1 Y MR gt FSMODE 1 gt CORECLK EMCLK SDIV 12 Clear STABLE bit CM_ICR gt STABLE 1 Y Change SYSCLK CM_MR1 MR1 amp 0x3 0 2 ea v mu Run by CORECLK IMCLK SDIV ____ 58 CM_RISR gt STABLE 1 e T S 1 Yes Run CORECLK PLLCLK SDIV Figure 5 22 Clock Initializatio
211. Saw Tooth Wave IMMODE 1 PWMSWAP 0 PWMPOLU 1 High Start and PWMPOLD 0 Low Start Figure 10 20 illustrates the Saw Tooth wave No SWAP a High Start PWMxUy Low Start PWMxDy TOB e ue ee Se a RC IMC_ASCRR2 a aa J PCCRR ee ee eg 1 2 IMC PBCRR oos we cua i na oh ir e at de 4 ASCRRO we al te te IESU ae IMC_PACRR PWMxDO PWMxD1 PWMxD2 Interrupt Can be used by ADC trigger signal Figure 10 20 Saw Tooth Save No SWAP a High Start PWMxUy and Low Start PWMxDy NOTE 1 Both the switches of upside and down side are low active 2 For 100 95 duty of upside you should set the rising falling compare register to For 0 duty of upside you should set the rising compare register to equal to TOPCMP value SAMSUNG ELECTRONICS 10 21 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 2 3 14 Saw Tooth Wave IMMODE 1 PWMSWAP 1 PWMPOLU 1 High Start and PWMPOLD 0 Low Start Figure 10 21 illustrates the Saw Tooth wave SWAP a High Start PWMXUy and Low Start PWMxDy IMC TOR oe My lee ERR REA IMC ASCRR2 iso ke meom PC eR LP RETE EE S IMG PCCRR o o m o y IMC_ASCRR1 m 5 se oom oe xe ee G
212. TOPHOLD KEEP IDLESL and OUTSL bits in TC_SR register Table 16 3 describes the differences of output polarity according to control bits Table 16 3 PWM Output Polarity According to Control Bits The timer stops immediately and TPWM is IDLESL NOTE Priorities among control bits are STOPCLEAR gt STOPHOLD gt KEEP gt IDLESL SAMSUNG ELECTRONICS 16 14 ex S3FN429_UM_REV1 20 16 Timer Counter When both STOPHOLD and STOPCLEAR are clear you can clear the START bit to make the timer stop after completing the current PERIOD cycle In this state if KEEP bit in TC_SR register is set then the TC keeps the output level on TPWM pin same as the opposite level of OUTSL If KEEP bit is set to clear then the IDLESL bit in TC_SR register determines the output level on TPWM pin Figure 16 11 illustrates the PWM waveform under IDLE state Conditions TC SR OVFM 0 REPEAT 1 PWMEN 1 PWMIM 0 STOPHOLD 0 STOPCLEAR 0 End of Period TC SR START KEEP IDLESL OUTSL j j Period ERESER Figure 16 11 PWM Waveform Under IDLE State When clearing START bit if STOPHOLD bit is set but STOPCLEAR bit is clear in TC_SR register then the TC immediately stops to increase the counter value As a result TC keeps the counter value and the output level on TPWM pin You can set the START bit again to restart the TC and to increase the counter value from the last value Figure 16 12 illustrat
213. TTX line then returns to high level idle state for at least 12 bit periods to ensure that the end of break is correctly detected Then the transmitter resumes normal operation 17 6 2 Receive Break The receiver detects the break condition when all data parity and stop bits are low When the low stop bit is detected the receiver asserts the RXBRK Break Received bit in the US SR register 17 6 3 Interrupts Most of the status bit in US SR has a corresponding bit in US IMSCR Interrupt Mask Set Clear Register US RISR Raw Interrupt Status Register US MISR Masked Interrupt Status Register and US ICR Interrupt Clear Register These bits controls the generation of interrupts by asserting the USART interrupt line connected to the NVIC SAMSUNG ELECTRONICS 17 17 ex S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 6 4 Test Modes You can program the USART to operate in three modes using the field 1 0 in the US MR register The three test modes are e Automatic Echo Mode e Local Loop back Mode e Remote Loop back Mode Automatic echo mode It allows bit by bit retransmission When the USARTRX line receives bit it is sent to the USARTTX line Programming the transmitter has no effect Local loop back mode It receives the transmitted characters This mode does not use the USARTTX and the USARTRX pins The output of the transmitter connects internally to the input of the receiver T
214. This section explains about Calibration Below registers are related to calibration DAT NCAL Converted result data without calibration e DAT CAL Converted result data with calibration e ADC_GCC Gain calibration constant e ADC_OCC Offset calibration constant If you want to use calibration function then you should get constants for a calibration unit Constants have different value depending on the noise level of real target system You can determine ADC Gain Calibration Constant ADC_GCC and ADC Offset Calibration Constant ADC_OCC by taking two samples of known reference voltages and use these samples to calculate their values After calculation store ADD_GCC values in ADC_GCCR and ADC_OCC values in ADC_OCCR A conversion result is calibrated according to the status of CALEN bit You should set CALEN bit to 1 to get calibrate conversion result of data ADC automatically calculates calibrate result before sending result to ADC Convert Data Register ADC_DR if CALEN bit is 1 It is directly send to ADC_DR if CALEN bit is 0 and it bypasses calibration unit 4 1 10 1 Calibration Unit Figure 4 7 illustrates the ADC calibration scheme ADCOCC in ADC_OCCR Offset Calibration Constant 14 bit signed value from ADC_OCCR DAT DAT_CAL in ADC_DR p Ne e Not Calibrated Conversion Data Calibrated Conversion Data 12 bit unsigned value 12 bit unsigned value ADCGCC in GCCR Gain Calibratio
215. UM_REV1 20 10 Inverter Motor Controller IMC 10 3 1 3 IMC_SRR Base Address 0 400 0000 Address Base Address 0x0008 Reset Value 0 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 Software Reset 0 No effect 1 Performs IMC Software Reset operation SAMSUNG ELECTRONICS 10 28 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 3 1 4 IMC_CRO Base Address 0 400 0000 e Address Base Address 0x000C Reset Value 0 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 IMCLKSEL PWMOUTOFFENBYCOMP gt ____ PWMOFFEN IMFILTER ESELPWMOFF zm zm __ _ PACRWM EE om gt ewo __ meme woe ERE EXE Reserved Phase C Compare Register Write Mode Selection Bit 0 Common Write mode PCCRR value written by the user is copied to the PCCRWM PCCFR field simultaneously User will use only PCCRR register 1 Separate Write modeUser should write both PCCRR and PCCFR register to each proper value Phase B Compare Register Write Mode Selection Bit 0 Common Write mode PBCRR value written by the user is copied to the PBCRWM PBCFR field simultaneously Us
216. Vector Eee ee e e uta er a diea Perg Rb 11 2 Device interrupt Ee derent eese ede 11 3 Function Mode 1 12 2 Pin DesGriptiON sassi ev db Let ded de evade 13 1 Gain Configuration Table direi 13 3 Pin 14 1 PERIOD and PULSE Field Relationship in Normal Mode 14 5 PWM QUEUE octane 14 6 SSP Pin 15 2 16 2 PWM Extension ET 16 14 PWM Output Polarity According to Control 16 14 USART Pin Descriptio EE eade edet 17 2 Asynchronous Mode SYNC 0 17 6 Synchronous Mode SYNG T encanto ner bu tb x da 17 9 Asynchronous Mode SYNC 0 17 46 Absolute Maximum Ratings 19 1 Recommended Operating Conditions sss eee nnne 19 2 5 mem Em 19 3 Reset Input Characteristics ccsccccecceceeeeeseeeeeaceseeeeeceaeeeeaaeeeeaeeseeeeeceaeeesaaeseeaeeseaeeesaeeseaeeeeeeeee 19 4 Reset Inpu
217. XIT zaj EX e S3FN429_UM_REV1 20 7 Pulse Position Decoder Description OS Reset Value 10 Selects both rising and falling edge of PHASEZ input 11 No detection at any edge of PHASEZ PHASEZ Signal Selection Bits 000 Specifies PHASEZ signal is the external signal asserted on PHASEZ pin Do not use the signal asserted from COMP as PHASEZ 001 Use the signal asserted from COMP as PHASEZ Others Not used 2 PHASEB Edge Selection Bits This field determines the edge selection for PHASEB 00 Selects rising edge of PHASEB input 01 Selects falling edge of PHASEB input 10 Selects both rising and falling edge of PHASEB input 11 No detection at any edge of PHASEB PHASEB Signal Selection Bits 000 Specifies PHASEB signal is the external signal asserted on PHASEB pin Do not use the signal asserted from COMP as PHASEB 001 Use the signal asserted from COMPO as PHASEB 010 Use the signal asserted from COMP1 as PHASEB PHASEZ 20 18 17 16 PHASEB 15 13 011 Use the signal asserted from COMP2 as PHASEB 100 Use the signal asserted from COMP3 as PHASEB Others Not used 2 PHASEA Edge Selection Bits This field determines the edge selection for PHASEA 00 Selects rising edge of PHASEA input 01 Selects falling edge of PHASEA input 10 Selects both rising and falling edge of PHASEA input 11 No detection at any edge of PHASEA PHASEA Signal Sele
218. Z 16 RSVD SCCUNF SCCOVF Speed Counter Carry Overflow Masked Interrupt State Gives the masked interrupt state prior to masking of SCCOVF interrupt Speed Capture Timer Overflow Masked Interrupt State Gives the masked interrupt state prior to masking of SCTOVF interrupt Speed Capture Masked Interrupt State Gives the masked interrupt state prior to masking of SCAPT interrupt Speed Counter Sign Underflow Masked Interrupt State Gives the masked interrupt state prior to masking of SCSUNF interrupt Speed Counter Sign Overflow Masked Interrupt State Gives the masked interrupt state prior to masking of SCSOVF interrupt Speed Counter Match Masked Interrupt State EM Gives the masked interrupt state prior to masking of SCMAT interrupt Reserved SCAPT SCSUNF SCSOVF SCMAT J 4 ak SAMSUNG ELECTRONICS 7 20 S3FN429_UM_REV1 20 7 Pulse Position Decoder Position Counter Carry Underflow Masked Interrupt State PCCUNF Gives the masked interrupt state prior to masking of PCCUNF interrupt Position Counter Carry Overflow Masked Interrupt State PCCOVF Gives the masked interrupt state prior to masking of PCCOVF interrupt Position Capture Timer Overflow Masked Interrupt State PCTOVF Gives the masked interrupt state prior to masking of PCTOVF interrupt Position Counter Sign Underflow Masked Interrupt State PCSUNF Gives the masked interrupt state prior to ma
219. ZE is 0x09 then the TC acts as 10 bit TC e If SIZE is OxOf then the TC acts as 16 bit Writing into the TC_CSMR register completes when UPDATE 1 or START 1 condition of register SAMSUNG ELECTRONICS 16 35 ex S3FN429_UM_REV1 20 16 Timer Counter 16 3 1 14 TC_PRDR e Base Address 0x4006 0000 0x4006 1000 0x4006 2000 e Address Base Address 0x0034 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 RIR R RIR RI R R IR R R R R R R R WINIWIWN IWIW W W W W W W W W W W mw R Resev _ Specifies PERIOD value Writing into the PRDR register completes when PERIOD 15 RW 9 19 0 UPDATE 1 or START 1 condition of TC CSR register Caution You should set PERIOD to any value greater than 0 in Overflow mode or greater than 1 in Period mode before starting the timer SAMSUNG ELECTRONICS 16 36 ex S3FN429_UM_REV1 20 16 Timer Counter 16 3 1 15 TC_PULR e Base Address 0x4006 0000 0x4006 1000 0 4006 2000 e Address Base Address 0x0038 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 RIR R RIR RI R R IR R R R R R R R R Specifies PULSE value Writing into the TC_PULR register completes when PULSE 15 RW a 15 UPDATE 1 or START 1 condition of CSR register SAMSUNG ELECTRONICS 16 37 ex
220. _REV1 20 14 Pulse Width Modulation 14 3 1 2 PWM_CEDR e Base Address 0 4007 0000 0x4007_ 1000 e Address Base Address 0x0004 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 R Debug mode enable 0 Disables debug mode Debugger interface generates Debug Acknowledge that has no influence on PWM function DBGEN 31 RW 1 Enables debug mode When you activate the debugger interface the Debug Acknowledge freezes the PWM function However keep the full Read Write access to internal register for debug purpose vo Jeon R Reseed 1971 Clock Enable Disable Bit 0 Disables PWM Clock bit CEREN 2 1 Enables PWM Clock bit PWM software reset does not affect CLKEN bit status SAMSUNG ELECTRONICS 14 15 ex S3FN429_UM_REV1 20 14 Pulse Width Modulation 14 3 1 3 PWM_SRR e Base Address 0x4007_0000 0x4007_ 1000 e Address Base Address 0 0008 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Software Reset 0 No effect 1 Performs PWM Software Reset operation SAMSUNG ELECTRONICS 14 16 ex S3FN429_UM_REV1 20 14 Pulse Width Modulation 14 3 1 4 PWM_CSR e Base Address 0x4007 0000 0x4007 1000 e Address Base Address 0x000C Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2
221. a Low Start PWMxUy and Low Start PWMxDy NOTE 1 The switch of upside is high active and the switch of down side is low active 2 For 100 95 duty of upside you should set the rising falling compare register to For 0 96 duty of upside you should set the rising compare register to equal to TOPCMP value SAMSUNG ELECTRONICS 10 19 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 2 3 12 Saw Tooth Wave IMMODE 1 PWMSWAP 1 PWMPOLU 0 Low Start and PWMPOLD 0 Low Start Figure 10 19 illustrates the Saw Tooth wave SWAP Low Start PWMxUy and Low Start PWMxDy IMC_TC bite lel dec binds 2 4 4 s IMC_ASCRR1 e qe te o o o IMG BBOBBL bem oh IMC ASCRRO th vc ok en xe ae IMC_PACRR PWMXxUO PWMxU1 PWMxU2 PWMxDO PWMxD1 PWMxD2 Interrupt Can be used by ADC trigger signal Figure 10 19 Saw Tooth Wave SWAP Low Start PWMxUy and Low Start PWMxDy NOTE 1 The switch of upside is low active and the switch of down side is high active 2 For 0 duty of upside you should set the rising falling compare register to For 100 duty of upside you should set the rising compare register to equal to TOPCMP value SAMSUNG ELECTRONICS 10 20 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 2 3 13
222. a Read the MISR register gives current masked status value of corresponding interrupt SAMSUNG ELECTRONICS 9 35 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 3 1 9 IFC_ICR e Base Address 0x4001_0000 e Address Base Address 0x0020 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 ERRn ERR Interrupt Clear Bit Error 2 Writes or erases to the protected memory region 0 No effect 1 Clears ERR2 interrupt clear bit ERRn ERR Interrupt Clear Bit Error 1 Writes undefined value CMD 2 0 111b into the CMD field of a control register during operation flow 0 No effect 1 Clears ERR interrupt clear bit ERRn ERR Interrupt Clear Bit Error 0 Tries to execute other operation program erase while operating by normal program command END END Interrupt Clear Bit END W 0 effect 1 Clears End interrupt clear bit NOTE When you set to 1 corresponding bit in raw interrupt status and masked interrupt status register is cleared Caution When ERRn occurs in operation it is impossible to write any value into CR register Clear it to execute next command You can clear ERRn interrupt status by the IFC_ICR register SAMSUNG ELECTRONICS 9 36 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 3 1 10 IFC_SR e Base Address 0x4001_0000 e Address Base Address 0x0024 Reset Value 0x0000 0000 31 30 29 2
223. ad and writes in the Register field The Reade VIS application sets this field by writing 1 b1 and clears it by writing 1 bO Register Value Conventions Expression Description X Undefined bit X Undefined multiple bits Undefined but depends on the device or pin status Device dependent The value depends on the device Pin value The value depends on the pin status Reset Value Conventions Expression Description 0 Clears the register field 1 Sets the register field X Don t care condition Warning Some bits of control registers are driven by hardware or write operation only As a result the indicated reset value and the read value after reset might be different SAMSUNG ELECTRONICS ex S3FN429_UM_REV1 20 1 Product Overview Product Overview 1 1 Introduction The S38FN429 user manual describes the complete reference specification of S3FN429 The improved features of S8FN429 ARM Cortex MO Core Built in 32 KB flash memory Internal 2 KB SRAM for stack data memory or code memory 32 General Purpose 10 GPIO Operating temperature 40 to 105 C Operating voltage range 2 5 to 5 5 V Interrupt controller Dynamically reconfigurable Nested Vectored Interrupt Controller NVIC Clock and Power Management Controller CM Watchdog Timer WDT 3 x 16 bit Timer Counter TC 4 x 16 bit Pulse Width Modulation PWM 1 x 16 bit Pulse Position Decoder PPD 1 x
224. alling compare register to For 0 96 duty of upside you should set the rising compare register to equal to TOPCMP value SAMSUNG ELECTRONICS 10 23 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 2 3 16 Saw Tooth Wave IMMODE 1 PWMSWAP 1 PWMPOLU 1 High Start and PWMPOLD 1 High Start Figure 10 23 illustrates the Saw Tooth wave SWAP a High Start PWMxUy and High Start PWMxDy TCR ce ee RR ee IMG PCCRR J o so n ae PBCRR o ASCRRO 2 PWMXxUO PWMxU1 PWMxU2 PWMxDO PWMxD1 PWMxD2 Interrupt Can be used by ADC trigger signal Figure 10 23 Saw Tooth Wave SWAP a High Start PWMxUy and High Start PWMxDy NOTE 1 The switch of upside is high active and the switch of down side is low active 2 For 0 96 duty of upside you should set the rising falling compare register to 0 For 100 96 duty of upside you should set the rising compare register to equal to TOPCMP value SAMSUNG ELECTRONICS 10 24 x S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 3 Register Description 10 3 1 Register Map Summary Base Address 0 400 0000 IMC_IDR 0x0000 IMC ID register 0x0001 0012 IMC_CEDR IMC_SRR IMC_CRO _ 1 IMC_CNTR IMC_SR IMC_IMSCR IMC_RISR IMC_MISR IMC_ICR IMC_TCR IMC_DTCR IMC_PACRR IMC_PBCRR IMC_PCCRR IMC_PACFR IMC_PBCFR IMC_PCCFR IMC_ASTSR IMC_ASCRRO IMC_ASCRR1 IMC_ASCRR2 IMC_AS
225. alue 0x0000 0000 31 30 29 28 27 26 25 24 29 28 27 26 25 24 23 22 21 20 19 18 17 16 22 21 20 19 18 17 16 15 14 13 12 11 10 14 13 12 1 Bonam ES Port y Output Data Clear 0 Py 0 effect 1 Clears GPIO output data on the corresponding pin You can read the result through GPIO_PDSR register SAMSUNG ELECTRONICS 8 18 27 S3FN429_UM_REV1 20 8 General Purpose I O GPIO 8 3 1 14 GPIO_ODSR e Base Address 0x4005 0000 e Address Base Address 0x0034 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 Port y Output Data Status 0 GPIO output data for the corresponding pin is Py y programmed to 0 Low Level 1 GPIO output data for the corresponding pin is programmed to 1 High Level SAMSUNG ELECTRONICS 8 19 ex S3FN429_UM_REV1 20 8 General Purpose I O GPIO 8 3 1 15 GPIO_PDSR e Base Address 0x4005 0000 e Address Base Address 0x0038 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 Port y Pin Status Py y 0 The real level of corresponding pin is at logic 0 1 The real level of corresponding pin is at logic 1 SAMSUNG ELECTRONICS 8 20 27 S3FN429_UM_REV1 20 9 Internal Flash Controller IFC Internal Flash Controller IFC 9 1 Overview S3FN429 has an on chip program flash ROM internally The flash memory size is
226. alue 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 IDLE e __ gt meor Idle Masked Interrupt State Gives the masked interrupt state prior to masking of the idle interrupt Transmitter Empty Masked Interrupt State TXEMPTY Gives the masked interrupt state prior to masking of the TXEMPTY interrupt Time Out Masked Interrupt State TIMEOUT Gives the masked interrupt state prior to masking of the TIMEOUT interrupt Parity Error Masked Interrupt State PARE Gives the masked interrupt state prior to masking of the PARE interrupt Framing Error Masked Interrupt State FRAME Gives the masked interrupt state prior to masking of the FRAME interrupt Overrun Error Masked Interrupt State Gives the masked interrupt state prior to masking of the OVRE interrupt WS R Rewd Receiver Break Masked Interrupt State RXBRK 2 Gives the masked interrupt state prior to masking of the RXBRK interrupt Transmitter Ready Masked Interrupt State TXRDY 1 Gives the masked interrupt state prior to masking of the TXRDY interrupt RXRDY Receiver Ready Masked Interrupt State Gives the masked interrupt state prior to masking of the a SAMSUNG ELECTRONICS 17 35 S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter LL RXR inter 227212 NOTE On a Read the US MISR register provides the current masked status value of the corresponding inter
227. art PWMXxDy 10 20 Saw Tooth Save No SWAP a High Start PWMxUy and Low Start PWMXDy 10 21 Saw Tooth Wave SWAP a High Start PWMxUy and Low Start PWMXDy 10 22 Saw Tooth Wave No SWAP a High Start PWMXUy and High Start PWMXDYy 10 23 Saw Tooth Wave SWAP a High Start PWMxUy and High Start PWMXDy 10 24 Synchronous Write at Zero and IMC TCR Match SYNCSEL 00 b NUMSKIP 00000 b 10 33 Synchronous Write at Zero and IMC TCR Match SYNCSEL 00 b NUMSKIP 00000 b 10 34 Synchronous Write at Zero Match SYNCSEL 01 b NUMSKIP 000005 10 34 Synchronous Write at IMC TCR Match SYNCSEL 10 b NUMSKIP 00000 5 10 35 Synchronous Write at Zero and IMC TCR Match SYNCSEL 00 b NUMSKIP 00001 b 10 35 Synchronous Write at Zero Match SYNCSEL 01 b NUMSKIP 00001 b 10 36 SAMSUNG ELECTRONICS ex Figure 10 30 Figure 10 31 Figure 11 1 Figure 13 1 Figure 14 1 Figure 14 2 Figure 14 3 Figure 14 4 Figure 14 5 Figure 14 6 Figure 14 7 Figure 14 8 Figure 14 9 Figure 15 1 Figure 15 2 Figure 15 3 Figure 15 4 Figure 15 5 Figure 15 6 Figure 15 7 Figure 15 8 Figure 15 9 Figure 16 1 Figure 16 2 Figure 16 3 Figure 16 4 Figure 16 5 Figure 16 6 Figure 16 7 Figure 16 8 Figure 16 9 Figure 16 10 Figure 16 11 Figure 16 12
228. as soon as it executes the WFI or the WFE instruction STOP Sleep on Exit If the SLEEPONEXIT and the SLEEPDEEP bits of the System Control Register in the Cortex MO are set to 1 then the MCU enters the STOP mode as soon as it exits the lowest priority of the ISR register e Entry Sequence Configure Wake Up sources Configure Clock Source Configure Oscillator and PLL f you want to use the WFI then copy the Interrupt Set Enable Registers into the CM NISR register Execute entry condition The System Control Register of the Cotex MO NVIC has the Sleep on Exit bit SLEEPONEXIT If it is set to 0 then the processor completes the execution of an exception handler Later it returns to the thread mode and immediately enters into the STOP mode Caution If you don t the external main oscillator when pin7 and pin8 are defined XOUT and XIN function you should tie XIN to ground XOUT should be opened 5 4 2 4 Exit STOP Mode The microcontroller can exit the STOP mode by issuing an interrupt or a Wake Up event After the exit from STOP mode the clock source of the SYSCLK can differ by condition before entering the STOP mode 5 4 2 5 Wake Up from IDLE STOP Mode Before the entry of IDLE or STOP mode executing WFE or WFI allows the processor to Wake Up by an event or interrupts As the previous section describes enable the interrupt that you use for Wake Up source before the entry of the IDLE or the STOP mode Table 5
229. ase Address 0 4004 2000 e Address Base Address 0x0010 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 o gt N cus INTREFSEL3 INTREFSELO gt e mo EXE COMP2FILTER COMPOFILTER gt RSVD en R Comparator 3 Edge Detection Filter Selection Bit 000 bypass 001 PCLK 1 010 PCLK 16 COMP3FILTER 30 28 RW 011 PCLK 64 100 PCLK 128 101 PCLK 256 110 PCLK 512 111 PCLK 1024 mw 41 Comparator 3 Reference Level Selection Bit 000 0 45 001 0 50 010 0 55 INTREFSEL3 26 24 RW 011 20 60 Vpp 100 0 65 Vpp 101 0 70 110 2 0 75 Vpp 111 2 0 80 Vpp Emu R Rew 9 Comparator 2 Edge Detection Filter Selection Bit 000 bypass 001 PCLK 1 COMP2FILTER 22 20 RW 010 PCLK 16 011 PCLK 64 100 PCLK 128 101 PCLK 256 110 PCLK 512 SAMSUNG ELECTRONICS 6 10 27 EET 22 EXE INTREFSEL2 2 COMP1FILTER J INTREFSEL1 zal EXE pue S3FN429_UM_REV1 20 6 Comparator Mam Twe Reset vawe Ng R Comparator 2 Reference Level Selection Bit 000 0 45 Vpp 001 0
230. ask the interrupt Disables this interrupt 1 Unmask the interrupt Enables this interrupt Period End Interrupt Mask 0 Mask the interrupt Disables this interrupt 1 Unmask the interrupt Enables this interrupt Period Start Interrupt Mask PSTARTI 0 Mask the interrupt Disables this interrupt 1 Unmask the interrupt Enables this interrupt Stop Interrupt Mask STOPI 0 Mask the interrupt Disables this interrupt 1 Unmask the interrupt Enables this interrupt Start Interrupt Mask STARTI 0 Mask the interrupt Disables this interrupt 1 Unmask the interrupt Enables this interrupt NOTE On a Read TC_IMSCR register gives the current value of the mask on the relevant interrupt A Write of 1 to a particular bit sets the mask and Write of 0 clears the corresponding mask SAMSUNG ELECTRONICS 16 30 ex S3FN429_UM_REV1 20 16 Timer Counter 16 3 1 9 TC_RISR e Base Address 0 4006 0000 4006 1000 0 4006 2000 e Address Base Address 0x0020 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 81 7 gt gt mn e gt 2 e gt som gt je Capture Interrupt Gives the raw interrupt state prior to masking of the Capture interrupt Overflow Interrupt Gives the raw interrupt state prior to masking of the Overflow interrupt Pulse Match Interrupt Gives the raw inte
231. atus 1 update abqut 1 ms SYSCLK IMCLK IMCLK SYSCLK EMCLK case pm EMCLK Status 1 update SYSCLK EMCLK EMCLK gt EMCLK Status 1 update SYSCLK PLLCLK case 5 gt PLL Lockup time about 200 us SYSCLK PLLCLK PLLCLK 1 A Figure 5 19 Basic Timer and Exit of Stop Mode when FWAKE is 0 SAMSUNG ELECTRONICS 5 32 ex S3FN429_UM_REV1 20 5 Clock and Power Manager Figure 5 20 illustrates the BT and exit of stop mode when FWAKE is 1 SYSCLK IMCLK Asserted Wakeup event Interrupt System Wakeup RN MODE NORMAL STOP Mode Transition NORMAL Mode Enable or IMCLK Disable Enable EMCLK PLLCLK or IMCLK SYSCLK Figure 5 20 Basic Timer and Exit of Stop Mode when FWAKE is 1 SYSCLK IMCLK SAMSUNG ELECTRONICS 5 33 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 Register Description 5 9 1 Register Map Summary e Base Address 0 4002 0000 Interrupt mask CM_IMSCR 0x0030 Interrupt mask set clear register 0x0000_0000 CM_BTCDR Basic timer clock divider register 0x0000_000X SAMSUNG ELECTRONICS 5 34 S3FN429_UM_REV1 20 5 Clock and Power Manager Resistor Reset vae 0 00 4 Power status register 0x0000_0002 NOTE Smart option decides X value and real reset source decides Y at reset time CM_NISR 0x0098 NVIC interrupt status register 0x0000_0000
232. audRate Selected Clock CD where the selected clock is PCLK 8 or USARTCLK In synchronous mode when the external clock CLKS 1 1 in the Mode Register US is selected the signal directly provides the clock on the USARTCLK pin No division is active The value written in US BRGR has no effect 17 3 1 1 Block Diagram Figure 17 2 illustrates the block diagram of USART BaudRate generator US MR CLKSIO ys MR CLKS 1 US BRGR CD 15 0 CD 15 0 16 bit Counter USARTCLK Baud Rate Clock US MR SYNC US MR CLKS Figure 17 2 USART BaudRate Generator Block Diagram SAMSUNG ELECTRONICS 17 5 ex S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 3 1 2 BaudRate Configuration Example The Table 17 2 describes different registers configuration of the US BRGR register for different core frequency For each case the calculated error shows the difference between the real BaudRate and the expected BaudRate In Table 17 2 CLKS 1 0 00 PCLK selected as USART clock USARTCLK and SYNC 0 asynchronous mode in the US MR register Table 17 2 describes the asynchronous mode SYNC 0 Table 17 2 Asynchronous Mode SYNC 0 SAMSUNG ELECTRONICS 17 6 S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter a 88 2800008 34 4 99 9 8 m 995 SAMSUNG ELECTRONICS 477 27
233. being received by the USART 1 No frame is being received by the USART IDLEFLAG This bit indicates a frame transmission in J1587 protocol It is turned low when a reception starts and turned high when a reception is followed by at least 10 stop bits 10 bits at high level Idle Interrupt IDLE 0 end of J1587 protocol frame 1 An end of J1587 protocol frame occurs 9 Transmitter Empty 0 There are characters in either US_THR or the Transmit Shift Register TXEMPTY 1 There are no characters in both US_THR and the Transmit Shift Register Equals to zero when the USART is disabled or after reset Transmitter Enable command in US_CR sets this bit to 1 IDLEFLAG IDLE gt gt timeout EET gt e FRAME Time Out 0 There is no time out since the last Start Time out TIMEOUT command or the Time Out Register is 0 1 There is a time out since the last Start Time Out command Parity Error 0 No parity bit is detected false or a parity bit high in PARE multi drop mode since the last Reset Status Bits command 1 At least one parity bit is detected false or a parity bit high in multi drop mode since the last Reset Status Bits SAMSUNG ELECTRONICS 17 38 ex 10 r S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter Framing Error 0 No stop bit is detected low since the last Reset Status Bits command 1 A
234. bes the relation between the ICNUMx values and input selected Table 4 4 ICNUMXx Value and Selected Input For example assume e CONT 3 0 0x2 e ICNUMO 3 0 0x5 AINO5 e I CNUM1 3 0 0 2 AINO2 e I CNUM2 3 0 0 1 AINO1 After a start conversion request ADC converts input 5 AINO5 then input 2 AINO2 and it finishes by converting input 1 AINO1 Each converted data is saved in CRR5 CRR2 and register You can get information of current conversion channel and conversion count value from ADC Sequence State Register ADC 558 SAMSUNG ELECTRONICS 4 6 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 1 6 2 One Shot Conversion Mode The ADC programs in two modes The two modes are e One Shot conversion mode e Continuous conversion mode Enable one shot conversion mode by setting control register bit to 0 In this mode the ADC performs the complete conversion of sequence at conversion start request and it stops It waits for another start request The ADC does not stops until it finishes the conversion sequence Figure 4 3 illustrates single channel conversion for one shot mode CSTOP ICNUMx EOC Int Req Figure 4 3 One Shot Mode Single Channel Conversion Figure 4 4 illustrates multi channel conversion for one shot mode CSTOP BUSY ____ Lo AIN6 AIN9 AIN7 AIN5 ICNUMx l EOC Int Req Figure 4 4 One Shot Mode Multi Chann
235. ble in 44 QFP e Width x Length 10 0 mm x 10 0 mm e Lead pitch 0 8 mm SAMSUNG ELECTRONICS 1 Product Overview S3FN429_UM_REV1 20 1 Product Overview 1 3 Block Diagram Figure 1 1 illustrates the block diagram of S8FN429 device E INTMI Interrupts Cortex 0 ae E Peripheral IRQ Cortex MO SWDBG APB AHB2APB Internal Flash 32KB nRESET XIN Figure 1 1 Block Diagram SAMSUNG ELECTRONICS i lt S3FN429_UM_REV1 20 Pin Configuration 2 1 Overview The Pin Configuration chapter describes the pin information of SSFN429 This chapter includes Pin map diagram Pin assignment table Mirror pins Pin description Power pins System pins Function pins Debug interface pins Flash serial program pins Pin circuit type TypeA pins nReset SAMSUNG ELECTRONICS 2 1 2 Pin Configuration S3FN429_UM_REV1 20 2 Pin Configuration 2 2 Pin Map Figure 2 1 illustrates the pin map for SSFN429 device 40 P0 26 COMP2_N USARTRXO EXI18 39 P0 25 COMP1_P FSS0 COP4 38 0 24 1_ 2 P0 23 COMP0_P MOSI0 PWM1 P0 22 COMPO N MISOO EXI17 P0 21 PHASEZ USARTCLKO EXI16 43 P0 29 COMP3 P EXI21 SWDCLK P0 20 PHASEB USARTTXO EXI15 42 P0 28 COMP3 N EXI20 SWDIO 41 P0 27 COMP2 P USARTTXO EXI19 Qa PLLCAP P0 19 PHASEA USARTRXO EXIH 4 P0 18 PWMOFF COPS EXI13 VDDIO VSSIO S3FN429 P0 17
236. bles 1 Enables 1 This bit controls the LVD Reset To use the L VD Reset you should set this bit to 1 LVDRL fields decide the target voltage to detect LVD Reset Level refer to Electrical Data chapter 000 LVD LEVELS Typical 2 4 V Reset Value 001 LVD LEVELA Typical 2 6 V 010 LVD LEVEL3 Typical 2 8 V 011 LVD_LEVEL2 Typical 3 8 V 100 LEVEL1 Typical 4 3 V Others You should not set other values iL 5 47 S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 1 9 CM_MR1 e Base Address 0x4002 0000 e Address Base Address 0x002C Reset Value 0x0000 001X 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 Timer Clock Source Selection Bits 00 EMCLK 01 IMCLK 10 PLLCLK 11 Disconnects WDTCLK NOTE 1 If you try to change the clock source when the target clock source to exchange is in disable state then the value does not change and command error occurs When WDTCLK 5 4 RW the command error occurs the CMDERR bit becomes 1 2 When switched clock becomes stable after you switch on the clock source the WDTCLK interrupt occurs You can use WDTCLK interrupt event to check that WDTCLK switching completes or not If you change the value of the WDTCLK to 11 b disconnect WDTCLK then the WDTCLK interrupt does not occur 3 When you do not run the WDTCLK and want to reduce the power it is recommended to use the Disconnect
237. bles FWAKE After Wake Up SYSCLK becomes IMCLK SYSCLK Clock Stable Status Bit STABLE 4 1 Clock source switching for SYSCLK completes and 1 status becomes stable WDTCLK Status Bit WDTCLKS 3 0 WDTCLK inactive status 1 WDTCLK active status mv ___ _ a Internal Main Clock Status IMCLK 1 0 Disables IMCLK 1 Enables and stabilizes IMCLK rework R Eemal Cock Situs i SAMSUNG ELECTRONICS 5 58 en S3FN429_UM_REV1 20 5 Clock and Power Manager 0 Disables EMCLK 1 Enables and stabilizes EMCLK CM_SR 81 24 bits are Read and Write After checking the status of each reset you should clear each bit of CM_SR 81 24 by writing 1 NOTE Command Error Event Command error occurs at these events 1 If you disable the IMCLK when the Clock Monitor function is enabled then command error occurs If you want to disable the IMCLK when the Clock Monitor function is enabled you should disable the Clock Monitor function 2 If you enable the clock monitor function when the IMCLK is disabled then the command error occurs If you want to enable the Clock Monitor function then you should enable the IMCLK Caution If you don t the external main oscillator when and pin8 are defined XOUT and XIN function you should tie XIN to ground XOUT should be opened SAMSUNG ELECTRONICS 5 59 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 1 15 CM_SCDR e Base Addr
238. ccurs when writing the undefined value CMD 2 0 111b into CMD field of a control register Sequence according to the each interrupt is e END Enable END interrupt IMSCR register Configuration for a target operation KEY AR or DR register Start the operation by a command CR register END interrupt occurs MISR register Clear an END interrupt ICR register Finish e ERRO Enable ERRO interrupt IMSCR register Configuration for a target operation KEY AR or DR register Start the operation by a command CR register ERRO interrupt occurs MISR register Clear an ERRO interrupt ICR register Wait END status interrupt RISR MISR register Clear an END status interrupt ICR register Finish e or ERR2 Enable ERR1 or ERR2 interrupt IMSCR register Configuration for a target operation KEY AR or DR register Start the operation by a command CR register ERR1 or ERR2 interrupt occur MISR register Clear an ERR1 or ERR2 interrupt ICR register Finish SAMSUNG ELECTRONICS 9 14 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 2 3 2 Tool Mode Tool program mode is a flash memory program mode that uses an equipment tool such as AS pro Flash ROM Writer To program with Tool Program Mode MODE1 and MODEO should be set as Tool Mode Refer to Pin Configuration chapter The microcontroller has several pins u
239. ch of IMCNT is used for OSEL 1 RW ADC trigger signal not 0 Does not select 1 Selects ADC Start Trigger Signal by TOPCMP Match This bit determines whether TOPCMP match of IMCNT is TOPCMPSEL RW used for ADC trigger signal or not 0 Does not select 1 Selects NOTE 1 The ADC conversion should not be overlapped by setting the appropriate value to each compare register 2 The setting of IMC_ASTSR register bit does not affect interrupt generation 3 When IMC is in an Saw Tooth wave mode the values of ADCCMPFOSEL ADCCMPF1SEL and ADC MPF2SEL bit do not have any effect in operation SAMSUNG ELECTRONICS 10 60 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 3 1 21 IMC_ASCRRO Base Address 0 400 0000 Address Base Address 0x0050 Reset Value 0 0000 0000 31 30 29 28 27 26 25 24123 22 21 20 19 18 17 16 15 14 13 12 11 10 o gt o ADCMPRODAT EXER es RIR R R R R R R R R RSVD Resena ADC Compare Data 0 for Rising time ADCMPRODAT 15 0 RW This field determines the ADC compare register value at 0x0000 rising SAMSUNG ELECTRONICS 10 61 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 3 1 22 IMC_ASCRR1 Base Address 0x400B_ 0000 e Address Base Address 0x0054 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24123 22 21 20
240. ch of down side is high active 2 For 100 duty of upside you should set the rising falling compare register to For 0 duty of upside you should set the rising compare register to equal to TOPCMP value SAMSUNG ELECTRONICS 10 14 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 2 3 8 Tri Angular Wave IMMODE 0 PWMSWAP 1 PWMPOLU 1 High Start and PWMPOLD 1 High Start Figure 10 14 illustrates the Tri Angular wave SWAP a High Start PWMxUy and High Start PWMxDy ASCRR1 eR pee e eo m n t x eti duc illatis IMC_ASCFR2 IMC_ASCRRO e es te e f i E IMC_PACRR s s e Dex col TEMA RNC ME d IMC_ASCFRO e PWMxUO PWMxU1 PWMxU2 PWMxDO PWMxD1 PWMxD2 Interrupt Can be used by ADC trigger signal Figure 10 14 Tri Angular Wave SWAP a High Start PWMxUy and High Start PWMxDy NOTE 1 The switch of upside is high active and the switch of down side is low active 2 For 0 96 duty of upside you should set the rising falling compare register to For 100 96 duty of upside you should set the rising compare register to equal to TOPCMP value SAMSUNG ELECTRONICS 10 15 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 2 3 9 Saw Tooth Wave IMMODE 1 PWMSWAP 0 PWMPOLU 0 Low Start and PWMPOLD 1 High Start Figure 10 15 illustrat
241. chdog Pending masked interrupt Status Gives the masked interrupt status after masking of the WDTPEND interrupt 0 The WDTPEND interrupt does not occur 1 The WDTPEND interrupt occurs NOTE On a Read WDT MISR register gives the current masked status value of the corresponding interrupt SAMSUNG ELECTRONICS 18 13 ex S3FN429_UM_REV1 20 18 Watchdog Timer 18 3 1 9 WDT_ICR e Base Address 0 4003 0000 e Address Base Address 0x0020 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24123 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 gt www weno e Watchdog Overflow Clear 0 No effect 1 Clears Watchdog overflow interrupt Watchdog Pending Clear 0 No effect 1 Clears Watchdog pending interrupt SAMSUNG ELECTRONICS 18 14 ex S3FN429_UM_REV1 20 18 Watchdog Timer 18 3 1 10 WDT PWR e Base Address 0x4003 0000 Address Base Address 0x0024 Reset Value OxOOFF_FFOO 30 29 28 27 26 25 24 23 22 21 20 19 48 17 16 15 14 13 12 11 R R R R R R wy wy ww Ww WIW W W Ww RSTALW Pending window access key This is used only when writing in WDT PWR PWKEY is 24 W iid Eben read as 0 Allows Write access in PWR only if PWKEY 7 0 0x91 Pending Window Length PWL pasaj artha window OxFFFF The time difference between preload value and watchdog timer pending is PCV 15 0 PWL 15 0 WDTCLK freq aR Resend 92 Restart
242. configuration GPIO Interrupt Mask Set and Clear Raw Interrupt Status Masked Interrupt Status Clear Interrupt 8 1 2 Pin Description Table 8 1 describes GPIO pin description Table8 1 GPIO Pin Description PO 31 0 General Purpose Input Output Reset Input Status NOTE P0 30 and 0 31 are defined as XOUT and XIN function by fabrication But you can change the function by using Smart Option program Refer to IFC chapter SAMSUNG ELECTRONICS 8 1 227 S3FN429_UM_REV1 20 8 General Purpose I O GPIO 8 2 Functional Description This section describes GPIO Configuration Input Configuration Output Configuration Operation Mode and Interrupt 8 2 1 GPIO Configuration Pins have their multiplexed functions from 0 to 3 IOCONF defines these functions After IOCONF has defined multiplexed pins as GPIO pins you should configure the GPIO Therefore it is necessary to control IOCONF before using the GPIO Each of 32 bits of control registers such as enable disable and status registers is corresponding to individual I O ports You can either configure I O port individually or you can configure the entire port by writing a value to the 32 bits register Before configuring I O ports it is mandatory to enable the clock supply to the I O ports The registers responsible for clock supply are e Clock Enable Disable Register GPIO_CEDR e Software Reset Register GPIO_SRR It is also possible to reset each of GPIO block
243. corresponding GPIO is output on this line SAMSUNG ELECTRONICS 8 15 27 S3FN429_UM_REV1 20 8 General Purpose I O GPIO 8 3 1 11 GPIO_WODR e Base Address 0x4005 0000 e Address Base Address 0x0028 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 29 28 27 26 25 24 23 22 21 20 19 18 17 16 22 21 20 19 18 17 16 15 14 1 12 11 10 9 14 13 12 1 Bee eee ee ee a Port y Output Data Control Bit 0 Programs GPIO output data on the corresponding pin to 0 Low Level 1 Programs GPIO output data on the corresponding pin Py y W to 1 High Level The purpose of GPIO_WODR register is similar to GPIO_SODR and GPIO_CODR But the output data 1 and 0 affects it at the same time This function differs from the GPIO_SODR and GPIO_CODR SAMSUNG ELECTRONICS 8 16 ex S3FN429_UM_REV1 20 8 General Purpose I O GPIO 8 3 1 12 GPIO_SODR e Base Address 0x4005 0000 e Address Base Address 0x002C Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 29 28 27 26 25 24 23 22 21 20 19 18 17 16 22 21 20 19 18 17 16 15 14 13 12 11 10 14 13 12 1 Bonam ES Port y Output Data Set 1 Py 0 effect 1 Sets GPIO output data on the corresponding pin You can read the result through GPIO PDSR register SAMSUNG ELECTRONICS 8 17 27 S3FN429_UM_REV1 20 8 General Purpose I O GPIO 8 3 1 13 GPIO_CODR e Base Address 0x4005 0000 e Address Base Address 0x0030 Reset V
244. ction Bit 000 Specifies PHASEA signal is the external signal asserted on PHASEA pin Do not use the signal asserted from COMP as PHASEA 001 Use the signal asserted from COMPO as PHASEA 010 Use the signal asserted from COMP1 as PHASEA 011 Use the signal asserted from COMP2 as PHASEA 100 Use the signal asserted from COMP3 as PHASEA Others Not used 2 PHASEA 10 8 Speed Counter Direction Up or Down Control Bit 1 0 Speed counter does not use DIRECTION status which Pulse Position Decoder Type Analyzer detects Speed SCDCTRL RW counter always increases 1 Speed counter uses DIRECTION status which Pulse Position Decoder Type Analyzer detects Speed counter increases or decreases according to the DIRECTION SAMSUNG ELECTRONICS 7 11 S3FN429_UM_REV1 20 7 Pulse Position Decoder information E Pulse Position Decoder Type Selection Bits The pulse position decoder type analyzer block generates direction and input signal for speed and position counter with this value 00 The way to use a pulse position decoder type 0 01 The way to use a pulse position decoder type 1 10 The way to use a pulse position decoder type 2 11 Not used 2 e The feature of Type 1 is The difference of phase between phase A and phase B PPDTYPE 5 4 pulse is 90 e The feature of Type 2 is The input of PHASEA is Clockwise CW signal The PCR up counts using PHASEA pulse The inp
245. d Disables the interrupt 1 RxFIFO written to while full condition interrupt is not masked Enables the interrupt E o Receive FIFO Interrupt Mask 0 Rx FIFO trigger level 1 2 1 4 or 1 8 condition interrupt is masked Disables the interrupt 1 Rx FIFO trigger level 1 2 1 4 or 1 8 condition interrupt is not masked Enables the interrupt NOTE On a Read SSP_IMSCR register gives the current value of the mask the relevant interrupt A Write of 1 to a particular bit sets the mask thus enabling the interrupt to be read A Write of 0 clears the corresponding mask SAMSUNG ELECTRONICS 15 24 x S3FN429_UM_REV1 20 15 Serial Peripheral Interface SPI 15 3 1 7 SSP_RISR e Base Address 0x4009 0000 0x4009 1000 e Address Base Address 0x0018 Reset Value 0x0000 0008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 Transmit FIFO Raw Interrupt State Gives the raw interrupt state prior to masking of the SSPTXINTR interrupt Receive FIFO Raw Interrupt State Gives the raw interrupt state prior to masking of the SSPRXINTR interrupt Receive Timeout Raw Interrupt State Gives the raw interrupt state prior to masking of the SSPRTINTR interrupt Receive Overrun Raw Interrupt State Gives the raw interrupt state prior to masking of the SSPRORINTR interrupt NOTE On a Read SSP_RISR register gives the current raw status value of the corresponding interrupt prior to
246. d 40 MHz Table 5 11 describes the 256 counting time by BT Table 5 11 256 Counting Time by BT The SYSCLK source and the BT clock divider in smart option decide the BT counting frequency MCU releases the chip reset when BT completes 256 counting To optimize on system you can change the reset release time by BT You can do this by re programming the flash smart option SAMSUNG ELECTRONICS 5 30 ex S3FN429_UM_REV1 20 5 Clock and Power Manager Figure 5 16 illustrates the BT count in reset sequence VDD Regulator Released core runs Internal RESET Internal Voltage lt lt Tbt SYSCLK IMCLK or EMCLK Basic Timer Start amp Counting Figure 5 16 RESET EMCLK Internal VDD Timing 4 Ts Released core runs RESET SYSCLK Ts The time for an internal initialization 1ms init clock stabilization smart option configuration internal trimming etc Tbt The time for a system initialization by basic timer It can be configurable because a clock divider for basic timer is decided by smart option If user wants to optimize the start up time user can use it considering the condition i e clock source of a target system Figure 5 17 Start Up with Basic Timer The Ts Tbt value which is defined as 1st code run from exit of reset
247. ddress 0x0004 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 14 13 12 11 10 9 8 RSTKEY m o a apes sls EPIS EIE EE Sk mme Descrip DBGEN 81 Debug Enable Disable Control Bit 0 Disables debug mode The WDT counter keeps W running when a debug is requested 1 Enables debug mode The WDT counter stops running when a debug is requested ___ US A Reeve Restart Key Field 0xC071 Restarts the Watchdog counter if its value is RSTKEY 15 0 equal or less than the length of a pending window or if the pending window is disabled Other values No effect NOTE A restart command write the restart key in WDT_CR will be effective if Watchdog counter becomes greater than 2WDTCLK 1 2 FIN periods SAMSUNG ELECTRONICS 18 7 ex S3FN429_UM_REV1 20 18 Watchdog Timer 18 3 1 3 WDT_MR e Base Address 0 4003 0000 Address Base Address 0x0008 Reset Value OxOOFF_FFO7 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 gt a Clock Access Key Field CKEY 31 24 is used only when writing is read as Allows Write access in MR only if CKEY 7 0 0x37 Preload Counter Value PCV 23 8 RW Preloads the counter when watchdog counter restarts OxFFFF Time to generate overflow PCV 15 0 WDTCL
248. des either normal mode or tool mode If on board writing programming in tool mode is needed 0 1 uF capacitor should be connected between MODEO pin and ground Parallel 4 resistor should be connected for better noise immunity 3 MODE But if you use S8FN429 only in normal mode without MODEO on board writing this pin should be connected to Internal ground directly pull down Mode modeo Mode Setting o NomaiMode 0 1 Caution If you don t the external main oscillator when pin7 and pin8 are defined XOUT and XIN function you should tie XIN to ground XOUT should be opened SAMSUNG ELECTRONICS 2 7 ex S3FN429_UM_REV1 20 2 Pin Configuration NOTE 1 After reset the default function of pin8 can be one of two One is XIN the other is P0 30 The hardware reset condition is decided by smart option That means you need to program the chip configuration smart option if you want to change that pin s reset function You can program and erase the smart option in normal or tool mode Refer to Chapter 9 Internal Flash Controller IFC 2 After reset the default function of pin7 can be one of two One is XOUT the other is 31 The hardware reset condition is decided by smart option That means you need to program the chip configuration smart option if you want to change that pin s reset function You can program and erase the smart option in normal or tool mode Refer to Chapter 9 Internal Flash Controller IFC
249. ding area is disabled Svo Gu R rese This register shows the Smart Option value Programmed smart option affects on hardware after chip reset After chip reset the value to read is real current smart option status The reset value of fabrication is OxFFFFFFFF but you can change the value using Smart Option Program SAMSUNG ELECTRONICS 9 41 x S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 3 1 15 SO_CSR e Base Address 0x4001_0000 e Address Base Address 0x0038 Reset Value OxFFFF_FFFF Timer Divider selection bit in the reset time 0000 0001 0010 Not used 0011 1 0100 22 0101 24 0110 8 0111 16 15 12 1000 32 1001 64 1010 128 1011 256 1100 512 1101 1024 1110 2048 1111 4096 External Main Clock Input Output Pin Configuration Bit 0 Configure IO pin as the corresponding pin 1 Configure XOUT as the corresponding pin External Main Clock Input Output Pin Configuration Bit 0 Configure IO pin as the corresponding pin 1 Configure XIN as the corresponding pin mv m A 1 1 Power On CPU system Clock Selection Field When Power On the selected clock source by Smart Option is used for operation CPU Clock 0 Selects EMCLK External Main Clock 1 Selects IMCLK Internal Main Clock SAMSUNG ELECTRONICS 9 42 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC Control bits are related to Clock Manager for chip operation You can c
250. disabling the appropriate bits in the registers under software control Enters by sleep command that belongs to the Cortex MO e STOP MODE This mode stops all clocks and operations SAMSUNG ELECTRONICS 5 3 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 1 2 Block Diagram Figure 5 1 illustrates the system clock tree block diagram PLL PLLCLK r CORECLK amp Coretex EMOSC EMCLK SYSCLK LK SRAM Flash En Dis gt Debug IMOSC En Dis 8 Systic Timer P gt Peripheral x lt gt EMCLK 8 lt MCLK 8 Camm PLLCLK gt lt PCLK 8 EMCLK WDT FIN clock x Figure 5 1 System Clock Tree Block Diagram Table 5 1 describes the clock definition Table 5 1 Clock Definition mms O FCLK Free running clock for Cortex MO SYSCLK SDIV oe Cortex MO clock and AHB bus peripherals clock SYSCLK SDIV STCLK Sys tick timer clock in cortex MO SYSCLK SDIV 8 PCLK Peripherals clock SYSCLK SIDV PDIV NOTE 1 Configurable SDIV 1 2 3 4 5 6 7 or 8 2 Configurable PDIV 1 2 4 8 or 16 SAMSUNG ELECTRONICS 5 4 en S3FN429_UM_REV1 20 5 Clock and Power Manager 5 2 Clocks 5 2 1 SYSCLK The Sys
251. dress Reeve Stating vaveofMSP 000 1 ooexmw Re 1 Resend CS Rem O SAMSUNG ELECTRONICS 11 2 ex S3FN429_UM_REV1 20 11 Interrupt Controller INTC 11 2 1 2 Device Interrupt Vector Table 11 2 describes the device interrupt vector for 5 429 Table 11 2 Device Interrupt Vector Num Address Vector Name iOS 0 WOT Reter to watchdog timer intrupt register 00000 0060 PPD PPD Poston countrcapture and phasez SAMSUNG ELECTRONICS 11 3 27 S3FN429_UM_REV1 20 11 Interrupt Controller INTC 11 2 2 Block Diagram VECTOR x IRQx Interrupt Line Active 2 VECTOR Y RQy Interrupt Line Active VECTOR S RQs Interrupt Line Active Block Y Cortex MO Figure 11 1 Interrupt Block Diagram SAMSUNG ELECTRONICS 7 S3FN429_UM_REV1 20 11 Interrupt Controller INTC Figure 11 1 is the block diagram to show the connection and relationship between device interrupt sources and interrupt vectors Each vector has one or several interrupt event sources Each interrupt event source has control and status bits as follows interrupt mask set clear raw interrupt status masked interrupt status and interrupt clear bit That control should be done at each block The specific interrupt source in some blocks has one
252. e e PACRR Ga ee a Wate ys PWMxU1 PWMxU2 PWMxDO PWMxD1 PWMxD2 Interrupt Can be used by ADC trigger signal Figure 10 21 Saw Tooth Wave SWAP a High Start PWMxUy and Low Start PWMxDy NOTE 1 Both the switches of upside and down side are low active 2 For 0 duty of upside you should set the rising falling compare register to For 100 duty of upside you should set the rising compare register to equal to TOPCMP value SAMSUNG ELECTRONICS 10 22 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 2 3 15 Saw Tooth Wave IMMODE 1 PWMSWAP 0 PWMPOLU 1 High Start and PWMPOLD 1 High Start Figure 10 22 illustrates the Saw Tooth wave No SWAP a High Start PWMxUy and High Start PWMxDy TCR o tt tt n ASCRR2 m m m m D m m PCCRR s o n IMG ASCRR1 es AG PBCRR IMC_ASCRRO PWMXxUO PWMxU1 PWMxU2 PWMxDO PWMxD1 PWMxD2 Interrupt Can be used by ADC trigger signal Figure 10 22 Saw Tooth Wave No SWAP a High Start PWMxUy and High Start PWMxDy NOTE 1 The switch of upside is low active and the switch of down side is high active 2 For 100 95 duty of upside you should set the rising f
253. e ADCRW2 interrupt ADC 1 Falling Match Masked Interrupt State ADCFM1 Gives the masked interrupt state prior to masking of the ADCFM1 interrupt ADC Compare Rising Match Masked Interrupt State ADCRM1 Gives the masked interrupt state prior to masking of the ADCRMI interrupt ADC Compare Falling Match Masked Interrupt State ADCFMO Gives the masked interrupt state prior to masking of the ADCFMO interrupt ADC Rising Match Masked Interrupt State ADCRMO Gives the masked interrupt state prior to masking of the interrupt TOP Match Masked Interrupt State Gives the masked interrupt state prior to masking of the TOP interrupt ZERO Match Masked Interrupt State Gives the masked interrupt state prior to masking of the ZERO interrupt FAULT Masked Interrupt State SAMSUNG ELECTRONICS 10 47 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC Gives the masked interrupt state prior to masking of the FAULT interrupt NOTE 1 Ona Read the IMC_MISR register gives the current masked status value of the corresponding interrupt 2 AWrite has no effect SAMSUNG ELECTRONICS 10 48 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 3 1 11 IMC_ICR Base Address 0 400 0000 e Address Base Address 0x0028 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 ADCFM1 ADCFM2
254. e the PARE bit in the US_SR register is set when the data is identified as an address byte The PARE status bit in the US_SR register is cleared by setting the PARE bit in the US_CSR Clear Status Register to 1 If the parity bit is detected low the data is identified as an address byte and PARE bit in the US_SR register is not set The transmitter sends an address byte parity bit set wnen a Send Address Command SENDA is written to US_CR In this case the byte written to US_THR immediately after setting SENDA bit in the US_CR is transmitted as an address After this transmission any byte transmitted will have the parity bit cleared SAMSUNG ELECTRONICS 17 16 ex S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 6 Break The break section includes e Transmit Break e Receive Break e Interrupts e Test Modes e Smart Card Protocol e Character Transmission to Smart Card e Character Reception from Smart Card e USART Configuration in Smart Card Mode 17 6 1 Transmit Break The transmitter generates a break condition on the USARTTX line when the STTBRK Start Break command is setto 1 in US CR Control Register In this case the characters present in the Transmit Shift Register will complete before the line is held low To remove this break condition on the USARTTX line the STPBRK command in US CR should be set The USART generates a minimum break duration of one character length The USAR
255. e 125 is a trademark of Phillips Electronics e 2C is a trademark of Phillips Semiconductor Corp e and Slimbus are registered trademarks of the Mobile Industry Processor Interface Alliance All other trademarks used in this publication are the property of their respective owners SAMSUNG ELECTRONICS 227 Chip Handling Guide Precaution against Electrostatic Discharge When using semiconductor devices ensure that the environment is protected against static electricity 1 Wear antistatic clothes and use earth band 2 All objects that are in direct contact with devices must be made up of materials that do not produce static electricity 3 Ensure that the equipment and work table are earthed Use ionizer to remove electron charge Contamination Do not use semiconductor products in an environment exposed to dust or dirt adhesion Temperature Humidity Semiconductor devices are sensitive to e Environment e Temperature e Humidity High temperature or humidity deteriorates the characteristics of semiconductor devices Therefore do not store or use semiconductor devices in such conditions Mechanical Shock Do not to apply excessive mechanical shock or force on semiconductor devices Chemical Do not expose semiconductor devices to chemicals because exposure to chemicals leads to reactions that deteriorate the characteristics of the devices Light Protection In non Epoxy Molding Compound E
256. e 2 3 Power Pin Description Pin Name Function Description Commens Fvsscone ___ CoreGroundvotage Sd vso Sid Power avss ADC Ground Voltage p AVREF ADC Reference InputVoltage o O VDDCOREOUT Cap Output Port from Internal Connected to GND through a 0 1 uF Regulator capacitor From internal regulator PLLCAP Cap Output Port for PLL Connected to GND through a 220 pF capacitor for PLL SAMSUNG ELECTRONICS 2 6 ex S3FN429_UM_REV1 20 2 Pin Configuration 2 5 2 System Pins Table 2 4 System Pin Description Hardware Reset Input This nRESET pin contains an internal pull up resistor typical 250 Setting this pin to low level initialize the internal state of the device Thereafter setting the input RESET RESET to high release the reset status The S3FN429 waits for the system clock to be stabled and the the reset interrupt vector Internal Reset is generated after clock stabilization XIN 1 External Main Oscillator Input 1 XOUT 2 External Main Oscillator Output Alo CM Internal Clock Out Port EMCLK 8 COP1 IMCLK 8 COP2 PLLCLK 8 COP 4 0 COPS CORECLK 8 COP4 PCLK 8 These pins help you to check clock status when your system has some problem or you are sure about programmed clock configuration Mode Selection Internal MODE1 is for a factory test so it should be connected pull down with ground in user mode This pin deci
257. e AMBA system hierarchy The AMBA APB groups narrow bus peripherals to avoid loading the system bus and provides an interface using memory mapped registers that can be accessed under programmed control 15 2 2 1 2 2 Register Block The register block stores the data written or to be read across the AMBA APB interface 15 2 2 1 2 3 Clock Pre Scaler When configured as a master an internal pre scaler comprising of two free running reloadable serially linked counters is used to provide the serial output clock SSPCLKOUT The clock pre scaler is programmable through the SSPCPSR register that divides the FSSPCLK by a factor of 2 to 254 in steps of two By not utilizing the least significant bit of the SSPCPSR register division by an odd number is not possible ad this ensures a symmetrical equal mark space ratio clock is generated The output of the pre scaler is further divided by a factor of 1 to 256 through the programming of the SSPCRO control register to give the final master output clock SSPCLKOUT 15 2 2 1 2 4 Transmit FIFO The common Transmit FIFO is a 16 bit wide 8 locations deep FIFO memory buffer CPU data written across the AMBA APB interface are stored in the buffer until read out by the transmit logic When configured as a master or a slave parallel data is written into the transmit FIFO prior to serial conversion and transmission to the attached slave or master respectively through the SSPTXD pin 15 2 2 1 2 5 Receive FIFO
258. e Address 0x0004 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 OO o Clock Enable Disable Control Bit 0 Disables OP AMP Clock bit 1 Enables OP AMP Clock bit OP AMP software reset does not affect CLKEN bit status SAMSUNG ELECTRONICS 13 6 ex S3FN429_UM_REV1 20 13 Operational Amplifier 13 2 1 3 OPA_SRR e Base Address 0 4004 1000 e Address Base Address 0x0008 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 1 0 Reserved Software Reset 0 No effect 1 Performs OP AMP software reset Software Reset operation SAMSUNG ELECTRONICS 13 7 ex S3FN429_UM_REV1 20 13 Operational Amplifier 13 2 1 4 OPA_CR e Base Address 0 4004 1000 e Address Base Address 0x000C Reset Value 0x0000 0000 W o o mem OP AMP Enable Bit 0 Disables OP AMP 1 Enables OP AMP NOTE If OP AMP is enabled P0 2 should be set to OP AMP output pin SAMSUNG ELECTRONICS 13 8 27 S3FN429_UM_REV1 20 13 Operational Amplifier 13 2 1 5 OPA_GCR e Base Address 0 4004 1000 Address Base Address 0x0014 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 W IW W W CNN AMP Gain Control Type Selection Bit HW Selects external gai
259. e Internal Interrupt Request 18 2 3 1 Internal Chip Reset Pulse Generation If the RSTEN bit is set in the register then it generates an internal system chip reset pulse when the overflow occurs After a reset the clock selected by the Watchdog Timer is FIN 512 18 2 3 2 Internal Interrupt Request The Watchdog generates an Internal Interrupt Request when the overflow occurs You can enable or disable the state by using the WDT module IMSCR register configuration How to use the Watchdog Timer Use the windows to generate an interrupt and reload the Watchdog counter within the windows only If there is a bug and the interruption is not called then a reset occurs when the Watchdog counter reaches 0 18 2 3 3 Configuration The four types of configurations are e Configuration of WDT MR Choice of the clock to decrease counter preload value from where counter starts to decrease e Configuration of WDT PWR This is the upper limit of the window from where it generates an interrupt when reached The bit restarts the counter only within this window e Configuration of WDT IMSCR It enables Interrupt at the peripheral level when the window is reached upper limit bit WDTPEND or when the counter overflows bit WDTOVF if watchdog reset is not enabled Then you should configure the interrupt mask e Configuration of WDT It enables the Watchdog starts decrementing the counter and enables the Watchdog rese
260. e Raw Interrupt Status Register GPIO RISR e Masked Interrupt Status Register GPIO MISR e Interrupt Clear Register GPIO Corresponding bits in the GPIO IMSCR enables or disables the interrupt for a pin When an edge transition occurs on a pin the corresponding bit in the GPIO RISR register is set to 1 If a bit in GPIO IMSCR register is set to 1 then an interrupt for the pin is enabled The PIO interrupt is cleared when 1 is set to a corresponding bit of register NOTE The interrupt registers mentioned above are different types of interrupt from the external interrupt in the Clock Manager CM SAMSUNG ELECTRONICS 8 4 ex S3FN429_UM_REV1 20 8 General Purpose I O GPIO 8 3 Register Description 8 3 1 Register Map Summary e Base Address 0x4005 0000 Resistor Reset vame GPIO_OSR 0x0024 Output status register 0x0000_0000 SAMSUNG ELECTRONICS 8 5 ex S3FN429_UM_REV1 20 8 General Purpose I O GPIO 8 3 1 1 GPIO_IDR e Base Address 0x4005 0000 e Address Base Address 0x0000 Reset Value 0x0001 0020 Identification Code Register 0x0001_ 0020 This field stores the ID code for the corresponding IP SAMSUNG ELECTRONICS 8 6 ex S3FN429_UM_REV1 20 8 General Purpose I O GPIO 8 3 1 2 GPIO_CEDR e Base Address 0x4005 0000 e Address Base Address 0x0004 Reset Value 0x0000 0000 31 30 29
261. e SYSCLK Yes PLLCLK from EMCLK to other CM PDPR value Setting P M S value No Y Check IMCLK status CM_PSTR value Setting Stabilization Time CM_SR gt IMCLK 1 Y CM CSR2PLL 71 Enable PLL lt M ____ PLL stat s IMCLK SDIV gt 20MHz 1 No Yes Yes PLLCLK SDIV gt 20MHz CM PCSR 2S IFCCLK 1 Enable Flash Gate Clock CM PCSR gt IFCCLK 1 No Y Enable Flash Gate Clock CEDR 2 CLKEN 1 Y Enable Flash Clock IFC_CEDR gt CLKEN 1 Y Enable Flash Clock MR gt FSMODE 1 Y Enable Fast Mode IFC MR gt FSMODE 1 Enable Fast Mode Y Y Clear STABLE pit Clear STABLE bit CM_ICR gt STABLE 1 CM_ICR gt STABLE 1 Y Change SYSCLK Change SYSCLK _ 1 _ 1 amp 0 3 10 1 _ 1 iM R1 amp 0x3 0x2 lt 5 SR gt STABLE 1 a gt STAB Y Run by CORECLK IMCLK SDIV Run by CORECLK EMCLK SDIV Run by CORECLK PLLCLK SDIV Figure 5 21 Clock Initialization when Reset Value of SYSCLK is EMCLK SAMSUNG ELECTRONICS 5 76 S3FN429_UM_REV1 20 5 Clock and Power Manager Reset ID check CM SR amp OxDF000000 Recommend corresponding service execution according to the reset source SYSRSTS EMCMRSTS PORR
262. e asynchronous mode character reception Example 8 Bit Parity enabled 1 Stop 0 5 Bit 1 Bit Periods Periods 4 gt 4 gt Sampling ity DO D1 D2 D3 D4 D5 D6 D7 Stop Bit True Start Parity Bit Detection Figure 17 4 Asynchronous Mode Character Reception SAMSUNG ELECTRONICS 17 12 iD S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 4 2 Synchronous Receiver When the receiver is configured for synchronous operation SYNC 1 it samples the RXD signal on each rising edge of USARTCLK If a low level is detected then it is considered as a start After sampling data bits parity bit and stop bit the receiver waits for the next start bit Figure 17 5 illustrates the Synchronous mode character reception diagram USARTCLK RXD Sampling DO D1 D2 D3 D4 D5 D6 D7 Stop Bit True Start Parity Bit Detection Figure 17 5 Synchronous Mode Character Reception 17 4 2 1 Receiver Ready When a complete character is received it is transferred to the US_RHR and then the RXRDY status bit in US_SR is set 17 4 2 2 Overrun Error If the US_RHR register has not been read since the last transfer and another character is transferred to the US_RHR register then the OVRE status bit in US_SR register is set 17 4 2 3 Parity Error Each time a character is received the receiver calculates the parity of t
263. e the value to keep When programming smart option user should rewrite them with a changing value END Bit Set SOE Smart Option Erase 110 b Figure 9 9 Smart Option Erase Flowchart SAMSUNG ELECTRONICS 9 21 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 2 5 Error 9 2 5 1 Error Case 0 When a new Read access or normal program occurs while executing normal program operation this new access is not taken into account and an interrupt for error event is generated Figure 9 10 illustrates the Error Case 0 B Start program or erase Error NM A area will destroy and generate bus fault A On programming or erasing CODE Write data toB Executable CODE 1 at CPU RUN option or erase B sector CODEO Write data to A or erase A sector Figure 9 10 Condition SAMSUNG ELECTRONICS 9 22 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC If you perform other operation erase normal program while executing normal program operation that operation is not taken into account and an interrupt for error event is generated Figure 9 11 illustrates the Error Case 0 Error B Start program or erase A area can destroy and generate bus fault CODEO Write data to A or erase A sector A On programming or N SRAM CODE 1 Write data to B or erase sector Figure 9 11 Condition SAMSUNG ELECTRONICS 9 23 ex S3FN429_UM_R
264. eL p PWM output extension status 0 Corresponding extension bits are disabled 1 Corresponding extension bits are enabled Swretched Cycle Number PWMEXBON 9 9 S3FN429_UM_REV1 20 16 Timer Counter ADC Trigger 0 ADC Trigger Signal Out is disabled 1 ADC Trigger Signal Out is enabled If ADC trigger selection field is TC and this bit is set then the ADC conversion starts by Pulse Match event ADTRIG OVFM 14 REPEAT Overflow Mode 0 Period mode is enabled The counter value is increased until the end of period 1 Overflow mode is enabled The counter value is increased until it overflows Repeat Mode 0 Repeat mode is disabled 1 Repeat mode is enabled The counter automatically restarts when it overflows in Overflow mode or the end of period in Period mode Interval Mode 0 The type of output signal is PWM operation PWMIM 11 KEEP 10 OUTSL 1 The type of output signal is Interval operation Keep Stop Level 0 Keep state mode is disabled 1 Keep state mode is enabled When the counter stops the TC keeps the output signal E HE level as the last level regardless of IDLESL Output Start Level 0 The output signal level is LOW when starting 1 The output signal level is HIGH when starting IDLE State Level 0 The output signal level is LOW in Idle state IDLESL 1 The output signal level is HIGH in Idle state 85 0 Stop Count
265. ection flag clock recovery flag and clock monitor reset control After entering into the STOP mode hardware does not affect the clock monitor function After Wake Up from STOP mode the status of the Clock Monitor function will stay as enabled or disabled Figure 5 5 illustrates the clock monitor function diagram EMCLK or EMCLK amp PLL enable IMCLK enable SYSCLK EMCLK or PLLCLK EMCM enable EMCLK fail event is triggered Chip reset by EMCMRST occurs After reset SYSCLK is IMCLK not EMCLK or PLLCLK EMCMRSTS bit in CM SR register is set to 1 NOTE1 EMCMRST don t care Reset ID flag enable or disable i EMCLK or EMCLK amp PLL enable EMCLK fail event IMCLK enable is triggered SYSCLK IMCLK EMCM enable EMCMRST enable Chip reset by EMCMRST occurs After reset SYSCLK is IMCLK not EMCLK or PLLCLK EMCMRSTS bit in CM SR register is set to 1 Reset ID flag EMCLK or EMCLK amp PLL enable EMCLK fail event IMCLK enable is triggered SYSCLK IMCLK EMCM enable NOTE2 EMCMRST disable P Chip reset by EMCMRST does not occur SYSCLK is IMCLK without change EMCKFAIL bit in CM SR register is set to 1 Fail flag Figure 5 5 Clock Monitor Function NOTE 1 Although the reset function by a Clock Monitor is disabled the EMCMRST occurs to make a system safe But you should enable a Clock Monitor function before detecting clock fail 2 Although
266. ed Counter Reference SCRR PPD_IMSCR PPD_RISR L PPD_MISR PHASEZ Figure 7 1 PPD Block Diagram SAMSUNG ELECTRONICS 7 2 x S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 2 2 Operating Mode The Operating Mode section describes the types of operating modes of PPD The modes are e Type 0 e Type 1 e Type 2 7 2 2 1 Type 0 Type 0 includes two modes The two modes are 4 Multiplication Mode 1 Multiplication Mode 7 2 2 1 1 4 Multiplication Mode PPD CRO ESELA 0b10 PPD CRO ESELB 0b10 Use the three input signals PHASEA PHASEB and PHASEZ to measure the position and speed for Type 0 Use 4 multiplication modes if the phase difference between PHASEA and PHASEB pulse is 90 The PHASEZ input generates one pulse signal at specific position 1 cyclic Figure 7 2 illustrates the counter operation for 4 Multiplication Mode PHASEA PHASEB EN ENCSTATUSO DIRECTION 0 1 Figure 7 2 Counter Operation 4 Multiplication Mode SAMSUNG ELECTRONICS 7 3 iD S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 2 2 1 2 1 Multiplication Mode PPD CRO ESELA 0b00 PPD CRO ESELB 0b11 Use the three input signals PHASEA PHASEB and PHASEZ to measure the position and speed of Type 0 Use 1 multiplication mode if the phase difference between PHASEA and PHASEB pulse is not 90 The PHASEZ input generates one pulse signal at specific position 1 cyclic
267. ed interrupt or an external event signal pulse via the RXEV signal Inside the processor there is a latch for events so a past event can wake up a processor from WFE Event lat Y Clear event latch and Enter IDLE Enter STOP continue to next instruction Figure 5 10 Instruction for IDLE and STOP e WFE Wait for Event The WFE instruction The WFE causes an entry into the IDLE STOP mode conditional on the value of a one bit event register When the processor executes a WFE instruction it checks this register Ifthe register is 0 then the processor stops executing the instructions and enters IDLE STOP mode Ifthe register is 1 then the processor clears the register to 0 and continues executing the instructions without entering IDLE STOP mode e WFI Wait for Interrupt The WFI instruction The causes immediate entry into the IDLE STOP mode When the processor executes WFI instruction the WFI stops executing the instructions and enters the IDLE STOP mode SAMSUNG ELECTRONICS 5 18 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 4 2 1 Enter IDLE Mode The Idle mode is applicable when it requires Wake up with the minimum latency When it enters IDLE mode controller disconnects only the core clock There are two options available to select the IDLE mode entry mechanism depending on the SLEEPONEXIT bit in the Cortex MO System Control Register e Entry condition IDLE Sle
268. eed Counter Carry Overflow Raw Interrupt State Gives the raw interrupt state prior to masking of SCCOVF interrupt Speed Capture Raw Interrupt State Gives the raw interrupt state prior to masking of SCAPT interrupt SCSUNF 10 SCSOVF SCMAT Speed Counter Sign Underflow Raw Interrupt State Gives the raw interrupt state prior to masking of SCSUNMF interrupt Speed Counter Sign Overflow Raw Interrupt State Gives the raw interrupt state prior to masking of SCSOVF interrupt Speed Counter Match Raw Interrupt State Gives the raw interrupt state prior to masking of SCMAT interrupt Reserved Speed Capture Timer Overflow Raw Interrupt State SCTOVF 12 Gives the raw interrupt state prior to masking of SCTOVF interrupt n SAMSUNG ELECTRONICS 7 18 ex S3FN429_UM_REV1 20 7 Pulse Position Decoder Position Counter Carry Underflow Raw Interrupt State PCCUNF Gives the raw interrupt state prior to masking of PCCUNF interrupt Position Counter Carry Overflow Raw Interrupt State PCCOVF Gives the raw interrupt state prior to masking of PCCOVF interrupt Position Capture Timer Overflow Raw Interrupt State PCTOVF Gives the raw interrupt state prior to masking of PCTOVF interrupt Position Counter Sign Underflow Raw Interrupt State PCSUNF Gives the raw interrupt state prior to masking of PCSUMF interrupt Position Counter Sign Overflow Raw Interrupt State PCSOVF Gives the raw interrupt state prior t
269. el Conversion SAMSUNG ELECTRONICS 4 7 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 1 6 3 Continuous Mode Enable continuous conversion mode by setting control register bit to 1 In this mode the ADC repetitively performs conversions sequences until it is forced to stop To stop continuous conversion the CPU writes CSTOP bit in control register When it requests a stop ADC finishes its current conversion and updates data register with last conversion result The CPU does not perform any other conversion even if the sequence remains unfinished Figure 4 5 illustrates single channel conversion for continuous mode __________ __ ____ CSTOP BUSY M Aine aine Aine Aine Aine Aine AING ICNUMx Int Req Figure 4 5 Continuous Mode Single Channel Conversion Figure 4 6 illustrates multi channel conversion for continuous mode soc CSTOP BUSY E ICNUMx XO EN XO _ PENT XO TY _ 0 px AIN6 AIN2 AIN9 AIN6 AIN2 AIN9 AIN6 AIN2 AIN9 AIN6 AIN2 Eee 22 4 Int Req Figure 4 6 Continuous Mode Multi Channel Conversion SAMSUNG ELECTRONICS 4 8 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 1 7 Conversion Start Trigger You can select start signal for conversion by selecting TRIG 2 0 field in ADC_MR Mode Register There are five types of start triggers Software START bit in ADC_CR ADTRG R
270. en to the Transmit FIFO prior to enabling the PrimeCell SSP and the interrupts Alternatively the PrimeCell SSP and interrupts can be enabled so that data can be written to Transmit FIFO by an interrupt service routine e SSPRORINTR The receive overrun interrupt SSPORINTR is asserted when the FIFO is already full and an additional data frame is received causing an overrun of the FIFO Data is over written in the receive shift register but not the FIFO e SSPRTINTR receive timeout interrupt is asserted when the Receive FIFO is not empty and the PrimeCell SSP has remained idle for a fixed 32 bit period This mechanism ensures that the user is aware that the data is still present in the Receive FIFO and requires servicing This interrupt is de asserted if the Receive FIFO becomes empty by subsequent reads or if new data is received on SSPRXD It can also be cleared by writing to the RTIC bit in the SSPICR register SAMSUNG ELECTRONICS 15 17 x S3FN429_UM_REV1 20 15 Serial Peripheral Interface SPI 15 3 Register Description 15 3 1 Register Map Summary e Base Address 0 4009 0000 SSP_CRO 0x0000 SSP control register 0 0x0000_0000 SSP_CR1 0x0004 SSP control register 1 0x0000 0010 SSP receive FIFO data register read P DR 0x0000 0000 Sor 90908 SSP transmit FIFO data register Write SSP_SR 0x000C SSP status register 0x0000_0003 SSP_CPSR 0x0010 SSP clock rescale register 0x0000_0000 SAMSUNG ELECTRONICS 15
271. ep APB 16x12 Register EXER Receive Transmitter SSPFSS Block FIFO Receiver MRxFWrData 15 0 TX RX Params SSPCLKDIV SSPCLK SSPCLK Clock Prescaler SSPRTINTR Interrupt Generator SSPRORINTR SSPTXINTR SSPRXINTR Figure 15 1 SSP Block Diagram SAMSUNG ELECTRONICS 15 3 Lm S3FN429_UM_REV1 20 15 Serial Peripheral Interface SPI 15 2 2 Operation The operation section describes the functional description of ARM PrimeCell PrimeCell SSP Register Block Pre scaler and FIFO receive and transmit 15 2 2 1 Function Description This section describes the overview and functionality of ARM PrimeCell SSP 15 2 2 1 1 ARM PrimeCell SSP PL022 Overview The PrimeCell SSP is either a master or slave interface for synchronous serial communication with peripheral devices having Motorola SPI The PrimeCell SSP performs serial to parallel conversion on the data received from a peripheral device The CPU accesses data control and status information through the AMBA APB interface Transmit and receive paths are buffered with internal FIFO memories allowing up to eight 16 bit values to be stored independently in both transmit and the receive modes The serial data is transmitted on SSPTXD and received on SSPRXD The PrimeCell SSP includes a programmable bit rate clock divider and pre scaler to generate the serial output clock SSPCLK from the input clock FSSPCLK Bit rates are supported u
272. ep Now If it clears the SLEEPONEXIT bit of System Control Register in Cortex MO then the MCU enters IDLE mode as soon as it executes the WFI or WFE instruction IDLE Sleep on Exit If the SLEEPONEXIT bit of System Control Register in Cortex MO is set then the MCU enters IDLE mode as soon as it exits the lowest priority Interrupt Status Register ISR e Entry sequence Configure Wake Up source Configure clock source Configure Oscillator and PLL Select the WFE WFI by setting the IDLEW bit the and the CM register If you want to use the WFE then set the RXEV bit in the CM register f you want to use the then copy the Interrupt Set Enable Registers into the CM NISR register Execute entry condition The System Control Register of the Cotex MO NVIC has the Sleep on Exit bit SLEEPONEXIT If it is set then the processor completes the execution of an exception handler Then it returns to the thread mode and immediately enters into the IDLE mode Use this mechanism in applications that only requires the processor to run when an exception occurs After exiting from IDLE mode if you use the IMCLK without the external oscillator then you should not perform the accuracy critical code and the PLL The processor should wait until EMCLK is enabled and stabilized By configuring the PCLK in the register it is possible to disconnect the clock supply to peripherals Thu
273. er 16 3 1 12 TC_CDR e Base Address 0 4006 0000 4006 1000 0 4006 2000 e Address Base Address 0x002C Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 R R R RI R R R R R R R R R R R Resei value R resen o ow 9 NOTE 1 The equation to define Counter Clock is Timer Counter Clock Clock Source DIVM 1 2 DIVN 2 Writing into the register completes when UPDATE 1 or START 1 condition of TC CSR register Caution not set DIVM to zero when DIVN is not zero For example If the counter clock is four times slower than the clock source then the allowed settings are DIVN 0 and DIVM 3 DIVN 1 and DIVM 1 But following is forbidden DIVN 2 and DIVM 0 SAMSUNG ELECTRONICS 16 34 iD S3FN429_UM_REV1 20 16 Timer Counter 16 3 1 13 TC_CSMR e Base Address 0 4006 0000 4006 1000 0 4006 2000 Address Base Address 0x0030 Reset Value 0x0000 000F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 WIW W W __ Specifies the counter size For example e If SIZE is 0x07 then the TC acts as 8 bit TC e If SI
274. er clock selection of IMC 000 IMCLK 001 IMCLK 2 010 IMCLK 4 011 IMCLK 8 IMFILTER 10 8 RW 100 IMCLK 16 000 b 101 IMCLK 32 110 IMCLK 64 111 IMCLK 128 NOTE Only six times same level in a row is recognized as effective signal PWMXxOFF Active Selection This field determines the active selection for PWMOOFF 00 Falling Edge ESELPWMOFF 7 6 RW 01 Rising Edge 10 Low Level 11 High Level NOTE You can change these bits only when 0 is 0 Polarity of PWM in the PWMxD0 1 2 This field determines the polarity of PWM signal in the PWMPOLD RW 1 2 0 Low Start 1 High Start Polarity of PWM in the PWMxU0 1 2 This field determines the polarity of PWM signal in the PWMPOLU RW PWMXxUO 1 2 0 Low Start 1 High Start SAMSUNG ELECTRONICS 10 31 S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC Swapping of PWMxUx and PWMxDx This field determines swapping of PWMxUx and PWMXxDx PWMSWAP 3 RW 0 No swap 1 Swap NOTE You can change this bit only when is 0 Write Mode of Compare Register This field determines the Write mode of all compare registers 0 Immediate write 1 Synchronous write WMODE 2 RW NOTE In the synchronous write if IMCNT is equal to 0 or TOPCMP compare registers including dead time compare register which are written are updated simultaneously Synchronous write relates to NUMSKIP For example if NUMSKIP is 30 then the sy
275. er in the low power mode IDLE or STOP The maximum number that you can use at the same time is eight You can select any external event using EESRCx field in CM_EECRO _ 1 registers There are the values of EESROXx field into Table 5 14 Table 5 9 External Event Function OPERATING Specific event trigger External Interrupt IDLE SLEEP Core wake up trigger STOP DEEPSLEEP Core wake up trigger 5 5 1 Operating Mode You can use something among 24 external interrupts in general operating modes To use external interrupt the corresponding port should be configured as EXI function Each external interrupt can be independently configured with EECRO and CM register You can select the trigger edge type rising falling or both Their interrupts can be enabled or disable through CM EIMSCR register The occurred interrupt status can be read through CM ERISR or CM EMISR To clear interrupt status you should use CM EICR register The example configuration for EXI2 is the followings Define interrupt handler service routine for EEIA vector Refer to INTC and CM EXI2 pin configuration Refer to IOCONF Assign EXI2 interrupt source to EEO interrupt Refer to CM Enable EEIA Vector Enable Unmask EEO interrupt defined with an EXI2 interrupt source Check an interrupt pending status If external interrupt signal is asserted through EXI2 port EEO bit in CM RISR and CM register will be set to 1
276. er is frozen when the CPU is halted in debug mode mewo won a Reen Clock Enable Disable Control Bit BW 0 Disables Counter Clock 1 Enables Counter Clock SWRST does not affect CLKEN bit status Caution You should set the CLKEN bit before writing to other registers When the CLKEN bit is clear you cannot change values in registers Regardless of CLKEN Reading from registers and writing to DBGEN and SWRST are always available SAMSUNG ELECTRONICS 16 21 x S3FN429_UM_REV1 20 16 Timer Counter 16 3 1 4 SRR e Base Address 0 4006 0000 4006 1000 0 4006 2000 e Address Base Address 0x000C Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 Reserved Software Reset 0 No effect 1 Performs Software reset SAMSUNG ELECTRONICS 16 22 ex S3FN429_UM_REV1 20 16 Timer Counter 16 3 1 5 TC_CSR e Base Address 0 4006 0000 0x4006_1000 0 4006 2000 e Address Base Address 0x0010 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24123 22 21 20 19 16 15 11 10 9 y 0 4 N STOPHOLD UPDATE fe Pwes s s fe Pwes fe s fe RSVD EXET EXE CAPT_R A s ame s s __ EXT EL e E
277. er will use only PBCRR register 1 Separate Write mode User should write both PBCRR and PBCFR register to each proper value Phase A Compare Register Write Mode Selection Bit 0 Common Write mode User written PACRR value copies to the PACFR field PACRWM simultaneously You can use only PACRR register 1 Separate Write mode You should write PACRR and PACFR registers with proper value each by each Synchronous Write Selection SYNCSEL This field determines the timing of synchronous write 00 Synchronous write at counter matches ZERO and SAMSUNG ELECTRONICS 10 29 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC IMC_TCR 01 Synchronous write at counter matches ZERO 10 Synchronous write at counter matches TOPCMP 11 Should not use mo 210971 Numbers of Skip for Motor Match Interrupt This field determines the number of skips for motor match interrupt and ADC trigger signal The unit of skip is PWM full cycle 00000 No skip 00001 1 Time skip NUMSKIP p 908105 Times skip 00011 2 3 Times skip 00100 4 Times skip 11100 28 Times skip 11101 2 29 Times skip 11110 2 30 Times skip 11111 231 Times skip mo Ro mew Inverter Clock IMCLK Selection This field determines the inverter motor clock selection Also you can select the clock source IMCLK EMCLK PLLCLK or PCLK in a Clock Manager FIN means the frequency of the clock source that Cloc
278. errupt MSCR EEO CM_EECR RISR EEO EESRCO 4 0 MISR EEO CR EEO Vector EEIA MSCR EE1 CM_EECR RISR EE1 EESRC1 4 0 MISR EE1 CR EE1 Vector EEIB MSCR EE2 RISR EE2 EESRC2 4 0 MISR EE2 CR EE2 Vector MSCR EES3 CM RISR EE3 EESRC3 4 0 MISR EE3 CR EE3 Vector EEID MSCR EE4 CM_EECR EES RISR EE4 RC4 4 0 MISR EE4 CR EE4 Vector EEIE MSCR EES CM_EECR RISR EES EESRC5 4 0 MISR EES 5 MSCR EE6 CM_EECR RISR EE6 EESRC6 4 0 MISR EE6 CR EE6 Vector EEIF MSCR EE7 CM_EECR RISR EE7 EESRC7 4 0 MISR EE7 CR EE7 Figure 5 13 External Interrupt Diagram SAMSUNG ELECTRONICS 5 25 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 6 Reset Management The seven sources for a reset are e External Pin Reset e Power on Reset e Low Voltage Detect Reset e External Main Clock Monitor Reset e Watchdog Timer Reset e Software Reset e CPU Request Reset Figure 5 74 illustrates the reset sources NRST Pin Reset PORST Power on Reset LVDRST Low Voltage Detect Reset Ext Main OSC Moni
279. errupt TOP Match Interrupt Mask 0 This interrupt is masked Disables the interrupt 1 This interrupt is not masked Enables the interrupt ZERO Match Interrupt Mask 0 This interrupt is masked Disables the interrupt 1 This interrupt is not masked Enables the interrupt FAULT Interrupt Mask 2 NN 31 14 D 2 SAMSUNG ELECTRONICS 10 43 S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 0 Mask the interrupt Disables the interrupt 1 Unmask the interrupt Enables the interrupt SAMSUNG ELECTRONICS 10 44 en S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 3 1 9 IMC_RISR Base Address 0 400 0000 Address Base Address 0x0020 Reset Value 0 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 ADCFM1 ADCFM2 __ acm EXEC ADC Falling Match Raw Interrupt State ADCFM2 Gives the raw interrupt state prior to masking of the ADCFN2 interrupt ADC Rising Match Raw Interrupt State ADCRM2 Gives the raw interrupt state prior to masking of the ADCRM2 interrupt ADC 1 Falling Match Raw Interrupt State ADCFM1 Gives the raw interrupt state prior to masking of the ADCFM1 interrupt ADC Compare Rising Match Raw Interrupt State ADCRM1 Gives the raw interrupt state prior to masking of the ADCRMI interrupt ADC Compare Falling Match Ra
280. errupt is masked Disables an interrupt 1 This interrupt is not masked Enables an interrupt Receiver Break Interrupt Mask 0 This interrupt is masked Disables an interrupt 1 This interrupt is not masked Enables an interrupt Transmitter Ready Interrupt Mask 0 This interrupt is masked Disables an interrupt 1 This interrupt is not masked Enables an interrupt Receiver Ready Interrupt Mask 0 This interrupt is masked Disables an interrupt Framing Error Interrupt Mask FRAME 0 This interrupt is masked Disables an interrupt 1 This interrupt is not masked Enables an interrupt SAMSUNG ELECTRONICS 17 31 ex S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter ee ee 1 This interrupt is not masked Enables an interrupt NOTE On a Read the US_IMSCR register gives the current value of the mask on the relevant interrupt A Write of 1 toa particular bit sets the mask enabling the interrupt to be read A Write of 0 clears the corresponding mask SAMSUNG ELECTRONICS 17 32 ex S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 8 1 7 US_RISR e Base Address 0x4008_0000 e Address Base Address 0x0018 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 Idle Raw Interrupt State IDLE 10 gt 5 wy ayo 8 2 4 Gives the raw interrupt sta
281. errupts are Start Interrupt STARTI Start interrupt is generated when the timer starts Stop Interrupt STOPI Stop interrupt is generated when the timer stops Period Start Interrupt PSTARTI Period Start interrupt is generated when the period starts Period End Interrupt PENDI Period End interrupt is generated when the period ends Pulse Match Interrupt MATI Pulse Match interrupt is generated when the counter value is identical to PULSE Overflow Interrupt OVFI Overflow interrupt is generated when the counter overflows Capture Interrupt CAPTI Capture interrupt is generated when the external capture signal is triggered 16 2 8 2 Interruption Handling The mechanism to carry out the interrupt handling is Interrupt Service Routine ISR Entry and call C function Read from the TC_MISR register and verify the source of the interrupt Clear the corresponding interrupt by writing 1 to relevant bit in the TC_ICR register Interrupt service Exit ISR SAMSUNG ELECTRONICS 16 17 ex S3FN429_UM_REV1 20 16 Timer Counter 16 3 Register Description 16 3 1 Register Map Summary e Base Address 0x4006 0000 0x4006 1000 0x4006 2000 Reges Reset vame SAMSUNG ELECTRONICS 16 18 ex S3FN429_UM_REV1 20 16 Timer Counter 16 3 1 1 TC e Base Address 0x4006 0000 0x4006 1000 0 4006 2000 e Address Base Address 0x0000 Reset Value 0x0011 000A 31 30 29 28 27 26 25 24 23 22 21
282. es the PWM waveform with STOPHOLD 1 and STOPCLEAR 0 Conditions SR OVFM 0 REPEAT 1 PWMEN 1 PWMIM 0 STOPHOLD 1 STOPCLEAR 0 KEEP X Counter Clock TC_SR START TC_CVR COUNT IDLESL X OUTSL 0 IDLESL X OUTSL 1 Figure 16 12 PWM Waveform with STOPHOLD 1 STOPCLEAR 0 SAMSUNG ELECTRONICS 16 15 ex S3FN429_UM_REV1 20 16 Timer Counter If STOPCLEAR bit in TC SR register is set when clearing START bit then the TC stops immediately As a result the output level on TPWM pin changes to the level specified by IDLESL bit in SR register Figure 16 13 illustrates the PWM waveform with STOPCLEAR 1 Conditions TC_SR OVFM 0 REPEAT 1 PWMEN 1 PWMIM 0 STOPHOLD X STOPCLEAR 1 KEEP X commerce TPY UU U U U UAA TC_SR START TC_CVR COUNT IDLESL 0 OUTSL 0 IDLESL 0 OUTSL 1 IDLESL 1 OUTSL 0 IDLESL 1 OUTSL 1 Figure 16 13 PWM Waveform with STOPCLEAR 1 When the TC is reset the initial level of output signal is LOW You can immediately change the output level to the level specified by the IDLESL bit by changing the IDLESL bit when STOPCLEAR bit is set and the timer is not running SAMSUNG ELECTRONICS 16 16 ex S3FN429_UM_REV1 20 16 Timer Counter 16 2 8 Interrupt The section describes interrupts supported by the TC 16 2 8 1 Types of interrupt The TC can generate seven types of interrupt The seven int
283. es the Saw Tooth wave No SWAP a Low Start PWMxUy and High Start PWMxDy IMC ASCRR2 PET TT PCCRR IMG ASCRR se Se em PBCRR 2112222 IMG ASCRRO emo om EORR 5 ae me ced a IMC_PACRR Interrupt Can be used by ADC trigger signal Figure 10 15 Saw Tooth Wave No SWAP Low Start PWMxUy and High Start PWMxDy NOTE 1 Both the switches of upside and down side are high active 2 For 100 95 duty of upside you should set the rising falling compare register to For 0 duty of upside you should set the rising compare register to equal to TOPCMP value SAMSUNG ELECTRONICS 10 16 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC Figure 10 16 illustrates the Saw Tooth wave duty No SWAP a Low Start PWMxUy and High Start PWMxDy Upside 0 duty setting Upside Upside 5095 duty setting Upside 196 duty setting Upside 99 duty setting Figure 10 16 Saw Tooth Wave Duty No SWAP Low Start PWMxUy and High Start PWMxDy SAMSUNG ELECTRONICS 10 17 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 2 3 10 Saw Tooth Wave IMMODE 1 PWMSWAP 1 PWMPOLU 0 Low Start and PWMPOLD 1 High Start Figure 10 17 illustrates the Saw Tooth wave SWAP a Low Start PWMxUy and High Start PWMxDy gum ees Cece
284. esponding region Sector 1 that is composed of four sectors 8 KB Bacio 16 0 Enables HARDWARE protection of selected regions 1 Disables HARDWARE protection of selected regions Should be 1 NOTE You should define the region or regions for protection to enable hardware protection and then perform smart option program The hardware protection data in Protection Smart Option should include Hardware Protection Bit Bit 17 and hardware protection region bits Sector 3 9 2 2 2 1 SWD Interface Protection Bit 8 Use SWD interface protection to enable or disable SWD access If you do debug through SWD in initial chip development state then you should disable SWD interface protection But in final design development state if you enable the SWD interface protection then the other users cannot access the flash memory data through SWD interface 9 2 2 2 2 Hardware Hard Lock Protection Bit 17 When the Hard Lock protection bit is enabled you cannot write or erase the data in selected regions of flash memory You can protect the partial or all flash memory and unprotect it by Software Tool can clear the protection using the entire erase SAMSUNG ELECTRONICS 9 8 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 2 2 2 3 Read Protection Bit 27 If you want your data and code in memory to be inaccessible to others you can do this by read protection prevents flash data from being read serially in the
285. ess 0 4002 0000 e Address Base Address 0x0044 Reset Value 0x0000 0007 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 SDIVKEY ze R R RHR WINIWIWIWIW WI W W W W Name Bit Type Description Reset Value Key for Write Access into the CM SCDR SDIVKEY 31 16 Any Write in SCDR register bits is only effective if the SDIVKEY is 2 to OxACDC SYSCLK Divider 8 0 ow SSO This field selects the division ratio for SYSCLK EM Table 5 12 SYSCLK Divider Value _ 5 24 32 amp 10 0666007 1333333 2 2666667 6 666667 om 8 05 1 w 2 5 SAMSUNG ELECTRONICS add x S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 1 16 CM_PCDR e Base Address 0 4002 0000 e Address Base Address 0x0048 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 PDIVKEY 2 WIW W W PCDR Register Key Key for Write Access into the CM PCDR Any Write in PCDR register bits is only effective if the PDIVKEY is equal to 5 EE Reserved PCLK Divider This field selects the division ratio for PCLK e vce SAMSUNG ELECTRONICS 5 61 en S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 1 17 CM_PSTR e Base Address
286. etect the failure of an external main clock External Main Clock Monitor Reset Enable Control Bit EMCMRST 22 W 1 Enables Reset by Main Clock Monitor When it detects a clock failure a clock monitor circuit generates the chip reset Svo IDLEW Control Bit 1 2 Sets IDLEW roa R Rewd PCLK Enable Control Bit in IDLE Mode 1 Connects PCLK supplied to peripherals in IDLE Mode PCLK is supplied to peripherals in IDLE Mode STCLK Enables Control in IDLE Mode 1 Enables STCLK in IDLE mode This is one of the options with the IDLE mode If the STCLK bit sets to 1 before entering the IDLE mode then the STCLK supplies to the systick timer in the IDLE mode PLL ON Control Bit 1 Enables PLL After enabling PLL you should check the PLL status bit in CM_SR register to use the PLL Clock which is stable Reserved Fast Wake Up Enable Control Field 1 Enables FWAKE SAMSUNG ELECTRONICS 5 38 en S3FN429_UM_REV1 20 5 Clock and Power Manager If a microcontroller enters stop mode after being enable a fast Wake Up SYSCLK becomes IMCLK after Wake Up wa mme Internal Main Clock Enable Control Bit 1 IMCLK 1 mw 1 Enables IMCLK clocking External Main Clock Enable Control Bit 1 EMCLK W NOTE 1 The complement of Enable action means that each clock EMCLK or IMCLK becomes stable after you enable each clock The status register CM SR reflects the result of t
287. evel as last period output level when PWM stops In this case Ignore IDLE level Idle State Level IDLESL W 0 Noeffect 1 Idle State PWM output level is low Logic O Rv aR Resend Start PWM START 0 No effect 1 Stops PWM Operation PWM Start Level 0 No effect TSL W oe 1 Starts PWM output level from low Logic 0 for the specified PERIOD SAMSUNG ELECTRONICS 14 20 ex S3FN429_UM_REV1 20 14 Pulse Width Modulation 14 3 1 6 PWM_SR e Base Address 0 4007 0000 0x4007_ 1000 Address Base Address 0x0014 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10987 6 5 o 4 x Xx i amp NN PWMEX5 PWMEX4 PWM Extension Bit Control PWMEX3 0 PWM Extension is not effective to the corresponding bit PWMEX2 field PWMEX1 1 PWM Extension is effective to the corresponding bit field PWMEXO e ee e we e e Rsv O 0 PWMIM 11 1 Interval Mode Keep Last Period Status KEEP 10 0 IDLESL determines the PWM output level when PWM stops 1 Keeps the PWM output level as last period output level when PWM stops Ignores IDLESL in this case 92 PWM Output Mode Status 0 PWM Mode PWM Output Start Level Status 0 Starts PWM output level from LOW Logic 0 for the OUTSL 9 PERIOD that it specifies 1 Starts PWM Output Level from High Logic 1 for the PERIOD that it specifies IDLE State PWM
288. f the FWAKE STOP mode If a microcontroller enters the STOP mode after disabling a Fast Wake Up the SYSCLK is the same before entry of STOP mode mv Wa R mew SAMSUNG ELECTRONICS 5 40 27 S3FN429_UM_REV1 20 5 Clock and Power Manager Internal Main Clock Disable Control Bit IMCLK 1 W 1 INE IMCLK cloaking If EMCM bit in the CM_SR register is 1 there is no effect not even disable even if this bit is set to 1 External Main Clock Disable Control Bit EMEN 1 Disables the EMCLK clocking 1 The register is Write only The opposite control should use the register All defined control bits have no effect on writing 2 For each bit you should write 1 Each clock is a source of any block to operate Before disabling any clock you should check the usage of the clock by any block For example if the WDTCLK uses the IMCLK as a timer clock source you should stop the operation of the WDTCLK before disabling the IMCLK If the operating clock of watchdog timer stops while the watchdog timer runs then the CMDERR bit of the CM_SR register is set to 1 Caution If you don t the external main oscillator when pin7 and pin8 are defined XOUT and XIN function you should tie XIN to ground XOUT should be opened SAMSUNG ELECTRONICS 5 41 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 1 5 CM_PCSR e Base Address 0 4002 0000 e Address Base Addres
289. ffect 1 Performs PPD Software Reset SAMSUNG ELECTRONICS 7 9 ex S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 3 1 4 PPD_CRO e Base Address 0x400C_0000 e Address Base Address 0x000C Reset Value 0x0000 0000 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 40 9 8 7 a gt PPDFILTER PPDCLKSEL gt zaa RIR R R R R R R R R R R R R R Name Bit Type o Description Reset Value Hold Trigger Source This field determines the trigger source for hold function 0000 No Trigger Disconnect 0001 IMC Zero HOLDTRIG 31 28 Rw 0010 Top 0011 IMC Zero and Top 0100 TIMERO Match 0101 TIMER1 Match 0110 TIMER2 Match Others Not used 2 Filter Clock Selection of Pulse Position Decoder This field determines the filter clock selection of a pulse position decoder 000 PPDCLK 001 PPDCLK 2 010 PPDCLK 4 PPDFILTER 26 24 RW 011 PPDCLK 8 100 PPDCLK 16 101 PPDCLK 32 110 PPDCLK 64 111 PPDCLK 128 NOTE Recognizes as effective signal only five times in a CO in the same level Edge Selection ESELZ 22 24 RW This field the edge Selecion for PHASEZ 00 Selects rising edge of PHASEZ input 01 Selects falling edge of PHASEZ input a SAMSUNG ELECTRONICS 7 10 gt 21 PHASEZ PHASEB PHASEA pale soca PPDTYPE Ee E
290. field determines the ADC compare register value at 0x0000 falling SAMSUNG ELECTRONICS 10 64 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 3 1 25 IMC_ASCFR1 Base Address 0 400 0000 Address Base Address 0 0060 Reset Value 0 0000 0000 31 30 29 28 27 26 25 24123 22 21 20 19 18 17 16 15 14 13 12 11 10 a B A ADCMPF1DAT ele es RIR R R R R R R R R RSVD R ADC Compare Data 1 for Falling time ADCMPF1DAT 15 0 RW This field determines the ADC compare register value at 0x0000 falling SAMSUNG ELECTRONICS 10 65 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 3 1 26 IMC_ASCFR2 Base Address 0 400 0000 Address Base Address 0x0064 Reset Value 0 0000 0000 31 30 29 28 27 26 25 24123 22 21 20 19 18 17 16 15 14 13 12 11 10 a B A ADCMPF2DAT ele es RIR R R R R R R R R RSVD erat n ADC Compare Data 2 for Falling time ADCMPF2DAT 15 0 RW This field determines the ADC compare register value at 0x0000 falling SAMSUNG ELECTRONICS 10 66 ex S3FN429_UM_REV1 20 11 Interrupt Controller INTC Interrupt Controller INTC 11 1 Overview Interrupt Controller includes NVIC of Cortex MO processors These proce
291. fined function value to xFSEL 1 0 Fx Function x then x FSEL 1 0 will not change and will remain as the valid pre configuration Table 12 1 I O Function Mode Configuration describes the function values for each Table 12 1 I O Function Mode Configuration describes the function values for each I O 2 reset value 11 b of IOO 28 and 00 29 are for Serial Wire Debug SWD SAMSUNG ELECTRONICS 12 6 ex S3FN429_UM_REV1 20 12 Configuration 12 3 1 3 IO PUCRO Base Address 0x4005 8000 e Address Base Address 0x0008 Reset Value 0x3000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 0 30 29 PUEN 28 PUEN 27 PUEN 26 PUEN 0 25 24 23 PUEN 22 PUEN 21 20 PUEN 19 PUEN 18 PUEN 17 16 15 14 PUEN 13 PUEN 0 12 PUEN 100 7 00 6 PUEN 00 5 00 4 100 3 100 2 IO0 1 00 0 11 0 10 0 9 PUEN z iu 2 a 5 o 0 8 PUEN R R R R R R R RI IRI IRIRIR I IRIRIR I R I IR I RIRIRIRIRIRIRIR RI R wiwiwiwi iw w wW WwW W W W WIWINWINWINWINWINWINWIWIWIWIWIWIW W W lOO y Pull Up Enable Disable 0 y y RW 0 Disables Pull Up resistor IOO y 1
292. flag for J1587 protocol e Line break generation and detection e Automatic echo local loopback and remote loopback channel modes e Multi drop mode address detection and generation e Interrupt generation e Character length of 5 to 9 bits e Configurable start bit of data transmission e Smart Card protocol error signaling and re transmission e Asynchronous mode maximum BaudRate PCLK 16 e Synchronous mode maximum BaudRate when providing USARTCLK clock PCLK 2 e Synchronous mode maximum BaudRate when receiving USARTCLK clock PCLK 4 17 1 2 Pin Description Table 17 1 describes the USART pin description Table 17 1 USART Pin Description SAMSUNG ELECTRONICS 17 2 x S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 2 Functional Description This section contains functional description of USART The functional description includes e Block diagram e BaudRate generator e General description 17 2 1 Block Diagram Figure 17 1 illustrates the block diagram of USART Peripheral Data Controller USART Channel Receiver Shift Register USARTRX Transmitter USARTTX Baud Rate Shift Register Generator BaudRate Clcok USARTCLK Figure 17 1 USART Block Diagram SAMSUNG ELECTRONICS 17 3 ex S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 2 2 BaudRate Generator Figure 17 2 illustrates the BaudRate generator 17 2 3 General
293. g of the Period End interrupt Period Start Interrupt PSTARTI Gives the masked interrupt status after masking of the Period Start interrupt Stop Interrupt STOPI Gives the masked interrupt status after masking of the Stop interrupt Start Interrupt STARTI Gives the masked interrupt status after masking of the Start interrupt NOTE 1 TC IMSCR register affects MISR register MISR IMSCR AND RISR 2 Ona Read TC MISR register gives the current masked status value of the corresponding interrupt A Write has no effect 0 Each interrupt does not occur 1 Each interrupt occurs SAMSUNG ELECTRONICS 16 32 ex S3FN429_UM_REV1 20 16 Timer Counter 16 3 1 11 TC_ICR e Base Address 0 4006 0000 4006 1000 0 4006 2000 e Address Base Address 0x0028 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 o CAPTI a Fac f gt __ s gt __ gt smm ASV R Rma m 2 Capture interrupt Overflow interrupt s Clear dle Pulse Match interrupt Period End interrupt Period Start interrupt 2 Stop interrupt om w NOTE On a Write of 1 the corresponding interrupt is cleared A Write of 0 has no effect SAMSUNG ELECTRONICS 16 33 en S3FN429_UM_REV1 20 16 Timer Count
294. g Samsung products notwithstanding Copyright 2012 Samsung Electronics Co Ltd Samsung Electronics Co Ltd San 24 Nongseo Dong Giheung Gu Yongin City Gyeonggi Do Korea 446 711 Contact Us como jin samsung com TEL 82 31 209 4956 FAX 82 31 8000 2005 Home http www samsungsemi com SAMSUNG ELECTRONICS any information provided in this publication Customer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim including but not limited to personal injury or death that may be associated with such unintended unauthorized and or illegal use WARNING No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung This publication is intended for use by designated recipients only This publication contains confidential information including trade secrets of Samsung protected by Competition Law Trade Secrets Protection Act and other related laws and therefore may not be in part or in whole directly or indirectly publicized distributed photocopied or used including in a posting on the Internet where unspecified access is possible by any unauthorized
295. g register OxO00XX_XXXX NOTE For 1 and 2 the reset value by fabrication is But you can change the reset value by using Smart Option program Caution CR AR DR and IFC KR are auto cleared as command operation finish Other Write registers except IFC_IOTR can write when flash is not in running operation by commana SAMSUNG ELECTRONICS 9 26 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 3 1 1 IFC_ID e Base Address 0x4001_0000 Address Base Address 0x0000 Reset Value 0 0002 0039 ID Code Register 0x0002_0039 This field stores the ID code for the corresponding IP m SAMSUNG ELECTRONICS 9 27 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 3 1 2 IFC_CEDR e Base Address 0 4001 0000 e Address Base Address 0x0004 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 Clock Enable Bit 0 Disables Flash Clock 1 Enables Flash Clock Flash software reset does not affect CLKEN bit status Flash Clock controls can access Special Function Register SFR for flash controller SAMSUNG ELECTRONICS 9 28 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 3 1 3 IFC_SRR e Base Address 0x4001_0000 Address Base Address 0x0008 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19
296. ge across the internal filter This controls the VCO 5 2 4 3 Voltage Controlled Oscillator VCO The VCO controls the output voltage from the loop filter This results into its oscillation frequency to increase or decrease as a function of variations in voltage When the VCO output matches the System Clock in frequency and phase the Phase Frequency Detector stops sending a control signal to the charge pump Then the VCO frequency remains constant and the PLL remains locked onto the System Clock SAMSUNG ELECTRONICS 5 9 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 2 4 4 PLL Value Change Steps If the PLL setting requires change while using Four PLLCLK as a SYSCLK then the PLL transition noise may be asserted to system Therefore you should change PLL configuration in the NORMAL mode Steps to change the PLL configuration are 1 NOTE If you use CM_RISR register it needs to check that PLL bit in CM_RISR register is cleared or not before enabling PLL If it is set to 1 clear by writing 1 to PLL bit of ICR register If you use CM RISR register it needs to check that STABLE bit in CM RISR register is cleared or not before changing the SYSCLK If it is set to 1 clear by writing 1 to STABLE bit of ICR register 1 After Reset Enable an External Main Oscillator by controlling the EMCLK bit in the CM CSR register if EMCLK is disabled Check an External Main Stable by monitoring the EMCLK bit in the CM SR reg
297. gister of a target D TC2CLK Peripheral Status TC1CLK 0 Disables each peripheral clock disconnected TCOCLK It is impossible to control Write SFR register of a target IMCCLK peripheral SAMSUNG ELECTRONICS 5 44 ex S3FN429_UM_REV1 20 5 Clock and Power Manager PPDCLK PWM3CLK PWM2CLK PWM1CLK PWMOCLK WDTCLK OPACLK SAMSUNG ELECTRONICS 1 Enables each peripheral clock connected It is possible to control Write SFR register of a target peripheral NOTE After reset WDTCLK is enabled by default and WDT watchdog timer counts automatically 5 45 S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 1 8 CM_MRO e Base Address 0 4002 0000 Address Base Address 0x0028 Reset Value 0x0000 0828 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 o gt EN s ee R LVDPD gt sw RXEV owes es mv R Reses LVD Power Down Control Bit 0 2 LVD powers down 1 2 LVD powers up LVDPD 11 Rw When you set to 0 then you cannot use the LVD interrupt and the LVD reset function To reduce power you can configure this bit To use LVD Reset LVDRST or and LVD Interrupt LVDINT you should set the LVDPD bit On reset LVD is in the power up state SYSTIC Timer Clock Enable Disable Control Bit ST
298. hange the reset value of a Clock Manager by programming smart option value If Program Smart Option and chip reset do not occur the value that SO_CSR register shows is different from current Smart Option because the programmed Smart Option new option is effective after chip reset The reset value of fabrication is OxFFFFFFFF but you can change the value using Smart Option program If you program with target value to change a configuration option then other bits except control bits is set to 1 SAMSUNG ELECTRONICS 9 43 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 3 1 16 IOTR e Base Address 0 4001 0000 e Address Base Address 0x003C Reset Value 0 00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 o x x x x x x x o x x WINIWINI IWINIWIWIWIWI W W W W W W W W W Key for Write Access into the CM IOTR Register IOTKEY 31 24 Any Write in CM IOTR register bits is effective only if the is equal to 0x53 85 6 AW Internal Oscillator 40 MHz Trim Value You can use this field to trim values on changed condition OSC RW Voltage Temperature and so NOTE Reset value depends on trimming value by fabrication SAMSUNG ELECTRONICS 9 44 ex S3FN429_UM_REV1 20
299. hase Locked Loop is a frequency synthesizer and provides frequency multiplication capabilities The PLLs Output Clock Frequency FOUT is related to the Input Clock Frequency FIN The FOUT equation is FOUT m 8 FIN 2 x 2 s when LFPASS 0 FOUT m 8 FIN 2 5 when LFPASS 1 M 7 0 p P 5 0 s S170 Where FOUT is the Output Clock Frequency and FIN is the Input Clock Frequency m p and s are the decimal values for programmable dividers The PLL contains a Phase Frequency Detector PFD a Charge Pump a Voltage Controlled Oscillator VCO a 6 bit Pre Divider an 8 bit Main Divider and a 2 bit Post Scaler Figure 5 4 illustrates this The PLL multiplies the EMCLK and provides the clock source for SYSCLK The input range of source is from 1 to 12 MHz and the PLL amplifies the source clock to the PLLCLK Finish the PLL configuration before enabling the PLL by writing 1 to the PLL bit in the CM CSR register Additionally check the stabilization of the Input Clock EMCLK before the PLL is on After enabling and stabilizing the PLL it allows you to configure the CM MR register to supply the PLL clock to the SYSCLK When the clock transition completes the STABLE bit in the CM SR register is set to 1 After the reset it has the disable PLL by default Fin PLL multipliers M 7 0 16 to 255 Input frequency of PLL PLL pre divider P 5 0 1 to 63 EMCLK PLL post scaler S 1 0 0 to 3 D
300. he USARTRX pin level has no effect and the USARTTX pin is held high as in idle state Remote loop back mode It directly connects the USARTRX pin to the USARTTX pin Disable The transmitter and the receiver are disabled and have no effect This mode allows bit by bit retransmission 17 6 5 Smart Card Protocol The USARTs are 1507816 3 compliant and allow character repetition or error signaling on parity errors When the SMCARDPT bit is set on the US MR register the available functions are e The USART smart card protocol requires that the transmitter and the receiver are enabled e f PIO block allows it then the USARTTX can be configured as an open drain output and connected to the USARTRX pin with an additional external pull up resistor resulting in the smart card COMMS line SAMSUNG ELECTRONICS 17 18 ex S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 6 6 Character Transmission to Smart Card The USART is able to detect that the smart card has not received correctly the last transmitted byte by checking the parity error signal generated by the smart card When the smart card generates the parity error signal the last transmitted byte is re transmitted multiple times as determined in the SENDTIME 2 0 bits of the US_MR register until the error signal is no longer generated by the smart card When the USART detects the error signal the FRAME error flag is set in the US_SR register The USART check
301. he received data bits in accordance with the field PAR 2 0 in US_MR USART Mode Register Then the US_MR register compares the result with the received parity bit If the result is different then the parity error bit PARE is set in US_SR 17 4 2 4 Framing Error If the receiver receives a character with a stop bit at a low level and with at least one data bit at a high level then it generates a framing error This sets FRAME in US_SR SAMSUNG ELECTRONICS 17 13 ex S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 4 2 5 IDLE Flag The idle flag turns low when USART receives a start bit and the flag turns high at the end of a J1587 protocol frame after 10 stop bits It generates an interrupt at the rising edge of the flag Figure 17 6 illustrates the IDLE flag diagram 10 Stop Bits MID PID Dum PID Data Data ChkSum IDLE Flag or Not Busy USART IRQ IDLE Flag Figure 17 6 IDLE Flag 17 4 2 6 Time Out The Time Out is used to detect an idle condition on the RXD line The maximum delay for the USART to wait for a new character while the RXD line is inactive high level is programmed in TO 15 0 of US RTOR Receiver Time out register When this register is set to 0 no time out is detected Otherwise the receiver waits for a first character and then initializes a counter that decrements at each bit period and reloads at each byte reception When the counter reaches to 0 the TIMEOUT bi
302. his execution by hardware 2 Before you enable the clock monitor function you should check IMCLK is enabled or disabled If IMCLK is disabled you should enable IMCLK before enabling the clock monitor function Because the clock monitor circuit uses IMCLK as a reference clock to monitor the external main clock If you enable a clock monitor without enabling IMCLK the command error generates 3 The CM register is Write only The opposite control should use CM All defined control bits have no effect on writing O SAMSUNG ELECTRONICS 5 39 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 1 4 CM_CCR e Base Address 0 4002 0000 e Address Base Address 0x000C Reset Value 0x0000 0000 S External Main Clock Monitor Function Disable Control Bit 23 W 1 Disables the Main Clock Monitor function External Main Clock Monitor Reset Disable Control Bit EMCMRST 22 W 1 Disables reset by Clock Monitor When it detects Clock fail it reports a Clock fail flag mwo n Rem IDLEW IDLEW Control Bit 1 Disconnects the PCLK supplied to peripherals in an IDLE Mode STCLK Disable Control in IDLE Mode 1 Disconnects the STCLK supplied to a SYSTICK timer of Cortex MO IDLE mode PLL OFF Control Bit 1 D 2 20 PLL Fast Wake Up Disable o Field 1 Disables the FWAKE after Wake Up from the STOP mode the SYSCLK source is the same before entry o
303. iagram sse enne nennen 4 4 One Shot Mode Single Channel 4 7 One Shot Mode Multi Channel 4 7 Continuous Mode Single Channel 4 8 Continuous Mode Multi Channel Conversion 4 8 ADG Calibration be exea ete ducc Fe eta 4 11 2 Point CaliDrahO N n eas nr RR xe ran E RE neue nena Reed 4 12 dis eli 4 14 System Clock Tree Block Diagram 5 4 System Clock Selection 5 5 Crystal Ceramic Resonator or External Clock Circuit essen 5 7 PLL Phase Locked Loop Block 5 9 Glock Monitor E 5 11 External Main Oscillator Fail and Reset 5 12 End Of Cook Fall ors 5 13 Clock Control State Machine 5 14 The Change Clock Source of 5 15 Instruction for IDLE and 5 5 18 Interrupt and 5 22 Different Handling Process for Interrupt and Event in IDLE or Stop Mode 5 23 External Interrupt Diagram iicet desees
304. ile the PrimeCell SSP is idle and transitions at the programmed frequency only during active transmission or reception of data The idle state of SSPCLKOUT is utilized to provide a receive timeout indication that occurs when the Receive FIFO still contains data after a timeout period For Motorola SPI the serial frame SSPFSSOUT pin is active LOW and is asserted pulled down during the entire transmission of the frame SAMSUNG ELECTRONICS 15 9 ex S3FN429_UM_REV1 20 15 Serial Peripheral Interface SPI 15 2 2 1 3 8 Motorola SPI Frame Format The Motorola SPI interface is a four wire interface where the SSPFSSOUT signal behaves as a slave select The main feature of the Motorola SPI format is that the inactive state and phase of the SSPCLKOUT signal are programmable through the SPO and SPH bits within the SSPSCRO control register e SPO Clock Polarity When the SPO clock polarity control bit is LOW it produces a steady state low value on the SSPCLKOUT pin if the SPO clock polarity control bit is HIGH a steady state high value is placed on the SSPCLKOUT pin when data is not being transferred e SPH Clock Phase The SPH control bit selects the clock edge that captures data and allows it to change state It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge When the SPH phase control bit is LOW data is captured on the first clock edge transition
305. ime The compare registersare The compare registersare Th xcompare registersare written in the falling time written in the falling time the falling time Real update time Real update time P IMC TCR Shun Ses 2 The compare registers are written in the rising time The compare registers are The registers are written in the rising time writtep in the rising time Real update time Real update time Real update time Figure 10 28 Synchronous Write at Zero and IMC TCR Match SYNCSEL 00 b NUMSKIP 00001 b SAMSUNG ELECTRONICS 10 35 ex S3FN429_UM_REV1 20 Figure 10 29 illustrates the synchronous write at zero match The compare registersare The compare registersare written in the rising falling written in the rising falling time time IMC_TCR Real update time 10 Inverter Motor Controller IMC The compare registersare written in the rising falling time Real update time Figure 10 29 Synchronous Write at Zero Match SYNCSEL 01 b NUMSKIP 00001 b Figure 10 30 illustrates the synchronous write at IMC TCR match Real update time The compare registersare Real update time The compare registersare written in the rising falling time IMC TCR The compare registers are written in the rising time Real update time written in the rising falling time Figure 10 30 Synchronous Write at IMC TCR Match SYNCSEL 10 b NUMSKIP 00001 b NOTE
306. immediate Write Mode WMODE is equal to 0 and Saw Tooth mode IMMODE is equal to 1 then the compare register update operation looks like the illustration in Figure 10 25 SAMSUNG ELECTRONICS 10 33 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC Figure 10 25 illustrates the synchronous Write at Zero and IMC_TCR Match SYNCSEL 00 b NUMSKIP 00000 b The compare registers IMC_ASCRRx ASCFRx IMC_PACR FR PBCR FR PCCR FR are written in the falling time All real update of written compare registers is executed at the time simultaneously TOR sone The compare registers The compare registers ASCRRx IMC_ASCFRx ASCRRx ASCFRx IMC_PACR FR PBCR FR PACR FR PBCR FR IMC_PCCR FR are written IMC_PCCR FR are written in the rising time in the rising time All real update of written compare All real update of written compare registers is executed at the IMC_TCR registers is executed at the time simultaneously IMC_TCR time simultaneously Figure 10 25 Synchronous Write at Zero and IMC_TCR Match SYNCSEL 00 b NUMSKIP 00000 b NOTE If WMODE is equal to 1 and NUMSKIP is equal to 0 then the update of compare registers looks like the illustration in Figure 10 26 If NUMSKIP is 0 then the written compare registers are updated every TCR and 0 time Figure 10 26 illustrates the synchronous Write at Zero Match SYNCSEL 01 b NUMSKIP
307. in oscillator characteristics Table 19 8 Internal Main Oscillator Characteristics Ta 40 to 105 C 2 5 to 5 5 V Oscillator frequency Vpp 5 0 V Ta 25 C Accuracy Tacc Vpp 5 0 V Ta 40 to 105 C Vpp 2 5 to 5 5 V Ta 40 to 105 C Internal oscillator stabilization occurs Stabilization time Tsta when Vppis equal to the minimum oscillator voltage range SAMSUNG ELECTRONICS 19 8 19 Electrical Data S3FN429 UM REV1 20 19 Electrical Data 19 9 Current Consumption 1 The supply current does not include the current drawn through the internal pull up resistor and the external output current loads 2 Stop current has two conditions with LVD When you power LVD up the band gap for LVD reference is alive and then stop current Ipps will be increased To minimize stop current 15551 you can enter stop mode after LVD OFF Table 19 9 describes the current consumption details Table 19 9 Current Consumption at 5 5 V Ta 40 to 105 Vppio 5 5 V Disable PLLCLK Enable EMCLK and IMCLK Normal Enable all peripherals operating Run CPU at EMCLK 8 MHz Disable EMCLK PLLCLK Enable IMCLK Normal Enable all peripherals operating Run CPU at IMCLK 40 MHz ex E Run CPU at 40 MHz operating ws CPU stops noon conditon ______ Normalidle ees CPU st
308. interrupt occurs mw pou Interrupt Level Detect of LVD Interrupt Gives the unmasked interrupt state after unmasking of LVDINT 16 the LVDINT interrupt 0 Each interrupt does not occur 1 Each interrupt occurs External Main Clock Failure Interrupt Gives the unmasked interrupt state after unmasking of EMCKFAIL 15 the EMCKFAIL interrupt 0 Each interrupt does not occur 1 Each interrupt occurs External Main Clock Failure End Interrupt Gives the unmasked interrupt state after unmasking of a 14 the EMCKFAIL_END B 0 Each interrupt does not occur 1 Each interrupt occurs mewo weap R Rene SSS PLL Stable Interrupt Gives the unmasked interrupt state after unmasking of the PLL interrupt 0 Each interrupt does not occur 1 Each interrupt occurs SAMSUNG ELECTRONICS 5 53 ex S3FN429_UM_REV1 20 5 Clock and Power Manager RSVD ss n reee SYSCLK Clock Switching Stable Interrupt Gives the unmasked interrupt state after unmasking of STABLE 4 the STABLE interrupt 0 Each interrupt does not occur 1 Each interrupt occurs mew ma A esen External Main Clock Stable Interrupt Gives the unmasked interrupt state after unmasking of the EMCLK interrupt 0 Each interrupt does not occur 1 Each interrupt occurs __ Internal Main Clock Stable Interrupt Gives the unmasked interrupt state after unmasking of IMCLK 1 the I
309. iod Mode Timing The TC can also generate two types of output signals according to PWMIM bit in SR register The two output signals are Interval signal and PWM signal You should set the PWMEN bit in SR register in order to output the signal generated through the TPWM pin You should also configure the pin as the relevant alternative function SAMSUNG ELECTRONICS 16 8 ex S3FN429_UM_REV1 20 16 Timer Counter 16 2 7 1 Interval Operation In an interval mode operation the Pulse Width Modulated Output Signal TPWM level toggles for all instances whenever the time period end is detected For example if you write a value of 0x08 to the TC_PRDR register then the timer increments until it reaches a count of 0x08 At this instance the timer period end interrupt is generated The time period of TPWM is 2 x TCCLK x PERIOD Figure 16 6 illustrates the interval operation Conditions TC SR OVFM 0 REPEAT 1 PWMEN 1 PWMIM 1 TC_CCSMR SIZE gt 3 TC CPRDR PERIOD 8 Counter Clock TC_CVR COUNT TC_RISR PENDI TPWM Period Interrupts are cleared by writing 1 to corresponding bits in ICR Figure 16 6 Interval Operation SAMSUNG ELECTRONICS 16 9 ex S3FN429_UM_REV1 20 16 Timer Counter 16 2 7 2 PWM Operation You can use the for generating the Pulse Width Modulation PWM signal In this operation you should specify the TC_CPULR register by writing a relevant value to PULSE bi
310. ion e Up to 22 bit resolution including extension function 14 1 2 Pin Description Table 14 1 describes the function of PWM pin Table 14 1 PWM Pin Description NOTE x stands for channel number of PWM For example PWMO or PWM1 SAMSUNG ELECTRONICS 14 1 S3FN429_UM_REV1 20 14 Pulse Width Modulation 14 2 Functional Description The functional description section includes e Block Diagram e General Description e Clock and Operation Frequency Period e PULSE Level e nPULSE Width e IDLE Level e Parameter Relationship e Extension Bit 14 2 1 Block Diagram Figure 14 1 illustrates the Pulse Width Modulation PWM block diagram PWM Start Interrupt PCLK gt EN Pre Scale N PWM_CDR DIVN Divider PWM_CDR DIVM PWM Stop Interrupt PWMCLK PWM_CEDR CLKEN UP COUNTER Period Start Interrupt PWM_INT Period End PWM PRDR PERIOD Interrupt d Pulse Match PWM PULR PULSE Interrupt PWM Generator PWMx Figure 14 1 Pulse Width Modulation PWM Block Diagram SAMSUNG ELECTRONICS 14 2 ex S3FN429_UM_REV1 20 14 Pulse Width Modulation 14 2 2 General Description The PWM generates the periodic waveform The waveform includes PULSE and nPULSE width Figure 14 2 illustrates the diagram of PWM cycle description PULSE will be high or low by OUTPUTL control bit gt idle sta
311. ion data ADC_SSR shows the channel to be converted and the count value However after conversion ends the data in a conversion buffer register is invalid 4 1 9 Interrupt and Flag The ADC generates an interrupt if any one of the EOC or OVR is active set to 1 in the masked interrupt status register and corresponding bit in the ADC_MISR is set to active set to 1 Use Interrupt Mask Set Clear Register ADC_IMSCR to enable or disable each interrupt bit 4 1 9 1 End of Conversion EOC ADC generates an EOC interrupt when conversion sequence is completed while ADC interrupt is enabled You can check whether interrupt has occurred by reading interrupt status register Use ADC_IMSCR register to enable or disable interrupt bit respectively You can clear EOC interrupt by writing 1 into EOC bit in ADC_ICR register It is auto cleared when you read the conversion result register 4 1 9 2 Over Run OVR OVR indicates that new data overwrites previously converted data that is not read and is lost OVR flag is cleared by CPU writing OVR bit in interrupt clear register The channel also has an overrun data and you can get this data from status register ADC_SR 4 1 9 3 BUSY Flag The BUSY bit indicates whether ADC is converting analog data or not The other conversion trigger signal asserted in busy status BUSY 1 is ignored SAMSUNG ELECTRONICS 4 10 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 1 10 Calibration
312. ising ADTRG Falling ADTRG Rising or Falling both TCx Software trigger by control register bit setting External input trigger Signal which is asserted from ADTRG pin You should configure ADTRG pin for use before ADC conversion When you select ADTRG TRIG 2 0 10 b define edge type of ADTRG Trigger which is generated by Timer Counter TC Trigger which is generated by Inverter Motor Controller IMC block TRIG 2 0 Start Trigger Source 000 b Software START bit in ADC_CR 001 b ADTRG Rising ADTRG Rising or Falling both START Conversions are started by the CPU writing the START bit in the ADC_CR ADTRG Conversions are started by an external signal using a dedicated input pin ADTRG Peripheral TC Conversions are started by the internal hardware signal TC period match signal Peripheral IMC Conversions are started by the internal hardware signal ADC trigger signal in the IMC SAMSUNG ELECTRONICS 4 9 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 1 8 Conversion Data This section describes the Conversion Data process 4 1 8 1 Conversion Result and Buffer Register Conversion buffer register is used for saving the converted data temporarily while converting a sequence After completing the conversion the ADC generates End of Conversion EOC event interrupt and saves converted data into conversion result registers During conversion use conversion buffer registers to view convers
313. ister Set the PLL stabilization time to prevent an abnormal operation Change the PMS value in the CM PDPR register Enable the PLL by controlling the PLL bit in the CM register Check the PLL stable by monitoring the PLL bit in the CM SR or CM RISR 1 register If a PLL is stable then set the SYSCLK fields in the CM MR register Later SYSCLK is fed from the PLLCLK Check the switching status by monitoring the STABLE bit in the CM SR or CM RISR 2 register PLL Configuration Change in the PLL Mode Change the System Clock to the External Main Clock Oscillator EMCLK or Internal Main Clock IMCLK Disable the PLL by setting the PLL bit in the CCR register Change the PMS value in the CM PDPR register Enable the PLL by controlling the PLL bit in the CM register Check the PLL stable by monitoring the PLL bit the CM SR or CM RISR 1 register If a PLL is stable then set the SYSCLK fields in the MR register Later SYSCLK is fed from the PLLCLK Check the switching status by monitoring the STABLE bit in the CM SR or CM RISR 2 register SAMSUNG ELECTRONICS 5 10 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 2 5 Clock Monitor The function of clock monitor is to monitor the availability of External Main Clock Oscillator When you enable the clock monitor you should also enable the Internal Main Clock Oscillator The Clock Monitor has clock monitor function enable disable control bit clock fail det
314. ister in the interrupt mask will set or clear register It is a Read Write register On a Read this register gives the current value of the mask on the relevant interrupt A Write of 1 to the particular bit sets the mask enabling the interrupt to be read A Write of 0 clears the corresponding mask SAMSUNG ELECTRONICS 18 11 ex S3FN429_UM_REV1 20 18 Watchdog Timer 18 3 1 7 WDT_RISR e Base Address 0 4003 0000 e Address Base Address 0x0018 Reset Value 0x0000 0001 31 30 29 28 27 26 25 24123 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 e wow worew Watchdog Overflow interrupt raw state Gives the raw interrupt state prior to masking of the WDTOVF interrupt Watchdog Pending interrupt raw state Gives the raw interrupt state prior to masking of the WDTPEND interrupt NOTE On a Read WDT RISR register gives the current raw status value of the corresponding interrupt prior to masking SAMSUNG ELECTRONICS 18 12 ex S3FN429_UM_REV1 20 18 Watchdog Timer 18 3 1 8 WDT_MISR e Base Address 0 4003 0000 e Address Base Address 0x001C Reset Value 0x0000 0000 31 30 29 28 27 26 25 24123 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 gt wow worreno __ Watchdog Overflow interrupt mask Gives the masked interrupt status after masking of the WDTOVF interrupt 0 The WDTOVF interrupt does not occur 1 The WDTOVF interrupt occurs Wat
315. it in ADC_CR e Sample analog input voltage and every channel completes conversion with 5 ADC clock cycles e When the channels defined as a sequence are converted the EOC bit in ADC_RISR sets to 1 e CPU then reads the digital value in ADC_CRRx that automatically clears the EOC You can clear EOC by writing 1 in ADC_ICR SAMSUNG ELECTRONICS 4 15 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 2 Register Description 4 2 1 Register Map Summary e Base Address 0 4004 0000 RSVD ADC_CBRO 0x0100 Conversion buffer register 0 0x0000_0000 SAMSUNG ELECTRONICS 4 16 S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC Description Resetvalee SAMSUNG ELECTRONICS 4 17 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 2 1 1 ADC_IDR e Base Address 0 4004 0000 e Address Base Address 0x0000 Reset Value 0x0001_001F Reserved ID Code Register 0x0001_001F This field stores the ID code for the corresponding IP SAMSUNG ELECTRONICS 4 18 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 2 1 2 ADC_CEDR e Base Address 0 4004 0000 e Address Base Address 0x0004 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 R WwW Debug Mode Enable 0 Disables debug mode DBGEN 31 RW ADC not halted during processor debug mode
316. itor Reset 5 29 5 6 5 Watchdog Timer Reset sse nennen netten sinn niter ens 5 29 5 6 6 Software Reset 1 nsn tris sitne entente sentis intet nnns 5 29 5 6 7 CPU Request Reset SYSRST 5 29 5 7 BASIC TIMO 5 30 5 8 Fast Wake UP eal elie dni 5 32 5 9 Register 5 34 5 9 1 Register Map tee EXERCERE ELE He ERE e re REC e dene 5 34 5 10 Guide Glock Initialization 5 76 6 COMPARATOR 6 1 E 6 1 Gull EE 6 1 6 1 2 Pin DeSCrIDlHIOD een opto tpe E REDE 6 1 6 2 Functional DesCriptiOH tuns Eun tet uv dul ot ua de uu dut eur 6 2 6 21 Block Diagram eter orm 6 3 06 22 Comparator Input ioc emeret titi at epa cuta 6 4 6 2 3 Comparator OUID L s ro c se pains ete aa Eo i D 6 4 mur av lexeievmeuesism 6 4 0 2 5 Intetr pl cci dae 6 4 5 3 Register DESCriptlon eer cm
317. k Manager defines 000 FIN 001 FIN 2 IMCLKSEL 18 16 RW 010 FIN A 011 FIN 8 100 FIN 16 101 FIN 32 110 FIN 64 111 FIN 128 NOTE The clock source of dead time compare register is IMCLK PWM Output off Enable by Comparator This field determines whether the PWM output signal is enabled disabled by detecting edge in the comparator een 15 RW block The PWM output goes to High Z state if this bit is BYCOMP 4 set to 1 0 Enables PWM output signal 1 Disables PWM output signal PWM Output Enable Bit PWMOUTEN 14 Rw This field determines whether the PWM output signal is enabled disabled The PWM output goes to High Z state when this bit is set to 1 You can use this bit SAMSUNG ELECTRONICS 10 30 227 S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC during debugging 0 Enables PWM output signal 1 Disables PWM output signal PWM Output Disable by PWMxOFF This field determines the PWM output disable by PWMXxOFF PWMOUTOFFEN 13 RW 0 Disables PWM output disable by PWMxOFF 1 Enables PWM output disable by PWMxOFF NOTE If this bit is set to 1 and PWMXxOFF condition is met then the PWM output goes to High Z state L x PWMXxOFF Enable Bit PWMOFFEN 12 This field determines the PWMxOFF enable disable 0 Disables fault detection of PWMxOFF 1 Enables fault detection of PWMxOFF mv 188 007 Filter Clock Selection of PWMxOFF Pin This field determines the filt
318. k Pre scale Divisor Field CPSDVSR 7 0 RW Should be an even number from 2 to 254 depending on the frequency of FSSPCLK The least significant bit always returns zero on reads SSPCPSR is the clock pre scale register and specifies the division factor by which the input should be internally divided before any use The value programmed into this register should be an even number between 2 to 254 The least significant bit of the programmed number is hard coded to zero If an odd number is written to this register the data can be read back from this register that has zero as its least significant bit SAMSUNG ELECTRONICS 15 23 ex S3FN429_UM_REV1 20 15 Serial Peripheral Interface SPI 15 3 1 6 SSP_IMSCR e Base Address 0x4009 0000 0x4009 1000 e Address Base Address 0x0014 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 Transmit FIFO Interrupt Mask 0 Tx FIFO half full or less condition interrupt is masked Disables the interrupt 1 Tx FIFO half full or less condition interrupt is not masked Enables the interrupt Receive Timeout Interrupt Mask 0 RxFIFO not empty and no read prior to timeout period interrupt is masked Disables the interrupt 1 RxFIFO not empty and no read prior to timeout period interrupt is not masked Enables the interrupt Receive Overrun Interrupt Mask 0 RxFIFO written to while full condition interrupt is maske
319. lable 55K pull up resistor and 2500 analog input The status of input data is high when this is an output mode NOTE B4 Output Max Operation Freq 8 MHz Output Data gt Output Enable Co Pull up Enable Input Enable C gt Input Data lt Analog In Output lt gt Figure 2 2 Pin Circuit Type P0 0 to P0 11 and 0 18 to P0 31 SAMSUNG ELECTRONICS 2 11 ex S3FN429_UM_REV1 20 2 Pin Configuration 2 6 1 2 Type B Bi directional buffer with lol 24 mA 1 V in 5 V operation at 25 C output driver and enables schmitt trigger cmos input with controllable 55K pull up resistor and 250 analog input Output Data gt Output Enable gt Pull up Enable Input Enable gt Input Data lt lt Analog In Output lt gt Figure 2 3 Pin Circuit Type B 0 12 to 17 2 6 1 3 MODE1 and MODEO Schmitt trigger cmos input with 55K pull down resistor Input Data Figure 2 4 Pin Circuit Type C MODE1 and MODEO SAMSUNG ELECTRONICS 2 12 ex S3FN429_UM_REV1 20 2 Pin Configuration 2 6 1 4 nRESET Bi directional buffer with B8 NOTE output driver and enable schmitt trigger cmos input with always 250K pull up resistor NOTE 8 Output Max Operating Freq 15 MHz Output Data gt Output Enable gt Input Enable gt Input Data lt Figure 2 5 Pin Circuit Type D nRESET SAMSUNG ELECTRONICS 243 ex S3FN429_UM_REV1 20 3 System Memory Management System Memo
320. mask set clear control Bit Interrupt Source X X RW 0 Disables Source X interrupt 1 Enables Source X interrupt Reserved 9 NOTE Read CM_IMSCR register provides the current value of the mask the relevant interrupt A Write of 1 to the particular bit clears the mask A Write of 0 sets the corresponding mask SAMSUNG ELECTRONICS 5 50 en S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 1 11 CM_RISR e Base Address 0 4002 0000 e Address Base Address 0x0034 Reset Value 0x0000 001B o EMCKFAIL END RSVD Revo 2119 Command Error Interrupt CMDERR Gives the raw interrupt state prior to masking of the CMDERR interrupt Reset Level Detect Status This bit is only to show the status It does not generate the interrupt when it is set to 1 This bit is set to 1 when the LVDRS LVD detect the defined reset voltage level regardless of LVDRSTEN bit status This bit has the same value with LVDRS bit of CM SR register Write 1 into the LVDRS bit of the CM ICR register to Clear this bit Interrupt Level Detect of LVD Interrupt Gives the raw interrupt state prior to masking of the LVDINT LVDINT interrupt This bit becomes 1 when LVDINTEN bit in CM_MR register is set to 1 External Main Clock Failure Interrupt EMCKFAIL Gives the raw interrupt state prior to masking of the EMCKFAIL interrupt EMCKFAIL Main ook Failure Eng Interrupt END Gives the raw interrupt state prior to maski
321. masking A Write has no effect SAMSUNG ELECTRONICS 15 25 ex S3FN429_UM_REV1 20 15 Serial Peripheral Interface SPI 15 3 1 8 SSP_MISR e Base Address 0x4009 0000 0x4009 1000 e Address Base Address 0x001C Reset Value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 Transmit FIFO Masked Interrupt State Gives the transmit FIFO masked interrupt state after masking of the SSPTXINTR interrupt Receive FIFO Masked Interrupt State Gives the receive FIFO masked interrupt state after masking of the SSPRXINTR interrupt Receive Timeout Masked Interrupt State Gives the receive timeout masked interrupt state after masking of the SSPRTINTR interrupt Receive Overrun Masked Interrupt State Gives the receive overrun masked interrupt status after masking of the SSPRORINTR interrupt NOTE Ona Read SSP_MISR register gives the current masked status value of the corresponding interrupt A Write has no effect SAMSUNG ELECTRONICS 15 26 ex S3FN429_UM_REV1 20 15 Serial Peripheral Interface SPI 15 3 1 9 SSP_ICR e Base Address 0x4009 0000 0x4009 1000 e Address Base Address 0x0020 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 Receive Timeout Interrupt Clear 0 No effect 1 Clears the SSPRTINTR interrupt Receive Overrun Interrupt Clear 0 No effect 1 Clears the SSPRORINTR interrupt
322. memory addresses for Smart Options e Configuration Smart Option 0x0000 00 e Protection Smart Option 0x0000_00C4 9 2 2 1 Configuration Smart Option The Configuration Smart Option includes four hardware configuration values If you want to change the configuration you can do that by Smart Option Erase and Smart Operation Program The Configuration Smart Option value should be configured at address 0x0000_00CO The four kinds of configuration are e POCCS Configuration CPU clock selection at reset time XIN Pin Configuration Selection between XIN and P0 31 general function pin e XOUT Pin Configuration Selection between XOUT and P0 30 general function BT Divider Configuration Basic timer divider value selection Table 9 5 describes the Configuration Smart Option address and control bits Table 9 4 Configuration Smart Option Address and Control Bits Power On CPU system Clock Selection Bit 0 0 External Main Clock EMCLK 1 Internal Main Clock IMCLK XIN Pin Configuration Bit Bit 2 0 31 as the general function pin 1 XIN as the system pin XOUT Pin Configuration Bit Bit 3 0 P0 30 as the general function pin 0x0000 00CO 1 XOUT as the system pin Basic Timer Divider Value Configuration Bit 0000 0001 0010 Not used 0011 1 0100 2 0101 4 0110 8 15 12 0111 16 1000 32 OxF 1001 64 1010 128 1011 256 1100 512 1101 2 1024 1110 2048 1111 2 4096 x
323. n Bit 0 Low Level 1 High Level PWMXxD1 Output Level Selection Bit 0 Low Level 1 High Level PWMXxD 2 Output Level Selection Bit 0 Low Level 1 High Level Reserved 7 2 2 2 2 2 2 PWMXxUO PWM Output Enable Bit 0 Enables PWM signal to PWMxU0 1 Disables PWM signal to PWMxU0 5 IMCON1 13 determines the level of PWMxUO PWMxU1 PWM Output Enable Bit 0 Enables PWM signal to PWMxU1 1 Disables PWM signal to PWMxU1 IMCON1 12 determines the level of PWMxU1 PWMxU2 PWM Output Enable Bit 0 Enables PWM signal to PWMxU2 1 Disables PWM signal to PWMxU2 IMCON1 11 determines the level of PWMxU2 PWMXxDO PWM Output Enable Bit 0 Enables PWM signal to P MxDO 1 Disables PWM signal to PNMxDO IMCON1 10 determines the level of PWMxD2 PWMxD1 PWM Output Enable Bit 0 Enables PWM signal to PWMxD1 1 Disables PWM signal to PWMxD1 IMCON1 9 determines the level of PWMxD1 2 2 D 20 D PWMxDOEN PWMxD1EN mn SAMSUNG ELECTRONICS 10 39 z S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC PWMxD2 PWM Output Enable Bit 0 Enables PWM signal to PWMxD2 PWMxD2EN RW 1 Disables PWM signal to PWMxD2 IMCON1 8 determines the level of PWMxD2 NOTE There is no relationship between level setting in the IMC_CR1 register and SWAP function in the register SAMSUNG ELECTRONICS 10 40 ex S3FN429_UM_REV1 20 10 Inverter Motor C
324. n Constant 15 bit fixed point unsigned value from ADC GCCR Figure 4 7 ADC Calibration Scheme The process to get adjusted ADC conversion data consists of two steps The two steps are e Determine the gain and offset calibration constants e Run calibration unit with the non calibrated data generated by direct conversion on ADC macro cell SAMSUNG ELECTRONICS 4 11 x S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 1 10 2 Calibration Unit Operation DAT_CAL ADC_GCC x DAT_NCAL ADC_OCC 2 You should determine these constants and write corresponding register ADC_GCCR and ADC_OCCR values before using calibration function You should determine two pairs of expected DAT_CAL and measured DAT_NCAL values that are available for two reference voltages You can select between internal and external voltage Reference voltages are 25 percent and 75 percent of VREF e VREF Reference voltage value to convert ADC input voltage selected by you in voltage range e 1 4VREF 25 percent point voltage of VREF voltage value e 3 4VREF 75 percent point voltage of VREF voltage value Figure 4 8 illustrates 2 point calibration Expected Conversion Measured DAT NCAL 3 4 VREF Expected DAT CAL 9 3 4 VREF Expected CAL 1 4 VREF Measured DAT NCAL Q 1 4 VREF OV 1 AVREF 3 4 VREF Figure 4 8 2 Point Calibration SAMSUNG ELECTRONICS 4 12 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC The
325. n capture timer whenever position counter is changed up or down Position Counter Clear Bit This bit clears the content of position counter register PCCL 2 RW 0 effect 1 Clears the counter register NOTE This bit is automatically cleared after clear Position Capture Timer Clear Bit PCTCL 1 Clears the position capture timer NOTE This bit is automatically cleared after clear Position Capture Timer Enable This bit enables or disables position capture timer 0 Disables position capture timer Stop 1 Enables position capture timer Start NOTE PCCL SCCL PCTCL and SCTCL are automatically cleared after clears PZCL bit clears PCR SAMSUNG ELECTRONICS 7 14 ex S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 3 1 6 PPD_SR e Base Address 0x400C_0000 e Address Base Address 0x0014 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 gt estar e Par e gt gt gt __ PHASEB Status Bit 0 Specifies Low level 1 Specifies High level NOTE This bit is a read only bit PHASE A Status Bit 0 Specifies Low level PAREAN 2 1 Specifies High level NOTE This bit is a read only bit Glitch Detection of PHASEA PHASEB and PHASEZ This bit notifies the glitch detection in the PHASEA PHASEB or PHASEZ pin Read 0 Glitch does not occur GLIT
326. n control 1 Selects internal gain control 11911411 99 111490 eo pt x00 pt 1 o Feud This has an effect on an internal gain control _ _ _ a _ 1 6 0005 _____ lt pt pt 1 x50 pt e SAMSUNG ELECTRONICS 13 9 02000000 S3FN429_UM_REV1 20 14 Pulse Width Modulation Pulse Width Modulation 14 1 Overview The Pulse Width Modulation PWM chapter describes the on chip PWM generator The PWM is common technique to control power devices in industrial fields PWM output channel uses 16 bit up counter to generate rectangular pluses with the programmable period and duty ratio It has output extensions up to 22 bit resolution 14 1 1 Features The features of PWM are e The control bit allows the new configuration of Programmable duty cycle and frequency Programmable active level Duty ratio from 0 to 1 with 16 bit resolution e The PWM output signal control is Programmable idle level e The Enable Disable interrupt sources are Pulse start and stop Period start and end Pulse match e The extension cycle circuit implements the PWM extension funct
327. n describes the phase signal generation process 10 2 3 1 Tri Angular Wave IMMODE 0 PWMSWAP 0 PWMPOLU 0 Low Start and PWMPOLD 1 High Start You can use these phase signals when switches of UP side and DOWN side are High active in three phase motor application This implies one pair of switches of UP side and DOWN side do not have the conditions that are High active simultaneously It inserts the dead time appropriately Figure 10 4 illustrates the Tri Angular wave No SWAP Low Start PWMxUy and High Start PWMxDy MG TCA i osx ois ee ASCRR2 IMC P CRR ce eb Ga ASCRR1 PCCFR dor IMC_ASCFR2 IMC_ASCRRO IMC_PACRR IMC_ASCFR1 o Romo 2205052 e de Pere eoe nS Ie ie ee PACFR ASCFRO Interrupt Can be used by ADC trigger signal Figure 10 4 Tri Angular Wave No SWAP Low Start PWMxUy and High Start PWMxDy NOTE For 100 duty of upside you should set the rising falling compare register to 0 For 0 95 duty of upside you should set the rising compare register to equal to TOPCMP value SAMSUNG ELECTRONICS 10 5 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC Figure 10 5 illustrates the signal of PWM Assumption Duration of dead time is 2 percent duty Upside Upside 025 duty 33 duty setting Setting
328. n time ADCSTABLE bit in Status Register SR is set after stabilization SAMSUNG ELECTRONICS 4 21 x S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 2 1 5 ADC_CCR e Base Address 0 4004 0000 e Address Base Address 0x0010 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 ert ADC Core Enable Clear Bit W 0 Noeffect 1 Disables ADC core bit SAMSUNG ELECTRONICS 4 22 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 2 1 6 ADC_CDR e Base Address 0 4004 0000 e Address Base Address 0x0014 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R R R R R R WIN WIW W W mw era n resem 9 ADC Clock Divider Selection Field This field determines the ADC clock frequency The frequency is from 1 to 5 MHz FADC PCLK 2 x CDIV 1 Ex PCLK 20 MHz CDIV 1 FADC ADC clock 5 MHz PCLK 20 MHz 9 FADC ADC clock 1 MHz NOTE The clock for ADC should not exceed 5 MHz SAMSUNG ELECTRONICS 4 23 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 2 1 7 ADC_MR e Base Address 0 4004 0000 e Address Base Address 0x0018 Reset Value 0x0000 0000 30 29 28 27 26 25 24 23 22 21 20 19 18 17 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WIN W W W
329. n when Reset Value of SYSCLK is IMCLK If you use an interrupt method you should configure corresponding interrupt source interrupt vector and interrupt service routine before target event execution In a step on Figure 5 21 and Figure 5 22 you need to check CM MISR instead of CM RISR register SAMSUNG ELECTRONICS 5 77 iD S3FN429_UM_REV1 20 5 Clock and Power Manager For example if you use STABLE interrupt when changing SYSCLK the interrupt configuration includes the followings e Interrupt handler function Also be called Interrupt Service Routine ISR e Interrupt source selection and unmask Interrupt Enable e Interrupt vector enable Define interrupt handler service routine Void if CM MISR amp STABLE STABLE CM ICROSTABLE 1 Clear interrupt pending bit UserCommand Handler code for STABLE interrupt Enable CM included STABLE interrupt vector IRQ14 NVIC ISERO IRQ14 1 Enable STABLE interrupt CM IMSCR gt STABLE 1 SAMSUNG ELECTRONICS 5 78 ex S3FN429_UM_REV1 20 6 Comparator Comparator 6 1 Overview The chapter describes comparators in S8FN429 device This microcontroller has four Comparators The operation of four Comparators is individually controlled by registers 6 1 1 Features The three features of Comparators are e Configurable reference voltage selection e Output voltage of OP AMP is used for comparator input e Comparator ou
330. nchronous Receiver Transmitter 17 4 Receiver The receiver section includes e Asynchronous Receiver e Synchronous Receiver 17 4 1 Asynchronous Receiver The USART is configured for asynchronous operation when SYNC 0 8 bit of US_MR In asynchronous mode the USART detects the start of a received character by sampling the RXD signal until it detects a valid start bit USART interprets a low level signal on RXD as a valid start bit if it detects the signal for more than seven cycles of the sampling clock which is 16 times the BaudRate Therefore it detects the signal that is longer than 7 16 of the bit period as a valid start bit It ignores a signal that is 7 16 of a bit period or shorter and the receiver continues to wait for a valid start bit When the receiver detects a valid start bit it samples the RXD at the theoretical mid point of each bit It assumes that each bit lasts for 16 cycles of the sampling clock one bit period Therefore the sampling point is eight cycles 0 5 bit periods after the start of the bit The first sampling point is 24 cycles 1 5 bit periods after detecting the falling edge of the start bit The receiver samples 16 cycles 1 bit period for each subsequent bit after the previous bit Figure 17 3 illustrates the asynchronous mode start bit detection Rate Clock OUT Sampling True Start DO Detection Figure 17 3 Asynchronous Mode Start Bit Detection Figure 17 4 illustrates th
331. nchronous write happens only once in every 30 times ADC trigger signal is in the same situation Inverter Motor Mode Selection Bit 0 Tri Angular shape IMMODE 1 RW 1 Saw Tooth snaps You can change this bit only when 0 is 0 If this bit is set 1 then the comparison with has no effect INT ZEROXx will not be occurred Inverter Motor Block Enable Bit This field determines the inverter motor block enable disable IMEN 0 Disables inverter motor block 1 Enables inverter motor block NOTE If this bit is set to 0 then the IMCNT bit is automatically cleared to 0 NOTE If IMEN is equal to 0 all PWM output PWMxU Dx goes to High Z state SAMSUNG ELECTRONICS 10 32 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC Figure 10 24 illustrates the synchronous write at zero and IMC_TCR match If PxCRR is changed from 0x30 to Ox60 in the immediate mode in the A period the PWM signal is changed immediately in that period IMO PxGR MEER Mee IMC_PxCR x x Ox30 0 60 IMC_TCR 0x90 PWMxUx If PxCRR is changed from 0x30 to Ox60 in the immediate mode in the period the PWM signal is changed immediately in the next period IMO PxOR IMC_PxCR IMC_PxCR x x x 0x30 0x60 A B IMC_TCR 0x90 PWMxUx Figure 10 24 Synchronous Write at Zero and IMC_TCR Match SYNCSEL 00 b NUMSKIP 00000 b NOTE If the
332. ng of the EMCKFAIL_END interrupt PLL Stable Interrupt Gives the raw interrupt state prior to masking of the PLL interrupt SAMSUNG ELECTRONICS 5 51 ex S3FN429_UM_REV1 20 5 Clock and Power Manager SYSCLK Clock Switching Stable Interrupt STABLE 4 Gives the raw interrupt state prior to masking of the STABLE interrupt mew ea a Reseed Internal Main Clock Stable Interrupt IMCLK 1 Gives the raw interrupt state prior to masking of the 1 IMCLK interrupt External Main Clock Stable Interrupt EMCLK Gives the raw interrupt state prior to masking of the 1 EMCLK interrupt NOTE 1 Read CM_RISR register gives the current raw status value of the corresponding interrupt prior to masking A Write has no effect 2 After reset release some bits STABLE ISCLK ESCLK IMCLK EMCLK are set to 1 Therefore we recommend clearing those bits above to use the CM ICR register after the Reset release SAMSUNG ELECTRONICS 5 52 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 1 12 CM_MISR e Base Address 0 4002 0000 e Address Base Address 0x0038 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 gt gt ___ __ e EMCKFAILEND 9 Command Error Interrupt Gives the unmasked interrupt state after unmasking of CMDERR 18 the CMDERR interrupt 0 Each interrupt does not occur 1 Each
333. nnel nPULSE width starts at the end of PULSE width When you configure a PWM channel to disable in the middle of the PWM PERIOD it will not disable the PWM output immediately Disable of the PWM output will be activate at the end of nPULSE The nPULSE width represents the PWM output nACTIVE state PULSE field in PWM_PULR register controls the number of up counter cycles to fix nACTIVE width e PULSE 15 0 for the 16 bit PWM PULSE Width PMATCH bit in the PWM RISR register indicates the start of nPULSE width and PEND bit indicates the PERIOD cycle end PWM_CSR register bit clears the status of PMATCH and PEND bits The software has the possibility to enable disable the PSTA or PEND or both the interrupts If you configure PULSE field at 0 then the PULSE cycle does not exist The logical level configured by OUTPUTL bit drive PWM output until PWM channel remains enable For this particular case consider the configuration set by the UPDATE bit at the end of PERIOD cycle SAMSUNG ELECTRONICS 14 4 x S3FN429_UM_REV1 20 14 Pulse Width Modulation 14 2 7 IDLE Level IDLESL bit in the PWM_CSR Control Set Register PWM_CCR Control Clear Register controls idle level to fix the PWM output level on the high or low It is done when PWM stops on the START bit in PWM_CCR Control Clear Register or when CLKEN bit in the PWM_CEDR Clock Enable Disable Register disables the clock 14 2 8 Parameter Relationship The parameter relationships are e
334. nsfer occurs the TXRDY bit in US SR is set to 1 until a new character is written to US THR If the Transmit Shift Register and the 05 THR are empty then the TXEMPTY bit in 05 SR is set to 1 after the last stop bit of the last transfer Figure 17 7 illustrates the synchronous and asynchronous modes of character transmission Example 8 Bit Parity enabled 1 Stop Baud Rate DO D1 D2 D3 D4 D5 D6 D7 Stop Bit Start Bit Parity Bit Figure 17 7 Synchronous and Asynchronous Modes Character Transmission SAMSUNG ELECTRONICS 17 15 ex S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 5 2 Time Guard The time guard allows the transmitter to insert an idle state on the USARTTX line between two characters The duration of the idle state is programmed in US_TTGR Transmitter Time Guard When the US_TTGR register is set to zero then no time guard is generated Otherwise the transmitter holds a high level on USARTTX after each transmitted byte during the number of bit periods programmed in US_TTGR register 17 5 3 Multi Drop Mode When a PAR field in the US_MR register is equal to 11xB the USART is configured to run in multi drop mode for automatic address data detection The PARE Parity Error bit in the US_SR register is used to identify a data byte parity bit is detected low or an address byte parity bit is detected high Therefore in the multi drop mod
335. ntegral linearity error 3 5 LSB Max at 2 5 to 5 5 V 4 1 2 Pin Description Table 4 1 describes the pin description of ADC Table 4 1 ADC Pin Description AVREF Reference top voltage Analog Input o AIN 10 1 Analog inputs Analog Input ADTRG External start trigger signal Digital Input NOTE You should write AIN1 value in ICNUM field of CCSRx register to convert analog signal asserted on pin SAMSUNG ELECTRONICS 4 1 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 1 3 Block Diagram Figure 4 1 illustrates the block diagram of ADC ADC_CBRO ADC CRRO 11 0 ADC CBR1 ADC CRR1 11 0 ADC CBR2 ADC CRR2 11 0 ADC CBR3 ADC CRR3 11 0 ADC CBR4 ADC CRR4 11 0 ADC CBR5 _ 5 11 0 CBR6 ADC_CRR6 11 0 ADC_CBR7 ADC CRR7 11 0 CBR8 ADC CRR8 11 0 Calibration ADC OCR ADC_CBR9 CRR9 11 0 ADC CBR10 CRR10 11 0 Conversion Channel Select MUX ADC IMSCR x ADC_MR CCNT CCSRO ICNUM 7 0 Interrupt INT_OVR ADC_CCSR1 ICNUM 10 8 controller INT_EOC ADC MR x x START S W ADTRG Timer IMC ADCTrigger Figure 4 1 ADC Block Diagram SAMSUNG ELECTRONICS 4 2 ex S3FN429_UM_REV1 20 4 Analog to Digital Converte
336. ntroller IMC supports e 3 Phase 16 bit PWM generation e Programmable dead time insertion e Output off control by fault input signals e ADC conversion start signal generation Universal Synchronous Asynchronous Receiver Transmitter USART The Universal Synchronous Asynchronous Receiver Transmitter USART supports e 5 6 7 8 and 9 bit data length e Programmable baud rate generator e Parity framing and overrun error detection Loop back mode e Full duplex e flag for 41587 protocol e Smart card protocol error signaling and re transmission Serial Peripheral Interface SPI The Serial Peripheral Interface SPI supports e Programmable data frame from 4 to 16 bit e Master and slave mode e Programmable clock pre scale e Separate 8 8 x 16 bit width Transmit Receive First In First Out FIFO Analog to Digital Converter ADC The Analog to Digital Converter ADC contains e 12 bit resolution e 10 input pins for conversion input signal AIN 10 1 e ADC has a conversion channel for OP AMP AINO e Various conversion start sources START software ADTRG external input signal and internal peripherals IMC Timer SAMSUNG ELECTRONICS 1 5 ex S3FN429_UM_REV1 20 Operational Amplifier OP AMP The Operational Amplifier OP AMP supports e The operation with ADC e Both an internal and external gain control Comparator COMP The Comparator contains e Configurable reference voltage selection
337. o 17 29 Reset Value S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter Number of re transmission Indicates the maximum number of repetitions a character has to be transmitted by the USART when configured as smart card protocol e SENDTIME configuration field RSVD 1 0 Reserved 0 SAMSUNG ELECTRONICS 17 30 ex S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 8 1 6 US IMSCR e Base Address 0x4008 0000 e Address Base Address 0x0014 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RSVD era R Reeve 0 7 IDLE Interrupt Mask IDLE 10 RW 0 This interrupt is masked Disables an interrupt 1 This interrupt is not masked Enables an interrupt Transmitter Empty Interrupt Mask TXEMPTY 0 This interrupt is masked Disables an interrupt 1 This interrupt is not masked Enables an interrupt Time Out Interrupt Mask TIMEOUT 0 This interrupt is masked Disables an interrupt 1 This interrupt is not masked Enables an interrupt Parity Error Interrupt Mask PARE 0 This interrupt is masked Disables an interrupt 1 This interrupt is not masked Enables an interrupt me tour gt e Overrun Error Interrupt Mask OVRE 0 This int
338. o masking of PCSOVF interrupt Position Counter Match Raw Interrupt State PCMAT Gives the raw interrupt state prior to masking of PCMAT interrupt NOTE On a Read PPD RISR gives the current raw status value of the corresponding interrupt prior to masking A Write has no effect Position Capture Raw Interrupt State PCAPT Gives the raw interrupt state prior to masking of PCAPT interrupt e Sign overflow bit is set when counter value is changed from Ox7FFF to 0x8000 e Sign underflow bit is set when counter value is changed from 0x8000 to Ox7FFF e Carry overflow bit is set when counter value is changed from OxFFFF to 0x0000 e Carry underflow bit is set when counter value is changed from 0x0000 to SAMSUNG ELECTRONICS 7 19 ex S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 3 1 9 PPD_MISR e Base Address 0x400C_0000 e Address Base Address 0x0020 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCTOVF gt gt scsov gt somt SCCUNF SCCOVF PHASEZ Masked Interrupt State Gives the masked interrupt state prior to masking of PHASEZ interrupt Reserved Speed Counter Carry Underflow Masked Interrupt State Gives the masked interrupt state prior to masking of SCCUMF interrupt N e lt L a PCCUNF 22 recor PCTOVF PCSUNF s e PHASE
339. o not set the value P 5 0 or M 7 0 to all zeros Four M 7 0 8 x FIN P 5 0 2 2 1 0 when LFPASS 0 Output frequency of PLL 5 PLLCLK M 7 0 8 x FIN 2 1 0 when LFPASS 1 SAMSUNG ELECTRONICS 5 8 ex S3FN429_UM_REV1 20 5 Clock and Power Manager Figure 5 4 illustrates the PLL block diagram Pump Detector Oscillator LFPASS M F Fs Phase gt charge Voltage Pre Divider Frequency gt 9 Controlled Post Scaler Four i Figure 5 4 PLL Phase Locked Loop Block Diagram The PLL within the clock generator is the circuit that synchronizes the Output Signal with a reference or Input Signal in the frequencies and phases It includes the VCO to generate the Output Frequency the divider P to divide the reference frequency by p the divider M to divide the VCO Output Frequency by m the divider S to divide the VCO Output Frequency the phase detector charge pump and loop filter 5 2 4 1 Phase Frequency Detector The Phase Frequency Detector monitors the phase difference between the the reference frequency and the the feedback frequency The Phase Frequency Detector generates a control signal when it detects a difference between the two frequencies 5 2 4 2 Charge Pump The Charge Pump converts the Phase Frequency Detector control signal to a charge in volta
340. ock up Cortex MO supports the flag of CPU Lock up status and reset signal Use this in case of a malfunction SAMSUNG ELECTRONICS 18 9 x S3FN429_UM_REV1 20 18 Watchdog Timer 18 3 1 5 WDT_SR e Base Address 0 4003 0000 e Address Base Address 0x0010 Reset Value 0x8000 0100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 09 amp 2 1 4 EN Status DBGEN 0 Disables debug mode 1 Enables debug mode e CLEAR STATUS gt Watchdog Pending status 0 Watchdog counter is more than the pending window PENDING length 1 Watchdog counter is equal or less than pending window length Clear Status 0 Finishes Watchdog Counter Reset LEAR_STATUS 5 1 Watchdog Counter Reset operation starts and does not end SAMSUNG ELECTRONICS 18 10 ex S3FN429_UM_REV1 20 18 Watchdog Timer 18 3 1 6 WDT_IMSCR e Base Address 0 4003 0000 e Address Base Address 0x0014 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24123 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 gt woren Watchdog Timer Overflow Interrupt Mask 0 Disables the interrupt This interrupt is masked 1 Enables the interrupt This interrupt is not masked Watchdog Timer Pending Interrupt Mask 0 Disables the interrupt This interrupt is masked 1 Enables the interrupt This interrupt is not masked NOTE WDT_IMSCR reg
341. omes one of the error cases If you use the command not to be defined the flash controller generates the signal for an error That is defined as an ERR1 You can catch the error occurred with RISR status and MISR interrupt register SAMSUNG ELECTRONICS 9 30 __ mw _ 164 A 5 S3FN429_UM_REV1 20 9 Internal Flash Controller IFC NOTE The register clears automatically after finishing the operation of command You can write any value in the register but it will not be affected You should check END status interrupt for next command operation 1 The operations that support are SOP Smart Option Program SOE Smart Option Erase 2 The IFC_CR determines the program erase operation In user program mode internal flash controller can support Normal Program Smart Option Program Smart Option Erase Sector Erase and Entire Erase Among six operations select only one operation SAMSUNG ELECTRONICS 9 31 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 3 1 5 IFC_MR e Base Address 0x4001_0000 e Address Base Address 0x0010 Reset Value 0x0000 0080 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 revo __ _ Flash Speed Mode Selection Bit You should change the flash mode before the clock switching occurs from normal speed mode to high speed FSMODE p Rw ede 0 Selects normal speed flash mode Use this when the system clock frequency is less than or
342. ontroller IMC 10 3 1 6 IMC_CNTR Base Address 0 400 0000 Address Base Address 0x0014 Reset Value 0 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 91 16 0 Count Value 050 This contains the count value of the current IMC SAMSUNG ELECTRONICS 10 41 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 3 1 7 IMC_SR Base Address 0 400 0000 Address Base Address 0x0018 Reset Value 0 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 Reserved gt wow s gt gt Comparator Edge Detect This bit notifies the status of edge detection from comparator block 0 Does not detect 1 Detects NOTE If it detects the comparator edge then this bit retains The software clears this bit Status of PWM Counter Read Only Bit This bit notifies the status of PWM counter 0 Up counting 1 Down counting NOTE This bit is always 0 in the Saw Tooth mode Status of PWM Output Signal 0 Normal operating 1 High Z Inverter motor block is operating but the status of PWM signal is High Z This bit can be set by fault detection of PWMxOFF pin or IMC_CR0 14 NOTE If you write this bit to 0 and _ 14 is 0 then the inverter motor control signal is output to PWM output SAMSUNG
343. ops in conditon CPU stops 1502 condition EC Disabled EMCLK and IMCLK id All peripherals stop LVD OFF Disabled EMCLK and IMCLK PR All peripherals stop LVD ON NOTE Before entering into the Stop Mode each clock source will have an enabled or disabled status that is set by the user configuration Stop current implies that the microcontroller is in the stop mode In the stop mode all clocks are dead automatically 3 2 m D SAMSUNG ELECTRONICS 19 9 ex S3FN429_UM_REV1 20 19 Electrical Data 19 10 PLL Characteristics Table 19 10 describes the parameters belonging to the PLL characteristics Table 19 10 PLL Characteristics 40 to 105 Vppio 2 5to 5 5 Input frequency 0 NS 40 50 e _ 20 3 14 SAMSUNG ELECTRONICS 19 10 ex S3FN429_UM_REV1 20 19 Electrical Data 19 11 LVD Characteristics Table 19 11 describes the LVD characteristic parameters Table 19 11 LVD Characteristics 40 to 105 Vpp Vppio 2 5 to 5 5 V ei Vm o o y y 26 27 LVD detect voltage at Vpp falling Muell 5 1 35 Si E 11 of 1 You
344. p EMCMRST Clock fail Figure 5 6 External Main Oscillator Fail and Reset SAMSUNG ELECTRONICS 5 12 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 2 5 2 End of Clock Fail The EMCKFAIL_END bit indicates the end of External Main Oscillator Clock failure When External Main Oscillator Clock is recovered EMCKFAIL END bit in CM SR and CM_RISR register will be set to 1 Also you can use this event with an interrupt When the failure disappears EMCKFAIL END bit in CM SR register is set to 1 by edge recognition of the External Oscillator by Hardware the EMCKFAIL bit clears automatically The software is able to use the external oscillator again as the source clock Before switching to EMCLK the software should refer to these recommendations e Check the EMCLK bit in the CM SR register e Select the EMCLK by configuring the SYSCLK fields in the CM register Ensure to stabilize the External Main Clock Oscillator Figure 5 7 illustrates the end of clock fail diagram IMCLK Stabilized sampling Enable External Oscillator SYSCLK Change EMCLK for SYSCLK EMCKFAIL Clear EMCKFAIL EMCKFAIL_END Figure 5 7 of Clock Fail 5 2 6 Clock Out S3FN429 includes the five clock out ports to be configurable as an alternate function The clock frequency to output onto COPx is the divided speed by 8 because of the maximum IO speed You can output five different clock sources onto the COP pin using
345. p to 2 MHz and higher subjected to choice of frequency for SSPCLK The maximum bit rate is determined by the peripheral devices The PrimeCell SSP operating mode frame format and size are programmed through the control registers namely SSPCRO and SSPCR1 The four individually generated output interrupts that can be masked are SSPTXINTR SSPRXINTR SSPRORINTR and SSPRTINTR These contribute to e SSPTXINTR requests servicing of the transmit buffer SSPRXINTR requests servicing of the receive buffer e SSPRORINTR indicates an overrun condition in the receive FIFO e SSPHTINTR indicates that a timeout period expired while the data was present in the receive FIFO Depending on the operating mode selected the SSPFSSOUT output will operate as an active low slave select for the SPI 15 2 2 1 2 PrimeCell SSP Functional Description The functional descriptions for PrimeCell SSP are AMBA APB Interface e Register Block e Clock Pre scaler e Transmit FIFO e Receive FIFO e Transmit and Receive Logic e Interrupt Generation Logic SAMSUNG ELECTRONICS 15 4 x S3FN429_UM_REV1 20 15 Serial Peripheral Interface SPI 15 2 2 1 2 1 AMBA APB Interface The AMBA APB interface generates Read and Write decodes for accessing e Status and control registers e Transmit and receive FIFO memories The AMBA APB is a local secondary bus that provides a low power extension to the higher bandwidth AMBA Advanced High performance Bus AHB within th
346. pheral Interface SPI 15 1 1 1 Features of the PrimeCell SSP The features of the PrimeCell are Compliant to the AMBA Specification Revision 2 0 for easy integration into SOC implementation Master or slave operation Programmable clock bit rate and pre scale Separate transmit and receive FIFO memory buffers 16 bit wide and 8 locations deep Programmable data frame size of 4 16 bits Independent masking of transmit FIFO receive FIFO and receive overrun interrupts Internal loopback test mode 15 1 1 2 Programmable Parameters The programmable parameters are Master or slave mode Enabling of operation Frame format Communication baud rate Clock phase and polarity Data widths of 4 16 bits Interrupt masking 15 1 1 3 SPI Features The features of the Motorola SPI compatible interface are Full duplex four wired synchronous transfer Programmable clock polarity and phase 15 1 2 Pin Description Table 15 1 describes the pin description of the SSP SPI serial dock Table 15 1 SSP Pin Description Master in slave out Frame slave select master Frame input slave SAMSUNG ELECTRONICS 15 2 x S3FN429_UM_REV1 20 15 Serial Peripheral Interface SPI 15 2 Functional Description The functional description section includes e Block Diagram e Operation e Register Description 15 2 1 Block Diagram Figure 15 1 illustrates the SSP block diagram Transmit FIFO TxFRdDataln 15 0 16 bit wide 8 de
347. ponding mask SAMSUNG ELECTRONICS 14 22 ex S3FN429_UM_REV1 20 14 Pulse Width Modulation 14 3 1 8 PWM_RISR e Base Address 0x4007_0000 0x4007_ 1000 e Address Base Address 0x001C Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 e gt gt mee PEND emer Pulse Match Raw Interrupt State Gives the raw interrupt state prior to masking of PMATCH interrupt RSVD PMATCH PEND Period End Raw Interrupt State Gives the raw interrupt state prior to masking of PEND interrupt PWM Stop Raw Interrupt State Gives the raw interrupt state prior to masking of PWMSTOP interrupt PWM Start Raw Interrupt State Gives the raw interrupt state prior to masking of PWMSTART interrupt PWMSTOP PWMSTART NOTE On a Read PWM RISR register gives current raw status value of the corresponding interrupt prior to masking A Write has no effect Period Start Raw Interrupt State PSTART Gives the raw interrupt state prior to masking of PSTART interrupt SAMSUNG ELECTRONICS 14 23 ex S3FN429_UM_REV1 20 14 Pulse Width Modulation 14 3 1 9 PWM_MISR e Base Address 0x4007_0000 0x4007_ 1000 e Address Base Address 0x0020 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 e gt gt gt gt ___
348. r ADC 4 1 4 Input and Output ADC operation converts the signal asserted on AINx input pin to digital data The valid input signals are e Voltage range is from reference bottom to Top ADC uses AINx function pins to convert an analog input source e Input signal range is from reference top to reference bottom Input Voltage Range 0 0 V Vayner Reference Bottom 0 0 V Reference Top Vavrer Vavyner be from 2 5 to 5 5 V typical 5 V Assume Vayner 5 V UM 2 Resolution 4096 Table 4 2 describes the ADC Input and digital Output values Table 4 2 ADC Input and Digital Output index AMxinpsVolage v Digital Output Binary Digital Output EX _ 4093 4 996338 4 997558594 1111 1111 1101 4094 4 997559 4 998779297 1111 1111 1110 OxFFE 4095 4 998779 to 1111 1111 1111 OxFFF SAMSUNG ELECTRONICS 4 3 x S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 1 5 Clock Frequency and Conversion Time ADC operation obtains clock from PCLK ADC clock is not more than 5 MHz This feature is effective up toa 5 MHz maximum ADC clock If ADC operates with 5 MHz the conversion per channel is done in the minimum time 1 us Figure 4 2 illustrates the ADC operation timing T 73 T Disable Ts Enable AINx Conversioni Enable ADCEN START Trigger Pi BUSY Access CRRx Figure 4 2 ADC Operation Timing Diagram
349. ration SAMSUNG ELECTRONICS 14 18 ex S3FN429_UM_REV1 20 14 Pulse Width Modulation 14 3 1 5 PWM_CCR e Base Address 0x4007_0000 0x4007_ 1000 e Address Base Address 0x0010 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24123 22 21 20 19 18 17 16 15 14 13 12 11 10 6 5 4 3 2 1 0 wo ft amp s 19 Pwe e Pwes Pwe s fe pm 8 1 3 5 7 9 11 13 15 17 19 21 23 25 27 5 29 31 33 35 37 39 41 43 45 47 49 51 PWMEX2 53 55 57 59 61 63 PWMEX1 PWMEXO NOTE Combination of six control bits can contro PWMEXy For example e 1 Extension Case 1 PWMEX1 1 PWMEX2 1 1 PWMEX4 1 PWMEX5 1 e 2 Extension Case PWMEXO 1 and PWMEX5 1 PWMEX2 1 PWMEX3 1 and so on e Extension Case PWMEX1 1 PWMEX3 1 PWMEXA 1 PWMEXO 1 PWMEX2 1 PWMEX5 1 and so on 85 0 n ______ PWM Extension Control Bit 0 No effect 1 Deletes the a stretched cycle number fe 28 10 14 18 22 26 30 34 38 42 46 50 __ la 4 SAMSUNG ELECTRONICS 14 19 S3FN429_UM_REV1 20 14 Pulse Width Modulation PWM Interval Mode 0 No effect 11 w 1 Specifies PWM interval mode PWM phase toggles every period Keep Last Period State 0 No effect KEEP 10 W 119 1 Keep the PWM output l
350. ration describes the function values for each NOTE If OP AMP is enabled 2 should be set to OP AMP output pin SAMSUNG ELECTRONICS 12 5 ex S3FN429_UM_REV1 20 12 Configuration 12 3 1 2 IOCONF_MHRO e Base Address 0x4005 8000 e Address Base Address 0x0004 Reset Value 0x0000 F000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 1 0 100_16_FSEL 100_31_FSEL 100_30_FSEL 00 29 FSEL 00 28 FSEL 100_27_FSEL 100_26_FSEL 00 25 FSEL 00 24 FSEL 00 23 FSEL 00 22 FSEL 100 21 FSEL 00 20 FSEL 00 19 FSEL 0 18 FSEL 100_17_FSEL Nam Bk Tme Desorption Reset Value 00 31 FSEL 31 30 00 30 FSEL 29 28 00 29 FSEL 27 26 00 28 FSEL 25 24 00 27 FSEL 23 22 00 26 FSEL 21 20 00 25 FSEL 19 18 100 y Function Selection 24 FSEL 17 16 005 Function 0 GPIO 0_23 FSEL 15 14 rs elie 5 00 22 FSEL 13 12 11 b Function 3 00 21 FSEL 11 10 00 20 FSEL 9 8 00 19 FSEL 7 6 00 18 FSEL 5 4 100_17_FSEL 3 2 00 16 FSEL 1 0 NOTE 1 If you write unde
351. re 14 4 illustrates the PWM basic waveform OUTSL 0 diagram OUTSL 0 Low PERIOD 15 0 0x40 PULSE 15 0 0x0 PULSE 15 0 0x1 PULSE 15 0 0x20 PULSE 15 0 Ox3F rr FI PULSE 15 0 0x40 Figure 14 4 PWM Basic Waveform OUTSL 0 PWM Period 0x40 Pulse 0x0 0x1 0x20 0x40 SAMSUNG ELECTRONICS 14 7 ex S3FN429_UM_REV1 20 14 Pulse Width Modulation 14 2 9 Extension Bit Compare the values of extension counter with extension settings in the extension bits In every 64 periods some periods are Extension Periods Extension period with extended Pulse width is a clock longer than normal period PWMEX bits in TC SR register determines which period is Extension Period Because PWMEX is 6 bits long the PWM output has approximately up to 22 bit resolution though the counter is 16 bit long The stretch value is an extra clock period at specific intervals or cycles For example in 8 bit base and 6 bit extension value of 0 is equals to 1 then 29 cycle is one pulse longer than the other 63 cycles If the base duty cycle is 50 percent then the duty of the 329 cycle stretches approximately to 51 percent duty PWMEXS 4 12 20 28 36 44 52 60 PWMEX4 2 6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 en 53 55 57 59 61 63 For example if PWMEX 4
352. roller IMC 10 2 2 Operation There are two modes for the operation of IMC Tri Angular Wave mode e Saw Tooth Wave mode 10 2 2 1 Tri Angular Wave Some examples of Tri Angular wave mode are High Active Switch ON Inverter Motor Control PWMPOLU is to the value of LOW START PWMPOLD is the value of HIGH START TCR 7 DTCR 2 ASCRR0 6 PACRR PACFR 4 Figure 10 2 illustrates the Tri Angular wave signal generation DTCNT IMC TCR IMC DTCR IMC PACRR IMC PACFR IMC ASCRRO PWMXxUO PWMXxDO INTERRUPT can be used as ADC Trigger Signal Figure 10 2 Tri Angular Wave Signal Generation SAMSUNG ELECTRONICS 10 3 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 2 2 2 Saw Tooth Wave Some examples of Saw Tooth wave mode are e High Active Switch ON Inverter Motor Control PWMPOLU is set to the value of LOW START PWMPOLD is the value of HIGH START IMC_TCR 7 IMC_DTCR 2 IMC_ASCRRO 6 PACRR Figure 10 3 illustrates the Saw Tooth wave signal generation CV DTCNT IMC_TCR IMC DTCR IMC PACRR IMC ASCRRO PWMxUO 0 Interrupt Can be used by ADC trigger signal Figure 10 3 Saw Tooth Wave Signal Generation SAMSUNG ELECTRONICS 10 4 x S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 2 3 Phase Signal Generation This sectio
353. rrupt state prior to masking of the Pulse Match interrupt Period End Interrupt Gives the raw interrupt state prior to masking of the Period End interrupt Period Start Interrupt PSTARTI Gives the raw interrupt state prior to masking of the Period Start interrupt Stop Interrupt STOPI Gives the raw interrupt state prior to masking of the Stop interrupt Start Interrupt STARTI Gives the raw interrupt state prior to masking of the Start interrupt NOTE 1 TC IMSCR register does not affect the TC_RISR register 2 Ona Read TC RISR register gives the current raw status value of the corresponding interrupt prior to masking A Write has no effect SAMSUNG ELECTRONICS 16 31 ex S3FN429_UM_REV1 20 16 Timer Counter 16 3 1 10 TC_MISR e Base Address 0x4006 0000 0x4006 1000 0 4006 2000 e Address Base Address 0x0024 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 gt gt mn e gt 2 e gt som gt je Capture Interrupt Gives the masked interrupt status after masking of the Capture interrupt Overflow Interrupt Gives the masked interrupt status after masking of the Overflow interrupt Pulse Match Interrupt Gives the masked interrupt status after masking of the Pulse Match interrupt Period End Interrupt Gives the masked interrupt status after maskin
354. rupt Write has no effect SAMSUNG ELECTRONICS 17 36 ex S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 8 1 9 US_ICR e Base Address 0x4008_0000 e Address Base Address 0x0020 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 ASV pug R Idle Masked Interrupt State IDLE 10 W 0 Noeffect 1 Clears the idle interrupt Time Out Masked Interrupt State TIMEOUT 0 No effect 1 Clears the TIMEOUT interrupt Parity Error Masked Interrupt State PARE 7 0 No effect 1 Clears the PARE interrupt RSVD W Framing Error Masked Interrupt State FRAME 0 No effect 1 Clears the FRAME interrupt Overrun Error Masked Interrupt State OVRE 5 0 No effect 1 Clears the OVRE interrupt aR Resend Receiver Break Masked Interrupt State RXBRK 2 W 0 Noeffect 1 Clears the RXBRK interrupt RSVD R Reed SSS NOTE On a Write of 1 the corresponding interrupt is cleared A Write of 0 has no effect SAMSUNG ELECTRONICS 17 37 27 S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 8 1 10 US_SR e Base Address 0 4008 0000 e Address Base Address 0x0024 Reset Value 0x0000 0800 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 7 6 5 4 3 2 1 0 Idle Flag 0 A frame is
355. ry Management 3 1 Overview The System Memory Management chapter describes the system memory management for S3FN429 The chapter includes e Memory map e Special function register map The register maps are Core special function register map Peripheral special function register map 3 2 Default Memory Map Table 3 1 describes the SSFN429 memory space allocation Table 3 1 53 429 Memory 32 KB internal program flash memory Including smart option area SAMSUNG ELECTRONICS 3 1 ex S3FN429_UM_REV1 20 3 System Memory Management Reserved OxEOOF FFFF Cortex MO Internal Peripheral Registers 000 0000 v Reserved 400 FFFF Special Function Registers 0x4000_0000 Reserved 0x2000_07FF 2Kbytes Internal SRAM Memory 0x2000_0000 i Reserved 0x0000 7FFF 0x0000 00 4 gt 32Kbytes Internal Flash Memory 0x0000 00C0 0 0000_0000 a Protection Smart Option b Configuration Smart Option Figure 31 S3FN429 Memory SAMSUNG ELECTRONICS 3 1 227 S3FN429_UM_REV1 20 3 System Memory Management 3 3 Special Function Register Map The two types of special function register maps are e Core special function register map e Peripheral special function register map 3 3 1 Core Special Function Register Map Table 3 2 describes the core special function register map Table 3 2 Core Special Function
356. s 0x0010 Reset Value 0x0000 0000 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 40 9 87 6 5 4 e N WDTCLK gt ___ SPIOCLK gt ___ gt gt ___ _ IMCCLK gt ___ gt ___ gt ___ gt ___ gt ___ gt APB Clock Gating Control IPxCLK 0 No effect 1 Enables each peripheral clock NOTE The IOCLK includes the Configuration IOCONF and the GPIO pin SAMSUNG ELECTRONICS 5 42 ex S3FN429_UM_REV1 20 5 9 1 6 CM_PCCR e Base Address 0 4002 0000 e Address Base Address 0x0018 Reset Value 0x0000 0000 1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 14 13 12 11 10 9 8 gt ___ SPIOCLK gt ___ gt _ gt ___ _ PCLK APB Clock Gating Control IPxCLK 0 No effect 1 Disables each peripheral clock NOTE The IOCLK includes the IOCONF and the GPIO SAMSUNG ELECTRONICS 5 43 5 Clock and Power Manager e N k 7 6 5 4 gt ___ gt ___ gt ___ gt ___ gt ___ gt
357. s you can further optimize the power SAMSUNG ELECTRONICS 5 19 x S3FN429_UM_REV1 20 5 Clock and Power Manager 5 4 2 2 Exit IDLE Mode If you use the WFI instruction to enter the IDLE mode then any peripheral interrupt acknowledge by the Nested Vectored Interrupt Controller NVIC wakes up the device from the IDLE mode If you use the WFE instruction to enter the IDLE mode then the MCU exits the IDLE mode as soon as an event occurs Table 5 6 describes the IDLE on Sleep Now Table 5 6 IDLE on Sleep Now Use the WFI or WFE while e SLEEPDEEP 0 and SLEEPONEXIT 0 For more information refer to Cortex MO the System Control Register Mode exit If you use for entry Interrupt If you use WFE for entry Wake Up event Table 5 7 describes the IDLE on Sleep Exit Mode Entry Table 5 7 IDLE on Sleep on Exit Use the WFI or WFE e SLEEPDEEP 0 and SLEEPONEXIT 1 For more information refer to Cortex MO the System Control Register SAMSUNG ELECTRONICS 5 20 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 4 2 3 Enter STOP Mode The STOP mode is based on the SLEEPDEEP in the Cortex MO core All clocks stop operating It disconnects the clock supply to the SYSCLK in entry of the STOP mode and connects in exit of the STOP mode e Entry Condition STOP Sleep Now If the SLEEPDEEP bit of the System Control Register in the Cortex MO is set to 1 then the MCU enters the STOP mode
358. s IDLE and the other is STOP mode In low power modes you can disable the watchdog and LVD when it is not necessary This reduces the current consumption After reset the default mode is NORMAL mode 5 4 1 Operation Modes The four types of operation modes are e NORMAL Mode Use this mode to supply one of the four clock sources EMCLK or IMCLK to the CPU as well as to all the peripherals Power consumption increases when all the peripherals are enabled Appropriate actions on the corresponding clock source enable bit of the CM_PCSR register controls the ON and OFF on the clock gate of the individual clock source for each peripheral device e PLL Mode Use this mode to supply the PLLCLK for the system That means the SYSCLK becomes the PLLCLK e IDLE Mode This mode is one of the low power modes In the IDLE mode disconnecting the Clock to a CPU halts the operation Some peripherals remain active using the software STOP Mode This mode halts all logics You can activate the external interrupt the USARTRXO the SPIO or a chip reset to perform the Wake Up from the STOP mode The microcontroller can enter the STOP mode from Normal or the PLL mode SAMSUNG ELECTRONICS 5 17 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 4 2 Low Power Modes and Wake Up Low power modes are invoked by WFE instructions stands for Wait For Interrupt and WFE stands for Wait For Events Events can be interrupts a previously trigger
359. s and recall the default values For example you can reset PIOO using the GPIO_SRR 8 2 2 Input Configuration When you use the input function of I O port the output function of I O port disables The default of I O port is the input function When the I O port is an input function an external condition decides the level status of I O You can read the level status of I O through GPIO PDSR register To configure the ports as input the registers are e Output Disable Register e Pin Data Status Register GPIO PDSR SAMSUNG ELECTRONICS 8 2 ex S3FN429_UM_REV1 20 8 General Purpose I O GPIO 8 2 3 Output Configuration The data direction of I O ports should be configured as output This data can be written to the ports To configure the data direction enable disable monitor and data value the registers used are e Output Enable Register GPIO_OER e Write Output Data Register GPIO_WODR e Set Output Data Register GPIO_SODR e Clear Output Data Register GPIO_CODR e Output Data Status Register GPIO_ODSR e Pin Data Status Register GPIO_PDSR GPIO_WODR is to set the data value to I O ports in accordance with the register value high or low level On the contrary GPIO_SODR GPIO CODR set or clear the data value of I O ports according to the register value In other words GPIO SODR sets the I O ports to high level when values are written to the register sets the I O ports to low level
360. s error signal at 10 11 bits where 10 is the falling edge of the start bit that is between the 2 stop bits In the Figure 17 8 smart card detects the parity error The smart card generates the error signal on the COMMS line The USART detects the error signal and re transmits the last character Figure 17 8 illustrates the smart card transmission error diagram Frame Error Checking by the USART USARTTX STA 8 Bit Data Par STO 8 Bit Data re transmitted PAR 10 11 bits Figure 17 8 Smart Card Transmission Error If a Direct Memory Access DMA transfer is used to send data byte to the smart card then the DMA counter will not be decremented and the DMA memory pointer is not be incremented until the smart card receives a correct byte or the maximum repetition time is reached SAMSUNG ELECTRONICS 17 19 ex S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 6 7 Character Reception from Smart Card The USART is able to generate the error signal See 1507816 3 protocol when it receives the last byte that has parity error When USART detects the parity error the USART transmission line is driven low for 1 0625 bit period This period starts at t0 10 625 0 0 0625 that is during the 2 stop bits to indicate the smart card that a bad reception has occurred on the USART With T 0 protocol type smart cards the smart card should re send the last character In this scenario the US
361. s of 8 KB Therefore the total size of flash ROM is 4 sector number x 8 KB each sector size 32 KB One sector is made up of 32 pages Figure 9 3 illustrates the physical configuration 0x0000 7FFF PAGE127 256Byte PAGE126 256Byte 8KB PAGE97 256Byte 0x0000 6100 0x0000 6000 PAGES 256BYI9 950000 00D 0x0000 5FFF 95 256Byte 94 256Byte SECTOR2 8KB 2 PAGE65 256Byte 0x0000 4100 0x0000 4000 PAGE64 256Byte 6 0000 4000 0x0000 PAGE63 256Byte PAGE62 256Byte SECTOR1 8KB PAGE33 256Byte 0x0000 2100 0x0000 2000 0 0000 2000 0 0000 1 1 256 256Byte SECTORO 8KB PAGE 256Byte 0x0000 0100 0x0000 0054 0 0000 00 0 0x0000 0000 0x0000 0000 PAGEO 256Byte Figure 9 3 Physical Configuration SAMSUNG ELECTRONICS 9 3 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 2 1 2 Address Alignment This sub section describes the address alignment method to set an address value in IFC_AR Register according to each operation 9 2 1 2 1 Program To write data to flash you should set lower 2 bits to 0 To write data to flash by word unit 4 bytes you should set lower 2 bits to 0 during flash programming You can select address from the range 0 0000 to Ox7FFF in 32 KB In the tool program the low 2
362. s own interrupt vector For example USART has 15 interrupt sources including RXRDY Among them RXRDY interrupt source is mapped to IRQ13 Other interrupt sources are mapped to IRQ30 For more details about interrupt sources refer to the corresponding block of manual NOTE Refer to each corresponding block chapter of manual related to registers mentioned Figure 11 1 IMSCR Interrupt Mask Set Clear Register Read Write RISR Raw Interrupt Status Register Read only MISR Masked Interrupt Status Register Read only ICR Interrupt Clear Register Write only ISER Interrupt Set Enable Register Read Write ISPR Interrupt Set Pending Register Read Write Block X or Block Y is as follows WDT IMC COMP ADC PPD USART CM IFC TC PWM SPI GPIO SAMSUNG ELECTRONICS 11 5 ex S3FN429_UM_REV1 20 11 Interrupt Controller INTC 11 3 Register Description 11 3 1 Register Map Summary The tables in this section describe NVIC specific registers in System Control Space SCS of Base Address 0 000 0000 Reset Value NVIC_IPR5 OxE414 IRQ 20 to 23 interrupt priority register 0x0000 0000 NVIC IPR6 OxE418 IRQ 24 to 27 interrupt priority register 0x0000 0000 NVIC_IPR7 OxE41C IRQ 28 to 31 interrupt priority register 0x0000 0000 The system control region includes the status and configuration registers that apply to the NVIC as a part of the general exception model All other external interrupt
363. s that data is captured on the falling edges and be propagated on the rising edges of the SSPCLKOUT signal In the case of a single word transmission after all bits of the data word are transferred the SSPFSSOUT line is returned to its idle HIGH state one SSPCLKOUT period after the last bit has been captured SAMSUNG ELECTRONICS 15 13 ex S3FN429_UM_REV1 20 15 Serial Peripheral Interface SPI However in case of continuous back to back transmissions the SSPFSSOUT signal must be pulsed HIGH between each data word transfer This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the SPH bit is logic zero Therefore the master device must raise the SSPFSSIN pin of the slave device between each data transfer to enable the serial peripheral data write On completion of the continuous transfer the SSPFSSOUT pin is returned to its idle state one SSPCLKOUT period after the last bit has been captured 15 2 2 1 3 12 Motorola SPI Format with SPO 1 SPH 1 Figure 15 7 illustrates the transfer signal sequence for Motorola SPI format with SPO 1 SPH 1 for both single and continuous transfers SSPCLK SSS VS NS Na SSPRXD COIS EE a cau 4 to 4 SSPR Figure 15 7 Motorola SPI Frame Format with SPO 1 and SPH 1 In this configuration during idle periods e The SSPCLK signal is forced HIGH SSPFSS is forced HIGH e
364. sc ES gt sme EXE CAPT F 17 PWMEX2 8 24 40 56 PWMEX3 4 12 20 28 36 44 52 60 PWMEX4 2 6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 5 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 Reserved Capture by Falling Edge Trigger 0 No effect 1 Enables falling edge capture When the TC detects falling edge of external input signal on TCAP pin it stores the current counter value into the capture down register RSVD 16 Reseved CC ADTRIG 15 ADC Trigger EE SAMSUNG ELECTRONICS 16 23 ex Capture by Rising Edge Trigger 0 No effect 1 Enables rising edge capture When the TC detects rising edge of external input signal on TCAP pin it stores the current counter value into the capture up register PWM Output Extension 0 No effect 1 Enables corresponding extension bits _________ OR _ Reseved __ ES EN S3FN429_UM_REV1 20 16 Timer Counter i RSVD UPDATE 1 START Caution If you set the UPDATE bit when the timer is running then the CCDR TC_CCSMR CPRDR and CPULR registers immediately change to new values in CDR TC CSMR PRDR and PULR registers respectively But values in them will take effect only after Overflow event in Overflow mode or Period End event in Period mode da No effect Enables ADC trigger signal
365. se the base address of page 3 Write the page erase command and start control bit to Control Register CR 4 Check whether the operation of page erase is completed or not You can use one ways between polling and interrupt check If you monitor the status bit of END check END bit in Raw Interrupt Status Register RISR SAMSUNG ELECTRONICS 9 10 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 2 3 1 3 Sector Erase Operation A sector has 8 KB size The sector erase operation erases one sector to include address written into d Address Register IFC_AR To perform sector erase the steps are 1 Write the value Ox5A5A5A5A into the IFC_KEY register 2 Write the base address for target sector to the Address Register IFC_AR The address should be one in range of target sector Simply use the base address of sector 3 Write the sector erase command and start control bit to Control Register IFC_CR 4 Check whether the operation of sector erase is completed or not You can use one ways between polling and interrupt check If you monitor the status bit of END check END bit in Raw Interrupt Status Register IFC_RISR 9 2 3 1 4 Entire Erase Operation Basically the entire erase initializes all memory area But if BACEN bit in Mode Register MR is set to 1 the sector 0 is excluded from erase area BACEN means Boot Area Configuration bit When you include the specific code like as bootloader you can use
366. sector0 with Boot Area Configuration To perform entire erase the steps are 1 Write the value Ox5A5A5A5A into the IFC_KEY register If you require entire erase then there is no need to select address and data 2 Write the entire erase command and start control bit to Control Register IFC_CR You can use one ways between polling and interrupt check If you monitor the status bit of END check END bit in Raw Interrupt Status Register IFC_RISR SAMSUNG ELECTRONICS 9 11 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 2 3 1 5 Normal Program Operation The normal program operation writes one word data or code to the target address selected by IFC_AR register That means the writing size is 4B The data size that you can program is one word at a time So the lower 2 bits of target address should be 0 e AR 31 0 ADDRESS and You can perform normal program of flash memory using software in SRAM or flash memory The flash memory of S3FN429 is full flash because you can program flash memory by code programmed in flash memory Before program target address should be initialized by any erase operation To program a normal flash memory the steps are 1 Write the value Ox5A5A5A5A into the IFC KEY register 2 Write the address to be written into the Address Register AR 3 Write the data into the Data Register DR 4 Write the normal program command and start control bit in
367. sed for flash ROM Writer to Read Write Erase the flash memory VDDIO VSSIO nRESET VDDCORE VSSCORE F_SDAT and F SCLK Table 9 7 describes the pins used to Read Write Erase the flash ROM in Tool Program Mode Table 9 7 Pins Used to Read Write Erase the Flash ROM in Tool Program Mode Signal VO Function F SDAT P0 14 Serial bi directional DATA pin Output when reading Input when writing Input and push pull output port can be assigned SCLK P0 13 Serial CLOCK input pin RESET nRESET 1 Chip Initialization VDD VDDCORE Power pin for flash block VDDIO Power pin for interface VSSCORE Power pin for flash block vss VSSIO Power pin for I O interface VDDCOREOUT Connected to GND through 0 1 uF capacitor From internal regulator Flash program mode using flash writing tool serial interface The value should 01 b 9 2 3 2 1 Flash Program Tool There are several Flash Program Tools like a GW uni2 If you want to make a dedicated Flash Program Tool Flash ROM Writer please contact www seminix com for more detail document SAMSUNG ELECTRONICS 9 15 x S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 2 4 Flow Chart 9 2 4 1 Normal Program Figure 9 4 illustrates the Normal Program flowchart Loop Counter lt lt The number to program KEY lt lt 0x5A5A5A5A Y ADDR Address DATA Data to write
368. ser must right justify the data written to the Transmit FIFO The transmit logic ignores the unused bits Received data that are less than 16 bit is automatically right justified in the receive buffer SAMSUNG ELECTRONICS 15 21 ex S3FN429_UM_REV1 20 15 Serial Peripheral Interface SPI 15 3 1 4 SSP SR e Base Address 0x4009 0000 0x4009 1000 e Address Base Address 0x000C Reset Value 0x0000 0003 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 5 ol 4 3 2 1 0 gt we Ww ey u MD L Z Z Prime Cell SSP Busy Flag Bit 1 SSP is currently transmitting And or receiving a frame or the transmit FIFO is not empty Receive FIFO Full Status Bit 0 Receive FIFO is not full 1 Receive is full Receive Empty Status Bit 0 Receive FIFO is empty 1 Receive FIFO is not empty Transmit FIFO Full Status Bit 0 Transmit FIFO is full 1 Transmit FIFO is not full Transmit FIFO Empty Status Bit 0 Transmit FIFO is not empty 1 Transmit FIFO is empty SAMSUNG ELECTRONICS 15 22 en S3FN429_UM_REV1 20 15 Serial Peripheral Interface SPI 15 3 1 5 SSP_CPSR e Base Address 0x4009 0000 0x4009 1000 e Address Base Address 0x0010 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 CPSDVSR R R R R R R R R RSVD ere R Ty Cloc
369. ses Write the correct bit pattern to the control access key bit simultaneously with the control bits write access to update the contents of the mode and control registers SAMSUNG ELECTRONICS 18 1 ex S3FN429_UM_REV1 20 18 Watchdog Timer 18 2 Functional Description The functional description section describes the function of Watchdog Timer 18 2 1 Block Diagram Figure 18 1 illustrates the Watchdog Timer block diagram WDT_CTR WDT_FISR CM MR1 WDT MR COUNT WDTOVF WDTCLK PCV 15 0 Internal Chip PLLCLK WDT OMR FIN Programmable Down Counter RSTEN Divider lt PWL 15 0 Reset WDTPDIV WDT_MR WDT_OMR WDTPDIV 2 0 WDTEN WDT PWR RSTALW Write access to WDT CR RSTKEY 0xC071 Figure 181 Watchdog Timer Block Diagram SAMSUNG ELECTRONICS 18 2 ex S3FN429_UM_REV1 20 18 Watchdog Timer 18 2 2 Watchdog Timer Functionality The general description of the Watchdog Timer functionality is described in this section 18 2 2 1 General Description The Watchdog Timer contains a programmable length down counter The down counter input clock is a subdivision of the FIN EMCLK IMCLK from the clock manager NOTE The count value for overflow should be greater than 3 PCLK 5 FIN e WDTCLK FIN WDTPDIV 2 0 ofofo m U s o9 3 P 3 6 o9 9
370. should write into key register at first step KEY 31 0 W If you write other value not at first step you cannot execute the command operation If the sequence for a flash operation has the invalid key value not 0x5A5A5A58A it has No effect NOTE The KR register is cleared automatically after the completion of erase or program NOTE The KR register is auto cleared after finishing command operation SAMSUNG ELECTRONICS 9 40 ex S3FN429_UM_REV1 20 9 Internal Flash Controller IFC 9 3 1 14 SO PSR e Base Address 0x4001 0000 e Address Base Address 0x0034 Reset Value OxFFFF_FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 1 1 EN gt mwas gt gt Serial Read Protection Status Flag nSRP 27 0 Enables Serial Read Protection 1 Disables Serial Read Protection Hardware Protection Status Flag nHWP 17 0 Enables Hardware Protection 1 Disables Hardware Protection mw nen A SWD Protection Status Flag nSWDP 0 Enables SWD Protection 1 Disables SWD Protection Hardware Protection Area Area is a unit that consists of nHWPAx 7 4 0 Specifies area to be protected by Hardware Protection Smart Option 1 Specifies area not to be protected because Hardware Protection of correspon
371. sion 0 No effect 1 Disables corresponding extension bits stretched Cycle Number EAA AE 18 22 26 30 34 38 42 46 50 __ Oo 0 pop 1 8 5 7 9 11 13 15 17 19 21 23 25 27 PWMEX5 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 RSVD 23 19 Reserved Capture by Rising Edge Trigger CAPT R 0 No effect 1 Disables rising edge capture Capture by Falling Edge Trigger CAPT F 17 W 0 effect 1 Disables falling edge capture RSVD 16 Reserved ADC Trigger ADTRIG 15 0 No effect 1 Disables ADC trigger signal out OVFM Overflow Mode SAMSUNG ELECTRONICS 16 25 27 S3FN429_UM_REV1 20 16 Timer Counter REPEAT PWMEN PWMIM KEEP 0 No effect 1 Disables Overflow mode The counter value increases until the end of period Repeat Mode 0 No effect 1 Disables Repeat mode PWM Enable 0 No effect 1 Disables the signal output Interval Mode 0 1 Disables Interval mode The type of output signal is PWM operation Keep Stop Level 0 No effect 1 Disables Keep State mode Output Start Level 0 No effect 1 The output signal level will be LOW when starting OUTSL IDLESL a Stop Count Clear STOPCLEAR 3 W 0 Noeffect 1 Disables Stop Clear mode Stop Count Hold STOPHOLD 2 W 0 Noeffect 1 Disables Stop Hold mode 78 Resend Stop the START 0 No effect 1
372. sking of PCSUNF interrupt Position Counter Sign Overflow Masked Interrupt State PCSOVF Gives the masked interrupt state prior to masking of PCSOVF interrupt Position Counter Match Masked Interrupt State PCMAT Gives the masked interrupt state prior to masking of interrupt NOTE On a Read PPD MISR register gives the current masked status value of the corresponding interrupt A Write has no effect Position Capture Masked Interrupt State PCAPT Gives the masked interrupt state prior to masking of PCAPT interrupt SAMSUNG ELECTRONICS 7 21 ex S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 3 1 10 PPD_ICR e Base Address 0x400C_0000 e Address Base Address 0x0024 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 PCSOVF PHASEZ s e sccunr e sccovr SCAPT s e scsunr gt ___ gt ___ s e gt ___ gt ___ s e s e w w w w w PHASEZ Interrupt Clear 0 No effect 1 Clears PHASEZ interrupt Reserved Speed Counter Carry Underflow Interrupt Clear 0 No effect 1 Clears SCCUNF interrupt PHASEZ 16 s SCMAT n Speed Counter Carry Overflow Interrupt Clear 0 No effect 1 Clears SCCOVF interrupt Speed Capture Timer Overflow Interrupt Clear 0 No effect 1 Clears SCTOVF interr
373. specific registers are within the NVIC region of the SCS NVIC OxE410 IRQ 16 to 19 interrupt priority register 0x0000 0000 SAMSUNG ELECTRONICS 11 6 ex S3FN429_UM_REV1 20 11 Interrupt Controller INTC 11 3 1 1 NVIC_ISER e Base Address 0xE000_0000 e Address Base Address 0xE100 Reset Value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 lt z Lu WwiW IN IW WIW IW W W W W W W W W W W W W W W W W W W W W W W W W W Enables for device interrupt vector 0 31 Each bit represents an interrupt vector from IRQO to IRQ3 Writing 1 enables the associated interrupt Writing 0 has no effect Th ist ds back with th t enable state SETENA eho BW 0x0000 0000 Bit 0 for IRQO Bit 2 for IRQ1 Bit x for IRQx SAMSUNG ELECTRONICS 11 7 ex S3FN429_UM_REV1 20 11 Interrupt Controller INTC 11 3 1 2 NVIC_ICER e Base Address 0xE000_0000 e Address Base Address 0xE180 Reset Value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 lt z LLI tr WwiW IWN IW WIW IW W W W W W W W W W W W W W W W W W W W W W W W W W Disables for device interrupt vector 0 31 Each bit represents an interrupt vector
374. ss 0x0094 Reset Value 0x0000 0000 RJR JR R I RIRIRIR RIRYIR WIN WIW IW W W W W W W Control Interrupt to NVIC of CORTEX MO 0 NVICx interrupt does not occur 1 NVICx interrupt occurs When IDLEW bit of CM SR is set to 1 this register is effective Interrupt signal is handed over to NVIC regardless of CM NISR register When IDLEW bit is set to 1 0 000 E100 value to CM NISR you should copy the values of Interrupt Set Register of CPU to this register to generate interrupt SAMSUNG ELECTRONICS 5 74 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 9 1 28 CM_PSR e Base Address 0 4002 0000 e Address Base Address 0x00A4 Reset Value 0x0000_0002 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 ASV R Normal IVC Stable Bit NORIVC 1 0 Not stable 1 1 for a normal mode is stable mw A Reeves a 2 SAMSUNG ELECTRONICS 5 75 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 10 Guide Clock Initialization Reset ID check Recommend corresponding service execution M SR OxDF000000 according to the reset source SYSRSTS EMCMRSTS PORRSTS WDTRSTS LVDRSTS NRSTS or SWRS S 00 b heck SYSCLK initial value MR1 amp 0 3 hange SYSCLK divide Yes 1 lt N lt 7 from 8 to N 1 7 Figure 5 22 CM SCDR SDIVKEY SDIV Yes IMCLK Chang
375. ssors enable the low latency interrupt processing and provide efficient service for late arriving interrupts There are 38 individual interrupt vector sources including six Cortex MO interrupt vector sources 11 1 1 Features The features of the interrupt controller are Cortex MO s NVIC interface Six core interrupt vector sources Reset NMI HardFault SVCall PendSW SysTick 32 device interrupt vector sources Dynamically reconfigurable interrupt priority exist at four levels Low latency exception and interrupt handling Implement Cortex MO system control registers NVIC and the processor core interface are closely coupled which enable low latency interrupt processing and efficient processing of late arriving interrupts NVIC manages all interrupts including core exceptions NVIC manages all interrupts including core exceptions Refer to Vectored Interrupt Controller of ARM Cortex MO TM Technical Reference Manual SAMSUNG ELECTRONICS 11 1 ex S3FN429_UM_REV1 20 11 Interrupt Controller INTC 11 2 Functional Description Functional description section includes e Interrupt vector e Block diagram 11 2 1 Interrupt Vector The interrupt vector section includes e Core interrupt vector e Device interrupt vector 11 2 1 1 Core Interrupt Vector S3FN429 has six core interrupt vectors to be supported by Cortex MO as below Table 11 1 describes the core interrupt vector Table 11 1 Core Interrupt Vector Number Ad
376. stance is configured and connected either as a master or as a slave Figure 15 8 and Figure 15 9 illustrates PrimeCell SSP master coupled to two slaves and SPI master coupled to two PrimeCell SSP slaves respectively PL022 Configured as SPI Slave Master SSPTXD MOSI SSPRXD SSPFSS SSPCLK Figure 15 8 PrimeCell SSP Master Coupled Two Slaves The PrimeCell SSP 1022 is configured as master and is interfaced to two Motorola SPI slaves Each SPI Slave Select SS signal is permanently tied LOW and configures them as slaves Similar to the above operation the master can broadcast to two slaves through the master PrimeCell SSP SSPTXD line In response only one slave drives its SPI MISO port onto the SSPRXD line of the master SAMSUNG ELECTRONICS 15 15 ex S3FN429_UM_REV1 20 15 Serial Peripheral Interface SPI SPI Master 1022 Configured as Slave MOSI SSPRXD SSPTXD SSPFSS SSPCLK PL022 Configured as Slave SSPTXD SSPFSS SSPCLK Figure 15 9 SPI Master Coupled to two PrimeCell SSP Slaves The Motorola SPI is configured as a master and interfaced to two instances of PrimeCell SSP PL022 configured as slaves In this case the slave Select Signal SS is permanently HIGH and configures it as a master The master can broadcast to the two slaves through the master SPI MOSI line and in response only one slave drives its SSPTXD data onto the MISO line of the master SAMSUNG ELECTRONICS 15 16 ex S3FN42
377. ster or slave mode e Enable the PrimeCell SSP peripheral To configure the PrimeCell SSP as a master clear the SSPCR1 register Master or Slave Selection MS bit to 0 which is the default value on reset Setting the SSPCR1 register MS bit to 1 configures the PrimeCell SSP as a slave When configured as a slave enabling or disabling of the PrimeCell SSP SSPTXD signal is provided through the SSPCR 1 slave mode SSPTXD output disable bit SOD This can be used in some multi slave environments where master might parallel broadcast To enable the operation of the PrimeCell SSP set the Synchronous Serial Port Enable SSE bit to 1 Bit Rate Generation The serial bit rate is derived by dividing down the input clock SSPCLK The clock is first divided by an even pre scale value CPSDVSR from 2 to 254 which is programmed in SSPCPSR The clock is further divided by a value from 1 to 256 which is 1 SCR where SCR is the value programmed in SSPCRO The frequency of the output signal bit clock SSPCLKOUT is defined below e FssPoikour Fssecu CPSDVR 1 SCR For example if SSPCLK is 3 6864 MHz and CPSDVSR 2 then the SSPCLKOUT has a frequency range from 7 2 kHz to 1 8432 MHz 15 2 2 1 3 7 Frame Format Each data frame is between 4 and 16 bits long depending on the size of the data programmed and is transmitted starting with the Most Significant Bit MSB For all three formats the serial clock SSPCLKOUT is held inactive wh
378. t Position Counter Sign Overflow Interrupt Mask PCSOVF 1 0 Mask the interrupt disables the interrupt 1 Unmask the interrupt enables the interrupt Position Counter Match Interrupt Mask RW 0 Mask the interrupt disables the interrupt 1 Unmask the interrupt enables the interrupt NOTE Ona Read PPD_IMSCR register gives the current value of mask on the relevant interrupt A Write of 1 to a particular bit sets the mask and enables the interrupt to be read A Write of 0 to a particular bit clears the corresponding mask Position Capture Interrupt Mask PCAPT 3 0 Mask the interrupt disables the interrupt 1 Unmask the interrupt enables the interrupt SAMSUNG ELECTRONICS 7 17 ex S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 3 1 8 PPD_RISR e Base Address 0x400C_0000 e Address Base Address 0x001C Reset Value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 81 7 e N PCSUNF PCSOVF PHASEZ gt gt scour gt ___ SCAPT sosur 2 sosovr 2 sor Ea 2 gt __ PHASEZ Raw Interrupt State Gives the raw interrupt state prior to masking of PHASEZ interrupt Reserved Speed Counter Carry Underflow Raw Interrupt State Gives the raw interrupt state prior to masking of SCCUMF interrupt PHASEZ 16 s SCCUNF 14 SCCOVF 13 Sp
379. t GharacteristiCs ter Le ntn hi eee Dn aaa ge tagen 19 5 External interrupt Input Characteristics nennen nennen 19 6 External Main Oscillator Characteristics 19 7 Internal Main Oscillator Characteristics 110000 nennen nennen 19 8 Current Consumption at 5 9 Ln Eee va apu nx 19 9 PLL GharaCteriStics 19 10 LVD 1851 EEN 19 11 ADC Characteristics E 19 12 Comparator Electrical Characteristics 100000000 19 13 OP AMP Electrical Characteristics sess 19 14 Flash Memory Characteristics er b ERA 19 15 SAMSUNG ELECTRONICS ex Table 19 16 SPI Timing Characteristics esee 19 16 Table 19 17 ESD Characteristics Table 20 1 Package Specification 0 eee enne 20 1 SAMSUNG ELECTRONICS List of Conventions Register RW Access Type Conventions Read The application has permission to read the Register field Writes to read only fields have no effect Write Only The application has permission to write in the Register field The application has permission to re
380. t in US SR is set to 1 You can start or restart waiting for a first character by setting the STTTO Start Time Out bit in 05 CR register To start a time out the mandatory conditions are e US RTOR should not be equal to 0 e Start the time out by setting the STTTO bit in the US CR register to 1 e Receive one character Calculation of Time Out Duration is e Duration Value x Bit period in asynchronous mode e Duration Value x 16 x Bit period in synchronous mode SAMSUNG ELECTRONICS 17 14 iD S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 5 Transmitter The transmitter section includes e General Description e Multi Drop Mode 17 5 1 General Description The transmitter has the same behavior in both synchronous and asynchronous operating modes The start bit data bit parity bit and stop bits are serially shifted keeping the least significant bit first The number of data bits is selected in the CHRL 1 0 field in US MR The parity bit is set according to the PAR 2 0 field in 05 MR register If the parity type is even then the parity bit depends on the one bit sum of all data bits For odd parity the parity bit is the inverted sum of all data bits The number of stop bits is selected in the NBSTOP 1 0 field in 05 MR When a character is written to US THR Transmit Holding it is transferred to the Shift Register as soon as the register is empty When the tra
381. t in a situation when the counter overflows 18 2 3 4 Interrupt Handing The procedure for interrupt handling is 1 IRQ Entry and call C function 2 Read WDT MISR and verify the source of the interrupt 3 Clear the corresponding interrupt at peripheral level by writing in the WDT 4 Interrupt treatment If this is a windows pending interrupt restart the Watchdog by writing CR 5 Exit IRQ SAMSUNG ELECTRONICS 18 4 ex S3FN429_UM_REV1 20 18 Watchdog Timer 18 3 Register Description 18 3 1 Register Map Summary e Base Address 0 4003 0000 Reset value WDT ICR 0x0020 Watchdog interrupt clear register 0x0000 0000 WDT PWR 0x0024 Watchdog pending window register OxOOFF WDT CTR 0x0028 Watchdog counter test register 0x0000 FFFF WDT MISR 0x001C Watchdog masked interrupt status register 0x0000 0000 SAMSUNG ELECTRONICS 18 5 ex S3FN429_UM_REV1 20 18 Watchdog Timer 18 3 1 1 WDT_IDR e Base Address 0 4003 0000 Address Base Address 0x0000 Reset Value 0 0001 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 ID Code Register 0 0001_0000 DOUDE eo This field stores the ID code for the corresponding IP SAMSUNG ELECTRONICS 18 6 ex S3FN429_UM_REV1 20 18 Watchdog Timer 18 3 1 2 WDT_CR e Base Address 0 4003 0000 e Address Base A
382. t least one stop bit is detected low since the last Reset Status Bits command Overrun Error 0 No byte is transferred from the Receive Shift Register to the US RHR when RxRDY was asserted since the last Reset Status Bits command 1 At least one byte is transferred from the Receive Shift Register to the US when RxRDY was asserted since the last Reset Status Bits command e A Reseed Transmitter Ready 0 Acharacter is in the US THR waiting to be transferred to the Transmit Shift Register or the TXRDY 1 transmitter is disabled 1 There is no character in the US THR Equals to zero when the USART is disabled or at reset Transmitter Enable command in 05 CR sets this bit to 1 Receiver Ready 0 No complete character has been received since the last read of the US RHR or the receiver is disabled 1 At least one complete character is received and the US RHR has not been read yet Receiver Break 0 No Break Received is detected since the last Reset RXBRK 2 Status Bits command in the Control Register 1 Break Received is detected since the last Reset Status Bits command in the Control Register SAMSUNG ELECTRONICS 17 39 ex S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 8 1 11 US_RHR e Base Address 0x4008_0000 e Address Base Address 0x0028 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1
383. te prior to masking of the idle interrupt Time Out Raw Interrupt State Gives the raw interrupt state prior to masking of the PARE 7 PARE interrupt Framing Error Raw Interrupt State FRAME Gives the raw interrupt state prior to masking of the FRAME interrupt a TIME OUT interrupt Parity Error Raw Interrupt State Gives the raw interrupt state prior to masking of the Transmitter Empty Raw Interrupt State TXEMPTY Gives the raw interrupt state prior to masking of the TXEMPTY interrupt Overrun Error Raw Interrupt State OVRE 5 Gives the raw interrupt state prior to masking of the OVRE interrupt mv Mq R Receiver Break Raw Interrupt State RXBRK 2 Gives the raw interrupt state prior to masking of the RXBRK interrupt Transmitter Ready Raw Interrupt State TXRDY 1 Gives the raw interrupt state prior to masking of the TXRDY interrupt Receiver Ready Raw Interrupt State RXRDY Gives the raw interrupt state prior to masking of the RXRDY interrupt SAMSUNG ELECTRONICS 17 33 S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter NOTE On Read US RISR register gives the current raw status value of the corresponding interrupt prior to masking A Write has no effect SAMSUNG ELECTRONICS 17 34 ex S3FN429_UM_REV1 20 17 Universal Synchronous Asynchronous Receiver Transmitter 17 8 1 8 US_MISR e Base Address 0 4008 0000 e Address Base Address 0x001C Reset V
384. tem Clock SYSCLK is the symbol name of central bridge in clock tree The manufacture initial clock source is the IMCLK But the SYSCLK can be selected among three clock sources IMCLK EMCLK or PLLCLK and it can be explained with two different views e Initial default SYSCLK at reset e Inthis case the available clock sources are IMCLK and EMCLK The SYSCLK is decided between IMCLK and EMCLK by configuration smart option It is the same as like hardware configuration If you want to change the SYSCLK s reset value you need to change the smart option It can be done by smart option erase and program Refer to the flash memory controller related to the smart option erase and program e f you select EMCLK as the SYSCLK the XIN or XIN XOUT to obtain external clock source should be configured into configuration smart option e SYSCLK when the CPU executes code e This case is to change the SYSCLK from initial clock defined at reset to other different clock source The available clock sources are IMCLK EMCLK and PLLCLK To change you should use the control bit in Mode Register CM MR It is the control by user and software When you switch the SYSCLK the precise sequence is required because of critical event to microcontroller Refer to 1 3 2 SYSCLK Change Figure 5 2 illustrates the system clock selection diagram SYSCLK while CPU runs after reset SYSCLK at reset time normal or PLL mode SO POCCS O0 SO
385. terrupt PWM Start Interrupt clear PWMSTART 0 No effect 1 Clears PWM started interrupt NOTE Write of 1 clears the corresponding interrupt A Write of 0 has no effect SAMSUNG ELECTRONICS 14 25 ex S3FN429_UM_REV1 20 14 3 1 11 PWM_CDR 14 Pulse Width Modulation e Base Address 0 4007 0000 0x4007_ 1000 e Address Base Address 0x0028 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 SAMSUNG ELECTRONICS R R R R R R R R R R R R R R R Reserved Clock divider value PWMCLK M 1 where 0 lt M lt 2 Pre scale value PWMCLK 2 where 0 lt lt 16 r 14 26 ex S3FN429_UM_REV1 20 14 Pulse Width Modulation 14 3 1 12 PWM_PRDR e Base Address 0 4007 0000 0x4007_ 1000 e Address Base Address 0x002C Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 WINIWIW IW W W W W W W W W W W W 81 16 PWM Period Value PERIOD 15191 RUM Refer to Section 14 2 8 Parameter Relationship 9605 SAMSUNG ELECTRONICS 14 27 ex S3FN429_UM_REV1 20 14 Pulse Width Modulation 14 3 1 13 PWM_PULR e Base Address 0x4007_0000 0x4007_ 1000 e Address Base Address 0x0030 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 3 2 41 0 RIR
386. terrupt voltage level External Main Clock Fail Status 0 The External Main Oscillator failure does not occur EMCKFAIL 15 1 The External Main Oscillator failure has been detected It clears this bit when EMCKFAIL END or reset occurs CM ICR register does not clear this bit SAMSUNG ELECTRONICS 5 57 27 S3FN429_UM_REV1 20 5 Clock and Power Manager _ 0 of the External Oscillator failure is detected 1 At least one end of the External Main Oscillator Clock failure is detected To clear this bit write to 1 into the EMCKFAIL_END bit of CM_ICR register awo ra R Reser ooo 0 IDLE Control Status 0 Clears IDLEW 1 Sets IDLEW NOTE IDLEW bit in the CM_CSR and the CM_CCR registers IDLEW 11 controls this bit This bit shows the status of the SEVONPEND bit in Cortex M0 When this bit is 1 it can wake up from WFE if a new interrupt is pending regardless of whether the interrupt has priority higher than the current level SEVONPEND means Send Event on Pending RSVD R Remd 9 PCLK Control Status in IDLE Mode PCLK 0 Disables disconnect PCLK in IDLE mode 1 Enables connect PCLK in IDLE mode STCLK Control Status in IDLE Mode STCLK 0 Disables STCLK in IDLE mode 1 Enables STCLK in IDLE mode PLL Stable Interrupt PLL 7 0 Disables PLL 1 Enables and stabilizes PLL Fast Wake Up Control Enable Disable Status 0 Disables FWAKE 5 1 Ena
387. than the internal clock frequency PCLK 16 2 2 Counter Size You can use TC CSMR Counter Size Mask Register and TC CCSMR Current Counter Size Mask Register to determine the timer count size Both the registers include SIZE 3 0 field If the value of SIZE 3 0 is n then the TC will become a n 1 bit timer In other words this timer can count from 1 to geris When the TC starts or UPDATE bit is set in the Control Set Register CSMR is copied to the TC CCSMR register SIZE field in CCSMR register shows the information for the counter bit size of a current operating timer During the operation you can prepare the new counter size with SIZE field in CSMR register SAMSUNG ELECTRONICS 16 3 S3FN429_UM_REV1 20 16 Timer Counter 16 2 3 Counter Clock The counter clock increases the counter value The clock source and the clock divisor determine the frequency of the counter clock 16 2 3 1 Clock Source TC can use either the internal clock or the external clock as the counter clock source TC can use either the internal clock or the external clock as the counter clock source The internal clock is the PCLK and the external clock is a clock asserted on the TCLK pin To use the external clock supplied by TCLK you should configure the pin properly before starting the timer In case of using an external clock source the external clock frequency TCLK should be less than the internal clock frequency
388. tion interrupt is masked EDGEDET1 RW Disables the interrupt 1 Specifies Edge Detection interrupt is not masked Enables the interrupt Edge Detection Interrupt Mask 0 Specifies Edge Detection interrupt is masked EDGEDETO RW Disables the interrupt 1 Specifies Edge Detection interrupt is not masked Enables the interrupt NOTE On a Read the COMP IMSCR register gives the current value of the mask on the relevant interrupt A Write of 1 to a particular bit sets the mask and enables the interrupt A Write of 0 to a particular bit clears the corresponding mask Bit 181 4 Ege Edge Detection Interrupt Mask 0 Specifies Edge Detection interrupt is masked EDGEDET2 RW Disables the interrupt 1 Specifies Edge Detection interrupt is not masked Enables the interrupt SAMSUNG ELECTRONICS 6 15 ex S3FN429_UM_REV1 20 6 Comparator 6 3 1 9 COMP_RISR e Base Address 0 4004 2000 e Address Base Address 0x0020 Reset Value 0x0000 000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987 6 5 4 gt gt evcevers gt gt e sper e evaevero RSVD Reseved __ _ _ Edge Detection Raw Interrupt Status EDGEDETS Gives the raw interrupt state prior to masking of EDGEDETS interrupt Edge Detection Raw Interrupt Status EDGEDET2 Gives the raw interrupt state prior to masking of EDGEDET2 interrupt Edge Detection Raw Interrupt Status EDGED
389. tional Amplifier Operational Amplifier 13 1 Overview The Operation Amplifier chapter describes OP AMP that operates separately or with an Analog to Digital Converter ADC You can configure OP AMP gain using control bits 13 1 1 Features The features of OP AMP are e Amplification of input signal e Configurable internal gain from x2 5 to x15 by register setting e Gain control by external circuit 13 1 2 Pin Description Table 13 1 describes the pin description of OP AMP Table 13 1 OP AMP Pin Description OPA_Ox Operational Amplifier Output OPA_Px Operational Amplifier Positive Input 3 OPA_Nx Operational Amplifier Negative Input Bod dq 4 NOTE x represents the channel of For example has channels represented as OO and OPA_NO SAMSUNG ELECTRONICS 13 1 ex S3FN429_UM_REV1 20 13 Operational Amplifier 13 1 3 Block Diagram Figure 13 1 illustrates the block diagram for an OP AMP ADC Channel Selection ADC amp OP AMP The Oth channel ADC can be used for OP amp output OP AMP MODE OP amp can be used for discrete OP amp Figure 13 1 Block Diagram If the ADC has to convert the signal amplified by the OP AMP with internal gain then you have to enable the OP AMP and program it with a gain value before the ADC operation The ADC should select AINO as a conversion input channel SAMSUNG ELECTRONICS 13 2 x
390. tor Reset Internal RESET WDTRST Watch dog Timer Reset SWRST Software Reset SYSRST X CPU request Reset Figure 5 14 Reset Sources The Clock Manager has status bits that show the reset logging information The CM SR Clock Manager Status Register includes the information of reset logging ID from 24 to 31 bit When reset occurs each source triggers a reset and updates the status of each reset ID You can clear all reset ID flags by software Especially you should clear PORRSTS and LVDRSTS bits only by software Other reset ID flags clear if any reset occurs Table 5 10 describes the Reset ID flag Table 5 10 Reset ID Flag The software register control generates the last reset SAMSUNG ELECTRONICS 5 26 ex S3FN429_UM_REV1 20 5 Clock and Power Manager 5 6 1 nRESET Pin Reset NRST When the unmaskable nRESET pin asserts as Low then it generates the internal hardware reset signal After assertion of nRESET pin the MUC enters into the reset state regardless of the previous states After the nRESET resets the NRSTS bit in the CM SR register sets to 1 User software or other resets hardware can clear this bit 5 6 2 Power On Reset PORST The Power on Reset circuit is built in the microcontroller When power initially passes through the microcontroller or VDD drops below the POR voltage level typically 1 2 V then the POR circuit holds the microcontroller in reset until the VDD rises above the V
391. tput is used for Inverter Motor Controller IMC or Pulse Position Decoder PPD block 6 1 2 Pin Description Table 6 1 describes the pin description of Comparator Table 6 1 Pin Description PinNam COMPx P Comparator Positive Input po COMPx Comparator Negative Input a eee NOTE represents the channel for a Comparator For example Comparator 0 has channels represented as P and COMPO N SAMSUNG ELECTRONICS 6 1 ex S3FN429_UM_REV1 20 6 2 Functional Description The function of the comparator is to handle Block Diagram Comparator input Comparator output IMC Output off Control Interrupt SAMSUNG ELECTRONICS 6 Comparator S3FN429_UM_REV1 20 6 2 1 Block Diagram Figure 6 1 illustrates the comparator block diagram CR1 INTREFSELO COMPOPSEL CR0 0 8000 1 COMP SR COMPOUTSTATUSO 0 45VDD 0 50VDD P gt 2 6 Comparator COMP_IMSCR EDGEDETO _ COMPOEDGESEL GOMF RISR COMP MISR COMPOIMCEN Filter COMP_CR1 COMPCLK COMPOFILTER PWMUO PWMU1 output N gt 1 COMPONSEL PWMU2 4 CR2 CHKSRCSELO M _ 1 INTREFSEL1 0 45VDD h COMP
392. ts in TC_PULR register The TC copies the PULSE bits in TC_PULR register into TC_CPULR register when the timer starts or UPDATE bit in TC_CSR register is set PULSE in TC_CPULR register should be less than or equal to PERIOD in TC_CPRDR register The OUTSL bit in TC_SR register determines the TPWM output signal when the timer starts When OUTSL is clear the output signal will be LOW and When OUTSL is set the output signal will be HIGH When the counter value is equal to TC_CPULR the pulse match signal is generated TPWM output is toggled to the opposite level of OUTSL bit After that the counter value will be increased until PERIOD value specified in TC_CPRDR and the period end signal is generated At this time if REPEAT bit is set in TC_SR register then the counter value restarts from 1 If REPEAT is clear then the timer stops and the counter value is cleared to 0 Figure 16 7 illustrates the PWM operation Condition TC SR OVFM 0 REPEAT 1 PWMEN 1 PWMIM 0 OUTSL 0 TC CCSMR SIZE gt 3 TC_CPULR PULSE 4 TC CPRDR PERIOD 8 Counter Clock TC_CVR COUNT TC_RISR MATI TC_RISR PENDI TPWM Period Interrupts are cleared by writing 1 to corresponding bits in TC_ICR Figure 16 7 PWM Operation SAMSUNG ELECTRONICS 16 10 ex S3FN429_UM_REV1 20 16 Timer Counter 16 2 7 2 1 Extension Bit Some Periods can be Extension Periods in every 64 Periods Extension Period has an extended pulse width that
393. tus level will be decided nPULSE will be the opposite level by IDLE control a lt PULSE nPULSE s PULSE nPULSE PULSE lt nPULSE IDLE gt K PERIOD x PERIOD X PERIOD lt PWM 1 cycle 3 PWM 1 PWM 1 cycle gt START STOP or DISABLE Figure 14 2 PWM Cycle Description The functions of periodic waveform are e PERIOD The PERIOD means the period width You can define the periodic width time of PWM with setting the PERIOD 15 0 field in the PWM_PRDR register e PULSE The PULSE means the duty On time of PWM You can define the periodic duty ratio of PWM with setting PULSE 15 0 field in the PWM_PULR register Also you can select the level of PULSE with setting PWM CSR PWM CCR register e nPULSE PERIOD PULSE 15 0 value calculates the active width time for nPulse e IDLE IDLESL bit CSR PWM register decides the idle level e OUTPUTL Output Level is the level for an active width It means start level at each period and OUTPUTL bit in the PNM CSR PWM CCR register defines the output level The CLKEN bit in the PWM CEDR Clock Enable Disable Register enables disables the PWM clock MCU chip reset or IP software reset resets the module on the SWRST bit in the PWM SRR Software Reset Register When you stop or disable PWM PWM operation should be in IDLE state at next PWM period cycle
394. uit you should place them close to the chip This proximity to the chip provides a stable clock and minimizes the stabilization time You should choose the capacitance value of the load capacitor according to the external oscillator frequency If XIN XOUT or XIN pin is defined after any reset it has the enabled EMCLK by default That is decided by the configuration smart option While microcontroller is operating you can enable or disable the EMCLK by controlling the EMCLK bit in the CCR CM CSR register You can use EMCLK for the SYSCLK and several blocks Especially the PLL has only the EMCLK as an Input Clock source EMCLK can become SYSCLK by the POCCS bit of the SO CSR register at reset time Refer to IFC chapter for more details After enabling and stabilizing the External Oscillator the EMCLK supplies clock to the SYSCLK when the SYSCLK field in the CM MR register is 00 b Figure 5 3 illustrates the crystal ceramic resonator or the external clock circuit diagram External Clock Open Pin XOUT Main Oscillator Circuit External Crystal or Ceramic Resonator sock Circuit Figure 5 3 Crystal Ceramic Resonator or External Clock Circuit SAMSUNG ELECTRONICS 5 7 x S3FN429_UM_REV1 20 5 Clock and Power Manager Caution If you don t the external main oscillator when pin7 and pin8 are defined XOUT and XIN function you should tie XIN to ground XOUT should be opened 5 2 4 PLL The PLL P
395. upt Speed Capture Interrupt Clear 0 No effect 1 Clears SCAPT interrupt Speed Counter Sign Underflow Interrupt Clear 0 No effect 1 Clears interrupt Speed Counter Sign Overflow Interrupt Clear 0 No effect 1 Clears SCSOVF interrupt Speed Counter Match Interrupt Clear 0 No effect 1 Clears SCMAT interrupt Reserved SAMSUNG ELECTRONICS 7 22 27 Te efe efe S3FN429_UM_REV1 20 7 Pulse Position Decoder Position Capture Carry Underflow Interrupt Clear PCCUNF 0 No effect 1 Clears PCCUNF interrupt Position Counter Carry Overflow Interrupt Clear PCCOVF 0 No effect 1 Clears PCCOVF interrupt Position Capture Timer Interrupt Clear PCTOVF 0 No effect 1 Clears interrupt Position Capture Sign Underflow Interrupt Clear PCSUNF 0 No effect 1 Clears PCSUNF interrupt Position Counter Sign Overflow Interrupt Clear PCSOVF 0 No effect 1 Clears PCSOVF interrupt Position Counter Match Interrupt Clear PCMAT 0 No effect 1 Clears PCMAT interrupt A Write of 1 clears the corresponding interrupt A Write of 0 has no effect Position Capture Interrupt Clear PCAPT 0 No effect 1 Clears PCAPT interrupt NOTE 1 Position Counter Sign Carry Overflow PCSOVF PCCOVF and Position Counter Sign Carry Underflow PCSUNF PCCUNF will be cleared automatically by PHASEZ and PCCL CR
396. ut of PHASEB is Counter Clockwise CCW signal The PCR down counts using the PHASEB pulse e The feature of Type 3 is The input of PHASEA is the direction signal The input of PHASEZ is the pulse signal Pulse Position Decoder Block Enable Disable Control Bit 0 Disables pulse position decoder block bit PPDEN 3 1 Enables pulse position decoder block bit Pulse Position Decoder Clock PPDCLK Selection This field determines the PPDCLK 000 PCLK 001 PCLK 2 PPDCLKSEL 2 0 RW 010 PCLK 4 000 b 011 PCLK 8 100 PCLK 16 101 PCLK 32 110 PCLK 64 111 PCLK 128 NOTE 1 SCDCTRL bit is valid only in Type 0 This bit has no effect in type 1 and 2 2 Ifyou write a not used value for control bits the value will not change The control bit will have the previous value RW RW W SAMSUNG ELECTRONICS 7 12 ex S3FN429_UM_REV1 20 7 Pulse Position Decoder 7 3 1 5 PPD_CR1 e Base Address 0x400C_0000 Address Base Address 0x0010 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 14 13 12 11 10 9 81 7 R R R R R Ww WIW W W WIW W W Position Counter Clear by PHASEZ This field determines PCNT clear enable by Phase Z 0 Disables position counter 1 RW 31 1 Enables position counter NOTE PZCL bit clears position counter only when PPDEN is set to 1 SCSYNCHCL D 2 m PCTPRESCALE D a ac z ra 71 ror l roren
397. w Interrupt State ADCFMO Gives the raw interrupt state prior to masking of the ADCFMO interrupt ADC Rising Match Raw Interrupt State ADCRMO Gives the raw interrupt state prior to masking of the interrupt TOP Match Raw Interrupt State Gives the raw interrupt state prior to masking of the TOP interrupt ZERO Match Raw Interrupt State Gives the raw interrupt state prior to masking of the ZERO interrupt FAULT Raw Interrupt State SAMSUNG ELECTRONICS 10 45 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC Gives the raw interrupt state prior to masking of the FAULT interrupt NOTE 1 Read the IMC_RISR register gives the current raw status value of the corresponding interrupt prior to masking 2 Write has no effect ZERO is set right after IMC enable SAMSUNG ELECTRONICS 10 46 ex S3FN429_UM_REV1 20 10 Inverter Motor Controller IMC 10 3 1 10 IMC_MISR Base Address 0 400 0000 Address Base Address 0 0024 Reset Value 0 0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 ADCFM1 ADCFM2 __ acm EXEC ADC 2 Falling Match Masked Interrupt State ADCFM2 Gives the masked interrupt state prior to masking of the ADCFN2 interrupt ADC Compare2 Rising Match Masked Interrupt State ADCRM2 Gives the masked interrupt state prior to masking of th
398. x0044 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 o z RIR RI R R R R R R R R R WINIWI IW IWI IW W W W W W W Analog Input Channel Number Selection Field 0000 AINO an input for OP AMP 0001 AIN1 0010 AIN2 0011 AIN3 ICNUM10 0100 AIN4 ICNUM9 0101 AIN5 ICNUM8 0110 AIN6 0111 AIN7 1000 AIN8 1001 9 1010 AIN10 Others Invalid SAMSUNG ELECTRONICS 4 28 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter ADC 4 2 1 10 ADC_SSR e Base Address 0 4004 0000 e Address Base Address 0x0048 Reset Value 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 41 0 Conversion Count Value 0000 No 0001 1 conversion is ended 0010 2 conversion is ended 0011 3 conversion is ended 0100 4 conversion is ended 0101 5 conversion is ended 0110 6 conversion is ended 0111 7 conversion is ended 1000 8 conversion is ended 1001 9 conversion is ended 1010 10 conversion is ended 1011 11 conversion is ended When ADC is not in busy status the value in this register is invalid Revo R NOTE The is maintained the last value in the continuous mode and is set to 0 in the multiple one shot mode at the end of last conversion SAMSUNG ELECTRONICS 4 29 ex S3FN429_UM_REV1 20 4 Analog to Digital Converter

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